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fix: add missing debug module port build #4704: Commit 2b2e120 pushed by ricted98
2m 7s gwaihir-common-cells-v2
gwaihir-common-cells-v2
2m 7s
hw: add generated regs and plic cfg files build #4703: Commit 6fc9020 pushed by gabbo993
3m 51s glodi/ucie
glodi/ucie
3m 51s
hw: add 4 NumExtInIntrs for ucie integration build #4702: Commit df73b47 pushed by gabbo993
2m 5s glodi/ucie
glodi/ucie
2m 5s
chore(bender): update iommu. build #4701: Pull request #288 opened by yvantor
2m 5s yt/iommu
yt/iommu
2m 5s
chore(bender): update iommu. build #4700: Commit 999934e pushed by yvantor
2m 22s yt/iommu
yt/iommu
2m 22s
chore: bump cva6 build #4699: Commit f58788e pushed by ricted98
1m 55s gwaihir-common-cells-v2
gwaihir-common-cells-v2
1m 55s
chore: bump axi and common_cells build #4698: Commit c7c951d pushed by ricted98
1m 53s gwaihir-common-cells-v2
gwaihir-common-cells-v2
1m 53s
feat(iommu): iommu integration. (#286) build #4697: Commit abc95b9 pushed by ricted98
2m 6s gwaihir-common-cells-v2
gwaihir-common-cells-v2
2m 6s
fix(sw): update CLIC tests build #4696: Commit 1327f32 pushed by ricted98
2m 19s gwaihir
gwaihir
2m 19s
chore: bump cva6rt to latest version build #4695: Commit 2abc78e pushed by ricted98
1m 44s gwaihir
gwaihir
1m 44s
bender: update axi_llc build #4694: Commit 4ecb088 pushed by ricted98
2m 19s gwaihir
gwaihir
2m 19s
feat: parametrize Cheshire for 32-bit cores + SerialLink fix build #4693: Pull request #287 synchronize by Xeratec
1m 56s wiesep/32bit-support
wiesep/32bit-support
1m 56s
32-bit Cheshire build #4692: Commit 6fbe675 pushed by Xeratec
2m 34s wiesep/32bit-support
wiesep/32bit-support
2m 34s
Adaptions for Torik build #4691: Commit 2499482 pushed by Xeratec
2m 0s wiesep/torik-main
wiesep/torik-main
2m 0s
Bufixes build #4690: Commit b0495c9 pushed by Xeratec
1m 34s wiesep/chimera-main
wiesep/chimera-main
1m 34s
Adaptions for Torik build #4689: Commit 8882660 pushed by Xeratec
2m 4s wiesep/torik-main
wiesep/torik-main
2m 4s
Bufixes build #4688: Commit ad168f8 pushed by Xeratec
1m 58s wiesep/chimera-main
wiesep/chimera-main
1m 58s
feat(iommu): iommu integration. (#286) build #4687: Commit abc95b9 pushed by ricted98
2m 0s gwaihir-common-cells-v2-legacy
gwaihir-common-cells-v2-legacy
2m 0s
feat: parametrize Cheshire for 32-bit cores + SerialLink fix build #4686: Pull request #287 opened by Xeratec
2m 59s wiesep/32bit-support
wiesep/32bit-support
2m 59s
32-bit Cheshire build #4685: Commit bd4c2db pushed by Xeratec
1m 27s wiesep/32bit-support
wiesep/32bit-support
1m 27s
Revert "Add peripheral clock gates" build #4684: Commit 70a7c23 pushed by Xeratec
2m 39s wiesep/chimera-main
wiesep/chimera-main
2m 39s
chore: adopt OpenHW CVA6 build #4683: Commit 25b7945 pushed by ricted98
3m 14s feat/openhw-pulp
feat/openhw-pulp
3m 14s
chore: adopt OpenHW CVA6 build #4682: Commit 39a1ef8 pushed by ricted98
1m 56s feat/openhw-pulp
feat/openhw-pulp
1m 56s
chore: adopt OpenHW CVA6 build #4681: Commit c065df2 pushed by ricted98
1m 13s feat/openhw-pulp
feat/openhw-pulp
1m 13s
feat(iommu): iommu integration. build #4680: Pull request #286 synchronize by yvantor
1m 37s yt/iommu
yt/iommu
1m 37s