feat: parametrize Cheshire for 32-bit cores + SerialLink fix

[Xeratec]

Generic (non-Chimera) changes extracted from the wiesep/chimera-main integration branch,
proposed for upstream. No functional change for the default 64-bit configuration.

fix: guard SerialLink APB mask

When SerialLink is disabled, gen_cheshire_cfg still set the APB mask bit for the slink
reg-bus port, pointing the APB demux at a port that isn't instantiated. Guarded on
cfg.SerialLink, matching the other optional ports.

feat: parametrize Cheshire for 32-bit (XLEN) cores

Generalizes Cheshire so it can be instantiated with a 32-bit core (riscv::XLEN == 32),
today hardcoded to 64.

HW

• Derive RiscvWordWidth from riscv::XLEN instead of hardcoding 64 in every
  axi_riscv_atomics wrapper (reg, LLC, debug, DMA-conf).
• Size boot_addr_i / hart_id_i to riscv::XLEN.
• Add config fields TFLenWidth, AxiSlvIdWidth, and external wide-AXI port counts
  (AxiExtNumWideMst / AxiExtNumWideSlv).
• Swap cheshire_idma_wrap for the standard dma_core_wrap (typed AXI channels,
  configurable TFLenWidth / EnableAxiCut).

SW / build

• Split crt0.S into sw/lib/32/ and sw/lib/64/; add a 32-bit startup path.
• Make sw.mk build for the selected XLEN; add rv32 linker support in common.ldh.
• Widths in dif/uart changed from uint64_t to uint32_t (valid on both XLENs).

Open points for review

• cheshire_idma_wrap.sv is left in Bender.yml but no longer instantiated — remove it,
  or gate the DMA wrapper choice behind a parameter?
• Confirm the new config fields are the right home for the wide-AXI port counts.

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Draft: split out of the Chimera 64-bit upgrade work (pulp-platform/chimera#84).

[ricted98]

Hi @Xeratec, this is an unprompted comment but I did something similar (but much more reduced in scope and quick and dirty) some time ago: 54f4350. I don't know if something can be complementary or be saved from it, for example it could be likely possible to have a unified crt0.S. Feel free to use this info as you like!