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feat: parametrize Cheshire for 32-bit cores + SerialLink fix #287

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333042c
fix: Resolve problem if SerialLink is disagbled
Xeratec Jul 9, 2026
6fbe675
32-bit Cheshire
Xeratec Jul 23, 2026
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10 changes: 10 additions & 0 deletions .gitignore
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Expand Up @@ -53,3 +53,13 @@ target/xilinx/build
target/xilinx/out
target/xilinx/scripts/add_sources.*
vivado*

# Bender lock
Bender.lock

# Emacs undo-tree files
*undo-tree*

# Temp files
*~
*#
9 changes: 8 additions & 1 deletion cheshire.mk
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Expand Up @@ -160,6 +160,13 @@ $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.sv: $(CHS_ROOT)/hw/bootrom/cheshire_boot

CHS_BOOTROM_ALL += $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.sv $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.dump

.PHONY: chs_bootrom_clean

chs_bootrom_clean:
rm -f $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.sv
rm -f $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.elf
rm -f $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.bin

##############
# Simulation #
##############
Expand Down Expand Up @@ -216,7 +223,7 @@ CHS_ALL += $(CHS_SW_ALL) $(CHS_HW_ALL) $(CHS_SIM_ALL)
chs-all: $(CHS_ALL)
chs-sw-all: $(CHS_SW_ALL)
chs-hw-all: $(CHS_HW_ALL)
chs-bootrom-all: $(CHS_BOOTROM_ALL)
chs-bootrom-all: chs_bootrom_clean $(CHS_BOOTROM_ALL)
chs-sim-all: $(CHS_SIM_ALL)
chs-dramsys-all: $(CHS_DRAMSYS_ALL)
chs-xilinx-all: $(CHS_XILINX_ALL)
Expand Down
6 changes: 6 additions & 0 deletions hw/bootrom/cheshire_bootrom.S
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Expand Up @@ -113,17 +113,23 @@ boot_next_stage:
// Non-SMP hart: Write boot address into global scratch registers
la t0, __regs_base_addr__
sw a0, 16(t0) // regs.SCRATCH[4]
#if XLEN==64
srli a0, a0, 32
sw a0, 20(t0) // regs.SCRATCH[5]
#endif
fence
// Resume SMP harts
smp_resume(t0, t1, t2)
// Load boot address from global scratch registers
la t0, __regs_base_addr__
#if XLEN==64
lwu t1, 20(t0) // regs.SCRATCH[5]
slli t1, t1, 32
#endif
lwu t0, 16(t0) // regs.SCRATCH[4]
#if XLEN==64
or t0, t0, t1
#endif
// Store hartid to a0
csrr a0, mhartid
// Jump to boot address
Expand Down
2 changes: 1 addition & 1 deletion hw/bootrom/cheshire_bootrom.ld
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Expand Up @@ -9,7 +9,7 @@
INCLUDE common.ldh

SECTIONS {
__stack_pointer$ = ORIGIN(spm) + LENGTH(spm) - 8;
__stack_pointer$ = __stack_start - 8;

.text : {
*(.text._start)
Expand Down
2 changes: 1 addition & 1 deletion hw/cheshire_addrmap_pkg.sv
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Expand Up @@ -160,4 +160,4 @@ typedef enum logic [1:0] {
I2C_24XX1025 = 2'd3
} BootMode_e;

endpackage;
endpackage
60 changes: 42 additions & 18 deletions hw/cheshire_idma_wrap.sv
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Expand Up @@ -9,20 +9,26 @@

/// DMA core wrapper for the integration into Cheshire.
module cheshire_idma_wrap #(
parameter int unsigned AxiAddrWidth = 0,
parameter int unsigned AxiDataWidth = 0,
parameter int unsigned AxiIdWidth = 0,
parameter int unsigned AxiUserWidth = 0,
parameter int unsigned AxiSlvIdWidth = 0,
parameter int unsigned NumAxInFlight = 0,
parameter int unsigned MemSysDepth = 0,
parameter int unsigned JobFifoDepth = 0,
parameter bit RAWCouplingAvail = 0,
parameter bit IsTwoD = 0,
parameter type axi_mst_req_t = logic,
parameter type axi_mst_rsp_t = logic,
parameter type axi_slv_req_t = logic,
parameter type axi_slv_rsp_t = logic
parameter int unsigned AxiAddrWidth = 0,
parameter int unsigned AxiDataWidth = 0,
parameter int unsigned AxiIdWidth = 0,
parameter int unsigned AxiUserWidth = 0,
parameter int unsigned AxiSlvIdWidth = 0,
parameter int unsigned NumAxInFlight = 0,
parameter int unsigned MemSysDepth = 0,
parameter int unsigned JobFifoDepth = 0,
parameter bit EnableAxiCut = 1'b1,
parameter bit RAWCouplingAvail = 0,
parameter bit IsTwoD = 0,
parameter type axi_mst_aw_chan_t = logic,
parameter type axi_mst_ar_chan_t = logic,
parameter type axi_mst_w_chan_t = logic,
parameter type axi_mst_r_chan_t = logic,
parameter type axi_mst_b_chan_t = logic,
parameter type axi_mst_req_t = logic,
parameter type axi_mst_rsp_t = logic,
parameter type axi_slv_req_t = logic,
parameter type axi_slv_rsp_t = logic
) (
input logic clk_i,
input logic rst_ni,
Expand Down Expand Up @@ -119,8 +125,8 @@ module cheshire_idma_wrap #(
logic me_busy;

// Internal AXI channels
axi_mst_req_t axi_read_req, axi_write_req;
axi_mst_rsp_t axi_read_rsp, axi_write_rsp;
axi_mst_req_t axi_read_req, axi_write_req, axi_cut_req;
axi_mst_rsp_t axi_read_rsp, axi_write_rsp, axi_cut_rsp;

axi_to_reg_v2 #(
.AxiAddrWidth ( AxiAddrWidth ),
Expand Down Expand Up @@ -337,8 +343,26 @@ module cheshire_idma_wrap #(
.slv_read_resp_o ( axi_read_rsp ),
.slv_write_req_i ( axi_write_req ),
.slv_write_resp_o ( axi_write_rsp ),
.mst_req_o ( axi_mst_req_o ),
.mst_resp_i ( axi_mst_rsp_i )
.mst_req_o ( axi_cut_req ),
.mst_resp_i ( axi_cut_rsp )
);

axi_cut #(
.Bypass ( ~EnableAxiCut ),
.aw_chan_t ( axi_mst_aw_chan_t ),
.w_chan_t ( axi_mst_w_chan_t ),
.b_chan_t ( axi_mst_b_chan_t ),
.ar_chan_t ( axi_mst_ar_chan_t ),
.r_chan_t ( axi_mst_r_chan_t ),
.axi_req_t ( axi_mst_req_t ),
.axi_resp_t ( axi_mst_rsp_t )
) i_axi_cut (
.clk_i,
.rst_ni,
.slv_req_i ( axi_cut_req ),
.slv_resp_o ( axi_cut_rsp ),
.mst_req_o ( axi_mst_req_o ),
.mst_resp_i ( axi_mst_rsp_i )
);

endmodule
9 changes: 8 additions & 1 deletion hw/cheshire_pkg.sv
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Expand Up @@ -95,6 +95,8 @@ package cheshire_pkg;
dw_bt AxiDataWidth;
dw_bt AxiUserWidth;
aw_bt AxiMstIdWidth;
aw_bt TFLenWidth;
aw_bt AxiSlvIdWidth;
dw_bt AxiMaxMstTrans;
dw_bt AxiMaxSlvTrans;
// User signals identify atomics masters.
Expand All @@ -117,6 +119,9 @@ package cheshire_pkg;
byte_bt [2**MaxExtAxiSlvWidth-1:0] AxiExtRegionIdx;
doub_bt [2**MaxExtAxiSlvWidth-1:0] AxiExtRegionStart;
doub_bt [2**MaxExtAxiSlvWidth-1:0] AxiExtRegionEnd;
// External Wide AXI ports (limited number of ports and rules)
bit [MaxExtAxiMstWidth-1:0] AxiExtNumWideMst;
bit [MaxExtAxiSlvWidth-1:0] AxiExtNumWideSlv;
// External reg slaves (limited number of ports and rules)
bit [MaxExtRegSlvWidth-1:0] RegExtNumSlv;
bit [MaxExtRegSlvWidth-1:0] RegExtNumRules;
Expand Down Expand Up @@ -438,7 +443,7 @@ package cheshire_pkg;
// Set APB mask for all reg-bus ports whose IP uses an APB4-flat interface
ret.apb_mask = '0;
ret.apb_mask[ret.regs] = 1'b1;
ret.apb_mask[ret.slink] = 1'b1;
if (cfg.SerialLink) begin ret.apb_mask[ret.slink] = 1'b1; end
return ret;
endfunction

Expand Down Expand Up @@ -557,6 +562,8 @@ package cheshire_pkg;
AxiDataWidth : 64,
AxiUserWidth : 2, // AMO(2)
AxiMstIdWidth : 2,
TFLenWidth : 32,
AxiSlvIdWidth : 3,
AxiMaxMstTrans : 24,
AxiMaxSlvTrans : 24,
AxiUserAmoMsb : 1, // Convention: lower AMO bits for cores, MSB for serial link
Expand Down
21 changes: 15 additions & 6 deletions hw/cheshire_soc.sv
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Expand Up @@ -118,6 +118,9 @@ module cheshire_soc import cheshire_pkg::*; #(

import cheshire_addrmap_pkg::*;

localparam int unsigned RiscvWordWidth = riscv::XLEN;


//////////////////
// Interrupts //
//////////////////
Expand Down Expand Up @@ -338,7 +341,7 @@ module cheshire_soc import cheshire_pkg::*; #(
.AxiUserAsId ( 1 ),
.AxiUserIdMsb ( Cfg.AxiUserAmoMsb ),
.AxiUserIdLsb ( Cfg.AxiUserAmoLsb ),
.RiscvWordWidth ( 64 ),
.RiscvWordWidth ( RiscvWordWidth ),
.NAxiCuts ( Cfg.RegAmoNumCuts ),
.axi_req_t ( axi_slv_req_t ),
.axi_rsp_t ( axi_slv_rsp_t )
Expand Down Expand Up @@ -487,7 +490,7 @@ module cheshire_soc import cheshire_pkg::*; #(
.AxiUserAsId ( 1 ),
.AxiUserIdMsb ( Cfg.AxiUserAmoMsb ),
.AxiUserIdLsb ( Cfg.AxiUserAmoLsb ),
.RiscvWordWidth ( 64 ),
.RiscvWordWidth ( RiscvWordWidth ),
.NAxiCuts ( Cfg.LlcAmoNumCuts ),
.axi_req_t ( axi_slv_req_t ),
.axi_rsp_t ( axi_slv_rsp_t )
Expand Down Expand Up @@ -641,8 +644,8 @@ module cheshire_soc import cheshire_pkg::*; #(
) i_core_cva6 (
.clk_i,
.rst_ni,
.boot_addr_i ( BootAddr ),
.hart_id_i ( 64'(i) ),
.boot_addr_i ( BootAddr[riscv::XLEN-1:0] ),
.hart_id_i ( riscv::XLEN'(i) ),
.irq_i ( xeip[i] ),
.ipi_i ( msip[i] ),
.time_irq_i ( mtip[i] ),
Expand Down Expand Up @@ -862,7 +865,7 @@ module cheshire_soc import cheshire_pkg::*; #(
.AxiUserAsId ( 1 ),
.AxiUserIdMsb ( Cfg.AxiUserAmoMsb ),
.AxiUserIdLsb ( Cfg.AxiUserAmoLsb ),
.RiscvWordWidth ( 64 ),
.RiscvWordWidth ( RiscvWordWidth ),
.NAxiCuts ( Cfg.DbgAmoNumCuts ),
.axi_req_t ( axi_slv_req_t ),
.axi_rsp_t ( axi_slv_rsp_t )
Expand Down Expand Up @@ -1446,7 +1449,7 @@ module cheshire_soc import cheshire_pkg::*; #(
.AxiUserAsId ( 1 ),
.AxiUserIdMsb ( Cfg.AxiUserAmoMsb ),
.AxiUserIdLsb ( Cfg.AxiUserAmoLsb ),
.RiscvWordWidth ( 64 ),
.RiscvWordWidth ( RiscvWordWidth ),
.NAxiCuts ( Cfg.DmaConfAmoNumCuts ),
.axi_req_t ( axi_slv_req_t ),
.axi_rsp_t ( axi_slv_rsp_t )
Expand Down Expand Up @@ -1495,8 +1498,14 @@ module cheshire_soc import cheshire_pkg::*; #(
.NumAxInFlight ( Cfg.DmaNumAxInFlight ),
.MemSysDepth ( Cfg.DmaMemSysDepth ),
.JobFifoDepth ( Cfg.DmaJobFifoDepth ),
.EnableAxiCut ( 1'b1 ),
.RAWCouplingAvail ( Cfg.DmaRAWCouplingAvail ),
.IsTwoD ( Cfg.DmaConfEnableTwoD ),
.axi_mst_aw_chan_t( axi_mst_aw_chan_t ),
.axi_mst_ar_chan_t( axi_mst_ar_chan_t ),
.axi_mst_r_chan_t ( axi_mst_r_chan_t ),
.axi_mst_w_chan_t ( axi_mst_w_chan_t ),
.axi_mst_b_chan_t ( axi_mst_b_chan_t ),
.axi_mst_req_t ( axi_mst_req_t ),
.axi_mst_rsp_t ( axi_mst_rsp_t ),
.axi_slv_req_t ( axi_slv_req_t ),
Expand Down
6 changes: 3 additions & 3 deletions sw/include/dif/uart.h
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Expand Up @@ -27,19 +27,19 @@
#define UART_LINE_STATUS_THR_EMPTY_BIT 5
#define UART_LINE_STATUS_TMIT_EMPTY_BIT 6

void uart_init(void *uart_base, uint64_t freq, uint64_t baud);
void uart_init(void *uart_base, uint32_t freq, uint32_t baud);

int uart_read_ready(void *uart_base);

void uart_write(void *uart_base, uint8_t byte);

void uart_write_str(void *uart_base, void *src, uint64_t len);
void uart_write_str(void *uart_base, void *src, uint32_t len);

void uart_write_flush(void *uart_base);

uint8_t uart_read(void *uart_base);

void uart_read_str(void *uart_base, void *dst, uint64_t len);
void uart_read_str(void *uart_base, void *dst, uint32_t len);

// Default UART provides console
void _putchar(char byte);
Expand Down
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