feat: add native axi_to_apb converter

.gitlab-ci.yml

@@ -119,6 +119,7 @@ run_vsim:
           - axi_modify_address
           - axi_serializer
           - axi_sim_mem
+          - axi_to_apb
 
 # Modules that pull in shared submodules keep explicit additional dependencies
 # to avoid missing a rerun when a shared submodule changes.

Bender.yml

@@ -91,6 +91,7 @@ sources:
   - src/axi_interleaved_xbar.sv
   - src/axi_iw_converter.sv
   - src/axi_lite_xbar.sv
+  - src/axi_to_apb.sv
   - src/axi_xbar_unmuxed.sv
   - src/axi_to_mem_banked.sv
   - src/axi_to_mem_interleaved.sv
@@ -131,6 +132,7 @@ sources:
       - test/tb_axi_lite_regs.sv
       - test/tb_axi_iw_converter.sv
       - test/tb_axi_lite_to_apb.sv
+      - test/tb_axi_to_apb.sv
       - test/tb_axi_lite_to_axi.sv
       - test/tb_axi_lite_xbar.sv
       - test/tb_axi_modify_address.sv

CHANGELOG.md

@@ -7,6 +7,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 
 ## Unreleased
 
+### Added
+- `axi_to_apb`: AXI4+ATOP to APB4 bridge supporting data-width downsizing and address truncation,
+  built on `axi_to_detailed_mem`. Adds the `axi_to_apb_intf` interface variant and the
+  `tb_axi_to_apb` testbench.
+
 ## 0.39.10 - 2026-06-19
 
 ### Added

Makefile

@@ -35,6 +35,7 @@ TBS         ?= axi_addr_test \
                axi_modify_address \
                axi_serializer \
                axi_sim_mem \
+               axi_to_apb \
                axi_to_axi_lite \
                axi_to_mem_banked \
                axi_xbar

README.md

@@ -67,6 +67,7 @@ In addition to the documents linked in the following table, we are setting up [d
 | [`axi_serializer`](src/axi_serializer.sv)                   | Serializes transactions with different IDs to the same ID.                                           |                                  |
 | [`axi_throttle`](src/axi_throttle.sv)                       | Limits the maximum number of outstanding transfers sent to the downstream logic.                     |                                  |
 | [`axi_test`](src/axi_test.sv)                               | A set of testbench utilities for AXI interfaces.                                                     |                                  |
+| [`axi_to_apb`](src/axi_to_apb.sv)                           | AXI4 to APB4 protocol converter with data-width downsizing and optional address decoding.            |                                  |
 | [`axi_to_axi_lite`](src/axi_to_axi_lite.sv)                 | AXI4 to AXI4-Lite protocol converter.                                                                |                                  |
 | [`axi_to_mem`](src/axi_to_mem.sv)                           | AXI4 to memory protocol (req, gnt, rvalid) converter. Additional banked, interleaved, split variant. |                                  |
 | [`axi_xbar`](src/axi_xbar.sv)                               | Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports.               | [Doc](doc/axi_xbar.md)           |

scripts/run_vsim.sh

@@ -241,6 +241,12 @@ exec_test() {
                 done
             done
             ;;
+        axi_to_apb)
+            for DW in 32 64; do
+                call_vsim tb_axi_to_apb -gTbAxiDataWidth=$DW \
+                        -t 1ns -coverage -voptargs="+acc +cover=bcesfx"
+            done
+            ;;
         *)
             call_vsim tb_$1 -t 1ns -coverage -voptargs="+acc +cover=bcesfx"
             ;;