feat: add native axi_to_apb converter

[fischeti]

This PR adds a native axi_to_apb converter, which supports both downsizing datawidth and truncating the address.

Current situation

It is already possible now to convert from AXI to APB but multiple modules are needed like 1) axi_to_axi_lite ─▶ axi_lite_to_apb or 2) axi_to_reg ─▶ reg_to_apb. Both add intermediate protocol signals and generally make the code more verbose. Further, 2) uses a non-standard protocol and pulls in register_interface as a dependency.

Also, 1) has the disadvantage that it pulls in a axi_to_axi_lite which has relatively heavy burst splitter and other components, which is overkill to convert to APB. Further, neither axi_to_axi_lite nor axi_lite_to_apb allow to natively downsize the datawidth, hence a axi_lite_dw_converter is also needed.

Exploration

I prototyped three ways to bridge AXI4+ATOP to APB4 and compared area (post-synth, gate equivalents):

Approach	Area
axi_to_axi_lite → axi_lite_dw_converter → axi_lite_to_apb chain	11.6 kGE
axi_to_detailed_mem + inline APB master (this PR)	9.3 kGE	✅ chosen
Native AXI→APB FSM	8.3 kGE

The AXI4-Lite chain was the heaviest: it drags in burst splitting, and a Lite data-width converter.

A fully native FSM was the smallest (~10% below the chosen option), but it was vibecoded so not proven logic, and code complexity is higher.

The chosen axi_to_detailed_mem + inline APB master sits in between: it reuses axi_to_detailed_mem the AXI conversion. It is ~20% smaller than the Lite chain.

Verification

The adapter is verified with a tb_axi_to_apb testbench, that checks the APB interface for protocol compliancy, as well as an AXI scoreboard to check for correct data. I also added different types of slaves (ideal, random) to simulate backpressure.