Add DDR-based MLO support for Zynq devices#1607

Draft

klassen9 wants to merge 16 commits into

klassen9:feature/mlo_ddr

Commits on Jun 11, 2026

Add a static and runtime writeable address offsets to fetch weights and loop control
klassen9
committed

Commits on Jun 12, 2026

Add a address config to set the base address for MLO
klassen9
committed

Commits on Jun 15, 2026

Commits on Jun 18, 2026

Change logic to wire for continuously updating signals
klassen9
committed
Change mux to prioritize intermediate frames to fix batch size issue
klassen9
committed

Commits on Jun 23, 2026

Enable multi-job write_bitstream based on NUM_DEFAULT_WORKERS
klassen9
committed

Commits on Jun 24, 2026

Commits on Jun 25, 2026

Change m_axi_hbm to m_axi_intermediate_frame
klassen9
committed