Add DDR-based MLO support for Zynq devices

[klassen9]

Extends FINN's MLO flow (loop-based weight offloading via FINNLoop) to store weights and intermediate frames in DDR rather than only HBM, enabling MLO on Zynq-class boards without HBM. Memory placement is selectable via build config, with address offsets generated automatically and threaded through the RTL, Zynq build, and PYNQ driver. The existing HBM path is unchanged by default.

• Build config: new mlo_weight_mem option to select between HBM and DDR
• Address handling: new AssignMemoryOffset transform assigns offsets to weight and intermediate-frame regions in a shared DDR layout. Offset and base-address signals added to fetch_weights/loop_control, plus a new address_config RTL module.
• Zynq build & driver: make_zynq_proj/stitched IP wired up for DDR base addresses. PYNQ driver extended for MLO.
• RTL fixes: byte-aligned intermediate_frames padding, mux prioritizes intermediate frames to fix a batch-size bug, corrected fetch-weight sizing and .dat generation.
• Testing: New end-to-end DDR MLO test plus extended FINNLoop tests covering additional MLO edge cases.

TODO:

• Rename m_axi_hbm (no longer HBM-specific now that DDR is supported).
• Merge with dev after PR Feature/tiling mlo #1566 is merged.
• Some test cases currently fail due to the fetch weight component. At least some of these are fixed by Feature/tiling mlo #1566.

Misc:

• Parallel write_bitstream jobs via NUM_DEFAULT_WORKERS
• verify_step now has a batched argument which allows for real batching