[LSQ] Move vhdl_gen files to core_gen

tools/backend/lsq-generator-python/README.md

@@ -89,7 +89,7 @@ Configuration parameters needed for both chisel and Python based LSQ-generator c
 - **lsq-generator.py**  
   Runs the tool.
 
-- **vhdl_gen/**
+- **core_gen/**
   - **\_\_init__.py**  
     Re-exports a curated list of public API symbols (e.g. `main`, `generate`, `Logic`, `LSQ`).
 
@@ -103,7 +103,7 @@ Configuration parameters needed for both chisel and Python based LSQ-generator c
     Defines the `Configs` class.
 
   - **context.py**  
-    Defines the `VHDLContext` class. It substitutes the previous `global` VHDL context variables.
+    Defines the `VHDLContext` class. It substitutes the previous `global` context variables.
 
   - **utils.py**  
     - Defines `VHDLLogicType`, `VHDLLogicVecType`, `VHDLLogicTypeArray`, `VHDLLogicVecTypeArray`, `OpTab`.
@@ -113,8 +113,8 @@ Configuration parameters needed for both chisel and Python based LSQ-generator c
   - **signals.py**  
     Defines the four signal classes:  `Logic`, `LogicVec`, `LogicArray`, `LogicVecArray`.
 
-  - **vhdlgen/operators/**  
-    Low-level functions that generate VHDL snippets:  
+  - **core_gen/operators/**  
+    Low-level functions that generate snippets:  
     - `assign.py`: `Op`  
     - `arithmetic.py`: `WrapAdd`, `WrapAddConst`, `WrapSub`
     - `conversions.py`: `VecToArray`, `BitsToOH`, `BitsToOHSub1`, `OHToBits`
@@ -123,7 +123,7 @@ Configuration parameters needed for both chisel and Python based LSQ-generator c
     - `reduction.py`: `ReduceLogicVec`, `ReduceLogicArray`, `ReduceLogicVecArray`, `Reduce`
     - `shifts.py`: `RotateLogicVec`, `RotateLogicArray`, `RotateLogicVecArray`, `CyclicLeftShift`
 
-  - **vhdlgen/generators/**  
+  - **core_gen/generators/**  
     High-level modules that build complete entities/architectures:  
     - `dispatchers.py` : `PortToQueueDispatcher`, `QueueToPortDispatcher`, `PortToQueueDispatcherInit`, `QueueToPortDispatcherInit`
     - `group_allocator.py` : `GroupAllocator`, `GroupAllocatorInit`

tools/backend/lsq-generator-python/vhdl_gen/__init__.py → tools/backend/lsq-generator-python/core_gen/__init__.py

@@ -1,10 +1,10 @@
-# vhdl_gen/__init__.py
-from vhdl_gen.utils import (
+# core_gen/__init__.py
+from core_gen.utils import (
     VHDLLogicType, VHDLLogicVecType, VHDLLogicTypeArray, VHDLLogicVecTypeArray,
     OpTab,
 )
-from vhdl_gen.configs import GetConfigs, Configs
-from vhdl_gen.codegen import codeGen
+from core_gen.configs import GetConfigs, Configs
+from core_gen.codegen import codeGen
 
 
 # from vhdlgen import *

tools/backend/lsq-generator-python/vhdl_gen/cli.py → tools/backend/lsq-generator-python/core_gen/cli.py

@@ -1,6 +1,6 @@
 import argparse
-import vhdl_gen.configs as configs
-import vhdl_gen.codegen as code_gen
+import core_gen.configs as configs
+import core_gen.codegen as code_gen
 
 
 def parse_args():

tools/backend/lsq-generator-python/vhdl_gen/codegen.py → tools/backend/lsq-generator-python/core_gen/codegen.py

@@ -1,9 +1,9 @@
-from vhdl_gen.context import VHDLContext
-import vhdl_gen.generators.group_allocator as group_allocator
-import vhdl_gen.generators.dispatchers as dispatchers
-import vhdl_gen.generators.lsq as lsq
+from core_gen.context import VHDLContext
+import core_gen.generators.group_allocator as group_allocator
+import core_gen.generators.dispatchers as dispatchers
+import core_gen.generators.lsq as lsq
 
-import vhdl_gen.generators.lsq_submodule_wrapper as lsq_submodule_wrapper
+import core_gen.generators.lsq_submodule_wrapper as lsq_submodule_wrapper
 
 
 def codeGen(path_rtl, configs):

tools/backend/lsq-generator-python/vhdl_gen/configs.py → tools/backend/lsq-generator-python/core_gen/configs.py

@@ -30,7 +30,7 @@ class Configs:
     they are one of possible default configurations.
     """
 
-    name:          str = 'test'     # Name prefix used for generated VHDL files
+    name:          str = 'test'     # Name prefix used for generated files
     dataW:         int = 16         # Data width        (Number of bits for load/store data)
     addrW:         int = 13         # Address width     (Number of bits for memory address)
     idW:           int = 2          # ID width          (Number of bits for ID in the memory interface)

tools/backend/lsq-generator-python/vhdl_gen/context.py → tools/backend/lsq-generator-python/core_gen/context.py

@@ -3,7 +3,7 @@
 # ===----------------------------------------------------------------------===#
 class VHDLContext:
     """
-    A context object to replace global variables for VHDL code generation.
+    A context object to replace global variables for code generation.
     Holds indentation level, temporary name counter, and initialization strings.
     """
 

tools/backend/lsq-generator-python/vhdl_gen/generators/README.md → tools/backend/lsq-generator-python/core_gen/generators/README.md

@@ -1,7 +1,7 @@
-# `vhdl_gen.generators` — Folder Overview
+# `core_gen.generators` — Folder Overview
 
 This folder contains all code‑generation helpers responsible for emitting
-parameterized VHDL RTL used by the Load/Store Queue (LSQ) for the spatial computing and
+parameterized RTL used by the Load/Store Queue (LSQ) for the spatial computing and
 its supporting structures.
 
 
@@ -17,13 +17,13 @@ its supporting structures.
 - `dispatchers.py`
     - `PortToQueueDispatcher`: Generates the `entity` and `architecture` for port-to-queue dispatchers (load/store address & store data ports)
     - `QueueToPortDispatcher`: Generates the `entity` and `architecture` for queue-to-port dispatchers (load data & store-back ports).
-    - `PortToQueueDispatcherInst`: Produces the VHDL `port map` string to instantiate a Port-to-Queue dispatcher, connecting top-level signal (reset, clock, entries, and ports) to the dispatcher entity.
-    - `QueueToPortDispatcherInst`: Produces the VHDL `port map` string to instantiate a Queue-to-Port dispatcher, connecting top-level signal (reset, clock, entries, and ports) to the dispatcher entity.
+    - `PortToQueueDispatcherInst`: Produces the `port map` string to instantiate a Port-to-Queue dispatcher, connecting top-level signal (reset, clock, entries, and ports) to the dispatcher entity.
+    - `QueueToPortDispatcherInst`: Produces the `port map` string to instantiate a Queue-to-Port dispatcher, connecting top-level signal (reset, clock, entries, and ports) to the dispatcher entity.
 
 
 - `group_allocator.py`
     - `GroupAllocator`: Generates the `entity` and `architecture` for the group allocator, managing handshake between load and store groups based on free entry counts and load-store ordering.
-    - `GroupAllocatorInst`: Produces the VHDL `port map` string to instantiate the Group Allocator, connecting top-level signal to the group allocator entity.
+    - `GroupAllocatorInst`: Produces the `port map` string to instantiate the Group Allocator, connecting top-level signal to the group allocator entity.
 
 - `lsq.py`
-    - `LSQ`: Top-Level generator that emits a complete LSQ VHDL design by instantiating the GroupAllocator and various dispatchers, connecting them to memory interfaces, load/store queues, and optional features (pipelining, master interface).
+    - `LSQ`: Top-Level generator that emits a complete LSQ design by instantiating the GroupAllocator and various dispatchers, connecting them to memory interfaces, load/store queues, and optional features (pipelining, master interface).

tools/backend/lsq-generator-python/core_gen/generators/__init__.py

@@ -0,0 +1,10 @@
+# core_gen/generators/__init__.py
+from core_gen.generators.dispatchers import PortToQueueDispatcher, QueueToPortDispatcher
+from core_gen.generators.group_allocator import GroupAllocator
+from core_gen.generators.lsq import LSQ
+
+__all__ = [
+    "PortToQueueDispatcher", "QueueToPortDispatcher",
+    "GroupAllocator",
+    "LSQ",
+]

tools/backend/lsq-generator-python/vhdl_gen/generators/dispatchers.py → tools/backend/lsq-generator-python/core_gen/generators/dispatchers.py

@@ -1,6 +1,6 @@
-from vhdl_gen.context import VHDLContext
-from vhdl_gen.signals import *
-from vhdl_gen.operators import *
+from core_gen.context import VHDLContext
+from core_gen.signals import *
+from core_gen.operators import *
 
 
 class PortToQueueDispatcher:
@@ -18,7 +18,7 @@ def __init__(
 
         Models a dispatcher that routes signals from multiple ports to queue entries.
 
-        This class encapsulates the logic for generating a VHDL module that takes
+        This class encapsulates the logic for generating a module that takes
         arguments from a specific access port and passes them to a corresponding
         queue entry. 
 
@@ -51,9 +51,9 @@ def __init__(
                                     configs.ldpAddrW
                                 )
 
-            # You can later generate VHDL entity and architecture by
+            # You can later generate entity and architecture by
             #     ptq_dispatcher_lda.generate(...)
-            # You can later instantiate VHDL entity by
+            # You can later instantiate entity by
             #     ptq_dispatcher_lda.instantiate(...)
 
         """
@@ -67,11 +67,11 @@ def __init__(
 
     def generate(self, path_rtl) -> None:
         """
-        Generates the VHDL 'entity' and 'architecture' sections for a dispatcher
+        Generates the 'entity' and 'architecture' sections for a dispatcher
         that passes arguments from a specific access port to a corresponding queue entry.
 
         Parameters:
-            path_rtl    : Output directory for VHDL files.
+            path_rtl    : Output directory for files.
 
         Output:
             Appends the 'entity' and 'architecture' definitions
@@ -99,9 +99,9 @@ def generate(self, path_rtl) -> None:
         """
 
         # ctx: VHDLContext for code generation state.
-        # When we generate VHDL entity and architecture, we can use this context as a local variable.
+        # When we generate entity and architecture, we can use this context as a local variable.
         # We only need to get the context as a parameter when we instantiate the module.
-        # It saves all information we need when we generate VHDL entity and architecture code.
+        # It saves all information we need when we generate entity and architecture code.
         ctx = VHDLContext()
 
         ctx.tabLevel = 1
@@ -210,7 +210,7 @@ def instantiate(
         """
         Port-to-Queue Dispatcher Instantiation
 
-        Creates the VHDL port mapping for the Port-to-Queue dispatcher entity.
+        Creates the port mapping for the Port-to-Queue dispatcher entity.
         Connects the top-level signals (reset, clock, port and entry signals)
         to the internal dispatcher instance named <self.module_name>_dispatcher.
 
@@ -227,7 +227,7 @@ def instantiate(
             queue_head_oh_i      : One-hot vector indicating the current head index of the queue.
 
         Returns:
-            VHDL instantiation string for inclusion in the architecture body.
+            instantiation string for inclusion in the architecture body.
 
         Example (Load Address Port Dispatcher):
             arch += ptq_dispatcher_lda.instantiate(
@@ -332,7 +332,7 @@ def __init__(
 
         Models a dispatcher that routes signals from queue entries to access ports.
 
-        This class encapsulates the logic for generating a VHDL module that takes
+        This class encapsulates the logic for generating a module that takes
         data from queue entries and routes it to the correct outgoing port based on
         priority. 
 
@@ -361,9 +361,9 @@ def __init__(
                                     portAddrW=configs.ldpAddrW
                                 )
 
-            # You can later generate VHDL entity and architecture by
+            # You can later generate entity and architecture by
             #     qtp_dispatcher_ldd.generate(...)
-            # You can later instantiate VHDL entity by
+            # You can later instantiate entity by
             #     qtp_dispatcher_ldd.instantiate(...)
         """
 
@@ -379,11 +379,11 @@ def generate(self, path_rtl) -> None:
         """
         Queue-to-Port (Entry-to-Port) Dispatcher
 
-        Generates the VHDL 'entity' and 'architecture' sections for a dispatcher
+        Generates the 'entity' and 'architecture' sections for a dispatcher
         that routes data from queue entries to their access ports.
 
         Parameters:
-            path_rtl    : Output directory for VHDL files.
+            path_rtl    : Output directory for files.
 
         Output:
             Appends the 'entity' and 'architecture' definitions
@@ -412,9 +412,9 @@ def generate(self, path_rtl) -> None:
         """
 
         # ctx: VHDLContext for code generation state.
-        # When we generate VHDL entity and architecture, we can use this context as a local variable.
+        # When we generate entity and architecture, we can use this context as a local variable.
         # We only need to get the context as a parameter when we instantiate the module.
-        # It saves all information we need when we generate VHDL entity and architecture code.
+        # It saves all information we need when we generate entity and architecture code.
         ctx = VHDLContext()
 
         ctx.tabLevel = 1
@@ -526,7 +526,7 @@ def instantiate(
         """
         Queue-to-Port Dispatcher Instantiation
 
-        Creates the VHDL port mapping for the Queue-to-Port dispatcher entity.
+        Creates the port mapping for the Queue-to-Port dispatcher entity.
         Connects the top-level signals (reset, clock, entry and port signals)
         to the internal dispatcher instance named <self.module_name>_dispatcher.
 
@@ -543,7 +543,7 @@ def instantiate(
             queue_head_oh_i      : One-hot vector indicating the current head index of the queue.
 
         Returns:
-            VHDL instantiation string for inclusion in the architecture body.
+            instantiation string for inclusion in the architecture body.
 
 
         Example:

tools/backend/lsq-generator-python/vhdl_gen/generators/group_allocator.py → tools/backend/lsq-generator-python/core_gen/generators/group_allocator.py

@@ -1,8 +1,8 @@
-from vhdl_gen.context import VHDLContext
-from vhdl_gen.signals import Logic, LogicArray, LogicVec, LogicVecArray
-from vhdl_gen.operators import Op, WrapSub, Mux1HROM, CyclicLeftShift, CyclicPriorityMasking
-from vhdl_gen.utils import MaskLess
-from vhdl_gen.configs import Configs
+from core_gen.context import VHDLContext
+from core_gen.signals import Logic, LogicArray, LogicVec, LogicVecArray
+from core_gen.operators import Op, WrapSub, Mux1HROM, CyclicLeftShift, CyclicPriorityMasking
+from core_gen.utils import MaskLess
+from core_gen.configs import Configs
 
 
 class GroupAllocator:
@@ -17,7 +17,7 @@ def __init__(
 
         Models a group allocator for a Load-Store Queue (LSQ) system.
 
-        This class encapsulates the logic for generating a VHDL module that allocates
+        This class encapsulates the logic for generating a module that allocates
         space for groups of memory operations (loads and stores) in the load queue and 
         the store queue.
 
@@ -36,9 +36,9 @@ def __init__(
                     configs=configs
                 )
 
-            # You can later generate VHDL entity and architecture by
+            # You can later generate entity and architecture by
             #     ga.generate(...)
-            # You can later instantiate VHDL entity by
+            # You can later instantiate entity by
             #     ga.instantiate(...)
         """
 
@@ -48,10 +48,10 @@ def __init__(
 
     def generate(self, path_rtl) -> None:
         """
-        Generates the VHDL 'entity' and 'architecture' sections for a group allocator.
+        Generates the 'entity' and 'architecture' sections for a group allocator.
 
         Parameters:
-            path_rtl    : Output directory for VHDL files.
+            path_rtl    : Output directory for files.
 
         Output:
             Appends the 'entity' and 'architecture' definitions
@@ -80,9 +80,9 @@ def generate(self, path_rtl) -> None:
         """
 
         # ctx: VHDLContext for code generation state.
-        # When we generate VHDL entity and architecture, we can use this context as a local variable.
+        # When we generate entity and architecture, we can use this context as a local variable.
         # We only need to get the context as a parameter when we instantiate the module.
-        # It saves all information we need when we generate VHDL entity and architecture code.
+        # It saves all information we need when we generate entity and architecture code.
         ctx = VHDLContext()
 
         ctx.tabLevel = 1
@@ -277,7 +277,7 @@ def instantiate(
         """
         Group Allocator Instantiation
 
-        Creates the VHDL port mapping for the group allocator entity.
+        Creates the port mapping for the group allocator entity.
 
         Parameters:
             ctx                  : VHDLContext for code generation state.
@@ -298,7 +298,7 @@ def instantiate(
             ga_ls_order_o        : Group Allocator load-store order matrix
 
         Returns:
-            VHDL instantiation string for inclusion in the architecture body.
+            instantiation string for inclusion in the architecture body.
 
         Example:
             arch += ga.instantiate(