[LSQ] Move vhdl_gen files to core_gen - #982
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Jiahui17
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Jun 21, 2026
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I don't have the rights to merge myself, so if no other approvals are required someone else will have to merge |
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Move all the
vhdl_genfiles tocore_genand remove comment mentions of VHDL in preparation for making the script more general such that it can also generate Verilog, these are purely cosmetic changes. This is part of the larger pull request #914There are still two mentions of VHDL:
VHDLContext-> This will be replaced by the Emitter systemVHDLSignalsin utils.py -> These will be removed as they are duplicates of the signal definitions insignals.py