[BACKEND] Restrict broadcast-mul-reduce combine to f32 - #11164
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CombineBroadcastMulReducePattern matched any float addition of 32 bits or fewer, but its rewrite hardcodes an f32 zero scalar while typing the accumulator from the source element type. A half-precision reduction therefore built `tt.splat : (f32) -> tensor<MxNxf16>`, which fails the verifier, so a valid kernel using `tl.sum(x[:, :, None] * y[None, :, :], axis=1)` in f16 failed to compile. The predicate and rewrite have disagreed since the pattern was added in triton-lang#1889, so no narrow-precision reduction could produce a valid tt.dot. Match only f32, the only type the current rewrite handles validly, and leave narrower reductions as tt.reduce instead of producing invalid IR.
Jokeren
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Aug 4, 2026
| // The rewrite below creates an f32 zero scalar, so it can only handle f32 | ||
| // reductions without producing an ill-typed tt.splat. | ||
| if (auto addf = dyn_cast_or_null<arith::AddFOp>(op)) | ||
| return addf.getType().getIntOrFloatBitWidth() <= 32; |
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I remembered that this is a legacy pattern that we may consider to deprecate. cc @ThomasRaoux
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CombineBroadcastMulReducePatternrewrites:into:
Its
isAddF32predicate accepted any floating-pointarith.addfof 32 bits or fewer, but the rewrite hardcodes anf32zero scalar while typing the accumulator tensor from the source element type. Forf16, this produces an ill-typed splat that fails verification:An ordinary half-precision kernel therefore fails to compile:
The predicate and rewrite have disagreed since the pattern was added in #1889, so no narrow-precision reduction could produce a valid
tt.dot. This change therefore removes no working path: it matches onlyf32, the one type the current rewrite handles validly, while narrower reductions remain astt.reduceinstead of producing invalid IR.Adds an
f16negative lit test totest/Triton/combine.mlir.