WCD9375 support

arch/arm64/boot/dts/qcom/sm7150-xiaomi-davinci.dtsi

@@ -586,6 +586,41 @@
 	};
 };
 
+&swr1 {
+	status = "okay";
+
+	wcd_rx: codec@0,4 {
+		compatible = "sdw20217010a00";
+		reg = <0 4>;
+
+		qcom,rx-port-mapping = <1 2 3 4 5>;
+		qcom,rx-channel-mapping = /bits/ 8 <1 2 1 1 2 1 1 2>;
+	};
+};
+
+&swr2 {
+	status = "okay";
+	wcd_tx: codec@0,3 {
+		compatible = "sdw20217010a00";
+		reg = <0 3>;
+
+		qcom,tx-port-mapping = <2 3 4 5>;
+		qcom,tx-channel-mapping = /bits/ 8 <1 1 2 1 2 4 1 2 4 8>;
+	};
+};
+
+&vamacro {
+	status = "okay";
+};
+
+&txmacro {
+	status = "okay";
+};
+
+&rxmacro {
+	status = "okay";
+};
+
 &venus {
 	firmware-name = "qcom/sm7150/xiaomi/davinci/venus.mbn";
 };

arch/arm64/boot/dts/qcom/sm7150.dtsi

@@ -4664,6 +4664,119 @@
 			status = "disabled";
 		};
 
+		txmacro: txmacro@62ec0000 {
+			compatible = "qcom,sm7150-lpass-tx-macro",
+				     "qcom,sm8250-lpass-tx-macro";
+			reg = <0 0x62ec0000 0 0x1000>;
+
+			clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&vamacro>;
+			clock-names = "mclk", "npl", "macro", "fsgen";
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&tx_swr_active>;
+
+			#clock-cells = <0>;
+			clock-output-names = "mclk";
+			#sound-dai-cells = <1>;
+			status = "disabled";
+		};
+
+		swr2: soundwire-controller@62ed0000 {
+			reg = <0 0x62ed0000 0 0x2000>;
+			compatible = "qcom,soundwire-v1.5.1";
+			status = "disabled";
+			interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&txmacro>;
+			clock-names = "iface";
+			label = "TX";
+
+			qcom,din-ports = <6>;
+			qcom,dout-ports = <1>;
+			qcom,ports-sinterval-low =		/bits/ 8 <0xff 0x01 0x01 0x03 0x03 0xff 0xff>;
+			qcom,ports-offset1 =			/bits/ 8 <0xff 0x01 0x00 0x01 0x00 0xff 0xff>;
+			qcom,ports-offset2 =			/bits/ 8 <0xff 0x00 0x00 0x00 0x00 0xff 0xff>;
+			qcom,ports-hstart =			/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-hstop =			/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-word-length =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-block-pack-mode =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-block-group-count =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-lane-control =		/bits/ 8 <0xff 0x00 0x01 0x00 0x01 0xff 0xff>;
+
+			#sound-dai-cells = <1>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+		};
+
+		rxmacro: rxmacro@62ee0000 {
+			compatible = "qcom,sm7150-lpass-rx-macro",
+				     "qcom,sm8250-lpass-rx-macro";
+			reg = <0 0x62ee0000 0 0x1000>;
+
+			clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&vamacro>;
+			clock-names = "mclk", "npl", "macro", "fsgen";
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&rx_swr_active>;
+
+			#clock-cells = <0>;
+			clock-output-names = "mclk";
+			#sound-dai-cells = <1>;
+		};
+
+
+		swr1: soundwire-controller@62ef0000 {
+			reg = <0 0x62ef0000 0 0x2000>;
+			compatible = "qcom,soundwire-v1.5.1";
+			status = "disabled";
+			interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&rxmacro>;
+			clock-names = "iface";
+			label = "RX";
+
+			qcom,din-ports = <1>;
+			qcom,dout-ports = <6>;
+
+			qcom,ports-sinterval-low =      /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff>;
+			qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff>;
+			qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff>;
+			qcom,ports-hstart =             /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-hstop =              /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff>;
+			qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff>;
+			qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0xff 0xff>;
+			qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff>;
+
+			#sound-dai-cells = <1>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+		};
+
+		vamacro: codec@62f20000 {
+			compatible = "qcom,sm7150-lpass-va-macro",
+				     "qcom,sm8250-lpass-va-macro";
+			reg = <0 0x62f20000 0 0x1000>;
+
+			clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+			clock-names = "mclk", "npl", "macro";
+
+			qcom,dmic-sample-rate = <2400000>; // insisted by the controller
+			vdd-micb-supply = <&vreg_l15a_1p8>; // insisted by the controller
+
+			#clock-cells = <0>;
+			clock-output-names = "fsgen";
+			#sound-dai-cells = <1>;
+		};
+
 		lpass_tlmm: pinctrl@62b52000 {
 			compatible = "qcom,sm7150-lpass-lpi-pinctrl";
 			/* SSC range: <0 0x62b40000 0 0x12000> */