slaclab · ruck314 · May 14, 2026 · Apr 9, 2026 · Apr 9, 2026 · Apr 10, 2026
diff --git a/.gitignore b/.gitignore
@@ -28,3 +28,4 @@ sim_build/
 .planning/
 planning/
 CLAUDE.md
+.DS_Store
diff --git a/axi/axi-lite/ip_integrator/AxiLiteCrossbarIpIntegrator.vhd b/axi/axi-lite/ip_integrator/AxiLiteCrossbarIpIntegrator.vhd
@@ -46,7 +46,7 @@ end entity AxiLiteCrossbarIpIntegrator;
 
 architecture mapping of AxiLiteCrossbarIpIntegrator is
 
-   constant NUM_AXIL_MASTERS_C : positive := 2;
+   constant NUM_AXIL_MASTERS_C : positive                                                        := 2;
    constant AXIL_XBAR_CONFIG_C : AxiLiteCrossbarMasterConfigArray(NUM_AXIL_MASTERS_C-1 downto 0) := genAxiLiteConfig(NUM_AXIL_MASTERS_C, x"0000_0000", 22, 20);
 
    constant NUM_CASCADE_MASTERS_C : positive := 2;
@@ -60,16 +60,16 @@ architecture mapping of AxiLiteCrossbarIpIntegrator is
          addrBits     => 17,
          connectivity => X"0001"));
 
-   signal axilClk : sl;
-   signal axilRst : sl;
-   signal axilReadMaster  : AxiLiteReadMasterType;
-   signal axilReadSlave   : AxiLiteReadSlaveType;
-   signal axilWriteMaster : AxiLiteWriteMasterType;
-   signal axilWriteSlave  : AxiLiteWriteSlaveType;
-   signal axilReadMasters  : AxiLiteReadMasterArray(NUM_AXIL_MASTERS_C-1 downto 0);
-   signal axilReadSlaves   : AxiLiteReadSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0)  := (others => AXI_LITE_READ_SLAVE_EMPTY_DECERR_C);
-   signal axilWriteMasters : AxiLiteWriteMasterArray(NUM_AXIL_MASTERS_C-1 downto 0);
-   signal axilWriteSlaves  : AxiLiteWriteSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C);
+   signal axilClk             : sl;
+   signal axilRst             : sl;
+   signal axilReadMaster      : AxiLiteReadMasterType;
+   signal axilReadSlave       : AxiLiteReadSlaveType;
+   signal axilWriteMaster     : AxiLiteWriteMasterType;
+   signal axilWriteSlave      : AxiLiteWriteSlaveType;
+   signal axilReadMasters     : AxiLiteReadMasterArray(NUM_AXIL_MASTERS_C-1 downto 0);
+   signal axilReadSlaves      : AxiLiteReadSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0)     := (others => AXI_LITE_READ_SLAVE_EMPTY_DECERR_C);
+   signal axilWriteMasters    : AxiLiteWriteMasterArray(NUM_AXIL_MASTERS_C-1 downto 0);
+   signal axilWriteSlaves     : AxiLiteWriteSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0)    := (others => AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C);
    signal cascadeReadMasters  : AxiLiteReadMasterArray(NUM_CASCADE_MASTERS_C-1 downto 0);
    signal cascadeReadSlaves   : AxiLiteReadSlaveArray(NUM_CASCADE_MASTERS_C-1 downto 0)  := (others => AXI_LITE_READ_SLAVE_EMPTY_DECERR_C);
    signal cascadeWriteMasters : AxiLiteWriteMasterArray(NUM_CASCADE_MASTERS_C-1 downto 0);

diff --git a/axi/axi-lite/ip_integrator/AxiLiteFifoPopIpIntegrator.vhd b/axi/axi-lite/ip_integrator/AxiLiteFifoPopIpIntegrator.vhd
@@ -55,7 +55,7 @@ end entity AxiLiteFifoPopIpIntegrator;
 
 architecture rtl of AxiLiteFifoPopIpIntegrator is
 
-   signal axilResetN        : sl := '1';
+   signal axilResetN        : sl                     := '1';
    signal axilReadMaster    : AxiLiteReadMasterType  := AXI_LITE_READ_MASTER_INIT_C;
    signal axilReadSlave     : AxiLiteReadSlaveType   := AXI_LITE_READ_SLAVE_INIT_C;
    signal axilWriteMaster   : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C;

diff --git a/axi/axi-lite/ip_integrator/AxiLiteFifoPushIpIntegrator.vhd b/axi/axi-lite/ip_integrator/AxiLiteFifoPushIpIntegrator.vhd
@@ -51,7 +51,7 @@ end entity AxiLiteFifoPushIpIntegrator;
 
 architecture rtl of AxiLiteFifoPushIpIntegrator is
 
-   signal axilResetN       : sl := '1';
+   signal axilResetN       : sl                     := '1';
    signal axilReadMaster   : AxiLiteReadMasterType  := AXI_LITE_READ_MASTER_INIT_C;
    signal axilReadSlave    : AxiLiteReadSlaveType   := AXI_LITE_READ_SLAVE_INIT_C;
    signal axilWriteMaster  : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C;

diff --git a/axi/axi-lite/ip_integrator/AxiLiteFifoPushPopIpIntegrator.vhd b/axi/axi-lite/ip_integrator/AxiLiteFifoPushPopIpIntegrator.vhd
@@ -59,7 +59,7 @@ end entity AxiLiteFifoPushPopIpIntegrator;
 
 architecture rtl of AxiLiteFifoPushPopIpIntegrator is
 
-   signal axilResetN        : sl := '1';
+   signal axilResetN        : sl                     := '1';
    signal axilReadMaster    : AxiLiteReadMasterType  := AXI_LITE_READ_MASTER_INIT_C;
    signal axilReadSlave     : AxiLiteReadSlaveType   := AXI_LITE_READ_SLAVE_INIT_C;
    signal axilWriteMaster   : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C;
@@ -159,11 +159,11 @@ begin
    ---------------------------------------------------------------------------
    -- Flatten the single exposed FIFO lanes
    ---------------------------------------------------------------------------
-   popFifoValid  <= popFifoValidVec(0);
-   loopFifoValid <= loopFifoValidVec(0);
+   popFifoValid   <= popFifoValidVec(0);
+   loopFifoValid  <= loopFifoValidVec(0);
    loopFifoAEmpty <= loopFifoAEmptyVec(0);
-   loopFifoAFull <= loopFifoAFullVec(0);
-   pushFifoValid <= pushFifoValidVec(0);
-   pushFifoDout  <= pushFifoDoutVec(0);
+   loopFifoAFull  <= loopFifoAFullVec(0);
+   pushFifoValid  <= pushFifoValidVec(0);
+   pushFifoDout   <= pushFifoDoutVec(0);
 
 end architecture rtl;
diff --git a/axi/axi-lite/ip_integrator/AxiLiteRamSyncStatusVectorIpIntegrator.vhd b/axi/axi-lite/ip_integrator/AxiLiteRamSyncStatusVectorIpIntegrator.vhd
@@ -52,7 +52,7 @@ end entity AxiLiteRamSyncStatusVectorIpIntegrator;
 
 architecture rtl of AxiLiteRamSyncStatusVectorIpIntegrator is
 
-   signal axilResetN      : sl := '1';
+   signal axilResetN      : sl                     := '1';
    signal axilReadMaster  : AxiLiteReadMasterType  := AXI_LITE_READ_MASTER_INIT_C;
    signal axilReadSlave   : AxiLiteReadSlaveType   := AXI_LITE_READ_SLAVE_INIT_C;
    signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C;
@@ -105,9 +105,9 @@ begin
    ---------------------------------------------------------------------------
    U_DUT : entity surf.AxiLiteRamSyncStatusVector
       generic map (
-         COMMON_CLK_G   => true,
-         CNT_WIDTH_G    => 8,
-         WIDTH_G        => 4)
+         COMMON_CLK_G => true,
+         CNT_WIDTH_G  => 8,
+         WIDTH_G      => 4)
       port map (
          wrClk           => wrClk,
          wrRst           => wrRst,

diff --git a/axi/axi-lite/ip_integrator/AxiLiteRingBufferIpIntegrator.vhd b/axi/axi-lite/ip_integrator/AxiLiteRingBufferIpIntegrator.vhd
@@ -60,7 +60,7 @@ end entity AxiLiteRingBufferIpIntegrator;
 
 architecture rtl of AxiLiteRingBufferIpIntegrator is
 
-   signal axilResetN      : sl := '1';
+   signal axilResetN      : sl                     := '1';
    signal axilReadMaster  : AxiLiteReadMasterType  := AXI_LITE_READ_MASTER_INIT_C;
    signal axilReadSlave   : AxiLiteReadSlaveType   := AXI_LITE_READ_SLAVE_INIT_C;
    signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C;

diff --git a/axi/axi-lite/ip_integrator/AxiLiteSequencerRamIpIntegrator.vhd b/axi/axi-lite/ip_integrator/AxiLiteSequencerRamIpIntegrator.vhd
@@ -76,7 +76,7 @@ end entity AxiLiteSequencerRamIpIntegrator;
 
 architecture rtl of AxiLiteSequencerRamIpIntegrator is
 
-   signal sAxiAResetN     : sl                     := '1';
+   signal sAxiAResetN      : sl                     := '1';
    signal sAxilReadMaster  : AxiLiteReadMasterType  := AXI_LITE_READ_MASTER_INIT_C;
    signal sAxilReadSlave   : AxiLiteReadSlaveType   := AXI_LITE_READ_SLAVE_INIT_C;
    signal sAxilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C;

diff --git a/axi/axi-lite/ip_integrator/AxiLiteWriteFilterIpIntegrator.vhd b/axi/axi-lite/ip_integrator/AxiLiteWriteFilterIpIntegrator.vhd
@@ -73,17 +73,17 @@ end entity AxiLiteWriteFilterIpIntegrator;
 
 architecture rtl of AxiLiteWriteFilterIpIntegrator is
 
-   constant FILTER_ADDR_C : Slv32Array(FILTER_SIZE_G-1 downto 0) := (0 => toSlv(FILTER_ADDR_0_G, 32), others => toSlv(FILTER_ADDR_0_G, 32));
-   signal sAxiAResetN     : sl := '1';
-   signal mAxiAResetN     : sl := '1';
-   signal sAxilReadMaster : AxiLiteReadMasterType  := AXI_LITE_READ_MASTER_INIT_C;
-   signal sAxilReadSlave  : AxiLiteReadSlaveType   := AXI_LITE_READ_SLAVE_INIT_C;
-   signal sAxilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C;
-   signal sAxilWriteSlave  : AxiLiteWriteSlaveType  := AXI_LITE_WRITE_SLAVE_INIT_C;
-   signal mAxilReadMaster  : AxiLiteReadMasterType  := AXI_LITE_READ_MASTER_INIT_C;
-   signal mAxilReadSlave   : AxiLiteReadSlaveType   := AXI_LITE_READ_SLAVE_INIT_C;
-   signal mAxilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C;
-   signal mAxilWriteSlave  : AxiLiteWriteSlaveType  := AXI_LITE_WRITE_SLAVE_INIT_C;
+   constant FILTER_ADDR_C  : Slv32Array(FILTER_SIZE_G-1 downto 0) := (0 => toSlv(FILTER_ADDR_0_G, 32), others => toSlv(FILTER_ADDR_0_G, 32));
+   signal sAxiAResetN      : sl                                   := '1';
+   signal mAxiAResetN      : sl                                   := '1';
+   signal sAxilReadMaster  : AxiLiteReadMasterType                := AXI_LITE_READ_MASTER_INIT_C;
+   signal sAxilReadSlave   : AxiLiteReadSlaveType                 := AXI_LITE_READ_SLAVE_INIT_C;
+   signal sAxilWriteMaster : AxiLiteWriteMasterType               := AXI_LITE_WRITE_MASTER_INIT_C;
+   signal sAxilWriteSlave  : AxiLiteWriteSlaveType                := AXI_LITE_WRITE_SLAVE_INIT_C;
+   signal mAxilReadMaster  : AxiLiteReadMasterType                := AXI_LITE_READ_MASTER_INIT_C;
+   signal mAxilReadSlave   : AxiLiteReadSlaveType                 := AXI_LITE_READ_SLAVE_INIT_C;
+   signal mAxilWriteMaster : AxiLiteWriteMasterType               := AXI_LITE_WRITE_MASTER_INIT_C;
+   signal mAxilWriteSlave  : AxiLiteWriteSlaveType                := AXI_LITE_WRITE_SLAVE_INIT_C;
 
 begin
 

diff --git a/axi/axi-stream/ip_integrator/AxiStreamBatchingFifoIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamBatchingFifoIpIntegrator.vhd
@@ -74,7 +74,7 @@ architecture rtl of AxiStreamBatchingFifoIpIntegrator is
       TUSER_BITS_C  => 1,
       TUSER_MODE_C  => TUSER_NORMAL_C);
 
-   signal axiResetN       : sl := '1';
+   signal axiResetN       : sl                     := '1';
    signal axilReadMaster  : AxiLiteReadMasterType  := AXI_LITE_READ_MASTER_INIT_C;
    signal axilReadSlave   : AxiLiteReadSlaveType   := AXI_LITE_READ_SLAVE_INIT_C;
    signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C;

diff --git a/axi/axi-stream/ip_integrator/AxiStreamCombinerIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamCombinerIpIntegrator.vhd
@@ -75,11 +75,11 @@ architecture rtl of AxiStreamCombinerIpIntegrator is
       TUSER_BITS_C  => TUSER_WIDTH_G,
       TUSER_MODE_C  => TUSER_NORMAL_C);
 
-   signal axisAResetN : sl := '1';
+   signal axisAResetN  : sl                               := '1';
    signal sAxisMasters : AxiStreamMasterArray(1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C);
-   signal sAxisSlaves  : AxiStreamSlaveArray(1 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C);
-   signal mAxisMaster  : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C;
-   signal mAxisSlave   : AxiStreamSlaveType  := AXI_STREAM_SLAVE_INIT_C;
+   signal sAxisSlaves  : AxiStreamSlaveArray(1 downto 0)  := (others => AXI_STREAM_SLAVE_INIT_C);
+   signal mAxisMaster  : AxiStreamMasterType              := AXI_STREAM_MASTER_INIT_C;
+   signal mAxisSlave   : AxiStreamSlaveType               := AXI_STREAM_SLAVE_INIT_C;
 
 begin
 

diff --git a/axi/axi-stream/ip_integrator/AxiStreamCompactIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamCompactIpIntegrator.vhd
@@ -69,7 +69,7 @@ architecture rtl of AxiStreamCompactIpIntegrator is
       TUSER_BITS_C  => TUSER_WIDTH_G,
       TUSER_MODE_C  => TUSER_NORMAL_C);
 
-   signal axisAResetN : sl := '1';
+   signal axisAResetN : sl                  := '1';
    signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C;
    signal sAxisSlave  : AxiStreamSlaveType  := AXI_STREAM_SLAVE_INIT_C;
    signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C;

diff --git a/axi/axi-stream/ip_integrator/AxiStreamConcatIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamConcatIpIntegrator.vhd
@@ -68,7 +68,7 @@ architecture rtl of AxiStreamConcatIpIntegrator is
       TUSER_BITS_C  => TUSER_WIDTH_G,
       TUSER_MODE_C  => TUSER_FIRST_LAST_C);
 
-   signal axisAResetN : sl := '1';
+   signal axisAResetN : sl                  := '1';
    signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C;
    signal sAxisSlave  : AxiStreamSlaveType  := AXI_STREAM_SLAVE_INIT_C;
    signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C;

diff --git a/axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd
@@ -71,13 +71,13 @@ architecture rtl of AxiStreamDeMuxIpIntegrator is
       0 => toSlv(TDEST_ROUTE_0_G, 8),
       1 => toSlv(TDEST_ROUTE_1_G, 8));
 
-   signal axisAResetN      : sl := '1';
-   signal dynamicRouteMasks : Slv8Array(1 downto 0) := (others => (others => '0'));
-   signal dynamicRouteDests : Slv8Array(1 downto 0) := (others => (others => '0'));
-   signal sAxisMaster      : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C;
-   signal sAxisSlave       : AxiStreamSlaveType  := AXI_STREAM_SLAVE_INIT_C;
-   signal mAxisMasters     : AxiStreamMasterArray(1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C);
-   signal mAxisSlaves      : AxiStreamSlaveArray(1 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C);
+   signal axisAResetN       : sl                               := '1';
+   signal dynamicRouteMasks : Slv8Array(1 downto 0)            := (others => (others => '0'));
+   signal dynamicRouteDests : Slv8Array(1 downto 0)            := (others => (others => '0'));
+   signal sAxisMaster       : AxiStreamMasterType              := AXI_STREAM_MASTER_INIT_C;
+   signal sAxisSlave        : AxiStreamSlaveType               := AXI_STREAM_SLAVE_INIT_C;
+   signal mAxisMasters      : AxiStreamMasterArray(1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C);
+   signal mAxisSlaves       : AxiStreamSlaveArray(1 downto 0)  := (others => AXI_STREAM_SLAVE_INIT_C);
 
 begin
 

diff --git a/axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd
@@ -26,59 +26,59 @@ use surf.AxiStreamPkg.all;
 entity AxiStreamFifoV2IpIntegrator is
    generic (
       -- IP Integrator Slave AXI Stream Configuration
-      S_INTERFACENAME      : string                     := "S_AXIS";
-      S_HAS_TLAST          : natural range 0 to 1       := 1;
-      S_HAS_TKEEP          : natural range 0 to 1       := 1;
-      S_HAS_TSTRB          : natural range 0 to 1       := 0;
-      S_HAS_TREADY         : natural range 0 to 1       := 1;
-      S_TUSER_WIDTH        : natural range 1 to 8       := 2;
-      S_TID_WIDTH          : natural range 1 to 8       := 1;
-      S_TDEST_WIDTH        : natural range 1 to 8       := 1;
-      S_TDATA_NUM_BYTES    : natural range 1 to 128     := 1;
+      S_INTERFACENAME   : string                 := "S_AXIS";
+      S_HAS_TLAST       : natural range 0 to 1   := 1;
+      S_HAS_TKEEP       : natural range 0 to 1   := 1;
+      S_HAS_TSTRB       : natural range 0 to 1   := 0;
+      S_HAS_TREADY      : natural range 0 to 1   := 1;
+      S_TUSER_WIDTH     : natural range 1 to 8   := 2;
+      S_TID_WIDTH       : natural range 1 to 8   := 1;
+      S_TDEST_WIDTH     : natural range 1 to 8   := 1;
+      S_TDATA_NUM_BYTES : natural range 1 to 128 := 1;
 
       -- IP Integrator Master AXI Stream Configuration
-      M_INTERFACENAME      : string                     := "M_AXIS";
-      M_HAS_TLAST          : natural range 0 to 1       := 1;
-      M_HAS_TKEEP          : natural range 0 to 1       := 1;
-      M_HAS_TSTRB          : natural range 0 to 1       := 0;
-      M_HAS_TREADY         : natural range 0 to 1       := 1;
-      M_TUSER_WIDTH        : natural range 1 to 8       := 2;
-      M_TID_WIDTH          : natural range 1 to 8       := 1;
-      M_TDEST_WIDTH        : natural range 1 to 8       := 1;
-      M_TDATA_NUM_BYTES    : natural range 1 to 128     := 1;
+      M_INTERFACENAME   : string                 := "M_AXIS";
+      M_HAS_TLAST       : natural range 0 to 1   := 1;
+      M_HAS_TKEEP       : natural range 0 to 1   := 1;
+      M_HAS_TSTRB       : natural range 0 to 1   := 0;
+      M_HAS_TREADY      : natural range 0 to 1   := 1;
+      M_TUSER_WIDTH     : natural range 1 to 8   := 2;
+      M_TID_WIDTH       : natural range 1 to 8   := 1;
+      M_TDEST_WIDTH     : natural range 1 to 8   := 1;
+      M_TDATA_NUM_BYTES : natural range 1 to 128 := 1;
 
       -- General Configurations
-      RST_ASYNC            : boolean                    := false;
-      INT_PIPE_STAGES      : natural range 0 to 16      := 0;  -- Internal FIFO setting
-      PIPE_STAGES          : natural range 0 to 16      := 1;
-      VALID_BURST_MODE     : boolean                    := false;  -- only used in VALID_THOLD_G>1
-      VALID_THOLD          : integer range 0 to (2**24) := 1;  -- =1 = normal operation
+      RST_ASYNC        : boolean                    := false;
+      INT_PIPE_STAGES  : natural range 0 to 16      := 0;  -- Internal FIFO setting
+      PIPE_STAGES      : natural range 0 to 16      := 1;
+      VALID_BURST_MODE : boolean                    := false;  -- only used in VALID_THOLD_G>1
+      VALID_THOLD      : integer range 0 to (2**24) := 1;  -- =1 = normal operation
                                         -- =0 = only when frame ready
                                                            -- >1 = only when frame ready or # entries
 
       -- FIFO configurations
-      GEN_SYNC_FIFO        : boolean                    := false;
-      FIFO_ADDR_WIDTH      : integer range 4 to 48      := 9;
-      FIFO_FIXED_THRESH    : boolean                    := true;
-      FIFO_PAUSE_THRESH    : integer range 1 to (2**24) := 1;
-      SYNTH_MODE           : string                     := "inferred";
-      MEMORY_TYPE          : string                     := "block";
+      GEN_SYNC_FIFO     : boolean                    := false;
+      FIFO_ADDR_WIDTH   : integer range 4 to 48      := 9;
+      FIFO_FIXED_THRESH : boolean                    := true;
+      FIFO_PAUSE_THRESH : integer range 1 to (2**24) := 1;
+      SYNTH_MODE        : string                     := "inferred";
+      MEMORY_TYPE       : string                     := "block";
 
       -- Internal FIFO width select, "WIDE", "NARROW" or "CUSTOM"
       -- WIDE uses wider of slave / master. NARROW  uses narrower.
       -- CUSOTM uses passed FIFO_DATA_WIDTH_G
-      INT_WIDTH_SELECT     : string                     := "WIDE";
-      INT_DATA_WIDTH       : natural range 1 to 16      := 16;
+      INT_WIDTH_SELECT : string                := "WIDE";
+      INT_DATA_WIDTH   : natural range 1 to 16 := 16;
 
       -- If VALID_THOLD_G /=1, FIFO that stores on tLast txns can be smaller.
       -- Set to 0 for same size as primary fifo (default)
       -- Set >4 for custom size.
       -- Use at own risk. Overflow of tLast fifo is not checked
-      LAST_FIFO_ADDR_WIDTH : integer range 0 to 48      := 0;
+      LAST_FIFO_ADDR_WIDTH : integer range 0 to 48 := 0;
 
       -- Index = 0 is output, index = n is input
-      CASCADE_PAUSE_SEL    : integer range 0 to (2**24) := 0;
-      CASCADE_SIZE         : integer range 1 to (2**24) := 1);
+      CASCADE_PAUSE_SEL : integer range 0 to (2**24) := 0;
+      CASCADE_SIZE      : integer range 1 to (2**24) := 1);
    port (
       -- IP Integrator Slave AXI Stream Interface
       S_AXIS_ACLK     : in  std_logic                                          := '0';

diff --git a/axi/axi-stream/ip_integrator/AxiStreamFlushIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamFlushIpIntegrator.vhd
@@ -61,7 +61,7 @@ architecture rtl of AxiStreamFlushIpIntegrator is
       TUSER_BITS_C  => TUSER_WIDTH_G,
       TUSER_MODE_C  => TUSER_NORMAL_C);
 
-   signal axisAResetN : sl := '1';
+   signal axisAResetN : sl                  := '1';
    signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C;
    signal sAxisSlave  : AxiStreamSlaveType  := AXI_STREAM_SLAVE_INIT_C;
    signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C;
@@ -133,11 +133,11 @@ begin
 
    U_DUT : entity surf.AxiStreamFlush
       generic map (
-         TPD_G         => TPD_G,
+         TPD_G          => TPD_G,
          RST_POLARITY_G => RST_POLARITY_G,
-         RST_ASYNC_G   => RST_ASYNC_G,
-         AXIS_CONFIG_G => AXIS_CONFIG_C,
-         SSI_EN_G      => SSI_EN_G)
+         RST_ASYNC_G    => RST_ASYNC_G,
+         AXIS_CONFIG_G  => AXIS_CONFIG_C,
+         SSI_EN_G       => SSI_EN_G)
       port map (
          axisClk     => axisClk,
          axisRst     => axisRst,