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Fixes and CI version bumps #45
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@@ -7,7 +7,7 @@ stages: | |
| - sim | ||
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| variables: | ||
| VSIM: "questa-2022.3 vsim" | ||
| VSIM: "questa-2026.1 vsim" | ||
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| build: | ||
| stage: build | ||
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| Original file line number | Diff line number | Diff line change |
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@@ -41,25 +41,27 @@ module obi_demux #( | |
| logic sbr_port_gnt; | ||
| logic sbr_port_rready; | ||
| logic rsp_phase_stalled; | ||
| logic [NumMgrPorts-1:0] mgr_reqs; | ||
| logic [NumMgrPorts-1:0] mgr_connect; | ||
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| select_t select_d, select_q; | ||
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| always_comb begin : proc_req | ||
| select_d = select_q; | ||
| cnt_up = 1'b0; | ||
| for (int i = 0; i < NumMgrPorts; i++) begin | ||
| mgr_ports_req_o[i].req = 1'b0; | ||
| mgr_ports_req_o[i].a = '0; | ||
| mgr_reqs[i] = 1'b0; | ||
| mgr_connect[i] = 1'b0; | ||
| end | ||
| sbr_port_gnt = 1'b0; | ||
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| if (!overflow) begin | ||
| // R-4.1.1: block source changes while a stalled R phase is active | ||
| if (sbr_port_select_i == select_q || (!rsp_phase_stalled && | ||
| (in_flight == '0 || (in_flight == 1 && cnt_down)))) begin | ||
|
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. An issue I see (not related to this PR), is that |
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| mgr_ports_req_o[sbr_port_select_i].req = sbr_port_req_i.req; | ||
| mgr_ports_req_o[sbr_port_select_i].a = sbr_port_req_i.a; | ||
| sbr_port_gnt = mgr_ports_rsp_i[sbr_port_select_i].gnt; | ||
| mgr_reqs[sbr_port_select_i] = sbr_port_req_i.req; | ||
| mgr_connect[sbr_port_select_i] = 1'b1; | ||
| sbr_port_gnt = mgr_ports_rsp_i[sbr_port_select_i].gnt; | ||
| end | ||
| end | ||
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@@ -69,6 +71,11 @@ module obi_demux #( | |
| end | ||
| end | ||
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| for (genvar i = 0; i < NumMgrPorts; i++) begin : gen_req_assign | ||
| assign mgr_ports_req_o[i].req = mgr_reqs[i]; | ||
| assign mgr_ports_req_o[i].a = mgr_connect[i] ? sbr_port_req_i.a : '0; | ||
| end | ||
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| assign sbr_port_rsp_o.gnt = sbr_port_gnt; | ||
| assign sbr_port_rsp_o.r = mgr_ports_rsp_i[select_q].r; | ||
| assign sbr_port_rsp_o.rvalid = mgr_ports_rsp_i[select_q].rvalid; | ||
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Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
You could drop this for-loop and just have a
mgr_reqs = '0;andmgr_connect = '0;to have nicer default signals, if you wanted to.