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This PR fixes the popcount output width calculation. The hamming weight of an input of width **INPUT_WIDTH** can range from **0** (all bits deasserted) to **INPUT_WIDTH** (all bits asserted), giving a total of **INPUT_WIDTH + 1** values. The minimum number of bits required to represent these values is **ceil(log2(INPUT_WIDTH+1))**. Some simulation waveforms generated using Vivado2024 are shown below:   Happy New Year! diskouna
Creates an `empty` signal to track when the linked data table is empty, and exposes both the `empty` and `full` signals at the interface of the module.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Assertion for the one bank case to make sure HideStrb is not used with it (incompatible). Warning for the one bank case generally (may be inefficient).
- Remove legacy Travis CI and Make targets used only therein - Add per-module Verilator elaboration target to Makefile - Fix Verilator elaboration errors - Implicit casting to enum (actual error that I got in Snitch, which triggered the need for this PR) - Errors with the default parameters - Add elaboration tests to both Github and Gitlab CIs - Add a script for environment setup on IIS machines (used also by Gitlab CI) --------- Co-authored-by: Claude Sonnet 4.6 <noreply@anthropic.com>
Replaces `parameter integer` and `localparam integer` with `parameter int unsigned` / `localparam int unsigned`, as `integer` is a 4-state type and has no meaningful applicability for parameters. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
This includes: - Module parameter port lists (parameters and dependent localparams) - Module body localparams derived from module parameters - All instantiation sites using named parameter binding - Comments and string literals that referenced old names - Both RTL source modules and testbench modules Hardcoded architectural constants (e.g. WIDTH = 16 in cc_exp_backoff) that do not depend on any module parameter are left in ALL_CAPS. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Remove the separate cc_stream_arbiter_flushable source and make the main stream arbiter carry the clearable implementation. Update the round-robin arbiter clear API, stream crossbar/omega-net users, manifests, waivers, and tests accordingly. Co-authored-by: Philippe Sauter <phsauter@iis.ee.ethz.ch>
Normalize clk_i, rst_ni, clr_i, and flush_i descriptions across affected modules and document the common sequential ports and macro usage in the README. Co-authored-by: Philippe Sauter <phsauter@iis.ee.ethz.ch>
When NumIn==1 and AxiVldRdy==0, gnt_o[0] was passed through unconditionally from gnt_i, ignoring req_i[0]. The multi-input path correctly gates with (AxiVldRdy | req_i[0]). Align the single-input corner case to the same logic. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
The read and write pointer updates previously fired on valid_i/ready_i alone, without checking the other side of the handshake. With assertions disabled or in synthesized netlists this corrupted the FIFO pointers whenever a push happened while full, or a pop happened while empty. Fix: gate read-pointer advance on (ready_i && valid_o) and write-pointer advance on (valid_i && ready_o). The SameCycleRW mechanism is unaffected — ready_o already includes the (SameCycleRW && ready_i && valid_o) term, so simultaneous push+pop when full continues to work correctly (#313). Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Addresses #323 Commits: Makefile: Remove -Wno-fatal from vlt-elab target src: Fix Verilator IMPLICIT warnings src: Fix Verilator MULTIDRIVEN warnings src: Fix Verilator UNOPTFLAT warnings src: Remove stale Verilator lint waivers src: Fix Verilator UNSIGNED warnings --------- Co-authored-by: Philippe Sauter <phsauter@iis.ee.ethz.ch>
Capture the receiver phase before decoding it into clear_o or isolate_o. This keeps the async phase payload contained within the CDC handshake instead of letting it fan out into the reset-control clear logic. isolate_o is now asserted more conservatively on each FSM phase transition while the registered phase decode catches up.
Forwards SyncStages into the gray FIFO sides and splits pointer/data handling into clearer source and destination path modules. Adds timed gray FIFO test coverage with async delay injection.
Renames the existing split side wrappers to the clearer _src / _dst naming scheme. Also adds section headers in the clearable 2-phase CDC testbench for readability.
Forwards the top-level SyncStages parameter into the 4-phase source and destination halves. Adds timed async-boundary test coverage for the 4-phase CDC.
Makes SyncStages configurable for cc_cdc_2phase and forwards it into the source and destination synchronizers. Adds timed async-boundary test coverage for the 2-phase CDC.
…338) Forwards async-reset control into the reset controller, clamps reset-controller sync stages, and splits the clearable gray FIFO reset handling into source/destination sides. Adds timed clear/reset coverage and updates the TB to inject delays across the exposed async channels.
Split reusable test support from common_cells-local testbenches by moving testbench sources into a separate Bender `tb` target. Include `test`, `tb`, `formal`, and `synth_test` sources in elaboration checks so CI catches standalone testbench, formal, and synthesis wrapper issues. Update the simulation scripts to compile both `test` and `tb` targets.
This PR restores the old modules, defines and functions defined from common_cells v1, rewritten as wrappers around the new v2 modules, defines and functions. Coexistence of v2 and v1 IPs allows larger projects (e.g. Cheshire) to gradually transition to common_cells v2, one IP at a time, significantly simplifying regression testing. A project can enforce strict v2 compliance with the bender target `cc_no_deprecated`. All v1 IPs print a warning about the deprecated status to inform the user that the replacement is needed. See discussion initiated by @ricted98 in #287. --------- Co-authored-by: Riccardo Tedeschi <riccardo.tedeschi6@unibo.it> Co-authored-by: Claude Sonnet 4.6 <noreply@anthropic.com> Co-authored-by: Philippe Sauter <phsauter@iis.ee.ethz.ch>
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This PR merges the v2 development branch into master and prepares the common_cells v2 beta API. It prefixes public modules, interfaces, testbenches and formal properties with
cc_, consolidates shared types/packages intocc_pkg, updates parameter and port naming, and restructures the CDC modules with explicit source/ destination sides.To ease migration, deprecated v1 compatibility wrappers are provided and can be disabled with the
cc_no_deprecatedBender target for strict v2-only builds. The branch also brings the accumulated functional fixes, expanded CDC/formal coverage, and the updated CI/lint/elaboration setup used during v2 testing.