fix(fpga): implement VCU128 DRAM controller without ECC correction - #272
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Tested locally on VCU128 with hpdcache and legacy, works good.
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The VCU128 DRAM controller comes natively with ECC protection. The current configuration generates erroneous AXI responses for any read on an uninitialized memory region, which can easily happen with caches implementing a WB policy. The legacy cache simply does not check if a response is erroneous, so the problem is hidden but still present. See: #247.
This PR fixes the issue by avoiding ECC usage on VCU128.