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gitlab-ci: Use detect-rtl-changes script #433

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221 changes: 25 additions & 196 deletions .gitlab-ci.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -3,56 +3,32 @@ variables:
VSIM: questa-2025.1 vsim
VERILATOR: oseda -2026.04 verilator

# Fetch the detect-rtl-changes script to skip a job if none of the sources it
# actually depends on changed with respect to master.
before_script:
- mkdir -p build
- curl --proto '=https' --tlsv1.2 -sSf
https://raw.githubusercontent.com/pulp-platform/pulp-actions/refs/heads/detect-rtl-changes/detect-rtl-changes/detect-rtl-changes.sh
-o build/detect-rtl-changes.sh
- chmod +x build/detect-rtl-changes.sh

# Recompile the simulation library only when the sources, their dependencies or
# the simulator version (pinned in this file) change. The compiled `work`
# library is handed to the test jobs as a regular GitLab artifact. The `changes`
# list is a superset of every `run_vsim` test trigger, so whenever a test runs
# its `needs: vsim` dependency is guaranteed to be part of the pipeline.
#
# Every `changes` rule compares against `master` (`compare_to`) rather than the
# previous commit. This makes the trigger reflect the cumulative diff of the
# whole branch, like memora's content-addressed cache did: a file touched
# anywhere on the branch keeps triggering its job until merged, so a later
# unrelated commit cannot "hide" an earlier failing change behind a green
# pipeline. Note this still trusts the hand-maintained dependency lists below;
# a missing entry silently skips a test.
vsim:
stage: build
script:
- build/detect-rtl-changes.sh -t test -t rtl -t simulation
-w .gitlab-ci.yml -w scripts/compile_vsim.sh || exit 0
- cd build && ../scripts/compile_vsim.sh
artifacts:
paths:
- build/work
expire_in: 1 day
rules:
- &build_common_change_rule
changes:
compare_to: 'refs/heads/master'
paths:
- .gitlab-ci.yml
- Bender.yml
- include/**/*
- src/**/*
- test/**/*
- changes:
compare_to: 'refs/heads/master'
paths:
- scripts/compile_vsim.sh
- scripts/run_vsim.sh

synopsys_dc:
stage: build
script:
- build/detect-rtl-changes.sh -t synth_test
-w .gitlab-ci.yml -w scripts/synth.sh || exit 0
- cd build && ../scripts/synth.sh
rules:
- *build_common_change_rule
- changes:
compare_to: 'refs/heads/master'
paths:
- scripts/synth.sh

fuse_xsim:
stage: build
Expand All @@ -70,189 +46,42 @@ verilator_lint:
script:
- scripts/run_verilator.sh

# Shared definition for the per-module simulation tests. The anchored rules are
# the full dependency set for modules that only depend on their own DUT and
# testbench. Modules with shared submodule dependencies append one local rule.
# All per-module simulation tests share this template. `TEST_MODULE` names
# both the DUT and its testbench (`test/tb_$TEST_MODULE.sv`); the testbench is
# the entry point `bender pickle --top` uses to resolve the module's actual
# (transitive) source dependencies.
.run_vsim:
stage: test
needs:
- vsim
script:
- build/detect-rtl-changes.sh -t test -t rtl -t simulation
-w .gitlab-ci.yml -w scripts/run_vsim.sh -- tb_$TEST_MODULE || exit 0
- cd build && ../scripts/run_vsim.sh --random-seed $TEST_MODULE
rules:
- &run_vsim_common_change_rule
changes:
compare_to: 'refs/heads/master'
paths:
- .gitlab-ci.yml
- Bender.yml
- include/**/*
- scripts/run_vsim.sh
- src/axi_pkg.sv
- src/axi_intf.sv
- src/axi_test.sv
- &run_vsim_module_change_rule
changes:
compare_to: 'refs/heads/master'
paths:
- src/$TEST_MODULE.sv
- test/tb_$TEST_MODULE.sv

# "Leaf" modules whose only RTL dependency is their own source file. Their
# trigger list is fully derivable from $TEST_MODULE, so they share a single
# matrix job. (`src/axi_addr_test.sv` does not exist; that path simply never
# matches and the test is triggered by its testbench instead.)
run_vsim:
extends: .run_vsim
parallel:
matrix:
- TEST_MODULE:
- axi_addr_test
- axi_atop_filter
- axi_cdc
- axi_delayer
- axi_dw_downsizer
- axi_dw_upsizer
- axi_fifo
- axi_isolate
- axi_iw_converter
- axi_lite_dw_converter
- axi_lite_mailbox
- axi_lite_regs
- axi_lite_to_apb
- axi_lite_to_axi
- axi_lite_xbar
- axi_modify_address
- axi_serializer
- axi_sim_mem

# Modules that pull in shared submodules keep explicit additional dependencies
# to avoid missing a rerun when a shared submodule changes.
axi_cdc:
extends: .run_vsim
variables:
TEST_MODULE: axi_cdc
rules:
- *run_vsim_common_change_rule
- *run_vsim_module_change_rule
- changes:
compare_to: 'refs/heads/master'
paths:
- src/axi_cdc_dst.sv
- src/axi_cdc_src.sv

axi_dw_downsizer:
extends: .run_vsim
variables:
TEST_MODULE: axi_dw_downsizer
rules:
- *run_vsim_common_change_rule
- *run_vsim_module_change_rule
- changes:
compare_to: 'refs/heads/master'
paths:
- src/axi_err_slv.sv
- src/axi_demux.sv
- src/axi_demux_simple.sv
- src/axi_dw_converter.sv

axi_dw_upsizer:
extends: .run_vsim
variables:
TEST_MODULE: axi_dw_upsizer
rules:
- *run_vsim_common_change_rule
- *run_vsim_module_change_rule
- changes:
compare_to: 'refs/heads/master'
paths:
- src/axi_err_slv.sv
- src/axi_demux.sv
- src/axi_demux_simple.sv
- src/axi_dw_converter.sv

axi_isolate:
extends: .run_vsim
variables:
TEST_MODULE: axi_isolate
rules:
- *run_vsim_common_change_rule
- *run_vsim_module_change_rule
- changes:
compare_to: 'refs/heads/master'
paths:
- src/axi_demux.sv
- src/axi_demux_simple.sv
- src/axi_err_slv.sv

axi_iw_converter:
extends: .run_vsim
variables:
TEST_MODULE: axi_iw_converter
rules:
- *run_vsim_common_change_rule
- *run_vsim_module_change_rule
- changes:
compare_to: 'refs/heads/master'
paths:
- src/axi_id_prepend.sv
- src/axi_id_remap.sv
- src/axi_demux.sv
- src/axi_demux_simple.sv
- src/axi_serializer.sv
- src/axi_mux.sv
- src/axi_id_serialize.sv

axi_lite_xbar:
extends: .run_vsim
variables:
TEST_MODULE: axi_lite_xbar
rules:
- *run_vsim_common_change_rule
- *run_vsim_module_change_rule
- changes:
compare_to: 'refs/heads/master'
paths:
- src/axi_err_slv.sv
- src/axi_lite_demux.sv
- src/axi_lite_mux.sv
- src/axi_lite_to_axi.sv

axi_to_axi_lite:
extends: .run_vsim
variables:
TEST_MODULE: axi_to_axi_lite
rules:
- *run_vsim_common_change_rule
- *run_vsim_module_change_rule
- changes:
compare_to: 'refs/heads/master'
paths:
- src/axi_atop_filter.sv
- src/axi_burst_splitter.sv

axi_to_mem_banked:
extends: .run_vsim
variables:
TEST_MODULE: axi_to_mem_banked
rules:
- *run_vsim_common_change_rule
- *run_vsim_module_change_rule
- changes:
compare_to: 'refs/heads/master'
paths:
- src/axi_demux.sv
- src/axi_demux_simple.sv
- src/axi_to_detailed_mem.sv
- src/axi_to_mem.sv

axi_xbar:
extends: .run_vsim
variables:
TEST_MODULE: axi_xbar
rules:
- *run_vsim_common_change_rule
- *run_vsim_module_change_rule
- changes:
compare_to: 'refs/heads/master'
paths:
- src/axi_demux.sv
- src/axi_demux_simple.sv
- src/axi_err_slv.sv
- src/axi_mux.sv
- src/axi_multicut.sv
- src/axi_xbar_unmuxed.sv
- axi_to_axi_lite
- axi_to_mem_banked
- axi_xbar
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