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Allow overlapping basic blocks#3662

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Schaeff wants to merge 17 commits into
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allow-overlapping-basic-blocks
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Allow overlapping basic blocks#3662
Schaeff wants to merge 17 commits into
mainfrom
allow-overlapping-basic-blocks

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@Schaeff

@Schaeff Schaeff commented Mar 12, 2026

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Comment thread openvm-riscv/src/isa/mod.rs Outdated
) -> Option<u64> {
match instruction.opcode.as_usize() {
opcode::OPCODE_JAL => Some(pc + instruction.c.as_canonical_u32() as u64),
opcode::OPCODE_JALR => None,

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can be removed to fallback to _ because it's dynamic

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Or actually:
We could potentially support this: JALR uses a register as input for the high bits of the destination, which is often set by AUIPC just before JALR.
Example (something like this):

auipc ra, <some_imm_hi> # sets ra = pc + some_imm_hi << 12 (something like this)
jalr ra, <some_imm_lo> # sets pc = ra + some_imm_lo

So we need to find the value of ra here. If jalr x0, imm, easy.
If jalr ra, imm, we can look at the previous instruction to check if it's AUIPC and read what was written to ra.

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ah right i remember this

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Implemented AUIPC + JALR


fn is_branching(instr: &Self::Instruction) -> bool;

/// Returns the static jump target of after a series of instructions, if known.

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typo

Comment on lines +51 to +69
fn signed_field_to_i64<F: PrimeField32>(value: F) -> i64 {
let value = value.as_canonical_u32();
if value < F::ORDER_U32 / 2 {
value as i64
} else {
value as i64 - F::ORDER_U32 as i64
}
}

fn jalr_imm<F: PrimeField32>(instruction: &Instruction<F>) -> u32 {
let imm_low = instruction.c.as_canonical_u32() & 0xffff;
let imm_high = if instruction.g == F::ONE {
0xffff0000
} else {
0
};
imm_low | imm_high
}

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Not sure about these..

@Schaeff

Schaeff commented Mar 18, 2026

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closing in favor or #3669

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2 participants