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1. huawei-csl/spire-hdl huawei-csl/spire-hdl Public

   Spire is a Python embedded domain-specific language (DSL) for RTL generation. Its built-in optimizations reduce area and delay of circuits and often beat the traditional Verilog/Yosys flow.

   Python 24 2

2. ioda_lidar ioda_lidar Public

   Open source time-of-flight 3D lidar from scratch: Optics, PCB, HDL, FW, SW.

   9

3. huawei-csl/rtlscout huawei-csl/rtlscout Public

   RTLScout is a agentic RTL optimization framework

   Verilog 21 3

4. SpinalDev SpinalDev Public

   Docker Development Environment for SpinalHDL

   Dockerfile 20 2

5. turpy turpy Public

   Python simulation of turbo and viterbi decoding.

   Jupyter Notebook 4 1

6. turpy_scppm_sim turpy_scppm_sim Public

   Python SCPPM simulation

   Python 3