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Specified the status of the VRAM DMA register once a transfer is done. #624

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Specified the status of the VRAM DMA register once a transfer is done. #624

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Update CGB_Registers.md
Phidias618 Sep 14, 2025
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Phidias618 Sep 14, 2025
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Moved the description of the state of the VRAM DMA source and destina…
Phidias618 Sep 26, 2025
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21 changes: 21 additions & 0 deletions src/CGB_Registers.md
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Expand Up @@ -39,13 +39,34 @@ tested on Echo RAM, OAM, FEXX, IO and HRAM\]. Trying to specify a source
address in VRAM will cause garbage to be copied.

The four lower bits of this address will be ignored and treated as 0.
After a transfer the address contained in this register pair is
by $10 for each block of $10 bytes transfered, these

@avivace avivace Apr 21, 2026

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Maybe this can be moved to a footnote (the fact that they cannot be observed directly etc)

registers being write-only, this can only be observed by doing another
transfer without updating these registers.


#### FF53–FF54 — HDMA3, HDMA4 (CGB Mode only): VRAM DMA destination (high, low) \[write-only\]

These two registers specify the address within 8000-9FF0 to which the
data will be copied. Only bits 12-4 are respected; others are ignored.
The four lower bits of this address will be ignored and treated as 0.

#### State of the VRAM DMA source/destination registers after a transfer

After a transfer, the source/destination registers are incremented by $10
for each block of $10 bytes transfered.
Despite both the VRAM DMA source/destination registers being write-only,
knowing their state after a transfer can turn useful when performing
multiple transfer in a row.
For instance, a transfer of one large block is mostly equivalent to
multiple transfers of smaller blocks, without needing to update the source
nor the destination registers between each of the smaller transfers.
Another use case would be to fill VRAM with the same $10 bytes block repeated
all over, as only the source address register would need be updated after each
transfer, the destination register being automatically incremented by
the block size after each transfer.


Comment on lines +42 to +69

@alloncm alloncm Apr 30, 2026

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IMO the "State of the VRAM DMA source/destination registers after a transfer" is redundant and just add noise to the page.

I think the best way representing this info is by adding the lines you added to FF51-FF52 to FF53-FF54 too by just copy pasting it.

Something like this:

Suggested change
After a transfer the address contained in this register pair is
by $10 for each block of $10 bytes transfered, these
registers being write-only, this can only be observed by doing another
transfer without updating these registers.
#### FF53–FF54 — HDMA3, HDMA4 (CGB Mode only): VRAM DMA destination (high, low) \[write-only\]
These two registers specify the address within 8000-9FF0 to which the
data will be copied. Only bits 12-4 are respected; others are ignored.
The four lower bits of this address will be ignored and treated as 0.
#### State of the VRAM DMA source/destination registers after a transfer
After a transfer, the source/destination registers are incremented by $10
for each block of $10 bytes transfered.
Despite both the VRAM DMA source/destination registers being write-only,
knowing their state after a transfer can turn useful when performing
multiple transfer in a row.
For instance, a transfer of one large block is mostly equivalent to
multiple transfers of smaller blocks, without needing to update the source
nor the destination registers between each of the smaller transfers.
Another use case would be to fill VRAM with the same $10 bytes block repeated
all over, as only the source address register would need be updated after each
transfer, the destination register being automatically incremented by
the block size after each transfer.
After a transfer the address pointed by those two registers equals `initial_address + ($10 * num_of_blocks_transferred)`.
Since those are write-only registers, this can only be observed by doing another transfer without writing them again.
#### FF53–FF54 — HDMA3, HDMA4 (CGB Mode only): VRAM DMA destination (high, low) \[write-only\]
These two registers specify the address within 8000-9FF0 to which the
data will be copied. Only bits 12-4 are respected; others are ignored.
The four lower bits of this address will be ignored and treated as 0.
After a transfer the address pointed by those two registers equals `initial_address + ($10 * num_of_blocks_transferred)`.
Since those are write-only registers, this can only be observed by doing another transfer without writing them again.

@ISSOtm ISSOtm May 1, 2026

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I've found that it makes sense to describe the overall functioning of the system in a single place, so that the reader can start to form a vague mental picture before getting into the individual components; otherwise, IME, the scattered information is very hard to assemble into the big picture. This line of reasoning is what has led us to creating the Graphics or Audio introduction pages.

@alloncm alloncm May 1, 2026

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I pretty much agree with you about the overview sections for complex systems, I just don't think that this specific case (post-transfer register state) rises to that level.
It's niche enough that IMO most developers will never really need it, and I worry that a dedicated section gives it more focus than it deserves and risks burying the more critical parts about the VRAM DMA system.

#### FF55 — HDMA5 (CGB Mode only): VRAM DMA length/mode/start

These registers are used to initiate a DMA transfer from ROM or RAM to
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