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Refactored, consolidated, and cleaned up RV32/RV64 ports#536

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fdesbiens:risc-v-refactoring
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Refactored, consolidated, and cleaned up RV32/RV64 ports#536
fdesbiens wants to merge 4 commits into
eclipse-threadx:devfrom
fdesbiens:risc-v-refactoring

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@fdesbiens fdesbiens commented May 26, 2026

Phase 1a — Clang port: use GNU assembly sources

  • Delete ports/risc-v32/clang/src/ (all 8 .S files had no Clang-specific directives; diverged only due to missing bug fixes)
  • Update clang/CMakeLists.txt to compile from ../gnu/src/
  • Change .global -> .weak for _tx_initialize_low_level in gnu/src/ (allows BSP override without linker conflicts; adopted from Clang port)

Phase 2a — tx_port.h consolidation

  • Create ports/risc-v32/common/tx_port_riscv32_common.h with all definitions shared between GNU and Clang ports
  • Reduce risc-v32/gnu/inc/tx_port.h to a thin wrapper (adds regression test extension block + version string)
  • Reduce risc-v32/clang/inc/tx_port.h to a thin wrapper (version string only, no regression test block)

Phase 2b — RV64 LONG/ULONG documentation

  • Add prominent comment in risc-v64/gnu/inc/tx_port.h explaining why LONG/ULONG are intentionally 32-bit on RV64 (ThreadX ABI requirement)

Phase 3a — Shared CMake helper

  • Create cmake/threadx_riscv_port.cmake with threadx_add_riscv_port()
  • Reduce all three port CMakeLists.txt to ~8 lines each

Phase 4a/b/c/d — Shared example-build drivers

  • Create canonical files in ports/risc-v_common/:
    inc/csr.h (uintptr_t, works RV32+RV64)
    example_build/plic/ (plic.c, plic.h)
    example_build/uart/ (uart_qemu_ns16550.c/h; static inline putc_nolock)
    example_build/trap/ (trap_qemu.c; XLEN-portable mcause constants)
  • Replace per-example copies with symlinks in all qemu_virt dirs and cva6_ariane
  • Fix OS_IS_INTERRUPT typo (was OS_IS_INTERUPT) in shared trap_qemu.c
  • Gate print_hex() behind TX_RISCV_TRAP_DEBUG

Phase 5a — RV64 QEMU CI test

  • Add ports/risc-v64/gnu/example_build/qemu_virt/test/ threadx_test_tx_gnu_riscv64_qemu.py

Phase 6a — entry.s → entry.S rename

  • Normalize case on all 4 example entry point files

Housekeeping

  • Rename azrtos_test_* → threadx_test_* (eliminate Azure RTOS branding)
  • Update CMakeLists.txt reference to match renamed test script

@fdesbiens
risc-v: refactor, consolidate, and clean up RV32/RV64 ports
3e53681 
Phase 1a — Clang port: use GNU assembly sources
- Delete ports/risc-v32/clang/src/ (all 8 .S files had no Clang-specific
  directives; diverged only due to missing bug fixes)
- Update clang/CMakeLists.txt to compile from ../gnu/src/
- Change .global -> .weak for _tx_initialize_low_level in gnu/src/
  (allows BSP override without linker conflicts; adopted from Clang port)

Phase 2a — tx_port.h consolidation
- Create ports/risc-v32/common/tx_port_riscv32_common.h with all
  definitions shared between GNU and Clang ports
- Reduce risc-v32/gnu/inc/tx_port.h to a thin wrapper (adds regression
  test extension block + version string)
- Reduce risc-v32/clang/inc/tx_port.h to a thin wrapper (version string
  only, no regression test block)

Phase 2b — RV64 LONG/ULONG documentation
- Add prominent comment in risc-v64/gnu/inc/tx_port.h explaining why
  LONG/ULONG are intentionally 32-bit on RV64 (ThreadX ABI requirement)

Phase 3a — Shared CMake helper
- Create cmake/threadx_riscv_port.cmake with threadx_add_riscv_port()
- Reduce all three port CMakeLists.txt to ~8 lines each

Phase 4a/b/c/d — Shared example-build drivers
- Create canonical files in ports/risc-v_common/:
    inc/csr.h               (uintptr_t, works RV32+RV64)
    example_build/plic/     (plic.c, plic.h)
    example_build/uart/     (uart_qemu_ns16550.c/h; static inline putc_nolock)
    example_build/trap/     (trap_qemu.c; XLEN-portable mcause constants)
- Replace per-example copies with symlinks in all qemu_virt dirs and cva6_ariane
- Fix OS_IS_INTERRUPT typo (was OS_IS_INTERUPT) in shared trap_qemu.c
- Gate print_hex() behind TX_RISCV_TRAP_DEBUG

Phase 5a — RV64 QEMU CI test
- Add ports/risc-v64/gnu/example_build/qemu_virt/test/
    threadx_test_tx_gnu_riscv64_qemu.py

Phase 6a — entry.s → entry.S rename
- Normalize case on all 4 example entry point files

Housekeeping
- Rename azrtos_test_* → threadx_test_* (eliminate Azure RTOS branding)
- Update CMakeLists.txt reference to match renamed test script

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
@fdesbiens fdesbiens requested a review from akifejaz May 26, 2026 14:31
@fdesbiens fdesbiens changed the title Reefactored, consolidated, and cleaned up RV32/RV64 ports Refactored, consolidated, and cleaned up RV32/RV64 ports May 26, 2026
@fdesbiens fdesbiens self-assigned this May 26, 2026
@fdesbiens fdesbiens moved this to In review in ThreadX Roadmap May 26, 2026
fdesbiens and others added 3 commits May 26, 2026 16:54
@fdesbiens
risc-v32: fix lazy FPU and mepc bugs; consolidate cmake and -Wconversion
8fb66e4 
Fix two pre-existing bugs in the RV32 GNU port assembly:

1. tx_thread_schedule.S: Solicited return path restores mstatus from slot
   14 before csrw to avoid clobbering mstatus with the fcsr value that t0
   held after the FP register restore block.

2. tx_thread_system_return.S: FP callee-saved registers were saved
   unconditionally before checking mstatus.FS, causing an illegal
   instruction trap (mcause=0x2) when a thread with FS=Off (lazy FPU,
   thread has never used FP) voluntarily yielded. Apply the same
   mstatus.FS guard pattern used in tx_thread_context_save.S: read
   mstatus first, isolate FS[1:0] bits, and skip fsw/fsd instructions
   if FS == Off.

Also fix cmake include path in all three port CMakeLists.txt files
(risc-v32/gnu, risc-v32/clang, risc-v64/gnu) to use a path relative to
CMAKE_CURRENT_LIST_DIR so the shared threadx_riscv_port.cmake helper is
found correctly whether ports are built standalone or as a subdirectory
of the test framework.

Disable -Wconversion for the RV64 test configuration: ULONG = unsigned
int (32-bit) is intentional for ThreadX ABI compatibility, but causes
spurious conversion warnings when sizeof() (size_t, 8 bytes on RV64) is
used in arithmetic with ULONG throughout common/src/.

Verified: 95/95 RV32 regression tests pass with QEMU virt.

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
@fdesbiens
gitignore: exclude build_m7/ and .codex local artifacts
d388596 
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
@fdesbiens
ci: disable RISC-V regression job (re-enable when ready)
052333b 
Comment out the riscv job in the regression workflow and remove it from
the deploy job's needs list. The job definition is preserved in-place
for easy re-enablement.

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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