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16 workflow runs

16 workflow runs

New: dCache Architecture Update (#2) FRISCV #298: Commit ca49894 pushed by dpretet

15m 41s amo

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15m 41s

New: dCache Architecture Update (#2) FRISCV #297: Commit a601aed pushed by dpretet

13m 31s amo

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New: dCache Architecture Update (#2) FRISCV #296: Commit ec2bad2 pushed by dpretet

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New: dCache Architecture Update (#2) FRISCV #295: Commit adecbd8 pushed by dpretet

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New: dCache Architecture Update (#12) FRISCV #294: Commit a9bdfff pushed by dpretet

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New: drafting a new bypass in dcache to address the AMO and IO reques… FRISCV #293: Commit 699c3fc pushed by dpretet

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New: Add A extension in memfy, now need to decide what to do in dcach… FRISCV #292: Commit 7373b05 pushed by dpretet

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New: Add A extension decoding FRISCV #291: Commit 9871c22 pushed by dpretet

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New: Add A extension decoding FRISCV #290: Commit ccbe3c7 pushed by dpretet

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New: Add A extension decoding FRISCV #289: Commit 68e7ed3 pushed by dpretet

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New: Add A extension decoding FRISCV #288: Commit 928b258 pushed by dpretet

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New: Replace testbench's RAM with the AXI4 version FRISCV #287: Commit 8f47b11 pushed by dpretet

1h 39m 43s amo

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1h 39m 43s

Fix: correct AXI4 signals and paths along the AXI fabric FRISCV #286: Commit 3bca727 pushed by dpretet

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Change: Move to AXI4 infrastructure FRISCV #285: Commit 804846e pushed by dpretet

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Fix simulation fileset FRISCV #284: Commit 3f6cc8d pushed by dpretet

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Change: Upgrade AXI-Crossbar to v1.1 FRISCV #283: Commit 29bb7aa pushed by dpretet

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