lopper:assists: Add RV32E (embedded) compiler/ABI support for MicroBlaze-V.#786
lopper:assists: Add RV32E (embedded) compiler/ABI support for MicroBlaze-V.#786sushil-dev-amd wants to merge 1 commit into
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…aze-V. Propagate the xlnx,use-embedded CPU property (set by SDTGen for MicroBlaze-V cores with C_USE_EMBEDDED) through to the generated build flags: - lop-microblaze-riscv.dts: emit rv32e/-mabi=ilp32e in cflags.yaml instead of rv32i/ilp32 when the core is configured as embedded, and apply the ABI flag to linkflags as well as cflags so BSP link-time multilib selection matches. Guard against the invalid use-embedded + hardware-FPU combination (RV32E has no standard hard-float ABI) and warn if use-embedded is set alongside a 64-bit data size (RV32E is 32-bit only). - gen_domain_dts.py: select RISCV_ISA_RV32E instead of RISCV_ISA_RV32I in the generated Zephyr SoC and board Kconfig when the parsed ISA string indicates an embedded (rv32e) core. Signed-off-by: Sushil Singh <sushilkumar.singh@amd.com>
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@sathishkumar-amd, @sivadur and @kedareswararao, please review the downstream compilation flags support to enable rv32e compilation for 32-bit arch using use_embedded flag (C_HAS_EMBEDDED parameter) from the DT. |
| content += "config RISCV_ISA_RV32I\n" | ||
| # Base ISA configuration - RV32E for embedded (reduced register set) MB-V | ||
| # cores (xlnx,use-embedded), RV32I otherwise. | ||
| isa_base_check = isa_string.split('_')[0] if isa_string else '' |
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can you add check to make sure isa_string variable is not empty like if isa_string: and keep your code inside it?
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okay will add it inside the if block below.
| is_embedded = use_embedded != [''] and use_embedded[0] == 1 and n['xlnx,data-size'].value[0] != 64 | ||
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| if is_embedded and n['xlnx,use-fpu'].value[0] != 0: | ||
| raise Exception('Invalid MicroBlaze-V configuration at {}: xlnx,use-embedded=1 (RV32E/ilp32e) is not compatible with a hardware FPU (xlnx,use-fpu={}). The RV32E ABI has no standard hard-float variant; disable the FPU or the embedded (RV32E) option.'.format(n.abs_path, n['xlnx,use-fpu'].value[0])) |
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so this configuration is allowed at Vivado level and not valid? should we be asking the IP owner to update it such away that vivado GUI to not to allow this configuration?
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Yes ideally, it should be blocked at hardware IP design level, and lopper layer should not decide on this. But not sure who to reach out for implementing this configuration logic in hardware level.
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Propagate the xlnx,use-embedded CPU property (set by SDTGen for MicroBlaze-V cores with C_USE_EMBEDDED) through to the generated build flags:
Signed-off-by: sushilkumar.singh@amd.com