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Modularize the bus. Add example of usage. #38
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ea4d64a
Modularize the bus. Add example of usage.
jimktrains e6ab55e
fixing a bug in the jump handler
jimktrains a45b655
Fixing bugs introduced while refactoring
jimktrains 94ad2f8
Fixing bug with jump handler. This needs to be broken out.
jimktrains 0980ab0
Remove jump handler code. Ensure tests work.
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,104 +1,114 @@ | ||
| //! The bus module contains the system bus which can access the memroy or memory-mapped peripheral | ||
| //! devices. | ||
|
|
||
| use crate::devices::{clint::Clint, plic::Plic, uart::Uart, virtio_blk::Virtio}; | ||
| use crate::dram::{Dram, DRAM_SIZE}; | ||
| use crate::devices::clint::Clint; | ||
| use crate::devices::plic::Plic; | ||
| use crate::exception::Exception; | ||
| use crate::rom::Rom; | ||
| use std::sync::{Arc, Mutex}; | ||
|
|
||
| // QEMU virt machine: | ||
| // https://github.com/qemu/qemu/blob/master/hw/riscv/virt.c#L46-L63 | ||
|
|
||
| /// The address which the mask ROM starts. | ||
| pub const MROM_BASE: u64 = 0x1000; | ||
| /// The address which the mask ROM ends. | ||
| const MROM_END: u64 = MROM_BASE + 0xf000; | ||
| use std::ops::RangeInclusive; | ||
|
|
||
| /// The address which the core-local interruptor (CLINT) starts. It contains the timer and generates | ||
| /// per-hart software interrupts and timer interrupts. | ||
| pub const CLINT_BASE: u64 = 0x200_0000; | ||
| /// The address which the core-local interruptor (CLINT) ends. | ||
| const CLINT_END: u64 = CLINT_BASE + 0x10000; | ||
|
|
||
| /// The address which the platform-level interrupt controller (PLIC) starts. The PLIC connects all | ||
| /// external interrupts in the system to all hart contexts in the system, via the external interrupt | ||
| /// source in each hart. | ||
| pub const PLIC_BASE: u64 = 0xc00_0000; | ||
| /// The address which the platform-level interrupt controller (PLIC) ends. | ||
| const PLIC_END: u64 = PLIC_BASE + 0x208000; | ||
|
|
||
| /// The address which UART starts. QEMU puts UART registers here in physical memory. | ||
| pub const UART_BASE: u64 = 0x1000_0000; | ||
| /// The size of UART. | ||
| pub const UART_SIZE: u64 = 0x100; | ||
| /// The address which UART ends. | ||
| const UART_END: u64 = UART_BASE + 0x100; | ||
|
|
||
| /// The address which virtio starts. | ||
| pub const VIRTIO_BASE: u64 = 0x1000_1000; | ||
| /// The address which virtio ends. | ||
| const VIRTIO_END: u64 = VIRTIO_BASE + 0x1000; | ||
|
|
||
| /// The address which DRAM starts. | ||
| pub const DRAM_BASE: u64 = 0x8000_0000; | ||
| /// The address which DRAM ends. | ||
| const DRAM_END: u64 = DRAM_BASE + DRAM_SIZE; | ||
|
|
||
| pub trait Device { | ||
| /// Load `size`-bit data from the memory. | ||
| fn read(&mut self, addr: u64, size: u8) -> Result<u64, Exception>; | ||
| /// Store `size`-bit data to the memory. | ||
| fn write(&mut self, addr: u64, value: u64, size: u8) -> Result<(), Exception>; | ||
|
|
||
| fn size(&self) -> u64; | ||
|
|
||
| fn is_interrupting(&mut self) -> bool; | ||
|
|
||
| fn irq(&self) -> Option<u64>; | ||
|
|
||
| fn reset(&mut self); | ||
| } | ||
|
|
||
| /// The system bus. | ||
| pub struct Bus { | ||
| devices: Vec<(RangeInclusive<u64>, Arc<Mutex<dyn Device>>)>, | ||
|
|
||
| pub clint: Clint, | ||
| pub plic: Plic, | ||
| pub uart: Uart, | ||
| pub virtio: Virtio, | ||
| dram: Dram, | ||
| pub rom: Rom, | ||
| clint_addr_range: RangeInclusive<u64>, | ||
| plic_addr_range: RangeInclusive<u64>, | ||
| } | ||
|
|
||
| impl Bus { | ||
| /// Create a new bus object. | ||
| pub fn new() -> Bus { | ||
| let clint = Clint::new(); | ||
| let plic = Plic::new(); | ||
| Self { | ||
| clint: Clint::new(), | ||
| plic: Plic::new(), | ||
| uart: Uart::new(), | ||
| virtio: Virtio::new(), | ||
| dram: Dram::new(), | ||
| rom: Rom::new(), | ||
| devices: vec![], | ||
| clint_addr_range: (CLINT_BASE..=(CLINT_BASE + clint.size())), | ||
| plic_addr_range: (PLIC_BASE..=(PLIC_BASE + plic.size())), | ||
| clint: clint, | ||
| plic: plic, | ||
| } | ||
| } | ||
|
|
||
| /// Set the binary data to the memory. | ||
| pub fn initialize_dram(&mut self, data: Vec<u8>) { | ||
| self.dram.initialize(data); | ||
| pub fn is_interrupting(&mut self) -> bool { | ||
| let mut saw_interrupt = false; | ||
| for (_, device) in self.devices.iter_mut() { | ||
| let mut device = device.lock().unwrap(); | ||
| if device.is_interrupting() { | ||
| if let Some(irq) = device.irq() { | ||
| self.plic.update_pending(irq); | ||
| saw_interrupt = true; | ||
| } | ||
| } | ||
| } | ||
| saw_interrupt | ||
| } | ||
|
|
||
| /// Set the binary data to the virtIO disk. | ||
| pub fn initialize_disk(&mut self, data: Vec<u8>) { | ||
| self.virtio.initialize(data); | ||
| pub fn mount(&mut self, memory_start: u64, device: Arc<Mutex<dyn Device>>) { | ||
| let size = device.lock().unwrap().size(); | ||
| let addr_range = memory_start..=(memory_start + size); | ||
| self.devices.push((addr_range, device)); | ||
| } | ||
|
|
||
| /// Load a `size`-bit data from the device that connects to the system bus. | ||
| pub fn read(&mut self, addr: u64, size: u8) -> Result<u64, Exception> { | ||
| match addr { | ||
| MROM_BASE..=MROM_END => self.rom.read(addr, size), | ||
| CLINT_BASE..=CLINT_END => self.clint.read(addr, size), | ||
| PLIC_BASE..=PLIC_END => self.plic.read(addr, size), | ||
| UART_BASE..=UART_END => self.uart.read(addr, size), | ||
| VIRTIO_BASE..=VIRTIO_END => self.virtio.read(addr, size), | ||
| DRAM_BASE..=DRAM_END => self.dram.read(addr, size), | ||
| _ => Err(Exception::LoadAccessFault), | ||
| if self.clint_addr_range.contains(&addr) { | ||
| self.clint.read(addr - self.clint_addr_range.start(), size) | ||
| } else if self.plic_addr_range.contains(&addr) { | ||
| self.plic.read(addr - self.plic_addr_range.start(), size) | ||
| } else { | ||
| for (addr_range, device) in self.devices.iter_mut() { | ||
| if addr_range.contains(&addr) { | ||
| let mut device = device.lock().unwrap(); | ||
| return device.read(addr - addr_range.start(), size); | ||
| } | ||
| } | ||
| Err(Exception::LoadAccessFault) | ||
| } | ||
| } | ||
|
|
||
| /// Store a `size`-bit data to the device that connects to the system bus. | ||
| pub fn write(&mut self, addr: u64, value: u64, size: u8) -> Result<(), Exception> { | ||
| match addr { | ||
| CLINT_BASE..=CLINT_END => self.clint.write(addr, value, size), | ||
| PLIC_BASE..=PLIC_END => self.plic.write(addr, value, size), | ||
| UART_BASE..=UART_END => self.uart.write(addr, value as u8, size), | ||
| VIRTIO_BASE..=VIRTIO_END => self.virtio.write(addr, value as u32, size), | ||
| DRAM_BASE..=DRAM_END => self.dram.write(addr, value, size), | ||
| _ => Err(Exception::StoreAMOAccessFault), | ||
| if self.clint_addr_range.contains(&addr) { | ||
| self.clint | ||
| .write(addr - self.clint_addr_range.start(), value, size) | ||
| } else if self.plic_addr_range.contains(&addr) { | ||
| self.plic | ||
| .write(addr - self.plic_addr_range.start(), value, size) | ||
| } else { | ||
| for (addr_range, device) in self.devices.iter_mut() { | ||
| if addr_range.contains(&addr) { | ||
| let mut device = device.lock().unwrap(); | ||
| return device.write(addr - addr_range.start(), value, size); | ||
| } | ||
| } | ||
| Err(Exception::StoreAMOAccessFault) | ||
| } | ||
| } | ||
| } |
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Since the stack is based on where the system wants it, we don't know where we would have to initialize this, and it needs to be done elsewhere. When the DRAM is initialized on the bus, I do set the stack pointer to the end of ram.