[AIEX][OLP] resolve WAR dependencies - #1190
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…nUtils Pull the free-register search out of AIEWawRegRewriter into a shared Utils/AIERegAllocationUtils helper so a second reallocation pass can reuse it. Switch the WAW round-robin from std::list to SmallVector along the way. No functional change to WAW register rewriting.
Add a common physical-copy materialization helper on AIEBaseInstrInfo and implement it for AIE1/AIE2/AIE2P/AIE2PS so downstream passes can emit register copies without duplicating per-subtarget copy-splitting logic.
Introduce the AIEEpilogueRegRewriter pass as a registered no-op and wire it into the AIE2/AIE2P/AIE2PS optimized register-allocation pipelines behind EnableEpilogueRegRewrite (default on), plus a second greedy pass. The pass declares its analysis dependencies but does not yet rename anything. Also register the --aie-epilogue-reg-rewrite-copy-budget and --aie-olp-war-rename options and add the epilogue-reg-rewrite MIR test with CHECK lines capturing the pre-rewrite (before) baseline, so the follow-up that implements the renaming shows a clean before/after diff. Pipeline listing tests updated to include the pass.
Fill in the epilogue register rewriter: collect def-driven WAR candidates (registers read before they are rewritten in a block carrying the aie-olp-war-rename hint), find a free non-overlapping physical register via the shared search helper, and materialize a repair copy that restores the old name at the block end. The copy budget bounds how many renames are taken. Both VLDA- and COPY-defined accumulators are handled. Updates the epilogue-reg-rewrite MIR test CHECK lines to the post-rewrite (after) state, so the diff against the baseline shows exactly what the pass changes.
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| ; CHECK-NEXT: vlda bmlh0, [p4], #64; vst.srs.4x dm2, s0, srssign0, [p2], m5; jnzd r1, r1, p5; vshuffle x10, x10, x0, r20 | ||
| ; CHECK-NEXT: vlda bmhl0, [p4], #64; vst.srs.4x dm1, s0, srssign0, [p2], #64; vshuffle x1, x1, x0, r26 // Delay Slot 5 | ||
| ; CHECK-NEXT: vlda bmhh0, [p4], #64; vst.2d.srs.4x dm0, s0, srssign0, [p2], d2; movx srssign0, #0; vmov cml3, cml4 // Delay Slot 4 | ||
| ; CHECK-NEXT: vmov cmh3, cmh4 // Delay Slot 3 |
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Nice 3 cycle reduction.
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To schedule epilogues of Steadystates in the OLP we can remove WriteAfterRead (WAR) dependencies by splitting VRegs and assigning separate PhysRegs to them.
This option has to be enabled by loop hint.