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chvamshi-xilinx merged 5 commits into from
Jul 7, 2026
Merged

opcode and patching schema for pl ip to transfer wts #315

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1e45efe
opcode and patching schema for pl ip to transfer wts
HimanshuChoudhary-Xilinx Jul 1, 2026
bbf21e3
droped num_entries
HimanshuChoudhary-Xilinx Jul 6, 2026
2f9928f
Update ctrlcode.txt with new control codes
chvamshi-xilinx Jul 6, 2026
f1c75c5
fix patching schema
HimanshuChoudhary-Xilinx Jul 6, 2026
1034c32
fix
HimanshuChoudhary-Xilinx Jul 6, 2026
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91 changes: 91 additions & 0 deletions specification/aie2ps/isa-spec.html
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Original file line number Diff line number Diff line change
Expand Up @@ -135,6 +135,8 @@ <h1>AIE Control-Code ISA</h1>
<li><a href="#sleep-0x1d">SLEEP (0x1d)</a></li>
<li><a href="#save_register-0x1e">SAVE_REGISTER (0x1e)</a></li>
<li><a href="#rel_acq_sync-0x21">REL_ACQ_SYNC (0x21)</a></li>
<li><a href="#uc_dma_mask_poll_ext-0x22">UC_DMA_MASK_POLL_EXT (0x22)</a></li>
<li><a href="#apply_offset_pl-0x23">APPLY_OFFSET_PL (0x23)</a></li>
</ul>
</li>
<li><a href="#directives">Directives</a><ul>
Expand Down Expand Up @@ -1647,6 +1649,95 @@ <h2 id="rel_acq_sync-0x21">REL_ACQ_SYNC (0x21)</h2>

REL_ACQ_SYNC 0x0205720c, 0x02057004 ; barrierId: 0, lockId: 28, release_aquire relVal: 1 acqVal: 3

</code></pre>
<h2 id="uc_dma_mask_poll_ext-0x22">UC_DMA_MASK_POLL_EXT (0x22)</h2>
<p>Polls an external (NoC-mapped) register until (read &amp; mask) == value.</p>
<table>
<thead>
<tr>
<th style="text-align: center;">0x22</th>
<th>-</th>
<th>-</th>
<th>addr_hi</th>
<th>addr_lo</th>
<th>mask</th>
<th>value</th>
<th style="text-align: right;">instruction size</th>
</tr>
</thead>
<tbody>
<tr>
<td style="text-align: center;">opcode (8b)</td>
<td>pad (8b)</td>
<td>pad (16b)</td>
<td>const (32b)</td>
<td>const (32b)</td>
<td>const (32b)</td>
<td>const (32b)</td>
<td style="text-align: right;">20B</td>
</tr>
</tbody>
</table>
<p>Reads a 32-bit value from the external address formed by (addr_hi &lt;&lt; 32 | addr_lo) via
a uC-DMA MM2DM transfer and busy-waits until (read_value &amp; mask) == value.
Analogous to MASK_POLL_32 but for addresses outside the AIE array register space,
reachable via NMU -&gt; NoC (e.g. PL IP AXI-Lite registers).
Used to poll ap_done (bit[1]) of a wts_pl_ctrl AP_CTRL register after triggering ap_start.
Example:</p>
<pre><code>; Poll ap_done (bit[1]) on wts_pl_ctrl instance 0 (base 0x80000030000):
UC_DMA_MASK_POLL_EXT 0x00000800, 0x00030000, 0x00000002, 0x00000002
</code></pre>
<h2 id="apply_offset_pl-0x23">APPLY_OFFSET_PL (0x23)</h2>
<p>Patches the physical DDR address (words 8+9) of one or more wts_params blocks for PL IP start_address.</p>
<table>
<thead>
<tr>
<th style="text-align: center;">0x23</th>
<th>-</th>
<th>table_ptr</th>
<th>buffer_id</th>
<th>-</th>
<th style="text-align: right;">instruction size</th>
</tr>
</thead>
<tbody>
<tr>
<td style="text-align: center;">opcode (8b)</td>
<td>pad (8b)</td>
<td>const (16b)</td>
<td>const (16b)</td>
<td>pad (16b)</td>
<td style="text-align: right;">8B</td>
</tr>
</tbody>
</table>
<p>Patches wts_params blocks (each 10 words / 40 bytes) starting at <code>table_ptr</code>.
XRT resolves <code>buffer_id</code> to a 64-bit physical address at BO bind time and
writes word[8] &lt;- phys_addr[31:0] and word[9] &lt;- phys_addr[63:32] in each block.
Example:</p>
<pre><code>START_JOB 1
APPLY_OFFSET_PL @wts_params, WTS_BUFFER_ID
UC_DMA_WRITE_DES_SYNC @wts_pl_bd_chain
UC_DMA_MASK_POLL_EXT 0x00000800, 0x00030000, 0x00000002, 0x00000002
END_JOB
.align 16
wts_pl_bd_chain:
UC_DMA_BD 0x800, 0x00030010, @wts_params, 10, 1, 1
UC_DMA_BD 0x800, 0x00030000, @val_ap_start, 1, 1, 0
.align 4
wts_params:
.long 0x00000000 ; word 0 offset
.long 0x00000000 ; word 1 (reserved)
.long 0x00000004 ; word 2 length
.long 0x00000000 ; word 3 (reserved)
.long 0x00000000 ; word 4 stride
.long 0x00000000 ; word 5 (reserved)
.long 0x00000001 ; word 6 iterations
.long 0x00000000 ; word 7 (reserved)
.long 0x00000000 ; word 8 start_addr[31:0] &lt;- APPLY_OFFSET_PL
.long 0x00000000 ; word 9 start_addr[63:32] &lt;- APPLY_OFFSET_PL
val_ap_start:
.long 0x00000001
</code></pre>
<h1 id="directives">Directives</h1>
<p>The directive syntax is same as that used by GNU assembler <a href="https://sourceware.org/binutils/docs/as/Pseudo-Ops.html">https://sourceware.org/binutils/docs/as/Pseudo-Ops.html</a>,
Expand Down
59 changes: 59 additions & 0 deletions specification/aie2ps/isa-spec.md
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Expand Up @@ -862,6 +862,65 @@ REL_ACQ_SYNC 0x0205720c, 0x02057004 ; barrierId: 0, lockId: 28, release_aquire r
```


## UC_DMA_MASK_POLL_EXT (0x22)

Polls an external (NoC-mapped) register until (read & mask) == value.

| 0x22 | - | - | addr_hi | addr_lo | mask | value | instruction size |
| :-: | - | - | - | - | - | - | -: |
| opcode (8b) | pad (8b) | pad (16b) | const (32b) | const (32b) | const (32b) | const (32b) | 20B |

Reads a 32-bit value from the external address formed by (addr_hi << 32 | addr_lo) via
a uC-DMA MM2DM transfer and busy-waits until (read_value & mask) == value.
Analogous to MASK_POLL_32 but for addresses outside the AIE array register space,
reachable via NMU -> NoC (e.g. PL IP AXI-Lite registers).
Used to poll ap_done (bit[1]) of a wts_pl_ctrl AP_CTRL register after triggering ap_start.
Example:
```
; Poll ap_done (bit[1]) on wts_pl_ctrl instance 0 (base 0x80000030000):
UC_DMA_MASK_POLL_EXT 0x00000800, 0x00030000, 0x00000002, 0x00000002
```


## APPLY_OFFSET_PL (0x23)

Patches the physical DDR address (words 8+9) of one or more wts_params blocks for PL IP start_address.

| 0x23 | - | table_ptr | buffer_id | - | instruction size |
| :-: | - | - | - | - | -: |
| opcode (8b) | pad (8b) | const (16b) | const (16b) | pad (16b) | 8B |

Patches wts_params blocks (each 10 words / 40 bytes) starting at `table_ptr`.
XRT resolves `buffer_id` to a 64-bit physical address at BO bind time and
writes word[8] <- phys_addr[31:0] and word[9] <- phys_addr[63:32] in each block.
Example:
```
START_JOB 1
APPLY_OFFSET_PL @wts_params, WTS_BUFFER_ID
UC_DMA_WRITE_DES_SYNC @wts_pl_bd_chain
UC_DMA_MASK_POLL_EXT 0x00000800, 0x00030000, 0x00000002, 0x00000002
END_JOB
.align 16
wts_pl_bd_chain:
UC_DMA_BD 0x800, 0x00030010, @wts_params, 10, 1, 1
UC_DMA_BD 0x800, 0x00030000, @val_ap_start, 1, 1, 0
.align 4
wts_params:
.long 0x00000000 ; word 0 offset
.long 0x00000000 ; word 1 (reserved)
.long 0x00000004 ; word 2 length
.long 0x00000000 ; word 3 (reserved)
.long 0x00000000 ; word 4 stride
.long 0x00000000 ; word 5 (reserved)
.long 0x00000001 ; word 6 iterations
.long 0x00000000 ; word 7 (reserved)
.long 0x00000000 ; word 8 start_addr[31:0] <- APPLY_OFFSET_PL
.long 0x00000000 ; word 9 start_addr[63:32] <- APPLY_OFFSET_PL
val_ap_start:
.long 0x00000001
```



# Directives
The directive syntax is same as that used by GNU assembler <https://sourceware.org/binutils/docs/as/Pseudo-Ops.html>,
Expand Down
75 changes: 75 additions & 0 deletions specification/aie2ps/isa-spec.yaml
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Expand Up @@ -815,6 +815,81 @@ operations:

```

- mnemonic: UC_DMA_MASK_POLL_EXT
opcode: 0x22
regular: True
arguments:
- type: pad
width: 16
- name: addr_hi
type: const
width: 32
- name: addr_lo
type: const
width: 32
- name: mask
type: const
width: 32
- name: value
type: const
width: 32
brief: Polls an external (NoC-mapped) register until (read & mask) == value.
description: |
Reads a 32-bit value from the external address formed by (addr_hi << 32 | addr_lo) via
a uC-DMA MM2DM transfer and busy-waits until (read_value & mask) == value.
Analogous to MASK_POLL_32 but for addresses outside the AIE array register space,
reachable via NMU -> NoC (e.g. PL IP AXI-Lite registers).
Used to poll ap_done (bit[1]) of a wts_pl_ctrl AP_CTRL register after triggering ap_start.
Example:
```
; Poll ap_done (bit[1]) on wts_pl_ctrl instance 0 (base 0x80000030000):
UC_DMA_MASK_POLL_EXT 0x00000800, 0x00030000, 0x00000002, 0x00000002
```

- mnemonic: APPLY_OFFSET_PL
opcode: 0x23
regular: True
arguments:
- name: table_ptr
type: const
width: 16
- name: buffer_id
type: const
width: 16
- type: pad
width: 16
brief: Patches the physical DDR address (words 8+9) of one or more wts_params blocks for PL IP start_address.
description: |
Patches wts_params blocks (each 10 words / 40 bytes) starting at `table_ptr`.
XRT resolves `buffer_id` to a 64-bit physical address at BO bind time and
writes word[8] <- phys_addr[31:0] and word[9] <- phys_addr[63:32] in each block.
Example:
```
START_JOB 1
APPLY_OFFSET_PL @wts_params, WTS_BUFFER_ID
UC_DMA_WRITE_DES_SYNC @wts_pl_bd_chain
UC_DMA_MASK_POLL_EXT 0x00000800, 0x00030000, 0x00000002, 0x00000002
END_JOB
.align 16
wts_pl_bd_chain:
UC_DMA_BD 0x800, 0x00030010, @wts_params, 10, 1, 1
UC_DMA_BD 0x800, 0x00030000, @val_ap_start, 1, 1, 0
.align 4
wts_params:
.long 0x00000000 ; word 0 offset
.long 0x00000000 ; word 1 (reserved)
.long 0x00000004 ; word 2 length
.long 0x00000000 ; word 3 (reserved)
.long 0x00000000 ; word 4 stride
.long 0x00000000 ; word 5 (reserved)
.long 0x00000001 ; word 6 iterations
.long 0x00000000 ; word 7 (reserved)
.long 0x00000000 ; word 8 start_addr[31:0] <- APPLY_OFFSET_PL
.long 0x00000000 ; word 9 start_addr[63:32] <- APPLY_OFFSET_PL
val_ap_start:
.long 0x00000001
```

directives:
- mnemonic: .long
brief: Specifies a 4 byte integer value.
Expand Down
18 changes: 18 additions & 0 deletions specification/aie2ps/isa.h
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Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,8 @@ constexpr int OPCODE_SAVE_TIMESTAMPS = 28;
constexpr int OPCODE_SLEEP = 29;
constexpr int OPCODE_SAVE_REGISTER = 30;
constexpr int OPCODE_REL_ACQ_SYNC = 33;
constexpr int OPCODE_UC_DMA_MASK_POLL_EXT = 34;
constexpr int OPCODE_APPLY_OFFSET_PL = 35;
constexpr int OPCODE_ALIGN = 0xA5;
constexpr int BIT_WIDTH_8 = 8;
constexpr int BIT_WIDTH_16 = 16;
Expand Down Expand Up @@ -196,6 +198,14 @@ class isa
opArg("_pad", opArg::optype::PAD, BIT_WIDTH_16), opArg("rel_address", opArg::optype::CONST, BIT_WIDTH_32), opArg("acq_address", opArg::optype::CONST, BIT_WIDTH_32),
});

(*m_isa)["uc_dma_mask_poll_ext"] = std::make_shared<isa_op>("uc_dma_mask_poll_ext", OPCODE_UC_DMA_MASK_POLL_EXT, std::vector<opArg>{
opArg("_pad", opArg::optype::PAD, BIT_WIDTH_16), opArg("addr_hi", opArg::optype::CONST, BIT_WIDTH_32), opArg("addr_lo", opArg::optype::CONST, BIT_WIDTH_32), opArg("mask", opArg::optype::CONST, BIT_WIDTH_32), opArg("value", opArg::optype::CONST, BIT_WIDTH_32),
});

(*m_isa)["apply_offset_pl"] = std::make_shared<isa_op>("apply_offset_pl", OPCODE_APPLY_OFFSET_PL, std::vector<opArg>{
opArg("table_ptr", opArg::optype::CONST, BIT_WIDTH_16), opArg("buffer_id", opArg::optype::CONST, BIT_WIDTH_16), opArg("_pad", opArg::optype::PAD, BIT_WIDTH_16),
});

(*m_isa)[".align"] = std::make_shared<isa_op>(".align", OPCODE_ALIGN, std::vector<opArg>{});
(*m_isa)[".long"] = std::make_shared<isa_op>(".long", 0/* dummy*/, std::vector<opArg>{});
(*m_isa)["uc_dma_bd"] = std::make_shared<isa_op>("uc_dma_bd", 0/* dummy*/, std::vector<opArg>{});
Expand Down Expand Up @@ -349,6 +359,14 @@ class isa_disassembler
opArg("_pad", opArg::optype::PAD, BIT_WIDTH_16), opArg("rel_address", opArg::optype::CONST, BIT_WIDTH_32), opArg("acq_address", opArg::optype::CONST, BIT_WIDTH_32),
}));

m_isa_disasm.emplace(OPCODE_UC_DMA_MASK_POLL_EXT, isa_op_disasm("uc_dma_mask_poll_ext", OPCODE_UC_DMA_MASK_POLL_EXT, std::vector<opArg>{
opArg("_pad", opArg::optype::PAD, BIT_WIDTH_16), opArg("addr_hi", opArg::optype::CONST, BIT_WIDTH_32), opArg("addr_lo", opArg::optype::CONST, BIT_WIDTH_32), opArg("mask", opArg::optype::CONST, BIT_WIDTH_32), opArg("value", opArg::optype::CONST, BIT_WIDTH_32),
}));

m_isa_disasm.emplace(OPCODE_APPLY_OFFSET_PL, isa_op_disasm("apply_offset_pl", OPCODE_APPLY_OFFSET_PL, std::vector<opArg>{
opArg("table_ptr", opArg::optype::CONST, BIT_WIDTH_16), opArg("buffer_id", opArg::optype::CONST, BIT_WIDTH_16), opArg("_pad", opArg::optype::PAD, BIT_WIDTH_16),
}));

m_isa_disasm.emplace(OPCODE_EOF, isa_op_disasm("eof", OPCODE_EOF, std::vector<opArg>{
opArg("_pad", opArg::optype::PAD, BIT_WIDTH_16),
}));
Expand Down
26 changes: 25 additions & 1 deletion specification/aie2ps/isa_defines.h
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Expand Up @@ -45,6 +45,8 @@ static unsigned int control_op_save_timestamps(const uint8_t *_pc, uint32_t unq_
static unsigned int control_op_sleep(const uint8_t *_pc, uint32_t target);
static unsigned int control_op_save_register(const uint8_t *_pc, uint32_t address, uint32_t unq_id);
static unsigned int control_op_rel_acq_sync(const uint8_t *_pc, uint32_t rel_address, uint32_t acq_address);
static unsigned int control_op_uc_dma_mask_poll_ext(const uint8_t *_pc, uint32_t addr_hi, uint32_t addr_lo, uint32_t mask, uint32_t value);
static unsigned int control_op_apply_offset_pl(const uint8_t *_pc, uint16_t table_ptr, uint16_t buffer_id);


// Dispatchers
Expand Down Expand Up @@ -344,6 +346,26 @@ FORCE_INLINE_FOR_RELEASE_ONLY static inline unsigned int control_dispatch_rel_ac
);
}

FORCE_INLINE_FOR_RELEASE_ONLY static inline unsigned int control_dispatch_uc_dma_mask_poll_ext(const uint8_t *pc)
{
return control_op_uc_dma_mask_poll_ext(

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warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]

  return control_op_uc_dma_mask_poll_ext(
         ^

pc,
/* addr_hi (const) */ *(uint32_t *)(&pc[4]),

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warning: do not use C-style cast to convert between unrelated types [cppcoreguidelines-pro-type-cstyle-cast]

    /* addr_hi (const) */ *(uint32_t *)(&pc[4]),
                           ^

/* addr_lo (const) */ *(uint32_t *)(&pc[8]),

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warning: 8 is a magic number; consider replacing it with a named constant [cppcoreguidelines-avoid-magic-numbers]

    /* addr_lo (const) */ *(uint32_t *)(&pc[8]),
                                            ^

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warning: do not use C-style cast to convert between unrelated types [cppcoreguidelines-pro-type-cstyle-cast]

    /* addr_lo (const) */ *(uint32_t *)(&pc[8]),
                           ^

/* mask (const) */ *(uint32_t *)(&pc[12]),

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warning: 12 is a magic number; consider replacing it with a named constant [cppcoreguidelines-avoid-magic-numbers]

    /* mask (const) */ *(uint32_t *)(&pc[12]),
                                         ^

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warning: do not use C-style cast to convert between unrelated types [cppcoreguidelines-pro-type-cstyle-cast]

    /* mask (const) */ *(uint32_t *)(&pc[12]),
                        ^

/* value (const) */ *(uint32_t *)(&pc[16])

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warning: 16 is a magic number; consider replacing it with a named constant [cppcoreguidelines-avoid-magic-numbers]

    /* value (const) */ *(uint32_t *)(&pc[16])
                                          ^

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warning: do not use C-style cast to convert between unrelated types [cppcoreguidelines-pro-type-cstyle-cast]

    /* value (const) */ *(uint32_t *)(&pc[16])
                         ^

);
}

FORCE_INLINE_FOR_RELEASE_ONLY static inline unsigned int control_dispatch_apply_offset_pl(const uint8_t *pc)
{
return control_op_apply_offset_pl(

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warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]

  return control_op_apply_offset_pl(
         ^

pc,
/* table_ptr (const) */ *(uint16_t *)(&pc[2]),

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warning: do not use C-style cast to convert between unrelated types [cppcoreguidelines-pro-type-cstyle-cast]

    /* table_ptr (const) */ *(uint16_t *)(&pc[2]),
                             ^

/* buffer_id (const) */ *(uint16_t *)(&pc[4])

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warning: do not use C-style cast to convert between unrelated types [cppcoreguidelines-pro-type-cstyle-cast]

    /* buffer_id (const) */ *(uint16_t *)(&pc[4])
                             ^

);
}


// Case statements for regular operations

Expand Down Expand Up @@ -376,7 +398,9 @@ FORCE_INLINE_FOR_RELEASE_ONLY static inline unsigned int control_dispatch_rel_ac
case ISA_OPCODE_SAVE_TIMESTAMPS: pc += control_dispatch_save_timestamps(pc); break; \
case ISA_OPCODE_SLEEP: pc += control_dispatch_sleep(pc); break; \
case ISA_OPCODE_SAVE_REGISTER: pc += control_dispatch_save_register(pc); break; \
case ISA_OPCODE_REL_ACQ_SYNC: pc += control_dispatch_rel_acq_sync(pc); break;
case ISA_OPCODE_REL_ACQ_SYNC: pc += control_dispatch_rel_acq_sync(pc); break; \
case ISA_OPCODE_UC_DMA_MASK_POLL_EXT: pc += control_dispatch_uc_dma_mask_poll_ext(pc); break; \
case ISA_OPCODE_APPLY_OFFSET_PL: pc += control_dispatch_apply_offset_pl(pc); break;


#endif
4 changes: 4 additions & 0 deletions specification/aie2ps/isa_stubs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -59,6 +59,8 @@
#define ISA_OPCODE_SLEEP 0x1d
#define ISA_OPCODE_SAVE_REGISTER 0x1e
#define ISA_OPCODE_REL_ACQ_SYNC 0x21
#define ISA_OPCODE_UC_DMA_MASK_POLL_EXT 0x22

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warning: macro 'ISA_OPCODE_UC_DMA_MASK_POLL_EXT' used to declare a constant; consider using a 'constexpr' constant [cppcoreguidelines-macro-usage]

#define ISA_OPCODE_UC_DMA_MASK_POLL_EXT 0x22
        ^

#define ISA_OPCODE_APPLY_OFFSET_PL 0x23

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warning: macro 'ISA_OPCODE_APPLY_OFFSET_PL' used to declare a constant; consider using a 'constexpr' constant [cppcoreguidelines-macro-usage]

#define ISA_OPCODE_APPLY_OFFSET_PL 0x23
        ^



// Operation sizes
Expand Down Expand Up @@ -97,5 +99,7 @@
#define ISA_OPSIZE_SLEEP 0x08
#define ISA_OPSIZE_SAVE_REGISTER 0x0c
#define ISA_OPSIZE_REL_ACQ_SYNC 0x0c
#define ISA_OPSIZE_UC_DMA_MASK_POLL_EXT 0x14

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warning: macro 'ISA_OPSIZE_UC_DMA_MASK_POLL_EXT' used to declare a constant; consider using a 'constexpr' constant [cppcoreguidelines-macro-usage]

#define ISA_OPSIZE_UC_DMA_MASK_POLL_EXT 0x14
        ^

#define ISA_OPSIZE_APPLY_OFFSET_PL 0x08

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warning: macro 'ISA_OPSIZE_APPLY_OFFSET_PL' used to declare a constant; consider using a 'constexpr' constant [cppcoreguidelines-macro-usage]

#define ISA_OPSIZE_APPLY_OFFSET_PL 0x08
        ^


#endif
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