support pl ip patching schema pl_ddr_64 #9890
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Signed-off-by: Himanshu Choudhary <Himanshu.Choudhary@amd.com>
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clang-tidy review says "All clean, LGTM! 👍" |
stsoe
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Jul 1, 2026
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Lots of a magic numbers and accessing bd_data_ptr[] without a clue as to whether this is safe or not. Anyways, your change builds on top of existing and LGTM in the context of existing code.
I think all this patching code should be refactored and moved to AIEBU, but that's separate from this PR.
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Problem solved by the commit
support pl ip patching schema "pl_ddr_64"
https://amd.atlassian.net/wiki/spaces/AIE/pages/1744115100/Weight+Prefetch+via+PL+IP+and+PLIO+Feature+Specification
XRT patches words 8+9 of wts_params with the physical weight buffer address via APPLY_OFFSET_PL at BO bind time.
Bug / issue (if any) fixed, which PR introduced the bug, how it was discovered
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