Step 1. Chip Specification Step 2. Design Entry / Functional Verification Step 3. RTL block synthesis / RTL Function Step 4. Chip Partitioning Step 5. Design for Test (DFT) Insertion Step 6. Floor Planning and power planning Step 7. Placement Step 8. Clock tree synthesis Step 9. Routing Step 10. Final Verification EMIR PV STA Step 11. GDS II