For the VLSI module, I worked on two separate assignments: a VLSI lab report and an individual VLSI project.

VLSI Lab Report: In this lab, I implemented a range of fundamental VLSI components using VHDL, including multiplexers, demultiplexers, full adders, subtractors, SR and JK flip-flops, and a 4-bit binary to Gray code converter. I developed the VHDL codes for these components and verified their functionality through testbenches and waveform simulations. Each component was tested for accuracy against its corresponding truth table. The project allowed me to deepen my understanding of digital logic design, VHDL coding, and hardware simulation using Quartus software.

VLSI Individual Assignment: For the individual project, I designed a highly efficient VHDL-based digital counter optimized for VLSI systems. This counter counts from 0 to 99 and interfaces with a seven-segment display for user-friendly output. The project focused on optimizing the design for power efficiency and modularity. I also developed submodules such as a binary-coded decimal (BCD) to seven-segment converter and a multiplexer for display control. Through simulation tests, I evaluated the counter’s performance, ensuring it met the timing and accuracy requirements of modern VLSI systems. These assignments provided valuable insights into the design and optimization of digital circuits for VLSI applications.