CLUE-SYCL

CLUE-SYCL is a SYCL-based implementation of the CLUE clustering algorithm, designed to run efficiently on heterogeneous hardware including FPGAs using Intel's oneAPI toolchain.

⚙️ Requirements

• Intel oneAPI DPC++/C++ Compiler (icpx)
• SYCL-compatible hardware or emulator (e.g. FPGA emulator)
• C++17 or later
• CMake (optional if you prefer build automation)

📁 Directory Structure

.
├── main.cpp
├── clueLib/
│   └── include/
│       └── ...
├── data/
│   └── input/
│       └── aniso_1000.csv

▶️ How to Run on FPGA Emulator

To compile and run CLUE-SYCL using the FPGA emulator:

1. Compile

icpx -fsycl main.cpp -I clueLib/include/ -o cluestering

2. Run

./cluestering -i data/input/aniso_1000.csv -d 7.0 -r 10.0 -o 2 -e 10 -v

🔍 Flags Explanation

Flag	Description
-i	Path to input CSV file
-d	dc — Distance cutoff for density calculation
-r	rhoc — Density threshold to qualify as a seed
-o	Outlier delta factor
-e	Number of repeated session(s)
-v	Verbose mode

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💡 Notes

• This setup targets the FPGA emulator, which simulates FPGA behavior for testing and development.
• You can set the target device using the SYCL device selector inside main.cpp, or via environment variables like:

  SYCL_DEVICE_FILTER=host ./cluestering

For targeting an actual FPGA card, further configuration and FPGA bitstream compilation would be required.

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📫 Contact

For questions or contributions, please open an issue or submit a pull request.