About Me

Electronics & Communication Engineering graduate focused on Design Verification and RTL Verification.

• Strong interest in SystemVerilog and UVM-based verification
• Hands-on experience developing constrained-random verification environments
• Working with functional coverage, assertions, scoreboards, monitors, drivers, sequences, and reference models
• Experience with AXI4-Lite, APB, memory-mapped interfaces, and SoC interconnects
• Developing and verifying RISC-V based SoC architectures
• Familiar with simulation, debugging, waveform analysis, and FPGA-based validation
• Interested in developing scalable and reusable verification environments for complex digital designs

Design Verification Skills

Verification Methodologies

Protocol & Interface Verification

RTL & Hardware Skills

• Verilog
• SystemVerilog
• RTL Design
• FSM Design
• Datapath and Control Logic
• Memory and Register Interfaces
• RISC-V RV32I
• SoC Architecture
• FPGA Implementation
• VGA / Video Display Logic
• CDC and Reset Synchronization

Verification Tools

Programming & Scripting

Featured Projects

RISC-V Video Display Processor SoC

RISC-V based SoC integrating a PicoRV32 processor, SoC interconnect, RAM, AXI4-Lite peripherals, VDP/VGA controller, sensor and telemetry peripherals.

Verification Focus:

• SystemVerilog/UVM verification environment
• AXI4-Lite transaction generation and monitoring
• Register and peripheral verification
• Scoreboard-based checking
• Functional coverage
• Assertions
• SoC-level integration verification
• Reset and CDC verification
• FPGA validation using Vivado

UVM-Based AXI4-Lite Verification Environment

Reusable SystemVerilog/UVM environment for verifying AXI4-Lite based RTL designs.

Key Components:

• UVM Test
• Environment
• Agent
• Sequencer
• Driver
• Monitor
• Sequence Items
• Scoreboard
• Reference Model
• Functional Coverage
• SystemVerilog Assertions

APB Verification Environment

SystemVerilog-based verification environment for APB interfaces.

• Constrained-random stimulus
• Generator and Driver
• Input and Output Monitors
• Reference Model
• Scoreboard
• Functional Coverage
• Reset and protocol checking

RISC-V / Edge AI Hardware

Exploring hardware-software co-design using RISC-V processors and lightweight AI acceleration for resource-constrained embedded systems.

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