Counter module Basics

ports/psoc-edge/Makefile

@@ -351,6 +351,7 @@ PSE_LIB_SRC_C += $(addprefix $(PSE_LIB_TOP_DIR)/, \
 	mtb-dsl-pse8xxgp/pdl/drivers/source/cy_systick_v2.c \
 	mtb-dsl-pse8xxgp/pdl/drivers/source/cy_tcpwm_counter.c \
 	mtb-dsl-pse8xxgp/pdl/drivers/source/cy_tcpwm_pwm.c \
+	mtb-dsl-pse8xxgp/pdl/drivers/source/cy_trigmux.c \
 	mtb-dsl-pse8xxgp/pdl/drivers/source/ppu_v1.c \
 	\
 	mtb-dsl-pse8xxgp/support/source/mtb_stdlib_stubs.c \
@@ -595,6 +596,7 @@ MOD_SRC_C += \
 	machine_scb.c \
 	tcpwm.c \
 	machine_timer.c \
+	machine_counter.c \
 	machine_bitstream.c \
 	modpsocedge.c \
 

ports/psoc-edge/boards/KIT_PSE84_AI/pins.csv

@@ -120,7 +120,7 @@ USER_LED1,P10_7
 ,-P11_0
 
 # PCKL level translator
-,-P11_1
+,P11_1
 
 # Bluetooth
 ,-P11_2

ports/psoc-edge/boards/make-pins.py

@@ -13,6 +13,7 @@
     "SPI": ["CLK", "MOSI", "MISO", "SELECT0", "SELECT1"],
     "PDM": ["CLK", "DATA"],
     "TCPWM": ["LINE"],
+    "PERI_TR_IO": ["INPUT", "OUTPUT"],
     # TODO: Other active functionalities that we need to figure out:
     # - TDM
     # - SMIF
@@ -55,6 +56,8 @@ def __init__(self, cpu_pin_name):
 
         # List of PinAF instances
         self._afs = []
+        # Optional Counter source routing metadata parsed from PERI0_TR_IO_INPUTx AFs.
+        self._counter_src = None
 
     def definition(self):
         return f"PIN({self._port}, {self._pin}, pin_{self.name()}_af)"
@@ -128,6 +131,23 @@ def add_af_tcpwm(self, af_idx, af_name, af):
         pin_af = PinAf(af_idx, af_fn, af_unit, af_signal, af_supported, af_name, af_ptr)
         self._afs.append(pin_af)
 
+    def add_af_peri_tr_io(self, af_idx, af_name, af):
+        # Map PERIx_TR_IO_INPUT/OUTPUTy to regular pin AF objects so consumers can
+        # validate capability through the shared AF metadata path.
+        # Matches patterns like: PERI0_TR_IO_INPUT4, PERI1_TR_IO_OUTPUT1
+        match = re.match(r"^(PERI\d+)_TR_IO_(INPUT|OUTPUT)(\d+)$", af)
+        if not match:
+            return
+
+        af_ptr = match.group(1)  # e.g., "PERI0", "PERI1"
+        af_signal = match.group(2)  # e.g., "INPUT", "OUTPUT"
+        af_unit = match.group(3)  # e.g., "4", "1"
+        af_fn = "PERI_TR_IO"
+        af_supported = af_fn in SUPPORTED_AF and af_signal in SUPPORTED_AF[af_fn]
+
+        pin_af = PinAf(af_idx, af_fn, af_unit, af_signal, af_supported, af_name, af_ptr)
+        self._afs.append(pin_af)
+
     def add_af(self, af_idx, af_name, af):
         # The AF index matches the column index for the ACTx functions 0-15
         # while for DSx functions the columns 16-19 are mapped to DS2-DS5 respectively.
@@ -172,6 +192,8 @@ def add_af(self, af_idx, af_name, af):
             self.add_af_pdm(af_idx, af_name, af)
         elif "TCPWM" in af:
             self.add_af_tcpwm(af_idx, af_name, af)
+        elif af.startswith("PERI"):
+            self.add_af_peri_tr_io(af_idx, af_name, af)
         else:
             # TODO: Extend the parsing to other peripherals.
             pass
@@ -222,6 +244,17 @@ def __init__(self):
         self._tcpwm_counter_max = 0  # highest counter number seen across all LINE AFs
         self._tcpwm_counters = []  # sorted unique TCPWM counter IDs seen in LINE AFs
 
+        # Trigger routing
+        self._unhidden_peri0_tr_io_input = []
+        self._unhidden_peri0_tr_io_output = []
+        self._peri0_tr_io_input_max_index = 0
+        self._peri0_tr_io_output_max_index = 0
+
+        self._unhidden_peri1_tr_io_input = []
+        self._unhidden_peri1_tr_io_output = []
+        self._peri1_tr_io_input_max_index = 0
+        self._peri1_tr_io_output_max_index = 0
+
     # Collect all unhidden ports from the available
     # pins.
     # This function can be only used after parse_board_csv()
@@ -280,13 +313,46 @@ def add_tcpwm(self):
         self._tcpwm_counters = sorted(seen_counters)
         self._pwm_pin_count = len(seen_counters)
 
+    def add_peri_tr_ios(self):
+        for pin in self.available_pins(exclude_hidden=True):
+            for af in pin._afs:
+                if af.af_fn == "PERI_TR_IO":
+                    if af.af_ptr == "PERI0":
+                        if af.af_signal == "INPUT":
+                            if af.af_unit not in self._unhidden_peri0_tr_io_input:
+                                self._unhidden_peri0_tr_io_input.append(af.af_unit)
+                                if int(af.af_unit) > self._peri0_tr_io_input_max_index:
+                                    self._peri0_tr_io_input_max_index = int(af.af_unit)
+                        elif af.af_signal == "OUTPUT":
+                            if af.af_unit not in self._unhidden_peri0_tr_io_output:
+                                self._unhidden_peri0_tr_io_output.append(af.af_unit)
+                                if int(af.af_unit) > self._peri0_tr_io_output_max_index:
+                                    self._peri0_tr_io_output_max_index = int(af.af_unit)
+                    elif af.af_ptr == "PERI1":
+                        if af.af_signal == "INPUT":
+                            if af.af_unit not in self._unhidden_peri1_tr_io_input:
+                                self._unhidden_peri1_tr_io_input.append(af.af_unit)
+                                if int(af.af_unit) > self._peri1_tr_io_input_max_index:
+                                    self._peri1_tr_io_input_max_index = int(af.af_unit)
+                        elif af.af_signal == "OUTPUT":
+                            if af.af_unit not in self._unhidden_peri1_tr_io_output:
+                                self._unhidden_peri1_tr_io_output.append(af.af_unit)
+                                if int(af.af_unit) > self._peri1_tr_io_output_max_index:
+                                    self._peri1_tr_io_output_max_index = int(af.af_unit)
+
+        self._unhidden_peri0_tr_io_input.sort(key=int)
+        self._unhidden_peri0_tr_io_output.sort(key=int)
+        self._unhidden_peri1_tr_io_input.sort(key=int)
+        self._unhidden_peri1_tr_io_output.sort(key=int)
+
     # Override the parse_board_csv to add
     # the unhidden ports after parsing the board CSV.
     def parse_board_csv(self, filename):
         super().parse_board_csv(filename)
         self.add_ports()
         self.add_scbs()
         self.add_tcpwm()
+        self.add_peri_tr_ios()
 
     # Override the default implementation just to change the default arguments
     # (extra header row, skip first column).
@@ -426,20 +492,72 @@ def print_tcpwm_hw_map(self, out_header):
 
         print(file=out_header)
         print(
-            "// Unified TCPWM hardware map: timer_id, counter_num, IRQ, PCLK destination.",
+            "// Unified TCPWM map: timer_id, counter_num, IRQ, PCLK destination, and one-to-one trigger input route.",
             file=out_header,
         )
-        print("// Each row: X(timer_id, tcpwm_counter_num, irq, pclk_dst)", file=out_header)
-        print("#define MICROPY_PY_MACHINE_TCPWM_HW_MAP(X) \\", file=out_header)
+        print(
+            "// Each row: X(timer_id, tcpwm_counter_num, irq, pclk_dst, trig_out_enum)",
+            file=out_header,
+        )
+        print("#define MICROPY_PY_MACHINE_TCPWM_MAP(X) \\", file=out_header)
         for i, (tid, counter, irq, pclk) in enumerate(hw_entries):
+            counter_token = counter[:-1] if counter.endswith("U") else counter
+            trig = f"PERI_0_TRIG_OUT_MUX_3_TCPWM0_ONE_CNT_TR_IN{counter_token}"
             suffix = " \\" if i < len(hw_entries) - 1 else ""
-            print(f"    X({tid:2d}, {counter}, {irq}, {pclk}){suffix}", file=out_header)
+            print(f"    X({tid:2d}, {counter}, {irq}, {pclk}, {trig}){suffix}", file=out_header)
+        print(file=out_header)
+
+    def print_peri_tr_io_defines(self, out_header):
+        print(file=out_header)
+        print(
+            f"#define MICROPY_PY_MACHINE_PERI0_TR_IO_INPUT_NUM_ENTRIES ({self._peri0_tr_io_input_max_index + 1})",
+            file=out_header,
+        )
+        print(
+            f"#define MICROPY_PY_MACHINE_PERI0_TR_IO_OUTPUT_NUM_ENTRIES ({self._peri0_tr_io_output_max_index + 1})",
+            file=out_header,
+        )
+        print(
+            f"#define MICROPY_PY_MACHINE_PERI1_TR_IO_INPUT_NUM_ENTRIES ({self._peri1_tr_io_input_max_index + 1})",
+            file=out_header,
+        )
+        print(
+            f"#define MICROPY_PY_MACHINE_PERI1_TR_IO_OUTPUT_NUM_ENTRIES ({self._peri1_tr_io_output_max_index + 1})",
+            file=out_header,
+        )
+        print(file=out_header)
+
+        print("#define MICROPY_PY_MACHINE_FOR_ALL_PERI0_TR_IO_INPUTS(DO) \\", file=out_header)
+        lines = [f"DO({in_idx})" for in_idx in self._unhidden_peri0_tr_io_input]
+        macro_body = " \\\n".join(lines)
+        print(macro_body, file=out_header)
+        print(file=out_header)
+
+        print("#define MICROPY_PY_MACHINE_FOR_ALL_PERI0_TR_IO_OUTPUTS(DO) \\", file=out_header)
+        lines = [f"DO({out_idx})" for out_idx in self._unhidden_peri0_tr_io_output]
+        macro_body = " \\\n".join(lines)
+        print(macro_body, file=out_header)
+        print(file=out_header)
+
+        print("#define MICROPY_PY_MACHINE_FOR_ALL_PERI1_TR_IO_INPUTS(DO) \\", file=out_header)
+        lines = [f"DO({in_idx})" for in_idx in self._unhidden_peri1_tr_io_input]
+        macro_body = " \\\n".join(lines)
+        print(macro_body, file=out_header)
+        print(file=out_header)
+
+        print("#define MICROPY_PY_MACHINE_FOR_ALL_PERI1_TR_IO_OUTPUTS(DO) \\", file=out_header)
+        lines = [f"DO({out_idx})" for out_idx in self._unhidden_peri1_tr_io_output]
+        macro_body = " \\\n".join(lines)
+        print(macro_body, file=out_header)
+        print(file=out_header)
+
         print(file=out_header)
 
     def print_af_header(self, out_af_header):
         self.print_scb_defines(out_af_header)
         self.print_tcpwm_defines(out_af_header)
         self.print_tcpwm_hw_map(out_af_header)
+        self.print_peri_tr_io_defines(out_af_header)
 
     # Add additional header file for AF defines and constants
     def extra_args(self, parser):

ports/psoc-edge/boards/pse8x_af.csv

@@ -57,7 +57,7 @@ Port10,P10_4,                         ,TCPWM0_LINE3                        ,TCPW
 Port10,P10_5,                         ,TCPWM0_LINE_COMPL3                  ,TCPWM0_LINE_COMPL259                  ,                  ,                ,                 ,SCB4_SPI_SELECT1 ,                 ,              ,             ,                   ,                   ,      ,             ,                          ,ETH_RX_CTL                            ,                ,                ,                 ,                        
 Port10,P10_6,                         ,TCPWM0_LINE4                        ,TCPWM0_LINE260                        ,                  ,                ,                 ,                 ,                 ,              ,             ,                   ,                   ,      ,             ,                          ,ETH_RXD0                              ,                ,                ,                 ,                        
 Port10,P10_7,                         ,TCPWM0_LINE_COMPL4                  ,TCPWM0_LINE_COMPL260                  ,                  ,                ,                 ,                 ,                 ,              ,             ,                   ,                   ,      ,             ,                          ,ETH_RXD1                              ,                ,                ,                 ,                        
-Port10,P11_0,                         ,TCPWM0_LINE5                        ,TCPWM0_LINE261                        ,                  ,                ,TDM_TDM_TX_SCK1  ,                 ,SCB6_I2C_SCL     ,              ,             ,                   ,                   ,      ,             ,                          ,ETH_RXD2                              ,                ,                ,                 ,                        
+Port10,P11_0,                         ,TCPWM0_LINE5                        ,TCPWM0_LINE261                        ,                  ,                ,TDM_TDM_TX_SCK1  ,                 ,SCB6_I2C_SCL     ,              ,             ,PERI0_TR_IO_INPUT0 ,PERI1_TR_IO_INPUT0 ,      ,             ,                          ,ETH_RXD2                              ,                ,                ,                 ,                        
 Port11,P11_1,                         ,TCPWM0_LINE_COMPL5                  ,TCPWM0_LINE_COMPL261                  ,                  ,                ,TDM_TDM_TX_FSYNC1,SCB6_SPI_MOSI    ,SCB6_I2C_SDA     ,SCB6_UART_TX  ,             ,PERI0_TR_IO_INPUT1 ,PERI1_TR_IO_INPUT1 ,      ,             ,                          ,ETH_RX_ER                             ,                ,                ,                 ,                        
 Port11,P11_2,                         ,TCPWM0_LINE6                        ,TCPWM0_LINE262                        ,                  ,                ,TDM_TDM_TX_SD1   ,SCB6_SPI_MISO    ,                 ,SCB6_UART_CTS ,             ,PERI0_TR_IO_INPUT2 ,PERI1_TR_IO_INPUT2 ,      ,             ,                          ,ETH_TXD0                              ,                ,                ,                 ,                        
 Port11,P11_3,                         ,TCPWM0_LINE_COMPL6                  ,TCPWM0_LINE_COMPL262                  ,                  ,                ,TDM_TDM_RX_MCK1  ,SCB6_SPI_SELECT0 ,                 ,SCB6_UART_RTS ,             ,PERI0_TR_IO_INPUT3 ,PERI1_TR_IO_INPUT3 ,      ,             ,                          ,ETH_TXD1                              ,                ,                ,                 ,