Initial cut at assembly hybrid / purecap unification. by qwattash · Pull Request #2606 · CTSRD-CHERI/cheribsd

qwattash · 2026-03-19T21:15:19Z

Move towards a unified assembly implementation that relies more heavily on compiler aliases and asm.h definitions to abstract away ISAv9-specific bits.

NOTE: requires compiler patches for

tail -> ctail [Cheri] [RISCV] Add alias for ctail instruction. llvm-project#813
lly and lgy for LLA_PTR and LA_PTR macros [CHERI-RISC-V] Add aliases for lly and lgy to llc and lgc. llvm-project#825

arichardson

Not managed to review everything in detail but this cleanup is great 👍

arichardson · 2026-03-20T12:39:36Z

-	sb	a4, 0(a1)		/* Store byte in dest */
-	addi	a1, a1, 1
-#endif
+	CLB	a4, 0(CAP(a0))		/* Load byte from src */


Can we use a plain lb here? Or does the compiler not accept that yet?

And the same for the other ones

Good point, will check.

So, it appears that aliasing lb to lb.cap is much more involved than anticipated. I think I will leave these definitions here.

Another ways of doing this would be to always mode switch and avoid using .cap instructions at all, but mode switching is more involved in ISAv9 than RVY and I'm worried about perturbation to the hybrid kernel syscall performance measurement.

Ah did not realize this needed to be hybrid compatible

Yeah, it is a bit annoying. At some point all this will become simpler, hopefully.

qwattash · 2026-03-20T14:41:34Z

I think for the purposes of this patch I 'd like to split the ASM unification refactor from the RVY-specific bits, which is admittedly not straightforward because we rely on some of the compiler aliases that make assumptions about the RVY instruction mnemonics.

In the RVY branch I have macros for all the capability instructions. One of the reasons for splitting the patches is that those macros should be relatively easy to revert and replace with compiler aliases once we have the frozen mnemonics.

Another thing I'd like to do here is to pretend that xxx.cap instructions don't exist and instead have a mode-switch, in the same way we would do on RVY. The problem with that is that on ISAv9 it adds a significant number of instructions in some cases (like fuword/fuecap).

brooksdavis

A couple comments before I get on a flight without wifi. I've made it up do "cheri riscv: Implement MODESW macros"

arichardson

This is great but we will need to use something like ADD_PTR for RVY compatibility

arichardson · 2026-05-21T14:26:19Z

+	csetaddr	CAP(t1), CAP(t1), t0
+	li	t0, 1
+	csetflags	CAP(t1), CAP(t1), t0
+	cspecialw	stcc, ct1


Could write to ct0 and then share the set_stvec between modes?

Trying to see if I can simplify this with some LLVM support, which we would need to replace cspecialrw with csrrrw

qwattash · 2026-06-25T07:42:11Z

The CSR story is still a bit sad here, as I can't easily use csrrw for xcheri without more compiler changes. This could be done, I think, in the same way Zcheri LLVM.

Rely on compiler menmonic aliases.

Unify copyin/out assembly for hybrid and purecap. Use the new machine/asm.h macros and rely on complier mnemonic aliases.

Unify support.S assembly for hybrid and purecap. Rely on asm.h macros and compiler mnemonic aliases. Partial patch, no csr registers yet.

Unify locore assembly for hybrid and purecap. This reduces the amount of ifdefs and relies on both asm.h definitions and compilier mnemonic aliases.

Unify context switch assembly hybrid and purecap. Rely on asm.h and compiler mnemonic aliases.

Unify hybrid and purecap assembly for exception handling. Rely on compiler mnemonic aliases and asm.h macros.

Unify bus space assembly for hybrid and purecap.

qwattash · 2026-07-28T20:03:32Z

+#define	ADD_CAP		yadd
+#define	ADDI_CAP	yaddi
+/* Note: xcheri */
+#define	MODESW_CAP(tmp, tmp1)					\


Maybe should distinguish between modesw that are always enabled and those that only exist when building for hybrid. Most of them really exist only for hybrid.

Update assembly in libc, libsys and rtld.

These are used to abstract away switching between hybrid and purecap encodings in the hybrid kernel. This patch facilitates migration to cheri-rv64y.

jrtc27 self-requested a review March 20, 2026 01:07

arichardson reviewed Mar 20, 2026

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qwattash force-pushed the cheri-rv64y-asm-refactor branch from fb8b664 to 09b28bc Compare March 23, 2026 15:32

qwattash force-pushed the cheri-rv64y-asm-refactor branch from 09b28bc to d1dd6e8 Compare April 1, 2026 12:19

qwattash marked this pull request as ready for review April 1, 2026 12:20

qwattash requested review from brooksdavis and bsdjhb April 1, 2026 12:20

qwattash force-pushed the cheri-rv64y-asm-refactor branch from d1dd6e8 to 480d75a Compare April 1, 2026 14:28

qwattash force-pushed the cheri-rv64y-asm-refactor branch from bcc3863 to 34a0120 Compare May 9, 2026 10:45

brooksdavis reviewed May 12, 2026

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Comment thread lib/libc/riscv/gen/setjmp.S Outdated

Comment thread sys/riscv/riscv/locore.S Outdated

jrtc27 reviewed May 12, 2026

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Comment thread lib/libc/riscv/gen/setjmp.S Outdated

qwattash force-pushed the cheri-rv64y-asm-refactor branch from 34a0120 to 2675da5 Compare May 19, 2026 10:11

arichardson reviewed May 21, 2026

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Comment thread lib/libsys/riscv/cerror.S Outdated

arichardson reviewed May 21, 2026

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qwattash force-pushed the cheri-rv64y-asm-refactor branch from 2675da5 to 7ab8cfb Compare June 25, 2026 07:39

qwattash force-pushed the cheri-rv64y-asm-refactor branch 2 times, most recently from 285c65f to 822d3be Compare June 25, 2026 14:54

qwattash force-pushed the cheri-rv64y-asm-refactor branch from 822d3be to 2fec88b Compare July 28, 2026 17:07

qwattash added 8 commits July 28, 2026 18:29

cheri-rv64y: asm.h macros for rv64y 0.9.8 mnemonics support.

3249893

cheri-rv64y: Remove unnecessary ASM macro from cpufunc assembly.

db892a1

Rely on compiler menmonic aliases.

cheri-rv64y: copyinout.S use rv64y 0.9.8 mnemonics for xcheri.

3e27e16

Unify copyin/out assembly for hybrid and purecap. Use the new machine/asm.h macros and rely on complier mnemonic aliases.

cheri-rv64y: support.S use rv64y 0.9.8 mnemonics for xcheri.

77466f0

Unify support.S assembly for hybrid and purecap. Rely on asm.h macros and compiler mnemonic aliases. Partial patch, no csr registers yet.

cheri-rv64y: locore.S use rv64y 0.9.8 mnemonics for xcheri.

260e274

Unify locore assembly for hybrid and purecap. This reduces the amount of ifdefs and relies on both asm.h definitions and compilier mnemonic aliases.

cheri-rv64y: swtch.S use rv64y 0.9.8 mnemonics.

ab7783d

Unify context switch assembly hybrid and purecap. Rely on asm.h and compiler mnemonic aliases.

cheri-rv64y: exception.S use rv64y 0.9.8 mnemonics.

177a95b

Unify hybrid and purecap assembly for exception handling. Rely on compiler mnemonic aliases and asm.h macros.

cheri-rv64y: bus_space_asm.S use rv64y 0.9.8 mnemonics.

a24ce71

Unify bus space assembly for hybrid and purecap.

qwattash commented Jul 28, 2026

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Comment thread sys/riscv/riscv/sigtramp.S

qwattash commented Jul 28, 2026

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Comment thread sys/riscv/include/asm.h Outdated

qwattash commented Jul 28, 2026

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qwattash added 4 commits July 28, 2026 21:11

cheri-rv64y: Update userspace assembly with rv64y 0.9.8 mnemonics.

26c1419

Update assembly in libc, libsys and rtld.

cheri-rv64y: sigtramp.S use rv64y 0.9.8 mnemonics for xcheri.

b6c6a02

cheri riscv: Restrict capability permissions on boot PCC.

35eaba7

cheri-rv64y: Implement MODESW macros.

5d562e9

These are used to abstract away switching between hybrid and purecap encodings in the hybrid kernel. This patch facilitates migration to cheri-rv64y.

qwattash force-pushed the cheri-rv64y-asm-refactor branch from 2fec88b to 5d562e9 Compare July 28, 2026 20:18

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qwattash commented Mar 20, 2026

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qwattash commented Jun 25, 2026

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qwattash commented Mar 19, 2026 •

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