From 08b16838cbd7349c4f340123fac2b1b32dfff131 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Fri, 8 Sep 2023 22:30:21 +0300 Subject: [PATCH 001/116] FROMLIST: dt-bindings: cpufreq: qcom-hw: Add the SM7150 compatible Add the compatible for the cpufreq present on SM7150 platforms. Signed-off-by: Danila Tikhonov --- Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index 98eb36bff1727d..09cdb8b400c229 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -29,6 +29,7 @@ properties: - qcom,sdm845-cpufreq-hw - qcom,sm6115-cpufreq-hw - qcom,sm6350-cpufreq-hw + - qcom,sm7150-cpufreq-hw - qcom,sm8150-cpufreq-hw - const: qcom,cpufreq-hw @@ -148,6 +149,7 @@ allOf: - qcom,sm6115-cpufreq-hw - qcom,sm6350-cpufreq-hw - qcom,sm6375-cpufreq-epss + - qcom,sm7150-cpufreq-hw then: properties: reg: From 116fde7434552d40a10338e110b7c3c01cd2ee40 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Fri, 8 Sep 2023 22:22:26 +0300 Subject: [PATCH 002/116] FROMLIST: dt-bindings: watchdog: qcom-wdt: Add the SM7150 compatible Document the SM7150 watchdog compatible. Signed-off-by: Danila Tikhonov --- Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml index 9f861045b71e83..627dd5bb868bd2 100644 --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml @@ -42,6 +42,7 @@ properties: - qcom,apss-wdt-sdx65 - qcom,apss-wdt-sm6115 - qcom,apss-wdt-sm6350 + - qcom,apss-wdt-sm7150 - qcom,apss-wdt-sm8150 - qcom,apss-wdt-sm8250 - qcom,apss-wdt-x1e80100 From baa91195810f868b9f02edd287b8831a49cc837b Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Fri, 8 Sep 2023 22:05:24 +0300 Subject: [PATCH 003/116] FROMLIST: dt-bindings: thermal: tsens: Add the SM7150 compatible Add the TSENS v2.x controller found on SM7150. Signed-off-by: Danila Tikhonov --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 7d34ba00e684fc..fe466304cdc611 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -77,6 +77,7 @@ properties: - qcom,sm6115-tsens - qcom,sm6350-tsens - qcom,sm6375-tsens + - qcom,sm7150-tsens - qcom,sm8150-tsens - qcom,sm8250-tsens - qcom,sm8350-tsens From 3a5e1a2873933dcd91100a5887443d88d1a312fb Mon Sep 17 00:00:00 2001 From: David Wronek Date: Fri, 8 Sep 2023 22:00:13 +0300 Subject: [PATCH 004/116] FROMLIST: dt-bindings: interrupt-controller: qcom-pdc: Add the SM7150 compatible Add a compatible for the Power Domain Controller on SM7150 platforms. Signed-off-by: David Wronek Signed-off-by: Danila Tikhonov --- .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml index b4942881b9c963..5517b1badd7d19 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -48,6 +48,7 @@ properties: - qcom,sdx75-pdc - qcom,sm4450-pdc - qcom,sm6350-pdc + - qcom,sm7150-pdc - qcom,sm8150-pdc - qcom,sm8250-pdc - qcom,sm8350-pdc From 16eda4e44c62f1542172982768b4d975dac1a12d Mon Sep 17 00:00:00 2001 From: David Wronek Date: Fri, 8 Sep 2023 21:57:06 +0300 Subject: [PATCH 005/116] FROMLIST: dt-bindings: usb: dwc3: Add the SM7150 compatible Document the SM7150 dwc3 compatible. Signed-off-by: David Wronek Signed-off-by: Danila Tikhonov --- Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index a7f58114c02e8a..6ce44a2210cc79 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -60,6 +60,7 @@ properties: - qcom,sm6125-dwc3 - qcom,sm6350-dwc3 - qcom,sm6375-dwc3 + - qcom,sm7150-dwc3 - qcom,sm8150-dwc3 - qcom,sm8250-dwc3 - qcom,sm8350-dwc3 @@ -227,6 +228,7 @@ allOf: - qcom,sdx65-dwc3 - qcom,sdx75-dwc3 - qcom,sm6350-dwc3 + - qcom,sm7150-dwc3 then: properties: clocks: @@ -504,6 +506,7 @@ allOf: - qcom,sdx75-dwc3 - qcom,sm4250-dwc3 - qcom,sm6350-dwc3 + - qcom,sm7150-dwc3 - qcom,sm8150-dwc3 - qcom,sm8250-dwc3 - qcom,sm8350-dwc3 From c2827ded8ed705eb525023a439c048666b745239 Mon Sep 17 00:00:00 2001 From: David Wronek Date: Fri, 8 Sep 2023 21:54:20 +0300 Subject: [PATCH 006/116] FROMLIST: dt-bindings: phy: qcom,qusb2: Add the SM7150 compatible Add devicetree compatible for the usb phy on SM7150 SoC. Signed-off-by: David Wronek Signed-off-by: Danila Tikhonov --- Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml index 39851ba9de4369..51dd79e6db6bb8 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml @@ -36,6 +36,7 @@ properties: - qcom,sdm670-qusb2-phy - qcom,sdm845-qusb2-phy - qcom,sm6350-qusb2-phy + - qcom,sm7150-qusb2-phy - const: qcom,qusb2-v2-phy reg: maxItems: 1 From f177c4e5d967f1e55e447746d696f8132e597894 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Fri, 8 Sep 2023 21:39:40 +0300 Subject: [PATCH 007/116] FROMLIST: dt-bindings: mfd: qcom,tcsr: Add the SM7150 compatible Document the qcom,sm7150-tcsr compatible. Signed-off-by: Danila Tikhonov --- Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml index 14ae3f00ef7e00..de8193897f03b4 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml @@ -35,6 +35,7 @@ properties: - qcom,sdx75-tcsr - qcom,sm4450-tcsr - qcom,sm6115-tcsr + - qcom,sm7150-tcsr - qcom,sm8150-tcsr - qcom,sm8250-tcsr - qcom,sm8350-tcsr From 8d412b65b81cc4cc210b4b442e2a49b77dddbb99 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Fri, 8 Sep 2023 21:33:13 +0300 Subject: [PATCH 008/116] FROMLIST: dt-bindings: net: qcom,ipa: Add the SM7150 compatible SM7150 and SC7180 both use IPA v4.2. Define corresponding compatible string, having the SC7180 as a fallback. Signed-off-by: Danila Tikhonov --- Documentation/devicetree/bindings/net/qcom,ipa.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/qcom,ipa.yaml b/Documentation/devicetree/bindings/net/qcom,ipa.yaml index fdeaa81b96454e..6e39fab4be3bc0 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipa.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipa.yaml @@ -57,6 +57,7 @@ properties: - items: - enum: - qcom,qcm2290-ipa + - qcom,sm7150-ipa - const: qcom,sc7180-ipa - items: - enum: From d7840b90155fa72c77f7549aad5bab15e2039005 Mon Sep 17 00:00:00 2001 From: David Wronek Date: Fri, 8 Sep 2023 21:30:53 +0300 Subject: [PATCH 009/116] FROMLIST: dt-bindings: ufs: qcom: Add the SM7150 compatible Document the compatible for the UFS found on SM7150. Signed-off-by: David Wronek Signed-off-by: Danila Tikhonov --- Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index 516bb61a46241f..7525e7207524d3 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -38,6 +38,7 @@ properties: - qcom,sm6115-ufshc - qcom,sm6125-ufshc - qcom,sm6350-ufshc + - qcom,sm7150-ufshc - qcom,sm8150-ufshc - const: qcom,ufshc - const: jedec,ufs-2.0 From 403a6c4c91be5b54dd5b7e8fb0547cadb12a3e73 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Fri, 8 Sep 2023 21:23:18 +0300 Subject: [PATCH 010/116] FROMLIST: dt-bindings: dmaengine: qcom: gpi: Add the SM7150 compatible Add a compatible for the GPI DMA controller on SM7150. It uses the same 0x0 offset as SDM845. Signed-off-by: Danila Tikhonov --- Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml index fde1df035ad12b..f078baab114d14 100644 --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -49,6 +49,7 @@ properties: - qcom,qcs615-gpi-dma - qcom,sdm670-gpi-dma - qcom,sm6125-gpi-dma + - qcom,sm7150-gpi-dma - qcom,sm8150-gpi-dma - qcom,sm8250-gpi-dma - const: qcom,sdm845-gpi-dma From 9e7c19551067daa630be7c75e9c1b69a0f193574 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Fri, 8 Sep 2023 21:14:47 +0300 Subject: [PATCH 011/116] FROMLIST: dt-bindings: nvmem: qfprom: Add the SM7150 compatible Document QFPROM compatible for SM7150. Signed-off-by: Danila Tikhonov --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 2ab047f2bb69de..ca87c0f3c1f1a0 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -51,6 +51,7 @@ properties: - qcom,sm6115-qfprom - qcom,sm6350-qfprom - qcom,sm6375-qfprom + - qcom,sm7150-qfprom - qcom,sm8150-qfprom - qcom,sm8250-qfprom - qcom,sm8450-qfprom From 3f0c59bbaf22546f42e7e2eb4a5e2526b5b7d032 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Fri, 21 Feb 2025 21:46:31 +0300 Subject: [PATCH 012/116] FROMLIST: dt-bindings: crypto: qcom,inline-crypto-engine: Add the SM7150 compatible Document the Inline Crypto Engine (ICE) on the SM7150 Platform. Signed-off-by: Danila Tikhonov --- .../devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml index 876bf90ed96ef3..2c689a24536f94 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml @@ -20,6 +20,7 @@ properties: - qcom,sa8775p-inline-crypto-engine - qcom,sc7180-inline-crypto-engine - qcom,sc7280-inline-crypto-engine + - qcom,sm7150-inline-crypto-engine - qcom,sm8450-inline-crypto-engine - qcom,sm8550-inline-crypto-engine - qcom,sm8650-inline-crypto-engine From 15e1228edf1df60e0bd08b30c781b2f2277b671e Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Fri, 21 Feb 2025 22:24:59 +0300 Subject: [PATCH 013/116] FROMLIST: dt-bindings: interconnect: qcom-bwmon: Add the SM7150 compatible Document the compatibles used to describe the bwmons present on the SM7150 platform. Signed-off-by: Danila Tikhonov --- .../devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml index ce79521bb1ef2c..f197851e7b3557 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml @@ -37,6 +37,7 @@ properties: - qcom,sdm845-cpu-bwmon - qcom,sm6115-cpu-bwmon - qcom,sm6350-llcc-bwmon + - qcom,sm7150-cpu-bwmon - qcom,sm8250-cpu-bwmon - qcom,sm8550-cpu-bwmon - qcom,sm8650-cpu-bwmon @@ -51,6 +52,7 @@ properties: - qcom,sc7180-llcc-bwmon - qcom,sc8280xp-llcc-bwmon - qcom,sm6350-cpu-bwmon + - qcom,sm7150-llcc-bwmon - qcom,sm8250-llcc-bwmon - qcom,sm8550-llcc-bwmon - qcom,sm8650-llcc-bwmon From 500d1df226aba11eaf9f4568e2b063efd42e2af7 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Fri, 21 Feb 2025 22:29:10 +0300 Subject: [PATCH 014/116] FROMLIST: dt-bindings: i2c: qcom-cci: Add the SM7150 compatible Add the SM7150 CCI device string compatible. Signed-off-by: Danila Tikhonov --- Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index 7c497a358e1dc8..289fee7441f3f9 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -37,6 +37,7 @@ properties: - qcom,sdm845-cci - qcom,sm6150-cci - qcom,sm6350-cci + - qcom,sm7150-cci - qcom,sm8250-cci - qcom,sm8450-cci - qcom,sm8550-cci @@ -214,6 +215,7 @@ allOf: contains: enum: - qcom,sc7280-cci + - qcom,sm7150-cci - qcom,sm8250-cci - qcom,sm8450-cci then: From d33ed7cd0801ed72ed935f826e2384fbd009b0ee Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Fri, 21 Feb 2025 22:35:04 +0300 Subject: [PATCH 015/116] FROMLIST: dt-bindings: clock: qcom-rpmhcc: Add the SM7150 compatible Update the documentation for clock rpmh driver on SM7150 SoCs. Signed-off-by: Danila Tikhonov --- .../bindings/clock/qcom,rpmhcc.yaml | 63 ++++++++++--------- 1 file changed, 34 insertions(+), 29 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index a2c404a579812d..4f6b77a2d1e585 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -16,35 +16,40 @@ description: | properties: compatible: - enum: - - qcom,eliza-rpmh-clk - - qcom,glymur-rpmh-clk - - qcom,kaanapali-rpmh-clk - - qcom,milos-rpmh-clk - - qcom,nord-rpmh-clk - - qcom,qcs615-rpmh-clk - - qcom,qdu1000-rpmh-clk - - qcom,sa8775p-rpmh-clk - - qcom,sar2130p-rpmh-clk - - qcom,sc7180-rpmh-clk - - qcom,sc7280-rpmh-clk - - qcom,sc8180x-rpmh-clk - - qcom,sc8280xp-rpmh-clk - - qcom,sdm670-rpmh-clk - - qcom,sdm845-rpmh-clk - - qcom,sdx55-rpmh-clk - - qcom,sdx65-rpmh-clk - - qcom,sdx75-rpmh-clk - - qcom,sm4450-rpmh-clk - - qcom,sm6350-rpmh-clk - - qcom,sm8150-rpmh-clk - - qcom,sm8250-rpmh-clk - - qcom,sm8350-rpmh-clk - - qcom,sm8450-rpmh-clk - - qcom,sm8550-rpmh-clk - - qcom,sm8650-rpmh-clk - - qcom,sm8750-rpmh-clk - - qcom,x1e80100-rpmh-clk + oneOf: + - enum: + - qcom,eliza-rpmh-clk + - qcom,glymur-rpmh-clk + - qcom,kaanapali-rpmh-clk + - qcom,milos-rpmh-clk + - qcom,nord-rpmh-clk + - qcom,qcs615-rpmh-clk + - qcom,qdu1000-rpmh-clk + - qcom,sa8775p-rpmh-clk + - qcom,sar2130p-rpmh-clk + - qcom,sc7180-rpmh-clk + - qcom,sc7280-rpmh-clk + - qcom,sc8180x-rpmh-clk + - qcom,sc8280xp-rpmh-clk + - qcom,sdm670-rpmh-clk + - qcom,sdm845-rpmh-clk + - qcom,sdx55-rpmh-clk + - qcom,sdx65-rpmh-clk + - qcom,sdx75-rpmh-clk + - qcom,sm4450-rpmh-clk + - qcom,sm6350-rpmh-clk + - qcom,sm8150-rpmh-clk + - qcom,sm8250-rpmh-clk + - qcom,sm8350-rpmh-clk + - qcom,sm8450-rpmh-clk + - qcom,sm8550-rpmh-clk + - qcom,sm8650-rpmh-clk + - qcom,sm8750-rpmh-clk + - qcom,x1e80100-rpmh-clk + - items: + - enum: + - qcom,sm7150-rpmh-clk + - const: qcom,sc7180-rpmh-clk clocks: maxItems: 1 From 4bdfc0f925d6351bff75dbf7d3fd98b92cc53aef Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Fri, 21 Feb 2025 22:46:26 +0300 Subject: [PATCH 016/116] FROMLIST: dt-bindings: interconnect: OSM L3: Add the SM7150 compatible Document the OSM L3 found in the Qualcomm SM7150 platform. Signed-off-by: Danila Tikhonov --- Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index 41b9f758bf8b80..c58e21c7484186 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -24,6 +24,7 @@ properties: - qcom,sdm670-osm-l3 - qcom,sdm845-osm-l3 - qcom,sm6350-osm-l3 + - qcom,sm7150-osm-l3 - qcom,sm8150-osm-l3 - const: qcom,osm-l3 - items: From ea39442376003ce7f9b4010fd12d46455fb20ddf Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Fri, 21 Feb 2025 22:47:04 +0300 Subject: [PATCH 017/116] FROMLIST: dt-bindings: arm-smmu: Add the SM7150 compatible Document the SM7150 SMMU block. Signed-off-by: Danila Tikhonov --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 06fb5c8e7547cb..10be8ca2397f5b 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -59,6 +59,7 @@ properties: - qcom,sm6125-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 + - qcom,sm7150-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - qcom,sm8350-smmu-500 @@ -107,6 +108,7 @@ properties: - qcom,sc8280xp-smmu-500 - qcom,sm6115-smmu-500 - qcom,sm6125-smmu-500 + - qcom,sm7150-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - qcom,sm8350-smmu-500 @@ -597,6 +599,7 @@ allOf: - qcom,sdx65-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 + - qcom,sm7150-smmu-500 then: properties: clock-names: false From 330dbf3d98bd7ec95087800cb1a94221ec8daf92 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Mon, 21 Apr 2025 21:59:45 +0300 Subject: [PATCH 018/116] FROMLIST: dt-bindings: clock: qcom,gpucc: Add the SM7150 compatible SM7150 is fully compatible with the existing SC7180 GPU Clock Controller driver. Define corresponding compatible string, having the qcom,sc7180-gpucc as a fallback. Signed-off-by: Danila Tikhonov --- .../devicetree/bindings/clock/qcom,gpucc.yaml | 29 +++++++++++-------- 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index 4cdff6161bf0b1..2bbe42523f99ae 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -28,18 +28,23 @@ description: | properties: compatible: - enum: - - qcom,qcs8300-gpucc - - qcom,sdm845-gpucc - - qcom,sa8775p-gpucc - - qcom,sc7180-gpucc - - qcom,sc7280-gpucc - - qcom,sc8180x-gpucc - - qcom,sc8280xp-gpucc - - qcom,sm6350-gpucc - - qcom,sm8150-gpucc - - qcom,sm8250-gpucc - - qcom,sm8350-gpucc + oneOf: + - enum: + - qcom,qcs8300-gpucc + - qcom,sdm845-gpucc + - qcom,sa8775p-gpucc + - qcom,sc7180-gpucc + - qcom,sc7280-gpucc + - qcom,sc8180x-gpucc + - qcom,sc8280xp-gpucc + - qcom,sm6350-gpucc + - qcom,sm8150-gpucc + - qcom,sm8250-gpucc + - qcom,sm8350-gpucc + - items: + - enum: + - qcom,sm7150-gpucc + - const: qcom,sc7180-gpucc clocks: items: From 1aebf4cbd219afa5f54262b3f4fa956e20758cfb Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Fri, 21 Feb 2025 21:54:33 +0300 Subject: [PATCH 019/116] FROMLIST: dt-bindings: remoteproc: qcom: sc7180-pas: Add the SM7150 compatible Add the compatibles and constraints for the ADSP, CDSP and MPSS found on the SM7150 SoC. Signed-off-by: Danila Tikhonov --- .../bindings/remoteproc/qcom,sc7180-pas.yaml | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml index 66b455d0a8e327..439350f8898557 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/remoteproc/qcom,sc7180-pas.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm SC7180/SC7280 Peripheral Authentication Service +title: Qualcomm SC7180/SC7280/SM7150 Peripheral Authentication Service maintainers: - Manivannan Sadhasivam description: - Qualcomm SC7180/SC7280 SoC Peripheral Authentication Service loads and boots - firmware on the Qualcomm DSP Hexagon cores. + Qualcomm SC7180/SC7280/SM7150 SoC Peripheral Authentication Service loads and + boots firmware on the Qualcomm DSP Hexagon cores. properties: compatible: @@ -22,6 +22,9 @@ properties: - qcom,sc7280-cdsp-pas - qcom,sc7280-mpss-pas - qcom,sc7280-wpss-pas + - qcom,sm7150-adsp-pas + - qcom,sm7150-cdsp-pas + - qcom,sm7150-mpss-pas reg: maxItems: 1 @@ -60,6 +63,8 @@ allOf: compatible: enum: - qcom,sc7180-adsp-pas + - qcom,sm7150-adsp-pas + - qcom,sm7150-cdsp-pas then: properties: interrupts: @@ -79,6 +84,7 @@ allOf: enum: - qcom,sc7180-adsp-pas - qcom,sc7280-adsp-pas + - qcom,sm7150-adsp-pas then: properties: power-domains: @@ -95,6 +101,7 @@ allOf: compatible: enum: - qcom,sc7180-mpss-pas + - qcom,sm7150-mpss-pas then: properties: power-domains: @@ -130,6 +137,7 @@ allOf: enum: - qcom,sc7280-cdsp-pas - qcom,sc7280-wpss-pas + - qcom,sm7150-cdsp-pas then: properties: power-domains: From 695f15ef9437f13ce09b7785f09707d91c3b256d Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Tue, 22 Apr 2025 20:13:46 +0300 Subject: [PATCH 020/116] FROMLIST: remoteproc: qcom: pas: Add SM7150 remoteproc support Add DSP Peripheral Authentication Service support for the SM7150 platform. Signed-off-by: Danila Tikhonov --- drivers/remoteproc/qcom_q6v5_pas.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index da27d1d3c9da64..56aed30ab5d20b 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -1580,6 +1580,9 @@ static const struct of_device_id qcom_pas_of_match[] = { { .compatible = "qcom,sm6375-adsp-pas", .data = &sm6350_adsp_resource }, { .compatible = "qcom,sm6375-cdsp-pas", .data = &sm8150_cdsp_resource }, { .compatible = "qcom,sm6375-mpss-pas", .data = &sm6375_mpss_resource }, + { .compatible = "qcom,sm7150-adsp-pas", .data = &sm8350_adsp_resource }, + { .compatible = "qcom,sm7150-cdsp-pas", .data = &sm6350_cdsp_resource }, + { .compatible = "qcom,sm7150-mpss-pas", .data = &mpss_resource_init }, { .compatible = "qcom,sm8150-adsp-pas", .data = &sm8150_adsp_resource }, { .compatible = "qcom,sm8150-cdsp-pas", .data = &sm8150_cdsp_resource }, { .compatible = "qcom,sm8150-mpss-pas", .data = &mpss_resource_init }, From a54638ff3707daab72abd1fef77af94c1461d4ee Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Wed, 5 Apr 2023 18:37:07 +0300 Subject: [PATCH 021/116] FROMLIST: cpufreq: Add SM7150 to cpufreq-dt-platdev blocklist The Qualcomm SM7150 platform uses the qcom-cpufreq-hw driver, so add it to the cpufreq-dt-platdev driver's blocklist. Signed-off-by: Danila Tikhonov --- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index ff1204c666b197..95489fcb930e20 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -177,6 +177,7 @@ static const struct of_device_id blocklist[] __initconst = { { .compatible = "qcom,sm6350", }, { .compatible = "qcom,sm6375", }, { .compatible = "qcom,sm7125", }, + { .compatible = "qcom,sm7150", }, { .compatible = "qcom,sm7225", }, { .compatible = "qcom,sm7325", }, { .compatible = "qcom,sm8150", }, From 262f34e647e26b8e5577a95005556d9dc430858a Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Tue, 24 May 2022 00:17:04 +0300 Subject: [PATCH 022/116] FROMLIST: arm64: dts: qcom: Add dtsi for Snapdragon 730/730g/732g (SM7150) SoCs Add base dtsi for SM7150-AA/SM7150-AB/SM7150-AC SoCs Co-developed-by: David Wronek Signed-off-by: David Wronek Co-developed-by: Jens Reidel Signed-off-by: Jens Reidel Signed-off-by: Danila Tikhonov --- arch/arm64/boot/dts/qcom/sm7150.dtsi | 5013 ++++++++++++++++++++++++++ 1 file changed, 5013 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm7150.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm7150.dtsi b/arch/arm64/boot/dts/qcom/sm7150.dtsi new file mode 100644 index 00000000000000..2e6c17961083fd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7150.dtsi @@ -0,0 +1,5013 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Danila Tikhonov + * Copyright (c) 2025, David Wronek + * Copyright (c) 2025, Jens Reidel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + mmc1 = &sdhc_1; + mmc2 = &sdhc_2; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + spi0 = &spi0; + spi1 = &spi1; + spi3 = &spi3; + spi4 = &spi4; + spi6 = &spi6; + spi7 = &spi7; + spi8 = &spi8; + spi10 = &spi10; + spi11 = &spi11; + }; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo470"; + reg = <0x0 0x0>; + + clocks = <&cpufreq_hw 0>; + + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + + power-domains = <&cpu_pd0>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_0>; + capacity-dmips-mhz = <488>; + dynamic-power-coefficient = <137>; + + qcom,freq-domain = <&cpufreq_hw 0>; + + operating-points-v2 = <&cpu0_opp_table>; + + #cooling-cells = <2>; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + + l3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo470"; + reg = <0x0 0x100>; + + clocks = <&cpufreq_hw 0>; + + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + + power-domains = <&cpu_pd1>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_100>; + capacity-dmips-mhz = <488>; + dynamic-power-coefficient = <137>; + + qcom,freq-domain = <&cpufreq_hw 0>; + + operating-points-v2 = <&cpu0_opp_table>; + + #cooling-cells = <2>; + + l2_100: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo470"; + reg = <0x0 0x200>; + + clocks = <&cpufreq_hw 0>; + + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + + power-domains = <&cpu_pd2>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_200>; + capacity-dmips-mhz = <488>; + dynamic-power-coefficient = <137>; + + qcom,freq-domain = <&cpufreq_hw 0>; + + operating-points-v2 = <&cpu0_opp_table>; + + #cooling-cells = <2>; + + l2_200: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo470"; + reg = <0x0 0x300>; + + clocks = <&cpufreq_hw 0>; + + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + + power-domains = <&cpu_pd3>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_300>; + capacity-dmips-mhz = <488>; + dynamic-power-coefficient = <137>; + + qcom,freq-domain = <&cpufreq_hw 0>; + + operating-points-v2 = <&cpu0_opp_table>; + + #cooling-cells = <2>; + + l2_300: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo470"; + reg = <0x0 0x400>; + + clocks = <&cpufreq_hw 0>; + + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + + power-domains = <&cpu_pd4>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_400>; + capacity-dmips-mhz = <488>; + dynamic-power-coefficient = <137>; + + qcom,freq-domain = <&cpufreq_hw 0>; + + operating-points-v2 = <&cpu0_opp_table>; + + #cooling-cells = <2>; + + l2_400: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo470"; + reg = <0x0 0x500>; + + clocks = <&cpufreq_hw 0>; + + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + + power-domains = <&cpu_pd5>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_500>; + capacity-dmips-mhz = <488>; + dynamic-power-coefficient = <137>; + + qcom,freq-domain = <&cpufreq_hw 0>; + + operating-points-v2 = <&cpu0_opp_table>; + + #cooling-cells = <2>; + + l2_500: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo470"; + reg = <0x0 0x600>; + + clocks = <&cpufreq_hw 1>; + + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + + power-domains = <&cpu_pd6>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_600>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <480>; + + qcom,freq-domain = <&cpufreq_hw 1>; + + operating-points-v2 = <&cpu6_opp_table>; + + #cooling-cells = <2>; + + l2_600: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo470"; + reg = <0x0 0x700>; + + clocks = <&cpufreq_hw 1>; + + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + + power-domains = <&cpu_pd7>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_700>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <480>; + + qcom,freq-domain = <&cpufreq_hw 1>; + + operating-points-v2 = <&cpu6_opp_table>; + + #cooling-cells = <2>; + + l2_700: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + + core5 { + cpu = <&cpu5>; + }; + + core6 { + cpu = <&cpu6>; + }; + + core7 { + cpu = <&cpu7>; + }; + }; + }; + + cpu_idle_states: idle-states { + entry-method = "psci"; + + little_cpu_sleep_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <549>; + exit-latency-us = <901>; + min-residency-us = <1774>; + local-timer-stop; + }; + + little_cpu_sleep_1: cpu-sleep-0-1 { + compatible = "arm,idle-state"; + idle-state-name = "little-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <915>; + min-residency-us = <4001>; + local-timer-stop; + }; + + big_cpu_sleep_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <523>; + exit-latency-us = <1244>; + min-residency-us = <2207>; + local-timer-stop; + }; + + big_cpu_sleep_1: cpu-sleep-1-1 { + compatible = "arm,idle-state"; + idle-state-name = "big-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <526>; + exit-latency-us = <1854>; + min-residency-us = <5555>; + local-timer-stop; + }; + }; + + domain-idle-states { + cluster_sleep_pc: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + }; + + cluster_sleep_cx_ret: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41001244>; + entry-latency-us = <3638>; + exit-latency-us = <4562>; + min-residency-us = <8467>; + }; + + cluster_aoss_sleep: cluster-sleep-2 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100b244>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9826>; + }; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-sm7150", + "qcom,scm"; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_opp1: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */ + opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; + }; + + cpu0_opp2: opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <(200000 * 4 * 2 * 2) (556800 * 16 * 2)>; + }; + + cpu0_opp3: opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + opp-peak-kBps = <(300000 * 4 * 2 * 2) (768000 * 16 * 2)>; + }; + + cpu0_opp4: opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <(300000 * 4 * 2 * 2) (940800 * 16 * 2)>; + }; + + cpu0_opp5: opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-peak-kBps = <(451000 * 4 * 2 * 2) (1190400 * 16 * 2)>; + }; + + cpu0_opp6: opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <(451000 * 4 * 2 * 2) (1305600 * 16 * 2)>; + }; + + cpu0_opp7: opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <(547000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + cpu0_opp8: opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <(547000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + cpu0_opp9: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(547000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + cpu0_opp10: opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <(768000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + }; + + cpu6_opp_table: opp-table-cpu6 { + compatible = "operating-points-v2"; + opp-shared; + + cpu6_opp1: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; + }; + + cpu6_opp2: opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-peak-kBps = <(200000 * 4 * 2 * 2) (652800 * 16 * 2)>; + }; + + cpu6_opp3: opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-peak-kBps = <(200000 * 4 * 2 * 2) (768000 * 16 * 2)>; + }; + + cpu6_opp4: opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-peak-kBps = <(200000 * 4 * 2 * 2) (940800 * 16 * 2)>; + }; + + cpu6_opp5: opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + opp-peak-kBps = <(300000 * 4 * 2 * 2) (940800 * 16 * 2)>; + }; + + cpu6_opp6: opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-peak-kBps = <(300000 * 4 * 2 * 2) (1190400 * 16 * 2)>; + }; + + cpu6_opp7: opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <(547000 * 4 * 2 * 2) (1305600 * 16 * 2)>; + }; + + cpu6_opp8: opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + opp-peak-kBps = <(768000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + cpu6_opp9: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + cpu6_opp10: opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + cpu6_opp11: opp-1939200000 { + opp-hz = /bits/ 64 <1939200000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + cpu6_opp12: opp-2169600000 { + opp-hz = /bits/ 64 <2169600000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + cpu6_opp13: opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + cpu6_opp14: opp-2304000000 { + opp-hz = /bits/ 64 <2304000000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-275000000 { + opp-hz = /bits/ 64 <275000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + + qup_opp_table: opp-table-qup { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + + pmu-a76 { + compatible = "arm,cortex-a78-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0 + &little_cpu_sleep_1>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0 + &little_cpu_sleep_1>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0 + &little_cpu_sleep_1>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0 + &little_cpu_sleep_1>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0 + &little_cpu_sleep_1>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0 + &little_cpu_sleep_1>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&big_cpu_sleep_0 + &big_cpu_sleep_1>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&big_cpu_sleep_0 + &big_cpu_sleep_1>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&cluster_sleep_pc + &cluster_sleep_cx_ret + &cluster_aoss_sleep>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hypervisor@85700000 { + reg = <0x0 0x85700000 0x0 0x600000>; + no-map; + }; + + /* XBL and AOP are splitted */ + xbl_mem: xbl@85d00000 { + reg = <0x0 0x85d00000 0x0 0x200000>; + no-map; + }; + + aop_mem: aop@85f00000 { + reg = <0x0 0x85f00000 0x0 0x20000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@85f20000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x85f20000 0x0 0x20000>; + no-map; + }; + + sec_apps_mem: sec-apps@85fff000 { + reg = <0x0 0x85fff000 0x0 0x1000>; + no-map; + }; + + smem_mem: smem@86000000 { + reg = <0x0 0x86000000 0x0 0x200000>; + no-map; + }; + + tz_mem: trust-zone@86200000 { + reg = <0x0 0x86200000 0x0 0x2d00000>; + no-map; + }; + + camera_mem: camera@8ab00000 { + reg = <0x0 0x8ab00000 0x0 0x500000>; + no-map; + }; + + mpss_mem: mpss@8b000000 { + reg = <0x0 0x8b000000 0x0 0x8400000>; + no-map; + }; + + venus_mem: venus@93400000 { + reg = <0x0 0x93400000 0x0 0x500000>; + no-map; + }; + + cdsp_mem: cdsp@93900000 { + reg = <0x0 0x93900000 0x0 0x1e00000>; + no-map; + }; + + adsp_mem: adsp@95700000 { + reg = <0x0 0x95700000 0x0 0x1e00000>; + no-map; + }; + + wlan_msa_mem: wlan-msa@97500000 { + reg = <0x0 0x97500000 0x0 0x180000>; + no-map; + }; + + npu_mem: npu@97680000 { + reg = <0x0 0x97680000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@97700000 { + reg = <0x0 0x97700000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@97710000 { + reg = <0x0 0x97710000 0x0 0x5000>; + no-map; + }; + + gpu_mem: gpu@97715000 { + reg = <0x0 0x97715000 0x0 0x2000>; + no-map; + }; + + qseecom_mem: qseecom@9e400000 { + reg = <0x0 0x9e400000 0x0 0x1400000>; + no-map; + }; + + sec_cdsp_mem: sec-cdsp@9f800000 { + reg = <0x0 0x9f800000 0x0 0x1e00000>; + no-map; + }; + + dfps_data_mem: dfps-data@9e300000 { + reg = <0x0 0x9d700000 0x0 0x0100000>; + no-map; + }; + }; + + smem: smem { + compatible = "qcom,smem"; + + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupts = ; + + mboxes = <&apss_shared 26>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + + interrupts = ; + + mboxes = <&apss_shared 6>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + + interrupts = ; + + mboxes = <&apss_shared 14>; + + qcom,smem = <435>, <428>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_ipa_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible = "qcom,sm7150-gcc"; + reg = <0x0 0x00100000 0x0 0x1f0000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + qfprom: efuse@784000 { + compatible = "qcom,sm7150-qfprom", + "qcom,qfprom"; + reg = <0x0 0x00784000 0x0 0x8ff>; + + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu-speed-bin@1a2 { + reg = <0x1a2 0x2>; + bits = <5 8>; + }; + }; + + gpi_dma0: dma-controller@800000 { + compatible = "qcom,sm7150-gpi-dma", + "qcom,sdm845-gpi-dma"; + reg = <0x0 0x00800000 0x0 0x60000>; + + interrupts = , + , + , + , + , + , + , + ; + + dma-channels = <8>; + dma-channel-mask = <0x0f>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x216 0x0>; + + dma-coherent; + + status = "disabled"; + }; + + qupv3_id_0: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x6000>; + + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + iommus = <&apps_smmu 0x203 0x0>; + + dma-coherent; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + i2c0: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00880000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c0_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi0: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00880000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi0_spi>, + <&qup_spi0_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c1: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00884000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c1_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi1: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00884000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi1_spi>, + <&qup_spi1_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c2: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00888000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c2_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c3: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0088c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c3_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi3: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0088c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi3_spi>, + <&qup_spi3_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart3: serial@88c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x0088c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc A1NOC_SNOC_MAS QCOM_ICC_TAG_ALWAYS + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart3_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c4: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00890000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c4_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi4: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00890000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi4_spi>, + <&qup_spi4_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart4: serial@890000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00890000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc A1NOC_SNOC_MAS QCOM_ICC_TAG_ALWAYS + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart4_default>; + + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,sm7150-gpi-dma", + "qcom,sdm845-gpi-dma"; + reg = <0x0 0x00a00000 0x0 0x60000>; + + interrupts = , + , + , + , + , + , + , + ; + + dma-channels = <8>; + dma-channel-mask = <0x0f>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x4d6 0x0>; + + dma-coherent; + + status = "disabled"; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x6000>; + + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + iommus = <&apps_smmu 0x4c3 0x0>; + + dma-coherent; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + i2c6: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c6_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi6: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi6_spi>, + <&qup_spi6_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c7: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a84000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c7_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi7: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a84000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi7_spi>, + <&qup_spi7_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c8: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c8_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi8: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi8_spi>, + <&qup_spi8_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart8: serial@a88000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&system_noc A1NOC_SNOC_MAS QCOM_ICC_TAG_ALWAYS + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart8_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c9: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c9_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c10: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a90000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c10_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi10: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a90000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi10_spi>, + <&qup_spi10_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart10: serial@a90000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a90000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&system_noc A1NOC_SNOC_MAS QCOM_ICC_TAG_ALWAYS + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart10_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c11: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a94000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c11_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi11: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a94000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi11_spi>, + <&qup_spi11_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart11: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a94000 0x0 0x4000>; + + interrupts = ; + + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + + interconnects = <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&system_noc A1NOC_SNOC_MAS QCOM_ICC_TAG_ALWAYS + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart11_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + }; + + mc_virt: interconnect@1380000 { + compatible = "qcom,sm7150-mc-virt"; + reg = <0x0 0x01380000 0x0 0x40000>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + config_noc: interconnect@1500000 { + compatible = "qcom,sm7150-config-noc"; + reg = <0x0 0x01500000 0x0 0x28000>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sm7150-system-noc"; + reg = <0x0 0x01620000 0x0 0x40000>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + + camnoc_virt: interconnect-0 { + compatible = "qcom,sm7150-camnoc-virt"; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sm7150-aggre1-noc"; + reg = <0x0 0x016e0000 0x0 0x11080>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sm7150-aggre2-noc"; + reg = <0x0 0x01700000 0x0 0x1f080>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sm7150-mmss-noc"; + reg = <0x0 0x01740000 0x0 0x1c100>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,sm7150-ufshc", + "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x0 0x01d84000 0x0 0x3000>; + + interrupts = ; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + operating-points-v2 = <&ufs_opp_table>; + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ufs-ddr", + "cpu-ufs"; + + power-domains = <&gcc UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0x300 0x0>; + + lanes-per-direction = <1>; + qcom,ice = <&ice>; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + + #reset-cells = <1>; + + status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <37500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sm7150-qmp-ufs-phy"; + reg = <0x0 0x01d87000 0x0 0x1000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>; + clock-names = "ref", + "ref_aux", + "qref"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + power-domains = <&gcc UFS_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + ice: crypto@1d90000 { + compatible = "qcom,sm7150-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x01d90000 0x0 0x8000>; + + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + + ipa: ipa@1e40000 { + compatible = "qcom,sm7150-ipa", + "qcom,sc7180-ipa"; + reg = <0x0 0x01e40000 0x0 0x7000>, + <0x0 0x01e47000 0x0 0x2000>, + <0x0 0x01e04000 0x0 0x2c000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + iommus = <&apps_smmu 0x520 0x0>, + <&apps_smmu 0x522 0x0>; + + interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_ipa_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_ipa_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + clock-names = "core"; + + interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI_CH0 0>, + <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>; + interconnect-names = "memory", + "imem", + "config"; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_ipa_out 0>, + <&smp2p_ipa_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + status = "disabled"; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x20000>; + + #hwlock-cells = <1>; + }; + + tcsr_regs_1: syscon@1f60000 { + compatible = "qcom,sm7150-tcsr", + "syscon"; + reg = <0x0 0x01f60000 0x0 0x20000>; + }; + + tcsr_regs_2: syscon@1fc0000 { + compatible = "qcom,sm7150-tcsr", + "syscon"; + reg = <0x0 0x01fc0000 0x0 0x40000>; + }; + + tlmm: pinctrl@3500000 { + compatible = "qcom,sm7150-tlmm"; + reg = <0x0 0x03500000 0x0 0x300000>, + <0x0 0x03900000 0x0 0x300000>, + <0x0 0x03d00000 0x0 0x300000>; + reg-names = "west", + "north", + "south"; + + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&tlmm 0 0 120>; + + wakeup-parent = <&pdc>; + + cci0_default: cci0-default-state { + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci0_sleep: cci0-sleep-state { + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_default: cci1-default-state { + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci1_sleep: cci1-sleep-state { + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci2_default: cci2-default-state { + pins = "gpio27", "gpio28"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci2_sleep: cci2-sleep-state { + pins = "gpio27", "gpio28"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio49", "gpio50"; + function = "qup00"; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio0", "gpio1"; + function = "qup01"; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio34", "gpio35"; + function = "qup02"; + }; + + qup_i2c3_default: qup-i2c3-default-state { + pins = "gpio38", "gpio39"; + function = "qup03"; + }; + + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio53", "gpio54"; + function = "qup04"; + }; + + qup_i2c6_default: qup-i2c6-default-state { + pins = "gpio59", "gpio60"; + function = "qup10"; + }; + + qup_i2c7_default: qup-i2c7-default-state { + pins = "gpio6", "gpio7"; + function = "qup11"; + }; + + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio42", "gpio43"; + function = "qup12"; + }; + + qup_i2c9_default: qup-i2c9-default-state { + pins = "gpio46", "gpio47"; + function = "qup13"; + }; + + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio110", "gpio111"; + function = "qup14"; + }; + + qup_i2c11_default: qup-i2c11-default-state { + pins = "gpio101", "gpio102"; + function = "qup15"; + }; + + qup_spi0_spi: qup-spi0-spi-state { + pins = "gpio49", "gpio50", "gpio51"; + function = "qup00"; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio52"; + function = "qup00"; + }; + + qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { + pins = "gpio52"; + function = "gpio"; + }; + + qup_spi1_spi: qup-spi1-spi-state { + pins = "gpio0", "gpio1", "gpio2"; + function = "qup01"; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins = "gpio3"; + function = "qup01"; + }; + + qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { + pins = "gpio3"; + function = "gpio"; + }; + + qup_spi3_spi: qup-spi3-spi-state { + pins = "gpio38", "gpio39", "gpio40"; + function = "qup03"; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins = "gpio41"; + function = "qup03"; + }; + + qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { + pins = "gpio41"; + function = "gpio"; + }; + + qup_spi4_spi: qup-spi4-spi-state { + pins = "gpio53", "gpio54", "gpio55"; + function = "qup04"; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins = "gpio56"; + function = "qup04"; + }; + + qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { + pins = "gpio56"; + function = "gpio"; + }; + + qup_spi6_spi: qup-spi6-spi-state { + pins = "gpio59", "gpio60", "gpio61"; + function = "qup10"; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio62"; + function = "qup10"; + }; + + qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { + pins = "gpio62"; + function = "gpio"; + }; + + qup_spi7_spi: qup-spi7-spi-state { + pins = "gpio6", "gpio7", "gpio8"; + function = "qup11"; + }; + + qup_spi7_cs: qup-spi7-cs-state { + pins = "gpio9"; + function = "qup11"; + }; + + qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { + pins = "gpio9"; + function = "gpio"; + }; + + qup_spi8_spi: qup-spi8-spi-state { + pins = "gpio42", "gpio43", "gpio44"; + function = "qup12"; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins = "gpio45"; + function = "qup12"; + }; + + qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { + pins = "gpio45"; + function = "gpio"; + }; + + qup_spi10_spi: qup-spi10-spi-state { + pins = "gpio110", "gpio111", "gpio112"; + function = "qup14"; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins = "gpio113"; + function = "qup14"; + }; + + qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { + pins = "gpio113"; + function = "gpio"; + }; + + qup_spi11_spi: qup-spi11-spi-state { + pins = "gpio101", "gpio102", "gpio103"; + function = "qup15"; + }; + + qup_spi11_cs: qup-spi11-cs-state { + pins = "gpio92", "gpio102", "gpio103"; + function = "qup15"; + }; + + qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { + pins = "gpio92"; + function = "gpio"; + }; + + qup_uart0_default: qup-uart0-default-state { + qup_uart0_cts: cts-pins { + pins = "gpio34"; + function = "qup00"; + }; + + qup_uart0_rts: rts-pins { + pins = "gpio35"; + function = "qup00"; + }; + + qup_uart0_tx: tx-pins { + pins = "gpio36"; + function = "qup00"; + }; + + qup_uart0_rx: rx-pins { + pins = "gpio37"; + function = "qup00"; + }; + }; + + qup_uart3_default: qup-uart3-default-state { + qup_uart3_cts: cts-pins { + pins = "gpio38"; + function = "qup03"; + }; + + qup_uart3_rts: rts-pins { + pins = "gpio39"; + function = "qup03"; + }; + + qup_uart3_tx: tx-pins { + pins = "gpio40"; + function = "qup03"; + }; + + qup_uart3_rx: rx-pins { + pins = "gpio41"; + function = "qup03"; + }; + }; + + qup_uart4_default: qup-uart4-default-state { + qup_uart4_tx: tx-pins { + pins = "gpio53"; + function = "qup04"; + }; + + qup_uart4_rx: rx-pins { + pins = "gpio56"; + function = "qup04"; + }; + }; + + qup_uart8_default: qup-uart8-default-state { + qup_uart8_tx: tx-pins { + pins = "gpio44"; + function = "qup12"; + }; + + qup_uart8_rx: rx-pins { + pins = "gpio45"; + function = "qup12"; + }; + }; + + qup_uart10_default: qup-uart10-default-state { + qup_uart10_tx: tx-pins { + pins = "gpio110"; + function = "qup14"; + }; + + qup_uart10_rx: rx-pins { + pins = "gpio113"; + function = "qup14"; + }; + }; + + qup_uart11_default: qup-uart11-default-state { + qup_uart11_tx: tx-pins { + pins = "gpio101"; + function = "qup15"; + }; + + qup_uart11_rx: rx-pins { + pins = "gpio92"; + function = "qup15"; + }; + }; + + pri_mi2s_active: pri-mi2s-active-state { + pins = "gpio49", "gpio51", "gpio52"; + function = "pri_mi2s"; + }; + + pri_mi2s_ws_active: pri-mi2s-ws-active-state { + pins = "gpio50"; + function = "pri_mi2s_ws"; + }; + + ter_mi2s_active: ter-mi2s-active-state { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + function = "ter_mi2s"; + }; + + sec_mi2s_active: sec-mi2s-active-state { + pins = "gpio57"; + function = "sec_mi2s"; + }; + + qua_mi2s_active: qua-mi2s-active-state { + pins = "gpio58"; + function = "qua_mi2s"; + }; + }; + + remoteproc_adsp: remoteproc@62400000 { + compatible = "qcom,sm7150-adsp-pas"; + reg = <0x0 0x62400000 0x0 0x100>; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + memory-region = <&adsp_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts = ; + + mboxes = <&apss_shared 24>; + qcom,remote-pid = <2>; + + label = "lpass"; + + apr { + compatible = "qcom,apr-v2"; + + qcom,glink-channels = "apr_audio_svc"; + + qcom,domain = ; + + #address-cells = <1>; + #size-cells = <0>; + + service@3 { + compatible = "qcom,q6core"; + reg = ; + + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + }; + + q6afe: service@4 { + compatible = "qcom,q6afe"; + reg = ; + + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6afedai: dais { + compatible = "qcom,q6afe-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + }; + + q6afecc: clock-controller { + compatible = "qcom,q6afe-clocks"; + #clock-cells = <2>; + }; + }; + + q6asm: service@7 { + compatible = "qcom,q6asm"; + reg = ; + + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6asmdai: dais { + compatible = "qcom,q6asm-dais"; + + iommus = <&apps_smmu 0x1b21 0x0>; + + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + }; + }; + + q6adm: service@8 { + compatible = "qcom,q6adm"; + reg = ; + + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6routing: routing { + compatible = "qcom,q6adm-routing"; + + #sound-dai-cells = <0>; + }; + }; + }; + + fastrpc { + compatible = "qcom,fastrpc"; + + qcom,glink-channels = "fastrpcglink-apps-dsp"; + + label = "adsp"; + + qcom,non-secure-domain; + + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + + iommus = <&apps_smmu 0x1b23 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + + iommus = <&apps_smmu 0x1b24 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + + iommus = <&apps_smmu 0x1b25 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + + iommus = <&apps_smmu 0x1b26 0x0>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + + iommus = <&apps_smmu 0x1b27 0x0>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + + qcom,nsessions = <3>; + + iommus = <&apps_smmu 0x1b28 0x0>; + dma-coherent; + }; + }; + }; + }; + + remoteproc_cdsp: remoteproc@8300000 { + compatible = "qcom,sm7150-cdsp-pas"; + reg = <0x0 0x08300000 0x0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names = "cx", + "mx"; + + memory-region = <&cdsp_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "cdsp"; + qcom,remote-pid = <5>; + mboxes = <&apss_shared 4>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + + iommus = <&apps_smmu 0x1421 0x0>, + <&apps_smmu 0x1441 0x0>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + + iommus = <&apps_smmu 0x1422 0x0>, + <&apps_smmu 0x1442 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + + iommus = <&apps_smmu 0x1423 0x0>, + <&apps_smmu 0x1443 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + + iommus = <&apps_smmu 0x1424 0x0>, + <&apps_smmu 0x1444 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + + iommus = <&apps_smmu 0x1425 0x0>, + <&apps_smmu 0x1445 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + + iommus = <&apps_smmu 0x1406 0x60>; + dma-coherent; + }; + }; + }; + }; + + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sm7150-mpss-pas"; + reg = <0x0 0x04080000 0x0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_MSS>; + power-domain-names = "cx", + "mx", + "mss"; + + memory-region = <&mpss_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_modem_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apss_shared 12>; + }; + }; + + gpu: gpu@5000000 { + compatible = "qcom,adreno-618.0", + "qcom,adreno"; + reg = <0x0 0x05000000 0x0 0x40000>, + <0x0 0x0509e000 0x0 0x1000>, + <0x0 0x05061000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + interconnects = <&gem_noc MASTER_GRAPHICS_3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + + iommus = <&adreno_smmu 0 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + #cooling-cells = <2>; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + zap-shader { + memory-region = <&gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-825000000 { + opp-hz = /bits/ 64 <825000000>; + opp-level = ; + opp-supported-hw = <0x11>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-level = ; + opp-supported-hw = <0x19>; + }; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-level = ; + opp-supported-hw = <0x04>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-level = ; + opp-supported-hw = <0x1d>; + }; + + opp-610000000 { + opp-hz = /bits/ 64 <610000000>; + opp-level = ; + opp-supported-hw = <0x02>; + }; + + opp-565000000 { + opp-hz = /bits/ 64 <565000000>; + opp-level = ; + opp-supported-hw = <0x1f>; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + opp-level = ; + opp-supported-hw = <0x1f>; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + opp-level = ; + opp-supported-hw = <0x1f>; + }; + + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-level = ; + opp-supported-hw = <0x1f>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + opp-level = ; + opp-supported-hw = <0x1f>; + }; + }; + }; + + adreno_smmu: iommu@5040000 { + compatible = "qcom,sm7150-smmu-v2", + "qcom,adreno-smmu", + "qcom,smmu-v2"; + reg = <0x0 0x05040000 0x0 0x10000>; + + interrupts = , + , + , + , + , + , + , + , + , + ; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "ahb", + "bus", + "iface"; + + power-domains = <&gpucc CX_GDSC>; + + #iommu-cells = <1>; + #global-interrupts = <2>; + }; + + gmu: gmu@506a000 { + compatible = "qcom,adreno-gmu-618.0", + "qcom,adreno-gmu"; + reg = <0x0 0x0506a000 0x0 0x31000>, + <0x0 0x0b290000 0x0 0x10000>, + <0x0 0x0b490000 0x0 0x10000>; + reg-names = "gmu", + "gmu_pdc", + "gmu_pdc_seq"; + + interrupts = , + ; + interrupt-names = "hfi", + "gmu"; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", + "cxo", + "axi", + "memnoc"; + + power-domains = <&gpucc CX_GDSC>, + <&gpucc GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + + gpucc: clock-controller@5090000 { + compatible = "qcom,sm7150-gpucc", + "qcom,sc7180-gpucc"; + reg = <0x0 0x05090000 0x0 0x9000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + sdhc_1: mmc@7c4000 { + compatible = "qcom,sm7150-sdhci", + "qcom,sdhci-msm-v5"; + reg = <0x0 0x007c4000 0x0 0x1000>, + <0x0 0x007c5000 0x0 0x1000>; + reg-names = "hc", + "cqhci"; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + + interconnects = <&aggre1_noc MASTER_EMMC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_EMMC_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + + iommus = <&apps_smmu 0x340 0x0>; + + bus-width = <8>; + + qcom,dll-config = <0x000f642c>; + qcom,ddr-config = <0x80040868>; + + non-removable; + supports-cqe; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + status = "disabled"; + + sdhc1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <200000 100000>; + opp-avg-kBps = <100000 50000>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <2718822 1359411>; + opp-avg-kBps = <261438 300000>; + }; + }; + }; + + sdhc_2: mmc@8804000 { + compatible = "qcom,sm7150-sdhci", + "qcom,sdhci-msm-v5"; + reg = <0x0 0x08804000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + + interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + iommus = <&apps_smmu 0x2a0 0x0>; + + bus-width = <4>; + + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <120000 80000>; + opp-avg-kBps = <60000 40000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <160000 100000>; + opp-avg-kBps = <80000 50000>; + }; + + opp-208000000 { + opp-hz = /bits/ 64 <208000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <200000 120000>; + opp-avg-kBps = <100000 60000>; + }; + }; + }; + + usb_1_hsphy: phy@88e2000 { + compatible = "qcom,sm7150-qusb2-phy", + "qcom,qusb2-v2-phy"; + reg = <0x0 0x088e2000 0x0 0x400>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_ahb", + "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pmu@90b6300 { + compatible = "qcom,sm7150-cpu-bwmon", + "qcom,sdm845-bwmon"; + reg = <0x0 0x090b6300 0x0 0x600>; + + interrupts = ; + + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <4577000>; + }; + + opp-1 { + opp-peak-kBps = <7110000>; + }; + + opp-2 { + opp-peak-kBps = <9155000>; + }; + + opp-3 { + opp-peak-kBps = <12298000>; + }; + + opp-4 { + opp-peak-kBps = <14236000>; + }; + }; + }; + + pmu@90cd000 { + compatible = "qcom,sm7150-llcc-bwmon", + "qcom,sc7280-llcc-bwmon"; + reg = <0x0 0x090cd000 0x0 0x1000>; + + interrupts = ; + + interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <762000>; + }; + + opp-1 { + opp-peak-kBps = <1144000>; + }; + + opp-2 { + opp-peak-kBps = <1720000>; + }; + + opp-3 { + opp-peak-kBps = <2086000>; + }; + + opp-4 { + opp-peak-kBps = <2597000>; + }; + + opp-5 { + opp-peak-kBps = <2929000>; + }; + + opp-6 { + opp-peak-kBps = <3879000>; + }; + + opp-7 { + opp-peak-kBps = <5161000>; + }; + + opp-8 { + opp-peak-kBps = <5931000>; + }; + + opp-9 { + opp-peak-kBps = <6881000>; + }; + }; + }; + + compute_noc: interconnect@80a8000 { + compatible = "qcom,sm7150-compute-noc"; + reg = <0x0 0x080a8000 0x0 0x1400>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + dc_noc: interconnect@9160000 { + compatible = "qcom,sm7150-dc-noc"; + reg = <0x0 0x09160000 0x0 0x3200>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + system-cache-controller@9200000 { + compatible = "qcom,sm7150-llcc"; + reg = <0x0 0x09200000 0x0 0x50000>, + <0x0 0x09280000 0x0 0x50000>, + <0x0 0x09600000 0x0 0x50000>; + reg-names = "llcc0_base", + "llcc1_base", + "llcc_broadcast_base"; + interrupts = ; + }; + + gem_noc: interconnect@9680000 { + compatible = "qcom,sm7150-gem-noc"; + reg = <0x0 0x09680000 0x0 0x3e200>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + usb_1: usb@a6f8800 { + compatible = "qcom,sm7150-dwc3", + "qcom,dwc3"; + reg = <0x0 0x0a6f8800 0x0 0x400>; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 9 IRQ_TYPE_EDGE_BOTH>, + <&pdc 8 IRQ_TYPE_EDGE_BOTH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, + <150000000>; + + interconnects = <&aggre2_noc MASTER_USB3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_USB3 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "usb-ddr", + "apps-usb"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + power-domains = <&gcc USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + #address-cells = <2>; + #size-cells = <2>; + wakeup-source; + ranges; + dma-ranges; + + status = "disabled"; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0x0 0x0a600000 0x0 0xe000>; + + interrupts = ; + + iommus = <&apps_smmu 0x540 0>; + + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + + dma-coherent; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { }; + }; + }; + }; + }; + + cci0: cci@ac4a000 { + compatible = "qcom,sm7150-cci", + "qcom,msm8996-cci"; + reg = <0x0 0x0ac4a000 0x0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_0_CLK>, + <&camcc CAMCC_CCI_0_CLK_SRC>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + pinctrl-names = "default", + "sleep"; + + power-domains = <&camcc TITAN_TOP_GDSC>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac4b000 { + compatible = "qcom,sm7150-cci", + "qcom,msm8996-cci"; + reg = <0x0 0x0ac4b000 0x0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_1_CLK>, + <&camcc CAMCC_CCI_1_CLK_SRC>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + pinctrl-0 = <&cci2_default>; + pinctrl-1 = <&cci2_sleep>; + pinctrl-names = "default", + "sleep"; + + power-domains = <&camcc TITAN_TOP_GDSC>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + videocc: clock-controller@ab00000 { + compatible = "qcom,sm7150-videocc"; + reg = <0x0 0x0ab00000 0x0 0x10000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>; + + power-domains = <&rpmhpd RPMHPD_CX>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + camcc: clock-controller@ad00000 { + compatible = "qcom,sm7150-camcc"; + reg = <0x0 0x0ad00000 0x0 0x10000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + + power-domains = <&rpmhpd RPMHPD_CX>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + mdss: display-subsystem@ae00000 { + compatible = "qcom,sm7150-mdss"; + reg = <0x0 0x0ae00000 0x0 0x1000>; + reg-names = "mdss"; + + interrupts = ; + + clocks = <&dispcc DISPCC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISPCC_MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "nrt_bus", + "core"; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_MDP_PORT1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + power-domains = <&dispcc MDSS_GDSC>; + + iommus = <&apps_smmu 0x800 0x440>; + + resets = <&dispcc DISPCC_MDSS_CORE_BCR>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdp: display-controller@ae01000 { + compatible = "qcom,sm7150-dpu"; + reg = <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x3000>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISPCC_MDSS_AHB_CLK>, + <&dispcc DISPCC_MDSS_ROT_CLK>, + <&dispcc DISPCC_MDSS_MDP_LUT_CLK>, + <&dispcc DISPCC_MDSS_MDP_CLK>, + <&dispcc DISPCC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "iface", + "rot", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISPCC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_CX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-344000000 { + opp-hz = /bits/ 64 <344000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sm7150-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x0ae94000 0x0 0x400>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 4>; + + clocks = <&dispcc DISPCC_MDSS_BYTE0_CLK>, + <&dispcc DISPCC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISPCC_MDSS_PCLK0_CLK>, + <&dispcc DISPCC_MDSS_ESC0_CLK>, + <&dispcc DISPCC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISPCC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISPCC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + power-domains = <&rpmhpd RPMHPD_CX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0x0 0x0ae94400 0x0 0x200>, + <0x0 0x0ae94600 0x0 0x280>, + <0x0 0x0ae94a00 0x0 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISPCC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,sm7150-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x0ae96000 0x0 0x400>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 5>; + + clocks = <&dispcc DISPCC_MDSS_BYTE1_CLK>, + <&dispcc DISPCC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISPCC_MDSS_PCLK1_CLK>, + <&dispcc DISPCC_MDSS_ESC1_CLK>, + <&dispcc DISPCC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISPCC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISPCC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + power-domains = <&rpmhpd RPMHPD_CX>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0x0 0x0ae96400 0x0 0x200>, + <0x0 0x0ae96600 0x0 0x280>, + <0x0 0x0ae96a00 0x0 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISPCC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm7150-dispcc"; + reg = <0x0 0x0af00000 0x0 0x20000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&sleep_clk>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, + <0>, + <0>; + + power-domains = <&rpmhpd RPMHPD_CX>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm7150-pdc", + "qcom,pdc"; + reg = <0x0 0x0b220000 0x0 0x30000>; + + interrupt-parent = <&intc>; + + qcom,pdc-ranges = <0 480 94>, + <94 609 31>, + <125 63 1>; + + #interrupt-cells = <2>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sm7150-tsens", + "qcom,tsens-v2"; + reg = <0x0 0x0c263000 0x0 0x1ff>, /* TM */ + <0x0 0x0c222000 0x0 0x1ff>; /* SROT */ + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <15>; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sm7150-tsens", + "qcom,tsens-v2"; + reg = <0x0 0x0c265000 0x0 0x1ff>, /* TM */ + <0x0 0x0c223000 0x0 0x1ff>; /* SROT */ + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <10>; + #thermal-sensor-cells = <1>; + }; + + aoss_qmp: power-management@c300000 { + compatible = "qcom,sm7150-aoss-qmp", + "qcom,aoss-qmp"; + reg = <0x0 0x0c300000 0x0 0x400>; + + interrupts = ; + mboxes = <&apss_shared 0>; + + #clock-cells = <0>; + }; + + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0x0 0x0c3f0000 0x0 0x400>; + }; + + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c440000 0x0 0x0001100>, + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x0100000>, + <0x0 0x0e700000 0x0 0x00a0000>, + <0x0 0x0c40a000 0x0 0x0026000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + + qcom,ee = <0>; + qcom,channel = <0>; + + interrupt-controller; + #interrupt-cells = <4>; + + #address-cells = <2>; + #size-cells = <0>; + }; + + sram@146aa000 { + compatible = "qcom,sm7150-imem", + "syscon", + "simple-mfd"; + reg = <0x0 0x146aa000 0x0 0x2000>; + + ranges = <0 0 0x146aa000 0x2000>; + + #address-cells = <1>; + #size-cells = <1>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sm7150-smmu-500", + "qcom,smmu-500", + "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + #iommu-cells = <2>; + #global-interrupts = <1>; + + dma-coherent; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + + interrupts = ; + + #interrupt-cells = <3>; + interrupt-controller; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; + + apss_shared: mailbox@17c00000 { + compatible = "qcom,sm7150-apss-shared", + "qcom,sdm845-apss-shared"; + reg = <0x0 0x17c00000 0x0 0x1000>; + + #mbox-cells = <1>; + }; + + watchdog@17c10000 { + compatible = "qcom,apss-wdt-sm7150", + "qcom,kpss-wdt"; + reg = <0x0 0x17c10000 0x0 0x1000>; + + clocks = <&sleep_clk>; + + interrupts = ; + }; + + timer@17c20000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17c20000 0x0 0x1000>; + + ranges = <0 0 0 0x20000000>; + + #address-cells = <1>; + #size-cells = <1>; + + frame@17c21000 { + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + + interrupts = , + ; + + frame-number = <0>; + }; + + frame@17c23000 { + reg = <0x17c23000 0x1000>; + + interrupts = ; + + frame-number = <1>; + + status = "disabled"; + }; + + frame@17c25000 { + reg = <0x17c25000 0x1000>; + + interrupts = ; + + frame-number = <2>; + + status = "disabled"; + }; + + frame@17c27000 { + reg = <0x17c27000 0x1000>; + + interrupts = ; + + frame-number = <3>; + + status = "disabled"; + }; + + frame@17c29000 { + reg = <0x17c29000 0x1000>; + + interrupts = ; + + frame-number = <4>; + + status = "disabled"; + }; + + frame@17c2b000 { + reg = <0x17c2b000 0x1000>; + + interrupts = ; + + frame-number = <5>; + + status = "disabled"; + }; + + frame@17c2d000 { + reg = <0x17c2d000 0x1000>; + + interrupts = ; + + frame-number = <6>; + + status = "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names = "drv-0", + "drv-1", + "drv-2"; + + interrupts = , + , + ; + + power-domains = <&cluster_pd>; + + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , , + , ; + + label = "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sm7150-rpmh-clk", + "qcom,sc7180-rpmh-clk"; + + clocks = <&xo_board>; + clock-names = "xo"; + + #clock-cells = <1>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sm7150-rpmhpd"; + + operating-points-v2 = <&rpmhpd_opp_table>; + + #power-domain-cells = <1>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_svs_l2: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp8 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp10 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp11 { + opp-level = ; + }; + }; + }; + }; + + osm_l3: interconnect@18321000 { + compatible = "qcom,sm7150-osm-l3", + "qcom,osm-l3"; + reg = <0x0 0x18321000 0x0 0x1400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>; + clock-names = "xo", + "alternate"; + + #interconnect-cells = <1>; + }; + + cpufreq_hw: cpufreq@18323000 { + compatible = "qcom,sm7150-cpufreq-hw", + "qcom,cpufreq-hw"; + reg = <0x0 0x18323000 0x0 0x1400>, + <0x0 0x18325800 0x0 0x1400>; + reg-names = "freq-domain0", + "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>; + clock-names = "xo", + "alternate"; + + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + + wifi: wifi@18800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0x0 0x18800000 0x0 0x800000>; + reg-names = "membase"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + iommus = <&apps_smmu 0x240 0x1>; + + memory-region = <&wlan_msa_mem>; + + status = "disabled"; + }; + }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 1>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu0_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1_thermal: cpu1-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 2>; + + trips { + cpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu1_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu1_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu2_thermal: cpu2-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu2_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu2_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu3_thermal: cpu3-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 4>; + + trips { + cpu3_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu3_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu3_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4_thermal: cpu4-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 5>; + + trips { + cpu4_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu4_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu4_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu5_thermal: cpu5-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 6>; + + trips { + cpu5_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu5_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu5_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu6_thermal: cpu6-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 9>; + + trips { + cpu6_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu6_alert0>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu6_alert1>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu7_thermal: cpu7-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 10>; + + trips { + cpu7_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu7_alert0>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu7_alert1>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu8_thermal: cpu8-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 11>; + + trips { + cpu8_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu8_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu8_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu8_alert0>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu8_alert1>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu9_thermal: cpu9-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 12>; + + trips { + cpu9_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu9_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu9_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu9_alert0>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu9_alert1>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + aoss0-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 0>; + + trips { + aoss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss0_crit: aoss0-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 7>; + + trips { + cpuss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss0_crit: cluster0-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 8>; + + trips { + cpuss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss1_crit: cluster0-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpuss0-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 13>; + + trips { + gpuss0_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpuss0_crit: gpuss0-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpuss0_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss1-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 14>; + + trips { + gpuss1_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpuss1_crit: gpuss1-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpuss1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 0>; + + trips { + aoss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss1_crit: aoss1-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cwlan-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 1>; + + trips { + cwlan_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cwlan_crit: cwlan-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + audio-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 2>; + + trips { + audio_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + audio_crit: audio-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + ddr-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 3>; + + trips { + ddr_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + ddr_crit: ddr-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + q6-hvx-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 4>; + + trips { + q6_hvx_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + q6_hvx_crit: q6-hvx-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 5>; + + trips { + camera_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + camera_crit: camera-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + mdm-core-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 6>; + + trips { + mdm_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + mdm_crit: mdm-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + mdm-dsp-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 7>; + + trips { + mdm_dsp_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + mdm_dsp_crit: mdm-dsp-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + npu-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 8>; + + trips { + npu_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + npu_crit: npu-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 9>; + + trips { + video_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + video_crit: video-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + + interrupts = , + , + , + ; + }; +}; From 21ba6fa92b19be7879b46776d155a46ac36d986a Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Fri, 21 Feb 2025 22:19:30 +0300 Subject: [PATCH 023/116] FROMLIST: dt-bindings: display: panel: samsung,ams581vf01: Add google,sunfish This panel is used in Google Pixel 4a (google,sunfish). Document the corresponding string. Signed-off-by: Danila Tikhonov --- .../bindings/display/panel/samsung,ams581vf01.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/panel/samsung,ams581vf01.yaml b/Documentation/devicetree/bindings/display/panel/samsung,ams581vf01.yaml index 70dff9c0ef2bec..a3a1de32d8be38 100644 --- a/Documentation/devicetree/bindings/display/panel/samsung,ams581vf01.yaml +++ b/Documentation/devicetree/bindings/display/panel/samsung,ams581vf01.yaml @@ -17,7 +17,13 @@ allOf: properties: compatible: - const: samsung,ams581vf01 + oneOf: + - enum: + - samsung,ams581vf01 + - items: + - enum: + - google,ams581vf01-sunfish + - const: samsung,ams581vf01 reg: maxItems: 1 From 6f4c96eb08a4b6357af386d7a78bd52d709eeaa4 Mon Sep 17 00:00:00 2001 From: Connor Mitchell Date: Sat, 8 Oct 2022 22:29:30 -0400 Subject: [PATCH 024/116] FROMLIST: arm64: dts: qcom: sm7150: Add device-tree for Google Pixel 4a Add device tree for the Google Pixel 4a (sunfish) smartphone. This device is based on Snapdragon 730G (sm7150) SoC. Signed-off-by: Connor Mitchell Co-developed-by: Danila Tikhonov Signed-off-by: Danila Tikhonov --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm7150-google-sunfish.dts | 901 ++++++++++++++++++ 2 files changed, 902 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm7150-google-sunfish.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4ba8e730641949..216f12b049f914 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -339,6 +339,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-curtana.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-joyeuse.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm7150-google-sunfish.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7325-nothing-spacewar.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb diff --git a/arch/arm64/boot/dts/qcom/sm7150-google-sunfish.dts b/arch/arm64/boot/dts/qcom/sm7150-google-sunfish.dts new file mode 100644 index 00000000000000..26298399dbdb03 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7150-google-sunfish.dts @@ -0,0 +1,901 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024, Connor Mitchell + * Copyright (c) 2025, Danila Tikhonov + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include + +#include "sm7150.dtsi" +#include "pm6150.dtsi" +#include "pm6150l.dtsi" + +/delete-node/ &mpss_mem; +/delete-node/ &venus_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &adsp_mem; +/delete-node/ &wlan_msa_mem; +/delete-node/ &npu_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &gpu_mem; + +/ { + model = "Google Pixel 4a"; + compatible = "google,sunfish", "qcom,sm7150"; + chassis-type = "handset"; + + aliases { + bluetooth0 = &bluetooth; + hsuart0 = &uart3; + serial0 = &uart8; + wifi0 = &wifi; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0:115200n8"; + + framebuffer@9c000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x9c000000 0x0 (1080 * 2340 * 4)>; + width = <1080>; + height = <2340>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&vol_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm6150l_gpios 2 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + reserved-memory { + mpss_mem: memory@8b000000 { + reg = <0x0 0x8b000000 0x0 0x9800000>; + no-map; + }; + + venus_mem: memory@94800000 { + reg = <0x0 0x94800000 0x0 0x500000>; + no-map; + }; + + cdsp_mem: memory@94d00000 { + reg = <0x0 0x94d00000 0x0 0x1e00000>; + no-map; + }; + + adsp_mem: memory@96b00000 { + reg = <0x00 0x96b00000 0x00 0x2200000>; + no-map; + }; + + wlan_msa_mem: memory@98d00000 { + reg = <0x0 0x98d00000 0x0 0x200000>; + no-map; + }; + + npu_mem: memory@98f00000 { + reg = <0x0 0x98f00000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: memory@98f80000 { + reg = <0x0 0x98f80000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: memory@98f90000 { + reg = <0x0 0x98f90000 0x0 0x5000>; + no-map; + }; + + gpu_mem: memory@98f95000 { + reg = <0x0 0x98f95000 0x0 0x2000>; + no-map; + }; + + cont_splash_mem: cont-splash@9c000000 { + reg = <0x0 0x9c000000 0x0 (1080 * 2340 * 4)>; + no-map; + }; + + ramoops_mem: ramoops@a481f000 { + compatible = "ramoops"; + reg = <0x0 0xa481f000 0x0 0x400000>; + + record-size = <0x40000>; + pmsg-size = <0x200000>; + console-size = <0x100000>; + }; + + rmtfs_mem: rmtfs@fde01000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xfde01000 0x0 0x600000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_ibb: regulator-ibb { + compatible = "regulator-fixed"; + + regulator-name = "ibb"; + regulator-min-microvolt = <6000000>; + regulator-max-microvolt = <6000000>; + }; + + vreg_lab: regulator-lab { + compatible = "regulator-fixed"; + + regulator-name = "lab"; + regulator-min-microvolt = <6100000>; + regulator-max-microvolt = <6100000>; + }; + + // S3A is really mx.lvl but it's there for supply map completeness sake. + vreg_s3a_0p8: regulator-smpa3 { + compatible = "regulator-fixed"; + + regulator-name = "vreg_s3a_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + + regulator-always-on; + vin-supply = <&vph_pwr>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm6150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + + vdd-l1-supply = <&vreg_s8c_1p2>; + vdd-l2-l3-supply = <&vreg_s4a_1p1>; + vdd-l4-l7-l8-supply = <&vreg_s4a_1p1>; + vdd-l5-l16-l17-l18-l19-supply = <&vreg_bob>; + vdd-l6-supply = <&vreg_s8c_1p2>; + vdd-l9-supply = <&vreg_s3a_0p8>; + vdd-l10-l14-l15-supply = <&vreg_s5a_2p0>; + vdd-l11-l12-l13-supply = <&vreg_s5a_2p0>; + + /* + * S1, S4, S5 are unused. + * S2-S3 and L7-L8 are ARCs: + * S2 - gfx.lvl, + * S3 - mx.lvl, + * L7 - lmx.lvl, + * L8 - lcx.lvl. + */ + + vreg_s4a_1p1: smps4 { + regulator-name = "vreg_s4a_1p1"; + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = ; + }; + + vreg_s5a_2p0: smps5 { + regulator-name = "vreg_s5a_2p0"; + regulator-min-microvolt = <1744000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = ; + }; + + vreg_l1a_1p2: ldo1 { + regulator-name = "vreg_l1a_1p2"; + regulator-min-microvolt = <1096000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l2a_1p0: ldo2 { + regulator-name = "vreg_l2a_1p0"; + regulator-min-microvolt = <944000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + }; + + vdda_pll_cc_ebi01: + vreg_l3a_1p0: ldo3 { + regulator-name = "vreg_l3a_1p0"; + regulator-min-microvolt = <968000>; + regulator-max-microvolt = <1064000>; + regulator-initial-mode = ; + }; + + vdd_qlink_lv: + vdd_qlink_lv_ck: + vdd_usb_hs_core: + vdda_mipi_csi0_0p9: + vdda_mipi_csi1_0p9: + vdda_mipi_csi2_0p9: + vdda_mipi_csi3_0p9: + vdda_mipi_dsi0_pll: + vdda_qrefs_0p9: + vdda_ufs_core: + vdda_usb_ss_dp_core: + vreg_l4a_0p88: ldo4 { + regulator-name = "vreg_l4a_0p88"; + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5a_2p7: ldo5 { + regulator-name = "vreg_l5a_2p7"; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l6a_1p2: ldo6 { + regulator-name = "vreg_l6a_1p2"; + regulator-min-microvolt = <1096000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vdd_wcss_cx: + vreg_l9a_0p8: ldo9 { + regulator-name = "vreg_l9a_0p8"; + regulator-min-microvolt = <624000>; + regulator-max-microvolt = <760000>; + regulator-initial-mode = ; + }; + + vddpx_3: + vreg_l10a_1p8: ldo10 { + regulator-name = "vreg_l10a_1p8"; + regulator-min-microvolt = <1720000>; + regulator-max-microvolt = <1832000>; + regulator-initial-mode = ; + }; + + vdd_qfprom: + vdda_apc1_cs_1p8: + vdda_qrefs_1p8: + vdda_usb_hs_1p8: + vddpx_11: + vreg_l11a_1p8: ldo11 { + regulator-name = "vreg_l11a_1p8"; + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1984000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1952000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l13a_1p8: ldo13 { + regulator-name = "vreg_l13a_1p8"; + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-name = "vreg_l14a_1p8"; + regulator-min-microvolt = <1720000>; + regulator-max-microvolt = <1856000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-name = "vreg_l15a_1p8"; + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p8: ldo16 { + regulator-name = "vreg_l16a_2p8"; + regulator-min-microvolt = <2424000>; + regulator-max-microvolt = <2976000>; + regulator-initial-mode = ; + }; + + vdda_usb_hs_3p1: + vreg_l17a_3p1: ldo17 { + regulator-name = "vreg_l17a_3p1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3232000>; + regulator-initial-mode = ; + }; + + vreg_l19a_2p85: ldo19 { + regulator-name = "vreg_l19a_2p85"; + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm6150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + + vdd-l2-l3-supply = <&vreg_s8c_1p2>; + vdd-l4-l5-l6-supply = <&vreg_bob>; + vdd-l7-l11-supply = <&vreg_bob>; + vdd-l9-l10-supply = <&vreg_bob>; + + vdd-bob-supply = <&vph_pwr>; + vdd-flash-supply = <&vreg_bob>; + vdd-rgb-supply = <&vreg_bob>; + + /* + * S4, S5 are unused. + * S2, S3, S7 are ARCs: + * S2-S3 - cx.lvl, + * S7 - mss.lvl. + */ + + vreg_s1c_1p13: smps1 { + regulator-name = "vreg_s1c_1p13"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_s8c_1p2: smps8 { + regulator-name = "vreg_s8c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1730000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1616000>; + regulator-max-microvolt = <1984000>; + regulator-initial-mode = ; + }; + + vdd_wcss_adc_dac: + vreg_l2c_1p3: ldo2 { + regulator-name = "vreg_l2c_1p3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + vdda_csi0_1p25: + vdda_csi1_1p25: + vdda_csi2_1p25: + vdda_csi3_1p25: + vdda_hv_ebi0: + vdda_mipi_dsi0_1p2: + vdda_ufs_1p2: + vdda_usb_ss_dp_1p2: + vddpx_10: + vreg_l3c_1p23: ldo3 { + regulator-name = "vreg_l3c_1p23"; + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vddpx_5: + vreg_l4c_1p8: ldo4 { + regulator-name = "vreg_l4c_1p8"; + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2950000>; + regulator-initial-mode = ; + }; + + vddpx_6: + vreg_l5c_1p8: ldo5 { + regulator-name = "vreg_l5c_1p8"; + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2950000>; + regulator-initial-mode = ; + }; + + vddpx_2: + vreg_l6c_3p0: ldo6 { + regulator-name = "vreg_l6c_3p0"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + vreg_l9c_3p1: ldo9 { + regulator-name = "vreg_l9c_3p1"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l10c_3p3: ldo10 { + regulator-name = "vreg_l10c_3p3"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-name = "vreg_l11c_3p3"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + regulator-allow-bypass; + }; + }; +}; + +&cci0 { + status = "okay"; +}; + +&cci1 { + status = "okay"; +}; + +&dispcc { + status = "okay"; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + zap-shader { + firmware-name = "qcom/sm7150/google/sunfish/a615_zap.mbn"; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + /* st21nfc nfc@8 */ + /* realtek,rt5514 codec@57 */ +}; + +&i2c7 { + status = "okay"; + clock-frequency = <1000000>; + + /* st,fts touchscreen@49 */ +}; + +&i2c9 { + status= "okay"; + clock-frequency = <400000>; + + /* microchip,pac1934 power-monitor@10 */ + /* cirrus,cs35l41 speaker-amp@40 */ + /* cirrus,cs35l41 speaker-amp@41 */ + + typec-mux@43 { + compatible = "fcs,fsa4480"; + reg = <0x43>; + + interrupts-extended = <&tlmm 42 IRQ_TYPE_LEVEL_LOW>; + + vcc-supply = <&vreg_bob>; + + mode-switch; + orientation-switch; + + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pm6150_typec_sbu_out>; + }; + }; + }; + + /* st,m24c08 e2prom@50 */ + /* ti,drv2624 haptic@5a */ + /* dlg,slg51000 pmic@75*/ +}; + +&ipa { + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sm7150/google/sunfish/ipa_fws.mbn"; + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vdda_mipi_dsi0_1p2>; + status = "okay"; + + panel: panel@0 { + compatible = "google,ams581vf01-sunfish", + "samsung,ams581vf01"; + reg = <0>; + + vddio-supply = <&vreg_l13a_1p8>; + vdd3p3-supply = <&vreg_l7c_3p0>; + vsn-supply = <&vreg_ibb>; + vsp-supply = <&vreg_lab>; + + reset-gpios = <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&lcd_reset_n>, + <&mdp_vsync_p>; + pinctrl-names = "default"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; + status = "okay"; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vdda_mipi_dsi0_pll>; + status = "okay"; +}; + +&pm6150_resin { + linux,code = ; + status = "okay"; +}; + +&pm6150_rtc { + status = "okay"; +}; + +&pm6150_typec { + vdd-vbus-supply = <&pm6150_vbus>; + vdd-pdphy-supply = <&vdda_usb_hs_3p1>; + status = "okay"; + + connector { + compatible = "usb-c-connector"; + + power-role = "source"; + data-role = "dual"; + self-powered; + + source-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pm6150_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + /* port@1 is for usb3 */ + + port@2 { + reg = <2>; + pm6150_typec_sbu_out: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; + }; + }; + }; + }; +}; + +&pm6150_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <3000000>; + status = "okay"; +}; + +&pm6150l_flash { + status = "okay"; + + led-1 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>; + led-max-microamp = <150000>; + flash-max-microamp = <1000000>; + flash-max-timeout-us = <1280000>; + }; +}; + +&pm6150l_gpios { + vol_up_n: vol-up-n-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-up; + power-source = <0>; + }; + + lcd_reset_n: lcd-reset-n-state { + pins = "gpio9"; + function = PMIC_GPIO_FUNC_FUNC1; + qcom,drive-strength = ; + bias-disable; + output-low; + power-source = <1>; + }; +}; + +&qfprom { + vcc-supply = <&vdd_qfprom>; +}; + +&qup_uart3_cts { + bias-pull-down; +}; + +&qup_uart3_rts { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart3_tx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart3_rx { + bias-pull-up; +}; + +&qup_uart8_tx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart8_rx { + drive-strength = <2>; + bias-pull-up; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm7150/google/sunfish/adsp.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm7150/google/sunfish/cdsp.mbn"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm7150/google/sunfish/modem.mbn"; + status = "okay"; +}; + +&spi0 { + status = "okay"; + + /* realtek,rt5514 codec@0 */ +}; + +&spi1 { + status = "okay"; + + /* google,citadel @ 0 */ + /* st,st54j_se @ 1 */ +}; + +&tlmm { + gpio-reserved-ranges = <59 4>; + + mdp_vsync_p: mdp-vsync-p-state { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_uart3_sleep: qup-uart3-sleep-state { + cts-pins { + pins = "gpio38"; + function = "gpio"; + bias-pull-down; + }; + + rts-pins { + pins = "gpio39"; + function = "gpio"; + bias-pull-down; + }; + + tx-pins { + pins = "gpio40"; + function = "gpio"; + bias-pull-up; + }; + + rx-pins { + pins = "gpio41"; + function = "gpio"; + bias-pull-up; + }; + }; +}; + +&uart3 { + /delete-property/interrupts; + interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 41 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-1 = <&qup_uart3_sleep>; + pinctrl-names = "default", + "sleep"; + + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_l10a_1p8>; + vddxo-supply = <&vreg_l1c_1p8>; + vddrf-supply = <&vdd_wcss_adc_dac>; + vddch0-supply = <&vreg_l10c_3p3>; + max-speed = <3200000>; + }; +}; + +&uart8 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l19a_2p85>; + vcc-max-microamp = <600000>; + vccq2-supply = <&vreg_l12a_1p8>; + vccq2-max-microamp = <600000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vdda_ufs_core>; + vdda-pll-supply = <&vdda_ufs_1p2>; + status = "okay"; +}; + +&usb_1 { + qcom,select-utmi-as-pipe-clk; + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "otg"; + usb-role-switch; + /* SM7150 doesn't support USB3 yet */ + maximum-speed = "high-speed"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pm6150_hs_in>; +}; + +&usb_1_hsphy { + vdd-supply = <&vdd_usb_hs_core>; + vdda-pll-supply = <&vdda_usb_hs_1p8>; + vdda-phy-dpdm-supply = <&vdda_usb_hs_3p1>; + status = "okay"; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&vdd_wcss_cx>; + vdd-1.8-xo-supply = <&vreg_l1c_1p8>; + vdd-1.3-rfa-supply = <&vdd_wcss_adc_dac>; + vdd-3.3-ch0-supply = <&vreg_l10c_3p3>; + vdd-3.3-ch1-supply = <&vreg_l11c_3p3>; + status = "okay"; +}; From 8a92e11e34680736b508591dbea5e8e3e85af4f0 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Sat, 24 Feb 2024 21:52:58 +0300 Subject: [PATCH 025/116] HACK: drm/msm/adreno: Add support for SM7150 SoC machine --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 550ff3a9b82e7e..0ab597340dca03 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -762,6 +762,7 @@ static const struct adreno_info a6xx_gpus[] = { .machine = "qcom,sm7150", .chip_ids = ADRENO_CHIP_IDS(0x06010800), .family = ADRENO_6XX_GEN1, + .revn = 618, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a630_gmu.bin", From 6c9c76bf35110039cad707629494d21755377cf0 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Mon, 13 Mar 2023 19:20:22 -0400 Subject: [PATCH 026/116] DOWNSTREAM: wifi: ath10k: make in-order rx amsdu buffers persistent The WCN3990 might split MSDUs among multiple "in-order" indications. The driver needs information from previous indications to handle MPDUs that are not started by the same indications that complete them. Move the list that tracks unprocessed MSDUs to the driver state so the driver can handle MPDUs that are split in this way and be less confused. Fixes: c545070e404b ("ath10k: implement rx reorder support") Signed-off-by: Richard Acayan --- drivers/net/wireless/ath/ath10k/htt.h | 4 +++ drivers/net/wireless/ath/ath10k/htt_rx.c | 45 +++++++++++++++++++----- 2 files changed, 40 insertions(+), 9 deletions(-) diff --git a/drivers/net/wireless/ath/ath10k/htt.h b/drivers/net/wireless/ath/ath10k/htt.h index 603f6de62b0a02..ec897175c93397 100644 --- a/drivers/net/wireless/ath/ath10k/htt.h +++ b/drivers/net/wireless/ath/ath10k/htt.h @@ -1929,6 +1929,10 @@ struct ath10k_htt { bool bundle_tx; struct sk_buff_head tx_req_head; struct sk_buff_head tx_complete_head; + + u8 rx_in_ord_split_tid; + u16 rx_in_ord_split_peer_id; + struct sk_buff_head rx_in_ord_split; }; struct ath10k_htt_tx_ops { diff --git a/drivers/net/wireless/ath/ath10k/htt_rx.c b/drivers/net/wireless/ath/ath10k/htt_rx.c index 25ab945fecef2c..54b5f68925c91f 100644 --- a/drivers/net/wireless/ath/ath10k/htt_rx.c +++ b/drivers/net/wireless/ath/ath10k/htt_rx.c @@ -297,6 +297,8 @@ void ath10k_htt_rx_free(struct ath10k_htt *htt) skb_queue_purge(&htt->rx_in_ord_compl_q); skb_queue_purge(&htt->tx_fetch_ind_q); + skb_queue_purge(&htt->rx_in_ord_split); + spin_lock_bh(&htt->rx_ring.lock); ath10k_htt_rx_ring_free(htt); spin_unlock_bh(&htt->rx_ring.lock); @@ -845,6 +847,8 @@ int ath10k_htt_rx_alloc(struct ath10k_htt *htt) skb_queue_head_init(&htt->tx_fetch_ind_q); atomic_set(&htt->num_mpdus_ready, 0); + skb_queue_head_init(&htt->rx_in_ord_split); + ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt rx ring size %d fill_level %d\n", htt->rx_ring.size, htt->rx_ring.fill_level); return 0; @@ -3162,6 +3166,10 @@ static int ath10k_htt_rx_extract_amsdu(struct ath10k_hw_params *hw, if (WARN_ON(!skb_queue_empty(amsdu))) return -EINVAL; + msdu = skb_peek(list); + rxd = HTT_RX_BUF_TO_RX_DESC(hw, + (void *)msdu->data - hw->rx_desc_ops->rx_desc_size); + while ((msdu = __skb_dequeue(list))) { __skb_queue_tail(amsdu, msdu); @@ -3263,7 +3271,6 @@ static int ath10k_htt_rx_in_ord_ind(struct ath10k *ar, struct sk_buff *skb) struct ath10k_htt *htt = &ar->htt; struct htt_resp *resp = (void *)skb->data; struct ieee80211_rx_status *status = &htt->rx_status; - struct sk_buff_head list; struct sk_buff_head amsdu; u16 peer_id; u16 msdu_count; @@ -3298,16 +3305,32 @@ static int ath10k_htt_rx_in_ord_ind(struct ath10k *ar, struct sk_buff *skb) return -EINVAL; } + if (!skb_queue_empty(&htt->rx_in_ord_split)) { + /* It might still be possible to handle this case if there is + * only one peer that splits at each given moment. We are + * bailing out because we should have a test case for this + * before trying to fix it. + */ + if (tid != htt->rx_in_ord_split_tid + || peer_id != htt->rx_in_ord_split_peer_id + || offload) { + ath10k_warn(ar, "split amsdu did not resume immediately\n"); + htt->rx_confused = true; + return -EIO; + } + } + /* The event can deliver more than 1 A-MSDU. Each A-MSDU is later * extracted and processed. + * + * It can also continue a previous A-MSDU. */ - __skb_queue_head_init(&list); if (ar->hw_params.target_64bit) ret = ath10k_htt_rx_pop_paddr64_list(htt, &resp->rx_in_ord_ind, - &list); + &htt->rx_in_ord_split); else ret = ath10k_htt_rx_pop_paddr32_list(htt, &resp->rx_in_ord_ind, - &list); + &htt->rx_in_ord_split); if (ret < 0) { ath10k_warn(ar, "failed to pop paddr list: %d\n", ret); @@ -3319,11 +3342,12 @@ static int ath10k_htt_rx_in_ord_ind(struct ath10k *ar, struct sk_buff *skb) * separately. */ if (offload) - ath10k_htt_rx_h_rx_offload(ar, &list); + ath10k_htt_rx_h_rx_offload(ar, &htt->rx_in_ord_split); - while (!skb_queue_empty(&list)) { + while (!skb_queue_empty(&htt->rx_in_ord_split)) { __skb_queue_head_init(&amsdu); - ret = ath10k_htt_rx_extract_amsdu(&ar->hw_params, &list, &amsdu); + ret = ath10k_htt_rx_extract_amsdu(&ar->hw_params, + &htt->rx_in_ord_split, &amsdu); switch (ret) { case 0: /* Note: The in-order indication may report interleaved @@ -3339,12 +3363,15 @@ static int ath10k_htt_rx_in_ord_ind(struct ath10k *ar, struct sk_buff *skb) ath10k_htt_rx_h_enqueue(ar, &amsdu, status); break; case -EAGAIN: - fallthrough; + htt->rx_in_ord_split_tid = tid; + htt->rx_in_ord_split_peer_id = peer_id; + + return -EIO; default: /* Should not happen. */ ath10k_warn(ar, "failed to extract amsdu: %d\n", ret); htt->rx_confused = true; - __skb_queue_purge(&list); + __skb_queue_purge(&htt->rx_in_ord_split); return -EIO; } } From c939e6d242621254791ac930eb53d3b25a9bf35b Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Thu, 7 Aug 2025 17:18:28 -0400 Subject: [PATCH 027/116] DOWNSTREAM: wifi: ath10k: only wait for response to SET_KEY When sending DELETE_KEY, the driver times out waiting for a response that doesn't come. Only wait for a response when sending SET_KEY. Sample dmesg: [ 117.285854] wlan0: deauthenticating from XX:XX:XX:XX:XX:XX by local choice (Reason: 3=DEAUTH_LEAVING) [ 120.302934] ath10k_snoc 18800000.wifi: failed to install key for vdev 0 peer XX:XX:XX:XX:XX:XX: -110 [ 120.302996] wlan0: failed to remove key (0, XX:XX:XX:XX:XX:XX) from hardware (-110) Signed-off-by: Richard Acayan --- drivers/net/wireless/ath/ath10k/mac.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/net/wireless/ath/ath10k/mac.c b/drivers/net/wireless/ath/ath10k/mac.c index 8e604697d6c20d..0558041e3697b8 100644 --- a/drivers/net/wireless/ath/ath10k/mac.c +++ b/drivers/net/wireless/ath/ath10k/mac.c @@ -324,9 +324,11 @@ static int ath10k_install_key(struct ath10k_vif *arvif, if (ret) return ret; - time_left = wait_for_completion_timeout(&ar->install_key_done, 3 * HZ); - if (time_left == 0) - return -ETIMEDOUT; + if (cmd != DISABLE_KEY) { + time_left = wait_for_completion_timeout(&ar->install_key_done, 3 * HZ); + if (time_left == 0) + return -ETIMEDOUT; + } return 0; } From 1a85cccfb2d8e74c267f2d027ef56219be12bb3a Mon Sep 17 00:00:00 2001 From: Jens Reidel Date: Thu, 18 Sep 2025 16:02:48 +0200 Subject: [PATCH 028/116] FROMLIST: dt-bindings: input: document Goodix GTX8 Touchscreen ICs Document the Goodix GT9886 and GT9896 which are part of the GTX8 series of Touchscreen controller ICs from Goodix. Signed-off-by: Jens Reidel --- .../input/touchscreen/goodix,gt9886.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/touchscreen/goodix,gt9886.yaml diff --git a/Documentation/devicetree/bindings/input/touchscreen/goodix,gt9886.yaml b/Documentation/devicetree/bindings/input/touchscreen/goodix,gt9886.yaml new file mode 100644 index 00000000000000..b1635032c81105 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/goodix,gt9886.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/goodix,gt9886.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Goodix GTX8 series touchscreen controller + +maintainers: + - Jens Reidel + +allOf: + - $ref: touchscreen.yaml# + +properties: + compatible: + enum: + - goodix,gt9886 + - goodix,gt9896 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + avdd-supply: + description: Analog power supply regulator on AVDD pin + + vddio-supply: + description: power supply regulator on VDDIO pin + + touchscreen-inverted-x: true + touchscreen-inverted-y: true + touchscreen-size-x: true + touchscreen-size-y: true + touchscreen-swapped-x-y: true + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - avdd-supply + - touchscreen-size-x + - touchscreen-size-y + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + touchscreen@5d { + compatible = "goodix,gt9886"; + reg = <0x5d>; + interrupt-parent = <&gpio>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + avdd-supply = <&ts_avdd>; + touchscreen-size-x = <1080>; + touchscreen-size-y = <2340>; + }; + }; + +... From ce0d8962f8746d444e41c707ee4f88ef208cfcda Mon Sep 17 00:00:00 2001 From: Jens Reidel Date: Thu, 18 Sep 2025 16:02:49 +0200 Subject: [PATCH 029/116] FROMLIST: Input: add support for Goodix GTX8 Touchscreen ICs Add initial support for the Goodix GTX8 touchscreen ICs. These ICs support SPI and I2C interfaces, up to 10 finger touch, stylus and gesture events. This driver is derived from the Goodix gtx8_driver_linux available at [1] and only supports the GT9886 and GT9896 ICs present in the Xiaomi Mi 9T and Xiaomi Redmi Note 10 Pro smartphones. The current implementation only supports Normandy and Yellowstone type ICs, aka only GT9886 and GT9896. It is also limited to I2C only, since I don't have a device with GTX8 over SPI at hand. Adding support for SPI should be fairly easy in the future, since the code uses a regmap. Support for advanced features like: - Firmware updates - Stylus events - Gesture events - Nanjing IC support is not included in current version. The current support requires a previously flashed firmware to be present. As I did not have access to datasheets for these ICs, I extracted the addresses from a couple of config files using a small tool [2]. The addresses are identical for the same IC families in all configs I observed, however not all of them make sense and I stubbed out firmware request support due to this. [1] https://github.com/goodix/gtx8_driver_linux [2] https://github.com/sm7150-mainline/goodix-cfg-bin Signed-off-by: Jens Reidel --- drivers/input/touchscreen/Kconfig | 15 + drivers/input/touchscreen/Makefile | 1 + drivers/input/touchscreen/goodix_gtx8.c | 562 ++++++++++++++++++++++++ drivers/input/touchscreen/goodix_gtx8.h | 137 ++++++ 4 files changed, 715 insertions(+) create mode 100644 drivers/input/touchscreen/goodix_gtx8.c create mode 100644 drivers/input/touchscreen/goodix_gtx8.h diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index aeaf9a9cbb416e..1f0a5b187970ec 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -429,6 +429,21 @@ config TOUCHSCREEN_GOODIX_BERLIN_SPI To compile this driver as a module, choose M here: the module will be called goodix_berlin_spi. +config TOUCHSCREEN_GOODIX_GTX8 + tristate "Goodix GTX8 touchscreen" + depends on I2C + select REGMAP_I2C + help + Say Y here if you have a Goodix GTX8 IC connected to + your system via I2C. This driver supports Normandy and + Yellowstone ICs like the GT9886 and GT9896. + They are commonly found in mobile phones. + + if unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called goodix_gtx8. + config TOUCHSCREEN_HIDEEP tristate "HiDeep Touch IC" depends on I2C diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile index f2b002abebe8a0..a2d4b1032e739f 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_TOUCHSCREEN_GOODIX) += goodix_ts.o obj-$(CONFIG_TOUCHSCREEN_GOODIX_BERLIN_CORE) += goodix_berlin_core.o obj-$(CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C) += goodix_berlin_i2c.o obj-$(CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI) += goodix_berlin_spi.o +obj-$(CONFIG_TOUCHSCREEN_GOODIX_GTX8) += goodix_gtx8.o obj-$(CONFIG_TOUCHSCREEN_HIDEEP) += hideep.o obj-$(CONFIG_TOUCHSCREEN_HIMAX_HX852X) += himax_hx852x.o obj-$(CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX) += hynitron_cstxxx.o diff --git a/drivers/input/touchscreen/goodix_gtx8.c b/drivers/input/touchscreen/goodix_gtx8.c new file mode 100644 index 00000000000000..bd2ccfc2c6919b --- /dev/null +++ b/drivers/input/touchscreen/goodix_gtx8.c @@ -0,0 +1,562 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Driver for Goodix GTX8 Touchscreens + * + * Copyright (c) 2019 - 2020 Goodix, Inc. + * Copyright (C) 2023 Linaro Ltd. + * Copyright (c) 2025 Jens Reidel + * + * Based on gtx8_driver_linux vendor driver and goodix_berlin kernel driver. + * + * The driver currently relies on the pre-flashed firmware and only supports + * Normandy / Yellowstone ICs. + * Pen support is also missing. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "goodix_gtx8.h" + +static const struct regmap_config goodix_gtx8_regmap_conf = { + .reg_bits = 16, + .val_bits = 8, + .max_raw_read = I2C_MAX_TRANSFER_SIZE, + .max_raw_write = I2C_MAX_TRANSFER_SIZE, +}; + +/* vendor & product left unassigned here, should probably be updated from fw info */ +static const struct input_id goodix_gtx8_input_id = { + .bustype = BUS_I2C, +}; + +static bool goodix_gtx8_checksum_valid_normandy(const u8 *data, int size) +{ + u8 cal_checksum = 0; + int i; + + if (size < GOODIX_GTX8_CHECKSUM_SIZE) + return false; + + for (i = 0; i < size; i++) + cal_checksum += data[i]; + + return cal_checksum == 0; +} + +static bool goodix_gtx8_checksum_valid_yellowstone(const u8 *data, int size) +{ + u16 cal_checksum = 0; + u16 r_checksum; + int i; + + if (size < GOODIX_GTX8_CHECKSUM_SIZE) + return false; + + for (i = 0; i < size - GOODIX_GTX8_CHECKSUM_SIZE; i++) + cal_checksum += data[i]; + + r_checksum = get_unaligned_be16(&data[i]); + + return cal_checksum == r_checksum; +} + +static int goodix_gtx8_get_remaining_contacts(struct goodix_gtx8_core *cd, + int n) +{ + size_t offset = cd->ic_data->header_size + GOODIX_GTX8_TOUCH_SIZE + + GOODIX_GTX8_CHECKSUM_SIZE; + u32 addr = cd->ic_data->touch_data_addr + offset; + int error; + + error = regmap_raw_read(cd->regmap, addr, &cd->event_buffer[offset], + (n - 1) * GOODIX_GTX8_TOUCH_SIZE); + if (error) { + dev_err_ratelimited(cd->dev, "failed to get touch data, %d\n", + error); + return error; + } + + return 0; +} + +static void goodix_gtx8_report_state(struct goodix_gtx8_core *cd, u8 touch_num, + union goodix_gtx8_touch *touch_data) +{ + union goodix_gtx8_touch *t; + int i; + u8 finger_id; + + for (i = 0; i < touch_num; i++) { + t = &touch_data[i]; + + if (cd->ic_data->ic_type == IC_TYPE_NORMANDY) { + input_mt_slot(cd->input_dev, t->normandy.finger_id); + input_mt_report_slot_state(cd->input_dev, + MT_TOOL_FINGER, true); + + touchscreen_report_pos(cd->input_dev, &cd->props, + __le16_to_cpu(t->normandy.x), + __le16_to_cpu(t->normandy.y), + true); + input_report_abs(cd->input_dev, ABS_MT_TOUCH_MAJOR, + t->normandy.w); + } else { + finger_id = FIELD_GET( + GOODIX_GTX8_FINGER_ID_MASK_YELLOWSTONE, + t->yellowstone.finger_id); + input_mt_slot(cd->input_dev, finger_id); + input_mt_report_slot_state(cd->input_dev, + MT_TOOL_FINGER, true); + + touchscreen_report_pos(cd->input_dev, &cd->props, + __be16_to_cpu(t->yellowstone.x), + __be16_to_cpu(t->yellowstone.y), + true); + input_report_abs(cd->input_dev, ABS_MT_TOUCH_MAJOR, + t->yellowstone.w); + } + } + + input_mt_sync_frame(cd->input_dev); + input_sync(cd->input_dev); +} + +static void goodix_gtx8_touch_handler(struct goodix_gtx8_core *cd, u8 touch_num, + union goodix_gtx8_touch *touch_data) +{ + int error; + + touch_num = FIELD_GET(GOODIX_GTX8_TOUCH_COUNT_MASK, touch_num); + + if (touch_num > GOODIX_GTX8_MAX_TOUCH) { + dev_warn(cd->dev, "invalid touch num %d\n", touch_num); + return; + } + + if (touch_num > 1) { + /* read additional contact data if more than 1 touch event */ + error = goodix_gtx8_get_remaining_contacts(cd, touch_num); + if (error) + return; + } + + if (touch_num) { + /* + * Normandy checksum is for the entire read buffer, + * Yellowstone is only for the touch data (since header + * has a separate checksum) + */ + if (cd->ic_data->ic_type == IC_TYPE_NORMANDY) { + int len = GOODIX_GTX8_HEADER_SIZE_NORMANDY + + touch_num * GOODIX_GTX8_TOUCH_SIZE + + GOODIX_GTX8_CHECKSUM_SIZE; + if (!goodix_gtx8_checksum_valid_normandy( + cd->event_buffer, len)) { + dev_err(cd->dev, + "touch data checksum error: %*ph\n", + len, cd->event_buffer); + return; + } + } else { + int len = touch_num * GOODIX_GTX8_TOUCH_SIZE + + GOODIX_GTX8_CHECKSUM_SIZE; + if (!goodix_gtx8_checksum_valid_yellowstone( + (u8 *)touch_data, len)) { + dev_err(cd->dev, + "touch data checksum error: %*ph\n", + len, (u8 *)touch_data); + return; + } + } + } + + goodix_gtx8_report_state(cd, touch_num, touch_data); +} + +static irqreturn_t goodix_gtx8_irq(int irq, void *data) +{ + struct goodix_gtx8_core *cd = data; + struct goodix_gtx8_event_normandy *ev_normandy; + struct goodix_gtx8_event_yellowstone *ev_yellowstone; + union goodix_gtx8_touch *touch_data; + int error; + u8 status, touch_num; + + error = regmap_raw_read( + cd->regmap, cd->ic_data->touch_data_addr, cd->event_buffer, + cd->ic_data->header_size + GOODIX_GTX8_TOUCH_SIZE + + GOODIX_GTX8_CHECKSUM_SIZE); + if (error) { + dev_warn_ratelimited( + cd->dev, "failed to get event head data: %d\n", error); + goto out; + } + + /* + * Both IC types have the same data in the header, just at different + * offsets + */ + if (cd->ic_data->ic_type == IC_TYPE_NORMANDY) { + ev_normandy = + (struct goodix_gtx8_event_normandy *)cd->event_buffer; + status = ev_normandy->hdr.status; + touch_num = ev_normandy->hdr.touch_num; + touch_data = (union goodix_gtx8_touch *)ev_normandy->data; + } else { + ev_yellowstone = (struct goodix_gtx8_event_yellowstone *) + cd->event_buffer; + status = ev_yellowstone->hdr.status; + touch_num = ev_yellowstone->hdr.touch_num; + touch_data = (union goodix_gtx8_touch *)ev_yellowstone->data; + } + + if (status == 0) + goto out; + + /* Yellowstone ICs have a checksum for the header */ + if (cd->ic_data->ic_type == IC_TYPE_YELLOWSTONE && + !goodix_gtx8_checksum_valid_yellowstone( + cd->event_buffer, GOODIX_GTX8_HEADER_SIZE_YELLOWSTONE)) { + dev_warn_ratelimited(cd->dev, + "touch head checksum error: %*ph\n", + (int)GOODIX_GTX8_HEADER_SIZE_YELLOWSTONE, + cd->event_buffer); + goto out_clear; + } + + if (status & GOODIX_GTX8_TOUCH_EVENT) + goodix_gtx8_touch_handler(cd, touch_num, touch_data); + + if (status & GOODIX_GTX8_REQUEST_EVENT) { + /* + * All configs seen so far either set the firmware request + * address to 0 (Normandy) or have it equal the touch data + * address (Yellowstone). Neither seems correct, and this + * is not testable. Therefore it is currently omitted. + */ + dev_dbg(cd->dev, "received request event, ignoring\n"); + } + +out_clear: + /* Clear up status field */ + regmap_write(cd->regmap, cd->ic_data->touch_data_addr, 0); + +out: + return IRQ_HANDLED; +} + +static int goodix_gtx8_input_dev_config(struct goodix_gtx8_core *cd) +{ + struct input_dev *input_dev; + int error; + + input_dev = devm_input_allocate_device(cd->dev); + if (!input_dev) + return -ENOMEM; + + cd->input_dev = input_dev; + input_set_drvdata(input_dev, cd); + + input_dev->name = "Goodix GTX8 Capacitive TouchScreen"; + input_dev->phys = "input/ts"; + + input_dev->id = goodix_gtx8_input_id; + + input_set_abs_params(cd->input_dev, ABS_MT_POSITION_X, 0, SZ_64K - 1, 0, + 0); + input_set_abs_params(cd->input_dev, ABS_MT_POSITION_Y, 0, SZ_64K - 1, 0, + 0); + input_set_abs_params(cd->input_dev, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0); + + touchscreen_parse_properties(cd->input_dev, true, &cd->props); + + error = input_mt_init_slots(cd->input_dev, GOODIX_GTX8_MAX_TOUCH, + INPUT_MT_DIRECT | INPUT_MT_DROP_UNUSED); + if (error) + return error; + + error = input_register_device(cd->input_dev); + if (error) + return error; + + return 0; +} + +static int goodix_gtx8_read_version(struct goodix_gtx8_core *cd) +{ + int error; + + /* + * The vendor driver reads a whole lot more data to calculate and + * verify a checksum. Without documentation, we don't know what + * most of that data is, so we only read the parts we know about + * and instead ensure their values are as expected + */ + error = regmap_raw_read(cd->regmap, cd->ic_data->fw_version_addr, + &cd->fw_version, sizeof(cd->fw_version)); + if (error) { + dev_err(cd->dev, "error reading fw version, %d\n", error); + return error; + } + + /* + * Since we don't verify the checksum, do a basic check that the + * product ID meets expectations + */ + if (memcmp(cd->fw_version.product_id, cd->ic_data->product_id, + sizeof(cd->fw_version.product_id))) { + dev_err(cd->dev, "unexpected product ID, got: %c%c%c%c\n", + cd->fw_version.product_id[0], + cd->fw_version.product_id[1], + cd->fw_version.product_id[2], + cd->fw_version.product_id[3]); + return -EINVAL; + } + + return 0; +} + +static int goodix_gtx8_dev_confirm(struct goodix_gtx8_core *cd) +{ + u8 rx_buf[1]; + int retry = 3; + int error; + + while (retry--) { + /* + * test_addr appears to always be the touch_data_addr for + * Normandy, but it doesn't really matter since all we + * need is a valid address + */ + error = regmap_raw_read(cd->regmap, + cd->ic_data->touch_data_addr, rx_buf, + sizeof(rx_buf)); + + if (!error) + return 0; + + usleep_range(5000, 5100); + } + + dev_err(cd->dev, "device confirm failed\n"); + + return -EINVAL; +} + +static int goodix_gtx8_power_on(struct goodix_gtx8_core *cd) +{ + int error; + + error = regulator_enable(cd->vddio); + if (error) { + dev_err(cd->dev, "Failed to enable VDDIO: %d\n", error); + return error; + } + + error = regulator_enable(cd->avdd); + if (error) { + dev_err(cd->dev, "Failed to enable AVDD: %d\n", error); + goto err_vddio_disable; + } + + /* Vendors usually configure the power on delay as 300ms */ + msleep(GOODIX_GTX8_POWER_ON_DELAY_MS); + + gpiod_set_value_cansleep(cd->reset_gpio, 0); + + /* Vendor waits 5ms for firmware to initialize */ + usleep_range(5000, 5100); + + error = goodix_gtx8_dev_confirm(cd); + if (error) + goto err_dev_reset; + + /* Vendor waits 100ms for firmware to fully boot */ + msleep(GOODIX_GTX8_NORMAL_RESET_DELAY_MS); + + return 0; + +err_dev_reset: + gpiod_set_value_cansleep(cd->reset_gpio, 1); + regulator_disable(cd->avdd); +err_vddio_disable: + regulator_disable(cd->vddio); + return error; +} + +static void goodix_gtx8_power_off(struct goodix_gtx8_core *cd) +{ + gpiod_set_value_cansleep(cd->reset_gpio, 1); + regulator_disable(cd->avdd); + regulator_disable(cd->vddio); +} + +static int goodix_gtx8_suspend(struct device *dev) +{ + struct goodix_gtx8_core *cd = dev_get_drvdata(dev); + + disable_irq(cd->irq); + goodix_gtx8_power_off(cd); + + return 0; +} + +static int goodix_gtx8_resume(struct device *dev) +{ + struct goodix_gtx8_core *cd = dev_get_drvdata(dev); + int error; + + error = goodix_gtx8_power_on(cd); + if (error) + return error; + + enable_irq(cd->irq); + + return 0; +} + +EXPORT_GPL_SIMPLE_DEV_PM_OPS(goodix_gtx8_pm_ops, goodix_gtx8_suspend, + goodix_gtx8_resume); + +static void goodix_gtx8_power_off_act(void *data) +{ + struct goodix_gtx8_core *cd = data; + + goodix_gtx8_power_off(cd); +} + +static int goodix_gtx8_probe(struct i2c_client *client) +{ + struct goodix_gtx8_core *cd; + struct regmap *regmap; + int error; + + cd = devm_kzalloc(&client->dev, sizeof(*cd), GFP_KERNEL); + if (!cd) + return -ENOMEM; + + regmap = devm_regmap_init_i2c(client, &goodix_gtx8_regmap_conf); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + cd->dev = &client->dev; + cd->irq = client->irq; + cd->regmap = regmap; + cd->ic_data = i2c_get_match_data(client); + + cd->event_buffer = + devm_kzalloc(cd->dev, cd->ic_data->event_size, GFP_KERNEL); + if (!cd->event_buffer) + return -ENOMEM; + + cd->reset_gpio = + devm_gpiod_get_optional(cd->dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(cd->reset_gpio)) + return dev_err_probe(cd->dev, PTR_ERR(cd->reset_gpio), + "Failed to request reset GPIO\n"); + + cd->avdd = devm_regulator_get(cd->dev, "avdd"); + if (IS_ERR(cd->avdd)) + return dev_err_probe(cd->dev, PTR_ERR(cd->avdd), + "Failed to request AVDD regulator\n"); + + cd->vddio = devm_regulator_get(cd->dev, "vddio"); + if (IS_ERR(cd->vddio)) + return dev_err_probe(cd->dev, PTR_ERR(cd->vddio), + "Failed to request VDDIO regulator\n"); + + error = goodix_gtx8_power_on(cd); + if (error) { + dev_err(cd->dev, "failed power on"); + return error; + } + + error = devm_add_action_or_reset(cd->dev, goodix_gtx8_power_off_act, + cd); + if (error) + return error; + + error = goodix_gtx8_read_version(cd); + if (error) { + dev_err(cd->dev, "failed to get version info"); + return error; + } + + error = goodix_gtx8_input_dev_config(cd); + if (error) { + dev_err(cd->dev, "failed to set input device"); + return error; + } + + error = devm_request_threaded_irq(cd->dev, cd->irq, NULL, + goodix_gtx8_irq, IRQF_ONESHOT, + "goodix-gtx8", cd); + if (error) { + dev_err(cd->dev, "request threaded IRQ failed: %d\n", error); + return error; + } + + dev_set_drvdata(cd->dev, cd); + + dev_dbg(cd->dev, + "Goodix GT%c%c%c%c Touchscreen Controller, Version %d.%d.%d.%d\n", + cd->fw_version.product_id[0], cd->fw_version.product_id[1], + cd->fw_version.product_id[2], cd->fw_version.product_id[3], + cd->fw_version.fw_version[0], cd->fw_version.fw_version[1], + cd->fw_version.fw_version[2], cd->fw_version.fw_version[3]); + + return 0; +} + +static const struct goodix_gtx8_ic_data gt9886_data = { + .event_size = GOODIX_GTX8_EVENT_SIZE_NORMANDY, + .fw_version_addr = GOODIX_GTX8_FW_VERSION_ADDR_NORMANDY, + .header_size = GOODIX_GTX8_HEADER_SIZE_NORMANDY, + .ic_type = IC_TYPE_NORMANDY, + .product_id = { '9', '8', '8', '6' }, + .touch_data_addr = GOODIX_GTX8_TOUCH_DATA_ADDR_NORMANDY, +}; + +static const struct goodix_gtx8_ic_data gt9896_data = { + .event_size = GOODIX_GTX8_EVENT_SIZE_YELLOWSTONE, + .fw_version_addr = GOODIX_GTX8_FW_VERSION_ADDR_YELLOWSTONE, + .header_size = GOODIX_GTX8_HEADER_SIZE_YELLOWSTONE, + .ic_type = IC_TYPE_YELLOWSTONE, + .product_id = { '9', '8', '9', '6' }, + .touch_data_addr = GOODIX_GTX8_TOUCH_DATA_ADDR_YELLOWSTONE, +}; + +static const struct i2c_device_id goodix_gtx8_i2c_id[] = { + { .name = "gt9886", .driver_data = (long)>9886_data }, + { .name = "gt9896", .driver_data = (long)>9896_data }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, goodix_gtx8_i2c_id); + +static const struct of_device_id goodix_gtx8_of_match[] = { + { .compatible = "goodix,gt9886", .data = >9886_data }, + { .compatible = "goodix,gt9896", .data = >9896_data }, + {}, +}; +MODULE_DEVICE_TABLE(of, goodix_gtx8_of_match); + +static struct i2c_driver goodix_gtx8_driver = { + .probe = goodix_gtx8_probe, + .id_table = goodix_gtx8_i2c_id, + .driver = { + .name = "goodix-gtx8", + .of_match_table = of_match_ptr(goodix_gtx8_of_match), + .pm = pm_sleep_ptr(&goodix_gtx8_pm_ops), + }, +}; +module_i2c_driver(goodix_gtx8_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Goodix GTX8 Touchscreen driver"); +MODULE_AUTHOR("Jens Reidel "); diff --git a/drivers/input/touchscreen/goodix_gtx8.h b/drivers/input/touchscreen/goodix_gtx8.h new file mode 100644 index 00000000000000..79e79988869b46 --- /dev/null +++ b/drivers/input/touchscreen/goodix_gtx8.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __GOODIX_GTX8_H__ +#define __GOODIX_GTX8_H__ + +#define GOODIX_GTX8_NORMAL_RESET_DELAY_MS 100 +#define GOODIX_GTX8_POWER_ON_DELAY_MS 300 + +#define GOODIX_GTX8_TOUCH_EVENT BIT(7) +#define GOODIX_GTX8_REQUEST_EVENT BIT(6) +#define GOODIX_GTX8_TOUCH_COUNT_MASK GENMASK(3, 0) +#define GOODIX_GTX8_FINGER_ID_MASK_YELLOWSTONE GENMASK(7, 4) + +#define GOODIX_GTX8_MAX_TOUCH 10 +#define GOODIX_GTX8_CHECKSUM_SIZE sizeof(u16) + +#define GOODIX_GTX8_FW_VERSION_ADDR_NORMANDY 0x4535 +#define GOODIX_GTX8_FW_VERSION_ADDR_YELLOWSTONE 0x4022 +#define GOODIX_GTX8_TOUCH_DATA_ADDR_NORMANDY 0x4100 +#define GOODIX_GTX8_TOUCH_DATA_ADDR_YELLOWSTONE 0x4180 + +#define I2C_MAX_TRANSFER_SIZE 256 + +enum goodix_gtx8_ic_type { + IC_TYPE_NORMANDY, + IC_TYPE_YELLOWSTONE, +}; + +struct goodix_gtx8_ic_data { + size_t event_size; + /* + * This is technically not the firmware version address + * referenced in the vendor driver, but rather the + * address of the product ID part. The meaning of the + * other parts is unknown and they are therefore omitted + * for now. + */ + int fw_version_addr; + size_t header_size; + enum goodix_gtx8_ic_type ic_type; + char product_id[4]; + int touch_data_addr; +}; + +struct goodix_gtx8_header_normandy { + u8 status; + /* Only the lower 4 bits are actually used */ + u8 touch_num; +}; +#define GOODIX_GTX8_HEADER_SIZE_NORMANDY \ + sizeof(struct goodix_gtx8_header_normandy) + +struct goodix_gtx8_header_yellowstone { + u8 status; + /* Most likely unused */ + u8 __unknown1; + /* Only the lower 4 bits are actually used */ + u8 touch_num; + /* Most likely unused */ + u8 __unknown2[3]; + __le16 checksum; +} __packed __aligned(1); +#define GOODIX_GTX8_HEADER_SIZE_YELLOWSTONE \ + sizeof(struct goodix_gtx8_header_yellowstone) + +struct goodix_gtx8_touch_normandy { + u8 finger_id; + __le16 x; + __le16 y; + u8 w; + u8 __unknown[2]; +} __packed __aligned(1); + +struct goodix_gtx8_touch_yellowstone { + /* + * Only the upper 4 bits are used, lower 4 bits are + * probably the sensor ID. + */ + u8 finger_id; + u8 __unknown1; + __be16 x; + __be16 y; + /* + * Vendor driver claims that this is a single __be16, + * but testing shows that it likely isn't. + */ + u8 __unknown2; + u8 w; +} __packed __aligned(1); + +union goodix_gtx8_touch { + struct goodix_gtx8_touch_normandy normandy; + struct goodix_gtx8_touch_yellowstone yellowstone; +}; +#define GOODIX_GTX8_TOUCH_SIZE sizeof(union goodix_gtx8_touch) + +struct goodix_gtx8_event_normandy { + struct goodix_gtx8_header_normandy hdr; + /* The data below is u16 aligned */ + u8 data[GOODIX_GTX8_TOUCH_SIZE * GOODIX_GTX8_MAX_TOUCH + + GOODIX_GTX8_CHECKSUM_SIZE]; +}; +#define GOODIX_GTX8_EVENT_SIZE_NORMANDY \ + sizeof(struct goodix_gtx8_event_normandy) + +struct goodix_gtx8_event_yellowstone { + struct goodix_gtx8_header_yellowstone hdr; + /* The data below is u16 aligned */ + u8 data[GOODIX_GTX8_TOUCH_SIZE * GOODIX_GTX8_MAX_TOUCH + + GOODIX_GTX8_CHECKSUM_SIZE]; +}; +#define GOODIX_GTX8_EVENT_SIZE_YELLOWSTONE \ + sizeof(struct goodix_gtx8_event_yellowstone) + +struct goodix_gtx8_fw_version { + /* 4 digits IC number */ + char product_id[4]; + /* Most likely unused */ + u8 __unknown[4]; + /* Four components version number */ + u8 fw_version[4]; +}; + +struct goodix_gtx8_core { + struct device *dev; + struct regmap *regmap; + struct regulator *avdd; + struct regulator *vddio; + struct gpio_desc *reset_gpio; + struct touchscreen_properties props; + struct goodix_gtx8_fw_version fw_version; + struct input_dev *input_dev; + int irq; + const struct goodix_gtx8_ic_data *ic_data; + u8 *event_buffer; +}; + +#endif From fdcec73bd930c7dbd6c70b7f693e302cd046a075 Mon Sep 17 00:00:00 2001 From: Jens Reidel Date: Thu, 18 Sep 2025 16:02:50 +0200 Subject: [PATCH 030/116] FROMLIST: MAINTAINERS: add an entry for Goodix GTX8 Touchscreen driver Add MAINTAINERS entry for the Goodix GTX8 Touchscreen IC driver. Signed-off-by: Jens Reidel --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b2040011a38659..9cad9aba213a98 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10919,6 +10919,13 @@ M: Maud Spierings S: Maintained F: Documentation/devicetree/bindings/connector/gocontroll,moduline-module-slot.yaml +GOODIX GTX8 TOUCHSCREEN +M: Jens Reidel +L: linux-input@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/input/touchscreen/goodix,gt9886.yaml +F: drivers/input/touchscreen/goodix_gtx8* + GOODIX TOUCHSCREEN M: Hans de Goede L: linux-input@vger.kernel.org From 12474e10f7357ab3d636f8ec61a544a03c9803a8 Mon Sep 17 00:00:00 2001 From: Jens Reidel Date: Tue, 9 Dec 2025 14:04:27 +0100 Subject: [PATCH 031/116] iommu/arm-smmu-qcom: add actlr settings for mdss on SM7150 Signed-off-by: Jens Reidel --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index edd41b5a3b6ac2..0a8de073fdce84 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -59,6 +59,8 @@ static const struct of_device_id qcom_smmu_actlr_client_of_match[] = { .data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, { .compatible = "qcom,sm6350-mdss", .data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, + { .compatible = "qcom,sm7150-mdss", + .data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, { .compatible = "qcom,sm8150-mdss", .data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, { .compatible = "qcom,sm8250-mdss", From bcba28c72ccfd943759e0e0c7b851d9b904d9ab7 Mon Sep 17 00:00:00 2001 From: Jens Reidel Date: Tue, 15 Apr 2025 21:47:22 +0200 Subject: [PATCH 032/116] ufs: qcom: Add some missing frequency to gear mappings Signed-off-by: Jens Reidel --- drivers/ufs/host/ufs-qcom.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index bc037db46624ad..e18bd762ba7e53 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -2491,7 +2491,9 @@ static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq) case 300000000: gear = UFS_HS_G4; break; + case 240000000: case 201500000: + case 200000000: gear = UFS_HS_G3; break; case 150000000: @@ -2499,6 +2501,7 @@ static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq) gear = UFS_HS_G2; break; case 75000000: + case 50000000: case 37500000: gear = UFS_HS_G1; break; From ef5c6e3f32d6315e118ddf4ab044761fe9b6b158 Mon Sep 17 00:00:00 2001 From: David Wronek Date: Sat, 28 May 2022 08:18:35 +0200 Subject: [PATCH 033/116] drm: panel: Generate huaxing-nt36672c driver Signed-off-by: David Wronek --- drivers/gpu/drm/panel/Kconfig | 10 + drivers/gpu/drm/panel/Makefile | 1 + .../gpu/drm/panel/panel-huaxing-nt36672c.c | 341 ++++++++++++++++++ 3 files changed, 352 insertions(+) create mode 100644 drivers/gpu/drm/panel/panel-huaxing-nt36672c.c diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index d592f4f4b939a9..dcc130dcfaf142 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -227,6 +227,16 @@ config DRM_PANEL_HIMAX_HX8394 If M is selected the module will be called panel-himax-hx8394. +config DRM_PANEL_HUAXING_NT36672C + tristate "Huaxing FHD panel with NT36672C controller" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + select VIDEOMODE_HELPERS + help + Say Y or M here if you want to enable support for the Huaxing FHD + (2400x1080@120Hz) video mode panel. + config DRM_PANEL_HYDIS_HV101HD1 tristate "Hydis HV101HD1 panel" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index a4291dc3905bed..f0bf1581ca43a3 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_DRM_PANEL_HIMAX_HX83112A) += panel-himax-hx83112a.o obj-$(CONFIG_DRM_PANEL_HIMAX_HX83112B) += panel-himax-hx83112b.o obj-$(CONFIG_DRM_PANEL_HIMAX_HX83121A) += panel-himax-hx83121a.o obj-$(CONFIG_DRM_PANEL_HIMAX_HX8394) += panel-himax-hx8394.o +obj-$(CONFIG_DRM_PANEL_HUAXING_NT36672C) += panel-huaxing-nt36672c.o obj-$(CONFIG_DRM_PANEL_HYDIS_HV101HD1) += panel-hydis-hv101hd1.o obj-$(CONFIG_DRM_PANEL_ILITEK_IL9322) += panel-ilitek-ili9322.o obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9341) += panel-ilitek-ili9341.o diff --git a/drivers/gpu/drm/panel/panel-huaxing-nt36672c.c b/drivers/gpu/drm/panel/panel-huaxing-nt36672c.c new file mode 100644 index 00000000000000..428ee60e31b9c9 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-huaxing-nt36672c.c @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) 2025 FIXME +// Generated with linux-mdss-dsi-panel-driver-generator from vendor device tree: +// Copyright (c) 2013, The Linux Foundation. All rights reserved. (FIXME) + +#include +#include +#include +#include +#include + +#include