From 0f5814acdcc8ada0d85da02e5c4be28740791fc7 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 14 May 2026 21:03:34 -0700 Subject: [PATCH 01/10] AxiLiteCrossbarI2cMux: deselect MUX channels between transactions Each AXIL transaction previously wrote a single byte to the I2C MUX channel-select register and assumed the device would atomically replace the prior channel. On the BittWare XUP-VV8 this leaves enough sticky state on TCA9548 channels 5 and 7 (QSFP slots 1 and 3) that the second I2C transaction targeting those slots returns RESP=2 SLVERR and every subsequent access cascades. Channels 4 and 6 (slots 0, 2) happen to tolerate the same sequence, which made the failure look QSFP+ specific when the actual differential is the TCA9548 channel mask. Insert an explicit deselect-all write (0x00) before the channel-select write. 0x00 is the documented "no channel selected" state for every device in I2cMuxPkg.vhd (TCA9548, PCA9547, PCA9544A, PCA9546A, PCA9540B), so the fix applies uniformly regardless of which decode map is used. Two new states are added to the existing FSM: DESELECT_S - waits for the 0x00 write to ack, then loads the saved target channel mask and pulses i2cRstL low again. MUX_RST_S - mirrors RST_S but transitions straight to MUX_S so the deselect path does not re-enter DESELECT_S. The chanMask record field carries the target channel mask through the deselect-write phase. Flow is now: IDLE_S -> RST_S -> DESELECT_S -> MUX_RST_S -> MUX_S -> XBAR_S -> IDLE_S Validated on a BittWare XUP-VV8 (VU13P) with QSFP28 in slot 0 and QSFP+ modules in slots 1, 2, 3: Before: slots 1 and 3 fail every transaction after the first one; Qsfp[1].ReadDevice() cascades into hundreds of SLVERRs. After: 300/300 ok on every slot in a sustained burst (~940 txn/s), Qsfp[i].ReadDevice() succeeds on all 4 slots, ErrorCount = 0. The change is additive for existing surf users - the deselect step is a single extra I2C byte write per AXIL transaction and gives every MUX-fronted bus the same clean channel-select handshake regardless of whether the previous downstream device left the bus in a marginal state. --- protocols/i2c/axi/AxiLiteCrossbarI2cMux.vhd | 81 +++++++++++++++++++-- 1 file changed, 75 insertions(+), 6 deletions(-) diff --git a/protocols/i2c/axi/AxiLiteCrossbarI2cMux.vhd b/protocols/i2c/axi/AxiLiteCrossbarI2cMux.vhd index 0a790fa9a0..e744474585 100644 --- a/protocols/i2c/axi/AxiLiteCrossbarI2cMux.vhd +++ b/protocols/i2c/axi/AxiLiteCrossbarI2cMux.vhd @@ -91,6 +91,8 @@ architecture mapping of AxiLiteCrossbarI2cMux is type StateType is ( IDLE_S, RST_S, + DESELECT_S, + MUX_RST_S, MUX_S, XBAR_S); @@ -98,6 +100,7 @@ architecture mapping of AxiLiteCrossbarI2cMux is cnt : natural range 0 to FILTER_C; i2cRstL : sl; rnw : sl; + chanMask : slv(7 downto 0); axilReadSlave : AxiLiteReadSlaveType; axilWriteSlave : AxiLiteWriteSlaveType; i2cRegMasterIn : I2cRegMasterInType; @@ -109,6 +112,7 @@ architecture mapping of AxiLiteCrossbarI2cMux is cnt => 0, i2cRstL => '1', rnw => '0', + chanMask => (others => '0'), axilReadSlave => AXI_LITE_READ_SLAVE_INIT_C, axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C, i2cRegMasterIn => I2C_MUX_INIT_C, @@ -216,8 +220,9 @@ begin v.i2cRstL := '0'; v.rnw := '0'; - -- Setup the I2C MUX - v.i2cRegMasterIn.regWrData(7 downto 0) := MUX_DECODE_MAP_G(wrIdx); + -- Save the target channel mask; deselect step writes 0x00 first + v.chanMask := MUX_DECODE_MAP_G(wrIdx); + v.i2cRegMasterIn.regWrData(7 downto 0) := (others => '0'); -- Next state v.state := RST_S; @@ -229,8 +234,9 @@ begin v.i2cRstL := '0'; v.rnw := '1'; - -- Setup the I2C MUX - v.i2cRegMasterIn.regWrData(7 downto 0) := MUX_DECODE_MAP_G(rdIdx); + -- Save the target channel mask; deselect step writes 0x00 first + v.chanMask := MUX_DECODE_MAP_G(rdIdx); + v.i2cRegMasterIn.regWrData(7 downto 0) := (others => '0'); -- Next state v.state := RST_S; @@ -249,17 +255,80 @@ begin -- Reset the flag v.i2cRstL := '1'; - -- Start the I2C transaction + -- Start the I2C transaction (deselect-all write = 0x00 already loaded) v.i2cRegMasterIn.regReq := '1'; + -- Write 0x00 first to deselect all channels, then write the + -- target channel mask, to avoid the previous channel sticking + -- if the channel-select write is short or marginal. + -- Next state - v.state := MUX_S; + v.state := DESELECT_S; else -- Increment the counter v.cnt := r.cnt + 1; end if; ---------------------------------------------------------------------- + when DESELECT_S => + -- Wait for the deselect (0x00) I2C write to ack + if (i2cRegMasterOut.regAck = '1' and r.i2cRegMasterIn.regReq = '1') then + + -- Reset the flag + v.i2cRegMasterIn.regReq := '0'; + + -- If the deselect write itself failed, surface the error and abort + if (i2cRegMasterOut.regFail = '1') then + + if (r.rnw = '0') then + axiSlaveWriteResponse(v.axilWriteSlave, AXI_RESP_SLVERR_C); + else + v.axilReadSlave.rData := x"000000" & i2cRegMasterOut.regFailCode; + axiSlaveReadResponse(v.axilReadSlave, AXI_RESP_SLVERR_C); + end if; + + -- Next state + v.state := IDLE_S; + + else + + -- Load the actual target channel mask for the next I2C write, + -- then route through MUX_RST_S to get the proper i2cRstL pulse + -- and a clean regReq 0->1 transition. MUX_RST_S mirrors RST_S + -- but transitions straight to MUX_S without re-entering + -- DESELECT_S (which would be an infinite loop). + v.i2cRstL := '0'; + v.i2cRegMasterIn.regWrData(7 downto 0) := r.chanMask; + + -- Next state + v.state := MUX_RST_S; + + end if; + + end if; + ---------------------------------------------------------------------- + when MUX_RST_S => + -- Symmetric to RST_S, but transitions directly to MUX_S after the + -- reset pulse. Used after DESELECT_S to give I2cRegMaster a clean + -- handshake (regReq falling+rising edge plus i2cRstL pulse) before + -- issuing the channel-select write. + if (r.cnt = FILTER_C) then + + v.cnt := 0; + + v.i2cRstL := '1'; + + -- Start the channel-select I2C transaction (data already loaded + -- with r.chanMask by DESELECT_S). + v.i2cRegMasterIn.regReq := '1'; + + -- Next state + v.state := MUX_S; + + else + v.cnt := r.cnt + 1; + end if; + ---------------------------------------------------------------------- when MUX_S => -- Wait for DONE to set if (i2cRegMasterOut.regAck = '1' and r.i2cRegMasterIn.regReq = '1') then From 5164d3720388c0ac64be018e4698636511ee466c Mon Sep 17 00:00:00 2001 From: Dawood Alnajjar Date: Fri, 15 May 2026 16:37:15 -0700 Subject: [PATCH 02/10] Removed redundant description attribute causing software to fail --- python/surf/protocols/htsp/_HtspAxiL.py | 4 ---- 1 file changed, 4 deletions(-) diff --git a/python/surf/protocols/htsp/_HtspAxiL.py b/python/surf/protocols/htsp/_HtspAxiL.py index 39e576dec0..2639a3a0f5 100644 --- a/python/surf/protocols/htsp/_HtspAxiL.py +++ b/python/surf/protocols/htsp/_HtspAxiL.py @@ -285,7 +285,6 @@ def __init__(self, def addStatusCountVar(**ecvkwargs): self.add(pr.RemoteVariable( - description = 'Status count', bitSize = statusCountBits, mode = 'RO', disp = '{:d}', @@ -294,7 +293,6 @@ def addStatusCountVar(**ecvkwargs): def addErrorCountVar(**ecvkwargs): self.add(pr.RemoteVariable( - description = 'Error count', bitSize = errorCountBits, mode = 'RO', disp = '{:d}', @@ -477,7 +475,6 @@ def __init__(self, def addStatusCountVar(**ecvkwargs): self.add(pr.RemoteVariable( - description = 'Status count', bitSize = statusCountBits, mode = 'RO', disp = '{:d}', @@ -486,7 +483,6 @@ def addStatusCountVar(**ecvkwargs): def addErrorCountVar(**ecvkwargs): self.add(pr.RemoteVariable( - description = 'Error count', bitSize = errorCountBits, mode = 'RO', disp = '{:d}', From 2869a21bcbdd49ca0839921c0f6adcfb4ae8094f Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 15 May 2026 21:40:40 -0700 Subject: [PATCH 03/10] Typo cleanup: Python descriptions/comments and VHDL comments Post-PR #1421 cleanup pass focused on English-word typos in user-facing prose, plus one small kwargs-collision fix retained from the original audit. No behavioural change. Net changes: 143 files, +237/-237 lines. Python typos -- 24 files, 39 fixes Audited every .py under python/ and tests/ via 6 parallel review passes. tests/ was clean. Highlights: analog_devices/_Adt7420.py Analod Deviced -> Analog Devices analog_devices/_Ad9249.py Regsisters -> Registers analog_devices/_Ad9249.py Compliment -> Complement silabs/_Si5{324,326,5345Lite,5394Lite}.py conflagration -> configuration silabs/_Si5345Pages.py Ready Only -> Read Only ti/_Ads54J54.py dcimation -> decimation ti/_Lmk61e2.py retreived -> retrieved xilinx/_AxiSysMonUltraScale.py Managment -> Management xilinx/_AxiSysMonUltraScale.py defatul -> default protocols/jesd204b/_JesdRx.py / _JesdTx.py brake/missaligned/Indicades/undeflow/funtionality/ checkes/re-syncronisations -> fixed British spellings (synchronised, re-synchronisations) preserved where already used. VHDL typos -- 119 files, 197 fixes Audited every .vhd under axi/, base/, devices/, dsp/, ethernet/, protocols/, and xilinx/ via 8 parallel review passes (1146 files total). Only -- comment text was touched. No signal, port, process, entity, generic, or component names were renamed; no string literals in report/assert statements were modified. Most prevalent (boilerplate copy-paste families): 7Series GT clones (gtx7/gth7/gtp7) sucessfully -> successfully (x9) Tranceiver -> Transceiver (x3) PGP Axi banners Errror -> Error (x6) pgp2b/pgp2fc/pgp3 *Pkg / *RxPhy / *RxCell occured -> occurred (x10) XauiCore wrappers adn -> and (x16 in repeated boilerplate) AD9249/AD9681 readout primatives/primative/curDealy -> primitives/primitive/curDelay xvc-udp JTAG paylod/paralle/the the -> fixed Real-English-word substitutions verified per occurrence (not bulk-replaced): weather->whether, it->if, na->and, od->of, got->go, dessert->deassert, rests->resets, with->without, read->ready, an->and, save->same, though->through, knowns->knows, incase->in case, to to->to, the the->the, Interfac e->Interface Pre-flight verified that every misspelled string only appears in -- comment lines (never as an identifier or in code) before any bulk substitution. British spellings preserved. AdcTester kwargs fix -- 1 file The only kwarg-hardening change retained from the post-PR #1421 audit: python/surf/devices/analog_devices/_Ad9249.py AdcTester.__init__ accepts description as a named parameter, eliminating the TypeError: got multiple values for keyword argument 'description' when a caller passes description=. The other 8 wrappers identified in the original audit (AxiMonAxiL, Ltm4664, Si5345, Si5394, PhantomS711, PMBus, Pgp3AxiL, Pgp4AxiL) were prepared but reverted; they remain at their pre-release shape. Verification: python -m compileall -f python/ -- clean flake8 --count python/ -- 0 scripts/vsg_linter.sh -- No issues found cocotb regression suite NOT run locally; it requires the make MODULES=$PWD import HDL pipeline only available in CI. --- axi/axi-lite/rtl/AxiLitePkg.vhd | 2 +- axi/axi-lite/rtl/AxiLiteSequencerRam.vhd | 2 +- .../AxiStreamFifoV2IpIntegrator.vhd | 2 +- axi/axi-stream/rtl/AxiStreamBatchingFifo.vhd | 2 +- axi/axi-stream/rtl/AxiStreamCompact.vhd | 2 +- axi/axi-stream/rtl/AxiStreamConcat.vhd | 2 +- axi/axi-stream/rtl/AxiStreamFifoV2.vhd | 6 +++--- axi/axi-stream/rtl/AxiStreamFlush.vhd | 2 +- axi/axi-stream/rtl/AxiStreamGearbox.vhd | 2 +- axi/axi-stream/rtl/AxiStreamMux.vhd | 4 ++-- axi/axi-stream/rtl/AxiStreamResize.vhd | 2 +- axi/axi-stream/tb/AxiStreamBatchingFifoTb.vhd | 2 +- axi/axi4/rtl/AxiReadEmulate.vhd | 2 +- axi/axi4/rtl/AxiReadPathMux.vhd | 2 +- axi/axi4/rtl/AxiWritePathMux.vhd | 4 ++-- axi/axi4/tb/AxiRingBufferTb.vhd | 2 +- axi/dma/rtl/v1/AxiStreamDmaWrite.vhd | 2 +- axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd | 2 +- base/general/rtl/TextUtilPkg.vhd | 2 +- base/ram/xilinx/SinglePortRamPrimitive.vhd | 2 +- .../ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd | 6 +++--- .../ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd | 8 ++++---- .../UltraScale/rtl/Ad9249ReadoutGroup2.vhd | 2 +- .../ad9681/7Series/rtl/Ad9681ReadoutManual.vhd | 4 ++-- devices/Linear/lct2270/rtl/AxiLtc2270Reg.vhd | 2 +- devices/Microchip/sy89297/rtl/Sy89297.vhd | 4 ++-- devices/Silabs/si5345/rtl/Si5345.vhd | 2 +- devices/Ti/adc32rf45/rtl/adc32rf45.vhd | 2 +- devices/Ti/ads54j60/rtl/ads54j60.vhd | 2 +- dsp/xilinx/fixed/CfixedMult.vhd | 2 +- dsp/xilinx/fixed/CfixedMultAdd.vhd | 2 +- dsp/xilinx/fixed/SinCosTaylor.vhd | 2 +- ethernet/EthMacCore/rtl/EthMacRxImportXgmii.vhd | 4 ++-- ethernet/EthMacCore/rtl/EthMacTop.vhd | 2 +- ethernet/EthMacCore/rtl/EthMacTxExportGmii.vhd | 2 +- ethernet/EthMacCore/rtl/EthMacTxExportXgmii.vhd | 2 +- .../GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd | 2 +- ethernet/RoCEv2/rtl/RoceResizeAndSwap.vhd | 2 +- ethernet/XauiCore/gth7/rtl/XauiGth7Core.vhd | 16 ++++++++-------- ethernet/XauiCore/gtx7/rtl/XauiGtx7Core.vhd | 16 ++++++++-------- .../batcher/rtl/AxiStreamBatcherEventBuilder.vhd | 2 +- protocols/coaxpress/core/rtl/CoaXPressConfig.vhd | 2 +- .../rtl/EventFrameSequencerDemux.vhd | 6 +++--- .../rtl/EventFrameSequencerMux.vhd | 2 +- protocols/glink/gtx7/rtl/GLinkGtx7RxRst.vhd | 2 +- protocols/htsp/core/rtl/HtspAxiL.vhd | 2 +- protocols/htsp/core/rtl/HtspRx.vhd | 4 ++-- protocols/i2c/rtl/I2cMaster.vhd | 2 +- protocols/i2c/rtl/I2cPkg.vhd | 2 +- protocols/i2c/rtl/I2cRegMaster.vhd | 2 +- protocols/i2c/rtl/I2cRegSlave.vhd | 2 +- protocols/i2c/rtl/I2cSlave.vhd | 2 +- protocols/i2c/rtl/i2c_master_bit_ctrl.vhd | 8 ++++---- protocols/i2c/rtl/i2c_master_byte_ctrl.vhd | 2 +- protocols/i2c/rtl/orig/i2c2ahbx.vhd | 2 +- protocols/i2c/rtl/orig/i2cmst.vhd | 4 ++-- protocols/i2c/rtl/orig/i2cslv.vhd | 2 +- protocols/jesd204b/rtl/JesdAlignChGen.vhd | 4 ++-- protocols/jesd204b/rtl/JesdIlasGen.vhd | 2 +- protocols/jesd204b/rtl/JesdSysrefMon.vhd | 2 +- protocols/line-codes/rtl/Code12b14bPkg.vhd | 2 +- .../packetizer/rtl/AxiStreamDepacketizer.vhd | 2 +- protocols/packetizer/rtl/AxiStreamPacketizer.vhd | 2 +- protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd | 4 ++-- protocols/pgp/pgp2b/core/rtl/Pgp2bPkg.vhd | 6 +++--- protocols/pgp/pgp2b/core/rtl/Pgp2bRxCell.vhd | 4 ++-- protocols/pgp/pgp2b/core/rtl/Pgp2bRxPhy.vhd | 6 +++--- protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd | 2 +- protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd | 2 +- .../pgp2b/gtp7/rtl/Pgp2bGtp7FixedLatWrapper.vhd | 2 +- .../pgp2b/gtx7/rtl/Pgp2bGtx7FixedLatWrapper.vhd | 2 +- protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd | 4 ++-- protocols/pgp/pgp2fc/core/rtl/Pgp2fcPkg.vhd | 6 +++--- protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxCell.vhd | 4 ++-- protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxPhy.vhd | 4 ++-- protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxCell.vhd | 2 +- protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxSched.vhd | 2 +- .../gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd | 2 +- .../pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7Wrapper.vhd | 2 +- .../gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd | 2 +- protocols/pgp/pgp3/core/rtl/Pgp3AxiL.vhd | 4 ++-- protocols/pgp/pgp3/core/rtl/Pgp3Pkg.vhd | 6 +++--- protocols/pgp/pgp3/core/rtl/Pgp3RxEb.vhd | 4 ++-- .../pgp/pgp3/core/rtl/Pgp3RxGearboxAligner.vhd | 2 +- protocols/pgp/pgp3/core/rtl/Pgp3RxProtocol.vhd | 6 +++--- protocols/pgp/pgp3/core/rtl/Pgp3Tx.vhd | 6 +++--- protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUs.vhd | 2 +- protocols/pgp/pgp4/core/rtl/Pgp4AxiL.vhd | 2 +- protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd | 2 +- protocols/pgp/pgp4/core/rtl/Pgp4Tx.vhd | 2 +- protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUs.vhd | 2 +- protocols/rssi/v1/rtl/RssiAxiLiteRegItf.vhd | 8 ++++---- protocols/rssi/v1/rtl/RssiHeaderReg.vhd | 2 +- protocols/rssi/v1/rtl/RssiRxFsm.vhd | 10 +++++----- protocols/rssi/v1/rtl/RssiTxFsm.vhd | 2 +- protocols/saci/saci1/rtl/SaciSlaveOld.vhd | 2 +- protocols/srp/rtl/SrpV3Core.vhd | 6 +++--- protocols/ssi/rtl/SsiFifo.vhd | 2 +- protocols/sugoi/rtl/SugoiManagerCore.vhd | 2 +- protocols/uart/rtl/UartAxiLiteMasterFsm.vhd | 4 ++-- python/surf/axi/_AxiLiteMasterProxy.py | 2 +- python/surf/axi/_AxiRingBuffer.py | 2 +- python/surf/axi/_AxiVersion.py | 4 ++-- python/surf/devices/analog_devices/_Ad9249.py | 6 +++--- python/surf/devices/analog_devices/_Ad9681.py | 2 +- python/surf/devices/analog_devices/_Adt7420.py | 2 +- python/surf/devices/linear/_Ltc2945.py | 4 ++-- python/surf/devices/nxp/_Sa56004x.py | 2 +- python/surf/devices/silabs/_Si5324.py | 2 +- python/surf/devices/silabs/_Si5326.py | 2 +- python/surf/devices/silabs/_Si5345Lite.py | 2 +- python/surf/devices/silabs/_Si5345Pages.py | 2 +- python/surf/devices/silabs/_Si5394Lite.py | 2 +- python/surf/devices/ti/_Ads54J54.py | 2 +- python/surf/devices/ti/_Lmk61e2.py | 2 +- python/surf/devices/ti/_Tmp461.py | 2 +- python/surf/devices/transceivers/_Qsfp.py | 4 ++-- python/surf/protocols/jesd204b/_JesdRx.py | 14 +++++++------- python/surf/protocols/jesd204b/_JesdTx.py | 6 +++--- .../surf/protocols/pgp/_Pgp4RxLiteLowSpeedReg.py | 2 +- .../surf/protocols/ssp/_SspLowSpeedDecoderReg.py | 6 +++--- python/surf/protocols/sugoi/_SugoiAxiL.py | 2 +- python/surf/xilinx/_AxiSysMonUltraScale.py | 4 ++-- python/surf/xilinx/_SpiPs.py | 2 +- xilinx/7Series/gth7/rtl/Gth7AutoPhaseAligner.vhd | 2 +- xilinx/7Series/gth7/rtl/Gth7RecClkMonitor.vhd | 12 ++++++------ .../gth7/rtl/Gth7RxFixedLatPhaseAligner.vhd | 2 +- xilinx/7Series/gth7/rtl/Gth7RxRst.vhd | 2 +- xilinx/7Series/gth7/rtl/Gth7TxRst.vhd | 2 +- xilinx/7Series/gtp7/rtl/Gtp7AutoPhaseAligner.vhd | 2 +- xilinx/7Series/gtp7/rtl/Gtp7RecClkMonitor.vhd | 12 ++++++------ .../gtp7/rtl/Gtp7RxFixedLatPhaseAligner.vhd | 2 +- xilinx/7Series/gtp7/rtl/Gtp7RxRst.vhd | 2 +- xilinx/7Series/gtp7/rtl/Gtp7TxRst.vhd | 2 +- xilinx/7Series/gtx7/rtl/Gtx7AutoPhaseAligner.vhd | 2 +- xilinx/7Series/gtx7/rtl/Gtx7RecClkMonitor.vhd | 12 ++++++------ .../gtx7/rtl/Gtx7RxFixedLatPhaseAligner.vhd | 2 +- xilinx/7Series/gtx7/rtl/Gtx7RxRst.vhd | 2 +- xilinx/7Series/gtx7/rtl/Gtx7TxRst.vhd | 2 +- xilinx/xvc-udp/jtag/rtl/AxisToJtag.vhd | 2 +- xilinx/xvc-udp/jtag/rtl/AxisToJtagCore.vhd | 2 +- xilinx/xvc-udp/jtag/rtl/AxisToJtagPkg.vhd | 2 +- xilinx/xvc-udp/jtag/rtl/JtagSerDesCore.vhd | 2 +- 143 files changed, 237 insertions(+), 237 deletions(-) diff --git a/axi/axi-lite/rtl/AxiLitePkg.vhd b/axi/axi-lite/rtl/AxiLitePkg.vhd index bfd1d791de..0f4880cc2a 100755 --- a/axi/axi-lite/rtl/AxiLitePkg.vhd +++ b/axi/axi-lite/rtl/AxiLitePkg.vhd @@ -262,7 +262,7 @@ package AxiLitePkg is connectivity => X"FFFF")); ------------------------------------------------------------------------------------------------- - -- Initilize masters with uppder address bits already set to configuration base address + -- Initialize masters with upper address bits already set to configuration base address ------------------------------------------------------------------------------------------------- function axiWriteMasterInit (constant config : AxiLiteCrossbarMasterConfigArray) return AxiLiteWriteMasterArray; function axiWriteMasterInit (constant config : AxiLiteCrossbarMasterConfigType) return AxiLiteWriteMasterType; diff --git a/axi/axi-lite/rtl/AxiLiteSequencerRam.vhd b/axi/axi-lite/rtl/AxiLiteSequencerRam.vhd index 70205cdddb..9bec34966b 100755 --- a/axi/axi-lite/rtl/AxiLiteSequencerRam.vhd +++ b/axi/axi-lite/rtl/AxiLiteSequencerRam.vhd @@ -451,7 +451,7 @@ begin end if; ---------------------------------------------------------------------- when SEQ_DONE_S => - -- Set all bits to 1 so SW knowns it done + -- Set all bits to 1 so SW knows it done v.addr := (others => '0'); v.din := (others => '1'); v.wstrb := (others => '1'); diff --git a/axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd index bf1eb81b7e..b3b86c0897 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd @@ -66,7 +66,7 @@ entity AxiStreamFifoV2IpIntegrator is -- Internal FIFO width select, "WIDE", "NARROW" or "CUSTOM" -- WIDE uses wider of slave / master. NARROW uses narrower. - -- CUSOTM uses passed FIFO_DATA_WIDTH_G + -- CUSTOM uses passed FIFO_DATA_WIDTH_G INT_WIDTH_SELECT : string := "WIDE"; INT_DATA_WIDTH : natural range 1 to 16 := 16; diff --git a/axi/axi-stream/rtl/AxiStreamBatchingFifo.vhd b/axi/axi-stream/rtl/AxiStreamBatchingFifo.vhd index de1198f63d..0d35338014 100644 --- a/axi/axi-stream/rtl/AxiStreamBatchingFifo.vhd +++ b/axi/axi-stream/rtl/AxiStreamBatchingFifo.vhd @@ -216,7 +216,7 @@ begin ------- END MAIN DATA FIFO ------- ---------------------------------- - -- These signals are not responsible for hanshakes and can + -- These signals are not responsible for handshakes and can -- just be forwarded combAxisMaster.tData <= axisMasterFifo.tData; combAxisMaster.tStrb <= axisMasterFifo.tStrb; diff --git a/axi/axi-stream/rtl/AxiStreamCompact.vhd b/axi/axi-stream/rtl/AxiStreamCompact.vhd index eef9d22c73..8862b3af1b 100755 --- a/axi/axi-stream/rtl/AxiStreamCompact.vhd +++ b/axi/axi-stream/rtl/AxiStreamCompact.vhd @@ -142,7 +142,7 @@ begin -- architecture rtl -- Reset full flags v.fullBus := false; - -- get tKeet boundaries + -- get tKeep boundaries tKeepMin := getTKeepMin(sAxisMaster.tKeep, SLAVE_AXI_CONFIG_G); tKeepWidth := getTKeep(sAxisMaster.tKeep, SLAVE_AXI_CONFIG_G); tDataWidth := to_integer(shift_left(to_unsigned(tKeepWidth, SLV_BYTES_C), 3)); diff --git a/axi/axi-stream/rtl/AxiStreamConcat.vhd b/axi/axi-stream/rtl/AxiStreamConcat.vhd index d047cb7a15..6f4ad7a597 100755 --- a/axi/axi-stream/rtl/AxiStreamConcat.vhd +++ b/axi/axi-stream/rtl/AxiStreamConcat.vhd @@ -4,7 +4,7 @@ -- Description: Firmware module that AxiStreamConcat multiple AXI stream frames -- together. It will ignore TKEEP and the format of the frame. ------------------------------------------------------------------------------- --- Note: This module is similiar to "AxiStreamBatcher.vhd" but does NOT +-- Note: This module is similar to "AxiStreamBatcher.vhd" but does NOT -- have the following features -- 1) No super header -- 2) No tail footer diff --git a/axi/axi-stream/rtl/AxiStreamFifoV2.vhd b/axi/axi-stream/rtl/AxiStreamFifoV2.vhd index 27273b3870..f77f1e0653 100755 --- a/axi/axi-stream/rtl/AxiStreamFifoV2.vhd +++ b/axi/axi-stream/rtl/AxiStreamFifoV2.vhd @@ -49,7 +49,7 @@ entity AxiStreamFifoV2 is -- Internal FIFO width select, "WIDE", "NARROW" or "CUSTOM" -- WIDE uses wider of slave / master. NARROW uses narrower. - -- CUSOTM uses passed FIFO_DATA_WIDTH_G + -- CUSTOM uses passed FIFO_DATA_WIDTH_G INT_WIDTH_SELECT_G : string := "WIDE"; INT_DATA_WIDTH_G : natural range 1 to AXI_STREAM_MAX_TKEEP_WIDTH_C := 16; @@ -176,7 +176,7 @@ architecture rtl of AxiStreamFifoV2 is begin - -- Cant use tkeep_fixed on master side when resizing or if not on slave side + -- Can't use tkeep_fixed on master side when resizing or if not on slave side assert (not (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_FIXED_C and SLAVE_AXI_CONFIG_G.TKEEP_MODE_C /= TKEEP_FIXED_C)) report "AxiStreamFifoV2: Can't have TKEEP_MODE = TKEEP_FIXED on master side if not on slave side" @@ -225,7 +225,7 @@ begin -- Is ready enabled? fifoReady <= (not fifoAFull) when SLAVE_READY_EN_G else '1'; - -- Output a copy of FIFO WR count incase application needs more than one threshold + -- Output a copy of FIFO WR count in case application needs more than one threshold fifoWrCnt <= fifoWrCount; -- Map bits diff --git a/axi/axi-stream/rtl/AxiStreamFlush.vhd b/axi/axi-stream/rtl/AxiStreamFlush.vhd index 06c3dae1a9..8c6dc94929 100755 --- a/axi/axi-stream/rtl/AxiStreamFlush.vhd +++ b/axi/axi-stream/rtl/AxiStreamFlush.vhd @@ -2,7 +2,7 @@ -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- -- Description: --- Block to flush AXI Stream frames, being mindfull of frame boundaries. +-- Block to flush AXI Stream frames, being mindful of frame boundaries. -- This module is designed to feed into an AxiStreamFifo using pause to determine -- backpressure situations. ------------------------------------------------------------------------------- diff --git a/axi/axi-stream/rtl/AxiStreamGearbox.vhd b/axi/axi-stream/rtl/AxiStreamGearbox.vhd index ba466f39a0..b438d9957d 100755 --- a/axi/axi-stream/rtl/AxiStreamGearbox.vhd +++ b/axi/axi-stream/rtl/AxiStreamGearbox.vhd @@ -118,7 +118,7 @@ begin assert (SLV_BYTES_C <= MST_BYTES_C or READY_EN_G = true) report "READY_EN_G must be true if slave width is great than master" severity failure; - -- Cant use tkeep_fixed on master side when resizing or if not on slave side + -- Can't use tkeep_fixed on master side when resizing or if not on slave side assert (not (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_FIXED_C and SLAVE_AXI_CONFIG_G.TKEEP_MODE_C /= TKEEP_FIXED_C)) report "AxiStreamGearbox: Can't have TKEEP_MODE = TKEEP_FIXED on master side if not on slave side" diff --git a/axi/axi-stream/rtl/AxiStreamMux.vhd b/axi/axi-stream/rtl/AxiStreamMux.vhd index 680ab12e82..43169f455c 100644 --- a/axi/axi-stream/rtl/AxiStreamMux.vhd +++ b/axi/axi-stream/rtl/AxiStreamMux.vhd @@ -47,7 +47,7 @@ entity AxiStreamMux is -- Assign a priority for each input stream index. -- Higher priority streams will be selected over those with lower priority of both are active. -- Format is (index => priority) - -- Leave unchanged for equal priority round-robbin + -- Leave unchanged for equal priority round-robin PRIORITY_G : IntegerArray := (0 => 0); -- In INDEXED mode, assign slave index to TDEST at this bit offset TDEST_LOW_G : integer range 0 to 7 := 0; @@ -179,7 +179,7 @@ begin end process; -- When in INDEXED priority mode, tvalid on a given slave side index disables selection - -- for all channels with higer index + -- for all channels with higher index PRIORITY_CONTROL : process (disableSel, sAxisMasters) is variable tmp : slv(NUM_SLAVES_G-1 downto 0); begin diff --git a/axi/axi-stream/rtl/AxiStreamResize.vhd b/axi/axi-stream/rtl/AxiStreamResize.vhd index 69bf70693d..c5c2567a0b 100644 --- a/axi/axi-stream/rtl/AxiStreamResize.vhd +++ b/axi/axi-stream/rtl/AxiStreamResize.vhd @@ -98,7 +98,7 @@ begin assert (SLV_BYTES_C <= MST_BYTES_C or READY_EN_G = true) report "READY_EN_G must be true if slave width is great than master" severity failure; - -- Cant use tkeep_fixed on master side when resizing or if not on slave side + -- Can't use tkeep_fixed on master side when resizing or if not on slave side assert (not (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_FIXED_C and SLAVE_AXI_CONFIG_G.TKEEP_MODE_C /= TKEEP_FIXED_C)) report "AxiStreamResize: Can't have TKEEP_MODE = TKEEP_FIXED on master side if not on slave side" diff --git a/axi/axi-stream/tb/AxiStreamBatchingFifoTb.vhd b/axi/axi-stream/tb/AxiStreamBatchingFifoTb.vhd index d939675d41..182cf2b2d4 100644 --- a/axi/axi-stream/tb/AxiStreamBatchingFifoTb.vhd +++ b/axi/axi-stream/tb/AxiStreamBatchingFifoTb.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- --- Description: Simulation Testbed for testing the AxiStreamBatchinFifo module +-- Description: Simulation Testbed for testing the AxiStreamBatchingFifo module ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the diff --git a/axi/axi4/rtl/AxiReadEmulate.vhd b/axi/axi4/rtl/AxiReadEmulate.vhd index a6baf21201..642c063bec 100644 --- a/axi/axi4/rtl/AxiReadEmulate.vhd +++ b/axi/axi4/rtl/AxiReadEmulate.vhd @@ -146,7 +146,7 @@ begin ---------------------------------------------------------------------- end case; - -- Combinatoral outputs before reset + -- Combinatorial outputs before reset intReadSlave <= v.iSlave; -- Reset diff --git a/axi/axi4/rtl/AxiReadPathMux.vhd b/axi/axi4/rtl/AxiReadPathMux.vhd index 61a1399cf4..58924d140d 100755 --- a/axi/axi4/rtl/AxiReadPathMux.vhd +++ b/axi/axi4/rtl/AxiReadPathMux.vhd @@ -139,7 +139,7 @@ begin v.master.arcache := selAddr.arcache; v.addrState := S_LAST_C; - -- Laster transfer + -- Last transfer when S_LAST_C => if mAxiReadSlave.arready = '1' then v.master.arvalid := '0'; diff --git a/axi/axi4/rtl/AxiWritePathMux.vhd b/axi/axi4/rtl/AxiWritePathMux.vhd index dcf3c904b3..9547a3d52b 100755 --- a/axi/axi4/rtl/AxiWritePathMux.vhd +++ b/axi/axi4/rtl/AxiWritePathMux.vhd @@ -121,7 +121,7 @@ begin v.master.awvalid := '0'; v.dataReq := '0'; - -- Aribrate between requesters + -- Arbitrate between requesters if r.addrValid = '0' then arbitrate(addrRequests, r.addrAckNum, v.addrAckNum, v.addrValid, v.addrAcks); end if; @@ -216,7 +216,7 @@ begin end if; end if; - -- Laster transfer + -- Last transfer when S_LAST_C => if mAxiWriteSlave.wready = '1' then v.master.wvalid := '0'; diff --git a/axi/axi4/tb/AxiRingBufferTb.vhd b/axi/axi4/tb/AxiRingBufferTb.vhd index 87637d32f3..5589dd1925 100755 --- a/axi/axi4/tb/AxiRingBufferTb.vhd +++ b/axi/axi4/tb/AxiRingBufferTb.vhd @@ -167,7 +167,7 @@ begin axisSlave => AXI_STREAM_SLAVE_FORCE_C); -------------------------------------- - -- Load waveofrm and check the Results + -- Load waveform and check the Results -------------------------------------- comb : process (axisMaster, r, rst) is variable v : RegType; diff --git a/axi/dma/rtl/v1/AxiStreamDmaWrite.vhd b/axi/dma/rtl/v1/AxiStreamDmaWrite.vhd index 954cfb889b..9b81f2a480 100644 --- a/axi/dma/rtl/v1/AxiStreamDmaWrite.vhd +++ b/axi/dma/rtl/v1/AxiStreamDmaWrite.vhd @@ -352,7 +352,7 @@ begin if (v.wMaster.awvalid = '0') then -- Set the memory address v.wMaster.awaddr(AXI_CONFIG_G.ADDR_WIDTH_C-1 downto 0) := r.dmaReq.address(AXI_CONFIG_G.ADDR_WIDTH_C-1 downto 0); - -- Bursts after the FIRST are garunteed to be aligned. + -- Bursts after the FIRST are guaranteed to be aligned. v.wMaster.awlen := AWLEN_C; if r.dmaReq.maxSize(31 downto ADDR_LSB_C) < v.wMaster.awlen then v.wMaster.awlen := resize(r.dmaReq.maxSize(ADDR_LSB_C+AXI_CONFIG_G.LEN_BITS_C-1 downto ADDR_LSB_C)-1, 8); diff --git a/axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd b/axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd index 885b477e3a..0bd6e58512 100755 --- a/axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd +++ b/axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd @@ -45,7 +45,7 @@ entity AxiStreamDmaV2Desc is -- Choose between one-clock arbitration for return descriptors or count and check selection DESC_ARB_G : boolean := true; - -- Choose between infeered or xpm generated descriptor FIFOs + -- Choose between inferred or xpm generated descriptor FIFOs DESC_SYNTH_MODE_G : string := "inferred"; -- Choose the type of resources for the descriptor FIFOs when DESC_SYNTH_MODE_G="xpm" diff --git a/base/general/rtl/TextUtilPkg.vhd b/base/general/rtl/TextUtilPkg.vhd index c12869d438..2a8a0b596b 100755 --- a/base/general/rtl/TextUtilPkg.vhd +++ b/base/general/rtl/TextUtilPkg.vhd @@ -199,7 +199,7 @@ package body TextUtilPkg is -- converts an integer into a character -- for 0 to 9 the obvious mapping is used, higher -- values are mapped to the characters A-Z - -- (this is usefull for systems with base > 10) + -- (this is useful for systems with base > 10) -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) function chr(intValue : integer) return character is variable c : character; diff --git a/base/ram/xilinx/SinglePortRamPrimitive.vhd b/base/ram/xilinx/SinglePortRamPrimitive.vhd index 2b49f4e6e5..018348bd7d 100644 --- a/base/ram/xilinx/SinglePortRamPrimitive.vhd +++ b/base/ram/xilinx/SinglePortRamPrimitive.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- --- Description: Manual instantation of RAM32X1S, RAM64X1S, RAM128X1S, +-- Description: Manual instantiation of RAM32X1S, RAM64X1S, RAM128X1S, -- RAM256X1S, or RAM512X1S. ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. diff --git a/devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd b/devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd index 91b5acff3c..34351f51df 100644 --- a/devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd +++ b/devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd @@ -230,9 +230,9 @@ begin axiSlaveWaitTxn(axilEp, axilWriteMaster, axilReadMaster, v.axilWriteSlave, v.axilReadSlave); -- Up to 8 delay registers - -- Write delay values to IDELAY primatives + -- Write delay values to IDELAY primitives -- All writes go to same r.delay register, - -- dataDelaySet(i) or frameDelaySet enables the primative write + -- dataDelaySet(i) or frameDelaySet enables the primitive write for i in 0 to NUM_CHANNELS_G-1 loop axiSlaveRegister(axilEp, X"00"+toSlv((i*4), 8), 0, v.delay); axiSlaveRegister(axilEp, X"00"+toSlv((i*4), 8), 5, v.dataDelaySet(i), '1'); @@ -240,7 +240,7 @@ begin axiSlaveRegister(axilEp, X"20", 0, v.delay); axiSlaveRegister(axilEp, X"20", 5, v.frameDelaySet, '1'); - -- Override read from r.delay and use curDealy output from delay primative instead + -- Override read from r.delay and use curDelay output from delay primitive instead for i in 0 to NUM_CHANNELS_G-1 loop axiSlaveRegisterR(axilEp, X"00"+toSlv((i*4), 8), 0, axilR.curDelayData(i)); end loop; diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd index ea9602677b..d51afe304c 100644 --- a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd @@ -71,7 +71,7 @@ entity Ad9249ReadoutGroup is adcStreamClk : in sl; adcStreams : out AxiStreamMasterArray(NUM_CHANNELS_G-1 downto 0) := (others => axiStreamMasterInit((false, 2, 8, 0, TKEEP_NORMAL_C, 0, TUSER_NORMAL_C))); - -- optional ready to allow evenout samples readout in adcStreamClk + -- optional ready to allow even out samples readout in adcStreamClk adcReady : in slv(NUM_CHANNELS_G-1 downto 0) := (others => '1')); end Ad9249ReadoutGroup; @@ -251,9 +251,9 @@ begin axiSlaveWaitTxn(axilEp, axilWriteMaster, axilReadMaster, v.axilWriteSlave, v.axilReadSlave); -- Up to 8 delay registers - -- Write delay values to IDELAY primatives + -- Write delay values to IDELAY primitives -- All writes go to same r.delay register, - -- dataDelaySet(i) or frameDelaySet enables the primative write + -- dataDelaySet(i) or frameDelaySet enables the primitive write for i in 0 to NUM_CHANNELS_G-1 loop axiSlaveRegister(axilEp, X"00"+toSlv((i*4), 8), 0, v.delay); axiSlaveRegister(axilEp, X"00"+toSlv((i*4), 8), 9, v.dataDelaySet(i), '1'); @@ -261,7 +261,7 @@ begin axiSlaveRegister(axilEp, X"20", 0, v.delay); axiSlaveRegister(axilEp, X"20", 9, v.frameDelaySet, '1'); - -- Override read from r.delay and use curDealy output from delay primative instead + -- Override read from r.delay and use curDelay output from delay primitive instead for i in 0 to NUM_CHANNELS_G-1 loop axiSlaveRegisterR(axilEp, X"00"+toSlv((i*4), 8), 0, curDelayData(i)); end loop; diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd index 5324c0fd5a..e9daaf4ddf 100644 --- a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd @@ -304,7 +304,7 @@ begin axiSlaveWaitTxn(axilEp, axilWriteMaster, axilReadMaster, v.axilWriteSlave, v.axilReadSlave); - -- Write delay values to IDELAY primatives + -- Write delay values to IDELAY primitives -- Overriding gearbox aligner -- All writes go to same r.delay register, axiSlaveRegister(axilEp, X"00", 0, v.delay); diff --git a/devices/AnalogDevices/ad9681/7Series/rtl/Ad9681ReadoutManual.vhd b/devices/AnalogDevices/ad9681/7Series/rtl/Ad9681ReadoutManual.vhd index 2cbfea2961..b55e527d19 100644 --- a/devices/AnalogDevices/ad9681/7Series/rtl/Ad9681ReadoutManual.vhd +++ b/devices/AnalogDevices/ad9681/7Series/rtl/Ad9681ReadoutManual.vhd @@ -273,9 +273,9 @@ begin axiSlaveWaitTxn(axilEp, axilWriteMaster, axilReadMaster, v.axilWriteSlave, v.axilReadSlave); -- Up to 8 delay registers - -- Write delay values to IDELAY primatives + -- Write delay values to IDELAY primitives -- All writes go to same r.delay register, - -- dataDelaySet(ch) or frameDelaySet enables the primative write + -- dataDelaySet(ch) or frameDelaySet enables the primitive write for i in 1 downto 0 loop for ch in 0 to NUM_CHANNELS_C-1 loop axiSlaveRegister(axilEp, X"00"+toSlv((ch*8+i*4), 8), 0, v.delay); diff --git a/devices/Linear/lct2270/rtl/AxiLtc2270Reg.vhd b/devices/Linear/lct2270/rtl/AxiLtc2270Reg.vhd index 3a2facf8d8..59da21432d 100755 --- a/devices/Linear/lct2270/rtl/AxiLtc2270Reg.vhd +++ b/devices/Linear/lct2270/rtl/AxiLtc2270Reg.vhd @@ -380,7 +380,7 @@ begin v.pntr := r.pntr + 1; if r.pntr = 15 then v.pntr := (others => '0'); - -- Check if we need to perform a read or write reponse + -- Check if we need to perform a read or write response if r.serReg(15) = '0' then axiSlaveWriteResponse(v.axiWriteSlave); else diff --git a/devices/Microchip/sy89297/rtl/Sy89297.vhd b/devices/Microchip/sy89297/rtl/Sy89297.vhd index cbf5e8ac27..e6c19a95e5 100755 --- a/devices/Microchip/sy89297/rtl/Sy89297.vhd +++ b/devices/Microchip/sy89297/rtl/Sy89297.vhd @@ -118,7 +118,7 @@ begin v.sclkCnt := r.sckHalfCycle; else - -- Decreament counter + -- Decrement counter v.sclkCnt := r.sclkCnt - 1; end if; @@ -200,7 +200,7 @@ begin v.shiftReg := v.delayB & v.delayA; ------------------------------------------------- when SEND_DATA_S => - -- Check for SCLK fallling edge + -- Check for SCLK falling edge if (r.sclk = '1') and (v.sclk = '0') then -- Update the shift register diff --git a/devices/Silabs/si5345/rtl/Si5345.vhd b/devices/Silabs/si5345/rtl/Si5345.vhd index 858bf9d3ad..5b3d88ba6b 100755 --- a/devices/Silabs/si5345/rtl/Si5345.vhd +++ b/devices/Silabs/si5345/rtl/Si5345.vhd @@ -196,7 +196,7 @@ begin -- Next State v.state := INIT_S; - -- Check if booting comand and BOOT ROM generated + -- Check if booting command and BOOT ROM generated elsif (axiWriteMaster.awaddr(14) = '1') and BOOT_ROM_C then -- Reset the counter v.ramAddr := (others => '0'); diff --git a/devices/Ti/adc32rf45/rtl/adc32rf45.vhd b/devices/Ti/adc32rf45/rtl/adc32rf45.vhd index 78f93c6cd6..7b9956360d 100644 --- a/devices/Ti/adc32rf45/rtl/adc32rf45.vhd +++ b/devices/Ti/adc32rf45/rtl/adc32rf45.vhd @@ -279,7 +279,7 @@ begin -- Send the write response axiSlaveWriteResponse(v.axiWriteSlave); else - -- Reade the bit + -- Read the bit v.axiReadSlave.rdata(7 downto 0) := ("0000000" & r.rst); -- Send the response axiSlaveReadResponse(v.axiReadSlave); diff --git a/devices/Ti/ads54j60/rtl/ads54j60.vhd b/devices/Ti/ads54j60/rtl/ads54j60.vhd index 99d1e2ebb5..c6d26cf7af 100644 --- a/devices/Ti/ads54j60/rtl/ads54j60.vhd +++ b/devices/Ti/ads54j60/rtl/ads54j60.vhd @@ -228,7 +228,7 @@ begin -- Send the write response axiSlaveWriteResponse(v.axiWriteSlave); else - -- Reade the bit + -- Read the bit v.axiReadSlave.rdata(7 downto 0) := ("0000000" & r.rst); -- Send the response axiSlaveReadResponse(v.axiReadSlave); diff --git a/dsp/xilinx/fixed/CfixedMult.vhd b/dsp/xilinx/fixed/CfixedMult.vhd index b7ad6ee349..b7cccaf5a7 100644 --- a/dsp/xilinx/fixed/CfixedMult.vhd +++ b/dsp/xilinx/fixed/CfixedMult.vhd @@ -37,7 +37,7 @@ use surf.ComplexFixedPkg.all; -- y(n) = p(n) ( REG_OUT_G = false ) -- y(n) = p(n-1) ( REG_OUT_G = true ) -- --- Defaults to wrap and trucnated output for size(y) +-- Defaults to wrap and truncated output for size(y) entity cfixedMult is generic ( diff --git a/dsp/xilinx/fixed/CfixedMultAdd.vhd b/dsp/xilinx/fixed/CfixedMultAdd.vhd index 8fb224580e..30200880d4 100644 --- a/dsp/xilinx/fixed/CfixedMultAdd.vhd +++ b/dsp/xilinx/fixed/CfixedMultAdd.vhd @@ -39,7 +39,7 @@ use surf.ComplexFixedPkg.all; -- y(n) = p(n) ( REG_OUT_G = false ) -- y(n) = p(n-1) ( REG_OUT_G = true ) -- --- Defaults to wrap and trucnated output for size(y) +-- Defaults to wrap and truncated output for size(y) entity cfixedMultAdd is generic ( diff --git a/dsp/xilinx/fixed/SinCosTaylor.vhd b/dsp/xilinx/fixed/SinCosTaylor.vhd index fa1e07a6a1..a8c36e5f7e 100644 --- a/dsp/xilinx/fixed/SinCosTaylor.vhd +++ b/dsp/xilinx/fixed/SinCosTaylor.vhd @@ -3,7 +3,7 @@ ------------------------------------------------------------------------------- -- Description: Taylor series corrected SinCosLut, stores 1/4 cos in -- INT_PHASE_WIDTH_G - 2 bits LUT and does 1st order Taylor series --- correction on ouput (3 real multipliers) +-- correction on output (3 real multipliers) -- dout.re <= cos -- dout.im <= sin -- diff --git a/ethernet/EthMacCore/rtl/EthMacRxImportXgmii.vhd b/ethernet/EthMacCore/rtl/EthMacRxImportXgmii.vhd index ee4cb2b74d..caac5c75cc 100755 --- a/ethernet/EthMacCore/rtl/EthMacRxImportXgmii.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRxImportXgmii.vhd @@ -274,7 +274,7 @@ begin rxCrcError <= intAdvance and intLastLine and (not crcGood); rxCountEn <= intAdvance and intLastLine and crcGood; - -- Logic to dermine CRC width and valid clear timing. + -- Logic to determine CRC width and valid clear timing. process (crcDataValid, crcDataWidth, phyRxc, phyRxcDly, rxdAlign) begin @@ -361,7 +361,7 @@ begin crcInit <= '1' after TPD_G; rxdAlign <= '0' after TPD_G; - -- shifted aligment + -- shifted alignment elsif lastSOF = '1' and phyReady = '1' then frameShift0 <= '1' after TPD_G; crcInit <= '1' after TPD_G; diff --git a/ethernet/EthMacCore/rtl/EthMacTop.vhd b/ethernet/EthMacCore/rtl/EthMacTop.vhd index d278648685..7b13841a01 100755 --- a/ethernet/EthMacCore/rtl/EthMacTop.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTop.vhd @@ -165,7 +165,7 @@ begin -- Misc. Configurations ROCEV2_EN_G => ROCEV2_EN_G, BYP_EN_G => BYP_EN_G, - -- RAM sythesis Mode + -- RAM synthesis Mode SYNTH_MODE_G => SYNTH_MODE_G) port map ( -- Clocks diff --git a/ethernet/EthMacCore/rtl/EthMacTxExportGmii.vhd b/ethernet/EthMacCore/rtl/EthMacTxExportGmii.vhd index c1631a7e50..7367849238 100755 --- a/ethernet/EthMacCore/rtl/EthMacTxExportGmii.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxExportGmii.vhd @@ -260,7 +260,7 @@ begin v.gmiiTxEn := '0'; v.gmiiTxd := x"00"; v.txCount := r.txCount +1; - if r.txCount = x"0A" then -- 12 Octels (11 in INTERGAP_S + 1 in IDLE_S) + if r.txCount = x"0A" then -- 12 Octets (11 in INTERGAP_S + 1 in IDLE_S) v.txCount := x"00"; v.state := IDLE_S; end if; diff --git a/ethernet/EthMacCore/rtl/EthMacTxExportXgmii.vhd b/ethernet/EthMacCore/rtl/EthMacTxExportXgmii.vhd index a6b04bae36..fc7bc8d62b 100755 --- a/ethernet/EthMacCore/rtl/EthMacTxExportXgmii.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxExportXgmii.vhd @@ -504,7 +504,7 @@ begin nxtEOF <= '0' after TPD_G; else - -- EOF Charactor Required If CRC was in last word and there was + -- EOF Character Required If CRC was in last word and there was -- not enough space for EOF if nxtEOF = '1' then phyTxd <= X"07070707070707FD" after TPD_G; diff --git a/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd b/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd index 3cbda5c1ba..cb5f47f2df 100644 --- a/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd +++ b/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd @@ -210,7 +210,7 @@ begin qPllReset => qpllReset); -- Once the QPLL is locked, prevent the - -- IP cores from accidentally reseting each other + -- IP cores from accidentally resetting each other qpllReset(0) <= sysRst125 or (uOr(qpllRst) and not(qPllLock(0))); qPllReset(1) <= '1'; -- Not using QPLL[1] diff --git a/ethernet/RoCEv2/rtl/RoceResizeAndSwap.vhd b/ethernet/RoCEv2/rtl/RoceResizeAndSwap.vhd index ae7c5aeda3..3c0408821b 100755 --- a/ethernet/RoCEv2/rtl/RoceResizeAndSwap.vhd +++ b/ethernet/RoCEv2/rtl/RoceResizeAndSwap.vhd @@ -120,7 +120,7 @@ begin assert (SLV_BYTES_C <= MST_BYTES_C or READY_EN_G = true) report "READY_EN_G must be true if slave width is great than master" severity failure; - -- Cant use tkeep_fixed on master side when resizing or if not on slave side + -- Can't use tkeep_fixed on master side when resizing or if not on slave side assert (not (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_FIXED_C and SLAVE_AXI_CONFIG_G.TKEEP_MODE_C /= TKEEP_FIXED_C)) report "AxiStreamResize: Can't have TKEEP_MODE = TKEEP_FIXED on master side if not on slave side" diff --git a/ethernet/XauiCore/gth7/rtl/XauiGth7Core.vhd b/ethernet/XauiCore/gth7/rtl/XauiGth7Core.vhd index 75b27dbe88..e59cdc3339 100644 --- a/ethernet/XauiCore/gth7/rtl/XauiGth7Core.vhd +++ b/ethernet/XauiCore/gth7/rtl/XauiGth7Core.vhd @@ -107,7 +107,7 @@ architecture wrapper of XauiGth7Core is gt0_txphinitdone_out : out std_logic; gt0_txdlysresetdone_out : out std_logic; gt0_cplllock_out : out std_logic; - -- Signal Integrity adn Functionality + -- Signal Integrity and Functionality -- Eye Scan gt0_eyescantrigger_in : in std_logic; gt0_eyescanreset_in : in std_logic; @@ -165,7 +165,7 @@ architecture wrapper of XauiGth7Core is gt1_txphinitdone_out : out std_logic; gt1_txdlysresetdone_out : out std_logic; gt1_cplllock_out : out std_logic; - -- Signal Integrity adn Functionality + -- Signal Integrity and Functionality -- Eye Scan gt1_eyescantrigger_in : in std_logic; gt1_eyescanreset_in : in std_logic; @@ -223,7 +223,7 @@ architecture wrapper of XauiGth7Core is gt2_txphinitdone_out : out std_logic; gt2_txdlysresetdone_out : out std_logic; gt2_cplllock_out : out std_logic; - -- Signal Integrity adn Functionality + -- Signal Integrity and Functionality -- Eye Scan gt2_eyescantrigger_in : in std_logic; gt2_eyescanreset_in : in std_logic; @@ -281,7 +281,7 @@ architecture wrapper of XauiGth7Core is gt3_txphinitdone_out : out std_logic; gt3_txdlysresetdone_out : out std_logic; gt3_cplllock_out : out std_logic; - -- Signal Integrity adn Functionality + -- Signal Integrity and Functionality -- Eye Scan gt3_eyescantrigger_in : in std_logic; gt3_eyescanreset_in : in std_logic; @@ -380,7 +380,7 @@ begin gt0_txphinitdone_out => open, gt0_txdlysresetdone_out => open, gt0_cplllock_out => open, - -- Signal Integrity adn Functionality + -- Signal Integrity and Functionality -- Eye Scan gt0_eyescantrigger_in => '0', gt0_eyescanreset_in => '0', @@ -438,7 +438,7 @@ begin gt1_txphinitdone_out => open, gt1_txdlysresetdone_out => open, gt1_cplllock_out => open, - -- Signal Integrity adn Functionality + -- Signal Integrity and Functionality -- Eye Scan gt1_eyescantrigger_in => '0', gt1_eyescanreset_in => '0', @@ -496,7 +496,7 @@ begin gt2_txphinitdone_out => open, gt2_txdlysresetdone_out => open, gt2_cplllock_out => open, - -- Signal Integrity adn Functionality + -- Signal Integrity and Functionality -- Eye Scan gt2_eyescantrigger_in => '0', gt2_eyescanreset_in => '0', @@ -554,7 +554,7 @@ begin gt3_txphinitdone_out => open, gt3_txdlysresetdone_out => open, gt3_cplllock_out => open, - -- Signal Integrity adn Functionality + -- Signal Integrity and Functionality -- Eye Scan gt3_eyescantrigger_in => '0', gt3_eyescanreset_in => '0', diff --git a/ethernet/XauiCore/gtx7/rtl/XauiGtx7Core.vhd b/ethernet/XauiCore/gtx7/rtl/XauiGtx7Core.vhd index 08b7e2b930..7d3203d129 100644 --- a/ethernet/XauiCore/gtx7/rtl/XauiGtx7Core.vhd +++ b/ethernet/XauiCore/gtx7/rtl/XauiGtx7Core.vhd @@ -105,7 +105,7 @@ architecture wrapper of XauiGtx7Core is gt0_txphinitdone_out : out std_logic; gt0_txdlysresetdone_out : out std_logic; gt_qplllock_out : out std_logic; - -- Signal Integrity adn Functionality + -- Signal Integrity and Functionality -- Eye Scan gt0_eyescantrigger_in : in std_logic; gt0_eyescanreset_in : in std_logic; @@ -160,7 +160,7 @@ architecture wrapper of XauiGtx7Core is gt1_txphaligndone_out : out std_logic; gt1_txphinitdone_out : out std_logic; gt1_txdlysresetdone_out : out std_logic; - -- Signal Integrity adn Functionality + -- Signal Integrity and Functionality -- Eye Scan gt1_eyescantrigger_in : in std_logic; gt1_eyescanreset_in : in std_logic; @@ -215,7 +215,7 @@ architecture wrapper of XauiGtx7Core is gt2_txphaligndone_out : out std_logic; gt2_txphinitdone_out : out std_logic; gt2_txdlysresetdone_out : out std_logic; - -- Signal Integrity adn Functionality + -- Signal Integrity and Functionality -- Eye Scan gt2_eyescantrigger_in : in std_logic; gt2_eyescanreset_in : in std_logic; @@ -270,7 +270,7 @@ architecture wrapper of XauiGtx7Core is gt3_txphaligndone_out : out std_logic; gt3_txphinitdone_out : out std_logic; gt3_txdlysresetdone_out : out std_logic; - -- Signal Integrity adn Functionality + -- Signal Integrity and Functionality -- Eye Scan gt3_eyescantrigger_in : in std_logic; gt3_eyescanreset_in : in std_logic; @@ -367,7 +367,7 @@ begin gt0_txphinitdone_out => open, gt0_txdlysresetdone_out => open, gt_qplllock_out => open, - -- Signal Integrity adn Functionality + -- Signal Integrity and Functionality -- Eye Scan gt0_eyescantrigger_in => '0', gt0_eyescanreset_in => '0', @@ -422,7 +422,7 @@ begin gt1_txphaligndone_out => open, gt1_txphinitdone_out => open, gt1_txdlysresetdone_out => open, - -- Signal Integrity adn Functionality + -- Signal Integrity and Functionality -- Eye Scan gt1_eyescantrigger_in => '0', gt1_eyescanreset_in => '0', @@ -477,7 +477,7 @@ begin gt2_txphaligndone_out => open, gt2_txphinitdone_out => open, gt2_txdlysresetdone_out => open, - -- Signal Integrity adn Functionality + -- Signal Integrity and Functionality -- Eye Scan gt2_eyescantrigger_in => '0', gt2_eyescanreset_in => '0', @@ -532,7 +532,7 @@ begin gt3_txphaligndone_out => open, gt3_txphinitdone_out => open, gt3_txdlysresetdone_out => open, - -- Signal Integrity adn Functionality + -- Signal Integrity and Functionality -- Eye Scan gt3_eyescantrigger_in => '0', gt3_eyescanreset_in => '0', diff --git a/protocols/batcher/rtl/AxiStreamBatcherEventBuilder.vhd b/protocols/batcher/rtl/AxiStreamBatcherEventBuilder.vhd index 8f9e333fb8..15c40e7d74 100755 --- a/protocols/batcher/rtl/AxiStreamBatcherEventBuilder.vhd +++ b/protocols/batcher/rtl/AxiStreamBatcherEventBuilder.vhd @@ -495,7 +495,7 @@ begin end if; - -- Check if reseting counters + -- Check if resetting counters if (r.cntRst = '1') then v.dataCnt := (others => (others => '0')); v.nullCnt := (others => (others => '0')); diff --git a/protocols/coaxpress/core/rtl/CoaXPressConfig.vhd b/protocols/coaxpress/core/rtl/CoaXPressConfig.vhd index b3db0f11cf..b1b1748555 100644 --- a/protocols/coaxpress/core/rtl/CoaXPressConfig.vhd +++ b/protocols/coaxpress/core/rtl/CoaXPressConfig.vhd @@ -211,7 +211,7 @@ begin v.tDataK(0) := '1'; v.tData(0) := CXP_SOP_C; - -- Control command indication: with or with tag + -- Control command indication: with or without tag if (r.configPktTag = '1') then -- Type=0x05 = Indicates control command with tag diff --git a/protocols/event-frame-sequencer/rtl/EventFrameSequencerDemux.vhd b/protocols/event-frame-sequencer/rtl/EventFrameSequencerDemux.vhd index 8e3d7cea25..360b3abb61 100755 --- a/protocols/event-frame-sequencer/rtl/EventFrameSequencerDemux.vhd +++ b/protocols/event-frame-sequencer/rtl/EventFrameSequencerDemux.vhd @@ -3,7 +3,7 @@ ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- --- Description: Event Frame Sequencer DEUX +-- Description: Event Frame Sequencer DEMUX ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the @@ -340,7 +340,7 @@ begin v.frameCnt := r.frameCnt + 1; v.dataCnt(r.index) := r.dataCnt(r.index) + 1; - -- Check if reseting frame counters + -- Check if resetting frame counters if (r.numFrames = r.frameCnt) then -- Increment counter @@ -353,7 +353,7 @@ begin end if; - -- Check if reseting status counters + -- Check if resetting status counters if (r.cntRst = '1') then v.dataCnt := (others => (others => '0')); v.dropCnt := (others => '0'); diff --git a/protocols/event-frame-sequencer/rtl/EventFrameSequencerMux.vhd b/protocols/event-frame-sequencer/rtl/EventFrameSequencerMux.vhd index e94c0f8ce7..0a3ca812a0 100755 --- a/protocols/event-frame-sequencer/rtl/EventFrameSequencerMux.vhd +++ b/protocols/event-frame-sequencer/rtl/EventFrameSequencerMux.vhd @@ -458,7 +458,7 @@ begin end if; - -- Check if reseting counters + -- Check if resetting counters if (r.cntRst = '1') then v.dataCnt := (others => (others => '0')); v.transCnt := (others => '0'); diff --git a/protocols/glink/gtx7/rtl/GLinkGtx7RxRst.vhd b/protocols/glink/gtx7/rtl/GLinkGtx7RxRst.vhd index 7f7bd783f3..13012e96e8 100755 --- a/protocols/glink/gtx7/rtl/GLinkGtx7RxRst.vhd +++ b/protocols/glink/gtx7/rtl/GLinkGtx7RxRst.vhd @@ -41,7 +41,7 @@ entity GLinkGtx7RxRst is GTRXRESET : out std_logic := '0'; MMCM_RESET : out std_logic := '1'; PLL_RESET : out std_logic := '0'; --Reset PLL - RX_FSM_RESET_DONE : out std_logic; --Reset-sequence has sucessfully been finished. + RX_FSM_RESET_DONE : out std_logic; --Reset-sequence has successfully been finished. RXUSERRDY : out std_logic := '0'; RUN_PHALIGNMENT : out std_logic; PHALIGNMENT_DONE : in std_logic; -- Drive high if phase alignment not needed diff --git a/protocols/htsp/core/rtl/HtspAxiL.vhd b/protocols/htsp/core/rtl/HtspAxiL.vhd index da008e0a06..15e9464dde 100755 --- a/protocols/htsp/core/rtl/HtspAxiL.vhd +++ b/protocols/htsp/core/rtl/HtspAxiL.vhd @@ -307,7 +307,7 @@ begin -- Uptime counter --------------------------------- - -- Check for timout + -- Check for timeout if r.timer = TIMEOUT_1HZ_C then -- Reset the timer diff --git a/protocols/htsp/core/rtl/HtspRx.vhd b/protocols/htsp/core/rtl/HtspRx.vhd index 7fa624695a..cae8fa14fa 100755 --- a/protocols/htsp/core/rtl/HtspRx.vhd +++ b/protocols/htsp/core/rtl/HtspRx.vhd @@ -145,7 +145,7 @@ begin case r.state is ---------------------------------------------------------------------- when IDLE_S => - -- Check if read to move data + -- Check if ready to move data if (phyRxMaster.tValid = '1') and (phyRxRdy = '1') then -- Calculate the checksum @@ -235,7 +235,7 @@ begin end if; ---------------------------------------------------------------------- when PAYLOAD_S => - -- Check if read to move data + -- Check if ready to move data if (phyRxMaster.tValid = '1') and (phyRxRdy = '1') then -- Advance the output pipeline diff --git a/protocols/i2c/rtl/I2cMaster.vhd b/protocols/i2c/rtl/I2cMaster.vhd index a6549ba355..026e84cbe0 100644 --- a/protocols/i2c/rtl/I2cMaster.vhd +++ b/protocols/i2c/rtl/I2cMaster.vhd @@ -342,7 +342,7 @@ begin v.i2cMasterOut.txnError := '0'; -- Necessary, should already be 0? v.state := WAIT_TXN_REQ_S; else - -- If not last byte, write nother + -- If not last byte, write another v.state := WRITE_S; end if; else diff --git a/protocols/i2c/rtl/I2cPkg.vhd b/protocols/i2c/rtl/I2cPkg.vhd index cd1e912fdc..159bdf0af0 100755 --- a/protocols/i2c/rtl/I2cPkg.vhd +++ b/protocols/i2c/rtl/I2cPkg.vhd @@ -71,7 +71,7 @@ package I2cPkg is type I2cMasterOutType is record busAck : sl; - txnError : sl; -- An error occured during the txn + txnError : sl; -- An error occurred during the txn wrAck : sl; rdValid : sl; rdData : slv(7 downto 0); -- Data received during read txn diff --git a/protocols/i2c/rtl/I2cRegMaster.vhd b/protocols/i2c/rtl/I2cRegMaster.vhd index e75dc713b5..a1b48dff0d 100644 --- a/protocols/i2c/rtl/I2cRegMaster.vhd +++ b/protocols/i2c/rtl/I2cRegMaster.vhd @@ -241,7 +241,7 @@ begin end case; - -- Always check for errors an cancel the txn if they happen + -- Always check for errors and cancel the txn if they happen if (i2cMasterOut.txnError = '1' and i2cMasterOut.rdValid = '1') then v.regOut.regFail := '1'; v.regOut.regFailCode := i2cMasterOut.rdData; diff --git a/protocols/i2c/rtl/I2cRegSlave.vhd b/protocols/i2c/rtl/I2cRegSlave.vhd index 3d8bd697b8..7637bf4416 100755 --- a/protocols/i2c/rtl/I2cRegSlave.vhd +++ b/protocols/i2c/rtl/I2cRegSlave.vhd @@ -127,7 +127,7 @@ begin -- Enable the i2cSlave after reset v.i2cSlaveIn.enable := '1'; - -- Read and Write enables are pulsed, defualt to 0 + -- Read and Write enables are pulsed, default to 0 v.wrEn := '0'; v.rdEn := '0'; diff --git a/protocols/i2c/rtl/I2cSlave.vhd b/protocols/i2c/rtl/I2cSlave.vhd index bce8c86c3b..f78726b3a6 100644 --- a/protocols/i2c/rtl/I2cSlave.vhd +++ b/protocols/i2c/rtl/I2cSlave.vhd @@ -362,7 +362,7 @@ begin v.o.nack := '1'; end if; end if; - -- Risinge edge + -- Rising edge if (not r.scl and v.scl) = '1' then if r.addr then v.slvstate := movebyte; diff --git a/protocols/i2c/rtl/i2c_master_bit_ctrl.vhd b/protocols/i2c/rtl/i2c_master_bit_ctrl.vhd index 2cdaa08003..63c1bfef56 100755 --- a/protocols/i2c/rtl/i2c_master_bit_ctrl.vhd +++ b/protocols/i2c/rtl/i2c_master_bit_ctrl.vhd @@ -82,7 +82,7 @@ -- Cleaned up code -- -- Revision 1.3 2002/10/30 18:09:53 rherveille --- Fixed some reported minor start/stop generation timing issuess. +-- Fixed some reported minor start/stop generation timing issues. -- -- Revision 1.2 2002/06/15 07:37:04 rherveille -- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. @@ -162,7 +162,7 @@ -- Th_scl 4.0us 0.6us High period of SCL -- Tl_scl 4.7us 1.3us Low period of SCL -- Tsu:sta 4.7us 0.6us setup time for a repeated start condition --- Tsu:sto 4.0us 0.6us setup time for a stop conditon +-- Tsu:sto 4.0us 0.6us setup time for a stop condition -- Tbuf 4.7us 1.3us Bus free time between a stop and start condition -- @@ -328,7 +328,7 @@ begin csync <= andv(discl_oen(DR downto 1)) and not fSCL(0) and fSCL(1); -- generate arbitration lost signal - -- aribitration lost when: + -- arbitration lost when: -- 1) master drives SDA high, but the i2c bus is low -- 2) stop detected while not requested (detect during 'idle' state) gen_al : process(clk, nReset) @@ -449,7 +449,7 @@ begin csync <= andv(fiscl_oen) and not fSCL(0) and fSCL(1); -- generate arbitration lost signal - -- aribitration lost when: + -- arbitration lost when: -- 1) master drives SDA high, but the i2c bus is low -- 2) stop detected while not requested (detect during 'idle' state) gen_ald : process(clk, nReset) diff --git a/protocols/i2c/rtl/i2c_master_byte_ctrl.vhd b/protocols/i2c/rtl/i2c_master_byte_ctrl.vhd index 3ff092c025..b6aa6e6073 100755 --- a/protocols/i2c/rtl/i2c_master_byte_ctrl.vhd +++ b/protocols/i2c/rtl/i2c_master_byte_ctrl.vhd @@ -277,7 +277,7 @@ begin c_state <= st_idle; ack_out <= '0'; else - -- initialy reset all signal + -- initially reset all signal core_txd <= sr(7); shift <= '0'; ld <= '0'; diff --git a/protocols/i2c/rtl/orig/i2c2ahbx.vhd b/protocols/i2c/rtl/orig/i2c2ahbx.vhd index c4f26a73f2..9e7f41f07a 100644 --- a/protocols/i2c/rtl/orig/i2c2ahbx.vhd +++ b/protocols/i2c/rtl/orig/i2c2ahbx.vhd @@ -380,7 +380,7 @@ begin end if; end if; end if; - -- Risinge edge + -- Rising edge if (not r.scl and v.scl) = '1' then if (r.i2caddr or not r.ahbacc) = '1' then if r.sda = I2C_ACK then diff --git a/protocols/i2c/rtl/orig/i2cmst.vhd b/protocols/i2c/rtl/orig/i2cmst.vhd index e81d8f74de..6e7df76018 100644 --- a/protocols/i2c/rtl/orig/i2cmst.vhd +++ b/protocols/i2c/rtl/orig/i2cmst.vhd @@ -29,7 +29,7 @@ -- The OC byte- and bit-controller are located under lib/opencores/i2c -- -- The original master had a WISHBONE interface with registers --- aligned at byte boundaries. This wrapper has a slighly different +-- aligned at byte boundaries. This wrapper has a slightly different -- alignment of the registers, and also (optionally) adds a filter -- filter register (FR): -- @@ -159,7 +159,7 @@ architecture rtl of i2cmst is signal done : std_logic; -- Signals completion of command signal rxack : std_logic; -- Received acknowledge signal busy : std_logic; -- I2C core busy - signal al : std_logic; -- Aribitration lost + signal al : std_logic; -- Arbitration lost signal irst : std_ulogic; -- Internal, negated reset signal signal iscloen : std_ulogic; -- Internal SCL output enable signal isdaoen : std_ulogic; -- Internal SDA output enable diff --git a/protocols/i2c/rtl/orig/i2cslv.vhd b/protocols/i2c/rtl/orig/i2cslv.vhd index 604b0f9182..a1734ab718 100644 --- a/protocols/i2c/rtl/orig/i2cslv.vhd +++ b/protocols/i2c/rtl/orig/i2cslv.vhd @@ -462,7 +462,7 @@ begin v.reg.sts.nak := '1'; end if; end if; - -- Risinge edge + -- Rising edge if (not r.scl and v.scl) = '1' then if r.addr then v.slvstate := movebyte; diff --git a/protocols/jesd204b/rtl/JesdAlignChGen.vhd b/protocols/jesd204b/rtl/JesdAlignChGen.vhd index 096be27b09..00730b2fda 100755 --- a/protocols/jesd204b/rtl/JesdAlignChGen.vhd +++ b/protocols/jesd204b/rtl/JesdAlignChGen.vhd @@ -9,9 +9,9 @@ -- A(K28.3) - x"7C" - Inserted at the end of a multi-frame. -- F(K28.7) - x"FC" - Inserted at the end of a frame. -- --- Note: Character replacement mechanism is different weather scrambler is enabled or disabled. +-- Note: Character replacement mechanism is different whether scrambler is enabled or disabled. -- Disabled: The characters are inserted if two corresponding octets in consecutive samples have the same value. --- Enabled: The characters are inserted it the corresponding octet has the same value as the inserted character. +-- Enabled: The characters are inserted if the corresponding octet has the same value as the inserted character. -- -- 3 c-c data latency -- diff --git a/protocols/jesd204b/rtl/JesdIlasGen.vhd b/protocols/jesd204b/rtl/JesdIlasGen.vhd index 6721b7108a..d7e92a7bf5 100755 --- a/protocols/jesd204b/rtl/JesdIlasGen.vhd +++ b/protocols/jesd204b/rtl/JesdIlasGen.vhd @@ -2,7 +2,7 @@ -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- -- Description: Initial lane alignment sequence Generator --- Adds A na R characters at the LMFC borders. +-- Adds A and R characters at the LMFC borders. ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the diff --git a/protocols/jesd204b/rtl/JesdSysrefMon.vhd b/protocols/jesd204b/rtl/JesdSysrefMon.vhd index 39e929a925..45fc7fb147 100644 --- a/protocols/jesd204b/rtl/JesdSysrefMon.vhd +++ b/protocols/jesd204b/rtl/JesdSysrefMon.vhd @@ -115,7 +115,7 @@ begin end if; - -- Check for reseting statistics + -- Check for resetting statistics if (clr = '1') then v := REG_INIT_C; end if; diff --git a/protocols/line-codes/rtl/Code12b14bPkg.vhd b/protocols/line-codes/rtl/Code12b14bPkg.vhd index 05a3520191..d425388bd7 100644 --- a/protocols/line-codes/rtl/Code12b14bPkg.vhd +++ b/protocols/line-codes/rtl/Code12b14bPkg.vhd @@ -351,7 +351,7 @@ package body Code12b14bPkg is -- Given an running disparity and a selected code disparity, - -- determine whether the selected code needs to be complimented, and what the out disparity is + -- determine whether the selected code needs to be complemented, and what the out disparity is -- Should maybe implement DisparityType as a constrained integer and just use math here -- instead of this state machine. Not sure which is better. procedure disparityControl ( diff --git a/protocols/packetizer/rtl/AxiStreamDepacketizer.vhd b/protocols/packetizer/rtl/AxiStreamDepacketizer.vhd index 555f43d2ca..8ec48340ec 100755 --- a/protocols/packetizer/rtl/AxiStreamDepacketizer.vhd +++ b/protocols/packetizer/rtl/AxiStreamDepacketizer.vhd @@ -3,7 +3,7 @@ ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- --- Description: AXI stream DePacketerizer Module (non-interleave only) +-- Description: AXI stream Depacketizer Module (non-interleave only) -- Formats an AXI-Stream for a transport link. -- Sideband fields are placed into the data stream in a header. -- Long frames are broken into smaller packets. diff --git a/protocols/packetizer/rtl/AxiStreamPacketizer.vhd b/protocols/packetizer/rtl/AxiStreamPacketizer.vhd index 26593794d9..d3f9dd7488 100755 --- a/protocols/packetizer/rtl/AxiStreamPacketizer.vhd +++ b/protocols/packetizer/rtl/AxiStreamPacketizer.vhd @@ -3,7 +3,7 @@ ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- --- Description: AXI stream DePacketerizer Module (non-interleave only) +-- Description: AXI stream Depacketizer Module (non-interleave only) -- Formats an AXI-Stream for a transport link. -- Sideband fields are placed into the data stream in a header. -- Long frames are broken into smaller packets. diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd index 991021f940..68fbcc9327 100644 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd @@ -227,7 +227,7 @@ begin rxStatusSync.remLinkData <= pgpRxOut.remLinkData; end generate; - -- Errror counters and non counted values + -- Error counters and non counted values U_RxError : entity surf.SyncStatusVector generic map ( TPD_G => TPD_G, @@ -367,7 +367,7 @@ begin valid => open, dout => txStatusSync.txOpCodeLast); - -- Errror counters and non counted values + -- Error counters and non counted values U_TxError : entity surf.SyncStatusVector generic map ( TPD_G => TPD_G, diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bPkg.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bPkg.vhd index c7710d7e7c..8985dde0b6 100755 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bPkg.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bPkg.vhd @@ -70,9 +70,9 @@ package Pgp2bPkg is linkPolarity : slv(1 downto 0); -- Receive link polarity frameRx : sl; -- A good frame was received frameRxErr : sl; -- An errored frame was received - cellError : sl; -- A cell error has occured - linkDown : sl; -- A link down event has occured - linkError : sl; -- A link error has occured + cellError : sl; -- A cell error has occurred + linkDown : sl; -- A link down event has occurred + linkError : sl; -- A link error has occurred opCodeEn : sl; -- Opcode receive enable opCode : slv(7 downto 0); -- Opcode receive value remLinkReady : sl; -- Far end side has link diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bRxCell.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bRxCell.vhd index 5e4b3d10f3..7560fe7960 100755 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bRxCell.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bRxCell.vhd @@ -43,7 +43,7 @@ entity Pgp2bRxCell is pgpRxLinkReady : in sl; -- Local side has link -- Cell Error, one pulse per error - pgpRxCellError : out sl; -- A cell error has occured + pgpRxCellError : out sl; -- A cell error has occurred -- Interface to PHY Logic cellRxPause : in sl; -- Cell data pause @@ -703,7 +703,7 @@ begin end process; - -- Update buffer status on successfull cell reception + -- Update buffer status on successful cell reception process (pgpRxClk) begin if rising_edge(pgpRxClk) then diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bRxPhy.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bRxPhy.vhd index 4b62122f50..c8e09e7fef 100755 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bRxPhy.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bRxPhy.vhd @@ -38,8 +38,8 @@ entity Pgp2bRxPhy is pgpRxLinkReady : out sl; -- Local side has link -- Error Flags, one pulse per event - pgpRxLinkDown : out sl := '0'; -- A link down event has occured - pgpRxLinkError : out sl := '0'; -- A link error has occured + pgpRxLinkDown : out sl := '0'; -- A link down event has occurred + pgpRxLinkError : out sl := '0'; -- A link error has occurred -- Opcode Receive Interface pgpRxOpCodeEn : out sl; -- Opcode receive enable @@ -49,7 +49,7 @@ entity Pgp2bRxPhy is pgpRemLinkReady : out sl := '0'; -- Far end side has link pgpRemData : out slv(7 downto 0) := (others => '0'); -- Far end side User Data - -- Cell Receive Interfac e + -- Cell Receive Interface cellRxPause : out sl; -- Cell data pause cellRxSOC : out sl; -- Cell data start of cell cellRxSOF : out sl; -- Cell data start of frame diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd index b0ee678113..87a0449ca8 100755 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd @@ -406,7 +406,7 @@ begin -- Go back to idle nxtState <= ST_IDLE_C; - -- Send first charactor of cell, assert ready + -- Send first character of cell, assert ready when ST_SOC_C => cellCntRst <= '1'; nxtFrameTxReady <= not intTimeout; diff --git a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd index 501d8e1293..4230bb71d5 100755 --- a/protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd +++ b/protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd @@ -85,7 +85,7 @@ architecture Pgp2bTxSched of Pgp2bTxSched is signal vcTimeout : slv(3 downto 0) := (others => '0'); signal gateTxValid : slv(3 downto 0); - -- Schedular state + -- Scheduler state constant ST_RST_C : slv(2 downto 0) := "001"; constant ST_ARB_C : slv(2 downto 0) := "010"; constant ST_CELL_C : slv(2 downto 0) := "011"; diff --git a/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7FixedLatWrapper.vhd b/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7FixedLatWrapper.vhd index 5607c16377..ccc0d35d2e 100644 --- a/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7FixedLatWrapper.vhd +++ b/protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7FixedLatWrapper.vhd @@ -425,7 +425,7 @@ begin pgpRxReset => pgpRxReset, --extRst, pgpRxRecClk => pgpRxRecClk, pgpRxRecClkRst => pgpRxRecClkRst, - pgpRxClk => pgpRxClkLoc, -- RecClk fed back, optionally though MMCM + pgpRxClk => pgpRxClkLoc, -- RecClk fed back, optionally through MMCM pgpRxMmcmReset => pgpRxMmcmReset, pgpRxMmcmLocked => pgpRxMmcmLocked, -- Non VC Rx Signals diff --git a/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLatWrapper.vhd b/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLatWrapper.vhd index d32659176c..62444ffef8 100644 --- a/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLatWrapper.vhd +++ b/protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLatWrapper.vhd @@ -418,7 +418,7 @@ begin pgpRxReset => pgpRxReset, --extRst, pgpRxRecClk => pgpRxRecClk, pgpRxRecClkRst => pgpRxRecClkRst, - pgpRxClk => pgpRxClkLoc, -- RecClk fed back, optionally though MMCM + pgpRxClk => pgpRxClkLoc, -- RecClk fed back, optionally through MMCM pgpRxMmcmReset => pgpRxMmcmReset, pgpRxMmcmLocked => pgpRxMmcmLocked, -- Non VC Rx Signals diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd index aa1b53e951..3b840227ee 100755 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd @@ -222,7 +222,7 @@ begin rxStatusSync.remLinkData <= pgpRxOut.remLinkData; end generate; - -- Errror counters and non counted values + -- Error counters and non counted values U_RxError : entity surf.SyncStatusVector generic map ( TPD_G => TPD_G, @@ -362,7 +362,7 @@ begin dout => txStatusSync.txFcWordLast); - -- Errror counters and non counted values + -- Error counters and non counted values U_TxError : entity surf.SyncStatusVector generic map ( TPD_G => TPD_G, diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcPkg.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcPkg.vhd index fd655a0e9e..b140713f6e 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcPkg.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcPkg.vhd @@ -72,9 +72,9 @@ package Pgp2fcPkg is linkReady : sl; -- Local side has link frameRx : sl; -- A good frame was received frameRxErr : sl; -- An errored frame was received - cellError : sl; -- A cell error has occured - linkDown : sl; -- A link down event has occured - linkError : sl; -- A link error has occured + cellError : sl; -- A cell error has occurred + linkDown : sl; -- A link down event has occurred + linkError : sl; -- A link error has occurred fcValid : sl; -- Fast Control word received fcError : sl; -- Fast Control word received with error fcWord : slv(MAX_FC_BITS_C-1 downto 0); -- Fast control word diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxCell.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxCell.vhd index bbefa1611c..add84e5169 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxCell.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxCell.vhd @@ -42,7 +42,7 @@ entity Pgp2fcRxCell is pgpRxLinkReady : in sl; -- Local side has link -- Cell Error, one pulse per error - pgpRxCellError : out sl; -- A cell error has occured + pgpRxCellError : out sl; -- A cell error has occurred -- Interface to PHY Logic cellRxPause : in sl; -- Cell data pause @@ -699,7 +699,7 @@ begin end process; - -- Update buffer status on successfull cell reception + -- Update buffer status on successful cell reception process (pgpRxClk) begin if rising_edge(pgpRxClk) then diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxPhy.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxPhy.vhd index 0111c065a8..42248f862d 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxPhy.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxPhy.vhd @@ -38,8 +38,8 @@ entity Pgp2fcRxPhy is pgpRxLinkReady : out sl; -- Local side has link -- Error Flags, one pulse per event - pgpRxLinkDown : out sl := '0'; -- A link down event has occured - pgpRxLinkError : out sl := '0'; -- A link error has occured + pgpRxLinkDown : out sl := '0'; -- A link down event has occurred + pgpRxLinkError : out sl := '0'; -- A link error has occurred -- Fast control interface fcValid : out sl := '0'; diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxCell.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxCell.vhd index aaa027e49d..ee12a63e2e 100755 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxCell.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxCell.vhd @@ -409,7 +409,7 @@ begin -- Go back to idle nxtState <= IDLE_S; - -- Send first charactor of cell, assert ready + -- Send first character of cell, assert ready when SOC_S => cellCntRst <= '1'; nxtFrameTxReady <= not intTimeout; diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxSched.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxSched.vhd index f7823f38e9..a9c63d76db 100755 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxSched.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxSched.vhd @@ -88,7 +88,7 @@ architecture Pgp2fcTxSched of Pgp2fcTxSched is signal vcTimeout : slv(3 downto 0) := (others => '0'); signal gateTxValid : slv(3 downto 0); - -- Schedular state + -- Scheduler state constant ST_RST_C : slv(2 downto 0) := "001"; constant ST_ARB_C : slv(2 downto 0) := "010"; constant ST_CELL_C : slv(2 downto 0) := "011"; diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd index 00b5e3d48b..ec6f10188e 100755 --- a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd @@ -515,7 +515,7 @@ begin DIV => "000", O => rxOutClkB); - -- Cant seem to use txoutclk to drive txusrclk without placement errors + -- Can't seem to use txoutclk to drive txusrclk without placement errors -- if one does not use the userRefClk for the txOutClk, placement errors occur -- TXOUTCLK_BUFG_GT : BUFG_GT -- port map ( diff --git a/protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7Wrapper.vhd b/protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7Wrapper.vhd index 3eca2b52b3..f43445a28f 100644 --- a/protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7Wrapper.vhd +++ b/protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7Wrapper.vhd @@ -436,7 +436,7 @@ begin pgpRxReset => pgpRxReset, --extRst, pgpRxRecClk => pgpRxRecClk, pgpRxRecClkRst => pgpRxRecClkRst, - pgpRxClk => pgpRxClkLoc, -- RecClk fed back, optionally though MMCM + pgpRxClk => pgpRxClkLoc, -- RecClk fed back, optionally through MMCM pgpRxMmcmReset => pgpRxMmcmReset, pgpRxMmcmLocked => pgpRxMmcmLocked, -- Non VC Rx Signals diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd index ccbd0394b9..89b5c0359f 100755 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd @@ -515,7 +515,7 @@ begin DIV => "000", O => rxOutClkB); - -- Cant seem to use txoutclk to drive txusrclk without placement errors + -- Can't seem to use txoutclk to drive txusrclk without placement errors -- if one does not use the userRefClk for the txOutClk, placement errors occur -- TXOUTCLK_BUFG_GT : BUFG_GT -- port map ( diff --git a/protocols/pgp/pgp3/core/rtl/Pgp3AxiL.vhd b/protocols/pgp/pgp3/core/rtl/Pgp3AxiL.vhd index 7d5fa43c11..41e40e029e 100644 --- a/protocols/pgp/pgp3/core/rtl/Pgp3AxiL.vhd +++ b/protocols/pgp/pgp3/core/rtl/Pgp3AxiL.vhd @@ -212,7 +212,7 @@ begin dout(47 downto 0) => rxStatusSync.rxOpCodeDataLast, dout(50 downto 48) => rxStatusSync.rxOpCodeNumberLast); - -- Errror counters and non counted values + -- Error counters and non counted values U_RxError : entity surf.SyncStatusVector generic map ( TPD_G => TPD_G, @@ -429,7 +429,7 @@ begin dout(47 downto 0) => txStatusSync.txOpCodeDataLast, dout(50 downto 48) => txStatusSync.txOpCodeNumberLast); - -- Errror counters and non counted values + -- Error counters and non counted values U_TxError : entity surf.SyncStatusVector generic map ( TPD_G => TPD_G, diff --git a/protocols/pgp/pgp3/core/rtl/Pgp3Pkg.vhd b/protocols/pgp/pgp3/core/rtl/Pgp3Pkg.vhd index 4cdffdfa83..0cf3cb9239 100644 --- a/protocols/pgp/pgp3/core/rtl/Pgp3Pkg.vhd +++ b/protocols/pgp/pgp3/core/rtl/Pgp3Pkg.vhd @@ -160,9 +160,9 @@ package Pgp3Pkg is linkReady : sl; -- locRxLinkReady frameRx : sl; -- A good frame was received frameRxErr : sl; -- An errored frame was received - cellError : sl; -- A cell error has occured - linkDown : sl; -- A link down event has occured - linkError : sl; -- A link error has occured + cellError : sl; -- A cell error has occurred + linkDown : sl; -- A link down event has occurred + linkError : sl; -- A link error has occurred opCodeEn : sl; -- Opcode valid opCodeNumber : slv(2 downto 0); -- Opcode number opCodeData : slv(47 downto 0); -- Opcode data diff --git a/protocols/pgp/pgp3/core/rtl/Pgp3RxEb.vhd b/protocols/pgp/pgp3/core/rtl/Pgp3RxEb.vhd index aa0a106a81..e002c7141c 100644 --- a/protocols/pgp/pgp3/core/rtl/Pgp3RxEb.vhd +++ b/protocols/pgp/pgp3/core/rtl/Pgp3RxEb.vhd @@ -31,7 +31,7 @@ entity Pgp3RxEb is phyRxClk : in sl; phyRxRst : in sl; phyRxValid : in sl; - phyRxData : in slv(63 downto 0); -- Unscrabled data from the phy + phyRxData : in slv(63 downto 0); -- Unscrambled data from the phy phyRxHeader : in slv(1 downto 0); -- User Transmit interface @@ -89,7 +89,7 @@ begin -- Reset if (phyRxRst = '1') then - -- Maintain save behavior before the remLinkData update (not reseting fifoIn or fifoWrEn) + -- Maintain same behavior before the remLinkData update (not resetting fifoIn or fifoWrEn) v.remLinkData := (others => '0'); end if; diff --git a/protocols/pgp/pgp3/core/rtl/Pgp3RxGearboxAligner.vhd b/protocols/pgp/pgp3/core/rtl/Pgp3RxGearboxAligner.vhd index 64dd849114..6db28bf236 100755 --- a/protocols/pgp/pgp3/core/rtl/Pgp3RxGearboxAligner.vhd +++ b/protocols/pgp/pgp3/core/rtl/Pgp3RxGearboxAligner.vhd @@ -5,7 +5,7 @@ ------------------------------------------------------------------------------- -- Description: Aligns a GT RX gearbox. -- After reset, require GOOD_COUNT_C consecutive valid headers to lock. --- Once locked, require BAD_COUNT_C invalid headers withing GOOD_COUNT_C +-- Once locked, require BAD_COUNT_C invalid headers within GOOD_COUNT_C -- total headers to break the lock. ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. diff --git a/protocols/pgp/pgp3/core/rtl/Pgp3RxProtocol.vhd b/protocols/pgp/pgp3/core/rtl/Pgp3RxProtocol.vhd index 5f155108d2..6d7f06b783 100644 --- a/protocols/pgp/pgp3/core/rtl/Pgp3RxProtocol.vhd +++ b/protocols/pgp/pgp3/core/rtl/Pgp3RxProtocol.vhd @@ -47,7 +47,7 @@ entity Pgp3RxProtocol is remRxLinkReady : out sl; locRxLinkReady : out sl; - -- Received data from descramber/CC FIFO + -- Received data from descrambler/CC FIFO phyRxActive : in sl; protRxValid : in sl; protRxPhyInit : out sl; @@ -138,7 +138,7 @@ begin else -- Linked - -- Increment count on every incomming word + -- Increment count on every incoming word -- reset when IDLE or SOF or SOC seen v.count := r.count + 1; @@ -182,7 +182,7 @@ begin if (btf = PGP3_USER_C(i)) then v.pgpRxOut.opCodeNumber := toSlv(i, 3); v.pgpRxOut.opCodeData := protRxData(PGP3_USER_OPCODE_FIELD_C); - -- Verify checksun + -- Verify checksum if (protRxData(PGP3_USER_CHECKSUM_FIELD_C) = opCodeChecksum) then v.pgpRxOut.opCodeEn := '1'; else diff --git a/protocols/pgp/pgp3/core/rtl/Pgp3Tx.vhd b/protocols/pgp/pgp3/core/rtl/Pgp3Tx.vhd index 03da2b9a37..e885db3c51 100644 --- a/protocols/pgp/pgp3/core/rtl/Pgp3Tx.vhd +++ b/protocols/pgp/pgp3/core/rtl/Pgp3Tx.vhd @@ -141,7 +141,7 @@ begin end generate; -- Use synchronized remote status to disable channels from mux selection - -- All flow control overriden by pgpTxIn 'disable' and 'flowCntlDis' + -- All flow control overridden by pgpTxIn 'disable' and 'flowCntlDis' DISABLE_SEL : process (pgpTxIn, syncRemRxFifoCtrl) is begin for i in NUM_VC_G-1 downto 0 loop @@ -155,7 +155,7 @@ begin end loop; end process; - -- Multiplex the incomming tx streams with interleaving + -- Multiplex the incoming tx streams with interleaving U_AxiStreamMux_1 : entity surf.AxiStreamMux generic map ( TPD_G => TPD_G, @@ -199,7 +199,7 @@ begin mAxisSlave => packetizedTxSlave); -- [in] -- Feed packets into PGP TX Protocol engine - -- Translates Packetizer2 frames, status, and opcodes into unscrambled 64b66b charachters + -- Translates Packetizer2 frames, status, and opcodes into unscrambled 64b66b characters U_Pgp3TxProtocol_1 : entity surf.Pgp3TxProtocol generic map ( TPD_G => TPD_G, diff --git a/protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUs.vhd b/protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUs.vhd index 32866825f9..e1a77aa9de 100644 --- a/protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUs.vhd +++ b/protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUs.vhd @@ -3,7 +3,7 @@ ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- --- Description: PGPv3 GTH Ultrscale Core Module +-- Description: PGPv3 GTH Ultrascale Core Module ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4AxiL.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4AxiL.vhd index e1bea5d2fb..2483a151d7 100755 --- a/protocols/pgp/pgp4/core/rtl/Pgp4AxiL.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4AxiL.vhd @@ -216,7 +216,7 @@ begin -- Uptime counter --------------------------------- - -- Check for timout + -- Check for timeout if r.timer = TIMEOUT_1HZ_C then -- Reset the timer diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd index 826ba2461d..5bf7663c76 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd @@ -109,7 +109,7 @@ begin -- Reset if (RST_ASYNC_G = false and phyRxRst = RST_POLARITY_G) then - -- Maintain save behavior before the remLinkData update (not reseting fifoIn or fifoWrEn) + -- Maintain same behavior before the remLinkData update (not resetting fifoIn or fifoWrEn) v.remLinkData := (others => '0'); end if; diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4Tx.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4Tx.vhd index 6f422d86b1..9faa94cbcb 100755 --- a/protocols/pgp/pgp4/core/rtl/Pgp4Tx.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4Tx.vhd @@ -220,7 +220,7 @@ begin mAxisSlave => packetizedTxSlave); -- [in] -- Feed packets into PGP TX Protocol engine - -- Translates Packetizer2 frames, status, and opcodes into unscrambled 64b66b charachters + -- Translates Packetizer2 frames, status, and opcodes into unscrambled 64b66b characters U_Pgp4TxProtocol_1 : entity surf.Pgp4TxProtocol generic map ( TPD_G => TPD_G, diff --git a/protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUs.vhd b/protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUs.vhd index b688b46631..5cdc24f414 100644 --- a/protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUs.vhd +++ b/protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUs.vhd @@ -3,7 +3,7 @@ ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- --- Description: PGPv4 GTH Ultrscale Core Module +-- Description: PGPv4 GTH Ultrascale Core Module ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the diff --git a/protocols/rssi/v1/rtl/RssiAxiLiteRegItf.vhd b/protocols/rssi/v1/rtl/RssiAxiLiteRegItf.vhd index f3f479fda8..6cd31dcd97 100644 --- a/protocols/rssi/v1/rtl/RssiAxiLiteRegItf.vhd +++ b/protocols/rssi/v1/rtl/RssiAxiLiteRegItf.vhd @@ -47,13 +47,13 @@ -- bit(5) : Connection to peer timed out -- bit(6) : Parameters from peer rejected (Client) or new proposed(Server) -- 0x11 (R)- Number of valid segments [31:0]: --- The value rests to 0 when new connection open is requested. +-- The value resets to 0 when new connection open is requested. -- 0x12 (R)- Number of dropped segments [31:0]: --- The value rests to 0 when new connection open is requested. +-- The value resets to 0 when new connection open is requested. -- 0x13 (R)- Counts all retransmission requests within the active connection [31:0]: --- The value rests to 0 when new connection open is requested. +-- The value resets to 0 when new connection open is requested. -- 0x14 (R)- Counts all reconnections from reset [31:0]: --- The value rests to 0 when module is reset. +-- The value resets to 0 when module is reset. ------------------------------------------------------------------------------ -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the diff --git a/protocols/rssi/v1/rtl/RssiHeaderReg.vhd b/protocols/rssi/v1/rtl/RssiHeaderReg.vhd index dd5ed77b74..d4825c7b56 100644 --- a/protocols/rssi/v1/rtl/RssiHeaderReg.vhd +++ b/protocols/rssi/v1/rtl/RssiHeaderReg.vhd @@ -57,7 +57,7 @@ entity RssiHeaderReg is -- Header values txSeqN_i : in slv(7 downto 0); -- Sequence number of the current packet - rxAckN_i : in slv(7 downto 0); -- Acknowledgment number of the recived packet handelled by receiver + rxAckN_i : in slv(7 downto 0); -- Acknowledgment number of the received packet handled by receiver -- Negotiated or from GENERICS headerValues_i : in RssiParamType; diff --git a/protocols/rssi/v1/rtl/RssiRxFsm.vhd b/protocols/rssi/v1/rtl/RssiRxFsm.vhd index 6c4e88010f..b70f44262f 100644 --- a/protocols/rssi/v1/rtl/RssiRxFsm.vhd +++ b/protocols/rssi/v1/rtl/RssiRxFsm.vhd @@ -22,7 +22,7 @@ -- 1. increment the in order SEQn -- 2. save seqN, type, and occupied to the window buffer at current rxBufferAddr -- 3. increment rxBufferAddr --- - DROP Just report dropped packet and got back to WAIT_SOF +-- - DROP Just report dropped packet and go back to WAIT_SOF -- Receiver side FSM. Send data to App side. -- - CHECK_BUFFER and DATA Send the data frame to the Application -- when the data at the next txSegmentAddr is ready. @@ -150,7 +150,7 @@ architecture rtl of RssiRxFsm is type RegType is record - -- Resception buffer window + -- Reception buffer window windowArray : WindowTypeArray(0 to 2 ** WINDOW_ADDR_SIZE_G-1); -- Transport side FSM (Receive and check segments) @@ -251,7 +251,7 @@ architecture rtl of RssiRxFsm is tspState => WAIT_SOF_S, rxTspState => (others => '0'), - -- Application side FSM (Send segments when received next in odrer received) + -- Application side FSM (Send segments when received next in order received) ----------------------------------------------------------- txBufferAddr => (others => '0'), txSegmentAddr => (others => '0'), @@ -325,7 +325,7 @@ begin v.chkEn := '1'; v.chkStb := '1'; - -- When SOF has been received dessert ready until package is checked + -- When SOF has been received deassert ready until package is checked v.tspSsiSlave := SSI_SLAVE_RDY_C; -- If the packet is longer than one set the data flag @@ -635,7 +635,7 @@ begin -- These flags will hold if not overridden v.appSsiMaster := SSI_MASTER_INIT_C; - -- Pipeline incomming slave + -- Pipeline incoming slave v.appSsiSlave := appSsiSlave_i; case r.appState is diff --git a/protocols/rssi/v1/rtl/RssiTxFsm.vhd b/protocols/rssi/v1/rtl/RssiTxFsm.vhd index 6608f94373..61449bf991 100644 --- a/protocols/rssi/v1/rtl/RssiTxFsm.vhd +++ b/protocols/rssi/v1/rtl/RssiTxFsm.vhd @@ -20,7 +20,7 @@ -- - If it does not find the SEQ number it reports Ack Error, -- - Goes back to IDLE. -- Transport side FSM. Send and resend various segments to Transport side. --- - INIT Initializes seqN to initSeqN. Waits until new connection requested. ConnFSM goin out od Closed state. +-- - INIT Initializes seqN to initSeqN. Waits until new connection requested. ConnFSM going out of Closed state. -- - DISS_CONN allows sending SYN, ACK, or RST segments. Goes to CONN when connection becomes active. -- - CONN allows sending DATA, NULL, ACK, or RST segments. -- In Resend procedure the FSM resends all the unacknowledged (DATA, NULL, RST) segments in the buffer window. diff --git a/protocols/saci/saci1/rtl/SaciSlaveOld.vhd b/protocols/saci/saci1/rtl/SaciSlaveOld.vhd index c02ede2a12..7a16284092 100755 --- a/protocols/saci/saci1/rtl/SaciSlaveOld.vhd +++ b/protocols/saci/saci1/rtl/SaciSlaveOld.vhd @@ -118,7 +118,7 @@ begin begin rVar := r; - -- Defualt values + -- Default values -- Overridden in some states rVar.exec := '0'; rVar.saciRsp := '0'; diff --git a/protocols/srp/rtl/SrpV3Core.vhd b/protocols/srp/rtl/SrpV3Core.vhd index 57d1f2f91e..2810c0c7e0 100755 --- a/protocols/srp/rtl/SrpV3Core.vhd +++ b/protocols/srp/rtl/SrpV3Core.vhd @@ -444,7 +444,7 @@ begin ------------------------------------------------------------------------------- - -- If no error found above, procede with read or write request + -- If no error found above, proceed with read or write request if (v.state /= FOOTER_S) then -- Issue an SRP request v.srpReq.request := '1'; @@ -490,7 +490,7 @@ begin -- Count each txn -- If tLast before cntSize, eofe - -- if cntSize reached and no tlast, blead read data, eofe + -- if cntSize reached and no tlast, bleed read data, eofe v.txnCnt := r.txnCnt + 1; if r.txnCnt = r.srpReq.reqSize(31 downto 2) and srpRdMasterInt.tLast = '1' then -- Done when reqSize and tlast @@ -555,7 +555,7 @@ begin -- Count each txn -- If tLast before cntSize, frameError - -- if cntSize reached and no tlast, blead write data, frame error + -- if cntSize reached and no tlast, bleed write data, frame error v.txnCnt := r.txnCnt + 1; if r.txnCnt = r.srpReq.reqSize(31 downto 2) and rxMaster.tLast = '1' then -- Done when reqSize reached and tlast diff --git a/protocols/ssi/rtl/SsiFifo.vhd b/protocols/ssi/rtl/SsiFifo.vhd index cba087f110..211db98916 100755 --- a/protocols/ssi/rtl/SsiFifo.vhd +++ b/protocols/ssi/rtl/SsiFifo.vhd @@ -52,7 +52,7 @@ entity SsiFifo is MEMORY_TYPE_G : string := "block"; -- Internal FIFO width select, "WIDE", "NARROW" or "CUSTOM" -- WIDE uses wider of slave / master. NARROW uses narrower. - -- CUSOTM uses passed FIFO_DATA_WIDTH_G + -- CUSTOM uses passed FIFO_DATA_WIDTH_G INT_WIDTH_SELECT_G : string := "WIDE"; INT_DATA_WIDTH_G : positive := 16; -- If VALID_THOLD_G /=1, FIFO that stores on tLast transaction can be smaller. diff --git a/protocols/sugoi/rtl/SugoiManagerCore.vhd b/protocols/sugoi/rtl/SugoiManagerCore.vhd index e3c4bc6ebe..98b5d91eba 100644 --- a/protocols/sugoi/rtl/SugoiManagerCore.vhd +++ b/protocols/sugoi/rtl/SugoiManagerCore.vhd @@ -223,7 +223,7 @@ begin TPD_G => TPD_G, RST_POLARITY_G => '1', -- active HIGH reset RST_ASYNC_G => RST_ASYNC_G, - -- FLOW_CTRL_EN_G => true, -- placeholder incase FLOW_CTRL_EN_G is added in the future + -- FLOW_CTRL_EN_G => true, -- placeholder in case FLOW_CTRL_EN_G is added in the future NUM_BYTES_G => 1) port map ( -- Clock and Reset diff --git a/protocols/uart/rtl/UartAxiLiteMasterFsm.vhd b/protocols/uart/rtl/UartAxiLiteMasterFsm.vhd index a7fb6d468a..60bfa47a62 100644 --- a/protocols/uart/rtl/UartAxiLiteMasterFsm.vhd +++ b/protocols/uart/rtl/UartAxiLiteMasterFsm.vhd @@ -150,7 +150,7 @@ begin -- Blank lines ignored -- Extra words ignored. - -- Auto clear uartTxValid upton uartTxReady + -- Auto clear uartTxValid upon uartTxReady if (uartTxReady = '1') then v.uartTxValid := '0'; end if; @@ -246,7 +246,7 @@ begin when WAIT_EOL_S => -- Issue AXIL TXN once EOL seen - -- Any other charachters are echo'd but otherwise ignored + -- Any other characters are echo'd but otherwise ignored if (uartRxValid = '1') then uartTx(uartRxData); if (isEOL(uartRxData)) then diff --git a/python/surf/axi/_AxiLiteMasterProxy.py b/python/surf/axi/_AxiLiteMasterProxy.py index d26ad2b12a..790a059bc0 100644 --- a/python/surf/axi/_AxiLiteMasterProxy.py +++ b/python/surf/axi/_AxiLiteMasterProxy.py @@ -139,7 +139,7 @@ def _pollWorker(self): resp = self.Resp.get(read=True) #print(f'Resp: {resp}') if resp != 0: - transaction.error(f'AXIL tranaction failed with RESP: {resp}') + transaction.error(f'AXIL transaction failed with RESP: {resp}') # Finish the transaction elif self.Rnw.valueDisp() == 'Write': diff --git a/python/surf/axi/_AxiRingBuffer.py b/python/surf/axi/_AxiRingBuffer.py index 46e01dabc6..74b6d8407d 100755 --- a/python/surf/axi/_AxiRingBuffer.py +++ b/python/surf/axi/_AxiRingBuffer.py @@ -138,7 +138,7 @@ def __init__(self, **kwargs): self.add(pr.RemoteCommand( name = 'SoftTrig', - description = 'Software trigging ring buffer', + description = 'Software triggering ring buffer', offset = 0xF8, bitSize = 1, bitOffset = 0, diff --git a/python/surf/axi/_AxiVersion.py b/python/surf/axi/_AxiVersion.py index 4ffe087484..1f865702fc 100644 --- a/python/surf/axi/_AxiVersion.py +++ b/python/surf/axi/_AxiVersion.py @@ -170,7 +170,7 @@ def UserRst(): self.add(pr.RemoteVariable( name = 'DeviceId', - description = 'Device Identification (configued by generic)', + description = 'Device Identification (configured by generic)', offset = 0x500, bitSize = 32, bitOffset = 0x00, @@ -273,7 +273,7 @@ def parseBuildStamp(var,read): self.add(pr.LocalCommand( name = 'PrintStatus', function = self.getStatus, - hidden = True, # Indended for use in VirtualClient + hidden = True, # Intended for use in VirtualClient )) def hardReset(self): diff --git a/python/surf/devices/analog_devices/_Ad9249.py b/python/surf/devices/analog_devices/_Ad9249.py index 7694c164fb..67bffc451e 100644 --- a/python/surf/devices/analog_devices/_Ad9249.py +++ b/python/surf/devices/analog_devices/_Ad9249.py @@ -204,7 +204,7 @@ def __init__(self, bitSize = 1, bitOffset = 0, enum = { - 1: 'Twos Compliment', + 1: 'Twos Complement', 0: 'Offset Binary', }, )) @@ -597,9 +597,9 @@ def readBlocks(self, *, recurse=True, variable=None, checkEach=False, index=-1, class AdcTester(pr.Device): - def __init__(self, **kwargs): + def __init__(self, description='ADC Pattern Tester Registers', **kwargs): """Create AdcTester""" - super().__init__(description='ADC Pattern Tester Regsisters', **kwargs) + super().__init__(description=description, **kwargs) # Creation. memBase is either the register bus server (srp, rce mapped memory, etc) or the device which # contains this object. In most cases the parent and memBase are the same but they can be diff --git a/python/surf/devices/analog_devices/_Ad9681.py b/python/surf/devices/analog_devices/_Ad9681.py index 8c153e5f44..7a0618e299 100644 --- a/python/surf/devices/analog_devices/_Ad9681.py +++ b/python/surf/devices/analog_devices/_Ad9681.py @@ -195,7 +195,7 @@ def __init__(self, bitSize = 1, bitOffset = 0, enum = { - 1: 'Twos Compliment', + 1: 'Twos Complement', 0: 'Offset Binary', }, )) diff --git a/python/surf/devices/analog_devices/_Adt7420.py b/python/surf/devices/analog_devices/_Adt7420.py index 152f3256b2..32bc86daa3 100644 --- a/python/surf/devices/analog_devices/_Adt7420.py +++ b/python/surf/devices/analog_devices/_Adt7420.py @@ -1,6 +1,6 @@ #!/usr/bin/env python #----------------------------------------------------------------------------- -# Title : PyRogue Analod Deviced ADT7420 +# Title : PyRogue Analog Devices ADT7420 #----------------------------------------------------------------------------- # File : _Adt7420.py # Created : 2019-07-17 diff --git a/python/surf/devices/linear/_Ltc2945.py b/python/surf/devices/linear/_Ltc2945.py index 5330ce6895..22ed7d2670 100644 --- a/python/surf/devices/linear/_Ltc2945.py +++ b/python/surf/devices/linear/_Ltc2945.py @@ -391,7 +391,7 @@ def __init__(self, **kwargs): self.add(pr.RemoteVariable( name = 'MaxVinThresholdLsb', - description = 'Maximum ADC VIN Threshold LSB Dto Generate Alert', + description = 'Maximum ADC VIN Threshold LSB to Generate Alert', offset = (0x25 << 2), bitSize = 8, bitOffset = 0, @@ -491,7 +491,7 @@ def __init__(self, **kwargs): self.add(pr.RemoteVariable( name = 'MaxAdinThresholdLsb', - description = 'Maximum ADIN Threshold LSB Dto Generate Alert', + description = 'Maximum ADIN Threshold LSB to Generate Alert', offset = (0x2F << 2), bitSize = 8, bitOffset = 0, diff --git a/python/surf/devices/nxp/_Sa56004x.py b/python/surf/devices/nxp/_Sa56004x.py index 608ec42df9..8e3cd2a999 100644 --- a/python/surf/devices/nxp/_Sa56004x.py +++ b/python/surf/devices/nxp/_Sa56004x.py @@ -32,7 +32,7 @@ def getTempReg(var, read): x = var.dependencies[0].get(read=read) sign = x >> 7 # Get the sign bit x &= 0x7F # mask off sign bit - x = float(x)# Covert to degC + x = float(x)# Convert to degC if (sign==1): x *= -1.0 return int(x) diff --git a/python/surf/devices/silabs/_Si5324.py b/python/surf/devices/silabs/_Si5324.py index 82b4eea99c..3a5e047650 100644 --- a/python/surf/devices/silabs/_Si5324.py +++ b/python/surf/devices/silabs/_Si5324.py @@ -75,7 +75,7 @@ def LoadTxtFile(arg): data = int(data,16), ) - # Update local RemoteVariables and verify conflagration + # Update local RemoteVariables and verify configuration self.readBlocks(recurse=True) self.checkBlocks(recurse=True) diff --git a/python/surf/devices/silabs/_Si5326.py b/python/surf/devices/silabs/_Si5326.py index c742c447ee..8ef41d98a5 100644 --- a/python/surf/devices/silabs/_Si5326.py +++ b/python/surf/devices/silabs/_Si5326.py @@ -75,7 +75,7 @@ def LoadTxtFile(arg): data = int(data,16), ) - # Update local RemoteVariables and verify conflagration + # Update local RemoteVariables and verify configuration self.readBlocks(recurse=True) self.checkBlocks(recurse=True) diff --git a/python/surf/devices/silabs/_Si5345Lite.py b/python/surf/devices/silabs/_Si5345Lite.py index c302009e8f..44dd2bd1d9 100644 --- a/python/surf/devices/silabs/_Si5345Lite.py +++ b/python/surf/devices/silabs/_Si5345Lite.py @@ -64,7 +64,7 @@ def LoadCsvFile(arg): data = int(row[1],16), ) - # Update local RemoteVariables and verify conflagration + # Update local RemoteVariables and verify configuration self.readBlocks(recurse=True) self.checkBlocks(recurse=True) diff --git a/python/surf/devices/silabs/_Si5345Pages.py b/python/surf/devices/silabs/_Si5345Pages.py index 5f5987a8d0..748f236f5d 100644 --- a/python/surf/devices/silabs/_Si5345Pages.py +++ b/python/surf/devices/silabs/_Si5345Pages.py @@ -1051,7 +1051,7 @@ def __init__(self, self.MyLinkVariable( name = 'DEVICE_READY', - description = 'Ready Only byte to indicate device is ready. When read data is 0x0F one can safely read/write registers. This register is repeated on every page therefore a page write is not ever required to read the DEVICE_READY status.', + description = 'Read Only byte to indicate device is ready. When read data is 0x0F one can safely read/write registers. This register is repeated on every page therefore a page write is not ever required to read the DEVICE_READY status.', offset = (0xFE << 2), bitSize = 8, bitOffset = 0, diff --git a/python/surf/devices/silabs/_Si5394Lite.py b/python/surf/devices/silabs/_Si5394Lite.py index d239fe924b..9141f5fbde 100644 --- a/python/surf/devices/silabs/_Si5394Lite.py +++ b/python/surf/devices/silabs/_Si5394Lite.py @@ -72,7 +72,7 @@ def LoadCsvFile(arg): data = int(row[1],16), ) - # Update local RemoteVariables and verify conflagration + # Update local RemoteVariables and verify configuration self.readBlocks(recurse=True) self.checkBlocks(recurse=True) diff --git a/python/surf/devices/ti/_Ads54J54.py b/python/surf/devices/ti/_Ads54J54.py index 97ce0f2542..8491e8495f 100755 --- a/python/surf/devices/ti/_Ads54J54.py +++ b/python/surf/devices/ti/_Ads54J54.py @@ -94,7 +94,7 @@ def __init__(self, **kwargs): self.add(pr.RemoteVariable( name = "DEC_EN_CD", - description = "Enables dcimation filter for channel CD", + description = "Enables decimation filter for channel CD", offset = (4*0x00), bitSize = 1, bitOffset = 10, diff --git a/python/surf/devices/ti/_Lmk61e2.py b/python/surf/devices/ti/_Lmk61e2.py index a5536807e0..f1abc2beba 100644 --- a/python/surf/devices/ti/_Lmk61e2.py +++ b/python/surf/devices/ti/_Lmk61e2.py @@ -336,7 +336,7 @@ def __init__(self, **kwargs): self.add(pr.RemoteVariable( name = 'NVMSCRC', - description = 'The NVMSCRC register holds the Stored CRC (Cyclic Redundancy Check) byte that has been retreived from onchip EEPROM', + description = 'The NVMSCRC register holds the Stored CRC (Cyclic Redundancy Check) byte that has been retrieved from onchip EEPROM', offset = (47 << 2), bitSize = 8, bitOffset = 0, diff --git a/python/surf/devices/ti/_Tmp461.py b/python/surf/devices/ti/_Tmp461.py index d2c094b446..d70c357fa1 100644 --- a/python/surf/devices/ti/_Tmp461.py +++ b/python/surf/devices/ti/_Tmp461.py @@ -24,7 +24,7 @@ def getTempReg(var, read): x = var.dependencies[0].get(read=read) sign = x >> 7 # Get the sign bit x &= 0x7F # mask off sign bit - x = float(x)# Covert to degC + x = float(x)# Convert to degC if (sign==1): x *= -1.0 return int(x) diff --git a/python/surf/devices/transceivers/_Qsfp.py b/python/surf/devices/transceivers/_Qsfp.py index ca973a8477..5234780ae2 100644 --- a/python/surf/devices/transceivers/_Qsfp.py +++ b/python/surf/devices/transceivers/_Qsfp.py @@ -814,14 +814,14 @@ def __init__(self, advDebug=False, **kwargs): name = 'UpperPage00h', memBase = self.proxy, advDebug = advDebug, - offset = (0+1)<<10, # Page00 plus 1 mem addres region offset + offset = (0+1)<<10, # Page00 plus 1 mem address region offset )) self.add(transceivers.QsfpUpperPage03h( name = 'UpperPage03h', memBase = self.proxy, advDebug = advDebug, - offset = (3+1)<<10, # Page03 plus 1 mem addres region offset + offset = (3+1)<<10, # Page03 plus 1 mem address region offset )) def add(self, node): diff --git a/python/surf/protocols/jesd204b/_JesdRx.py b/python/surf/protocols/jesd204b/_JesdRx.py index 1284fc3412..a2af67eb9e 100644 --- a/python/surf/protocols/jesd204b/_JesdRx.py +++ b/python/surf/protocols/jesd204b/_JesdRx.py @@ -130,7 +130,7 @@ def __init__( self.add(pr.RemoteVariable( name = "LinkErrMask", - description = "Mask Enable the errors that are required to brake the link. bit 5-0: positionErr - s_bufOvf - s_bufUnf - dispErr - decErr - s_alignErr", + description = "Mask Enable the errors that are required to break the link. bit 5-0: positionErr - s_bufOvf - s_bufUnf - dispErr - decErr - s_alignErr", offset = 0x14, bitSize = 6, bitOffset = 0x00, @@ -202,7 +202,7 @@ def __init__( self.add(pr.RemoteVariable( name = "AlignErr", - description = "Jesd Character Alignment Error. The control characters in the data are missaligned. This error will trigger JESD re-synchronization.", + description = "Jesd Character Alignment Error. The control characters in the data are misaligned. This error will trigger JESD re-synchronization.", offset = range(0x40,0x40+4*numRxLanes,4), bitSize = 1, bitOffset = 2, @@ -212,7 +212,7 @@ def __init__( self.add(pr.RemoteVariable( name = "nSync", - description = "Synchronisation request. 0 - Not synchronised. 1 - Indicades that code group synchronization has been completed.", + description = "Synchronisation request. 0 - Not synchronised. 1 - Indicates that code group synchronization has been completed.", offset = range(0x40,0x40+4*numRxLanes,4), bitSize = 1, bitOffset = 3, @@ -221,7 +221,7 @@ def __init__( self.add(pr.RemoteVariable( name = "RxBuffUfl", - description = "Jesd sync fifo buffer undeflow. This error will trigger JESD re-synchronization.", + description = "Jesd sync fifo buffer underflow. This error will trigger JESD re-synchronization.", offset = range(0x40,0x40+4*numRxLanes,4), bitSize = 1, bitOffset = 4, @@ -322,7 +322,7 @@ def __init__( if (debug): self.addRemoteVariables( name = "ThresholdLow", - description = "Threshold_Low. Debug funtionality. Threshold for generating a digital signal from the ADC data.", + description = "Threshold_Low. Debug functionality. Threshold for generating a digital signal from the ADC data.", offset = 0xC0, bitSize = 16, bitOffset = 0x00, @@ -334,7 +334,7 @@ def __init__( self.addRemoteVariables( name = "ThresholdHigh", - description = "Threshold_High. Debug funtionality. Threshold for generating a digital signal from the ADC data.", + description = "Threshold_High. Debug functionality. Threshold for generating a digital signal from the ADC data.", offset = 0xC0, bitSize = 16, bitOffset = 16, @@ -346,7 +346,7 @@ def __init__( self.addRemoteVariables( name = "StatusValidCnt", - description = "StatusValidCnt. Shows stability of JESD lanes. Counts number of JESD re-syncronisations.", + description = "StatusValidCnt. Shows stability of JESD lanes. Counts number of JESD re-synchronisations.", offset = 0x100, bitSize = 32, bitOffset = 0x00, diff --git a/python/surf/protocols/jesd204b/_JesdTx.py b/python/surf/protocols/jesd204b/_JesdTx.py index 65bc48af49..03c9c82ad0 100644 --- a/python/surf/protocols/jesd204b/_JesdTx.py +++ b/python/surf/protocols/jesd204b/_JesdTx.py @@ -98,7 +98,7 @@ def __init__( self.add(pr.RemoteVariable( name = "InvertSync", - description = "InvertSync. Invert sync input (the AMC card schematics should be checkes if inverted). ", + description = "InvertSync. Invert sync input (the AMC card schematics should be checked if inverted). ", offset = 0x10, bitSize = 1, bitOffset = 0x04, @@ -244,7 +244,7 @@ def __init__( self.add(pr.RemoteVariable( name = "nSync", - description = "nSync. 0 - Not synchronised. 1 - Indicades that code group synchronization has been completed.", + description = "nSync. 0 - Not synchronised. 1 - Indicates that code group synchronization has been completed.", offset = range(0x40,0x40+4*numTxLanes+1,4), bitSize = 1, bitOffset = 3, @@ -274,7 +274,7 @@ def __init__( self.addRemoteVariables( name = "StatusValidCnt", - description = "StatusValidCnt[31:0]. Shows stability of JESD lanes. Counts number of JESD re-syncronisations.", + description = "StatusValidCnt[31:0]. Shows stability of JESD lanes. Counts number of JESD re-synchronisations.", offset = 0x100, bitSize = 32, bitOffset = 0x00, diff --git a/python/surf/protocols/pgp/_Pgp4RxLiteLowSpeedReg.py b/python/surf/protocols/pgp/_Pgp4RxLiteLowSpeedReg.py index c212568d92..a29eba9547 100644 --- a/python/surf/protocols/pgp/_Pgp4RxLiteLowSpeedReg.py +++ b/python/surf/protocols/pgp/_Pgp4RxLiteLowSpeedReg.py @@ -93,7 +93,7 @@ def __init__(self, self.add(pr.RemoteVariable( name = 'NUM_LANE_G', - description = 'NUM_LANE_G VHDL genenic value', + description = 'NUM_LANE_G VHDL generic value', offset = 0x7FC, bitSize = 8, bitOffset = 8, diff --git a/python/surf/protocols/ssp/_SspLowSpeedDecoderReg.py b/python/surf/protocols/ssp/_SspLowSpeedDecoderReg.py index de2edefbf6..29205f1593 100644 --- a/python/surf/protocols/ssp/_SspLowSpeedDecoderReg.py +++ b/python/surf/protocols/ssp/_SspLowSpeedDecoderReg.py @@ -90,7 +90,7 @@ def __init__(self, numberLanes=1, **kwargs): self.add(pr.RemoteVariable( name = 'DATA_WIDTH_G', - description = 'DATA_WIDTH_G VHDL genenic value', + description = 'DATA_WIDTH_G VHDL generic value', offset = 0x7FC, bitSize = 8, bitOffset = 0, @@ -100,7 +100,7 @@ def __init__(self, numberLanes=1, **kwargs): self.add(pr.RemoteVariable( name = 'NUM_LANE_G', - description = 'NUM_LANE_G VHDL genenic value', + description = 'NUM_LANE_G VHDL generic value', offset = 0x7FC, bitSize = 8, bitOffset = 8, @@ -188,7 +188,7 @@ def __init__(self, numberLanes=1, **kwargs): self.add(pr.RemoteVariable( name = 'MaskOffDispErr', - description = '1: Mask off dsispErr (debug only) , 0: normal operation', + description = '1: Mask off dispErr (debug only) , 0: normal operation', offset = 0x81C, bitSize = 1, bitOffset = 1, diff --git a/python/surf/protocols/sugoi/_SugoiAxiL.py b/python/surf/protocols/sugoi/_SugoiAxiL.py index 268902a504..7ee6404003 100644 --- a/python/surf/protocols/sugoi/_SugoiAxiL.py +++ b/python/surf/protocols/sugoi/_SugoiAxiL.py @@ -114,7 +114,7 @@ def __init__(self,**kwargs): self.addRemoteVariables( name = 'DropTrigOpCodeCnt', - description = 'Increments if unable to transmit the OP-cde control word', + description = 'Increments if unable to transmit the OP-code control word', offset = 0x80, bitSize = statusCntSize, mode = 'RO', diff --git a/python/surf/xilinx/_AxiSysMonUltraScale.py b/python/surf/xilinx/_AxiSysMonUltraScale.py index 844d5b8912..1e2a3fc531 100644 --- a/python/surf/xilinx/_AxiSysMonUltraScale.py +++ b/python/surf/xilinx/_AxiSysMonUltraScale.py @@ -13,7 +13,7 @@ class AxiSysMonUltraScale(pr.Device): def __init__( self, - description = "AXI-Lite System Managment for Xilinx Ultra Scale (Refer to PG185)", + description = "AXI-Lite System Management for Xilinx Ultra Scale (Refer to PG185)", XIL_DEVICE_G = "ULTRASCALE", simpleViewList = None, pollInterval = 5, @@ -434,7 +434,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll self.add(pr.RemoteVariable( name = "OTAutomaticShutdown", - description = "OT_AUTOMATIC_SHUTDOWN, set to 0x3 to enable (defatul 125 degC)", + description = "OT_AUTOMATIC_SHUTDOWN, set to 0x3 to enable (default 125 degC)", offset = 0x54C, bitSize = 4, bitOffset = 0x0, diff --git a/python/surf/xilinx/_SpiPs.py b/python/surf/xilinx/_SpiPs.py index 029e4e1e65..eefef81043 100644 --- a/python/surf/xilinx/_SpiPs.py +++ b/python/surf/xilinx/_SpiPs.py @@ -517,7 +517,7 @@ def _pollWorker(self): #print(f'Resp: {resp}') if resp != 0: self.ResetHw() - transaction.error(f'AXIL tranaction failed with RESP: {resp}') + transaction.error(f'AXIL transaction failed with RESP: {resp}') # Finish the transaction elif transaction.type() == rogue.interfaces.memory.Write: diff --git a/xilinx/7Series/gth7/rtl/Gth7AutoPhaseAligner.vhd b/xilinx/7Series/gth7/rtl/Gth7AutoPhaseAligner.vhd index 27ac88846e..1e51fb68a1 100755 --- a/xilinx/7Series/gth7/rtl/Gth7AutoPhaseAligner.vhd +++ b/xilinx/7Series/gth7/rtl/Gth7AutoPhaseAligner.vhd @@ -84,7 +84,7 @@ entity Gth7AutoPhaseAligner is STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB --or reference-clock present at startup. RUN_PHALIGNMENT : in std_logic; --Signal from the main Reset-FSM to run the auto phase-alignment procedure - PHASE_ALIGNMENT_DONE : out std_logic := '0'; -- Auto phase-alignment performed sucessfully + PHASE_ALIGNMENT_DONE : out std_logic := '0'; -- Auto phase-alignment performed successfully PHALIGNDONE : in std_logic; --\ Phase-alignment signals from and to the DLYSRESET : out std_logic; -- |transceiver. DLYSRESETDONE : in std_logic; --/ diff --git a/xilinx/7Series/gth7/rtl/Gth7RecClkMonitor.vhd b/xilinx/7Series/gth7/rtl/Gth7RecClkMonitor.vhd index f1abf372de..1ea1cf5a96 100755 --- a/xilinx/7Series/gth7/rtl/Gth7RecClkMonitor.vhd +++ b/xilinx/7Series/gth7/rtl/Gth7RecClkMonitor.vhd @@ -28,13 +28,13 @@ -- running on a BUFG. -- -- To set the parameters correctly here is what you need to --- do. Lets assume taht the reference and recovered +-- do. Lets assume that the reference and recovered -- clocks are running at 156MHz and the system clock is -- running at 50MHz. -- --- To ensure that the interval is long enough we want to +-- To ensure that the interval is long enough we want -- to make the COUNTER_UPPER_VALUE to be reasonable. The --- CLOCK_PULSES is the number of sytem clock cycles we can +-- CLOCK_PULSES is the number of system clock cycles we can -- expect to be off based on these frequencies: -- -- Example: Rec Clk and Ref Clk 156MHz, System clock 50MHz @@ -46,7 +46,7 @@ -- PPM OFFSET = 5000 => 32768 * 5000/1000000 = 164 -- -- Now we are using the system clock to do the --- calculations, therfore we need to scale the PPM_OFFSET +-- calculations, therefore we need to scale the PPM_OFFSET -- accordingly. -- -- CLOCK_PULSES = PPM_OFFSET * sysclk_freq/refclk_freq @@ -54,7 +54,7 @@ -- -- -- When the counters are checked if they are off by less --- than 52, we can delcare that the particular RECCLK is +-- than 52, we can declare that the particular RECCLK is -- stable. -- -- All FFs that have the _meta are metastability FFs and @@ -357,7 +357,7 @@ begin --- On clock roll-over, latch counter value once and event occurance. +-- On clock roll-over, latch counter value once and event occurrence. process (SYSTEM_CLK) begin if rising_edge(SYSTEM_CLK) then diff --git a/xilinx/7Series/gth7/rtl/Gth7RxFixedLatPhaseAligner.vhd b/xilinx/7Series/gth7/rtl/Gth7RxFixedLatPhaseAligner.vhd index e1e1b0e90a..c26ef9f2e9 100755 --- a/xilinx/7Series/gth7/rtl/Gth7RxFixedLatPhaseAligner.vhd +++ b/xilinx/7Series/gth7/rtl/Gth7RxFixedLatPhaseAligner.vhd @@ -49,7 +49,7 @@ end entity Gth7RxFixedLatPhaseAligner; architecture rtl of Gth7RxFixedLatPhaseAligner is - constant SLIDE_WAIT_C : integer := 32; -- Dictated by UG476 GTX Tranceiver Guide + constant SLIDE_WAIT_C : integer := 32; -- Dictated by UG476 GTX Transceiver Guide type StateType is (SEARCH_S, RESET_S, SLIDE_S, SLIDE_WAIT_S, ALIGNED_S); diff --git a/xilinx/7Series/gth7/rtl/Gth7RxRst.vhd b/xilinx/7Series/gth7/rtl/Gth7RxRst.vhd index 0146c45528..e3a4dc4f20 100755 --- a/xilinx/7Series/gth7/rtl/Gth7RxRst.vhd +++ b/xilinx/7Series/gth7/rtl/Gth7RxRst.vhd @@ -99,7 +99,7 @@ entity Gth7RxRst is GTRXRESET : out std_logic := '0'; MMCM_RESET : out std_logic := '1'; PLL_RESET : out std_logic := '0'; --Reset PLL - RX_FSM_RESET_DONE : out std_logic; --Reset-sequence has sucessfully been finished. + RX_FSM_RESET_DONE : out std_logic; --Reset-sequence has successfully been finished. RXUSERRDY : out std_logic := '0'; RUN_PHALIGNMENT : out std_logic; PHALIGNMENT_DONE : in std_logic; -- Drive high if phase alignment not needed diff --git a/xilinx/7Series/gth7/rtl/Gth7TxRst.vhd b/xilinx/7Series/gth7/rtl/Gth7TxRst.vhd index 426dde42f0..5b75877eda 100755 --- a/xilinx/7Series/gth7/rtl/Gth7TxRst.vhd +++ b/xilinx/7Series/gth7/rtl/Gth7TxRst.vhd @@ -91,7 +91,7 @@ entity Gth7TxRst is GTTXRESET : out std_logic := '0'; MMCM_RESET : out std_logic := '1'; PLL_RESET : out std_logic := '0'; --Reset PLL - TX_FSM_RESET_DONE : out std_logic; --Reset-sequence has sucessfully been finished. + TX_FSM_RESET_DONE : out std_logic; --Reset-sequence has successfully been finished. TXUSERRDY : out std_logic := '0'; RUN_PHALIGNMENT : out std_logic := '0'; RESET_PHALIGNMENT : out std_logic := '0'; diff --git a/xilinx/7Series/gtp7/rtl/Gtp7AutoPhaseAligner.vhd b/xilinx/7Series/gtp7/rtl/Gtp7AutoPhaseAligner.vhd index f5762eb1a5..395ba42ef1 100755 --- a/xilinx/7Series/gtp7/rtl/Gtp7AutoPhaseAligner.vhd +++ b/xilinx/7Series/gtp7/rtl/Gtp7AutoPhaseAligner.vhd @@ -86,7 +86,7 @@ entity Gtp7AutoPhaseAligner is STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB --or reference-clock present at startup. RUN_PHALIGNMENT : in std_logic; --Signal from the main Reset-FSM to run the auto phase-alignment procedure - PHASE_ALIGNMENT_DONE : out std_logic := '0'; -- Auto phase-alignment performed sucessfully + PHASE_ALIGNMENT_DONE : out std_logic := '0'; -- Auto phase-alignment performed successfully PHALIGNDONE : in std_logic; --\ Phase-alignment signals from and to the DLYSRESET : out std_logic; -- |transceiver. DLYSRESETDONE : in std_logic; --/ diff --git a/xilinx/7Series/gtp7/rtl/Gtp7RecClkMonitor.vhd b/xilinx/7Series/gtp7/rtl/Gtp7RecClkMonitor.vhd index 313689a85c..ffbe99aefe 100755 --- a/xilinx/7Series/gtp7/rtl/Gtp7RecClkMonitor.vhd +++ b/xilinx/7Series/gtp7/rtl/Gtp7RecClkMonitor.vhd @@ -28,13 +28,13 @@ -- running on a BUFG. -- -- To set the parameters correctly here is what you need to --- do. Lets assume taht the reference and recovered +-- do. Lets assume that the reference and recovered -- clocks are running at 156MHz and the system clock is -- running at 50MHz. -- --- To ensure that the interval is long enough we want to +-- To ensure that the interval is long enough we want -- to make the COUNTER_UPPER_VALUE to be reasonable. The --- CLOCK_PULSES is the number of sytem clock cycles we can +-- CLOCK_PULSES is the number of system clock cycles we can -- expect to be off based on these frequencies: -- -- Example: Rec Clk and Ref Clk 156MHz, System clock 50MHz @@ -46,7 +46,7 @@ -- PPM OFFSET = 5000 => 32768 * 5000/1000000 = 164 -- -- Now we are using the system clock to do the --- calculations, therfore we need to scale the PPM_OFFSET +-- calculations, therefore we need to scale the PPM_OFFSET -- accordingly. -- -- CLOCK_PULSES = PPM_OFFSET * sysclk_freq/refclk_freq @@ -54,7 +54,7 @@ -- -- -- When the counters are checked if they are off by less --- than 52, we can delcare that the particular RECCLK is +-- than 52, we can declare that the particular RECCLK is -- stable. -- -- All FFs that have the _meta are metastability FFs and @@ -357,7 +357,7 @@ begin --- On clock roll-over, latch counter value once and event occurance. +-- On clock roll-over, latch counter value once and event occurrence. process (SYSTEM_CLK) begin if rising_edge(SYSTEM_CLK) then diff --git a/xilinx/7Series/gtp7/rtl/Gtp7RxFixedLatPhaseAligner.vhd b/xilinx/7Series/gtp7/rtl/Gtp7RxFixedLatPhaseAligner.vhd index e392314a80..d7f30eebc0 100644 --- a/xilinx/7Series/gtp7/rtl/Gtp7RxFixedLatPhaseAligner.vhd +++ b/xilinx/7Series/gtp7/rtl/Gtp7RxFixedLatPhaseAligner.vhd @@ -52,7 +52,7 @@ end entity Gtp7RxFixedLatPhaseAligner; architecture rtl of Gtp7RxFixedLatPhaseAligner is - constant SLIDE_WAIT_C : integer := 64; -- Dictated by UG476 GTX Tranceiver Guide + constant SLIDE_WAIT_C : integer := 64; -- Dictated by UG476 GTX Transceiver Guide type StateType is (SEARCH_S, RESET_S, SLIDE_S, SLIDE_WAIT_S, ALIGNED_S); diff --git a/xilinx/7Series/gtp7/rtl/Gtp7RxRst.vhd b/xilinx/7Series/gtp7/rtl/Gtp7RxRst.vhd index 496b314391..9fed466875 100755 --- a/xilinx/7Series/gtp7/rtl/Gtp7RxRst.vhd +++ b/xilinx/7Series/gtp7/rtl/Gtp7RxRst.vhd @@ -107,7 +107,7 @@ entity Gtp7RxRst is MMCM_RESET : out std_logic := '1'; PLL0_RESET : out std_logic := '0'; --Reset PLL0 (only if RX uses PLL0) PLL1_RESET : out std_logic := '0'; --Reset PLL1 (only if RX uses PLL1) - RX_FSM_RESET_DONE : out std_logic; --Reset-sequence has sucessfully been finished. + RX_FSM_RESET_DONE : out std_logic; --Reset-sequence has successfully been finished. RXUSERRDY : out std_logic := '0'; RUN_PHALIGNMENT : out std_logic; PHALIGNMENT_DONE : in std_logic; diff --git a/xilinx/7Series/gtp7/rtl/Gtp7TxRst.vhd b/xilinx/7Series/gtp7/rtl/Gtp7TxRst.vhd index 79f03068f7..f0532779a6 100755 --- a/xilinx/7Series/gtp7/rtl/Gtp7TxRst.vhd +++ b/xilinx/7Series/gtp7/rtl/Gtp7TxRst.vhd @@ -98,7 +98,7 @@ entity Gtp7TxRst is MMCM_RESET : out std_logic := '1'; PLL0_RESET : out std_logic := '0'; --Reset PLL0 PLL1_RESET : out std_logic := '0'; --Reset PLL1 - TX_FSM_RESET_DONE : out std_logic; --Reset-sequence has sucessfully been finished. + TX_FSM_RESET_DONE : out std_logic; --Reset-sequence has successfully been finished. TXUSERRDY : out std_logic := '0'; RUN_PHALIGNMENT : out std_logic := '0'; RESET_PHALIGNMENT : out std_logic := '0'; diff --git a/xilinx/7Series/gtx7/rtl/Gtx7AutoPhaseAligner.vhd b/xilinx/7Series/gtx7/rtl/Gtx7AutoPhaseAligner.vhd index fe716b211a..8888be71f9 100755 --- a/xilinx/7Series/gtx7/rtl/Gtx7AutoPhaseAligner.vhd +++ b/xilinx/7Series/gtx7/rtl/Gtx7AutoPhaseAligner.vhd @@ -86,7 +86,7 @@ entity Gtx7AutoPhaseAligner is STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB --or reference-clock present at startup. RUN_PHALIGNMENT : in std_logic; --Signal from the main Reset-FSM to run the auto phase-alignment procedure - PHASE_ALIGNMENT_DONE : out std_logic := '0'; -- Auto phase-alignment performed sucessfully + PHASE_ALIGNMENT_DONE : out std_logic := '0'; -- Auto phase-alignment performed successfully PHALIGNDONE : in std_logic; --\ Phase-alignment signals from and to the DLYSRESET : out std_logic; -- |transceiver. DLYSRESETDONE : in std_logic; --/ diff --git a/xilinx/7Series/gtx7/rtl/Gtx7RecClkMonitor.vhd b/xilinx/7Series/gtx7/rtl/Gtx7RecClkMonitor.vhd index 9e32a9d784..2490372be6 100755 --- a/xilinx/7Series/gtx7/rtl/Gtx7RecClkMonitor.vhd +++ b/xilinx/7Series/gtx7/rtl/Gtx7RecClkMonitor.vhd @@ -28,13 +28,13 @@ -- running on a BUFG. -- -- To set the parameters correctly here is what you need to --- do. Lets assume taht the reference and recovered +-- do. Lets assume that the reference and recovered -- clocks are running at 156MHz and the system clock is -- running at 50MHz. -- --- To ensure that the interval is long enough we want to +-- To ensure that the interval is long enough we want -- to make the COUNTER_UPPER_VALUE to be reasonable. The --- CLOCK_PULSES is the number of sytem clock cycles we can +-- CLOCK_PULSES is the number of system clock cycles we can -- expect to be off based on these frequencies: -- -- Example: Rec Clk and Ref Clk 156MHz, System clock 50MHz @@ -46,7 +46,7 @@ -- PPM OFFSET = 5000 => 32768 * 5000/1000000 = 164 -- -- Now we are using the system clock to do the --- calculations, therfore we need to scale the PPM_OFFSET +-- calculations, therefore we need to scale the PPM_OFFSET -- accordingly. -- -- CLOCK_PULSES = PPM_OFFSET * sysclk_freq/refclk_freq @@ -54,7 +54,7 @@ -- -- -- When the counters are checked if they are off by less --- than 52, we can delcare that the particular RECCLK is +-- than 52, we can declare that the particular RECCLK is -- stable. -- -- All FFs that have the _meta are metastability FFs and @@ -357,7 +357,7 @@ begin --- On clock roll-over, latch counter value once and event occurance. +-- On clock roll-over, latch counter value once and event occurrence. process (SYSTEM_CLK) begin if rising_edge(SYSTEM_CLK) then diff --git a/xilinx/7Series/gtx7/rtl/Gtx7RxFixedLatPhaseAligner.vhd b/xilinx/7Series/gtx7/rtl/Gtx7RxFixedLatPhaseAligner.vhd index e9215b517d..e3f508a4a8 100755 --- a/xilinx/7Series/gtx7/rtl/Gtx7RxFixedLatPhaseAligner.vhd +++ b/xilinx/7Series/gtx7/rtl/Gtx7RxFixedLatPhaseAligner.vhd @@ -49,7 +49,7 @@ end entity Gtx7RxFixedLatPhaseAligner; architecture rtl of Gtx7RxFixedLatPhaseAligner is - constant SLIDE_WAIT_C : integer := 32; -- Dictated by UG476 GTX Tranceiver Guide + constant SLIDE_WAIT_C : integer := 32; -- Dictated by UG476 GTX Transceiver Guide type StateType is (SEARCH_S, RESET_S, SLIDE_S, SLIDE_WAIT_S, ALIGNED_S); diff --git a/xilinx/7Series/gtx7/rtl/Gtx7RxRst.vhd b/xilinx/7Series/gtx7/rtl/Gtx7RxRst.vhd index 3fcdcde5fe..48c67838c8 100755 --- a/xilinx/7Series/gtx7/rtl/Gtx7RxRst.vhd +++ b/xilinx/7Series/gtx7/rtl/Gtx7RxRst.vhd @@ -98,7 +98,7 @@ entity Gtx7RxRst is GTRXRESET : out std_logic := '0'; MMCM_RESET : out std_logic := '1'; PLL_RESET : out std_logic := '0'; --Reset PLL - RX_FSM_RESET_DONE : out std_logic; --Reset-sequence has sucessfully been finished. + RX_FSM_RESET_DONE : out std_logic; --Reset-sequence has successfully been finished. RXUSERRDY : out std_logic := '0'; RUN_PHALIGNMENT : out std_logic; PHALIGNMENT_DONE : in std_logic; -- Drive high if phase alignment not needed diff --git a/xilinx/7Series/gtx7/rtl/Gtx7TxRst.vhd b/xilinx/7Series/gtx7/rtl/Gtx7TxRst.vhd index 2976665b12..7c1b90ba8a 100755 --- a/xilinx/7Series/gtx7/rtl/Gtx7TxRst.vhd +++ b/xilinx/7Series/gtx7/rtl/Gtx7TxRst.vhd @@ -91,7 +91,7 @@ entity Gtx7TxRst is GTTXRESET : out std_logic := '0'; MMCM_RESET : out std_logic := '1'; PLL_RESET : out std_logic := '0'; --Reset PLL - TX_FSM_RESET_DONE : out std_logic; --Reset-sequence has sucessfully been finished. + TX_FSM_RESET_DONE : out std_logic; --Reset-sequence has successfully been finished. TXUSERRDY : out std_logic := '0'; RUN_PHALIGNMENT : out std_logic := '0'; RESET_PHALIGNMENT : out std_logic := '0'; diff --git a/xilinx/xvc-udp/jtag/rtl/AxisToJtag.vhd b/xilinx/xvc-udp/jtag/rtl/AxisToJtag.vhd index bdeef2c596..38207c9d1a 100755 --- a/xilinx/xvc-udp/jtag/rtl/AxisToJtag.vhd +++ b/xilinx/xvc-udp/jtag/rtl/AxisToJtag.vhd @@ -46,7 +46,7 @@ use surf.AxisToJtagPkg.all; -- [27:00] Command-specific parameter(s) -- -- Note that if the core is configured for a stream width (AXIS_WIDTH_G) > 4 --- then the header is padded up to the desired width, i.e., the paylod must +-- then the header is padded up to the desired width, i.e., the payload must -- be word-aligned. -- -- Each command word is answered with a reply word on the outgoing stream diff --git a/xilinx/xvc-udp/jtag/rtl/AxisToJtagCore.vhd b/xilinx/xvc-udp/jtag/rtl/AxisToJtagCore.vhd index 89dc36a89a..2ac4a76ead 100755 --- a/xilinx/xvc-udp/jtag/rtl/AxisToJtagCore.vhd +++ b/xilinx/xvc-udp/jtag/rtl/AxisToJtagCore.vhd @@ -76,7 +76,7 @@ use surf.AxiStreamPkg.all; -- the return stream truncated as well). If TLAST is asserted -- after the announced number of bits then the excess words are -- discarded. --- If the TLAST_IGNORE_G generic is true the the behavior is +-- If the TLAST_IGNORE_G generic is true the behavior is -- changed and no data are discarded if TLAST is missing (an early -- TLAST still leads to truncated data). -- This TLAST_IGNORE_G allows the core to be used with implicit diff --git a/xilinx/xvc-udp/jtag/rtl/AxisToJtagPkg.vhd b/xilinx/xvc-udp/jtag/rtl/AxisToJtagPkg.vhd index d0fc1929da..c6cd862b31 100755 --- a/xilinx/xvc-udp/jtag/rtl/AxisToJtagPkg.vhd +++ b/xilinx/xvc-udp/jtag/rtl/AxisToJtagPkg.vhd @@ -45,7 +45,7 @@ use surf.AxiStreamPkg.all; -- [27:00] Command-specific parameter(s) -- -- Note that if the core is configured for a stream width (AXIS_WIDTH_G) > 4 --- then the header is padded up to the desired width, i.e., the paylod must +-- then the header is padded up to the desired width, i.e., the payload must -- be word-aligned. -- -- Each command word is answered with a reply word on the outgoing stream diff --git a/xilinx/xvc-udp/jtag/rtl/JtagSerDesCore.vhd b/xilinx/xvc-udp/jtag/rtl/JtagSerDesCore.vhd index a3b4ff3490..6e24b5c4b6 100755 --- a/xilinx/xvc-udp/jtag/rtl/JtagSerDesCore.vhd +++ b/xilinx/xvc-udp/jtag/rtl/JtagSerDesCore.vhd @@ -20,7 +20,7 @@ library surf; use surf.StdRtlPkg.all; -- Serialize a TMS/TDI word pair into JTAG signals and deserialize --- TDO into a paralle output word. +-- TDO into a parallel output word. entity JtagSerDesCore is generic ( From 60097c8b4876f3301b9bbba093c8b6da67abe9e2 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Wed, 20 May 2026 08:42:25 -0700 Subject: [PATCH 04/10] Deepen base regression coverage Add targeted cocotb regression coverage for FIFO pressure and recovery, RAM collision and enable semantics, SynchronizerFifo read-enable gaps, Arbiter starvation rotation, WatchDogRst near-timeout keepalive noise, and SlvDelayFifo/SlvDelayRam reset and runtime-delay behavior. Document the SlvDelayRam runtime maxCount contract in the RTL description header. Formalize the cocotb regression test style guide in tests/README.md and refine the CoaXPress regression docs and tests. --- base/delay/rtl/SlvDelayRam.vhd | 33 ++- scripts/build_rtl_instantiation_graph.py | 20 +- tests/README.md | 196 ++++++++++++++++-- tests/base/delay/test_SlvDelayFifo.py | 34 ++- tests/base/delay/test_SlvDelayRam.py | 77 ++++++- tests/base/fifo/test_FifoAsync.py | 133 +++++++++++- tests/base/fifo/test_FifoCascade.py | 53 ++++- tests/base/fifo/test_FifoMux.py | 32 ++- tests/base/fifo/test_FifoSync.py | 69 +++++- tests/base/general/test_Arbiter.py | 46 +++- tests/base/general/test_WatchDogRst.py | 29 ++- tests/base/ram/test_DualPortRam.py | 50 ++++- tests/base/ram/test_SimpleDualPortRam.py | 68 +++++- tests/base/ram/test_TrueDualPortRam.py | 59 +++++- tests/base/sync/test_SynchronizerFifo.py | 93 ++++++++- tests/protocols/coaxpress/README.md | 34 ++- .../coaxpress/test_CoaXPressConfig.py | 121 ++++++----- .../test_CoaXPressOverFiberBridgeRx.py | 152 +++++++++++++- 18 files changed, 1173 insertions(+), 126 deletions(-) diff --git a/base/delay/rtl/SlvDelayRam.vhd b/base/delay/rtl/SlvDelayRam.vhd index 3e5a05f702..28b560d1d6 100644 --- a/base/delay/rtl/SlvDelayRam.vhd +++ b/base/delay/rtl/SlvDelayRam.vhd @@ -1,13 +1,34 @@ ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- --- Description: Shift Register Delay module for std_logic_vector --- Uses a counter and single port RAM (distributed, block, ultra) --- Single port RAM setup in read first mode --- Counter counts 0...maxCount --- Optional data out register (DO_REG_G) on the RAM +-- Description: Runtime-configurable delay line for std_logic_vector data. -- --- delay = maxCount + ite(DO_REG_G, 3, 2) +-- SlvDelayRam stores each accepted din sample in an inferred +-- single-port RAM and reads back the sample located at the +-- current circular address. The RAM is used in read-before-write +-- mode, so the visible output is the sample captured on an +-- earlier visit to the same address. The address counter wraps +-- when it reaches the registered maxCount value, which sets the +-- requested delay depth. The en input freezes the address +-- counter, maxCount register, RAM write, and output update. +-- +-- DO_REG_G adds an output register after the RAM read data. +-- With the current implementation, the observable delay is: +-- +-- delay = maxCount + ite(DO_REG_G, 3, 2) +-- +-- maxCount is sampled while en is asserted and is intended to be +-- programmed during initialization or while the module is held in +-- reset. If maxCount is changed while traffic is flowing, the +-- circular address phase is not automatically realigned. The +-- transition samples are therefore undefined, and shrinking +-- maxCount below the current address can violate the internal +-- counter range in simulation. Software or firmware that changes +-- maxCount at runtime must assert rst afterward and should discard +-- any pre-reset output history before relying on dout again. In +-- practice, allow at least one newly configured delay interval +-- after reset release before treating dout as aligned to the new +-- maxCount setting. ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the diff --git a/scripts/build_rtl_instantiation_graph.py b/scripts/build_rtl_instantiation_graph.py index e7aade60b0..9be4efca31 100644 --- a/scripts/build_rtl_instantiation_graph.py +++ b/scripts/build_rtl_instantiation_graph.py @@ -17,6 +17,7 @@ from dataclasses import dataclass from pathlib import Path import re +import tempfile RE_ENTITY_DECL = re.compile(r"\bentity\s+(?P[A-Za-z][A-Za-z0-9_]*)\s+is\b", re.IGNORECASE) @@ -73,6 +74,10 @@ def _repo_root() -> Path: return Path(__file__).resolve().parents[1] +def _default_output_dir() -> Path: + return Path(tempfile.gettempdir()) / "surf_rtl_instantiation_graph" + + def _strip_comments(text: str) -> str: return "\n".join(line.split("--", 1)[0] for line in text.splitlines()) @@ -957,6 +962,10 @@ def _write_phase1_queue_artifacts( layers = _bottom_up_layers(phase1_graph, phase1_defs) queue = [node_id for layer in layers for node_id in layer] queue, applied_overrides = _apply_order_overrides(queue, phase1_graph, phase1_defs, overrides) + try: + displayed_override_path = override_path.relative_to(repo_root) + except ValueError: + displayed_override_path = override_path layer_by_node = { node_id: layer_index @@ -967,7 +976,7 @@ def _write_phase1_queue_artifacts( _write_phase1_queue_json( output_dir / "rtl_phase1_queue.json", scan_dirs=scan_dirs, - override_path=override_path.relative_to(repo_root), + override_path=displayed_override_path, overrides=overrides, definitions=phase1_defs, graph=phase1_graph, @@ -980,7 +989,7 @@ def _write_phase1_queue_artifacts( _write_phase1_queue_markdown( output_dir / "rtl_phase1_queue.md", scan_dirs=scan_dirs, - override_path=override_path.relative_to(repo_root), + override_path=displayed_override_path, overrides=overrides, definitions=phase1_defs, graph=phase1_graph, @@ -1016,8 +1025,11 @@ def main() -> None: ) parser.add_argument( "--output-dir", - default=str(_repo_root() / "docs" / "_meta"), - help="Directory for generated graph and queue artifacts.", + default=str(_default_output_dir()), + help=( + "Directory for generated graph and queue artifacts. Defaults to a temporary " + "directory so generated analysis does not become normal docs context." + ), ) parser.add_argument( "--scan-dir", diff --git a/tests/README.md b/tests/README.md index 035c318498..450e7fb1b0 100644 --- a/tests/README.md +++ b/tests/README.md @@ -1,22 +1,180 @@ -# Regression Test Layout +# SURF Cocotb Regression Style Guide -New SURF regressions should be organized by subsystem under `tests/`. +This directory holds Python-authored regressions for synthesizable SURF RTL. +The default stack is `pytest + cocotb + GHDL + ruckus`; VHDL should only be +used for thin wrappers, shims, or required simulation models. ## Layout -- `tests/common/`: shared Python regression helpers -- `tests/legacy/`: archived flat tests that are superseded by subsystem tests and excluded from default pytest collection -- `tests/base/`: regressions for `base/*` -- `tests/axi/`: regressions for `axi/*` -- `tests/protocols/`: regressions for `protocols/*` -- `tests/ethernet/`: regressions for `ethernet/*` -- `tests/devices/`: regressions for `devices/*` -- `tests/xilinx/`: regressions for `xilinx/*` - -Within each subsystem, keep tests grouped by functional area when useful, such as -`tests/base/fifo/` or `tests/axi/axi_stream/`. - -## Policy -- All executable regression logic belongs in Python. -- VHDL is only for thin wrappers, shims, or required simulation models. -- New regressions should not be added as flat `tests/test_*.py` files. -- Flat tests with subsystem replacements should move to `tests/legacy/`; uncovered legacy tests can remain at the root until they are replaced. + +- Keep executable tests under subsystem packages, such as `tests/base/fifo/`, + `tests/axi/axi_stream/`, `tests/protocols/srp/`, or + `tests/ethernet/UdpEngine/`. +- Do not add new flat `tests/test_*.py` files. +- Move superseded flat tests to `tests/legacy/` when they are replaced by + subsystem tests. Uncovered legacy tests may stay at the root until migrated. +- Put reusable helpers in the nearest suitable helper module before adding + another local copy of transaction code: + - `tests/common/regression_utils.py` for repo-wide runner and environment + helpers. + - `tests/axi/utils.py` for AXI-family primitives shared across subsystems. + - `*_test_utils.py` files beside subsystem tests for protocol-specific + frames, scoreboards, setup, and source/sink helpers. +- Keep checked-in cocotb-facing VHDL wrappers beside the RTL family they adapt, + usually in a local `wrappers/` or `ip_integrator/` directory. Do not hide + durable wrappers under `tests/`. + +## Python Test Files + +Every checked-in cocotb test file should start with the standard SLAC/SURF +license header followed immediately by a module-specific `Test methodology` +block: + +```python +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## ... +############################################################################## + +# Test methodology: +# - Sweep: Describe the curated parameter/configuration cases this file runs. +# - Stimulus: Describe the actual input sequences driven into the DUT. +# - Checks: Describe the outputs, state changes, sidebands, or errors asserted. +# - Timing: Describe latency, reset, handshake, backpressure, pulse, or timeout +# behavior that the bench depends on or verifies. +``` + +Do not use generic methodology text. The block should tell a reader what this +specific bench proves and what it intentionally does not prove. + +Use in-body comments at the major coroutine steps: clock startup, reset, +stimulus phases, backpressure, trigger waits, and result checks. Keep comments +tutorial-level for module tests, assuming the reader may not know cocotb well. +Shared helper modules may be denser, but non-obvious protocol or timing behavior +still needs a short explanation. + +Common structure: + +- Imports: standard library, cocotb/pytest, third-party helpers such as + `cocotbext.axi`, then repo helpers. +- A small `TB` class when setup/reset/clocking is nontrivial. +- One or more `@cocotb.test()` coroutine entrypoints that each prove a clear + behavior. +- A `PARAMETER_SWEEP` list using `pytest.param(..., id="readable_case_name")` + or `parameter_case()`. +- A final pytest wrapper named for the RTL target, calling + `run_surf_vhdl_test(test_file=__file__, ...)`. + +## Parameter Sweeps + +Prefer curated matrices over broad Cartesian products. A good sweep covers +representative behavior: default path, one or two interesting generic branches, +reset polarity/asynchronous reset when relevant, a narrow/wide data path if that +changes packing, and a backpressure or staged case when timing is part of the +contract. + +Keep sweep IDs short and meaningful because they become pytest IDs and sim-build +directory names. Use `sim_build_key` when a case has enough metadata to create +fragile or overly long build paths. + +Pass only HDL generics as `parameters`. Put Python-only case metadata in +`extra_env`, or use `hdl_parameters_from(parameters)` when a case dictionary +contains both. + +## Reuse And Helpers + +Before writing transaction code, search nearby helpers and related subsystems. +Existing patterns include: + +- AXI-Lite register helpers and common runner utilities in `tests/axi/utils.py` + and `tests/common/regression_utils.py`. +- SSI beat/frame helpers in `tests/protocols/ssi/ssi_test_utils.py`. +- SRPv3 request/response models in `tests/protocols/srp/srp_test_utils.py`. +- Ethernet, UDP, IPv4, RawEth, PGP, and CoaXPress frame builders in their + local `*_test_utils.py` files. + +Prefer extending a helper with one narrow reusable primitive over duplicating +ready/valid loops, packet builders, register accesses, or frame receivers in a +new test file. + +For AXI Stream, SSI, and other flattened ready/valid sources, hold the current +beat stable until a sampled accepting clock edge. Use +`wait_sampled_ready()` when a `cocotbext.axi` source is not appropriate. After +`wait_sampled_ready()` returns, the transfer has already completed; advance or +deassert the source immediately. + +Use `start_lockstep_clocks()` for `COMMON_CLK_G` or similar wrappers that expect +truly shared clock edges. Do not start two independent same-period clock +coroutines when the DUT contract is common-clock behavior. + +## Assertions And Timing + +Assert externally visible behavior, not implementation accidents. Good checks +usually include payload bytes, `TKEEP`, `TLAST`, `TUSER`/SOF/EOFE bits, address +or ID sidebands, response codes, counters, or accepted-handshake timing. + +Use bounded waits and explicit timeouts for protocol progress. Avoid +open-ended `while True` loops unless they are wrapped by `with_timeout()` or a +helper that has a cycle limit. + +When a contract includes backpressure, burst length, sideband propagation, or +arbitration order, monitor accepted handshakes directly. Final memory contents +alone are not enough for timing-visible behavior. + +Account for `TPD_G`, registered outputs, and GHDL scheduling. Sampling exactly +on a clock edge can create false failures; most helpers settle with a short +`Timer` after `RisingEdge()`. + +Known RTL issues or intentionally open coverage should be explicit. If a bench +is checked in skipped or opt-in, document the condition and gate it with a clear +environment variable such as `RUN_KNOWN_ISSUE_TESTS`. + +## Running Tests + +Use the repo virtualenv interpreter unless the virtualenv is already activated: + +```bash +make MODULES="$PWD" import +./.venv/bin/python -m pytest -n auto --dist=worksteal -q tests/ +``` + +Run `make ... import` when the imported HDL source cache is missing or stale. +Use `-n 0` for focused debug runs when serial simulator logs matter. + +After any command that launches pytest, cocotb, GHDL, or another simulator +runner, check for stale simulator child processes before starting another run. + +## VHDL Wrappers + +Checked-in cocotb-facing wrappers are repo HDL and should be readable in the +same style as surrounding SURF files: + +- Start with the standard SLAC/SURF VHDL banner and a concise description. +- Keep wrappers thin. They should flatten records, expose simulator-friendly + generics, tie off unused fields deterministically, compose existing shim + layers, or instantiate a small integration topology. +- Prefer `SlaveAxiStreamIpIntegrator`, `MasterAxiStreamIpIntegrator`, + `SlaveAxiLiteIpIntegrator`, and `MasterAxiLiteIpIntegrator` for SURF record + ports instead of hand-writing standard bus packing. +- Add short section comments for the major adapter regions. Typical sections + are input flattening, output/status flattening, shim layer, DUT instantiation, + and wrapper-specific topology. +- Name the real RTL instance `U_DUT` unless the wrapper intentionally contains + more than one peer instance. +- Do not put executable stimulus, scoreboards, or test sequencing in VHDL. + That belongs in Python. + +For any VHDL file created or edited, run the same linter configuration used by +CI before considering the wrapper done: + +```bash +./.venv/bin/vsg -c vsg-linter.yml path/to/Wrapper.vhd +``` + +If `vsg` reports fixable issues, run with `--fix` first, then rerun the lint +command to confirm the file is clean. + +## Coverage Scope + +VHDL packages are usually covered transitively through modules that use them. +Add a dedicated package wrapper only when a behavioral function or procedure is +important and not reached naturally through existing DUT coverage. diff --git a/tests/base/delay/test_SlvDelayFifo.py b/tests/base/delay/test_SlvDelayFifo.py index 80cf2fa413..45be4259e2 100644 --- a/tests/base/delay/test_SlvDelayFifo.py +++ b/tests/base/delay/test_SlvDelayFifo.py @@ -14,7 +14,8 @@ # across both storage styles. # - Stimulus: Issue short and mixed-delay requests with explicit timestamps so # multiple delayed outputs are queued and released out of order in wall-clock -# time but in programmed-delay order. +# time but in programmed-delay order, then optionally reset while delayed +# entries are pending. # - Checks: Returned data must match the request payload associated with each # timestamp and emerge in the same order implied by the requested delay # schedule. @@ -119,6 +120,27 @@ async def timestamped_outputs_preserve_programmed_order_test(dut): assert await tb.wait_for_output() == 0x22 +@cocotb.test() +async def reset_flushes_pending_entries_test(dut): + if not env_flag("CHECK_RESET_FLUSH", default=False): + return + + tb = TB(dut) + await tb.reset() + + # Queue several delayed entries, reset before any requested timestamp can + # mature, and then confirm that only post-reset traffic is observable. + for delay, value in [(10, 0x77), (12, 0x88), (14, 0x55)]: + await tb.load_delay(delay) + await tb.write_word(value) + await tb.cycle(2) + await tb.reset() + + await tb.load_delay(1) + await tb.write_word(0x99) + assert await tb.wait_for_output() == 0x99 + + PARAMETER_SWEEP = [ parameter_case( "block_sync_reset", @@ -138,6 +160,16 @@ async def timestamped_outputs_preserve_programmed_order_test(dut): FIFO_MEMORY_TYPE_G="distributed", CLK_PERIOD_NS="7", ), + parameter_case( + "reset_flush_pending", + RST_ASYNC_G="true", + DATA_WIDTH_G="8", + DELAY_BITS_G="6", + FIFO_ADDR_WIDTH_G="4", + FIFO_MEMORY_TYPE_G="distributed", + CHECK_RESET_FLUSH="1", + CLK_PERIOD_NS="5", + ), ] diff --git a/tests/base/delay/test_SlvDelayRam.py b/tests/base/delay/test_SlvDelayRam.py index 40c3379ad5..dc91b1d776 100644 --- a/tests/base/delay/test_SlvDelayRam.py +++ b/tests/base/delay/test_SlvDelayRam.py @@ -13,10 +13,11 @@ # unregistered active-low reset case to cover the RAM-backed delay line # across its two main shapes. # - Stimulus: Drive known input patterns while programming delay, hold the -# enable low to freeze the output, and assert reset after the RAM has -# buffered data. +# enable low to freeze the output, assert reset after the RAM has buffered +# data, and optionally change `maxCount` followed by the required reset. # - Checks: The output must reproduce the delayed sample selected by the -# programmed latency, hold steady while disabled, and clear after reset. +# programmed latency, reproduce the new delay after a reset-aligned +# reprogramming event, hold steady while disabled, and clear after reset. # - Timing: Checks are cycle-accurate against the programmed delay, with one # extra observable cycle for the registered-output configuration before the # delayed sample appears. @@ -100,6 +101,12 @@ async def reset(self) -> None: await self.cycle() await self.cycle() + async def set_max_count(self, value: int) -> None: + self.dut.maxCount.value = value + self.max_count = value + self.effective_delay = self.max_count + (2 if self.do_reg else 1) + await self.cycle(en=1) + @cocotb.test() async def configured_delay_test(dut): @@ -142,6 +149,59 @@ async def enable_hold_test(dut): assert int(dut.dout.value) == held +@cocotb.test() +async def dynamic_delay_change_requires_reset_test(dut): + if not env_flag("CHECK_DYNAMIC_DELAY_CHANGE", default=False): + return + + tb = TB(dut) + await tb.reset() + + # Start with a short delay and prove live traffic emerges normally. + await tb.set_max_count(1) + short_delay_values = [0x10 + index for index in range(8)] + short_observed = [] + for value in short_delay_values: + observed = await tb.cycle(din=value, en=1) + if observed is not None: + short_observed.append(observed) + for _ in range(tb.effective_delay): + observed = await tb.cycle(din=0x00, en=1) + if observed is not None: + short_observed.append(observed) + assert short_observed[-len(short_delay_values) :] == short_delay_values + + # The RTL contract requires reset after reprogramming maxCount. Apply the + # new value, reset the circular address phase, and then start fresh traffic + # against the new delay setting. + tb.dut.maxCount.value = 4 + tb.max_count = 4 + tb.effective_delay = tb.max_count + (2 if tb.do_reg else 1) + await tb.reset() + for _ in range(tb.effective_delay): + await tb.cycle(din=0x00, en=1) + + long_delay_values = [0x80 + index for index in range(10)] + long_observed = [] + for value in long_delay_values: + observed = await tb.cycle(din=value, en=1) + if observed is not None: + long_observed.append(observed) + for _ in range(tb.effective_delay + 2): + observed = await tb.cycle(din=0x00, en=1) + if observed is not None: + long_observed.append(observed) + + # The first few post-reset samples are still part of the documented output + # history discard interval. Once that interval has passed, later traffic + # must follow the newly configured delay. + stable_values = long_delay_values[2:] + assert any( + long_observed[index : index + len(stable_values)] == stable_values + for index in range(len(long_observed) - len(stable_values) + 1) + ) + + @cocotb.test() async def reset_behavior_test(dut): tb = TB(dut) @@ -170,6 +230,17 @@ async def reset_behavior_test(dut): MAX_COUNT="3", CLK_PERIOD_NS="5", ), + parameter_case( + "block_dynamic_delay_change", + RST_POLARITY_G="'1'", + MEMORY_TYPE_G="block", + DO_REG_G="true", + DELAY_G="8", + WIDTH_G="8", + MAX_COUNT="1", + CHECK_DYNAMIC_DELAY_CHANGE="1", + CLK_PERIOD_NS="5", + ), parameter_case( "distributed_unregistered_active_low", RST_POLARITY_G="'0'", diff --git a/tests/base/fifo/test_FifoAsync.py b/tests/base/fifo/test_FifoAsync.py index 6d44c453cd..9b96ecd66d 100644 --- a/tests/base/fifo/test_FifoAsync.py +++ b/tests/base/fifo/test_FifoAsync.py @@ -14,8 +14,10 @@ # threshold placements with a small curated matrix instead of a Cartesian # explosion. # - Stimulus: Drive burst writes and reads on independent clocks so the FIFO -# fills, drains, crosses programmable threshold points, and encounters both -# empty and full boundaries. +# fills, drains, crosses programmable threshold points, encounters both +# empty and full boundaries, optionally turns over near full with concurrent +# reads and writes, and optionally resets while traffic history is still +# present. # - Checks: The bench checks end-to-end ordering, `full`/`empty` behavior, # programmable threshold flags, deeper and wider geometry variants, and the # behavioral difference between `FWFT` and standard read mode. @@ -89,6 +91,11 @@ async def write_word(self, value: int) -> None: # Let FWFT outputs settle before the next operation samples status. await Timer(2, unit="ns") + async def cycle_rd(self, count: int = 1) -> None: + for _ in range(count): + await RisingEdge(self.dut.rd_clk) + await Timer(2, unit="ns") + async def read_word(self) -> int: if self.fwft_enabled: await with_timeout(self._wait_valid(), 5, "us") @@ -138,6 +145,14 @@ async def _wait_prog_empty(self, expected: int) -> None: while int(self.dut.prog_empty.value) != expected: await RisingEdge(self.dut.rd_clk) + async def assert_reset_clears_visible_state(self) -> None: + # Apply reset after data has moved into the FIFO. The storage contents + # themselves are not part of the contract, but the public status must + # return to an empty/no-valid state before new traffic is accepted. + await self.reset() + assert int(self.dut.valid.value) == 0 + await with_timeout(self._wait_empty(), 5, "us") + @cocotb.test() async def basic_ordering_test(dut): @@ -226,6 +241,100 @@ async def threshold_flag_test(dut): await with_timeout(tb._wait_prog_empty(1), 5, "us") +@cocotb.test() +async def burst_backpressure_and_reset_test(dut): + if not env_flag("CHECK_STRESS_BEHAVIOR", default=False): + return + + tb = TB( + dut, + wr_clk_period_ns=float(os.environ["WR_CLK_PERIOD_NS"]), + rd_clk_period_ns=float(os.environ["RD_CLK_PERIOD_NS"]), + ) + await tb.reset() + + # Fill enough entries to let FWFT prefetch and pointer synchronization + # settle, then drain only part of the burst to emulate a read side that + # periodically withholds service. + first_burst = [0x20 + index for index in range(8)] + for value in first_burst: + await tb.write_word(value) + + observed = [] + for _ in range(3): + observed.append(await tb.read_word()) + assert observed == first_burst[:3] + + # Keep writing while the read side is intentionally idle. This stresses the + # near-full bookkeeping path without depending on one exact CDC count. + second_burst = [0x80 + index for index in range(6)] + for value in second_burst: + await tb.write_word(value) + await tb.cycle_rd(2) + + expected_tail = first_burst[3:] + second_burst + for expected in expected_tail[:5]: + assert await tb.read_word() == expected + + await tb.assert_reset_clears_visible_state() + + # After reset, new traffic must not be contaminated by the discarded + # pre-reset tail. + post_reset = [0xA0, 0xA1, 0xA2] + for value in post_reset: + await tb.write_word(value) + for expected in post_reset: + assert await tb.read_word() == expected + + +@cocotb.test() +async def near_full_turnover_test(dut): + if not env_flag("CHECK_NEAR_FULL_TURNOVER", default=False): + return + + tb = TB( + dut, + wr_clk_period_ns=float(os.environ["WR_CLK_PERIOD_NS"]), + rd_clk_period_ns=float(os.environ["RD_CLK_PERIOD_NS"]), + ) + await tb.reset() + + # Fill the FIFO close to capacity, but leave enough margin that the writer + # can make progress as the slower read clock begins popping data. This + # stresses pointer synchronization and full deassertion during sustained + # boundary turnover without relying on one exact gray-pointer latency. + capacity = 2 ** int(os.environ["ADDR_WIDTH_G"]) + seed_values = [0x100 + index for index in range(capacity - 2)] + replacement_values = [0x180 + index for index in range(6)] + for value in seed_values: + await tb.write_word(value) + + observed = [] + + async def reader() -> None: + for _ in range(10): + observed.append(await tb.read_word()) + await tb.cycle_rd(1) + + async def writer() -> None: + for value in replacement_values: + await tb.write_word(value) + + read_task = cocotb.start_soon(reader()) + write_task = cocotb.start_soon(writer()) + await read_task + await write_task + + expected_stream = seed_values + replacement_values + assert observed == expected_stream[: len(observed)] + + # Drain the rest to prove the near-full turnover did not reorder or drop + # the new tail words that arrived while the read side was active. + for expected in expected_stream[len(observed) :]: + assert await tb.read_word() == expected + await with_timeout(tb._wait_empty(), 5, "us") + + PARAMETER_SWEEP = [ # These cases cover the major functional axes of FifoAsync without trying # to brute-force every generic combination. TPD_G is timing-only, INIT_G is @@ -447,6 +556,26 @@ async def threshold_flag_test(dut): RD_CLK_PERIOD_NS="13", RST_ACTIVE_HIGH="1", ), + parameter_case( + "fwft_adversarial_backpressure", + DATA_WIDTH_G="16", + ADDR_WIDTH_G="4", + FWFT_EN_G="true", + MEMORY_TYPE_G="block", + PIPE_STAGES_G="0", + RST_ASYNC_G="false", + RST_POLARITY_G="'1'", + SYNC_STAGES_G="3", + FULL_THRES_G="12", + EMPTY_THRES_G="2", + CHECK_FULL_EMPTY="0", + CHECK_THRESHOLD_FLAGS="0", + CHECK_STRESS_BEHAVIOR="1", + CHECK_NEAR_FULL_TURNOVER="1", + WR_CLK_PERIOD_NS="3", + RD_CLK_PERIOD_NS="17", + RST_ACTIVE_HIGH="1", + ), ] diff --git a/tests/base/fifo/test_FifoCascade.py b/tests/base/fifo/test_FifoCascade.py index e4ab224733..7cd9b9948c 100644 --- a/tests/base/fifo/test_FifoCascade.py +++ b/tests/base/fifo/test_FifoCascade.py @@ -12,9 +12,9 @@ # - Sweep: Sweep a single-stage cascade and a three-stage cascade with an # asynchronous tail so the bench covers both the minimal wrapper case and a # real multi-stage chain. -# - Stimulus: Push an ordered burst through the cascade and then inspect both -# the final output stream and the exported per-stage vector signals during -# movement. +# - Stimulus: Push ordered bursts through the cascade, intermittently pause the +# read side so stage boundaries fill and drain, and then inspect both the +# final output stream and exported per-stage vector signals during movement. # - Checks: The final stream must preserve ordering across all stages, and the # stage vector mapping must reflect the expected stage-local occupancy/data # plumbing for the selected cascade depth. @@ -166,6 +166,37 @@ async def stage_vector_mapping_test(dut): assert top_prog_full == int(dut.prog_full.value) +@cocotb.test() +async def staged_pressure_recovery_test(dut): + if not env_flag("CHECK_STAGE_PRESSURE", default=False): + return + + tb = TB(dut) + await tb.reset() + + first_burst = [0x40 + index for index in range(6)] + for value in first_burst: + await tb.write_word(value) + + # Let internal FWFT stages move data while the public consumer is paused. + await tb.cycle_wr(8) + await tb.cycle_rd(4) + + observed = [] + for _ in range(3): + observed.append(await tb.read_word()) + + assert observed == first_burst[:3] + + second_burst = [0x80 + index for index in range(4)] + for value in second_burst: + await tb.write_word(value) + + expected_tail = first_burst[3:] + second_burst + for expected in expected_tail: + assert await tb.read_word() == expected + + PARAMETER_SWEEP = [ parameter_case( "single_stage_async", @@ -197,6 +228,22 @@ async def stage_vector_mapping_test(dut): WR_CLK_PERIOD_NS="5", RD_CLK_PERIOD_NS="9", ), + parameter_case( + "three_stage_pressure", + RST_ASYNC_G="false", + RST_POLARITY_G="'1'", + CASCADE_SIZE_G="3", + LAST_STAGE_ASYNC_G="true", + GEN_SYNC_FIFO_G="false", + FWFT_EN_G="true", + SYNTH_MODE_G="inferred", + MEMORY_TYPE_G="distributed", + DATA_WIDTH_G="8", + ADDR_WIDTH_G="4", + CHECK_STAGE_PRESSURE="1", + WR_CLK_PERIOD_NS="5", + RD_CLK_PERIOD_NS="11", + ), ] diff --git a/tests/base/fifo/test_FifoMux.py b/tests/base/fifo/test_FifoMux.py index 45e3ea5ef3..e5038c1f54 100644 --- a/tests/base/fifo/test_FifoMux.py +++ b/tests/base/fifo/test_FifoMux.py @@ -9,11 +9,12 @@ ############################################################################## # Test methodology: -# - Sweep: Keep one explicit `split_to_narrow_little_endian` case so this file -# stays focused on the stable width-conversion path the wrapper is meant to -# expose. +# - Sweep: Keep explicit split-to-narrow and pack-to-wide cases so both sides +# of the FifoMux width-conversion logic are covered without turning the +# wrapper test into a broad FIFO matrix. # - Stimulus: Write wider words that must be unpacked into several narrower -# output beats, then reset the write packer while it still holds partial +# output beats, write narrower words that must be packed into one wider +# output beat, then reset the write packer while it still holds partial # state. # - Checks: The output beat order and byte ordering must match the # little-endian split model, and reset must discard any partially assembled @@ -142,6 +143,11 @@ async def _wait_valid(self) -> None: while int(self.dut.valid.value) == 0: await RisingEdge(self.dut.rd_clk) + async def assert_no_valid(self, cycles: int) -> None: + for _ in range(cycles): + await self.cycle_rd(1) + assert int(self.dut.valid.value) == 0 + @cocotb.test() async def width_conversion_test(dut): @@ -186,6 +192,7 @@ async def write_packer_reset_test(dut): # pre-reset fragments leak into the next output word. await tb.write_word(0xAA) await tb.reset() + await tb.assert_no_valid(4) post_reset_words = [0x11, 0x22] expected = _expected_reads( @@ -223,6 +230,23 @@ async def write_packer_reset_test(dut): WR_CLK_PERIOD_NS="5", RD_CLK_PERIOD_NS="9", ), + parameter_case( + "pack_to_wide_big_endian", + RST_ASYNC_G="true", + RST_POLARITY_G="'1'", + CASCADE_SIZE_G="1", + LAST_STAGE_ASYNC_G="true", + GEN_SYNC_FIFO_G="false", + SYNTH_MODE_G="inferred", + MEMORY_TYPE_G="distributed", + FWFT_EN_G="true", + WR_DATA_WIDTH_G="8", + RD_DATA_WIDTH_G="16", + LITTLE_ENDIAN_G="false", + ADDR_WIDTH_G="4", + WR_CLK_PERIOD_NS="7", + RD_CLK_PERIOD_NS="11", + ), ] diff --git a/tests/base/fifo/test_FifoSync.py b/tests/base/fifo/test_FifoSync.py index 0f62ee7fa0..aa3222471c 100644 --- a/tests/base/fifo/test_FifoSync.py +++ b/tests/base/fifo/test_FifoSync.py @@ -12,8 +12,9 @@ # - Sweep: Sweep memory type, `FWFT` vs standard mode, output pipeline depth, # reset polarity/style, width/depth scaling, and threshold placements under a # single common clock. -# - Stimulus: Drive burst writes and reads to fill, drain, and hover around the -# threshold points while the same clock advances both sides of the FIFO. +# - Stimulus: Drive burst writes and reads to fill, drain, hover around the +# threshold points, and optionally perform simultaneous read/write cycles at +# near-boundary occupancies while the same clock advances both sides. # - Checks: The bench verifies ordering, `full`/`empty` transitions, # programmable threshold behavior, and the latency difference between `FWFT` # and standard read operation. @@ -128,6 +129,23 @@ async def _wait_prog_empty(self, expected: int) -> None: while int(self.dut.prog_empty.value) != expected: await RisingEdge(self.dut.clk) + async def simultaneous_cycle(self, write_value: int) -> int: + # FWFT mode presents the current head word before the pop. Sampling + # before the edge lets the test prove that the same edge can consume the + # old head while accepting a new tail word. + await with_timeout(self._wait_valid(), 5, "us") + read_value = int(self.dut.dout.value) + await with_timeout(self._wait_not_full(), 5, "us") + self.dut.din.value = write_value + self.dut.wr_en.value = 1 + self.dut.rd_en.value = 1 + await RisingEdge(self.dut.clk) + self.dut.wr_en.value = 0 + self.dut.rd_en.value = 0 + await RisingEdge(self.dut.clk) + await Timer(2, unit="ns") + return read_value + @cocotb.test() async def basic_ordering_test(dut): @@ -207,6 +225,36 @@ async def threshold_flag_test(dut): await with_timeout(tb._wait_prog_empty(1), 5, "us") +@cocotb.test() +async def simultaneous_boundary_test(dut): + if not env_flag("CHECK_SIMULTANEOUS_BOUNDARY", default=False): + return + + tb = TB(dut, clk_period_ns=float(os.environ["CLK_PERIOD_NS"])) + await tb.reset() + + if not tb.fwft_enabled: + return + + capacity = 2 ** int(os.environ["ADDR_WIDTH_G"]) + seed_values = [0x30 + index for index in range(capacity - 1)] + for value in seed_values: + await tb.write_word(value) + + observed = [] + replacement_values = [0x90, 0x91, 0x92, 0x93] + for value in replacement_values: + observed.append(await tb.simultaneous_cycle(value)) + + assert observed == seed_values[: len(replacement_values)] + + expected_tail = seed_values[len(replacement_values) :] + replacement_values + for expected in expected_tail: + assert await tb.read_word() == expected + + await with_timeout(tb._wait_empty(), 5, "us") + + PARAMETER_SWEEP = [ # This matrix tracks the same behavior-changing axes as FifoAsync, minus # the async-only synchronizer depth controls that do not exist here. @@ -386,6 +434,23 @@ async def threshold_flag_test(dut): CLK_PERIOD_NS="5", RST_ACTIVE_HIGH="1", ), + parameter_case( + "fwft_simultaneous_near_full", + DATA_WIDTH_G="16", + ADDR_WIDTH_G="4", + FWFT_EN_G="true", + MEMORY_TYPE_G="block", + PIPE_STAGES_G="0", + RST_ASYNC_G="false", + RST_POLARITY_G="'1'", + FULL_THRES_G="12", + EMPTY_THRES_G="2", + CHECK_FULL_EMPTY="0", + CHECK_THRESHOLD_FLAGS="0", + CHECK_SIMULTANEOUS_BOUNDARY="1", + CLK_PERIOD_NS="5", + RST_ACTIVE_HIGH="1", + ), ] diff --git a/tests/base/general/test_Arbiter.py b/tests/base/general/test_Arbiter.py index c23abe32a6..700034fb72 100644 --- a/tests/base/general/test_Arbiter.py +++ b/tests/base/general/test_Arbiter.py @@ -13,7 +13,8 @@ # active-low reset case so the round-robin logic is exercised beyond a single # fixed width. # - Stimulus: Present competing request patterns, keep the current requester -# asserted to exercise hold behavior, and then rotate the contenders. +# asserted to exercise hold behavior, repeatedly rotate contenders to check +# starvation resistance, and then reset the pointer history. # - Checks: The grant must rotate in round-robin order, the hold case must keep # serving the same requester, and reset must clear the selection history. # - Timing: Grant updates are checked on arbitration boundaries only, and the @@ -162,6 +163,41 @@ async def reset_behavior_test(dut): assert int(dut.valid.value) == 0 +@cocotb.test() +async def starvation_rotation_test(dut): + if not env_flag("CHECK_STARVATION_ROTATION", default=False): + return + + tb = TB(dut) + await tb.reset() + + # Keep all requesters asserted, but drop the current winner for one cycle + # after every grant. Over several rounds every requester should be selected + # instead of the arbiter sticking to one low-index or high-index source. + seen = set() + all_requesters = (1 << tb.req_size) - 1 + request_mask = all_requesters + for _ in range(tb.req_size * 3): + tb.dut.req.value = request_mask + await tb.cycle(1) + assert int(dut.valid.value) == 1 + winner = int(dut.selected.value) + seen.add(winner) + + request_mask = all_requesters & ~(1 << winner) + tb.dut.req.value = request_mask + await tb.cycle(1) + assert int(dut.valid.value) == 1 + next_winner = int(dut.selected.value) + assert next_winner != winner + assert (request_mask >> next_winner) & 0x1 + seen.add(next_winner) + + request_mask = all_requesters + + assert seen == set(range(tb.req_size)) + + PARAMETER_SWEEP = [ parameter_case( "size4_baseline", @@ -184,6 +220,14 @@ async def reset_behavior_test(dut): RST_POLARITY_G="'0'", CLK_PERIOD_NS="7", ), + parameter_case( + "size5_starvation_rotation", + REQ_SIZE_G="5", + RST_ASYNC_G="false", + RST_POLARITY_G="'1'", + CHECK_STARVATION_ROTATION="1", + CLK_PERIOD_NS="5", + ), ] diff --git a/tests/base/general/test_WatchDogRst.py b/tests/base/general/test_WatchDogRst.py index 2ad47acbcc..3e3950506d 100644 --- a/tests/base/general/test_WatchDogRst.py +++ b/tests/base/general/test_WatchDogRst.py @@ -13,10 +13,11 @@ # active-low output case so both input and output polarity handling are # covered. # - Stimulus: Allow the watchdog to expire once with no keepalive activity, -# then periodically kick it before timeout to prove the non-expiring path. +# periodically kick it before timeout, and drive a chatter sequence that +# repeatedly approaches the timeout boundary before recovering. # - Checks: The timeout pulse or reset output must assert only after the # configured idle window and remain suppressed while keepalive pulses arrive -# in time. +# in time, including after multiple near-timeout noise bursts. # - Timing: The bench counts the timeout interval in exact cycles and checks # that each keepalive restarts the watchdog window rather than merely # delaying the already-expiring event. @@ -98,6 +99,30 @@ async def keepalive_prevents_timeout_test(dut): assert int(dut.rstOut.value) == tb.output_inactive_value() +@cocotb.test() +async def chattered_keepalive_sequence_test(dut): + tb = TB(dut) + await tb.cycle(4) + + # Exercise a noisier software/firmware keepalive pattern: each inactive + # stretch gets close to the programmed timeout, then a short active pulse + # must fully restart the watchdog window. + for inactive_cycles in [1, max(tb.duration - 1, 1), max(tb.duration - 2, 1), tb.duration // 2]: + dut.monIn.value = tb.input_inactive_value() + await tb.cycle(inactive_cycles) + assert int(dut.rstOut.value) == tb.output_inactive_value() + + dut.monIn.value = tb.input_active_value() + await tb.cycle(2) + assert int(dut.rstOut.value) == tb.output_inactive_value() + + # After the chatter sequence, a genuinely missing keepalive still needs to + # time out normally rather than leaving the watchdog wedged idle. + dut.monIn.value = tb.input_inactive_value() + await tb.cycle(tb.duration + 3) + assert int(dut.rstOut.value) == tb.output_active_value() + + PARAMETER_SWEEP = [ parameter_case( "active_high_baseline", diff --git a/tests/base/ram/test_DualPortRam.py b/tests/base/ram/test_DualPortRam.py index 7a39b97325..26b1ceed43 100644 --- a/tests/base/ram/test_DualPortRam.py +++ b/tests/base/ram/test_DualPortRam.py @@ -14,8 +14,9 @@ # active-high vs active-low reset so the wrapper-facing RAM modes are all # touched once. # - Stimulus: Write and read through both ports, create same-address read/write -# interactions to expose mode semantics, apply partial byte masks, and then -# assert reset on the B side. +# interactions to expose mode semantics, apply partial byte masks, optionally +# collide port-A writes with port-B reads, and then assert reset on the B +# side. # - Checks: The bench checks cross-port readback, port-A read-during-write # behavior, byte-lane merging, the extra hold behavior from `DOB_REG_G`, and # reset clearing of the registered output. @@ -174,6 +175,34 @@ async def byte_write_and_reset_test(dut): assert await tb.read_b(4) == 0xCAFE +@cocotb.test() +async def cross_port_collision_test(dut): + if not env_flag("CHECK_CROSS_PORT_COLLISION", default=False): + return + + tb = TB(dut) + await tb.warmup() + + await tb.write_a(5, 0x1357) + assert await tb.read_b(5) == 0x1357 + + # Schedule a port-A write and a port-B read to the same address on the same + # clock edge. The exact collision mode is backend dependent, so the durable + # contract for this portable inferred wrapper is that the new value is + # visible after the collision has settled. + tb.dut.addra.value = 5 + tb.dut.dina.value = 0x2468 + tb.dut.wea.value = 1 + tb.dut.weaByte.value = tb.full_byte_mask("weaByte") + tb.dut.addrb.value = 5 + await RisingEdge(dut.clka) + await tb.settle() + tb.dut.wea.value = 0 + tb.dut.weaByte.value = 0 + + assert await tb.read_b(5) == 0x2468 + + PARAMETER_SWEEP = [ parameter_case( "block_read_first", @@ -223,6 +252,23 @@ async def byte_write_and_reset_test(dut): CLKA_PERIOD_NS="5", CLKB_PERIOD_NS="5", ), + parameter_case( + "block_same_clock_collision", + MEMORY_TYPE_G="block", + REG_EN_G="true", + DOA_REG_G="false", + DOB_REG_G="false", + MODE_G="read-first", + BYTE_WR_EN_G="false", + DATA_WIDTH_G="16", + BYTE_WIDTH_G="8", + ADDR_WIDTH_G="4", + RST_ASYNC_G="false", + RST_POLARITY_G="'1'", + CHECK_CROSS_PORT_COLLISION="1", + CLKA_PERIOD_NS="5", + CLKB_PERIOD_NS="5", + ), ] diff --git a/tests/base/ram/test_SimpleDualPortRam.py b/tests/base/ram/test_SimpleDualPortRam.py index c0ac266b2e..3b114cb0cf 100644 --- a/tests/base/ram/test_SimpleDualPortRam.py +++ b/tests/base/ram/test_SimpleDualPortRam.py @@ -13,7 +13,8 @@ # registration, byte-write enable, and asynchronous plus active-low reset # behavior. # - Stimulus: Write through port A and read through port B, apply partial byte -# masks to an existing word, and then reset after a registered output has +# masks to an existing word, optionally hold port-B enable low in direct and +# registered-output modes, and then reset after a registered output has # captured data. # - Checks: The bench checks basic dual-port readback, byte-write merging, hold # behavior of the optional B output register, and reset clearing of that @@ -113,6 +114,56 @@ async def byte_write_enable_test(dut): assert await tb.read_word(2) == 0x12EF +@cocotb.test() +async def read_enable_hold_test(dut): + if not env_flag("CHECK_READ_ENABLE_HOLD", default=False): + return + + tb = TB(dut) + await tb.cycle_a(1) + await tb.cycle_b(1) + + await tb.write_word(0, 0x1111) + await tb.write_word(1, 0x2222) + assert await tb.read_word(0) == 0x1111 + + # Port B should hold its previous output while `enb` is low, even if the + # address changes underneath it. + dut.enb.value = 0 + dut.addrb.value = 1 + await tb.cycle_b(2) + assert int(dut.doutb.value) == 0x1111 + + dut.enb.value = 1 + assert await tb.read_word(1) == 0x2222 + + +@cocotb.test() +async def registered_read_enable_hold_test(dut): + if not env_flag("CHECK_REGISTERED_ENB_HOLD", default=False): + return + + tb = TB(dut) + await tb.cycle_a(1) + await tb.cycle_b(1) + assert tb.dob_reg_enabled + + await tb.write_word(0, 0x1111) + await tb.write_word(1, 0x2222) + assert await tb.read_word(0) == 0x1111 + + # With DOB_REG_G enabled, `enb=0` should hold the registered B output even + # while the address changes and port A updates the addressed memory word. + dut.enb.value = 0 + dut.addrb.value = 1 + await tb.write_word(1, 0x3333) + await tb.cycle_b(3) + assert int(dut.doutb.value) == 0x1111 + + dut.enb.value = 1 + assert await tb.read_word(1) == 0x3333 + + @cocotb.test() async def registered_output_hold_test(dut): tb = TB(dut) @@ -193,6 +244,7 @@ async def reset_behavior_test(dut): ADDR_WIDTH_G="4", RST_ASYNC_G="false", RST_POLARITY_G="'1'", + CHECK_REGISTERED_ENB_HOLD="1", CLKA_PERIOD_NS="5", CLKB_PERIOD_NS="5", ), @@ -235,6 +287,20 @@ async def reset_behavior_test(dut): CLKA_PERIOD_NS="5", CLKB_PERIOD_NS="5", ), + parameter_case( + "read_enable_hold", + MEMORY_TYPE_G="block", + DOB_REG_G="false", + BYTE_WR_EN_G="false", + DATA_WIDTH_G="16", + BYTE_WIDTH_G="8", + ADDR_WIDTH_G="4", + RST_ASYNC_G="false", + RST_POLARITY_G="'1'", + CHECK_READ_ENABLE_HOLD="1", + CLKA_PERIOD_NS="5", + CLKB_PERIOD_NS="5", + ), ] diff --git a/tests/base/ram/test_TrueDualPortRam.py b/tests/base/ram/test_TrueDualPortRam.py index 1d92cd3eeb..d900e7b9cc 100644 --- a/tests/base/ram/test_TrueDualPortRam.py +++ b/tests/base/ram/test_TrueDualPortRam.py @@ -13,8 +13,8 @@ # byte-write plus `DOB`-registered case, and include an asynchronous # active-low reset case. # - Stimulus: Alternate reads and writes on both ports, create same-address -# interactions to expose mode semantics, apply partial byte writes, and then -# reset after a registered capture. +# interactions to expose mode semantics, optionally collide both write ports, +# apply partial byte writes, and then reset after a registered capture. # - Checks: The bench verifies cross-port visibility, mode-specific # read-during-write results, byte-lane masking, registered-output hold # behavior, and reset recovery. @@ -173,6 +173,46 @@ async def byte_write_enable_test(dut): assert await tb.read_a(3) == 0x12EF +@cocotb.test() +async def dual_write_collision_test(dut): + if not env_flag("CHECK_DUAL_WRITE_COLLISION", default=False): + return + + tb = TB(dut) + await tb.warmup() + + await tb.write_a(5, 0x1111) + assert await tb.read_a(5) == 0x1111 + + # Drive simultaneous same-address writes from both ports on a shared clock. + # The final winner is not a portable contract for inferred dual-write RAMs, + # but the collision must not poison adjacent addresses or prevent later + # deterministic writes to the collided address. + dut.addra.value = 5 + dut.dina.value = 0xAAAA + dut.wea.value = 1 + dut.weaByte.value = tb.full_byte_mask("weaByte") + dut.addrb.value = 5 + dut.dinb.value = 0x5555 + dut.web.value = 1 + dut.webByte.value = tb.full_byte_mask("webByte") + await RisingEdge(dut.clka) + await tb.settle() + dut.wea.value = 0 + dut.weaByte.value = 0 + dut.web.value = 0 + dut.webByte.value = 0 + + observed = await tb.read_a(5) + assert observed in (0xAAAA, 0x5555) + + await tb.write_b(6, 0x3333) + assert await tb.read_a(6) == 0x3333 + + await tb.write_a(5, 0x7777) + assert await tb.read_b(5) == 0x7777 + + @cocotb.test() async def registered_output_hold_test(dut): tb = TB(dut) @@ -290,6 +330,21 @@ async def reset_behavior_test(dut): CLKA_PERIOD_NS="5", CLKB_PERIOD_NS="7", ), + parameter_case( + "same_clock_dual_write_collision", + MODE_G="read-first", + DOA_REG_G="false", + DOB_REG_G="false", + BYTE_WR_EN_G="false", + DATA_WIDTH_G="16", + BYTE_WIDTH_G="8", + ADDR_WIDTH_G="4", + RST_ASYNC_G="false", + RST_POLARITY_G="'1'", + CHECK_DUAL_WRITE_COLLISION="1", + CLKA_PERIOD_NS="5", + CLKB_PERIOD_NS="5", + ), ] diff --git a/tests/base/sync/test_SynchronizerFifo.py b/tests/base/sync/test_SynchronizerFifo.py index a9c05c8e9e..6e6919cf9c 100644 --- a/tests/base/sync/test_SynchronizerFifo.py +++ b/tests/base/sync/test_SynchronizerFifo.py @@ -13,7 +13,9 @@ # reset case so the small CDC FIFO is covered both in its fast path and in # real CDC mode. # - Stimulus: Send an ordered data stream through the FIFO, run a common-clock -# bypass transfer, and then assert reset while data history exists. +# bypass transfer, optionally pause the read side between bursty writes, +# optionally reset while FWFT data is pending, and then assert reset while +# data history exists. # - Checks: Data ordering must be preserved, the common-clock path must bypass # the deeper CDC behavior, and reset must restore the configured initial # output value. @@ -132,6 +134,21 @@ async def read(self) -> int: await self.cycle_rd(1) return value + async def read_with_pause(self) -> int: + assert not self.common_clk + + # Most SynchronizerFifo users tie rd_en high, but the FIFO still has a + # real read-enable input. This helper models a consumer that explicitly + # pauses between pops, so valid can rise and hold before the pop edge. + self.dut.rd_en.value = 0 + await with_timeout(self._wait_valid(), 5, "us") + value = int(self.dut.dout.value) + self.dut.rd_en.value = 1 + await self.cycle_rd(1) + self.dut.rd_en.value = 0 + await self.cycle_rd(1) + return value + async def _wait_valid(self) -> None: # Poll on the read clock because valid is generated in that domain and # can appear several cycles after the write that filled the FIFO. @@ -187,6 +204,67 @@ async def reset_value_test(dut): assert observed == tb.init_value +@cocotb.test() +async def async_burst_read_gap_test(dut): + if not env_flag("CHECK_ASYNC_BURST_GAPS", default=False): + return + + tb = TB(dut) + await tb.reset() + assert not tb.common_clk + dut.rd_en.value = 0 + + first_burst = [0x10 + index for index in range(5)] + for value in first_burst: + await tb.write(value) + + # Hold the read side idle long enough for pointer synchronization and FWFT + # prefetch to settle, then consume only part of the burst. + await tb.cycle_rd(8) + for expected in first_burst: + assert await tb.read_with_pause() == expected + + # After a paused burst drains, a second burst should still cross correctly. + # This keeps the test focused on explicit read-enable gaps rather than + # overflow behavior, because SynchronizerFifo intentionally exposes no + # source-side backpressure. + second_burst = [0x40 + index for index in range(4)] + for value in second_burst: + await tb.write(value) + for expected in second_burst: + assert await tb.read_with_pause() == expected + + +@cocotb.test() +async def reset_while_prefetched_test(dut): + if not env_flag("CHECK_RESET_WHILE_PREFETCHED", default=False): + return + + tb = TB(dut) + await tb.reset() + assert not tb.common_clk + dut.rd_en.value = 0 + + # Let a burst cross into the read domain while the consumer is paused. In + # FWFT mode that can leave a visible word waiting at dout before the pop + # edge, which is the reset crossing this case is meant to guard. + for value in [0x20, 0x21, 0x22]: + await tb.write(value) + await with_timeout(tb._wait_valid(), 5, "us") + + await tb.reset() + dut.rd_en.value = 0 + assert int(dut.valid.value) == 0 + + # Post-reset data should transfer cleanly with no stale pre-reset word + # leaking through the paused read path. + post_reset = [0x60, 0x61] + for value in post_reset: + await tb.write(value) + for expected in post_reset: + assert await tb.read_with_pause() == expected + + PARAMETER_SWEEP = [ parameter_case( "common_clock_bypass", @@ -210,6 +288,19 @@ async def reset_value_test(dut): WR_CLK_PERIOD_NS="5", RD_CLK_PERIOD_NS="9", ), + parameter_case( + "async_bursty_read_gaps", + RST_ASYNC_G="true", + RST_POLARITY_G="'1'", + COMMON_CLK_G="false", + MEMORY_TYPE_G="distributed", + DATA_WIDTH_G="8", + ADDR_WIDTH_G="4", + CHECK_ASYNC_BURST_GAPS="1", + CHECK_RESET_WHILE_PREFETCHED="1", + WR_CLK_PERIOD_NS="3", + RD_CLK_PERIOD_NS="13", + ), ] diff --git a/tests/protocols/coaxpress/README.md b/tests/protocols/coaxpress/README.md index c1633fb190..f67dab1496 100644 --- a/tests/protocols/coaxpress/README.md +++ b/tests/protocols/coaxpress/README.md @@ -57,7 +57,7 @@ intentional limitation, not as silent proof of complete spec compliance. | `test_CoaXPressEventAckMsg.py` | `CoaXPressEventAckMsg` | Event acknowledgment wire format, section `9.8.3`, Table 30 | Near-normative subset | | `test_CoaXPressTxLsFsm.py` | `CoaXPressTxLsFsm` | Low-speed idle cadence and default trigger serialization, section `9.3.1.1` / Table 15 | Partial protocol | | `test_CoaXPressTx.py` | `CoaXPressTx` | Control/event-acknowledgment arbitration and software-trigger path across the TX assembly | RTL-contract with spec packet classes | -| `test_CoaXPressConfig.py` | `CoaXPressConfig` | Control command packet formatting and tag handling, section `9.6.1.2` / `9.6.2` | Checked in but skipped | +| `test_CoaXPressConfig.py` | `CoaXPressConfig` | Control command packet formatting, CRC generation, tag handling, and SRPv3 response completion through the real `SrpV3AxiLite` ingress path, section `9.6.1.2` / `9.6.2` | Near-normative subset | | `test_CoaXPressCore.py` | `CoaXPressCore` | AXI-Lite control of tagged config request generation plus software-visible `RxOverflowCnt` / `RxFsmErrorCnt` status behavior at the full-core boundary | RTL-contract with spec request prefix and top-level error-status checks | | `test_CoaXPressOverFiberBridgeTx.py` | `CoaXPressOverFiberBridgeTx` | CXPoF start/control/payload/terminate words, section `6.3.1` to `6.3.6` in `CXPR-008-2021` | Near-normative subset | | `test_CoaXPressOverFiberBridgeRx.py` | `CoaXPressOverFiberBridgeRx` | CXPoF start-word decode back into CoaXPress packet and `IO_ACK` words | Partial protocol | @@ -105,10 +105,11 @@ exposed by the current checked-in RTL. The current checked-in coverage is split: - `test_CoaXPressConfig.py` - - intended normative request-format coverage for section `9.6.1.2` and - `9.6.2` - - currently skipped because the real `CoaXPressConfig` / `SrpV3AxiLite` - ingress path does not complete in the bench + - checks untagged read and tagged write control-command formatting for + section `9.6.1.2` and `9.6.2` + - drives requests through the real `CoaXPressConfig` / `SrpV3AxiLite` + ingress path and validates both the serialized config packet and the + completed SRPv3 response - `test_CoaXPressRxLane.py` and `test_CoaXPressRx.py` - now drive fuller control-ack shapes on the wire: code, size, reply data, CRC placeholder, and `EOP` @@ -212,10 +213,12 @@ Current checked-in coverage: - `/T/` plus `/I/` termination - `test_CoaXPressOverFiberBridgeRx.py` - RX start-word decode for normal packets and `IO_ACK` - - HKP forwarding, including a housekeeping-to-payload transition + - embedded EOP K-code reconstruction for stream marker and packet-end words + - HKP forwarding, including a housekeeping-to-payload transition and an + HKP-carried CXP EOP word - negative lane-placement checks for `/S/`, `/Q/`, `/T/`, and `/E/` - - lane-0 `/Q/` no-output guardrail, `/E/` packet abort behavior, and recovery - to a following valid low-speed packet + - lane-0 `/Q/` no-output guardrail, `/E/` packet abort behavior before and + after payload, and recovery to a following valid low-speed packet - `test_CoaXPressOverFiberBridge.py` - top-level 32b/64b gearbox integration around the bridge leaves - RX-side 64b gearbox coverage for `/E/` abort/recovery, HKP-to-payload @@ -228,6 +231,20 @@ Still open on the bridge side: - full housekeeping protocol semantics beyond raw HKP forwarding and the current HKP-to-payload transition check +Current RTL support limits observed while expanding the bridge tests: + +- `/Q/` ordered sets are not decoded into any bridge-visible state, sequence + tracker, status output, or CXP-side indication. The current contract is only + that `/Q/` in the interpacket gap is suppressed and later valid traffic + recovers. +- `/E/` has no bridge-visible status output. When it appears during a packet, + the RX bridge aborts the active nGMII packet and returns to idle; if the start + word was already accepted, the CXP `SOP` and packet-type words may already + have been emitted, but no synthetic CXP `EOP` is generated. +- HKP handling is raw forwarding. The RX bridge does not validate HKP content + semantics or expose a separate housekeeping parser; it reconstructs K-coded + words and then returns to normal payload/EOP handling. + ## Known Limitations The current checked-in CoaXPress suite should not be described as full protocol @@ -235,7 +252,6 @@ compliance coverage. The most important open limits are: -- `CoaXPressConfig` is still skipped - `CoaXPressRxHsFsm` still has an open bonded-receive issue on back-to-back short four-lane image frames: later one-word tails can miss `TLAST`, which merges or truncates adjacent frames diff --git a/tests/protocols/coaxpress/test_CoaXPressConfig.py b/tests/protocols/coaxpress/test_CoaXPressConfig.py index 9c78aee9b5..9e5d598bf1 100644 --- a/tests/protocols/coaxpress/test_CoaXPressConfig.py +++ b/tests/protocols/coaxpress/test_CoaXPressConfig.py @@ -11,17 +11,18 @@ # Test methodology: # - Sweep: Cover the two request-serialization branches that are unique to # `CoaXPressConfig`: untagged reads and tagged writes. -# - Stimulus: Drive one-beat SRPv3 request frames into `cfgIb` and capture the -# emitted CoaXPress low-speed byte stream on `cfgTx`. +# - Stimulus: Drive wide SRPv3 request frames into `cfgIb`, capture the emitted +# CoaXPress low-speed byte stream on `cfgTx`, and feed the completion side +# with one config receive acknowledgment. # - Checks: The DUT must emit the spec-shaped request prefix/suffix, select the # correct tagged or untagged packet type, preserve the address and write-data -# fields, and increment the tagged packet counter across transactions. +# fields, calculate the command CRC, increment the tagged packet counter, and +# complete the SRPv3 response frame. # - Timing: Requests are accepted through the real `TREADY` handshake and the -# test waits on the serialized CoaXPress bytes rather than assuming an ideal -# one-cycle transfer through the assembly. +# test waits on both serialized CoaXPress bytes and the returned SRPv3 frame +# rather than assuming an ideal one-cycle transfer through the assembly. import cocotb -import pytest from cocotb.triggers import RisingEdge, Timer, with_timeout from tests.common.regression_utils import run_surf_vhdl_test @@ -29,34 +30,24 @@ CXP_EOP, CXP_SOP, collect_stream_bytes, + cxp_crc_word, endian_swap32, - pack_u32_words_le, + repeat_byte, reset_signals, - send_axis_payload, set_initial_values, start_clock, word_to_bytes, ) - -pytestmark = pytest.mark.skip( - reason=( - "Blocked by a suspected CoaXPressConfig/SrpV3AxiLite integration issue: " - "the real SRP-driven request path does not complete within the current bench timeout." - ) +from tests.protocols.srp.srp_test_utils import ( + FlatSrpAxis, + SRP_READ, + SRP_WRITE, + SrpV3Request, + assert_srpv3_response, + srpv3_frame, ) -READ_OPCODE = 0x0 -WRITE_OPCODE = 0x1 - - -def _srp_request_words(*, opcode: int, tid: int, addr: int, req_size: int, write_data: int | None = None) -> list[int]: - words = [0x00000003 | (opcode << 8), tid, addr & 0xFFFFFFFF, 0x00000000, req_size] - if write_data is not None: - words.append(write_data & 0xFFFFFFFF) - return words - - async def _drive_cfg_rx_completion(dut, value: int, *, hold_cycles: int = 8) -> None: dut.cfgRxTData.value = value dut.cfgRxTValid.value = 1 @@ -67,8 +58,7 @@ async def _drive_cfg_rx_completion(dut, value: int, *, hold_cycles: int = 8) -> dut.cfgRxTData.value = 0 -@cocotb.test() -async def coaxpress_config_untagged_read_request_test(dut): +async def _setup_config_bench(dut, *, config_pkt_tag: int) -> FlatSrpAxis: start_clock(dut.cfgClk, period_ns=4.0) set_initial_values( dut, @@ -84,17 +74,36 @@ async def coaxpress_config_untagged_read_request_test(dut): "cfgRxTData": 0, "configTimerSize": 4096, "configErrResp": 1, - "configPktTag": 0, + "configPktTag": config_pkt_tag, }, ) - await reset_signals(dut, clk=dut.cfgClk, reset_names=("cfgRst",), assert_cycles=10, release_cycles=5) + await reset_signals( + dut, + clk=dut.cfgClk, + reset_names=("cfgRst",), + assert_cycles=10, + release_cycles=5, + ) + axis = FlatSrpAxis( + dut, + clk=dut.cfgClk, + source_prefix="S_CFG_IB", + sink_prefix="M_CFG_OB", + data_bytes=32, + ) + axis.init_source() + axis.init_sink() + return axis + + +@cocotb.test() +async def coaxpress_config_untagged_read_request_test(dut): + axis = await _setup_config_bench(dut, config_pkt_tag=0) tid = 0x12345678 addr = 0x00000040 read_data = 0xDDAA5501 - request_payload = pack_u32_words_le( - _srp_request_words(opcode=READ_OPCODE, tid=tid, addr=addr, req_size=0x00000003) - ) + request = SrpV3Request(SRP_READ, tid, addr, 4) tx_task = cocotb.start_soon( collect_stream_bytes( @@ -107,7 +116,8 @@ async def coaxpress_config_untagged_read_request_test(dut): timeout_cycles=8000, ) ) - await send_axis_payload(dut, clk=dut.cfgClk, prefix="S_CFG_IB", payload=request_payload, width_bytes=32, tuser=0x2) + response_task = cocotb.start_soon(axis.recv_response(timeout_time=20)) + await axis.send_words(srpv3_frame(request)) tx_bytes = await with_timeout(tx_task, 20, "us") @@ -117,33 +127,22 @@ async def coaxpress_config_untagged_read_request_test(dut): + bytes(word_to_bytes(0x04000000)) + bytes(word_to_bytes(endian_swap32(addr))) ) + expected_crc = cxp_crc_word([0x04000000, endian_swap32(addr)]) assert tx_bytes.startswith(expected_prefix) + assert tx_bytes[16:20] == bytes(word_to_bytes(expected_crc)) assert tx_bytes[-4:] == bytes(word_to_bytes(CXP_EOP)) - assert tx_bytes[16:20] != b"\x00\x00\x00\x00" + await _drive_cfg_rx_completion(dut, read_data << 32) + assert_srpv3_response( + await response_task, + request, + [read_data], + ) @cocotb.test() async def coaxpress_config_tagged_write_tag_increment_test(dut): - start_clock(dut.cfgClk, period_ns=4.0) - set_initial_values( - dut, - { - "S_CFG_IB_TVALID": 0, - "S_CFG_IB_TDATA": 0, - "S_CFG_IB_TKEEP": 0, - "S_CFG_IB_TLAST": 0, - "S_CFG_IB_TUSER": 0, - "M_CFG_OB_TREADY": 1, - "M_CFG_TX_TREADY": 0, - "cfgRxTValid": 0, - "cfgRxTData": 0, - "configTimerSize": 4096, - "configErrResp": 1, - "configPktTag": 1, - }, - ) - await reset_signals(dut, clk=dut.cfgClk, reset_names=("cfgRst",), assert_cycles=10, release_cycles=5) + axis = await _setup_config_bench(dut, config_pkt_tag=1) requests = [ (0x0BADB002, 0x00000020, 0x11223344, 0x00), @@ -151,9 +150,7 @@ async def coaxpress_config_tagged_write_tag_increment_test(dut): ] for tid, addr, write_data, expected_tag in requests: - request_payload = pack_u32_words_le( - _srp_request_words(opcode=WRITE_OPCODE, tid=tid, addr=addr, req_size=0x00000003, write_data=write_data) - ) + request = SrpV3Request(SRP_WRITE, tid, addr, 4) tx_task = cocotb.start_soon( collect_stream_bytes( @@ -166,7 +163,8 @@ async def coaxpress_config_tagged_write_tag_increment_test(dut): timeout_cycles=8000, ) ) - await send_axis_payload(dut, clk=dut.cfgClk, prefix="S_CFG_IB", payload=request_payload, width_bytes=32, tuser=0x2) + response_task = cocotb.start_soon(axis.recv_response(timeout_time=20)) + await axis.send_words(srpv3_frame(request, [write_data])) tx_bytes = await with_timeout(tx_task, 20, "us") assert tx_bytes[:4] == bytes(word_to_bytes(CXP_SOP)) @@ -175,9 +173,18 @@ async def coaxpress_config_tagged_write_tag_increment_test(dut): assert tx_bytes[12:16] == bytes(word_to_bytes(0x04000001)) assert tx_bytes[16:20] == bytes(word_to_bytes(endian_swap32(addr))) assert tx_bytes[20:24] == bytes(word_to_bytes(write_data)) + expected_crc = cxp_crc_word( + [repeat_byte(expected_tag), 0x04000001, endian_swap32(addr), write_data] + ) + assert tx_bytes[24:28] == bytes(word_to_bytes(expected_crc)) assert tx_bytes[-4:] == bytes(word_to_bytes(CXP_EOP)) await _drive_cfg_rx_completion(dut, 0) + assert_srpv3_response( + await response_task, + request, + [write_data], + ) def test_CoaXPressConfig(): diff --git a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py index 2a770cc356..e95b1a83e5 100644 --- a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py +++ b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py @@ -9,15 +9,18 @@ ############################################################################## # Test methodology: -# - Sweep: Exercise bridge RX low-speed packet decode, `IO_ACK`, HKP forwarding, -# HKP-to-payload transition, misplaced control-character guardrails, `/Q/` -# no-output behavior, `/E/` abort behavior, and recovery to a later packet. +# - Sweep: Exercise bridge RX low-speed packet decode, `IO_ACK`, embedded EOP +# K-code reconstruction, HKP forwarding, HKP-to-payload transition, misplaced +# control-character guardrails, `/Q/` no-output behavior, `/E/` abort behavior, +# and recovery to a later packet. # - Stimulus: Drive CXPoF start/payload/terminate sequences, housekeeping start -# words, lane-misplaced `/S/`, `/Q/`, `/T/`, and `/E/` controls, lane-0 `/Q/`, -# and an explicit `/E/` during an active low-speed packet. +# words, embedded marker/EOP K-codes, lane-misplaced `/S/`, `/Q/`, `/T/`, and +# `/E/` controls, lane-0 `/Q/`, and explicit `/E/` aborts during active +# low-speed packets. # - Checks: The bridge must reconstruct repeated-byte `SOP`, packet-type, -# payload, and `EOP` words for valid packets, emit standalone `IO_ACK`, forward -# raw HKP words, suppress malformed control traffic, and recover cleanly. +# payload, marker, and `EOP` words for valid packets, emit standalone `IO_ACK`, +# forward raw HKP words, suppress malformed control traffic, and recover +# cleanly. # - Timing: The bench samples the reconstructed CXP word stream every cycle so # it checks the bridge's real shift-register latency and output ordering. @@ -29,6 +32,7 @@ CXP_IDLE, CXP_IDLE_K, CXP_IO_ACK, + CXP_MARKER, CXP_PKT_EVENT_ACK, CXP_SOP, CXPOF_ERROR, @@ -196,6 +200,140 @@ async def drive(rxd: int, rxc: int) -> None: ] +@cocotb.test() +async def coaxpress_over_fiber_bridge_rx_embedded_eop_kcode_test(dut): + # A high-speed CXP-PHY EOP can carry an embedded CoaXPress K-code in + # EopData0. Cover the marker and packet-end cases explicitly so this bridge + # is not only checked against the common K29.7 packet-end path. + start_clock(dut.clk) + dut.rst.setimmediatevalue(1) + dut.xgmiiRxd.setimmediatevalue(0x07070707) + dut.xgmiiRxc.setimmediatevalue(0xF) + await reset_dut(dut, clk_name="clk", reset_names=("rst",)) + + observed: list[tuple[int, int]] = [] + + async def drive(rxd: int, rxc: int) -> None: + dut.xgmiiRxd.value = rxd + dut.xgmiiRxc.value = rxc + await cycle(dut.clk, 1) + sample = (int(dut.rxData.value), int(dut.rxDataK.value)) + if sample != (CXP_IDLE, CXP_IDLE_K): + observed.append(sample) + + # First packet ends with embedded K28.3, which should reconstruct a CXP + # stream-marker word rather than a packet-end word. + await drive(_cxp_start_word(CXP_PKT_EVENT_ACK), 0x1) + await drive(0x11223344, 0x0) + await drive(0x07FD007C, 0xC) + await drive(0x07070707, 0xF) + await drive(0x07070707, 0xF) + + # A later packet using embedded K29.7 should still reconstruct the normal + # CXP EOP word and prove the marker split did not corrupt state. + await drive(_cxp_start_word(CXP_PKT_EVENT_ACK), 0x1) + await drive(0x55667788, 0x0) + await drive(0x07FD00FD, 0xC) + await drive(0x07070707, 0xF) + await drive(0x07070707, 0xF) + + assert observed == [ + (CXP_SOP, 0xF), + (repeat_byte(CXP_PKT_EVENT_ACK), 0x0), + (0x11223344, 0x0), + (CXP_MARKER, 0xF), + (CXP_SOP, 0xF), + (repeat_byte(CXP_PKT_EVENT_ACK), 0x0), + (0x55667788, 0x0), + (CXP_EOP, 0xF), + ] + + +@cocotb.test() +async def coaxpress_over_fiber_bridge_rx_hkp_eop_kcode_test(dut): + # A high-speed HKP packet can carry a CoaXPress K-code word that is not + # represented with XGMII control bits. The current bridge forwards that HKP + # word on the CXP side with all K bits asserted and terminates cleanly when + # the HKP word itself is the CXP EOP code. + start_clock(dut.clk) + dut.rst.setimmediatevalue(1) + dut.xgmiiRxd.setimmediatevalue(0x07070707) + dut.xgmiiRxc.setimmediatevalue(0xF) + await reset_dut(dut, clk_name="clk", reset_names=("rst",)) + + observed: list[tuple[int, int]] = [] + + async def drive(rxd: int, rxc: int) -> None: + dut.xgmiiRxd.value = rxd + dut.xgmiiRxc.value = rxc + await cycle(dut.clk, 1) + sample = (int(dut.rxData.value), int(dut.rxDataK.value)) + if sample != (CXP_IDLE, CXP_IDLE_K): + observed.append(sample) + + await drive(CXPOF_START | (0x81 << 8), 0x1) + await drive(CXP_EOP, 0x0) + await drive(0x07070707, 0xF) + await drive(0x07070707, 0xF) + + await drive(_cxp_start_word(CXP_PKT_EVENT_ACK), 0x1) + await drive(0x99AABBCC, 0x0) + await drive(0x07FD00FD, 0xC) + await drive(0x07070707, 0xF) + await drive(0x07070707, 0xF) + + assert observed == [ + (CXP_EOP, 0xF), + (CXP_SOP, 0xF), + (repeat_byte(CXP_PKT_EVENT_ACK), 0x0), + (0x99AABBCC, 0x0), + (CXP_EOP, 0xF), + ] + + +@cocotb.test() +async def coaxpress_over_fiber_bridge_rx_error_after_sop_recovery_test(dut): + # `/E/` immediately after the SOP/type phase is another abort placement that + # matters for recovery. The bridge may already have emitted the CXP SOP and + # type words queued by the start word, but it must not invent an EOP for the + # aborted packet and must accept the next clean packet. + start_clock(dut.clk) + dut.rst.setimmediatevalue(1) + dut.xgmiiRxd.setimmediatevalue(0x07070707) + dut.xgmiiRxc.setimmediatevalue(0xF) + await reset_dut(dut, clk_name="clk", reset_names=("rst",)) + + observed: list[tuple[int, int]] = [] + + async def drive(rxd: int, rxc: int) -> None: + dut.xgmiiRxd.value = rxd + dut.xgmiiRxc.value = rxc + await cycle(dut.clk, 1) + sample = (int(dut.rxData.value), int(dut.rxDataK.value)) + if sample != (CXP_IDLE, CXP_IDLE_K): + observed.append(sample) + + await drive(_cxp_start_word(CXP_PKT_EVENT_ACK), 0x1) + await drive(CXPOF_ERROR | (CXPOF_IDLE << 8) | (CXPOF_IDLE << 16) | (CXPOF_IDLE << 24), 0x1) + await drive(0x07070707, 0xF) + await drive(0x07070707, 0xF) + + await drive(_cxp_start_word(CXP_PKT_EVENT_ACK), 0x1) + await drive(0x12345678, 0x0) + await drive(0x07FD00FD, 0xC) + await drive(0x07070707, 0xF) + await drive(0x07070707, 0xF) + + assert observed == [ + (CXP_SOP, 0xF), + (repeat_byte(CXP_PKT_EVENT_ACK), 0x0), + (CXP_SOP, 0xF), + (repeat_byte(CXP_PKT_EVENT_ACK), 0x0), + (0x12345678, 0x0), + (CXP_EOP, 0xF), + ] + + @cocotb.test() async def coaxpress_over_fiber_bridge_rx_hkp_then_payload_mix_test(dut): # A housekeeping start word may be followed by one raw K-coded HKP word and From 348b23459150ea9108c3dce36290a016ebf091ec Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 20 May 2026 15:16:22 -0700 Subject: [PATCH 05/10] Create AGENTS.md an supporting files. --- AGENTS.md | 115 ++++++++++++++++++++++++++++++++++++++++++++ README.md | 15 ++++++ axi/README.md | 14 ++++++ base/README.md | 14 ++++++ devices/README.md | 11 +++++ dsp/README.md | 10 ++++ ethernet/README.md | 14 ++++++ protocols/README.md | 12 +++++ python/README.md | 14 ++++++ xilinx/README.md | 12 +++++ 10 files changed, 231 insertions(+) create mode 100644 AGENTS.md create mode 100644 axi/README.md create mode 100644 base/README.md create mode 100644 devices/README.md create mode 100644 dsp/README.md create mode 100644 ethernet/README.md create mode 100644 protocols/README.md create mode 100644 python/README.md create mode 100644 xilinx/README.md diff --git a/AGENTS.md b/AGENTS.md new file mode 100644 index 0000000000..6ea84ba294 --- /dev/null +++ b/AGENTS.md @@ -0,0 +1,115 @@ +# Agent Guidance For SURF + +SURF is the SLAC Ultimate RTL Framework: a shared VHDL/IP, ruckus, cocotb, and PyRogue support library. Treat it as reusable infrastructure, not a single board project. Keep changes narrow, preserve existing public interfaces, and avoid broad style cleanups unless the user asks for them. + +Do not stage files or make git commits unless the user explicitly asks for staging or committing. + +## Repository Map + +Start with [README.md](README.md) for user-facing links and the source tree index. The most useful local orientation files are: + +- [axi/README.md](axi/README.md) for AXI-Lite, AXI4, AXI Stream, DMA, bridges, and simulation-link RTL. +- [base/README.md](base/README.md) for foundational RTL packages, FIFOs, RAMs, CDC, resets, CRCs, and generic helpers. +- [devices/README.md](devices/README.md) for vendor/device-specific RTL support blocks. +- [dsp/README.md](dsp/README.md) for generic and Xilinx-specific DSP support. +- [ethernet/README.md](ethernet/README.md) for MAC, UDP/IP, raw Ethernet, RoCEv2, and high-speed Ethernet cores. +- [protocols/README.md](protocols/README.md) for PGP, SSI, SRP, RSSI, CoaXPress, JESD204B, I2C/SPI/UART, and related protocol cores. +- [xilinx/README.md](xilinx/README.md) for Xilinx-family primitives, wrappers, and XVC UDP support. +- [python/README.md](python/README.md) for the PyRogue package under `python/surf`. +- [tests/README.md](tests/README.md) for cocotb regression layout, methodology comments, helper reuse, and simulator conventions. + +Top-level `ruckus.tcl` loads `axi`, `base`, `dsp`, `devices`, `ethernet`, `protocols`, and `xilinx`. Module-level `ruckus.tcl` files should continue to be the source of truth for which HDL files and submodules are part of a build. + +## VHDL Conventions + +- Keep the standard SLAC/SURF license banner at the top of maintained source files. Use the nearby file style when adding a new file. +- Target VHDL-2008 as used by the Makefile/GHDL flow. Do not modernize older files from `std_logic_arith`/`std_logic_unsigned` to `numeric_std` as an incidental change. +- Use three-space indentation. `vsg-linter.yml` is the style authority; run `./.venv/bin/vsg -c vsg-linter.yml path/to/file.vhd` for edited VHDL when practical. +- Prefer SURF package types and helpers, especially `surf.StdRtlPkg` aliases such as `sl` and `slv`, and established record types from AXI, AXI Stream, SSI, and related packages. +- Follow existing naming patterns: generics end in `_G`, constants in `_C`, record types use `Type`, and module names are PascalCase. +- For registered logic, match the local `RegType`, `REG_INIT_C`, `r`, `rin`, `comb`, and `seq` pattern. Preserve `TPD_G`, `RST_POLARITY_G`, and `RST_ASYNC_G` reset idioms when present. +- Use named association for component/entity instantiations and keep reset, clock, AXI, and stream ports grouped consistently with neighboring modules. On port maps, add aligned trailing direction comments using the instance port direction, for example `clk => axilClk, -- [in]` and `axiReadSlave => axiReadSlave); -- [out]`. Use `-- [inout]` when a port is bidirectional. +- Put synthesizable RTL in `rtl/`, simulation-only models in `sim/`, testbenches in `tb/`, flattened or tool-facing adapters in `wrappers/` or `ip_integrator/`, and FPGA-family specializations in family-named directories such as `gth7`, `gthUltraScale`, `gtyUltraScale+`, `7Series`, or `UltraScale`. +- Keep wrappers thin. Prefer existing SURF adapter entities for AXI/AXI Stream record flattening before hand-writing bus packing. +- Update the nearest `ruckus.tcl` when adding HDL. Use `loadRuckusTcl` for subdirectories and architecture guards such as `getFpgaArch` for family-specific sources. + +## Code Header Formats + +Use the existing header style for the file type and local subtree. Do not rewrite imported vendor, generated, or third-party headers unless the user explicitly asks for license repair. + +VHDL source files should use the standard dashed banner with company, description, and license text: + +```vhdl +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Short module description +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- +``` + +Python files should use the hash-comment license banner. PyRogue modules may include `Title` and `Description` sections when the surrounding package uses them; simple helper scripts may use only the license block. + +```python +#----------------------------------------------------------------------------- +# Title : Optional short title +#----------------------------------------------------------------------------- +# Description: +# Optional one- or two-line description +#----------------------------------------------------------------------------- +# This file is part of the 'SLAC Firmware Standard Library'. It is subject to +# the license terms in the LICENSE.txt file found in the top-level directory +# of this distribution and at: +# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +# No part of the 'SLAC Firmware Standard Library', including this file, may be +# copied, modified, propagated, or distributed except according to the terms +# contained in the LICENSE.txt file. +#----------------------------------------------------------------------------- +``` + +C, C++, and C header files should use the same license text with `//` comment delimiters. Match the local file's separator style, either `//-----------------------------------------------------------------------------` or `//////////////////////////////////////////////////////////////////////////////`. + +```c +//----------------------------------------------------------------------------- +// This file is part of 'SLAC Firmware Standard Library'. +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to +// the terms contained in the LICENSE.txt file. +//----------------------------------------------------------------------------- +``` + +Tcl, shell, YAML, and other hash-comment files should use the Python-style `#-----------------------------------------------------------------------------` license block when they are maintained SURF source. For executable scripts with a shebang, keep the shebang first and place the license block immediately after it. + +Checked-in cocotb regression files must also include the `Test methodology` block described in [tests/README.md](tests/README.md), immediately after the license header. + +## Python Conventions + +- Python support lives under `python/surf` and is packaged by `setup.py`. Most modules are PyRogue `pr.Device` descriptions of RTL register maps or support utilities. +- Keep the standard SLAC/SURF Python license banner at the top of Python files. +- Follow the existing module pattern: implementation files are usually private modules named `_Thing.py`, and package `__init__.py` files re-export them with aligned `from surf... import *` lines. +- Preserve the aligned keyword-argument style used in `pr.RemoteVariable`, `pr.LinkVariable`, `pr.RemoteCommand`, and `self.add(...)` blocks. Register offsets should remain explicit hex constants. +- Match PyRogue naming already used by the package: device classes in PascalCase, register names matching firmware/user documentation, local helpers in `_snake_case` where needed. +- `.flake8` intentionally relaxes many whitespace rules to support the existing aligned register-map style. Do not run an autoformatter that destroys that alignment unless the user explicitly asks for a larger formatting migration. +- Be cautious with `setup.py`: it appends a version string into `python/surf/__init__.py` as part of packaging. Do not run packaging commands casually during documentation or small-code tasks. + +## Tests And Verification + +- For RTL regressions, use the guidance in [tests/README.md](tests/README.md). The expected stack is `pytest + cocotb + GHDL + ruckus`. +- Run `make MODULES="$PWD" import` when the HDL import cache is missing or stale. +- For focused tests, prefer `./.venv/bin/python -m pytest -q tests/`. Use `-n 0` when serial simulator logs are needed. +- For edited VHDL, run the relevant pytest/cocotb target when practical and run `vsg` on changed files. +- Avoid hand-editing generated or cache directories such as `build/`, `tests/sim_build/`, `.pytest_cache/`, `docs/_build/`, and `docs/_generated/`. + +## Documentation Updates + +When adding a new subsystem, add or update the closest `README.md` if the layout or usage is not obvious. Keep README files short and navigational: describe what belongs in the folder, important subdirectories, and any local build/test conventions, then link upward through the parent README chain. diff --git a/README.md b/README.md index 1ed4406eba..a6f1548096 100644 --- a/README.md +++ b/README.md @@ -6,6 +6,21 @@ SLAC Ultimate RTL Framework +# Repository Map + +- [Agent guidance](AGENTS.md): project layout, coding conventions, and verification notes for contributors and coding agents. +- [AXI](axi/README.md): AXI-Lite, AXI4, AXI Stream, DMA, bridges, and simulation-link RTL. +- [Base](base/README.md): foundational packages, CDC, FIFO, RAM, reset, delay, CRC, and generic RTL helpers. +- [Devices](devices/README.md): vendor and component-specific RTL support. +- [DSP](dsp/README.md): generic and Xilinx-specific DSP support. +- [Ethernet](ethernet/README.md): MAC, raw Ethernet, IPv4, UDP, RoCEv2, and high-speed Ethernet cores. +- [Protocols](protocols/README.md): PGP, SSI, SRP, RSSI, CoaXPress, JESD204B, peripheral buses, and related protocol cores. +- [Xilinx](xilinx/README.md): Xilinx-family wrappers, primitive integrations, and XVC UDP support. +- [Python](python/README.md): PyRogue package layout under `python/surf`. +- [Tests](tests/README.md): cocotb regression layout, methodology, helpers, and simulator conventions. + + + # Before you clone the GIT repository Setup for large filesystems on github. `git-lfs` used for all binary files (example: .dcp) diff --git a/axi/README.md b/axi/README.md new file mode 100644 index 0000000000..6063fa23e5 --- /dev/null +++ b/axi/README.md @@ -0,0 +1,14 @@ +# AXI + +This tree contains reusable AXI-family RTL and wrappers. Top-level `axi/ruckus.tcl` loads the submodules used by SURF builds. + +## Layout + +- `axi-lite/`: AXI-Lite records, crossbars, endpoints, masters, slaves, monitors, and IP-integrator adapters. +- `axi-stream/`: AXI Stream records, FIFOs, muxes, monitors, protocol adapters, and stream wrappers. +- `axi4/`: full AXI4 support blocks and adapters. +- `bridge/`: bridges between AXI-family buses and SURF protocol records. +- `dma/`: DMA register, descriptor, FIFO, and stream integration cores. +- `simlink/`: simulator-link support and C/C++/VHDL pieces used by simulation flows. + +Use existing package record types before adding flattened ports. Put durable adapter entities in `ip_integrator/` or `wrappers/`, and keep executable cocotb tests under `tests/axi/`. diff --git a/base/README.md b/base/README.md new file mode 100644 index 0000000000..781392b0a9 --- /dev/null +++ b/base/README.md @@ -0,0 +1,14 @@ +# Base + +This tree contains the foundational RTL used by the rest of SURF. Top-level `base/ruckus.tcl` loads each base library area. + +## Layout + +- `general/`: common packages and generic utilities such as `StdRtlPkg`, arbiters, muxes, reset pipelines, gearboxes, counters, and watchdog/reset helpers. +- `sync/`: clock-domain crossing, synchronizers, reset synchronizers, trigger-rate, status, and frequency measurement helpers. +- `fifo/`: synchronous, asynchronous, muxing, cascade, FWFT, and output-pipeline FIFO blocks. +- `ram/`: inferred and Xilinx RAM implementations. +- `delay/`: fixed, RAM-backed, and FIFO-backed delay blocks. +- `crc/`: CRC packages and implementations. + +Most modules use SURF package aliases such as `sl` and `slv`, `_G` generics, `_C` constants, and the local `RegType`/`REG_INIT_C` registered-process style. Reuse these base modules rather than duplicating CDC, FIFO, RAM, reset, or CRC logic in higher-level subsystems. diff --git a/devices/README.md b/devices/README.md new file mode 100644 index 0000000000..b4b2deee2b --- /dev/null +++ b/devices/README.md @@ -0,0 +1,11 @@ +# Devices + +This tree contains vendor and component-specific RTL support. It is organized primarily by manufacturer, with shared transceiver support in `transceivers/`. + +## Layout + +- Manufacturer folders such as `AnalogDevices/`, `Microchip/`, `Micron/`, `Silabs/`, `Ti/`, and `Xilinx/` hold individual device cores. +- Device folders usually contain `rtl/` for synthesizable register/control logic, optional `sim/` models, optional FPGA-family implementation directories, and a local `ruckus.tcl`. +- `transceivers/` holds generic pluggable transceiver support such as SFP/QSFP control and status blocks. + +Keep register maps and control names aligned with vendor data sheets and with the matching PyRogue modules under `python/surf/devices` when they exist. Add new device sources to the nearest `ruckus.tcl`. diff --git a/dsp/README.md b/dsp/README.md new file mode 100644 index 0000000000..c1db4217cb --- /dev/null +++ b/dsp/README.md @@ -0,0 +1,10 @@ +# DSP + +This tree contains reusable signal-processing support blocks. + +## Layout + +- `generic/`: portable DSP RTL intended to work across FPGA families. +- `xilinx/`: Xilinx-specific DSP implementations and wrappers. + +Prefer generic implementations unless the design needs a family primitive, timing path, or vendor IP wrapper. Keep family-specific assumptions isolated under the vendor-specific subtree and guarded by ruckus logic when necessary. diff --git a/ethernet/README.md b/ethernet/README.md new file mode 100644 index 0000000000..81b70411bc --- /dev/null +++ b/ethernet/README.md @@ -0,0 +1,14 @@ +# Ethernet + +This tree contains Ethernet MAC, framing, IP/UDP, RoCEv2, and high-speed Ethernet cores. + +## Layout + +- `EthMacCore/`: common Ethernet MAC logic. +- `GigEthCore/`, `TenGigEthCore/`, `XauiCore/`, `XlauiCore/`, and `Caui4Core/`: speed and PHY-family specific Ethernet cores. +- `RawEthFramer/`: raw Ethernet frame transmit/receive support. +- `IpV4Engine/`: ARP, ICMP, IGMP, IPv4 receive/transmit, and demux helpers. +- `UdpEngine/`: UDP protocol support. +- `RoCEv2/`: RDMA over Converged Ethernet v2 support. + +High-speed cores commonly split shared `core/` logic from FPGA transceiver-family directories. Use `getFpgaArch` guards in ruckus files for family-specific source selection, and keep protocol-level tests under `tests/ethernet/`. diff --git a/protocols/README.md b/protocols/README.md new file mode 100644 index 0000000000..c3dfa34d9a --- /dev/null +++ b/protocols/README.md @@ -0,0 +1,12 @@ +# Protocols + +This tree contains reusable protocol cores layered above the base, AXI, and Ethernet libraries. + +## Layout + +- Link/protocol families include `pgp/`, `ssi/`, `srp/`, `rssi/`, `sugoi/`, `salt/`, `glink/`, `htsp/`, and `coaxpress/`. +- Peripheral/control protocols include `i2c/`, `spi/`, `uart/`, `mdio/`, `pmbus/`, and `saci/`. +- Data formatting and protection helpers include `batcher/`, `packetizer/`, `line-codes/`, `hamming-ecc/`, and `event-frame-sequencer/`. +- JESD support lives in `jesd204b/`. + +Many protocol folders split portable `core/` or `rtl/` logic from FPGA-family PHY wrappers. Preserve protocol record types and sideband semantics, especially `TKEEP`, `TLAST`, `TUSER`/SOF/EOFE, VC fields, and AXI-Lite status/control register maps. Put Python-facing register models under `python/surf/protocols` when the RTL exposes a PyRogue-visible register space. diff --git a/python/README.md b/python/README.md new file mode 100644 index 0000000000..58e78350e8 --- /dev/null +++ b/python/README.md @@ -0,0 +1,14 @@ +# Python + +The Python package lives under `python/surf` and is installed as `surf`. It primarily contains PyRogue device descriptions and small support utilities that mirror SURF RTL register maps. + +## Layout + +- `surf/axi/`: PyRogue models for AXI register blocks, DMA, stream monitors, version blocks, and related AXI support. +- `surf/devices/`: vendor and component-specific PyRogue register maps. +- `surf/ethernet/`: Ethernet, MAC, UDP, RoCE, and high-speed Ethernet support models. +- `surf/protocols/`: protocol-specific PyRogue models such as CoaXPress, PGP, RSSI, SSI, and related blocks. +- `surf/xilinx/`: Xilinx register maps and helper devices. +- `surf/misc/` and `surf/dsp/`: smaller utilities and DSP-related support. + +Implementation modules usually use private filenames such as `_AxiVersion.py` and are re-exported from package `__init__.py` files. Keep register names, offsets, bit offsets, modes, and descriptions synchronized with the corresponding RTL packages and user-facing hardware documentation. diff --git a/xilinx/README.md b/xilinx/README.md new file mode 100644 index 0000000000..14824b96e2 --- /dev/null +++ b/xilinx/README.md @@ -0,0 +1,12 @@ +# Xilinx + +This tree contains Xilinx-specific RTL wrappers, primitive integrations, and helper IP used by SURF. + +## Layout + +- Family folders such as `7Series/`, `Virtex5/`, `UltraScale/`, `UltraScale+/`, and `Versal/` hold family-specific wrappers and primitive integrations. +- `general/` contains Xilinx helpers that are not tied to a single family directory. +- `xvc-udp/` contains Xilinx Virtual Cable over UDP support and has its own [README.md](xvc-udp/README.md). +- `dummy/` contains placeholder or compatibility support used by build flows. + +Keep Xilinx primitive details isolated here or in explicitly family-named subdirectories of a subsystem. When a generic SURF wrapper exists, use it from higher-level RTL instead of instantiating primitives directly. From 81fd9f2bbb28cd99869601456391a54fdc09b582 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 20 May 2026 15:22:33 -0700 Subject: [PATCH 06/10] Add more conventions to follow. --- AGENTS.md | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 69 insertions(+), 3 deletions(-) diff --git a/AGENTS.md b/AGENTS.md index 6ea84ba294..b7df8790ec 100644 --- a/AGENTS.md +++ b/AGENTS.md @@ -33,6 +33,50 @@ Top-level `ruckus.tcl` loads `axi`, `base`, `dsp`, `devices`, `ethernet`, `proto - Keep wrappers thin. Prefer existing SURF adapter entities for AXI/AXI Stream record flattening before hand-writing bus packing. - Update the nearest `ruckus.tcl` when adding HDL. Use `loadRuckusTcl` for subdirectories and architecture guards such as `getFpgaArch` for family-specific sources. +## Two-Process VHDL Style + +SURF RTL generally follows the two-process style popularized by Gaisler: one combinational process computes next state and outputs, and one sequential process registers the state. + +- Put registered state in a `RegType` record. Use a `REG_INIT_C` constant for reset/default state, and declare `r` and `rin` signals for current and next state. +- Name the combinational process `comb` and the sequential process `seq` unless the surrounding file has a stronger local convention. +- At the top of `comb`, declare `variable v : RegType;` and immediately assign `v := r;`. Make all next-state updates to `v`. +- Assign `rin <= v;` near the end of `comb`. Drive module outputs from `r` for registered outputs and from `v` only when the local design intentionally exposes next-cycle/combinational behavior. +- Include all combinational inputs read by the process in the sensitivity list. Existing files often use explicit lists rather than `process(all)`; match nearby style. +- Apply synchronous reset in `comb` by assigning `v := REG_INIT_C` when `RST_ASYNC_G = false` and reset is asserted. +- Apply asynchronous reset only in `seq`, before the rising-edge branch, by assigning `r <= REG_INIT_C after TPD_G`. +- In `seq`, update state with `r <= rin after TPD_G;` on the rising edge. Preserve `after TPD_G` in existing RTL. +- Avoid scattering registers across multiple unrelated clocked processes in a module that otherwise uses this style. If independent clock domains are required, use one `RegType`/`comb`/`seq` set per clock domain and make CDC boundaries explicit. +- Keep one-off concurrent assignments for simple wires acceptable, but keep state-machine decisions, counters, handshakes, and registered outputs inside the two-process structure. + +## Ruckus Conventions + +- Treat `ruckus.tcl` files as build manifests. When adding, moving, or deleting HDL, update the closest manifest in the same change. +- Start maintained ruckus files with `source $::env(RUCKUS_PROC_TCL)` unless a nearby file shows a different established pattern. +- Use `loadSource -lib surf -dir "$::DIR_PATH/rtl"` or the local equivalent for source directories, and use `loadRuckusTcl "$::DIR_PATH/"` when a child directory owns its own manifest. +- Keep parent manifests short. They should load subdirectories and apply coarse selection logic, not list every leaf file when a child manifest exists. +- Use `getFpgaArch` for family-specific source selection. Keep architecture guards readable and follow existing family strings such as `kintexu`, `virtexu`, `kintexuplus`, `zynquplus`, `zynquplusRFSOC`, `virtexuplus`, and `virtexuplusHBM`. +- Do not add generated simulator outputs, build products, waveform files, imported cache files, or temporary conversion artifacts to ruckus manifests. +- After changing ruckus structure, run `make MODULES="$PWD" import` when practical to confirm the import graph still resolves. + +## Reset And CDC Rules + +- Prefer existing `base/sync` primitives for clock-domain crossing, reset synchronization, pulse transfer, status synchronization, and frequency/rate measurement. +- Do not hand-roll synchronizers, async FIFOs, reset pipelines, or CDC pulse logic unless there is a specific reason the existing base module cannot cover. +- Preserve existing reset generics and semantics: `TPD_G`, `RST_POLARITY_G`, `RST_ASYNC_G`, active-high/active-low defaults, and optional reset ports should remain compatible. +- Keep asynchronous reset handling in the sequential process and synchronous reset handling in the combinational next-state path when following the common SURF `comb`/`seq` pattern. +- For multi-clock designs, make the crossing explicit in names and structure. Avoid passing unsynchronized control/status bits between clock domains through ordinary signals. +- For reset fanout or deassertion timing, reuse `RstPipeline`, `RstPipelineVector`, `RstSync`, or local established wrappers instead of creating ad hoc chains. + +## Bus And Protocol Semantics + +- Use existing SURF record types and package helpers for AXI-Lite, AXI4, AXI Stream, SSI, PGP, SRP, Ethernet, and related protocols. Do not create parallel bus records for the same interface. +- AXI-Lite register maps should use explicit offsets, stable reset values, deterministic read data, and clear write side effects. Preserve response behavior and alignment/error handling from existing helpers. +- Keep AXI-Lite read/write endpoint code consistent with local helper procedures such as `axiSlaveWaitTxn`, `axiSlaveRegister`, `axiSlaveDefault`, and related package utilities where they are already used. +- AXI Stream and SSI changes must preserve payload byte order, `TKEEP`, `TLAST`, `TDEST`, `TID`, and `TUSER` semantics. For SSI, be especially careful with SOF, EOF, and EOFE encodings. +- Do not treat final payload data alone as sufficient for timing-visible behavior. Backpressure, arbitration order, burst length, sideband propagation, and frame boundaries are part of the interface contract. +- Keep protocol status/control register names and bit meanings aligned across RTL packages, PyRogue models, cocotb tests, and any user-facing documentation. +- Prefer extending existing protocol helpers or packages over duplicating encoders, decoders, CRC logic, packet builders, or stream handshake code. + ## Code Header Formats Use the existing header style for the file type and local subtree. Do not rewrite imported vendor, generated, or third-party headers unless the user explicitly asks for license repair. @@ -102,14 +146,36 @@ Checked-in cocotb regression files must also include the `Test methodology` bloc - `.flake8` intentionally relaxes many whitespace rules to support the existing aligned register-map style. Do not run an autoformatter that destroys that alignment unless the user explicitly asks for a larger formatting migration. - Be cautious with `setup.py`: it appends a version string into `python/surf/__init__.py` as part of packaging. Do not run packaging commands casually during documentation or small-code tasks. +## PyRogue Register Maps + +- PyRogue register maps must mirror the RTL-visible register layout exactly. Keep `offset`, `bitOffset`, `bitSize`, `mode`, endianness/base type, and reset assumptions synchronized with firmware. +- Use explicit offsets in hex and explicit bit fields. Avoid computed offsets unless the surrounding file already uses a clear repeated-register pattern. +- Preserve public variable names, command names, enum strings, and link-variable names unless the user explicitly wants an API change. Downstream scripts often depend on these names. +- Use `pr.RemoteVariable` for hardware-backed registers, `pr.RemoteCommand` for command strobes or command-like accesses, and `pr.LinkVariable` for derived display/state values. +- Keep descriptions hardware-specific and useful. Avoid generic descriptions that repeat the variable name without explaining the register meaning or side effect. +- Keep write guards, dependencies, polling behavior, and hidden/expert visibility consistent with neighboring PyRogue devices. +- When changing an RTL register map, update the matching PyRogue model and any cocotb register helpers/tests in the same change when practical. + +## Generated And Vendor Code + +- Treat vendor memory models, Xilinx stubs, XCI/DCP outputs, Bluespec/RoCE generated Verilog, and imported third-party protocol support as external code unless the user specifically asks to modify them. +- Do not reformat, license-normalize, rename signals, or modernize generated/vendor files as incidental cleanup. +- When a wrapper around vendor/generated code is needed, put project-maintained glue in a nearby SURF-owned `rtl/`, `wrappers/`, `ip_integrator/`, or family-specific directory rather than editing the imported source. +- Keep binary and generated artifacts out of source changes unless they are intentionally tracked release/build inputs already managed by the repository. + ## Tests And Verification - For RTL regressions, use the guidance in [tests/README.md](tests/README.md). The expected stack is `pytest + cocotb + GHDL + ruckus`. -- Run `make MODULES="$PWD" import` when the HDL import cache is missing or stale. -- For focused tests, prefer `./.venv/bin/python -m pytest -q tests/`. Use `-n 0` when serial simulator logs are needed. -- For edited VHDL, run the relevant pytest/cocotb target when practical and run `vsg` on changed files. +- For docs-only changes, no RTL or Python tests are required, but check links and headings if the edit adds navigation. +- For ruckus or source-list changes, run `make MODULES="$PWD" import` when practical. +- For edited VHDL, run `./.venv/bin/vsg -c vsg-linter.yml path/to/file.vhd` and the most focused relevant cocotb/pytest target when practical. +- For Python/PyRogue changes, run a focused import or pytest that exercises the changed module. Avoid packaging commands unless the task specifically requires packaging validation. +- For cocotb tests, prefer `./.venv/bin/python -m pytest -q tests/`. Use `-n 0` when serial simulator logs are needed. +- For protocol or bus behavior changes, include tests or a clear verification note covering sidebands, backpressure, reset behavior, and boundary/error cases relevant to the change. - Avoid hand-editing generated or cache directories such as `build/`, `tests/sim_build/`, `.pytest_cache/`, `docs/_build/`, and `docs/_generated/`. ## Documentation Updates When adding a new subsystem, add or update the closest `README.md` if the layout or usage is not obvious. Keep README files short and navigational: describe what belongs in the folder, important subdirectories, and any local build/test conventions, then link upward through the parent README chain. + +Add deeper README files as substantial areas are touched, especially in high-traffic module families such as `axi/axi-stream`, `axi/axi-lite`, `protocols/pgp`, `protocols/coaxpress`, `protocols/ssi`, `protocols/srp`, `ethernet/IpV4Engine`, `ethernet/UdpEngine`, and `ethernet/EthMacCore`. Prefer adding the README in the same change that introduces new layout or conventions for that area. From 73ac1b5743a13d5848b6a473ddbe135392152938 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 20 May 2026 15:27:52 -0700 Subject: [PATCH 07/10] More conventions. --- AGENTS.md | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/AGENTS.md b/AGENTS.md index b7df8790ec..5df62bbee6 100644 --- a/AGENTS.md +++ b/AGENTS.md @@ -48,6 +48,28 @@ SURF RTL generally follows the two-process style popularized by Gaisler: one com - Avoid scattering registers across multiple unrelated clocked processes in a module that otherwise uses this style. If independent clock domains are required, use one `RegType`/`comb`/`seq` set per clock domain and make CDC boundaries explicit. - Keep one-off concurrent assignments for simple wires acceptable, but keep state-machine decisions, counters, handshakes, and registered outputs inside the two-process structure. +## VHDL Package Conventions + +- Put shared interface records, constants, array types, configuration records, helper functions, and protocol encoders/decoders in the nearest appropriate `*Pkg.vhd`. +- Name record types with a `Type` suffix, arrays with an `Array` suffix, and initialization constants with an `_INIT_C` suffix, such as `Pgp2bRxOutType`, `Pgp2bRxOutArray`, and `PGP2B_RX_OUT_INIT_C`. +- Use package-specific constant prefixes for exported constants. Follow existing all-caps prefixes such as `AXI_`, `AXI_STREAM_`, `SSI_`, `PGP2B_`, `ROCE_`, or the local protocol/device prefix. +- Provide an init constant for every exported record type unless the record is intentionally never default-initialized. +- Define unconstrained arrays with `natural range <>` when the type is meant to scale across lanes, virtual channels, masters, or replicated devices. +- Keep protocol and bus semantics centralized in packages. Do not duplicate record definitions, init values, CRC functions, sideband constants, or stream configuration helpers inside leaf RTL files. +- Avoid package bloat. If a helper is only meaningful inside one entity and is not part of a shared interface, keep it local to that entity. +- Avoid circular package dependencies. Lower-level packages such as base, AXI, and Ethernet should not depend on higher-level protocol/device packages. +- Keep package body functions deterministic and synthesizable unless the package is explicitly simulation-only. + +## Simulation And Testbench VHDL + +- Prefer Python/cocotb for executable stimulus, scoreboards, transaction sequencing, and randomized or parameterized checks. +- Keep VHDL testbenches and wrappers thin. They should provide clocks/resets, flatten records, adapt simulator-facing ports, tie off unused fields, instantiate simple integration topologies, or host required vendor simulation models. +- Name the real RTL instance `U_DUT` in wrappers and testbenches unless the file intentionally contains multiple peer instances. +- Put reusable cocotb-facing wrappers beside the RTL family they adapt, usually under `wrappers/` or `ip_integrator/`, instead of hiding durable HDL under `tests/`. +- Put pure simulation models under `sim/` and legacy or VHDL-only benches under `tb/`. +- Keep wrapper port maps annotated with `-- [in]`, `-- [out]`, or `-- [inout]` comments just like production RTL. +- Do not put protocol stimulus or assertions in VHDL when an equivalent cocotb test can own them more clearly. + ## Ruckus Conventions - Treat `ruckus.tcl` files as build manifests. When adding, moving, or deleting HDL, update the closest manifest in the same change. @@ -77,6 +99,18 @@ SURF RTL generally follows the two-process style popularized by Gaisler: one com - Keep protocol status/control register names and bit meanings aligned across RTL packages, PyRogue models, cocotb tests, and any user-facing documentation. - Prefer extending existing protocol helpers or packages over duplicating encoders, decoders, CRC logic, packet builders, or stream handshake code. +## AXI-Lite Register Implementation Pattern + +- Prefer the existing SURF AXI-Lite endpoint helpers over hand-written read/write channel state machines for simple register blocks. +- In two-process register blocks, keep AXI-Lite read/write slave records in `RegType` and initialize them from `AXI_LITE_*_INIT_C` constants. +- Use `axiSlaveWaitTxn(...)` once near the start of the register section to decode the current transaction into an endpoint/status variable. +- Use `axiSlaveRegister(...)` for read/write registers and `axiSlaveRegisterR(...)` for read-only status fields. Keep offsets explicit and aligned to the documented map. +- Use `axiSlaveDefault(...)` at the end of the map so unmapped accesses return the intended response, commonly `AXI_RESP_DECERR_C`. +- Apply write side effects deliberately. Pulse, clear-on-write, FIFO-write, and counter-reset behavior should be visible in the surrounding next-state logic and documented in PyRogue descriptions when user-visible. +- For status counters and sampled signals crossing clock domains, synchronize before exposing them on AXI-Lite. Do not read raw signals from another clock domain through a register map. +- Maintain readback behavior for writable registers unless the existing hardware contract intentionally differs. +- When changing offsets, fields, reset values, or access modes, update matching PyRogue variables and focused tests in the same change when practical. + ## Code Header Formats Use the existing header style for the file type and local subtree. Do not rewrite imported vendor, generated, or third-party headers unless the user explicitly asks for license repair. @@ -174,6 +208,20 @@ Checked-in cocotb regression files must also include the `Test methodology` bloc - For protocol or bus behavior changes, include tests or a clear verification note covering sidebands, backpressure, reset behavior, and boundary/error cases relevant to the change. - Avoid hand-editing generated or cache directories such as `build/`, `tests/sim_build/`, `.pytest_cache/`, `docs/_build/`, and `docs/_generated/`. +## RTL Review Checklist + +Before considering an RTL change done, check: + +- Reset behavior remains compatible with existing `TPD_G`, `RST_POLARITY_G`, `RST_ASYNC_G`, and default reset values. +- CDC paths are explicit and use existing synchronizer, reset, FIFO, or status-crossing primitives. +- AXI-Lite, AXI Stream, SSI, Ethernet, PGP, and protocol sidebands are preserved, including error bits, SOF/EOF/EOFE flags, `TKEEP`, `TLAST`, `TDEST`, `TID`, and `TUSER`. +- State machines and counters follow the two-process style where the surrounding file uses it. +- New or moved HDL is included in the correct `ruckus.tcl`, and family-specific code is guarded appropriately. +- Register-map changes are reflected in PyRogue models, tests, and documentation. +- Simulation wrappers remain thin and do not hide production behavior changes. +- Generated/vendor files were not reformatted or modified incidentally. +- Verification notes identify what was run and what risk remains if focused tests or lint were not practical. + ## Documentation Updates When adding a new subsystem, add or update the closest `README.md` if the layout or usage is not obvious. Keep README files short and navigational: describe what belongs in the folder, important subdirectories, and any local build/test conventions, then link upward through the parent README chain. From 63dca300798a242f62a215bdce24dbda56815172 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 20 May 2026 15:29:05 -0700 Subject: [PATCH 08/10] Add PR guidance. --- AGENTS.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/AGENTS.md b/AGENTS.md index 5df62bbee6..10c0640806 100644 --- a/AGENTS.md +++ b/AGENTS.md @@ -227,3 +227,7 @@ Before considering an RTL change done, check: When adding a new subsystem, add or update the closest `README.md` if the layout or usage is not obvious. Keep README files short and navigational: describe what belongs in the folder, important subdirectories, and any local build/test conventions, then link upward through the parent README chain. Add deeper README files as substantial areas are touched, especially in high-traffic module families such as `axi/axi-stream`, `axi/axi-lite`, `protocols/pgp`, `protocols/coaxpress`, `protocols/ssi`, `protocols/srp`, `ethernet/IpV4Engine`, `ethernet/UdpEngine`, and `ethernet/EthMacCore`. Prefer adding the README in the same change that introduces new layout or conventions for that area. + +## Pull Requests + +When preparing pull request text, follow the repository template at [.github/pull_request_template.md](.github/pull_request_template.md). Keep the `Description` clean and release-note ready; the template notes that blank descriptions are not accepted and that this text feeds release notes. Use `Details`, `JIRA`, and `Related` only when they add useful context. From 40a15d5fad82cbc16b181b63b7bc41ee4a7e1453 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 20 May 2026 15:30:03 -0700 Subject: [PATCH 09/10] PR guidance. --- AGENTS.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/AGENTS.md b/AGENTS.md index 10c0640806..571c35effa 100644 --- a/AGENTS.md +++ b/AGENTS.md @@ -230,4 +230,4 @@ Add deeper README files as substantial areas are touched, especially in high-tra ## Pull Requests -When preparing pull request text, follow the repository template at [.github/pull_request_template.md](.github/pull_request_template.md). Keep the `Description` clean and release-note ready; the template notes that blank descriptions are not accepted and that this text feeds release notes. Use `Details`, `JIRA`, and `Related` only when they add useful context. +When preparing pull request text, follow the repository template at [.github/pull_request_template.md](.github/pull_request_template.md). PRs should generally target the `pre-release` branch unless the user or maintainer specifies a different base. Keep the `Description` clean and release-note ready; the template notes that blank descriptions are not accepted and that this text feeds release notes. Use `Details`, `JIRA`, and `Related` only when they add useful context. From 3340d96a8da7e7a8886949f759bfd3ba4f52be4a Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 20 May 2026 20:58:50 -0700 Subject: [PATCH 10/10] Task tracking and vendor code. --- AGENTS.md | 9 ++++++++- docs/plans/README.md | 22 ++++++++++++++++++++++ 2 files changed, 30 insertions(+), 1 deletion(-) create mode 100644 docs/plans/README.md diff --git a/AGENTS.md b/AGENTS.md index 571c35effa..14b4b6d882 100644 --- a/AGENTS.md +++ b/AGENTS.md @@ -17,6 +17,7 @@ Start with [README.md](README.md) for user-facing links and the source tree inde - [xilinx/README.md](xilinx/README.md) for Xilinx-family primitives, wrappers, and XVC UDP support. - [python/README.md](python/README.md) for the PyRogue package under `python/surf`. - [tests/README.md](tests/README.md) for cocotb regression layout, methodology comments, helper reuse, and simulator conventions. +- [docs/plans/README.md](docs/plans/README.md) for substantial task planning, progress notes, and handoff conventions. Top-level `ruckus.tcl` loads `axi`, `base`, `dsp`, `devices`, `ethernet`, `protocols`, and `xilinx`. Module-level `ruckus.tcl` files should continue to be the source of truth for which HDL files and submodules are part of a build. @@ -192,7 +193,7 @@ Checked-in cocotb regression files must also include the `Test methodology` bloc ## Generated And Vendor Code -- Treat vendor memory models, Xilinx stubs, XCI/DCP outputs, Bluespec/RoCE generated Verilog, and imported third-party protocol support as external code unless the user specifically asks to modify them. +- Treat vendor memory models, Xilinx stubs, XCI/DCP outputs, Bluespec/RoCE generated Verilog, imported third-party protocol support, and the imported I2C libraries with non-SLAC license headers under `protocols/i2c/rtl` as external code unless the user specifically asks to modify them. - Do not reformat, license-normalize, rename signals, or modernize generated/vendor files as incidental cleanup. - When a wrapper around vendor/generated code is needed, put project-maintained glue in a nearby SURF-owned `rtl/`, `wrappers/`, `ip_integrator/`, or family-specific directory rather than editing the imported source. - Keep binary and generated artifacts out of source changes unless they are intentionally tracked release/build inputs already managed by the repository. @@ -228,6 +229,12 @@ When adding a new subsystem, add or update the closest `README.md` if the layout Add deeper README files as substantial areas are touched, especially in high-traffic module families such as `axi/axi-stream`, `axi/axi-lite`, `protocols/pgp`, `protocols/coaxpress`, `protocols/ssi`, `protocols/srp`, `ethernet/IpV4Engine`, `ethernet/UdpEngine`, and `ethernet/EthMacCore`. Prefer adding the README in the same change that introduces new layout or conventions for that area. +## Task Tracking + +For substantial feature work, debug efforts, refactors, or multi-step investigations, keep planning, progress, and handoff Markdown under `docs/plans//`. Use a short kebab-case task name, keep notes factual, and update the plan as the work changes. + +Each task directory should include enough context for another contributor to resume without reconstructing the work from chat history. Capture the goal, current status, decisions made, files or modules involved, validation run, open risks, and next steps. Keep large logs, generated output, and simulator artifacts out of `docs/plans`; summarize them and link to durable locations instead. + ## Pull Requests When preparing pull request text, follow the repository template at [.github/pull_request_template.md](.github/pull_request_template.md). PRs should generally target the `pre-release` branch unless the user or maintainer specifies a different base. Keep the `Description` clean and release-note ready; the template notes that blank descriptions are not accepted and that this text feeds release notes. Use `Details`, `JIRA`, and `Related` only when they add useful context. diff --git a/docs/plans/README.md b/docs/plans/README.md new file mode 100644 index 0000000000..1b88473851 --- /dev/null +++ b/docs/plans/README.md @@ -0,0 +1,22 @@ +# Task Plans + +Use this directory for planning, progress notes, and handoff material for substantial SURF work. + +Create one task directory per effort: + +```text +docs/plans// +``` + +Use short kebab-case names, for example `coaxpress-link-debug` or `axi-stream-resize-tests`. + +Each task directory should capture: + +- Goal and scope. +- Current status. +- Important design or debugging decisions. +- Files, modules, or tests involved. +- Validation already run. +- Open risks, blockers, and next steps. + +Keep notes concise and factual. Do not store large simulator logs, generated outputs, build products, or waveform files here; summarize them and link to durable locations when needed.