From 9c6a035fa152db1f87a3110b4926bc622aa9e04f Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 8 Apr 2026 23:33:25 -0700 Subject: [PATCH 01/92] Linting. --- tests/protocols/ssi/test_SsiIbFrameFilter.py | 1 - tests/protocols/ssi/test_SsiInsertSof.py | 4 ++-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/tests/protocols/ssi/test_SsiIbFrameFilter.py b/tests/protocols/ssi/test_SsiIbFrameFilter.py index a11a315383..44cea7d1d5 100644 --- a/tests/protocols/ssi/test_SsiIbFrameFilter.py +++ b/tests/protocols/ssi/test_SsiIbFrameFilter.py @@ -30,7 +30,6 @@ from tests.common.regression_utils import env_flag, parameter_case, run_surf_vhdl_test from tests.protocols.ssi.ssi_test_utils import ( assert_beat_list, - cycle, env_data_bytes, expect_no_output, expect_no_output_data, diff --git a/tests/protocols/ssi/test_SsiInsertSof.py b/tests/protocols/ssi/test_SsiInsertSof.py index 1053b54691..4670e355b1 100644 --- a/tests/protocols/ssi/test_SsiInsertSof.py +++ b/tests/protocols/ssi/test_SsiInsertSof.py @@ -69,8 +69,8 @@ async def ssi_insert_sof_test(dut): # Run the source in the background so the test can first observe the # inserted header beat while the sink is still stalled. payload_send = cocotb.start_soon( - source.send( - SsiBeat(data=0x2211, keep=keep, last=1, dest=0x5, sof=0, eofe=1), + source.send( + SsiBeat(data=0x2211, keep=keep, last=1, dest=0x5, sof=0, eofe=1), clk=bench.clk, ) ) From 1318d7eb6f20a6f15895c39ce8c747dd8583f87e Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 8 Apr 2026 23:35:59 -0700 Subject: [PATCH 02/92] Linting. --- tests/protocols/pgp/pgp2b/test_Pgp2bTxCell.py | 2 +- tests/protocols/pgp/pgp2b/test_Pgp2bTxPhy.py | 2 +- tests/protocols/pgp/pgp2fc/test_Pgp2fcTxCell.py | 2 +- tests/protocols/pgp/pgp4/test_Pgp4RxEb.py | 1 - 4 files changed, 3 insertions(+), 4 deletions(-) diff --git a/tests/protocols/pgp/pgp2b/test_Pgp2bTxCell.py b/tests/protocols/pgp/pgp2b/test_Pgp2bTxCell.py index 5e1c197a57..718d2c8929 100644 --- a/tests/protocols/pgp/pgp2b/test_Pgp2bTxCell.py +++ b/tests/protocols/pgp/pgp2b/test_Pgp2bTxCell.py @@ -12,7 +12,7 @@ import cocotb -from tests.protocols.pgp.pgp2_test_utils import K_EOC, PgpModuleTB, signal_int +from tests.protocols.pgp.pgp2_test_utils import PgpModuleTB, signal_int from tests.protocols.pgp.pgp_test_utils import pgp_family_sources, run_pgp_wrapper_test diff --git a/tests/protocols/pgp/pgp2b/test_Pgp2bTxPhy.py b/tests/protocols/pgp/pgp2b/test_Pgp2bTxPhy.py index 6eeb8a01a3..7c48040e72 100644 --- a/tests/protocols/pgp/pgp2b/test_Pgp2bTxPhy.py +++ b/tests/protocols/pgp/pgp2b/test_Pgp2bTxPhy.py @@ -12,7 +12,7 @@ import cocotb -from tests.protocols.pgp.pgp2_test_utils import D_102, K_COM, K_LTS, K_SOF, K_SKP, PgpModuleTB, signal_int +from tests.protocols.pgp.pgp2_test_utils import D_102, K_LTS, K_SOF, PgpModuleTB, signal_int from tests.protocols.pgp.pgp_test_utils import pgp_family_sources, run_pgp_wrapper_test diff --git a/tests/protocols/pgp/pgp2fc/test_Pgp2fcTxCell.py b/tests/protocols/pgp/pgp2fc/test_Pgp2fcTxCell.py index f7c00588d9..7d222b00b7 100644 --- a/tests/protocols/pgp/pgp2fc/test_Pgp2fcTxCell.py +++ b/tests/protocols/pgp/pgp2fc/test_Pgp2fcTxCell.py @@ -18,7 +18,7 @@ import cocotb -from tests.protocols.pgp.pgp2_test_utils import K_EOC, PgpModuleTB, signal_int +from tests.protocols.pgp.pgp2_test_utils import PgpModuleTB, signal_int from tests.protocols.pgp.pgp_test_utils import pgp_family_sources, run_pgp_wrapper_test diff --git a/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py b/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py index b2887103d2..fc7f422947 100644 --- a/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py +++ b/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py @@ -24,7 +24,6 @@ from tests.common.regression_utils import parameter_case, start_lockstep_clocks from tests.protocols.pgp.pgp4.pgp4_test_utils import ( - PGP4_D_HEADER, PGP4_K_HEADER, pgp4_idle_word, pgp4_skip_word, From 6805ec5a96818212b16e9dae82d1ec654e85d558 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 10 Apr 2026 00:27:54 -0700 Subject: [PATCH 03/92] Ethernet tests. --- ethernet/EthMacCore/rtl/EthCrc32Parallel.vhd | 3 + .../wrappers/EthMacFlowCtrlWrapper.vhd | 76 +++ .../EthMacImportExportLoopbackWrapper.vhd | 148 ++++++ .../wrappers/EthMacRxCsumWrapper.vhd | 110 +++++ .../wrappers/EthMacRxFilterWrapper.vhd | 108 +++++ .../wrappers/EthMacRxPauseWrapper.vhd | 101 ++++ .../wrappers/EthMacRxShiftWrapper.vhd | 98 ++++ .../wrappers/EthMacTopLoopbackWrapper.vhd | 193 ++++++++ .../wrappers/EthMacTxCsumLoopbackWrapper.vhd | 137 ++++++ .../wrappers/EthMacTxPauseWrapper.vhd | 122 +++++ .../wrappers/EthMacTxShiftWrapper.vhd | 103 +++++ tests/ethernet/__init__.py | 9 + tests/ethernet/eth_mac/__init__.py | 9 + tests/ethernet/eth_mac/ethmac_test_utils.py | 437 ++++++++++++++++++ .../ethernet/eth_mac/test_EthCrc32Parallel.py | 116 +++++ tests/ethernet/eth_mac/test_EthMacFlowCtrl.py | 104 +++++ tests/ethernet/eth_mac/test_EthMacRxCsum.py | 108 +++++ tests/ethernet/eth_mac/test_EthMacRxFilter.py | 102 ++++ tests/ethernet/eth_mac/test_EthMacRxImport.py | 87 ++++ tests/ethernet/eth_mac/test_EthMacRxPause.py | 100 ++++ tests/ethernet/eth_mac/test_EthMacRxShift.py | 78 ++++ tests/ethernet/eth_mac/test_EthMacTop.py | 107 +++++ tests/ethernet/eth_mac/test_EthMacTxCsum.py | 100 ++++ tests/ethernet/eth_mac/test_EthMacTxExport.py | 88 ++++ tests/ethernet/eth_mac/test_EthMacTxPause.py | 104 +++++ tests/ethernet/eth_mac/test_EthMacTxShift.py | 81 ++++ 26 files changed, 2829 insertions(+) create mode 100644 ethernet/EthMacCore/wrappers/EthMacFlowCtrlWrapper.vhd create mode 100644 ethernet/EthMacCore/wrappers/EthMacImportExportLoopbackWrapper.vhd create mode 100644 ethernet/EthMacCore/wrappers/EthMacRxCsumWrapper.vhd create mode 100644 ethernet/EthMacCore/wrappers/EthMacRxFilterWrapper.vhd create mode 100644 ethernet/EthMacCore/wrappers/EthMacRxPauseWrapper.vhd create mode 100644 ethernet/EthMacCore/wrappers/EthMacRxShiftWrapper.vhd create mode 100644 ethernet/EthMacCore/wrappers/EthMacTopLoopbackWrapper.vhd create mode 100644 ethernet/EthMacCore/wrappers/EthMacTxCsumLoopbackWrapper.vhd create mode 100644 ethernet/EthMacCore/wrappers/EthMacTxPauseWrapper.vhd create mode 100644 ethernet/EthMacCore/wrappers/EthMacTxShiftWrapper.vhd create mode 100644 tests/ethernet/__init__.py create mode 100644 tests/ethernet/eth_mac/__init__.py create mode 100644 tests/ethernet/eth_mac/ethmac_test_utils.py create mode 100644 tests/ethernet/eth_mac/test_EthCrc32Parallel.py create mode 100644 tests/ethernet/eth_mac/test_EthMacFlowCtrl.py create mode 100644 tests/ethernet/eth_mac/test_EthMacRxCsum.py create mode 100644 tests/ethernet/eth_mac/test_EthMacRxFilter.py create mode 100644 tests/ethernet/eth_mac/test_EthMacRxImport.py create mode 100644 tests/ethernet/eth_mac/test_EthMacRxPause.py create mode 100644 tests/ethernet/eth_mac/test_EthMacRxShift.py create mode 100644 tests/ethernet/eth_mac/test_EthMacTop.py create mode 100644 tests/ethernet/eth_mac/test_EthMacTxCsum.py create mode 100644 tests/ethernet/eth_mac/test_EthMacTxExport.py create mode 100644 tests/ethernet/eth_mac/test_EthMacTxPause.py create mode 100644 tests/ethernet/eth_mac/test_EthMacTxShift.py diff --git a/ethernet/EthMacCore/rtl/EthCrc32Parallel.vhd b/ethernet/EthMacCore/rtl/EthCrc32Parallel.vhd index f6fa2e37fd..264eb1d81e 100755 --- a/ethernet/EthMacCore/rtl/EthCrc32Parallel.vhd +++ b/ethernet/EthMacCore/rtl/EthCrc32Parallel.vhd @@ -321,6 +321,9 @@ begin v.crc := crc32Parallel16Byte(prevCrc, r.data(BYTE_WIDTH_G*8-1 downto (BYTE_WIDTH_G-16)*8)); end if; end if; + --------------------------------------------------------------------------------------------------------------- + when others => + null; --------------------------------------------------------------------------------------------------------------- end case; elsif (USE_DSP_G = false) then diff --git a/ethernet/EthMacCore/wrappers/EthMacFlowCtrlWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacFlowCtrlWrapper.vhd new file mode 100644 index 0000000000..796f6e2986 --- /dev/null +++ b/ethernet/EthMacCore/wrappers/EthMacFlowCtrlWrapper.vhd @@ -0,0 +1,76 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for EthMacFlowCtrl +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; + +entity EthMacFlowCtrlWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + BYP_EN_G : boolean := false); + port ( + ethClk : in sl; + ethRst : in sl; + primPause : in sl; + primOverflow : in sl; + bypPause : in sl; + bypOverflow : in sl; + flowPause : out sl; + flowOverflow : out sl); +end entity EthMacFlowCtrlWrapper; + +architecture rtl of EthMacFlowCtrlWrapper is + + signal primCtrl : AxiStreamCtrlType := AXI_STREAM_CTRL_INIT_C; + signal bypCtrl : AxiStreamCtrlType := AXI_STREAM_CTRL_INIT_C; + signal flowCtrl : AxiStreamCtrlType := AXI_STREAM_CTRL_INIT_C; + +begin + + -- Flatten the small `AxiStreamCtrlType` record into individual pause and + -- overflow bits so cocotb can drive the public control contract directly. + primCtrl.pause <= primPause; + primCtrl.overflow <= primOverflow; + primCtrl.idle <= '0'; + + bypCtrl.pause <= bypPause; + bypCtrl.overflow <= bypOverflow; + bypCtrl.idle <= '0'; + + -- Instantiate the real DUT. + U_DUT : entity surf.EthMacFlowCtrl + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + BYP_EN_G => BYP_EN_G) + port map ( + ethClk => ethClk, + ethRst => ethRst, + primCtrl => primCtrl, + bypCtrl => bypCtrl, + flowCtrl => flowCtrl); + + -- Re-expand the output record so the test can observe the merged flow + -- control result without record-field access. + flowPause <= flowCtrl.pause; + flowOverflow <= flowCtrl.overflow; + +end architecture rtl; diff --git a/ethernet/EthMacCore/wrappers/EthMacImportExportLoopbackWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacImportExportLoopbackWrapper.vhd new file mode 100644 index 0000000000..d93a8017b9 --- /dev/null +++ b/ethernet/EthMacCore/wrappers/EthMacImportExportLoopbackWrapper.vhd @@ -0,0 +1,148 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing EthMac import/export loopback wrapper +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity EthMacImportExportLoopbackWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + PHY_TYPE_G : string := "XGMII"; + SYNTH_MODE_G : string := "inferred"); + port ( + ethClk : in sl; + ethRst : in sl; + ethClkEn : in sl := '1'; + phyReady : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTDest : in slv(7 downto 0); + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTDest : out slv(7 downto 0); + mAxisTReady : in sl := '1'; + mAxisSof : out sl; + mAxisEofe : out sl; + rxCountEn : out sl; + rxCrcError : out sl; + txCountEn : out sl; + txUnderRun : out sl; + txLinkNotReady : out sl); +end entity EthMacImportExportLoopbackWrapper; + +architecture rtl of EthMacImportExportLoopbackWrapper is + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + + signal xgmiiTxd : slv(63 downto 0) := (others => '0'); + signal xgmiiTxc : slv(7 downto 0) := (others => '0'); + signal gmiiTxEn : sl := '0'; + signal gmiiTxEr : sl := '0'; + signal gmiiTxd : slv(7 downto 0) := (others => '0'); + +begin + + -- Flatten the source stream for the export-side stimulus path. + sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTDest, sAxisTKeep, sAxisTLast, sAxisTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(127 downto 0) := sAxisTData; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + v.tDest(7 downto 0) := sAxisTDest; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); + sAxisMaster <= v; + end process sAxisComb; + + sAxisTReady <= sAxisSlave.tReady; + + -- Export the recovered AXIS frame from the import-side DUT. + mAxisView : process (mAxisMaster) is + begin + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisTDest <= mAxisMaster.tDest(7 downto 0); + mAxisSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + end process mAxisView; + + -- Generate the PHY-coded stream from a clean AXIS packet source. + U_Tx : entity surf.EthMacTxExport + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + PHY_TYPE_G => PHY_TYPE_G, + SYNTH_MODE_G => SYNTH_MODE_G) + port map ( + ethClkEn => ethClkEn, + ethClk => ethClk, + ethRst => ethRst, + macObMaster => sAxisMaster, + macObSlave => sAxisSlave, + xlgmiiTxd => open, + xlgmiiTxc => open, + xgmiiTxd => xgmiiTxd, + xgmiiTxc => xgmiiTxc, + gmiiTxEn => gmiiTxEn, + gmiiTxEr => gmiiTxEr, + gmiiTxd => gmiiTxd, + phyReady => phyReady, + txCountEn => txCountEn, + txUnderRun => txUnderRun, + txLinkNotReady => txLinkNotReady); + + -- Feed the generated PHY stream into the import-side DUT under test. + U_Rx : entity surf.EthMacRxImport + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + PHY_TYPE_G => PHY_TYPE_G, + SYNTH_MODE_G => SYNTH_MODE_G) + port map ( + ethClkEn => ethClkEn, + ethClk => ethClk, + ethRst => ethRst, + macIbMaster => mAxisMaster, + xlgmiiRxd => (others => '0'), + xlgmiiRxc => (others => '1'), + xgmiiRxd => xgmiiTxd, + xgmiiRxc => xgmiiTxc, + gmiiRxDv => gmiiTxEn, + gmiiRxEr => gmiiTxEr, + gmiiRxd => gmiiTxd, + phyReady => phyReady, + rxCountEn => rxCountEn, + rxCrcError => rxCrcError); + +end architecture rtl; diff --git a/ethernet/EthMacCore/wrappers/EthMacRxCsumWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacRxCsumWrapper.vhd new file mode 100644 index 0000000000..893e702cf9 --- /dev/null +++ b/ethernet/EthMacCore/wrappers/EthMacRxCsumWrapper.vhd @@ -0,0 +1,110 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for EthMacRxCsum +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity EthMacRxCsumWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + JUMBO_G : boolean := false; + ROCEV2_EN_G : boolean := false); + port ( + ethClk : in sl; + ethRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTReady : in sl := '1'; + mAxisSof : out sl; + mAxisFrag : out sl; + mAxisEofe : out sl; + mAxisIpErr : out sl; + mAxisTcpErr : out sl; + mAxisUdpErr : out sl; + ipCsumEn : in sl; + tcpCsumEn : in sl; + udpCsumEn : in sl); +end entity EthMacRxCsumWrapper; + +architecture rtl of EthMacRxCsumWrapper is + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + +begin + + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(127 downto 0) := sAxisTData; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); + sAxisMaster <= v; + end process sAxisComb; + + sAxisTReady <= '1'; + + mAxisView : process (mAxisMaster) is + begin + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + mAxisIpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_IPERR_BIT_C); + mAxisTcpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_TCPERR_BIT_C); + mAxisUdpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_UDPERR_BIT_C); + end process mAxisView; + + U_DUT : entity surf.EthMacRxCsum + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + JUMBO_G => JUMBO_G, + ROCEV2_EN_G => ROCEV2_EN_G) + port map ( + ethClk => ethClk, + ethRst => ethRst, + ipCsumEn => ipCsumEn, + tcpCsumEn => tcpCsumEn, + udpCsumEn => udpCsumEn, + sAxisMaster => sAxisMaster, + mAxisMaster => mAxisMaster); + +end architecture rtl; diff --git a/ethernet/EthMacCore/wrappers/EthMacRxFilterWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacRxFilterWrapper.vhd new file mode 100644 index 0000000000..c08a60826e --- /dev/null +++ b/ethernet/EthMacCore/wrappers/EthMacRxFilterWrapper.vhd @@ -0,0 +1,108 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for EthMacRxFilter +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity EthMacRxFilterWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + FILT_EN_G : boolean := true); + port ( + ethClk : in sl; + ethRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTReady : in sl := '1'; + mAxisSof : out sl; + mAxisFrag : out sl; + mAxisEofe : out sl; + mAxisPause : in sl; + dropOnPause : in sl; + macAddress : in slv(47 downto 0); + filtEnable : in sl); +end entity EthMacRxFilterWrapper; + +architecture rtl of EthMacRxFilterWrapper is + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisCtrl : AxiStreamCtrlType := AXI_STREAM_CTRL_INIT_C; + +begin + + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(127 downto 0) := sAxisTData; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); + sAxisMaster <= v; + end process sAxisComb; + + sAxisTReady <= '1'; + mAxisCtrl.pause <= mAxisPause; + mAxisCtrl.overflow <= '0'; + mAxisCtrl.idle <= '0'; + + mAxisView : process (mAxisMaster) is + begin + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + end process mAxisView; + + U_DUT : entity surf.EthMacRxFilter + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + FILT_EN_G => FILT_EN_G) + port map ( + ethClk => ethClk, + ethRst => ethRst, + sAxisMaster => sAxisMaster, + mAxisMaster => mAxisMaster, + mAxisCtrl => mAxisCtrl, + dropOnPause => dropOnPause, + macAddress => macAddress, + filtEnable => filtEnable); + +end architecture rtl; diff --git a/ethernet/EthMacCore/wrappers/EthMacRxPauseWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacRxPauseWrapper.vhd new file mode 100644 index 0000000000..fde618c4b7 --- /dev/null +++ b/ethernet/EthMacCore/wrappers/EthMacRxPauseWrapper.vhd @@ -0,0 +1,101 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for EthMacRxPause +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity EthMacRxPauseWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + PAUSE_EN_G : boolean := true); + port ( + ethClk : in sl; + ethRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTReady : in sl := '1'; + mAxisSof : out sl; + mAxisFrag : out sl; + mAxisEofe : out sl; + rxPauseReq : out sl; + rxPauseValue : out slv(15 downto 0)); +end entity EthMacRxPauseWrapper; + +architecture rtl of EthMacRxPauseWrapper is + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + +begin + + -- Build the EMAC stream record from cocotb-facing scalar ports. + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(127 downto 0) := sAxisTData; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); + sAxisMaster <= v; + end process sAxisComb; + + sAxisTReady <= '1'; + + -- Expose the filtered output stream on plain scalar ports again. + mAxisView : process (mAxisMaster) is + begin + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + end process mAxisView; + + -- Instantiate the real DUT. + U_DUT : entity surf.EthMacRxPause + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + PAUSE_EN_G => PAUSE_EN_G) + port map ( + ethClk => ethClk, + ethRst => ethRst, + sAxisMaster => sAxisMaster, + mAxisMaster => mAxisMaster, + rxPauseReq => rxPauseReq, + rxPauseValue => rxPauseValue); + +end architecture rtl; diff --git a/ethernet/EthMacCore/wrappers/EthMacRxShiftWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacRxShiftWrapper.vhd new file mode 100644 index 0000000000..6264396807 --- /dev/null +++ b/ethernet/EthMacCore/wrappers/EthMacRxShiftWrapper.vhd @@ -0,0 +1,98 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for EthMacRxShift +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity EthMacRxShiftWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + SHIFT_EN_G : boolean := true); + port ( + ethClk : in sl; + ethRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTReady : in sl := '1'; + mAxisSof : out sl; + mAxisFrag : out sl; + mAxisEofe : out sl; + rxShift : in slv(3 downto 0)); +end entity EthMacRxShiftWrapper; + +architecture rtl of EthMacRxShiftWrapper is + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + +begin + + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(127 downto 0) := sAxisTData; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); + sAxisMaster <= v; + end process sAxisComb; + + sAxisTReady <= '1'; + + mAxisView : process (mAxisMaster) is + begin + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + end process mAxisView; + + U_DUT : entity surf.EthMacRxShift + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + SHIFT_EN_G => SHIFT_EN_G) + port map ( + ethClk => ethClk, + ethRst => ethRst, + sAxisMaster => sAxisMaster, + mAxisMaster => mAxisMaster, + rxShift => rxShift); + +end architecture rtl; diff --git a/ethernet/EthMacCore/wrappers/EthMacTopLoopbackWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacTopLoopbackWrapper.vhd new file mode 100644 index 0000000000..434ba9ad55 --- /dev/null +++ b/ethernet/EthMacCore/wrappers/EthMacTopLoopbackWrapper.vhd @@ -0,0 +1,193 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing XGMII loopback wrapper for EthMacTop +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity EthMacTopLoopbackWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + PAUSE_EN_G : boolean := false; + PAUSE_512BITS_G : positive range 1 to 1024 := 8; + DROP_ERR_PKT_G : boolean := true; + JUMBO_G : boolean := false; + INT_PIPE_STAGES_G : natural := 1; + PIPE_STAGES_G : natural := 1; + FIFO_ADDR_WIDTH_G : positive := 11; + SYNTH_MODE_G : string := "inferred"; + MEMORY_TYPE_G : string := "block"; + ROCEV2_EN_G : boolean := false; + FILT_EN_G : boolean := false); + port ( + ethClk : in sl; + ethRst : in sl; + phyReady : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTDest : in slv(7 downto 0); + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTDest : out slv(7 downto 0); + mAxisTReady : in sl := '1'; + mAxisSof : out sl; + mAxisEofe : out sl; + localMac : in slv(47 downto 0); + filtEnable : in sl; + pauseEnable : in sl; + pauseTime : in slv(15 downto 0); + pauseThresh : in slv(15 downto 0); + ipCsumEn : in sl; + tcpCsumEn : in sl; + udpCsumEn : in sl; + dropOnPause : in sl; + rxPauseCnt : out sl; + rxOverFlow : out sl; + rxCountEn : out sl; + rxCrcErrorCnt : out sl; + txCountEn : out sl; + txUnderRunCnt : out sl; + txNotReadyCnt : out sl); +end entity EthMacTopLoopbackWrapper; + +architecture rtl of EthMacTopLoopbackWrapper is + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal ethConfig : EthMacConfigType := ETH_MAC_CONFIG_INIT_C; + signal ethStatus : EthMacStatusType := ETH_MAC_STATUS_INIT_C; + signal xgmiiTxd : slv(63 downto 0) := (others => '0'); + signal xgmiiTxc : slv(7 downto 0) := (others => '1'); + +begin + + -- Flatten the primary AXIS source used by the test. + sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTDest, sAxisTKeep, sAxisTLast, sAxisTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(127 downto 0) := sAxisTData; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + v.tDest(7 downto 0) := sAxisTDest; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); + sAxisMaster <= v; + end process sAxisComb; + + sAxisTReady <= sAxisSlave.tReady; + mAxisSlave.tReady <= mAxisTReady; + + -- Re-expand the received primary AXIS stream for cocotb checks. + mAxisView : process (mAxisMaster) is + begin + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisTDest <= mAxisMaster.tDest(7 downto 0); + mAxisSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + end process mAxisView; + + -- Flatten the public EthMacTop config record. + ethConfig.macAddress <= localMac; + ethConfig.filtEnable <= filtEnable; + ethConfig.pauseEnable <= pauseEnable; + ethConfig.pauseTime <= pauseTime; + ethConfig.pauseThresh <= pauseThresh; + ethConfig.ipCsumEn <= ipCsumEn; + ethConfig.tcpCsumEn <= tcpCsumEn; + ethConfig.udpCsumEn <= udpCsumEn; + ethConfig.dropOnPause <= dropOnPause; + + -- Flatten the small status record for direct cocotb observation. + rxPauseCnt <= ethStatus.rxPauseCnt; + rxOverFlow <= ethStatus.rxOverFlow; + rxCountEn <= ethStatus.rxCountEn; + rxCrcErrorCnt <= ethStatus.rxCrcErrorCnt; + txCountEn <= ethStatus.txCountEn; + txUnderRunCnt <= ethStatus.txUnderRunCnt; + txNotReadyCnt <= ethStatus.txNotReadyCnt; + + -- Instantiate the real top-level MAC in XGMII loopback mode. + U_DUT : entity surf.EthMacTop + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, + PHY_TYPE_G => "XGMII", + DROP_ERR_PKT_G => DROP_ERR_PKT_G, + JUMBO_G => JUMBO_G, + INT_PIPE_STAGES_G => INT_PIPE_STAGES_G, + PIPE_STAGES_G => PIPE_STAGES_G, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + SYNTH_MODE_G => SYNTH_MODE_G, + MEMORY_TYPE_G => MEMORY_TYPE_G, + ROCEV2_EN_G => ROCEV2_EN_G, + FILT_EN_G => FILT_EN_G, + PRIM_COMMON_CLK_G => true, + PRIM_CONFIG_G => EMAC_AXIS_CONFIG_C, + BYP_EN_G => false, + BYP_COMMON_CLK_G => false, + BYP_CONFIG_G => EMAC_AXIS_CONFIG_C) + port map ( + ethClkEn => '1', + ethClk => ethClk, + ethRst => ethRst, + primClk => ethClk, + primRst => ethRst, + ibMacPrimMaster => sAxisMaster, + ibMacPrimSlave => sAxisSlave, + obMacPrimMaster => mAxisMaster, + obMacPrimSlave => mAxisSlave, + bypClk => '0', + bypRst => '0', + ibMacBypMaster => AXI_STREAM_MASTER_INIT_C, + ibMacBypSlave => open, + obMacBypMaster => open, + obMacBypSlave => AXI_STREAM_SLAVE_FORCE_C, + xlgmiiRxd => (others => '0'), + xlgmiiRxc => (others => '1'), + xgmiiRxd => xgmiiTxd, + xgmiiRxc => xgmiiTxc, + xgmiiTxd => xgmiiTxd, + xgmiiTxc => xgmiiTxc, + gmiiRxDv => '0', + gmiiRxEr => '0', + gmiiRxd => (others => '0'), + gmiiTxEn => open, + gmiiTxEr => open, + gmiiTxd => open, + phyReady => phyReady, + ethConfig => ethConfig, + ethStatus => ethStatus); + +end architecture rtl; diff --git a/ethernet/EthMacCore/wrappers/EthMacTxCsumLoopbackWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacTxCsumLoopbackWrapper.vhd new file mode 100644 index 0000000000..7471ff5981 --- /dev/null +++ b/ethernet/EthMacCore/wrappers/EthMacTxCsumLoopbackWrapper.vhd @@ -0,0 +1,137 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing loopback wrapper for EthMacTxCsum +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity EthMacTxCsumLoopbackWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + DROP_ERR_PKT_G : boolean := true; + JUMBO_G : boolean := false; + ROCEV2_EN_G : boolean := false; + SYNTH_MODE_G : string := "inferred"); + port ( + ethClk : in sl; + ethRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTReady : in sl := '1'; + mAxisSof : out sl; + mAxisFrag : out sl; + mAxisEofe : out sl; + mAxisIpErr : out sl; + mAxisTcpErr : out sl; + mAxisUdpErr : out sl; + ipCsumEn : in sl; + tcpCsumEn : in sl; + udpCsumEn : in sl); +end entity EthMacTxCsumLoopbackWrapper; + +architecture rtl of EthMacTxCsumLoopbackWrapper is + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal txAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal txAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + +begin + + -- Flatten the source packet stream that will be repaired by TxCsum. + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(127 downto 0) := sAxisTData; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); + sAxisMaster <= v; + end process sAxisComb; + + sAxisTReady <= sAxisSlave.tReady; + txAxisSlave.tReady <= '1'; + + -- Present the post-checker stream to cocotb so the test can confirm the + -- repaired packet exits without RX-side checksum errors. + mAxisView : process (mAxisMaster) is + begin + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + mAxisIpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_IPERR_BIT_C); + mAxisTcpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_TCPERR_BIT_C); + mAxisUdpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_UDPERR_BIT_C); + end process mAxisView; + + U_TxCsum : entity surf.EthMacTxCsum + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + DROP_ERR_PKT_G => DROP_ERR_PKT_G, + JUMBO_G => JUMBO_G, + ROCEV2_EN_G => ROCEV2_EN_G, + SYNTH_MODE_G => SYNTH_MODE_G) + port map ( + ethClk => ethClk, + ethRst => ethRst, + ipCsumEn => ipCsumEn, + tcpCsumEn => tcpCsumEn, + udpCsumEn => udpCsumEn, + sAxisMaster => sAxisMaster, + sAxisSlave => sAxisSlave, + mAxisMaster => txAxisMaster, + mAxisSlave => txAxisSlave); + + U_RxCheck : entity surf.EthMacRxCsum + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => false, + JUMBO_G => JUMBO_G, + ROCEV2_EN_G => ROCEV2_EN_G) + port map ( + ethClk => ethClk, + ethRst => ethRst, + ipCsumEn => ipCsumEn, + tcpCsumEn => tcpCsumEn, + udpCsumEn => udpCsumEn, + sAxisMaster => txAxisMaster, + mAxisMaster => mAxisMaster); + +end architecture rtl; diff --git a/ethernet/EthMacCore/wrappers/EthMacTxPauseWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacTxPauseWrapper.vhd new file mode 100644 index 0000000000..9abc259540 --- /dev/null +++ b/ethernet/EthMacCore/wrappers/EthMacTxPauseWrapper.vhd @@ -0,0 +1,122 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for EthMacTxPause +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity EthMacTxPauseWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : natural range 1 to 1024 := 8); + port ( + ethClk : in sl; + ethRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTReady : in sl; + mAxisSof : out sl; + mAxisFrag : out sl; + mAxisEofe : out sl; + clientPause : in sl; + rxPauseReq : in sl; + rxPauseValue : in slv(15 downto 0); + phyReady : in sl; + pauseEnable : in sl; + pauseTime : in slv(15 downto 0); + macAddress : in slv(47 downto 0); + pauseTx : out sl); +end entity EthMacTxPauseWrapper; + +architecture rtl of EthMacTxPauseWrapper is + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + -- Flatten the source-side EMAC stream for cocotb. + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(127 downto 0) := sAxisTData; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); + sAxisMaster <= v; + end process sAxisComb; + + sAxisTReady <= sAxisSlave.tReady; + mAxisSlave.tReady <= mAxisTReady; + + -- Flatten the DUT output so the pause-frame payload and pass-through data + -- can be inspected without record access. + mAxisView : process (mAxisMaster) is + begin + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + end process mAxisView; + + U_DUT : entity surf.EthMacTxPause + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G) + port map ( + ethClk => ethClk, + ethRst => ethRst, + sAxisMaster => sAxisMaster, + sAxisSlave => sAxisSlave, + mAxisMaster => mAxisMaster, + mAxisSlave => mAxisSlave, + clientPause => clientPause, + rxPauseReq => rxPauseReq, + rxPauseValue => rxPauseValue, + phyReady => phyReady, + pauseEnable => pauseEnable, + pauseTime => pauseTime, + macAddress => macAddress, + pauseTx => pauseTx); + +end architecture rtl; diff --git a/ethernet/EthMacCore/wrappers/EthMacTxShiftWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacTxShiftWrapper.vhd new file mode 100644 index 0000000000..81f20d2ba6 --- /dev/null +++ b/ethernet/EthMacCore/wrappers/EthMacTxShiftWrapper.vhd @@ -0,0 +1,103 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for EthMacTxShift +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity EthMacTxShiftWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + SHIFT_EN_G : boolean := true); + port ( + ethClk : in sl; + ethRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTReady : in sl; + mAxisSof : out sl; + mAxisFrag : out sl; + mAxisEofe : out sl; + txShift : in slv(3 downto 0)); +end entity EthMacTxShiftWrapper; + +architecture rtl of EthMacTxShiftWrapper is + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(127 downto 0) := sAxisTData; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); + sAxisMaster <= v; + end process sAxisComb; + + sAxisTReady <= sAxisSlave.tReady; + mAxisSlave.tReady <= mAxisTReady; + + mAxisView : process (mAxisMaster) is + begin + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + end process mAxisView; + + U_DUT : entity surf.EthMacTxShift + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + SHIFT_EN_G => SHIFT_EN_G) + port map ( + ethClk => ethClk, + ethRst => ethRst, + sAxisMaster => sAxisMaster, + sAxisSlave => sAxisSlave, + mAxisMaster => mAxisMaster, + mAxisSlave => mAxisSlave, + txShift => txShift); + +end architecture rtl; diff --git a/tests/ethernet/__init__.py b/tests/ethernet/__init__.py new file mode 100644 index 0000000000..b0085f1a17 --- /dev/null +++ b/tests/ethernet/__init__.py @@ -0,0 +1,9 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## diff --git a/tests/ethernet/eth_mac/__init__.py b/tests/ethernet/eth_mac/__init__.py new file mode 100644 index 0000000000..b0085f1a17 --- /dev/null +++ b/tests/ethernet/eth_mac/__init__.py @@ -0,0 +1,9 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## diff --git a/tests/ethernet/eth_mac/ethmac_test_utils.py b/tests/ethernet/eth_mac/ethmac_test_utils.py new file mode 100644 index 0000000000..eb359aa83f --- /dev/null +++ b/tests/ethernet/eth_mac/ethmac_test_utils.py @@ -0,0 +1,437 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +from __future__ import annotations + +from dataclasses import dataclass +import ipaddress +from pathlib import Path + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer + + +ETHMAC_RTL_SOURCES = [ + str(path) + for path in sorted((Path(__file__).resolve().parents[3] / "ethernet" / "EthMacCore" / "rtl").glob("*.vhd")) + if path.name != "EthMacPkg.vhd" +] +ETHMAC_RTL_SOURCES.append(str(Path(__file__).resolve().parents[3] / "dsp" / "xilinx" / "logic" / "DspXor.vhd")) + + +@dataclass +class EmacBeat: + """One flattened EMAC transfer beat as exposed by the cocotb wrappers.""" + + data: int + keep: int + last: int + dest: int = 0 + sof: int = 0 + frag: int = 0 + eofe: int = 0 + iperr: int = 0 + tcperr: int = 0 + udperr: int = 0 + + +class FlatEmacEndpoint: + def __init__(self, dut, *, prefix: str): + self.dut = dut + self.prefix = prefix + + def _sig(self, suffix: str): + return getattr(self.dut, f"{self.prefix}{suffix}") + + def _has(self, suffix: str) -> bool: + return hasattr(self.dut, f"{self.prefix}{suffix}") + + def set_idle(self) -> None: + # Model an idle source by dropping `TVALID` and clearing the payload + # signals so stale values do not confuse waveform inspection. + for suffix, value in ( + ("TValid", 0), + ("TData", 0), + ("TKeep", 0), + ("TLast", 0), + ("TDest", 0), + ("Sof", 0), + ("Frag", 0), + ("Eofe", 0), + ("IpErr", 0), + ("TcpErr", 0), + ("UdpErr", 0), + ): + if self._has(suffix): + self._sig(suffix).value = value + + def drive(self, beat: EmacBeat) -> None: + # Present one visible beat. The helper keeps this beat stable until the + # DUT accepts it with `TREADY`. + self._sig("TValid").value = 1 + self._sig("TData").value = beat.data + self._sig("TKeep").value = beat.keep + self._sig("TLast").value = beat.last + if self._has("TDest"): + self._sig("TDest").value = beat.dest + if self._has("Sof"): + self._sig("Sof").value = beat.sof + if self._has("Frag"): + self._sig("Frag").value = beat.frag + if self._has("Eofe"): + self._sig("Eofe").value = beat.eofe + if self._has("IpErr"): + self._sig("IpErr").value = beat.iperr + if self._has("TcpErr"): + self._sig("TcpErr").value = beat.tcperr + if self._has("UdpErr"): + self._sig("UdpErr").value = beat.udperr + + async def wait_ready(self, *, clk) -> None: + # A source-side driver must hold the current beat until the DUT raises + # `TREADY`, even when that takes multiple cycles. + while True: + await RisingEdge(clk) + await Timer(1, unit="ns") + if int(self._sig("TReady").value) == 1: + return + + async def send(self, beat: EmacBeat, *, clk) -> None: + # `send()` is the simple one-beat helper: drive, wait for acceptance, + # then return the bus to idle. + self.drive(beat) + await self.wait_ready(clk=clk) + self.set_idle() + + def snapshot(self) -> EmacBeat: + return EmacBeat( + data=int(self._sig("TData").value), + keep=int(self._sig("TKeep").value), + last=int(self._sig("TLast").value), + dest=0 if not self._has("TDest") else int(self._sig("TDest").value), + sof=0 if not self._has("Sof") else int(self._sig("Sof").value), + frag=0 if not self._has("Frag") else int(self._sig("Frag").value), + eofe=0 if not self._has("Eofe") else int(self._sig("Eofe").value), + iperr=0 if not self._has("IpErr") else int(self._sig("IpErr").value), + tcperr=0 if not self._has("TcpErr") else int(self._sig("TcpErr").value), + udperr=0 if not self._has("UdpErr") else int(self._sig("UdpErr").value), + ) + + async def wait_valid(self, *, clk, timeout_cycles: int = 64) -> EmacBeat: + # Sink-side tests often want to notice a beat before deciding whether + # to consume it, so this helper only waits for visibility. + for _ in range(timeout_cycles): + await Timer(1, unit="ns") + if int(self._sig("TValid").value) == 1: + return self.snapshot() + await RisingEdge(clk) + raise AssertionError(f"Timed out waiting for {self.prefix} valid") + + async def recv(self, *, clk, ready_signal=None, keep_ready: bool = False) -> EmacBeat: + # Raise `TREADY` when needed, capture the visible beat, then consume it + # on the next rising edge. + if ready_signal is not None: + ready_signal.value = 1 + beat = await self.wait_valid(clk=clk) + await RisingEdge(clk) + await Timer(1, unit="ns") + if ready_signal is not None and not keep_ready: + ready_signal.value = 0 + return beat + + +@dataclass +class FlatEmacBench: + """Common cocotb bench wiring for flattened EMAC wrappers.""" + + clk: object + source: FlatEmacEndpoint | None = None + sink: FlatEmacEndpoint | None = None + + +def keep_mask(data_bytes: int) -> int: + return (1 << data_bytes) - 1 + + +def pack_bytes(data: bytes, *, lane_bytes: int = 16) -> int: + # SURF's EMAC stream places the first byte of the packet in the least + # significant byte lane of the flattened data word. + value = 0 + for index, byte_value in enumerate(data[:lane_bytes]): + value |= (byte_value & 0xFF) << (8 * index) + return value + + +def payload_from_beat(beat: EmacBeat, *, lane_bytes: int = 16) -> bytes: + payload = bytearray() + for index in range(lane_bytes): + if beat.keep & (1 << index): + payload.append((beat.data >> (8 * index)) & 0xFF) + return bytes(payload) + + +def payload_from_beats(beats: list[EmacBeat], *, lane_bytes: int = 16) -> bytes: + payload = bytearray() + for beat in beats: + payload.extend(payload_from_beat(beat, lane_bytes=lane_bytes)) + return bytes(payload) + + +def frame_beats_from_bytes( + data: bytes, + *, + beat_bytes: int = 16, + dest: int = 0, + eofe: int = 0, + frag: int = 0, +) -> list[EmacBeat]: + beats = [] + offset = 0 + while offset < len(data): + chunk = data[offset : offset + beat_bytes] + beats.append( + EmacBeat( + data=pack_bytes(chunk, lane_bytes=beat_bytes), + keep=keep_mask(len(chunk)), + last=1 if offset + beat_bytes >= len(data) else 0, + dest=dest, + sof=1 if offset == 0 else 0, + frag=frag if offset == 0 else 0, + eofe=eofe if offset + beat_bytes >= len(data) else 0, + ) + ) + offset += beat_bytes + return beats + + +def assert_beat_list(observed: list[EmacBeat], expected: list[EmacBeat]) -> None: + assert len(observed) == len(expected) + for index, (obs, exp) in enumerate(zip(observed, expected, strict=True)): + assert obs == exp, f"Mismatch at beat {index}: observed={obs} expected={exp}" + + +def mac_to_bytes(mac: int) -> bytes: + return mac.to_bytes(6, byteorder="big") + + +def ipv4_to_bytes(address: str) -> bytes: + return ipaddress.IPv4Address(address).packed + + +def internet_checksum(data: bytes) -> int: + # The IPv4, UDP, and TCP checksum blocks all use the standard one's- + # complement fold over 16-bit words, with a zero pad on odd byte counts. + if len(data) % 2 != 0: + data += b"\x00" + + checksum = 0 + for offset in range(0, len(data), 2): + checksum += int.from_bytes(data[offset : offset + 2], byteorder="big") + checksum = (checksum & 0xFFFF) + (checksum >> 16) + + return (~checksum) & 0xFFFF + + +def build_ethernet_frame(*, dst_mac: int, src_mac: int, eth_type: int, payload: bytes) -> bytes: + return mac_to_bytes(dst_mac) + mac_to_bytes(src_mac) + eth_type.to_bytes(2, byteorder="big") + payload + + +def build_ipv4_header( + *, + src_ip: str, + dst_ip: str, + protocol: int, + payload_length: int, + identification: int = 0x1234, + ttl: int = 64, + checksum_override: int | None = None, +) -> bytes: + total_length = 20 + payload_length + header_wo_checksum = bytes([0x45, 0x00]) + total_length.to_bytes(2, byteorder="big") + header_wo_checksum += identification.to_bytes(2, byteorder="big") + header_wo_checksum += b"\x00\x00" + header_wo_checksum += bytes([ttl, protocol]) + header_wo_checksum += b"\x00\x00" + header_wo_checksum += ipv4_to_bytes(src_ip) + ipv4_to_bytes(dst_ip) + + checksum = internet_checksum(header_wo_checksum) if checksum_override is None else checksum_override + return header_wo_checksum[:10] + checksum.to_bytes(2, byteorder="big") + header_wo_checksum[12:] + + +def build_udp_header( + *, + src_port: int, + dst_port: int, + payload: bytes, + src_ip: str, + dst_ip: str, + checksum_override: int | None = None, +) -> bytes: + udp_length = 8 + len(payload) + header_wo_checksum = ( + src_port.to_bytes(2, byteorder="big") + + dst_port.to_bytes(2, byteorder="big") + + udp_length.to_bytes(2, byteorder="big") + + b"\x00\x00" + ) + + pseudo_header = ( + ipv4_to_bytes(src_ip) + + ipv4_to_bytes(dst_ip) + + bytes([0x00, 0x11]) + + udp_length.to_bytes(2, byteorder="big") + ) + checksum = internet_checksum(pseudo_header + header_wo_checksum + payload) if checksum_override is None else checksum_override + return header_wo_checksum[:6] + checksum.to_bytes(2, byteorder="big") + + +def build_ipv4_udp_frame( + *, + dst_mac: int, + src_mac: int, + src_ip: str, + dst_ip: str, + src_port: int, + dst_port: int, + payload: bytes, + ip_checksum_override: int | None = None, + udp_checksum_override: int | None = None, +) -> bytes: + udp_header = build_udp_header( + src_port=src_port, + dst_port=dst_port, + payload=payload, + src_ip=src_ip, + dst_ip=dst_ip, + checksum_override=udp_checksum_override, + ) + ipv4_header = build_ipv4_header( + src_ip=src_ip, + dst_ip=dst_ip, + protocol=0x11, + payload_length=len(udp_header) + len(payload), + checksum_override=ip_checksum_override, + ) + return build_ethernet_frame( + dst_mac=dst_mac, + src_mac=src_mac, + eth_type=0x0800, + payload=ipv4_header + udp_header + payload, + ) + + +def build_pause_frame(pause_value: int) -> bytes: + # The pause opcode and pause quanta are part of the MAC control payload, + # which the TxPause block pads to Ethernet's 46-byte minimum payload. + payload = b"\x00\x01" + pause_value.to_bytes(2, byteorder="big") + bytes(42) + return build_ethernet_frame( + dst_mac=0x0180C2000001, + src_mac=0x000000000000, + eth_type=0x8808, + payload=payload, + ) + + +def start_clock(signal, *, period_ns: float = 5.0) -> None: + cocotb.start_soon(Clock(signal, period_ns, unit="ns").start()) + + +async def cycle(clk, count: int = 1) -> None: + for _ in range(count): + await RisingEdge(clk) + await Timer(1, unit="ns") + + +async def reset_dut(dut, *, clk_name: str = "ethClk", rst_name: str = "ethRst") -> None: + clk = getattr(dut, clk_name) + rst = getattr(dut, rst_name) + rst.value = 1 + await cycle(clk, 4) + rst.value = 0 + await cycle(clk, 2) + + +async def setup_flat_emac_testbench( + dut, + *, + clk_name: str = "ethClk", + rst_name: str = "ethRst", + period_ns: float = 5.0, + source_prefix: str | None = None, + sink_prefix: str | None = None, + initial_values: dict[str, int] | None = None, +) -> FlatEmacBench: + # Most EMAC wrapper benches share the same pattern: start one clock, drive + # reset high immediately, optionally create flat source/sink endpoints, + # seed a few sideband controls, then release reset. + clk = getattr(dut, clk_name) + rst = getattr(dut, rst_name) + start_clock(clk, period_ns=period_ns) + rst.setimmediatevalue(1) + + source = None if source_prefix is None else FlatEmacEndpoint(dut, prefix=source_prefix) + sink = None if sink_prefix is None else FlatEmacEndpoint(dut, prefix=sink_prefix) + + if source is not None: + source.set_idle() + + if initial_values is not None: + for signal_name, value in initial_values.items(): + getattr(dut, signal_name).setimmediatevalue(value) + + await reset_dut(dut, clk_name=clk_name, rst_name=rst_name) + return FlatEmacBench(clk=clk, source=source, sink=sink) + + +async def send_contiguous_frame(endpoint: FlatEmacEndpoint, beats: list[EmacBeat], *, clk) -> None: + # Some EMAC stages inspect packet continuity, so this helper keeps `TVALID` + # asserted across the entire frame instead of idling between beats. + for beat in beats: + endpoint.drive(beat) + await endpoint.wait_ready(clk=clk) + endpoint.set_idle() + + +async def recv_frame(endpoint: FlatEmacEndpoint, *, clk, ready_signal=None, timeout_cycles: int = 64) -> list[EmacBeat]: + beats = [] + if ready_signal is not None: + ready_signal.value = 1 + for _ in range(timeout_cycles): + await RisingEdge(clk) + await Timer(1, unit="ns") + if int(endpoint._sig("TValid").value) == 1: + beat = endpoint.snapshot() + beats.append(beat) + if beat.last == 1: + if ready_signal is not None: + ready_signal.value = 0 + return beats + if ready_signal is not None: + ready_signal.value = 0 + raise AssertionError("Timed out waiting for end of EMAC frame") + + +async def expect_no_output(endpoint: FlatEmacEndpoint, *, clk, cycles: int = 8) -> None: + for _ in range(cycles): + await Timer(1, unit="ns") + assert int(endpoint._sig("TValid").value) == 0 + await RisingEdge(clk) + + +async def wait_signal_pulse(signal, *, clk, timeout_cycles: int = 64) -> None: + # Many MAC status outputs are one-cycle pulses, so a dedicated helper keeps + # tests from relying on fragile fixed delays. + for _ in range(timeout_cycles): + await Timer(1, unit="ns") + if int(signal.value) == 1: + return + await RisingEdge(clk) + raise AssertionError(f"Timed out waiting for pulse on {signal._name}") diff --git a/tests/ethernet/eth_mac/test_EthCrc32Parallel.py b/tests/ethernet/eth_mac/test_EthCrc32Parallel.py new file mode 100644 index 0000000000..0c2e2545d8 --- /dev/null +++ b/tests/ethernet/eth_mac/test_EthCrc32Parallel.py @@ -0,0 +1,116 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Cover a smaller and larger byte-lane configuration so the Ethernet- +# specific CRC wrapper logic proves both narrow and full-width paths. +# - Stimulus: Present deterministic byte groups, leave the block idle for one +# cycle to prove hold behavior, and then assert the CRC reset input. +# - Checks: Each emitted CRC must match the software Ethernet CRC fold over the +# same byte sequence, the CRC must hold during idle cycles, and reset must +# restore the all-ones seed presentation. +# - Timing: `EthCrc32Parallel` consumes the presented word on one clock and +# updates the internal remainder on the next, so each transaction waits for +# that two-cycle cadence explicitly. + +from __future__ import annotations + +import os + +import cocotb +import pytest +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer + +from tests.base.crc.crc_test_utils import crc_out_from_remainder, crc_update, pack_active_bytes +from tests.common.regression_utils import hdl_parameters_from, parameter_case, run_surf_vhdl_test +from tests.ethernet.eth_mac.ethmac_test_utils import ETHMAC_RTL_SOURCES + + +async def cycle(clk, count: int = 1) -> None: + for _ in range(count): + await RisingEdge(clk) + # The CRC block registers state with `after TPD_G`, so leave a small + # margin beyond that delay before sampling outputs in Python. + await Timer(2, unit="ns") + + +async def apply_word(dut, *, clk, byte_width: int, payload: list[int]) -> int: + dut.crcDataValid.value = 1 + dut.crcDataWidth.value = len(payload) - 1 + dut.crcIn.value = pack_active_bytes(payload, byte_width=byte_width) + + # The input control word is captured on this edge. + await RisingEdge(clk) + dut.crcDataValid.value = 0 + await Timer(2, unit="ns") + + # The resulting CRC is available on the following edge. + await RisingEdge(clk) + await Timer(2, unit="ns") + return int(dut.crcOut.value) + + +@cocotb.test() +async def eth_crc32_parallel_test(dut): + byte_width = int(os.environ["BYTE_WIDTH_G"]) + + cocotb.start_soon(Clock(dut.crcClk, 5.0, unit="ns").start()) + dut.crcReset.setimmediatevalue(1) + dut.crcDataValid.setimmediatevalue(0) + dut.crcDataWidth.setimmediatevalue(0) + dut.crcIn.setimmediatevalue(0) + + await cycle(dut.crcClk, 3) + dut.crcReset.value = 0 + await cycle(dut.crcClk, 1) + + remainder = 0xFFFFFFFF + assert int(dut.crcOut.value) == crc_out_from_remainder(remainder) + + payloads = [ + [0x12], + [0x34, 0x56, 0x78][: min(byte_width, 3)], + list(range(0x90, 0x90 + min(byte_width, 6))), + ] + + for payload in payloads: + remainder = crc_update(remainder, payload) + observed_crc = await apply_word(dut, clk=dut.crcClk, byte_width=byte_width, payload=payload) + assert observed_crc == crc_out_from_remainder(remainder) + + # When no new valid word is presented, the CRC output should simply hold. + held_value = int(dut.crcOut.value) + await cycle(dut.crcClk, 2) + assert int(dut.crcOut.value) == held_value + + # The Ethernet block uses `crcReset` as a synchronous accumulator reset. + dut.crcReset.value = 1 + await cycle(dut.crcClk, 1) + dut.crcReset.value = 0 + await cycle(dut.crcClk, 1) + assert int(dut.crcOut.value) == crc_out_from_remainder(0xFFFFFFFF) + + +PARAMETER_SWEEP = [ + parameter_case("byte4", BYTE_WIDTH_G="4", USE_DSP_G="false"), + parameter_case("byte16", BYTE_WIDTH_G="16", USE_DSP_G="false"), +] + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +def test_EthCrc32Parallel(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ethcrc32parallel", + parameters=hdl_parameters_from(parameters), + extra_env=parameters, + extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES}, + ) diff --git a/tests/ethernet/eth_mac/test_EthMacFlowCtrl.py b/tests/ethernet/eth_mac/test_EthMacFlowCtrl.py new file mode 100644 index 0000000000..5f0ce6d57f --- /dev/null +++ b/tests/ethernet/eth_mac/test_EthMacFlowCtrl.py @@ -0,0 +1,104 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Cover the default primary-only path and the bypass-enabled merge +# path, since those are the only externally visible modes of this block. +# - Stimulus: Drive primary pause/overflow requests first, then drive bypass +# requests, and finally combine primary and bypass causes in one cycle. +# - Checks: Primary requests must always register through, bypass requests must +# only contribute when `BYP_EN_G=true`, and the merged output must behave as +# a logical OR of the enabled request sources. +# - Timing: The DUT is fully registered, so checks sample one clock after each +# control update instead of relying on combinational observation. + +import cocotb +import pytest +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer + +from tests.common.regression_utils import env_flag, parameter_case, run_surf_vhdl_test +from tests.ethernet.eth_mac.ethmac_test_utils import ETHMAC_RTL_SOURCES + + +WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacFlowCtrlWrapper.vhd" + + +async def cycle(clk, count: int = 1) -> None: + for _ in range(count): + await RisingEdge(clk) + await Timer(1, unit="ns") + + +@cocotb.test() +async def eth_mac_flow_ctrl_test(dut): + byp_en = env_flag("BYP_EN_G", default=False) + + cocotb.start_soon(Clock(dut.ethClk, 5.0, unit="ns").start()) + dut.ethRst.setimmediatevalue(1) + dut.primPause.setimmediatevalue(0) + dut.primOverflow.setimmediatevalue(0) + dut.bypPause.setimmediatevalue(0) + dut.bypOverflow.setimmediatevalue(0) + + await cycle(dut.ethClk, 4) + dut.ethRst.value = 0 + await cycle(dut.ethClk, 2) + + # The wrapper flattens the record interface, so a reset sanity check proves + # both the real DUT and the scalar mapping start from zero. + assert int(dut.flowPause.value) == 0 + assert int(dut.flowOverflow.value) == 0 + + dut.primPause.value = 1 + await cycle(dut.ethClk, 2) + assert int(dut.flowPause.value) == 1 + assert int(dut.flowOverflow.value) == 0 + + dut.primPause.value = 0 + dut.primOverflow.value = 1 + await cycle(dut.ethClk, 2) + assert int(dut.flowPause.value) == 0 + assert int(dut.flowOverflow.value) == 1 + + # Bypass requests are only legal contributors when the generic enables the + # second control plane. + dut.primOverflow.value = 0 + dut.bypPause.value = 1 + dut.bypOverflow.value = 1 + await cycle(dut.ethClk, 2) + assert int(dut.flowPause.value) == (1 if byp_en else 0) + assert int(dut.flowOverflow.value) == (1 if byp_en else 0) + + # When bypass is enabled the merge is bitwise OR, so mixed request sources + # must both appear in the registered output on the next cycle. + dut.primPause.value = 1 + dut.bypPause.value = 0 + dut.bypOverflow.value = 1 + await cycle(dut.ethClk, 2) + assert int(dut.flowPause.value) == 1 + assert int(dut.flowOverflow.value) == (1 if byp_en else 0) + + +PARAMETER_SWEEP = [ + parameter_case("primary_only", BYP_EN_G="false"), + parameter_case("bypass_enabled", BYP_EN_G="true"), +] + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +def test_EthMacFlowCtrl(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ethmacflowctrlwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/eth_mac/test_EthMacRxCsum.py b/tests/ethernet/eth_mac/test_EthMacRxCsum.py new file mode 100644 index 0000000000..fcb82c2367 --- /dev/null +++ b/tests/ethernet/eth_mac/test_EthMacRxCsum.py @@ -0,0 +1,108 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Keep one IPv4/UDP checksum-enabled configuration and exercise both a +# valid packet and an invalid-UDP-checksum packet. +# - Stimulus: Send one correctly checksummed IPv4/UDP Ethernet frame and then +# send the same packet shape with a deliberately wrong UDP checksum. +# - Checks: The valid packet must pass without error bits, while the bad packet +# must still pass through but mark the terminal beat with `UDPERR` and +# `EOFE`, matching the public RX checksum contract. +# - Timing: The RX checksum block has an internal pipeline, so the test waits +# for the visible output frame rather than assuming a fixed beat delay. + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.eth_mac.ethmac_test_utils import ( + ETHMAC_RTL_SOURCES, + build_ipv4_udp_frame, + frame_beats_from_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, +) + + +WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacRxCsumWrapper.vhd" + + +@cocotb.test() +async def eth_mac_rx_csum_test(dut): + bench = await setup_flat_emac_testbench( + dut, + source_prefix="sAxis", + sink_prefix="mAxis", + initial_values={ + "ipCsumEn": 1, + "tcpCsumEn": 0, + "udpCsumEn": 1, + }, + ) + source = bench.source + sink = bench.sink + assert source is not None + assert sink is not None + + payload = b"rx-checksum-good" + valid_frame = build_ipv4_udp_frame( + dst_mac=0x020304050607, + src_mac=0x0A0B0C0D0E0F, + src_ip="192.168.1.10", + dst_ip="192.168.1.20", + src_port=0x1234, + dst_port=0x5678, + payload=payload, + ) + valid_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(valid_frame), clk=bench.clk) + ) + valid_observed = await recv_frame(sink, clk=bench.clk) + await valid_send + + assert payload_from_beats(valid_observed) == valid_frame + assert valid_observed[-1].iperr == 0 + assert valid_observed[-1].udperr == 0 + assert valid_observed[-1].eofe == 0 + + bad_udp_frame = build_ipv4_udp_frame( + dst_mac=0x020304050607, + src_mac=0x0A0B0C0D0E0F, + src_ip="192.168.1.10", + dst_ip="192.168.1.20", + src_port=0x1234, + dst_port=0x5678, + payload=payload, + udp_checksum_override=0x0001, + ) + bad_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(bad_udp_frame), clk=bench.clk) + ) + bad_observed = await recv_frame(sink, clk=bench.clk) + await bad_send + + assert payload_from_beats(bad_observed) == bad_udp_frame + assert bad_observed[-1].iperr == 0 + assert bad_observed[-1].udperr == 1 + assert bad_observed[-1].eofe == 1 + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="ipv4_udp_checksum_check")]) +def test_EthMacRxCsum(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ethmacrxcsumwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/eth_mac/test_EthMacRxFilter.py b/tests/ethernet/eth_mac/test_EthMacRxFilter.py new file mode 100644 index 0000000000..6d03fc0c71 --- /dev/null +++ b/tests/ethernet/eth_mac/test_EthMacRxFilter.py @@ -0,0 +1,102 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Keep filtering enabled and exercise the three key externally visible +# decisions: accept local traffic, drop foreign unicast, and drop on pause. +# - Stimulus: Send one frame addressed to the configured local MAC, one frame +# addressed elsewhere, and one local frame while the downstream pause flag is +# asserted. +# - Checks: Local traffic must pass unchanged, foreign traffic must disappear, +# and the pause-driven drop path must suppress output even for a local frame. +# - Timing: The block has no output backpressure, so each frame is launched +# continuously and the sink watches for visible output rather than handshakes. + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.eth_mac.ethmac_test_utils import ( + ETHMAC_RTL_SOURCES, + build_ethernet_frame, + expect_no_output, + frame_beats_from_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, +) + + +WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacRxFilterWrapper.vhd" + + +@cocotb.test() +async def eth_mac_rx_filter_test(dut): + local_mac_wire = 0x001122334455 + # EthMacPkg stores MAC addresses in the same little-endian byte order used + # by the flattened EMAC data word, so the configured register image is the + # reverse of the human-readable wire-order MAC address. + local_mac_reg = 0x554433221100 + bench = await setup_flat_emac_testbench( + dut, + source_prefix="sAxis", + sink_prefix="mAxis", + initial_values={ + "mAxisPause": 0, + "dropOnPause": 0, + "macAddress": local_mac_reg, + "filtEnable": 1, + }, + ) + source = bench.source + sink = bench.sink + assert source is not None + assert sink is not None + + local_frame = build_ethernet_frame( + dst_mac=local_mac_wire, + src_mac=0x0A0B0C0D0E0F, + eth_type=0x88B5, + payload=bytes(range(18)), + ) + local_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(local_frame), clk=bench.clk) + ) + local_observed = await recv_frame(sink, clk=bench.clk) + await local_send + assert payload_from_beats(local_observed) == local_frame + + foreign_frame = build_ethernet_frame( + dst_mac=0x00AA00BB00CC, + src_mac=0x0A0B0C0D0E0F, + eth_type=0x88B5, + payload=b"foreign-unicast-drop", + ) + await send_contiguous_frame(source, frame_beats_from_bytes(foreign_frame), clk=bench.clk) + await expect_no_output(sink, clk=bench.clk, cycles=8) + + # The downstream pause indication is a separate control surface, so this + # check proves the block can suppress even a local destination frame. + dut.dropOnPause.value = 1 + dut.mAxisPause.value = 1 + await send_contiguous_frame(source, frame_beats_from_bytes(local_frame), clk=bench.clk) + await expect_no_output(sink, clk=bench.clk, cycles=8) + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="local_match_and_drop_paths")]) +def test_EthMacRxFilter(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ethmacrxfilterwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/eth_mac/test_EthMacRxImport.py b/tests/ethernet/eth_mac/test_EthMacRxImport.py new file mode 100644 index 0000000000..7985068478 --- /dev/null +++ b/tests/ethernet/eth_mac/test_EthMacRxImport.py @@ -0,0 +1,87 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Keep one XGMII loopback case so the test proves the import path +# using the most direct checked-in wrapper arrangement. +# - Stimulus: Send one minimum-size Ethernet frame through the shared +# export-to-import loopback wrapper. +# - Checks: The recovered AXIS frame must match the original bytes and the RX +# packet counter pulse must assert without any CRC error pulse. +# - Timing: The wrapper loops the PHY-coded stream internally, so the bench +# launches one contiguous AXIS frame and samples the recovered output frame. + +import cocotb +import pytest + +from tests.common.regression_utils import parameter_case, run_surf_vhdl_test +from tests.ethernet.eth_mac.ethmac_test_utils import ( + ETHMAC_RTL_SOURCES, + build_ethernet_frame, + frame_beats_from_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, + wait_signal_pulse, +) + + +WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacImportExportLoopbackWrapper.vhd" + + +@cocotb.test() +async def eth_mac_rx_import_test(dut): + bench = await setup_flat_emac_testbench( + dut, + source_prefix="sAxis", + sink_prefix="mAxis", + initial_values={ + "ethClkEn": 1, + "phyReady": 1, + }, + ) + source = bench.source + sink = bench.sink + assert source is not None + assert sink is not None + + frame = build_ethernet_frame( + dst_mac=0x020304050607, + src_mac=0x0A0B0C0D0E0F, + eth_type=0x88B5, + payload=bytes(range(46)), + ) + rx_pulse = cocotb.start_soon(wait_signal_pulse(dut.rxCountEn, clk=bench.clk)) + send_task = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(frame), clk=bench.clk) + ) + observed_beats = await recv_frame(sink, clk=bench.clk) + await send_task + await rx_pulse + + assert payload_from_beats(observed_beats) == frame + assert int(dut.rxCrcError.value) == 0 + + +PARAMETER_SWEEP = [ + parameter_case("xgmii_loopback", PHY_TYPE_G="XGMII"), +] + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +def test_EthMacRxImport(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ethmacimportexportloopbackwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/eth_mac/test_EthMacRxPause.py b/tests/ethernet/eth_mac/test_EthMacRxPause.py new file mode 100644 index 0000000000..61e977decb --- /dev/null +++ b/tests/ethernet/eth_mac/test_EthMacRxPause.py @@ -0,0 +1,100 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Keep one pause-enabled configuration and cover the three observable +# behaviors of the block: normal pass-through, valid pause detection, and +# EOFE-terminated pause rejection. +# - Stimulus: Send one ordinary Ethernet frame, one standards-compliant pause +# frame, and one identical pause frame marked bad with `EOFE`. +# - Checks: Ordinary traffic must pass unchanged, valid pause traffic must be +# dropped while pulsing the pause request/value outputs, and bad pause +# traffic must be dropped without raising a pause request. +# - Timing: The output path has no backpressure, so the test launches each +# frame continuously and watches the visible output beats directly. + +import cocotb +import pytest +from cocotb.triggers import RisingEdge, Timer + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.eth_mac.ethmac_test_utils import ( + ETHMAC_RTL_SOURCES, + build_ethernet_frame, + build_pause_frame, + expect_no_output, + frame_beats_from_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, + wait_signal_pulse, +) + + +WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacRxPauseWrapper.vhd" + + +@cocotb.test() +async def eth_mac_rx_pause_test(dut): + bench = await setup_flat_emac_testbench( + dut, + source_prefix="sAxis", + sink_prefix="mAxis", + ) + source = bench.source + sink = bench.sink + assert source is not None + assert sink is not None + + normal_frame = build_ethernet_frame( + dst_mac=0xDA0203040506, + src_mac=0x5A1122334455, + eth_type=0x88B5, + payload=bytes(range(20)), + ) + normal_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(normal_frame), clk=bench.clk) + ) + observed_normal = await recv_frame(sink, clk=bench.clk) + await normal_send + assert payload_from_beats(observed_normal) == normal_frame + + pause_value = 0x1234 + pause_frame = build_pause_frame(pause_value) + pause_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(pause_frame), clk=bench.clk) + ) + await wait_signal_pulse(dut.rxPauseReq, clk=bench.clk) + await pause_send + assert int(dut.rxPauseValue.value) == pause_value + await expect_no_output(sink, clk=bench.clk, cycles=8) + + # Mark the final beat bad so the pause decoder sees the same header but + # must suppress the resulting pause request. + bad_pause_beats = frame_beats_from_bytes(build_pause_frame(0xBEEF), eofe=1) + bad_pause_send = cocotb.start_soon(send_contiguous_frame(source, bad_pause_beats, clk=bench.clk)) + for _ in range(16): + await Timer(1, unit="ns") + assert int(dut.rxPauseReq.value) == 0 + await RisingEdge(bench.clk) + await bad_pause_send + await expect_no_output(sink, clk=bench.clk, cycles=8) + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="pause_decode_and_drop")]) +def test_EthMacRxPause(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ethmacrxpausewrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/eth_mac/test_EthMacRxShift.py b/tests/ethernet/eth_mac/test_EthMacRxShift.py new file mode 100644 index 0000000000..5500957900 --- /dev/null +++ b/tests/ethernet/eth_mac/test_EthMacRxShift.py @@ -0,0 +1,78 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Cover the enabled byte-insert path and the disabled pass-through +# path because those are the only meaningful modes of this wrapper. +# - Stimulus: Send one short single-beat frame with `rxShift=2`. +# - Checks: The enabled mode must prepend two zero bytes to the packet while +# preserving the frame boundary bits, and the disabled mode must leave the +# packet untouched. +# - Timing: The RX shift block has no sink-side backpressure, so the frame is +# launched continuously and the test samples the visible output beats. + +import cocotb +import pytest + +from tests.common.regression_utils import env_flag, parameter_case, run_surf_vhdl_test +from tests.ethernet.eth_mac.ethmac_test_utils import ( + ETHMAC_RTL_SOURCES, + frame_beats_from_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, +) + + +WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacRxShiftWrapper.vhd" + + +@cocotb.test() +async def eth_mac_rx_shift_test(dut): + shift_enabled = env_flag("SHIFT_EN_G", default=True) + bench = await setup_flat_emac_testbench( + dut, + source_prefix="sAxis", + sink_prefix="mAxis", + initial_values={"rxShift": 2}, + ) + source = bench.source + sink = bench.sink + assert source is not None + assert sink is not None + + input_bytes = b"\x10\x11\x12\x13\x14" + send_task = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(input_bytes), clk=bench.clk) + ) + observed_beats = await recv_frame(sink, clk=bench.clk) + await send_task + + expected_bytes = (b"\x00\x00" + input_bytes) if shift_enabled else input_bytes + assert payload_from_beats(observed_beats) == expected_bytes + assert observed_beats[-1].last == 1 + + +PARAMETER_SWEEP = [ + parameter_case("shift_enabled", SHIFT_EN_G="true"), + parameter_case("shift_disabled", SHIFT_EN_G="false"), +] + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +def test_EthMacRxShift(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ethmacrxshiftwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/eth_mac/test_EthMacTop.py b/tests/ethernet/eth_mac/test_EthMacTop.py new file mode 100644 index 0000000000..5e9043b1c7 --- /dev/null +++ b/tests/ethernet/eth_mac/test_EthMacTop.py @@ -0,0 +1,107 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Keep one XGMII top-level loopback case with filtering and pause +# features disabled so the first bench proves the primary data path cleanly. +# - Stimulus: Send one minimum-size Ethernet frame into the flattened primary +# AXIS input of the checked-in loopback wrapper. +# - Checks: The primary output frame must match the original bytes, both TX and +# RX packet counter pulses must assert, and the looped packet must not report +# a CRC error status pulse. +# - Timing: The wrapper ties the MAC's XGMII TX and RX sides together +# internally, so the bench waits on the real top-level AXIS output rather +# than assuming a fixed import/export/FIFO latency. + +import cocotb +import pytest +from pathlib import Path + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.eth_mac.ethmac_test_utils import ( + ETHMAC_RTL_SOURCES, + build_ethernet_frame, + frame_beats_from_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, + wait_signal_pulse, +) + + +WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacTopLoopbackWrapper.vhd" +ROCE_RTL_ROOT = Path(__file__).resolve().parents[3] / "ethernet" / "RoCEv2" / "rtl" +ROCE_ANALYSIS_SOURCES = [ + str(ROCE_RTL_ROOT / "RocePkg.vhd"), + *( + str(path) + for path in sorted(ROCE_RTL_ROOT.glob("*.vhd")) + if path.name != "RocePkg.vhd" + ), +] + + +@cocotb.test() +async def eth_mac_top_test(dut): + bench = await setup_flat_emac_testbench( + dut, + source_prefix="sAxis", + sink_prefix="mAxis", + initial_values={ + "phyReady": 1, + "mAxisTReady": 0, + "localMac": 0x001122334455, + "filtEnable": 0, + "pauseEnable": 0, + "pauseTime": 0x0020, + "pauseThresh": 0x0008, + "ipCsumEn": 0, + "tcpCsumEn": 0, + "udpCsumEn": 0, + "dropOnPause": 0, + }, + ) + source = bench.source + sink = bench.sink + assert source is not None + assert sink is not None + + frame = build_ethernet_frame( + dst_mac=0x5A0102030405, + src_mac=0x660102030405, + eth_type=0x88B5, + payload=bytes(range(46)), + ) + tx_pulse = cocotb.start_soon(wait_signal_pulse(dut.txCountEn, clk=bench.clk)) + rx_pulse = cocotb.start_soon(wait_signal_pulse(dut.rxCountEn, clk=bench.clk)) + send_task = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(frame), clk=bench.clk) + ) + observed_beats = await recv_frame(sink, clk=bench.clk, ready_signal=dut.mAxisTReady, timeout_cycles=256) + await send_task + await tx_pulse + await rx_pulse + + assert payload_from_beats(observed_beats) == frame + assert int(dut.rxCrcErrorCnt.value) == 0 + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="xgmii_top_loopback")]) +def test_EthMacTop(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ethmactoploopbackwrapper", + parameters=parameters, + extra_env=parameters, + # `EthMacTx` and `EthMacRx` reference the RoCE helper entities during + # analysis even when `ROCEV2_EN_G` is disabled in the loopback wrapper. + extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES + ROCE_ANALYSIS_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/eth_mac/test_EthMacTxCsum.py b/tests/ethernet/eth_mac/test_EthMacTxCsum.py new file mode 100644 index 0000000000..d2e6046d81 --- /dev/null +++ b/tests/ethernet/eth_mac/test_EthMacTxCsum.py @@ -0,0 +1,100 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Keep one IPv4/UDP checksum-enabled loopback case where the TX repair +# block feeds the RX checker wrapper directly. +# - Stimulus: Send one IPv4/UDP packet with the IP and UDP checksum fields +# cleared to zero. +# - Checks: The emitted packet bytes must match the software-computed checksum- +# inserted frame, and the RX checker must report no terminal checksum errors. +# - Timing: The wrapper's internal RX checker absorbs the post-TX packet, so +# the bench waits for the visible checked output frame rather than assuming a +# fixed internal pipeline depth. + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.eth_mac.ethmac_test_utils import ( + ETHMAC_RTL_SOURCES, + build_ipv4_udp_frame, + frame_beats_from_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, +) + + +WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacTxCsumLoopbackWrapper.vhd" + + +@cocotb.test() +async def eth_mac_tx_csum_test(dut): + bench = await setup_flat_emac_testbench( + dut, + source_prefix="sAxis", + sink_prefix="mAxis", + initial_values={ + "ipCsumEn": 1, + "tcpCsumEn": 0, + "udpCsumEn": 1, + }, + ) + source = bench.source + sink = bench.sink + assert source is not None + assert sink is not None + + payload = b"tx-checksum-fixup" + repaired_frame = build_ipv4_udp_frame( + dst_mac=0x112233445566, + src_mac=0xAABBCCDDEEFF, + src_ip="10.0.0.1", + dst_ip="10.0.0.2", + src_port=0x1001, + dst_port=0x2002, + payload=payload, + ) + input_frame = build_ipv4_udp_frame( + dst_mac=0x112233445566, + src_mac=0xAABBCCDDEEFF, + src_ip="10.0.0.1", + dst_ip="10.0.0.2", + src_port=0x1001, + dst_port=0x2002, + payload=payload, + ip_checksum_override=0x0000, + udp_checksum_override=0x0000, + ) + + send_task = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(input_frame), clk=bench.clk) + ) + observed_beats = await recv_frame(sink, clk=bench.clk) + await send_task + + assert payload_from_beats(observed_beats) == repaired_frame + assert observed_beats[-1].iperr == 0 + assert observed_beats[-1].tcperr == 0 + assert observed_beats[-1].udperr == 0 + assert observed_beats[-1].eofe == 0 + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="ipv4_udp_checksum_insert")]) +def test_EthMacTxCsum(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ethmactxcsumloopbackwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/eth_mac/test_EthMacTxExport.py b/tests/ethernet/eth_mac/test_EthMacTxExport.py new file mode 100644 index 0000000000..9f0321d5ef --- /dev/null +++ b/tests/ethernet/eth_mac/test_EthMacTxExport.py @@ -0,0 +1,88 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Keep one XGMII loopback case so the test proves the export path +# without mixing in additional PHY-family variables yet. +# - Stimulus: Send one minimum-size Ethernet frame into the shared export-to- +# import wrapper so the TX exporter has to build a real PHY stream. +# - Checks: The TX packet counter pulse must assert, the link/error status +# flags must stay low, and the recovered frame must still match the original. +# - Timing: The test relies on the wrapper's internal loopback to observe the +# exported packet through a clean end-to-end handshake path. + +import cocotb +import pytest + +from tests.common.regression_utils import parameter_case, run_surf_vhdl_test +from tests.ethernet.eth_mac.ethmac_test_utils import ( + ETHMAC_RTL_SOURCES, + build_ethernet_frame, + frame_beats_from_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, + wait_signal_pulse, +) + + +WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacImportExportLoopbackWrapper.vhd" + + +@cocotb.test() +async def eth_mac_tx_export_test(dut): + bench = await setup_flat_emac_testbench( + dut, + source_prefix="sAxis", + sink_prefix="mAxis", + initial_values={ + "ethClkEn": 1, + "phyReady": 1, + }, + ) + source = bench.source + sink = bench.sink + assert source is not None + assert sink is not None + + frame = build_ethernet_frame( + dst_mac=0x0C0D0E0F1011, + src_mac=0x121314151617, + eth_type=0x9000, + payload=bytes(range(46)), + ) + tx_pulse = cocotb.start_soon(wait_signal_pulse(dut.txCountEn, clk=bench.clk)) + send_task = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(frame), clk=bench.clk) + ) + observed_beats = await recv_frame(sink, clk=bench.clk) + await send_task + await tx_pulse + + assert payload_from_beats(observed_beats) == frame + assert int(dut.txUnderRun.value) == 0 + assert int(dut.txLinkNotReady.value) == 0 + + +PARAMETER_SWEEP = [ + parameter_case("xgmii_loopback", PHY_TYPE_G="XGMII"), +] + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +def test_EthMacTxExport(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ethmacimportexportloopbackwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/eth_mac/test_EthMacTxPause.py b/tests/ethernet/eth_mac/test_EthMacTxPause.py new file mode 100644 index 0000000000..97606f0069 --- /dev/null +++ b/tests/ethernet/eth_mac/test_EthMacTxPause.py @@ -0,0 +1,104 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Use one pause-enabled instance with a short pause quanta setting so +# the bench focuses on the visible transmit behavior instead of long waits. +# - Stimulus: Pulse `clientPause` while the link is ready, then send one normal +# frame after the generated pause frame has completed. +# - Checks: The emitted pause frame bytes must match the documented Ethernet +# MAC-control format, `pauseTx` must pulse once, and ordinary client traffic +# must still pass through unchanged when no pause frame is being emitted. +# - Timing: The sink uses explicit `TREADY` handshakes so the four-beat pause +# frame and the later pass-through frame are both consumed deliberately. + +import cocotb +import pytest + +from tests.common.regression_utils import parameter_case, run_surf_vhdl_test +from tests.ethernet.eth_mac.ethmac_test_utils import ( + ETHMAC_RTL_SOURCES, + build_ethernet_frame, + build_pause_frame, + cycle, + frame_beats_from_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, + wait_signal_pulse, +) + + +WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacTxPauseWrapper.vhd" + + +@cocotb.test() +async def eth_mac_tx_pause_test(dut): + pause_time = 0x0030 + bench = await setup_flat_emac_testbench( + dut, + source_prefix="sAxis", + sink_prefix="mAxis", + initial_values={ + "mAxisTReady": 0, + "clientPause": 0, + "rxPauseReq": 0, + "rxPauseValue": 0, + "phyReady": 1, + "pauseEnable": 1, + "pauseTime": pause_time, + "macAddress": 0x001122334455, + }, + ) + source = bench.source + sink = bench.sink + assert source is not None + assert sink is not None + + pause_pulse = cocotb.start_soon(wait_signal_pulse(dut.pauseTx, clk=bench.clk)) + dut.clientPause.value = 1 + await cycle(bench.clk, 1) + dut.clientPause.value = 0 + + pause_frame = await recv_frame(sink, clk=bench.clk, ready_signal=dut.mAxisTReady) + await pause_pulse + assert payload_from_beats(pause_frame) == build_pause_frame(pause_time) + + # Once the one-shot pause transmission is complete, the TX path should + # revert to ordinary client traffic forwarding. + payload_frame = build_ethernet_frame( + dst_mac=0x020304050607, + src_mac=0x08090A0B0C0D, + eth_type=0x9000, + payload=bytes(range(24)), + ) + payload_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(payload_frame), clk=bench.clk) + ) + observed_frame = await recv_frame(sink, clk=bench.clk, ready_signal=dut.mAxisTReady) + await payload_send + assert payload_from_beats(observed_frame) == payload_frame + + +PARAMETER_SWEEP = [ + parameter_case("pause_generator", PAUSE_512BITS_G="1"), +] + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +def test_EthMacTxPause(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ethmactxpausewrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/eth_mac/test_EthMacTxShift.py b/tests/ethernet/eth_mac/test_EthMacTxShift.py new file mode 100644 index 0000000000..adf6d00424 --- /dev/null +++ b/tests/ethernet/eth_mac/test_EthMacTxShift.py @@ -0,0 +1,81 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Cover the enabled byte-remove path and the disabled pass-through +# path because those are the only externally visible TX modes. +# - Stimulus: Send one short single-beat frame with `txShift=2`. +# - Checks: The enabled mode must remove the first two bytes of the packet +# while preserving the frame boundary bits, and the disabled mode must leave +# the packet untouched. +# - Timing: The TX shift stage participates in the AXI handshake, so the sink +# explicitly raises `TREADY` while consuming the output frame. + +import cocotb +import pytest + +from tests.common.regression_utils import env_flag, parameter_case, run_surf_vhdl_test +from tests.ethernet.eth_mac.ethmac_test_utils import ( + ETHMAC_RTL_SOURCES, + frame_beats_from_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, +) + + +WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacTxShiftWrapper.vhd" + + +@cocotb.test() +async def eth_mac_tx_shift_test(dut): + shift_enabled = env_flag("SHIFT_EN_G", default=True) + bench = await setup_flat_emac_testbench( + dut, + source_prefix="sAxis", + sink_prefix="mAxis", + initial_values={ + "txShift": 2, + "mAxisTReady": 0, + }, + ) + source = bench.source + sink = bench.sink + assert source is not None + assert sink is not None + + input_bytes = b"\xAA\xBB\x10\x11\x12\x13" + send_task = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(input_bytes), clk=bench.clk) + ) + observed_beats = await recv_frame(sink, clk=bench.clk, ready_signal=dut.mAxisTReady) + await send_task + + expected_bytes = input_bytes[2:] if shift_enabled else input_bytes + assert payload_from_beats(observed_beats) == expected_bytes + assert observed_beats[-1].last == 1 + + +PARAMETER_SWEEP = [ + parameter_case("shift_enabled", SHIFT_EN_G="true"), + parameter_case("shift_disabled", SHIFT_EN_G="false"), +] + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +def test_EthMacTxShift(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ethmactxshiftwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES + [WRAPPER_PATH]}, + ) From e30273d4f7a2518d155c086af6208f6a1c8354cb Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 10 Apr 2026 00:39:15 -0700 Subject: [PATCH 04/92] Expand top level tests. --- tests/ethernet/eth_mac/ethmac_test_utils.py | 25 ++ tests/ethernet/eth_mac/test_EthMacTop.py | 268 ++++++++++++++++++-- 2 files changed, 268 insertions(+), 25 deletions(-) diff --git a/tests/ethernet/eth_mac/ethmac_test_utils.py b/tests/ethernet/eth_mac/ethmac_test_utils.py index eb359aa83f..77ad78a57e 100644 --- a/tests/ethernet/eth_mac/ethmac_test_utils.py +++ b/tests/ethernet/eth_mac/ethmac_test_utils.py @@ -222,6 +222,13 @@ def mac_to_bytes(mac: int) -> bytes: return mac.to_bytes(6, byteorder="big") +def mac_config_word_from_wire(mac: int) -> int: + # EthMac config registers store MAC bytes in the same least-significant- + # lane-first order used by the flattened EMAC datapath, so reverse the + # normal wire-order MAC before driving config ports such as `localMac`. + return int.from_bytes(mac_to_bytes(mac)[::-1], byteorder="big") + + def ipv4_to_bytes(address: str) -> bytes: return ipaddress.IPv4Address(address).packed @@ -400,6 +407,24 @@ async def send_contiguous_frame(endpoint: FlatEmacEndpoint, beats: list[EmacBeat endpoint.set_idle() +async def send_frame_burst( + endpoint: FlatEmacEndpoint, + frames: list[list[EmacBeat]], + *, + clk, + inter_frame_gap_cycles: int = 0, +) -> None: + # Burst-style top-level tests need consecutive frames without rebuilding a + # new source coroutine for each packet. This helper keeps frame boundaries + # explicit while allowing zero-gap or small-gap sequencing. + for index, frame in enumerate(frames): + await send_contiguous_frame(endpoint, frame, clk=clk) + if index != len(frames) - 1: + for _ in range(inter_frame_gap_cycles): + await RisingEdge(clk) + await Timer(1, unit="ns") + + async def recv_frame(endpoint: FlatEmacEndpoint, *, clk, ready_signal=None, timeout_cycles: int = 64) -> list[EmacBeat]: beats = [] if ready_signal is not None: diff --git a/tests/ethernet/eth_mac/test_EthMacTop.py b/tests/ethernet/eth_mac/test_EthMacTop.py index 5e9043b1c7..6169407ace 100644 --- a/tests/ethernet/eth_mac/test_EthMacTop.py +++ b/tests/ethernet/eth_mac/test_EthMacTop.py @@ -9,29 +9,37 @@ ############################################################################## # Test methodology: -# - Sweep: Keep one XGMII top-level loopback case with filtering and pause -# features disabled so the first bench proves the primary data path cleanly. -# - Stimulus: Send one minimum-size Ethernet frame into the flattened primary -# AXIS input of the checked-in loopback wrapper. -# - Checks: The primary output frame must match the original bytes, both TX and -# RX packet counter pulses must assert, and the looped packet must not report -# a CRC error status pulse. -# - Timing: The wrapper ties the MAC's XGMII TX and RX sides together -# internally, so the bench waits on the real top-level AXIS output rather -# than assuming a fixed import/export/FIFO latency. +# - Sweep: Enable the checked-in top-level filter and pause generics so one +# wrapper build can exercise the meaningful runtime configuration matrix. +# - Stimulus: Run three curated scenarios through the real XGMII loopback path: +# filter plus backpressure behavior, TX checksum repair plus RX verification, +# and remote pause reception followed by gated outbound traffic. +# - Checks: Filtering must pass local and broadcast traffic while dropping +# foreign unicast, checksum-enabled packets must emerge repaired without RX +# error flags, and a received pause frame must suppress subsequent traffic +# until the pause interval expires. +# - Timing: The bench waits on visible AXIS/status behavior rather than assuming +# fixed internal pipeline depth, because the top-level MAC includes FIFO, +# pause, and import/export staging. import cocotb import pytest from pathlib import Path -from tests.common.regression_utils import run_surf_vhdl_test +from tests.common.regression_utils import parameter_case, run_surf_vhdl_test from tests.ethernet.eth_mac.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, build_ethernet_frame, + build_ipv4_udp_frame, + build_pause_frame, + cycle, + expect_no_output, frame_beats_from_bytes, + mac_config_word_from_wire, payload_from_beats, recv_frame, send_contiguous_frame, + send_frame_burst, setup_flat_emac_testbench, wait_signal_pulse, ) @@ -48,9 +56,102 @@ ), ] +LOCAL_MAC_WIRE = 0x001122334455 +LOCAL_MAC_CFG = mac_config_word_from_wire(LOCAL_MAC_WIRE) + + +@cocotb.test() +async def eth_mac_top_filter_and_backpressure_test(dut): + bench = await setup_flat_emac_testbench( + dut, + source_prefix="sAxis", + sink_prefix="mAxis", + initial_values={ + "phyReady": 1, + "mAxisTReady": 0, + "localMac": LOCAL_MAC_CFG, + "filtEnable": 1, + "pauseEnable": 0, + "pauseTime": 0x0020, + "pauseThresh": 0x0008, + "ipCsumEn": 0, + "tcpCsumEn": 0, + "udpCsumEn": 0, + "dropOnPause": 0, + }, + ) + source = bench.source + sink = bench.sink + assert source is not None + assert sink is not None + + local_frame = build_ethernet_frame( + dst_mac=LOCAL_MAC_WIRE, + src_mac=0x660102030405, + eth_type=0x88B5, + payload=bytes(range(46)), + ) + local_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(local_frame), clk=bench.clk) + ) + + # Hold the downstream ready low long enough to prove the top-level RX FIFO + # can retain a valid local frame without corrupting it or flagging overflow. + await sink.wait_valid(clk=bench.clk, timeout_cycles=256) + await cycle(bench.clk, 4) + assert int(dut.rxOverFlow.value) == 0 + + local_observed = await recv_frame( + sink, + clk=bench.clk, + ready_signal=dut.mAxisTReady, + timeout_cycles=256, + ) + await local_send + assert payload_from_beats(local_observed) == local_frame + + foreign_frame = build_ethernet_frame( + dst_mac=0x00AA00BB00CC, + src_mac=0x660102030405, + eth_type=0x88B5, + payload=b"foreign-unicast-drop", + ) + broadcast_frame = build_ethernet_frame( + dst_mac=0xFFFFFFFFFFFF, + src_mac=0x660102030405, + eth_type=0x88B5, + # Keep the payload at Ethernet's minimum so this scenario isolates the + # filter decision instead of also depending on TX-side padding. + payload=b"broadcast-pass-through" + bytes(24), + ) + + # Send a dropped foreign-unicast frame directly ahead of a broadcast frame + # so the filter test also proves the RX state machine resets cleanly across + # consecutive packets. + burst_send = cocotb.start_soon( + send_frame_burst( + source, + [ + frame_beats_from_bytes(foreign_frame), + frame_beats_from_bytes(broadcast_frame), + ], + clk=bench.clk, + ) + ) + broadcast_observed = await recv_frame( + sink, + clk=bench.clk, + ready_signal=dut.mAxisTReady, + timeout_cycles=512, + ) + await burst_send + + assert payload_from_beats(broadcast_observed) == broadcast_frame + await expect_no_output(sink, clk=bench.clk, cycles=8) + @cocotb.test() -async def eth_mac_top_test(dut): +async def eth_mac_top_checksum_loopback_test(dut): bench = await setup_flat_emac_testbench( dut, source_prefix="sAxis", @@ -58,11 +159,102 @@ async def eth_mac_top_test(dut): initial_values={ "phyReady": 1, "mAxisTReady": 0, - "localMac": 0x001122334455, + "localMac": LOCAL_MAC_CFG, "filtEnable": 0, "pauseEnable": 0, "pauseTime": 0x0020, "pauseThresh": 0x0008, + "ipCsumEn": 1, + "tcpCsumEn": 0, + "udpCsumEn": 1, + "dropOnPause": 0, + }, + ) + source = bench.source + sink = bench.sink + assert source is not None + assert sink is not None + + repaired_frame = build_ipv4_udp_frame( + dst_mac=0x112233445566, + src_mac=0xAABBCCDDEEFF, + src_ip="10.0.0.1", + dst_ip="10.0.0.2", + src_port=0x1001, + dst_port=0x2002, + payload=b"eth-mac-top-fixup!", + ) + checksum_clear_frame = build_ipv4_udp_frame( + dst_mac=0x112233445566, + src_mac=0xAABBCCDDEEFF, + src_ip="10.0.0.1", + dst_ip="10.0.0.2", + src_port=0x1001, + dst_port=0x2002, + payload=b"eth-mac-top-fixup!", + ip_checksum_override=0x0000, + udp_checksum_override=0x0000, + ) + already_valid_frame = build_ipv4_udp_frame( + dst_mac=0x010203040506, + src_mac=0xAABBCCDDEEFF, + src_ip="10.0.0.3", + dst_ip="10.0.0.4", + src_port=0x3003, + dst_port=0x4004, + payload=b"second-frame-stays-valid", + ) + + burst_send = cocotb.start_soon( + send_frame_burst( + source, + [ + frame_beats_from_bytes(checksum_clear_frame), + frame_beats_from_bytes(already_valid_frame), + ], + clk=bench.clk, + ) + ) + repaired_observed = await recv_frame( + sink, + clk=bench.clk, + ready_signal=dut.mAxisTReady, + timeout_cycles=512, + ) + valid_observed = await recv_frame( + sink, + clk=bench.clk, + ready_signal=dut.mAxisTReady, + timeout_cycles=512, + ) + await burst_send + + assert payload_from_beats(repaired_observed) == repaired_frame + assert payload_from_beats(valid_observed) == already_valid_frame + + # The top-level loopback bench is stronger than the leaf checksum benches + # because the repaired packet is immediately checked again by the RX path. + for beat in (repaired_observed[-1], valid_observed[-1]): + assert beat.iperr == 0 + assert beat.tcperr == 0 + assert beat.udperr == 0 + assert beat.eofe == 0 + + +@cocotb.test() +async def eth_mac_top_pause_gate_test(dut): + bench = await setup_flat_emac_testbench( + dut, + source_prefix="sAxis", + sink_prefix="mAxis", + initial_values={ + "phyReady": 1, + "mAxisTReady": 0, + "localMac": LOCAL_MAC_CFG, + "filtEnable": 0, + "pauseEnable": 1, + "pauseTime": 0x0002, + "pauseThresh": 0x0008, "ipCsumEn": 0, "tcpCsumEn": 0, "udpCsumEn": 0, @@ -74,27 +266,53 @@ async def eth_mac_top_test(dut): assert source is not None assert sink is not None - frame = build_ethernet_frame( + pause_frame = build_pause_frame(1) + pause_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(pause_frame), clk=bench.clk) + ) + await wait_signal_pulse(dut.rxPauseCnt, clk=bench.clk, timeout_cycles=256) + await pause_send + + # Pause control frames are consumed internally by the RX pause handler, so + # the primary application stream should stay quiet. + await expect_no_output(sink, clk=bench.clk, cycles=8) + + gated_frame = build_ethernet_frame( dst_mac=0x5A0102030405, src_mac=0x660102030405, eth_type=0x88B5, - payload=bytes(range(46)), + payload=b"pause-release-check" + bytes(27), + ) + gated_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(gated_frame), clk=bench.clk) ) - tx_pulse = cocotb.start_soon(wait_signal_pulse(dut.txCountEn, clk=bench.clk)) - rx_pulse = cocotb.start_soon(wait_signal_pulse(dut.rxCountEn, clk=bench.clk)) - send_task = cocotb.start_soon( - send_contiguous_frame(source, frame_beats_from_bytes(frame), clk=bench.clk) + + # The received pause request should suppress the next outbound packet long + # enough that it definitely does not appear immediately. + await expect_no_output(sink, clk=bench.clk, cycles=4) + gated_observed = await recv_frame( + sink, + clk=bench.clk, + ready_signal=dut.mAxisTReady, + timeout_cycles=512, ) - observed_beats = await recv_frame(sink, clk=bench.clk, ready_signal=dut.mAxisTReady, timeout_cycles=256) - await send_task - await tx_pulse - await rx_pulse + await gated_send - assert payload_from_beats(observed_beats) == frame + assert payload_from_beats(gated_observed) == gated_frame assert int(dut.rxCrcErrorCnt.value) == 0 -@pytest.mark.parametrize("parameters", [pytest.param({}, id="xgmii_top_loopback")]) +PARAMETER_SWEEP = [ + parameter_case( + "xgmii_feature_matrix", + FILT_EN_G="true", + PAUSE_EN_G="true", + PAUSE_512BITS_G="8", + ), +] + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) def test_EthMacTop(parameters): run_surf_vhdl_test( test_file=__file__, From 534963ef55aace228cd0b868c2d554cee3b3fdb9 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 10 Apr 2026 00:56:07 -0700 Subject: [PATCH 05/92] More eth mac tests. --- tests/ethernet/eth_mac/ethmac_test_utils.py | 6 + tests/ethernet/eth_mac/test_EthMacFlowCtrl.py | 29 ++++- tests/ethernet/eth_mac/test_EthMacRxCsum.py | 67 +++++++++-- tests/ethernet/eth_mac/test_EthMacRxImport.py | 111 +++++++++++++++--- tests/ethernet/eth_mac/test_EthMacRxPause.py | 31 +++-- tests/ethernet/eth_mac/test_EthMacTxCsum.py | 77 ++++++++++-- tests/ethernet/eth_mac/test_EthMacTxExport.py | 111 +++++++++++++++--- tests/ethernet/eth_mac/test_EthMacTxPause.py | 59 ++++++++-- 8 files changed, 418 insertions(+), 73 deletions(-) diff --git a/tests/ethernet/eth_mac/ethmac_test_utils.py b/tests/ethernet/eth_mac/ethmac_test_utils.py index 77ad78a57e..15dc607c52 100644 --- a/tests/ethernet/eth_mac/ethmac_test_utils.py +++ b/tests/ethernet/eth_mac/ethmac_test_utils.py @@ -251,6 +251,12 @@ def build_ethernet_frame(*, dst_mac: int, src_mac: int, eth_type: int, payload: return mac_to_bytes(dst_mac) + mac_to_bytes(src_mac) + eth_type.to_bytes(2, byteorder="big") + payload +def pad_ethernet_frame_to_min_size(frame: bytes) -> bytes: + # Ethernet transmits at least 60 bytes before FCS, so short frames that + # traverse the TX path emerge padded with zeros on the wire. + return frame if len(frame) >= 60 else frame + bytes(60 - len(frame)) + + def build_ipv4_header( *, src_ip: str, diff --git a/tests/ethernet/eth_mac/test_EthMacFlowCtrl.py b/tests/ethernet/eth_mac/test_EthMacFlowCtrl.py index 5f0ce6d57f..8722d5e146 100644 --- a/tests/ethernet/eth_mac/test_EthMacFlowCtrl.py +++ b/tests/ethernet/eth_mac/test_EthMacFlowCtrl.py @@ -11,11 +11,12 @@ # Test methodology: # - Sweep: Cover the default primary-only path and the bypass-enabled merge # path, since those are the only externally visible modes of this block. -# - Stimulus: Drive primary pause/overflow requests first, then drive bypass -# requests, and finally combine primary and bypass causes in one cycle. -# - Checks: Primary requests must always register through, bypass requests must -# only contribute when `BYP_EN_G=true`, and the merged output must behave as -# a logical OR of the enabled request sources. +# - Stimulus: Drive primary-only causes, bypass-only causes, sustained mixed +# requests, and then clear all request sources back to zero. +# - Checks: Primary requests must always pass, bypass requests must only +# contribute when `BYP_EN_G=true`, mixed requests must behave as a registered +# OR of the active sources, and the output must return to zero once all +# causes are removed. # - Timing: The DUT is fully registered, so checks sample one clock after each # control update instead of relying on combinational observation. @@ -86,6 +87,24 @@ async def eth_mac_flow_ctrl_test(dut): assert int(dut.flowPause.value) == 1 assert int(dut.flowOverflow.value) == (1 if byp_en else 0) + # Hold multiple request causes high together for a few cycles so the test + # proves the merged output remains stable rather than only pulsing once. + dut.primOverflow.value = 1 + dut.bypPause.value = 1 + await cycle(dut.ethClk, 3) + assert int(dut.flowPause.value) == 1 + assert int(dut.flowOverflow.value) == 1 + + # Once every contributing request is removed, the registered flow-control + # outputs must return cleanly to zero. + dut.primPause.value = 0 + dut.primOverflow.value = 0 + dut.bypPause.value = 0 + dut.bypOverflow.value = 0 + await cycle(dut.ethClk, 2) + assert int(dut.flowPause.value) == 0 + assert int(dut.flowOverflow.value) == 0 + PARAMETER_SWEEP = [ parameter_case("primary_only", BYP_EN_G="false"), diff --git a/tests/ethernet/eth_mac/test_EthMacRxCsum.py b/tests/ethernet/eth_mac/test_EthMacRxCsum.py index fcb82c2367..b0aedebaf2 100644 --- a/tests/ethernet/eth_mac/test_EthMacRxCsum.py +++ b/tests/ethernet/eth_mac/test_EthMacRxCsum.py @@ -9,15 +9,16 @@ ############################################################################## # Test methodology: -# - Sweep: Keep one IPv4/UDP checksum-enabled configuration and exercise both a -# valid packet and an invalid-UDP-checksum packet. -# - Stimulus: Send one correctly checksummed IPv4/UDP Ethernet frame and then -# send the same packet shape with a deliberately wrong UDP checksum. -# - Checks: The valid packet must pass without error bits, while the bad packet -# must still pass through but mark the terminal beat with `UDPERR` and -# `EOFE`, matching the public RX checksum contract. -# - Timing: The RX checksum block has an internal pipeline, so the test waits -# for the visible output frame rather than assuming a fixed beat delay. +# - Sweep: Keep one checksum-enabled instance but cover valid UDP traffic, bad +# UDP checksum, bad IPv4 header checksum, and a non-UDP IPv4 packet. +# - Stimulus: Send one good IPv4/UDP frame, one with a deliberately wrong UDP +# checksum, one with a deliberately wrong IPv4 checksum, and one ICMP-style +# IPv4 packet that should bypass transport checksum handling. +# - Checks: Good traffic must pass cleanly, bad UDP must assert `UDPERR` and +# `EOFE`, bad IP must assert `IPERR`, and non-UDP traffic must not spuriously +# set UDP/TCP error flags. +# - Timing: The RX checksum block has an internal pipeline, so every case waits +# on the visible output frame instead of assuming a fixed internal latency. import cocotb import pytest @@ -25,6 +26,8 @@ from tests.common.regression_utils import run_surf_vhdl_test from tests.ethernet.eth_mac.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, + build_ethernet_frame, + build_ipv4_header, build_ipv4_udp_frame, frame_beats_from_bytes, payload_from_beats, @@ -96,6 +99,52 @@ async def eth_mac_rx_csum_test(dut): assert bad_observed[-1].udperr == 1 assert bad_observed[-1].eofe == 1 + bad_ip_frame = build_ipv4_udp_frame( + dst_mac=0x020304050607, + src_mac=0x0A0B0C0D0E0F, + src_ip="192.168.1.10", + dst_ip="192.168.1.20", + src_port=0x1234, + dst_port=0x5678, + payload=payload, + ip_checksum_override=0x0001, + ) + bad_ip_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(bad_ip_frame), clk=bench.clk) + ) + bad_ip_observed = await recv_frame(sink, clk=bench.clk) + await bad_ip_send + + assert payload_from_beats(bad_ip_observed) == bad_ip_frame + assert bad_ip_observed[-1].iperr == 1 + assert bad_ip_observed[-1].tcperr == 0 + assert bad_ip_observed[-1].udperr == 0 + + icmp_payload = b"icmp-is-not-udp" + icmp_frame = build_ethernet_frame( + dst_mac=0x020304050607, + src_mac=0x0A0B0C0D0E0F, + eth_type=0x0800, + payload=build_ipv4_header( + src_ip="192.168.1.10", + dst_ip="192.168.1.20", + protocol=0x01, + payload_length=len(icmp_payload), + ) + + icmp_payload, + ) + icmp_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(icmp_frame), clk=bench.clk) + ) + icmp_observed = await recv_frame(sink, clk=bench.clk) + await icmp_send + + assert payload_from_beats(icmp_observed) == icmp_frame + assert icmp_observed[-1].iperr == 0 + assert icmp_observed[-1].tcperr == 0 + assert icmp_observed[-1].udperr == 0 + assert icmp_observed[-1].eofe == 0 + @pytest.mark.parametrize("parameters", [pytest.param({}, id="ipv4_udp_checksum_check")]) def test_EthMacRxCsum(parameters): diff --git a/tests/ethernet/eth_mac/test_EthMacRxImport.py b/tests/ethernet/eth_mac/test_EthMacRxImport.py index 7985068478..032003c1d9 100644 --- a/tests/ethernet/eth_mac/test_EthMacRxImport.py +++ b/tests/ethernet/eth_mac/test_EthMacRxImport.py @@ -9,23 +9,32 @@ ############################################################################## # Test methodology: -# - Sweep: Keep one XGMII loopback case so the test proves the import path -# using the most direct checked-in wrapper arrangement. -# - Stimulus: Send one minimum-size Ethernet frame through the shared -# export-to-import loopback wrapper. -# - Checks: The recovered AXIS frame must match the original bytes and the RX -# packet counter pulse must assert without any CRC error pulse. -# - Timing: The wrapper loops the PHY-coded stream internally, so the bench -# launches one contiguous AXIS frame and samples the recovered output frame. +# - Sweep: Cover both supported functional PHY mappings in this wrapper, +# `GMII` and `XGMII`, and include a link-not-ready interval in each run. +# - Stimulus: Send one minimum-size frame, one longer multi-beat frame, one +# frame while `phyReady=0`, and then one recovery frame after re-enabling the +# link. +# - Checks: Ready PHY modes must recover the original AXIS bytes and pulse +# `rxCountEn`, the blocked frame must not appear while the link is down, and +# the receiver must return to normal operation after `phyReady` is restored. +# The recovery expectation is PHY-specific: GMII drops traffic presented +# while the link is down, while the current XGMII loopback path presents that +# queued frame once `phyReady` returns. +# - Timing: GMII takes many more cycles than XGMII to serialize a frame, so the +# bench scales its receive timeout to the selected PHY mode. import cocotb +import os import pytest from tests.common.regression_utils import parameter_case, run_surf_vhdl_test from tests.ethernet.eth_mac.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, build_ethernet_frame, + cycle, + expect_no_output, frame_beats_from_bytes, + pad_ethernet_frame_to_min_size, payload_from_beats, recv_frame, send_contiguous_frame, @@ -39,6 +48,9 @@ @cocotb.test() async def eth_mac_rx_import_test(dut): + phy_type = os.environ["PHY_TYPE_G"] + timeout_cycles = 512 if phy_type == "XGMII" else 4096 + bench = await setup_flat_emac_testbench( dut, source_prefix="sAxis", @@ -53,26 +65,93 @@ async def eth_mac_rx_import_test(dut): assert source is not None assert sink is not None - frame = build_ethernet_frame( + min_frame = build_ethernet_frame( dst_mac=0x020304050607, src_mac=0x0A0B0C0D0E0F, eth_type=0x88B5, payload=bytes(range(46)), ) - rx_pulse = cocotb.start_soon(wait_signal_pulse(dut.rxCountEn, clk=bench.clk)) - send_task = cocotb.start_soon( - send_contiguous_frame(source, frame_beats_from_bytes(frame), clk=bench.clk) + min_pulse = cocotb.start_soon(wait_signal_pulse(dut.rxCountEn, clk=bench.clk, timeout_cycles=timeout_cycles)) + min_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(min_frame), clk=bench.clk) + ) + min_observed = await recv_frame(sink, clk=bench.clk, timeout_cycles=timeout_cycles) + await min_send + await min_pulse + assert payload_from_beats(min_observed) == min_frame + assert int(dut.rxCrcError.value) == 0 + + # Drive a second, longer frame so the import path is checked across a + # multi-beat packet instead of only a minimum-sized transfer. + long_frame = build_ethernet_frame( + dst_mac=0x111213141516, + src_mac=0x212223242526, + eth_type=0x88B5, + payload=bytes(range(96)), + ) + long_pulse = cocotb.start_soon(wait_signal_pulse(dut.rxCountEn, clk=bench.clk, timeout_cycles=timeout_cycles)) + long_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(long_frame), clk=bench.clk) + ) + long_observed = await recv_frame(sink, clk=bench.clk, timeout_cycles=timeout_cycles) + await long_send + await long_pulse + assert payload_from_beats(long_observed) == long_frame + assert int(dut.rxCrcError.value) == 0 + + # A deasserted PHY-ready input resets the import logic, so traffic that + # arrives in that interval must not leak partial output while the link is + # down. The current XGMII path replays the blocked frame after recovery, + # whereas the GMII path discards it. + dut.phyReady.value = 0 + blocked_frame = build_ethernet_frame( + dst_mac=0x313233343536, + src_mac=0x414243444546, + eth_type=0x9000, + payload=bytes(range(32)), + ) + blocked_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(blocked_frame), clk=bench.clk) + ) + await blocked_send + await expect_no_output(sink, clk=bench.clk, cycles=(24 if phy_type == "XGMII" else 128)) + + dut.phyReady.value = 1 + await cycle(bench.clk, 4) + + recovery_frame = build_ethernet_frame( + dst_mac=0x515253545556, + src_mac=0x616263646566, + eth_type=0x88B5, + payload=b"link-recovery-frame" + bytes(27), + ) + recovery_pulse = cocotb.start_soon(wait_signal_pulse(dut.rxCountEn, clk=bench.clk, timeout_cycles=timeout_cycles)) + recovery_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(recovery_frame), clk=bench.clk) ) - observed_beats = await recv_frame(sink, clk=bench.clk) - await send_task - await rx_pulse + recovery_observed = await recv_frame(sink, clk=bench.clk, timeout_cycles=timeout_cycles) + await recovery_send + await recovery_pulse + + if phy_type == "XGMII": + # The XGMII export/import loopback retains the blocked frame across the + # ready transition, so the first recovered packet is the stalled one. + # Because that packet traverses the TX path, it comes back padded to + # Ethernet's minimum 60-byte frame size. + assert payload_from_beats(recovery_observed) == pad_ethernet_frame_to_min_size(blocked_frame) + drained_observed = await recv_frame(sink, clk=bench.clk, timeout_cycles=timeout_cycles) + assert payload_from_beats(drained_observed) == recovery_frame + else: + # The GMII path drops the blocked frame entirely, so the next output is + # the fresh recovery packet. + assert payload_from_beats(recovery_observed) == recovery_frame - assert payload_from_beats(observed_beats) == frame assert int(dut.rxCrcError.value) == 0 PARAMETER_SWEEP = [ parameter_case("xgmii_loopback", PHY_TYPE_G="XGMII"), + parameter_case("gmii_loopback", PHY_TYPE_G="GMII"), ] diff --git a/tests/ethernet/eth_mac/test_EthMacRxPause.py b/tests/ethernet/eth_mac/test_EthMacRxPause.py index 61e977decb..659900a075 100644 --- a/tests/ethernet/eth_mac/test_EthMacRxPause.py +++ b/tests/ethernet/eth_mac/test_EthMacRxPause.py @@ -9,14 +9,14 @@ ############################################################################## # Test methodology: -# - Sweep: Keep one pause-enabled configuration and cover the three observable -# behaviors of the block: normal pass-through, valid pause detection, and -# EOFE-terminated pause rejection. -# - Stimulus: Send one ordinary Ethernet frame, one standards-compliant pause -# frame, and one identical pause frame marked bad with `EOFE`. -# - Checks: Ordinary traffic must pass unchanged, valid pause traffic must be -# dropped while pulsing the pause request/value outputs, and bad pause -# traffic must be dropped without raising a pause request. +# - Sweep: Keep one pause-enabled configuration and cover normal pass-through, +# multiple valid pause requests, and EOFE-terminated pause rejection. +# - Stimulus: Send one ordinary Ethernet frame, then two valid pause frames +# with different quanta, and finally one invalid pause frame marked with +# `EOFE`. +# - Checks: Ordinary traffic must pass unchanged, each valid pause frame must +# be consumed internally while updating the pause value output, and the bad +# pause frame must not reassert the pause request. # - Timing: The output path has no backpressure, so the test launches each # frame continuously and watches the visible output beats directly. @@ -77,8 +77,21 @@ async def eth_mac_rx_pause_test(dut): assert int(dut.rxPauseValue.value) == pause_value await expect_no_output(sink, clk=bench.clk, cycles=8) + # A later valid pause frame should refresh the reported pause quanta rather + # than latching the first value permanently. + pause_value_2 = 0x0055 + pause_frame_2 = build_pause_frame(pause_value_2) + pause_send_2 = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(pause_frame_2), clk=bench.clk) + ) + await wait_signal_pulse(dut.rxPauseReq, clk=bench.clk) + await pause_send_2 + assert int(dut.rxPauseValue.value) == pause_value_2 + await expect_no_output(sink, clk=bench.clk, cycles=8) + # Mark the final beat bad so the pause decoder sees the same header but - # must suppress the resulting pause request. + # must suppress the resulting pause request even though the decoded value + # register may still reflect the bad frame contents. bad_pause_beats = frame_beats_from_bytes(build_pause_frame(0xBEEF), eofe=1) bad_pause_send = cocotb.start_soon(send_contiguous_frame(source, bad_pause_beats, clk=bench.clk)) for _ in range(16): diff --git a/tests/ethernet/eth_mac/test_EthMacTxCsum.py b/tests/ethernet/eth_mac/test_EthMacTxCsum.py index d2e6046d81..bb70ce4252 100644 --- a/tests/ethernet/eth_mac/test_EthMacTxCsum.py +++ b/tests/ethernet/eth_mac/test_EthMacTxCsum.py @@ -9,15 +9,18 @@ ############################################################################## # Test methodology: -# - Sweep: Keep one IPv4/UDP checksum-enabled loopback case where the TX repair -# block feeds the RX checker wrapper directly. -# - Stimulus: Send one IPv4/UDP packet with the IP and UDP checksum fields -# cleared to zero. -# - Checks: The emitted packet bytes must match the software-computed checksum- -# inserted frame, and the RX checker must report no terminal checksum errors. -# - Timing: The wrapper's internal RX checker absorbs the post-TX packet, so -# the bench waits for the visible checked output frame rather than assuming a -# fixed internal pipeline depth. +# - Sweep: Keep one TxCsum loopback instance but vary the runtime enable matrix +# to cover full repair, already-valid no-op behavior, and IP-only repair with +# UDP repair disabled. +# - Stimulus: Send one UDP frame with both checksums cleared, one already-valid +# UDP frame, and then one more zeroed-checksum frame after disabling UDP +# checksum insertion. +# - Checks: Full repair must insert both checksums, a valid packet must remain +# unchanged, and when UDP insertion is disabled the block must only repair +# the IPv4 header checksum while preserving the zero UDP checksum field. +# - Timing: The wrapper's internal RX checker consumes the repaired stream, so +# the bench waits on the post-checker frame rather than assuming a fixed +# internal pipeline delay. import cocotb import pytest @@ -88,6 +91,62 @@ async def eth_mac_tx_csum_test(dut): assert observed_beats[-1].udperr == 0 assert observed_beats[-1].eofe == 0 + # A packet that already carries correct checksums should emerge unchanged, + # which proves the repair path does not rewrite valid traffic unnecessarily. + valid_frame = build_ipv4_udp_frame( + dst_mac=0x010203040506, + src_mac=0x112233445566, + src_ip="10.1.0.1", + dst_ip="10.1.0.2", + src_port=0x1111, + dst_port=0x2222, + payload=b"already-valid-packet", + ) + valid_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(valid_frame), clk=bench.clk) + ) + valid_observed = await recv_frame(sink, clk=bench.clk) + await valid_send + assert payload_from_beats(valid_observed) == valid_frame + assert valid_observed[-1].iperr == 0 + assert valid_observed[-1].udperr == 0 + assert valid_observed[-1].eofe == 0 + + # Disable UDP insertion at runtime to prove the block can selectively + # repair only the IPv4 checksum while leaving the UDP checksum field alone. + dut.udpCsumEn.value = 0 + ip_only_repaired_frame = build_ipv4_udp_frame( + dst_mac=0x102030405060, + src_mac=0xA1A2A3A4A5A6, + src_ip="10.2.0.1", + dst_ip="10.2.0.2", + src_port=0x3003, + dst_port=0x4004, + payload=b"ip-only-repair-mode", + udp_checksum_override=0x0000, + ) + ip_only_input_frame = build_ipv4_udp_frame( + dst_mac=0x102030405060, + src_mac=0xA1A2A3A4A5A6, + src_ip="10.2.0.1", + dst_ip="10.2.0.2", + src_port=0x3003, + dst_port=0x4004, + payload=b"ip-only-repair-mode", + ip_checksum_override=0x0000, + udp_checksum_override=0x0000, + ) + ip_only_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(ip_only_input_frame), clk=bench.clk) + ) + ip_only_observed = await recv_frame(sink, clk=bench.clk) + await ip_only_send + + assert payload_from_beats(ip_only_observed) == ip_only_repaired_frame + assert ip_only_observed[-1].iperr == 0 + assert ip_only_observed[-1].udperr == 0 + assert ip_only_observed[-1].eofe == 0 + @pytest.mark.parametrize("parameters", [pytest.param({}, id="ipv4_udp_checksum_insert")]) def test_EthMacTxCsum(parameters): diff --git a/tests/ethernet/eth_mac/test_EthMacTxExport.py b/tests/ethernet/eth_mac/test_EthMacTxExport.py index 9f0321d5ef..29b96ee912 100644 --- a/tests/ethernet/eth_mac/test_EthMacTxExport.py +++ b/tests/ethernet/eth_mac/test_EthMacTxExport.py @@ -9,23 +9,32 @@ ############################################################################## # Test methodology: -# - Sweep: Keep one XGMII loopback case so the test proves the export path -# without mixing in additional PHY-family variables yet. -# - Stimulus: Send one minimum-size Ethernet frame into the shared export-to- -# import wrapper so the TX exporter has to build a real PHY stream. -# - Checks: The TX packet counter pulse must assert, the link/error status -# flags must stay low, and the recovered frame must still match the original. -# - Timing: The test relies on the wrapper's internal loopback to observe the -# exported packet through a clean end-to-end handshake path. +# - Sweep: Cover both supported functional PHY mappings, `GMII` and `XGMII`, +# and explicitly exercise the exporter with `phyReady` both high and low. +# - Stimulus: Send one minimum-size frame, one longer multi-beat frame, one +# frame while the link is marked not ready, and then one recovery frame after +# the link returns. +# - Checks: Successful transmissions must pulse `txCountEn`, the blocked frame +# must raise `txLinkNotReady` without producing output data while the link is +# down, and normal export behavior must recover cleanly after the ready +# signal is restored. The recovery expectation is PHY-specific because the +# current XGMII path drains the blocked frame after the link returns, while +# the GMII path drops it. +# - Timing: The receive timeout is scaled to the chosen PHY because the GMII +# path serializes one byte per clock while XGMII transmits eight. import cocotb +import os import pytest from tests.common.regression_utils import parameter_case, run_surf_vhdl_test from tests.ethernet.eth_mac.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, build_ethernet_frame, + cycle, + expect_no_output, frame_beats_from_bytes, + pad_ethernet_frame_to_min_size, payload_from_beats, recv_frame, send_contiguous_frame, @@ -39,6 +48,9 @@ @cocotb.test() async def eth_mac_tx_export_test(dut): + phy_type = os.environ["PHY_TYPE_G"] + timeout_cycles = 512 if phy_type == "XGMII" else 4096 + bench = await setup_flat_emac_testbench( dut, source_prefix="sAxis", @@ -53,27 +65,94 @@ async def eth_mac_tx_export_test(dut): assert source is not None assert sink is not None - frame = build_ethernet_frame( + min_frame = build_ethernet_frame( dst_mac=0x0C0D0E0F1011, src_mac=0x121314151617, eth_type=0x9000, payload=bytes(range(46)), ) - tx_pulse = cocotb.start_soon(wait_signal_pulse(dut.txCountEn, clk=bench.clk)) - send_task = cocotb.start_soon( - send_contiguous_frame(source, frame_beats_from_bytes(frame), clk=bench.clk) + min_pulse = cocotb.start_soon(wait_signal_pulse(dut.txCountEn, clk=bench.clk, timeout_cycles=timeout_cycles)) + min_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(min_frame), clk=bench.clk) + ) + min_observed = await recv_frame(sink, clk=bench.clk, timeout_cycles=timeout_cycles) + await min_send + await min_pulse + + assert payload_from_beats(min_observed) == min_frame + assert int(dut.txUnderRun.value) == 0 + assert int(dut.txLinkNotReady.value) == 0 + + long_frame = build_ethernet_frame( + dst_mac=0x202122232425, + src_mac=0x303132333435, + eth_type=0x88B5, + payload=bytes(range(96)), + ) + long_pulse = cocotb.start_soon(wait_signal_pulse(dut.txCountEn, clk=bench.clk, timeout_cycles=timeout_cycles)) + long_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(long_frame), clk=bench.clk) + ) + long_observed = await recv_frame(sink, clk=bench.clk, timeout_cycles=timeout_cycles) + await long_send + await long_pulse + assert payload_from_beats(long_observed) == long_frame + assert int(dut.txUnderRun.value) == 0 + + # When the PHY is not ready, the exporter must flag the condition and avoid + # emitting partial output while the link is down. The exact post-recovery + # behavior is PHY-specific and is checked below. + dut.phyReady.value = 0 + blocked_frame = build_ethernet_frame( + dst_mac=0x404142434445, + src_mac=0x505152535455, + eth_type=0x9000, + payload=bytes(range(32)), + ) + blocked_pulse = cocotb.start_soon(wait_signal_pulse(dut.txLinkNotReady, clk=bench.clk, timeout_cycles=timeout_cycles)) + blocked_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(blocked_frame), clk=bench.clk) ) - observed_beats = await recv_frame(sink, clk=bench.clk) - await send_task - await tx_pulse + await blocked_send + await blocked_pulse + await expect_no_output(sink, clk=bench.clk, cycles=(24 if phy_type == "XGMII" else 128)) + assert int(dut.txUnderRun.value) == 0 + + dut.phyReady.value = 1 + await cycle(bench.clk, 4) + + recovery_frame = build_ethernet_frame( + dst_mac=0x606162636465, + src_mac=0x707172737475, + eth_type=0x88B5, + payload=b"post-link-recovery" + bytes(28), + ) + recovery_pulse = cocotb.start_soon(wait_signal_pulse(dut.txCountEn, clk=bench.clk, timeout_cycles=timeout_cycles)) + recovery_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(recovery_frame), clk=bench.clk) + ) + recovery_observed = await recv_frame(sink, clk=bench.clk, timeout_cycles=timeout_cycles) + await recovery_send + await recovery_pulse + + if phy_type == "XGMII": + # In the XGMII path the held-off frame drains first once the link + # returns, so the recovery frame arrives second. The stalled frame is + # padded by the TX path up to Ethernet's minimum non-FCS size. + assert payload_from_beats(recovery_observed) == pad_ethernet_frame_to_min_size(blocked_frame) + drained_observed = await recv_frame(sink, clk=bench.clk, timeout_cycles=timeout_cycles) + assert payload_from_beats(drained_observed) == recovery_frame + else: + # GMII drops the frame that arrived while the link was down. + assert payload_from_beats(recovery_observed) == recovery_frame - assert payload_from_beats(observed_beats) == frame assert int(dut.txUnderRun.value) == 0 assert int(dut.txLinkNotReady.value) == 0 PARAMETER_SWEEP = [ parameter_case("xgmii_loopback", PHY_TYPE_G="XGMII"), + parameter_case("gmii_loopback", PHY_TYPE_G="GMII"), ] diff --git a/tests/ethernet/eth_mac/test_EthMacTxPause.py b/tests/ethernet/eth_mac/test_EthMacTxPause.py index 97606f0069..60e3265aa9 100644 --- a/tests/ethernet/eth_mac/test_EthMacTxPause.py +++ b/tests/ethernet/eth_mac/test_EthMacTxPause.py @@ -9,15 +9,18 @@ ############################################################################## # Test methodology: -# - Sweep: Use one pause-enabled instance with a short pause quanta setting so -# the bench focuses on the visible transmit behavior instead of long waits. -# - Stimulus: Pulse `clientPause` while the link is ready, then send one normal -# frame after the generated pause frame has completed. -# - Checks: The emitted pause frame bytes must match the documented Ethernet -# MAC-control format, `pauseTx` must pulse once, and ordinary client traffic -# must still pass through unchanged when no pause frame is being emitted. -# - Timing: The sink uses explicit `TREADY` handshakes so the four-beat pause -# frame and the later pass-through frame are both consumed deliberately. +# - Sweep: Use one pause-enabled instance with a short pause quanta so the test +# can cover local pause generation, remote-pause gating, and runtime pause +# disable behavior in a single run. +# - Stimulus: Trigger a local pause-frame transmission, send a normal payload, +# inject a received pause request before another payload, and finally pulse +# `clientPause` again after disabling pause generation. +# - Checks: Local pause generation must emit the standards-compliant pause +# frame, received pause must delay client traffic before it is forwarded, and +# `pauseEnable=0` must suppress pause generation even when `clientPause` is +# asserted. +# - Timing: The sink uses explicit `TREADY` handshakes so pause frames, gated +# payload frames, and pass-through traffic are all observed deliberately. import cocotb import pytest @@ -28,6 +31,7 @@ build_ethernet_frame, build_pause_frame, cycle, + expect_no_output, frame_beats_from_bytes, payload_from_beats, recv_frame, @@ -87,6 +91,43 @@ async def eth_mac_tx_pause_test(dut): await payload_send assert payload_from_beats(observed_frame) == payload_frame + # A received pause request should gate the next payload frame for a short + # interval before normal forwarding resumes. + dut.rxPauseValue.value = 2 + dut.rxPauseReq.value = 1 + await cycle(bench.clk, 1) + dut.rxPauseReq.value = 0 + + gated_frame = build_ethernet_frame( + dst_mac=0x111213141516, + src_mac=0x1718191A1B1C, + eth_type=0x88B5, + payload=bytes(range(46)), + ) + gated_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(gated_frame), clk=bench.clk) + ) + await expect_no_output(sink, clk=bench.clk, cycles=4) + gated_observed = await recv_frame( + sink, + clk=bench.clk, + ready_signal=dut.mAxisTReady, + timeout_cycles=128, + ) + await gated_send + assert payload_from_beats(gated_observed) == gated_frame + + # Disabling pause generation at runtime should suppress the pause frame + # even if software still asserts the local pause request input. + dut.pauseEnable.value = 0 + dut.clientPause.value = 1 + await cycle(bench.clk, 1) + dut.clientPause.value = 0 + for _ in range(8): + await cycle(bench.clk, 1) + assert int(dut.pauseTx.value) == 0 + assert int(dut.mAxisTValid.value) == 0 + PARAMETER_SWEEP = [ parameter_case("pause_generator", PAUSE_512BITS_G="1"), From dd8b67893e7f19b4e9929822472840e1b09d9e7b Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 10 Apr 2026 20:18:33 -0700 Subject: [PATCH 06/92] Add more EthMac tests. --- docs/_meta/rtl_regression_handoff.md | 15 +++- docs/_meta/rtl_regression_progress.md | 17 +++- .../ethernet/eth_mac/test_EthCrc32Parallel.py | 24 ++--- tests/ethernet/eth_mac/test_EthMacRxFilter.py | 88 +++++++++++++++---- tests/ethernet/eth_mac/test_EthMacRxShift.py | 81 +++++++++++++---- tests/ethernet/eth_mac/test_EthMacTxShift.py | 77 ++++++++++++---- 6 files changed, 237 insertions(+), 65 deletions(-) diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index 2cbf63854e..6460e985e8 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -18,7 +18,7 @@ - Treat VHDL packages as transitively covered unless a behavioral function/procedure needs a dedicated wrapper ## Quick Resume Snapshot -- Current frontier: the axi-first pass is complete through the previously remaining final 11 `axi/` modules, and `dsp/` is now included in the generated phase-1 queue so DSP rollout can proceed on the normal tracked path. `ethernet` and `protocols` are still temporarily deferred in `docs/_meta/rtl_phase1_queue_overrides.json`, but DSP work no longer depends on unwinding those deferrals first. +- Current frontier: the axi-first pass is complete through the previously remaining final 11 `axi/` modules, `dsp/` is now included in the generated phase-1 queue, and a manual first-wave `ethernet/EthMacCore` slice is now also validated under `tests/ethernet/eth_mac/`. `ethernet` and `protocols` still remain temporarily deferred in `docs/_meta/rtl_phase1_queue_overrides.json`, so the generated queue is intentionally behind the manually advanced Ethernet work. - Current axi frontier: complete for the intended simulator-friendly pass in this branch snapshot; do not resume from the older stale `AxiResize` note. - Current validated-open issues: - None currently recorded on this merged branch. `AxiResize` and `AxiStreamDmaV2Read` are both fixed here; queue regeneration is the next step. @@ -26,6 +26,7 @@ - Keep `dsp/` in the generated queue scope. Do not track DSP rollout in a separate hand-maintained list. - The planned `dsp/generic/fixed` leaf set is now validated: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. - The later cross-subsystem cleanup still includes removing the temporary `ethernet` and `protocols` subsystem deferrals from `docs/_meta/rtl_phase1_queue_overrides.json` and regenerating `docs/_meta/rtl_phase1_queue.{md,json}` when that broader transition is actually taken. + - Until that happens, do not treat the generated queue artifacts as evidence that `ethernet` is untouched; the manually selected `EthMacCore` slice is already implemented and passing even though the queue inputs still defer the subsystem. - Do not hand-maintain queue order in the plan or handoff docs. - Current wrapper discipline: - Prefer the existing subsystem `ip_integrator/` shim layers over bespoke record flattening. @@ -33,6 +34,7 @@ - Use `start_lockstep_clocks()` when a DUT depends on truly shared clock edges. - Prefer explicit short sim-build keys for generated-wrapper benches when case metadata would otherwise create fragile build paths. - When a wrapper is checked in, write it like the surrounding repo HDL: include the SLAC/SURF banner and enough section comments that a new session can identify the shim, DUT, and flattening regions quickly. + - For `ethernet/EthMacCore`, the checked-in wrappers under `ethernet/EthMacCore/wrappers/` are now the expected cocotb surface. Keep using those flat EMAC beat wrappers rather than rebuilding record-packing logic in Python. - Current cocotb-file discipline: - New test files should start with the standard SURF/SLAC header block. - The `Test methodology` block belongs directly under that header. @@ -52,9 +54,14 @@ - For first-pass wrapper benches, prove the externally visible stable path first and defer shakier simulator-sensitive branches explicitly in the docs instead of stretching one bench to cover everything. - `AxiStreamDmaV2Read` needed a real RTL/runtime fix rather than a bench workaround: keep the bounded byte-count conversion fix in `axi/axi4/rtl/AxiPkg.vhd` and the direct terminal-mask generation in `axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd`. The current wrapper only exposes an 8-bit `TUSER`, so the observable contract in the checked-in bench is first-user propagation plus payload/keep/id/dest and descriptor return fields. - `tests/dsp/generic/dsp_test_utils.py` is now the shared home for DSP-specific signed helpers, rolling reference models, cocotb clock-settle timing, and generated FIR wrappers. Reuse it instead of cloning DSP arithmetic or wrapper boilerplate. +- `tests/ethernet/eth_mac/ethmac_test_utils.py` is now the shared home for the current Ethernet MAC slice: flat EMAC beat helpers, Ethernet/IPv4/UDP packet builders, checksum reference code, MAC-config byte-order helpers, and minimum-frame padding helpers. Reuse it instead of cloning packet or sideband plumbing across `EthMacCore` benches. +- The current `EthMacCore` slice is intentionally a checked-in-wrapper-first rollout, not a cocotb-generated-wrapper experiment. Keep new Ethernet work on that same pattern unless the simulator forces a very local generic adapter. +- The XGMII import/export loopback behavior differs from the GMII path when `phyReady` drops mid-traffic: the blocked frame is retained and drains after link recovery, padded to Ethernet's minimum frame size if it was short. The GMII path drops that blocked frame. Future import/export coverage should preserve that distinction instead of forcing one common expectation. +- `EthMacRxCsum` reliably raises `IPERR` on a bad IPv4 header checksum, but the checked-in wrapper contract does not currently require `EOFE` for that case. Keep the negative test aligned to the real observable contract rather than to a stronger assumption. +- The RX/TX shift benches need a small idle-plus-settle gap before changing runtime shift controls because the underlying `AxiStreamShift` samples those controls while idle. Preserve that guardrail if those benches are refactored or expanded. ## Current Status -Planning is complete enough to start implementation. The agreed direction is a Python-only executable regression framework with tiered `smoke` and `functional` coverage. Existing VHDL TBs are reference material only and should be rewritten in Python when migrated, unless a thin wrapper is still useful for cocotb access. +Planning is complete and implementation is well underway. The agreed direction is a Python-only executable regression framework with tiered `smoke` and `functional` coverage. Existing VHDL TBs are reference material only and should be rewritten in Python when migrated, unless a thin wrapper is still useful for cocotb access. The repo now has the initial handoff artifacts, a checked-in inventory scaffold at `docs/_meta/rtl_regression_inventory.yaml`, and local bootstrap helpers in `scripts/setup_regression_env.sh` plus `.vscode/tasks.json`. The first pilot modules were `FifoAsync`, `AxiStreamFifoV2`, and `AxiLiteAsync`, and the work has since moved into a graph-guided bottom-up rollout across `base/`. @@ -78,6 +85,8 @@ The project now also has a shared helper path in `tests/common/regression_utils. `tests/common/regression_utils.py` now also includes `start_lockstep_clocks()` for DUTs whose generics assume truly common clocks in both ports. Use that helper instead of launching two same-period clocks independently when the RTL assumes shared edge identity. +The first manual `ethernet/EthMacCore` wave is now also in place. The checked-in Ethernet MAC benches under `tests/ethernet/eth_mac/` cover `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`, and the current directory-level regression passes locally with `32 passed`. The current Ethernet wrappers live under `ethernet/EthMacCore/wrappers/` and should be treated as the stable cocotb-facing surfaces for deeper `EthMacCore` work. + The wrapper coverage policy is now more explicit in practice: test the wrapper-specific behavior, not the full leaf matrix again. `Fifo` validated both inferred sync/async selection branches, `FifoCascade` validated public stage-vector mapping plus a curated output smoke, and `FifoMux` is currently validated only on the stable split-to-narrow path. The pack-to-wide `FifoMux` path should be treated as still open rather than silently assumed covered. That same wrapper-policy lesson now applies to the late `base/sync` wrappers as well. `SyncClockFreq` is stable with a checked-in subsystem wrapper, but its common-clock measurement quantizes one count above the abstract target under the current GHDL flow, so the regression checks a bounded expected range rather than an exact integer. `SyncTrigRate` is intentionally covered as a wrapper/integration bench only: it proves aligned update publication, denser-window rate growth, reset-path liveness, and strobe pulse behavior, while exact min/max pipeline semantics remain the responsibility of the dedicated `SyncMinMax` leaf test. @@ -133,7 +142,7 @@ One small RTL fix landed during that validation pass because the new `AxiStreamD A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instantiation_graph.md` and `docs/_meta/rtl_instantiation_graph.json`, and the same generator now also emits a path-qualified bottom-up phase-1 queue at `docs/_meta/rtl_phase1_queue.md` and `docs/_meta/rtl_phase1_queue.json`. Keep the graph for provenance, but treat the generated queue as the default source of truth for what to implement next. Manual phase-1 deferrals and order exceptions belong in `docs/_meta/rtl_phase1_queue_overrides.json`, not as hand-edited ordering in the plan doc. ## Immediate Next Task -Choose the next broader phase-1 target from the generated queue now that the planned `dsp/generic/fixed` leaf batch is complete. Keep using the old VHDL benches under `dsp/generic/tb/` only as behavioral reference material if another DSP-adjacent wrapper or integration target is taken later. +Choose whether the next manual branch step stays in `ethernet/EthMacCore` or returns to another non-deferred subsystem. If staying in Ethernet, the most natural follow-on is the MAC assembly layer (`EthMacRx`, `EthMacTx`, `EthMacRxFifo`, `EthMacTxFifo`) or a move into the IPv4 / Raw Ethernet stack using the now-established `ethmac_test_utils.py` helper and checked-in wrapper pattern. If switching back to queue-driven work, remove the temporary subsystem deferrals and regenerate `docs/_meta/rtl_phase1_queue.{md,json}` first so the queue is authoritative again. ## Read Order 1. `docs/_meta/rtl_regression_handoff.md` diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 10b3c1e7a4..4ae9cd6b56 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -2,9 +2,9 @@ ## Summary - Current phase: Phase-1 implementation active -- Current subsystem: `protocols/pgp` -- Current focus module: `protocols/pgp/shared/*` VC FIFO coverage is now done; the next likely follow-on is deeper `pgp2b` / `pgp2fc` work or another non-deferred protocol area. `pgp3` is intentionally deferred for now. -- Last updated: 2026-04-08 +- Current subsystem: `ethernet/EthMacCore` +- Current focus module: the first manual `ethernet/EthMacCore` wave is now in place under `tests/ethernet/eth_mac/`, covering `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`, with the main follow-on choices now being deeper `EthMacRx` / `EthMacTx` / FIFO assembly work or a move into the IPv4 / Raw Ethernet stack. +- Last updated: 2026-04-10 ## Current Frontier Snapshot - Next queue target: broader phase-1 queue refresh needed after the completed `dsp/generic/fixed` leaf batch @@ -13,12 +13,14 @@ - The queue snapshot in earlier notes that still pointed at `AxiReadEmulate` / `AxiResize` is now stale and should not be reused. - `dsp/` had been missing from the generated queue scope. The queue generator now includes it so DSP rollout can stay on the normal bottom-up path instead of living as an ad hoc side list. - The broader post-axi transition should still make the queue authoritative again by removing the temporary subsystem deferrals and regenerating it before taking the next non-deferred cross-subsystem module. + - While `ethernet` remains deferred in the generated queue inputs, the manually selected `EthMacCore` slice is no longer unstarted on this branch; do not reuse the older docs wording that treated the whole subsystem as untouched. - `protocols/pgp/pgp3/` is now an explicit local defer in `rtl_phase1_queue_overrides.json`; do not treat it as the default next family breadth target on this branch. - Known expected-open tests on this branch: - None currently recorded. `AxiResize` and `AxiStreamDmaV2Read` both pass on this merged branch. - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. + - For `ethernet/EthMacCore`, keep using the checked-in wrappers under `ethernet/EthMacCore/wrappers/` plus the shared helper layer in `tests/ethernet/eth_mac/ethmac_test_utils.py`. The practical first-pass shape is a flat EMAC beat wrapper with explicit sideband bits, curated PHY/runtime sweeps instead of exhaustive `PHY_TYPE_G` coverage, and helper-side handling for wire-level quirks such as minimum-frame padding and MAC-config byte order. ## Status | Subsystem | Inventory | Smoke | Functional | Notes | @@ -28,7 +30,7 @@ | `dsp` | started | not started | started | The planned `dsp/generic/fixed` leaf batch is now validated under `tests/dsp/generic/`: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. Shared DSP helpers now live in `tests/dsp/generic/dsp_test_utils.py`, and the legacy VHDL benches under `dsp/generic/tb/` were treated as behavioral reference material rather than as execution constraints. | | `axi` | started | not started | started | The axi-first pass is now complete for the simulator-friendly queue. The final locally validated batch adds `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`, with a combined `11 passed` validation run on 2026-03-27. Added checked-in subsystem wrappers under `axi/axi4/ip_integrator/`, `axi/axi-lite/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/` for those benches. `AxiStreamFifoV2` now has an expanded `10 passed` wrapper regression under `tests/axi/axi_stream/` covering async and sync width conversion, metadata truncation, `VALID_THOLD` frame-ready and burst-release modes, dynamic pause-threshold behavior, `CASCADE_SIZE=2`, and the `S_HAS_TREADY=0` pause-only source-side path. `AxiResize` now passes its equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` wrapper regression on this branch after the read-hold RTL fix. `AxiLiteAsync`, `AxiLiteToDrp`, and `AxiRateGen` still keep intentionally narrow common-clock subsets while the more timing-sensitive async AXI-Lite crossing branches remain open. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` still keep intentionally narrow first-pass subsets. `AxiStreamDmaV2Read` is now validated with a two-case wrapper regression covering both aligned and short terminal-beat reads after fixing bounded byte-count conversion in `AxiPkg` and terminal-mask generation in `AxiStreamDmaV2Read`. | | `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. | -| `ethernet` | not started | not started | not started | Temporarily deferred during the current axi-first rollout pass | +| `ethernet` | started | not started | started | `tests/ethernet/eth_mac/` now covers a first manual `EthMacCore` slice: `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`, with the deeper filter/shift/CRC corner expansions also in place. The generated queue still keeps the broader subsystem deferred until the post-axi refresh removes the temporary queue override. | | `devices` | not started | not started | not started | Many vendor-heavy cases | | `xilinx` | not started | not started | not started | Many vendor-heavy cases | @@ -74,6 +76,10 @@ - Validated `tests/base/fifo/test_FifoAsync.py` locally with `./.venv/bin/python -m pytest -v tests/base/fifo/test_FifoAsync.py`. - Reorganized new regressions into subsystem packages under `tests/` and moved shared helpers to `tests/common/`. - Added `tests/README.md` to document the regression layout policy. +- Added the shared Ethernet MAC helper layer in `tests/ethernet/eth_mac/ethmac_test_utils.py`, including packet builders, checksum helpers, MAC-config byte-order handling, flat EMAC beat helpers, and Ethernet minimum-frame padding support for the import/export loopback benches. +- Added checked-in cocotb-facing wrappers under `ethernet/EthMacCore/wrappers/` for the first `EthMacCore` wave, including loopback wrappers for import/export and top-level tests plus flat wrappers for the checksum, pause, filter, and shift leaves. +- Implemented and validated the first `ethernet/EthMacCore` functional wave under `tests/ethernet/eth_mac/`: `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`. +- Expanded the first `EthMacCore` wave beyond the initial happy paths: `EthMacTop` now covers filter/backpressure/checksum/pause interactions, `EthMacRxImport` and `EthMacTxExport` now cover both GMII and XGMII plus link-not-ready recovery behavior, the RX/TX checksum benches now include negative and partial-repair cases, `EthMacRxFilter` now covers multicast/broadcast/filter-disable/multi-beat-drop behavior, the RX/TX shift benches now cover runtime shift changes and control-bit propagation, and `EthCrc32Parallel` now sweeps all byte widths `1..16`. - Ran a quick HDL coverage spike against the local Homebrew `ghdl` build and confirmed it does not expose `--coverage` or a `coverage` subcommand. - Migrated `AxiStreamFifoV2` into `tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py` and validated the current 10-case sweep locally. - Expanded `tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py` into a broader 10-case `AxiStreamFifoV2` regression covering thresholded release modes, metadata truncation, multi-stage cascade buffering, and the `S_HAS_TREADY=0` pause-only path, and validated it locally with `10 passed`. @@ -211,6 +217,7 @@ - `AxiStreamDmaV2Read` is stable with a thin IP-integrator wrapper once the read-path byte-count conversions stay bounded to the burst-size window. The checked-in bench proves both aligned and short terminal-beat reads; because the wrapper exports only an 8-bit `TUSER`, the observable contract is first-user propagation rather than separate first/last byte tagging. - The `axi/dma/rtl/v2/` benches are now intentionally split by behavior instead of repeatedly re-proving the same path through the top-level DMA stack: `AxiStreamDmaV2` and `AxiStreamDmaV2Desc` stay focused on descriptor-manager register/control surfaces, `AxiStreamDmaV2Read` owns aligned and short terminal-beat readout, `AxiStreamDmaV2Write` owns descriptor-return integrity plus burst splitting, `AxiStreamDmaV2WriteMux` owns arbitration ordering, and `AxiStreamDmaV2Fifo` owns the integrated FIFO register/count/pause-threshold surface. - For checked-in VHDL changes, use the repo virtualenv's `vsg` with `vsg-linter.yml` so local lint matches CI, and prefer `--fix` before manual spacing/alignment cleanup. +- The current `EthMacCore` wave has a few wrapper-visible behavior details worth preserving in the docs instead of rediscovering later: the XGMII import/export loopback retains a frame presented during `phyReady=0` and drains it after link recovery with Ethernet minimum-size padding applied, while the GMII path drops it; `EthMacRxCsum` reliably asserts `IPERR` on a bad IPv4 header checksum but the checked-in wrapper contract does not require `EOFE` on that case; and the RX/TX shift benches need a small idle-plus-settle gap before changing runtime shift controls because the underlying `AxiStreamShift` samples those controls from its IDLE state. ## Log - 2026-03-20: Agreed on Python-only executable regression logic and wrapper-only VHDL retention. @@ -239,6 +246,8 @@ - 2026-04-06: Completed the remaining manual `protocols/ssi` leaf batch. Added checked-in wrappers `protocols/ssi/wrappers/SsiCmdMasterPulserWrapper.vhd`, `protocols/ssi/wrappers/SsiCmdMasterWrapper.vhd`, `protocols/ssi/wrappers/SsiFrameLimiterWrapper.vhd`, `protocols/ssi/wrappers/SsiIncrementingTxWrapper.vhd`, `protocols/ssi/wrappers/SsiAxiLiteMasterWrapper.vhd`, and `protocols/ssi/wrappers/SsiDbgTapWrapper.vhd`; added `tests/protocols/ssi/test_SsiCmdMasterPulser.py`, `tests/protocols/ssi/test_SsiCmdMaster.py`, `tests/protocols/ssi/test_SsiFrameLimiter.py`, `tests/protocols/ssi/test_SsiIncrementingTx.py`, `tests/protocols/ssi/test_SsiAxiLiteMaster.py`, and `tests/protocols/ssi/test_SsiDbgTap.py`; extended `tests/protocols/ssi/ssi_test_utils.py` with optional `TID` handling plus shared frame-receive helpers; validated the new six-test batch locally with `6 passed`; and kept wrapper lint clean under `vsg --fix -c vsg-linter.yml -f` plus a clean follow-up lint pass. The current scope is intentionally uneven: `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiIncrementingTx`, and `SsiAxiLiteMaster` have functional first-pass checks, `SsiFrameLimiter` is currently a narrowed single-beat/missing-SOF subset, and `SsiDbgTap` is traffic smoke only because the RTL exposes no externally visible state. - 2026-04-07: Tightened the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` so flat SSI sources wait for a real handshake edge and shared frame receivers capture accepted handshakes instead of inferring contiguous traffic from post-send snapshots. Revalidated the existing SSI slice locally with `19 passed`. A focused follow-up on `SsiIbFrameFilter` and `SsiFifo` showed the earlier apparent 3-beat middle-word loss was a bench observation bug rather than an RTL bug, after which the checked-in `SsiFifo` regression added a real contiguous 3-beat pass-through assertion and the `SsiAxiLiteMaster` / `SsiIncrementingTx` benches were updated to assert the full emitted frame shapes. - 2026-04-07: Expanded `tests/protocols/ssi/test_SsiFifo.py` beyond the earlier single-beat subset. The checked-in FIFO bench now proves contiguous 3-beat frame preservation on the default, `VALID_THOLD_G=0`, and `VALID_THOLD_G=2` wrapper paths; exercises repeated-`SOF` malformed-frame handling across the buffered modes; and keeps the existing missing-`SOF` drop plus `SLAVE_READY_EN_G=false` overflow checks. The buffered malformed-frame result is mode-specific at the wrapper boundary: `VALID_THOLD_G=0` drops the malformed repeated-`SOF` frame outright, while `VALID_THOLD_G=2` emits the expected two-beat terminated `EOFE` frame. A follow-up backpressure pass also added explicit drain-side ready toggling on a good 5-beat frame, malformed termination under toggled ready, and thresholded release under intermittent drain stalls so SSI frame policy is now checked under nontrivial sink backpressure without duplicating the full `AxiStreamFifoV2` transport matrix. Revalidated the full touched SSI slice locally with `19 passed`. +- 2026-04-10: Landed the first manual `ethernet/EthMacCore` bench wave under `tests/ethernet/eth_mac/`, added the required checked-in wrappers under `ethernet/EthMacCore/wrappers/`, and validated the baseline 12-module slice covering `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`. +- 2026-04-10: Expanded that same `EthMacCore` slice beyond the initial happy paths. The checked-in Ethernet MAC suite now covers `EthMacTop` filter/backpressure/checksum/pause interactions, GMII and XGMII import/export plus link-not-ready recovery behavior, checksum negative cases, filter multicast/broadcast/filter-disable/multi-beat-drop behavior, shift runtime-control and control-bit propagation edges, and full byte-width `1..16` logic-path coverage for `EthCrc32Parallel`. The full `tests/ethernet/eth_mac` directory currently passes locally with `32 passed`. - 2026-03-20: Added an explicit project rule to comment new Python regression code where intent or runner behavior is not self-evident. - 2026-03-20: Expanded `FifoAsync` to a validated 12-case parameter matrix and enabled default pytest xdist parallelization with `pytest.ini`. - 2026-03-20: Added package-coverage policy: packages are covered transitively unless a behavioral helper warrants a dedicated wrapper test. diff --git a/tests/ethernet/eth_mac/test_EthCrc32Parallel.py b/tests/ethernet/eth_mac/test_EthCrc32Parallel.py index 0c2e2545d8..c80cfef4ec 100644 --- a/tests/ethernet/eth_mac/test_EthCrc32Parallel.py +++ b/tests/ethernet/eth_mac/test_EthCrc32Parallel.py @@ -9,13 +9,14 @@ ############################################################################## # Test methodology: -# - Sweep: Cover a smaller and larger byte-lane configuration so the Ethernet- -# specific CRC wrapper logic proves both narrow and full-width paths. -# - Stimulus: Present deterministic byte groups, leave the block idle for one -# cycle to prove hold behavior, and then assert the CRC reset input. -# - Checks: Each emitted CRC must match the software Ethernet CRC fold over the -# same byte sequence, the CRC must hold during idle cycles, and reset must -# restore the all-ones seed presentation. +# - Sweep: Cover every supported byte width from 1 through 16 with the logic +# implementation. +# - Stimulus: Present a short transaction, a small partial-width transaction, +# and two chained wider transactions before checking idle hold and reset. +# - Checks: Every emitted CRC must match the software Ethernet CRC fold over +# the same byte stream, chained transactions must continue the prior +# remainder, the CRC must hold during idle cycles, and reset must restore the +# all-ones seed presentation. # - Timing: `EthCrc32Parallel` consumes the presented word on one clock and # updates the internal remainder on the next, so each transaction waits for # that two-cycle cadence explicitly. @@ -77,8 +78,9 @@ async def eth_crc32_parallel_test(dut): payloads = [ [0x12], - [0x34, 0x56, 0x78][: min(byte_width, 3)], - list(range(0x90, 0x90 + min(byte_width, 6))), + list(range(0x30, 0x30 + min(byte_width, 2))), + list(range(0x50, 0x50 + byte_width)), + list(range(0x90, 0x90 + byte_width)), ] for payload in payloads: @@ -100,8 +102,7 @@ async def eth_crc32_parallel_test(dut): PARAMETER_SWEEP = [ - parameter_case("byte4", BYTE_WIDTH_G="4", USE_DSP_G="false"), - parameter_case("byte16", BYTE_WIDTH_G="16", USE_DSP_G="false"), + *[parameter_case(f"byte{byte_width}", BYTE_WIDTH_G=str(byte_width), USE_DSP_G="false") for byte_width in range(1, 17)], ] @@ -113,4 +114,5 @@ def test_EthCrc32Parallel(parameters): parameters=hdl_parameters_from(parameters), extra_env=parameters, extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES}, + sim_build_key="tests/sim_build/ethernet/eth_mac/test_EthCrc32Parallel.shared", ) diff --git a/tests/ethernet/eth_mac/test_EthMacRxFilter.py b/tests/ethernet/eth_mac/test_EthMacRxFilter.py index 6d03fc0c71..ec328a92d9 100644 --- a/tests/ethernet/eth_mac/test_EthMacRxFilter.py +++ b/tests/ethernet/eth_mac/test_EthMacRxFilter.py @@ -9,13 +9,15 @@ ############################################################################## # Test methodology: -# - Sweep: Keep filtering enabled and exercise the three key externally visible -# decisions: accept local traffic, drop foreign unicast, and drop on pause. -# - Stimulus: Send one frame addressed to the configured local MAC, one frame -# addressed elsewhere, and one local frame while the downstream pause flag is -# asserted. -# - Checks: Local traffic must pass unchanged, foreign traffic must disappear, -# and the pause-driven drop path must suppress output even for a local frame. +# - Sweep: Keep filtering enabled in the wrapper and exercise all externally +# visible runtime decisions: local pass, multicast pass, broadcast pass, +# foreign-unicast drop, `filtEnable=0` bypass, and pause-driven drop. +# - Stimulus: Send both short and multi-beat frames, including a dropped +# foreign unicast packet that is long enough to cross beat boundaries. +# - Checks: Accepted traffic must emerge byte-exact, dropped traffic must never +# assert output valid, disabling filtering must pass a foreign unicast frame, +# and a good frame sent after a dropped multi-beat packet must not inherit any +# stale `TVALID` or payload from the discarded traffic. # - Timing: The block has no output backpressure, so each frame is launched # continuously and the sink watches for visible output rather than handshakes. @@ -26,6 +28,7 @@ from tests.ethernet.eth_mac.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, build_ethernet_frame, + mac_config_word_from_wire, expect_no_output, frame_beats_from_bytes, payload_from_beats, @@ -41,10 +44,6 @@ @cocotb.test() async def eth_mac_rx_filter_test(dut): local_mac_wire = 0x001122334455 - # EthMacPkg stores MAC addresses in the same little-endian byte order used - # by the flattened EMAC data word, so the configured register image is the - # reverse of the human-readable wire-order MAC address. - local_mac_reg = 0x554433221100 bench = await setup_flat_emac_testbench( dut, source_prefix="sAxis", @@ -52,7 +51,7 @@ async def eth_mac_rx_filter_test(dut): initial_values={ "mAxisPause": 0, "dropOnPause": 0, - "macAddress": local_mac_reg, + "macAddress": mac_config_word_from_wire(local_mac_wire), "filtEnable": 1, }, ) @@ -61,11 +60,13 @@ async def eth_mac_rx_filter_test(dut): assert source is not None assert sink is not None + # Start with a multi-beat local-unicast frame so the pass path is checked + # across the internal PASS state instead of only a one-beat decision. local_frame = build_ethernet_frame( dst_mac=local_mac_wire, src_mac=0x0A0B0C0D0E0F, eth_type=0x88B5, - payload=bytes(range(18)), + payload=bytes(range(48)), ) local_send = cocotb.start_soon( send_contiguous_frame(source, frame_beats_from_bytes(local_frame), clk=bench.clk) @@ -74,14 +75,71 @@ async def eth_mac_rx_filter_test(dut): await local_send assert payload_from_beats(local_observed) == local_frame + multicast_frame = build_ethernet_frame( + dst_mac=0x01005E000001, + src_mac=0x0A0B0C0D0E0F, + eth_type=0x88B5, + payload=b"multicast-pass-frame", + ) + multicast_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(multicast_frame), clk=bench.clk) + ) + multicast_observed = await recv_frame(sink, clk=bench.clk) + await multicast_send + assert payload_from_beats(multicast_observed) == multicast_frame + + broadcast_frame = build_ethernet_frame( + dst_mac=0xFFFFFFFFFFFF, + src_mac=0x0A0B0C0D0E0F, + eth_type=0x88B5, + payload=b"broadcast-pass-frame" + bytes(range(24)), + ) + broadcast_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(broadcast_frame), clk=bench.clk) + ) + broadcast_observed = await recv_frame(sink, clk=bench.clk) + await broadcast_send + assert payload_from_beats(broadcast_observed) == broadcast_frame + foreign_frame = build_ethernet_frame( dst_mac=0x00AA00BB00CC, src_mac=0x0A0B0C0D0E0F, eth_type=0x88B5, - payload=b"foreign-unicast-drop", + payload=bytes(range(64)), ) await send_contiguous_frame(source, frame_beats_from_bytes(foreign_frame), clk=bench.clk) - await expect_no_output(sink, clk=bench.clk, cycles=8) + await expect_no_output(sink, clk=bench.clk, cycles=16) + + # After dropping a multi-beat frame the output must stay idle until a fresh + # accepted packet arrives; otherwise stale state would leak into the next + # frame. + post_drop_frame = build_ethernet_frame( + dst_mac=0xFFFFFFFFFFFF, + src_mac=0x0A0B0C0D0E0F, + eth_type=0x88B5, + payload=b"post-drop-idle-check" + bytes(20), + ) + post_drop_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(post_drop_frame), clk=bench.clk) + ) + post_drop_observed = await recv_frame(sink, clk=bench.clk) + await post_drop_send + assert payload_from_beats(post_drop_observed) == post_drop_frame + + dut.filtEnable.value = 0 + filt_bypass_frame = build_ethernet_frame( + dst_mac=0x00AA00BB00CC, + src_mac=0x0A0B0C0D0E0F, + eth_type=0x9000, + payload=b"filter-disabled-foreign-pass" + bytes(18), + ) + filt_bypass_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(filt_bypass_frame), clk=bench.clk) + ) + filt_bypass_observed = await recv_frame(sink, clk=bench.clk) + await filt_bypass_send + assert payload_from_beats(filt_bypass_observed) == filt_bypass_frame + dut.filtEnable.value = 1 # The downstream pause indication is a separate control surface, so this # check proves the block can suppress even a local destination frame. diff --git a/tests/ethernet/eth_mac/test_EthMacRxShift.py b/tests/ethernet/eth_mac/test_EthMacRxShift.py index 5500957900..633868abc7 100644 --- a/tests/ethernet/eth_mac/test_EthMacRxShift.py +++ b/tests/ethernet/eth_mac/test_EthMacRxShift.py @@ -9,12 +9,14 @@ ############################################################################## # Test methodology: -# - Sweep: Cover the enabled byte-insert path and the disabled pass-through -# path because those are the only meaningful modes of this wrapper. -# - Stimulus: Send one short single-beat frame with `rxShift=2`. -# - Checks: The enabled mode must prepend two zero bytes to the packet while -# preserving the frame boundary bits, and the disabled mode must leave the -# packet untouched. +# - Sweep: Cover both the enabled RX-shift datapath and the disabled bypass +# path, then vary the runtime shift count inside each run. +# - Stimulus: Exercise a zero-shift control-bit case, a one-beat non-zero +# shift, and a near-lane-width multi-beat shift (`rxShift=14`). +# - Checks: The enabled mode must prepend zero bytes to the payload, the +# disabled mode must leave payloads untouched, and the visible boundary bits +# (`SOF`, `EOFE`, and `last`) must match the current shift contract on both +# short and multi-beat packets. # - Timing: The RX shift block has no sink-side backpressure, so the frame is # launched continuously and the test samples the visible output beats. @@ -24,6 +26,7 @@ from tests.common.regression_utils import env_flag, parameter_case, run_surf_vhdl_test from tests.ethernet.eth_mac.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, + cycle, frame_beats_from_bytes, payload_from_beats, recv_frame, @@ -42,23 +45,69 @@ async def eth_mac_rx_shift_test(dut): dut, source_prefix="sAxis", sink_prefix="mAxis", - initial_values={"rxShift": 2}, + initial_values={"rxShift": 0}, ) source = bench.source sink = bench.sink assert source is not None assert sink is not None - input_bytes = b"\x10\x11\x12\x13\x14" - send_task = cocotb.start_soon( - send_contiguous_frame(source, frame_beats_from_bytes(input_bytes), clk=bench.clk) - ) - observed_beats = await recv_frame(sink, clk=bench.clk) - await send_task + test_cases = [ + { + "name": "zero_shift_control_bits", + "shift": 0, + "payload": b"\x10\x11\x12\x13\x14", + "eofe": 1, + }, + { + "name": "one_beat_shift1", + "shift": 1, + "payload": b"\x20\x21\x22\x23\x24", + "eofe": 0, + }, + { + "name": "multi_beat_shift14", + "shift": 14, + "payload": bytes(range(17)), + "eofe": 1, + }, + ] + + for index, case in enumerate(test_cases): + if index != 0: + # `AxiStreamShift` returns to IDLE one cycle after the previous + # frame drains, so leave a small gap before changing the runtime + # shift count for the next packet. + await cycle(bench.clk, 2) + + # `AxiStreamShift` samples the shift count while it is idle, so set the + # runtime port before driving the next packet. + dut.rxShift.value = case["shift"] + await cycle(bench.clk, 1) + + send_task = cocotb.start_soon( + send_contiguous_frame( + source, + frame_beats_from_bytes(case["payload"], eofe=case["eofe"]), + clk=bench.clk, + ) + ) + # The RX shift path can take noticeably longer to flush a packet than + # the simple leaf blocks because the left-shift engine inserts bytes and + # drains its delayed word state before asserting `tLast`. + observed_beats = await recv_frame(sink, clk=bench.clk, timeout_cycles=256) + await send_task + + expected_bytes = case["payload"] if not shift_enabled else (bytes(case["shift"]) + case["payload"]) + assert payload_from_beats(observed_beats) == expected_bytes, case["name"] - expected_bytes = (b"\x00\x00" + input_bytes) if shift_enabled else input_bytes - assert payload_from_beats(observed_beats) == expected_bytes - assert observed_beats[-1].last == 1 + # The wrapper exposes the lane-0 SOF bit. That remains visible on + # pass-through or zero-shift transfers, but a non-zero shift moves the + # first payload byte away from lane 0 and the visible SOF bit drops. + expected_sof = 1 if (not shift_enabled or case["shift"] == 0) else 0 + assert observed_beats[0].sof == expected_sof, case["name"] + assert observed_beats[-1].last == 1, case["name"] + assert observed_beats[-1].eofe == case["eofe"], case["name"] PARAMETER_SWEEP = [ diff --git a/tests/ethernet/eth_mac/test_EthMacTxShift.py b/tests/ethernet/eth_mac/test_EthMacTxShift.py index adf6d00424..c81ca54103 100644 --- a/tests/ethernet/eth_mac/test_EthMacTxShift.py +++ b/tests/ethernet/eth_mac/test_EthMacTxShift.py @@ -9,12 +9,14 @@ ############################################################################## # Test methodology: -# - Sweep: Cover the enabled byte-remove path and the disabled pass-through -# path because those are the only externally visible TX modes. -# - Stimulus: Send one short single-beat frame with `txShift=2`. -# - Checks: The enabled mode must remove the first two bytes of the packet -# while preserving the frame boundary bits, and the disabled mode must leave -# the packet untouched. +# - Sweep: Cover both the enabled TX-shift datapath and the disabled bypass +# path, then vary the runtime shift count inside each run. +# - Stimulus: Exercise a zero-shift control-bit case, a one-beat non-zero +# shift, and a near-lane-width multi-beat shift (`txShift=15`). +# - Checks: The enabled mode must remove the requested leading bytes from the +# payload, the disabled mode must leave payloads untouched, and the visible +# boundary bits (`SOF`, `EOFE`, and `last`) must match the current shift +# contract on both short and multi-beat packets. # - Timing: The TX shift stage participates in the AXI handshake, so the sink # explicitly raises `TREADY` while consuming the output frame. @@ -24,6 +26,7 @@ from tests.common.regression_utils import env_flag, parameter_case, run_surf_vhdl_test from tests.ethernet.eth_mac.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, + cycle, frame_beats_from_bytes, payload_from_beats, recv_frame, @@ -43,7 +46,7 @@ async def eth_mac_tx_shift_test(dut): source_prefix="sAxis", sink_prefix="mAxis", initial_values={ - "txShift": 2, + "txShift": 0, "mAxisTReady": 0, }, ) @@ -52,16 +55,58 @@ async def eth_mac_tx_shift_test(dut): assert source is not None assert sink is not None - input_bytes = b"\xAA\xBB\x10\x11\x12\x13" - send_task = cocotb.start_soon( - send_contiguous_frame(source, frame_beats_from_bytes(input_bytes), clk=bench.clk) - ) - observed_beats = await recv_frame(sink, clk=bench.clk, ready_signal=dut.mAxisTReady) - await send_task + test_cases = [ + { + "name": "zero_shift_control_bits", + "shift": 0, + "payload": b"\xAA\xBB\x10\x11\x12\x13", + "eofe": 1, + }, + { + "name": "one_beat_shift1", + "shift": 1, + "payload": b"\x31\x32\x33\x34\x35\x36", + "eofe": 0, + }, + { + "name": "multi_beat_shift15", + "shift": 15, + "payload": bytes(range(32)), + "eofe": 1, + }, + ] + + for index, case in enumerate(test_cases): + if index != 0: + # Mirror the RX bench spacing so each runtime shift update is + # sampled from a clean IDLE state. + await cycle(bench.clk, 2) + + # The TX shift block latches the runtime shift while idle, so update it + # before launching each frame. + dut.txShift.value = case["shift"] + await cycle(bench.clk, 1) + + send_task = cocotb.start_soon( + send_contiguous_frame( + source, + frame_beats_from_bytes(case["payload"], eofe=case["eofe"]), + clk=bench.clk, + ) + ) + observed_beats = await recv_frame(sink, clk=bench.clk, ready_signal=dut.mAxisTReady) + await send_task + + expected_bytes = case["payload"] if not shift_enabled else case["payload"][case["shift"] :] + assert payload_from_beats(observed_beats) == expected_bytes, case["name"] - expected_bytes = input_bytes[2:] if shift_enabled else input_bytes - assert payload_from_beats(observed_beats) == expected_bytes - assert observed_beats[-1].last == 1 + # As with RX shift, the wrapper only exposes the lane-0 SOF bit. It + # stays visible on pass-through or zero-shift transfers and drops once + # a non-zero right shift removes the original lane-0 byte. + expected_sof = 1 if (not shift_enabled or case["shift"] == 0) else 0 + assert observed_beats[0].sof == expected_sof, case["name"] + assert observed_beats[-1].last == 1, case["name"] + assert observed_beats[-1].eofe == case["eofe"], case["name"] PARAMETER_SWEEP = [ From 775660cfe8f7a477753ff04ddbf89f3b3e690ca5 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 10 Apr 2026 20:24:16 -0700 Subject: [PATCH 07/92] Rename folder. --- docs/_meta/rtl_regression_handoff.md | 8 ++++---- docs/_meta/rtl_regression_progress.md | 14 +++++++------- tests/ethernet/{eth_mac => EthMacCore}/__init__.py | 0 .../{eth_mac => EthMacCore}/ethmac_test_utils.py | 0 .../test_EthCrc32Parallel.py | 4 ++-- .../{eth_mac => EthMacCore}/test_EthMacFlowCtrl.py | 2 +- .../{eth_mac => EthMacCore}/test_EthMacRxCsum.py | 2 +- .../{eth_mac => EthMacCore}/test_EthMacRxFilter.py | 2 +- .../{eth_mac => EthMacCore}/test_EthMacRxImport.py | 2 +- .../{eth_mac => EthMacCore}/test_EthMacRxPause.py | 2 +- .../{eth_mac => EthMacCore}/test_EthMacRxShift.py | 2 +- .../{eth_mac => EthMacCore}/test_EthMacTop.py | 2 +- .../{eth_mac => EthMacCore}/test_EthMacTxCsum.py | 2 +- .../{eth_mac => EthMacCore}/test_EthMacTxExport.py | 2 +- .../{eth_mac => EthMacCore}/test_EthMacTxPause.py | 2 +- .../{eth_mac => EthMacCore}/test_EthMacTxShift.py | 2 +- 16 files changed, 24 insertions(+), 24 deletions(-) rename tests/ethernet/{eth_mac => EthMacCore}/__init__.py (100%) rename tests/ethernet/{eth_mac => EthMacCore}/ethmac_test_utils.py (100%) rename tests/ethernet/{eth_mac => EthMacCore}/test_EthCrc32Parallel.py (96%) rename tests/ethernet/{eth_mac => EthMacCore}/test_EthMacFlowCtrl.py (98%) rename tests/ethernet/{eth_mac => EthMacCore}/test_EthMacRxCsum.py (98%) rename tests/ethernet/{eth_mac => EthMacCore}/test_EthMacRxFilter.py (99%) rename tests/ethernet/{eth_mac => EthMacCore}/test_EthMacRxImport.py (99%) rename tests/ethernet/{eth_mac => EthMacCore}/test_EthMacRxPause.py (98%) rename tests/ethernet/{eth_mac => EthMacCore}/test_EthMacRxShift.py (98%) rename tests/ethernet/{eth_mac => EthMacCore}/test_EthMacTop.py (99%) rename tests/ethernet/{eth_mac => EthMacCore}/test_EthMacTxCsum.py (98%) rename tests/ethernet/{eth_mac => EthMacCore}/test_EthMacTxExport.py (99%) rename tests/ethernet/{eth_mac => EthMacCore}/test_EthMacTxPause.py (98%) rename tests/ethernet/{eth_mac => EthMacCore}/test_EthMacTxShift.py (98%) diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index 6460e985e8..f4ca290e53 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -18,7 +18,7 @@ - Treat VHDL packages as transitively covered unless a behavioral function/procedure needs a dedicated wrapper ## Quick Resume Snapshot -- Current frontier: the axi-first pass is complete through the previously remaining final 11 `axi/` modules, `dsp/` is now included in the generated phase-1 queue, and a manual first-wave `ethernet/EthMacCore` slice is now also validated under `tests/ethernet/eth_mac/`. `ethernet` and `protocols` still remain temporarily deferred in `docs/_meta/rtl_phase1_queue_overrides.json`, so the generated queue is intentionally behind the manually advanced Ethernet work. +- Current frontier: the axi-first pass is complete through the previously remaining final 11 `axi/` modules, `dsp/` is now included in the generated phase-1 queue, and a manual first-wave `ethernet/EthMacCore` slice is now also validated under `tests/ethernet/EthMacCore/`. `ethernet` and `protocols` still remain temporarily deferred in `docs/_meta/rtl_phase1_queue_overrides.json`, so the generated queue is intentionally behind the manually advanced Ethernet work. - Current axi frontier: complete for the intended simulator-friendly pass in this branch snapshot; do not resume from the older stale `AxiResize` note. - Current validated-open issues: - None currently recorded on this merged branch. `AxiResize` and `AxiStreamDmaV2Read` are both fixed here; queue regeneration is the next step. @@ -54,7 +54,7 @@ - For first-pass wrapper benches, prove the externally visible stable path first and defer shakier simulator-sensitive branches explicitly in the docs instead of stretching one bench to cover everything. - `AxiStreamDmaV2Read` needed a real RTL/runtime fix rather than a bench workaround: keep the bounded byte-count conversion fix in `axi/axi4/rtl/AxiPkg.vhd` and the direct terminal-mask generation in `axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd`. The current wrapper only exposes an 8-bit `TUSER`, so the observable contract in the checked-in bench is first-user propagation plus payload/keep/id/dest and descriptor return fields. - `tests/dsp/generic/dsp_test_utils.py` is now the shared home for DSP-specific signed helpers, rolling reference models, cocotb clock-settle timing, and generated FIR wrappers. Reuse it instead of cloning DSP arithmetic or wrapper boilerplate. -- `tests/ethernet/eth_mac/ethmac_test_utils.py` is now the shared home for the current Ethernet MAC slice: flat EMAC beat helpers, Ethernet/IPv4/UDP packet builders, checksum reference code, MAC-config byte-order helpers, and minimum-frame padding helpers. Reuse it instead of cloning packet or sideband plumbing across `EthMacCore` benches. +- `tests/ethernet/EthMacCore/ethmac_test_utils.py` is now the shared home for the current Ethernet MAC slice: flat EMAC beat helpers, Ethernet/IPv4/UDP packet builders, checksum reference code, MAC-config byte-order helpers, and minimum-frame padding helpers. Reuse it instead of cloning packet or sideband plumbing across `EthMacCore` benches. - The current `EthMacCore` slice is intentionally a checked-in-wrapper-first rollout, not a cocotb-generated-wrapper experiment. Keep new Ethernet work on that same pattern unless the simulator forces a very local generic adapter. - The XGMII import/export loopback behavior differs from the GMII path when `phyReady` drops mid-traffic: the blocked frame is retained and drains after link recovery, padded to Ethernet's minimum frame size if it was short. The GMII path drops that blocked frame. Future import/export coverage should preserve that distinction instead of forcing one common expectation. - `EthMacRxCsum` reliably raises `IPERR` on a bad IPv4 header checksum, but the checked-in wrapper contract does not currently require `EOFE` for that case. Keep the negative test aligned to the real observable contract rather than to a stronger assumption. @@ -85,7 +85,7 @@ The project now also has a shared helper path in `tests/common/regression_utils. `tests/common/regression_utils.py` now also includes `start_lockstep_clocks()` for DUTs whose generics assume truly common clocks in both ports. Use that helper instead of launching two same-period clocks independently when the RTL assumes shared edge identity. -The first manual `ethernet/EthMacCore` wave is now also in place. The checked-in Ethernet MAC benches under `tests/ethernet/eth_mac/` cover `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`, and the current directory-level regression passes locally with `32 passed`. The current Ethernet wrappers live under `ethernet/EthMacCore/wrappers/` and should be treated as the stable cocotb-facing surfaces for deeper `EthMacCore` work. +The first manual `ethernet/EthMacCore` wave is now also in place. The checked-in Ethernet MAC benches under `tests/ethernet/EthMacCore/` cover `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`, and the current directory-level regression passes locally with `32 passed`. The current Ethernet wrappers live under `ethernet/EthMacCore/wrappers/` and should be treated as the stable cocotb-facing surfaces for deeper `EthMacCore` work. The wrapper coverage policy is now more explicit in practice: test the wrapper-specific behavior, not the full leaf matrix again. `Fifo` validated both inferred sync/async selection branches, `FifoCascade` validated public stage-vector mapping plus a curated output smoke, and `FifoMux` is currently validated only on the stable split-to-narrow path. The pack-to-wide `FifoMux` path should be treated as still open rather than silently assumed covered. @@ -142,7 +142,7 @@ One small RTL fix landed during that validation pass because the new `AxiStreamD A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instantiation_graph.md` and `docs/_meta/rtl_instantiation_graph.json`, and the same generator now also emits a path-qualified bottom-up phase-1 queue at `docs/_meta/rtl_phase1_queue.md` and `docs/_meta/rtl_phase1_queue.json`. Keep the graph for provenance, but treat the generated queue as the default source of truth for what to implement next. Manual phase-1 deferrals and order exceptions belong in `docs/_meta/rtl_phase1_queue_overrides.json`, not as hand-edited ordering in the plan doc. ## Immediate Next Task -Choose whether the next manual branch step stays in `ethernet/EthMacCore` or returns to another non-deferred subsystem. If staying in Ethernet, the most natural follow-on is the MAC assembly layer (`EthMacRx`, `EthMacTx`, `EthMacRxFifo`, `EthMacTxFifo`) or a move into the IPv4 / Raw Ethernet stack using the now-established `ethmac_test_utils.py` helper and checked-in wrapper pattern. If switching back to queue-driven work, remove the temporary subsystem deferrals and regenerate `docs/_meta/rtl_phase1_queue.{md,json}` first so the queue is authoritative again. +Choose whether the next manual branch step stays in `ethernet/EthMacCore` or returns to another non-deferred subsystem. If staying in Ethernet, the most natural follow-on is the MAC assembly layer (`EthMacRx`, `EthMacTx`, `EthMacRxFifo`, `EthMacTxFifo`) or a move into the IPv4 / Raw Ethernet stack using the now-established `tests/ethernet/EthMacCore/ethmac_test_utils.py` helper and checked-in wrapper pattern. If switching back to queue-driven work, remove the temporary subsystem deferrals and regenerate `docs/_meta/rtl_phase1_queue.{md,json}` first so the queue is authoritative again. ## Read Order 1. `docs/_meta/rtl_regression_handoff.md` diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 4ae9cd6b56..6bbbab9ec2 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -3,7 +3,7 @@ ## Summary - Current phase: Phase-1 implementation active - Current subsystem: `ethernet/EthMacCore` -- Current focus module: the first manual `ethernet/EthMacCore` wave is now in place under `tests/ethernet/eth_mac/`, covering `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`, with the main follow-on choices now being deeper `EthMacRx` / `EthMacTx` / FIFO assembly work or a move into the IPv4 / Raw Ethernet stack. +- Current focus module: the first manual `ethernet/EthMacCore` wave is now in place under `tests/ethernet/EthMacCore/`, covering `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`, with the main follow-on choices now being deeper `EthMacRx` / `EthMacTx` / FIFO assembly work or a move into the IPv4 / Raw Ethernet stack. - Last updated: 2026-04-10 ## Current Frontier Snapshot @@ -20,7 +20,7 @@ - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. - - For `ethernet/EthMacCore`, keep using the checked-in wrappers under `ethernet/EthMacCore/wrappers/` plus the shared helper layer in `tests/ethernet/eth_mac/ethmac_test_utils.py`. The practical first-pass shape is a flat EMAC beat wrapper with explicit sideband bits, curated PHY/runtime sweeps instead of exhaustive `PHY_TYPE_G` coverage, and helper-side handling for wire-level quirks such as minimum-frame padding and MAC-config byte order. + - For `ethernet/EthMacCore`, keep using the checked-in wrappers under `ethernet/EthMacCore/wrappers/` plus the shared helper layer in `tests/ethernet/EthMacCore/ethmac_test_utils.py`. The practical first-pass shape is a flat EMAC beat wrapper with explicit sideband bits, curated PHY/runtime sweeps instead of exhaustive `PHY_TYPE_G` coverage, and helper-side handling for wire-level quirks such as minimum-frame padding and MAC-config byte order. ## Status | Subsystem | Inventory | Smoke | Functional | Notes | @@ -30,7 +30,7 @@ | `dsp` | started | not started | started | The planned `dsp/generic/fixed` leaf batch is now validated under `tests/dsp/generic/`: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. Shared DSP helpers now live in `tests/dsp/generic/dsp_test_utils.py`, and the legacy VHDL benches under `dsp/generic/tb/` were treated as behavioral reference material rather than as execution constraints. | | `axi` | started | not started | started | The axi-first pass is now complete for the simulator-friendly queue. The final locally validated batch adds `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`, with a combined `11 passed` validation run on 2026-03-27. Added checked-in subsystem wrappers under `axi/axi4/ip_integrator/`, `axi/axi-lite/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/` for those benches. `AxiStreamFifoV2` now has an expanded `10 passed` wrapper regression under `tests/axi/axi_stream/` covering async and sync width conversion, metadata truncation, `VALID_THOLD` frame-ready and burst-release modes, dynamic pause-threshold behavior, `CASCADE_SIZE=2`, and the `S_HAS_TREADY=0` pause-only source-side path. `AxiResize` now passes its equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` wrapper regression on this branch after the read-hold RTL fix. `AxiLiteAsync`, `AxiLiteToDrp`, and `AxiRateGen` still keep intentionally narrow common-clock subsets while the more timing-sensitive async AXI-Lite crossing branches remain open. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` still keep intentionally narrow first-pass subsets. `AxiStreamDmaV2Read` is now validated with a two-case wrapper regression covering both aligned and short terminal-beat reads after fixing bounded byte-count conversion in `AxiPkg` and terminal-mask generation in `AxiStreamDmaV2Read`. | | `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. | -| `ethernet` | started | not started | started | `tests/ethernet/eth_mac/` now covers a first manual `EthMacCore` slice: `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`, with the deeper filter/shift/CRC corner expansions also in place. The generated queue still keeps the broader subsystem deferred until the post-axi refresh removes the temporary queue override. | +| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers a first manual `EthMacCore` slice: `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`, with the deeper filter/shift/CRC corner expansions also in place. The generated queue still keeps the broader subsystem deferred until the post-axi refresh removes the temporary queue override. | | `devices` | not started | not started | not started | Many vendor-heavy cases | | `xilinx` | not started | not started | not started | Many vendor-heavy cases | @@ -76,9 +76,9 @@ - Validated `tests/base/fifo/test_FifoAsync.py` locally with `./.venv/bin/python -m pytest -v tests/base/fifo/test_FifoAsync.py`. - Reorganized new regressions into subsystem packages under `tests/` and moved shared helpers to `tests/common/`. - Added `tests/README.md` to document the regression layout policy. -- Added the shared Ethernet MAC helper layer in `tests/ethernet/eth_mac/ethmac_test_utils.py`, including packet builders, checksum helpers, MAC-config byte-order handling, flat EMAC beat helpers, and Ethernet minimum-frame padding support for the import/export loopback benches. +- Added the shared Ethernet MAC helper layer in `tests/ethernet/EthMacCore/ethmac_test_utils.py`, including packet builders, checksum helpers, MAC-config byte-order handling, flat EMAC beat helpers, and Ethernet minimum-frame padding support for the import/export loopback benches. - Added checked-in cocotb-facing wrappers under `ethernet/EthMacCore/wrappers/` for the first `EthMacCore` wave, including loopback wrappers for import/export and top-level tests plus flat wrappers for the checksum, pause, filter, and shift leaves. -- Implemented and validated the first `ethernet/EthMacCore` functional wave under `tests/ethernet/eth_mac/`: `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`. +- Implemented and validated the first `ethernet/EthMacCore` functional wave under `tests/ethernet/EthMacCore/`: `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`. - Expanded the first `EthMacCore` wave beyond the initial happy paths: `EthMacTop` now covers filter/backpressure/checksum/pause interactions, `EthMacRxImport` and `EthMacTxExport` now cover both GMII and XGMII plus link-not-ready recovery behavior, the RX/TX checksum benches now include negative and partial-repair cases, `EthMacRxFilter` now covers multicast/broadcast/filter-disable/multi-beat-drop behavior, the RX/TX shift benches now cover runtime shift changes and control-bit propagation, and `EthCrc32Parallel` now sweeps all byte widths `1..16`. - Ran a quick HDL coverage spike against the local Homebrew `ghdl` build and confirmed it does not expose `--coverage` or a `coverage` subcommand. - Migrated `AxiStreamFifoV2` into `tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py` and validated the current 10-case sweep locally. @@ -246,8 +246,8 @@ - 2026-04-06: Completed the remaining manual `protocols/ssi` leaf batch. Added checked-in wrappers `protocols/ssi/wrappers/SsiCmdMasterPulserWrapper.vhd`, `protocols/ssi/wrappers/SsiCmdMasterWrapper.vhd`, `protocols/ssi/wrappers/SsiFrameLimiterWrapper.vhd`, `protocols/ssi/wrappers/SsiIncrementingTxWrapper.vhd`, `protocols/ssi/wrappers/SsiAxiLiteMasterWrapper.vhd`, and `protocols/ssi/wrappers/SsiDbgTapWrapper.vhd`; added `tests/protocols/ssi/test_SsiCmdMasterPulser.py`, `tests/protocols/ssi/test_SsiCmdMaster.py`, `tests/protocols/ssi/test_SsiFrameLimiter.py`, `tests/protocols/ssi/test_SsiIncrementingTx.py`, `tests/protocols/ssi/test_SsiAxiLiteMaster.py`, and `tests/protocols/ssi/test_SsiDbgTap.py`; extended `tests/protocols/ssi/ssi_test_utils.py` with optional `TID` handling plus shared frame-receive helpers; validated the new six-test batch locally with `6 passed`; and kept wrapper lint clean under `vsg --fix -c vsg-linter.yml -f` plus a clean follow-up lint pass. The current scope is intentionally uneven: `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiIncrementingTx`, and `SsiAxiLiteMaster` have functional first-pass checks, `SsiFrameLimiter` is currently a narrowed single-beat/missing-SOF subset, and `SsiDbgTap` is traffic smoke only because the RTL exposes no externally visible state. - 2026-04-07: Tightened the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` so flat SSI sources wait for a real handshake edge and shared frame receivers capture accepted handshakes instead of inferring contiguous traffic from post-send snapshots. Revalidated the existing SSI slice locally with `19 passed`. A focused follow-up on `SsiIbFrameFilter` and `SsiFifo` showed the earlier apparent 3-beat middle-word loss was a bench observation bug rather than an RTL bug, after which the checked-in `SsiFifo` regression added a real contiguous 3-beat pass-through assertion and the `SsiAxiLiteMaster` / `SsiIncrementingTx` benches were updated to assert the full emitted frame shapes. - 2026-04-07: Expanded `tests/protocols/ssi/test_SsiFifo.py` beyond the earlier single-beat subset. The checked-in FIFO bench now proves contiguous 3-beat frame preservation on the default, `VALID_THOLD_G=0`, and `VALID_THOLD_G=2` wrapper paths; exercises repeated-`SOF` malformed-frame handling across the buffered modes; and keeps the existing missing-`SOF` drop plus `SLAVE_READY_EN_G=false` overflow checks. The buffered malformed-frame result is mode-specific at the wrapper boundary: `VALID_THOLD_G=0` drops the malformed repeated-`SOF` frame outright, while `VALID_THOLD_G=2` emits the expected two-beat terminated `EOFE` frame. A follow-up backpressure pass also added explicit drain-side ready toggling on a good 5-beat frame, malformed termination under toggled ready, and thresholded release under intermittent drain stalls so SSI frame policy is now checked under nontrivial sink backpressure without duplicating the full `AxiStreamFifoV2` transport matrix. Revalidated the full touched SSI slice locally with `19 passed`. -- 2026-04-10: Landed the first manual `ethernet/EthMacCore` bench wave under `tests/ethernet/eth_mac/`, added the required checked-in wrappers under `ethernet/EthMacCore/wrappers/`, and validated the baseline 12-module slice covering `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`. -- 2026-04-10: Expanded that same `EthMacCore` slice beyond the initial happy paths. The checked-in Ethernet MAC suite now covers `EthMacTop` filter/backpressure/checksum/pause interactions, GMII and XGMII import/export plus link-not-ready recovery behavior, checksum negative cases, filter multicast/broadcast/filter-disable/multi-beat-drop behavior, shift runtime-control and control-bit propagation edges, and full byte-width `1..16` logic-path coverage for `EthCrc32Parallel`. The full `tests/ethernet/eth_mac` directory currently passes locally with `32 passed`. +- 2026-04-10: Landed the first manual `ethernet/EthMacCore` bench wave under `tests/ethernet/EthMacCore/`, added the required checked-in wrappers under `ethernet/EthMacCore/wrappers/`, and validated the baseline 12-module slice covering `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`. +- 2026-04-10: Expanded that same `EthMacCore` slice beyond the initial happy paths. The checked-in Ethernet MAC suite now covers `EthMacTop` filter/backpressure/checksum/pause interactions, GMII and XGMII import/export plus link-not-ready recovery behavior, checksum negative cases, filter multicast/broadcast/filter-disable/multi-beat-drop behavior, shift runtime-control and control-bit propagation edges, and full byte-width `1..16` logic-path coverage for `EthCrc32Parallel`. The full `tests/ethernet/EthMacCore` directory currently passes locally with `32 passed`. - 2026-03-20: Added an explicit project rule to comment new Python regression code where intent or runner behavior is not self-evident. - 2026-03-20: Expanded `FifoAsync` to a validated 12-case parameter matrix and enabled default pytest xdist parallelization with `pytest.ini`. - 2026-03-20: Added package-coverage policy: packages are covered transitively unless a behavioral helper warrants a dedicated wrapper test. diff --git a/tests/ethernet/eth_mac/__init__.py b/tests/ethernet/EthMacCore/__init__.py similarity index 100% rename from tests/ethernet/eth_mac/__init__.py rename to tests/ethernet/EthMacCore/__init__.py diff --git a/tests/ethernet/eth_mac/ethmac_test_utils.py b/tests/ethernet/EthMacCore/ethmac_test_utils.py similarity index 100% rename from tests/ethernet/eth_mac/ethmac_test_utils.py rename to tests/ethernet/EthMacCore/ethmac_test_utils.py diff --git a/tests/ethernet/eth_mac/test_EthCrc32Parallel.py b/tests/ethernet/EthMacCore/test_EthCrc32Parallel.py similarity index 96% rename from tests/ethernet/eth_mac/test_EthCrc32Parallel.py rename to tests/ethernet/EthMacCore/test_EthCrc32Parallel.py index c80cfef4ec..f2b29e017c 100644 --- a/tests/ethernet/eth_mac/test_EthCrc32Parallel.py +++ b/tests/ethernet/EthMacCore/test_EthCrc32Parallel.py @@ -32,7 +32,7 @@ from tests.base.crc.crc_test_utils import crc_out_from_remainder, crc_update, pack_active_bytes from tests.common.regression_utils import hdl_parameters_from, parameter_case, run_surf_vhdl_test -from tests.ethernet.eth_mac.ethmac_test_utils import ETHMAC_RTL_SOURCES +from tests.ethernet.EthMacCore.ethmac_test_utils import ETHMAC_RTL_SOURCES async def cycle(clk, count: int = 1) -> None: @@ -114,5 +114,5 @@ def test_EthCrc32Parallel(parameters): parameters=hdl_parameters_from(parameters), extra_env=parameters, extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES}, - sim_build_key="tests/sim_build/ethernet/eth_mac/test_EthCrc32Parallel.shared", + sim_build_key="tests/sim_build/ethernet/EthMacCore/test_EthCrc32Parallel.shared", ) diff --git a/tests/ethernet/eth_mac/test_EthMacFlowCtrl.py b/tests/ethernet/EthMacCore/test_EthMacFlowCtrl.py similarity index 98% rename from tests/ethernet/eth_mac/test_EthMacFlowCtrl.py rename to tests/ethernet/EthMacCore/test_EthMacFlowCtrl.py index 8722d5e146..23c7f10dba 100644 --- a/tests/ethernet/eth_mac/test_EthMacFlowCtrl.py +++ b/tests/ethernet/EthMacCore/test_EthMacFlowCtrl.py @@ -26,7 +26,7 @@ from cocotb.triggers import RisingEdge, Timer from tests.common.regression_utils import env_flag, parameter_case, run_surf_vhdl_test -from tests.ethernet.eth_mac.ethmac_test_utils import ETHMAC_RTL_SOURCES +from tests.ethernet.EthMacCore.ethmac_test_utils import ETHMAC_RTL_SOURCES WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacFlowCtrlWrapper.vhd" diff --git a/tests/ethernet/eth_mac/test_EthMacRxCsum.py b/tests/ethernet/EthMacCore/test_EthMacRxCsum.py similarity index 98% rename from tests/ethernet/eth_mac/test_EthMacRxCsum.py rename to tests/ethernet/EthMacCore/test_EthMacRxCsum.py index b0aedebaf2..5d206b7464 100644 --- a/tests/ethernet/eth_mac/test_EthMacRxCsum.py +++ b/tests/ethernet/EthMacCore/test_EthMacRxCsum.py @@ -24,7 +24,7 @@ import pytest from tests.common.regression_utils import run_surf_vhdl_test -from tests.ethernet.eth_mac.ethmac_test_utils import ( +from tests.ethernet.EthMacCore.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, build_ethernet_frame, build_ipv4_header, diff --git a/tests/ethernet/eth_mac/test_EthMacRxFilter.py b/tests/ethernet/EthMacCore/test_EthMacRxFilter.py similarity index 99% rename from tests/ethernet/eth_mac/test_EthMacRxFilter.py rename to tests/ethernet/EthMacCore/test_EthMacRxFilter.py index ec328a92d9..21126f6b69 100644 --- a/tests/ethernet/eth_mac/test_EthMacRxFilter.py +++ b/tests/ethernet/EthMacCore/test_EthMacRxFilter.py @@ -25,7 +25,7 @@ import pytest from tests.common.regression_utils import run_surf_vhdl_test -from tests.ethernet.eth_mac.ethmac_test_utils import ( +from tests.ethernet.EthMacCore.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, build_ethernet_frame, mac_config_word_from_wire, diff --git a/tests/ethernet/eth_mac/test_EthMacRxImport.py b/tests/ethernet/EthMacCore/test_EthMacRxImport.py similarity index 99% rename from tests/ethernet/eth_mac/test_EthMacRxImport.py rename to tests/ethernet/EthMacCore/test_EthMacRxImport.py index 032003c1d9..df98b5b300 100644 --- a/tests/ethernet/eth_mac/test_EthMacRxImport.py +++ b/tests/ethernet/EthMacCore/test_EthMacRxImport.py @@ -28,7 +28,7 @@ import pytest from tests.common.regression_utils import parameter_case, run_surf_vhdl_test -from tests.ethernet.eth_mac.ethmac_test_utils import ( +from tests.ethernet.EthMacCore.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, build_ethernet_frame, cycle, diff --git a/tests/ethernet/eth_mac/test_EthMacRxPause.py b/tests/ethernet/EthMacCore/test_EthMacRxPause.py similarity index 98% rename from tests/ethernet/eth_mac/test_EthMacRxPause.py rename to tests/ethernet/EthMacCore/test_EthMacRxPause.py index 659900a075..f5d69db741 100644 --- a/tests/ethernet/eth_mac/test_EthMacRxPause.py +++ b/tests/ethernet/EthMacCore/test_EthMacRxPause.py @@ -25,7 +25,7 @@ from cocotb.triggers import RisingEdge, Timer from tests.common.regression_utils import run_surf_vhdl_test -from tests.ethernet.eth_mac.ethmac_test_utils import ( +from tests.ethernet.EthMacCore.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, build_ethernet_frame, build_pause_frame, diff --git a/tests/ethernet/eth_mac/test_EthMacRxShift.py b/tests/ethernet/EthMacCore/test_EthMacRxShift.py similarity index 98% rename from tests/ethernet/eth_mac/test_EthMacRxShift.py rename to tests/ethernet/EthMacCore/test_EthMacRxShift.py index 633868abc7..a58f1f030f 100644 --- a/tests/ethernet/eth_mac/test_EthMacRxShift.py +++ b/tests/ethernet/EthMacCore/test_EthMacRxShift.py @@ -24,7 +24,7 @@ import pytest from tests.common.regression_utils import env_flag, parameter_case, run_surf_vhdl_test -from tests.ethernet.eth_mac.ethmac_test_utils import ( +from tests.ethernet.EthMacCore.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, cycle, frame_beats_from_bytes, diff --git a/tests/ethernet/eth_mac/test_EthMacTop.py b/tests/ethernet/EthMacCore/test_EthMacTop.py similarity index 99% rename from tests/ethernet/eth_mac/test_EthMacTop.py rename to tests/ethernet/EthMacCore/test_EthMacTop.py index 6169407ace..eb8ecebaf0 100644 --- a/tests/ethernet/eth_mac/test_EthMacTop.py +++ b/tests/ethernet/EthMacCore/test_EthMacTop.py @@ -27,7 +27,7 @@ from pathlib import Path from tests.common.regression_utils import parameter_case, run_surf_vhdl_test -from tests.ethernet.eth_mac.ethmac_test_utils import ( +from tests.ethernet.EthMacCore.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, build_ethernet_frame, build_ipv4_udp_frame, diff --git a/tests/ethernet/eth_mac/test_EthMacTxCsum.py b/tests/ethernet/EthMacCore/test_EthMacTxCsum.py similarity index 98% rename from tests/ethernet/eth_mac/test_EthMacTxCsum.py rename to tests/ethernet/EthMacCore/test_EthMacTxCsum.py index bb70ce4252..50fa942b6c 100644 --- a/tests/ethernet/eth_mac/test_EthMacTxCsum.py +++ b/tests/ethernet/EthMacCore/test_EthMacTxCsum.py @@ -26,7 +26,7 @@ import pytest from tests.common.regression_utils import run_surf_vhdl_test -from tests.ethernet.eth_mac.ethmac_test_utils import ( +from tests.ethernet.EthMacCore.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, build_ipv4_udp_frame, frame_beats_from_bytes, diff --git a/tests/ethernet/eth_mac/test_EthMacTxExport.py b/tests/ethernet/EthMacCore/test_EthMacTxExport.py similarity index 99% rename from tests/ethernet/eth_mac/test_EthMacTxExport.py rename to tests/ethernet/EthMacCore/test_EthMacTxExport.py index 29b96ee912..6fa3505a21 100644 --- a/tests/ethernet/eth_mac/test_EthMacTxExport.py +++ b/tests/ethernet/EthMacCore/test_EthMacTxExport.py @@ -28,7 +28,7 @@ import pytest from tests.common.regression_utils import parameter_case, run_surf_vhdl_test -from tests.ethernet.eth_mac.ethmac_test_utils import ( +from tests.ethernet.EthMacCore.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, build_ethernet_frame, cycle, diff --git a/tests/ethernet/eth_mac/test_EthMacTxPause.py b/tests/ethernet/EthMacCore/test_EthMacTxPause.py similarity index 98% rename from tests/ethernet/eth_mac/test_EthMacTxPause.py rename to tests/ethernet/EthMacCore/test_EthMacTxPause.py index 60e3265aa9..6500f63ff1 100644 --- a/tests/ethernet/eth_mac/test_EthMacTxPause.py +++ b/tests/ethernet/EthMacCore/test_EthMacTxPause.py @@ -26,7 +26,7 @@ import pytest from tests.common.regression_utils import parameter_case, run_surf_vhdl_test -from tests.ethernet.eth_mac.ethmac_test_utils import ( +from tests.ethernet.EthMacCore.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, build_ethernet_frame, build_pause_frame, diff --git a/tests/ethernet/eth_mac/test_EthMacTxShift.py b/tests/ethernet/EthMacCore/test_EthMacTxShift.py similarity index 98% rename from tests/ethernet/eth_mac/test_EthMacTxShift.py rename to tests/ethernet/EthMacCore/test_EthMacTxShift.py index c81ca54103..551ae86bdf 100644 --- a/tests/ethernet/eth_mac/test_EthMacTxShift.py +++ b/tests/ethernet/EthMacCore/test_EthMacTxShift.py @@ -24,7 +24,7 @@ import pytest from tests.common.regression_utils import env_flag, parameter_case, run_surf_vhdl_test -from tests.ethernet.eth_mac.ethmac_test_utils import ( +from tests.ethernet.EthMacCore.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, cycle, frame_beats_from_bytes, From 6904364183a43ec6525c2d0de537a03f2e5bb37e Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 10 Apr 2026 21:05:22 -0700 Subject: [PATCH 08/92] Final eth mac tests. --- .../wrappers/EthMacRxFifoWrapper.vhd | 153 ++++++++++++ .../wrappers/EthMacRxLoopbackWrapper.vhd | 219 ++++++++++++++++++ .../wrappers/EthMacTxFifoWrapper.vhd | 129 +++++++++++ .../wrappers/EthMacTxLoopbackWrapper.vhd | 210 +++++++++++++++++ tests/ethernet/EthMacCore/test_EthMacRx.py | 166 +++++++++++++ .../ethernet/EthMacCore/test_EthMacRxFifo.py | 147 ++++++++++++ tests/ethernet/EthMacCore/test_EthMacTx.py | 205 ++++++++++++++++ .../ethernet/EthMacCore/test_EthMacTxFifo.py | 127 ++++++++++ 8 files changed, 1356 insertions(+) create mode 100644 ethernet/EthMacCore/wrappers/EthMacRxFifoWrapper.vhd create mode 100644 ethernet/EthMacCore/wrappers/EthMacRxLoopbackWrapper.vhd create mode 100644 ethernet/EthMacCore/wrappers/EthMacTxFifoWrapper.vhd create mode 100644 ethernet/EthMacCore/wrappers/EthMacTxLoopbackWrapper.vhd create mode 100644 tests/ethernet/EthMacCore/test_EthMacRx.py create mode 100644 tests/ethernet/EthMacCore/test_EthMacRxFifo.py create mode 100644 tests/ethernet/EthMacCore/test_EthMacTx.py create mode 100644 tests/ethernet/EthMacCore/test_EthMacTxFifo.py diff --git a/ethernet/EthMacCore/wrappers/EthMacRxFifoWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacRxFifoWrapper.vhd new file mode 100644 index 0000000000..457bc70f12 --- /dev/null +++ b/ethernet/EthMacCore/wrappers/EthMacRxFifoWrapper.vhd @@ -0,0 +1,153 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for EthMacRxFifo +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity EthMacRxFifoWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + SYNTH_MODE_G : string := "inferred"; + MEMORY_TYPE_G : string := "block"; + DROP_ERR_PKT_G : boolean := true; + INT_PIPE_STAGES_G : natural := 1; + PIPE_STAGES_G : natural := 1; + FIFO_ADDR_WIDTH_G : positive range 9 to 16 := 11; + PRIM_COMMON_CLK_G : boolean := false); + port ( + sClk : in sl; + sRst : in sl; + mPrimClk : in sl; + mPrimRst : in sl; + phyReady : in sl; + pauseThresh : in slv(15 downto 0); + rxFifoDrop : out sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + sAxisIpErr : in sl; + sAxisTcpErr : in sl; + sAxisUdpErr : in sl; + sAxisPause : out sl; + sAxisOverflow : out sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTReady : in sl := '1'; + mAxisSof : out sl; + mAxisFrag : out sl; + mAxisEofe : out sl; + mAxisIpErr : out sl; + mAxisTcpErr : out sl; + mAxisUdpErr : out sl); +end entity EthMacRxFifoWrapper; + +architecture rtl of EthMacRxFifoWrapper is + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisCtrl : AxiStreamCtrlType := AXI_STREAM_CTRL_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + -- The RX-side FIFO input is not backpressured by `TREADY`, so the wrapper + -- ties the source ready high and exposes the real pause/overflow controls + -- separately for observation in the sClk domain. + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisIpErr, sAxisSof, sAxisTData, sAxisTcpErr, sAxisTKeep, sAxisTLast, sAxisTValid, sAxisUdpErr) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(127 downto 0) := sAxisTData; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_IPERR_BIT_C, sAxisIpErr); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_TCPERR_BIT_C, sAxisTcpErr); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_UDPERR_BIT_C, sAxisUdpErr); + sAxisMaster <= v; + end process sAxisComb; + + sAxisTReady <= '1'; + sAxisPause <= sAxisCtrl.pause; + sAxisOverflow <= sAxisCtrl.overflow; + mAxisSlave.tReady <= mAxisTReady; + + -- Re-expand the primary output stream after the FIFO crossing. + mAxisView : process (mAxisMaster) is + begin + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + mAxisIpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_IPERR_BIT_C); + mAxisTcpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_TCPERR_BIT_C); + mAxisUdpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_UDPERR_BIT_C); + end process mAxisView; + + U_DUT : entity surf.EthMacRxFifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + SYNTH_MODE_G => SYNTH_MODE_G, + MEMORY_TYPE_G => MEMORY_TYPE_G, + DROP_ERR_PKT_G => DROP_ERR_PKT_G, + INT_PIPE_STAGES_G => INT_PIPE_STAGES_G, + PIPE_STAGES_G => PIPE_STAGES_G, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + PRIM_COMMON_CLK_G => PRIM_COMMON_CLK_G, + PRIM_CONFIG_G => INT_EMAC_AXIS_CONFIG_C, + BYP_EN_G => false, + BYP_COMMON_CLK_G => false, + BYP_CONFIG_G => INT_EMAC_AXIS_CONFIG_C) + port map ( + sClk => sClk, + sRst => sRst, + phyReady => phyReady, + rxFifoDrop => rxFifoDrop, + pauseThresh => pauseThresh, + mPrimClk => mPrimClk, + mPrimRst => mPrimRst, + sPrimMaster => sAxisMaster, + sPrimCtrl => sAxisCtrl, + mPrimMaster => mAxisMaster, + mPrimSlave => mAxisSlave, + mBypClk => '0', + mBypRst => '0', + sBypMaster => AXI_STREAM_MASTER_INIT_C, + sBypCtrl => open, + mBypMaster => open, + mBypSlave => AXI_STREAM_SLAVE_FORCE_C); + +end architecture rtl; diff --git a/ethernet/EthMacCore/wrappers/EthMacRxLoopbackWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacRxLoopbackWrapper.vhd new file mode 100644 index 0000000000..37aa4ccaa4 --- /dev/null +++ b/ethernet/EthMacCore/wrappers/EthMacRxLoopbackWrapper.vhd @@ -0,0 +1,219 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing loopback wrapper for EthMacRx +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity EthMacRxLoopbackWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + PAUSE_EN_G : boolean := true; + PHY_TYPE_G : string := "XGMII"; + JUMBO_G : boolean := false; + FILT_EN_G : boolean := true; + BYP_EN_G : boolean := true; + BYP_ETH_TYPE_G : slv(15 downto 0) := x"B588"; + SYNTH_MODE_G : string := "inferred"); + port ( + ethClk : in sl; + ethRst : in sl; + ethClkEn : in sl := '1'; + phyReady : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + mPrimTValid : out sl; + mPrimTData : out slv(127 downto 0); + mPrimTKeep : out slv(15 downto 0); + mPrimTLast : out sl; + mPrimSof : out sl; + mPrimFrag : out sl; + mPrimEofe : out sl; + mPrimIpErr : out sl; + mPrimTcpErr : out sl; + mPrimUdpErr : out sl; + mBypTValid : out sl; + mBypTData : out slv(127 downto 0); + mBypTKeep : out slv(15 downto 0); + mBypTLast : out sl; + mBypSof : out sl; + mBypFrag : out sl; + mBypEofe : out sl; + mBypIpErr : out sl; + mBypTcpErr : out sl; + mBypUdpErr : out sl; + mPrimPause : in sl := '0'; + dropOnPause : in sl; + macAddress : in slv(47 downto 0); + filtEnable : in sl; + ipCsumEn : in sl; + tcpCsumEn : in sl; + udpCsumEn : in sl; + rxPauseReq : out sl; + rxPauseValue : out slv(15 downto 0); + rxCountEn : out sl; + rxCrcError : out sl); +end entity EthMacRxLoopbackWrapper; + +architecture rtl of EthMacRxLoopbackWrapper is + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mPrimMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mBypMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mPrimCtrl : AxiStreamCtrlType := AXI_STREAM_CTRL_INIT_C; + signal xgmiiTxd : slv(63 downto 0) := (others => '0'); + signal xgmiiTxc : slv(7 downto 0) := (others => '1'); + signal gmiiTxEn : sl := '0'; + signal gmiiTxEr : sl := '0'; + signal gmiiTxd : slv(7 downto 0) := (others => '0'); + signal ethConfig : EthMacConfigType := ETH_MAC_CONFIG_INIT_C; + +begin + + -- Flatten the packet source that is exported onto the chosen PHY loopback. + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(127 downto 0) := sAxisTData; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); + sAxisMaster <= v; + end process sAxisComb; + + sAxisTReady <= sAxisSlave.tReady; + + -- Expose the primary-path AXIS payload and user bits directly to cocotb. + mPrimView : process (mPrimMaster) is + begin + mPrimTValid <= mPrimMaster.tValid; + mPrimTData <= mPrimMaster.tData(127 downto 0); + mPrimTKeep <= mPrimMaster.tKeep(15 downto 0); + mPrimTLast <= mPrimMaster.tLast; + mPrimSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_SOF_BIT_C, 0); + mPrimFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_FRAG_BIT_C, 0); + mPrimEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_EOFE_BIT_C); + mPrimIpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_IPERR_BIT_C); + mPrimTcpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_TCPERR_BIT_C); + mPrimUdpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_UDPERR_BIT_C); + end process mPrimView; + + -- Expose the bypass stream separately so tests can prove EtherType routing. + mBypView : process (mBypMaster) is + begin + mBypTValid <= mBypMaster.tValid; + mBypTData <= mBypMaster.tData(127 downto 0); + mBypTKeep <= mBypMaster.tKeep(15 downto 0); + mBypTLast <= mBypMaster.tLast; + mBypSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_SOF_BIT_C, 0); + mBypFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_FRAG_BIT_C, 0); + mBypEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_EOFE_BIT_C); + mBypIpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_IPERR_BIT_C); + mBypTcpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_TCPERR_BIT_C); + mBypUdpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_UDPERR_BIT_C); + end process mBypView; + + -- Only the pause bit of the primary control record matters for these tests. + mPrimCtrl.pause <= mPrimPause; + mPrimCtrl.overflow <= '0'; + mPrimCtrl.idle <= '0'; + + -- Flatten the small EthMac config record into simple scalar inputs. + ethConfig.macAddress <= macAddress; + ethConfig.filtEnable <= filtEnable; + ethConfig.pauseEnable <= '0'; + ethConfig.pauseTime <= (others => '0'); + ethConfig.pauseThresh <= (others => '0'); + ethConfig.ipCsumEn <= ipCsumEn; + ethConfig.tcpCsumEn <= tcpCsumEn; + ethConfig.udpCsumEn <= udpCsumEn; + ethConfig.dropOnPause <= dropOnPause; + + -- Use the real export path to generate protocol-correct PHY symbols. + U_Tx : entity surf.EthMacTxExport + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + PHY_TYPE_G => PHY_TYPE_G, + SYNTH_MODE_G => SYNTH_MODE_G) + port map ( + ethClkEn => ethClkEn, + ethClk => ethClk, + ethRst => ethRst, + macObMaster => sAxisMaster, + macObSlave => sAxisSlave, + xlgmiiTxd => open, + xlgmiiTxc => open, + xgmiiTxd => xgmiiTxd, + xgmiiTxc => xgmiiTxc, + gmiiTxEn => gmiiTxEn, + gmiiTxEr => gmiiTxEr, + gmiiTxd => gmiiTxd, + phyReady => phyReady, + txCountEn => open, + txUnderRun => open, + txLinkNotReady => open); + + -- Feed the generated PHY traffic into the full RX assembly under test. + U_DUT : entity surf.EthMacRx + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + PAUSE_EN_G => PAUSE_EN_G, + PHY_TYPE_G => PHY_TYPE_G, + JUMBO_G => JUMBO_G, + ROCEV2_EN_G => false, + FILT_EN_G => FILT_EN_G, + BYP_EN_G => BYP_EN_G, + BYP_ETH_TYPE_G => BYP_ETH_TYPE_G, + SYNTH_MODE_G => SYNTH_MODE_G) + port map ( + ethClkEn => ethClkEn, + ethClk => ethClk, + ethRst => ethRst, + mPrimMaster => mPrimMaster, + mPrimCtrl => mPrimCtrl, + mBypMaster => mBypMaster, + mBypCtrl => AXI_STREAM_CTRL_UNUSED_C, + xlgmiiRxd => (others => '0'), + xlgmiiRxc => (others => '1'), + xgmiiRxd => xgmiiTxd, + xgmiiRxc => xgmiiTxc, + gmiiRxDv => gmiiTxEn, + gmiiRxEr => gmiiTxEr, + gmiiRxd => gmiiTxd, + rxPauseReq => rxPauseReq, + rxPauseValue => rxPauseValue, + phyReady => phyReady, + ethConfig => ethConfig, + rxCountEn => rxCountEn, + rxCrcError => rxCrcError); + +end architecture rtl; diff --git a/ethernet/EthMacCore/wrappers/EthMacTxFifoWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacTxFifoWrapper.vhd new file mode 100644 index 0000000000..c58d10f3a2 --- /dev/null +++ b/ethernet/EthMacCore/wrappers/EthMacTxFifoWrapper.vhd @@ -0,0 +1,129 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for EthMacTxFifo +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity EthMacTxFifoWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + PRIM_COMMON_CLK_G : boolean := false; + SYNTH_MODE_G : string := "inferred"); + port ( + mClk : in sl; + mRst : in sl; + sPrimClk : in sl; + sPrimRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + sAxisIpErr : in sl; + sAxisTcpErr : in sl; + sAxisUdpErr : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTReady : in sl := '1'; + mAxisSof : out sl; + mAxisFrag : out sl; + mAxisEofe : out sl; + mAxisIpErr : out sl; + mAxisTcpErr : out sl; + mAxisUdpErr : out sl); +end entity EthMacTxFifoWrapper; + +architecture rtl of EthMacTxFifoWrapper is + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + -- Flatten the primary client stream entering the TX FIFO crossing. + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisIpErr, sAxisSof, sAxisTData, sAxisTcpErr, sAxisTKeep, sAxisTLast, sAxisTValid, sAxisUdpErr) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(127 downto 0) := sAxisTData; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_IPERR_BIT_C, sAxisIpErr); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_TCPERR_BIT_C, sAxisTcpErr); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_UDPERR_BIT_C, sAxisUdpErr); + sAxisMaster <= v; + end process sAxisComb; + + sAxisTReady <= sAxisSlave.tReady; + mAxisSlave.tReady <= mAxisTReady; + + -- Re-expand the MAC-facing output stream for cocotb assertions. + mAxisView : process (mAxisMaster) is + begin + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + mAxisIpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_IPERR_BIT_C); + mAxisTcpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_TCPERR_BIT_C); + mAxisUdpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_UDPERR_BIT_C); + end process mAxisView; + + U_DUT : entity surf.EthMacTxFifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + PRIM_COMMON_CLK_G => PRIM_COMMON_CLK_G, + PRIM_CONFIG_G => INT_EMAC_AXIS_CONFIG_C, + BYP_EN_G => false, + BYP_COMMON_CLK_G => false, + BYP_CONFIG_G => INT_EMAC_AXIS_CONFIG_C, + SYNTH_MODE_G => SYNTH_MODE_G) + port map ( + mClk => mClk, + mRst => mRst, + sPrimClk => sPrimClk, + sPrimRst => sPrimRst, + sPrimMaster => sAxisMaster, + sPrimSlave => sAxisSlave, + mPrimMaster => mAxisMaster, + mPrimSlave => mAxisSlave, + sBypClk => '0', + sBypRst => '0', + sBypMaster => AXI_STREAM_MASTER_INIT_C, + sBypSlave => open, + mBypMaster => open, + mBypSlave => AXI_STREAM_SLAVE_FORCE_C); + +end architecture rtl; diff --git a/ethernet/EthMacCore/wrappers/EthMacTxLoopbackWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacTxLoopbackWrapper.vhd new file mode 100644 index 0000000000..f59380a358 --- /dev/null +++ b/ethernet/EthMacCore/wrappers/EthMacTxLoopbackWrapper.vhd @@ -0,0 +1,210 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing loopback wrapper for EthMacTx +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity EthMacTxLoopbackWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + PAUSE_EN_G : boolean := true; + PAUSE_512BITS_G : positive range 1 to 1024 := 1; + PHY_TYPE_G : string := "XGMII"; + DROP_ERR_PKT_G : boolean := true; + JUMBO_G : boolean := false; + BYP_EN_G : boolean := true; + SYNTH_MODE_G : string := "inferred"); + port ( + ethClk : in sl; + ethRst : in sl; + ethClkEn : in sl := '1'; + phyReady : in sl; + sPrimTValid : in sl; + sPrimTData : in slv(127 downto 0); + sPrimTKeep : in slv(15 downto 0); + sPrimTLast : in sl; + sPrimTReady : out sl; + sPrimSof : in sl; + sPrimFrag : in sl; + sPrimEofe : in sl; + sBypTValid : in sl; + sBypTData : in slv(127 downto 0); + sBypTKeep : in slv(15 downto 0); + sBypTLast : in sl; + sBypTReady : out sl; + sBypSof : in sl; + sBypFrag : in sl; + sBypEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisSof : out sl; + mAxisFrag : out sl; + mAxisEofe : out sl; + clientPause : in sl; + rxPauseReq : in sl; + rxPauseValue : in slv(15 downto 0); + pauseEnable : in sl; + pauseTime : in slv(15 downto 0); + macAddress : in slv(47 downto 0); + ipCsumEn : in sl; + tcpCsumEn : in sl; + udpCsumEn : in sl; + pauseTx : out sl; + txCountEn : out sl; + txUnderRun : out sl; + txLinkNotReady : out sl); +end entity EthMacTxLoopbackWrapper; + +architecture rtl of EthMacTxLoopbackWrapper is + + signal sPrimMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sPrimSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal sBypMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sBypSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal xgmiiTxd : slv(63 downto 0) := (others => '0'); + signal xgmiiTxc : slv(7 downto 0) := (others => '1'); + signal gmiiTxEn : sl := '0'; + signal gmiiTxEr : sl := '0'; + signal gmiiTxd : slv(7 downto 0) := (others => '0'); + signal ethConfig : EthMacConfigType := ETH_MAC_CONFIG_INIT_C; + +begin + + -- Flatten the primary client stream that feeds the TX assembly. + sPrimComb : process (sPrimEofe, sPrimFrag, sPrimSof, sPrimTData, sPrimTKeep, sPrimTLast, sPrimTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sPrimTValid; + v.tData(127 downto 0) := sPrimTData; + v.tKeep(15 downto 0) := sPrimTKeep; + v.tLast := sPrimTLast; + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sPrimSof, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sPrimFrag, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sPrimEofe); + sPrimMaster <= v; + end process sPrimComb; + + -- Flatten the bypass stream independently so the test can drive both ports. + sBypComb : process (sBypEofe, sBypFrag, sBypSof, sBypTData, sBypTKeep, sBypTLast, sBypTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sBypTValid; + v.tData(127 downto 0) := sBypTData; + v.tKeep(15 downto 0) := sBypTKeep; + v.tLast := sBypTLast; + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sBypSof, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sBypFrag, 0); + axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sBypEofe); + sBypMaster <= v; + end process sBypComb; + + sPrimTReady <= sPrimSlave.tReady; + sBypTReady <= sBypSlave.tReady; + + -- Present the recovered on-wire frame back to cocotb as a flat AXIS view. + mAxisView : process (mAxisMaster) is + begin + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + end process mAxisView; + + -- Flatten the relevant TX config fields under software control. + ethConfig.macAddress <= macAddress; + ethConfig.filtEnable <= '0'; + ethConfig.pauseEnable <= pauseEnable; + ethConfig.pauseTime <= pauseTime; + ethConfig.pauseThresh <= (others => '0'); + ethConfig.ipCsumEn <= ipCsumEn; + ethConfig.tcpCsumEn <= tcpCsumEn; + ethConfig.udpCsumEn <= udpCsumEn; + ethConfig.dropOnPause <= '0'; + + -- Drive the full TX assembly, including checksum, pause, and export logic. + U_DUT : entity surf.EthMacTx + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + PAUSE_EN_G => PAUSE_EN_G, + PAUSE_512BITS_G => PAUSE_512BITS_G, + PHY_TYPE_G => PHY_TYPE_G, + DROP_ERR_PKT_G => DROP_ERR_PKT_G, + JUMBO_G => JUMBO_G, + ROCEV2_EN_G => false, + BYP_EN_G => BYP_EN_G, + SYNTH_MODE_G => SYNTH_MODE_G) + port map ( + ethClkEn => ethClkEn, + ethClk => ethClk, + ethRst => ethRst, + sPrimMaster => sPrimMaster, + sPrimSlave => sPrimSlave, + sBypMaster => sBypMaster, + sBypSlave => sBypSlave, + xlgmiiTxd => open, + xlgmiiTxc => open, + xgmiiTxd => xgmiiTxd, + xgmiiTxc => xgmiiTxc, + gmiiTxEn => gmiiTxEn, + gmiiTxEr => gmiiTxEr, + gmiiTxd => gmiiTxd, + clientPause => clientPause, + rxPauseReq => rxPauseReq, + rxPauseValue => rxPauseValue, + pauseTx => pauseTx, + phyReady => phyReady, + ethConfig => ethConfig, + txCountEn => txCountEn, + txUnderRun => txUnderRun, + txLinkNotReady => txLinkNotReady); + + -- Recover the transmitted PHY stream so cocotb can validate frame order. + U_Loopback : entity surf.EthMacRxImport + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + PHY_TYPE_G => PHY_TYPE_G, + SYNTH_MODE_G => SYNTH_MODE_G) + port map ( + ethClkEn => ethClkEn, + ethClk => ethClk, + ethRst => ethRst, + macIbMaster => mAxisMaster, + xlgmiiRxd => (others => '0'), + xlgmiiRxc => (others => '1'), + xgmiiRxd => xgmiiTxd, + xgmiiRxc => xgmiiTxc, + gmiiRxDv => gmiiTxEn, + gmiiRxEr => gmiiTxEr, + gmiiRxd => gmiiTxd, + phyReady => phyReady, + rxCountEn => open, + rxCrcError => open); + +end architecture rtl; diff --git a/tests/ethernet/EthMacCore/test_EthMacRx.py b/tests/ethernet/EthMacCore/test_EthMacRx.py new file mode 100644 index 0000000000..641f0e3d7e --- /dev/null +++ b/tests/ethernet/EthMacCore/test_EthMacRx.py @@ -0,0 +1,166 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Use one pause-enabled, filter-enabled, bypass-enabled loopback +# instance so the assembly bench covers the externally meaningful RX modes in +# one build. +# - Stimulus: Feed the real RX assembly from a checked-in TX export wrapper, +# then send a valid local IPv4/UDP frame, one bypass-EtherType frame, one +# pause frame, and one bad-UDP frame. +# - Checks: Local traffic must emerge on the primary output without checksum +# errors, bypass traffic must emerge on the bypass output, pause frames must +# be consumed internally while pulsing the pause request, and bad UDP must +# propagate to the primary output with `UDPERR` and `EOFE` asserted. +# - Timing: The bench waits on visible AXIS/status behavior rather than fixed +# internal latency because the DUT chains import, pause, checksum, bypass, +# and filter stages. + +import cocotb +import pytest +from pathlib import Path + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + ETHMAC_RTL_SOURCES, + FlatEmacEndpoint, + build_ethernet_frame, + build_ipv4_udp_frame, + build_pause_frame, + expect_no_output, + frame_beats_from_bytes, + mac_config_word_from_wire, + payload_from_beats, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, + wait_signal_pulse, +) + + +WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacRxLoopbackWrapper.vhd" +ROCE_RTL_ROOT = Path(__file__).resolve().parents[3] / "ethernet" / "RoCEv2" / "rtl" +ROCE_ANALYSIS_SOURCES = [ + str(ROCE_RTL_ROOT / "RocePkg.vhd"), + *( + str(path) + for path in sorted(ROCE_RTL_ROOT.glob("*.vhd")) + if path.name != "RocePkg.vhd" + ), +] +LOCAL_MAC_WIRE = 0x001122334455 +LOCAL_MAC_CFG = mac_config_word_from_wire(LOCAL_MAC_WIRE) + + +@cocotb.test() +async def eth_mac_rx_test(dut): + bench = await setup_flat_emac_testbench( + dut, + source_prefix="sAxis", + sink_prefix=None, + initial_values={ + "ethClkEn": 1, + "phyReady": 1, + "mPrimPause": 0, + "dropOnPause": 0, + "macAddress": LOCAL_MAC_CFG, + "filtEnable": 1, + "ipCsumEn": 1, + "tcpCsumEn": 0, + "udpCsumEn": 1, + }, + ) + source = bench.source + prim_sink = FlatEmacEndpoint(dut, prefix="mPrim") + byp_sink = FlatEmacEndpoint(dut, prefix="mByp") + assert source is not None + + # First prove the straight-through RX assembly path on a valid local IPv4 + # packet that exercises the checksum checker without triggering errors. + valid_frame = build_ipv4_udp_frame( + dst_mac=LOCAL_MAC_WIRE, + src_mac=0x0A0B0C0D0E0F, + src_ip="192.168.10.1", + dst_ip="192.168.10.2", + src_port=0x1234, + dst_port=0x5678, + payload=bytes(range(48)), + ) + valid_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(valid_frame), clk=bench.clk) + ) + valid_observed = await recv_frame(prim_sink, clk=bench.clk, timeout_cycles=256) + await valid_send + assert payload_from_beats(valid_observed) == valid_frame + assert valid_observed[-1].iperr == 0 + assert valid_observed[-1].udperr == 0 + assert valid_observed[-1].eofe == 0 + await expect_no_output(byp_sink, clk=bench.clk, cycles=8) + + # The bypass route sits ahead of the MAC filter, so a foreign destination + # with the configured EtherType must still emerge on the bypass output. + bypass_frame = build_ethernet_frame( + dst_mac=0xDEADBEEF1234, + src_mac=0x111213141516, + eth_type=0x88B5, + payload=bytes(range(46)), + ) + bypass_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(bypass_frame), clk=bench.clk) + ) + bypass_observed = await recv_frame(byp_sink, clk=bench.clk, timeout_cycles=256) + await bypass_send + assert payload_from_beats(bypass_observed) == bypass_frame + await expect_no_output(prim_sink, clk=bench.clk, cycles=8) + + # A standards-compliant pause frame should be consumed internally and only + # expose the pause request/value side effects to software. + pause_value = 0x0020 + pause_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(build_pause_frame(pause_value)), clk=bench.clk) + ) + await wait_signal_pulse(dut.rxPauseReq, clk=bench.clk, timeout_cycles=128) + await pause_send + assert int(dut.rxPauseValue.value) == pause_value + await expect_no_output(prim_sink, clk=bench.clk, cycles=8) + await expect_no_output(byp_sink, clk=bench.clk, cycles=8) + + # Finish with a bad UDP checksum to prove the integrated pause and filter + # stages do not hide the RX checksum error reporting on the primary output. + bad_udp_frame = build_ipv4_udp_frame( + dst_mac=LOCAL_MAC_WIRE, + src_mac=0x202122232425, + src_ip="10.0.0.10", + dst_ip="10.0.0.20", + src_port=0x1111, + dst_port=0x2222, + payload=b"rx-assembly-bad-udp" + bytes(19), + udp_checksum_override=0x0001, + ) + bad_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(bad_udp_frame), clk=bench.clk) + ) + bad_observed = await recv_frame(prim_sink, clk=bench.clk, timeout_cycles=256) + await bad_send + assert payload_from_beats(bad_observed) == bad_udp_frame + assert bad_observed[-1].iperr == 0 + assert bad_observed[-1].udperr == 1 + assert bad_observed[-1].eofe == 1 + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="rx_assembly_loopback")]) +def test_EthMacRx(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ethmacrxloopbackwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES + ROCE_ANALYSIS_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/EthMacCore/test_EthMacRxFifo.py b/tests/ethernet/EthMacCore/test_EthMacRxFifo.py new file mode 100644 index 0000000000..39a4b3d533 --- /dev/null +++ b/tests/ethernet/EthMacCore/test_EthMacRxFifo.py @@ -0,0 +1,147 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Keep one asynchronous primary-path FIFO instance because that is the +# most behavior-rich configuration and reuses the real SsiFifo crossing. +# - Stimulus: Send one clean frame across the clock boundary, then hold the +# output side stalled while injecting a longer frame to trip the pause +# threshold, and finally send a bad frame marked with `EOFE`. +# - Checks: Clean traffic must emerge intact, the source-side pause flag must +# assert while the sink is blocked, and the bad frame must be dropped while +# pulsing `rxFifoDrop`. +# - Timing: The test uses distinct source and sink clocks, and waits on the +# visible FIFO controls instead of assuming a fixed occupancy latency. + +import cocotb +import pytest + +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + ETHMAC_RTL_SOURCES, + FlatEmacEndpoint, + build_ethernet_frame, + cycle, + expect_no_output, + frame_beats_from_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, + start_clock, + wait_signal_pulse, +) +from tests.common.regression_utils import run_surf_vhdl_test + + +WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacRxFifoWrapper.vhd" + + +async def reset_async_fifo(dut) -> None: + dut.sRst.value = 1 + dut.mPrimRst.value = 1 + await cycle(dut.sClk, 4) + await cycle(dut.mPrimClk, 2) + dut.sRst.value = 0 + dut.mPrimRst.value = 0 + await cycle(dut.sClk, 2) + await cycle(dut.mPrimClk, 2) + + +@cocotb.test() +async def eth_mac_rx_fifo_test(dut): + start_clock(dut.sClk, period_ns=4.0) + start_clock(dut.mPrimClk, period_ns=6.0) + + dut.phyReady.setimmediatevalue(1) + dut.pauseThresh.setimmediatevalue(1) + dut.mAxisTReady.setimmediatevalue(0) + + source = FlatEmacEndpoint(dut, prefix="sAxis") + sink = FlatEmacEndpoint(dut, prefix="mAxis") + source.set_idle() + + await reset_async_fifo(dut) + + # A basic async transfer proves the wrapper flattening and the FIFO path + # both preserve the EMAC framing and user bits. + dut.mAxisTReady.value = 1 + clean_frame = build_ethernet_frame( + dst_mac=0x001122334455, + src_mac=0x66778899AABB, + eth_type=0x9000, + payload=bytes(range(64)), + ) + clean_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(clean_frame), clk=dut.sClk) + ) + clean_observed = await recv_frame( + sink, + clk=dut.mPrimClk, + ready_signal=dut.mAxisTReady, + timeout_cycles=256, + ) + await clean_send + assert payload_from_beats(clean_observed) == clean_frame + + # Holding the sink stalled should eventually raise the pause hint on the + # source side once the FIFO occupancy crosses the programmed threshold. + dut.mAxisTReady.value = 0 + long_frame = build_ethernet_frame( + dst_mac=0x102132435465, + src_mac=0x203142536475, + eth_type=0x9001, + payload=bytes(range(160)), + ) + long_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(long_frame), clk=dut.sClk) + ) + for _ in range(64): + if int(dut.sAxisPause.value) == 1: + break + await cycle(dut.sClk, 1) + else: + raise AssertionError("Timed out waiting for RX FIFO pause assertion") + + dut.mAxisTReady.value = 1 + long_observed = await recv_frame( + sink, + clk=dut.mPrimClk, + ready_signal=dut.mAxisTReady, + timeout_cycles=512, + ) + await long_send + assert payload_from_beats(long_observed) == long_frame + + # The RX FIFO inherits the SSI inbound frame filter, so a missing opening + # SOF is a real drop condition that should only report the side effect. + bad_frame = build_ethernet_frame( + dst_mac=0xABCDEF123456, + src_mac=0x112233445566, + eth_type=0x88B5, + payload=bytes(range(48)), + ) + bad_beats = frame_beats_from_bytes(bad_frame) + bad_beats[0].sof = 0 + bad_send = cocotb.start_soon( + send_contiguous_frame(source, bad_beats, clk=dut.sClk) + ) + await wait_signal_pulse(dut.rxFifoDrop, clk=dut.sClk, timeout_cycles=128) + await bad_send + await expect_no_output(sink, clk=dut.mPrimClk, cycles=16) + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="rx_fifo_async_primary")]) +def test_EthMacRxFifo(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ethmacrxfifowrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/EthMacCore/test_EthMacTx.py b/tests/ethernet/EthMacCore/test_EthMacTx.py new file mode 100644 index 0000000000..0e4d495d93 --- /dev/null +++ b/tests/ethernet/EthMacCore/test_EthMacTx.py @@ -0,0 +1,205 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Use one pause-enabled, bypass-enabled TX loopback so the bench can +# cover checksum repair, bypass arbitration, pause generation, remote-pause +# gating, and link-not-ready handling in one checked-in wrapper. +# - Stimulus: Send one checksum-cleared primary IPv4/UDP frame, then launch +# primary and bypass traffic together, request a local pause frame, inject a +# short remote pause before another payload, and finally transmit while the +# PHY is marked not ready. +# - Checks: The TX assembly must repair checksums before export, bypass traffic +# must win arbitration over simultaneous primary traffic, local pause must +# emit the standards-compliant frame, remote pause must delay client traffic, +# and `txLinkNotReady` must pulse without leaking partial output. +# - Timing: The bench observes the imported loopback stream rather than fixed +# cycle delays because the TX path includes arbitration, checksum, pause, and +# export staging. + +import cocotb +import pytest +from pathlib import Path + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + ETHMAC_RTL_SOURCES, + FlatEmacEndpoint, + build_ethernet_frame, + build_ipv4_udp_frame, + build_pause_frame, + cycle, + expect_no_output, + frame_beats_from_bytes, + mac_config_word_from_wire, + pad_ethernet_frame_to_min_size, + payload_from_beats, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, + wait_signal_pulse, +) + + +WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacTxLoopbackWrapper.vhd" +ROCE_RTL_ROOT = Path(__file__).resolve().parents[3] / "ethernet" / "RoCEv2" / "rtl" +ROCE_ANALYSIS_SOURCES = [ + str(ROCE_RTL_ROOT / "RocePkg.vhd"), + *( + str(path) + for path in sorted(ROCE_RTL_ROOT.glob("*.vhd")) + if path.name != "RocePkg.vhd" + ), +] +LOCAL_MAC_CFG = mac_config_word_from_wire(0x001122334455) + + +@cocotb.test() +async def eth_mac_tx_test(dut): + bench = await setup_flat_emac_testbench( + dut, + source_prefix=None, + sink_prefix=None, + initial_values={ + "ethClkEn": 1, + "phyReady": 1, + "clientPause": 0, + "rxPauseReq": 0, + "rxPauseValue": 0, + "pauseEnable": 1, + "pauseTime": 0x0002, + "macAddress": LOCAL_MAC_CFG, + "ipCsumEn": 1, + "tcpCsumEn": 0, + "udpCsumEn": 1, + }, + ) + prim_source = FlatEmacEndpoint(dut, prefix="sPrim") + byp_source = FlatEmacEndpoint(dut, prefix="sByp") + sink = FlatEmacEndpoint(dut, prefix="mAxis") + prim_source.set_idle() + byp_source.set_idle() + + # Start with a checksum-cleared IPv4/UDP packet so the assembly path has + # to repair both headers before the exported frame is looped back. + repaired_frame = build_ipv4_udp_frame( + dst_mac=0x112233445566, + src_mac=0xAABBCCDDEEFF, + src_ip="10.1.0.1", + dst_ip="10.1.0.2", + src_port=0x1001, + dst_port=0x2002, + payload=b"eth-mac-tx-assembly" + bytes(24), + ) + repair_input = build_ipv4_udp_frame( + dst_mac=0x112233445566, + src_mac=0xAABBCCDDEEFF, + src_ip="10.1.0.1", + dst_ip="10.1.0.2", + src_port=0x1001, + dst_port=0x2002, + payload=b"eth-mac-tx-assembly" + bytes(24), + ip_checksum_override=0x0000, + udp_checksum_override=0x0000, + ) + repair_send = cocotb.start_soon( + send_contiguous_frame(prim_source, frame_beats_from_bytes(repair_input), clk=bench.clk) + ) + repair_observed = await recv_frame(sink, clk=bench.clk, timeout_cycles=256) + await repair_send + assert payload_from_beats(repair_observed) == repaired_frame + + # Launch primary and bypass sources together. The TxBypass assembly logic + # should select bypass first and only forward the held primary frame after. + primary_frame = build_ethernet_frame( + dst_mac=0x010203040506, + src_mac=0x0708090A0B0C, + eth_type=0x0801, + payload=bytes(range(48)), + ) + bypass_frame = build_ethernet_frame( + dst_mac=0x0D0E0F101112, + src_mac=0x131415161718, + eth_type=0x88B5, + payload=bytes(range(32)), + ) + primary_send = cocotb.start_soon( + send_contiguous_frame(prim_source, frame_beats_from_bytes(primary_frame), clk=bench.clk) + ) + bypass_send = cocotb.start_soon( + send_contiguous_frame(byp_source, frame_beats_from_bytes(bypass_frame), clk=bench.clk) + ) + first_observed = await recv_frame(sink, clk=bench.clk, timeout_cycles=256) + second_observed = await recv_frame(sink, clk=bench.clk, timeout_cycles=256) + await primary_send + await bypass_send + assert payload_from_beats(first_observed) == pad_ethernet_frame_to_min_size(bypass_frame) + assert payload_from_beats(second_observed) == primary_frame + + # Local pause generation must inject the protocol-defined pause frame. + pause_pulse = cocotb.start_soon(wait_signal_pulse(dut.pauseTx, clk=bench.clk, timeout_cycles=128)) + dut.clientPause.value = 1 + await cycle(bench.clk, 1) + dut.clientPause.value = 0 + pause_observed = await recv_frame(sink, clk=bench.clk, timeout_cycles=256) + await pause_pulse + assert payload_from_beats(pause_observed) == build_pause_frame(0x0002) + + # A received pause request should hold off the next payload briefly before + # it is finally allowed onto the wire. + dut.rxPauseValue.value = 2 + dut.rxPauseReq.value = 1 + await cycle(bench.clk, 1) + dut.rxPauseReq.value = 0 + + gated_frame = build_ethernet_frame( + dst_mac=0x212223242526, + src_mac=0x313233343536, + eth_type=0x9000, + payload=b"gated-after-rx-pause" + bytes(24), + ) + gated_send = cocotb.start_soon( + send_contiguous_frame(prim_source, frame_beats_from_bytes(gated_frame), clk=bench.clk) + ) + await expect_no_output(sink, clk=bench.clk, cycles=4) + gated_observed = await recv_frame(sink, clk=bench.clk, timeout_cycles=256) + await gated_send + assert payload_from_beats(gated_observed) == pad_ethernet_frame_to_min_size(gated_frame) + + # When the link is not ready the exporter must flag the condition and + # suppress visible output until the link recovers. + dut.phyReady.value = 0 + blocked_frame = build_ethernet_frame( + dst_mac=0x414243444546, + src_mac=0x515253545556, + eth_type=0x9001, + payload=bytes(range(40)), + ) + blocked_pulse = cocotb.start_soon( + wait_signal_pulse(dut.txLinkNotReady, clk=bench.clk, timeout_cycles=128) + ) + blocked_send = cocotb.start_soon( + send_contiguous_frame(prim_source, frame_beats_from_bytes(blocked_frame), clk=bench.clk) + ) + await blocked_send + await blocked_pulse + await expect_no_output(sink, clk=bench.clk, cycles=8) + assert int(dut.txUnderRun.value) == 0 + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="tx_assembly_loopback")]) +def test_EthMacTx(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ethmactxloopbackwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES + ROCE_ANALYSIS_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/EthMacCore/test_EthMacTxFifo.py b/tests/ethernet/EthMacCore/test_EthMacTxFifo.py new file mode 100644 index 0000000000..d83f16e7e6 --- /dev/null +++ b/tests/ethernet/EthMacCore/test_EthMacTxFifo.py @@ -0,0 +1,127 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Keep one asynchronous primary-path instance so the bench exercises +# the actual AXI Stream FIFO rather than the common-clock bypass shortcut. +# - Stimulus: Send one ordinary frame across the clock crossing, then hold the +# sink stalled while streaming a longer frame that can fill the FIFO deeply +# enough to deassert source `TREADY`. +# - Checks: Ordinary traffic must emerge unchanged, source backpressure must +# assert while the sink is blocked, and the queued frame must recover cleanly +# once downstream readiness returns. +# - Timing: The two clocks intentionally run at different periods, so the test +# waits on visible handshakes instead of assuming synchronous phasing. + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + ETHMAC_RTL_SOURCES, + FlatEmacEndpoint, + build_ethernet_frame, + cycle, + frame_beats_from_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, + start_clock, +) + + +WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacTxFifoWrapper.vhd" + + +async def reset_async_fifo(dut) -> None: + dut.sPrimRst.value = 1 + dut.mRst.value = 1 + await cycle(dut.sPrimClk, 4) + await cycle(dut.mClk, 2) + dut.sPrimRst.value = 0 + dut.mRst.value = 0 + await cycle(dut.sPrimClk, 2) + await cycle(dut.mClk, 2) + + +@cocotb.test() +async def eth_mac_tx_fifo_test(dut): + start_clock(dut.sPrimClk, period_ns=4.0) + start_clock(dut.mClk, period_ns=6.0) + + dut.mAxisTReady.setimmediatevalue(0) + + source = FlatEmacEndpoint(dut, prefix="sAxis") + sink = FlatEmacEndpoint(dut, prefix="mAxis") + source.set_idle() + + await reset_async_fifo(dut) + + # First prove the simple async path works when the sink is ready. + dut.mAxisTReady.value = 1 + clean_frame = build_ethernet_frame( + dst_mac=0x001122334455, + src_mac=0x66778899AABB, + eth_type=0x9000, + payload=bytes(range(80)), + ) + clean_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(clean_frame), clk=dut.sPrimClk) + ) + clean_observed = await recv_frame( + sink, + clk=dut.mClk, + ready_signal=dut.mAxisTReady, + timeout_cycles=256, + ) + await clean_send + assert payload_from_beats(clean_observed) == clean_frame + + # Stall the sink and stream enough data to fill the small TX FIFO so the + # source-side `TREADY` must eventually deassert. + dut.mAxisTReady.value = 0 + queued_frame = build_ethernet_frame( + dst_mac=0x123456789ABC, + src_mac=0x0F1E2D3C4B5A, + eth_type=0x9001, + payload=bytes((index % 256 for index in range(640))), + ) + queued_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(queued_frame), clk=dut.sPrimClk) + ) + for _ in range(512): + await cycle(dut.sPrimClk, 1) + if int(dut.sAxisTReady.value) == 0: + break + else: + raise AssertionError("Timed out waiting for TX FIFO backpressure") + + # Once downstream readiness returns, the blocked send coroutine should + # drain and the queued frame should appear intact on the MAC-facing side. + dut.mAxisTReady.value = 1 + queued_observed = await recv_frame( + sink, + clk=dut.mClk, + ready_signal=dut.mAxisTReady, + timeout_cycles=512, + ) + await queued_send + assert payload_from_beats(queued_observed) == queued_frame + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="tx_fifo_async_primary")]) +def test_EthMacTxFifo(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ethmactxfifowrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES + [WRAPPER_PATH]}, + ) From ed8324f87577093862c6927b4ce330d14eda9180 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 10 Apr 2026 22:10:48 -0700 Subject: [PATCH 09/92] Start IPv4 tests. --- .../IpV4Engine/wrappers/ArpEngineWrapper.vhd | 153 ++++++++++ .../IpV4Engine/wrappers/IcmpEngineWrapper.vhd | 99 +++++++ .../wrappers/IpV4EngineDeMuxWrapper.vhd | 122 ++++++++ .../wrappers/IpV4EngineRxWrapper.vhd | 123 ++++++++ .../wrappers/IpV4EngineTopWrapper.vhd | 212 ++++++++++++++ .../wrappers/IpV4EngineTxWrapper.vhd | 130 +++++++++ tests/ethernet/IpV4Engine/__init__.py | 9 + tests/ethernet/IpV4Engine/ipv4_test_utils.py | 269 ++++++++++++++++++ tests/ethernet/IpV4Engine/test_ArpEngine.py | 177 ++++++++++++ tests/ethernet/IpV4Engine/test_IcmpEngine.py | 138 +++++++++ tests/ethernet/IpV4Engine/test_IpV4Engine.py | 214 ++++++++++++++ .../IpV4Engine/test_IpV4EngineDeMux.py | 145 ++++++++++ .../ethernet/IpV4Engine/test_IpV4EngineRx.py | 159 +++++++++++ .../ethernet/IpV4Engine/test_IpV4EngineTx.py | 152 ++++++++++ 14 files changed, 2102 insertions(+) create mode 100644 ethernet/IpV4Engine/wrappers/ArpEngineWrapper.vhd create mode 100644 ethernet/IpV4Engine/wrappers/IcmpEngineWrapper.vhd create mode 100644 ethernet/IpV4Engine/wrappers/IpV4EngineDeMuxWrapper.vhd create mode 100644 ethernet/IpV4Engine/wrappers/IpV4EngineRxWrapper.vhd create mode 100644 ethernet/IpV4Engine/wrappers/IpV4EngineTopWrapper.vhd create mode 100644 ethernet/IpV4Engine/wrappers/IpV4EngineTxWrapper.vhd create mode 100644 tests/ethernet/IpV4Engine/__init__.py create mode 100644 tests/ethernet/IpV4Engine/ipv4_test_utils.py create mode 100644 tests/ethernet/IpV4Engine/test_ArpEngine.py create mode 100644 tests/ethernet/IpV4Engine/test_IcmpEngine.py create mode 100644 tests/ethernet/IpV4Engine/test_IpV4Engine.py create mode 100644 tests/ethernet/IpV4Engine/test_IpV4EngineDeMux.py create mode 100644 tests/ethernet/IpV4Engine/test_IpV4EngineRx.py create mode 100644 tests/ethernet/IpV4Engine/test_IpV4EngineTx.py diff --git a/ethernet/IpV4Engine/wrappers/ArpEngineWrapper.vhd b/ethernet/IpV4Engine/wrappers/ArpEngineWrapper.vhd new file mode 100644 index 0000000000..098243ab3f --- /dev/null +++ b/ethernet/IpV4Engine/wrappers/ArpEngineWrapper.vhd @@ -0,0 +1,153 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for ArpEngine +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity ArpEngineWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + CLK_FREQ_G : real := 100.0E+06); + port ( + clk : in sl; + rst : in sl; + localMac : in slv(47 downto 0); + localIp : in slv(31 downto 0); + reqTValid : in sl; + reqTData : in slv(127 downto 0); + reqTKeep : in slv(15 downto 0); + reqTLast : in sl; + reqTReady : out sl; + reqSof : in sl; + reqEofe : in sl; + ackTValid : out sl; + ackTData : out slv(127 downto 0); + ackTKeep : out slv(15 downto 0); + ackTLast : out sl; + ackTReady : in sl := '1'; + ackSof : out sl; + ackEofe : out sl; + sArpTValid : in sl; + sArpTData : in slv(127 downto 0); + sArpTKeep : in slv(15 downto 0); + sArpTLast : in sl; + sArpTReady : out sl; + sArpSof : in sl; + sArpEofe : in sl; + mArpTValid : out sl; + mArpTData : out slv(127 downto 0); + mArpTKeep : out slv(15 downto 0); + mArpTLast : out sl; + mArpTReady : in sl := '1'; + mArpSof : out sl; + mArpEofe : out sl); +end entity ArpEngineWrapper; + +architecture rtl of ArpEngineWrapper is + + signal reqMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal reqSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal ackMaster : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal ackSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal sArpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sArpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mArpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mArpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + -- Flatten the client ARP request sideband stream. + reqComb : process (reqEofe, reqSof, reqTData, reqTKeep, reqTLast, reqTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := reqTValid; + v.tData(127 downto 0) := reqTData; + v.tKeep(15 downto 0) := reqTKeep; + v.tLast := reqTLast; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, reqSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, reqEofe); + reqMaster <= v; + end process reqComb; + + -- Flatten the inbound ARP frame stream from the MAC side. + sArpComb : process (sArpEofe, sArpSof, sArpTData, sArpTKeep, sArpTLast, sArpTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sArpTValid; + v.tData(127 downto 0) := sArpTData; + v.tKeep(15 downto 0) := sArpTKeep; + v.tLast := sArpTLast; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sArpSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sArpEofe); + sArpMaster <= v; + end process sArpComb; + + reqTReady <= reqSlave(0).tReady; + sArpTReady <= sArpSlave.tReady; + ackSlave(0).tReady <= ackTReady; + mArpSlave.tReady <= mArpTReady; + + -- Re-expand the client-facing ARP acknowledgement stream. + ackView : process (ackMaster(0)) is + begin + ackTValid <= ackMaster(0).tValid; + ackTData <= ackMaster(0).tData(127 downto 0); + ackTKeep <= ackMaster(0).tKeep(15 downto 0); + ackTLast <= ackMaster(0).tLast; + ackSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, ackMaster(0), EMAC_SOF_BIT_C, 0); + ackEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, ackMaster(0), EMAC_EOFE_BIT_C); + end process ackView; + + -- Re-expand the outbound ARP frame stream for direct payload checks. + mArpView : process (mArpMaster) is + begin + mArpTValid <= mArpMaster.tValid; + mArpTData <= mArpMaster.tData(127 downto 0); + mArpTKeep <= mArpMaster.tKeep(15 downto 0); + mArpTLast <= mArpMaster.tLast; + mArpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mArpMaster, EMAC_SOF_BIT_C, 0); + mArpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mArpMaster, EMAC_EOFE_BIT_C); + end process mArpView; + + U_DUT : entity surf.ArpEngine + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + CLIENT_SIZE_G => 1, + CLK_FREQ_G => CLK_FREQ_G) + port map ( + localMac => localMac, + localIp => localIp, + arpReqMasters(0) => reqMaster, + arpReqSlaves => reqSlave, + arpAckMasters => ackMaster, + arpAckSlaves => ackSlave, + ibArpMaster => sArpMaster, + ibArpSlave => sArpSlave, + obArpMaster => mArpMaster, + obArpSlave => mArpSlave, + clk => clk, + rst => rst); + +end architecture rtl; diff --git a/ethernet/IpV4Engine/wrappers/IcmpEngineWrapper.vhd b/ethernet/IpV4Engine/wrappers/IcmpEngineWrapper.vhd new file mode 100644 index 0000000000..ae7c7c880a --- /dev/null +++ b/ethernet/IpV4Engine/wrappers/IcmpEngineWrapper.vhd @@ -0,0 +1,99 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for IcmpEngine +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity IcmpEngineWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false); + port ( + clk : in sl; + rst : in sl; + localIp : in slv(31 downto 0); + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTReady : in sl := '1'; + mAxisSof : out sl; + mAxisEofe : out sl); +end entity IcmpEngineWrapper; + +architecture rtl of IcmpEngineWrapper is + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + -- Flatten the ICMP pseudo-header stream presented by cocotb. + sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(127 downto 0) := sAxisTData; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); + sAxisMaster <= v; + end process sAxisComb; + + sAxisTReady <= sAxisSlave.tReady; + mAxisSlave.tReady <= mAxisTReady; + + -- Re-expand the outbound ICMP reply pseudo-header stream for checks. + mAxisView : process (mAxisMaster) is + begin + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + end process mAxisView; + + U_DUT : entity surf.IcmpEngine + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G) + port map ( + localIp => localIp, + ibIcmpMaster => sAxisMaster, + ibIcmpSlave => sAxisSlave, + obIcmpMaster => mAxisMaster, + obIcmpSlave => mAxisSlave, + clk => clk, + rst => rst); + +end architecture rtl; diff --git a/ethernet/IpV4Engine/wrappers/IpV4EngineDeMuxWrapper.vhd b/ethernet/IpV4Engine/wrappers/IpV4EngineDeMuxWrapper.vhd new file mode 100644 index 0000000000..7792bfb592 --- /dev/null +++ b/ethernet/IpV4Engine/wrappers/IpV4EngineDeMuxWrapper.vhd @@ -0,0 +1,122 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for IpV4EngineDeMux +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity IpV4EngineDeMuxWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false); + port ( + clk : in sl; + rst : in sl; + localMac : in slv(47 downto 0); + sMacTValid : in sl; + sMacTData : in slv(127 downto 0); + sMacTKeep : in slv(15 downto 0); + sMacTLast : in sl; + sMacTReady : out sl; + sMacSof : in sl; + sMacEofe : in sl; + mArpTValid : out sl; + mArpTData : out slv(127 downto 0); + mArpTKeep : out slv(15 downto 0); + mArpTLast : out sl; + mArpTReady : in sl := '1'; + mArpSof : out sl; + mArpEofe : out sl; + mIpv4TValid : out sl; + mIpv4TData : out slv(127 downto 0); + mIpv4TKeep : out slv(15 downto 0); + mIpv4TLast : out sl; + mIpv4TReady : in sl := '1'; + mIpv4Sof : out sl; + mIpv4Eofe : out sl); +end entity IpV4EngineDeMuxWrapper; + +architecture rtl of IpV4EngineDeMuxWrapper is + + signal sMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mArpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mArpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mIpv4Master : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mIpv4Slave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + -- Flatten the inbound MAC frame source for direct cocotb stimulus. + sMacComb : process (sMacEofe, sMacSof, sMacTData, sMacTKeep, sMacTLast, sMacTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sMacTValid; + v.tData(127 downto 0) := sMacTData; + v.tKeep(15 downto 0) := sMacTKeep; + v.tLast := sMacTLast; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sMacSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sMacEofe); + sMacMaster <= v; + end process sMacComb; + + sMacTReady <= sMacSlave.tReady; + mArpSlave.tReady <= mArpTReady; + mIpv4Slave.tReady <= mIpv4TReady; + + -- Present the selected ARP output stream as a flat cocotb-facing bus. + mArpView : process (mArpMaster) is + begin + mArpTValid <= mArpMaster.tValid; + mArpTData <= mArpMaster.tData(127 downto 0); + mArpTKeep <= mArpMaster.tKeep(15 downto 0); + mArpTLast <= mArpMaster.tLast; + mArpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mArpMaster, EMAC_SOF_BIT_C, 0); + mArpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mArpMaster, EMAC_EOFE_BIT_C); + end process mArpView; + + -- Present the selected IPv4 output stream as a second flat bus. + mIpv4View : process (mIpv4Master) is + begin + mIpv4TValid <= mIpv4Master.tValid; + mIpv4TData <= mIpv4Master.tData(127 downto 0); + mIpv4TKeep <= mIpv4Master.tKeep(15 downto 0); + mIpv4TLast <= mIpv4Master.tLast; + mIpv4Sof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mIpv4Master, EMAC_SOF_BIT_C, 0); + mIpv4Eofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mIpv4Master, EMAC_EOFE_BIT_C); + end process mIpv4View; + + U_DUT : entity surf.IpV4EngineDeMux + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G) + port map ( + localMac => localMac, + obMacMaster => sMacMaster, + obMacSlave => sMacSlave, + ibArpMaster => mArpMaster, + ibArpSlave => mArpSlave, + ibIpv4Master => mIpv4Master, + ibIpv4Slave => mIpv4Slave, + clk => clk, + rst => rst); + +end architecture rtl; diff --git a/ethernet/IpV4Engine/wrappers/IpV4EngineRxWrapper.vhd b/ethernet/IpV4Engine/wrappers/IpV4EngineRxWrapper.vhd new file mode 100644 index 0000000000..702024bd94 --- /dev/null +++ b/ethernet/IpV4Engine/wrappers/IpV4EngineRxWrapper.vhd @@ -0,0 +1,123 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for IpV4EngineRx +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity IpV4EngineRxWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false); + port ( + clk : in sl; + rst : in sl; + sIpv4TValid : in sl; + sIpv4TData : in slv(127 downto 0); + sIpv4TKeep : in slv(15 downto 0); + sIpv4TLast : in sl; + sIpv4TReady : out sl; + sIpv4Sof : in sl; + sIpv4Eofe : in sl; + mUdpTValid : out sl; + mUdpTData : out slv(127 downto 0); + mUdpTKeep : out slv(15 downto 0); + mUdpTLast : out sl; + mUdpTReady : in sl := '1'; + mUdpSof : out sl; + mUdpEofe : out sl; + mIcmpTValid : out sl; + mIcmpTData : out slv(127 downto 0); + mIcmpTKeep : out slv(15 downto 0); + mIcmpTLast : out sl; + mIcmpTReady : in sl := '1'; + mIcmpSof : out sl; + mIcmpEofe : out sl); +end entity IpV4EngineRxWrapper; + +architecture rtl of IpV4EngineRxWrapper is + + constant PROTOCOL_C : Slv8Array(1 downto 0) := (0 => UDP_C, 1 => ICMP_C); + + signal sIpv4Master : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sIpv4Slave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal localhostSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal ibProtocolMaster : AxiStreamMasterArray(1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal ibProtocolSlave : AxiStreamSlaveArray(1 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + +begin + + -- Flatten the inbound IPv4 MAC frame stream. + sIpv4Comb : process (sIpv4Eofe, sIpv4Sof, sIpv4TData, sIpv4TKeep, sIpv4TLast, sIpv4TValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sIpv4TValid; + v.tData(127 downto 0) := sIpv4TData; + v.tKeep(15 downto 0) := sIpv4TKeep; + v.tLast := sIpv4TLast; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sIpv4Sof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sIpv4Eofe); + sIpv4Master <= v; + end process sIpv4Comb; + + sIpv4TReady <= sIpv4Slave.tReady; + ibProtocolSlave(0).tReady <= mUdpTReady; + ibProtocolSlave(1).tReady <= mIcmpTReady; + + -- Expose the UDP-routed output slot directly to cocotb. + mUdpView : process (ibProtocolMaster(0)) is + begin + mUdpTValid <= ibProtocolMaster(0).tValid; + mUdpTData <= ibProtocolMaster(0).tData(127 downto 0); + mUdpTKeep <= ibProtocolMaster(0).tKeep(15 downto 0); + mUdpTLast <= ibProtocolMaster(0).tLast; + mUdpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, ibProtocolMaster(0), EMAC_SOF_BIT_C, 0); + mUdpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, ibProtocolMaster(0), EMAC_EOFE_BIT_C); + end process mUdpView; + + -- Expose the ICMP-routed output slot in the same flattened format. + mIcmpView : process (ibProtocolMaster(1)) is + begin + mIcmpTValid <= ibProtocolMaster(1).tValid; + mIcmpTData <= ibProtocolMaster(1).tData(127 downto 0); + mIcmpTKeep <= ibProtocolMaster(1).tKeep(15 downto 0); + mIcmpTLast <= ibProtocolMaster(1).tLast; + mIcmpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, ibProtocolMaster(1), EMAC_SOF_BIT_C, 0); + mIcmpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, ibProtocolMaster(1), EMAC_EOFE_BIT_C); + end process mIcmpView; + + U_DUT : entity surf.IpV4EngineRx + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + PROTOCOL_SIZE_G => 2, + PROTOCOL_G => PROTOCOL_C) + port map ( + ibIpv4Master => sIpv4Master, + ibIpv4Slave => sIpv4Slave, + localhostMaster => AXI_STREAM_MASTER_INIT_C, + localhostSlave => localhostSlave, + ibProtocolMasters => ibProtocolMaster, + ibProtocolSlaves => ibProtocolSlave, + clk => clk, + rst => rst); + +end architecture rtl; diff --git a/ethernet/IpV4Engine/wrappers/IpV4EngineTopWrapper.vhd b/ethernet/IpV4Engine/wrappers/IpV4EngineTopWrapper.vhd new file mode 100644 index 0000000000..75cc47c08e --- /dev/null +++ b/ethernet/IpV4Engine/wrappers/IpV4EngineTopWrapper.vhd @@ -0,0 +1,212 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for IpV4Engine +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity IpV4EngineTopWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + CLK_FREQ_G : real := 100.0E+06; + TTL_G : slv(7 downto 0) := x"20"); + port ( + clk : in sl; + rst : in sl; + localMac : in slv(47 downto 0); + localIp : in slv(31 downto 0); + sMacTValid : in sl; + sMacTData : in slv(127 downto 0); + sMacTKeep : in slv(15 downto 0); + sMacTLast : in sl; + sMacTReady : out sl; + sMacSof : in sl; + sMacEofe : in sl; + mMacTValid : out sl; + mMacTData : out slv(127 downto 0); + mMacTKeep : out slv(15 downto 0); + mMacTLast : out sl; + mMacTReady : in sl := '1'; + mMacSof : out sl; + mMacEofe : out sl; + sProtTValid : in sl; + sProtTData : in slv(127 downto 0); + sProtTKeep : in slv(15 downto 0); + sProtTLast : in sl; + sProtTReady : out sl; + sProtSof : in sl; + sProtEofe : in sl; + mProtTValid : out sl; + mProtTData : out slv(127 downto 0); + mProtTKeep : out slv(15 downto 0); + mProtTLast : out sl; + mProtTReady : in sl := '1'; + mProtSof : out sl; + mProtEofe : out sl; + arpReqTValid : in sl; + arpReqTData : in slv(127 downto 0); + arpReqTKeep : in slv(15 downto 0); + arpReqTLast : in sl; + arpReqTReady : out sl; + arpReqSof : in sl; + arpReqEofe : in sl; + arpAckTValid : out sl; + arpAckTData : out slv(127 downto 0); + arpAckTKeep : out slv(15 downto 0); + arpAckTLast : out sl; + arpAckTReady : in sl := '1'; + arpAckSof : out sl; + arpAckEofe : out sl); +end entity IpV4EngineTopWrapper; + +architecture rtl of IpV4EngineTopWrapper is + + constant PROTOCOL_C : Slv8Array(0 downto 0) := (0 => UDP_C); + + signal sMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal sProtMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sProtSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal mProtMaster : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal mProtSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal arpReqMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal arpReqSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal arpAckMaster : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal arpAckSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal igmpIp : Slv32Array(0 downto 0) := (others => (others => '0')); + +begin + + -- Flatten the inbound MAC stream for end-to-end top-level stimulus. + sMacComb : process (sMacEofe, sMacSof, sMacTData, sMacTKeep, sMacTLast, sMacTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sMacTValid; + v.tData(127 downto 0) := sMacTData; + v.tKeep(15 downto 0) := sMacTKeep; + v.tLast := sMacTLast; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sMacSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sMacEofe); + sMacMaster <= v; + end process sMacComb; + + -- Flatten the single external protocol-engine source slot. + sProtComb : process (sProtEofe, sProtSof, sProtTData, sProtTKeep, sProtTLast, sProtTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sProtTValid; + v.tData(127 downto 0) := sProtTData; + v.tKeep(15 downto 0) := sProtTKeep; + v.tLast := sProtTLast; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sProtSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sProtEofe); + sProtMaster <= v; + end process sProtComb; + + -- Flatten the single ARP client request slot. + arpReqComb : process (arpReqEofe, arpReqSof, arpReqTData, arpReqTKeep, arpReqTLast, arpReqTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := arpReqTValid; + v.tData(127 downto 0) := arpReqTData; + v.tKeep(15 downto 0) := arpReqTKeep; + v.tLast := arpReqTLast; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, arpReqSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, arpReqEofe); + arpReqMaster <= v; + end process arpReqComb; + + sMacTReady <= sMacSlave.tReady; + sProtTReady <= sProtSlave(0).tReady; + arpReqTReady <= arpReqSlave(0).tReady; + mMacSlave.tReady <= mMacTReady; + mProtSlave(0).tReady <= mProtTReady; + arpAckSlave(0).tReady <= arpAckTReady; + + -- Re-expand the top-level outbound MAC stream. + mMacView : process (mMacMaster) is + begin + mMacTValid <= mMacMaster.tValid; + mMacTData <= mMacMaster.tData(127 downto 0); + mMacTKeep <= mMacMaster.tKeep(15 downto 0); + mMacTLast <= mMacMaster.tLast; + mMacSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mMacMaster, EMAC_SOF_BIT_C, 0); + mMacEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mMacMaster, EMAC_EOFE_BIT_C); + end process mMacView; + + -- Re-expand the exposed protocol slot that receives inbound UDP traffic. + mProtView : process (mProtMaster(0)) is + begin + mProtTValid <= mProtMaster(0).tValid; + mProtTData <= mProtMaster(0).tData(127 downto 0); + mProtTKeep <= mProtMaster(0).tKeep(15 downto 0); + mProtTLast <= mProtMaster(0).tLast; + mProtSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mProtMaster(0), EMAC_SOF_BIT_C, 0); + mProtEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mProtMaster(0), EMAC_EOFE_BIT_C); + end process mProtView; + + -- Re-expand the single client ARP acknowledgement slot. + arpAckView : process (arpAckMaster(0)) is + begin + arpAckTValid <= arpAckMaster(0).tValid; + arpAckTData <= arpAckMaster(0).tData(127 downto 0); + arpAckTKeep <= arpAckMaster(0).tKeep(15 downto 0); + arpAckTLast <= arpAckMaster(0).tLast; + arpAckSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, arpAckMaster(0), EMAC_SOF_BIT_C, 0); + arpAckEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, arpAckMaster(0), EMAC_EOFE_BIT_C); + end process arpAckView; + + U_DUT : entity surf.IpV4Engine + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + PROTOCOL_SIZE_G => 1, + PROTOCOL_G => PROTOCOL_C, + CLIENT_SIZE_G => 1, + CLK_FREQ_G => CLK_FREQ_G, + TTL_G => TTL_G, + IGMP_G => false, + IGMP_GRP_SIZE => 1) + port map ( + localMac => localMac, + localIp => localIp, + igmpIp => igmpIp, + obMacMaster => sMacMaster, + obMacSlave => sMacSlave, + ibMacMaster => mMacMaster, + ibMacSlave => mMacSlave, + obProtocolMasters => (0 => sProtMaster), + obProtocolSlaves => sProtSlave, + ibProtocolMasters => mProtMaster, + ibProtocolSlaves => mProtSlave, + arpReqMasters => (0 => arpReqMaster), + arpReqSlaves => arpReqSlave, + arpAckMasters => arpAckMaster, + arpAckSlaves => arpAckSlave, + clk => clk, + rst => rst); + +end architecture rtl; diff --git a/ethernet/IpV4Engine/wrappers/IpV4EngineTxWrapper.vhd b/ethernet/IpV4Engine/wrappers/IpV4EngineTxWrapper.vhd new file mode 100644 index 0000000000..09031dc84f --- /dev/null +++ b/ethernet/IpV4Engine/wrappers/IpV4EngineTxWrapper.vhd @@ -0,0 +1,130 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for IpV4EngineTx +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity IpV4EngineTxWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + TTL_G : slv(7 downto 0) := x"20"); + port ( + clk : in sl; + rst : in sl; + localMac : in slv(47 downto 0); + sProtTValid : in sl; + sProtTData : in slv(127 downto 0); + sProtTKeep : in slv(15 downto 0); + sProtTLast : in sl; + sProtTReady : out sl; + sProtSof : in sl; + sProtEofe : in sl; + mIpv4TValid : out sl; + mIpv4TData : out slv(127 downto 0); + mIpv4TKeep : out slv(15 downto 0); + mIpv4TLast : out sl; + mIpv4TReady : in sl := '1'; + mIpv4Sof : out sl; + mIpv4Eofe : out sl; + mLocalTValid : out sl; + mLocalTData : out slv(127 downto 0); + mLocalTKeep : out slv(15 downto 0); + mLocalTLast : out sl; + mLocalTReady : in sl := '1'; + mLocalSof : out sl; + mLocalEofe : out sl); +end entity IpV4EngineTxWrapper; + +architecture rtl of IpV4EngineTxWrapper is + + constant PROTOCOL_C : Slv8Array(0 downto 0) := (0 => UDP_C); + + signal sProtMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sProtSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal obProtocolMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal mIpv4Master : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mIpv4Slave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mLocalMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mLocalSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + -- Flatten the single protocol-source stream that feeds the TX engine. + sProtComb : process (sProtEofe, sProtSof, sProtTData, sProtTKeep, sProtTLast, sProtTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sProtTValid; + v.tData(127 downto 0) := sProtTData; + v.tKeep(15 downto 0) := sProtTKeep; + v.tLast := sProtTLast; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sProtSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sProtEofe); + sProtMaster <= v; + end process sProtComb; + + obProtocolMasters(0) <= sProtMaster; + sProtTReady <= sProtSlave(0).tReady; + mIpv4Slave.tReady <= mIpv4TReady; + mLocalSlave.tReady <= mLocalTReady; + + -- Re-expand the external-IPv4 output path. + mIpv4View : process (mIpv4Master) is + begin + mIpv4TValid <= mIpv4Master.tValid; + mIpv4TData <= mIpv4Master.tData(127 downto 0); + mIpv4TKeep <= mIpv4Master.tKeep(15 downto 0); + mIpv4TLast <= mIpv4Master.tLast; + mIpv4Sof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mIpv4Master, EMAC_SOF_BIT_C, 0); + mIpv4Eofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mIpv4Master, EMAC_EOFE_BIT_C); + end process mIpv4View; + + -- Re-expand the localhost shortcut output path separately. + mLocalView : process (mLocalMaster) is + begin + mLocalTValid <= mLocalMaster.tValid; + mLocalTData <= mLocalMaster.tData(127 downto 0); + mLocalTKeep <= mLocalMaster.tKeep(15 downto 0); + mLocalTLast <= mLocalMaster.tLast; + mLocalSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mLocalMaster, EMAC_SOF_BIT_C, 0); + mLocalEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mLocalMaster, EMAC_EOFE_BIT_C); + end process mLocalView; + + U_DUT : entity surf.IpV4EngineTx + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + PROTOCOL_SIZE_G => 1, + PROTOCOL_G => PROTOCOL_C, + TTL_G => TTL_G) + port map ( + localMac => localMac, + obIpv4Master => mIpv4Master, + obIpv4Slave => mIpv4Slave, + localhostMaster => mLocalMaster, + localhostSlave => mLocalSlave, + obProtocolMasters => obProtocolMasters, + obProtocolSlaves => sProtSlave, + clk => clk, + rst => rst); + +end architecture rtl; diff --git a/tests/ethernet/IpV4Engine/__init__.py b/tests/ethernet/IpV4Engine/__init__.py new file mode 100644 index 0000000000..b0085f1a17 --- /dev/null +++ b/tests/ethernet/IpV4Engine/__init__.py @@ -0,0 +1,9 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## diff --git a/tests/ethernet/IpV4Engine/ipv4_test_utils.py b/tests/ethernet/IpV4Engine/ipv4_test_utils.py new file mode 100644 index 0000000000..8f8e3bdbde --- /dev/null +++ b/tests/ethernet/IpV4Engine/ipv4_test_utils.py @@ -0,0 +1,269 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +from __future__ import annotations + +import ipaddress +from pathlib import Path + +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + build_ethernet_frame, + build_ipv4_header, + build_udp_header, + internet_checksum, + ipv4_to_bytes, + mac_to_bytes, +) + + +IPV4_RTL_SOURCES = [ + str(path) + for path in sorted((Path(__file__).resolve().parents[3] / "ethernet" / "IpV4Engine" / "rtl").glob("*.vhd")) +] + + +def ipv4_config_word(address: str) -> int: + # The flattened cocotb wrappers expose byte-stream traffic lane-first, so + # config words that are compared directly against stream slices need the + # same least-significant-lane ordering. + return int.from_bytes(ipaddress.IPv4Address(address).packed[::-1], byteorder="big") + + +def build_ipv4_frame( + *, + dst_mac: int, + src_mac: int, + src_ip: str, + dst_ip: str, + protocol: int, + payload: bytes, + identification: int = 0x1234, + ttl: int = 0x20, + checksum_override: int | None = None, +) -> bytes: + ipv4_header = build_ipv4_header( + src_ip=src_ip, + dst_ip=dst_ip, + protocol=protocol, + payload_length=len(payload), + identification=identification, + ttl=ttl, + checksum_override=checksum_override, + ) + return build_ethernet_frame( + dst_mac=dst_mac, + src_mac=src_mac, + eth_type=0x0800, + payload=ipv4_header + payload, + ) + + +def build_ipv4_protocol_pseudo_frame( + *, + mac_address: int, + first_ip: str, + second_ip: str, + protocol: int, + payload: bytes, +) -> bytes: + # The IPv4 engines exchange a private pseudo-header format: + # MAC address, two zero bytes, first IP word, second IP word, then a + # 4-byte shim of zero/protocol/protocol-length before the protocol payload. + # The meaning of the two IP words depends on direction: + # - RX output: source IP then destination IP + # - TX input: source IP then destination IP + return ( + mac_to_bytes(mac_address) + + b"\x00\x00" + + ipv4_to_bytes(first_ip) + + ipv4_to_bytes(second_ip) + + bytes([0x00, protocol & 0xFF]) + + len(payload).to_bytes(2, byteorder="big") + + payload + ) + + +def build_ipv4_rx_pseudo_frame( + *, + src_mac: int, + src_ip: str, + dst_ip: str, + protocol: int, + payload: bytes, +) -> bytes: + return build_ipv4_protocol_pseudo_frame( + mac_address=src_mac, + first_ip=src_ip, + second_ip=dst_ip, + protocol=protocol, + payload=payload, + ) + + +def build_ipv4_tx_pseudo_frame( + *, + dst_mac: int, + src_ip: str, + dst_ip: str, + protocol: int, + payload: bytes, +) -> bytes: + return build_ipv4_protocol_pseudo_frame( + mac_address=dst_mac, + first_ip=src_ip, + second_ip=dst_ip, + protocol=protocol, + payload=payload, + ) + + +def build_ipv4_tx_wire_frame( + *, + dst_mac: int, + src_mac: int, + src_ip: str, + dst_ip: str, + protocol: int, + payload: bytes, + identification: int = 0x0000, + ttl: int = 0x20, +) -> bytes: + # IpV4EngineTx leaves the IPv4 total length and checksum fields clear for + # downstream MAC checksum/length logic to repair. + ipv4_header = ( + bytes([0x45, 0x00]) + + b"\x00\x00" + + identification.to_bytes(2, byteorder="big") + + bytes([0x40, 0x00, ttl, protocol, 0x00, 0x00]) + + ipv4_to_bytes(src_ip) + + ipv4_to_bytes(dst_ip) + ) + return build_ethernet_frame( + dst_mac=dst_mac, + src_mac=src_mac, + eth_type=0x0800, + payload=ipv4_header + payload, + ) + + +def build_arp_frame( + *, + opcode: int, + sender_mac: int, + sender_ip: str, + target_mac: int, + target_ip: str, + dst_mac: int | None = None, + src_mac: int | None = None, +) -> bytes: + if dst_mac is None: + dst_mac = 0xFFFFFFFFFFFF if opcode == 1 else target_mac + if src_mac is None: + src_mac = sender_mac + + payload = ( + (0x0001).to_bytes(2, byteorder="big") + + (0x0800).to_bytes(2, byteorder="big") + + bytes([0x06, 0x04]) + + opcode.to_bytes(2, byteorder="big") + + mac_to_bytes(sender_mac) + + ipv4_to_bytes(sender_ip) + + mac_to_bytes(target_mac) + + ipv4_to_bytes(target_ip) + ) + return build_ethernet_frame( + dst_mac=dst_mac, + src_mac=src_mac, + eth_type=0x0806, + payload=payload, + ) + + +def build_icmp_echo_packet( + *, + payload: bytes, + identifier: int = 0x1234, + sequence: int = 0x0001, + icmp_type: int = 0x08, + code: int = 0x00, +) -> bytes: + header_wo_checksum = bytes([icmp_type, code]) + b"\x00\x00" + header_wo_checksum += identifier.to_bytes(2, byteorder="big") + header_wo_checksum += sequence.to_bytes(2, byteorder="big") + checksum = internet_checksum(header_wo_checksum + payload) + return ( + bytes([icmp_type, code]) + + checksum.to_bytes(2, byteorder="big") + + identifier.to_bytes(2, byteorder="big") + + sequence.to_bytes(2, byteorder="big") + + payload + ) + + +def build_icmp_echo_reply_packet( + *, + payload: bytes, + identifier: int = 0x1234, + sequence: int = 0x0001, +) -> bytes: + return build_icmp_echo_packet( + payload=payload, + identifier=identifier, + sequence=sequence, + icmp_type=0x00, + code=0x00, + ) + + +def build_icmp_echo_frame( + *, + dst_mac: int, + src_mac: int, + src_ip: str, + dst_ip: str, + payload: bytes, + identifier: int = 0x1234, + sequence: int = 0x0001, +) -> bytes: + icmp_payload = build_icmp_echo_packet( + payload=payload, + identifier=identifier, + sequence=sequence, + icmp_type=0x08, + code=0x00, + ) + return build_ipv4_frame( + dst_mac=dst_mac, + src_mac=src_mac, + src_ip=src_ip, + dst_ip=dst_ip, + protocol=0x01, + payload=icmp_payload, + ) + + +def build_ipv4_udp_payload( + *, + src_port: int, + dst_port: int, + payload: bytes, + src_ip: str, + dst_ip: str, + udp_checksum_override: int | None = None, +) -> bytes: + udp_header = build_udp_header( + src_port=src_port, + dst_port=dst_port, + payload=payload, + src_ip=src_ip, + dst_ip=dst_ip, + checksum_override=udp_checksum_override, + ) + return udp_header + payload diff --git a/tests/ethernet/IpV4Engine/test_ArpEngine.py b/tests/ethernet/IpV4Engine/test_ArpEngine.py new file mode 100644 index 0000000000..96f6e96e67 --- /dev/null +++ b/tests/ethernet/IpV4Engine/test_ArpEngine.py @@ -0,0 +1,177 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Stimulus: Exercise the ARP engine with a localhost lookup, a remote lookup +# that requires an outbound request and inbound reply, and an inbound ARP +# request addressed to the local host. +# - Checks: The localhost lookup must acknowledge immediately, the remote +# lookup must emit the expected ARP request then acknowledge with the reply +# MAC address, and an inbound request must generate a valid reply frame. +# - Timing: The test uses real ready/valid handshakes for both client and MAC +# sides so request/ack routing remains visible. + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + FlatEmacEndpoint, + frame_beats_from_bytes, + mac_config_word_from_wire, + payload_from_beat, + payload_from_beats, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, +) +from tests.ethernet.IpV4Engine.ipv4_test_utils import ( + IPV4_RTL_SOURCES, + build_arp_frame, + ipv4_config_word, + ipv4_to_bytes, +) + + +WRAPPER_PATH = "ethernet/IpV4Engine/wrappers/ArpEngineWrapper.vhd" + +LOCAL_MAC_WIRE = 0x001122334455 +LOCAL_MAC_CFG = mac_config_word_from_wire(LOCAL_MAC_WIRE) +REMOTE_MAC_WIRE = 0x665544332211 +LOCAL_IP = "192.168.50.10" +LOCAL_IP_CFG = ipv4_config_word(LOCAL_IP) +REMOTE_IP = "192.168.50.11" + + +async def setup_arp_bench(dut): + bench = await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + source_prefix="sArp", + sink_prefix="mArp", + initial_values={ + "localMac": LOCAL_MAC_CFG, + "localIp": LOCAL_IP_CFG, + "mArpTReady": 0, + "ackTReady": 0, + }, + ) + s_arp_source = bench.source + m_arp_sink = bench.sink + assert s_arp_source is not None + assert m_arp_sink is not None + + req_source = FlatEmacEndpoint(dut, prefix="req") + ack_sink = FlatEmacEndpoint(dut, prefix="ack") + req_source.set_idle() + return bench, s_arp_source, m_arp_sink, req_source, ack_sink + + +@cocotb.test() +async def arp_engine_localhost_lookup_test(dut): + bench, _, _, req_source, ack_sink = await setup_arp_bench(dut) + + localhost_lookup = frame_beats_from_bytes(ipv4_to_bytes(LOCAL_IP))[0] + req_source.drive(localhost_lookup) + localhost_ack = await ack_sink.recv( + clk=bench.clk, + ready_signal=dut.ackTReady, + ) + req_source.set_idle() + assert payload_from_beat(localhost_ack)[:6] == LOCAL_MAC_WIRE.to_bytes(6, byteorder="big") + + +@cocotb.test() +async def arp_engine_remote_lookup_ack_test(dut): + bench, s_arp_source, m_arp_sink, req_source, ack_sink = await setup_arp_bench(dut) + + remote_lookup = frame_beats_from_bytes(ipv4_to_bytes(REMOTE_IP))[0] + # The ARP client request is level-sensitive until the engine resolves the + # lookup, so hold it asserted across both the outbound request and reply. + req_source.drive(remote_lookup) + request_observed = await recv_frame( + m_arp_sink, + clk=bench.clk, + ready_signal=dut.mArpTReady, + timeout_cycles=256, + ) + request_expected = build_arp_frame( + opcode=1, + sender_mac=LOCAL_MAC_WIRE, + sender_ip=LOCAL_IP, + target_mac=0xFFFFFFFFFFFF, + target_ip=REMOTE_IP, + ) + assert payload_from_beats(request_observed) == request_expected + + arp_reply = build_arp_frame( + opcode=2, + sender_mac=REMOTE_MAC_WIRE, + sender_ip=REMOTE_IP, + target_mac=LOCAL_MAC_WIRE, + target_ip=LOCAL_IP, + dst_mac=LOCAL_MAC_WIRE, + src_mac=REMOTE_MAC_WIRE, + ) + reply_send = cocotb.start_soon( + send_contiguous_frame(s_arp_source, frame_beats_from_bytes(arp_reply), clk=bench.clk) + ) + remote_ack = await ack_sink.recv( + clk=bench.clk, + ready_signal=dut.ackTReady, + ) + req_source.set_idle() + await reply_send + assert payload_from_beat(remote_ack)[:6] == REMOTE_MAC_WIRE.to_bytes(6, byteorder="big") + + +@cocotb.test() +async def arp_engine_inbound_request_reply_test(dut): + bench, s_arp_source, m_arp_sink, _, _ = await setup_arp_bench(dut) + + inbound_request = build_arp_frame( + opcode=1, + sender_mac=REMOTE_MAC_WIRE, + sender_ip=REMOTE_IP, + target_mac=0xFFFFFFFFFFFF, + target_ip=LOCAL_IP, + ) + request_send = cocotb.start_soon( + send_contiguous_frame(s_arp_source, frame_beats_from_bytes(inbound_request), clk=bench.clk) + ) + reply_observed = await recv_frame( + m_arp_sink, + clk=bench.clk, + ready_signal=dut.mArpTReady, + timeout_cycles=256, + ) + await request_send + reply_expected = build_arp_frame( + opcode=2, + sender_mac=LOCAL_MAC_WIRE, + sender_ip=LOCAL_IP, + target_mac=REMOTE_MAC_WIRE, + target_ip=REMOTE_IP, + dst_mac=REMOTE_MAC_WIRE, + src_mac=LOCAL_MAC_WIRE, + ) + assert payload_from_beats(reply_observed) == reply_expected + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="arp_engine_wrapper")]) +def test_ArpEngine(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.arpenginewrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": IPV4_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/IpV4Engine/test_IcmpEngine.py b/tests/ethernet/IpV4Engine/test_IcmpEngine.py new file mode 100644 index 0000000000..8372fdc0f7 --- /dev/null +++ b/tests/ethernet/IpV4Engine/test_IcmpEngine.py @@ -0,0 +1,138 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Stimulus: Present ICMP pseudo-header traffic exactly as IpV4EngineRx would +# emit it, including a valid echo request, a non-local request, and a +# non-echo ICMP packet. +# - Checks: Only an echo request addressed to the configured local IP may +# produce a response, and that response must be a correctly swapped echo +# reply pseudo-frame. +# - Timing: The bench waits on AXIS visibility so the assertions remain stable +# across internal pipeline depth changes. + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + expect_no_output, + frame_beats_from_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, +) +from tests.ethernet.IpV4Engine.ipv4_test_utils import ( + IPV4_RTL_SOURCES, + build_icmp_echo_packet, + build_icmp_echo_reply_packet, + build_ipv4_rx_pseudo_frame, + build_ipv4_tx_pseudo_frame, + ipv4_config_word, +) + + +WRAPPER_PATH = "ethernet/IpV4Engine/wrappers/IcmpEngineWrapper.vhd" + +LOCAL_IP = "192.168.20.10" +LOCAL_IP_CFG = ipv4_config_word(LOCAL_IP) +REMOTE_IP = "192.168.20.11" +REMOTE_MAC = 0x665544332211 + + +@cocotb.test() +async def icmp_engine_reply_filtering_test(dut): + bench = await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + source_prefix="sAxis", + sink_prefix="mAxis", + initial_values={ + "localIp": LOCAL_IP_CFG, + "mAxisTReady": 0, + }, + ) + source = bench.source + sink = bench.sink + assert source is not None + assert sink is not None + + echo_payload = b"icmp-echo-request-payload" + echo_request = build_ipv4_rx_pseudo_frame( + src_mac=REMOTE_MAC, + src_ip=REMOTE_IP, + dst_ip=LOCAL_IP, + protocol=0x01, + payload=build_icmp_echo_packet( + payload=echo_payload, + identifier=0x3344, + sequence=0x0102, + ), + ) + expected_reply = build_ipv4_tx_pseudo_frame( + dst_mac=REMOTE_MAC, + src_ip=LOCAL_IP, + dst_ip=REMOTE_IP, + protocol=0x01, + payload=build_icmp_echo_reply_packet( + payload=echo_payload, + identifier=0x3344, + sequence=0x0102, + ), + ) + + reply_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(echo_request), clk=bench.clk) + ) + reply_observed = await recv_frame( + sink, + clk=bench.clk, + ready_signal=dut.mAxisTReady, + timeout_cycles=128, + ) + await reply_send + assert payload_from_beats(reply_observed) == expected_reply + + non_local_request = build_ipv4_rx_pseudo_frame( + src_mac=REMOTE_MAC, + src_ip=REMOTE_IP, + dst_ip="192.168.20.99", + protocol=0x01, + payload=build_icmp_echo_packet(payload=b"non-local"), + ) + await send_contiguous_frame(source, frame_beats_from_bytes(non_local_request), clk=bench.clk) + await expect_no_output(sink, clk=bench.clk, cycles=12) + + non_echo_message = build_ipv4_rx_pseudo_frame( + src_mac=REMOTE_MAC, + src_ip=REMOTE_IP, + dst_ip=LOCAL_IP, + protocol=0x01, + payload=build_icmp_echo_packet( + payload=b"not-an-echo-request", + icmp_type=0x03, + code=0x01, + ), + ) + await send_contiguous_frame(source, frame_beats_from_bytes(non_echo_message), clk=bench.clk) + await expect_no_output(sink, clk=bench.clk, cycles=12) + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="icmp_engine_wrapper")]) +def test_IcmpEngine(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.icmpenginewrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": IPV4_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/IpV4Engine/test_IpV4Engine.py b/tests/ethernet/IpV4Engine/test_IpV4Engine.py new file mode 100644 index 0000000000..76a74d2177 --- /dev/null +++ b/tests/ethernet/IpV4Engine/test_IpV4Engine.py @@ -0,0 +1,214 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Stimulus: Exercise the full IPv4 top with three focused scenarios: +# inbound UDP routing, inbound ICMP echo handling, and ARP client lookup. +# - Checks: UDP traffic must emerge on the protocol output slot as the expected +# pseudo-header frame, ICMP echo requests must produce outbound reply frames, +# and ARP requests must round-trip through the top-level ARP client ports. +# - Timing: Each scenario uses handshaked sources and sinks so the top-level +# assembly is verified through its real interfaces instead of local shortcuts. + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + FlatEmacEndpoint, + frame_beats_from_bytes, + mac_config_word_from_wire, + payload_from_beat, + payload_from_beats, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, +) +from tests.ethernet.IpV4Engine.ipv4_test_utils import ( + IPV4_RTL_SOURCES, + build_arp_frame, + build_icmp_echo_frame, + build_icmp_echo_reply_packet, + build_ipv4_rx_pseudo_frame, + build_ipv4_tx_wire_frame, + build_ipv4_udp_payload, + build_ipv4_frame, + ipv4_config_word, + ipv4_to_bytes, +) + + +WRAPPER_PATH = "ethernet/IpV4Engine/wrappers/IpV4EngineTopWrapper.vhd" + +LOCAL_MAC_WIRE = 0x001122334455 +LOCAL_MAC_CFG = mac_config_word_from_wire(LOCAL_MAC_WIRE) +REMOTE_MAC_WIRE = 0x665544332211 +LOCAL_IP = "192.168.60.10" +LOCAL_IP_CFG = ipv4_config_word(LOCAL_IP) +REMOTE_IP = "192.168.60.11" + + +async def setup_top_bench(dut): + bench = await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + source_prefix="sMac", + initial_values={ + "localMac": LOCAL_MAC_CFG, + "localIp": LOCAL_IP_CFG, + "mMacTReady": 0, + "mProtTReady": 0, + "arpAckTReady": 0, + }, + ) + assert bench.source is not None + mac_sink = FlatEmacEndpoint(dut, prefix="mMac") + prot_sink = FlatEmacEndpoint(dut, prefix="mProt") + prot_source = FlatEmacEndpoint(dut, prefix="sProt") + arp_req_source = FlatEmacEndpoint(dut, prefix="arpReq") + arp_ack_sink = FlatEmacEndpoint(dut, prefix="arpAck") + prot_source.set_idle() + arp_req_source.set_idle() + return bench, mac_sink, prot_sink, prot_source, arp_req_source, arp_ack_sink + + +@cocotb.test() +async def ipv4_top_udp_routing_test(dut): + bench, _, prot_sink, _, _, _ = await setup_top_bench(dut) + + udp_payload = build_ipv4_udp_payload( + src_port=0x2001, + dst_port=0x2002, + payload=b"top-level-udp-routing", + src_ip=REMOTE_IP, + dst_ip=LOCAL_IP, + ) + udp_frame = build_ipv4_frame( + dst_mac=LOCAL_MAC_WIRE, + src_mac=REMOTE_MAC_WIRE, + src_ip=REMOTE_IP, + dst_ip=LOCAL_IP, + protocol=0x11, + payload=udp_payload, + ) + udp_expected = build_ipv4_rx_pseudo_frame( + src_mac=REMOTE_MAC_WIRE, + src_ip=REMOTE_IP, + dst_ip=LOCAL_IP, + protocol=0x11, + payload=udp_payload, + ) + + udp_send = cocotb.start_soon( + send_contiguous_frame(bench.source, frame_beats_from_bytes(udp_frame), clk=bench.clk) + ) + udp_observed = await recv_frame( + prot_sink, + clk=bench.clk, + ready_signal=dut.mProtTReady, + timeout_cycles=256, + ) + await udp_send + assert payload_from_beats(udp_observed) == udp_expected + + +@cocotb.test() +async def ipv4_top_icmp_echo_reply_test(dut): + bench, mac_sink, _, _, _, _ = await setup_top_bench(dut) + + icmp_frame = build_icmp_echo_frame( + dst_mac=LOCAL_MAC_WIRE, + src_mac=REMOTE_MAC_WIRE, + src_ip=REMOTE_IP, + dst_ip=LOCAL_IP, + payload=b"top-level-icmp", + identifier=0x7788, + sequence=0x0304, + ) + expected_reply = build_ipv4_tx_wire_frame( + dst_mac=REMOTE_MAC_WIRE, + src_mac=LOCAL_MAC_WIRE, + src_ip=LOCAL_IP, + dst_ip=REMOTE_IP, + protocol=0x01, + payload=build_icmp_echo_reply_packet( + payload=b"top-level-icmp", + identifier=0x7788, + sequence=0x0304, + ), + ) + + icmp_send = cocotb.start_soon( + send_contiguous_frame(bench.source, frame_beats_from_bytes(icmp_frame), clk=bench.clk) + ) + icmp_observed = await recv_frame( + mac_sink, + clk=bench.clk, + ready_signal=dut.mMacTReady, + timeout_cycles=256, + ) + await icmp_send + assert payload_from_beats(icmp_observed) == expected_reply + + +@cocotb.test() +async def ipv4_top_arp_client_round_trip_test(dut): + bench, mac_sink, _, _, arp_req_source, arp_ack_sink = await setup_top_bench(dut) + + remote_lookup = frame_beats_from_bytes(ipv4_to_bytes(REMOTE_IP))[0] + # The top-level ARP client port inherits the same level-sensitive request + # semantics as the standalone ARP engine wrapper. + arp_req_source.drive(remote_lookup) + arp_request_observed = await recv_frame( + mac_sink, + clk=bench.clk, + ready_signal=dut.mMacTReady, + timeout_cycles=256, + ) + arp_request_expected = build_arp_frame( + opcode=1, + sender_mac=LOCAL_MAC_WIRE, + sender_ip=LOCAL_IP, + target_mac=0xFFFFFFFFFFFF, + target_ip=REMOTE_IP, + ) + assert payload_from_beats(arp_request_observed) == arp_request_expected + + arp_reply = build_arp_frame( + opcode=2, + sender_mac=REMOTE_MAC_WIRE, + sender_ip=REMOTE_IP, + target_mac=LOCAL_MAC_WIRE, + target_ip=LOCAL_IP, + dst_mac=LOCAL_MAC_WIRE, + src_mac=REMOTE_MAC_WIRE, + ) + reply_send = cocotb.start_soon( + send_contiguous_frame(bench.source, frame_beats_from_bytes(arp_reply), clk=bench.clk) + ) + arp_ack = await arp_ack_sink.recv( + clk=bench.clk, + ready_signal=dut.arpAckTReady, + ) + await reply_send + arp_req_source.set_idle() + assert payload_from_beat(arp_ack)[:6] == REMOTE_MAC_WIRE.to_bytes(6, byteorder="big") + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="ipv4_top_wrapper")]) +def test_IpV4Engine(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ipv4enginetopwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": IPV4_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/IpV4Engine/test_IpV4EngineDeMux.py b/tests/ethernet/IpV4Engine/test_IpV4EngineDeMux.py new file mode 100644 index 0000000000..766ee06f32 --- /dev/null +++ b/tests/ethernet/IpV4Engine/test_IpV4EngineDeMux.py @@ -0,0 +1,145 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Stimulus: Feed the de-mux with full Ethernet frames that exercise the ARP, +# IPv4, broadcast, foreign-destination, and bad-version cases. +# - Checks: ARP and IPv4 frames for the local or broadcast MAC must be +# forwarded unchanged to the correct output, while foreign or malformed IPv4 +# headers must be dropped silently. +# - Timing: The test waits on visible AXIS transfers instead of fixed cycle +# counts because the wrapper exposes real ready/valid behavior. + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + FlatEmacEndpoint, + expect_no_output, + frame_beats_from_bytes, + mac_config_word_from_wire, + payload_from_beats, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, +) +from tests.ethernet.IpV4Engine.ipv4_test_utils import ( + IPV4_RTL_SOURCES, + build_arp_frame, + build_ipv4_frame, +) + + +WRAPPER_PATH = "ethernet/IpV4Engine/wrappers/IpV4EngineDeMuxWrapper.vhd" + +LOCAL_MAC_WIRE = 0x001122334455 +LOCAL_MAC_CFG = mac_config_word_from_wire(LOCAL_MAC_WIRE) +REMOTE_MAC_WIRE = 0x665544332211 + + +@cocotb.test() +async def ipv4_demux_routes_and_drops_test(dut): + bench = await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + source_prefix="sMac", + initial_values={ + "localMac": LOCAL_MAC_CFG, + "mArpTReady": 0, + "mIpv4TReady": 0, + }, + ) + source = bench.source + assert source is not None + + arp_sink = FlatEmacEndpoint(dut, prefix="mArp") + ipv4_sink = FlatEmacEndpoint(dut, prefix="mIpv4") + + arp_frame = build_arp_frame( + opcode=1, + sender_mac=REMOTE_MAC_WIRE, + sender_ip="192.168.10.10", + target_mac=0xFFFFFFFFFFFF, + target_ip="192.168.10.20", + ) + arp_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(arp_frame), clk=bench.clk) + ) + arp_observed = await recv_frame( + arp_sink, + clk=bench.clk, + ready_signal=dut.mArpTReady, + timeout_cycles=128, + ) + await arp_send + assert payload_from_beats(arp_observed) == arp_frame + await expect_no_output(ipv4_sink, clk=bench.clk, cycles=8) + + broadcast_ipv4 = build_ipv4_frame( + dst_mac=0xFFFFFFFFFFFF, + src_mac=REMOTE_MAC_WIRE, + src_ip="192.168.10.10", + dst_ip="192.168.10.20", + protocol=0x11, + payload=b"demux-broadcast-ipv4-payload", + ) + ipv4_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(broadcast_ipv4), clk=bench.clk) + ) + ipv4_observed = await recv_frame( + ipv4_sink, + clk=bench.clk, + ready_signal=dut.mIpv4TReady, + timeout_cycles=128, + ) + await ipv4_send + assert payload_from_beats(ipv4_observed) == broadcast_ipv4 + await expect_no_output(arp_sink, clk=bench.clk, cycles=8) + + foreign_ipv4 = build_ipv4_frame( + dst_mac=0x0A0B0C0D0E0F, + src_mac=REMOTE_MAC_WIRE, + src_ip="192.168.10.10", + dst_ip="192.168.10.20", + protocol=0x11, + payload=b"foreign-destination-drop", + ) + await send_contiguous_frame(source, frame_beats_from_bytes(foreign_ipv4), clk=bench.clk) + await expect_no_output(arp_sink, clk=bench.clk, cycles=12) + await expect_no_output(ipv4_sink, clk=bench.clk, cycles=12) + + bad_version_ipv4 = bytearray( + build_ipv4_frame( + dst_mac=LOCAL_MAC_WIRE, + src_mac=REMOTE_MAC_WIRE, + src_ip="192.168.10.10", + dst_ip="192.168.10.20", + protocol=0x11, + payload=b"bad-version-drop", + ) + ) + # The de-mux only accepts IPv4 version/header-length byte 0x45. + bad_version_ipv4[14] = 0x46 + await send_contiguous_frame(source, frame_beats_from_bytes(bytes(bad_version_ipv4)), clk=bench.clk) + await expect_no_output(arp_sink, clk=bench.clk, cycles=12) + await expect_no_output(ipv4_sink, clk=bench.clk, cycles=12) + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="ipv4_demux_wrapper")]) +def test_IpV4EngineDeMux(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ipv4enginedemuxwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": IPV4_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/IpV4Engine/test_IpV4EngineRx.py b/tests/ethernet/IpV4Engine/test_IpV4EngineRx.py new file mode 100644 index 0000000000..fec12f306d --- /dev/null +++ b/tests/ethernet/IpV4Engine/test_IpV4EngineRx.py @@ -0,0 +1,159 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Stimulus: Drive complete Ethernet/IPv4 frames into IpV4EngineRx for one +# UDP packet, one ICMP packet, and one unsupported protocol packet. +# - Checks: The UDP and ICMP cases must emerge as the expected pseudo-header +# streams on their selected protocol slots, while the unsupported protocol +# must be dropped. +# - Timing: The bench waits on the protocol output streams rather than fixed +# latency assumptions because the receive engine has multiple header states. + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + FlatEmacEndpoint, + expect_no_output, + frame_beats_from_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, +) +from tests.ethernet.IpV4Engine.ipv4_test_utils import ( + IPV4_RTL_SOURCES, + build_icmp_echo_packet, + build_ipv4_frame, + build_ipv4_rx_pseudo_frame, + build_ipv4_udp_payload, +) + + +WRAPPER_PATH = "ethernet/IpV4Engine/wrappers/IpV4EngineRxWrapper.vhd" + +LOCAL_MAC = 0x001122334455 +REMOTE_MAC = 0x665544332211 +LOCAL_IP = "192.168.30.10" +REMOTE_IP = "192.168.30.11" + + +@cocotb.test() +async def ipv4_rx_routes_protocol_slots_test(dut): + bench = await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + source_prefix="sIpv4", + initial_values={ + "mUdpTReady": 0, + "mIcmpTReady": 0, + }, + ) + source = bench.source + assert source is not None + + udp_sink = FlatEmacEndpoint(dut, prefix="mUdp") + icmp_sink = FlatEmacEndpoint(dut, prefix="mIcmp") + + udp_payload = build_ipv4_udp_payload( + src_port=0x1234, + dst_port=0x5678, + payload=b"udp-payload-through-rx", + src_ip=REMOTE_IP, + dst_ip=LOCAL_IP, + ) + udp_frame = build_ipv4_frame( + dst_mac=LOCAL_MAC, + src_mac=REMOTE_MAC, + src_ip=REMOTE_IP, + dst_ip=LOCAL_IP, + protocol=0x11, + payload=udp_payload, + ) + udp_expected = build_ipv4_rx_pseudo_frame( + src_mac=REMOTE_MAC, + src_ip=REMOTE_IP, + dst_ip=LOCAL_IP, + protocol=0x11, + payload=udp_payload, + ) + + udp_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(udp_frame), clk=bench.clk) + ) + udp_observed = await recv_frame( + udp_sink, + clk=bench.clk, + ready_signal=dut.mUdpTReady, + timeout_cycles=128, + ) + await udp_send + assert payload_from_beats(udp_observed) == udp_expected + await expect_no_output(icmp_sink, clk=bench.clk, cycles=8) + + icmp_payload = build_icmp_echo_packet( + payload=b"icmp-through-rx", + identifier=0x5566, + sequence=0x0203, + ) + icmp_frame = build_ipv4_frame( + dst_mac=LOCAL_MAC, + src_mac=REMOTE_MAC, + src_ip=REMOTE_IP, + dst_ip=LOCAL_IP, + protocol=0x01, + payload=icmp_payload, + ) + icmp_expected = build_ipv4_rx_pseudo_frame( + src_mac=REMOTE_MAC, + src_ip=REMOTE_IP, + dst_ip=LOCAL_IP, + protocol=0x01, + payload=icmp_payload, + ) + + icmp_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(icmp_frame), clk=bench.clk) + ) + icmp_observed = await recv_frame( + icmp_sink, + clk=bench.clk, + ready_signal=dut.mIcmpTReady, + timeout_cycles=128, + ) + await icmp_send + assert payload_from_beats(icmp_observed) == icmp_expected + await expect_no_output(udp_sink, clk=bench.clk, cycles=8) + + unsupported_frame = build_ipv4_frame( + dst_mac=LOCAL_MAC, + src_mac=REMOTE_MAC, + src_ip=REMOTE_IP, + dst_ip=LOCAL_IP, + protocol=0x99, + payload=b"unsupported-protocol-drop", + ) + await send_contiguous_frame(source, frame_beats_from_bytes(unsupported_frame), clk=bench.clk) + await expect_no_output(udp_sink, clk=bench.clk, cycles=12) + await expect_no_output(icmp_sink, clk=bench.clk, cycles=12) + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="ipv4_rx_wrapper")]) +def test_IpV4EngineRx(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ipv4enginerxwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": IPV4_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/IpV4Engine/test_IpV4EngineTx.py b/tests/ethernet/IpV4Engine/test_IpV4EngineTx.py new file mode 100644 index 0000000000..74aa175254 --- /dev/null +++ b/tests/ethernet/IpV4Engine/test_IpV4EngineTx.py @@ -0,0 +1,152 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Stimulus: Feed the TX engine with curated pseudo-header traffic for one +# remote UDP packet and one localhost-routed UDP packet. +# - Checks: The remote packet must emerge as a fully framed Ethernet/IPv4 +# stream on the wire output, and the localhost packet must be diverted to the +# localhost output instead of the wire output. +# - Timing: The test drives one packet at a time and waits on the selected +# output stream so route-selection bugs are obvious in waveforms. + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + FlatEmacEndpoint, + expect_no_output, + frame_beats_from_bytes, + mac_config_word_from_wire, + payload_from_beats, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, +) +from tests.ethernet.IpV4Engine.ipv4_test_utils import ( + IPV4_RTL_SOURCES, + build_ipv4_tx_pseudo_frame, + build_ipv4_tx_wire_frame, + build_ipv4_udp_payload, +) + + +WRAPPER_PATH = "ethernet/IpV4Engine/wrappers/IpV4EngineTxWrapper.vhd" + +LOCAL_MAC_WIRE = 0x001122334455 +LOCAL_MAC_CFG = mac_config_word_from_wire(LOCAL_MAC_WIRE) +REMOTE_MAC_WIRE = 0x665544332211 +LOCAL_IP = "192.168.40.10" +REMOTE_IP = "192.168.40.11" + + +@cocotb.test() +async def ipv4_tx_generates_wire_and_localhost_paths_test(dut): + bench = await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + source_prefix="sProt", + initial_values={ + "localMac": LOCAL_MAC_CFG, + "mIpv4TReady": 0, + "mLocalTReady": 0, + }, + ) + source = bench.source + assert source is not None + + wire_sink = FlatEmacEndpoint(dut, prefix="mIpv4") + local_sink = FlatEmacEndpoint(dut, prefix="mLocal") + + udp_payload = build_ipv4_udp_payload( + src_port=0x1357, + dst_port=0x2468, + payload=b"tx-remote-path-payload", + src_ip=LOCAL_IP, + dst_ip=REMOTE_IP, + ) + remote_request = build_ipv4_tx_pseudo_frame( + dst_mac=REMOTE_MAC_WIRE, + src_ip=LOCAL_IP, + dst_ip=REMOTE_IP, + protocol=0x11, + payload=udp_payload, + ) + remote_expected = build_ipv4_tx_wire_frame( + dst_mac=REMOTE_MAC_WIRE, + src_mac=LOCAL_MAC_WIRE, + src_ip=LOCAL_IP, + dst_ip=REMOTE_IP, + protocol=0x11, + payload=udp_payload, + ) + + remote_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(remote_request), clk=bench.clk) + ) + remote_observed = await recv_frame( + wire_sink, + clk=bench.clk, + ready_signal=dut.mIpv4TReady, + timeout_cycles=128, + ) + await remote_send + assert payload_from_beats(remote_observed) == remote_expected + await expect_no_output(local_sink, clk=bench.clk, cycles=8) + + localhost_payload = build_ipv4_udp_payload( + src_port=0x1001, + dst_port=0x1002, + payload=b"tx-localhost-shortcut", + src_ip=LOCAL_IP, + dst_ip="192.168.40.99", + ) + localhost_request = build_ipv4_tx_pseudo_frame( + dst_mac=LOCAL_MAC_WIRE, + src_ip=LOCAL_IP, + dst_ip="192.168.40.99", + protocol=0x11, + payload=localhost_payload, + ) + localhost_expected = build_ipv4_tx_wire_frame( + dst_mac=LOCAL_MAC_WIRE, + src_mac=LOCAL_MAC_WIRE, + src_ip=LOCAL_IP, + dst_ip="192.168.40.99", + protocol=0x11, + payload=localhost_payload, + identification=0x0001, + ) + + local_send = cocotb.start_soon( + send_contiguous_frame(source, frame_beats_from_bytes(localhost_request), clk=bench.clk) + ) + local_observed = await recv_frame( + local_sink, + clk=bench.clk, + ready_signal=dut.mLocalTReady, + timeout_cycles=128, + ) + await local_send + assert payload_from_beats(local_observed) == localhost_expected + await expect_no_output(wire_sink, clk=bench.clk, cycles=8) + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="ipv4_tx_wrapper")]) +def test_IpV4EngineTx(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ipv4enginetxwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": IPV4_RTL_SOURCES + [WRAPPER_PATH]}, + ) From ce6022f36fc91fe3daec6e175331c426a0276db9 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 16 Apr 2026 12:08:39 -0700 Subject: [PATCH 10/92] Update plan docs. --- docs/_meta/rtl_regression_handoff.md | 11 ++++++----- docs/_meta/rtl_regression_plan.md | 6 +++--- docs/_meta/rtl_regression_progress.md | 20 ++++++++++++-------- 3 files changed, 21 insertions(+), 16 deletions(-) diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index f4ca290e53..3b2fb63bca 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -18,15 +18,16 @@ - Treat VHDL packages as transitively covered unless a behavioral function/procedure needs a dedicated wrapper ## Quick Resume Snapshot -- Current frontier: the axi-first pass is complete through the previously remaining final 11 `axi/` modules, `dsp/` is now included in the generated phase-1 queue, and a manual first-wave `ethernet/EthMacCore` slice is now also validated under `tests/ethernet/EthMacCore/`. `ethernet` and `protocols` still remain temporarily deferred in `docs/_meta/rtl_phase1_queue_overrides.json`, so the generated queue is intentionally behind the manually advanced Ethernet work. +- Current frontier: the axi-first pass is complete, the merged branch line now includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, and the earlier manual `ethernet/EthMacCore` slice is still in place. The immediate planning gap is that `docs/_meta/rtl_phase1_queue_overrides.json` still carries the old temporary `ethernet` / `protocols` deferrals, so the checked-in queue artifacts are now behind the real branch frontier. - Current axi frontier: complete for the intended simulator-friendly pass in this branch snapshot; do not resume from the older stale `AxiResize` note. - Current validated-open issues: - - None currently recorded on this merged branch. `AxiResize` and `AxiStreamDmaV2Read` are both fixed here; queue regeneration is the next step. + - None currently recorded on this merged branch. `AxiResize` and `AxiStreamDmaV2Read` are both fixed here; queue/override refresh is the next step. - Current queue discipline: - Keep `dsp/` in the generated queue scope. Do not track DSP rollout in a separate hand-maintained list. - The planned `dsp/generic/fixed` leaf set is now validated: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. - - The later cross-subsystem cleanup still includes removing the temporary `ethernet` and `protocols` subsystem deferrals from `docs/_meta/rtl_phase1_queue_overrides.json` and regenerating `docs/_meta/rtl_phase1_queue.{md,json}` when that broader transition is actually taken. - - Until that happens, do not treat the generated queue artifacts as evidence that `ethernet` is untouched; the manually selected `EthMacCore` slice is already implemented and passing even though the queue inputs still defer the subsystem. + - The next cross-subsystem cleanup is no longer hypothetical: remove the stale temporary `ethernet` and `protocols` subsystem deferrals from `docs/_meta/rtl_phase1_queue_overrides.json` before using the queue as the next-module source of truth again. + - Until that happens, do not treat the generated queue artifacts as evidence that `ethernet` or `protocols` are untouched; this branch already contains the Ethernet slice plus the merged SSI and PGP waves even though the current queue inputs still defer those subsystems. + - Keep the local `protocols/pgp/pgp3/` defer unless there is a deliberate decision to broaden the PGP family rollout. - Do not hand-maintain queue order in the plan or handoff docs. - Current wrapper discipline: - Prefer the existing subsystem `ip_integrator/` shim layers over bespoke record flattening. @@ -142,7 +143,7 @@ One small RTL fix landed during that validation pass because the new `AxiStreamD A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instantiation_graph.md` and `docs/_meta/rtl_instantiation_graph.json`, and the same generator now also emits a path-qualified bottom-up phase-1 queue at `docs/_meta/rtl_phase1_queue.md` and `docs/_meta/rtl_phase1_queue.json`. Keep the graph for provenance, but treat the generated queue as the default source of truth for what to implement next. Manual phase-1 deferrals and order exceptions belong in `docs/_meta/rtl_phase1_queue_overrides.json`, not as hand-edited ordering in the plan doc. ## Immediate Next Task -Choose whether the next manual branch step stays in `ethernet/EthMacCore` or returns to another non-deferred subsystem. If staying in Ethernet, the most natural follow-on is the MAC assembly layer (`EthMacRx`, `EthMacTx`, `EthMacRxFifo`, `EthMacTxFifo`) or a move into the IPv4 / Raw Ethernet stack using the now-established `tests/ethernet/EthMacCore/ethmac_test_utils.py` helper and checked-in wrapper pattern. If switching back to queue-driven work, remove the temporary subsystem deferrals and regenerate `docs/_meta/rtl_phase1_queue.{md,json}` first so the queue is authoritative again. +Refresh the phase-1 planning inputs before taking the next module. Remove the stale temporary `ethernet` and `protocols` subsystem deferrals from `docs/_meta/rtl_phase1_queue_overrides.json`, regenerate `docs/_meta/rtl_instantiation_graph.{md,json}` plus `docs/_meta/rtl_phase1_queue.{md,json}`, and then choose the next non-deferred frontier from that refreshed queue. If the follow-on still stays manual instead of queue-driven, the leading candidates remain the deeper `ethernet/EthMacCore` assembly layer (`EthMacRx`, `EthMacTx`, `EthMacRxFifo`, `EthMacTxFifo`) or the next wider non-`pgp3` protocol slice. ## Read Order 1. `docs/_meta/rtl_regression_handoff.md` diff --git a/docs/_meta/rtl_regression_plan.md b/docs/_meta/rtl_regression_plan.md index 5c3bca2717..f238083880 100644 --- a/docs/_meta/rtl_regression_plan.md +++ b/docs/_meta/rtl_regression_plan.md @@ -95,7 +95,7 @@ - Keep the graph artifacts for provenance, but use the generated path-qualified phase-1 queue in `docs/_meta/rtl_phase1_queue.{md,json}` as the day-to-day source of truth. - Record manual phase-1 deferrals and manual order exceptions only in `docs/_meta/rtl_phase1_queue_overrides.json`; do not hand-edit queue order in this plan. - Do not re-analyze `rtl_instantiation_graph.json` before every module. Regenerate the queue when needed and take the next non-deferred item from `rtl_phase1_queue.md` unless a concrete blocker forces a documented override. -- The current manual rollout preference is to finish `axi/` first. That preference is encoded as temporary subsystem deferrals in `docs/_meta/rtl_phase1_queue_overrides.json`, not as a hand-maintained side list in this plan. +- The earlier temporary `axi/`-first rollout preference has already been completed on the current branch line. The next planning step is to remove stale temporary `ethernet` and `protocols` subsystem deferrals from `docs/_meta/rtl_phase1_queue_overrides.json`, regenerate the queue, and then resume from the next real non-deferred frontier. ## Flat Build Order The phase-1 simulator-friendly queue is now generated from the checked-in graph as a path-qualified bottom-up order rather than maintained inline in this plan. @@ -131,11 +131,11 @@ Workflow: - The repo has a checked-in inventory and handoff system. - New windows can recover project state by reading the handoff artifacts only. - The Python-only regression direction is documented and stable. -- The first pilot modules are selected and ready for implementation. +- The queue artifacts and their override inputs stay aligned with the actual validated branch frontier instead of lagging behind completed subsystem waves. - The smoke/functional tier split is established in the plan and progress tracking. ## Open Questions And Deferred Decisions - Whether PR-vs-nightly split is needed immediately or only after runtime data. - Exact criteria for moving a vendor-heavy module out of `deferred_vendor_heavy`. -- Which subsystem should be the first large-scale migration after the pilot modules. +- Whether the next broad post-refresh wave should follow the regenerated queue directly or continue manually in `ethernet/EthMacCore`. - Whether a separate tracked list of high-risk behavioral package helpers is needed once the module inventory stabilizes. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 6bbbab9ec2..8f1b3e5535 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -2,18 +2,18 @@ ## Summary - Current phase: Phase-1 implementation active -- Current subsystem: `ethernet/EthMacCore` -- Current focus module: the first manual `ethernet/EthMacCore` wave is now in place under `tests/ethernet/EthMacCore/`, covering `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`, with the main follow-on choices now being deeper `EthMacRx` / `EthMacTx` / FIFO assembly work or a move into the IPv4 / Raw Ethernet stack. -- Last updated: 2026-04-10 +- Current subsystem: cross-subsystem planning refresh after the merged `protocols/ssi`, `protocols/pgp`, and `ethernet/EthMacCore` waves +- Current focus module: refresh the stale phase-1 queue inputs and handoff summary so the next resume point reflects the current merged branch rather than the earlier temporary `axi/`-first deferrals. +- Last updated: 2026-04-16 ## Current Frontier Snapshot -- Next queue target: broader phase-1 queue refresh needed after the completed `dsp/generic/fixed` leaf batch +- Next queue target: remove the stale temporary `ethernet` and `protocols` subsystem deferrals, regenerate `docs/_meta/rtl_phase1_queue.{md,json}`, then take the next real non-deferred frontier from the refreshed queue. - Queue note: - The axi-first pass is now complete through the previously remaining final 11 `axi/` modules. - - The queue snapshot in earlier notes that still pointed at `AxiReadEmulate` / `AxiResize` is now stale and should not be reused. - - `dsp/` had been missing from the generated queue scope. The queue generator now includes it so DSP rollout can stay on the normal bottom-up path instead of living as an ad hoc side list. - - The broader post-axi transition should still make the queue authoritative again by removing the temporary subsystem deferrals and regenerating it before taking the next non-deferred cross-subsystem module. - - While `ethernet` remains deferred in the generated queue inputs, the manually selected `EthMacCore` slice is no longer unstarted on this branch; do not reuse the older docs wording that treated the whole subsystem as untouched. + - The current `verification-2` branch already includes the merged `pre-release` state through PR #1392, so the validated `protocols/ssi`, `protocols/pgp`, and manual `ethernet/EthMacCore` waves are all part of the present branch snapshot. + - The queue snapshot in `docs/_meta/rtl_phase1_queue.{md,json}` is therefore intentionally behind the actual branch contents because `rtl_phase1_queue_overrides.json` still defers `ethernet` and `protocols` from the earlier `axi/`-first phase. + - `dsp/` is now included in the generated queue scope, so DSP rollout no longer needs to live on a hand-maintained side list. + - Do not use the currently checked-in queue files as the next-module source of truth until those stale subsystem deferrals have been removed and the queue has been regenerated. - `protocols/pgp/pgp3/` is now an explicit local defer in `rtl_phase1_queue_overrides.json`; do not treat it as the default next family breadth target on this branch. - Known expected-open tests on this branch: - None currently recorded. `AxiResize` and `AxiStreamDmaV2Read` both pass on this merged branch. @@ -49,10 +49,12 @@ - Keep wrappers only when they make Python interaction cleaner. - Run the `vsg` linter with CI's `vsg-linter.yml` settings on any created or edited VHDL files, and use autofix before doing manual cleanup when possible. - Treat VHDL packages as transitively covered unless a behavioral function/procedure needs a dedicated wrapper. +- Treat the checked-in queue and override artifacts as living planning inputs that must be refreshed when a previously deferred subsystem wave is merged. ## Completed Work Items - Surveyed repo structure and existing verification flow. - Reviewed existing Python regressions and representative VHDL testbenches. +- Merged the current `pre-release` branch into `verification-2`, bringing the already-landed `protocols/ssi` and `protocols/pgp` regression waves into the same branch line as the earlier `ethernet/EthMacCore` slice. - Re-added `dsp/` to the generated phase-1 queue scope so DSP work is tracked by the same bottom-up planner as the other simulator-friendly subsystems. - Implemented `tests/dsp/generic/test_DspAddSub.py`. - Validated `tests/dsp/generic/test_DspAddSub.py` locally with `./.venv/bin/python -m pytest -n 0 -q tests/dsp/generic/test_DspAddSub.py`. @@ -248,6 +250,8 @@ - 2026-04-07: Expanded `tests/protocols/ssi/test_SsiFifo.py` beyond the earlier single-beat subset. The checked-in FIFO bench now proves contiguous 3-beat frame preservation on the default, `VALID_THOLD_G=0`, and `VALID_THOLD_G=2` wrapper paths; exercises repeated-`SOF` malformed-frame handling across the buffered modes; and keeps the existing missing-`SOF` drop plus `SLAVE_READY_EN_G=false` overflow checks. The buffered malformed-frame result is mode-specific at the wrapper boundary: `VALID_THOLD_G=0` drops the malformed repeated-`SOF` frame outright, while `VALID_THOLD_G=2` emits the expected two-beat terminated `EOFE` frame. A follow-up backpressure pass also added explicit drain-side ready toggling on a good 5-beat frame, malformed termination under toggled ready, and thresholded release under intermittent drain stalls so SSI frame policy is now checked under nontrivial sink backpressure without duplicating the full `AxiStreamFifoV2` transport matrix. Revalidated the full touched SSI slice locally with `19 passed`. - 2026-04-10: Landed the first manual `ethernet/EthMacCore` bench wave under `tests/ethernet/EthMacCore/`, added the required checked-in wrappers under `ethernet/EthMacCore/wrappers/`, and validated the baseline 12-module slice covering `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`. - 2026-04-10: Expanded that same `EthMacCore` slice beyond the initial happy paths. The checked-in Ethernet MAC suite now covers `EthMacTop` filter/backpressure/checksum/pause interactions, GMII and XGMII import/export plus link-not-ready recovery behavior, checksum negative cases, filter multicast/broadcast/filter-disable/multi-beat-drop behavior, shift runtime-control and control-bit propagation edges, and full byte-width `1..16` logic-path coverage for `EthCrc32Parallel`. The full `tests/ethernet/EthMacCore` directory currently passes locally with `32 passed`. +- 2026-04-16: Merged the current `pre-release` branch into `verification-2`, so this branch line now contains the already-landed SSI and PGP waves from PR #1391 and PR #1392 in addition to the manual Ethernet slice. +- 2026-04-16: Refreshed the planning docs to move the active frontier from “continue Ethernet next” to “refresh the stale queue/override inputs, then resume from the real merged-branch frontier.” - 2026-03-20: Added an explicit project rule to comment new Python regression code where intent or runner behavior is not self-evident. - 2026-03-20: Expanded `FifoAsync` to a validated 12-case parameter matrix and enabled default pytest xdist parallelization with `pytest.ini`. - 2026-03-20: Added package-coverage policy: packages are covered transitively unless a behavioral helper warrants a dedicated wrapper test. From 9f17de6c53f8e8aad315de8d49d41ab4c2be56c5 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 16 Apr 2026 13:27:04 -0700 Subject: [PATCH 11/92] RawEthFramer tests. --- docs/_meta/rtl_regression_handoff.md | 3 + docs/_meta/rtl_regression_progress.md | 2 +- .../wrappers/RawEthFramerFlatWrapper.vhd | 218 +++++++++++ .../wrappers/RawEthFramerPairFlatWrapper.vhd | 206 ++++++++++ .../wrappers/RawEthFramerRxFlatWrapper.vhd | 117 ++++++ .../wrappers/RawEthFramerTxFlatWrapper.vhd | 117 ++++++ .../RawEthFramer/raw_eth_test_utils.py | 355 ++++++++++++++++++ .../RawEthFramer/test_RawEthFramer.py | 331 ++++++++++++++++ .../RawEthFramer/test_RawEthFramerPair.py | 108 ++++++ .../RawEthFramer/test_RawEthFramerRx.py | 215 +++++++++++ .../RawEthFramer/test_RawEthFramerTx.py | 135 +++++++ 11 files changed, 1806 insertions(+), 1 deletion(-) create mode 100644 ethernet/RawEthFramer/wrappers/RawEthFramerFlatWrapper.vhd create mode 100644 ethernet/RawEthFramer/wrappers/RawEthFramerPairFlatWrapper.vhd create mode 100644 ethernet/RawEthFramer/wrappers/RawEthFramerRxFlatWrapper.vhd create mode 100644 ethernet/RawEthFramer/wrappers/RawEthFramerTxFlatWrapper.vhd create mode 100644 tests/ethernet/RawEthFramer/raw_eth_test_utils.py create mode 100644 tests/ethernet/RawEthFramer/test_RawEthFramer.py create mode 100644 tests/ethernet/RawEthFramer/test_RawEthFramerPair.py create mode 100644 tests/ethernet/RawEthFramer/test_RawEthFramerRx.py create mode 100644 tests/ethernet/RawEthFramer/test_RawEthFramerTx.py diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index 3b2fb63bca..4187a0858f 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -56,6 +56,7 @@ - `AxiStreamDmaV2Read` needed a real RTL/runtime fix rather than a bench workaround: keep the bounded byte-count conversion fix in `axi/axi4/rtl/AxiPkg.vhd` and the direct terminal-mask generation in `axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd`. The current wrapper only exposes an 8-bit `TUSER`, so the observable contract in the checked-in bench is first-user propagation plus payload/keep/id/dest and descriptor return fields. - `tests/dsp/generic/dsp_test_utils.py` is now the shared home for DSP-specific signed helpers, rolling reference models, cocotb clock-settle timing, and generated FIR wrappers. Reuse it instead of cloning DSP arithmetic or wrapper boilerplate. - `tests/ethernet/EthMacCore/ethmac_test_utils.py` is now the shared home for the current Ethernet MAC slice: flat EMAC beat helpers, Ethernet/IPv4/UDP packet builders, checksum reference code, MAC-config byte-order helpers, and minimum-frame padding helpers. Reuse it instead of cloning packet or sideband plumbing across `EthMacCore` benches. +- `tests/ethernet/RawEthFramer/raw_eth_test_utils.py` now holds the shared raw-Ethernet helper pieces: flat app-side beat helpers, raw-Ethernet header/frame builders, and lookup-handshake utilities reused by the `RawEthFramer`, `RawEthFramerRx`, and `RawEthFramerTx` benches. - The current `EthMacCore` slice is intentionally a checked-in-wrapper-first rollout, not a cocotb-generated-wrapper experiment. Keep new Ethernet work on that same pattern unless the simulator forces a very local generic adapter. - The XGMII import/export loopback behavior differs from the GMII path when `phyReady` drops mid-traffic: the blocked frame is retained and drains after link recovery, padded to Ethernet's minimum frame size if it was short. The GMII path drops that blocked frame. Future import/export coverage should preserve that distinction instead of forcing one common expectation. - `EthMacRxCsum` reliably raises `IPERR` on a bad IPv4 header checksum, but the checked-in wrapper contract does not currently require `EOFE` for that case. Keep the negative test aligned to the real observable contract rather than to a stronger assumption. @@ -88,6 +89,8 @@ The project now also has a shared helper path in `tests/common/regression_utils. The first manual `ethernet/EthMacCore` wave is now also in place. The checked-in Ethernet MAC benches under `tests/ethernet/EthMacCore/` cover `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`, and the current directory-level regression passes locally with `32 passed`. The current Ethernet wrappers live under `ethernet/EthMacCore/wrappers/` and should be treated as the stable cocotb-facing surfaces for deeper `EthMacCore` work. +`ethernet/RawEthFramer/` now also has checked-in regression coverage under `tests/ethernet/RawEthFramer/`. The earlier top-level `RawEthFramer` wrapper bench is joined by direct leaf benches for `RawEthFramerRx` and `RawEthFramerTx`, plus a `RawEthFramerPair` integration bench whose wrapper cross-connects two `RawEthFramer` instances to mirror the legacy `ethernet/RawEthFramer/tb/RawEthFramerTb.vhd` topology. The validated RX leaf bench covers lookup-gated unicast decode, short-frame trim behavior, broadcast bypass, and representative reject cases. The validated TX leaf bench currently keeps a narrower first-pass subset: lookup-request exposure before forwarding, broadcast bypass with the observed padded wire image, and zero-MAC lookup-miss drop. Do not over-claim the broader multi-beat unicast completion path for `RawEthFramerTx`; that branch still needs follow-up before it should be considered a passing leaf-level contract. + The wrapper coverage policy is now more explicit in practice: test the wrapper-specific behavior, not the full leaf matrix again. `Fifo` validated both inferred sync/async selection branches, `FifoCascade` validated public stage-vector mapping plus a curated output smoke, and `FifoMux` is currently validated only on the stable split-to-narrow path. The pack-to-wide `FifoMux` path should be treated as still open rather than silently assumed covered. That same wrapper-policy lesson now applies to the late `base/sync` wrappers as well. `SyncClockFreq` is stable with a checked-in subsystem wrapper, but its common-clock measurement quantizes one count above the abstract target under the current GHDL flow, so the regression checks a bounded expected range rather than an exact integer. `SyncTrigRate` is intentionally covered as a wrapper/integration bench only: it proves aligned update publication, denser-window rate growth, reset-path liveness, and strobe pulse behavior, while exact min/max pipeline semantics remain the responsibility of the dedicated `SyncMinMax` leaf test. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 8f1b3e5535..6d3753a1d9 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -30,7 +30,7 @@ | `dsp` | started | not started | started | The planned `dsp/generic/fixed` leaf batch is now validated under `tests/dsp/generic/`: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. Shared DSP helpers now live in `tests/dsp/generic/dsp_test_utils.py`, and the legacy VHDL benches under `dsp/generic/tb/` were treated as behavioral reference material rather than as execution constraints. | | `axi` | started | not started | started | The axi-first pass is now complete for the simulator-friendly queue. The final locally validated batch adds `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`, with a combined `11 passed` validation run on 2026-03-27. Added checked-in subsystem wrappers under `axi/axi4/ip_integrator/`, `axi/axi-lite/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/` for those benches. `AxiStreamFifoV2` now has an expanded `10 passed` wrapper regression under `tests/axi/axi_stream/` covering async and sync width conversion, metadata truncation, `VALID_THOLD` frame-ready and burst-release modes, dynamic pause-threshold behavior, `CASCADE_SIZE=2`, and the `S_HAS_TREADY=0` pause-only source-side path. `AxiResize` now passes its equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` wrapper regression on this branch after the read-hold RTL fix. `AxiLiteAsync`, `AxiLiteToDrp`, and `AxiRateGen` still keep intentionally narrow common-clock subsets while the more timing-sensitive async AXI-Lite crossing branches remain open. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` still keep intentionally narrow first-pass subsets. `AxiStreamDmaV2Read` is now validated with a two-case wrapper regression covering both aligned and short terminal-beat reads after fixing bounded byte-count conversion in `AxiPkg` and terminal-mask generation in `AxiStreamDmaV2Read`. | | `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. | -| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers a first manual `EthMacCore` slice: `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`, with the deeper filter/shift/CRC corner expansions also in place. The generated queue still keeps the broader subsystem deferred until the post-axi refresh removes the temporary queue override. | +| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` covers the first manual `EthMacCore` slice, and `tests/ethernet/RawEthFramer/` now adds direct leaf coverage for `RawEthFramerRx` and `RawEthFramerTx`, the top-level `RawEthFramer` wrapper bench, and a two-node pair wrapper that mirrors the old `ethernet/RawEthFramer/tb/RawEthFramerTb.vhd` transport topology. The RawEthFramer helper layer lives in `tests/ethernet/RawEthFramer/raw_eth_test_utils.py`, with checked-in wrappers under `ethernet/RawEthFramer/wrappers/`. The validated TX subset stays intentionally narrow at the leaf level: lookup-request exposure, broadcast bypass, and zero-MAC miss drop, while the broader multi-beat unicast completion path still needs a follow-up before it should be treated as a passing leaf-level contract. The generated queue still keeps the broader subsystem deferred until the post-axi refresh removes the temporary queue override. | | `devices` | not started | not started | not started | Many vendor-heavy cases | | `xilinx` | not started | not started | not started | Many vendor-heavy cases | diff --git a/ethernet/RawEthFramer/wrappers/RawEthFramerFlatWrapper.vhd b/ethernet/RawEthFramer/wrappers/RawEthFramerFlatWrapper.vhd new file mode 100644 index 0000000000..219a91eb44 --- /dev/null +++ b/ethernet/RawEthFramer/wrappers/RawEthFramerFlatWrapper.vhd @@ -0,0 +1,218 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for RawEthFramer +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; +use surf.AxiStreamPkg.all; +use surf.SsiPkg.all; +use surf.RawEthFramerPkg.all; + +entity RawEthFramerFlatWrapper is + generic ( + TPD_G : time := 1 ns; + ETH_TYPE_G : slv(15 downto 0) := x"0010"); + port ( + clk : in sl; + rst : in sl; + localMac : in slv(47 downto 0); + sMacTValid : in sl; + sMacTData : in slv(63 downto 0); + sMacTKeep : in slv(7 downto 0); + sMacTLast : in sl; + sMacTReady : out sl; + sMacSof : in sl; + sMacEofe : in sl; + mMacTValid : out sl; + mMacTData : out slv(63 downto 0); + mMacTKeep : out slv(7 downto 0); + mMacTLast : out sl; + mMacTReady : in sl := '1'; + mMacSof : out sl; + mMacEofe : out sl; + sAppTValid : in sl; + sAppTData : in slv(63 downto 0); + sAppTKeep : in slv(7 downto 0); + sAppTLast : in sl; + sAppTReady : out sl; + sAppTDest : in slv(7 downto 0); + sAppSof : in sl; + sAppBcf : in sl; + sAppEofe : in sl; + mAppTValid : out sl; + mAppTData : out slv(63 downto 0); + mAppTKeep : out slv(7 downto 0); + mAppTLast : out sl; + mAppTReady : in sl := '1'; + mAppTDest : out slv(7 downto 0); + mAppSof : out sl; + mAppBcf : out sl; + mAppEofe : out sl; + S_AXI_AWADDR : in slv(31 downto 0); + S_AXI_AWPROT : in slv(2 downto 0); + S_AXI_AWVALID : in sl; + S_AXI_AWREADY : out sl; + S_AXI_WDATA : in slv(31 downto 0); + S_AXI_WSTRB : in slv(3 downto 0); + S_AXI_WVALID : in sl; + S_AXI_WREADY : out sl; + S_AXI_BRESP : out slv(1 downto 0); + S_AXI_BVALID : out sl; + S_AXI_BREADY : in sl; + S_AXI_ARADDR : in slv(31 downto 0); + S_AXI_ARPROT : in slv(2 downto 0); + S_AXI_ARVALID : in sl; + S_AXI_ARREADY : out sl; + S_AXI_RDATA : out slv(31 downto 0); + S_AXI_RRESP : out slv(1 downto 0); + S_AXI_RVALID : out sl; + S_AXI_RREADY : in sl); +end entity RawEthFramerFlatWrapper; + +architecture rtl of RawEthFramerFlatWrapper is + + signal sMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal sAppMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAppSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAppMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAppSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + +begin + + -- Flatten the inbound MAC-side stream that feeds the RX path. + sMacComb : process (sMacEofe, sMacSof, sMacTData, sMacTKeep, sMacTLast, sMacTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sMacTValid; + v.tData(63 downto 0) := sMacTData; + v.tKeep(7 downto 0) := sMacTKeep; + v.tLast := sMacTLast; + ssiSetUserSof(RAW_ETH_CONFIG_INIT_C, v, sMacSof); + ssiSetUserEofe(RAW_ETH_CONFIG_INIT_C, v, sMacEofe); + sMacMaster <= v; + end process sMacComb; + + -- Flatten the application-side stream that feeds the TX path. + sAppComb : process (sAppBcf, sAppEofe, sAppSof, sAppTData, sAppTDest, sAppTKeep, sAppTLast, sAppTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAppTValid; + v.tData(63 downto 0) := sAppTData; + v.tKeep(7 downto 0) := sAppTKeep; + v.tLast := sAppTLast; + v.tDest(7 downto 0) := sAppTDest; + ssiSetUserSof(RAW_ETH_CONFIG_INIT_C, v, sAppSof); + ssiSetUserBcf(RAW_ETH_CONFIG_INIT_C, v, sAppBcf); + ssiSetUserEofe(RAW_ETH_CONFIG_INIT_C, v, sAppEofe); + sAppMaster <= v; + end process sAppComb; + + sMacTReady <= sMacSlave.tReady; + sAppTReady <= sAppSlave.tReady; + mMacSlave.tReady <= mMacTReady; + mAppSlave.tReady <= mAppTReady; + + -- Re-expand the outbound MAC-side stream for cocotb inspection. + mMacView : process (mMacMaster) is + begin + mMacTValid <= mMacMaster.tValid; + mMacTData <= mMacMaster.tData(63 downto 0); + mMacTKeep <= mMacMaster.tKeep(7 downto 0); + mMacTLast <= mMacMaster.tLast; + mMacSof <= ssiGetUserSof(RAW_ETH_CONFIG_INIT_C, mMacMaster); + mMacEofe <= ssiGetUserEofe(RAW_ETH_CONFIG_INIT_C, mMacMaster); + end process mMacView; + + -- Re-expand the application-side output stream and metadata. + mAppView : process (mAppMaster) is + begin + mAppTValid <= mAppMaster.tValid; + mAppTData <= mAppMaster.tData(63 downto 0); + mAppTKeep <= mAppMaster.tKeep(7 downto 0); + mAppTLast <= mAppMaster.tLast; + mAppTDest <= mAppMaster.tDest(7 downto 0); + mAppSof <= ssiGetUserSof(RAW_ETH_CONFIG_INIT_C, mAppMaster); + mAppBcf <= ssiGetUserBcf(RAW_ETH_CONFIG_INIT_C, mAppMaster); + mAppEofe <= ssiGetUserEofe(RAW_ETH_CONFIG_INIT_C, mAppMaster); + end process mAppView; + + U_AxilShim : entity surf.SlaveAxiLiteIpIntegrator + generic map ( + INTERFACENAME => "S_AXI", + HAS_PROT => 1, + HAS_WSTRB => 1, + ADDR_WIDTH => 32) + port map ( + S_AXI_ACLK => clk, + S_AXI_ARESETN => not rst, + S_AXI_AWADDR => S_AXI_AWADDR, + S_AXI_AWPROT => S_AXI_AWPROT, + S_AXI_AWVALID => S_AXI_AWVALID, + S_AXI_AWREADY => S_AXI_AWREADY, + S_AXI_WDATA => S_AXI_WDATA, + S_AXI_WSTRB => S_AXI_WSTRB, + S_AXI_WVALID => S_AXI_WVALID, + S_AXI_WREADY => S_AXI_WREADY, + S_AXI_BRESP => S_AXI_BRESP, + S_AXI_BVALID => S_AXI_BVALID, + S_AXI_BREADY => S_AXI_BREADY, + S_AXI_ARADDR => S_AXI_ARADDR, + S_AXI_ARPROT => S_AXI_ARPROT, + S_AXI_ARVALID => S_AXI_ARVALID, + S_AXI_ARREADY => S_AXI_ARREADY, + S_AXI_RDATA => S_AXI_RDATA, + S_AXI_RRESP => S_AXI_RRESP, + S_AXI_RVALID => S_AXI_RVALID, + S_AXI_RREADY => S_AXI_RREADY, + axilClk => open, + axilRst => open, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + + U_DUT : entity surf.RawEthFramerWrapper + generic map ( + TPD_G => TPD_G, + ETH_TYPE_G => ETH_TYPE_G) + port map ( + localMac => localMac, + obMacMaster => sMacMaster, + obMacSlave => sMacSlave, + ibMacMaster => mMacMaster, + ibMacSlave => mMacSlave, + ibAppMaster => mAppMaster, + ibAppSlave => mAppSlave, + obAppMaster => sAppMaster, + obAppSlave => sAppSlave, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave, + clk => clk, + rst => rst); + +end architecture rtl; diff --git a/ethernet/RawEthFramer/wrappers/RawEthFramerPairFlatWrapper.vhd b/ethernet/RawEthFramer/wrappers/RawEthFramerPairFlatWrapper.vhd new file mode 100644 index 0000000000..a2f367658d --- /dev/null +++ b/ethernet/RawEthFramer/wrappers/RawEthFramerPairFlatWrapper.vhd @@ -0,0 +1,206 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing loopback wrapper for two RawEthFramer instances +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.SsiPkg.all; +use surf.RawEthFramerPkg.all; + +entity RawEthFramerPairFlatWrapper is + generic ( + TPD_G : time := 1 ns; + ETH_TYPE_G : slv(15 downto 0) := x"0010"); + port ( + clk : in sl; + rst : in sl; + serverLocalMac : in slv(47 downto 0); + clientLocalMac : in slv(47 downto 0); + sServerAppTValid : in sl; + sServerAppTData : in slv(63 downto 0); + sServerAppTKeep : in slv(7 downto 0); + sServerAppTLast : in sl; + sServerAppTReady : out sl; + sServerAppTDest : in slv(7 downto 0); + sServerAppSof : in sl; + sServerAppBcf : in sl; + sServerAppEofe : in sl; + mServerAppTValid : out sl; + mServerAppTData : out slv(63 downto 0); + mServerAppTKeep : out slv(7 downto 0); + mServerAppTLast : out sl; + mServerAppTReady : in sl := '1'; + mServerAppTDest : out slv(7 downto 0); + mServerAppSof : out sl; + mServerAppBcf : out sl; + mServerAppEofe : out sl; + sClientAppTValid : in sl; + sClientAppTData : in slv(63 downto 0); + sClientAppTKeep : in slv(7 downto 0); + sClientAppTLast : in sl; + sClientAppTReady : out sl; + sClientAppTDest : in slv(7 downto 0); + sClientAppSof : in sl; + sClientAppBcf : in sl; + sClientAppEofe : in sl; + mClientAppTValid : out sl; + mClientAppTData : out slv(63 downto 0); + mClientAppTKeep : out slv(7 downto 0); + mClientAppTLast : out sl; + mClientAppTReady : in sl := '1'; + mClientAppTDest : out slv(7 downto 0); + mClientAppSof : out sl; + mClientAppBcf : out sl; + mClientAppEofe : out sl); +end entity RawEthFramerPairFlatWrapper; + +architecture rtl of RawEthFramerPairFlatWrapper is + + signal serverObMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal serverObMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal serverIbMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal serverIbMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal clientObMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal clientObMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal clientIbMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal clientIbMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal sServerAppMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sServerAppSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mServerAppMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mServerAppSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal sClientAppMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sClientAppSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mClientAppMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mClientAppSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + --------------------------------------------------------------------------- + -- Application-side stream flattening + --------------------------------------------------------------------------- + sServerAppComb : process (sServerAppBcf, sServerAppEofe, sServerAppSof, sServerAppTData, sServerAppTDest, sServerAppTKeep, sServerAppTLast, sServerAppTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sServerAppTValid; + v.tData(63 downto 0) := sServerAppTData; + v.tKeep(7 downto 0) := sServerAppTKeep; + v.tLast := sServerAppTLast; + v.tDest(7 downto 0) := sServerAppTDest; + ssiSetUserSof(RAW_ETH_CONFIG_INIT_C, v, sServerAppSof); + ssiSetUserBcf(RAW_ETH_CONFIG_INIT_C, v, sServerAppBcf); + ssiSetUserEofe(RAW_ETH_CONFIG_INIT_C, v, sServerAppEofe); + sServerAppMaster <= v; + end process sServerAppComb; + + sClientAppComb : process (sClientAppBcf, sClientAppEofe, sClientAppSof, sClientAppTData, sClientAppTDest, sClientAppTKeep, sClientAppTLast, sClientAppTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sClientAppTValid; + v.tData(63 downto 0) := sClientAppTData; + v.tKeep(7 downto 0) := sClientAppTKeep; + v.tLast := sClientAppTLast; + v.tDest(7 downto 0) := sClientAppTDest; + ssiSetUserSof(RAW_ETH_CONFIG_INIT_C, v, sClientAppSof); + ssiSetUserBcf(RAW_ETH_CONFIG_INIT_C, v, sClientAppBcf); + ssiSetUserEofe(RAW_ETH_CONFIG_INIT_C, v, sClientAppEofe); + sClientAppMaster <= v; + end process sClientAppComb; + + sServerAppTReady <= sServerAppSlave.tReady; + sClientAppTReady <= sClientAppSlave.tReady; + mServerAppSlave.tReady <= mServerAppTReady; + mClientAppSlave.tReady <= mClientAppTReady; + + --------------------------------------------------------------------------- + -- Application-side output flattening + --------------------------------------------------------------------------- + mServerAppView : process (mServerAppMaster) is + begin + mServerAppTValid <= mServerAppMaster.tValid; + mServerAppTData <= mServerAppMaster.tData(63 downto 0); + mServerAppTKeep <= mServerAppMaster.tKeep(7 downto 0); + mServerAppTLast <= mServerAppMaster.tLast; + mServerAppTDest <= mServerAppMaster.tDest(7 downto 0); + mServerAppSof <= ssiGetUserSof(RAW_ETH_CONFIG_INIT_C, mServerAppMaster); + mServerAppBcf <= ssiGetUserBcf(RAW_ETH_CONFIG_INIT_C, mServerAppMaster); + mServerAppEofe <= ssiGetUserEofe(RAW_ETH_CONFIG_INIT_C, mServerAppMaster); + end process mServerAppView; + + mClientAppView : process (mClientAppMaster) is + begin + mClientAppTValid <= mClientAppMaster.tValid; + mClientAppTData <= mClientAppMaster.tData(63 downto 0); + mClientAppTKeep <= mClientAppMaster.tKeep(7 downto 0); + mClientAppTLast <= mClientAppMaster.tLast; + mClientAppTDest <= mClientAppMaster.tDest(7 downto 0); + mClientAppSof <= ssiGetUserSof(RAW_ETH_CONFIG_INIT_C, mClientAppMaster); + mClientAppBcf <= ssiGetUserBcf(RAW_ETH_CONFIG_INIT_C, mClientAppMaster); + mClientAppEofe <= ssiGetUserEofe(RAW_ETH_CONFIG_INIT_C, mClientAppMaster); + end process mClientAppView; + + --------------------------------------------------------------------------- + -- Cross-connect the MAC-side ports as a direct link + --------------------------------------------------------------------------- + serverObMacMaster <= clientIbMacMaster; + clientIbMacSlave <= serverObMacSlave; + clientObMacMaster <= serverIbMacMaster; + serverIbMacSlave <= clientObMacSlave; + + --------------------------------------------------------------------------- + -- DUT instantiation + --------------------------------------------------------------------------- + U_Server : entity surf.RawEthFramer + generic map ( + TPD_G => TPD_G, + ETH_TYPE_G => ETH_TYPE_G) + port map ( + localMac => serverLocalMac, + remoteMac => clientLocalMac, + tDest => open, + obMacMaster => serverObMacMaster, + obMacSlave => serverObMacSlave, + ibMacMaster => serverIbMacMaster, + ibMacSlave => serverIbMacSlave, + ibAppMaster => mServerAppMaster, + ibAppSlave => mServerAppSlave, + obAppMaster => sServerAppMaster, + obAppSlave => sServerAppSlave, + clk => clk, + rst => rst); + + U_Client : entity surf.RawEthFramer + generic map ( + TPD_G => TPD_G, + ETH_TYPE_G => ETH_TYPE_G) + port map ( + localMac => clientLocalMac, + remoteMac => serverLocalMac, + tDest => open, + obMacMaster => clientObMacMaster, + obMacSlave => clientObMacSlave, + ibMacMaster => clientIbMacMaster, + ibMacSlave => clientIbMacSlave, + ibAppMaster => mClientAppMaster, + ibAppSlave => mClientAppSlave, + obAppMaster => sClientAppMaster, + obAppSlave => sClientAppSlave, + clk => clk, + rst => rst); + +end architecture rtl; diff --git a/ethernet/RawEthFramer/wrappers/RawEthFramerRxFlatWrapper.vhd b/ethernet/RawEthFramer/wrappers/RawEthFramerRxFlatWrapper.vhd new file mode 100644 index 0000000000..57bc275596 --- /dev/null +++ b/ethernet/RawEthFramer/wrappers/RawEthFramerRxFlatWrapper.vhd @@ -0,0 +1,117 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for RawEthFramerRx +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.SsiPkg.all; +use surf.RawEthFramerPkg.all; + +entity RawEthFramerRxFlatWrapper is + generic ( + TPD_G : time := 1 ns; + ETH_TYPE_G : slv(15 downto 0) := x"0010"); + port ( + clk : in sl; + rst : in sl; + localMac : in slv(47 downto 0); + remoteMac : in slv(47 downto 0); + req : out sl; + ack : in sl; + tDest : out slv(7 downto 0); + sMacTValid : in sl; + sMacTData : in slv(63 downto 0); + sMacTKeep : in slv(7 downto 0); + sMacTLast : in sl; + sMacTReady : out sl; + sMacSof : in sl; + sMacEofe : in sl; + mAppTValid : out sl; + mAppTData : out slv(63 downto 0); + mAppTKeep : out slv(7 downto 0); + mAppTLast : out sl; + mAppTReady : in sl := '1'; + mAppTDest : out slv(7 downto 0); + mAppSof : out sl; + mAppBcf : out sl; + mAppEofe : out sl); +end entity RawEthFramerRxFlatWrapper; + +architecture rtl of RawEthFramerRxFlatWrapper is + + signal sMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAppMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAppSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + --------------------------------------------------------------------------- + -- Stream flattening + --------------------------------------------------------------------------- + sMacComb : process (sMacEofe, sMacSof, sMacTData, sMacTKeep, sMacTLast, sMacTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sMacTValid; + v.tData(63 downto 0) := sMacTData; + v.tKeep(7 downto 0) := sMacTKeep; + v.tLast := sMacTLast; + ssiSetUserSof(RAW_ETH_CONFIG_INIT_C, v, sMacSof); + ssiSetUserEofe(RAW_ETH_CONFIG_INIT_C, v, sMacEofe); + sMacMaster <= v; + end process sMacComb; + + sMacTReady <= sMacSlave.tReady; + mAppSlave.tReady <= mAppTReady; + + --------------------------------------------------------------------------- + -- Output flattening + --------------------------------------------------------------------------- + mAppView : process (mAppMaster) is + begin + mAppTValid <= mAppMaster.tValid; + mAppTData <= mAppMaster.tData(63 downto 0); + mAppTKeep <= mAppMaster.tKeep(7 downto 0); + mAppTLast <= mAppMaster.tLast; + mAppTDest <= mAppMaster.tDest(7 downto 0); + mAppSof <= ssiGetUserSof(RAW_ETH_CONFIG_INIT_C, mAppMaster); + mAppBcf <= ssiGetUserBcf(RAW_ETH_CONFIG_INIT_C, mAppMaster); + mAppEofe <= ssiGetUserEofe(RAW_ETH_CONFIG_INIT_C, mAppMaster); + end process mAppView; + + --------------------------------------------------------------------------- + -- DUT instantiation + --------------------------------------------------------------------------- + U_DUT : entity surf.RawEthFramerRx + generic map ( + TPD_G => TPD_G, + ETH_TYPE_G => ETH_TYPE_G) + port map ( + localMac => localMac, + remoteMac => remoteMac, + tDest => tDest, + req => req, + ack => ack, + obMacMaster => sMacMaster, + obMacSlave => sMacSlave, + ibAppMaster => mAppMaster, + ibAppSlave => mAppSlave, + clk => clk, + rst => rst); + +end architecture rtl; diff --git a/ethernet/RawEthFramer/wrappers/RawEthFramerTxFlatWrapper.vhd b/ethernet/RawEthFramer/wrappers/RawEthFramerTxFlatWrapper.vhd new file mode 100644 index 0000000000..b04611ca3f --- /dev/null +++ b/ethernet/RawEthFramer/wrappers/RawEthFramerTxFlatWrapper.vhd @@ -0,0 +1,117 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for RawEthFramerTx +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.SsiPkg.all; +use surf.RawEthFramerPkg.all; + +entity RawEthFramerTxFlatWrapper is + generic ( + TPD_G : time := 1 ns; + ETH_TYPE_G : slv(15 downto 0) := x"0010"); + port ( + clk : in sl; + rst : in sl; + localMac : in slv(47 downto 0); + remoteMac : in slv(47 downto 0); + req : out sl; + ack : in sl; + tDest : out slv(7 downto 0); + sAppTValid : in sl; + sAppTData : in slv(63 downto 0); + sAppTKeep : in slv(7 downto 0); + sAppTLast : in sl; + sAppTReady : out sl; + sAppTDest : in slv(7 downto 0); + sAppSof : in sl; + sAppBcf : in sl; + sAppEofe : in sl; + mMacTValid : out sl; + mMacTData : out slv(63 downto 0); + mMacTKeep : out slv(7 downto 0); + mMacTLast : out sl; + mMacTReady : in sl := '1'; + mMacSof : out sl; + mMacEofe : out sl); +end entity RawEthFramerTxFlatWrapper; + +architecture rtl of RawEthFramerTxFlatWrapper is + + signal sAppMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAppSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + --------------------------------------------------------------------------- + -- Stream flattening + --------------------------------------------------------------------------- + sAppComb : process (sAppBcf, sAppEofe, sAppSof, sAppTData, sAppTDest, sAppTKeep, sAppTLast, sAppTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAppTValid; + v.tData(63 downto 0) := sAppTData; + v.tKeep(7 downto 0) := sAppTKeep; + v.tLast := sAppTLast; + v.tDest(7 downto 0) := sAppTDest; + ssiSetUserSof(RAW_ETH_CONFIG_INIT_C, v, sAppSof); + ssiSetUserBcf(RAW_ETH_CONFIG_INIT_C, v, sAppBcf); + ssiSetUserEofe(RAW_ETH_CONFIG_INIT_C, v, sAppEofe); + sAppMaster <= v; + end process sAppComb; + + sAppTReady <= sAppSlave.tReady; + mMacSlave.tReady <= mMacTReady; + + --------------------------------------------------------------------------- + -- Output flattening + --------------------------------------------------------------------------- + mMacView : process (mMacMaster) is + begin + mMacTValid <= mMacMaster.tValid; + mMacTData <= mMacMaster.tData(63 downto 0); + mMacTKeep <= mMacMaster.tKeep(7 downto 0); + mMacTLast <= mMacMaster.tLast; + mMacSof <= ssiGetUserSof(RAW_ETH_CONFIG_INIT_C, mMacMaster); + mMacEofe <= ssiGetUserEofe(RAW_ETH_CONFIG_INIT_C, mMacMaster); + end process mMacView; + + --------------------------------------------------------------------------- + -- DUT instantiation + --------------------------------------------------------------------------- + U_DUT : entity surf.RawEthFramerTx + generic map ( + TPD_G => TPD_G, + ETH_TYPE_G => ETH_TYPE_G) + port map ( + localMac => localMac, + remoteMac => remoteMac, + tDest => tDest, + req => req, + ack => ack, + ibMacMaster => mMacMaster, + ibMacSlave => mMacSlave, + obAppMaster => sAppMaster, + obAppSlave => sAppSlave, + clk => clk, + rst => rst); + +end architecture rtl; diff --git a/tests/ethernet/RawEthFramer/raw_eth_test_utils.py b/tests/ethernet/RawEthFramer/raw_eth_test_utils.py new file mode 100644 index 0000000000..395f0c07a7 --- /dev/null +++ b/tests/ethernet/RawEthFramer/raw_eth_test_utils.py @@ -0,0 +1,355 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +from __future__ import annotations + +from dataclasses import dataclass +from pathlib import Path + +from cocotbext.axi import AxiLiteBus, AxiLiteMaster +from cocotb.triggers import RisingEdge, Timer + +from tests.axi.utils import axil_read_u32, axil_write_u32 +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + FlatEmacEndpoint, + cycle, + keep_mask, + mac_config_word_from_wire, + mac_to_bytes, + pack_bytes, + setup_flat_emac_testbench, +) + +RAWETH_RTL_SOURCES = [ + str(path) + for path in sorted((Path(__file__).resolve().parents[3] / "ethernet" / "RawEthFramer" / "rtl").glob("*.vhd")) +] + + +LOCAL_MAC_WIRE = 0x001122334455 +LOCAL_MAC_CFG = mac_config_word_from_wire(LOCAL_MAC_WIRE) +REMOTE_MAC_WIRE = 0x0A0B0C0D0E0F +REMOTE_MAC_CFG = mac_config_word_from_wire(REMOTE_MAC_WIRE) +ALT_REMOTE_MAC_WIRE = 0x102132435465 +ALT_REMOTE_MAC_CFG = mac_config_word_from_wire(ALT_REMOTE_MAC_WIRE) +ETH_TYPE_CFG = 0x0010 +RAWETH_BEAT_BYTES = 8 + + +@dataclass +class RawAppBeat: + data: int + keep: int + last: int + dest: int = 0 + sof: int = 0 + bcf: int = 0 + eofe: int = 0 + + +class FlatRawAppEndpoint: + def __init__(self, dut, *, prefix: str): + self.dut = dut + self.prefix = prefix + + def _sig(self, suffix: str): + return getattr(self.dut, f"{self.prefix}{suffix}") + + def set_idle(self) -> None: + for suffix, value in ( + ("TValid", 0), + ("TData", 0), + ("TKeep", 0), + ("TLast", 0), + ("TDest", 0), + ("Sof", 0), + ("Bcf", 0), + ("Eofe", 0), + ): + self._sig(suffix).value = value + + def drive(self, beat: RawAppBeat) -> None: + self._sig("TValid").value = 1 + self._sig("TData").value = beat.data + self._sig("TKeep").value = beat.keep + self._sig("TLast").value = beat.last + self._sig("TDest").value = beat.dest + self._sig("Sof").value = beat.sof + self._sig("Bcf").value = beat.bcf + self._sig("Eofe").value = beat.eofe + + async def wait_ready(self, *, clk) -> None: + while True: + await RisingEdge(clk) + await Timer(1, unit="ns") + if int(self._sig("TReady").value) == 1: + return + + def snapshot(self) -> RawAppBeat: + return RawAppBeat( + data=int(self._sig("TData").value), + keep=int(self._sig("TKeep").value), + last=int(self._sig("TLast").value), + dest=int(self._sig("TDest").value), + sof=int(self._sig("Sof").value), + bcf=int(self._sig("Bcf").value), + eofe=int(self._sig("Eofe").value), + ) + + +@dataclass +class RawEthWrapperBench: + clk: object + axil: AxiLiteMaster + mac_source: FlatEmacEndpoint + mac_sink: FlatEmacEndpoint + app_source: FlatRawAppEndpoint + app_sink: FlatRawAppEndpoint + + +@dataclass +class RawEthRxBench: + clk: object + source: FlatEmacEndpoint + sink: FlatRawAppEndpoint + + +@dataclass +class RawEthTxBench: + clk: object + source: FlatRawAppEndpoint + sink: FlatEmacEndpoint + + +@dataclass +class RawEthPairBench: + clk: object + server_source: FlatRawAppEndpoint + server_sink: FlatRawAppEndpoint + client_source: FlatRawAppEndpoint + client_sink: FlatRawAppEndpoint + + +def raw_app_beats_from_bytes( + data: bytes, + *, + dest: int, + bcf: int = 0, + eofe: int = 0, + beat_bytes: int = RAWETH_BEAT_BYTES, +) -> list[RawAppBeat]: + beats = [] + offset = 0 + while offset < len(data): + chunk = data[offset : offset + beat_bytes] + beats.append( + RawAppBeat( + data=pack_bytes(chunk, lane_bytes=beat_bytes), + keep=keep_mask(len(chunk)), + last=1 if offset + beat_bytes >= len(data) else 0, + dest=dest, + sof=1 if offset == 0 else 0, + bcf=bcf if offset == 0 else 0, + eofe=eofe if offset + beat_bytes >= len(data) else 0, + ) + ) + offset += beat_bytes + return beats + + +def payload_from_raw_beats(beats: list[RawAppBeat], *, lane_bytes: int = 8) -> bytes: + payload = bytearray() + for beat in beats: + for index in range(lane_bytes): + if beat.keep & (1 << index): + payload.append((beat.data >> (8 * index)) & 0xFF) + return bytes(payload) + + +def pad_to_raw_eth_lane_width(payload: bytes, *, lane_bytes: int = RAWETH_BEAT_BYTES) -> bytes: + return payload + bytes((-len(payload)) % lane_bytes) + + +def raweth_header_bytes(*, dest: int, bcf: int, min_byte_count: int) -> bytes: + return bytes([((bcf & 0x1) << 7) | (min_byte_count & 0x7F), dest & 0xFF]) + + +def build_raw_eth_wire_frame( + *, + dst_mac: int, + src_mac: int, + dest: int, + bcf: int, + payload: bytes, + min_byte_count: int, + eth_type_cfg: int = ETH_TYPE_CFG, +) -> bytes: + return ( + mac_to_bytes(dst_mac) + + mac_to_bytes(src_mac) + + eth_type_cfg.to_bytes(2, byteorder="little") + + raweth_header_bytes(dest=dest, bcf=bcf, min_byte_count=min_byte_count) + + payload + ) + + +def remote_mac_axil_addr(dest: int, *, high: bool = False) -> int: + return (dest << 3) | (4 if high else 0) + + +async def program_remote_mac(master, *, dest: int, mac_cfg: int) -> None: + await axil_write_u32(master, remote_mac_axil_addr(dest), mac_cfg & 0xFFFF_FFFF) + await axil_write_u32(master, remote_mac_axil_addr(dest, high=True), (mac_cfg >> 32) & 0xFFFF) + + +async def read_remote_mac(master, *, dest: int) -> int: + low = await axil_read_u32(master, remote_mac_axil_addr(dest)) + high = await axil_read_u32(master, remote_mac_axil_addr(dest, high=True)) + return low | ((high & 0xFFFF) << 32) + + +async def setup_raw_eth_wrapper_bench(dut) -> RawEthWrapperBench: + bench = await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + initial_values={ + "localMac": LOCAL_MAC_CFG, + "mMacTReady": 0, + "mAppTReady": 0, + "S_AXI_AWADDR": 0, + "S_AXI_AWPROT": 0, + "S_AXI_AWVALID": 0, + "S_AXI_WDATA": 0, + "S_AXI_WSTRB": 0, + "S_AXI_WVALID": 0, + "S_AXI_BREADY": 0, + "S_AXI_ARADDR": 0, + "S_AXI_ARPROT": 0, + "S_AXI_ARVALID": 0, + "S_AXI_RREADY": 0, + }, + ) + + mac_source = FlatEmacEndpoint(dut, prefix="sMac") + mac_sink = FlatEmacEndpoint(dut, prefix="mMac") + app_source = FlatRawAppEndpoint(dut, prefix="sApp") + app_sink = FlatRawAppEndpoint(dut, prefix="mApp") + mac_source.set_idle() + app_source.set_idle() + + axil = AxiLiteMaster( + AxiLiteBus.from_prefix(dut, "S_AXI"), + dut.clk, + dut.rst, + reset_active_level=True, + ) + await cycle(bench.clk, 2) + return RawEthWrapperBench( + clk=bench.clk, + axil=axil, + mac_source=mac_source, + mac_sink=mac_sink, + app_source=app_source, + app_sink=app_sink, + ) + + +async def setup_raw_eth_rx_bench(dut) -> RawEthRxBench: + await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + initial_values={ + "localMac": LOCAL_MAC_CFG, + "remoteMac": 0, + "ack": 0, + "mAppTReady": 0, + }, + ) + + source = FlatEmacEndpoint(dut, prefix="sMac") + sink = FlatRawAppEndpoint(dut, prefix="mApp") + source.set_idle() + await cycle(dut.clk, 2) + return RawEthRxBench(clk=dut.clk, source=source, sink=sink) + + +async def setup_raw_eth_tx_bench(dut) -> RawEthTxBench: + await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + initial_values={ + "localMac": LOCAL_MAC_CFG, + "remoteMac": 0, + "ack": 0, + "mMacTReady": 0, + }, + ) + + source = FlatRawAppEndpoint(dut, prefix="sApp") + sink = FlatEmacEndpoint(dut, prefix="mMac") + source.set_idle() + await cycle(dut.clk, 2) + return RawEthTxBench(clk=dut.clk, source=source, sink=sink) + + +async def setup_raw_eth_pair_bench(dut) -> RawEthPairBench: + await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + initial_values={ + "serverLocalMac": LOCAL_MAC_CFG, + "clientLocalMac": REMOTE_MAC_CFG, + "mServerAppTReady": 0, + "mClientAppTReady": 0, + }, + ) + + server_source = FlatRawAppEndpoint(dut, prefix="sServerApp") + server_sink = FlatRawAppEndpoint(dut, prefix="mServerApp") + client_source = FlatRawAppEndpoint(dut, prefix="sClientApp") + client_sink = FlatRawAppEndpoint(dut, prefix="mClientApp") + server_source.set_idle() + client_source.set_idle() + await cycle(dut.clk, 2) + return RawEthPairBench( + clk=dut.clk, + server_source=server_source, + server_sink=server_sink, + client_source=client_source, + client_sink=client_sink, + ) + + +async def wait_lookup_request( + dut, + *, + clk, + req_name: str = "req", + dest_name: str = "tDest", + timeout_cycles: int = 64, +) -> int: + for _ in range(timeout_cycles): + await Timer(1, unit="ns") + if int(getattr(dut, req_name).value) == 1: + return int(getattr(dut, dest_name).value) + await RisingEdge(clk) + raise AssertionError(f"Timed out waiting for {req_name}") + + +async def pulse_signal(signal, *, clk, cycles: int = 1) -> None: + signal.value = 1 + for _ in range(cycles): + await RisingEdge(clk) + await Timer(1, unit="ns") + signal.value = 0 diff --git a/tests/ethernet/RawEthFramer/test_RawEthFramer.py b/tests/ethernet/RawEthFramer/test_RawEthFramer.py new file mode 100644 index 0000000000..028b09be58 --- /dev/null +++ b/tests/ethernet/RawEthFramer/test_RawEthFramer.py @@ -0,0 +1,331 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Exercise the checked-in RawEthFramer wrapper across the major TX and +# RX branches: unicast lookup, broadcast bypass, unknown-remote drops, valid +# receive decode, and invalid receive filtering. +# - Stimulus: Drive app-side payload frames into the TX path, drive pre-framed +# raw-Ethernet MAC packets into the RX path, and program the remote-MAC LUT +# over AXI-Lite exactly as software would. +# - Checks: TX must prepend the raw-Ethernet header and route by `tDest`, RX +# must strip that header back to the app payload and recover `tDest`/`BCF`, +# missing LUT entries must drop traffic, and malformed or mismatched receive +# packets must be discarded without wedging the datapath. +# - Timing: The bench waits on stream handshakes and frame completion instead of +# fixed delays because both TX and RX include LUT-lookup sequencing. + +from __future__ import annotations + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + expect_no_output, + frame_beats_from_bytes, + mac_to_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, +) +from tests.ethernet.RawEthFramer.raw_eth_test_utils import ( + ALT_REMOTE_MAC_WIRE, + ETH_TYPE_CFG, + LOCAL_MAC_WIRE, + RAWETH_BEAT_BYTES, + RAWETH_RTL_SOURCES, + REMOTE_MAC_CFG, + REMOTE_MAC_WIRE, + build_raw_eth_wire_frame, + pad_to_raw_eth_lane_width, + payload_from_raw_beats, + program_remote_mac, + raw_app_beats_from_bytes, + raweth_header_bytes, + read_remote_mac, + setup_raw_eth_wrapper_bench, +) + + +WRAPPER_PATH = "ethernet/RawEthFramer/wrappers/RawEthFramerFlatWrapper.vhd" + + +@cocotb.test() +async def raw_eth_tx_unicast_and_broadcast_test(dut): + bench = await setup_raw_eth_wrapper_bench(dut) + + await program_remote_mac(bench.axil, dest=0x2A, mac_cfg=REMOTE_MAC_CFG) + assert await read_remote_mac(bench.axil, dest=0x2A) == REMOTE_MAC_CFG + + unicast_payload = b"raw-eth-tx-unicast" + unicast_wire_payload = pad_to_raw_eth_lane_width(unicast_payload) + unicast_send = cocotb.start_soon( + send_contiguous_frame( + bench.app_source, + raw_app_beats_from_bytes(unicast_payload, dest=0x2A), + clk=bench.clk, + ) + ) + unicast_observed = await recv_frame( + bench.mac_sink, + clk=bench.clk, + ready_signal=dut.mMacTReady, + timeout_cycles=128, + ) + await unicast_send + assert payload_from_beats(unicast_observed, lane_bytes=8) == build_raw_eth_wire_frame( + dst_mac=REMOTE_MAC_WIRE, + src_mac=LOCAL_MAC_WIRE, + dest=0x2A, + bcf=0, + payload=unicast_wire_payload, + min_byte_count=16 + len(unicast_payload), + ) + assert unicast_observed[0].sof == 1 + assert unicast_observed[-1].eofe == 0 + + broadcast_payload = b"raw-eth-tx-broadcast" + broadcast_wire_payload = pad_to_raw_eth_lane_width(broadcast_payload) + broadcast_send = cocotb.start_soon( + send_contiguous_frame( + bench.app_source, + raw_app_beats_from_bytes(broadcast_payload, dest=0xFF, bcf=1, eofe=1), + clk=bench.clk, + ) + ) + broadcast_observed = await recv_frame( + bench.mac_sink, + clk=bench.clk, + ready_signal=dut.mMacTReady, + timeout_cycles=128, + ) + await broadcast_send + assert payload_from_beats(broadcast_observed, lane_bytes=8) == build_raw_eth_wire_frame( + dst_mac=0xFFFF_FFFF_FFFF, + src_mac=LOCAL_MAC_WIRE, + dest=0xFF, + bcf=1, + payload=broadcast_wire_payload, + min_byte_count=16 + len(broadcast_payload), + ) + assert broadcast_observed[0].sof == 1 + assert broadcast_observed[-1].eofe == 1 + + +@cocotb.test() +async def raw_eth_tx_drops_unknown_dest_test(dut): + bench = await setup_raw_eth_wrapper_bench(dut) + + missing_payload = b"lut-miss" + missing_send = cocotb.start_soon( + send_contiguous_frame( + bench.app_source, + raw_app_beats_from_bytes(missing_payload, dest=0x33), + clk=bench.clk, + ) + ) + await missing_send + await expect_no_output(bench.mac_sink, clk=bench.clk, cycles=12) + + recovery_payload = b"recovery" + recovery_send = cocotb.start_soon( + send_contiguous_frame( + bench.app_source, + raw_app_beats_from_bytes(recovery_payload, dest=0xFF, bcf=1), + clk=bench.clk, + ) + ) + recovery_observed = await recv_frame( + bench.mac_sink, + clk=bench.clk, + ready_signal=dut.mMacTReady, + timeout_cycles=128, + ) + await recovery_send + assert payload_from_beats(recovery_observed, lane_bytes=8) == build_raw_eth_wire_frame( + dst_mac=0xFFFF_FFFF_FFFF, + src_mac=LOCAL_MAC_WIRE, + dest=0xFF, + bcf=1, + payload=recovery_payload, + min_byte_count=16 + len(recovery_payload), + ) + + +@cocotb.test() +async def raw_eth_rx_unicast_and_broadcast_test(dut): + bench = await setup_raw_eth_wrapper_bench(dut) + + await program_remote_mac(bench.axil, dest=0x19, mac_cfg=REMOTE_MAC_CFG) + + unicast_payload = b"rx-unicast-payload" + unicast_frame = build_raw_eth_wire_frame( + dst_mac=LOCAL_MAC_WIRE, + src_mac=REMOTE_MAC_WIRE, + dest=0x19, + bcf=0, + payload=unicast_payload, + min_byte_count=16 + len(unicast_payload), + ) + unicast_send = cocotb.start_soon( + send_contiguous_frame( + bench.mac_source, + frame_beats_from_bytes(unicast_frame, beat_bytes=RAWETH_BEAT_BYTES, eofe=1), + clk=bench.clk, + ) + ) + unicast_observed = await recv_frame( + bench.app_sink, + clk=bench.clk, + ready_signal=dut.mAppTReady, + timeout_cycles=128, + ) + await unicast_send + assert payload_from_raw_beats(unicast_observed) == unicast_payload + assert unicast_observed[0].sof == 1 + assert unicast_observed[0].dest == 0x19 + assert unicast_observed[0].bcf == 0 + assert unicast_observed[-1].eofe == 1 + + broadcast_payload = b"rx-broadcast" + broadcast_frame = build_raw_eth_wire_frame( + dst_mac=0xFFFF_FFFF_FFFF, + src_mac=ALT_REMOTE_MAC_WIRE, + dest=0xFF, + bcf=1, + payload=broadcast_payload, + min_byte_count=16 + len(broadcast_payload), + ) + broadcast_send = cocotb.start_soon( + send_contiguous_frame( + bench.mac_source, + frame_beats_from_bytes(broadcast_frame, beat_bytes=RAWETH_BEAT_BYTES), + clk=bench.clk, + ) + ) + broadcast_observed = await recv_frame( + bench.app_sink, + clk=bench.clk, + ready_signal=dut.mAppTReady, + timeout_cycles=128, + ) + await broadcast_send + assert payload_from_raw_beats(broadcast_observed) == broadcast_payload + assert broadcast_observed[0].dest == 0xFF + assert broadcast_observed[0].bcf == 1 + + +@cocotb.test() +async def raw_eth_rx_rejects_invalid_frames_test(dut): + bench = await setup_raw_eth_wrapper_bench(dut) + + await program_remote_mac(bench.axil, dest=0x41, mac_cfg=REMOTE_MAC_CFG) + + foreign_dest = mac_to_bytes(0x8899_AABB_CCDD) + mac_to_bytes(REMOTE_MAC_WIRE)[:2] + foreign_send = cocotb.start_soon( + send_contiguous_frame( + bench.mac_source, + frame_beats_from_bytes(foreign_dest, beat_bytes=RAWETH_BEAT_BYTES), + clk=bench.clk, + ) + ) + await foreign_send + await expect_no_output(bench.app_sink, clk=bench.clk, cycles=8) + + wrong_type = ( + mac_to_bytes(LOCAL_MAC_WIRE) + + mac_to_bytes(REMOTE_MAC_WIRE) + + b"\x08\x00" + + raweth_header_bytes(dest=0x41, bcf=0, min_byte_count=0) + ) + wrong_type_send = cocotb.start_soon( + send_contiguous_frame( + bench.mac_source, + frame_beats_from_bytes(wrong_type, beat_bytes=RAWETH_BEAT_BYTES), + clk=bench.clk, + ) + ) + await wrong_type_send + await expect_no_output(bench.app_sink, clk=bench.clk, cycles=8) + + bad_broadcast = build_raw_eth_wire_frame( + dst_mac=LOCAL_MAC_WIRE, + src_mac=ALT_REMOTE_MAC_WIRE, + dest=0x01, + bcf=1, + payload=b"", + min_byte_count=0, + ) + bad_broadcast_send = cocotb.start_soon( + send_contiguous_frame( + bench.mac_source, + frame_beats_from_bytes(bad_broadcast, beat_bytes=RAWETH_BEAT_BYTES), + clk=bench.clk, + ) + ) + await bad_broadcast_send + await expect_no_output(bench.app_sink, clk=bench.clk, cycles=8) + + src_mismatch = build_raw_eth_wire_frame( + dst_mac=LOCAL_MAC_WIRE, + src_mac=ALT_REMOTE_MAC_WIRE, + dest=0x41, + bcf=0, + payload=b"", + min_byte_count=0, + ) + src_mismatch_send = cocotb.start_soon( + send_contiguous_frame( + bench.mac_source, + frame_beats_from_bytes(src_mismatch, beat_bytes=RAWETH_BEAT_BYTES), + clk=bench.clk, + ) + ) + await src_mismatch_send + await expect_no_output(bench.app_sink, clk=bench.clk, cycles=8) + + valid_payload = b"rx-recovery" + valid_frame = build_raw_eth_wire_frame( + dst_mac=LOCAL_MAC_WIRE, + src_mac=REMOTE_MAC_WIRE, + dest=0x41, + bcf=0, + payload=valid_payload, + min_byte_count=16 + len(valid_payload), + ) + valid_send = cocotb.start_soon( + send_contiguous_frame( + bench.mac_source, + frame_beats_from_bytes(valid_frame, beat_bytes=RAWETH_BEAT_BYTES), + clk=bench.clk, + ) + ) + valid_observed = await recv_frame( + bench.app_sink, + clk=bench.clk, + ready_signal=dut.mAppTReady, + timeout_cycles=128, + ) + await valid_send + assert payload_from_raw_beats(valid_observed) == valid_payload + assert valid_observed[0].dest == 0x41 + assert valid_observed[0].bcf == 0 + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="raw_eth_framer_flat_wrapper")]) +def test_RawEthFramer(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.rawethframerflatwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": RAWETH_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/RawEthFramer/test_RawEthFramerPair.py b/tests/ethernet/RawEthFramer/test_RawEthFramerPair.py new file mode 100644 index 0000000000..3297aab647 --- /dev/null +++ b/tests/ethernet/RawEthFramer/test_RawEthFramerPair.py @@ -0,0 +1,108 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Recreate the legacy RawEthFramerTb integration path with two +# RawEthFramer instances cross-connected at the MAC boundary, then exercise +# end-to-end transport in both directions through the combined TX and RX +# datapaths. +# - Stimulus: Drive framed app payloads into the server side and then the +# client side of the pair wrapper using the same direct remote-MAC topology +# as the legacy VHDL bench. +# - Checks: The far-side receiver must recover the original payload, `tDest`, +# SOF, BCF, and EOFE metadata after the frame traverses TX header insertion, +# the MAC loopback link, and RX header stripping. +# - Timing: The bench waits on accepted AXIS handshakes and frame completion +# instead of fixed delays because the two-node path adds both TX and RX state +# machines to the transport latency. + +from __future__ import annotations + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + recv_frame, + send_contiguous_frame, +) +from tests.ethernet.RawEthFramer.raw_eth_test_utils import ( + RAWETH_RTL_SOURCES, + payload_from_raw_beats, + raw_app_beats_from_bytes, + setup_raw_eth_pair_bench, +) + + +WRAPPER_PATH = "ethernet/RawEthFramer/wrappers/RawEthFramerPairFlatWrapper.vhd" + + +@cocotb.test() +async def raw_eth_pair_matches_legacy_end_to_end_transport_test(dut): + bench = await setup_raw_eth_pair_bench(dut) + + # Mirror the legacy testbench's main path: source traffic on the server + # side and observe it emerge on the client side after both RawEthFramers. + server_payload = b"legacy-server-to-client-transport" + server_send = cocotb.start_soon( + send_contiguous_frame( + bench.server_source, + raw_app_beats_from_bytes(server_payload, dest=0x00, eofe=1), + clk=bench.clk, + ) + ) + client_observed = await recv_frame( + bench.client_sink, + clk=bench.clk, + ready_signal=dut.mClientAppTReady, + timeout_cycles=256, + ) + await server_send + + assert payload_from_raw_beats(client_observed) == server_payload + assert client_observed[0].dest == 0x00 + assert client_observed[0].bcf == 0 + assert client_observed[0].sof == 1 + assert client_observed[-1].eofe == 1 + + # Run the reverse path as well so both instances prove TX and RX behavior + # in the integrated topology instead of only one direction. + client_payload = b"client-to-server-reverse-path" + client_send = cocotb.start_soon( + send_contiguous_frame( + bench.client_source, + raw_app_beats_from_bytes(client_payload, dest=0x01, bcf=1), + clk=bench.clk, + ) + ) + server_observed = await recv_frame( + bench.server_sink, + clk=bench.clk, + ready_signal=dut.mServerAppTReady, + timeout_cycles=256, + ) + await client_send + + assert payload_from_raw_beats(server_observed) == client_payload + assert server_observed[0].dest == 0xFF + assert server_observed[0].bcf == 1 + assert server_observed[0].sof == 1 + assert server_observed[-1].eofe == 0 + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="raw_eth_framer_pair_flat_wrapper")]) +def test_RawEthFramerPair(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.rawethframerpairflatwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": RAWETH_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/RawEthFramer/test_RawEthFramerRx.py b/tests/ethernet/RawEthFramer/test_RawEthFramerRx.py new file mode 100644 index 0000000000..a0c9378020 --- /dev/null +++ b/tests/ethernet/RawEthFramer/test_RawEthFramerRx.py @@ -0,0 +1,215 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Cover the RawEthFramerRx leaf across lookup-gated unicast decode, +# broadcast bypass, short-frame trim behavior from the header `minByteCnt`, +# and representative reject cases for malformed or mismatched traffic. +# - Stimulus: Drive curated raw-Ethernet wire frames into the flattened RX +# wrapper, hold `ack` low until the DUT raises the exported lookup `req`, +# then answer with either the matching remote MAC or leave the frame to the +# broadcast/reject path without a lookup acknowledgement. +# - Checks: Valid unicast frames must request the expected `tDest`, wait for +# the lookup handshake, trim padded bytes back to the encoded payload length, +# preserve SOF/BCF/EOFE, accept broadcast frames without lookup, and drop +# invalid EtherType, invalid broadcast metadata, and source-MAC mismatches. +# - Timing: The bench synchronizes to `req` and output handshakes because the +# RX path has explicit header, lookup, and move states. + +from __future__ import annotations + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + expect_no_output, + frame_beats_from_bytes, + recv_frame, + send_contiguous_frame, +) +from tests.ethernet.RawEthFramer.raw_eth_test_utils import ( + ETH_TYPE_CFG, + LOCAL_MAC_CFG, + LOCAL_MAC_WIRE, + REMOTE_MAC_CFG, + REMOTE_MAC_WIRE, + ALT_REMOTE_MAC_WIRE, + RAWETH_BEAT_BYTES, + RAWETH_RTL_SOURCES, + build_raw_eth_wire_frame, + payload_from_raw_beats, + pulse_signal, + raweth_header_bytes, + setup_raw_eth_rx_bench, + wait_lookup_request, +) + + +WRAPPER_PATH = "ethernet/RawEthFramer/wrappers/RawEthFramerRxFlatWrapper.vhd" + + +@cocotb.test() +async def raw_eth_rx_waits_for_lookup_and_trims_short_frame_test(dut): + bench = await setup_raw_eth_rx_bench(dut) + + actual_payload = b"rx-trim-test" + padded_payload = actual_payload + bytes(16 - len(actual_payload)) + + # Model the short-frame TX output form: a padded MAC beat sequence with the + # real byte count carried in the raw-Ethernet header metadata. + short_frame = build_raw_eth_wire_frame( + dst_mac=LOCAL_MAC_WIRE, + src_mac=REMOTE_MAC_WIRE, + dest=0x19, + bcf=0, + payload=padded_payload, + min_byte_count=16 + len(actual_payload), + eth_type_cfg=ETH_TYPE_CFG, + ) + + send_task = cocotb.start_soon( + send_contiguous_frame( + bench.source, + frame_beats_from_bytes(short_frame, beat_bytes=RAWETH_BEAT_BYTES, eofe=1), + clk=bench.clk, + ) + ) + + # The leaf should publish the requested lookup destination before any app + # payload is released, which is the externally visible contract here. + observed_dest = await wait_lookup_request(dut, clk=bench.clk) + assert observed_dest == 0x19 + await expect_no_output(bench.sink, clk=bench.clk, cycles=4) + + dut.remoteMac.value = REMOTE_MAC_CFG + await pulse_signal(dut.ack, clk=bench.clk) + + # After the lookup is acknowledged, the output stream should trim away the + # padded zeros and recover the original short payload length. + observed = await recv_frame( + bench.sink, + clk=bench.clk, + ready_signal=dut.mAppTReady, + timeout_cycles=128, + ) + await send_task + + assert payload_from_raw_beats(observed) == actual_payload + assert observed[0].dest == 0x19 + assert observed[0].bcf == 0 + assert observed[0].sof == 1 + assert observed[-1].eofe == 1 + + +@cocotb.test() +async def raw_eth_rx_broadcast_bypass_and_reject_cases_test(dut): + bench = await setup_raw_eth_rx_bench(dut) + + broadcast_payload = b"rx-broadcast" + + # Broadcast traffic should bypass the lookup handshake and emerge directly + # on the app-side output with `BCF` asserted and `tDest` set to 0xFF. + broadcast_send = cocotb.start_soon( + send_contiguous_frame( + bench.source, + frame_beats_from_bytes( + build_raw_eth_wire_frame( + dst_mac=0xFFFF_FFFF_FFFF, + src_mac=ALT_REMOTE_MAC_WIRE, + dest=0xFF, + bcf=1, + payload=broadcast_payload, + min_byte_count=16 + len(broadcast_payload), + eth_type_cfg=ETH_TYPE_CFG, + ), + beat_bytes=RAWETH_BEAT_BYTES, + ), + clk=bench.clk, + ) + ) + broadcast_observed = await recv_frame( + bench.sink, + clk=bench.clk, + ready_signal=dut.mAppTReady, + timeout_cycles=128, + ) + await broadcast_send + + assert payload_from_raw_beats(broadcast_observed) == broadcast_payload + assert broadcast_observed[0].dest == 0xFF + assert broadcast_observed[0].bcf == 1 + assert int(dut.req.value) == 0 + + # Wrong-EtherType traffic must be discarded before the lookup state. + wrong_type = ( + LOCAL_MAC_WIRE.to_bytes(6, byteorder="big") + + REMOTE_MAC_WIRE.to_bytes(6, byteorder="big") + + b"\x08\x00" + + raweth_header_bytes(dest=0x41, bcf=0, min_byte_count=0) + ) + await send_contiguous_frame( + bench.source, + frame_beats_from_bytes(wrong_type, beat_bytes=RAWETH_BEAT_BYTES), + clk=bench.clk, + ) + await expect_no_output(bench.sink, clk=bench.clk, cycles=8) + + # A malformed broadcast marker must also be dropped without forwarding. + bad_broadcast = build_raw_eth_wire_frame( + dst_mac=LOCAL_MAC_WIRE, + src_mac=ALT_REMOTE_MAC_WIRE, + dest=0x01, + bcf=1, + payload=b"", + min_byte_count=0, + eth_type_cfg=ETH_TYPE_CFG, + ) + await send_contiguous_frame( + bench.source, + frame_beats_from_bytes(bad_broadcast, beat_bytes=RAWETH_BEAT_BYTES), + clk=bench.clk, + ) + await expect_no_output(bench.sink, clk=bench.clk, cycles=8) + + # A source-MAC mismatch should still make it through the lookup state, but + # it must drop before payload release once the lookup result is checked. + mismatch_frame = build_raw_eth_wire_frame( + dst_mac=LOCAL_MAC_WIRE, + src_mac=ALT_REMOTE_MAC_WIRE, + dest=0x41, + bcf=0, + payload=b"", + min_byte_count=0, + eth_type_cfg=ETH_TYPE_CFG, + ) + mismatch_send = cocotb.start_soon( + send_contiguous_frame( + bench.source, + frame_beats_from_bytes(mismatch_frame, beat_bytes=RAWETH_BEAT_BYTES), + clk=bench.clk, + ) + ) + assert await wait_lookup_request(dut, clk=bench.clk) == 0x41 + dut.remoteMac.value = REMOTE_MAC_CFG + await pulse_signal(dut.ack, clk=bench.clk) + await mismatch_send + await expect_no_output(bench.sink, clk=bench.clk, cycles=8) + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="raw_eth_framer_rx_flat_wrapper")]) +def test_RawEthFramerRx(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.rawethframerrxflatwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": RAWETH_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/RawEthFramer/test_RawEthFramerTx.py b/tests/ethernet/RawEthFramer/test_RawEthFramerTx.py new file mode 100644 index 0000000000..cfcb29a364 --- /dev/null +++ b/tests/ethernet/RawEthFramer/test_RawEthFramerTx.py @@ -0,0 +1,135 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Cover the RawEthFramerTx leaf across the lookup-facing request path, +# the stable broadcast bypass path, and the drop path when a unicast lookup +# resolves to zero. +# - Stimulus: Drive app-side raw-Ethernet payload frames into the flattened TX +# wrapper, hold the lookup `ack` low while observing `req`/`tDest`, then use +# the broadcast or zero-MAC miss branches for the complete on-wire checks. +# - Checks: Unicast traffic must expose the requested `tDest` and stall until +# lookup completion, broadcast traffic must bypass lookup and emit the +# expected padded wire image, and unicast traffic must drop when the resolved +# remote MAC is zero. +# - Timing: The bench waits on the exported lookup request and on accepted AXIS +# handshakes rather than assuming a fixed latency through the cache logic. + +from __future__ import annotations + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + expect_no_output, + payload_from_beats, + recv_frame, + send_contiguous_frame, +) +from tests.ethernet.RawEthFramer.raw_eth_test_utils import ( + ETH_TYPE_CFG, + LOCAL_MAC_WIRE, + RAWETH_BEAT_BYTES, + RAWETH_RTL_SOURCES, + build_raw_eth_wire_frame, + pad_to_raw_eth_lane_width, + pulse_signal, + raw_app_beats_from_bytes, + setup_raw_eth_tx_bench, + wait_lookup_request, +) + + +WRAPPER_PATH = "ethernet/RawEthFramer/wrappers/RawEthFramerTxFlatWrapper.vhd" + + +@cocotb.test() +async def raw_eth_tx_exposes_lookup_request_before_forwarding_test(dut): + bench = await setup_raw_eth_tx_bench(dut) + + payload = b"lookup1!" + beat = raw_app_beats_from_bytes(payload, dest=0x2A, eofe=1)[0] + + # Present a unicast SOF beat and hold it visible. The TX leaf should raise + # `req` with the selected `tDest` before it is allowed to forward anything. + bench.source.drive(beat) + + # The leaf contract is the exported lookup handshake, so observe it + # directly while `ack` remains low. + observed_dest = await wait_lookup_request(dut, clk=bench.clk) + assert observed_dest == 0x2A + await expect_no_output(bench.sink, clk=bench.clk, cycles=4) + bench.source.set_idle() + + +@cocotb.test() +async def raw_eth_tx_broadcast_bypasses_lookup_test(dut): + bench = await setup_raw_eth_tx_bench(dut) + + broadcast_payload = b"broadcast-leaf-path" + broadcast_wire_payload = pad_to_raw_eth_lane_width(broadcast_payload, lane_bytes=RAWETH_BEAT_BYTES) + + # Broadcast traffic should not need a lookup handshake at all; the module + # can forward it immediately with the all-ones destination MAC. + broadcast_send = cocotb.start_soon( + send_contiguous_frame( + bench.source, + raw_app_beats_from_bytes(broadcast_payload, dest=0xFF, bcf=1), + clk=bench.clk, + ) + ) + broadcast_observed = await recv_frame( + bench.sink, + clk=bench.clk, + ready_signal=dut.mMacTReady, + timeout_cycles=128, + ) + await broadcast_send + + assert payload_from_beats(broadcast_observed, lane_bytes=8) == build_raw_eth_wire_frame( + dst_mac=0xFFFF_FFFF_FFFF, + src_mac=LOCAL_MAC_WIRE, + dest=0xFF, + bcf=1, + payload=broadcast_wire_payload, + min_byte_count=16 + len(broadcast_payload), + eth_type_cfg=ETH_TYPE_CFG, + ) + assert int(dut.req.value) == 0 + + +@cocotb.test() +async def raw_eth_tx_zero_mac_lookup_miss_drops_before_forwarding_test(dut): + bench = await setup_raw_eth_tx_bench(dut) + + miss_beat = raw_app_beats_from_bytes(b"drop-miss", dest=0x33)[0] + + # Drive a unicast beat just far enough to reach the lookup state. + bench.source.drive(miss_beat) + assert await wait_lookup_request(dut, clk=bench.clk) == 0x33 + + # A zero remote-MAC response should cause the DUT to abandon the frame + # without ever presenting a MAC-side transfer. + dut.remoteMac.value = 0 + await pulse_signal(dut.ack, clk=bench.clk) + bench.source.set_idle() + await expect_no_output(bench.sink, clk=bench.clk, cycles=12) + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="raw_eth_framer_tx_flat_wrapper")]) +def test_RawEthFramerTx(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.rawethframertxflatwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": RAWETH_RTL_SOURCES + [WRAPPER_PATH]}, + ) From f5319c8b7150b7cf16c20bc0d99b570d5beea1ac Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 16 Apr 2026 13:54:56 -0700 Subject: [PATCH 12/92] Cleanup --- tests/ethernet/EthMacCore/ethmac_test_utils.py | 10 ++++++++++ tests/ethernet/EthMacCore/test_EthMacFlowCtrl.py | 2 ++ tests/ethernet/EthMacCore/test_EthMacRx.py | 13 +++---------- tests/ethernet/EthMacCore/test_EthMacRxCsum.py | 2 ++ tests/ethernet/EthMacCore/test_EthMacRxFifo.py | 2 ++ tests/ethernet/EthMacCore/test_EthMacRxFilter.py | 2 ++ tests/ethernet/EthMacCore/test_EthMacRxImport.py | 2 ++ tests/ethernet/EthMacCore/test_EthMacRxPause.py | 2 ++ tests/ethernet/EthMacCore/test_EthMacRxShift.py | 2 ++ tests/ethernet/EthMacCore/test_EthMacTop.py | 13 +++---------- tests/ethernet/EthMacCore/test_EthMacTx.py | 13 +++---------- tests/ethernet/EthMacCore/test_EthMacTxCsum.py | 2 ++ tests/ethernet/EthMacCore/test_EthMacTxExport.py | 2 ++ tests/ethernet/EthMacCore/test_EthMacTxFifo.py | 2 ++ tests/ethernet/EthMacCore/test_EthMacTxPause.py | 2 ++ tests/ethernet/EthMacCore/test_EthMacTxShift.py | 2 ++ tests/ethernet/IpV4Engine/test_ArpEngine.py | 4 ++++ tests/ethernet/IpV4Engine/test_IcmpEngine.py | 4 ++++ tests/ethernet/IpV4Engine/test_IpV4Engine.py | 4 ++++ tests/ethernet/IpV4Engine/test_IpV4EngineDeMux.py | 4 ++++ tests/ethernet/IpV4Engine/test_IpV4EngineRx.py | 4 ++++ tests/ethernet/IpV4Engine/test_IpV4EngineTx.py | 4 ++++ 22 files changed, 67 insertions(+), 30 deletions(-) diff --git a/tests/ethernet/EthMacCore/ethmac_test_utils.py b/tests/ethernet/EthMacCore/ethmac_test_utils.py index 15dc607c52..2134141164 100644 --- a/tests/ethernet/EthMacCore/ethmac_test_utils.py +++ b/tests/ethernet/EthMacCore/ethmac_test_utils.py @@ -26,6 +26,16 @@ ] ETHMAC_RTL_SOURCES.append(str(Path(__file__).resolve().parents[3] / "dsp" / "xilinx" / "logic" / "DspXor.vhd")) +ROCE_RTL_ROOT = Path(__file__).resolve().parents[3] / "ethernet" / "RoCEv2" / "rtl" +ROCE_ANALYSIS_SOURCES = [ + str(ROCE_RTL_ROOT / "RocePkg.vhd"), + *( + str(path) + for path in sorted(ROCE_RTL_ROOT.glob("*.vhd")) + if path.name != "RocePkg.vhd" + ), +] + @dataclass class EmacBeat: diff --git a/tests/ethernet/EthMacCore/test_EthMacFlowCtrl.py b/tests/ethernet/EthMacCore/test_EthMacFlowCtrl.py index 23c7f10dba..fc493935e2 100644 --- a/tests/ethernet/EthMacCore/test_EthMacFlowCtrl.py +++ b/tests/ethernet/EthMacCore/test_EthMacFlowCtrl.py @@ -20,6 +20,8 @@ # - Timing: The DUT is fully registered, so checks sample one clock after each # control update instead of relying on combinational observation. +from __future__ import annotations + import cocotb import pytest from cocotb.clock import Clock diff --git a/tests/ethernet/EthMacCore/test_EthMacRx.py b/tests/ethernet/EthMacCore/test_EthMacRx.py index 641f0e3d7e..6a534ff9cd 100644 --- a/tests/ethernet/EthMacCore/test_EthMacRx.py +++ b/tests/ethernet/EthMacCore/test_EthMacRx.py @@ -23,14 +23,16 @@ # internal latency because the DUT chains import, pause, checksum, bypass, # and filter stages. +from __future__ import annotations + import cocotb import pytest -from pathlib import Path from tests.common.regression_utils import run_surf_vhdl_test from tests.ethernet.EthMacCore.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, FlatEmacEndpoint, + ROCE_ANALYSIS_SOURCES, build_ethernet_frame, build_ipv4_udp_frame, build_pause_frame, @@ -46,15 +48,6 @@ WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacRxLoopbackWrapper.vhd" -ROCE_RTL_ROOT = Path(__file__).resolve().parents[3] / "ethernet" / "RoCEv2" / "rtl" -ROCE_ANALYSIS_SOURCES = [ - str(ROCE_RTL_ROOT / "RocePkg.vhd"), - *( - str(path) - for path in sorted(ROCE_RTL_ROOT.glob("*.vhd")) - if path.name != "RocePkg.vhd" - ), -] LOCAL_MAC_WIRE = 0x001122334455 LOCAL_MAC_CFG = mac_config_word_from_wire(LOCAL_MAC_WIRE) diff --git a/tests/ethernet/EthMacCore/test_EthMacRxCsum.py b/tests/ethernet/EthMacCore/test_EthMacRxCsum.py index 5d206b7464..e42fdd8338 100644 --- a/tests/ethernet/EthMacCore/test_EthMacRxCsum.py +++ b/tests/ethernet/EthMacCore/test_EthMacRxCsum.py @@ -20,6 +20,8 @@ # - Timing: The RX checksum block has an internal pipeline, so every case waits # on the visible output frame instead of assuming a fixed internal latency. +from __future__ import annotations + import cocotb import pytest diff --git a/tests/ethernet/EthMacCore/test_EthMacRxFifo.py b/tests/ethernet/EthMacCore/test_EthMacRxFifo.py index 39a4b3d533..29e0c93fc0 100644 --- a/tests/ethernet/EthMacCore/test_EthMacRxFifo.py +++ b/tests/ethernet/EthMacCore/test_EthMacRxFifo.py @@ -20,6 +20,8 @@ # - Timing: The test uses distinct source and sink clocks, and waits on the # visible FIFO controls instead of assuming a fixed occupancy latency. +from __future__ import annotations + import cocotb import pytest diff --git a/tests/ethernet/EthMacCore/test_EthMacRxFilter.py b/tests/ethernet/EthMacCore/test_EthMacRxFilter.py index 21126f6b69..590b6fb5ee 100644 --- a/tests/ethernet/EthMacCore/test_EthMacRxFilter.py +++ b/tests/ethernet/EthMacCore/test_EthMacRxFilter.py @@ -21,6 +21,8 @@ # - Timing: The block has no output backpressure, so each frame is launched # continuously and the sink watches for visible output rather than handshakes. +from __future__ import annotations + import cocotb import pytest diff --git a/tests/ethernet/EthMacCore/test_EthMacRxImport.py b/tests/ethernet/EthMacCore/test_EthMacRxImport.py index df98b5b300..4be4ef18f7 100644 --- a/tests/ethernet/EthMacCore/test_EthMacRxImport.py +++ b/tests/ethernet/EthMacCore/test_EthMacRxImport.py @@ -23,6 +23,8 @@ # - Timing: GMII takes many more cycles than XGMII to serialize a frame, so the # bench scales its receive timeout to the selected PHY mode. +from __future__ import annotations + import cocotb import os import pytest diff --git a/tests/ethernet/EthMacCore/test_EthMacRxPause.py b/tests/ethernet/EthMacCore/test_EthMacRxPause.py index f5d69db741..fd2f075112 100644 --- a/tests/ethernet/EthMacCore/test_EthMacRxPause.py +++ b/tests/ethernet/EthMacCore/test_EthMacRxPause.py @@ -20,6 +20,8 @@ # - Timing: The output path has no backpressure, so the test launches each # frame continuously and watches the visible output beats directly. +from __future__ import annotations + import cocotb import pytest from cocotb.triggers import RisingEdge, Timer diff --git a/tests/ethernet/EthMacCore/test_EthMacRxShift.py b/tests/ethernet/EthMacCore/test_EthMacRxShift.py index a58f1f030f..6f409ac834 100644 --- a/tests/ethernet/EthMacCore/test_EthMacRxShift.py +++ b/tests/ethernet/EthMacCore/test_EthMacRxShift.py @@ -20,6 +20,8 @@ # - Timing: The RX shift block has no sink-side backpressure, so the frame is # launched continuously and the test samples the visible output beats. +from __future__ import annotations + import cocotb import pytest diff --git a/tests/ethernet/EthMacCore/test_EthMacTop.py b/tests/ethernet/EthMacCore/test_EthMacTop.py index eb8ecebaf0..f4a2f77dfd 100644 --- a/tests/ethernet/EthMacCore/test_EthMacTop.py +++ b/tests/ethernet/EthMacCore/test_EthMacTop.py @@ -22,13 +22,15 @@ # fixed internal pipeline depth, because the top-level MAC includes FIFO, # pause, and import/export staging. +from __future__ import annotations + import cocotb import pytest -from pathlib import Path from tests.common.regression_utils import parameter_case, run_surf_vhdl_test from tests.ethernet.EthMacCore.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, + ROCE_ANALYSIS_SOURCES, build_ethernet_frame, build_ipv4_udp_frame, build_pause_frame, @@ -46,15 +48,6 @@ WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacTopLoopbackWrapper.vhd" -ROCE_RTL_ROOT = Path(__file__).resolve().parents[3] / "ethernet" / "RoCEv2" / "rtl" -ROCE_ANALYSIS_SOURCES = [ - str(ROCE_RTL_ROOT / "RocePkg.vhd"), - *( - str(path) - for path in sorted(ROCE_RTL_ROOT.glob("*.vhd")) - if path.name != "RocePkg.vhd" - ), -] LOCAL_MAC_WIRE = 0x001122334455 LOCAL_MAC_CFG = mac_config_word_from_wire(LOCAL_MAC_WIRE) diff --git a/tests/ethernet/EthMacCore/test_EthMacTx.py b/tests/ethernet/EthMacCore/test_EthMacTx.py index 0e4d495d93..42612682f3 100644 --- a/tests/ethernet/EthMacCore/test_EthMacTx.py +++ b/tests/ethernet/EthMacCore/test_EthMacTx.py @@ -24,14 +24,16 @@ # cycle delays because the TX path includes arbitration, checksum, pause, and # export staging. +from __future__ import annotations + import cocotb import pytest -from pathlib import Path from tests.common.regression_utils import run_surf_vhdl_test from tests.ethernet.EthMacCore.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, FlatEmacEndpoint, + ROCE_ANALYSIS_SOURCES, build_ethernet_frame, build_ipv4_udp_frame, build_pause_frame, @@ -49,15 +51,6 @@ WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacTxLoopbackWrapper.vhd" -ROCE_RTL_ROOT = Path(__file__).resolve().parents[3] / "ethernet" / "RoCEv2" / "rtl" -ROCE_ANALYSIS_SOURCES = [ - str(ROCE_RTL_ROOT / "RocePkg.vhd"), - *( - str(path) - for path in sorted(ROCE_RTL_ROOT.glob("*.vhd")) - if path.name != "RocePkg.vhd" - ), -] LOCAL_MAC_CFG = mac_config_word_from_wire(0x001122334455) diff --git a/tests/ethernet/EthMacCore/test_EthMacTxCsum.py b/tests/ethernet/EthMacCore/test_EthMacTxCsum.py index 50fa942b6c..19e83508f8 100644 --- a/tests/ethernet/EthMacCore/test_EthMacTxCsum.py +++ b/tests/ethernet/EthMacCore/test_EthMacTxCsum.py @@ -22,6 +22,8 @@ # the bench waits on the post-checker frame rather than assuming a fixed # internal pipeline delay. +from __future__ import annotations + import cocotb import pytest diff --git a/tests/ethernet/EthMacCore/test_EthMacTxExport.py b/tests/ethernet/EthMacCore/test_EthMacTxExport.py index 6fa3505a21..bfb7defc9b 100644 --- a/tests/ethernet/EthMacCore/test_EthMacTxExport.py +++ b/tests/ethernet/EthMacCore/test_EthMacTxExport.py @@ -23,6 +23,8 @@ # - Timing: The receive timeout is scaled to the chosen PHY because the GMII # path serializes one byte per clock while XGMII transmits eight. +from __future__ import annotations + import cocotb import os import pytest diff --git a/tests/ethernet/EthMacCore/test_EthMacTxFifo.py b/tests/ethernet/EthMacCore/test_EthMacTxFifo.py index d83f16e7e6..91faf124e5 100644 --- a/tests/ethernet/EthMacCore/test_EthMacTxFifo.py +++ b/tests/ethernet/EthMacCore/test_EthMacTxFifo.py @@ -20,6 +20,8 @@ # - Timing: The two clocks intentionally run at different periods, so the test # waits on visible handshakes instead of assuming synchronous phasing. +from __future__ import annotations + import cocotb import pytest diff --git a/tests/ethernet/EthMacCore/test_EthMacTxPause.py b/tests/ethernet/EthMacCore/test_EthMacTxPause.py index 6500f63ff1..a862f05642 100644 --- a/tests/ethernet/EthMacCore/test_EthMacTxPause.py +++ b/tests/ethernet/EthMacCore/test_EthMacTxPause.py @@ -22,6 +22,8 @@ # - Timing: The sink uses explicit `TREADY` handshakes so pause frames, gated # payload frames, and pass-through traffic are all observed deliberately. +from __future__ import annotations + import cocotb import pytest diff --git a/tests/ethernet/EthMacCore/test_EthMacTxShift.py b/tests/ethernet/EthMacCore/test_EthMacTxShift.py index 551ae86bdf..c15e35e842 100644 --- a/tests/ethernet/EthMacCore/test_EthMacTxShift.py +++ b/tests/ethernet/EthMacCore/test_EthMacTxShift.py @@ -20,6 +20,8 @@ # - Timing: The TX shift stage participates in the AXI handshake, so the sink # explicitly raises `TREADY` while consuming the output frame. +from __future__ import annotations + import cocotb import pytest diff --git a/tests/ethernet/IpV4Engine/test_ArpEngine.py b/tests/ethernet/IpV4Engine/test_ArpEngine.py index 96f6e96e67..29b18cc214 100644 --- a/tests/ethernet/IpV4Engine/test_ArpEngine.py +++ b/tests/ethernet/IpV4Engine/test_ArpEngine.py @@ -9,6 +9,8 @@ ############################################################################## # Test methodology: +# - Sweep: Exercise the ARP engine across localhost resolution, remote lookup +# plus reply handling, and inbound request-to-reply generation. # - Stimulus: Exercise the ARP engine with a localhost lookup, a remote lookup # that requires an outbound request and inbound reply, and an inbound ARP # request addressed to the local host. @@ -18,6 +20,8 @@ # - Timing: The test uses real ready/valid handshakes for both client and MAC # sides so request/ack routing remains visible. +from __future__ import annotations + import cocotb import pytest diff --git a/tests/ethernet/IpV4Engine/test_IcmpEngine.py b/tests/ethernet/IpV4Engine/test_IcmpEngine.py index 8372fdc0f7..605481e0c5 100644 --- a/tests/ethernet/IpV4Engine/test_IcmpEngine.py +++ b/tests/ethernet/IpV4Engine/test_IcmpEngine.py @@ -9,6 +9,8 @@ ############################################################################## # Test methodology: +# - Sweep: Cover the ICMP reply block with one valid local echo request plus +# two representative reject cases: wrong destination IP and non-echo type. # - Stimulus: Present ICMP pseudo-header traffic exactly as IpV4EngineRx would # emit it, including a valid echo request, a non-local request, and a # non-echo ICMP packet. @@ -18,6 +20,8 @@ # - Timing: The bench waits on AXIS visibility so the assertions remain stable # across internal pipeline depth changes. +from __future__ import annotations + import cocotb import pytest diff --git a/tests/ethernet/IpV4Engine/test_IpV4Engine.py b/tests/ethernet/IpV4Engine/test_IpV4Engine.py index 76a74d2177..dc9387cf5d 100644 --- a/tests/ethernet/IpV4Engine/test_IpV4Engine.py +++ b/tests/ethernet/IpV4Engine/test_IpV4Engine.py @@ -9,6 +9,8 @@ ############################################################################## # Test methodology: +# - Sweep: Exercise the IPv4 top across one UDP receive path, one ICMP +# echo-response path, and one ARP client lookup round-trip. # - Stimulus: Exercise the full IPv4 top with three focused scenarios: # inbound UDP routing, inbound ICMP echo handling, and ARP client lookup. # - Checks: UDP traffic must emerge on the protocol output slot as the expected @@ -17,6 +19,8 @@ # - Timing: Each scenario uses handshaked sources and sinks so the top-level # assembly is verified through its real interfaces instead of local shortcuts. +from __future__ import annotations + import cocotb import pytest diff --git a/tests/ethernet/IpV4Engine/test_IpV4EngineDeMux.py b/tests/ethernet/IpV4Engine/test_IpV4EngineDeMux.py index 766ee06f32..78f27e0c4e 100644 --- a/tests/ethernet/IpV4Engine/test_IpV4EngineDeMux.py +++ b/tests/ethernet/IpV4Engine/test_IpV4EngineDeMux.py @@ -9,6 +9,8 @@ ############################################################################## # Test methodology: +# - Sweep: Drive the de-mux through ARP forwarding, IPv4 forwarding, accepted +# broadcast handling, and two drop paths for foreign and malformed traffic. # - Stimulus: Feed the de-mux with full Ethernet frames that exercise the ARP, # IPv4, broadcast, foreign-destination, and bad-version cases. # - Checks: ARP and IPv4 frames for the local or broadcast MAC must be @@ -17,6 +19,8 @@ # - Timing: The test waits on visible AXIS transfers instead of fixed cycle # counts because the wrapper exposes real ready/valid behavior. +from __future__ import annotations + import cocotb import pytest diff --git a/tests/ethernet/IpV4Engine/test_IpV4EngineRx.py b/tests/ethernet/IpV4Engine/test_IpV4EngineRx.py index fec12f306d..0502476575 100644 --- a/tests/ethernet/IpV4Engine/test_IpV4EngineRx.py +++ b/tests/ethernet/IpV4Engine/test_IpV4EngineRx.py @@ -9,6 +9,8 @@ ############################################################################## # Test methodology: +# - Sweep: Cover one UDP protocol route, one ICMP protocol route, and one +# unsupported-protocol drop through the receive engine. # - Stimulus: Drive complete Ethernet/IPv4 frames into IpV4EngineRx for one # UDP packet, one ICMP packet, and one unsupported protocol packet. # - Checks: The UDP and ICMP cases must emerge as the expected pseudo-header @@ -17,6 +19,8 @@ # - Timing: The bench waits on the protocol output streams rather than fixed # latency assumptions because the receive engine has multiple header states. +from __future__ import annotations + import cocotb import pytest diff --git a/tests/ethernet/IpV4Engine/test_IpV4EngineTx.py b/tests/ethernet/IpV4Engine/test_IpV4EngineTx.py index 74aa175254..4431101e03 100644 --- a/tests/ethernet/IpV4Engine/test_IpV4EngineTx.py +++ b/tests/ethernet/IpV4Engine/test_IpV4EngineTx.py @@ -9,6 +9,8 @@ ############################################################################## # Test methodology: +# - Sweep: Cover both meaningful TX routes in one build: remote wire output +# and localhost short-circuit output. # - Stimulus: Feed the TX engine with curated pseudo-header traffic for one # remote UDP packet and one localhost-routed UDP packet. # - Checks: The remote packet must emerge as a fully framed Ethernet/IPv4 @@ -17,6 +19,8 @@ # - Timing: The test drives one packet at a time and waits on the selected # output stream so route-selection bugs are obvious in waveforms. +from __future__ import annotations + import cocotb import pytest From 43843c5a6a11eb7e5bbcbef4fc4504391ef5713f Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 17 Apr 2026 10:26:48 -0700 Subject: [PATCH 13/92] UDP tests first pass. --- docs/_meta/rtl_regression_handoff.md | 7 +- docs/_meta/rtl_regression_progress.md | 14 +- .../wrappers/ArpIpTableFlatWrapper.vhd | 72 +++ .../wrappers/UdpEngineArpFlatWrapper.vhd | 131 ++++++ .../wrappers/UdpEngineDhcpFlatWrapper.vhd | 107 +++++ .../wrappers/UdpEngineRxFlatWrapper.vhd | 181 +++++++ .../wrappers/UdpEngineTopFlatWrapper.vhd | 280 +++++++++++ .../wrappers/UdpEngineTxFlatWrapper.vhd | 163 +++++++ .../wrappers/UdpEngineWrapperFlatWrapper.vhd | 269 +++++++++++ .../UdpEngineWrapperPairFlatWrapper.vhd | 299 ++++++++++++ tests/ethernet/UdpEngine/__init__.py | 9 + tests/ethernet/UdpEngine/test_ArpIpTable.py | 127 +++++ tests/ethernet/UdpEngine/test_UdpEngine.py | 124 +++++ tests/ethernet/UdpEngine/test_UdpEngineArp.py | 123 +++++ .../ethernet/UdpEngine/test_UdpEngineDhcp.py | 132 ++++++ tests/ethernet/UdpEngine/test_UdpEngineRx.py | 146 ++++++ tests/ethernet/UdpEngine/test_UdpEngineTx.py | 110 +++++ .../UdpEngine/test_UdpEngineWrapper.py | 96 ++++ .../UdpEngine/test_UdpEngineWrapperPair.py | 128 +++++ tests/ethernet/UdpEngine/udp_test_utils.py | 445 ++++++++++++++++++ 20 files changed, 2955 insertions(+), 8 deletions(-) create mode 100644 ethernet/UdpEngine/wrappers/ArpIpTableFlatWrapper.vhd create mode 100644 ethernet/UdpEngine/wrappers/UdpEngineArpFlatWrapper.vhd create mode 100644 ethernet/UdpEngine/wrappers/UdpEngineDhcpFlatWrapper.vhd create mode 100644 ethernet/UdpEngine/wrappers/UdpEngineRxFlatWrapper.vhd create mode 100644 ethernet/UdpEngine/wrappers/UdpEngineTopFlatWrapper.vhd create mode 100644 ethernet/UdpEngine/wrappers/UdpEngineTxFlatWrapper.vhd create mode 100644 ethernet/UdpEngine/wrappers/UdpEngineWrapperFlatWrapper.vhd create mode 100644 ethernet/UdpEngine/wrappers/UdpEngineWrapperPairFlatWrapper.vhd create mode 100644 tests/ethernet/UdpEngine/__init__.py create mode 100644 tests/ethernet/UdpEngine/test_ArpIpTable.py create mode 100644 tests/ethernet/UdpEngine/test_UdpEngine.py create mode 100644 tests/ethernet/UdpEngine/test_UdpEngineArp.py create mode 100644 tests/ethernet/UdpEngine/test_UdpEngineDhcp.py create mode 100644 tests/ethernet/UdpEngine/test_UdpEngineRx.py create mode 100644 tests/ethernet/UdpEngine/test_UdpEngineTx.py create mode 100644 tests/ethernet/UdpEngine/test_UdpEngineWrapper.py create mode 100644 tests/ethernet/UdpEngine/test_UdpEngineWrapperPair.py create mode 100644 tests/ethernet/UdpEngine/udp_test_utils.py diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index 4187a0858f..70ba999b27 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -18,7 +18,7 @@ - Treat VHDL packages as transitively covered unless a behavioral function/procedure needs a dedicated wrapper ## Quick Resume Snapshot -- Current frontier: the axi-first pass is complete, the merged branch line now includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, and the earlier manual `ethernet/EthMacCore` slice is still in place. The immediate planning gap is that `docs/_meta/rtl_phase1_queue_overrides.json` still carries the old temporary `ethernet` / `protocols` deferrals, so the checked-in queue artifacts are now behind the real branch frontier. +- Current frontier: the axi-first pass is complete, the merged branch line now includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, and the manual Ethernet slice now spans `EthMacCore`, `RawEthFramer`, and `UdpEngine`. The immediate planning gap is still that `docs/_meta/rtl_phase1_queue_overrides.json` carries the old temporary `ethernet` / `protocols` deferrals, so the checked-in queue artifacts remain behind the real branch frontier. - Current axi frontier: complete for the intended simulator-friendly pass in this branch snapshot; do not resume from the older stale `AxiResize` note. - Current validated-open issues: - None currently recorded on this merged branch. `AxiResize` and `AxiStreamDmaV2Read` are both fixed here; queue/override refresh is the next step. @@ -35,7 +35,7 @@ - Use `start_lockstep_clocks()` when a DUT depends on truly shared clock edges. - Prefer explicit short sim-build keys for generated-wrapper benches when case metadata would otherwise create fragile build paths. - When a wrapper is checked in, write it like the surrounding repo HDL: include the SLAC/SURF banner and enough section comments that a new session can identify the shim, DUT, and flattening regions quickly. - - For `ethernet/EthMacCore`, the checked-in wrappers under `ethernet/EthMacCore/wrappers/` are now the expected cocotb surface. Keep using those flat EMAC beat wrappers rather than rebuilding record-packing logic in Python. + - For the current Ethernet slice, the checked-in wrappers under `ethernet/EthMacCore/wrappers/`, `ethernet/RawEthFramer/wrappers/`, and `ethernet/UdpEngine/wrappers/` are now the expected cocotb surfaces. Keep using those subsystem-local wrappers rather than rebuilding record-packing logic in Python. - Current cocotb-file discipline: - New test files should start with the standard SURF/SLAC header block. - The `Test methodology` block belongs directly under that header. @@ -57,6 +57,7 @@ - `tests/dsp/generic/dsp_test_utils.py` is now the shared home for DSP-specific signed helpers, rolling reference models, cocotb clock-settle timing, and generated FIR wrappers. Reuse it instead of cloning DSP arithmetic or wrapper boilerplate. - `tests/ethernet/EthMacCore/ethmac_test_utils.py` is now the shared home for the current Ethernet MAC slice: flat EMAC beat helpers, Ethernet/IPv4/UDP packet builders, checksum reference code, MAC-config byte-order helpers, and minimum-frame padding helpers. Reuse it instead of cloning packet or sideband plumbing across `EthMacCore` benches. - `tests/ethernet/RawEthFramer/raw_eth_test_utils.py` now holds the shared raw-Ethernet helper pieces: flat app-side beat helpers, raw-Ethernet header/frame builders, and lookup-handshake utilities reused by the `RawEthFramer`, `RawEthFramerRx`, and `RawEthFramerTx` benches. +- `tests/ethernet/UdpEngine/udp_test_utils.py` is now the shared home for the UDP slice: legacy-address constants, pseudo-frame builders, DHCP option helpers, and the common cocotb bench setup for the `ArpIpTable`, `UdpEngine*`, and `UdpEngineWrapper*` wrappers. Reuse it instead of rebuilding IPv4/UDP helper glue in each test module. - The current `EthMacCore` slice is intentionally a checked-in-wrapper-first rollout, not a cocotb-generated-wrapper experiment. Keep new Ethernet work on that same pattern unless the simulator forces a very local generic adapter. - The XGMII import/export loopback behavior differs from the GMII path when `phyReady` drops mid-traffic: the blocked frame is retained and drains after link recovery, padded to Ethernet's minimum frame size if it was short. The GMII path drops that blocked frame. Future import/export coverage should preserve that distinction instead of forcing one common expectation. - `EthMacRxCsum` reliably raises `IPERR` on a bad IPv4 header checksum, but the checked-in wrapper contract does not currently require `EOFE` for that case. Keep the negative test aligned to the real observable contract rather than to a stronger assumption. @@ -91,6 +92,8 @@ The first manual `ethernet/EthMacCore` wave is now also in place. The checked-in `ethernet/RawEthFramer/` now also has checked-in regression coverage under `tests/ethernet/RawEthFramer/`. The earlier top-level `RawEthFramer` wrapper bench is joined by direct leaf benches for `RawEthFramerRx` and `RawEthFramerTx`, plus a `RawEthFramerPair` integration bench whose wrapper cross-connects two `RawEthFramer` instances to mirror the legacy `ethernet/RawEthFramer/tb/RawEthFramerTb.vhd` topology. The validated RX leaf bench covers lookup-gated unicast decode, short-frame trim behavior, broadcast bypass, and representative reject cases. The validated TX leaf bench currently keeps a narrower first-pass subset: lookup-request exposure before forwarding, broadcast bypass with the observed padded wire image, and zero-MAC lookup-miss drop. Do not over-claim the broader multi-beat unicast completion path for `RawEthFramerTx`; that branch still needs follow-up before it should be considered a passing leaf-level contract. +`ethernet/UdpEngine/` now has checked-in regression coverage under `tests/ethernet/UdpEngine/` as well. The current validated set covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, all backed by checked-in wrappers under `ethernet/UdpEngine/wrappers/` and the shared helper layer in `tests/ethernet/UdpEngine/udp_test_utils.py`. The legacy `ethernet/UdpEngine/tb/UdpEngineTb.vhd` route-switching topology is also represented by `test_UdpEngineWrapperPair.py` plus a MAC-backed `UdpEngineWrapperPairFlatWrapper.vhd`, but that integrated pair bench has not yet been closed with a local passing run because the full four-MAC simulation is materially heavier than the rest of the slice. Treat the pair bench as implemented parity coverage that still needs dedicated validation time, not as a validated passing result. + The wrapper coverage policy is now more explicit in practice: test the wrapper-specific behavior, not the full leaf matrix again. `Fifo` validated both inferred sync/async selection branches, `FifoCascade` validated public stage-vector mapping plus a curated output smoke, and `FifoMux` is currently validated only on the stable split-to-narrow path. The pack-to-wide `FifoMux` path should be treated as still open rather than silently assumed covered. That same wrapper-policy lesson now applies to the late `base/sync` wrappers as well. `SyncClockFreq` is stable with a checked-in subsystem wrapper, but its common-clock measurement quantizes one count above the abstract target under the current GHDL flow, so the regression checks a bounded expected range rather than an exact integer. `SyncTrigRate` is intentionally covered as a wrapper/integration bench only: it proves aligned update publication, denser-window rate growth, reset-path liveness, and strobe pulse behavior, while exact min/max pipeline semantics remain the responsibility of the dedicated `SyncMinMax` leaf test. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 6d3753a1d9..bb34d6b258 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -2,15 +2,15 @@ ## Summary - Current phase: Phase-1 implementation active -- Current subsystem: cross-subsystem planning refresh after the merged `protocols/ssi`, `protocols/pgp`, and `ethernet/EthMacCore` waves -- Current focus module: refresh the stale phase-1 queue inputs and handoff summary so the next resume point reflects the current merged branch rather than the earlier temporary `axi/`-first deferrals. -- Last updated: 2026-04-16 +- Current subsystem: manual `ethernet/UdpEngine` wave during the broader post-merge queue-refresh gap +- Current focus module: stabilize and document the new `ethernet/UdpEngine` coverage while keeping the stale phase-1 queue-refresh gap explicit in the handoff artifacts. +- Last updated: 2026-04-17 ## Current Frontier Snapshot - Next queue target: remove the stale temporary `ethernet` and `protocols` subsystem deferrals, regenerate `docs/_meta/rtl_phase1_queue.{md,json}`, then take the next real non-deferred frontier from the refreshed queue. - Queue note: - The axi-first pass is now complete through the previously remaining final 11 `axi/` modules. - - The current `verification-2` branch already includes the merged `pre-release` state through PR #1392, so the validated `protocols/ssi`, `protocols/pgp`, and manual `ethernet/EthMacCore` waves are all part of the present branch snapshot. + - The current `verification-2` branch already includes the merged `pre-release` state through PR #1392, so the validated `protocols/ssi`, `protocols/pgp`, and manual Ethernet waves (`EthMacCore`, `RawEthFramer`, and now `UdpEngine`) are all part of the present branch snapshot. - The queue snapshot in `docs/_meta/rtl_phase1_queue.{md,json}` is therefore intentionally behind the actual branch contents because `rtl_phase1_queue_overrides.json` still defers `ethernet` and `protocols` from the earlier `axi/`-first phase. - `dsp/` is now included in the generated queue scope, so DSP rollout no longer needs to live on a hand-maintained side list. - Do not use the currently checked-in queue files as the next-module source of truth until those stale subsystem deferrals have been removed and the queue has been regenerated. @@ -20,7 +20,7 @@ - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. - - For `ethernet/EthMacCore`, keep using the checked-in wrappers under `ethernet/EthMacCore/wrappers/` plus the shared helper layer in `tests/ethernet/EthMacCore/ethmac_test_utils.py`. The practical first-pass shape is a flat EMAC beat wrapper with explicit sideband bits, curated PHY/runtime sweeps instead of exhaustive `PHY_TYPE_G` coverage, and helper-side handling for wire-level quirks such as minimum-frame padding and MAC-config byte order. + - For `ethernet`, keep using the checked-in wrappers under `ethernet/*/wrappers/` plus the shared helper layers in `tests/ethernet/EthMacCore/ethmac_test_utils.py`, `tests/ethernet/RawEthFramer/raw_eth_test_utils.py`, and `tests/ethernet/UdpEngine/udp_test_utils.py`. The practical first-pass shape is flat EMAC/app beat wrappers with explicit sideband bits, curated functional slices instead of exhaustive generic sweeps, and dedicated pair/integration wrappers only where an old VHDL bench contributes a topology worth preserving. The new `UdpEngineWrapperPair` legacy-topology bench is implemented on that pattern, but it still needs a longer dedicated local run before it should be treated as a validated parity result. ## Status | Subsystem | Inventory | Smoke | Functional | Notes | @@ -30,7 +30,7 @@ | `dsp` | started | not started | started | The planned `dsp/generic/fixed` leaf batch is now validated under `tests/dsp/generic/`: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. Shared DSP helpers now live in `tests/dsp/generic/dsp_test_utils.py`, and the legacy VHDL benches under `dsp/generic/tb/` were treated as behavioral reference material rather than as execution constraints. | | `axi` | started | not started | started | The axi-first pass is now complete for the simulator-friendly queue. The final locally validated batch adds `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`, with a combined `11 passed` validation run on 2026-03-27. Added checked-in subsystem wrappers under `axi/axi4/ip_integrator/`, `axi/axi-lite/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/` for those benches. `AxiStreamFifoV2` now has an expanded `10 passed` wrapper regression under `tests/axi/axi_stream/` covering async and sync width conversion, metadata truncation, `VALID_THOLD` frame-ready and burst-release modes, dynamic pause-threshold behavior, `CASCADE_SIZE=2`, and the `S_HAS_TREADY=0` pause-only source-side path. `AxiResize` now passes its equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` wrapper regression on this branch after the read-hold RTL fix. `AxiLiteAsync`, `AxiLiteToDrp`, and `AxiRateGen` still keep intentionally narrow common-clock subsets while the more timing-sensitive async AXI-Lite crossing branches remain open. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` still keep intentionally narrow first-pass subsets. `AxiStreamDmaV2Read` is now validated with a two-case wrapper regression covering both aligned and short terminal-beat reads after fixing bounded byte-count conversion in `AxiPkg` and terminal-mask generation in `AxiStreamDmaV2Read`. | | `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. | -| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` covers the first manual `EthMacCore` slice, and `tests/ethernet/RawEthFramer/` now adds direct leaf coverage for `RawEthFramerRx` and `RawEthFramerTx`, the top-level `RawEthFramer` wrapper bench, and a two-node pair wrapper that mirrors the old `ethernet/RawEthFramer/tb/RawEthFramerTb.vhd` transport topology. The RawEthFramer helper layer lives in `tests/ethernet/RawEthFramer/raw_eth_test_utils.py`, with checked-in wrappers under `ethernet/RawEthFramer/wrappers/`. The validated TX subset stays intentionally narrow at the leaf level: lookup-request exposure, broadcast bypass, and zero-MAC miss drop, while the broader multi-beat unicast completion path still needs a follow-up before it should be treated as a passing leaf-level contract. The generated queue still keeps the broader subsystem deferred until the post-axi refresh removes the temporary queue override. | +| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` covers the first manual `EthMacCore` slice, `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, and `tests/ethernet/UdpEngine/` now adds checked-in benches for `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper` backed by shared helpers in `tests/ethernet/UdpEngine/udp_test_utils.py` plus checked-in wrappers under `ethernet/UdpEngine/wrappers/`. The new `UdpEngineWrapperPair` bench and MAC-backed parity wrapper also exist to preserve the legacy `ethernet/UdpEngine/tb/UdpEngineTb.vhd` route-switching topology, but that integrated pair bench still needs a longer dedicated local validation run before it should be counted as a passing result. The RawEthFramer TX leaf and UdpEngine wrapper-pair parity paths therefore remain the two explicit Ethernet caveats inside an otherwise working manual subsystem wave. The generated queue still keeps the broader subsystem deferred until the post-axi refresh removes the temporary queue override. | | `devices` | not started | not started | not started | Many vendor-heavy cases | | `xilinx` | not started | not started | not started | Many vendor-heavy cases | @@ -250,6 +250,8 @@ - 2026-04-07: Expanded `tests/protocols/ssi/test_SsiFifo.py` beyond the earlier single-beat subset. The checked-in FIFO bench now proves contiguous 3-beat frame preservation on the default, `VALID_THOLD_G=0`, and `VALID_THOLD_G=2` wrapper paths; exercises repeated-`SOF` malformed-frame handling across the buffered modes; and keeps the existing missing-`SOF` drop plus `SLAVE_READY_EN_G=false` overflow checks. The buffered malformed-frame result is mode-specific at the wrapper boundary: `VALID_THOLD_G=0` drops the malformed repeated-`SOF` frame outright, while `VALID_THOLD_G=2` emits the expected two-beat terminated `EOFE` frame. A follow-up backpressure pass also added explicit drain-side ready toggling on a good 5-beat frame, malformed termination under toggled ready, and thresholded release under intermittent drain stalls so SSI frame policy is now checked under nontrivial sink backpressure without duplicating the full `AxiStreamFifoV2` transport matrix. Revalidated the full touched SSI slice locally with `19 passed`. - 2026-04-10: Landed the first manual `ethernet/EthMacCore` bench wave under `tests/ethernet/EthMacCore/`, added the required checked-in wrappers under `ethernet/EthMacCore/wrappers/`, and validated the baseline 12-module slice covering `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`. - 2026-04-10: Expanded that same `EthMacCore` slice beyond the initial happy paths. The checked-in Ethernet MAC suite now covers `EthMacTop` filter/backpressure/checksum/pause interactions, GMII and XGMII import/export plus link-not-ready recovery behavior, checksum negative cases, filter multicast/broadcast/filter-disable/multi-beat-drop behavior, shift runtime-control and control-bit propagation edges, and full byte-width `1..16` logic-path coverage for `EthCrc32Parallel`. The full `tests/ethernet/EthMacCore` directory currently passes locally with `32 passed`. +- 2026-04-17: Added the manual `ethernet/UdpEngine` wave under `tests/ethernet/UdpEngine/`. The checked-in helper layer now lives in `tests/ethernet/UdpEngine/udp_test_utils.py`, the new checked-in wrappers live under `ethernet/UdpEngine/wrappers/`, and the locally validated benches cover `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`. The current local validation command `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/UdpEngine/test_ArpIpTable.py tests/ethernet/UdpEngine/test_UdpEngineArp.py tests/ethernet/UdpEngine/test_UdpEngineDhcp.py tests/ethernet/UdpEngine/test_UdpEngineRx.py tests/ethernet/UdpEngine/test_UdpEngineTx.py tests/ethernet/UdpEngine/test_UdpEngine.py tests/ethernet/UdpEngine/test_UdpEngineWrapper.py` passes with `7 passed`. +- 2026-04-17: Added the legacy-topology parity bench for `ethernet/UdpEngine/tb/UdpEngineTb.vhd` as `tests/ethernet/UdpEngine/test_UdpEngineWrapperPair.py` backed by `ethernet/UdpEngine/wrappers/UdpEngineWrapperPairFlatWrapper.vhd`. That wrapper now includes the real `EthMacTop`/XGMII switch fabric instead of a simplified direct stream cross-couple so the preserved route-switching case matches the legacy bench architecture. The pair bench is implemented and lint-clean, but it still needs a longer dedicated local validation run before it should be counted as a passing result. - 2026-04-16: Merged the current `pre-release` branch into `verification-2`, so this branch line now contains the already-landed SSI and PGP waves from PR #1391 and PR #1392 in addition to the manual Ethernet slice. - 2026-04-16: Refreshed the planning docs to move the active frontier from “continue Ethernet next” to “refresh the stale queue/override inputs, then resume from the real merged-branch frontier.” - 2026-03-20: Added an explicit project rule to comment new Python regression code where intent or runner behavior is not self-evident. diff --git a/ethernet/UdpEngine/wrappers/ArpIpTableFlatWrapper.vhd b/ethernet/UdpEngine/wrappers/ArpIpTableFlatWrapper.vhd new file mode 100644 index 0000000000..36ce136922 --- /dev/null +++ b/ethernet/UdpEngine/wrappers/ArpIpTableFlatWrapper.vhd @@ -0,0 +1,72 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for ArpIpTable +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; + +entity ArpIpTableFlatWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + CLK_FREQ_G : real := 4.0; + COMM_TIMEOUT_G : positive := 2; + ENTRIES_G : positive range 1 to 255 := 4); + port ( + clk : in sl; + rst : in sl; + ipAddrIn : in slv(31 downto 0); + pos : in slv(7 downto 0); + found : out sl; + macAddr : out slv(47 downto 0); + ipAddrOut : out slv(31 downto 0); + clientRemoteDetIp : in slv(31 downto 0); + clientRemoteDetValid : in sl; + ipWrEn : in sl; + ipWrAddr : in slv(31 downto 0); + macWrEn : in sl; + macWrAddr : in slv(47 downto 0)); +end entity ArpIpTableFlatWrapper; + +architecture rtl of ArpIpTableFlatWrapper is + +begin + + U_DUT : entity surf.ArpIpTable + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + CLK_FREQ_G => CLK_FREQ_G, + COMM_TIMEOUT_G => COMM_TIMEOUT_G, + ENTRIES_G => ENTRIES_G) + port map ( + clk => clk, + rst => rst, + ipAddrIn => ipAddrIn, + pos => pos, + found => found, + macAddr => macAddr, + ipAddrOut => ipAddrOut, + clientRemoteDetIp => clientRemoteDetIp, + clientRemoteDetValid => clientRemoteDetValid, + ipWrEn => ipWrEn, + ipWrAddr => ipWrAddr, + macWrEn => macWrEn, + macWrAddr => macWrAddr); + +end architecture rtl; diff --git a/ethernet/UdpEngine/wrappers/UdpEngineArpFlatWrapper.vhd b/ethernet/UdpEngine/wrappers/UdpEngineArpFlatWrapper.vhd new file mode 100644 index 0000000000..cd13e26093 --- /dev/null +++ b/ethernet/UdpEngine/wrappers/UdpEngineArpFlatWrapper.vhd @@ -0,0 +1,131 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for UdpEngineArp +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity UdpEngineArpFlatWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + CLK_FREQ_G : real := 4.0; + COMM_TIMEOUT_G : positive := 2; + RESP_TIMEOUT_G : positive := 2); + port ( + clk : in sl; + rst : in sl; + localIp : in slv(31 downto 0); + arpTabFound : in sl; + arpTabMacAddr : in slv(47 downto 0); + arpTabIpWe : out sl; + arpTabMacWe : out sl; + arpTabMacAddrW : out slv(47 downto 0); + clientRemoteDetValid : in sl; + clientRemoteDetIp : in slv(31 downto 0); + clientRemoteIp : in slv(31 downto 0); + clientRemoteMac : out slv(47 downto 0); + arpReqTValid : out sl; + arpReqTData : out slv(127 downto 0); + arpReqTKeep : out slv(15 downto 0); + arpReqTLast : out sl; + arpReqTReady : in sl := '1'; + arpReqSof : out sl; + arpReqEofe : out sl; + arpAckTValid : in sl; + arpAckTData : in slv(127 downto 0); + arpAckTKeep : in slv(15 downto 0); + arpAckTLast : in sl; + arpAckTReady : out sl; + arpAckSof : in sl; + arpAckEofe : in sl); +end entity UdpEngineArpFlatWrapper; + +architecture rtl of UdpEngineArpFlatWrapper is + + signal arpReqMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal arpReqSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal arpAckMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal arpAckSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal arpTabMacAddrWArray : Slv48Array(0 downto 0); + signal clientRemoteDetIpArray : Slv32Array(0 downto 0); + signal clientRemoteIpArray : Slv32Array(0 downto 0); + signal clientRemoteMacArray : Slv48Array(0 downto 0); + +begin + + arpAckComb : process (arpAckEofe, arpAckSof, arpAckTData, arpAckTKeep, arpAckTLast, arpAckTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := arpAckTValid; + v.tData(127 downto 0) := arpAckTData; + v.tKeep(15 downto 0) := arpAckTKeep; + v.tLast := arpAckTLast; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, arpAckSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, arpAckEofe); + arpAckMasters(0) <= v; + end process arpAckComb; + + arpReqView : process (arpReqMasters(0)) is + begin + arpReqTValid <= arpReqMasters(0).tValid; + arpReqTData <= arpReqMasters(0).tData(127 downto 0); + arpReqTKeep <= arpReqMasters(0).tKeep(15 downto 0); + arpReqTLast <= arpReqMasters(0).tLast; + arpReqSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, arpReqMasters(0), EMAC_SOF_BIT_C, 0); + arpReqEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, arpReqMasters(0), EMAC_EOFE_BIT_C); + end process arpReqView; + + arpReqSlaves(0).tReady <= arpReqTReady; + arpAckTReady <= arpAckSlaves(0).tReady; + + clientRemoteDetIpArray(0) <= clientRemoteDetIp; + clientRemoteIpArray(0) <= clientRemoteIp; + clientRemoteMac <= clientRemoteMacArray(0); + arpTabMacAddrW <= arpTabMacAddrWArray(0); + + U_DUT : entity surf.UdpEngineArp + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + CLIENT_SIZE_G => 1, + CLK_FREQ_G => CLK_FREQ_G, + COMM_TIMEOUT_G => COMM_TIMEOUT_G, + RESP_TIMEOUT_G => RESP_TIMEOUT_G) + port map ( + localIp => localIp, + arpReqMasters => arpReqMasters, + arpReqSlaves => arpReqSlaves, + arpAckMasters => arpAckMasters, + arpAckSlaves => arpAckSlaves, + arpTabFound(0) => arpTabFound, + arpTabMacAddr(0) => arpTabMacAddr, + arpTabIpWe(0) => arpTabIpWe, + arpTabMacWe(0) => arpTabMacWe, + arpTabMacAddrW => arpTabMacAddrWArray, + clientRemoteDetValid(0) => clientRemoteDetValid, + clientRemoteDetIp => clientRemoteDetIpArray, + clientRemoteIp => clientRemoteIpArray, + clientRemoteMac => clientRemoteMacArray, + clk => clk, + rst => rst); + +end architecture rtl; diff --git a/ethernet/UdpEngine/wrappers/UdpEngineDhcpFlatWrapper.vhd b/ethernet/UdpEngine/wrappers/UdpEngineDhcpFlatWrapper.vhd new file mode 100644 index 0000000000..de4ecb303e --- /dev/null +++ b/ethernet/UdpEngine/wrappers/UdpEngineDhcpFlatWrapper.vhd @@ -0,0 +1,107 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for UdpEngineDhcp +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity UdpEngineDhcpFlatWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + CLK_FREQ_G : real := 4.0; + COMM_TIMEOUT_G : positive := 3; + SYNTH_MODE_G : string := "inferred"); + port ( + clk : in sl; + rst : in sl; + localMac : in slv(47 downto 0); + localIp : in slv(31 downto 0); + dhcpIp : out slv(31 downto 0); + sDhcpTValid : in sl; + sDhcpTData : in slv(127 downto 0); + sDhcpTKeep : in slv(15 downto 0); + sDhcpTLast : in sl; + sDhcpTReady : out sl; + sDhcpSof : in sl; + sDhcpEofe : in sl; + mDhcpTValid : out sl; + mDhcpTData : out slv(127 downto 0); + mDhcpTKeep : out slv(15 downto 0); + mDhcpTLast : out sl; + mDhcpTReady : in sl := '1'; + mDhcpSof : out sl; + mDhcpEofe : out sl); +end entity UdpEngineDhcpFlatWrapper; + +architecture rtl of UdpEngineDhcpFlatWrapper is + + signal sDhcpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sDhcpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mDhcpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mDhcpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + sDhcpComb : process (sDhcpEofe, sDhcpSof, sDhcpTData, sDhcpTKeep, sDhcpTLast, sDhcpTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sDhcpTValid; + v.tData(127 downto 0) := sDhcpTData; + v.tKeep(15 downto 0) := sDhcpTKeep; + v.tLast := sDhcpTLast; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sDhcpSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sDhcpEofe); + sDhcpMaster <= v; + end process sDhcpComb; + + mDhcpView : process (mDhcpMaster) is + begin + mDhcpTValid <= mDhcpMaster.tValid; + mDhcpTData <= mDhcpMaster.tData(127 downto 0); + mDhcpTKeep <= mDhcpMaster.tKeep(15 downto 0); + mDhcpTLast <= mDhcpMaster.tLast; + mDhcpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mDhcpMaster, EMAC_SOF_BIT_C, 0); + mDhcpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mDhcpMaster, EMAC_EOFE_BIT_C); + end process mDhcpView; + + sDhcpTReady <= sDhcpSlave.tReady; + mDhcpSlave.tReady <= mDhcpTReady; + + U_DUT : entity surf.UdpEngineDhcp + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + CLK_FREQ_G => CLK_FREQ_G, + COMM_TIMEOUT_G => COMM_TIMEOUT_G, + SYNTH_MODE_G => SYNTH_MODE_G) + port map ( + localMac => localMac, + localIp => localIp, + dhcpIp => dhcpIp, + ibDhcpMaster => sDhcpMaster, + ibDhcpSlave => sDhcpSlave, + obDhcpMaster => mDhcpMaster, + obDhcpSlave => mDhcpSlave, + clk => clk, + rst => rst); + +end architecture rtl; diff --git a/ethernet/UdpEngine/wrappers/UdpEngineRxFlatWrapper.vhd b/ethernet/UdpEngine/wrappers/UdpEngineRxFlatWrapper.vhd new file mode 100644 index 0000000000..ac5369e5f1 --- /dev/null +++ b/ethernet/UdpEngine/wrappers/UdpEngineRxFlatWrapper.vhd @@ -0,0 +1,181 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for UdpEngineRx +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity UdpEngineRxFlatWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false); + port ( + clk : in sl; + rst : in sl; + localIp : in slv(31 downto 0); + broadcastIp : in slv(31 downto 0); + igmpIp : in slv(31 downto 0); + serverRemotePort : out slv(15 downto 0); + serverRemoteIp : out slv(31 downto 0); + serverRemoteMac : out slv(47 downto 0); + clientRemoteDetValid : out sl; + clientRemoteDetIp : out slv(31 downto 0); + sUdpTValid : in sl; + sUdpTData : in slv(127 downto 0); + sUdpTKeep : in slv(15 downto 0); + sUdpTLast : in sl; + sUdpTReady : out sl; + sUdpSof : in sl; + sUdpEofe : in sl; + mServerTValid : out sl; + mServerTData : out slv(127 downto 0); + mServerTKeep : out slv(15 downto 0); + mServerTLast : out sl; + mServerTReady : in sl := '1'; + mServerTDest : out slv(7 downto 0); + mServerSof : out sl; + mServerEofe : out sl; + mClientTValid : out sl; + mClientTData : out slv(127 downto 0); + mClientTKeep : out slv(15 downto 0); + mClientTLast : out sl; + mClientTReady : in sl := '1'; + mClientTDest : out slv(7 downto 0); + mClientSof : out sl; + mClientEofe : out sl; + mDhcpTValid : out sl; + mDhcpTData : out slv(127 downto 0); + mDhcpTKeep : out slv(15 downto 0); + mDhcpTLast : out sl; + mDhcpTReady : in sl := '1'; + mDhcpSof : out sl; + mDhcpEofe : out sl); +end entity UdpEngineRxFlatWrapper; + +architecture rtl of UdpEngineRxFlatWrapper is + + signal igmpIpArray : Slv32Array(0 downto 0); + signal sUdpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sUdpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal serverRemotePortA : Slv16Array(0 downto 0); + signal serverRemoteIpA : Slv32Array(0 downto 0); + signal serverRemoteMacA : Slv48Array(0 downto 0); + signal clientRemoteDetVA : slv(0 downto 0); + signal clientRemoteDetIA : Slv32Array(0 downto 0); + signal mServerMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal mServerSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal mClientMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal mClientSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal mDhcpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mDhcpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + sUdpComb : process (sUdpEofe, sUdpSof, sUdpTData, sUdpTKeep, sUdpTLast, sUdpTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sUdpTValid; + v.tData(127 downto 0) := sUdpTData; + v.tKeep(15 downto 0) := sUdpTKeep; + v.tLast := sUdpTLast; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sUdpSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sUdpEofe); + sUdpMaster <= v; + end process sUdpComb; + + mServerView : process (mServerMasters(0)) is + begin + mServerTValid <= mServerMasters(0).tValid; + mServerTData <= mServerMasters(0).tData(127 downto 0); + mServerTKeep <= mServerMasters(0).tKeep(15 downto 0); + mServerTLast <= mServerMasters(0).tLast; + mServerTDest <= mServerMasters(0).tDest(7 downto 0); + mServerSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_SOF_BIT_C, 0); + mServerEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_EOFE_BIT_C); + end process mServerView; + + mClientView : process (mClientMasters(0)) is + begin + mClientTValid <= mClientMasters(0).tValid; + mClientTData <= mClientMasters(0).tData(127 downto 0); + mClientTKeep <= mClientMasters(0).tKeep(15 downto 0); + mClientTLast <= mClientMasters(0).tLast; + mClientTDest <= mClientMasters(0).tDest(7 downto 0); + mClientSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mClientMasters(0), EMAC_SOF_BIT_C, 0); + mClientEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mClientMasters(0), EMAC_EOFE_BIT_C); + end process mClientView; + + mDhcpView : process (mDhcpMaster) is + begin + mDhcpTValid <= mDhcpMaster.tValid; + mDhcpTData <= mDhcpMaster.tData(127 downto 0); + mDhcpTKeep <= mDhcpMaster.tKeep(15 downto 0); + mDhcpTLast <= mDhcpMaster.tLast; + mDhcpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mDhcpMaster, EMAC_SOF_BIT_C, 0); + mDhcpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mDhcpMaster, EMAC_EOFE_BIT_C); + end process mDhcpView; + + sUdpTReady <= sUdpSlave.tReady; + mServerSlaves(0).tReady <= mServerTReady; + mClientSlaves(0).tReady <= mClientTReady; + mDhcpSlave.tReady <= mDhcpTReady; + + igmpIpArray(0) <= igmpIp; + serverRemotePort <= serverRemotePortA(0); + serverRemoteIp <= serverRemoteIpA(0); + serverRemoteMac <= serverRemoteMacA(0); + clientRemoteDetValid <= clientRemoteDetVA(0); + clientRemoteDetIp <= clientRemoteDetIA(0); + + U_DUT : entity surf.UdpEngineRx + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + DHCP_G => true, + IGMP_G => false, + IGMP_GRP_SIZE => 1, + SERVER_EN_G => true, + SERVER_SIZE_G => 1, + SERVER_PORTS_G => (0 => 8192), + CLIENT_EN_G => true, + CLIENT_SIZE_G => 1, + CLIENT_PORTS_G => (0 => 8193)) + port map ( + localIp => localIp, + broadcastIp => broadcastIp, + igmpIp => igmpIpArray, + ibUdpMaster => sUdpMaster, + ibUdpSlave => sUdpSlave, + serverRemotePort => serverRemotePortA, + serverRemoteIp => serverRemoteIpA, + serverRemoteMac => serverRemoteMacA, + obServerMasters => mServerMasters, + obServerSlaves => mServerSlaves, + clientRemoteDetValid => clientRemoteDetVA, + clientRemoteDetIp => clientRemoteDetIA, + obClientMasters => mClientMasters, + obClientSlaves => mClientSlaves, + ibDhcpMaster => mDhcpMaster, + ibDhcpSlave => mDhcpSlave, + clk => clk, + rst => rst); + +end architecture rtl; diff --git a/ethernet/UdpEngine/wrappers/UdpEngineTopFlatWrapper.vhd b/ethernet/UdpEngine/wrappers/UdpEngineTopFlatWrapper.vhd new file mode 100644 index 0000000000..7e153392c7 --- /dev/null +++ b/ethernet/UdpEngine/wrappers/UdpEngineTopFlatWrapper.vhd @@ -0,0 +1,280 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for UdpEngine +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity UdpEngineTopFlatWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + CLK_FREQ_G : real := 4.0; + COMM_TIMEOUT_G : positive := 6); + port ( + clk : in sl; + rst : in sl; + localMac : in slv(47 downto 0); + localIp : in slv(31 downto 0); + broadcastIp : in slv(31 downto 0); + clientRemotePort : in slv(15 downto 0); + clientRemoteIp : in slv(31 downto 0); + dhcpIpOut : out slv(31 downto 0); + sUdpTValid : in sl; + sUdpTData : in slv(127 downto 0); + sUdpTKeep : in slv(15 downto 0); + sUdpTLast : in sl; + sUdpTReady : out sl; + sUdpSof : in sl; + sUdpEofe : in sl; + mUdpTValid : out sl; + mUdpTData : out slv(127 downto 0); + mUdpTKeep : out slv(15 downto 0); + mUdpTLast : out sl; + mUdpTReady : in sl := '1'; + mUdpSof : out sl; + mUdpEofe : out sl; + arpReqTValid : out sl; + arpReqTData : out slv(127 downto 0); + arpReqTKeep : out slv(15 downto 0); + arpReqTLast : out sl; + arpReqTReady : in sl := '1'; + arpReqSof : out sl; + arpReqEofe : out sl; + arpAckTValid : in sl; + arpAckTData : in slv(127 downto 0); + arpAckTKeep : in slv(15 downto 0); + arpAckTLast : in sl; + arpAckTReady : out sl; + arpAckSof : in sl; + arpAckEofe : in sl; + sServerTValid : in sl; + sServerTData : in slv(127 downto 0); + sServerTKeep : in slv(15 downto 0); + sServerTLast : in sl; + sServerTReady : out sl; + sServerTDest : in slv(7 downto 0); + sServerSof : in sl; + sServerEofe : in sl; + mServerTValid : out sl; + mServerTData : out slv(127 downto 0); + mServerTKeep : out slv(15 downto 0); + mServerTLast : out sl; + mServerTReady : in sl := '1'; + mServerTDest : out slv(7 downto 0); + mServerSof : out sl; + mServerEofe : out sl; + sClientTValid : in sl; + sClientTData : in slv(127 downto 0); + sClientTKeep : in slv(15 downto 0); + sClientTLast : in sl; + sClientTReady : out sl; + sClientTDest : in slv(7 downto 0); + sClientSof : in sl; + sClientEofe : in sl; + mClientTValid : out sl; + mClientTData : out slv(127 downto 0); + mClientTKeep : out slv(15 downto 0); + mClientTLast : out sl; + mClientTReady : in sl := '1'; + mClientTDest : out slv(7 downto 0); + mClientSof : out sl; + mClientEofe : out sl); +end entity UdpEngineTopFlatWrapper; + +architecture rtl of UdpEngineTopFlatWrapper is + + signal igmpIp : Slv32Array(0 downto 0) := (others => (others => '0')); + signal clientRemotePortA : Slv16Array(0 downto 0); + signal clientRemoteIpA : Slv32Array(0 downto 0); + signal sUdpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sUdpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mUdpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mUdpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal arpReqMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal arpReqSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal arpAckMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal arpAckSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal sServerMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal sServerSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal mServerMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal mServerSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal sClientMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal sClientSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal mClientMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal mClientSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + +begin + + clientRemotePortA(0) <= clientRemotePort; + clientRemoteIpA(0) <= clientRemoteIp; + + sUdpComb : process (sUdpEofe, sUdpSof, sUdpTData, sUdpTKeep, sUdpTLast, sUdpTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sUdpTValid; + v.tData(127 downto 0) := sUdpTData; + v.tKeep(15 downto 0) := sUdpTKeep; + v.tLast := sUdpTLast; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sUdpSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sUdpEofe); + sUdpMaster <= v; + end process sUdpComb; + + sServerComb : process (sServerEofe, sServerSof, sServerTData, sServerTDest, sServerTKeep, sServerTLast, sServerTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sServerTValid; + v.tData(127 downto 0) := sServerTData; + v.tKeep(15 downto 0) := sServerTKeep; + v.tLast := sServerTLast; + v.tDest(7 downto 0) := sServerTDest; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sServerSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sServerEofe); + sServerMasters(0) <= v; + end process sServerComb; + + sClientComb : process (sClientEofe, sClientSof, sClientTData, sClientTDest, sClientTKeep, sClientTLast, sClientTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sClientTValid; + v.tData(127 downto 0) := sClientTData; + v.tKeep(15 downto 0) := sClientTKeep; + v.tLast := sClientTLast; + v.tDest(7 downto 0) := sClientTDest; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sClientSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sClientEofe); + sClientMasters(0) <= v; + end process sClientComb; + + arpAckComb : process (arpAckEofe, arpAckSof, arpAckTData, arpAckTKeep, arpAckTLast, arpAckTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := arpAckTValid; + v.tData(127 downto 0) := arpAckTData; + v.tKeep(15 downto 0) := arpAckTKeep; + v.tLast := arpAckTLast; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, arpAckSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, arpAckEofe); + arpAckMasters(0) <= v; + end process arpAckComb; + + mUdpView : process (mUdpMaster) is + begin + mUdpTValid <= mUdpMaster.tValid; + mUdpTData <= mUdpMaster.tData(127 downto 0); + mUdpTKeep <= mUdpMaster.tKeep(15 downto 0); + mUdpTLast <= mUdpMaster.tLast; + mUdpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mUdpMaster, EMAC_SOF_BIT_C, 0); + mUdpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mUdpMaster, EMAC_EOFE_BIT_C); + end process mUdpView; + + arpReqView : process (arpReqMasters(0)) is + begin + arpReqTValid <= arpReqMasters(0).tValid; + arpReqTData <= arpReqMasters(0).tData(127 downto 0); + arpReqTKeep <= arpReqMasters(0).tKeep(15 downto 0); + arpReqTLast <= arpReqMasters(0).tLast; + arpReqSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, arpReqMasters(0), EMAC_SOF_BIT_C, 0); + arpReqEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, arpReqMasters(0), EMAC_EOFE_BIT_C); + end process arpReqView; + + mServerView : process (mServerMasters(0)) is + begin + mServerTValid <= mServerMasters(0).tValid; + mServerTData <= mServerMasters(0).tData(127 downto 0); + mServerTKeep <= mServerMasters(0).tKeep(15 downto 0); + mServerTLast <= mServerMasters(0).tLast; + mServerTDest <= mServerMasters(0).tDest(7 downto 0); + mServerSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_SOF_BIT_C, 0); + mServerEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_EOFE_BIT_C); + end process mServerView; + + mClientView : process (mClientMasters(0)) is + begin + mClientTValid <= mClientMasters(0).tValid; + mClientTData <= mClientMasters(0).tData(127 downto 0); + mClientTKeep <= mClientMasters(0).tKeep(15 downto 0); + mClientTLast <= mClientMasters(0).tLast; + mClientTDest <= mClientMasters(0).tDest(7 downto 0); + mClientSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mClientMasters(0), EMAC_SOF_BIT_C, 0); + mClientEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mClientMasters(0), EMAC_EOFE_BIT_C); + end process mClientView; + + sUdpTReady <= sUdpSlave.tReady; + mUdpSlave.tReady <= mUdpTReady; + arpReqSlaves(0).tReady <= arpReqTReady; + arpAckTReady <= arpAckSlaves(0).tReady; + sServerTReady <= sServerSlaves(0).tReady; + mServerSlaves(0).tReady <= mServerTReady; + sClientTReady <= sClientSlaves(0).tReady; + mClientSlaves(0).tReady <= mClientTReady; + + U_DUT : entity surf.UdpEngine + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + SERVER_EN_G => true, + SERVER_SIZE_G => 1, + SERVER_PORTS_G => (0 => 8192), + CLIENT_EN_G => true, + CLIENT_SIZE_G => 1, + CLIENT_PORTS_G => (0 => 8193), + ARP_TAB_ENTRIES_G => 4, + TX_FLOW_CTRL_G => true, + DHCP_G => false, + IGMP_G => false, + IGMP_GRP_SIZE => 1, + CLK_FREQ_G => CLK_FREQ_G, + COMM_TIMEOUT_G => COMM_TIMEOUT_G) + port map ( + localMac => localMac, + broadcastIp => broadcastIp, + igmpIp => igmpIp, + localIpIn => localIp, + dhcpIpOut => dhcpIpOut, + obUdpMaster => mUdpMaster, + obUdpSlave => mUdpSlave, + ibUdpMaster => sUdpMaster, + ibUdpSlave => sUdpSlave, + arpReqMasters => arpReqMasters, + arpReqSlaves => arpReqSlaves, + arpAckMasters => arpAckMasters, + arpAckSlaves => arpAckSlaves, + serverRemotePort => open, + serverRemoteIp => open, + obServerMasters => mServerMasters, + obServerSlaves => mServerSlaves, + ibServerMasters => sServerMasters, + ibServerSlaves => sServerSlaves, + clientRemotePort => clientRemotePortA, + clientRemoteIp => clientRemoteIpA, + obClientMasters => mClientMasters, + obClientSlaves => mClientSlaves, + ibClientMasters => sClientMasters, + ibClientSlaves => sClientSlaves, + clk => clk, + rst => rst); + +end architecture rtl; diff --git a/ethernet/UdpEngine/wrappers/UdpEngineTxFlatWrapper.vhd b/ethernet/UdpEngine/wrappers/UdpEngineTxFlatWrapper.vhd new file mode 100644 index 0000000000..1af3526797 --- /dev/null +++ b/ethernet/UdpEngine/wrappers/UdpEngineTxFlatWrapper.vhd @@ -0,0 +1,163 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for UdpEngineTx +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity UdpEngineTxFlatWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + IS_CLIENT_G : boolean := false; + PORT_G_VALUE : positive := 8192); + port ( + clk : in sl; + rst : in sl; + localMac : in slv(47 downto 0); + localIp : in slv(31 downto 0); + remotePort : in slv(15 downto 0); + remoteIp : in slv(31 downto 0); + remoteMac : in slv(47 downto 0); + linkUp : out sl; + arpTabPos : out slv(7 downto 0); + arpTabFound : in sl; + arpTabIpAddr : in slv(31 downto 0); + arpTabMacAddr : in slv(47 downto 0); + sAppTValid : in sl; + sAppTData : in slv(127 downto 0); + sAppTKeep : in slv(15 downto 0); + sAppTLast : in sl; + sAppTReady : out sl; + sAppTDest : in slv(7 downto 0); + sAppSof : in sl; + sAppEofe : in sl; + sDhcpTValid : in sl; + sDhcpTData : in slv(127 downto 0); + sDhcpTKeep : in slv(15 downto 0); + sDhcpTLast : in sl; + sDhcpTReady : out sl; + sDhcpSof : in sl; + sDhcpEofe : in sl; + mUdpTValid : out sl; + mUdpTData : out slv(127 downto 0); + mUdpTKeep : out slv(15 downto 0); + mUdpTLast : out sl; + mUdpTReady : in sl := '1'; + mUdpSof : out sl; + mUdpEofe : out sl); +end entity UdpEngineTxFlatWrapper; + +architecture rtl of UdpEngineTxFlatWrapper is + + signal sAppMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal sAppSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal arpTabPosA : Slv8Array(0 downto 0); + signal remotePortA : Slv16Array(0 downto 0); + signal remoteIpA : Slv32Array(0 downto 0); + signal remoteMacA : Slv48Array(0 downto 0); + signal arpTabIpAddrA : Slv32Array(0 downto 0); + signal arpTabMacA : Slv48Array(0 downto 0); + signal linkUpA : slv(0 downto 0); + signal sDhcpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sDhcpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mUdpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mUdpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + sAppComb : process (sAppEofe, sAppSof, sAppTData, sAppTDest, sAppTKeep, sAppTLast, sAppTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAppTValid; + v.tData(127 downto 0) := sAppTData; + v.tKeep(15 downto 0) := sAppTKeep; + v.tLast := sAppTLast; + v.tDest(7 downto 0) := sAppTDest; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAppSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAppEofe); + sAppMasters(0) <= v; + end process sAppComb; + + sDhcpComb : process (sDhcpEofe, sDhcpSof, sDhcpTData, sDhcpTKeep, sDhcpTLast, sDhcpTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sDhcpTValid; + v.tData(127 downto 0) := sDhcpTData; + v.tKeep(15 downto 0) := sDhcpTKeep; + v.tLast := sDhcpTLast; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sDhcpSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sDhcpEofe); + sDhcpMaster <= v; + end process sDhcpComb; + + mUdpView : process (mUdpMaster) is + begin + mUdpTValid <= mUdpMaster.tValid; + mUdpTData <= mUdpMaster.tData(127 downto 0); + mUdpTKeep <= mUdpMaster.tKeep(15 downto 0); + mUdpTLast <= mUdpMaster.tLast; + mUdpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mUdpMaster, EMAC_SOF_BIT_C, 0); + mUdpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mUdpMaster, EMAC_EOFE_BIT_C); + end process mUdpView; + + sAppTReady <= sAppSlaves(0).tReady; + sDhcpTReady <= sDhcpSlave.tReady; + mUdpSlave.tReady <= mUdpTReady; + + linkUp <= linkUpA(0); + arpTabPos <= arpTabPosA(0); + remotePortA(0) <= remotePort; + remoteIpA(0) <= remoteIp; + remoteMacA(0) <= remoteMac; + arpTabIpAddrA(0) <= arpTabIpAddr; + arpTabMacA(0) <= arpTabMacAddr; + + U_DUT : entity surf.UdpEngineTx + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + SIZE_G => 1, + TX_FLOW_CTRL_G => true, + IS_CLIENT_G => IS_CLIENT_G, + PORT_G => (0 => PORT_G_VALUE)) + port map ( + obUdpMaster => mUdpMaster, + obUdpSlave => mUdpSlave, + linkUp => linkUpA, + localMac => localMac, + localIp => localIp, + remotePort => remotePortA, + remoteIp => remoteIpA, + remoteMac => remoteMacA, + ibMasters => sAppMasters, + ibSlaves => sAppSlaves, + arpTabPos => arpTabPosA, + arpTabFound(0) => arpTabFound, + arpTabIpAddr => arpTabIpAddrA, + arpTabMacAddr => arpTabMacA, + obDhcpMaster => sDhcpMaster, + obDhcpSlave => sDhcpSlave, + clk => clk, + rst => rst); + +end architecture rtl; diff --git a/ethernet/UdpEngine/wrappers/UdpEngineWrapperFlatWrapper.vhd b/ethernet/UdpEngine/wrappers/UdpEngineWrapperFlatWrapper.vhd new file mode 100644 index 0000000000..2a3126d03b --- /dev/null +++ b/ethernet/UdpEngine/wrappers/UdpEngineWrapperFlatWrapper.vhd @@ -0,0 +1,269 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for UdpEngineWrapper +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity UdpEngineWrapperFlatWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + CLK_FREQ_G : real := 4.0; + COMM_TIMEOUT_G : positive := 6); + port ( + clk : in sl; + rst : in sl; + localMac : in slv(47 downto 0); + localIp : in slv(31 downto 0); + softMac : out slv(47 downto 0); + softIp : out slv(31 downto 0); + sMacTValid : in sl; + sMacTData : in slv(127 downto 0); + sMacTKeep : in slv(15 downto 0); + sMacTLast : in sl; + sMacTReady : out sl; + sMacSof : in sl; + sMacEofe : in sl; + mMacTValid : out sl; + mMacTData : out slv(127 downto 0); + mMacTKeep : out slv(15 downto 0); + mMacTLast : out sl; + mMacTReady : in sl := '1'; + mMacSof : out sl; + mMacEofe : out sl; + sServerTValid : in sl; + sServerTData : in slv(127 downto 0); + sServerTKeep : in slv(15 downto 0); + sServerTLast : in sl; + sServerTReady : out sl; + sServerTDest : in slv(7 downto 0); + sServerSof : in sl; + sServerEofe : in sl; + mServerTValid : out sl; + mServerTData : out slv(127 downto 0); + mServerTKeep : out slv(15 downto 0); + mServerTLast : out sl; + mServerTReady : in sl := '1'; + mServerTDest : out slv(7 downto 0); + mServerSof : out sl; + mServerEofe : out sl; + sClientTValid : in sl; + sClientTData : in slv(127 downto 0); + sClientTKeep : in slv(15 downto 0); + sClientTLast : in sl; + sClientTReady : out sl; + sClientTDest : in slv(7 downto 0); + sClientSof : in sl; + sClientEofe : in sl; + mClientTValid : out sl; + mClientTData : out slv(127 downto 0); + mClientTKeep : out slv(15 downto 0); + mClientTLast : out sl; + mClientTReady : in sl := '1'; + mClientTDest : out slv(7 downto 0); + mClientSof : out sl; + mClientEofe : out sl; + S_AXI_AWADDR : in slv(31 downto 0); + S_AXI_AWPROT : in slv(2 downto 0); + S_AXI_AWVALID : in sl; + S_AXI_AWREADY : out sl; + S_AXI_WDATA : in slv(31 downto 0); + S_AXI_WSTRB : in slv(3 downto 0); + S_AXI_WVALID : in sl; + S_AXI_WREADY : out sl; + S_AXI_BRESP : out slv(1 downto 0); + S_AXI_BVALID : out sl; + S_AXI_BREADY : in sl; + S_AXI_ARADDR : in slv(31 downto 0); + S_AXI_ARPROT : in slv(2 downto 0); + S_AXI_ARVALID : in sl; + S_AXI_ARREADY : out sl; + S_AXI_RDATA : out slv(31 downto 0); + S_AXI_RRESP : out slv(1 downto 0); + S_AXI_RVALID : out sl; + S_AXI_RREADY : in sl); +end entity UdpEngineWrapperFlatWrapper; + +architecture rtl of UdpEngineWrapperFlatWrapper is + + signal sMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal sServerMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal sServerSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal mServerMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal mServerSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal sClientMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal sClientSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal mClientMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal mClientSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + +begin + + sMacComb : process (sMacEofe, sMacSof, sMacTData, sMacTKeep, sMacTLast, sMacTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sMacTValid; + v.tData(127 downto 0) := sMacTData; + v.tKeep(15 downto 0) := sMacTKeep; + v.tLast := sMacTLast; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sMacSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sMacEofe); + sMacMaster <= v; + end process sMacComb; + + sServerComb : process (sServerEofe, sServerSof, sServerTData, sServerTDest, sServerTKeep, sServerTLast, sServerTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sServerTValid; + v.tData(127 downto 0) := sServerTData; + v.tKeep(15 downto 0) := sServerTKeep; + v.tLast := sServerTLast; + v.tDest(7 downto 0) := sServerTDest; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sServerSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sServerEofe); + sServerMasters(0) <= v; + end process sServerComb; + + sClientComb : process (sClientEofe, sClientSof, sClientTData, sClientTDest, sClientTKeep, sClientTLast, sClientTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sClientTValid; + v.tData(127 downto 0) := sClientTData; + v.tKeep(15 downto 0) := sClientTKeep; + v.tLast := sClientTLast; + v.tDest(7 downto 0) := sClientTDest; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sClientSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sClientEofe); + sClientMasters(0) <= v; + end process sClientComb; + + mMacView : process (mMacMaster) is + begin + mMacTValid <= mMacMaster.tValid; + mMacTData <= mMacMaster.tData(127 downto 0); + mMacTKeep <= mMacMaster.tKeep(15 downto 0); + mMacTLast <= mMacMaster.tLast; + mMacSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mMacMaster, EMAC_SOF_BIT_C, 0); + mMacEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mMacMaster, EMAC_EOFE_BIT_C); + end process mMacView; + + mServerView : process (mServerMasters(0)) is + begin + mServerTValid <= mServerMasters(0).tValid; + mServerTData <= mServerMasters(0).tData(127 downto 0); + mServerTKeep <= mServerMasters(0).tKeep(15 downto 0); + mServerTLast <= mServerMasters(0).tLast; + mServerTDest <= mServerMasters(0).tDest(7 downto 0); + mServerSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_SOF_BIT_C, 0); + mServerEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_EOFE_BIT_C); + end process mServerView; + + mClientView : process (mClientMasters(0)) is + begin + mClientTValid <= mClientMasters(0).tValid; + mClientTData <= mClientMasters(0).tData(127 downto 0); + mClientTKeep <= mClientMasters(0).tKeep(15 downto 0); + mClientTLast <= mClientMasters(0).tLast; + mClientTDest <= mClientMasters(0).tDest(7 downto 0); + mClientSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mClientMasters(0), EMAC_SOF_BIT_C, 0); + mClientEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mClientMasters(0), EMAC_EOFE_BIT_C); + end process mClientView; + + axilWriteMaster.awaddr <= S_AXI_AWADDR; + axilWriteMaster.awprot <= S_AXI_AWPROT; + axilWriteMaster.awvalid <= S_AXI_AWVALID; + axilWriteMaster.wdata <= S_AXI_WDATA; + axilWriteMaster.wstrb <= S_AXI_WSTRB; + axilWriteMaster.wvalid <= S_AXI_WVALID; + axilWriteMaster.bready <= S_AXI_BREADY; + axilReadMaster.araddr <= S_AXI_ARADDR; + axilReadMaster.arprot <= S_AXI_ARPROT; + axilReadMaster.arvalid <= S_AXI_ARVALID; + axilReadMaster.rready <= S_AXI_RREADY; + + S_AXI_AWREADY <= axilWriteSlave.awready; + S_AXI_WREADY <= axilWriteSlave.wready; + S_AXI_BRESP <= axilWriteSlave.bresp; + S_AXI_BVALID <= axilWriteSlave.bvalid; + S_AXI_ARREADY <= axilReadSlave.arready; + S_AXI_RDATA <= axilReadSlave.rdata; + S_AXI_RRESP <= axilReadSlave.rresp; + S_AXI_RVALID <= axilReadSlave.rvalid; + + sMacTReady <= sMacSlave.tReady; + mMacSlave.tReady <= mMacTReady; + sServerTReady <= sServerSlaves(0).tReady; + mServerSlaves(0).tReady <= mServerTReady; + sClientTReady <= sClientSlaves(0).tReady; + mClientSlaves(0).tReady <= mClientTReady; + + U_DUT : entity surf.UdpEngineWrapper + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + SERVER_EN_G => true, + SERVER_SIZE_G => 1, + SERVER_PORTS_G => (0 => 8192), + CLIENT_EN_G => true, + CLIENT_SIZE_G => 1, + CLIENT_PORTS_G => (0 => 8193), + CLIENT_EXT_CONFIG_G => false, + TX_FLOW_CTRL_G => true, + DHCP_G => false, + IGMP_G => false, + IGMP_GRP_SIZE => 1, + CLK_FREQ_G => CLK_FREQ_G, + COMM_TIMEOUT_G => COMM_TIMEOUT_G) + port map ( + localMac => localMac, + localIp => localIp, + softMac => softMac, + softIp => softIp, + obMacMaster => sMacMaster, + obMacSlave => sMacSlave, + ibMacMaster => mMacMaster, + ibMacSlave => mMacSlave, + obServerMasters => mServerMasters, + obServerSlaves => mServerSlaves, + ibServerMasters => sServerMasters, + ibServerSlaves => sServerSlaves, + obClientMasters => mClientMasters, + obClientSlaves => mClientSlaves, + ibClientMasters => sClientMasters, + ibClientSlaves => sClientSlaves, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave, + clk => clk, + rst => rst); + +end architecture rtl; diff --git a/ethernet/UdpEngine/wrappers/UdpEngineWrapperPairFlatWrapper.vhd b/ethernet/UdpEngine/wrappers/UdpEngineWrapperPairFlatWrapper.vhd new file mode 100644 index 0000000000..1c638d2bca --- /dev/null +++ b/ethernet/UdpEngine/wrappers/UdpEngineWrapperPairFlatWrapper.vhd @@ -0,0 +1,299 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Legacy-parity cocotb wrapper for a client/server UdpEngine set +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity UdpEngineWrapperPairFlatWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + CLK_FREQ_G : real := 4.0; + COMM_TIMEOUT_G : positive := 6); + port ( + clk : in sl; + rst : in sl; + clientLocalMac : in slv(47 downto 0); + clientLocalIp : in slv(31 downto 0); + clientRemotePort : in slv(15 downto 0); + clientRemoteIp : in slv(31 downto 0); + selectedServer : in slv(1 downto 0); + sClientTValid : in sl; + sClientTData : in slv(127 downto 0); + sClientTKeep : in slv(15 downto 0); + sClientTLast : in sl; + sClientTReady : out sl; + sClientTDest : in slv(7 downto 0); + sClientSof : in sl; + sClientEofe : in sl; + mServer0TValid : out sl; + mServer0TData : out slv(127 downto 0); + mServer0TKeep : out slv(15 downto 0); + mServer0TLast : out sl; + mServer0TReady : in sl := '1'; + mServer0TDest : out slv(7 downto 0); + mServer0Sof : out sl; + mServer0Eofe : out sl; + mServer1TValid : out sl; + mServer1TData : out slv(127 downto 0); + mServer1TKeep : out slv(15 downto 0); + mServer1TLast : out sl; + mServer1TReady : in sl := '1'; + mServer1TDest : out slv(7 downto 0); + mServer1Sof : out sl; + mServer1Eofe : out sl; + mServer2TValid : out sl; + mServer2TData : out slv(127 downto 0); + mServer2TKeep : out slv(15 downto 0); + mServer2TLast : out sl; + mServer2TReady : in sl := '1'; + mServer2TDest : out slv(7 downto 0); + mServer2Sof : out sl; + mServer2Eofe : out sl); +end entity UdpEngineWrapperPairFlatWrapper; + +architecture rtl of UdpEngineWrapperPairFlatWrapper is + + constant SERVER_MACS_C : Slv48Array(2 downto 0) := ( + 0 => x"020300564400", + 1 => x"030300564400", + 2 => x"040300564400"); + constant SERVER_IPS_C : Slv32Array(2 downto 0) := ( + 0 => x"0B02A8C0", + 1 => x"0C02A8C0", + 2 => x"0D02A8C0"); + constant PHY_D_IDLE_C : slv(63 downto 0) := x"0707070707070707"; + constant PHY_C_IDLE_C : slv(7 downto 0) := x"FF"; + + signal obMacMasters : AxiStreamMasterArray(3 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal obMacSlaves : AxiStreamSlaveArray(3 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal ibMacMasters : AxiStreamMasterArray(3 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal ibMacSlaves : AxiStreamSlaveArray(3 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal sClientMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal sClientSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal mServerMasters : AxiStreamMasterArray(2 downto 0); + signal mServerSlaves : AxiStreamSlaveArray(2 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal ethConfig : EthMacConfigArray(3 downto 0) := (others => ETH_MAC_CONFIG_INIT_C); + signal phyD : Slv64Array(3 downto 0) := (others => (others => '0')); + signal phyC : Slv8Array(3 downto 0) := (others => (others => '0')); + signal phyDSelected : slv(63 downto 0) := PHY_D_IDLE_C; + signal phyCSelected : slv(7 downto 0) := PHY_C_IDLE_C; + signal phyReady : sl; + +begin + + sClientComb : process (sClientEofe, sClientSof, sClientTData, sClientTDest, sClientTKeep, sClientTLast, sClientTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sClientTValid; + v.tData(127 downto 0) := sClientTData; + v.tKeep(15 downto 0) := sClientTKeep; + v.tLast := sClientTLast; + v.tDest(7 downto 0) := sClientTDest; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sClientSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sClientEofe); + sClientMasters(0) <= v; + end process sClientComb; + + mServer0View : process (mServerMasters(0)) is + begin + mServer0TValid <= mServerMasters(0).tValid; + mServer0TData <= mServerMasters(0).tData(127 downto 0); + mServer0TKeep <= mServerMasters(0).tKeep(15 downto 0); + mServer0TLast <= mServerMasters(0).tLast; + mServer0TDest <= mServerMasters(0).tDest(7 downto 0); + mServer0Sof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_SOF_BIT_C, 0); + mServer0Eofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_EOFE_BIT_C); + end process mServer0View; + + mServer1View : process (mServerMasters(1)) is + begin + mServer1TValid <= mServerMasters(1).tValid; + mServer1TData <= mServerMasters(1).tData(127 downto 0); + mServer1TKeep <= mServerMasters(1).tKeep(15 downto 0); + mServer1TLast <= mServerMasters(1).tLast; + mServer1TDest <= mServerMasters(1).tDest(7 downto 0); + mServer1Sof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(1), EMAC_SOF_BIT_C, 0); + mServer1Eofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(1), EMAC_EOFE_BIT_C); + end process mServer1View; + + mServer2View : process (mServerMasters(2)) is + begin + mServer2TValid <= mServerMasters(2).tValid; + mServer2TData <= mServerMasters(2).tData(127 downto 0); + mServer2TKeep <= mServerMasters(2).tKeep(15 downto 0); + mServer2TLast <= mServerMasters(2).tLast; + mServer2TDest <= mServerMasters(2).tDest(7 downto 0); + mServer2Sof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(2), EMAC_SOF_BIT_C, 0); + mServer2Eofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(2), EMAC_EOFE_BIT_C); + end process mServer2View; + + sClientTReady <= sClientSlaves(0).tReady; + mServerSlaves(0).tReady <= mServer0TReady; + mServerSlaves(1).tReady <= mServer1TReady; + mServerSlaves(2).tReady <= mServer2TReady; + phyReady <= not rst; + + --------------------------------------------------------------------------- + -- Match the legacy XGMII PHY multiplexer from UdpEngineTb. + --------------------------------------------------------------------------- + process (phyC, phyD, selectedServer) is + variable index : natural range 0 to 3; + begin + phyDSelected <= PHY_D_IDLE_C; + phyCSelected <= PHY_C_IDLE_C; + index := to_integer(unsigned(selectedServer)); + if (index >= 1) and (index <= 3) then + phyDSelected <= phyD(index); + phyCSelected <= phyC(index); + end if; + end process; + ethConfig(0).macAddress <= clientLocalMac; + ethConfig(1).macAddress <= SERVER_MACS_C(0); + ethConfig(2).macAddress <= SERVER_MACS_C(1); + ethConfig(3).macAddress <= SERVER_MACS_C(2); + + U_Client : entity surf.UdpEngineWrapper + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + SERVER_EN_G => false, + CLIENT_EN_G => true, + CLIENT_SIZE_G => 1, + CLIENT_PORTS_G => (0 => 8193), + CLIENT_EXT_CONFIG_G => true, + TX_FLOW_CTRL_G => true, + DHCP_G => false, + IGMP_G => false, + IGMP_GRP_SIZE => 1, + CLK_FREQ_G => CLK_FREQ_G, + COMM_TIMEOUT_G => COMM_TIMEOUT_G) + port map ( + localMac => clientLocalMac, + localIp => clientLocalIp, + softMac => open, + softIp => open, + clientRemotePort(0) => clientRemotePort, + clientRemoteIp(0) => clientRemoteIp, + obMacMaster => obMacMasters(0), + obMacSlave => obMacSlaves(0), + ibMacMaster => ibMacMasters(0), + ibMacSlave => ibMacSlaves(0), + obServerMasters => open, + obServerSlaves => (others => AXI_STREAM_SLAVE_FORCE_C), + ibServerMasters => (others => AXI_STREAM_MASTER_INIT_C), + ibServerSlaves => open, + obClientMasters => open, + obClientSlaves => (others => AXI_STREAM_SLAVE_FORCE_C), + ibClientMasters => sClientMasters, + ibClientSlaves => sClientSlaves, + clk => clk, + rst => rst); + + U_ClientMac : entity surf.EthMacTop + generic map ( + TPD_G => TPD_G, + PHY_TYPE_G => "XGMII", + PRIM_CONFIG_G => EMAC_AXIS_CONFIG_C) + port map ( + primClk => clk, + primRst => rst, + ibMacPrimMaster => ibMacMasters(0), + ibMacPrimSlave => ibMacSlaves(0), + obMacPrimMaster => obMacMasters(0), + obMacPrimSlave => obMacSlaves(0), + ethClk => clk, + ethRst => rst, + ethConfig => ethConfig(0), + phyReady => phyReady, + xgmiiTxd => phyD(0), + xgmiiTxc => phyC(0), + xgmiiRxd => phyDSelected, + xgmiiRxc => phyCSelected); + + GEN_SERVERS : for i in 0 to 2 generate + signal obServerMasters : AxiStreamMasterArray(0 downto 0); + signal obServerSlaves : AxiStreamSlaveArray(0 downto 0); + begin + obServerSlaves(0) <= mServerSlaves(i); + mServerMasters(i) <= obServerMasters(0); + + U_Server : entity surf.UdpEngineWrapper + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + SERVER_EN_G => true, + SERVER_SIZE_G => 1, + SERVER_PORTS_G => (0 => 8192), + CLIENT_EN_G => false, + CLIENT_EXT_CONFIG_G => false, + TX_FLOW_CTRL_G => true, + DHCP_G => false, + IGMP_G => false, + IGMP_GRP_SIZE => 1, + CLK_FREQ_G => CLK_FREQ_G, + COMM_TIMEOUT_G => COMM_TIMEOUT_G) + port map ( + localMac => SERVER_MACS_C(i), + localIp => SERVER_IPS_C(i), + softMac => open, + softIp => open, + obMacMaster => obMacMasters(i+1), + obMacSlave => obMacSlaves(i+1), + ibMacMaster => ibMacMasters(i+1), + ibMacSlave => ibMacSlaves(i+1), + obServerMasters => obServerMasters, + obServerSlaves => obServerSlaves, + ibServerMasters => (others => AXI_STREAM_MASTER_INIT_C), + ibServerSlaves => open, + obClientMasters => open, + obClientSlaves => (others => AXI_STREAM_SLAVE_FORCE_C), + ibClientMasters => (others => AXI_STREAM_MASTER_INIT_C), + ibClientSlaves => open, + clk => clk, + rst => rst); + + U_ServerMac : entity surf.EthMacTop + generic map ( + TPD_G => TPD_G, + PHY_TYPE_G => "XGMII", + PRIM_CONFIG_G => EMAC_AXIS_CONFIG_C) + port map ( + primClk => clk, + primRst => rst, + ibMacPrimMaster => ibMacMasters(i+1), + ibMacPrimSlave => ibMacSlaves(i+1), + obMacPrimMaster => obMacMasters(i+1), + obMacPrimSlave => obMacSlaves(i+1), + ethClk => clk, + ethRst => rst, + ethConfig => ethConfig(i+1), + phyReady => phyReady, + xgmiiTxd => phyD(i+1), + xgmiiTxc => phyC(i+1), + xgmiiRxd => phyD(0), + xgmiiRxc => phyC(0)); + end generate GEN_SERVERS; + +end architecture rtl; diff --git a/tests/ethernet/UdpEngine/__init__.py b/tests/ethernet/UdpEngine/__init__.py new file mode 100644 index 0000000000..b0085f1a17 --- /dev/null +++ b/tests/ethernet/UdpEngine/__init__.py @@ -0,0 +1,9 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## diff --git a/tests/ethernet/UdpEngine/test_ArpIpTable.py b/tests/ethernet/UdpEngine/test_ArpIpTable.py new file mode 100644 index 0000000000..b2c24b3fe7 --- /dev/null +++ b/tests/ethernet/UdpEngine/test_ArpIpTable.py @@ -0,0 +1,127 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Exercise direct lookup, indexed lookup, and timeout-driven slot +# reclamation in the ARP IP/MAC table. +# - Stimulus: Write entries through the IP/MAC write ports, query them by IP +# and by explicit table position, then let one entry expire before writing a +# replacement mapping. +# - Checks: Lookups must return the stored MAC/IP pair while live, and an +# expired entry must disappear so a later write can replace it cleanly. +# - Timing: The wrapper uses a tiny clock-frequency generic so expiration is +# proven with real timer rollovers instead of long fixed simulation delays. + +from __future__ import annotations + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import cycle, setup_flat_emac_testbench +from tests.ethernet.UdpEngine.udp_test_utils import LEGACY_IP_CFGS, LEGACY_MAC_CFGS, UDP_RTL_SOURCES + + +WRAPPER_PATH = "ethernet/UdpEngine/wrappers/ArpIpTableFlatWrapper.vhd" + + +async def setup_arp_ip_table_bench(dut): + return await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + initial_values={ + "ipAddrIn": 0, + "pos": 0, + "clientRemoteDetIp": 0, + "clientRemoteDetValid": 0, + "ipWrEn": 0, + "ipWrAddr": 0, + "macWrEn": 0, + "macWrAddr": 0, + }, + ) + + +async def pulse(signal, *, clk) -> None: + signal.value = 1 + await cycle(clk, 1) + signal.value = 0 + await cycle(clk, 1) + + +@cocotb.test() +async def arp_ip_table_lookup_by_ip_and_position_test(dut): + bench = await setup_arp_ip_table_bench(dut) + + dut.ipWrAddr.value = LEGACY_IP_CFGS[1] + await pulse(dut.ipWrEn, clk=bench.clk) + dut.macWrAddr.value = LEGACY_MAC_CFGS[1] + await pulse(dut.macWrEn, clk=bench.clk) + + # `pos=0` uses IP-match lookup while `pos=1` directly addresses entry 0. + dut.ipAddrIn.value = LEGACY_IP_CFGS[1] + dut.pos.value = 0 + await cycle(bench.clk, 1) + assert int(dut.found.value) == 1 + assert int(dut.macAddr.value) == LEGACY_MAC_CFGS[1] + + dut.pos.value = 1 + await cycle(bench.clk, 1) + assert int(dut.found.value) == 1 + assert int(dut.macAddr.value) == LEGACY_MAC_CFGS[1] + assert int(dut.ipAddrOut.value) == LEGACY_IP_CFGS[1] + + +@cocotb.test() +async def arp_ip_table_expiration_reclaims_entry_test(dut): + bench = await setup_arp_ip_table_bench(dut) + + dut.ipWrAddr.value = LEGACY_IP_CFGS[1] + await pulse(dut.ipWrEn, clk=bench.clk) + dut.macWrAddr.value = LEGACY_MAC_CFGS[1] + await pulse(dut.macWrEn, clk=bench.clk) + + # With the wrapper's tiny timing generics the entry should expire after a + # handful of clock cycles if no inbound traffic refreshes the timer. + await cycle(bench.clk, 24) + dut.ipAddrIn.value = LEGACY_IP_CFGS[1] + dut.pos.value = 0 + await cycle(bench.clk, 2) + assert int(dut.found.value) == 0 + + # Reuse the reclaimed slot with a new mapping and confirm the old one no + # longer answers while the new one does. + dut.ipWrAddr.value = LEGACY_IP_CFGS[2] + await pulse(dut.ipWrEn, clk=bench.clk) + await cycle(bench.clk, 2) + dut.macWrAddr.value = LEGACY_MAC_CFGS[2] + await pulse(dut.macWrEn, clk=bench.clk) + + dut.ipAddrIn.value = LEGACY_IP_CFGS[1] + dut.pos.value = 0 + await cycle(bench.clk, 2) + assert int(dut.found.value) == 0 + + dut.ipAddrIn.value = LEGACY_IP_CFGS[2] + await cycle(bench.clk, 2) + assert int(dut.found.value) == 1 + assert int(dut.macAddr.value) == LEGACY_MAC_CFGS[2] + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="arp_ip_table_flat_wrapper")]) +def test_ArpIpTable(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.arpiptableflatwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": UDP_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/UdpEngine/test_UdpEngine.py b/tests/ethernet/UdpEngine/test_UdpEngine.py new file mode 100644 index 0000000000..e79a5e337b --- /dev/null +++ b/tests/ethernet/UdpEngine/test_UdpEngine.py @@ -0,0 +1,124 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Exercise the UDP top across the client ARP-assisted TX path and the +# server RX path. +# - Stimulus: Allow the client side to request ARP resolution, acknowledge it, +# then send an outbound client payload while separately injecting a server- +# targeted pseudo-UDP frame into the inbound path. +# - Checks: The top must emit the expected ARP lookup and outbound pseudo-UDP +# frame on the client side, and must route inbound server traffic to the +# exposed server output with the header removed. +# - Timing: The bench waits on actual AXIS handshakes on all exposed streams so +# the integrated ARP, TX, and RX state transitions are observed in flight. + +from __future__ import annotations + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + frame_beats_from_bytes, + payload_from_beat, + payload_from_beats, + recv_frame, + send_contiguous_frame, + cycle, +) +from tests.ethernet.UdpEngine.udp_test_utils import ( + LEGACY_IPS, + LEGACY_MAC_CFGS, + LEGACY_MAC_WIRES, + UDP_RTL_SOURCES, + build_udp_rx_pseudo_frame, + build_udp_tx_pseudo_frame, + ipv4_to_bytes, + setup_udp_top_bench, +) + + +WRAPPER_PATH = "ethernet/UdpEngine/wrappers/UdpEngineTopFlatWrapper.vhd" + + +@cocotb.test() +async def udp_engine_client_arp_then_transmit_test(dut): + bench = await setup_udp_top_bench(dut) + + arp_request = await bench.arp_req_sink.recv( + clk=bench.clk, + ready_signal=dut.arpReqTReady, + ) + assert payload_from_beat(arp_request)[:4] == ipv4_to_bytes(LEGACY_IPS[1]) + + arp_ack = frame_beats_from_bytes(LEGACY_MAC_WIRES[1].to_bytes(6, byteorder="big")) + ack_send = cocotb.start_soon(send_contiguous_frame(bench.arp_ack_source, arp_ack, clk=bench.clk)) + await cycle(bench.clk, 6) + await ack_send + + client_payload = b"udp-top-client-path" + client_send = cocotb.start_soon( + send_contiguous_frame(bench.client_source, frame_beats_from_bytes(client_payload), clk=bench.clk) + ) + udp_observed = await recv_frame( + bench.udp_sink, + clk=bench.clk, + ready_signal=dut.mUdpTReady, + timeout_cycles=64, + ) + await client_send + + assert payload_from_beats(udp_observed) == build_udp_tx_pseudo_frame( + dst_mac=LEGACY_MAC_WIRES[1], + src_ip=LEGACY_IPS[0], + dst_ip=LEGACY_IPS[1], + src_port=8193, + dst_port=8192, + payload=client_payload, + ) + + +@cocotb.test() +async def udp_engine_server_rx_path_test(dut): + bench = await setup_udp_top_bench(dut) + + server_payload = b"udp-top-server-path" + server_frame = build_udp_rx_pseudo_frame( + remote_mac=LEGACY_MAC_WIRES[1], + remote_ip=LEGACY_IPS[1], + local_ip=LEGACY_IPS[0], + remote_port=0x4567, + local_port=8192, + payload=server_payload, + ) + server_send = cocotb.start_soon( + send_contiguous_frame(bench.udp_source, frame_beats_from_bytes(server_frame), clk=bench.clk) + ) + server_observed = await recv_frame( + bench.server_sink, + clk=bench.clk, + ready_signal=dut.mServerTReady, + timeout_cycles=64, + ) + await server_send + + assert payload_from_beats(server_observed) == server_payload + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="udp_engine_top_flat_wrapper")]) +def test_UdpEngine(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.udpenginetopflatwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": UDP_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/UdpEngine/test_UdpEngineArp.py b/tests/ethernet/UdpEngine/test_UdpEngineArp.py new file mode 100644 index 0000000000..504f3888aa --- /dev/null +++ b/tests/ethernet/UdpEngine/test_UdpEngineArp.py @@ -0,0 +1,123 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Exercise the UDP ARP helper across a table-hit path and a miss path +# that requires an outbound request and inbound acknowledgement. +# - Stimulus: Present a configured remote IP with either an already-populated +# ARP-table hit or an empty table entry followed by an ARP-ack beat. +# - Checks: Table hits must publish the cached remote MAC without emitting a +# request, while misses must raise a request for the configured IP and then +# latch/write back the acknowledged MAC. +# - Timing: The tests keep the ARP request asserted until the helper reaches a +# stable outcome, matching the level-sensitive contract used in the real top. + +from __future__ import annotations + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + FlatEmacEndpoint, + frame_beats_from_bytes, + payload_from_beat, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, + cycle, +) +from tests.ethernet.UdpEngine.udp_test_utils import ( + LEGACY_IP_CFGS, + LEGACY_IPS, + LEGACY_MAC_CFGS, + LEGACY_MAC_WIRES, + UDP_RTL_SOURCES, + ipv4_to_bytes, +) + + +WRAPPER_PATH = "ethernet/UdpEngine/wrappers/UdpEngineArpFlatWrapper.vhd" + + +async def setup_udp_arp_bench(dut): + bench = await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + initial_values={ + "localIp": LEGACY_IP_CFGS[0], + "arpTabFound": 0, + "arpTabMacAddr": 0, + "clientRemoteDetValid": 0, + "clientRemoteDetIp": 0, + "clientRemoteIp": 0, + "arpReqTReady": 0, + "arpAckTValid": 0, + "arpAckTData": 0, + "arpAckTKeep": 0, + "arpAckTLast": 0, + "arpAckSof": 0, + "arpAckEofe": 0, + }, + ) + arp_req_sink = FlatEmacEndpoint(dut, prefix="arpReq") + arp_ack_source = FlatEmacEndpoint(dut, prefix="arpAck") + arp_ack_source.set_idle() + return bench, arp_req_sink, arp_ack_source + + +@cocotb.test() +async def udp_engine_arp_uses_cached_mac_without_request_test(dut): + bench, _, _ = await setup_udp_arp_bench(dut) + + dut.clientRemoteIp.value = LEGACY_IP_CFGS[1] + dut.arpTabFound.value = 1 + dut.arpTabMacAddr.value = LEGACY_MAC_CFGS[1] + await cycle(bench.clk, 6) + + assert int(dut.clientRemoteMac.value) == LEGACY_MAC_CFGS[1] + assert int(dut.arpReqTValid.value) == 0 + assert int(dut.arpTabIpWe.value) == 0 + + +@cocotb.test() +async def udp_engine_arp_request_ack_round_trip_test(dut): + bench, arp_req_sink, arp_ack_source = await setup_udp_arp_bench(dut) + + dut.clientRemoteIp.value = LEGACY_IP_CFGS[1] + await cycle(bench.clk, 6) + + # A miss should emit an outbound ARP request carrying the configured + # remote IP in the low 32 bits. + request_observed = await arp_req_sink.recv( + clk=bench.clk, + ready_signal=dut.arpReqTReady, + ) + assert payload_from_beat(request_observed)[:4] == ipv4_to_bytes(LEGACY_IPS[1]) + + arp_ack = frame_beats_from_bytes(LEGACY_MAC_WIRES[1].to_bytes(6, byteorder="big")) + ack_send = cocotb.start_soon(send_contiguous_frame(arp_ack_source, arp_ack, clk=bench.clk)) + await cycle(bench.clk, 4) + await ack_send + + assert int(dut.clientRemoteMac.value) == LEGACY_MAC_CFGS[1] + assert int(dut.arpTabMacAddrW.value) == LEGACY_MAC_CFGS[1] + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="udp_engine_arp_flat_wrapper")]) +def test_UdpEngineArp(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.udpenginearpflatwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": UDP_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/UdpEngine/test_UdpEngineDhcp.py b/tests/ethernet/UdpEngine/test_UdpEngineDhcp.py new file mode 100644 index 0000000000..6a84de1671 --- /dev/null +++ b/tests/ethernet/UdpEngine/test_UdpEngineDhcp.py @@ -0,0 +1,132 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Exercise the DHCP engine across the full discover/offer/request/ack +# exchange that establishes a leased address. +# - Stimulus: Allow the engine to emit its initial discover, inject a matching +# DHCP offer, capture the resulting request, then inject the matching ack. +# - Checks: The outbound discover and request must advertise the correct DHCP +# message type and XID continuity, and the final ack must update `dhcpIp`. +# - Timing: The test relies on the wrapper's shortened timers so the protocol +# steps occur through the real timeout logic rather than direct state forcing. + +from __future__ import annotations + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + FlatEmacEndpoint, + cycle, + frame_beats_from_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, +) +from tests.ethernet.UdpEngine.udp_test_utils import ( + LEGACY_IPS, + LEGACY_MAC_CFGS, + LEGACY_MAC_WIRES, + UDP_RTL_SOURCES, + build_dhcp_reply_payload, + extract_dhcp_message_type, + extract_dhcp_requested_ip, + extract_dhcp_server_identifier, + extract_dhcp_xid, + ipv4_config_word, +) + + +WRAPPER_PATH = "ethernet/UdpEngine/wrappers/UdpEngineDhcpFlatWrapper.vhd" + + +async def setup_udp_dhcp_bench(dut): + bench = await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + source_prefix="sDhcp", + initial_values={ + "localMac": LEGACY_MAC_CFGS[0], + "localIp": 0, + "mDhcpTReady": 0, + }, + ) + assert bench.source is not None + return bench, bench.source, FlatEmacEndpoint(dut, prefix="mDhcp") + + +@cocotb.test() +async def udp_engine_dhcp_offer_ack_sequence_test(dut): + bench, dhcp_source, dhcp_sink = await setup_udp_dhcp_bench(dut) + + discover_observed = await recv_frame( + dhcp_sink, + clk=bench.clk, + ready_signal=dut.mDhcpTReady, + timeout_cycles=256, + ) + discover_payload = payload_from_beats(discover_observed) + discover_xid = extract_dhcp_xid(discover_payload) + assert extract_dhcp_message_type(discover_payload) == 1 + + offer_payload = build_dhcp_reply_payload( + message_type=2, + xid=discover_xid, + client_mac=LEGACY_MAC_WIRES[0], + yiaddr="192.168.2.44", + siaddr=LEGACY_IPS[1], + ) + offer_send = cocotb.start_soon( + send_contiguous_frame(dhcp_source, frame_beats_from_bytes(offer_payload), clk=bench.clk) + ) + request_observed = await recv_frame( + dhcp_sink, + clk=bench.clk, + ready_signal=dut.mDhcpTReady, + timeout_cycles=256, + ) + await offer_send + request_payload = payload_from_beats(request_observed) + request_xid = extract_dhcp_xid(request_payload) + assert extract_dhcp_message_type(request_payload) == 3 + assert extract_dhcp_requested_ip(request_payload) == "192.168.2.44" + assert extract_dhcp_server_identifier(request_payload) == LEGACY_IPS[1] + + ack_payload = build_dhcp_reply_payload( + message_type=5, + xid=request_xid, + client_mac=LEGACY_MAC_WIRES[0], + yiaddr="192.168.2.44", + siaddr=LEGACY_IPS[1], + ) + ack_send = cocotb.start_soon( + send_contiguous_frame(dhcp_source, frame_beats_from_bytes(ack_payload), clk=bench.clk) + ) + await ack_send + for _ in range(128): + await cycle(bench.clk, 1) + if int(dut.dhcpIp.value) == ipv4_config_word("192.168.2.44"): + break + assert int(dut.dhcpIp.value) == ipv4_config_word("192.168.2.44") + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="udp_engine_dhcp_flat_wrapper")]) +def test_UdpEngineDhcp(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.udpenginedhcpflatwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": UDP_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/UdpEngine/test_UdpEngineRx.py b/tests/ethernet/UdpEngine/test_UdpEngineRx.py new file mode 100644 index 0000000000..1640efc956 --- /dev/null +++ b/tests/ethernet/UdpEngine/test_UdpEngineRx.py @@ -0,0 +1,146 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Exercise server routing, client routing, and DHCP routing through +# the UDP RX path. +# - Stimulus: Inject pseudo-UDP frames targeted at the server port, the client +# port, and the DHCP socket tuple. +# - Checks: Each frame must emerge on the correct output with the UDP header +# stripped, and the server/client sideband metadata must latch the sender. +# - Timing: The sink-side assertions wait on real ready/valid handshakes so +# the test observes the RX state machine rather than sampling combinationally. + +from __future__ import annotations + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + cycle, + frame_beats_from_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, +) +from tests.ethernet.UdpEngine.udp_test_utils import ( + DHCP_CLIENT_PORT, + DHCP_SERVER_PORT, + LEGACY_IPS, + LEGACY_MAC_CFGS, + LEGACY_MAC_WIRES, + UDP_RTL_SOURCES, + build_udp_rx_pseudo_frame, + port_config_word, + setup_udp_rx_bench, + ipv4_config_word, +) + + +WRAPPER_PATH = "ethernet/UdpEngine/wrappers/UdpEngineRxFlatWrapper.vhd" + + +@cocotb.test() +async def udp_engine_rx_routes_server_payload_and_debug_test(dut): + bench = await setup_udp_rx_bench(dut) + + server_payload = b"udp-rx-server-path" + server_frame = build_udp_rx_pseudo_frame( + remote_mac=LEGACY_MAC_WIRES[1], + remote_ip=LEGACY_IPS[1], + local_ip=LEGACY_IPS[0], + remote_port=0x1234, + local_port=8192, + payload=server_payload, + ) + + server_send = cocotb.start_soon( + send_contiguous_frame(bench.source, frame_beats_from_bytes(server_frame), clk=bench.clk) + ) + server_observed = await recv_frame( + bench.server_sink, + clk=bench.clk, + ready_signal=dut.mServerTReady, + timeout_cycles=64, + ) + await server_send + + assert payload_from_beats(server_observed) == server_payload + assert int(dut.serverRemotePort.value) == port_config_word(0x1234) + assert int(dut.serverRemoteIp.value) == ipv4_config_word(LEGACY_IPS[1]) + assert int(dut.serverRemoteMac.value) == LEGACY_MAC_CFGS[1] + + +@cocotb.test() +async def udp_engine_rx_routes_client_payload_and_detection_test(dut): + bench = await setup_udp_rx_bench(dut) + + client_payload = b"udp-rx-client-path" + client_frame = build_udp_rx_pseudo_frame( + remote_mac=LEGACY_MAC_WIRES[1], + remote_ip=LEGACY_IPS[1], + local_ip=LEGACY_IPS[0], + remote_port=0x5678, + local_port=8193, + payload=client_payload, + ) + + client_send = cocotb.start_soon( + send_contiguous_frame(bench.source, frame_beats_from_bytes(client_frame), clk=bench.clk) + ) + client_observed = await recv_frame( + bench.client_sink, + clk=bench.clk, + ready_signal=dut.mClientTReady, + timeout_cycles=64, + ) + await client_send + + assert payload_from_beats(client_observed) == client_payload + + +@cocotb.test() +async def udp_engine_rx_routes_dhcp_socket_test(dut): + bench = await setup_udp_rx_bench(dut) + + dhcp_payload = b"udp-rx-dhcp-path" + dhcp_frame = build_udp_rx_pseudo_frame( + remote_mac=LEGACY_MAC_WIRES[1], + remote_ip=LEGACY_IPS[1], + local_ip=LEGACY_IPS[0], + remote_port=DHCP_SERVER_PORT, + local_port=DHCP_CLIENT_PORT, + payload=dhcp_payload, + ) + + dhcp_send = cocotb.start_soon( + send_contiguous_frame(bench.source, frame_beats_from_bytes(dhcp_frame), clk=bench.clk) + ) + dhcp_observed = await recv_frame( + bench.dhcp_sink, + clk=bench.clk, + ready_signal=dut.mDhcpTReady, + timeout_cycles=64, + ) + await dhcp_send + + assert payload_from_beats(dhcp_observed) == dhcp_payload + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="udp_engine_rx_flat_wrapper")]) +def test_UdpEngineRx(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.udpenginerxflatwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": UDP_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/UdpEngine/test_UdpEngineTx.py b/tests/ethernet/UdpEngine/test_UdpEngineTx.py new file mode 100644 index 0000000000..f7dbecedb5 --- /dev/null +++ b/tests/ethernet/UdpEngine/test_UdpEngineTx.py @@ -0,0 +1,110 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Exercise the UDP TX path across normal server traffic and DHCP +# passthrough traffic. +# - Stimulus: Drive one application payload with a live remote endpoint, then +# drive one DHCP payload through the dedicated DHCP ingress. +# - Checks: The emitted pseudo-UDP frames must contain the expected source and +# destination metadata, and `linkUp` must assert once the endpoint is valid. +# - Timing: The tests wait on accepted AXIS transfers instead of assuming fixed +# latency so the TX state machine and pipeline remain visible. + +from __future__ import annotations + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + frame_beats_from_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, +) +from tests.ethernet.UdpEngine.udp_test_utils import ( + DHCP_CLIENT_PORT, + DHCP_SERVER_PORT, + LEGACY_IPS, + LEGACY_MAC_WIRES, + UDP_RTL_SOURCES, + build_udp_tx_pseudo_frame, + setup_udp_tx_bench, + wait_for_link_up, +) + + +WRAPPER_PATH = "ethernet/UdpEngine/wrappers/UdpEngineTxFlatWrapper.vhd" + + +@cocotb.test() +async def udp_engine_tx_server_payload_header_test(dut): + bench = await setup_udp_tx_bench(dut) + + await wait_for_link_up(dut.linkUp, clk=bench.clk) + + payload = b"udp-tx-server-payload" + send_task = cocotb.start_soon( + send_contiguous_frame(bench.source, frame_beats_from_bytes(payload), clk=bench.clk) + ) + observed = await recv_frame( + bench.sink, + clk=bench.clk, + ready_signal=dut.mUdpTReady, + timeout_cycles=64, + ) + await send_task + + assert payload_from_beats(observed) == build_udp_tx_pseudo_frame( + dst_mac=LEGACY_MAC_WIRES[1], + src_ip=LEGACY_IPS[0], + dst_ip=LEGACY_IPS[1], + src_port=8192, + dst_port=8192, + payload=payload, + ) + + +@cocotb.test() +async def udp_engine_tx_dhcp_passthrough_test(dut): + bench = await setup_udp_tx_bench(dut) + + dhcp_payload = b"dhcp-client-discover" + dhcp_send = cocotb.start_soon( + send_contiguous_frame(bench.dhcp_source, frame_beats_from_bytes(dhcp_payload), clk=bench.clk) + ) + observed = await recv_frame( + bench.sink, + clk=bench.clk, + ready_signal=dut.mUdpTReady, + timeout_cycles=64, + ) + await dhcp_send + + assert payload_from_beats(observed) == build_udp_tx_pseudo_frame( + dst_mac=0xFFFFFFFFFFFF, + src_ip="0.0.0.0", + dst_ip="255.255.255.255", + src_port=DHCP_CLIENT_PORT, + dst_port=DHCP_SERVER_PORT, + payload=dhcp_payload, + ) + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="udp_engine_tx_flat_wrapper")]) +def test_UdpEngineTx(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.udpenginetxflatwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": UDP_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/UdpEngine/test_UdpEngineWrapper.py b/tests/ethernet/UdpEngine/test_UdpEngineWrapper.py new file mode 100644 index 0000000000..3b632de07c --- /dev/null +++ b/tests/ethernet/UdpEngine/test_UdpEngineWrapper.py @@ -0,0 +1,96 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Exercise the wrapper-specific AXI-Lite register bank alongside one +# inbound server-routing path through the integrated MAC/IPv4/UDP stack. +# - Stimulus: Program the client configuration and soft-IP registers through +# AXI-Lite, then inject a UDP/IP/Ethernet frame addressed to the local host. +# - Checks: AXI-Lite writes and reads must reflect the programmed values, the +# wrapper must route the UDP payload to the server output, and the server +# debug readbacks must report the remote endpoint that sent the packet. +# - Timing: The test uses the wrapper's real AXI-Lite and AXIS interfaces so +# register-bank behavior is verified in the same integration topology as RTL. + +from __future__ import annotations + +import cocotb +import pytest + +from tests.axi.utils import axil_read_u32, axil_write_u32 +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + build_ipv4_udp_frame, + frame_beats_from_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, +) +from tests.ethernet.IpV4Engine.ipv4_test_utils import IPV4_RTL_SOURCES +from tests.ethernet.UdpEngine.udp_test_utils import ( + LEGACY_IPS, + LEGACY_MAC_WIRES, + UDP_RTL_SOURCES, + port_config_word, + ipv4_config_word, + setup_udp_wrapper_bench, +) + + +WRAPPER_PATH = "ethernet/UdpEngine/wrappers/UdpEngineWrapperFlatWrapper.vhd" + + +@cocotb.test() +async def udp_engine_wrapper_axil_and_server_path_test(dut): + bench = await setup_udp_wrapper_bench(dut) + + await axil_write_u32(bench.axil, 0x000, 0x0020) + await axil_write_u32(bench.axil, 0x004, ipv4_config_word(LEGACY_IPS[1])) + await axil_write_u32(bench.axil, 0xFE4, ipv4_config_word("192.168.2.99")) + + assert await axil_read_u32(bench.axil, 0x000) == 0x0020 + assert await axil_read_u32(bench.axil, 0x004) == ipv4_config_word(LEGACY_IPS[1]) + assert await axil_read_u32(bench.axil, 0xFE4) == ipv4_config_word("192.168.2.99") + assert int(dut.softIp.value) == ipv4_config_word("192.168.2.99") + + inbound_frame = build_ipv4_udp_frame( + dst_mac=LEGACY_MAC_WIRES[0], + src_mac=LEGACY_MAC_WIRES[1], + src_ip=LEGACY_IPS[1], + dst_ip=LEGACY_IPS[0], + src_port=0x4567, + dst_port=8192, + payload=b"udp-wrapper-server-path", + ) + inbound_send = cocotb.start_soon( + send_contiguous_frame(bench.mac_source, frame_beats_from_bytes(inbound_frame), clk=bench.clk) + ) + server_observed = await recv_frame( + bench.server_sink, + clk=bench.clk, + ready_signal=dut.mServerTReady, + timeout_cycles=128, + ) + await inbound_send + + assert payload_from_beats(server_observed) == b"udp-wrapper-server-path" + assert await axil_read_u32(bench.axil, 0x800) == port_config_word(0x4567) + assert await axil_read_u32(bench.axil, 0x804) == ipv4_config_word(LEGACY_IPS[1]) + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="udp_engine_wrapper_flat_wrapper")]) +def test_UdpEngineWrapper(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.udpenginewrapperflatwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": IPV4_RTL_SOURCES + UDP_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/UdpEngine/test_UdpEngineWrapperPair.py b/tests/ethernet/UdpEngine/test_UdpEngineWrapperPair.py new file mode 100644 index 0000000000..48e3efc69f --- /dev/null +++ b/tests/ethernet/UdpEngine/test_UdpEngineWrapperPair.py @@ -0,0 +1,128 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Recreate the legacy `UdpEngineTb` topology with one client wrapper +# talking to three server wrappers through a selectable link. +# - Stimulus: Send client traffic after learning server 0, switch the remote IP +# and physical link to learn server 1, then send a third packet with `tDest` +# selecting the cached server-0 ARP entry while server 1 remains configured. +# - Checks: The first packet must arrive at server 0, the second at server 1, +# and the indexed-route packet must return to server 0 just like the legacy +# bench's post-switch `tDest <= x"01"` case. +# - Timing: The test waits for the integrated wrappers to resolve ARP through +# their real MAC-side cross-link before launching each UDP payload. + +from __future__ import annotations + +import cocotb +import pytest +from cocotb.triggers import with_timeout + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + ETHMAC_RTL_SOURCES, + ROCE_ANALYSIS_SOURCES, + frame_beats_from_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, + cycle, +) +from tests.ethernet.IpV4Engine.ipv4_test_utils import IPV4_RTL_SOURCES +from tests.ethernet.UdpEngine.udp_test_utils import LEGACY_IP_CFGS, UDP_RTL_SOURCES, setup_udp_wrapper_pair_bench + + +WRAPPER_PATH = "ethernet/UdpEngine/wrappers/UdpEngineWrapperPairFlatWrapper.vhd" + + +async def wait_for_pair_arp_resolution(dut, *, clk, cycles: int = 256) -> None: + # The client wrapper needs time to emit an ARP request, receive the server + # response through the selected link, and update its internal ARP table. + await cycle(clk, cycles) + + +@cocotb.test() +async def udp_engine_wrapper_pair_matches_legacy_route_switching_test(dut): + bench = await setup_udp_wrapper_pair_bench(dut) + + await wait_for_pair_arp_resolution(dut, clk=bench.clk) + payload0 = b"legacy-path-server0" + send0 = cocotb.start_soon( + send_contiguous_frame(bench.client_source, frame_beats_from_bytes(payload0), clk=bench.clk) + ) + observed0 = await with_timeout( + recv_frame( + bench.server_sinks[0], + clk=bench.clk, + ready_signal=dut.mServer0TReady, + timeout_cycles=1024, + ), + 10, + "us", + ) + await with_timeout(send0, 10, "us") + assert payload_from_beats(observed0) == payload0 + + dut.clientRemoteIp.value = LEGACY_IP_CFGS[2] + dut.selectedServer.value = 2 + await wait_for_pair_arp_resolution(dut, clk=bench.clk) + payload1 = b"legacy-path-server1" + send1 = cocotb.start_soon( + send_contiguous_frame(bench.client_source, frame_beats_from_bytes(payload1), clk=bench.clk) + ) + observed1 = await with_timeout( + recv_frame( + bench.server_sinks[1], + clk=bench.clk, + ready_signal=dut.mServer1TReady, + timeout_cycles=1024, + ), + 10, + "us", + ) + await with_timeout(send1, 10, "us") + assert payload_from_beats(observed1) == payload1 + + dut.selectedServer.value = 1 + await cycle(bench.clk, 8) + payload2 = b"legacy-indexed-server0" + send2 = cocotb.start_soon( + send_contiguous_frame( + bench.client_source, + frame_beats_from_bytes(payload2, dest=1), + clk=bench.clk, + ) + ) + observed2 = await with_timeout( + recv_frame( + bench.server_sinks[0], + clk=bench.clk, + ready_signal=dut.mServer0TReady, + timeout_cycles=1024, + ), + 10, + "us", + ) + await with_timeout(send2, 10, "us") + assert payload_from_beats(observed2) == payload2 + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="udp_engine_wrapper_pair_flat_wrapper")]) +def test_UdpEngineWrapperPair(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.udpenginewrapperpairflatwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={ + "surf": ETHMAC_RTL_SOURCES + ROCE_ANALYSIS_SOURCES + IPV4_RTL_SOURCES + UDP_RTL_SOURCES + [WRAPPER_PATH] + }, + ) diff --git a/tests/ethernet/UdpEngine/udp_test_utils.py b/tests/ethernet/UdpEngine/udp_test_utils.py new file mode 100644 index 0000000000..8bfeabba84 --- /dev/null +++ b/tests/ethernet/UdpEngine/udp_test_utils.py @@ -0,0 +1,445 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +from __future__ import annotations + +from dataclasses import dataclass +import ipaddress +from pathlib import Path + +from cocotb.triggers import Timer +from cocotbext.axi import AxiLiteBus, AxiLiteMaster + +from tests.axi.utils import axil_read_u32, axil_write_u32 +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + FlatEmacEndpoint, + cycle, + frame_beats_from_bytes, + mac_config_word_from_wire, + payload_from_beats, + setup_flat_emac_testbench, +) +from tests.ethernet.IpV4Engine.ipv4_test_utils import ipv4_config_word + + +UDP_RTL_SOURCES = [ + str(path) + for path in sorted((Path(__file__).resolve().parents[3] / "ethernet" / "UdpEngine" / "rtl").glob("*.vhd")) +] + + +LEGACY_MAC_WIRES = ( + 0x004456000301, + 0x004456000302, + 0x004456000303, + 0x004456000304, +) +LEGACY_MAC_CFGS = tuple(mac_config_word_from_wire(value) for value in LEGACY_MAC_WIRES) +LEGACY_IPS = ( + "192.168.2.10", + "192.168.2.11", + "192.168.2.12", + "192.168.2.13", +) +LEGACY_IP_CFGS = tuple(ipv4_config_word(value) for value in LEGACY_IPS) + +UDP_PROTOCOL = 0x11 +DHCP_CLIENT_PORT = 68 +DHCP_SERVER_PORT = 67 + + +@dataclass +class UdpRxBench: + clk: object + source: FlatEmacEndpoint + server_sink: FlatEmacEndpoint + client_sink: FlatEmacEndpoint + dhcp_sink: FlatEmacEndpoint + + +@dataclass +class UdpTxBench: + clk: object + source: FlatEmacEndpoint + sink: FlatEmacEndpoint + dhcp_source: FlatEmacEndpoint + + +@dataclass +class UdpTopBench: + clk: object + udp_source: FlatEmacEndpoint + udp_sink: FlatEmacEndpoint + server_source: FlatEmacEndpoint + server_sink: FlatEmacEndpoint + client_source: FlatEmacEndpoint + client_sink: FlatEmacEndpoint + arp_req_sink: FlatEmacEndpoint + arp_ack_source: FlatEmacEndpoint + + +@dataclass +class UdpWrapperBench: + clk: object + axil: AxiLiteMaster + mac_source: FlatEmacEndpoint + mac_sink: FlatEmacEndpoint + server_source: FlatEmacEndpoint + server_sink: FlatEmacEndpoint + client_source: FlatEmacEndpoint + client_sink: FlatEmacEndpoint + + +@dataclass +class UdpWrapperPairBench: + clk: object + client_source: FlatEmacEndpoint + server_sinks: list[FlatEmacEndpoint] + + +def ipv4_to_bytes(address: str) -> bytes: + return ipaddress.IPv4Address(address).packed + + +def port_config_word(port: int) -> int: + return int.from_bytes(port.to_bytes(2, byteorder="big")[::-1], byteorder="big") + + +def pack_udp_app_payload(payload: bytes) -> list: + return frame_beats_from_bytes(payload) + + +def build_udp_rx_pseudo_frame( + *, + remote_mac: int, + remote_ip: str, + local_ip: str, + remote_port: int, + local_port: int, + payload: bytes, + udp_checksum: int = 0, + extra_trailer: bytes = b"", +) -> bytes: + udp_length = 8 + len(payload) + len(extra_trailer) + header0 = remote_mac.to_bytes(6, byteorder="big") + b"\x00\x00" + ipv4_to_bytes(remote_ip) + ipv4_to_bytes(local_ip) + header1 = ( + bytes([0x00, UDP_PROTOCOL]) + + b"\x00\x00" + + remote_port.to_bytes(2, byteorder="big") + + local_port.to_bytes(2, byteorder="big") + + udp_length.to_bytes(2, byteorder="big") + + udp_checksum.to_bytes(2, byteorder="big") + + payload[:4].ljust(4, b"\x00") + ) + return header0 + header1 + payload[4:] + extra_trailer + + +def build_udp_tx_pseudo_frame( + *, + dst_mac: int, + src_ip: str, + dst_ip: str, + src_port: int, + dst_port: int, + payload: bytes, +) -> bytes: + header0 = dst_mac.to_bytes(6, byteorder="big") + b"\x00\x00" + ipv4_to_bytes(src_ip) + ipv4_to_bytes(dst_ip) + header1 = ( + bytes([0x00, UDP_PROTOCOL]) + + b"\x00\x00" + + src_port.to_bytes(2, byteorder="big") + + dst_port.to_bytes(2, byteorder="big") + + b"\x00\x00" + + b"\x00\x00" + + payload[:4].ljust(4, b"\x00") + ) + return header0 + header1 + payload[4:] + + +def build_dhcp_reply_payload( + *, + message_type: int, + xid: int, + client_mac: int, + yiaddr: str, + siaddr: str, + lease_time: int = 120, +) -> bytes: + payload = bytearray(240) + payload[0] = 0x02 + payload[1] = 0x01 + payload[2] = 0x06 + payload[3] = 0x00 + payload[4:8] = xid.to_bytes(4, byteorder="big") + payload[16:20] = ipv4_to_bytes(yiaddr) + payload[20:24] = ipv4_to_bytes(siaddr) + payload[28:34] = client_mac.to_bytes(6, byteorder="big") + payload[236:240] = bytes.fromhex("63825363") + payload.extend( + bytes( + [ + 53, + 1, + message_type & 0xFF, + 51, + 4, + ] + ) + ) + payload.extend(lease_time.to_bytes(4, byteorder="big")) + payload.extend(bytes([255])) + return bytes(payload) + + +def extract_dhcp_xid(payload: bytes) -> int: + return int.from_bytes(payload[4:8], byteorder="big") + + +def extract_dhcp_message_type(payload: bytes) -> int | None: + index = 240 + while index < len(payload): + code = payload[index] + if code == 0: + index += 1 + continue + if code == 255: + return None + if index + 1 >= len(payload): + return None + length = payload[index + 1] + data_start = index + 2 + data_stop = data_start + length + if data_stop > len(payload): + return None + if code == 53 and length == 1: + return payload[data_start] + index = data_stop + return None + + +def extract_dhcp_requested_ip(payload: bytes) -> str | None: + index = 240 + while index < len(payload): + code = payload[index] + if code == 0: + index += 1 + continue + if code == 255: + return None + length = payload[index + 1] + data_start = index + 2 + data_stop = data_start + length + if code == 50 and length == 4: + return str(ipaddress.IPv4Address(payload[data_start:data_stop])) + index = data_stop + return None + + +def extract_dhcp_server_identifier(payload: bytes) -> str | None: + index = 240 + while index < len(payload): + code = payload[index] + if code == 0: + index += 1 + continue + if code == 255: + return None + length = payload[index + 1] + data_start = index + 2 + data_stop = data_start + length + if code == 54 and length == 4: + return str(ipaddress.IPv4Address(payload[data_start:data_stop])) + index = data_stop + return None + + +async def axil_read_u48(master, address: int) -> int: + low = await axil_read_u32(master, address) + high = await axil_read_u32(master, address + 4) + return low | ((high & 0xFFFF) << 32) + + +async def axil_write_u48(master, address: int, value: int) -> None: + await axil_write_u32(master, address, value & 0xFFFF_FFFF) + await axil_write_u32(master, address + 4, (value >> 32) & 0xFFFF) + + +async def wait_for_link_up(signal, *, clk, timeout_cycles: int = 64) -> None: + for _ in range(timeout_cycles): + await Timer(1, unit="ns") + if int(signal.value) != 0: + return + await cycle(clk, 1) + raise AssertionError("Timed out waiting for link-up") + + +async def setup_udp_rx_bench(dut) -> UdpRxBench: + bench = await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + source_prefix="sUdp", + initial_values={ + "localIp": LEGACY_IP_CFGS[0], + "broadcastIp": ipv4_config_word("255.255.255.255"), + "igmpIp": 0, + "mServerTReady": 0, + "mClientTReady": 0, + "mDhcpTReady": 0, + }, + ) + assert bench.source is not None + return UdpRxBench( + clk=bench.clk, + source=bench.source, + server_sink=FlatEmacEndpoint(dut, prefix="mServer"), + client_sink=FlatEmacEndpoint(dut, prefix="mClient"), + dhcp_sink=FlatEmacEndpoint(dut, prefix="mDhcp"), + ) + + +async def setup_udp_tx_bench(dut) -> UdpTxBench: + bench = await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + initial_values={ + "localMac": LEGACY_MAC_CFGS[0], + "localIp": LEGACY_IP_CFGS[0], + "remotePort": 0x0020, + "remoteIp": LEGACY_IP_CFGS[1], + "remoteMac": LEGACY_MAC_CFGS[1], + "arpTabFound": 0, + "arpTabIpAddr": 0, + "arpTabMacAddr": 0, + "mUdpTReady": 0, + "sDhcpTValid": 0, + "sDhcpTData": 0, + "sDhcpTKeep": 0, + "sDhcpTLast": 0, + "sDhcpSof": 0, + "sDhcpEofe": 0, + }, + ) + source = FlatEmacEndpoint(dut, prefix="sApp") + dhcp_source = FlatEmacEndpoint(dut, prefix="sDhcp") + sink = FlatEmacEndpoint(dut, prefix="mUdp") + source.set_idle() + dhcp_source.set_idle() + return UdpTxBench(clk=bench.clk, source=source, sink=sink, dhcp_source=dhcp_source) + + +async def setup_udp_top_bench(dut) -> UdpTopBench: + bench = await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + source_prefix="sUdp", + initial_values={ + "localMac": LEGACY_MAC_CFGS[0], + "localIp": LEGACY_IP_CFGS[0], + "broadcastIp": ipv4_config_word("255.255.255.255"), + "clientRemotePort": 0x0020, + "clientRemoteIp": LEGACY_IP_CFGS[1], + "mUdpTReady": 0, + "mServerTReady": 0, + "mClientTReady": 0, + "arpReqTReady": 0, + }, + ) + assert bench.source is not None + server_source = FlatEmacEndpoint(dut, prefix="sServer") + client_source = FlatEmacEndpoint(dut, prefix="sClient") + arp_ack_source = FlatEmacEndpoint(dut, prefix="arpAck") + server_source.set_idle() + client_source.set_idle() + arp_ack_source.set_idle() + return UdpTopBench( + clk=bench.clk, + udp_source=bench.source, + udp_sink=FlatEmacEndpoint(dut, prefix="mUdp"), + server_source=server_source, + server_sink=FlatEmacEndpoint(dut, prefix="mServer"), + client_source=client_source, + client_sink=FlatEmacEndpoint(dut, prefix="mClient"), + arp_req_sink=FlatEmacEndpoint(dut, prefix="arpReq"), + arp_ack_source=arp_ack_source, + ) + + +async def setup_udp_wrapper_bench(dut) -> UdpWrapperBench: + bench = await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + source_prefix="sMac", + initial_values={ + "localMac": LEGACY_MAC_CFGS[0], + "localIp": LEGACY_IP_CFGS[0], + "mMacTReady": 0, + "mServerTReady": 0, + "mClientTReady": 0, + "S_AXI_AWADDR": 0, + "S_AXI_AWPROT": 0, + "S_AXI_AWVALID": 0, + "S_AXI_WDATA": 0, + "S_AXI_WSTRB": 0, + "S_AXI_WVALID": 0, + "S_AXI_BREADY": 0, + "S_AXI_ARADDR": 0, + "S_AXI_ARPROT": 0, + "S_AXI_ARVALID": 0, + "S_AXI_RREADY": 0, + }, + ) + assert bench.source is not None + server_source = FlatEmacEndpoint(dut, prefix="sServer") + client_source = FlatEmacEndpoint(dut, prefix="sClient") + server_source.set_idle() + client_source.set_idle() + axil = AxiLiteMaster( + AxiLiteBus.from_prefix(dut, "S_AXI"), + dut.clk, + dut.rst, + reset_active_level=True, + ) + await cycle(bench.clk, 2) + return UdpWrapperBench( + clk=bench.clk, + axil=axil, + mac_source=bench.source, + mac_sink=FlatEmacEndpoint(dut, prefix="mMac"), + server_source=server_source, + server_sink=FlatEmacEndpoint(dut, prefix="mServer"), + client_source=client_source, + client_sink=FlatEmacEndpoint(dut, prefix="mClient"), + ) + + +async def setup_udp_wrapper_pair_bench(dut) -> UdpWrapperPairBench: + bench = await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + initial_values={ + "clientLocalMac": LEGACY_MAC_CFGS[0], + "clientLocalIp": LEGACY_IP_CFGS[0], + "clientRemotePort": 0x0020, + "clientRemoteIp": LEGACY_IP_CFGS[1], + "selectedServer": 1, + "mServer0TReady": 0, + "mServer1TReady": 0, + "mServer2TReady": 0, + }, + ) + client_source = FlatEmacEndpoint(dut, prefix="sClient") + client_source.set_idle() + server_sinks = [FlatEmacEndpoint(dut, prefix=f"mServer{index}") for index in range(3)] + return UdpWrapperPairBench(clk=bench.clk, client_source=client_source, server_sinks=server_sinks) From 76b819ff4e7da733b44050b6e7b9e69a10d71653 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 17 Apr 2026 10:34:31 -0700 Subject: [PATCH 14/92] Refactoring. --- tests/ethernet/UdpEngine/test_ArpIpTable.py | 51 +++------ tests/ethernet/UdpEngine/test_UdpEngine.py | 8 +- tests/ethernet/UdpEngine/test_UdpEngineArp.py | 45 ++------ .../ethernet/UdpEngine/test_UdpEngineDhcp.py | 36 ++---- tests/ethernet/UdpEngine/test_UdpEngineRx.py | 7 +- tests/ethernet/UdpEngine/test_UdpEngineTx.py | 6 + .../UdpEngine/test_UdpEngineWrapper.py | 4 + .../UdpEngine/test_UdpEngineWrapperPair.py | 23 ++-- tests/ethernet/UdpEngine/udp_test_utils.py | 106 ++++++++++++++++++ 9 files changed, 184 insertions(+), 102 deletions(-) diff --git a/tests/ethernet/UdpEngine/test_ArpIpTable.py b/tests/ethernet/UdpEngine/test_ArpIpTable.py index b2c24b3fe7..753e52a1ad 100644 --- a/tests/ethernet/UdpEngine/test_ArpIpTable.py +++ b/tests/ethernet/UdpEngine/test_ArpIpTable.py @@ -25,46 +25,29 @@ import pytest from tests.common.regression_utils import run_surf_vhdl_test -from tests.ethernet.EthMacCore.ethmac_test_utils import cycle, setup_flat_emac_testbench -from tests.ethernet.UdpEngine.udp_test_utils import LEGACY_IP_CFGS, LEGACY_MAC_CFGS, UDP_RTL_SOURCES +from tests.ethernet.EthMacCore.ethmac_test_utils import cycle +from tests.ethernet.UdpEngine.udp_test_utils import ( + LEGACY_IP_CFGS, + LEGACY_MAC_CFGS, + UDP_RTL_SOURCES, + pulse_signal, + setup_arp_ip_table_bench, +) WRAPPER_PATH = "ethernet/UdpEngine/wrappers/ArpIpTableFlatWrapper.vhd" -async def setup_arp_ip_table_bench(dut): - return await setup_flat_emac_testbench( - dut, - clk_name="clk", - rst_name="rst", - initial_values={ - "ipAddrIn": 0, - "pos": 0, - "clientRemoteDetIp": 0, - "clientRemoteDetValid": 0, - "ipWrEn": 0, - "ipWrAddr": 0, - "macWrEn": 0, - "macWrAddr": 0, - }, - ) - - -async def pulse(signal, *, clk) -> None: - signal.value = 1 - await cycle(clk, 1) - signal.value = 0 - await cycle(clk, 1) - - @cocotb.test() async def arp_ip_table_lookup_by_ip_and_position_test(dut): bench = await setup_arp_ip_table_bench(dut) + # Seed the table exactly the way the integrated UDP stack does: one write + # pulse for the IP half and one for the MAC half of the same entry. dut.ipWrAddr.value = LEGACY_IP_CFGS[1] - await pulse(dut.ipWrEn, clk=bench.clk) + await pulse_signal(dut.ipWrEn, clk=bench.clk) dut.macWrAddr.value = LEGACY_MAC_CFGS[1] - await pulse(dut.macWrEn, clk=bench.clk) + await pulse_signal(dut.macWrEn, clk=bench.clk) # `pos=0` uses IP-match lookup while `pos=1` directly addresses entry 0. dut.ipAddrIn.value = LEGACY_IP_CFGS[1] @@ -84,10 +67,12 @@ async def arp_ip_table_lookup_by_ip_and_position_test(dut): async def arp_ip_table_expiration_reclaims_entry_test(dut): bench = await setup_arp_ip_table_bench(dut) + # Start with one live entry so the wrapper's shortened timeout logic has + # something concrete to age out. dut.ipWrAddr.value = LEGACY_IP_CFGS[1] - await pulse(dut.ipWrEn, clk=bench.clk) + await pulse_signal(dut.ipWrEn, clk=bench.clk) dut.macWrAddr.value = LEGACY_MAC_CFGS[1] - await pulse(dut.macWrEn, clk=bench.clk) + await pulse_signal(dut.macWrEn, clk=bench.clk) # With the wrapper's tiny timing generics the entry should expire after a # handful of clock cycles if no inbound traffic refreshes the timer. @@ -100,10 +85,10 @@ async def arp_ip_table_expiration_reclaims_entry_test(dut): # Reuse the reclaimed slot with a new mapping and confirm the old one no # longer answers while the new one does. dut.ipWrAddr.value = LEGACY_IP_CFGS[2] - await pulse(dut.ipWrEn, clk=bench.clk) + await pulse_signal(dut.ipWrEn, clk=bench.clk) await cycle(bench.clk, 2) dut.macWrAddr.value = LEGACY_MAC_CFGS[2] - await pulse(dut.macWrEn, clk=bench.clk) + await pulse_signal(dut.macWrEn, clk=bench.clk) dut.ipAddrIn.value = LEGACY_IP_CFGS[1] dut.pos.value = 0 diff --git a/tests/ethernet/UdpEngine/test_UdpEngine.py b/tests/ethernet/UdpEngine/test_UdpEngine.py index e79a5e337b..4f973caeae 100644 --- a/tests/ethernet/UdpEngine/test_UdpEngine.py +++ b/tests/ethernet/UdpEngine/test_UdpEngine.py @@ -36,7 +36,6 @@ ) from tests.ethernet.UdpEngine.udp_test_utils import ( LEGACY_IPS, - LEGACY_MAC_CFGS, LEGACY_MAC_WIRES, UDP_RTL_SOURCES, build_udp_rx_pseudo_frame, @@ -53,17 +52,22 @@ async def udp_engine_client_arp_then_transmit_test(dut): bench = await setup_udp_top_bench(dut) + # The integrated top first needs an ARP resolution for the configured + # client remote IP before any outbound client payload can be emitted. arp_request = await bench.arp_req_sink.recv( clk=bench.clk, ready_signal=dut.arpReqTReady, ) assert payload_from_beat(arp_request)[:4] == ipv4_to_bytes(LEGACY_IPS[1]) + # Feed back the learned MAC so the client-side transmit path can continue. arp_ack = frame_beats_from_bytes(LEGACY_MAC_WIRES[1].to_bytes(6, byteorder="big")) ack_send = cocotb.start_soon(send_contiguous_frame(bench.arp_ack_source, arp_ack, clk=bench.clk)) await cycle(bench.clk, 6) await ack_send + # Once ARP is resolved, the outbound client payload should emerge on the + # shared UDP transmit stream with the expected pseudo-header fields. client_payload = b"udp-top-client-path" client_send = cocotb.start_soon( send_contiguous_frame(bench.client_source, frame_beats_from_bytes(client_payload), clk=bench.clk) @@ -90,6 +94,8 @@ async def udp_engine_client_arp_then_transmit_test(dut): async def udp_engine_server_rx_path_test(dut): bench = await setup_udp_top_bench(dut) + # The same top-level wrapper also exposes the inbound server-routing path, + # so inject one server-targeted frame and confirm the UDP header is gone. server_payload = b"udp-top-server-path" server_frame = build_udp_rx_pseudo_frame( remote_mac=LEGACY_MAC_WIRES[1], diff --git a/tests/ethernet/UdpEngine/test_UdpEngineArp.py b/tests/ethernet/UdpEngine/test_UdpEngineArp.py index 504f3888aa..61c067be6d 100644 --- a/tests/ethernet/UdpEngine/test_UdpEngineArp.py +++ b/tests/ethernet/UdpEngine/test_UdpEngineArp.py @@ -26,12 +26,9 @@ from tests.common.regression_utils import run_surf_vhdl_test from tests.ethernet.EthMacCore.ethmac_test_utils import ( - FlatEmacEndpoint, frame_beats_from_bytes, payload_from_beat, - recv_frame, send_contiguous_frame, - setup_flat_emac_testbench, cycle, ) from tests.ethernet.UdpEngine.udp_test_utils import ( @@ -41,43 +38,19 @@ LEGACY_MAC_WIRES, UDP_RTL_SOURCES, ipv4_to_bytes, + setup_udp_arp_bench, ) WRAPPER_PATH = "ethernet/UdpEngine/wrappers/UdpEngineArpFlatWrapper.vhd" -async def setup_udp_arp_bench(dut): - bench = await setup_flat_emac_testbench( - dut, - clk_name="clk", - rst_name="rst", - initial_values={ - "localIp": LEGACY_IP_CFGS[0], - "arpTabFound": 0, - "arpTabMacAddr": 0, - "clientRemoteDetValid": 0, - "clientRemoteDetIp": 0, - "clientRemoteIp": 0, - "arpReqTReady": 0, - "arpAckTValid": 0, - "arpAckTData": 0, - "arpAckTKeep": 0, - "arpAckTLast": 0, - "arpAckSof": 0, - "arpAckEofe": 0, - }, - ) - arp_req_sink = FlatEmacEndpoint(dut, prefix="arpReq") - arp_ack_source = FlatEmacEndpoint(dut, prefix="arpAck") - arp_ack_source.set_idle() - return bench, arp_req_sink, arp_ack_source - - @cocotb.test() async def udp_engine_arp_uses_cached_mac_without_request_test(dut): - bench, _, _ = await setup_udp_arp_bench(dut) + bench = await setup_udp_arp_bench(dut) + # Present a pre-populated lookup result so the helper can publish the + # cached MAC immediately without entering its request state. dut.clientRemoteIp.value = LEGACY_IP_CFGS[1] dut.arpTabFound.value = 1 dut.arpTabMacAddr.value = LEGACY_MAC_CFGS[1] @@ -90,21 +63,25 @@ async def udp_engine_arp_uses_cached_mac_without_request_test(dut): @cocotb.test() async def udp_engine_arp_request_ack_round_trip_test(dut): - bench, arp_req_sink, arp_ack_source = await setup_udp_arp_bench(dut) + bench = await setup_udp_arp_bench(dut) + # Leave the table empty so the helper must emit a request for the remote + # IP instead of short-circuiting to a cached result. dut.clientRemoteIp.value = LEGACY_IP_CFGS[1] await cycle(bench.clk, 6) # A miss should emit an outbound ARP request carrying the configured # remote IP in the low 32 bits. - request_observed = await arp_req_sink.recv( + request_observed = await bench.arp_req_sink.recv( clk=bench.clk, ready_signal=dut.arpReqTReady, ) assert payload_from_beat(request_observed)[:4] == ipv4_to_bytes(LEGACY_IPS[1]) + # Return the learned MAC on the acknowledgement port and let the helper + # update both its output MAC and its table-writeback sideband. arp_ack = frame_beats_from_bytes(LEGACY_MAC_WIRES[1].to_bytes(6, byteorder="big")) - ack_send = cocotb.start_soon(send_contiguous_frame(arp_ack_source, arp_ack, clk=bench.clk)) + ack_send = cocotb.start_soon(send_contiguous_frame(bench.arp_ack_source, arp_ack, clk=bench.clk)) await cycle(bench.clk, 4) await ack_send diff --git a/tests/ethernet/UdpEngine/test_UdpEngineDhcp.py b/tests/ethernet/UdpEngine/test_UdpEngineDhcp.py index 6a84de1671..98dabc73d8 100644 --- a/tests/ethernet/UdpEngine/test_UdpEngineDhcp.py +++ b/tests/ethernet/UdpEngine/test_UdpEngineDhcp.py @@ -25,17 +25,14 @@ from tests.common.regression_utils import run_surf_vhdl_test from tests.ethernet.EthMacCore.ethmac_test_utils import ( - FlatEmacEndpoint, cycle, frame_beats_from_bytes, payload_from_beats, recv_frame, send_contiguous_frame, - setup_flat_emac_testbench, ) from tests.ethernet.UdpEngine.udp_test_utils import ( LEGACY_IPS, - LEGACY_MAC_CFGS, LEGACY_MAC_WIRES, UDP_RTL_SOURCES, build_dhcp_reply_payload, @@ -44,34 +41,21 @@ extract_dhcp_server_identifier, extract_dhcp_xid, ipv4_config_word, + setup_udp_dhcp_bench, ) WRAPPER_PATH = "ethernet/UdpEngine/wrappers/UdpEngineDhcpFlatWrapper.vhd" -async def setup_udp_dhcp_bench(dut): - bench = await setup_flat_emac_testbench( - dut, - clk_name="clk", - rst_name="rst", - source_prefix="sDhcp", - initial_values={ - "localMac": LEGACY_MAC_CFGS[0], - "localIp": 0, - "mDhcpTReady": 0, - }, - ) - assert bench.source is not None - return bench, bench.source, FlatEmacEndpoint(dut, prefix="mDhcp") - - @cocotb.test() async def udp_engine_dhcp_offer_ack_sequence_test(dut): - bench, dhcp_source, dhcp_sink = await setup_udp_dhcp_bench(dut) + bench = await setup_udp_dhcp_bench(dut) + # Let the engine boot through its shortened timeout logic and emit the + # first discover message on the dedicated DHCP stream. discover_observed = await recv_frame( - dhcp_sink, + bench.sink, clk=bench.clk, ready_signal=dut.mDhcpTReady, timeout_cycles=256, @@ -80,6 +64,8 @@ async def udp_engine_dhcp_offer_ack_sequence_test(dut): discover_xid = extract_dhcp_xid(discover_payload) assert extract_dhcp_message_type(discover_payload) == 1 + # A matching offer should move the state machine into the request phase + # while preserving the same DHCP transaction identifier. offer_payload = build_dhcp_reply_payload( message_type=2, xid=discover_xid, @@ -88,10 +74,10 @@ async def udp_engine_dhcp_offer_ack_sequence_test(dut): siaddr=LEGACY_IPS[1], ) offer_send = cocotb.start_soon( - send_contiguous_frame(dhcp_source, frame_beats_from_bytes(offer_payload), clk=bench.clk) + send_contiguous_frame(bench.source, frame_beats_from_bytes(offer_payload), clk=bench.clk) ) request_observed = await recv_frame( - dhcp_sink, + bench.sink, clk=bench.clk, ready_signal=dut.mDhcpTReady, timeout_cycles=256, @@ -103,6 +89,8 @@ async def udp_engine_dhcp_offer_ack_sequence_test(dut): assert extract_dhcp_requested_ip(request_payload) == "192.168.2.44" assert extract_dhcp_server_identifier(request_payload) == LEGACY_IPS[1] + # The ack is the step that should finally publish the leased IP address on + # the wrapper-visible `dhcpIp` output. ack_payload = build_dhcp_reply_payload( message_type=5, xid=request_xid, @@ -111,7 +99,7 @@ async def udp_engine_dhcp_offer_ack_sequence_test(dut): siaddr=LEGACY_IPS[1], ) ack_send = cocotb.start_soon( - send_contiguous_frame(dhcp_source, frame_beats_from_bytes(ack_payload), clk=bench.clk) + send_contiguous_frame(bench.source, frame_beats_from_bytes(ack_payload), clk=bench.clk) ) await ack_send for _ in range(128): diff --git a/tests/ethernet/UdpEngine/test_UdpEngineRx.py b/tests/ethernet/UdpEngine/test_UdpEngineRx.py index 1640efc956..d6ecb579e6 100644 --- a/tests/ethernet/UdpEngine/test_UdpEngineRx.py +++ b/tests/ethernet/UdpEngine/test_UdpEngineRx.py @@ -25,7 +25,6 @@ from tests.common.regression_utils import run_surf_vhdl_test from tests.ethernet.EthMacCore.ethmac_test_utils import ( - cycle, frame_beats_from_bytes, payload_from_beats, recv_frame, @@ -52,6 +51,8 @@ async def udp_engine_rx_routes_server_payload_and_debug_test(dut): bench = await setup_udp_rx_bench(dut) + # Drive one server-destined pseudo-UDP frame into the RX path so the DUT + # has to strip the header and capture the sender debug metadata. server_payload = b"udp-rx-server-path" server_frame = build_udp_rx_pseudo_frame( remote_mac=LEGACY_MAC_WIRES[1], @@ -83,6 +84,8 @@ async def udp_engine_rx_routes_server_payload_and_debug_test(dut): async def udp_engine_rx_routes_client_payload_and_detection_test(dut): bench = await setup_udp_rx_bench(dut) + # The client route uses the same on-wire format but a different local port, + # so this packet should emerge on the client-side output instead. client_payload = b"udp-rx-client-path" client_frame = build_udp_rx_pseudo_frame( remote_mac=LEGACY_MAC_WIRES[1], @@ -111,6 +114,8 @@ async def udp_engine_rx_routes_client_payload_and_detection_test(dut): async def udp_engine_rx_routes_dhcp_socket_test(dut): bench = await setup_udp_rx_bench(dut) + # DHCP is recognized by its dedicated socket tuple even though it rides + # through the shared UDP RX datapath. dhcp_payload = b"udp-rx-dhcp-path" dhcp_frame = build_udp_rx_pseudo_frame( remote_mac=LEGACY_MAC_WIRES[1], diff --git a/tests/ethernet/UdpEngine/test_UdpEngineTx.py b/tests/ethernet/UdpEngine/test_UdpEngineTx.py index f7dbecedb5..539e8b2e24 100644 --- a/tests/ethernet/UdpEngine/test_UdpEngineTx.py +++ b/tests/ethernet/UdpEngine/test_UdpEngineTx.py @@ -49,12 +49,16 @@ async def udp_engine_tx_server_payload_header_test(dut): bench = await setup_udp_tx_bench(dut) + # Wait for the wrapper-visible `linkUp` output before sending traffic so + # the test matches the contract exposed to the integrated top-level logic. await wait_for_link_up(dut.linkUp, clk=bench.clk) payload = b"udp-tx-server-payload" send_task = cocotb.start_soon( send_contiguous_frame(bench.source, frame_beats_from_bytes(payload), clk=bench.clk) ) + # The sink observes the internal pseudo-header stream, so compare against a + # pseudo-header builder rather than a full Ethernet wire image. observed = await recv_frame( bench.sink, clk=bench.clk, @@ -77,6 +81,8 @@ async def udp_engine_tx_server_payload_header_test(dut): async def udp_engine_tx_dhcp_passthrough_test(dut): bench = await setup_udp_tx_bench(dut) + # DHCP bypasses the normal remote-endpoint registers and always targets + # the broadcast client/server socket pair. dhcp_payload = b"dhcp-client-discover" dhcp_send = cocotb.start_soon( send_contiguous_frame(bench.dhcp_source, frame_beats_from_bytes(dhcp_payload), clk=bench.clk) diff --git a/tests/ethernet/UdpEngine/test_UdpEngineWrapper.py b/tests/ethernet/UdpEngine/test_UdpEngineWrapper.py index 3b632de07c..5360bf7736 100644 --- a/tests/ethernet/UdpEngine/test_UdpEngineWrapper.py +++ b/tests/ethernet/UdpEngine/test_UdpEngineWrapper.py @@ -51,6 +51,8 @@ async def udp_engine_wrapper_axil_and_server_path_test(dut): bench = await setup_udp_wrapper_bench(dut) + # Start with the wrapper-local AXI-Lite register bank, since that behavior + # is unique to `UdpEngineWrapper` rather than the underlying UDP core. await axil_write_u32(bench.axil, 0x000, 0x0020) await axil_write_u32(bench.axil, 0x004, ipv4_config_word(LEGACY_IPS[1])) await axil_write_u32(bench.axil, 0xFE4, ipv4_config_word("192.168.2.99")) @@ -60,6 +62,8 @@ async def udp_engine_wrapper_axil_and_server_path_test(dut): assert await axil_read_u32(bench.axil, 0xFE4) == ipv4_config_word("192.168.2.99") assert int(dut.softIp.value) == ipv4_config_word("192.168.2.99") + # Then prove one real inbound server-routing path through the integrated + # MAC/IPv4/UDP stack and check the exported debug readbacks. inbound_frame = build_ipv4_udp_frame( dst_mac=LEGACY_MAC_WIRES[0], src_mac=LEGACY_MAC_WIRES[1], diff --git a/tests/ethernet/UdpEngine/test_UdpEngineWrapperPair.py b/tests/ethernet/UdpEngine/test_UdpEngineWrapperPair.py index 48e3efc69f..f1ef29a4f1 100644 --- a/tests/ethernet/UdpEngine/test_UdpEngineWrapperPair.py +++ b/tests/ethernet/UdpEngine/test_UdpEngineWrapperPair.py @@ -37,23 +37,24 @@ cycle, ) from tests.ethernet.IpV4Engine.ipv4_test_utils import IPV4_RTL_SOURCES -from tests.ethernet.UdpEngine.udp_test_utils import LEGACY_IP_CFGS, UDP_RTL_SOURCES, setup_udp_wrapper_pair_bench +from tests.ethernet.UdpEngine.udp_test_utils import ( + LEGACY_IP_CFGS, + UDP_RTL_SOURCES, + setup_udp_wrapper_pair_bench, + wait_for_pair_arp_resolution, +) WRAPPER_PATH = "ethernet/UdpEngine/wrappers/UdpEngineWrapperPairFlatWrapper.vhd" -async def wait_for_pair_arp_resolution(dut, *, clk, cycles: int = 256) -> None: - # The client wrapper needs time to emit an ARP request, receive the server - # response through the selected link, and update its internal ARP table. - await cycle(clk, cycles) - - @cocotb.test() async def udp_engine_wrapper_pair_matches_legacy_route_switching_test(dut): bench = await setup_udp_wrapper_pair_bench(dut) - await wait_for_pair_arp_resolution(dut, clk=bench.clk) + # The legacy bench learns server 0 first, so leave time for the client + # wrapper to emit and resolve its initial ARP transaction. + await wait_for_pair_arp_resolution(clk=bench.clk) payload0 = b"legacy-path-server0" send0 = cocotb.start_soon( send_contiguous_frame(bench.client_source, frame_beats_from_bytes(payload0), clk=bench.clk) @@ -71,9 +72,11 @@ async def udp_engine_wrapper_pair_matches_legacy_route_switching_test(dut): await with_timeout(send0, 10, "us") assert payload_from_beats(observed0) == payload0 + # Now retarget the remote IP and the selected physical link so the second + # transfer follows server 1, matching the route switch in `UdpEngineTb`. dut.clientRemoteIp.value = LEGACY_IP_CFGS[2] dut.selectedServer.value = 2 - await wait_for_pair_arp_resolution(dut, clk=bench.clk) + await wait_for_pair_arp_resolution(clk=bench.clk) payload1 = b"legacy-path-server1" send1 = cocotb.start_soon( send_contiguous_frame(bench.client_source, frame_beats_from_bytes(payload1), clk=bench.clk) @@ -91,6 +94,8 @@ async def udp_engine_wrapper_pair_matches_legacy_route_switching_test(dut): await with_timeout(send1, 10, "us") assert payload_from_beats(observed1) == payload1 + # Finally switch only the physical link back to server 0 and use `tDest=1` + # so the client reuses its cached indexed ARP entry from the first route. dut.selectedServer.value = 1 await cycle(bench.clk, 8) payload2 = b"legacy-indexed-server0" diff --git a/tests/ethernet/UdpEngine/udp_test_utils.py b/tests/ethernet/UdpEngine/udp_test_utils.py index 8bfeabba84..ef1083a3bd 100644 --- a/tests/ethernet/UdpEngine/udp_test_utils.py +++ b/tests/ethernet/UdpEngine/udp_test_utils.py @@ -104,6 +104,25 @@ class UdpWrapperPairBench: server_sinks: list[FlatEmacEndpoint] +@dataclass +class UdpArpBench: + clk: object + arp_req_sink: FlatEmacEndpoint + arp_ack_source: FlatEmacEndpoint + + +@dataclass +class UdpDhcpBench: + clk: object + source: FlatEmacEndpoint + sink: FlatEmacEndpoint + + +@dataclass +class ArpIpTableBench: + clk: object + + def ipv4_to_bytes(address: str) -> bytes: return ipaddress.IPv4Address(address).packed @@ -272,6 +291,8 @@ async def axil_write_u48(master, address: int, value: int) -> None: async def wait_for_link_up(signal, *, clk, timeout_cycles: int = 64) -> None: + # The TX wrapper only becomes usable once the remote endpoint information + # has propagated through the DUT and `linkUp` rises. for _ in range(timeout_cycles): await Timer(1, unit="ns") if int(signal.value) != 0: @@ -280,6 +301,91 @@ async def wait_for_link_up(signal, *, clk, timeout_cycles: int = 64) -> None: raise AssertionError("Timed out waiting for link-up") +async def pulse_signal(signal, *, clk, idle_cycles: int = 1) -> None: + # Several UdpEngine leaves use one-cycle write enables or acknowledge + # strobes. Model those as clean pulses instead of open-coded toggles. + signal.value = 1 + await cycle(clk, 1) + signal.value = 0 + await cycle(clk, idle_cycles) + + +async def wait_for_pair_arp_resolution(*, clk, cycles: int = 256) -> None: + # The legacy wrapper-pair bench relies on genuine ARP learning through the + # integrated client/server stack, so leave time for request/response + # traffic to settle before launching the next client payload. + await cycle(clk, cycles) + + +async def setup_arp_ip_table_bench(dut) -> ArpIpTableBench: + bench = await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + initial_values={ + "ipAddrIn": 0, + "pos": 0, + "clientRemoteDetIp": 0, + "clientRemoteDetValid": 0, + "ipWrEn": 0, + "ipWrAddr": 0, + "macWrEn": 0, + "macWrAddr": 0, + }, + ) + return ArpIpTableBench(clk=bench.clk) + + +async def setup_udp_arp_bench(dut) -> UdpArpBench: + bench = await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + initial_values={ + "localIp": LEGACY_IP_CFGS[0], + "arpTabFound": 0, + "arpTabMacAddr": 0, + "clientRemoteDetValid": 0, + "clientRemoteDetIp": 0, + "clientRemoteIp": 0, + "arpReqTReady": 0, + "arpAckTValid": 0, + "arpAckTData": 0, + "arpAckTKeep": 0, + "arpAckTLast": 0, + "arpAckSof": 0, + "arpAckEofe": 0, + }, + ) + arp_ack_source = FlatEmacEndpoint(dut, prefix="arpAck") + arp_ack_source.set_idle() + return UdpArpBench( + clk=bench.clk, + arp_req_sink=FlatEmacEndpoint(dut, prefix="arpReq"), + arp_ack_source=arp_ack_source, + ) + + +async def setup_udp_dhcp_bench(dut) -> UdpDhcpBench: + bench = await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + source_prefix="sDhcp", + initial_values={ + "localMac": LEGACY_MAC_CFGS[0], + "localIp": 0, + "mDhcpTReady": 0, + }, + ) + assert bench.source is not None + return UdpDhcpBench( + clk=bench.clk, + source=bench.source, + sink=FlatEmacEndpoint(dut, prefix="mDhcp"), + ) + + async def setup_udp_rx_bench(dut) -> UdpRxBench: bench = await setup_flat_emac_testbench( dut, From 293e59ec72f3e929393ecc87bd3f42313fe1f693 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 17 Apr 2026 13:13:36 -0700 Subject: [PATCH 15/92] Remove TB test clone. Not a proper regression target. --- docs/_meta/rtl_regression_handoff.md | 2 +- docs/_meta/rtl_regression_progress.md | 5 +- .../UdpEngineWrapperPairFlatWrapper.vhd | 299 ------------------ .../UdpEngine/test_UdpEngineWrapperPair.py | 133 -------- tests/ethernet/UdpEngine/udp_test_utils.py | 35 -- 5 files changed, 3 insertions(+), 471 deletions(-) delete mode 100644 ethernet/UdpEngine/wrappers/UdpEngineWrapperPairFlatWrapper.vhd delete mode 100644 tests/ethernet/UdpEngine/test_UdpEngineWrapperPair.py diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index 70ba999b27..c8e96ac83f 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -92,7 +92,7 @@ The first manual `ethernet/EthMacCore` wave is now also in place. The checked-in `ethernet/RawEthFramer/` now also has checked-in regression coverage under `tests/ethernet/RawEthFramer/`. The earlier top-level `RawEthFramer` wrapper bench is joined by direct leaf benches for `RawEthFramerRx` and `RawEthFramerTx`, plus a `RawEthFramerPair` integration bench whose wrapper cross-connects two `RawEthFramer` instances to mirror the legacy `ethernet/RawEthFramer/tb/RawEthFramerTb.vhd` topology. The validated RX leaf bench covers lookup-gated unicast decode, short-frame trim behavior, broadcast bypass, and representative reject cases. The validated TX leaf bench currently keeps a narrower first-pass subset: lookup-request exposure before forwarding, broadcast bypass with the observed padded wire image, and zero-MAC lookup-miss drop. Do not over-claim the broader multi-beat unicast completion path for `RawEthFramerTx`; that branch still needs follow-up before it should be considered a passing leaf-level contract. -`ethernet/UdpEngine/` now has checked-in regression coverage under `tests/ethernet/UdpEngine/` as well. The current validated set covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, all backed by checked-in wrappers under `ethernet/UdpEngine/wrappers/` and the shared helper layer in `tests/ethernet/UdpEngine/udp_test_utils.py`. The legacy `ethernet/UdpEngine/tb/UdpEngineTb.vhd` route-switching topology is also represented by `test_UdpEngineWrapperPair.py` plus a MAC-backed `UdpEngineWrapperPairFlatWrapper.vhd`, but that integrated pair bench has not yet been closed with a local passing run because the full four-MAC simulation is materially heavier than the rest of the slice. Treat the pair bench as implemented parity coverage that still needs dedicated validation time, not as a validated passing result. +`ethernet/UdpEngine/` now has checked-in regression coverage under `tests/ethernet/UdpEngine/` as well. The current validated set covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, all backed by checked-in wrappers under `ethernet/UdpEngine/wrappers/` and the shared helper layer in `tests/ethernet/UdpEngine/udp_test_utils.py`. The wrapper coverage policy is now more explicit in practice: test the wrapper-specific behavior, not the full leaf matrix again. `Fifo` validated both inferred sync/async selection branches, `FifoCascade` validated public stage-vector mapping plus a curated output smoke, and `FifoMux` is currently validated only on the stable split-to-narrow path. The pack-to-wide `FifoMux` path should be treated as still open rather than silently assumed covered. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index bb34d6b258..4dbaa9e829 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -20,7 +20,7 @@ - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. - - For `ethernet`, keep using the checked-in wrappers under `ethernet/*/wrappers/` plus the shared helper layers in `tests/ethernet/EthMacCore/ethmac_test_utils.py`, `tests/ethernet/RawEthFramer/raw_eth_test_utils.py`, and `tests/ethernet/UdpEngine/udp_test_utils.py`. The practical first-pass shape is flat EMAC/app beat wrappers with explicit sideband bits, curated functional slices instead of exhaustive generic sweeps, and dedicated pair/integration wrappers only where an old VHDL bench contributes a topology worth preserving. The new `UdpEngineWrapperPair` legacy-topology bench is implemented on that pattern, but it still needs a longer dedicated local run before it should be treated as a validated parity result. + - For `ethernet`, keep using the checked-in wrappers under `ethernet/*/wrappers/` plus the shared helper layers in `tests/ethernet/EthMacCore/ethmac_test_utils.py`, `tests/ethernet/RawEthFramer/raw_eth_test_utils.py`, and `tests/ethernet/UdpEngine/udp_test_utils.py`. The practical first-pass shape is flat EMAC/app beat wrappers with explicit sideband bits, curated functional slices instead of exhaustive generic sweeps, and dedicated pair/integration wrappers only where an old VHDL bench contributes a topology worth preserving. ## Status | Subsystem | Inventory | Smoke | Functional | Notes | @@ -30,7 +30,7 @@ | `dsp` | started | not started | started | The planned `dsp/generic/fixed` leaf batch is now validated under `tests/dsp/generic/`: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. Shared DSP helpers now live in `tests/dsp/generic/dsp_test_utils.py`, and the legacy VHDL benches under `dsp/generic/tb/` were treated as behavioral reference material rather than as execution constraints. | | `axi` | started | not started | started | The axi-first pass is now complete for the simulator-friendly queue. The final locally validated batch adds `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`, with a combined `11 passed` validation run on 2026-03-27. Added checked-in subsystem wrappers under `axi/axi4/ip_integrator/`, `axi/axi-lite/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/` for those benches. `AxiStreamFifoV2` now has an expanded `10 passed` wrapper regression under `tests/axi/axi_stream/` covering async and sync width conversion, metadata truncation, `VALID_THOLD` frame-ready and burst-release modes, dynamic pause-threshold behavior, `CASCADE_SIZE=2`, and the `S_HAS_TREADY=0` pause-only source-side path. `AxiResize` now passes its equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` wrapper regression on this branch after the read-hold RTL fix. `AxiLiteAsync`, `AxiLiteToDrp`, and `AxiRateGen` still keep intentionally narrow common-clock subsets while the more timing-sensitive async AXI-Lite crossing branches remain open. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` still keep intentionally narrow first-pass subsets. `AxiStreamDmaV2Read` is now validated with a two-case wrapper regression covering both aligned and short terminal-beat reads after fixing bounded byte-count conversion in `AxiPkg` and terminal-mask generation in `AxiStreamDmaV2Read`. | | `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. | -| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` covers the first manual `EthMacCore` slice, `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, and `tests/ethernet/UdpEngine/` now adds checked-in benches for `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper` backed by shared helpers in `tests/ethernet/UdpEngine/udp_test_utils.py` plus checked-in wrappers under `ethernet/UdpEngine/wrappers/`. The new `UdpEngineWrapperPair` bench and MAC-backed parity wrapper also exist to preserve the legacy `ethernet/UdpEngine/tb/UdpEngineTb.vhd` route-switching topology, but that integrated pair bench still needs a longer dedicated local validation run before it should be counted as a passing result. The RawEthFramer TX leaf and UdpEngine wrapper-pair parity paths therefore remain the two explicit Ethernet caveats inside an otherwise working manual subsystem wave. The generated queue still keeps the broader subsystem deferred until the post-axi refresh removes the temporary queue override. | +| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` covers the first manual `EthMacCore` slice, `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, and `tests/ethernet/UdpEngine/` now adds checked-in benches for `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper` backed by shared helpers in `tests/ethernet/UdpEngine/udp_test_utils.py` plus checked-in wrappers under `ethernet/UdpEngine/wrappers/`. The RawEthFramer TX leaf remains the explicit Ethernet caveat inside an otherwise working manual subsystem wave. The generated queue still keeps the broader subsystem deferred until the post-axi refresh removes the temporary queue override. | | `devices` | not started | not started | not started | Many vendor-heavy cases | | `xilinx` | not started | not started | not started | Many vendor-heavy cases | @@ -251,7 +251,6 @@ - 2026-04-10: Landed the first manual `ethernet/EthMacCore` bench wave under `tests/ethernet/EthMacCore/`, added the required checked-in wrappers under `ethernet/EthMacCore/wrappers/`, and validated the baseline 12-module slice covering `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`. - 2026-04-10: Expanded that same `EthMacCore` slice beyond the initial happy paths. The checked-in Ethernet MAC suite now covers `EthMacTop` filter/backpressure/checksum/pause interactions, GMII and XGMII import/export plus link-not-ready recovery behavior, checksum negative cases, filter multicast/broadcast/filter-disable/multi-beat-drop behavior, shift runtime-control and control-bit propagation edges, and full byte-width `1..16` logic-path coverage for `EthCrc32Parallel`. The full `tests/ethernet/EthMacCore` directory currently passes locally with `32 passed`. - 2026-04-17: Added the manual `ethernet/UdpEngine` wave under `tests/ethernet/UdpEngine/`. The checked-in helper layer now lives in `tests/ethernet/UdpEngine/udp_test_utils.py`, the new checked-in wrappers live under `ethernet/UdpEngine/wrappers/`, and the locally validated benches cover `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`. The current local validation command `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/UdpEngine/test_ArpIpTable.py tests/ethernet/UdpEngine/test_UdpEngineArp.py tests/ethernet/UdpEngine/test_UdpEngineDhcp.py tests/ethernet/UdpEngine/test_UdpEngineRx.py tests/ethernet/UdpEngine/test_UdpEngineTx.py tests/ethernet/UdpEngine/test_UdpEngine.py tests/ethernet/UdpEngine/test_UdpEngineWrapper.py` passes with `7 passed`. -- 2026-04-17: Added the legacy-topology parity bench for `ethernet/UdpEngine/tb/UdpEngineTb.vhd` as `tests/ethernet/UdpEngine/test_UdpEngineWrapperPair.py` backed by `ethernet/UdpEngine/wrappers/UdpEngineWrapperPairFlatWrapper.vhd`. That wrapper now includes the real `EthMacTop`/XGMII switch fabric instead of a simplified direct stream cross-couple so the preserved route-switching case matches the legacy bench architecture. The pair bench is implemented and lint-clean, but it still needs a longer dedicated local validation run before it should be counted as a passing result. - 2026-04-16: Merged the current `pre-release` branch into `verification-2`, so this branch line now contains the already-landed SSI and PGP waves from PR #1391 and PR #1392 in addition to the manual Ethernet slice. - 2026-04-16: Refreshed the planning docs to move the active frontier from “continue Ethernet next” to “refresh the stale queue/override inputs, then resume from the real merged-branch frontier.” - 2026-03-20: Added an explicit project rule to comment new Python regression code where intent or runner behavior is not self-evident. diff --git a/ethernet/UdpEngine/wrappers/UdpEngineWrapperPairFlatWrapper.vhd b/ethernet/UdpEngine/wrappers/UdpEngineWrapperPairFlatWrapper.vhd deleted file mode 100644 index 1c638d2bca..0000000000 --- a/ethernet/UdpEngine/wrappers/UdpEngineWrapperPairFlatWrapper.vhd +++ /dev/null @@ -1,299 +0,0 @@ -------------------------------------------------------------------------------- --- Company : SLAC National Accelerator Laboratory -------------------------------------------------------------------------------- --- Description: Legacy-parity cocotb wrapper for a client/server UdpEngine set -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library surf; -use surf.StdRtlPkg.all; -use surf.AxiStreamPkg.all; -use surf.EthMacPkg.all; - -entity UdpEngineWrapperPairFlatWrapper is - generic ( - TPD_G : time := 1 ns; - RST_POLARITY_G : sl := '1'; - RST_ASYNC_G : boolean := false; - CLK_FREQ_G : real := 4.0; - COMM_TIMEOUT_G : positive := 6); - port ( - clk : in sl; - rst : in sl; - clientLocalMac : in slv(47 downto 0); - clientLocalIp : in slv(31 downto 0); - clientRemotePort : in slv(15 downto 0); - clientRemoteIp : in slv(31 downto 0); - selectedServer : in slv(1 downto 0); - sClientTValid : in sl; - sClientTData : in slv(127 downto 0); - sClientTKeep : in slv(15 downto 0); - sClientTLast : in sl; - sClientTReady : out sl; - sClientTDest : in slv(7 downto 0); - sClientSof : in sl; - sClientEofe : in sl; - mServer0TValid : out sl; - mServer0TData : out slv(127 downto 0); - mServer0TKeep : out slv(15 downto 0); - mServer0TLast : out sl; - mServer0TReady : in sl := '1'; - mServer0TDest : out slv(7 downto 0); - mServer0Sof : out sl; - mServer0Eofe : out sl; - mServer1TValid : out sl; - mServer1TData : out slv(127 downto 0); - mServer1TKeep : out slv(15 downto 0); - mServer1TLast : out sl; - mServer1TReady : in sl := '1'; - mServer1TDest : out slv(7 downto 0); - mServer1Sof : out sl; - mServer1Eofe : out sl; - mServer2TValid : out sl; - mServer2TData : out slv(127 downto 0); - mServer2TKeep : out slv(15 downto 0); - mServer2TLast : out sl; - mServer2TReady : in sl := '1'; - mServer2TDest : out slv(7 downto 0); - mServer2Sof : out sl; - mServer2Eofe : out sl); -end entity UdpEngineWrapperPairFlatWrapper; - -architecture rtl of UdpEngineWrapperPairFlatWrapper is - - constant SERVER_MACS_C : Slv48Array(2 downto 0) := ( - 0 => x"020300564400", - 1 => x"030300564400", - 2 => x"040300564400"); - constant SERVER_IPS_C : Slv32Array(2 downto 0) := ( - 0 => x"0B02A8C0", - 1 => x"0C02A8C0", - 2 => x"0D02A8C0"); - constant PHY_D_IDLE_C : slv(63 downto 0) := x"0707070707070707"; - constant PHY_C_IDLE_C : slv(7 downto 0) := x"FF"; - - signal obMacMasters : AxiStreamMasterArray(3 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal obMacSlaves : AxiStreamSlaveArray(3 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal ibMacMasters : AxiStreamMasterArray(3 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal ibMacSlaves : AxiStreamSlaveArray(3 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal sClientMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal sClientSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal mServerMasters : AxiStreamMasterArray(2 downto 0); - signal mServerSlaves : AxiStreamSlaveArray(2 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal ethConfig : EthMacConfigArray(3 downto 0) := (others => ETH_MAC_CONFIG_INIT_C); - signal phyD : Slv64Array(3 downto 0) := (others => (others => '0')); - signal phyC : Slv8Array(3 downto 0) := (others => (others => '0')); - signal phyDSelected : slv(63 downto 0) := PHY_D_IDLE_C; - signal phyCSelected : slv(7 downto 0) := PHY_C_IDLE_C; - signal phyReady : sl; - -begin - - sClientComb : process (sClientEofe, sClientSof, sClientTData, sClientTDest, sClientTKeep, sClientTLast, sClientTValid) is - variable v : AxiStreamMasterType; - begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sClientTValid; - v.tData(127 downto 0) := sClientTData; - v.tKeep(15 downto 0) := sClientTKeep; - v.tLast := sClientTLast; - v.tDest(7 downto 0) := sClientTDest; - axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sClientSof, 0); - axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sClientEofe); - sClientMasters(0) <= v; - end process sClientComb; - - mServer0View : process (mServerMasters(0)) is - begin - mServer0TValid <= mServerMasters(0).tValid; - mServer0TData <= mServerMasters(0).tData(127 downto 0); - mServer0TKeep <= mServerMasters(0).tKeep(15 downto 0); - mServer0TLast <= mServerMasters(0).tLast; - mServer0TDest <= mServerMasters(0).tDest(7 downto 0); - mServer0Sof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_SOF_BIT_C, 0); - mServer0Eofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_EOFE_BIT_C); - end process mServer0View; - - mServer1View : process (mServerMasters(1)) is - begin - mServer1TValid <= mServerMasters(1).tValid; - mServer1TData <= mServerMasters(1).tData(127 downto 0); - mServer1TKeep <= mServerMasters(1).tKeep(15 downto 0); - mServer1TLast <= mServerMasters(1).tLast; - mServer1TDest <= mServerMasters(1).tDest(7 downto 0); - mServer1Sof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(1), EMAC_SOF_BIT_C, 0); - mServer1Eofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(1), EMAC_EOFE_BIT_C); - end process mServer1View; - - mServer2View : process (mServerMasters(2)) is - begin - mServer2TValid <= mServerMasters(2).tValid; - mServer2TData <= mServerMasters(2).tData(127 downto 0); - mServer2TKeep <= mServerMasters(2).tKeep(15 downto 0); - mServer2TLast <= mServerMasters(2).tLast; - mServer2TDest <= mServerMasters(2).tDest(7 downto 0); - mServer2Sof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(2), EMAC_SOF_BIT_C, 0); - mServer2Eofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(2), EMAC_EOFE_BIT_C); - end process mServer2View; - - sClientTReady <= sClientSlaves(0).tReady; - mServerSlaves(0).tReady <= mServer0TReady; - mServerSlaves(1).tReady <= mServer1TReady; - mServerSlaves(2).tReady <= mServer2TReady; - phyReady <= not rst; - - --------------------------------------------------------------------------- - -- Match the legacy XGMII PHY multiplexer from UdpEngineTb. - --------------------------------------------------------------------------- - process (phyC, phyD, selectedServer) is - variable index : natural range 0 to 3; - begin - phyDSelected <= PHY_D_IDLE_C; - phyCSelected <= PHY_C_IDLE_C; - index := to_integer(unsigned(selectedServer)); - if (index >= 1) and (index <= 3) then - phyDSelected <= phyD(index); - phyCSelected <= phyC(index); - end if; - end process; - ethConfig(0).macAddress <= clientLocalMac; - ethConfig(1).macAddress <= SERVER_MACS_C(0); - ethConfig(2).macAddress <= SERVER_MACS_C(1); - ethConfig(3).macAddress <= SERVER_MACS_C(2); - - U_Client : entity surf.UdpEngineWrapper - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - RST_ASYNC_G => RST_ASYNC_G, - SERVER_EN_G => false, - CLIENT_EN_G => true, - CLIENT_SIZE_G => 1, - CLIENT_PORTS_G => (0 => 8193), - CLIENT_EXT_CONFIG_G => true, - TX_FLOW_CTRL_G => true, - DHCP_G => false, - IGMP_G => false, - IGMP_GRP_SIZE => 1, - CLK_FREQ_G => CLK_FREQ_G, - COMM_TIMEOUT_G => COMM_TIMEOUT_G) - port map ( - localMac => clientLocalMac, - localIp => clientLocalIp, - softMac => open, - softIp => open, - clientRemotePort(0) => clientRemotePort, - clientRemoteIp(0) => clientRemoteIp, - obMacMaster => obMacMasters(0), - obMacSlave => obMacSlaves(0), - ibMacMaster => ibMacMasters(0), - ibMacSlave => ibMacSlaves(0), - obServerMasters => open, - obServerSlaves => (others => AXI_STREAM_SLAVE_FORCE_C), - ibServerMasters => (others => AXI_STREAM_MASTER_INIT_C), - ibServerSlaves => open, - obClientMasters => open, - obClientSlaves => (others => AXI_STREAM_SLAVE_FORCE_C), - ibClientMasters => sClientMasters, - ibClientSlaves => sClientSlaves, - clk => clk, - rst => rst); - - U_ClientMac : entity surf.EthMacTop - generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => "XGMII", - PRIM_CONFIG_G => EMAC_AXIS_CONFIG_C) - port map ( - primClk => clk, - primRst => rst, - ibMacPrimMaster => ibMacMasters(0), - ibMacPrimSlave => ibMacSlaves(0), - obMacPrimMaster => obMacMasters(0), - obMacPrimSlave => obMacSlaves(0), - ethClk => clk, - ethRst => rst, - ethConfig => ethConfig(0), - phyReady => phyReady, - xgmiiTxd => phyD(0), - xgmiiTxc => phyC(0), - xgmiiRxd => phyDSelected, - xgmiiRxc => phyCSelected); - - GEN_SERVERS : for i in 0 to 2 generate - signal obServerMasters : AxiStreamMasterArray(0 downto 0); - signal obServerSlaves : AxiStreamSlaveArray(0 downto 0); - begin - obServerSlaves(0) <= mServerSlaves(i); - mServerMasters(i) <= obServerMasters(0); - - U_Server : entity surf.UdpEngineWrapper - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - RST_ASYNC_G => RST_ASYNC_G, - SERVER_EN_G => true, - SERVER_SIZE_G => 1, - SERVER_PORTS_G => (0 => 8192), - CLIENT_EN_G => false, - CLIENT_EXT_CONFIG_G => false, - TX_FLOW_CTRL_G => true, - DHCP_G => false, - IGMP_G => false, - IGMP_GRP_SIZE => 1, - CLK_FREQ_G => CLK_FREQ_G, - COMM_TIMEOUT_G => COMM_TIMEOUT_G) - port map ( - localMac => SERVER_MACS_C(i), - localIp => SERVER_IPS_C(i), - softMac => open, - softIp => open, - obMacMaster => obMacMasters(i+1), - obMacSlave => obMacSlaves(i+1), - ibMacMaster => ibMacMasters(i+1), - ibMacSlave => ibMacSlaves(i+1), - obServerMasters => obServerMasters, - obServerSlaves => obServerSlaves, - ibServerMasters => (others => AXI_STREAM_MASTER_INIT_C), - ibServerSlaves => open, - obClientMasters => open, - obClientSlaves => (others => AXI_STREAM_SLAVE_FORCE_C), - ibClientMasters => (others => AXI_STREAM_MASTER_INIT_C), - ibClientSlaves => open, - clk => clk, - rst => rst); - - U_ServerMac : entity surf.EthMacTop - generic map ( - TPD_G => TPD_G, - PHY_TYPE_G => "XGMII", - PRIM_CONFIG_G => EMAC_AXIS_CONFIG_C) - port map ( - primClk => clk, - primRst => rst, - ibMacPrimMaster => ibMacMasters(i+1), - ibMacPrimSlave => ibMacSlaves(i+1), - obMacPrimMaster => obMacMasters(i+1), - obMacPrimSlave => obMacSlaves(i+1), - ethClk => clk, - ethRst => rst, - ethConfig => ethConfig(i+1), - phyReady => phyReady, - xgmiiTxd => phyD(i+1), - xgmiiTxc => phyC(i+1), - xgmiiRxd => phyD(0), - xgmiiRxc => phyC(0)); - end generate GEN_SERVERS; - -end architecture rtl; diff --git a/tests/ethernet/UdpEngine/test_UdpEngineWrapperPair.py b/tests/ethernet/UdpEngine/test_UdpEngineWrapperPair.py deleted file mode 100644 index f1ef29a4f1..0000000000 --- a/tests/ethernet/UdpEngine/test_UdpEngineWrapperPair.py +++ /dev/null @@ -1,133 +0,0 @@ -############################################################################## -## This file is part of 'SLAC Firmware Standard Library'. -## It is subject to the license terms in the LICENSE.txt file found in the -## top-level directory of this distribution and at: -## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -## No part of 'SLAC Firmware Standard Library', including this file, -## may be copied, modified, propagated, or distributed except according to -## the terms contained in the LICENSE.txt file. -############################################################################## - -# Test methodology: -# - Sweep: Recreate the legacy `UdpEngineTb` topology with one client wrapper -# talking to three server wrappers through a selectable link. -# - Stimulus: Send client traffic after learning server 0, switch the remote IP -# and physical link to learn server 1, then send a third packet with `tDest` -# selecting the cached server-0 ARP entry while server 1 remains configured. -# - Checks: The first packet must arrive at server 0, the second at server 1, -# and the indexed-route packet must return to server 0 just like the legacy -# bench's post-switch `tDest <= x"01"` case. -# - Timing: The test waits for the integrated wrappers to resolve ARP through -# their real MAC-side cross-link before launching each UDP payload. - -from __future__ import annotations - -import cocotb -import pytest -from cocotb.triggers import with_timeout - -from tests.common.regression_utils import run_surf_vhdl_test -from tests.ethernet.EthMacCore.ethmac_test_utils import ( - ETHMAC_RTL_SOURCES, - ROCE_ANALYSIS_SOURCES, - frame_beats_from_bytes, - payload_from_beats, - recv_frame, - send_contiguous_frame, - cycle, -) -from tests.ethernet.IpV4Engine.ipv4_test_utils import IPV4_RTL_SOURCES -from tests.ethernet.UdpEngine.udp_test_utils import ( - LEGACY_IP_CFGS, - UDP_RTL_SOURCES, - setup_udp_wrapper_pair_bench, - wait_for_pair_arp_resolution, -) - - -WRAPPER_PATH = "ethernet/UdpEngine/wrappers/UdpEngineWrapperPairFlatWrapper.vhd" - - -@cocotb.test() -async def udp_engine_wrapper_pair_matches_legacy_route_switching_test(dut): - bench = await setup_udp_wrapper_pair_bench(dut) - - # The legacy bench learns server 0 first, so leave time for the client - # wrapper to emit and resolve its initial ARP transaction. - await wait_for_pair_arp_resolution(clk=bench.clk) - payload0 = b"legacy-path-server0" - send0 = cocotb.start_soon( - send_contiguous_frame(bench.client_source, frame_beats_from_bytes(payload0), clk=bench.clk) - ) - observed0 = await with_timeout( - recv_frame( - bench.server_sinks[0], - clk=bench.clk, - ready_signal=dut.mServer0TReady, - timeout_cycles=1024, - ), - 10, - "us", - ) - await with_timeout(send0, 10, "us") - assert payload_from_beats(observed0) == payload0 - - # Now retarget the remote IP and the selected physical link so the second - # transfer follows server 1, matching the route switch in `UdpEngineTb`. - dut.clientRemoteIp.value = LEGACY_IP_CFGS[2] - dut.selectedServer.value = 2 - await wait_for_pair_arp_resolution(clk=bench.clk) - payload1 = b"legacy-path-server1" - send1 = cocotb.start_soon( - send_contiguous_frame(bench.client_source, frame_beats_from_bytes(payload1), clk=bench.clk) - ) - observed1 = await with_timeout( - recv_frame( - bench.server_sinks[1], - clk=bench.clk, - ready_signal=dut.mServer1TReady, - timeout_cycles=1024, - ), - 10, - "us", - ) - await with_timeout(send1, 10, "us") - assert payload_from_beats(observed1) == payload1 - - # Finally switch only the physical link back to server 0 and use `tDest=1` - # so the client reuses its cached indexed ARP entry from the first route. - dut.selectedServer.value = 1 - await cycle(bench.clk, 8) - payload2 = b"legacy-indexed-server0" - send2 = cocotb.start_soon( - send_contiguous_frame( - bench.client_source, - frame_beats_from_bytes(payload2, dest=1), - clk=bench.clk, - ) - ) - observed2 = await with_timeout( - recv_frame( - bench.server_sinks[0], - clk=bench.clk, - ready_signal=dut.mServer0TReady, - timeout_cycles=1024, - ), - 10, - "us", - ) - await with_timeout(send2, 10, "us") - assert payload_from_beats(observed2) == payload2 - - -@pytest.mark.parametrize("parameters", [pytest.param({}, id="udp_engine_wrapper_pair_flat_wrapper")]) -def test_UdpEngineWrapperPair(parameters): - run_surf_vhdl_test( - test_file=__file__, - toplevel="surf.udpenginewrapperpairflatwrapper", - parameters=parameters, - extra_env=parameters, - extra_vhdl_sources={ - "surf": ETHMAC_RTL_SOURCES + ROCE_ANALYSIS_SOURCES + IPV4_RTL_SOURCES + UDP_RTL_SOURCES + [WRAPPER_PATH] - }, - ) diff --git a/tests/ethernet/UdpEngine/udp_test_utils.py b/tests/ethernet/UdpEngine/udp_test_utils.py index ef1083a3bd..66f32c4504 100644 --- a/tests/ethernet/UdpEngine/udp_test_utils.py +++ b/tests/ethernet/UdpEngine/udp_test_utils.py @@ -97,13 +97,6 @@ class UdpWrapperBench: client_sink: FlatEmacEndpoint -@dataclass -class UdpWrapperPairBench: - clk: object - client_source: FlatEmacEndpoint - server_sinks: list[FlatEmacEndpoint] - - @dataclass class UdpArpBench: clk: object @@ -310,13 +303,6 @@ async def pulse_signal(signal, *, clk, idle_cycles: int = 1) -> None: await cycle(clk, idle_cycles) -async def wait_for_pair_arp_resolution(*, clk, cycles: int = 256) -> None: - # The legacy wrapper-pair bench relies on genuine ARP learning through the - # integrated client/server stack, so leave time for request/response - # traffic to settle before launching the next client payload. - await cycle(clk, cycles) - - async def setup_arp_ip_table_bench(dut) -> ArpIpTableBench: bench = await setup_flat_emac_testbench( dut, @@ -528,24 +514,3 @@ async def setup_udp_wrapper_bench(dut) -> UdpWrapperBench: client_sink=FlatEmacEndpoint(dut, prefix="mClient"), ) - -async def setup_udp_wrapper_pair_bench(dut) -> UdpWrapperPairBench: - bench = await setup_flat_emac_testbench( - dut, - clk_name="clk", - rst_name="rst", - initial_values={ - "clientLocalMac": LEGACY_MAC_CFGS[0], - "clientLocalIp": LEGACY_IP_CFGS[0], - "clientRemotePort": 0x0020, - "clientRemoteIp": LEGACY_IP_CFGS[1], - "selectedServer": 1, - "mServer0TReady": 0, - "mServer1TReady": 0, - "mServer2TReady": 0, - }, - ) - client_source = FlatEmacEndpoint(dut, prefix="sClient") - client_source.set_idle() - server_sinks = [FlatEmacEndpoint(dut, prefix=f"mServer{index}") for index in range(3)] - return UdpWrapperPairBench(clk=bench.clk, client_source=client_source, server_sinks=server_sinks) From 42aea171077bd95f2303ced05d2b6ee76a761f70 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 17 Apr 2026 13:24:15 -0700 Subject: [PATCH 16/92] Update planning docs. --- docs/_meta/rtl_regression_handoff.md | 36 ++++++++++++++------------- docs/_meta/rtl_regression_plan.md | 26 +++++++++---------- docs/_meta/rtl_regression_progress.md | 32 +++++++++++++----------- 3 files changed, 48 insertions(+), 46 deletions(-) diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index c8e96ac83f..976cae48b4 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -18,24 +18,23 @@ - Treat VHDL packages as transitively covered unless a behavioral function/procedure needs a dedicated wrapper ## Quick Resume Snapshot -- Current frontier: the axi-first pass is complete, the merged branch line now includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, and the manual Ethernet slice now spans `EthMacCore`, `RawEthFramer`, and `UdpEngine`. The immediate planning gap is still that `docs/_meta/rtl_phase1_queue_overrides.json` carries the old temporary `ethernet` / `protocols` deferrals, so the checked-in queue artifacts remain behind the real branch frontier. +- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, and the current Ethernet coverage now spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, and `IpV4Engine`. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. - Current axi frontier: complete for the intended simulator-friendly pass in this branch snapshot; do not resume from the older stale `AxiResize` note. - Current validated-open issues: - - None currently recorded on this merged branch. `AxiResize` and `AxiStreamDmaV2Read` are both fixed here; queue/override refresh is the next step. -- Current queue discipline: - - Keep `dsp/` in the generated queue scope. Do not track DSP rollout in a separate hand-maintained list. - - The planned `dsp/generic/fixed` leaf set is now validated: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. - - The next cross-subsystem cleanup is no longer hypothetical: remove the stale temporary `ethernet` and `protocols` subsystem deferrals from `docs/_meta/rtl_phase1_queue_overrides.json` before using the queue as the next-module source of truth again. - - Until that happens, do not treat the generated queue artifacts as evidence that `ethernet` or `protocols` are untouched; this branch already contains the Ethernet slice plus the merged SSI and PGP waves even though the current queue inputs still defer those subsystems. - - Keep the local `protocols/pgp/pgp3/` defer unless there is a deliberate decision to broaden the PGP family rollout. - - Do not hand-maintain queue order in the plan or handoff docs. + - `RawEthFramerTx` still has an intentionally narrow first-pass contract. Do not claim broader multi-beat unicast completion coverage yet. + - `IgmpV2Engine` still has no checked-in cocotb coverage. + - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, `Caui4Core`, and `RoCEv2` remain untouched in phase 1. +- Current planning discipline: + - Use manual user-directed area selection as the active source of truth for what to work on next. + - Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the actual validated branch frontier. + - Keep the graph and queue artifacts only as historical provenance or optional analysis context; do not use them as the next-module selector unless the user explicitly opts back into queue-driven planning. - Current wrapper discipline: - Prefer the existing subsystem `ip_integrator/` shim layers over bespoke record flattening. - Keep first-pass wrapper benches intentionally narrow and document any omitted branches explicitly. - Use `start_lockstep_clocks()` when a DUT depends on truly shared clock edges. - Prefer explicit short sim-build keys for generated-wrapper benches when case metadata would otherwise create fragile build paths. - When a wrapper is checked in, write it like the surrounding repo HDL: include the SLAC/SURF banner and enough section comments that a new session can identify the shim, DUT, and flattening regions quickly. - - For the current Ethernet slice, the checked-in wrappers under `ethernet/EthMacCore/wrappers/`, `ethernet/RawEthFramer/wrappers/`, and `ethernet/UdpEngine/wrappers/` are now the expected cocotb surfaces. Keep using those subsystem-local wrappers rather than rebuilding record-packing logic in Python. + - For the current Ethernet slice, the checked-in wrappers under `ethernet/EthMacCore/wrappers/`, `ethernet/RawEthFramer/wrappers/`, `ethernet/UdpEngine/wrappers/`, and `ethernet/IpV4Engine/wrappers/` are the expected cocotb surfaces. Keep using those subsystem-local wrappers rather than rebuilding record-packing logic in Python. - Current cocotb-file discipline: - New test files should start with the standard SURF/SLAC header block. - The `Test methodology` block belongs directly under that header. @@ -58,6 +57,7 @@ - `tests/ethernet/EthMacCore/ethmac_test_utils.py` is now the shared home for the current Ethernet MAC slice: flat EMAC beat helpers, Ethernet/IPv4/UDP packet builders, checksum reference code, MAC-config byte-order helpers, and minimum-frame padding helpers. Reuse it instead of cloning packet or sideband plumbing across `EthMacCore` benches. - `tests/ethernet/RawEthFramer/raw_eth_test_utils.py` now holds the shared raw-Ethernet helper pieces: flat app-side beat helpers, raw-Ethernet header/frame builders, and lookup-handshake utilities reused by the `RawEthFramer`, `RawEthFramerRx`, and `RawEthFramerTx` benches. - `tests/ethernet/UdpEngine/udp_test_utils.py` is now the shared home for the UDP slice: legacy-address constants, pseudo-frame builders, DHCP option helpers, and the common cocotb bench setup for the `ArpIpTable`, `UdpEngine*`, and `UdpEngineWrapper*` wrappers. Reuse it instead of rebuilding IPv4/UDP helper glue in each test module. +- `tests/ethernet/IpV4Engine/ipv4_test_utils.py` is now the shared home for the IPv4 slice: packet/header builders and common cocotb bench setup for the `ArpEngine`, `IcmpEngine`, and `IpV4Engine*` wrappers. Reuse it instead of cloning IPv4 framing helpers across that directory. - The current `EthMacCore` slice is intentionally a checked-in-wrapper-first rollout, not a cocotb-generated-wrapper experiment. Keep new Ethernet work on that same pattern unless the simulator forces a very local generic adapter. - The XGMII import/export loopback behavior differs from the GMII path when `phyReady` drops mid-traffic: the blocked frame is retained and drains after link recovery, padded to Ethernet's minimum frame size if it was short. The GMII path drops that blocked frame. Future import/export coverage should preserve that distinction instead of forcing one common expectation. - `EthMacRxCsum` reliably raises `IPERR` on a bad IPv4 header checksum, but the checked-in wrapper contract does not currently require `EOFE` for that case. Keep the negative test aligned to the real observable contract rather than to a stronger assumption. @@ -88,12 +88,14 @@ The project now also has a shared helper path in `tests/common/regression_utils. `tests/common/regression_utils.py` now also includes `start_lockstep_clocks()` for DUTs whose generics assume truly common clocks in both ports. Use that helper instead of launching two same-period clocks independently when the RTL assumes shared edge identity. -The first manual `ethernet/EthMacCore` wave is now also in place. The checked-in Ethernet MAC benches under `tests/ethernet/EthMacCore/` cover `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`, and the current directory-level regression passes locally with `32 passed`. The current Ethernet wrappers live under `ethernet/EthMacCore/wrappers/` and should be treated as the stable cocotb-facing surfaces for deeper `EthMacCore` work. +`ethernet/EthMacCore/` now has checked-in regression coverage under `tests/ethernet/EthMacCore/` for both the original leaf slice and the deeper assembly layer. The current benches cover `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, `EthMacTop`, `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`. The current Ethernet wrappers live under `ethernet/EthMacCore/wrappers/` and should be treated as the stable cocotb-facing surfaces for further `EthMacCore` work. `ethernet/RawEthFramer/` now also has checked-in regression coverage under `tests/ethernet/RawEthFramer/`. The earlier top-level `RawEthFramer` wrapper bench is joined by direct leaf benches for `RawEthFramerRx` and `RawEthFramerTx`, plus a `RawEthFramerPair` integration bench whose wrapper cross-connects two `RawEthFramer` instances to mirror the legacy `ethernet/RawEthFramer/tb/RawEthFramerTb.vhd` topology. The validated RX leaf bench covers lookup-gated unicast decode, short-frame trim behavior, broadcast bypass, and representative reject cases. The validated TX leaf bench currently keeps a narrower first-pass subset: lookup-request exposure before forwarding, broadcast bypass with the observed padded wire image, and zero-MAC lookup-miss drop. Do not over-claim the broader multi-beat unicast completion path for `RawEthFramerTx`; that branch still needs follow-up before it should be considered a passing leaf-level contract. `ethernet/UdpEngine/` now has checked-in regression coverage under `tests/ethernet/UdpEngine/` as well. The current validated set covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, all backed by checked-in wrappers under `ethernet/UdpEngine/wrappers/` and the shared helper layer in `tests/ethernet/UdpEngine/udp_test_utils.py`. +`ethernet/IpV4Engine/` now also has checked-in regression coverage under `tests/ethernet/IpV4Engine/`. The current validated set covers `ArpEngine`, `IcmpEngine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, all backed by checked-in wrappers under `ethernet/IpV4Engine/wrappers/` and the shared helper layer in `tests/ethernet/IpV4Engine/ipv4_test_utils.py`. `IgmpV2Engine` remains the obvious uncovered gap in that slice. + The wrapper coverage policy is now more explicit in practice: test the wrapper-specific behavior, not the full leaf matrix again. `Fifo` validated both inferred sync/async selection branches, `FifoCascade` validated public stage-vector mapping plus a curated output smoke, and `FifoMux` is currently validated only on the stable split-to-narrow path. The pack-to-wide `FifoMux` path should be treated as still open rather than silently assumed covered. That same wrapper-policy lesson now applies to the late `base/sync` wrappers as well. `SyncClockFreq` is stable with a checked-in subsystem wrapper, but its common-clock measurement quantizes one count above the abstract target under the current GHDL flow, so the regression checks a bounded expected range rather than an exact integer. `SyncTrigRate` is intentionally covered as a wrapper/integration bench only: it proves aligned update publication, denser-window rate growth, reset-path liveness, and strobe pulse behavior, while exact min/max pipeline semantics remain the responsibility of the dedicated `SyncMinMax` leaf test. @@ -146,16 +148,16 @@ The combined validation command for that batch is `./.venv/bin/python -m pytest One small RTL fix landed during that validation pass because the new `AxiStreamDmaRingWrite` test exposed a real simulation-width hazard: `axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd` now slices `dmaAck.size` back to `RAM_DATA_WIDTH_C` before incrementing `nextAddr`. Keep that change; it is what allows the checked-in narrow wrapper to simulate cleanly under GHDL. -A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instantiation_graph.md` and `docs/_meta/rtl_instantiation_graph.json`, and the same generator now also emits a path-qualified bottom-up phase-1 queue at `docs/_meta/rtl_phase1_queue.md` and `docs/_meta/rtl_phase1_queue.json`. Keep the graph for provenance, but treat the generated queue as the default source of truth for what to implement next. Manual phase-1 deferrals and order exceptions belong in `docs/_meta/rtl_phase1_queue_overrides.json`, not as hand-edited ordering in the plan doc. +A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instantiation_graph.md` and `docs/_meta/rtl_instantiation_graph.json`, and the same generator now also emits a path-qualified bottom-up phase-1 queue at `docs/_meta/rtl_phase1_queue.md` and `docs/_meta/rtl_phase1_queue.json`. Keep the graph and queue for provenance, but treat them as historical context rather than as the default source of truth for what to implement next. ## Immediate Next Task -Refresh the phase-1 planning inputs before taking the next module. Remove the stale temporary `ethernet` and `protocols` subsystem deferrals from `docs/_meta/rtl_phase1_queue_overrides.json`, regenerate `docs/_meta/rtl_instantiation_graph.{md,json}` plus `docs/_meta/rtl_phase1_queue.{md,json}`, and then choose the next non-deferred frontier from that refreshed queue. If the follow-on still stays manual instead of queue-driven, the leading candidates remain the deeper `ethernet/EthMacCore` assembly layer (`EthMacRx`, `EthMacTx`, `EthMacRxFifo`, `EthMacTxFifo`) or the next wider non-`pgp3` protocol slice. +Wait for the next user-directed area selection, then keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with whatever lands in the tree. The immediate documentation priority is accuracy of the real done/open frontier, not regeneration of the historical queue artifacts. ## Read Order 1. `docs/_meta/rtl_regression_handoff.md` 2. `docs/_meta/rtl_regression_progress.md` 3. `docs/_meta/rtl_regression_plan.md` -4. `docs/_meta/rtl_phase1_queue.md` +4. `docs/_meta/rtl_phase1_queue.md` only if historical graph output is useful for context; it is no longer the active planning driver. Before writing code in a fresh session: 1. Re-read the Python comment rules and the checked-in wrapper comment/header rules above. @@ -180,13 +182,13 @@ Before writing code in a fresh session: - Many VHDL wrappers live under `*/tb/` - The initial regression inventory lives in `docs/_meta/rtl_regression_inventory.yaml` - The RTL instantiation graph lives in `docs/_meta/rtl_instantiation_graph.{md,json}` -- The generated path-qualified phase-1 module queue lives in `docs/_meta/rtl_phase1_queue.{md,json}`; use that queue plus the progress doc as the next-module source of truth instead of re-analyzing the graph JSON every time -- Manual phase-1 queue deferrals and order overrides live in `docs/_meta/rtl_phase1_queue_overrides.json` +- The generated path-qualified phase-1 queue lives in `docs/_meta/rtl_phase1_queue.{md,json}`, but it is now historical context only rather than the next-module source of truth +- Manual phase-1 queue deferrals and order overrides still live in `docs/_meta/rtl_phase1_queue_overrides.json`, but that file is not the active task-selection mechanism anymore - Use `./.venv/bin/python ...` for repo-local Python commands unless the virtualenv has already been activated in the current shell; do not assume a `python` shim exists on `PATH` - If GHDL rejects a direct command-line override for a non-scalar or real generic, prefer a generated thin test-only wrapper over simulator-specific literal workarounds or another checked-in one-off HDL shim - If a wrapper branch is unstable under the current open-source flow, keep the validated subset narrow and record the omitted branch explicitly in the docs instead of over-claiming wrapper coverage - `LutFixedDelay` remains intentionally deferred because it depends on `SinglePortRamPrimitive`; do not accidentally treat the now-small remaining `base/` set as phase-1 work that still needs to be forced through -- Regenerate the graph and the phase-1 queue with `./.venv/bin/python scripts/build_rtl_instantiation_graph.py` +- Regenerate the graph and the phase-1 queue with `./.venv/bin/python scripts/build_rtl_instantiation_graph.py` only when historical analysis is useful or the user explicitly asks for it - Local bootstrap entrypoint: `scripts/setup_regression_env.sh` - Local `ruckus` is linked from `~/ruckus` diff --git a/docs/_meta/rtl_regression_plan.md b/docs/_meta/rtl_regression_plan.md index f238083880..06e88ac34f 100644 --- a/docs/_meta/rtl_regression_plan.md +++ b/docs/_meta/rtl_regression_plan.md @@ -92,24 +92,22 @@ - Use a checked-in RTL instantiation graph to guide bottom-up rollout decisions. - Prefer testing high-reuse leaf primitives directly before spending effort on higher-level assemblies that mostly repackage them. - Use the graph to reduce repeated behavioral testing across adjacent hierarchy levels, not as a substitute for engineering judgment about externally visible behavior. -- Keep the graph artifacts for provenance, but use the generated path-qualified phase-1 queue in `docs/_meta/rtl_phase1_queue.{md,json}` as the day-to-day source of truth. -- Record manual phase-1 deferrals and manual order exceptions only in `docs/_meta/rtl_phase1_queue_overrides.json`; do not hand-edit queue order in this plan. -- Do not re-analyze `rtl_instantiation_graph.json` before every module. Regenerate the queue when needed and take the next non-deferred item from `rtl_phase1_queue.md` unless a concrete blocker forces a documented override. -- The earlier temporary `axi/`-first rollout preference has already been completed on the current branch line. The next planning step is to remove stale temporary `ethernet` and `protocols` subsystem deferrals from `docs/_meta/rtl_phase1_queue_overrides.json`, regenerate the queue, and then resume from the next real non-deferred frontier. +- Keep the graph and queue artifacts for provenance and optional analysis, but do not use them as the active day-to-day source of truth for task selection. +- The active planning driver is now manual user-directed area selection, with `docs/_meta/rtl_regression_progress.md` and `docs/_meta/rtl_regression_handoff.md` tracking what is done, what is intentionally narrow, and what remains open. +- Do not hand-maintain queue order in this plan. If the graph or queue is regenerated for analysis, treat it as secondary context unless the user explicitly switches back to queue-driven planning. -## Flat Build Order -The phase-1 simulator-friendly queue is now generated from the checked-in graph as a path-qualified bottom-up order rather than maintained inline in this plan. +## Historical Queue Artifacts +The phase-1 simulator-friendly queue remains available as a generated bottom-up artifact, but it is now historical context rather than the active workflow. -Operational artifacts: +Retained artifacts: - `docs/_meta/rtl_phase1_queue.md` - `docs/_meta/rtl_phase1_queue.json` - `docs/_meta/rtl_phase1_queue_overrides.json` -Workflow: -1. Regenerate the graph and queue with `./.venv/bin/python scripts/build_rtl_instantiation_graph.py`. -2. Use `docs/_meta/rtl_regression_progress.md` plus the inventory to identify the current completion frontier. -3. Take the next unfinished, non-deferred entry from `docs/_meta/rtl_phase1_queue.md`. -4. If a concrete blocker forces a defer or reorder, record that exception in `docs/_meta/rtl_phase1_queue_overrides.json` instead of hand-editing this plan. +If they are regenerated: +1. Use `./.venv/bin/python scripts/build_rtl_instantiation_graph.py`. +2. Treat the resulting graph and queue as reference material only. +3. Keep the real done/open frontier in `docs/_meta/rtl_regression_progress.md` and `docs/_meta/rtl_regression_handoff.md`. ## Phase Breakdown ### Phase 1 @@ -131,11 +129,11 @@ Workflow: - The repo has a checked-in inventory and handoff system. - New windows can recover project state by reading the handoff artifacts only. - The Python-only regression direction is documented and stable. -- The queue artifacts and their override inputs stay aligned with the actual validated branch frontier instead of lagging behind completed subsystem waves. +- The progress and handoff artifacts stay aligned with the actual validated branch frontier instead of lagging behind completed subsystem waves. - The smoke/functional tier split is established in the plan and progress tracking. ## Open Questions And Deferred Decisions - Whether PR-vs-nightly split is needed immediately or only after runtime data. - Exact criteria for moving a vendor-heavy module out of `deferred_vendor_heavy`. -- Whether the next broad post-refresh wave should follow the regenerated queue directly or continue manually in `ethernet/EthMacCore`. +- Which user-directed subsystem slice should be taken next after the current documented frontier. - Whether a separate tracked list of high-risk behavioral package helpers is needed once the module inventory stabilizes. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 4dbaa9e829..a39c4af926 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -2,35 +2,34 @@ ## Summary - Current phase: Phase-1 implementation active -- Current subsystem: manual `ethernet/UdpEngine` wave during the broader post-merge queue-refresh gap -- Current focus module: stabilize and document the new `ethernet/UdpEngine` coverage while keeping the stale phase-1 queue-refresh gap explicit in the handoff artifacts. +- Current subsystem: manual user-directed rollout tracking +- Current focus module: keep the planning docs aligned with the actual validated branch frontier while work proceeds by user-directed area selection instead of by the generated queue. - Last updated: 2026-04-17 ## Current Frontier Snapshot -- Next queue target: remove the stale temporary `ethernet` and `protocols` subsystem deferrals, regenerate `docs/_meta/rtl_phase1_queue.{md,json}`, then take the next real non-deferred frontier from the refreshed queue. -- Queue note: - - The axi-first pass is now complete through the previously remaining final 11 `axi/` modules. - - The current `verification-2` branch already includes the merged `pre-release` state through PR #1392, so the validated `protocols/ssi`, `protocols/pgp`, and manual Ethernet waves (`EthMacCore`, `RawEthFramer`, and now `UdpEngine`) are all part of the present branch snapshot. - - The queue snapshot in `docs/_meta/rtl_phase1_queue.{md,json}` is therefore intentionally behind the actual branch contents because `rtl_phase1_queue_overrides.json` still defers `ethernet` and `protocols` from the earlier `axi/`-first phase. - - `dsp/` is now included in the generated queue scope, so DSP rollout no longer needs to live on a hand-maintained side list. - - Do not use the currently checked-in queue files as the next-module source of truth until those stale subsystem deferrals have been removed and the queue has been regenerated. - - `protocols/pgp/pgp3/` is now an explicit local defer in `rtl_phase1_queue_overrides.json`; do not treat it as the default next family breadth target on this branch. +- Active planning rule: take the next work item from the user's manual direction, not from `docs/_meta/rtl_phase1_queue.{md,json}`. +- Manual planning note: + - The axi-first pass is complete through the previously remaining final 11 `axi/` modules. + - The current `verification-2` branch already includes the merged `pre-release` state through PR #1392, so the validated `protocols/ssi`, `protocols/pgp`, and current Ethernet waves (`EthMacCore`, `RawEthFramer`, `UdpEngine`, and `IpV4Engine`) are all part of the present branch snapshot. + - The checked-in queue and override artifacts are now retained only as historical provenance and optional graph output; they are no longer the source of truth for choosing the next area. + - Keep the done/open frontier in this progress file and in `docs/_meta/rtl_regression_handoff.md` aligned to the actual tree even if the queue artifacts are stale. - Known expected-open tests on this branch: - - None currently recorded. `AxiResize` and `AxiStreamDmaV2Read` both pass on this merged branch. + - `ethernet/RawEthFramer/rtl/RawEthFramerTx.vhd`: the broader multi-beat unicast completion path is still intentionally not claimed as covered by the current first-pass bench. + - `ethernet/IpV4Engine/rtl/IgmpV2Engine.vhd`: no checked-in cocotb coverage yet. - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. - - For `ethernet`, keep using the checked-in wrappers under `ethernet/*/wrappers/` plus the shared helper layers in `tests/ethernet/EthMacCore/ethmac_test_utils.py`, `tests/ethernet/RawEthFramer/raw_eth_test_utils.py`, and `tests/ethernet/UdpEngine/udp_test_utils.py`. The practical first-pass shape is flat EMAC/app beat wrappers with explicit sideband bits, curated functional slices instead of exhaustive generic sweeps, and dedicated pair/integration wrappers only where an old VHDL bench contributes a topology worth preserving. + - For `ethernet`, keep using the checked-in wrappers under `ethernet/*/wrappers/` plus the shared helper layers in `tests/ethernet/EthMacCore/ethmac_test_utils.py`, `tests/ethernet/RawEthFramer/raw_eth_test_utils.py`, `tests/ethernet/UdpEngine/udp_test_utils.py`, and `tests/ethernet/IpV4Engine/ipv4_test_utils.py`. The practical first-pass shape is flat EMAC/app beat wrappers with explicit sideband bits, curated functional slices instead of exhaustive generic sweeps, and dedicated pair/integration wrappers only where an old VHDL bench contributes a topology worth preserving. ## Status | Subsystem | Inventory | Smoke | Functional | Notes | | --- | --- | --- | --- | --- | -| Cross-cutting infrastructure | started | not started | started | Shared helper structure now lives in `tests/common/regression_utils.py`; pytest now defaults to `xdist` parallel execution via `pytest.ini`; the phase-1 rollout queue is now generated into `docs/_meta/rtl_phase1_queue.{md,json}` with explicit inputs in `docs/_meta/rtl_phase1_queue_overrides.json` | +| Cross-cutting infrastructure | started | not started | started | Shared helper structure now lives in `tests/common/regression_utils.py`; pytest now defaults to `xdist` parallel execution via `pytest.ini`; the checked-in graph/queue artifacts under `docs/_meta/` are retained for provenance, while `rtl_regression_progress.md` and `rtl_regression_handoff.md` are the active planning inputs | | `base` | started | not started | started | Validated low-level regressions now exist for `FifoAsync`, `FifoSync`, `FifoOutputPipeline`, `FifoWrFsm`, `FifoRdFsm`, `Fifo`, `FifoCascade`, `FifoMux`, `Synchronizer`, `SynchronizerVector`, `SynchronizerEdge`, `SynchronizerOneShot`, `SynchronizerFifo`, `SynchronizerOneShotCnt`, `SynchronizerOneShotVector`, `SynchronizerOneShotCntVector`, `SyncStatusVector`, `SyncTrigPeriod`, `SyncMinMax`, `SyncClockFreq`, `SyncTrigRate`, `SyncTrigRateVector`, `RstSync`, `RstPipeline`, `RstPipelineVector`, `PwrUpRst`, `Arbiter`, `ClockDivider`, `Debouncer`, `Gearbox`, `AsyncGearbox`, `Heartbeat`, `Mux`, `OneShot`, `RegisterVector`, `WatchDogRst`, `Scrambler`, `MasterRamIpIntegrator`, `SlaveRamIpIntegrator`, `SimpleDualPortRam`, `DualPortRam`, `TrueDualPortRam`, `LutRam`, `SlvDelay`, `SlvFixedDelay`, `SlvDelayRam`, `SlvDelayFifo`, `Crc32Parallel`, `Crc32`, and `CRC32Rtl` under subsystem-organized `tests/base/` packages. Remaining uncovered `base/` entities are vendor-heavy, dummy-backed, or `LutFixedDelay`, which is deferred because it depends on `SinglePortRamPrimitive`. | | `dsp` | started | not started | started | The planned `dsp/generic/fixed` leaf batch is now validated under `tests/dsp/generic/`: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. Shared DSP helpers now live in `tests/dsp/generic/dsp_test_utils.py`, and the legacy VHDL benches under `dsp/generic/tb/` were treated as behavioral reference material rather than as execution constraints. | | `axi` | started | not started | started | The axi-first pass is now complete for the simulator-friendly queue. The final locally validated batch adds `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`, with a combined `11 passed` validation run on 2026-03-27. Added checked-in subsystem wrappers under `axi/axi4/ip_integrator/`, `axi/axi-lite/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/` for those benches. `AxiStreamFifoV2` now has an expanded `10 passed` wrapper regression under `tests/axi/axi_stream/` covering async and sync width conversion, metadata truncation, `VALID_THOLD` frame-ready and burst-release modes, dynamic pause-threshold behavior, `CASCADE_SIZE=2`, and the `S_HAS_TREADY=0` pause-only source-side path. `AxiResize` now passes its equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` wrapper regression on this branch after the read-hold RTL fix. `AxiLiteAsync`, `AxiLiteToDrp`, and `AxiRateGen` still keep intentionally narrow common-clock subsets while the more timing-sensitive async AXI-Lite crossing branches remain open. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` still keep intentionally narrow first-pass subsets. `AxiStreamDmaV2Read` is now validated with a two-case wrapper regression covering both aligned and short terminal-beat reads after fixing bounded byte-count conversion in `AxiPkg` and terminal-mask generation in `AxiStreamDmaV2Read`. | | `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. | -| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` covers the first manual `EthMacCore` slice, `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, and `tests/ethernet/UdpEngine/` now adds checked-in benches for `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper` backed by shared helpers in `tests/ethernet/UdpEngine/udp_test_utils.py` plus checked-in wrappers under `ethernet/UdpEngine/wrappers/`. The RawEthFramer TX leaf remains the explicit Ethernet caveat inside an otherwise working manual subsystem wave. The generated queue still keeps the broader subsystem deferred until the post-axi refresh removes the temporary queue override. | +| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers both the original leaf slice and the deeper assembly benches for `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`; `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice; `tests/ethernet/UdpEngine/` covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`; and `tests/ethernet/IpV4Engine/` covers `ArpEngine`, `IcmpEngine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`. The explicit Ethernet caveats are the still-narrow `RawEthFramerTx` contract, the uncovered `IgmpV2Engine`, and the larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, `Caui4Core`, and `RoCEv2`. | | `devices` | not started | not started | not started | Many vendor-heavy cases | | `xilinx` | not started | not started | not started | Many vendor-heavy cases | @@ -49,7 +48,7 @@ - Keep wrappers only when they make Python interaction cleaner. - Run the `vsg` linter with CI's `vsg-linter.yml` settings on any created or edited VHDL files, and use autofix before doing manual cleanup when possible. - Treat VHDL packages as transitively covered unless a behavioral function/procedure needs a dedicated wrapper. -- Treat the checked-in queue and override artifacts as living planning inputs that must be refreshed when a previously deferred subsystem wave is merged. +- Treat `docs/_meta/rtl_regression_progress.md` and `docs/_meta/rtl_regression_handoff.md` as the living planning inputs, and treat the checked-in queue artifacts as archival unless the user explicitly asks to resume queue-driven planning. ## Completed Work Items - Surveyed repo structure and existing verification flow. @@ -250,9 +249,12 @@ - 2026-04-07: Expanded `tests/protocols/ssi/test_SsiFifo.py` beyond the earlier single-beat subset. The checked-in FIFO bench now proves contiguous 3-beat frame preservation on the default, `VALID_THOLD_G=0`, and `VALID_THOLD_G=2` wrapper paths; exercises repeated-`SOF` malformed-frame handling across the buffered modes; and keeps the existing missing-`SOF` drop plus `SLAVE_READY_EN_G=false` overflow checks. The buffered malformed-frame result is mode-specific at the wrapper boundary: `VALID_THOLD_G=0` drops the malformed repeated-`SOF` frame outright, while `VALID_THOLD_G=2` emits the expected two-beat terminated `EOFE` frame. A follow-up backpressure pass also added explicit drain-side ready toggling on a good 5-beat frame, malformed termination under toggled ready, and thresholded release under intermittent drain stalls so SSI frame policy is now checked under nontrivial sink backpressure without duplicating the full `AxiStreamFifoV2` transport matrix. Revalidated the full touched SSI slice locally with `19 passed`. - 2026-04-10: Landed the first manual `ethernet/EthMacCore` bench wave under `tests/ethernet/EthMacCore/`, added the required checked-in wrappers under `ethernet/EthMacCore/wrappers/`, and validated the baseline 12-module slice covering `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`. - 2026-04-10: Expanded that same `EthMacCore` slice beyond the initial happy paths. The checked-in Ethernet MAC suite now covers `EthMacTop` filter/backpressure/checksum/pause interactions, GMII and XGMII import/export plus link-not-ready recovery behavior, checksum negative cases, filter multicast/broadcast/filter-disable/multi-beat-drop behavior, shift runtime-control and control-bit propagation edges, and full byte-width `1..16` logic-path coverage for `EthCrc32Parallel`. The full `tests/ethernet/EthMacCore` directory currently passes locally with `32 passed`. +- 2026-04-17: Expanded the `ethernet/EthMacCore` slice into the deeper assembly layer. The checked-in Ethernet MAC benches now also cover `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo` through the existing subsystem-local wrappers under `ethernet/EthMacCore/wrappers/`. - 2026-04-17: Added the manual `ethernet/UdpEngine` wave under `tests/ethernet/UdpEngine/`. The checked-in helper layer now lives in `tests/ethernet/UdpEngine/udp_test_utils.py`, the new checked-in wrappers live under `ethernet/UdpEngine/wrappers/`, and the locally validated benches cover `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`. The current local validation command `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/UdpEngine/test_ArpIpTable.py tests/ethernet/UdpEngine/test_UdpEngineArp.py tests/ethernet/UdpEngine/test_UdpEngineDhcp.py tests/ethernet/UdpEngine/test_UdpEngineRx.py tests/ethernet/UdpEngine/test_UdpEngineTx.py tests/ethernet/UdpEngine/test_UdpEngine.py tests/ethernet/UdpEngine/test_UdpEngineWrapper.py` passes with `7 passed`. +- 2026-04-17: Added the manual `ethernet/IpV4Engine` wave under `tests/ethernet/IpV4Engine/`. The checked-in helper layer now lives in `tests/ethernet/IpV4Engine/ipv4_test_utils.py`, the checked-in wrappers live under `ethernet/IpV4Engine/wrappers/`, and the validated benches cover `ArpEngine`, `IcmpEngine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`. `IgmpV2Engine` remains open. - 2026-04-16: Merged the current `pre-release` branch into `verification-2`, so this branch line now contains the already-landed SSI and PGP waves from PR #1391 and PR #1392 in addition to the manual Ethernet slice. - 2026-04-16: Refreshed the planning docs to move the active frontier from “continue Ethernet next” to “refresh the stale queue/override inputs, then resume from the real merged-branch frontier.” +- 2026-04-17: Switched the planning docs from queue-driven task selection to user-directed frontier tracking. The graph and queue artifacts remain checked in for provenance, but `rtl_regression_progress.md` and `rtl_regression_handoff.md` are now the active done/open source of truth. - 2026-03-20: Added an explicit project rule to comment new Python regression code where intent or runner behavior is not self-evident. - 2026-03-20: Expanded `FifoAsync` to a validated 12-case parameter matrix and enabled default pytest xdist parallelization with `pytest.ini`. - 2026-03-20: Added package-coverage policy: packages are covered transitively unless a behavioral helper warrants a dedicated wrapper test. From aaad7b8a29878e4c7a578e641c23aa99d60dc71b Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 17 Apr 2026 13:38:19 -0700 Subject: [PATCH 17/92] Additional RawEthFramerTx test. --- docs/_meta/rtl_regression_handoff.md | 3 +- docs/_meta/rtl_regression_progress.md | 4 +- .../RawEthFramer/test_RawEthFramerTx.py | 87 +++++++++++++++++-- 3 files changed, 85 insertions(+), 9 deletions(-) diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index 976cae48b4..e8425bb6be 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -21,7 +21,6 @@ - Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, and the current Ethernet coverage now spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, and `IpV4Engine`. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. - Current axi frontier: complete for the intended simulator-friendly pass in this branch snapshot; do not resume from the older stale `AxiResize` note. - Current validated-open issues: - - `RawEthFramerTx` still has an intentionally narrow first-pass contract. Do not claim broader multi-beat unicast completion coverage yet. - `IgmpV2Engine` still has no checked-in cocotb coverage. - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, `Caui4Core`, and `RoCEv2` remain untouched in phase 1. - Current planning discipline: @@ -90,7 +89,7 @@ The project now also has a shared helper path in `tests/common/regression_utils. `ethernet/EthMacCore/` now has checked-in regression coverage under `tests/ethernet/EthMacCore/` for both the original leaf slice and the deeper assembly layer. The current benches cover `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, `EthMacTop`, `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`. The current Ethernet wrappers live under `ethernet/EthMacCore/wrappers/` and should be treated as the stable cocotb-facing surfaces for further `EthMacCore` work. -`ethernet/RawEthFramer/` now also has checked-in regression coverage under `tests/ethernet/RawEthFramer/`. The earlier top-level `RawEthFramer` wrapper bench is joined by direct leaf benches for `RawEthFramerRx` and `RawEthFramerTx`, plus a `RawEthFramerPair` integration bench whose wrapper cross-connects two `RawEthFramer` instances to mirror the legacy `ethernet/RawEthFramer/tb/RawEthFramerTb.vhd` topology. The validated RX leaf bench covers lookup-gated unicast decode, short-frame trim behavior, broadcast bypass, and representative reject cases. The validated TX leaf bench currently keeps a narrower first-pass subset: lookup-request exposure before forwarding, broadcast bypass with the observed padded wire image, and zero-MAC lookup-miss drop. Do not over-claim the broader multi-beat unicast completion path for `RawEthFramerTx`; that branch still needs follow-up before it should be considered a passing leaf-level contract. +`ethernet/RawEthFramer/` now also has checked-in regression coverage under `tests/ethernet/RawEthFramer/`. The earlier top-level `RawEthFramer` wrapper bench is joined by direct leaf benches for `RawEthFramerRx` and `RawEthFramerTx`, plus a `RawEthFramerPair` integration bench whose wrapper cross-connects two `RawEthFramer` instances to mirror the legacy `ethernet/RawEthFramer/tb/RawEthFramerTb.vhd` topology. The validated RX leaf bench covers lookup-gated unicast decode, short-frame trim behavior, broadcast bypass, and representative reject cases. The validated TX leaf bench now covers lookup-request exposure before forwarding, successful multi-beat unicast forwarding after lookup resolution, broadcast bypass with the observed padded wire image, and zero-MAC lookup-miss drop. The successful unicast leaf case intentionally models the nonzero lookup latency that the integrated `RawEthFramer` wrapper inserts before `ack`, so keep that timing assumption if the TX bench is expanded further. `ethernet/UdpEngine/` now has checked-in regression coverage under `tests/ethernet/UdpEngine/` as well. The current validated set covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, all backed by checked-in wrappers under `ethernet/UdpEngine/wrappers/` and the shared helper layer in `tests/ethernet/UdpEngine/udp_test_utils.py`. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index a39c4af926..79371060d9 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -14,7 +14,6 @@ - The checked-in queue and override artifacts are now retained only as historical provenance and optional graph output; they are no longer the source of truth for choosing the next area. - Keep the done/open frontier in this progress file and in `docs/_meta/rtl_regression_handoff.md` aligned to the actual tree even if the queue artifacts are stale. - Known expected-open tests on this branch: - - `ethernet/RawEthFramer/rtl/RawEthFramerTx.vhd`: the broader multi-beat unicast completion path is still intentionally not claimed as covered by the current first-pass bench. - `ethernet/IpV4Engine/rtl/IgmpV2Engine.vhd`: no checked-in cocotb coverage yet. - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. @@ -29,7 +28,7 @@ | `dsp` | started | not started | started | The planned `dsp/generic/fixed` leaf batch is now validated under `tests/dsp/generic/`: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. Shared DSP helpers now live in `tests/dsp/generic/dsp_test_utils.py`, and the legacy VHDL benches under `dsp/generic/tb/` were treated as behavioral reference material rather than as execution constraints. | | `axi` | started | not started | started | The axi-first pass is now complete for the simulator-friendly queue. The final locally validated batch adds `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`, with a combined `11 passed` validation run on 2026-03-27. Added checked-in subsystem wrappers under `axi/axi4/ip_integrator/`, `axi/axi-lite/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/` for those benches. `AxiStreamFifoV2` now has an expanded `10 passed` wrapper regression under `tests/axi/axi_stream/` covering async and sync width conversion, metadata truncation, `VALID_THOLD` frame-ready and burst-release modes, dynamic pause-threshold behavior, `CASCADE_SIZE=2`, and the `S_HAS_TREADY=0` pause-only source-side path. `AxiResize` now passes its equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` wrapper regression on this branch after the read-hold RTL fix. `AxiLiteAsync`, `AxiLiteToDrp`, and `AxiRateGen` still keep intentionally narrow common-clock subsets while the more timing-sensitive async AXI-Lite crossing branches remain open. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` still keep intentionally narrow first-pass subsets. `AxiStreamDmaV2Read` is now validated with a two-case wrapper regression covering both aligned and short terminal-beat reads after fixing bounded byte-count conversion in `AxiPkg` and terminal-mask generation in `AxiStreamDmaV2Read`. | | `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. | -| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers both the original leaf slice and the deeper assembly benches for `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`; `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice; `tests/ethernet/UdpEngine/` covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`; and `tests/ethernet/IpV4Engine/` covers `ArpEngine`, `IcmpEngine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`. The explicit Ethernet caveats are the still-narrow `RawEthFramerTx` contract, the uncovered `IgmpV2Engine`, and the larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, `Caui4Core`, and `RoCEv2`. | +| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers both the original leaf slice and the deeper assembly benches for `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`; `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, including the successful multi-beat `RawEthFramerTx` unicast-forwarding path after lookup resolution; `tests/ethernet/UdpEngine/` covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`; and `tests/ethernet/IpV4Engine/` covers `ArpEngine`, `IcmpEngine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`. The explicit Ethernet caveats are the uncovered `IgmpV2Engine` and the larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, `Caui4Core`, and `RoCEv2`. | | `devices` | not started | not started | not started | Many vendor-heavy cases | | `xilinx` | not started | not started | not started | Many vendor-heavy cases | @@ -255,6 +254,7 @@ - 2026-04-16: Merged the current `pre-release` branch into `verification-2`, so this branch line now contains the already-landed SSI and PGP waves from PR #1391 and PR #1392 in addition to the manual Ethernet slice. - 2026-04-16: Refreshed the planning docs to move the active frontier from “continue Ethernet next” to “refresh the stale queue/override inputs, then resume from the real merged-branch frontier.” - 2026-04-17: Switched the planning docs from queue-driven task selection to user-directed frontier tracking. The graph and queue artifacts remain checked in for provenance, but `rtl_regression_progress.md` and `rtl_regression_handoff.md` are now the active done/open source of truth. +- 2026-04-17: Expanded `tests/ethernet/RawEthFramer/test_RawEthFramerTx.py` to cover the successful multi-beat unicast forwarding path after lookup resolution. The new leaf test holds the source frame through the exported request phase, models the same nonzero lookup latency the integrated `RawEthFramer` wrapper inserts before `ack`, and validates the full MAC-side wire image alongside the existing request, broadcast-bypass, and zero-MAC drop checks. - 2026-03-20: Added an explicit project rule to comment new Python regression code where intent or runner behavior is not self-evident. - 2026-03-20: Expanded `FifoAsync` to a validated 12-case parameter matrix and enabled default pytest xdist parallelization with `pytest.ini`. - 2026-03-20: Added package-coverage policy: packages are covered transitively unless a behavioral helper warrants a dedicated wrapper test. diff --git a/tests/ethernet/RawEthFramer/test_RawEthFramerTx.py b/tests/ethernet/RawEthFramer/test_RawEthFramerTx.py index cfcb29a364..fb22ac9ed9 100644 --- a/tests/ethernet/RawEthFramer/test_RawEthFramerTx.py +++ b/tests/ethernet/RawEthFramer/test_RawEthFramerTx.py @@ -10,15 +10,18 @@ # Test methodology: # - Sweep: Cover the RawEthFramerTx leaf across the lookup-facing request path, -# the stable broadcast bypass path, and the drop path when a unicast lookup +# a successful multi-beat unicast transfer after lookup resolution, the +# stable broadcast bypass path, and the drop path when a unicast lookup # resolves to zero. # - Stimulus: Drive app-side raw-Ethernet payload frames into the flattened TX # wrapper, hold the lookup `ack` low while observing `req`/`tDest`, then use -# the broadcast or zero-MAC miss branches for the complete on-wire checks. +# a nonzero resolved MAC for the successful unicast case plus the broadcast and +# zero-MAC miss branches for the complete on-wire checks. # - Checks: Unicast traffic must expose the requested `tDest` and stall until -# lookup completion, broadcast traffic must bypass lookup and emit the -# expected padded wire image, and unicast traffic must drop when the resolved -# remote MAC is zero. +# lookup completion, a successful multi-beat unicast must emit the full +# framed wire image after lookup resolution, broadcast traffic must bypass +# lookup and emit the expected padded wire image, and unicast traffic must +# drop when the resolved remote MAC is zero. # - Timing: The bench waits on the exported lookup request and on accepted AXIS # handshakes rather than assuming a fixed latency through the cache logic. @@ -26,9 +29,11 @@ import cocotb import pytest +from cocotb.triggers import Timer from tests.common.regression_utils import run_surf_vhdl_test from tests.ethernet.EthMacCore.ethmac_test_utils import ( + cycle, expect_no_output, payload_from_beats, recv_frame, @@ -39,6 +44,8 @@ LOCAL_MAC_WIRE, RAWETH_BEAT_BYTES, RAWETH_RTL_SOURCES, + REMOTE_MAC_CFG, + REMOTE_MAC_WIRE, build_raw_eth_wire_frame, pad_to_raw_eth_lane_width, pulse_signal, @@ -51,6 +58,20 @@ WRAPPER_PATH = "ethernet/RawEthFramer/wrappers/RawEthFramerTxFlatWrapper.vhd" +async def send_contiguous_raw_frame(endpoint, beats, *, clk) -> None: + # Keep the raw-app source valid across the whole frame so the TX leaf sees + # the same contiguous traffic pattern as the MAC-side EMAC helpers use. + for beat in beats: + endpoint.drive(beat) + await endpoint.wait_ready(clk=clk) + # The TX RTL registers state with `TPD_G` delay, so hold the accepted + # beat stable slightly past the handshake edge before presenting the + # next beat. This preserves cycle-contiguous traffic without letting a + # same-delta update overwrite the just-accepted app word. + await Timer(1, unit="ns") + endpoint.set_idle() + + @cocotb.test() async def raw_eth_tx_exposes_lookup_request_before_forwarding_test(dut): bench = await setup_raw_eth_tx_bench(dut) @@ -70,6 +91,62 @@ async def raw_eth_tx_exposes_lookup_request_before_forwarding_test(dut): bench.source.set_idle() +@cocotb.test() +async def raw_eth_tx_successful_multi_beat_unicast_forwards_full_wire_image_test(dut): + bench = await setup_raw_eth_tx_bench(dut) + + payload = b"lookup-success-multi-beat" + framed_payload = pad_to_raw_eth_lane_width(payload, lane_bytes=RAWETH_BEAT_BYTES) + + # Choose a payload that needs multiple app beats so the test proves the + # positive unicast forwarding path instead of only the initial lookup + # request handshake. + send_task = cocotb.start_soon( + send_contiguous_raw_frame( + bench.source, + raw_app_beats_from_bytes(payload, dest=0x2A, eofe=1), + clk=bench.clk, + ) + ) + + # The leaf should first expose the lookup request and remain stalled until + # software-like logic returns a valid remote MAC. + observed_dest = await wait_lookup_request(dut, clk=bench.clk) + assert observed_dest == 0x2A + await expect_no_output(bench.sink, clk=bench.clk, cycles=4) + + # Resolve the lookup with a nonzero MAC address so the full framed unicast + # transfer can progress onto the MAC-side stream. Leave `req` asserted for + # a couple of cycles first so the leaf sees the same nonzero lookup latency + # that the integrated RawEthFramer wrapper naturally inserts. + await cycle(bench.clk, 2) + dut.remoteMac.value = REMOTE_MAC_CFG + await pulse_signal(dut.ack, clk=bench.clk) + + observed = await recv_frame( + bench.sink, + clk=bench.clk, + ready_signal=dut.mMacTReady, + timeout_cycles=128, + ) + await send_task + + assert payload_from_beats(observed, lane_bytes=8) == build_raw_eth_wire_frame( + dst_mac=REMOTE_MAC_WIRE, + src_mac=LOCAL_MAC_WIRE, + dest=0x2A, + bcf=0, + payload=framed_payload, + min_byte_count=16 + len(payload), + eth_type_cfg=ETH_TYPE_CFG, + ) + assert len(observed) > 4 + assert observed[0].sof == 1 + assert observed[-1].last == 1 + assert observed[-1].eofe == 1 + assert int(dut.req.value) == 0 + + @cocotb.test() async def raw_eth_tx_broadcast_bypasses_lookup_test(dut): bench = await setup_raw_eth_tx_bench(dut) From 4e0a442d8b2e8780efadd8c79a4788b6ca96b88c Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 17 Apr 2026 13:47:44 -0700 Subject: [PATCH 18/92] IGMP tests --- docs/_meta/rtl_regression_handoff.md | 5 +- docs/_meta/rtl_regression_progress.md | 7 +- .../wrappers/IgmpV2EngineWrapper.vhd | 109 +++++++++ tests/ethernet/IpV4Engine/ipv4_test_utils.py | 45 ++++ .../ethernet/IpV4Engine/test_IgmpV2Engine.py | 231 ++++++++++++++++++ 5 files changed, 391 insertions(+), 6 deletions(-) create mode 100644 ethernet/IpV4Engine/wrappers/IgmpV2EngineWrapper.vhd create mode 100644 tests/ethernet/IpV4Engine/test_IgmpV2Engine.py diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index e8425bb6be..af7d15bf61 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -21,7 +21,6 @@ - Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, and the current Ethernet coverage now spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, and `IpV4Engine`. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. - Current axi frontier: complete for the intended simulator-friendly pass in this branch snapshot; do not resume from the older stale `AxiResize` note. - Current validated-open issues: - - `IgmpV2Engine` still has no checked-in cocotb coverage. - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, `Caui4Core`, and `RoCEv2` remain untouched in phase 1. - Current planning discipline: - Use manual user-directed area selection as the active source of truth for what to work on next. @@ -56,7 +55,7 @@ - `tests/ethernet/EthMacCore/ethmac_test_utils.py` is now the shared home for the current Ethernet MAC slice: flat EMAC beat helpers, Ethernet/IPv4/UDP packet builders, checksum reference code, MAC-config byte-order helpers, and minimum-frame padding helpers. Reuse it instead of cloning packet or sideband plumbing across `EthMacCore` benches. - `tests/ethernet/RawEthFramer/raw_eth_test_utils.py` now holds the shared raw-Ethernet helper pieces: flat app-side beat helpers, raw-Ethernet header/frame builders, and lookup-handshake utilities reused by the `RawEthFramer`, `RawEthFramerRx`, and `RawEthFramerTx` benches. - `tests/ethernet/UdpEngine/udp_test_utils.py` is now the shared home for the UDP slice: legacy-address constants, pseudo-frame builders, DHCP option helpers, and the common cocotb bench setup for the `ArpIpTable`, `UdpEngine*`, and `UdpEngineWrapper*` wrappers. Reuse it instead of rebuilding IPv4/UDP helper glue in each test module. -- `tests/ethernet/IpV4Engine/ipv4_test_utils.py` is now the shared home for the IPv4 slice: packet/header builders and common cocotb bench setup for the `ArpEngine`, `IcmpEngine`, and `IpV4Engine*` wrappers. Reuse it instead of cloning IPv4 framing helpers across that directory. +- `tests/ethernet/IpV4Engine/ipv4_test_utils.py` is now the shared home for the IPv4 slice: packet/header builders and common cocotb bench setup for the `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, and `IpV4Engine*` wrappers. Reuse it instead of cloning IPv4 framing helpers across that directory. - The current `EthMacCore` slice is intentionally a checked-in-wrapper-first rollout, not a cocotb-generated-wrapper experiment. Keep new Ethernet work on that same pattern unless the simulator forces a very local generic adapter. - The XGMII import/export loopback behavior differs from the GMII path when `phyReady` drops mid-traffic: the blocked frame is retained and drains after link recovery, padded to Ethernet's minimum frame size if it was short. The GMII path drops that blocked frame. Future import/export coverage should preserve that distinction instead of forcing one common expectation. - `EthMacRxCsum` reliably raises `IPERR` on a bad IPv4 header checksum, but the checked-in wrapper contract does not currently require `EOFE` for that case. Keep the negative test aligned to the real observable contract rather than to a stronger assumption. @@ -93,7 +92,7 @@ The project now also has a shared helper path in `tests/common/regression_utils. `ethernet/UdpEngine/` now has checked-in regression coverage under `tests/ethernet/UdpEngine/` as well. The current validated set covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, all backed by checked-in wrappers under `ethernet/UdpEngine/wrappers/` and the shared helper layer in `tests/ethernet/UdpEngine/udp_test_utils.py`. -`ethernet/IpV4Engine/` now also has checked-in regression coverage under `tests/ethernet/IpV4Engine/`. The current validated set covers `ArpEngine`, `IcmpEngine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, all backed by checked-in wrappers under `ethernet/IpV4Engine/wrappers/` and the shared helper layer in `tests/ethernet/IpV4Engine/ipv4_test_utils.py`. `IgmpV2Engine` remains the obvious uncovered gap in that slice. +`ethernet/IpV4Engine/` now also has checked-in regression coverage under `tests/ethernet/IpV4Engine/`. The current validated set covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, all backed by checked-in wrappers under `ethernet/IpV4Engine/wrappers/` and the shared helper layer in `tests/ethernet/IpV4Engine/ipv4_test_utils.py`. The `IgmpV2Engine` leaf bench covers power-up reports, general-query re-arming, and report suppression on matching inbound membership reports; it also documents the leaf-level stale pseudo-header bytes that are ignored by downstream `IpV4EngineTx` assembly. The wrapper coverage policy is now more explicit in practice: test the wrapper-specific behavior, not the full leaf matrix again. `Fifo` validated both inferred sync/async selection branches, `FifoCascade` validated public stage-vector mapping plus a curated output smoke, and `FifoMux` is currently validated only on the stable split-to-narrow path. The pack-to-wide `FifoMux` path should be treated as still open rather than silently assumed covered. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 79371060d9..3fea63c313 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -14,7 +14,7 @@ - The checked-in queue and override artifacts are now retained only as historical provenance and optional graph output; they are no longer the source of truth for choosing the next area. - Keep the done/open frontier in this progress file and in `docs/_meta/rtl_regression_handoff.md` aligned to the actual tree even if the queue artifacts are stale. - Known expected-open tests on this branch: - - `ethernet/IpV4Engine/rtl/IgmpV2Engine.vhd`: no checked-in cocotb coverage yet. + - No simulator-friendly expected-open leaf tests remain in the currently covered `ethernet/IpV4Engine` slice; the remaining Ethernet work is in larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, `Caui4Core`, and `RoCEv2`. - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. @@ -28,7 +28,7 @@ | `dsp` | started | not started | started | The planned `dsp/generic/fixed` leaf batch is now validated under `tests/dsp/generic/`: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. Shared DSP helpers now live in `tests/dsp/generic/dsp_test_utils.py`, and the legacy VHDL benches under `dsp/generic/tb/` were treated as behavioral reference material rather than as execution constraints. | | `axi` | started | not started | started | The axi-first pass is now complete for the simulator-friendly queue. The final locally validated batch adds `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`, with a combined `11 passed` validation run on 2026-03-27. Added checked-in subsystem wrappers under `axi/axi4/ip_integrator/`, `axi/axi-lite/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/` for those benches. `AxiStreamFifoV2` now has an expanded `10 passed` wrapper regression under `tests/axi/axi_stream/` covering async and sync width conversion, metadata truncation, `VALID_THOLD` frame-ready and burst-release modes, dynamic pause-threshold behavior, `CASCADE_SIZE=2`, and the `S_HAS_TREADY=0` pause-only source-side path. `AxiResize` now passes its equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` wrapper regression on this branch after the read-hold RTL fix. `AxiLiteAsync`, `AxiLiteToDrp`, and `AxiRateGen` still keep intentionally narrow common-clock subsets while the more timing-sensitive async AXI-Lite crossing branches remain open. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` still keep intentionally narrow first-pass subsets. `AxiStreamDmaV2Read` is now validated with a two-case wrapper regression covering both aligned and short terminal-beat reads after fixing bounded byte-count conversion in `AxiPkg` and terminal-mask generation in `AxiStreamDmaV2Read`. | | `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. | -| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers both the original leaf slice and the deeper assembly benches for `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`; `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, including the successful multi-beat `RawEthFramerTx` unicast-forwarding path after lookup resolution; `tests/ethernet/UdpEngine/` covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`; and `tests/ethernet/IpV4Engine/` covers `ArpEngine`, `IcmpEngine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`. The explicit Ethernet caveats are the uncovered `IgmpV2Engine` and the larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, `Caui4Core`, and `RoCEv2`. | +| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers both the original leaf slice and the deeper assembly benches for `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`; `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, including the successful multi-beat `RawEthFramerTx` unicast-forwarding path after lookup resolution; `tests/ethernet/UdpEngine/` covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`; and `tests/ethernet/IpV4Engine/` covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`. The explicit Ethernet caveats are now the larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, `Caui4Core`, and `RoCEv2`. | | `devices` | not started | not started | not started | Many vendor-heavy cases | | `xilinx` | not started | not started | not started | Many vendor-heavy cases | @@ -250,7 +250,8 @@ - 2026-04-10: Expanded that same `EthMacCore` slice beyond the initial happy paths. The checked-in Ethernet MAC suite now covers `EthMacTop` filter/backpressure/checksum/pause interactions, GMII and XGMII import/export plus link-not-ready recovery behavior, checksum negative cases, filter multicast/broadcast/filter-disable/multi-beat-drop behavior, shift runtime-control and control-bit propagation edges, and full byte-width `1..16` logic-path coverage for `EthCrc32Parallel`. The full `tests/ethernet/EthMacCore` directory currently passes locally with `32 passed`. - 2026-04-17: Expanded the `ethernet/EthMacCore` slice into the deeper assembly layer. The checked-in Ethernet MAC benches now also cover `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo` through the existing subsystem-local wrappers under `ethernet/EthMacCore/wrappers/`. - 2026-04-17: Added the manual `ethernet/UdpEngine` wave under `tests/ethernet/UdpEngine/`. The checked-in helper layer now lives in `tests/ethernet/UdpEngine/udp_test_utils.py`, the new checked-in wrappers live under `ethernet/UdpEngine/wrappers/`, and the locally validated benches cover `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`. The current local validation command `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/UdpEngine/test_ArpIpTable.py tests/ethernet/UdpEngine/test_UdpEngineArp.py tests/ethernet/UdpEngine/test_UdpEngineDhcp.py tests/ethernet/UdpEngine/test_UdpEngineRx.py tests/ethernet/UdpEngine/test_UdpEngineTx.py tests/ethernet/UdpEngine/test_UdpEngine.py tests/ethernet/UdpEngine/test_UdpEngineWrapper.py` passes with `7 passed`. -- 2026-04-17: Added the manual `ethernet/IpV4Engine` wave under `tests/ethernet/IpV4Engine/`. The checked-in helper layer now lives in `tests/ethernet/IpV4Engine/ipv4_test_utils.py`, the checked-in wrappers live under `ethernet/IpV4Engine/wrappers/`, and the validated benches cover `ArpEngine`, `IcmpEngine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`. `IgmpV2Engine` remains open. +- 2026-04-17: Added the manual `ethernet/IpV4Engine` wave under `tests/ethernet/IpV4Engine/`. The checked-in helper layer now lives in `tests/ethernet/IpV4Engine/ipv4_test_utils.py`, the checked-in wrappers live under `ethernet/IpV4Engine/wrappers/`, and the validated benches cover `ArpEngine`, `IcmpEngine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`. +- 2026-04-17: Added `ethernet/IpV4Engine/wrappers/IgmpV2EngineWrapper.vhd` plus `tests/ethernet/IpV4Engine/test_IgmpV2Engine.py`, extending the IPv4 helper layer with IGMP packet builders in `tests/ethernet/IpV4Engine/ipv4_test_utils.py`. The new leaf bench covers power-up membership reports, general-query re-arming, and suppression of a pending local report when a matching inbound membership report is observed, while documenting the two leaf-boundary stale-field quirks that `IpV4EngineTx` ignores. - 2026-04-16: Merged the current `pre-release` branch into `verification-2`, so this branch line now contains the already-landed SSI and PGP waves from PR #1391 and PR #1392 in addition to the manual Ethernet slice. - 2026-04-16: Refreshed the planning docs to move the active frontier from “continue Ethernet next” to “refresh the stale queue/override inputs, then resume from the real merged-branch frontier.” - 2026-04-17: Switched the planning docs from queue-driven task selection to user-directed frontier tracking. The graph and queue artifacts remain checked in for provenance, but `rtl_regression_progress.md` and `rtl_regression_handoff.md` are now the active done/open source of truth. diff --git a/ethernet/IpV4Engine/wrappers/IgmpV2EngineWrapper.vhd b/ethernet/IpV4Engine/wrappers/IgmpV2EngineWrapper.vhd new file mode 100644 index 0000000000..ba200104b4 --- /dev/null +++ b/ethernet/IpV4Engine/wrappers/IgmpV2EngineWrapper.vhd @@ -0,0 +1,109 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for IgmpV2Engine +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity IgmpV2EngineWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + CLK_FREQ_G : real := 10.0); + port ( + clk : in sl; + rst : in sl; + localIp : in slv(31 downto 0); + igmpIp0 : in slv(31 downto 0); + igmpIp1 : in slv(31 downto 0); + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTReady : in sl := '1'; + mAxisSof : out sl; + mAxisEofe : out sl); +end entity IgmpV2EngineWrapper; + +architecture rtl of IgmpV2EngineWrapper is + + signal igmpIp : Slv32Array(1 downto 0); + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + igmpIp(0) <= igmpIp0; + igmpIp(1) <= igmpIp1; + + -- Flatten the IGMP pseudo-header stream presented by cocotb. + sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(127 downto 0) := sAxisTData; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); + sAxisMaster <= v; + end process sAxisComb; + + sAxisTReady <= sAxisSlave.tReady; + mAxisSlave.tReady <= mAxisTReady; + + -- Re-expand the outbound IGMP report pseudo-header stream for checks. + mAxisView : process (mAxisMaster) is + begin + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + end process mAxisView; + + U_DUT : entity surf.IgmpV2Engine + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + IGMP_GRP_SIZE => 2, + CLK_FREQ_G => CLK_FREQ_G) + port map ( + localIp => localIp, + igmpIp => igmpIp, + ibIgmpMaster => sAxisMaster, + ibIgmpSlave => sAxisSlave, + obIgmpMaster => mAxisMaster, + obIgmpSlave => mAxisSlave, + clk => clk, + rst => rst); + +end architecture rtl; diff --git a/tests/ethernet/IpV4Engine/ipv4_test_utils.py b/tests/ethernet/IpV4Engine/ipv4_test_utils.py index 8f8e3bdbde..6d071a3251 100644 --- a/tests/ethernet/IpV4Engine/ipv4_test_utils.py +++ b/tests/ethernet/IpV4Engine/ipv4_test_utils.py @@ -249,6 +249,51 @@ def build_icmp_echo_frame( ) +def build_igmp_packet( + *, + igmp_type: int, + max_resp_time: int = 0x00, + group_ip: str = "0.0.0.0", + checksum_override: int | None = None, +) -> bytes: + group_ip_bytes = ipv4_to_bytes(group_ip) + header_wo_checksum = bytes([igmp_type & 0xFF, max_resp_time & 0xFF]) + b"\x00\x00" + group_ip_bytes + checksum = internet_checksum(header_wo_checksum) if checksum_override is None else checksum_override + return bytes([igmp_type & 0xFF, max_resp_time & 0xFF]) + checksum.to_bytes(2, byteorder="big") + group_ip_bytes + + +def build_igmp_membership_query_packet( + *, + max_resp_time: int, + group_ip: str = "0.0.0.0", + checksum_override: int | None = None, +) -> bytes: + return build_igmp_packet( + igmp_type=0x11, + max_resp_time=max_resp_time, + group_ip=group_ip, + checksum_override=checksum_override, + ) + + +def build_igmp_membership_report_packet( + *, + group_ip: str, + checksum_override: int | None = None, +) -> bytes: + return build_igmp_packet( + igmp_type=0x16, + max_resp_time=0x00, + group_ip=group_ip, + checksum_override=checksum_override, + ) + + +def igmp_group_mac(group_ip: str) -> int: + group_ip_bytes = ipv4_to_bytes(group_ip) + return int.from_bytes(b"\x01\x00\x5E" + group_ip_bytes[1:], byteorder="big") + + def build_ipv4_udp_payload( *, src_port: int, diff --git a/tests/ethernet/IpV4Engine/test_IgmpV2Engine.py b/tests/ethernet/IpV4Engine/test_IgmpV2Engine.py new file mode 100644 index 0000000000..d769050465 --- /dev/null +++ b/tests/ethernet/IpV4Engine/test_IgmpV2Engine.py @@ -0,0 +1,231 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Cover the IGMPv2 leaf across the main transmit and receive branches: +# power-up membership reports, general-query-triggered reports, and report +# suppression when another host has already advertised the same group. +# - Stimulus: Present IGMP pseudo-header traffic exactly as IpV4EngineRx would +# emit it, including valid membership reports and queries plus an invalid +# checksum query that should be ignored. +# - Checks: Configured multicast groups must emit the expected pseudo-header +# report frames, a valid general query must re-arm reporting, and an inbound +# membership report with a matching group address must suppress the local +# pending report for that group. +# - Timing: The wrapper runs the engine at a tiny simulated `CLK_FREQ_G` so the +# 100 ms tick is one cycle, but the bench still waits on AXIS visibility +# rather than assuming exact internal cycle counts for report emission. + +from __future__ import annotations + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + cycle, + expect_no_output, + frame_beats_from_bytes, + payload_from_beats, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, +) +from tests.ethernet.IpV4Engine.ipv4_test_utils import ( + IPV4_RTL_SOURCES, + build_igmp_membership_query_packet, + build_igmp_membership_report_packet, + build_ipv4_rx_pseudo_frame, + igmp_group_mac, + ipv4_config_word, + ipv4_to_bytes, +) + + +WRAPPER_PATH = "ethernet/IpV4Engine/wrappers/IgmpV2EngineWrapper.vhd" + +LOCAL_IP = "192.168.70.10" +LOCAL_IP_CFG = ipv4_config_word(LOCAL_IP) +ROUTER_IP = "192.168.70.1" +GROUP0 = "239.1.2.3" +GROUP0_CFG = ipv4_config_word(GROUP0) +GROUP1 = "239.9.8.7" +GROUP1_CFG = ipv4_config_word(GROUP1) +OTHER_HOST_IP = "192.168.70.44" +ROUTER_MAC = 0x665544332211 +OTHER_HOST_MAC = 0x112233445566 + + +async def setup_igmp_bench(dut, *, group0_cfg: int, group1_cfg: int): + bench = await setup_flat_emac_testbench( + dut, + clk_name="clk", + rst_name="rst", + source_prefix="sAxis", + sink_prefix="mAxis", + initial_values={ + "localIp": LOCAL_IP_CFG, + "igmpIp0": group0_cfg, + "igmpIp1": group1_cfg, + "mAxisTReady": 0, + }, + ) + assert bench.source is not None + assert bench.sink is not None + return bench + + +def expected_report_frame(*, group_ip: str) -> bytes: + group_mac = igmp_group_mac(group_ip).to_bytes(6, byteorder="big") + return ( + group_mac + + b"\x00\x00" + + ipv4_to_bytes(LOCAL_IP) + + ipv4_to_bytes(group_ip) + # IgmpV2Engine leaves the low 32 bits of beat 1 untouched, and the + # downstream IPv4 TX path ignores them. At the leaf boundary they still + # appear as the carried-over low 32 bits of the multicast MAC. + + group_mac[:4] + + build_igmp_membership_report_packet(group_ip=group_ip) + ) + + +def assert_report_frame(frame: bytes, *, group_ip: str) -> None: + expected = expected_report_frame(group_ip=group_ip) + assert len(frame) == len(expected) + assert frame[:6] == expected[:6] + assert frame[8:16] == expected[8:16] + assert frame[16:20] == expected[16:20] + assert frame[20:] == expected[20:] + + +def general_query_frame(*, checksum_override: int | None = None) -> bytes: + return build_ipv4_rx_pseudo_frame( + src_mac=ROUTER_MAC, + src_ip=ROUTER_IP, + dst_ip="224.0.0.1", + protocol=0x02, + payload=build_igmp_membership_query_packet( + max_resp_time=0x02, + group_ip="0.0.0.0", + checksum_override=checksum_override, + ), + ) + + +def inbound_membership_report_frame(*, group_ip: str) -> bytes: + return build_ipv4_rx_pseudo_frame( + src_mac=OTHER_HOST_MAC, + src_ip=OTHER_HOST_IP, + dst_ip=group_ip, + protocol=0x02, + payload=build_igmp_membership_report_packet(group_ip=group_ip), + ) + + +@cocotb.test() +async def igmp_engine_power_up_reports_all_groups_test(dut): + bench = await setup_igmp_bench(dut, group0_cfg=GROUP0_CFG, group1_cfg=GROUP1_CFG) + + first_report = await recv_frame( + bench.sink, + clk=bench.clk, + ready_signal=dut.mAxisTReady, + timeout_cycles=768, + ) + assert_report_frame(payload_from_beats(first_report), group_ip=GROUP0) + assert first_report[0].sof == 1 + assert first_report[-1].last == 1 + + second_report = await recv_frame( + bench.sink, + clk=bench.clk, + ready_signal=dut.mAxisTReady, + timeout_cycles=64, + ) + assert_report_frame(payload_from_beats(second_report), group_ip=GROUP1) + assert second_report[0].sof == 1 + assert second_report[-1].last == 1 + + +@cocotb.test() +async def igmp_engine_general_query_rearms_report_test(dut): + bench = await setup_igmp_bench(dut, group0_cfg=GROUP0_CFG, group1_cfg=0) + + initial_report = await recv_frame( + bench.sink, + clk=bench.clk, + ready_signal=dut.mAxisTReady, + timeout_cycles=768, + ) + assert_report_frame(payload_from_beats(initial_report), group_ip=GROUP0) + await expect_no_output(bench.sink, clk=bench.clk, cycles=12) + + # Let the random counter advance beyond the query's max-response time so + # the engine keeps the deterministic two-tick timeout set by the query. + await cycle(bench.clk, 10) + + query_send = cocotb.start_soon( + send_contiguous_frame(bench.source, frame_beats_from_bytes(general_query_frame()), clk=bench.clk) + ) + query_report = await recv_frame( + bench.sink, + clk=bench.clk, + ready_signal=dut.mAxisTReady, + timeout_cycles=64, + ) + await query_send + assert_report_frame(payload_from_beats(query_report), group_ip=GROUP0) + await expect_no_output(bench.sink, clk=bench.clk, cycles=12) + + +@cocotb.test() +async def igmp_engine_report_suppression_and_bad_checksum_ignore_test(dut): + bench = await setup_igmp_bench(dut, group0_cfg=GROUP0_CFG, group1_cfg=GROUP1_CFG) + + suppression_send = cocotb.start_soon( + send_contiguous_frame( + bench.source, + frame_beats_from_bytes(inbound_membership_report_frame(group_ip=GROUP0)), + clk=bench.clk, + ) + ) + await suppression_send + + bad_query_send = cocotb.start_soon( + send_contiguous_frame( + bench.source, + frame_beats_from_bytes(general_query_frame(checksum_override=0x0000)), + clk=bench.clk, + ) + ) + await bad_query_send + + surviving_report = await recv_frame( + bench.sink, + clk=bench.clk, + ready_signal=dut.mAxisTReady, + timeout_cycles=768, + ) + assert_report_frame(payload_from_beats(surviving_report), group_ip=GROUP1) + + # Group 0 was explicitly suppressed and the bad query must not re-arm it. + await expect_no_output(bench.sink, clk=bench.clk, cycles=24) + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="igmp_v2_engine_wrapper")]) +def test_IgmpV2Engine(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.igmpv2enginewrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": IPV4_RTL_SOURCES + [WRAPPER_PATH]}, + ) From e6645a5d8ff3426884e6cb2249789d8e68b16c9c Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 17 Apr 2026 14:33:07 -0700 Subject: [PATCH 19/92] Deeper testing. --- docs/_meta/rtl_regression_handoff.md | 9 +- docs/_meta/rtl_regression_progress.md | 9 +- .../EthMacImportExportLoopbackWrapper.vhd | 10 +- .../wrappers/EthMacRxBypassWrapper.vhd | 117 +++++++++++++++ .../wrappers/EthMacTxBypassWrapper.vhd | 127 ++++++++++++++++ .../EthMacCore/test_EthMacRxBypass.py | 106 ++++++++++++++ .../EthMacCore/test_EthMacRxImport.py | 29 +++- .../EthMacCore/test_EthMacTxBypass.py | 137 ++++++++++++++++++ .../EthMacCore/test_EthMacTxExport.py | 40 +++-- tests/ethernet/IpV4Engine/test_IcmpEngine.py | 121 ++++++++++++---- tests/ethernet/IpV4Engine/test_IpV4Engine.py | 56 ++++++- tests/ethernet/UdpEngine/test_UdpEngine.py | 92 +++++++++++- .../UdpEngine/test_UdpEngineWrapper.py | 33 ++++- 13 files changed, 810 insertions(+), 76 deletions(-) create mode 100644 ethernet/EthMacCore/wrappers/EthMacRxBypassWrapper.vhd create mode 100644 ethernet/EthMacCore/wrappers/EthMacTxBypassWrapper.vhd create mode 100644 tests/ethernet/EthMacCore/test_EthMacRxBypass.py create mode 100644 tests/ethernet/EthMacCore/test_EthMacTxBypass.py diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index af7d15bf61..6843f6ecce 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -18,10 +18,11 @@ - Treat VHDL packages as transitively covered unless a behavioral function/procedure needs a dedicated wrapper ## Quick Resume Snapshot -- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, and the current Ethernet coverage now spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, and `IpV4Engine`. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. +- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, and the current Ethernet coverage now spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, and `IpV4Engine`, including the recent thin-area cleanup across direct bypass leaves, broader top-level UDP/IPv4 paths, and deeper ICMP negatives. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. - Current axi frontier: complete for the intended simulator-friendly pass in this branch snapshot; do not resume from the older stale `AxiResize` note. - Current validated-open issues: - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, `Caui4Core`, and `RoCEv2` remain untouched in phase 1. + - `EthMacRxImportXlgmii` and `EthMacTxExportXlgmii` are still placeholder no-op RTL; the checked-in tests now lock down that inert contract instead of claiming functional XLGMII support. - Current planning discipline: - Use manual user-directed area selection as the active source of truth for what to work on next. - Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the actual validated branch frontier. @@ -58,8 +59,10 @@ - `tests/ethernet/IpV4Engine/ipv4_test_utils.py` is now the shared home for the IPv4 slice: packet/header builders and common cocotb bench setup for the `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, and `IpV4Engine*` wrappers. Reuse it instead of cloning IPv4 framing helpers across that directory. - The current `EthMacCore` slice is intentionally a checked-in-wrapper-first rollout, not a cocotb-generated-wrapper experiment. Keep new Ethernet work on that same pattern unless the simulator forces a very local generic adapter. - The XGMII import/export loopback behavior differs from the GMII path when `phyReady` drops mid-traffic: the blocked frame is retained and drains after link recovery, padded to Ethernet's minimum frame size if it was short. The GMII path drops that blocked frame. Future import/export coverage should preserve that distinction instead of forcing one common expectation. +- The current `EthMacRxImportXlgmii.vhd` and `EthMacTxExportXlgmii.vhd` leaves are placeholders: they drive no data-path activity and never pulse the count/status outputs. Future work should treat functional XLGMII support as an RTL gap, not as a missing bench. - `EthMacRxCsum` reliably raises `IPERR` on a bad IPv4 header checksum, but the checked-in wrapper contract does not currently require `EOFE` for that case. Keep the negative test aligned to the real observable contract rather than to a stronger assumption. - The RX/TX shift benches need a small idle-plus-settle gap before changing runtime shift controls because the underlying `AxiStreamShift` samples those controls while idle. Preserve that guardrail if those benches are refactored or expanded. +- `EthMacRxBypass` compares the EtherType field in the flattened EMAC byte-lane order, not normal wire-order host integer order. In practice that means a wire EtherType like `0x9000` must be compared as `x"0090"` at the wrapper/DUT generic boundary, just as `0x88B5` appears as `x"B588"` in the existing wrappers. ## Current Status Planning is complete and implementation is well underway. The agreed direction is a Python-only executable regression framework with tiered `smoke` and `functional` coverage. Existing VHDL TBs are reference material only and should be rewritten in Python when migrated, unless a thin wrapper is still useful for cocotb access. @@ -86,7 +89,9 @@ The project now also has a shared helper path in `tests/common/regression_utils. `tests/common/regression_utils.py` now also includes `start_lockstep_clocks()` for DUTs whose generics assume truly common clocks in both ports. Use that helper instead of launching two same-period clocks independently when the RTL assumes shared edge identity. -`ethernet/EthMacCore/` now has checked-in regression coverage under `tests/ethernet/EthMacCore/` for both the original leaf slice and the deeper assembly layer. The current benches cover `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, `EthMacTop`, `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`. The current Ethernet wrappers live under `ethernet/EthMacCore/wrappers/` and should be treated as the stable cocotb-facing surfaces for further `EthMacCore` work. +`ethernet/EthMacCore/` now has checked-in regression coverage under `tests/ethernet/EthMacCore/` for both the original leaf slice and the deeper assembly layer. The current benches cover `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, `EthMacTop`, `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, `EthMacTxFifo`, `EthMacRxBypass`, and `EthMacTxBypass`. The import/export benches now also explicitly encode the current placeholder `XLGMII` contract so future functional XLGMII RTL work will show up as a deliberate expectation change instead of an accidental gap. The current Ethernet wrappers live under `ethernet/EthMacCore/wrappers/` and should be treated as the stable cocotb-facing surfaces for further `EthMacCore` work. + +`ethernet/UdpEngine/` and `ethernet/IpV4Engine/` also received a thin-area cleanup pass on this branch. The `UdpEngine` top/wrapper benches now cover additional client/server routing paths beyond the earlier single happy-path smoke, while `IpV4Engine` now has a top-level protocol-TX path and deeper `IcmpEngine` negative/recovery coverage. The combined local validation command for that focused follow-up is `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/EthMacCore/test_EthMacRxImport.py tests/ethernet/EthMacCore/test_EthMacTxExport.py tests/ethernet/EthMacCore/test_EthMacRxBypass.py tests/ethernet/EthMacCore/test_EthMacTxBypass.py tests/ethernet/UdpEngine/test_UdpEngine.py tests/ethernet/UdpEngine/test_UdpEngineWrapper.py tests/ethernet/IpV4Engine/test_IpV4Engine.py tests/ethernet/IpV4Engine/test_IcmpEngine.py`, and it passes locally with `14 passed`. `ethernet/RawEthFramer/` now also has checked-in regression coverage under `tests/ethernet/RawEthFramer/`. The earlier top-level `RawEthFramer` wrapper bench is joined by direct leaf benches for `RawEthFramerRx` and `RawEthFramerTx`, plus a `RawEthFramerPair` integration bench whose wrapper cross-connects two `RawEthFramer` instances to mirror the legacy `ethernet/RawEthFramer/tb/RawEthFramerTb.vhd` topology. The validated RX leaf bench covers lookup-gated unicast decode, short-frame trim behavior, broadcast bypass, and representative reject cases. The validated TX leaf bench now covers lookup-request exposure before forwarding, successful multi-beat unicast forwarding after lookup resolution, broadcast bypass with the observed padded wire image, and zero-MAC lookup-miss drop. The successful unicast leaf case intentionally models the nonzero lookup latency that the integrated `RawEthFramer` wrapper inserts before `ack`, so keep that timing assumption if the TX bench is expanded further. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 3fea63c313..3732f6a965 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -3,7 +3,7 @@ ## Summary - Current phase: Phase-1 implementation active - Current subsystem: manual user-directed rollout tracking -- Current focus module: keep the planning docs aligned with the actual validated branch frontier while work proceeds by user-directed area selection instead of by the generated queue. +- Current focus module: keep the planning docs aligned with the actual validated branch frontier while waiting for the next user-directed subsystem slice after the Ethernet thin-area cleanup. - Last updated: 2026-04-17 ## Current Frontier Snapshot @@ -14,7 +14,9 @@ - The checked-in queue and override artifacts are now retained only as historical provenance and optional graph output; they are no longer the source of truth for choosing the next area. - Keep the done/open frontier in this progress file and in `docs/_meta/rtl_regression_handoff.md` aligned to the actual tree even if the queue artifacts are stale. - Known expected-open tests on this branch: - - No simulator-friendly expected-open leaf tests remain in the currently covered `ethernet/IpV4Engine` slice; the remaining Ethernet work is in larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, `Caui4Core`, and `RoCEv2`. + - No simulator-friendly expected-open leaf tests remain in the currently covered `ethernet/IpV4Engine` slice, and the recent `EthMacCore` / `UdpEngine` thin-area follow-up is also checked in on this branch. + - The current `EthMac*Xlgmii` import/export leaves are still placeholder no-op RTL, so the checked-in benches document that inert contract rather than claiming functional XLGMII datapath coverage. + - The remaining Ethernet work is in larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, `Caui4Core`, and `RoCEv2`. - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. @@ -28,7 +30,7 @@ | `dsp` | started | not started | started | The planned `dsp/generic/fixed` leaf batch is now validated under `tests/dsp/generic/`: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. Shared DSP helpers now live in `tests/dsp/generic/dsp_test_utils.py`, and the legacy VHDL benches under `dsp/generic/tb/` were treated as behavioral reference material rather than as execution constraints. | | `axi` | started | not started | started | The axi-first pass is now complete for the simulator-friendly queue. The final locally validated batch adds `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`, with a combined `11 passed` validation run on 2026-03-27. Added checked-in subsystem wrappers under `axi/axi4/ip_integrator/`, `axi/axi-lite/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/` for those benches. `AxiStreamFifoV2` now has an expanded `10 passed` wrapper regression under `tests/axi/axi_stream/` covering async and sync width conversion, metadata truncation, `VALID_THOLD` frame-ready and burst-release modes, dynamic pause-threshold behavior, `CASCADE_SIZE=2`, and the `S_HAS_TREADY=0` pause-only source-side path. `AxiResize` now passes its equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` wrapper regression on this branch after the read-hold RTL fix. `AxiLiteAsync`, `AxiLiteToDrp`, and `AxiRateGen` still keep intentionally narrow common-clock subsets while the more timing-sensitive async AXI-Lite crossing branches remain open. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` still keep intentionally narrow first-pass subsets. `AxiStreamDmaV2Read` is now validated with a two-case wrapper regression covering both aligned and short terminal-beat reads after fixing bounded byte-count conversion in `AxiPkg` and terminal-mask generation in `AxiStreamDmaV2Read`. | | `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. | -| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers both the original leaf slice and the deeper assembly benches for `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`; `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, including the successful multi-beat `RawEthFramerTx` unicast-forwarding path after lookup resolution; `tests/ethernet/UdpEngine/` covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`; and `tests/ethernet/IpV4Engine/` covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`. The explicit Ethernet caveats are now the larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, `Caui4Core`, and `RoCEv2`. | +| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers both the original leaf slice and the deeper assembly benches for `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`, plus direct `EthMacRxBypass` / `EthMacTxBypass` leaf benches and import/export sweeps that now explicitly include the current placeholder `XLGMII` contract. `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, including the successful multi-beat `RawEthFramerTx` unicast-forwarding path after lookup resolution. `tests/ethernet/UdpEngine/` covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, with the top/wrapper benches now widened across client/server routing paths. `tests/ethernet/IpV4Engine/` covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, and the top/leaf benches now also include protocol-TX and deeper ICMP reject/recovery coverage. The explicit Ethernet caveats are now the larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, `Caui4Core`, and `RoCEv2`, plus the still-placeholder `EthMac*Xlgmii` RTL. | | `devices` | not started | not started | not started | Many vendor-heavy cases | | `xilinx` | not started | not started | not started | Many vendor-heavy cases | @@ -256,6 +258,7 @@ - 2026-04-16: Refreshed the planning docs to move the active frontier from “continue Ethernet next” to “refresh the stale queue/override inputs, then resume from the real merged-branch frontier.” - 2026-04-17: Switched the planning docs from queue-driven task selection to user-directed frontier tracking. The graph and queue artifacts remain checked in for provenance, but `rtl_regression_progress.md` and `rtl_regression_handoff.md` are now the active done/open source of truth. - 2026-04-17: Expanded `tests/ethernet/RawEthFramer/test_RawEthFramerTx.py` to cover the successful multi-beat unicast forwarding path after lookup resolution. The new leaf test holds the source frame through the exported request phase, models the same nonzero lookup latency the integrated `RawEthFramer` wrapper inserts before `ack`, and validates the full MAC-side wire image alongside the existing request, broadcast-bypass, and zero-MAC drop checks. +- 2026-04-17: Completed the Ethernet thin-area follow-up across `EthMacCore`, `UdpEngine`, and `IpV4Engine`. Added checked-in wrappers `ethernet/EthMacCore/wrappers/EthMacRxBypassWrapper.vhd` and `ethernet/EthMacCore/wrappers/EthMacTxBypassWrapper.vhd`, added `tests/ethernet/EthMacCore/test_EthMacRxBypass.py` and `tests/ethernet/EthMacCore/test_EthMacTxBypass.py`, widened `test_EthMacRxImport.py` / `test_EthMacTxExport.py` to cover the current placeholder `XLGMII` contract, widened `tests/ethernet/UdpEngine/test_UdpEngine.py` and `tests/ethernet/UdpEngine/test_UdpEngineWrapper.py` across additional client/server routing paths, widened `tests/ethernet/IpV4Engine/test_IpV4Engine.py` with a top-level protocol-TX path, and deepened `tests/ethernet/IpV4Engine/test_IcmpEngine.py` with truncated-request rejection, EOFE preservation, and post-reject recovery checks. The combined local validation command `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/EthMacCore/test_EthMacRxImport.py tests/ethernet/EthMacCore/test_EthMacTxExport.py tests/ethernet/EthMacCore/test_EthMacRxBypass.py tests/ethernet/EthMacCore/test_EthMacTxBypass.py tests/ethernet/UdpEngine/test_UdpEngine.py tests/ethernet/UdpEngine/test_UdpEngineWrapper.py tests/ethernet/IpV4Engine/test_IpV4Engine.py tests/ethernet/IpV4Engine/test_IcmpEngine.py` passes locally with `14 passed`. - 2026-03-20: Added an explicit project rule to comment new Python regression code where intent or runner behavior is not self-evident. - 2026-03-20: Expanded `FifoAsync` to a validated 12-case parameter matrix and enabled default pytest xdist parallelization with `pytest.ini`. - 2026-03-20: Added package-coverage policy: packages are covered transitively unless a behavioral helper warrants a dedicated wrapper test. diff --git a/ethernet/EthMacCore/wrappers/EthMacImportExportLoopbackWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacImportExportLoopbackWrapper.vhd index d93a8017b9..690153e751 100644 --- a/ethernet/EthMacCore/wrappers/EthMacImportExportLoopbackWrapper.vhd +++ b/ethernet/EthMacCore/wrappers/EthMacImportExportLoopbackWrapper.vhd @@ -60,6 +60,8 @@ architecture rtl of EthMacImportExportLoopbackWrapper is signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal xlgmiiTxd : slv(127 downto 0) := (others => '0'); + signal xlgmiiTxc : slv(15 downto 0) := (others => '0'); signal xgmiiTxd : slv(63 downto 0) := (others => '0'); signal xgmiiTxc : slv(7 downto 0) := (others => '0'); signal gmiiTxEn : sl := '0'; @@ -110,8 +112,8 @@ begin ethRst => ethRst, macObMaster => sAxisMaster, macObSlave => sAxisSlave, - xlgmiiTxd => open, - xlgmiiTxc => open, + xlgmiiTxd => xlgmiiTxd, + xlgmiiTxc => xlgmiiTxc, xgmiiTxd => xgmiiTxd, xgmiiTxc => xgmiiTxc, gmiiTxEn => gmiiTxEn, @@ -134,8 +136,8 @@ begin ethClk => ethClk, ethRst => ethRst, macIbMaster => mAxisMaster, - xlgmiiRxd => (others => '0'), - xlgmiiRxc => (others => '1'), + xlgmiiRxd => xlgmiiTxd, + xlgmiiRxc => xlgmiiTxc, xgmiiRxd => xgmiiTxd, xgmiiRxc => xgmiiTxc, gmiiRxDv => gmiiTxEn, diff --git a/ethernet/EthMacCore/wrappers/EthMacRxBypassWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacRxBypassWrapper.vhd new file mode 100644 index 0000000000..c5a52afdb1 --- /dev/null +++ b/ethernet/EthMacCore/wrappers/EthMacRxBypassWrapper.vhd @@ -0,0 +1,117 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for EthMacRxBypass +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity EthMacRxBypassWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + BYP_EN_G : boolean := false; + BYP_ETH_TYPE_G : slv(15 downto 0) := x"0090"); + port ( + ethClk : in sl; + ethRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTDest : in slv(7 downto 0); + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisEofe : in sl; + mPrimTValid : out sl; + mPrimTData : out slv(127 downto 0); + mPrimTKeep : out slv(15 downto 0); + mPrimTLast : out sl; + mPrimTDest : out slv(7 downto 0); + mPrimSof : out sl; + mPrimEofe : out sl; + mBypTValid : out sl; + mBypTData : out slv(127 downto 0); + mBypTKeep : out slv(15 downto 0); + mBypTLast : out sl; + mBypTDest : out slv(7 downto 0); + mBypSof : out sl; + mBypEofe : out sl); +end entity EthMacRxBypassWrapper; + +architecture rtl of EthMacRxBypassWrapper is + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mPrimMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mBypMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + +begin + + sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTDest, sAxisTKeep, sAxisTLast, sAxisTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(127 downto 0) := sAxisTData; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + v.tDest(7 downto 0) := sAxisTDest; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); + sAxisMaster <= v; + end process sAxisComb; + + sAxisTReady <= '1'; + + mPrimView : process (mPrimMaster) is + begin + mPrimTValid <= mPrimMaster.tValid; + mPrimTData <= mPrimMaster.tData(127 downto 0); + mPrimTKeep <= mPrimMaster.tKeep(15 downto 0); + mPrimTLast <= mPrimMaster.tLast; + mPrimTDest <= mPrimMaster.tDest(7 downto 0); + mPrimSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_SOF_BIT_C, 0); + mPrimEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_EOFE_BIT_C); + end process mPrimView; + + mBypView : process (mBypMaster) is + begin + mBypTValid <= mBypMaster.tValid; + mBypTData <= mBypMaster.tData(127 downto 0); + mBypTKeep <= mBypMaster.tKeep(15 downto 0); + mBypTLast <= mBypMaster.tLast; + mBypTDest <= mBypMaster.tDest(7 downto 0); + mBypSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_SOF_BIT_C, 0); + mBypEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_EOFE_BIT_C); + end process mBypView; + + U_DUT : entity surf.EthMacRxBypass + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + BYP_EN_G => BYP_EN_G, + BYP_ETH_TYPE_G => BYP_ETH_TYPE_G) + port map ( + ethClk => ethClk, + ethRst => ethRst, + sAxisMaster => sAxisMaster, + mPrimMaster => mPrimMaster, + mBypMaster => mBypMaster); + +end architecture rtl; diff --git a/ethernet/EthMacCore/wrappers/EthMacTxBypassWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacTxBypassWrapper.vhd new file mode 100644 index 0000000000..0221740083 --- /dev/null +++ b/ethernet/EthMacCore/wrappers/EthMacTxBypassWrapper.vhd @@ -0,0 +1,127 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for EthMacTxBypass +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity EthMacTxBypassWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + BYP_EN_G : boolean := false); + port ( + ethClk : in sl; + ethRst : in sl; + sPrimTValid : in sl; + sPrimTData : in slv(127 downto 0); + sPrimTKeep : in slv(15 downto 0); + sPrimTLast : in sl; + sPrimTDest : in slv(7 downto 0); + sPrimTReady : out sl; + sPrimSof : in sl; + sPrimEofe : in sl; + sBypTValid : in sl; + sBypTData : in slv(127 downto 0); + sBypTKeep : in slv(15 downto 0); + sBypTLast : in sl; + sBypTDest : in slv(7 downto 0); + sBypTReady : out sl; + sBypSof : in sl; + sBypEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTDest : out slv(7 downto 0); + mAxisTReady : in sl := '1'; + mAxisSof : out sl; + mAxisEofe : out sl); +end entity EthMacTxBypassWrapper; + +architecture rtl of EthMacTxBypassWrapper is + + signal sPrimMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sPrimSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal sBypMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sBypSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + sPrimComb : process (sPrimEofe, sPrimSof, sPrimTData, sPrimTDest, sPrimTKeep, sPrimTLast, sPrimTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sPrimTValid; + v.tData(127 downto 0) := sPrimTData; + v.tKeep(15 downto 0) := sPrimTKeep; + v.tLast := sPrimTLast; + v.tDest(7 downto 0) := sPrimTDest; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sPrimSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sPrimEofe); + sPrimMaster <= v; + end process sPrimComb; + + sBypComb : process (sBypEofe, sBypSof, sBypTData, sBypTDest, sBypTKeep, sBypTLast, sBypTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sBypTValid; + v.tData(127 downto 0) := sBypTData; + v.tKeep(15 downto 0) := sBypTKeep; + v.tLast := sBypTLast; + v.tDest(7 downto 0) := sBypTDest; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sBypSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sBypEofe); + sBypMaster <= v; + end process sBypComb; + + mAxisSlave.tReady <= mAxisTReady; + + sPrimTReady <= sPrimSlave.tReady; + sBypTReady <= sBypSlave.tReady; + + mAxisView : process (mAxisMaster) is + begin + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisTDest <= mAxisMaster.tDest(7 downto 0); + mAxisSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + end process mAxisView; + + U_DUT : entity surf.EthMacTxBypass + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + BYP_EN_G => BYP_EN_G) + port map ( + ethClk => ethClk, + ethRst => ethRst, + sPrimMaster => sPrimMaster, + sPrimSlave => sPrimSlave, + sBypMaster => sBypMaster, + sBypSlave => sBypSlave, + mAxisMaster => mAxisMaster, + mAxisSlave => mAxisSlave); + +end architecture rtl; diff --git a/tests/ethernet/EthMacCore/test_EthMacRxBypass.py b/tests/ethernet/EthMacCore/test_EthMacRxBypass.py new file mode 100644 index 0000000000..f6f73e80fa --- /dev/null +++ b/tests/ethernet/EthMacCore/test_EthMacRxBypass.py @@ -0,0 +1,106 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Exercise both `BYP_EN_G=true` and `BYP_EN_G=false`. +# - Stimulus: Send one multi-beat frame with the configured bypass EtherType +# and one multi-beat frame with a normal EtherType. +# - Checks: When bypass is enabled the configured EtherType must route the +# entire frame to the bypass output and all other traffic must stay on the +# primary output; when bypass is disabled, even the bypass-tagged frame must +# pass through the primary output while the bypass output stays idle. +# - Timing: The test waits on complete frames from each exposed output so the +# route decision and frame-hold behavior are checked together. + +from __future__ import annotations + +import cocotb +import os +import pytest + +from tests.common.regression_utils import parameter_case, run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + ETHMAC_RTL_SOURCES, + FlatEmacEndpoint, + assert_beat_list, + build_ethernet_frame, + expect_no_output, + frame_beats_from_bytes, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, +) + + +WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacRxBypassWrapper.vhd" + + +@cocotb.test() +async def eth_mac_rx_bypass_routing_test(dut): + bypass_enabled = os.environ["BYP_EN_G"].lower() == "true" + bench = await setup_flat_emac_testbench( + dut, + source_prefix="sAxis", + ) + source = bench.source + assert source is not None + + prim_sink = FlatEmacEndpoint(dut, prefix="mPrim") + byp_sink = FlatEmacEndpoint(dut, prefix="mByp") + + bypass_frame = build_ethernet_frame( + dst_mac=0x101112131415, + src_mac=0x202122232425, + eth_type=0x9000, + payload=bytes(range(48)), + ) + bypass_expected = frame_beats_from_bytes(bypass_frame, dest=0x23, eofe=1) + bypass_send = cocotb.start_soon(send_contiguous_frame(source, bypass_expected, clk=bench.clk)) + + if bypass_enabled: + bypass_observed = await recv_frame(byp_sink, clk=bench.clk, timeout_cycles=64) + await bypass_send + assert_beat_list(bypass_observed, bypass_expected) + await expect_no_output(prim_sink, clk=bench.clk, cycles=8) + else: + primary_observed = await recv_frame(prim_sink, clk=bench.clk, timeout_cycles=64) + await bypass_send + assert_beat_list(primary_observed, bypass_expected) + await expect_no_output(byp_sink, clk=bench.clk, cycles=8) + + primary_frame = build_ethernet_frame( + dst_mac=0x313233343536, + src_mac=0x414243444546, + eth_type=0x88B5, + payload=b"ethmac-rx-bypass-primary-path" + bytes(range(17)), + ) + primary_expected = frame_beats_from_bytes(primary_frame, dest=0x5A) + primary_send = cocotb.start_soon(send_contiguous_frame(source, primary_expected, clk=bench.clk)) + primary_observed = await recv_frame(prim_sink, clk=bench.clk, timeout_cycles=64) + await primary_send + assert_beat_list(primary_observed, primary_expected) + await expect_no_output(byp_sink, clk=bench.clk, cycles=8) + + +PARAMETER_SWEEP = [ + parameter_case("bypass_enabled", BYP_EN_G=True), + parameter_case("bypass_disabled", BYP_EN_G=False), +] + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +def test_EthMacRxBypass(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ethmacrxbypasswrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/EthMacCore/test_EthMacRxImport.py b/tests/ethernet/EthMacCore/test_EthMacRxImport.py index 4be4ef18f7..f10941372d 100644 --- a/tests/ethernet/EthMacCore/test_EthMacRxImport.py +++ b/tests/ethernet/EthMacCore/test_EthMacRxImport.py @@ -9,17 +9,18 @@ ############################################################################## # Test methodology: -# - Sweep: Cover both supported functional PHY mappings in this wrapper, -# `GMII` and `XGMII`, and include a link-not-ready interval in each run. +# - Sweep: Cover the functional `GMII`/`XGMII` paths plus the current +# placeholder `XLGMII` path. # - Stimulus: Send one minimum-size frame, one longer multi-beat frame, one # frame while `phyReady=0`, and then one recovery frame after re-enabling the # link. -# - Checks: Ready PHY modes must recover the original AXIS bytes and pulse +# - Checks: `GMII` and `XGMII` must recover the original AXIS bytes and pulse # `rxCountEn`, the blocked frame must not appear while the link is down, and # the receiver must return to normal operation after `phyReady` is restored. # The recovery expectation is PHY-specific: GMII drops traffic presented # while the link is down, while the current XGMII loopback path presents that -# queued frame once `phyReady` returns. +# queued frame once `phyReady` returns. `XLGMII` is still a placeholder leaf, +# so the bench checks that it remains inert instead of over-claiming support. # - Timing: GMII takes many more cycles than XGMII to serialize a frame, so the # bench scales its receive timeout to the selected PHY mode. @@ -67,6 +68,19 @@ async def eth_mac_rx_import_test(dut): assert source is not None assert sink is not None + if phy_type == "XLGMII": + placeholder_frame = build_ethernet_frame( + dst_mac=0x020304050607, + src_mac=0x0A0B0C0D0E0F, + eth_type=0x88B5, + payload=bytes(range(46)), + ) + await send_contiguous_frame(source, frame_beats_from_bytes(placeholder_frame), clk=bench.clk) + await expect_no_output(sink, clk=bench.clk, cycles=24) + assert int(dut.rxCountEn.value) == 0 + assert int(dut.rxCrcError.value) == 0 + return + min_frame = build_ethernet_frame( dst_mac=0x020304050607, src_mac=0x0A0B0C0D0E0F, @@ -103,8 +117,8 @@ async def eth_mac_rx_import_test(dut): # A deasserted PHY-ready input resets the import logic, so traffic that # arrives in that interval must not leak partial output while the link is - # down. The current XGMII path replays the blocked frame after recovery, - # whereas the GMII path discards it. + # down. The current XGMII/XLGMII paths replay the blocked frame after + # recovery, whereas the GMII path discards it. dut.phyReady.value = 0 blocked_frame = build_ethernet_frame( dst_mac=0x313233343536, @@ -136,7 +150,7 @@ async def eth_mac_rx_import_test(dut): await recovery_pulse if phy_type == "XGMII": - # The XGMII export/import loopback retains the blocked frame across the + # The XGMII import/export loopback retains the blocked frame across the # ready transition, so the first recovered packet is the stalled one. # Because that packet traverses the TX path, it comes back padded to # Ethernet's minimum 60-byte frame size. @@ -152,6 +166,7 @@ async def eth_mac_rx_import_test(dut): PARAMETER_SWEEP = [ + parameter_case("xlgmii_loopback", PHY_TYPE_G="XLGMII"), parameter_case("xgmii_loopback", PHY_TYPE_G="XGMII"), parameter_case("gmii_loopback", PHY_TYPE_G="GMII"), ] diff --git a/tests/ethernet/EthMacCore/test_EthMacTxBypass.py b/tests/ethernet/EthMacCore/test_EthMacTxBypass.py new file mode 100644 index 0000000000..3774ac0419 --- /dev/null +++ b/tests/ethernet/EthMacCore/test_EthMacTxBypass.py @@ -0,0 +1,137 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Exercise both `BYP_EN_G=true` and `BYP_EN_G=false`. +# - Stimulus: Start primary and bypass traffic together to test selection from +# idle, then launch a bypass frame while a primary frame is already active. +# - Checks: With bypass enabled the bypass frame must win arbitration at idle +# but must not preempt an already-active primary frame; with bypass disabled +# the primary path must pass through unchanged and bypass traffic must be +# dropped. +# - Timing: The bench uses real ready/valid handshakes on both sources so the +# mux arbitration is checked under the DUT's own acceptance rules. + +from __future__ import annotations + +import cocotb +import os +import pytest + +from tests.common.regression_utils import parameter_case, run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + ETHMAC_RTL_SOURCES, + FlatEmacEndpoint, + assert_beat_list, + build_ethernet_frame, + cycle, + expect_no_output, + frame_beats_from_bytes, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, +) + + +WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacTxBypassWrapper.vhd" + + +@cocotb.test() +async def eth_mac_tx_bypass_arbitration_test(dut): + bypass_enabled = os.environ["BYP_EN_G"].lower() == "true" + bench = await setup_flat_emac_testbench( + dut, + source_prefix=None, + initial_values={ + "mAxisTReady": 0, + }, + ) + prim_source = FlatEmacEndpoint(dut, prefix="sPrim") + byp_source = FlatEmacEndpoint(dut, prefix="sByp") + sink = FlatEmacEndpoint(dut, prefix="mAxis") + prim_source.set_idle() + byp_source.set_idle() + + primary_frame = build_ethernet_frame( + dst_mac=0x010203040506, + src_mac=0x111213141516, + eth_type=0x88B5, + payload=b"tx-bypass-primary-idle" + bytes(range(28)), + ) + bypass_frame = build_ethernet_frame( + dst_mac=0x212223242526, + src_mac=0x313233343536, + eth_type=0x9000, + payload=b"tx-bypass-wins-idle" + bytes(range(29)), + ) + primary_expected = frame_beats_from_bytes(primary_frame, dest=0x31) + bypass_expected = frame_beats_from_bytes(bypass_frame, dest=0x72, eofe=1) + + primary_send = cocotb.start_soon(send_contiguous_frame(prim_source, primary_expected, clk=bench.clk)) + bypass_send = cocotb.start_soon(send_contiguous_frame(byp_source, bypass_expected, clk=bench.clk)) + first_observed = await recv_frame(sink, clk=bench.clk, ready_signal=dut.mAxisTReady, timeout_cycles=96) + + if bypass_enabled: + assert_beat_list(first_observed, bypass_expected) + second_observed = await recv_frame(sink, clk=bench.clk, ready_signal=dut.mAxisTReady, timeout_cycles=96) + assert_beat_list(second_observed, primary_expected) + else: + assert_beat_list(first_observed, primary_expected) + await expect_no_output(sink, clk=bench.clk, cycles=8) + + await primary_send + await bypass_send + + long_primary = build_ethernet_frame( + dst_mac=0x414243444546, + src_mac=0x515253545556, + eth_type=0x88B5, + payload=bytes(range(80)), + ) + late_bypass = build_ethernet_frame( + dst_mac=0x616263646566, + src_mac=0x717273747576, + eth_type=0x9000, + payload=b"late-bypass-frame" + bytes(range(24)), + ) + long_primary_expected = frame_beats_from_bytes(long_primary, dest=0x44) + late_bypass_expected = frame_beats_from_bytes(late_bypass, dest=0x55) + + long_primary_send = cocotb.start_soon(send_contiguous_frame(prim_source, long_primary_expected, clk=bench.clk)) + await cycle(bench.clk, 2) + late_bypass_send = cocotb.start_soon(send_contiguous_frame(byp_source, late_bypass_expected, clk=bench.clk)) + first_sequence = await recv_frame(sink, clk=bench.clk, ready_signal=dut.mAxisTReady, timeout_cycles=128) + assert_beat_list(first_sequence, long_primary_expected) + + if bypass_enabled: + second_sequence = await recv_frame(sink, clk=bench.clk, ready_signal=dut.mAxisTReady, timeout_cycles=96) + assert_beat_list(second_sequence, late_bypass_expected) + else: + await expect_no_output(sink, clk=bench.clk, cycles=8) + + await long_primary_send + await late_bypass_send + + +PARAMETER_SWEEP = [ + parameter_case("bypass_enabled", BYP_EN_G=True), + parameter_case("bypass_disabled", BYP_EN_G=False), +] + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +def test_EthMacTxBypass(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ethmactxbypasswrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/EthMacCore/test_EthMacTxExport.py b/tests/ethernet/EthMacCore/test_EthMacTxExport.py index bfb7defc9b..e3f73132e5 100644 --- a/tests/ethernet/EthMacCore/test_EthMacTxExport.py +++ b/tests/ethernet/EthMacCore/test_EthMacTxExport.py @@ -9,17 +9,20 @@ ############################################################################## # Test methodology: -# - Sweep: Cover both supported functional PHY mappings, `GMII` and `XGMII`, -# and explicitly exercise the exporter with `phyReady` both high and low. +# - Sweep: Cover the functional `GMII`/`XGMII` paths plus the current +# placeholder `XLGMII` path, and explicitly exercise the exporter with +# `phyReady` both high and low where the path is implemented. # - Stimulus: Send one minimum-size frame, one longer multi-beat frame, one # frame while the link is marked not ready, and then one recovery frame after # the link returns. -# - Checks: Successful transmissions must pulse `txCountEn`, the blocked frame -# must raise `txLinkNotReady` without producing output data while the link is -# down, and normal export behavior must recover cleanly after the ready -# signal is restored. The recovery expectation is PHY-specific because the -# current XGMII path drains the blocked frame after the link returns, while -# the GMII path drops it. +# - Checks: Successful `GMII`/`XGMII` transmissions must pulse `txCountEn`, the +# blocked frame must raise `txLinkNotReady` without producing output data +# while the link is down, and normal export behavior must recover cleanly +# after the ready signal is restored. The recovery expectation is PHY- +# specific because the current XGMII path drains the blocked frame after the +# link returns, while the GMII path drops it. `XLGMII` is still a placeholder +# leaf, so the bench checks that it remains inert instead of asserting a +# nonexistent data path. # - Timing: The receive timeout is scaled to the chosen PHY because the GMII # path serializes one byte per clock while XGMII transmits eight. @@ -67,6 +70,20 @@ async def eth_mac_tx_export_test(dut): assert source is not None assert sink is not None + if phy_type == "XLGMII": + placeholder_frame = build_ethernet_frame( + dst_mac=0x0C0D0E0F1011, + src_mac=0x121314151617, + eth_type=0x9000, + payload=bytes(range(46)), + ) + await send_contiguous_frame(source, frame_beats_from_bytes(placeholder_frame), clk=bench.clk) + await expect_no_output(sink, clk=bench.clk, cycles=24) + assert int(dut.txCountEn.value) == 0 + assert int(dut.txUnderRun.value) == 0 + assert int(dut.txLinkNotReady.value) == 0 + return + min_frame = build_ethernet_frame( dst_mac=0x0C0D0E0F1011, src_mac=0x121314151617, @@ -138,9 +155,9 @@ async def eth_mac_tx_export_test(dut): await recovery_pulse if phy_type == "XGMII": - # In the XGMII path the held-off frame drains first once the link - # returns, so the recovery frame arrives second. The stalled frame is - # padded by the TX path up to Ethernet's minimum non-FCS size. + # In the XGMII export/import path the held-off frame drains first once + # the link returns, so the recovery frame arrives second. The stalled + # frame is padded by the TX path up to Ethernet's minimum non-FCS size. assert payload_from_beats(recovery_observed) == pad_ethernet_frame_to_min_size(blocked_frame) drained_observed = await recv_frame(sink, clk=bench.clk, timeout_cycles=timeout_cycles) assert payload_from_beats(drained_observed) == recovery_frame @@ -153,6 +170,7 @@ async def eth_mac_tx_export_test(dut): PARAMETER_SWEEP = [ + parameter_case("xlgmii_loopback", PHY_TYPE_G="XLGMII"), parameter_case("xgmii_loopback", PHY_TYPE_G="XGMII"), parameter_case("gmii_loopback", PHY_TYPE_G="GMII"), ] diff --git a/tests/ethernet/IpV4Engine/test_IcmpEngine.py b/tests/ethernet/IpV4Engine/test_IcmpEngine.py index 605481e0c5..9dbf2e0a37 100644 --- a/tests/ethernet/IpV4Engine/test_IcmpEngine.py +++ b/tests/ethernet/IpV4Engine/test_IcmpEngine.py @@ -9,14 +9,16 @@ ############################################################################## # Test methodology: -# - Sweep: Cover the ICMP reply block with one valid local echo request plus -# two representative reject cases: wrong destination IP and non-echo type. +# - Sweep: Cover the ICMP reply block with valid multi-beat local echo +# requests, a truncated single-beat reject case, and representative protocol +# rejects. # - Stimulus: Present ICMP pseudo-header traffic exactly as IpV4EngineRx would -# emit it, including a valid echo request, a non-local request, and a -# non-echo ICMP packet. +# emit it, including valid echo requests, a truncated single-beat request, a +# non-local request, and a non-echo ICMP packet. # - Checks: Only an echo request addressed to the configured local IP may -# produce a response, and that response must be a correctly swapped echo -# reply pseudo-frame. +# produce a response, that response must be a correctly swapped echo reply +# pseudo-frame, the terminal EOFE bit must be preserved, and the block must +# recover cleanly after rejected traffic. # - Timing: The bench waits on AXIS visibility so the assertions remain stable # across internal pipeline depth changes. @@ -27,9 +29,9 @@ from tests.common.regression_utils import run_surf_vhdl_test from tests.ethernet.EthMacCore.ethmac_test_utils import ( + assert_beat_list, expect_no_output, frame_beats_from_bytes, - payload_from_beats, recv_frame, send_contiguous_frame, setup_flat_emac_testbench, @@ -70,33 +72,37 @@ async def icmp_engine_reply_filtering_test(dut): assert source is not None assert sink is not None - echo_payload = b"icmp-echo-request-payload" - echo_request = build_ipv4_rx_pseudo_frame( - src_mac=REMOTE_MAC, - src_ip=REMOTE_IP, - dst_ip=LOCAL_IP, - protocol=0x01, - payload=build_icmp_echo_packet( - payload=echo_payload, - identifier=0x3344, - sequence=0x0102, + echo_payload = b"icmp-echo-request-payload-with-extra-bytes" + echo_request = frame_beats_from_bytes( + build_ipv4_rx_pseudo_frame( + src_mac=REMOTE_MAC, + src_ip=REMOTE_IP, + dst_ip=LOCAL_IP, + protocol=0x01, + payload=build_icmp_echo_packet( + payload=echo_payload, + identifier=0x3344, + sequence=0x0102, + ), ), + eofe=1, ) - expected_reply = build_ipv4_tx_pseudo_frame( - dst_mac=REMOTE_MAC, - src_ip=LOCAL_IP, - dst_ip=REMOTE_IP, - protocol=0x01, - payload=build_icmp_echo_reply_packet( - payload=echo_payload, - identifier=0x3344, - sequence=0x0102, + expected_reply = frame_beats_from_bytes( + build_ipv4_tx_pseudo_frame( + dst_mac=REMOTE_MAC, + src_ip=LOCAL_IP, + dst_ip=REMOTE_IP, + protocol=0x01, + payload=build_icmp_echo_reply_packet( + payload=echo_payload, + identifier=0x3344, + sequence=0x0102, + ), ), + eofe=1, ) - reply_send = cocotb.start_soon( - send_contiguous_frame(source, frame_beats_from_bytes(echo_request), clk=bench.clk) - ) + reply_send = cocotb.start_soon(send_contiguous_frame(source, echo_request, clk=bench.clk)) reply_observed = await recv_frame( sink, clk=bench.clk, @@ -104,7 +110,25 @@ async def icmp_engine_reply_filtering_test(dut): timeout_cycles=128, ) await reply_send - assert payload_from_beats(reply_observed) == expected_reply + assert_beat_list(reply_observed, expected_reply) + + truncated_request = frame_beats_from_bytes( + build_ipv4_rx_pseudo_frame( + src_mac=REMOTE_MAC, + src_ip=REMOTE_IP, + dst_ip=LOCAL_IP, + protocol=0x01, + payload=build_icmp_echo_packet( + payload=b"", + identifier=0x0101, + sequence=0x0202, + ), + ) + ) + truncated_request[0].last = 1 + truncated_request[0].keep = 0xFFFF + await send_contiguous_frame(source, truncated_request[:1], clk=bench.clk) + await expect_no_output(sink, clk=bench.clk, cycles=12) non_local_request = build_ipv4_rx_pseudo_frame( src_mac=REMOTE_MAC, @@ -130,6 +154,43 @@ async def icmp_engine_reply_filtering_test(dut): await send_contiguous_frame(source, frame_beats_from_bytes(non_echo_message), clk=bench.clk) await expect_no_output(sink, clk=bench.clk, cycles=12) + second_payload = b"icmp-second-valid-request" + second_request = frame_beats_from_bytes( + build_ipv4_rx_pseudo_frame( + src_mac=REMOTE_MAC, + src_ip=REMOTE_IP, + dst_ip=LOCAL_IP, + protocol=0x01, + payload=build_icmp_echo_packet( + payload=second_payload, + identifier=0x5566, + sequence=0x0708, + ), + ) + ) + second_expected = frame_beats_from_bytes( + build_ipv4_tx_pseudo_frame( + dst_mac=REMOTE_MAC, + src_ip=LOCAL_IP, + dst_ip=REMOTE_IP, + protocol=0x01, + payload=build_icmp_echo_reply_packet( + payload=second_payload, + identifier=0x5566, + sequence=0x0708, + ), + ) + ) + second_send = cocotb.start_soon(send_contiguous_frame(source, second_request, clk=bench.clk)) + second_observed = await recv_frame( + sink, + clk=bench.clk, + ready_signal=dut.mAxisTReady, + timeout_cycles=128, + ) + await second_send + assert_beat_list(second_observed, second_expected) + @pytest.mark.parametrize("parameters", [pytest.param({}, id="icmp_engine_wrapper")]) def test_IcmpEngine(parameters): diff --git a/tests/ethernet/IpV4Engine/test_IpV4Engine.py b/tests/ethernet/IpV4Engine/test_IpV4Engine.py index dc9387cf5d..425364ca8b 100644 --- a/tests/ethernet/IpV4Engine/test_IpV4Engine.py +++ b/tests/ethernet/IpV4Engine/test_IpV4Engine.py @@ -9,13 +9,16 @@ ############################################################################## # Test methodology: -# - Sweep: Exercise the IPv4 top across one UDP receive path, one ICMP -# echo-response path, and one ARP client lookup round-trip. -# - Stimulus: Exercise the full IPv4 top with three focused scenarios: -# inbound UDP routing, inbound ICMP echo handling, and ARP client lookup. +# - Sweep: Exercise the IPv4 top across one UDP receive path, one protocol TX +# path, one ICMP echo-response path, and one ARP client lookup round-trip. +# - Stimulus: Exercise the full IPv4 top with four focused scenarios: +# inbound UDP routing, outbound protocol transmission, inbound ICMP echo +# handling, and ARP client lookup. # - Checks: UDP traffic must emerge on the protocol output slot as the expected -# pseudo-header frame, ICMP echo requests must produce outbound reply frames, -# and ARP requests must round-trip through the top-level ARP client ports. +# pseudo-header frame, outbound protocol traffic must emerge as a wire-format +# IPv4 frame on the MAC output, ICMP echo requests must produce outbound +# reply frames, and ARP requests must round-trip through the top-level ARP +# client ports. # - Timing: Each scenario uses handshaked sources and sinks so the top-level # assembly is verified through its real interfaces instead of local shortcuts. @@ -41,6 +44,7 @@ build_icmp_echo_frame, build_icmp_echo_reply_packet, build_ipv4_rx_pseudo_frame, + build_ipv4_tx_pseudo_frame, build_ipv4_tx_wire_frame, build_ipv4_udp_payload, build_ipv4_frame, @@ -124,6 +128,46 @@ async def ipv4_top_udp_routing_test(dut): assert payload_from_beats(udp_observed) == udp_expected +@cocotb.test() +async def ipv4_top_protocol_tx_path_test(dut): + bench, mac_sink, _, prot_source, _, _ = await setup_top_bench(dut) + + udp_payload = build_ipv4_udp_payload( + src_port=0x2468, + dst_port=0x1357, + payload=b"top-level-protocol-tx", + src_ip=LOCAL_IP, + dst_ip=REMOTE_IP, + ) + tx_request = build_ipv4_tx_pseudo_frame( + dst_mac=REMOTE_MAC_WIRE, + src_ip=LOCAL_IP, + dst_ip=REMOTE_IP, + protocol=0x11, + payload=udp_payload, + ) + tx_expected = build_ipv4_tx_wire_frame( + dst_mac=REMOTE_MAC_WIRE, + src_mac=LOCAL_MAC_WIRE, + src_ip=LOCAL_IP, + dst_ip=REMOTE_IP, + protocol=0x11, + payload=udp_payload, + ) + + tx_send = cocotb.start_soon( + send_contiguous_frame(prot_source, frame_beats_from_bytes(tx_request), clk=bench.clk) + ) + tx_observed = await recv_frame( + mac_sink, + clk=bench.clk, + ready_signal=dut.mMacTReady, + timeout_cycles=256, + ) + await tx_send + assert payload_from_beats(tx_observed) == tx_expected + + @cocotb.test() async def ipv4_top_icmp_echo_reply_test(dut): bench, mac_sink, _, _, _, _ = await setup_top_bench(dut) diff --git a/tests/ethernet/UdpEngine/test_UdpEngine.py b/tests/ethernet/UdpEngine/test_UdpEngine.py index 4f973caeae..39fbd43214 100644 --- a/tests/ethernet/UdpEngine/test_UdpEngine.py +++ b/tests/ethernet/UdpEngine/test_UdpEngine.py @@ -9,14 +9,16 @@ ############################################################################## # Test methodology: -# - Sweep: Exercise the UDP top across the client ARP-assisted TX path and the -# server RX path. -# - Stimulus: Allow the client side to request ARP resolution, acknowledge it, -# then send an outbound client payload while separately injecting a server- -# targeted pseudo-UDP frame into the inbound path. -# - Checks: The top must emit the expected ARP lookup and outbound pseudo-UDP -# frame on the client side, and must route inbound server traffic to the -# exposed server output with the header removed. +# - Sweep: Exercise the UDP top across client TX/RX coverage and server TX/RX +# coverage in the assembled ARP-integrated topology. +# - Stimulus: Allow the client side to request ARP resolution and acknowledge +# it, inject server- and client-targeted pseudo-UDP frames into the inbound +# path, and send one outbound server payload after the server metadata has +# been learned. +# - Checks: The top must emit the expected ARP lookup and outbound client +# pseudo-UDP frame, route inbound server and client traffic to the matching +# outputs with the UDP header removed, and reuse learned server endpoint +# metadata for an outbound server reply. # - Timing: The bench waits on actual AXIS handshakes on all exposed streams so # the integrated ARP, TX, and RX state transitions are observed in flight. @@ -119,6 +121,80 @@ async def udp_engine_server_rx_path_test(dut): assert payload_from_beats(server_observed) == server_payload +@cocotb.test() +async def udp_engine_client_rx_path_test(dut): + bench = await setup_udp_top_bench(dut) + + client_payload = b"udp-top-client-rx-path" + client_frame = build_udp_rx_pseudo_frame( + remote_mac=LEGACY_MAC_WIRES[1], + remote_ip=LEGACY_IPS[1], + local_ip=LEGACY_IPS[0], + remote_port=0x6789, + local_port=8193, + payload=client_payload, + ) + client_send = cocotb.start_soon( + send_contiguous_frame(bench.udp_source, frame_beats_from_bytes(client_frame), clk=bench.clk) + ) + client_observed = await recv_frame( + bench.client_sink, + clk=bench.clk, + ready_signal=dut.mClientTReady, + timeout_cycles=64, + ) + await client_send + + assert payload_from_beats(client_observed) == client_payload + + +@cocotb.test() +async def udp_engine_server_tx_path_test(dut): + bench = await setup_udp_top_bench(dut) + + inbound_payload = b"udp-top-server-metadata" + inbound_frame = build_udp_rx_pseudo_frame( + remote_mac=LEGACY_MAC_WIRES[1], + remote_ip=LEGACY_IPS[1], + local_ip=LEGACY_IPS[0], + remote_port=0x4567, + local_port=8192, + payload=inbound_payload, + ) + inbound_send = cocotb.start_soon( + send_contiguous_frame(bench.udp_source, frame_beats_from_bytes(inbound_frame), clk=bench.clk) + ) + inbound_observed = await recv_frame( + bench.server_sink, + clk=bench.clk, + ready_signal=dut.mServerTReady, + timeout_cycles=64, + ) + await inbound_send + assert payload_from_beats(inbound_observed) == inbound_payload + + outbound_payload = b"udp-top-server-tx-path" + outbound_send = cocotb.start_soon( + send_contiguous_frame(bench.server_source, frame_beats_from_bytes(outbound_payload), clk=bench.clk) + ) + outbound_observed = await recv_frame( + bench.udp_sink, + clk=bench.clk, + ready_signal=dut.mUdpTReady, + timeout_cycles=64, + ) + await outbound_send + + assert payload_from_beats(outbound_observed) == build_udp_tx_pseudo_frame( + dst_mac=LEGACY_MAC_WIRES[1], + src_ip=LEGACY_IPS[0], + dst_ip=LEGACY_IPS[1], + src_port=8192, + dst_port=0x4567, + payload=outbound_payload, + ) + + @pytest.mark.parametrize("parameters", [pytest.param({}, id="udp_engine_top_flat_wrapper")]) def test_UdpEngine(parameters): run_surf_vhdl_test( diff --git a/tests/ethernet/UdpEngine/test_UdpEngineWrapper.py b/tests/ethernet/UdpEngine/test_UdpEngineWrapper.py index 5360bf7736..a9234c3939 100644 --- a/tests/ethernet/UdpEngine/test_UdpEngineWrapper.py +++ b/tests/ethernet/UdpEngine/test_UdpEngineWrapper.py @@ -9,13 +9,15 @@ ############################################################################## # Test methodology: -# - Sweep: Exercise the wrapper-specific AXI-Lite register bank alongside one -# inbound server-routing path through the integrated MAC/IPv4/UDP stack. +# - Sweep: Exercise the wrapper-specific AXI-Lite register bank plus inbound +# server and client routing through the integrated MAC/IPv4/UDP stack. # - Stimulus: Program the client configuration and soft-IP registers through -# AXI-Lite, then inject a UDP/IP/Ethernet frame addressed to the local host. +# AXI-Lite, then inject one server-targeted and one client-targeted +# UDP/IP/Ethernet frame addressed to the local host. # - Checks: AXI-Lite writes and reads must reflect the programmed values, the -# wrapper must route the UDP payload to the server output, and the server -# debug readbacks must report the remote endpoint that sent the packet. +# wrapper must route server and client traffic to the matching outputs, and +# the server debug readbacks must report the remote endpoint that sent the +# server packet. # - Timing: The test uses the wrapper's real AXI-Lite and AXIS interfaces so # register-bank behavior is verified in the same integration topology as RTL. @@ -88,6 +90,27 @@ async def udp_engine_wrapper_axil_and_server_path_test(dut): assert await axil_read_u32(bench.axil, 0x800) == port_config_word(0x4567) assert await axil_read_u32(bench.axil, 0x804) == ipv4_config_word(LEGACY_IPS[1]) + client_inbound = build_ipv4_udp_frame( + dst_mac=LEGACY_MAC_WIRES[0], + src_mac=LEGACY_MAC_WIRES[1], + src_ip=LEGACY_IPS[1], + dst_ip=LEGACY_IPS[0], + src_port=0x6789, + dst_port=8193, + payload=b"udp-wrapper-client-rx", + ) + client_inbound_send = cocotb.start_soon( + send_contiguous_frame(bench.mac_source, frame_beats_from_bytes(client_inbound), clk=bench.clk) + ) + client_observed = await recv_frame( + bench.client_sink, + clk=bench.clk, + ready_signal=dut.mClientTReady, + timeout_cycles=128, + ) + await client_inbound_send + assert payload_from_beats(client_observed) == b"udp-wrapper-client-rx" + @pytest.mark.parametrize("parameters", [pytest.param({}, id="udp_engine_wrapper_flat_wrapper")]) def test_UdpEngineWrapper(parameters): From 590b0c647aaf9638277fadace58d96dc0c761fe8 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 17 Apr 2026 14:50:14 -0700 Subject: [PATCH 20/92] Comments. --- docs/_meta/rtl_regression_handoff.md | 4 ++ docs/_meta/rtl_regression_plan.md | 3 + docs/_meta/rtl_regression_progress.md | 2 + .../ethernet/EthMacCore/ethmac_test_utils.py | 30 ++++++--- .../EthMacCore/test_EthMacRxBypass.py | 13 +++- .../EthMacCore/test_EthMacTxBypass.py | 20 ++++-- tests/ethernet/IpV4Engine/ipv4_test_utils.py | 59 +++++++++++++----- tests/ethernet/IpV4Engine/test_ArpEngine.py | 5 +- tests/ethernet/IpV4Engine/test_IcmpEngine.py | 16 ++--- .../ethernet/IpV4Engine/test_IgmpV2Engine.py | 5 +- tests/ethernet/IpV4Engine/test_IpV4Engine.py | 15 +++-- .../IpV4Engine/test_IpV4EngineDeMux.py | 15 +++-- .../ethernet/IpV4Engine/test_IpV4EngineRx.py | 21 ++++--- .../ethernet/IpV4Engine/test_IpV4EngineTx.py | 19 +++--- .../RawEthFramer/raw_eth_test_utils.py | 10 +++ tests/ethernet/UdpEngine/test_ArpIpTable.py | 16 +++-- tests/ethernet/UdpEngine/test_UdpEngine.py | 21 ++++--- .../ethernet/UdpEngine/test_UdpEngineDhcp.py | 17 +++-- tests/ethernet/UdpEngine/test_UdpEngineRx.py | 17 +++-- tests/ethernet/UdpEngine/test_UdpEngineTx.py | 8 ++- .../UdpEngine/test_UdpEngineWrapper.py | 32 ++++++---- tests/ethernet/UdpEngine/udp_test_utils.py | 62 +++++++++++++------ 22 files changed, 286 insertions(+), 124 deletions(-) diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index 6843f6ecce..d8a94c7a21 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -16,6 +16,7 @@ - Give each checked-in cocotb-facing `*IpIntegrator.vhd` wrapper the normal SURF file banner plus section comments for shim setup, DUT instantiation, and any flattening/status wiring - For any VHDL file created or edited during this work, run `./.venv/bin/vsg` with `vsg-linter.yml`, the same config CI uses, and use `--fix`/autofix on fixable issues before moving on - Treat VHDL packages as transitively covered unless a behavioral function/procedure needs a dedicated wrapper +- Treat stale simulator cleanup as part of task completion: after any `pytest`, cocotb, GHDL, or similar launched verification step, sweep for leftover child processes and kill them before moving on ## Quick Resume Snapshot - Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, and the current Ethernet coverage now spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, and `IpV4Engine`, including the recent thin-area cleanup across direct bypass leaves, broader top-level UDP/IPv4 paths, and deeper ICMP negatives. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. @@ -63,6 +64,7 @@ - `EthMacRxCsum` reliably raises `IPERR` on a bad IPv4 header checksum, but the checked-in wrapper contract does not currently require `EOFE` for that case. Keep the negative test aligned to the real observable contract rather than to a stronger assumption. - The RX/TX shift benches need a small idle-plus-settle gap before changing runtime shift controls because the underlying `AxiStreamShift` samples those controls while idle. Preserve that guardrail if those benches are refactored or expanded. - `EthMacRxBypass` compares the EtherType field in the flattened EMAC byte-lane order, not normal wire-order host integer order. In practice that means a wire EtherType like `0x9000` must be compared as `x"0090"` at the wrapper/DUT generic boundary, just as `0x88B5` appears as `x"B588"` in the existing wrappers. +- Do not leave stale simulation trees behind between tasks. If a verification command launched `pytest`, cocotb, GHDL, or wrapper executables, treat post-run process cleanup as mandatory before the next edit or test cycle. ## Current Status Planning is complete and implementation is well underway. The agreed direction is a Python-only executable regression framework with tiered `smoke` and `functional` coverage. Existing VHDL TBs are reference material only and should be rewritten in Python when migrated, unless a thin wrapper is still useful for cocotb access. @@ -167,6 +169,7 @@ Before writing code in a fresh session: 2. If adding a permanent `*IpIntegrator.vhd`, include the standard SURF banner and section comments in the first edit, not as an afterthought. 3. If adding a Python regression, include the standard SURF/SLAC header, the `Test methodology` header block, and in-body tutorial comments in the first draft. 4. If creating or editing any VHDL file, run `./.venv/bin/vsg -c vsg-linter.yml ...` on that file set, use `--fix` when possible, and rerun the same lint command until it is clean. +5. After any step that launches `pytest`, cocotb, GHDL, or another simulator process, sweep for stale child processes and kill any leftovers before starting the next step. ## Important Repo Facts - New Python regressions should be organized under subsystem packages in `tests/` @@ -190,6 +193,7 @@ Before writing code in a fresh session: - Use `./.venv/bin/python ...` for repo-local Python commands unless the virtualenv has already been activated in the current shell; do not assume a `python` shim exists on `PATH` - If GHDL rejects a direct command-line override for a non-scalar or real generic, prefer a generated thin test-only wrapper over simulator-specific literal workarounds or another checked-in one-off HDL shim - If a wrapper branch is unstable under the current open-source flow, keep the validated subset narrow and record the omitted branch explicitly in the docs instead of over-claiming wrapper coverage +- Use `ps -Ao pid,ppid,stat,time,command` when needed to find stale simulation children, then terminate only the leftover run trees instead of broad process classes - `LutFixedDelay` remains intentionally deferred because it depends on `SinglePortRamPrimitive`; do not accidentally treat the now-small remaining `base/` set as phase-1 work that still needs to be forced through - Regenerate the graph and the phase-1 queue with `./.venv/bin/python scripts/build_rtl_instantiation_graph.py` only when historical analysis is useful or the user explicitly asks for it - Local bootstrap entrypoint: `scripts/setup_regression_env.sh` diff --git a/docs/_meta/rtl_regression_plan.md b/docs/_meta/rtl_regression_plan.md index 06e88ac34f..724ae44cfa 100644 --- a/docs/_meta/rtl_regression_plan.md +++ b/docs/_meta/rtl_regression_plan.md @@ -73,6 +73,9 @@ - Separate `smoke` and `functional` regression tiers. - Shard by subsystem only if runtime requires it. - Keep room for PR-vs-nightly expansion later if runtime and coverage needs justify it. +- Treat simulator process cleanup as part of every verification step, not as optional housekeeping. +- After any command that launches `pytest`, cocotb, GHDL, or another simulation runner, check for stale child processes and kill any leftovers before moving on to the next step. +- When cleanup is needed, prefer an explicit process sweep first (for example with `ps -Ao pid,ppid,stat,time,command`) so only the stale run trees are terminated. ## Reuse Policy - Legacy VHDL testbenches are reference material only. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 3732f6a965..bac63eb236 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -13,6 +13,7 @@ - The current `verification-2` branch already includes the merged `pre-release` state through PR #1392, so the validated `protocols/ssi`, `protocols/pgp`, and current Ethernet waves (`EthMacCore`, `RawEthFramer`, `UdpEngine`, and `IpV4Engine`) are all part of the present branch snapshot. - The checked-in queue and override artifacts are now retained only as historical provenance and optional graph output; they are no longer the source of truth for choosing the next area. - Keep the done/open frontier in this progress file and in `docs/_meta/rtl_regression_handoff.md` aligned to the actual tree even if the queue artifacts are stale. + - Treat stale simulator cleanup as mandatory after every launched verification command: after any `pytest`, cocotb, GHDL, or similar simulation step, sweep for leftover child processes and kill them before starting the next task. - Known expected-open tests on this branch: - No simulator-friendly expected-open leaf tests remain in the currently covered `ethernet/IpV4Engine` slice, and the recent `EthMacCore` / `UdpEngine` thin-area follow-up is also checked in on this branch. - The current `EthMac*Xlgmii` import/export leaves are still placeholder no-op RTL, so the checked-in benches document that inert contract rather than claiming functional XLGMII datapath coverage. @@ -220,6 +221,7 @@ - The `axi/dma/rtl/v2/` benches are now intentionally split by behavior instead of repeatedly re-proving the same path through the top-level DMA stack: `AxiStreamDmaV2` and `AxiStreamDmaV2Desc` stay focused on descriptor-manager register/control surfaces, `AxiStreamDmaV2Read` owns aligned and short terminal-beat readout, `AxiStreamDmaV2Write` owns descriptor-return integrity plus burst splitting, `AxiStreamDmaV2WriteMux` owns arbitration ordering, and `AxiStreamDmaV2Fifo` owns the integrated FIFO register/count/pause-threshold surface. - For checked-in VHDL changes, use the repo virtualenv's `vsg` with `vsg-linter.yml` so local lint matches CI, and prefer `--fix` before manual spacing/alignment cleanup. - The current `EthMacCore` wave has a few wrapper-visible behavior details worth preserving in the docs instead of rediscovering later: the XGMII import/export loopback retains a frame presented during `phyReady=0` and drains it after link recovery with Ethernet minimum-size padding applied, while the GMII path drops it; `EthMacRxCsum` reliably asserts `IPERR` on a bad IPv4 header checksum but the checked-in wrapper contract does not require `EOFE` on that case; and the RX/TX shift benches need a small idle-plus-settle gap before changing runtime shift controls because the underlying `AxiStreamShift` samples those controls from its IDLE state. +- Verification hygiene now includes process cleanup: if a `pytest`/cocotb/GHDL step leaves stale run trees behind, kill those leftovers immediately before starting another compile or simulation command. ## Log - 2026-03-20: Agreed on Python-only executable regression logic and wrapper-only VHDL retention. diff --git a/tests/ethernet/EthMacCore/ethmac_test_utils.py b/tests/ethernet/EthMacCore/ethmac_test_utils.py index 2134141164..efe1c8dfc0 100644 --- a/tests/ethernet/EthMacCore/ethmac_test_utils.py +++ b/tests/ethernet/EthMacCore/ethmac_test_utils.py @@ -19,6 +19,8 @@ from cocotb.triggers import RisingEdge, Timer +# Shared EMAC helpers centralize the flattened lane ordering and the common +# packet builders used throughout `tests/ethernet/`. ETHMAC_RTL_SOURCES = [ str(path) for path in sorted((Path(__file__).resolve().parents[3] / "ethernet" / "EthMacCore" / "rtl").glob("*.vhd")) @@ -36,6 +38,13 @@ ), ] +ETH_TYPE_IPV4 = 0x0800 +IPV4_VERSION_IHL = 0x45 +IP_PROTOCOL_UDP = 0x11 +MAC_CONTROL_ETHERTYPE = 0x8808 +MAC_CONTROL_PAUSE_OPCODE = b"\x00\x01" +MAC_CONTROL_PAUSE_DST = 0x0180C2000001 + @dataclass class EmacBeat: @@ -168,6 +177,7 @@ class FlatEmacBench: def keep_mask(data_bytes: int) -> int: + # AXI `TKEEP` uses one asserted bit per valid byte lane. return (1 << data_bytes) - 1 @@ -203,6 +213,7 @@ def frame_beats_from_bytes( eofe: int = 0, frag: int = 0, ) -> list[EmacBeat]: + # The first beat carries `SOF`; only the final beat may carry `EOFE`. beats = [] offset = 0 while offset < len(data): @@ -277,8 +288,11 @@ def build_ipv4_header( ttl: int = 64, checksum_override: int | None = None, ) -> bytes: + # Emit the minimal IPv4 header shape used throughout these benches: + # version/IHL `0x45`, zero DSCP/ECN, zero fragment offset, then TTL and + # protocol before the checksum and address fields. total_length = 20 + payload_length - header_wo_checksum = bytes([0x45, 0x00]) + total_length.to_bytes(2, byteorder="big") + header_wo_checksum = bytes([IPV4_VERSION_IHL, 0x00]) + total_length.to_bytes(2, byteorder="big") header_wo_checksum += identification.to_bytes(2, byteorder="big") header_wo_checksum += b"\x00\x00" header_wo_checksum += bytes([ttl, protocol]) @@ -309,7 +323,7 @@ def build_udp_header( pseudo_header = ( ipv4_to_bytes(src_ip) + ipv4_to_bytes(dst_ip) - + bytes([0x00, 0x11]) + + bytes([0x00, IP_PROTOCOL_UDP]) + udp_length.to_bytes(2, byteorder="big") ) checksum = internet_checksum(pseudo_header + header_wo_checksum + payload) if checksum_override is None else checksum_override @@ -339,14 +353,14 @@ def build_ipv4_udp_frame( ipv4_header = build_ipv4_header( src_ip=src_ip, dst_ip=dst_ip, - protocol=0x11, + protocol=IP_PROTOCOL_UDP, payload_length=len(udp_header) + len(payload), checksum_override=ip_checksum_override, ) return build_ethernet_frame( dst_mac=dst_mac, src_mac=src_mac, - eth_type=0x0800, + eth_type=ETH_TYPE_IPV4, payload=ipv4_header + udp_header + payload, ) @@ -354,11 +368,11 @@ def build_ipv4_udp_frame( def build_pause_frame(pause_value: int) -> bytes: # The pause opcode and pause quanta are part of the MAC control payload, # which the TxPause block pads to Ethernet's 46-byte minimum payload. - payload = b"\x00\x01" + pause_value.to_bytes(2, byteorder="big") + bytes(42) + payload = MAC_CONTROL_PAUSE_OPCODE + pause_value.to_bytes(2, byteorder="big") + bytes(42) return build_ethernet_frame( - dst_mac=0x0180C2000001, + dst_mac=MAC_CONTROL_PAUSE_DST, src_mac=0x000000000000, - eth_type=0x8808, + eth_type=MAC_CONTROL_ETHERTYPE, payload=payload, ) @@ -442,6 +456,8 @@ async def send_frame_burst( async def recv_frame(endpoint: FlatEmacEndpoint, *, clk, ready_signal=None, timeout_cycles: int = 64) -> list[EmacBeat]: + # Collect a whole frame so tests can reason about packet-level behavior + # instead of stitching together beat-level observations themselves. beats = [] if ready_signal is not None: ready_signal.value = 1 diff --git a/tests/ethernet/EthMacCore/test_EthMacRxBypass.py b/tests/ethernet/EthMacCore/test_EthMacRxBypass.py index f6f73e80fa..6d1b2c9579 100644 --- a/tests/ethernet/EthMacCore/test_EthMacRxBypass.py +++ b/tests/ethernet/EthMacCore/test_EthMacRxBypass.py @@ -40,6 +40,9 @@ WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacRxBypassWrapper.vhd" +BYPASS_ETH_TYPE = 0x9000 +BYPASS_DEST_TAG = 0x23 +PRIMARY_DEST_TAG = 0x5A @cocotb.test() @@ -58,10 +61,13 @@ async def eth_mac_rx_bypass_routing_test(dut): bypass_frame = build_ethernet_frame( dst_mac=0x101112131415, src_mac=0x202122232425, - eth_type=0x9000, + # The wrapper programs `0x9000` as the bypass EtherType on the wire. + eth_type=BYPASS_ETH_TYPE, payload=bytes(range(48)), ) - bypass_expected = frame_beats_from_bytes(bypass_frame, dest=0x23, eofe=1) + # The wrapper stamps bypass traffic with `dest=0x23` and sets `EOFE` so + # downstream logic can identify that alternate route. + bypass_expected = frame_beats_from_bytes(bypass_frame, dest=BYPASS_DEST_TAG, eofe=1) bypass_send = cocotb.start_soon(send_contiguous_frame(source, bypass_expected, clk=bench.clk)) if bypass_enabled: @@ -81,7 +87,8 @@ async def eth_mac_rx_bypass_routing_test(dut): eth_type=0x88B5, payload=b"ethmac-rx-bypass-primary-path" + bytes(range(17)), ) - primary_expected = frame_beats_from_bytes(primary_frame, dest=0x5A) + # Non-bypass traffic keeps the normal primary-output destination tag. + primary_expected = frame_beats_from_bytes(primary_frame, dest=PRIMARY_DEST_TAG) primary_send = cocotb.start_soon(send_contiguous_frame(source, primary_expected, clk=bench.clk)) primary_observed = await recv_frame(prim_sink, clk=bench.clk, timeout_cycles=64) await primary_send diff --git a/tests/ethernet/EthMacCore/test_EthMacTxBypass.py b/tests/ethernet/EthMacCore/test_EthMacTxBypass.py index 3774ac0419..3c20966f05 100644 --- a/tests/ethernet/EthMacCore/test_EthMacTxBypass.py +++ b/tests/ethernet/EthMacCore/test_EthMacTxBypass.py @@ -41,6 +41,11 @@ WRAPPER_PATH = "ethernet/EthMacCore/wrappers/EthMacTxBypassWrapper.vhd" +BYPASS_ETH_TYPE = 0x9000 +PRIMARY_DEST_TAG_IDLE = 0x31 +BYPASS_DEST_TAG_IDLE = 0x72 +PRIMARY_DEST_TAG_BUSY = 0x44 +BYPASS_DEST_TAG_BUSY = 0x55 @cocotb.test() @@ -68,11 +73,14 @@ async def eth_mac_tx_bypass_arbitration_test(dut): bypass_frame = build_ethernet_frame( dst_mac=0x212223242526, src_mac=0x313233343536, - eth_type=0x9000, + # `0x9000` is the wrapper's configured bypass EtherType on the wire. + eth_type=BYPASS_ETH_TYPE, payload=b"tx-bypass-wins-idle" + bytes(range(29)), ) - primary_expected = frame_beats_from_bytes(primary_frame, dest=0x31) - bypass_expected = frame_beats_from_bytes(bypass_frame, dest=0x72, eofe=1) + # The wrapper exports distinct destination tags for the primary and bypass + # ingress ports so arbitration decisions are visible in the captured beats. + primary_expected = frame_beats_from_bytes(primary_frame, dest=PRIMARY_DEST_TAG_IDLE) + bypass_expected = frame_beats_from_bytes(bypass_frame, dest=BYPASS_DEST_TAG_IDLE, eofe=1) primary_send = cocotb.start_soon(send_contiguous_frame(prim_source, primary_expected, clk=bench.clk)) bypass_send = cocotb.start_soon(send_contiguous_frame(byp_source, bypass_expected, clk=bench.clk)) @@ -98,11 +106,11 @@ async def eth_mac_tx_bypass_arbitration_test(dut): late_bypass = build_ethernet_frame( dst_mac=0x616263646566, src_mac=0x717273747576, - eth_type=0x9000, + eth_type=BYPASS_ETH_TYPE, payload=b"late-bypass-frame" + bytes(range(24)), ) - long_primary_expected = frame_beats_from_bytes(long_primary, dest=0x44) - late_bypass_expected = frame_beats_from_bytes(late_bypass, dest=0x55) + long_primary_expected = frame_beats_from_bytes(long_primary, dest=PRIMARY_DEST_TAG_BUSY) + late_bypass_expected = frame_beats_from_bytes(late_bypass, dest=BYPASS_DEST_TAG_BUSY) long_primary_send = cocotb.start_soon(send_contiguous_frame(prim_source, long_primary_expected, clk=bench.clk)) await cycle(bench.clk, 2) diff --git a/tests/ethernet/IpV4Engine/ipv4_test_utils.py b/tests/ethernet/IpV4Engine/ipv4_test_utils.py index 6d071a3251..ee4b483c72 100644 --- a/tests/ethernet/IpV4Engine/ipv4_test_utils.py +++ b/tests/ethernet/IpV4Engine/ipv4_test_utils.py @@ -23,11 +23,31 @@ ) +# Centralize recurring IPv4/ARP/ICMP/IGMP protocol constants here so the tests +# can describe behavior without repeating low-level packet-literal trivia. IPV4_RTL_SOURCES = [ str(path) for path in sorted((Path(__file__).resolve().parents[3] / "ethernet" / "IpV4Engine" / "rtl").glob("*.vhd")) ] +ETH_TYPE_IPV4 = 0x0800 +ETH_TYPE_ARP = 0x0806 +IPV4_VERSION_IHL = 0x45 +IPV4_DEFAULT_TTL = 0x20 +IPV4_DF_FLAGS = b"\x40\x00" +IP_PROTOCOL_ICMP = 0x01 +IP_PROTOCOL_IGMP = 0x02 +IP_PROTOCOL_UDP = 0x11 +ARP_HTYPE_ETHERNET = 0x0001 +ARP_PTYPE_IPV4 = 0x0800 +ARP_HLEN_ETHERNET = 0x06 +ARP_PLEN_IPV4 = 0x04 +ARP_BROADCAST_MAC = 0xFFFFFFFFFFFF +ICMP_ECHO_REPLY = 0x00 +ICMP_ECHO_REQUEST = 0x08 +IGMP_MEMBERSHIP_QUERY = 0x11 +IGMP_V2_MEMBERSHIP_REPORT = 0x16 + def ipv4_config_word(address: str) -> int: # The flattened cocotb wrappers expose byte-stream traffic lane-first, so @@ -45,7 +65,7 @@ def build_ipv4_frame( protocol: int, payload: bytes, identification: int = 0x1234, - ttl: int = 0x20, + ttl: int = IPV4_DEFAULT_TTL, checksum_override: int | None = None, ) -> bytes: ipv4_header = build_ipv4_header( @@ -60,7 +80,7 @@ def build_ipv4_frame( return build_ethernet_frame( dst_mac=dst_mac, src_mac=src_mac, - eth_type=0x0800, + eth_type=ETH_TYPE_IPV4, payload=ipv4_header + payload, ) @@ -133,22 +153,23 @@ def build_ipv4_tx_wire_frame( protocol: int, payload: bytes, identification: int = 0x0000, - ttl: int = 0x20, + ttl: int = IPV4_DEFAULT_TTL, ) -> bytes: # IpV4EngineTx leaves the IPv4 total length and checksum fields clear for # downstream MAC checksum/length logic to repair. ipv4_header = ( - bytes([0x45, 0x00]) + bytes([IPV4_VERSION_IHL, 0x00]) + b"\x00\x00" + identification.to_bytes(2, byteorder="big") - + bytes([0x40, 0x00, ttl, protocol, 0x00, 0x00]) + + IPV4_DF_FLAGS + + bytes([ttl, protocol, 0x00, 0x00]) + ipv4_to_bytes(src_ip) + ipv4_to_bytes(dst_ip) ) return build_ethernet_frame( dst_mac=dst_mac, src_mac=src_mac, - eth_type=0x0800, + eth_type=ETH_TYPE_IPV4, payload=ipv4_header + payload, ) @@ -164,14 +185,14 @@ def build_arp_frame( src_mac: int | None = None, ) -> bytes: if dst_mac is None: - dst_mac = 0xFFFFFFFFFFFF if opcode == 1 else target_mac + dst_mac = ARP_BROADCAST_MAC if opcode == 1 else target_mac if src_mac is None: src_mac = sender_mac payload = ( - (0x0001).to_bytes(2, byteorder="big") - + (0x0800).to_bytes(2, byteorder="big") - + bytes([0x06, 0x04]) + ARP_HTYPE_ETHERNET.to_bytes(2, byteorder="big") + + ARP_PTYPE_IPV4.to_bytes(2, byteorder="big") + + bytes([ARP_HLEN_ETHERNET, ARP_PLEN_IPV4]) + opcode.to_bytes(2, byteorder="big") + mac_to_bytes(sender_mac) + ipv4_to_bytes(sender_ip) @@ -181,7 +202,7 @@ def build_arp_frame( return build_ethernet_frame( dst_mac=dst_mac, src_mac=src_mac, - eth_type=0x0806, + eth_type=ETH_TYPE_ARP, payload=payload, ) @@ -191,7 +212,7 @@ def build_icmp_echo_packet( payload: bytes, identifier: int = 0x1234, sequence: int = 0x0001, - icmp_type: int = 0x08, + icmp_type: int = ICMP_ECHO_REQUEST, code: int = 0x00, ) -> bytes: header_wo_checksum = bytes([icmp_type, code]) + b"\x00\x00" @@ -217,7 +238,7 @@ def build_icmp_echo_reply_packet( payload=payload, identifier=identifier, sequence=sequence, - icmp_type=0x00, + icmp_type=ICMP_ECHO_REPLY, code=0x00, ) @@ -236,7 +257,7 @@ def build_icmp_echo_frame( payload=payload, identifier=identifier, sequence=sequence, - icmp_type=0x08, + icmp_type=ICMP_ECHO_REQUEST, code=0x00, ) return build_ipv4_frame( @@ -244,7 +265,7 @@ def build_icmp_echo_frame( src_mac=src_mac, src_ip=src_ip, dst_ip=dst_ip, - protocol=0x01, + protocol=IP_PROTOCOL_ICMP, payload=icmp_payload, ) @@ -257,6 +278,8 @@ def build_igmp_packet( checksum_override: int | None = None, ) -> bytes: group_ip_bytes = ipv4_to_bytes(group_ip) + # IGMPv2 packets are always a fixed 8 bytes: type, max-response-time, + # checksum, and group address. header_wo_checksum = bytes([igmp_type & 0xFF, max_resp_time & 0xFF]) + b"\x00\x00" + group_ip_bytes checksum = internet_checksum(header_wo_checksum) if checksum_override is None else checksum_override return bytes([igmp_type & 0xFF, max_resp_time & 0xFF]) + checksum.to_bytes(2, byteorder="big") + group_ip_bytes @@ -269,7 +292,7 @@ def build_igmp_membership_query_packet( checksum_override: int | None = None, ) -> bytes: return build_igmp_packet( - igmp_type=0x11, + igmp_type=IGMP_MEMBERSHIP_QUERY, max_resp_time=max_resp_time, group_ip=group_ip, checksum_override=checksum_override, @@ -282,7 +305,7 @@ def build_igmp_membership_report_packet( checksum_override: int | None = None, ) -> bytes: return build_igmp_packet( - igmp_type=0x16, + igmp_type=IGMP_V2_MEMBERSHIP_REPORT, max_resp_time=0x00, group_ip=group_ip, checksum_override=checksum_override, @@ -290,6 +313,8 @@ def build_igmp_membership_report_packet( def igmp_group_mac(group_ip: str) -> int: + # IPv4 multicast maps onto the Ethernet 01:00:5E prefix with the top bit + # of the group address dropped. group_ip_bytes = ipv4_to_bytes(group_ip) return int.from_bytes(b"\x01\x00\x5E" + group_ip_bytes[1:], byteorder="big") diff --git a/tests/ethernet/IpV4Engine/test_ArpEngine.py b/tests/ethernet/IpV4Engine/test_ArpEngine.py index 29b18cc214..c1a838f545 100644 --- a/tests/ethernet/IpV4Engine/test_ArpEngine.py +++ b/tests/ethernet/IpV4Engine/test_ArpEngine.py @@ -37,6 +37,7 @@ setup_flat_emac_testbench, ) from tests.ethernet.IpV4Engine.ipv4_test_utils import ( + ARP_BROADCAST_MAC, IPV4_RTL_SOURCES, build_arp_frame, ipv4_config_word, @@ -111,7 +112,7 @@ async def arp_engine_remote_lookup_ack_test(dut): opcode=1, sender_mac=LOCAL_MAC_WIRE, sender_ip=LOCAL_IP, - target_mac=0xFFFFFFFFFFFF, + target_mac=ARP_BROADCAST_MAC, target_ip=REMOTE_IP, ) assert payload_from_beats(request_observed) == request_expected @@ -145,7 +146,7 @@ async def arp_engine_inbound_request_reply_test(dut): opcode=1, sender_mac=REMOTE_MAC_WIRE, sender_ip=REMOTE_IP, - target_mac=0xFFFFFFFFFFFF, + target_mac=ARP_BROADCAST_MAC, target_ip=LOCAL_IP, ) request_send = cocotb.start_soon( diff --git a/tests/ethernet/IpV4Engine/test_IcmpEngine.py b/tests/ethernet/IpV4Engine/test_IcmpEngine.py index 9dbf2e0a37..bcdad8845b 100644 --- a/tests/ethernet/IpV4Engine/test_IcmpEngine.py +++ b/tests/ethernet/IpV4Engine/test_IcmpEngine.py @@ -37,6 +37,8 @@ setup_flat_emac_testbench, ) from tests.ethernet.IpV4Engine.ipv4_test_utils import ( + ICMP_ECHO_REQUEST, + IP_PROTOCOL_ICMP, IPV4_RTL_SOURCES, build_icmp_echo_packet, build_icmp_echo_reply_packet, @@ -78,7 +80,7 @@ async def icmp_engine_reply_filtering_test(dut): src_mac=REMOTE_MAC, src_ip=REMOTE_IP, dst_ip=LOCAL_IP, - protocol=0x01, + protocol=IP_PROTOCOL_ICMP, payload=build_icmp_echo_packet( payload=echo_payload, identifier=0x3344, @@ -92,7 +94,7 @@ async def icmp_engine_reply_filtering_test(dut): dst_mac=REMOTE_MAC, src_ip=LOCAL_IP, dst_ip=REMOTE_IP, - protocol=0x01, + protocol=IP_PROTOCOL_ICMP, payload=build_icmp_echo_reply_packet( payload=echo_payload, identifier=0x3344, @@ -117,7 +119,7 @@ async def icmp_engine_reply_filtering_test(dut): src_mac=REMOTE_MAC, src_ip=REMOTE_IP, dst_ip=LOCAL_IP, - protocol=0x01, + protocol=IP_PROTOCOL_ICMP, payload=build_icmp_echo_packet( payload=b"", identifier=0x0101, @@ -134,7 +136,7 @@ async def icmp_engine_reply_filtering_test(dut): src_mac=REMOTE_MAC, src_ip=REMOTE_IP, dst_ip="192.168.20.99", - protocol=0x01, + protocol=IP_PROTOCOL_ICMP, payload=build_icmp_echo_packet(payload=b"non-local"), ) await send_contiguous_frame(source, frame_beats_from_bytes(non_local_request), clk=bench.clk) @@ -144,7 +146,7 @@ async def icmp_engine_reply_filtering_test(dut): src_mac=REMOTE_MAC, src_ip=REMOTE_IP, dst_ip=LOCAL_IP, - protocol=0x01, + protocol=IP_PROTOCOL_ICMP, payload=build_icmp_echo_packet( payload=b"not-an-echo-request", icmp_type=0x03, @@ -160,7 +162,7 @@ async def icmp_engine_reply_filtering_test(dut): src_mac=REMOTE_MAC, src_ip=REMOTE_IP, dst_ip=LOCAL_IP, - protocol=0x01, + protocol=IP_PROTOCOL_ICMP, payload=build_icmp_echo_packet( payload=second_payload, identifier=0x5566, @@ -173,7 +175,7 @@ async def icmp_engine_reply_filtering_test(dut): dst_mac=REMOTE_MAC, src_ip=LOCAL_IP, dst_ip=REMOTE_IP, - protocol=0x01, + protocol=IP_PROTOCOL_ICMP, payload=build_icmp_echo_reply_packet( payload=second_payload, identifier=0x5566, diff --git a/tests/ethernet/IpV4Engine/test_IgmpV2Engine.py b/tests/ethernet/IpV4Engine/test_IgmpV2Engine.py index d769050465..f6f087437b 100644 --- a/tests/ethernet/IpV4Engine/test_IgmpV2Engine.py +++ b/tests/ethernet/IpV4Engine/test_IgmpV2Engine.py @@ -39,6 +39,7 @@ setup_flat_emac_testbench, ) from tests.ethernet.IpV4Engine.ipv4_test_utils import ( + IP_PROTOCOL_IGMP, IPV4_RTL_SOURCES, build_igmp_membership_query_packet, build_igmp_membership_report_packet, @@ -111,7 +112,7 @@ def general_query_frame(*, checksum_override: int | None = None) -> bytes: src_mac=ROUTER_MAC, src_ip=ROUTER_IP, dst_ip="224.0.0.1", - protocol=0x02, + protocol=IP_PROTOCOL_IGMP, payload=build_igmp_membership_query_packet( max_resp_time=0x02, group_ip="0.0.0.0", @@ -125,7 +126,7 @@ def inbound_membership_report_frame(*, group_ip: str) -> bytes: src_mac=OTHER_HOST_MAC, src_ip=OTHER_HOST_IP, dst_ip=group_ip, - protocol=0x02, + protocol=IP_PROTOCOL_IGMP, payload=build_igmp_membership_report_packet(group_ip=group_ip), ) diff --git a/tests/ethernet/IpV4Engine/test_IpV4Engine.py b/tests/ethernet/IpV4Engine/test_IpV4Engine.py index 425364ca8b..ee1565e754 100644 --- a/tests/ethernet/IpV4Engine/test_IpV4Engine.py +++ b/tests/ethernet/IpV4Engine/test_IpV4Engine.py @@ -39,6 +39,9 @@ setup_flat_emac_testbench, ) from tests.ethernet.IpV4Engine.ipv4_test_utils import ( + ARP_BROADCAST_MAC, + IP_PROTOCOL_ICMP, + IP_PROTOCOL_UDP, IPV4_RTL_SOURCES, build_arp_frame, build_icmp_echo_frame, @@ -104,14 +107,14 @@ async def ipv4_top_udp_routing_test(dut): src_mac=REMOTE_MAC_WIRE, src_ip=REMOTE_IP, dst_ip=LOCAL_IP, - protocol=0x11, + protocol=IP_PROTOCOL_UDP, payload=udp_payload, ) udp_expected = build_ipv4_rx_pseudo_frame( src_mac=REMOTE_MAC_WIRE, src_ip=REMOTE_IP, dst_ip=LOCAL_IP, - protocol=0x11, + protocol=IP_PROTOCOL_UDP, payload=udp_payload, ) @@ -143,7 +146,7 @@ async def ipv4_top_protocol_tx_path_test(dut): dst_mac=REMOTE_MAC_WIRE, src_ip=LOCAL_IP, dst_ip=REMOTE_IP, - protocol=0x11, + protocol=IP_PROTOCOL_UDP, payload=udp_payload, ) tx_expected = build_ipv4_tx_wire_frame( @@ -151,7 +154,7 @@ async def ipv4_top_protocol_tx_path_test(dut): src_mac=LOCAL_MAC_WIRE, src_ip=LOCAL_IP, dst_ip=REMOTE_IP, - protocol=0x11, + protocol=IP_PROTOCOL_UDP, payload=udp_payload, ) @@ -186,7 +189,7 @@ async def ipv4_top_icmp_echo_reply_test(dut): src_mac=LOCAL_MAC_WIRE, src_ip=LOCAL_IP, dst_ip=REMOTE_IP, - protocol=0x01, + protocol=IP_PROTOCOL_ICMP, payload=build_icmp_echo_reply_packet( payload=b"top-level-icmp", identifier=0x7788, @@ -225,7 +228,7 @@ async def ipv4_top_arp_client_round_trip_test(dut): opcode=1, sender_mac=LOCAL_MAC_WIRE, sender_ip=LOCAL_IP, - target_mac=0xFFFFFFFFFFFF, + target_mac=ARP_BROADCAST_MAC, target_ip=REMOTE_IP, ) assert payload_from_beats(arp_request_observed) == arp_request_expected diff --git a/tests/ethernet/IpV4Engine/test_IpV4EngineDeMux.py b/tests/ethernet/IpV4Engine/test_IpV4EngineDeMux.py index 78f27e0c4e..0b76e26b8c 100644 --- a/tests/ethernet/IpV4Engine/test_IpV4EngineDeMux.py +++ b/tests/ethernet/IpV4Engine/test_IpV4EngineDeMux.py @@ -36,6 +36,9 @@ setup_flat_emac_testbench, ) from tests.ethernet.IpV4Engine.ipv4_test_utils import ( + ARP_BROADCAST_MAC, + IP_PROTOCOL_UDP, + IPV4_VERSION_IHL, IPV4_RTL_SOURCES, build_arp_frame, build_ipv4_frame, @@ -72,7 +75,7 @@ async def ipv4_demux_routes_and_drops_test(dut): opcode=1, sender_mac=REMOTE_MAC_WIRE, sender_ip="192.168.10.10", - target_mac=0xFFFFFFFFFFFF, + target_mac=ARP_BROADCAST_MAC, target_ip="192.168.10.20", ) arp_send = cocotb.start_soon( @@ -89,11 +92,11 @@ async def ipv4_demux_routes_and_drops_test(dut): await expect_no_output(ipv4_sink, clk=bench.clk, cycles=8) broadcast_ipv4 = build_ipv4_frame( - dst_mac=0xFFFFFFFFFFFF, + dst_mac=ARP_BROADCAST_MAC, src_mac=REMOTE_MAC_WIRE, src_ip="192.168.10.10", dst_ip="192.168.10.20", - protocol=0x11, + protocol=IP_PROTOCOL_UDP, payload=b"demux-broadcast-ipv4-payload", ) ipv4_send = cocotb.start_soon( @@ -114,7 +117,7 @@ async def ipv4_demux_routes_and_drops_test(dut): src_mac=REMOTE_MAC_WIRE, src_ip="192.168.10.10", dst_ip="192.168.10.20", - protocol=0x11, + protocol=IP_PROTOCOL_UDP, payload=b"foreign-destination-drop", ) await send_contiguous_frame(source, frame_beats_from_bytes(foreign_ipv4), clk=bench.clk) @@ -127,12 +130,12 @@ async def ipv4_demux_routes_and_drops_test(dut): src_mac=REMOTE_MAC_WIRE, src_ip="192.168.10.10", dst_ip="192.168.10.20", - protocol=0x11, + protocol=IP_PROTOCOL_UDP, payload=b"bad-version-drop", ) ) # The de-mux only accepts IPv4 version/header-length byte 0x45. - bad_version_ipv4[14] = 0x46 + bad_version_ipv4[14] = IPV4_VERSION_IHL + 1 await send_contiguous_frame(source, frame_beats_from_bytes(bytes(bad_version_ipv4)), clk=bench.clk) await expect_no_output(arp_sink, clk=bench.clk, cycles=12) await expect_no_output(ipv4_sink, clk=bench.clk, cycles=12) diff --git a/tests/ethernet/IpV4Engine/test_IpV4EngineRx.py b/tests/ethernet/IpV4Engine/test_IpV4EngineRx.py index 0502476575..4ad9b0ec72 100644 --- a/tests/ethernet/IpV4Engine/test_IpV4EngineRx.py +++ b/tests/ethernet/IpV4Engine/test_IpV4EngineRx.py @@ -35,6 +35,8 @@ setup_flat_emac_testbench, ) from tests.ethernet.IpV4Engine.ipv4_test_utils import ( + IP_PROTOCOL_ICMP, + IP_PROTOCOL_UDP, IPV4_RTL_SOURCES, build_icmp_echo_packet, build_ipv4_frame, @@ -44,6 +46,9 @@ WRAPPER_PATH = "ethernet/IpV4Engine/wrappers/IpV4EngineRxWrapper.vhd" +UNSUPPORTED_PROTOCOL = 0x99 +UDP_REMOTE_PORT = 0x1234 +UDP_LOCAL_PORT = 0x5678 LOCAL_MAC = 0x001122334455 REMOTE_MAC = 0x665544332211 @@ -70,8 +75,8 @@ async def ipv4_rx_routes_protocol_slots_test(dut): icmp_sink = FlatEmacEndpoint(dut, prefix="mIcmp") udp_payload = build_ipv4_udp_payload( - src_port=0x1234, - dst_port=0x5678, + src_port=UDP_REMOTE_PORT, + dst_port=UDP_LOCAL_PORT, payload=b"udp-payload-through-rx", src_ip=REMOTE_IP, dst_ip=LOCAL_IP, @@ -81,14 +86,14 @@ async def ipv4_rx_routes_protocol_slots_test(dut): src_mac=REMOTE_MAC, src_ip=REMOTE_IP, dst_ip=LOCAL_IP, - protocol=0x11, + protocol=IP_PROTOCOL_UDP, payload=udp_payload, ) udp_expected = build_ipv4_rx_pseudo_frame( src_mac=REMOTE_MAC, src_ip=REMOTE_IP, dst_ip=LOCAL_IP, - protocol=0x11, + protocol=IP_PROTOCOL_UDP, payload=udp_payload, ) @@ -115,14 +120,14 @@ async def ipv4_rx_routes_protocol_slots_test(dut): src_mac=REMOTE_MAC, src_ip=REMOTE_IP, dst_ip=LOCAL_IP, - protocol=0x01, + protocol=IP_PROTOCOL_ICMP, payload=icmp_payload, ) icmp_expected = build_ipv4_rx_pseudo_frame( src_mac=REMOTE_MAC, src_ip=REMOTE_IP, dst_ip=LOCAL_IP, - protocol=0x01, + protocol=IP_PROTOCOL_ICMP, payload=icmp_payload, ) @@ -144,7 +149,9 @@ async def ipv4_rx_routes_protocol_slots_test(dut): src_mac=REMOTE_MAC, src_ip=REMOTE_IP, dst_ip=LOCAL_IP, - protocol=0x99, + # `0x99` is just an arbitrary unsupported protocol ID so the drop path + # is clearly distinct from UDP (`0x11`) and ICMP (`0x01`). + protocol=UNSUPPORTED_PROTOCOL, payload=b"unsupported-protocol-drop", ) await send_contiguous_frame(source, frame_beats_from_bytes(unsupported_frame), clk=bench.clk) diff --git a/tests/ethernet/IpV4Engine/test_IpV4EngineTx.py b/tests/ethernet/IpV4Engine/test_IpV4EngineTx.py index 4431101e03..54eb654c25 100644 --- a/tests/ethernet/IpV4Engine/test_IpV4EngineTx.py +++ b/tests/ethernet/IpV4Engine/test_IpV4EngineTx.py @@ -36,6 +36,7 @@ setup_flat_emac_testbench, ) from tests.ethernet.IpV4Engine.ipv4_test_utils import ( + IP_PROTOCOL_UDP, IPV4_RTL_SOURCES, build_ipv4_tx_pseudo_frame, build_ipv4_tx_wire_frame, @@ -44,6 +45,8 @@ WRAPPER_PATH = "ethernet/IpV4Engine/wrappers/IpV4EngineTxWrapper.vhd" +REMOTE_TIMEOUT_CYCLES = 128 +LOCALHOST_IDENTIFICATION = 0x0001 LOCAL_MAC_WIRE = 0x001122334455 LOCAL_MAC_CFG = mac_config_word_from_wire(LOCAL_MAC_WIRE) @@ -82,7 +85,7 @@ async def ipv4_tx_generates_wire_and_localhost_paths_test(dut): dst_mac=REMOTE_MAC_WIRE, src_ip=LOCAL_IP, dst_ip=REMOTE_IP, - protocol=0x11, + protocol=IP_PROTOCOL_UDP, payload=udp_payload, ) remote_expected = build_ipv4_tx_wire_frame( @@ -90,7 +93,7 @@ async def ipv4_tx_generates_wire_and_localhost_paths_test(dut): src_mac=LOCAL_MAC_WIRE, src_ip=LOCAL_IP, dst_ip=REMOTE_IP, - protocol=0x11, + protocol=IP_PROTOCOL_UDP, payload=udp_payload, ) @@ -101,7 +104,7 @@ async def ipv4_tx_generates_wire_and_localhost_paths_test(dut): wire_sink, clk=bench.clk, ready_signal=dut.mIpv4TReady, - timeout_cycles=128, + timeout_cycles=REMOTE_TIMEOUT_CYCLES, ) await remote_send assert payload_from_beats(remote_observed) == remote_expected @@ -118,7 +121,7 @@ async def ipv4_tx_generates_wire_and_localhost_paths_test(dut): dst_mac=LOCAL_MAC_WIRE, src_ip=LOCAL_IP, dst_ip="192.168.40.99", - protocol=0x11, + protocol=IP_PROTOCOL_UDP, payload=localhost_payload, ) localhost_expected = build_ipv4_tx_wire_frame( @@ -126,9 +129,11 @@ async def ipv4_tx_generates_wire_and_localhost_paths_test(dut): src_mac=LOCAL_MAC_WIRE, src_ip=LOCAL_IP, dst_ip="192.168.40.99", - protocol=0x11, + # The localhost-shortcut path still emits the IPv4/UDP frame shape, but + # it increments the internal IPv4 identification counter to `0x0001`. + protocol=IP_PROTOCOL_UDP, payload=localhost_payload, - identification=0x0001, + identification=LOCALHOST_IDENTIFICATION, ) local_send = cocotb.start_soon( @@ -138,7 +143,7 @@ async def ipv4_tx_generates_wire_and_localhost_paths_test(dut): local_sink, clk=bench.clk, ready_signal=dut.mLocalTReady, - timeout_cycles=128, + timeout_cycles=REMOTE_TIMEOUT_CYCLES, ) await local_send assert payload_from_beats(local_observed) == localhost_expected diff --git a/tests/ethernet/RawEthFramer/raw_eth_test_utils.py b/tests/ethernet/RawEthFramer/raw_eth_test_utils.py index 395f0c07a7..f0ff29fe35 100644 --- a/tests/ethernet/RawEthFramer/raw_eth_test_utils.py +++ b/tests/ethernet/RawEthFramer/raw_eth_test_utils.py @@ -27,6 +27,8 @@ setup_flat_emac_testbench, ) +# These helpers model the RawEthFramer private application stream, including +# the two-byte header the DUT inserts between EtherType and payload. RAWETH_RTL_SOURCES = [ str(path) for path in sorted((Path(__file__).resolve().parents[3] / "ethernet" / "RawEthFramer" / "rtl").glob("*.vhd")) @@ -39,7 +41,10 @@ REMOTE_MAC_CFG = mac_config_word_from_wire(REMOTE_MAC_WIRE) ALT_REMOTE_MAC_WIRE = 0x102132435465 ALT_REMOTE_MAC_CFG = mac_config_word_from_wire(ALT_REMOTE_MAC_WIRE) +# RawEthFramer stores EtherType lane-first at the config boundary, so the wire +# value `0x1000` appears here as `0x0010`. ETH_TYPE_CFG = 0x0010 +# The flattened raw-app wrappers are 64 bits wide. RAWETH_BEAT_BYTES = 8 @@ -178,6 +183,9 @@ def pad_to_raw_eth_lane_width(payload: bytes, *, lane_bytes: int = RAWETH_BEAT_B def raweth_header_bytes(*, dest: int, bcf: int, min_byte_count: int) -> bytes: + # Header byte 0 packs the broadcast-copy flag in bit 7 and the low 7 bits + # of the minimum-byte-count field in bits [6:0]. Byte 1 is the lookup + # destination index. return bytes([((bcf & 0x1) << 7) | (min_byte_count & 0x7F), dest & 0xFF]) @@ -201,6 +209,8 @@ def build_raw_eth_wire_frame( def remote_mac_axil_addr(dest: int, *, high: bool = False) -> int: + # Each destination slot consumes 8 bytes in AXI-Lite space: low word at + # `dest << 3`, high word four bytes later. return (dest << 3) | (4 if high else 0) diff --git a/tests/ethernet/UdpEngine/test_ArpIpTable.py b/tests/ethernet/UdpEngine/test_ArpIpTable.py index 753e52a1ad..dc2c2c0264 100644 --- a/tests/ethernet/UdpEngine/test_ArpIpTable.py +++ b/tests/ethernet/UdpEngine/test_ArpIpTable.py @@ -36,6 +36,9 @@ WRAPPER_PATH = "ethernet/UdpEngine/wrappers/ArpIpTableFlatWrapper.vhd" +POS_IP_MATCH_LOOKUP = 0 +POS_TABLE_ENTRY0 = 1 +EXPIRATION_WAIT_CYCLES = 24 @cocotb.test() @@ -49,14 +52,15 @@ async def arp_ip_table_lookup_by_ip_and_position_test(dut): dut.macWrAddr.value = LEGACY_MAC_CFGS[1] await pulse_signal(dut.macWrEn, clk=bench.clk) - # `pos=0` uses IP-match lookup while `pos=1` directly addresses entry 0. + # `pos=0` uses IP-match lookup while `pos=1` directly addresses entry 0 in + # the small wrapper-configured table. dut.ipAddrIn.value = LEGACY_IP_CFGS[1] - dut.pos.value = 0 + dut.pos.value = POS_IP_MATCH_LOOKUP await cycle(bench.clk, 1) assert int(dut.found.value) == 1 assert int(dut.macAddr.value) == LEGACY_MAC_CFGS[1] - dut.pos.value = 1 + dut.pos.value = POS_TABLE_ENTRY0 await cycle(bench.clk, 1) assert int(dut.found.value) == 1 assert int(dut.macAddr.value) == LEGACY_MAC_CFGS[1] @@ -76,9 +80,9 @@ async def arp_ip_table_expiration_reclaims_entry_test(dut): # With the wrapper's tiny timing generics the entry should expire after a # handful of clock cycles if no inbound traffic refreshes the timer. - await cycle(bench.clk, 24) + await cycle(bench.clk, EXPIRATION_WAIT_CYCLES) dut.ipAddrIn.value = LEGACY_IP_CFGS[1] - dut.pos.value = 0 + dut.pos.value = POS_IP_MATCH_LOOKUP await cycle(bench.clk, 2) assert int(dut.found.value) == 0 @@ -91,7 +95,7 @@ async def arp_ip_table_expiration_reclaims_entry_test(dut): await pulse_signal(dut.macWrEn, clk=bench.clk) dut.ipAddrIn.value = LEGACY_IP_CFGS[1] - dut.pos.value = 0 + dut.pos.value = POS_IP_MATCH_LOOKUP await cycle(bench.clk, 2) assert int(dut.found.value) == 0 diff --git a/tests/ethernet/UdpEngine/test_UdpEngine.py b/tests/ethernet/UdpEngine/test_UdpEngine.py index 39fbd43214..b560521e42 100644 --- a/tests/ethernet/UdpEngine/test_UdpEngine.py +++ b/tests/ethernet/UdpEngine/test_UdpEngine.py @@ -40,6 +40,8 @@ LEGACY_IPS, LEGACY_MAC_WIRES, UDP_RTL_SOURCES, + UDP_CLIENT_PORT, + UDP_SERVER_PORT, build_udp_rx_pseudo_frame, build_udp_tx_pseudo_frame, ipv4_to_bytes, @@ -48,6 +50,7 @@ WRAPPER_PATH = "ethernet/UdpEngine/wrappers/UdpEngineTopFlatWrapper.vhd" +ARP_RESOLUTION_LATENCY_CYCLES = 6 @cocotb.test() @@ -65,7 +68,9 @@ async def udp_engine_client_arp_then_transmit_test(dut): # Feed back the learned MAC so the client-side transmit path can continue. arp_ack = frame_beats_from_bytes(LEGACY_MAC_WIRES[1].to_bytes(6, byteorder="big")) ack_send = cocotb.start_soon(send_contiguous_frame(bench.arp_ack_source, arp_ack, clk=bench.clk)) - await cycle(bench.clk, 6) + # The integrated top samples the ARP-ack stream a few cycles after the + # request appears, so hold the reply stable across that short window. + await cycle(bench.clk, ARP_RESOLUTION_LATENCY_CYCLES) await ack_send # Once ARP is resolved, the outbound client payload should emerge on the @@ -86,8 +91,8 @@ async def udp_engine_client_arp_then_transmit_test(dut): dst_mac=LEGACY_MAC_WIRES[1], src_ip=LEGACY_IPS[0], dst_ip=LEGACY_IPS[1], - src_port=8193, - dst_port=8192, + src_port=UDP_CLIENT_PORT, + dst_port=UDP_SERVER_PORT, payload=client_payload, ) @@ -104,7 +109,7 @@ async def udp_engine_server_rx_path_test(dut): remote_ip=LEGACY_IPS[1], local_ip=LEGACY_IPS[0], remote_port=0x4567, - local_port=8192, + local_port=UDP_SERVER_PORT, payload=server_payload, ) server_send = cocotb.start_soon( @@ -131,7 +136,7 @@ async def udp_engine_client_rx_path_test(dut): remote_ip=LEGACY_IPS[1], local_ip=LEGACY_IPS[0], remote_port=0x6789, - local_port=8193, + local_port=UDP_CLIENT_PORT, payload=client_payload, ) client_send = cocotb.start_soon( @@ -158,7 +163,7 @@ async def udp_engine_server_tx_path_test(dut): remote_ip=LEGACY_IPS[1], local_ip=LEGACY_IPS[0], remote_port=0x4567, - local_port=8192, + local_port=UDP_SERVER_PORT, payload=inbound_payload, ) inbound_send = cocotb.start_soon( @@ -189,7 +194,9 @@ async def udp_engine_server_tx_path_test(dut): dst_mac=LEGACY_MAC_WIRES[1], src_ip=LEGACY_IPS[0], dst_ip=LEGACY_IPS[1], - src_port=8192, + # The server reply reuses the socket learned from the inbound server + # packet, so the local source port stays on the fixed server socket. + src_port=UDP_SERVER_PORT, dst_port=0x4567, payload=outbound_payload, ) diff --git a/tests/ethernet/UdpEngine/test_UdpEngineDhcp.py b/tests/ethernet/UdpEngine/test_UdpEngineDhcp.py index 98dabc73d8..640837ba5e 100644 --- a/tests/ethernet/UdpEngine/test_UdpEngineDhcp.py +++ b/tests/ethernet/UdpEngine/test_UdpEngineDhcp.py @@ -32,6 +32,10 @@ send_contiguous_frame, ) from tests.ethernet.UdpEngine.udp_test_utils import ( + DHCP_ACK, + DHCP_DISCOVER, + DHCP_OFFER, + DHCP_REQUEST, LEGACY_IPS, LEGACY_MAC_WIRES, UDP_RTL_SOURCES, @@ -46,6 +50,7 @@ WRAPPER_PATH = "ethernet/UdpEngine/wrappers/UdpEngineDhcpFlatWrapper.vhd" +DHCP_ACK_PUBLISH_TIMEOUT_CYCLES = 128 @cocotb.test() @@ -62,12 +67,12 @@ async def udp_engine_dhcp_offer_ack_sequence_test(dut): ) discover_payload = payload_from_beats(discover_observed) discover_xid = extract_dhcp_xid(discover_payload) - assert extract_dhcp_message_type(discover_payload) == 1 + assert extract_dhcp_message_type(discover_payload) == DHCP_DISCOVER # A matching offer should move the state machine into the request phase # while preserving the same DHCP transaction identifier. offer_payload = build_dhcp_reply_payload( - message_type=2, + message_type=DHCP_OFFER, xid=discover_xid, client_mac=LEGACY_MAC_WIRES[0], yiaddr="192.168.2.44", @@ -85,14 +90,14 @@ async def udp_engine_dhcp_offer_ack_sequence_test(dut): await offer_send request_payload = payload_from_beats(request_observed) request_xid = extract_dhcp_xid(request_payload) - assert extract_dhcp_message_type(request_payload) == 3 + assert extract_dhcp_message_type(request_payload) == DHCP_REQUEST assert extract_dhcp_requested_ip(request_payload) == "192.168.2.44" assert extract_dhcp_server_identifier(request_payload) == LEGACY_IPS[1] # The ack is the step that should finally publish the leased IP address on # the wrapper-visible `dhcpIp` output. ack_payload = build_dhcp_reply_payload( - message_type=5, + message_type=DHCP_ACK, xid=request_xid, client_mac=LEGACY_MAC_WIRES[0], yiaddr="192.168.2.44", @@ -102,7 +107,9 @@ async def udp_engine_dhcp_offer_ack_sequence_test(dut): send_contiguous_frame(bench.source, frame_beats_from_bytes(ack_payload), clk=bench.clk) ) await ack_send - for _ in range(128): + # The wrapper uses shortened DHCP timers, but the published lease still + # appears asynchronously a few cycles after the ACK frame is accepted. + for _ in range(DHCP_ACK_PUBLISH_TIMEOUT_CYCLES): await cycle(bench.clk, 1) if int(dut.dhcpIp.value) == ipv4_config_word("192.168.2.44"): break diff --git a/tests/ethernet/UdpEngine/test_UdpEngineRx.py b/tests/ethernet/UdpEngine/test_UdpEngineRx.py index d6ecb579e6..4a48864179 100644 --- a/tests/ethernet/UdpEngine/test_UdpEngineRx.py +++ b/tests/ethernet/UdpEngine/test_UdpEngineRx.py @@ -37,6 +37,8 @@ LEGACY_MAC_CFGS, LEGACY_MAC_WIRES, UDP_RTL_SOURCES, + UDP_CLIENT_PORT, + UDP_SERVER_PORT, build_udp_rx_pseudo_frame, port_config_word, setup_udp_rx_bench, @@ -45,6 +47,8 @@ WRAPPER_PATH = "ethernet/UdpEngine/wrappers/UdpEngineRxFlatWrapper.vhd" +SERVER_REMOTE_PORT = 0x1234 +CLIENT_REMOTE_PORT = 0x5678 @cocotb.test() @@ -58,8 +62,9 @@ async def udp_engine_rx_routes_server_payload_and_debug_test(dut): remote_mac=LEGACY_MAC_WIRES[1], remote_ip=LEGACY_IPS[1], local_ip=LEGACY_IPS[0], - remote_port=0x1234, - local_port=8192, + # Port 8192 is the wrapper's fixed server socket. + remote_port=SERVER_REMOTE_PORT, + local_port=UDP_SERVER_PORT, payload=server_payload, ) @@ -75,7 +80,9 @@ async def udp_engine_rx_routes_server_payload_and_debug_test(dut): await server_send assert payload_from_beats(server_observed) == server_payload - assert int(dut.serverRemotePort.value) == port_config_word(0x1234) + # The debug outputs expose the learned sender tuple in lane-first config + # order, so compare against the helper that mirrors that byte order. + assert int(dut.serverRemotePort.value) == port_config_word(SERVER_REMOTE_PORT) assert int(dut.serverRemoteIp.value) == ipv4_config_word(LEGACY_IPS[1]) assert int(dut.serverRemoteMac.value) == LEGACY_MAC_CFGS[1] @@ -91,8 +98,8 @@ async def udp_engine_rx_routes_client_payload_and_detection_test(dut): remote_mac=LEGACY_MAC_WIRES[1], remote_ip=LEGACY_IPS[1], local_ip=LEGACY_IPS[0], - remote_port=0x5678, - local_port=8193, + remote_port=CLIENT_REMOTE_PORT, + local_port=UDP_CLIENT_PORT, payload=client_payload, ) diff --git a/tests/ethernet/UdpEngine/test_UdpEngineTx.py b/tests/ethernet/UdpEngine/test_UdpEngineTx.py index 539e8b2e24..2e95fd151e 100644 --- a/tests/ethernet/UdpEngine/test_UdpEngineTx.py +++ b/tests/ethernet/UdpEngine/test_UdpEngineTx.py @@ -36,6 +36,7 @@ LEGACY_IPS, LEGACY_MAC_WIRES, UDP_RTL_SOURCES, + UDP_SERVER_PORT, build_udp_tx_pseudo_frame, setup_udp_tx_bench, wait_for_link_up, @@ -71,8 +72,10 @@ async def udp_engine_tx_server_payload_header_test(dut): dst_mac=LEGACY_MAC_WIRES[1], src_ip=LEGACY_IPS[0], dst_ip=LEGACY_IPS[1], - src_port=8192, - dst_port=8192, + # The standalone TX wrapper seeds both local and remote server ports to + # 8192 so the pseudo-header reflects that symmetric default socket. + src_port=UDP_SERVER_PORT, + dst_port=UDP_SERVER_PORT, payload=payload, ) @@ -96,6 +99,7 @@ async def udp_engine_tx_dhcp_passthrough_test(dut): await dhcp_send assert payload_from_beats(observed) == build_udp_tx_pseudo_frame( + # DHCP always broadcasts from client port 68 to server port 67. dst_mac=0xFFFFFFFFFFFF, src_ip="0.0.0.0", dst_ip="255.255.255.255", diff --git a/tests/ethernet/UdpEngine/test_UdpEngineWrapper.py b/tests/ethernet/UdpEngine/test_UdpEngineWrapper.py index a9234c3939..8bb21f6392 100644 --- a/tests/ethernet/UdpEngine/test_UdpEngineWrapper.py +++ b/tests/ethernet/UdpEngine/test_UdpEngineWrapper.py @@ -40,6 +40,8 @@ LEGACY_IPS, LEGACY_MAC_WIRES, UDP_RTL_SOURCES, + UDP_CLIENT_PORT, + UDP_SERVER_PORT, port_config_word, ipv4_config_word, setup_udp_wrapper_bench, @@ -47,7 +49,11 @@ WRAPPER_PATH = "ethernet/UdpEngine/wrappers/UdpEngineWrapperFlatWrapper.vhd" - +CLIENT_REMOTE_PORT_ADDR = 0x000 +CLIENT_REMOTE_IP_ADDR = 0x004 +SOFT_IP_ADDR = 0xFE4 +SERVER_REMOTE_PORT_STATUS = 0x800 +SERVER_REMOTE_IP_STATUS = 0x804 @cocotb.test() async def udp_engine_wrapper_axil_and_server_path_test(dut): @@ -55,13 +61,15 @@ async def udp_engine_wrapper_axil_and_server_path_test(dut): # Start with the wrapper-local AXI-Lite register bank, since that behavior # is unique to `UdpEngineWrapper` rather than the underlying UDP core. - await axil_write_u32(bench.axil, 0x000, 0x0020) - await axil_write_u32(bench.axil, 0x004, ipv4_config_word(LEGACY_IPS[1])) - await axil_write_u32(bench.axil, 0xFE4, ipv4_config_word("192.168.2.99")) + # `0x000`/`0x004` are the client remote port/IP registers, while `0xFE4` + # is the wrapper-specific soft-IP override register. + await axil_write_u32(bench.axil, CLIENT_REMOTE_PORT_ADDR, 0x0020) + await axil_write_u32(bench.axil, CLIENT_REMOTE_IP_ADDR, ipv4_config_word(LEGACY_IPS[1])) + await axil_write_u32(bench.axil, SOFT_IP_ADDR, ipv4_config_word("192.168.2.99")) - assert await axil_read_u32(bench.axil, 0x000) == 0x0020 - assert await axil_read_u32(bench.axil, 0x004) == ipv4_config_word(LEGACY_IPS[1]) - assert await axil_read_u32(bench.axil, 0xFE4) == ipv4_config_word("192.168.2.99") + assert await axil_read_u32(bench.axil, CLIENT_REMOTE_PORT_ADDR) == 0x0020 + assert await axil_read_u32(bench.axil, CLIENT_REMOTE_IP_ADDR) == ipv4_config_word(LEGACY_IPS[1]) + assert await axil_read_u32(bench.axil, SOFT_IP_ADDR) == ipv4_config_word("192.168.2.99") assert int(dut.softIp.value) == ipv4_config_word("192.168.2.99") # Then prove one real inbound server-routing path through the integrated @@ -72,7 +80,7 @@ async def udp_engine_wrapper_axil_and_server_path_test(dut): src_ip=LEGACY_IPS[1], dst_ip=LEGACY_IPS[0], src_port=0x4567, - dst_port=8192, + dst_port=UDP_SERVER_PORT, payload=b"udp-wrapper-server-path", ) inbound_send = cocotb.start_soon( @@ -87,8 +95,10 @@ async def udp_engine_wrapper_axil_and_server_path_test(dut): await inbound_send assert payload_from_beats(server_observed) == b"udp-wrapper-server-path" - assert await axil_read_u32(bench.axil, 0x800) == port_config_word(0x4567) - assert await axil_read_u32(bench.axil, 0x804) == ipv4_config_word(LEGACY_IPS[1]) + # `0x800`/`0x804` are the exported debug readbacks for the last remote + # server tuple learned by the integrated stack. + assert await axil_read_u32(bench.axil, SERVER_REMOTE_PORT_STATUS) == port_config_word(0x4567) + assert await axil_read_u32(bench.axil, SERVER_REMOTE_IP_STATUS) == ipv4_config_word(LEGACY_IPS[1]) client_inbound = build_ipv4_udp_frame( dst_mac=LEGACY_MAC_WIRES[0], @@ -96,7 +106,7 @@ async def udp_engine_wrapper_axil_and_server_path_test(dut): src_ip=LEGACY_IPS[1], dst_ip=LEGACY_IPS[0], src_port=0x6789, - dst_port=8193, + dst_port=UDP_CLIENT_PORT, payload=b"udp-wrapper-client-rx", ) client_inbound_send = cocotb.start_soon( diff --git a/tests/ethernet/UdpEngine/udp_test_utils.py b/tests/ethernet/UdpEngine/udp_test_utils.py index 66f32c4504..397f1cc4f2 100644 --- a/tests/ethernet/UdpEngine/udp_test_utils.py +++ b/tests/ethernet/UdpEngine/udp_test_utils.py @@ -29,12 +29,16 @@ from tests.ethernet.IpV4Engine.ipv4_test_utils import ipv4_config_word +# Shared UDP-engine helpers centralize the wrapper-specific pseudo-header +# layout and the legacy demo configuration still used by the checked-in RTL. UDP_RTL_SOURCES = [ str(path) for path in sorted((Path(__file__).resolve().parents[3] / "ethernet" / "UdpEngine" / "rtl").glob("*.vhd")) ] +# The wrappers power up with the original SURF example endpoint table, so the +# benches keep using those MAC/IP tuples instead of inventing a second config. LEGACY_MAC_WIRES = ( 0x004456000301, 0x004456000302, @@ -51,8 +55,24 @@ LEGACY_IP_CFGS = tuple(ipv4_config_word(value) for value in LEGACY_IPS) UDP_PROTOCOL = 0x11 +UDP_SERVER_PORT = 8192 +UDP_CLIENT_PORT = 8193 DHCP_CLIENT_PORT = 68 DHCP_SERVER_PORT = 67 +DHCP_DISCOVER = 1 +DHCP_OFFER = 2 +DHCP_REQUEST = 3 +DHCP_ACK = 5 +DHCP_BOOT_REPLY_OP = 0x02 +DHCP_HTYPE_ETHERNET = 0x01 +DHCP_HLEN_ETHERNET = 0x06 +DHCP_FIXED_HEADER_BYTES = 240 +DHCP_MAGIC_COOKIE = bytes.fromhex("63825363") +DHCP_OPT_MESSAGE_TYPE = 53 +DHCP_OPT_REQUESTED_IP = 50 +DHCP_OPT_LEASE_TIME = 51 +DHCP_OPT_SERVER_IDENTIFIER = 54 +DHCP_OPT_END = 255 @dataclass @@ -121,6 +141,8 @@ def ipv4_to_bytes(address: str) -> bytes: def port_config_word(port: int) -> int: + # The flattened wrappers expose 16-bit ports lane-first, so reverse the + # normal big-endian wire view before comparing against DUT config words. return int.from_bytes(port.to_bytes(2, byteorder="big")[::-1], byteorder="big") @@ -140,6 +162,8 @@ def build_udp_rx_pseudo_frame( extra_trailer: bytes = b"", ) -> bytes: udp_length = 8 + len(payload) + len(extra_trailer) + # The RX pseudo-header is remote MAC, two pad bytes, remote/local IP, then + # zero/protocol/UDP metadata before the payload bytes. header0 = remote_mac.to_bytes(6, byteorder="big") + b"\x00\x00" + ipv4_to_bytes(remote_ip) + ipv4_to_bytes(local_ip) header1 = ( bytes([0x00, UDP_PROTOCOL]) @@ -162,6 +186,8 @@ def build_udp_tx_pseudo_frame( dst_port: int, payload: bytes, ) -> bytes: + # The TX pseudo-header keeps the same private layout but uses the outgoing + # destination MAC and source/destination IP tuple. header0 = dst_mac.to_bytes(6, byteorder="big") + b"\x00\x00" + ipv4_to_bytes(src_ip) + ipv4_to_bytes(dst_ip) header1 = ( bytes([0x00, UDP_PROTOCOL]) @@ -184,29 +210,30 @@ def build_dhcp_reply_payload( siaddr: str, lease_time: int = 120, ) -> bytes: - payload = bytearray(240) - payload[0] = 0x02 - payload[1] = 0x01 - payload[2] = 0x06 + # DHCP options start after the 240-byte BOOTP fixed header. + payload = bytearray(DHCP_FIXED_HEADER_BYTES) + payload[0] = DHCP_BOOT_REPLY_OP + payload[1] = DHCP_HTYPE_ETHERNET + payload[2] = DHCP_HLEN_ETHERNET payload[3] = 0x00 payload[4:8] = xid.to_bytes(4, byteorder="big") payload[16:20] = ipv4_to_bytes(yiaddr) payload[20:24] = ipv4_to_bytes(siaddr) payload[28:34] = client_mac.to_bytes(6, byteorder="big") - payload[236:240] = bytes.fromhex("63825363") + payload[236:240] = DHCP_MAGIC_COOKIE payload.extend( bytes( [ - 53, + DHCP_OPT_MESSAGE_TYPE, 1, message_type & 0xFF, - 51, + DHCP_OPT_LEASE_TIME, 4, ] ) ) payload.extend(lease_time.to_bytes(4, byteorder="big")) - payload.extend(bytes([255])) + payload.extend(bytes([DHCP_OPT_END])) return bytes(payload) @@ -215,13 +242,13 @@ def extract_dhcp_xid(payload: bytes) -> int: def extract_dhcp_message_type(payload: bytes) -> int | None: - index = 240 + index = DHCP_FIXED_HEADER_BYTES while index < len(payload): code = payload[index] if code == 0: index += 1 continue - if code == 255: + if code == DHCP_OPT_END: return None if index + 1 >= len(payload): return None @@ -230,43 +257,43 @@ def extract_dhcp_message_type(payload: bytes) -> int | None: data_stop = data_start + length if data_stop > len(payload): return None - if code == 53 and length == 1: + if code == DHCP_OPT_MESSAGE_TYPE and length == 1: return payload[data_start] index = data_stop return None def extract_dhcp_requested_ip(payload: bytes) -> str | None: - index = 240 + index = DHCP_FIXED_HEADER_BYTES while index < len(payload): code = payload[index] if code == 0: index += 1 continue - if code == 255: + if code == DHCP_OPT_END: return None length = payload[index + 1] data_start = index + 2 data_stop = data_start + length - if code == 50 and length == 4: + if code == DHCP_OPT_REQUESTED_IP and length == 4: return str(ipaddress.IPv4Address(payload[data_start:data_stop])) index = data_stop return None def extract_dhcp_server_identifier(payload: bytes) -> str | None: - index = 240 + index = DHCP_FIXED_HEADER_BYTES while index < len(payload): code = payload[index] if code == 0: index += 1 continue - if code == 255: + if code == DHCP_OPT_END: return None length = payload[index + 1] data_start = index + 2 data_stop = data_start + length - if code == 54 and length == 4: + if code == DHCP_OPT_SERVER_IDENTIFIER and length == 4: return str(ipaddress.IPv4Address(payload[data_start:data_stop])) index = data_stop return None @@ -513,4 +540,3 @@ async def setup_udp_wrapper_bench(dut) -> UdpWrapperBench: client_source=client_source, client_sink=FlatEmacEndpoint(dut, prefix="mClient"), ) - From 5ec52b62e32734f51c15565b2ed9e9071b60067e Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 17 Apr 2026 14:51:22 -0700 Subject: [PATCH 21/92] Remove planning docs. --- docs/_meta/rtl_instantiation_graph.json | 14578 ------------------- docs/_meta/rtl_instantiation_graph.md | 270 - docs/_meta/rtl_phase1_queue.json | 5874 -------- docs/_meta/rtl_phase1_queue.md | 272 - docs/_meta/rtl_phase1_queue_overrides.json | 85 - docs/_meta/rtl_regression_handoff.md | 203 - docs/_meta/rtl_regression_inventory.yaml | 700 - docs/_meta/rtl_regression_plan.md | 142 - docs/_meta/rtl_regression_progress.md | 312 - 9 files changed, 22436 deletions(-) delete mode 100644 docs/_meta/rtl_instantiation_graph.json delete mode 100644 docs/_meta/rtl_instantiation_graph.md delete mode 100644 docs/_meta/rtl_phase1_queue.json delete mode 100644 docs/_meta/rtl_phase1_queue.md delete mode 100644 docs/_meta/rtl_phase1_queue_overrides.json delete mode 100644 docs/_meta/rtl_regression_handoff.md delete mode 100644 docs/_meta/rtl_regression_inventory.yaml delete mode 100644 docs/_meta/rtl_regression_plan.md delete mode 100644 docs/_meta/rtl_regression_progress.md diff --git a/docs/_meta/rtl_instantiation_graph.json b/docs/_meta/rtl_instantiation_graph.json deleted file mode 100644 index cac3414382..0000000000 --- a/docs/_meta/rtl_instantiation_graph.json +++ /dev/null @@ -1,14578 +0,0 @@ -{ - "generated_from": { - "scan_dirs": [ - "base", - "axi", - "dsp", - "protocols", - "ethernet", - "devices", - "xilinx" - ], - "parser_scope": "VHDL entities outside tb/build/.venv paths", - "parser_limitations": [ - "Package calls are not graph nodes.", - "Direct entity instantiations are handled explicitly.", - "Component-style instantiations are inferred only when the instantiated name matches a known entity name inside an architecture body." - ] - }, - "summary": { - "entity_count": 795, - "edge_count": 1584, - "duplicate_entity_names": { - "Ad9249Deserializer": [ - "devices/AnalogDevices/ad9249/7Series/rtl/Ad9249Deserializer.vhd", - "devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd" - ], - "Ad9249ReadoutGroup": [ - "devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd", - "devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd" - ], - "ClinkDataClk": [ - "protocols/clink/7Series/ClinkDataClk.vhd", - "protocols/clink/UltraScale/ClinkDataClk.vhd" - ], - "ClinkDataShift": [ - "protocols/clink/7Series/ClinkDataShift.vhd", - "protocols/clink/UltraScale/ClinkDataShift.vhd" - ], - "ClkOutBufDiff": [ - "xilinx/dummy/ClkOutBufDiffDummy.vhd", - "xilinx/general/rtl/ClkOutBufDiff.vhd" - ], - "ClkOutBufSingle": [ - "xilinx/dummy/ClkOutBufSingleDummy.vhd", - "xilinx/general/rtl/ClkOutBufSingle.vhd" - ], - "ClockManagerUltraScale": [ - "xilinx/UltraScale/clocking/rtl/ClockManagerUltraScale.vhd", - "xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd" - ], - "CoaXPressOverFiberGthUsIpWrapper": [ - "protocols/coaxpress/gthUs/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd", - "protocols/coaxpress/gthUs+/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd" - ], - "CoaxpressOverFiberGthUs": [ - "protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUs.vhd", - "protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUs.vhd" - ], - "CoaxpressOverFiberGthUsQpll": [ - "protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUsQpll.vhd", - "protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUsQpll.vhd" - ], - "DS2411Core": [ - "devices/Maxim/dummy/DS2411CoreDummy.vhd", - "devices/Maxim/rtl/DS2411Core.vhd" - ], - "DeviceDna": [ - "xilinx/dummy/DeviceDnaDummy.vhd", - "xilinx/general/rtl/DeviceDna.vhd" - ], - "FifoAlteraMf": [ - "base/fifo/rtl/altera/FifoAlteraMf.vhd", - "base/fifo/rtl/dummy/FifoAlteraMfDummy.vhd" - ], - "FifoXpm": [ - "base/fifo/rtl/dummy/FifoXpmDummy.vhd", - "base/fifo/rtl/xilinx/FifoXpm.vhd" - ], - "GigEthGthUltraScale": [ - "ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd", - "ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd" - ], - "GigEthGthUltraScaleWrapper": [ - "ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd", - "ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd" - ], - "GthUltraScaleQuadPll": [ - "xilinx/UltraScale/gthUs/rtl/GthUltraScaleQuadPll.vhd", - "xilinx/UltraScale+/gthUs+/rtl/GthUltraScaleQuadPll.vhd" - ], - "Idelaye3Wrapper": [ - "xilinx/7Series/dummy/Idelaye3WrapperDummy.vhd", - "xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd" - ], - "InputBufferReg": [ - "xilinx/7Series/general/rtl/InputBufferReg.vhd", - "xilinx/UltraScale/general/rtl/InputBufferReg.vhd" - ], - "IoBufWrapper": [ - "xilinx/dummy/IoBufWrapperDummy.vhd", - "xilinx/general/rtl/IoBufWrapper.vhd" - ], - "Iprog": [ - "xilinx/dummy/IprogDummy.vhd", - "xilinx/general/rtl/Iprog.vhd" - ], - "MicroblazeBasicCoreWrapper": [ - "xilinx/general/microblaze/bypass/MicroblazeBasicCoreWrapper.vhd", - "xilinx/general/microblaze/generate/MicroblazeBasicCoreWrapper.vhd" - ], - "Odelaye3Wrapper": [ - "xilinx/7Series/dummy/Odelaye3WrapperDummy.vhd", - "xilinx/UltraScale/general/rtl/Odelaye3Wrapper.vhd" - ], - "OutputBufferReg": [ - "xilinx/7Series/general/rtl/OutputBufferReg.vhd", - "xilinx/UltraScale/general/rtl/OutputBufferReg.vhd", - "xilinx/dummy/OutputBufferRegDummy.vhd" - ], - "Pgp2bGthUltra": [ - "protocols/pgp/pgp2b/gthUltraScale/rtl/Pgp2bGthUltra.vhd", - "protocols/pgp/pgp2b/gthUltraScale+/rtl/Pgp2bGthUltra.vhd" - ], - "Pgp3GthUs": [ - "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUs.vhd", - "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUs.vhd" - ], - "Pgp3GthUsIpWrapper": [ - "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd", - "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsIpWrapper.vhd" - ], - "Pgp3GthUsQpll": [ - "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd", - "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsQpll.vhd" - ], - "Pgp3GthUsWrapper": [ - "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsWrapper.vhd", - "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsWrapper.vhd" - ], - "Pgp4GthUs": [ - "protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUs.vhd", - "protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUs.vhd" - ], - "Pgp4GthUsWrapper": [ - "protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUsWrapper.vhd", - "protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUsWrapper.vhd" - ], - "PgpGthCoreWrapper": [ - "protocols/pgp/pgp2b/gthUltraScale/rtl/PgpGthCoreWrapper.vhd", - "protocols/pgp/pgp2b/gthUltraScale+/rtl/PgpGthCoreWrapper.vhd" - ], - "RogueSideBand": [ - "axi/simlink/ghdl/RogueSideBand.vhd", - "axi/simlink/sim/RogueSideBand.vhd" - ], - "RogueTcpMemory": [ - "axi/simlink/ghdl/RogueTcpMemory.vhd", - "axi/simlink/sim/RogueTcpMemory.vhd" - ], - "RogueTcpStream": [ - "axi/simlink/ghdl/RogueTcpStream.vhd", - "axi/simlink/sim/RogueTcpStream.vhd" - ], - "SaltRxDeser": [ - "protocols/salt/rtl/7Series/SaltRxDeser.vhd", - "protocols/salt/rtl/UltraScale/SaltRxDeser.vhd" - ], - "SaltTxSer": [ - "protocols/salt/rtl/7Series/SaltTxSer.vhd", - "protocols/salt/rtl/UltraScale/SaltTxSer.vhd" - ], - "SimpleDualPortRamXpm": [ - "base/ram/dummy/SimpleDualPortRamXpmDummy.vhd", - "base/ram/xilinx/SimpleDualPortRamXpm.vhd" - ], - "SinglePortRamPrimitive": [ - "base/ram/dummy/SinglePortRamPrimitiveDummy.vhd", - "base/ram/xilinx/SinglePortRamPrimitive.vhd" - ], - "Srl16Delay": [ - "xilinx/dummy/Srl16DelayDummy.vhd", - "xilinx/general/rtl/Srl16Delay.vhd" - ], - "SugoiManagerRx7Series": [ - "protocols/sugoi/rtl/7Series/SugoiManagerRx7Series.vhd", - "protocols/sugoi/rtl/dummy/SugoiManagerRx7SeriesDummy.vhd" - ], - "SugoiManagerRxUltrascale": [ - "protocols/sugoi/rtl/UltraScale/SugoiManagerRxUltrascale.vhd", - "protocols/sugoi/rtl/dummy/SugoiManagerRxUltrascaleDummy.vhd" - ], - "TenGigEthGthUltraScale": [ - "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd", - "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd" - ], - "TenGigEthGthUltraScaleClk": [ - "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleClk.vhd", - "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleClk.vhd" - ], - "TenGigEthGthUltraScaleRst": [ - "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleRst.vhd", - "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleRst.vhd" - ], - "TenGigEthGthUltraScaleWrapper": [ - "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd", - "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd" - ], - "TrueDualPortRamXpm": [ - "base/ram/dummy/TrueDualPortRamXpmDummy.vhd", - "base/ram/xilinx/TrueDualPortRamXpm.vhd" - ], - "UdpDebugBridge": [ - "xilinx/xvc-udp/dcp/7Series/Impl/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/7Series/Stub/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/UltraScale/Impl/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/UltraScale/Stub/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd", - "xilinx/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd" - ], - "UdpDebugBridgeWrapper": [ - "xilinx/xvc-udp/dcp/core/UdpDebugBridgeWrapper.vhd", - "xilinx/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd" - ], - "XauiGthUltraScale": [ - "ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd", - "ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd" - ], - "XauiGthUltraScaleWrapper": [ - "ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd", - "ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd" - ] - }, - "top_instantiated_entities": [ - { - "entity": "RstSync", - "instantiated_by_count": 75, - "instantiates_count": 1, - "path": "base/sync/rtl/RstSync.vhd" - }, - { - "entity": "Synchronizer", - "instantiated_by_count": 73, - "instantiates_count": 0, - "path": "base/sync/rtl/Synchronizer.vhd" - }, - { - "entity": "AxiStreamFifoV2", - "instantiated_by_count": 41, - "instantiates_count": 5, - "path": "axi/axi-stream/rtl/AxiStreamFifoV2.vhd" - }, - { - "entity": "SynchronizerVector", - "instantiated_by_count": 41, - "instantiates_count": 0, - "path": "base/sync/rtl/SynchronizerVector.vhd" - }, - { - "entity": "AxiStreamPipeline", - "instantiated_by_count": 38, - "instantiates_count": 0, - "path": "axi/axi-stream/rtl/AxiStreamPipeline.vhd" - }, - { - "entity": "MasterAxiStreamIpIntegrator", - "instantiated_by_count": 37, - "instantiates_count": 1, - "path": "axi/axi-stream/ip_integrator/MasterAxiStreamIpIntegrator.vhd" - }, - { - "entity": "SlaveAxiLiteIpIntegrator", - "instantiated_by_count": 37, - "instantiates_count": 1, - "path": "axi/axi-lite/ip_integrator/SlaveAxiLiteIpIntegrator.vhd" - }, - { - "entity": "SlaveAxiStreamIpIntegrator", - "instantiated_by_count": 37, - "instantiates_count": 1, - "path": "axi/axi-stream/ip_integrator/SlaveAxiStreamIpIntegrator.vhd" - }, - { - "entity": "SynchronizerFifo", - "instantiated_by_count": 37, - "instantiates_count": 1, - "path": "base/sync/rtl/SynchronizerFifo.vhd" - }, - { - "entity": "PwrUpRst", - "instantiated_by_count": 36, - "instantiates_count": 1, - "path": "base/general/rtl/PwrUpRst.vhd" - }, - { - "entity": "AxiLiteCrossbar", - "instantiated_by_count": 32, - "instantiates_count": 0, - "path": "axi/axi-lite/rtl/AxiLiteCrossbar.vhd" - }, - { - "entity": "AxiLiteToDrp", - "instantiated_by_count": 28, - "instantiates_count": 1, - "path": "axi/bridge/rtl/AxiLiteToDrp.vhd" - }, - { - "entity": "SynchronizerOneShot", - "instantiated_by_count": 28, - "instantiates_count": 2, - "path": "base/sync/rtl/SynchronizerOneShot.vhd" - }, - { - "entity": "AxiLiteAsync", - "instantiated_by_count": 23, - "instantiates_count": 1, - "path": "axi/axi-lite/rtl/AxiLiteAsync.vhd" - }, - { - "entity": "Fifo", - "instantiated_by_count": 18, - "instantiates_count": 4, - "path": "base/fifo/rtl/Fifo.vhd" - }, - { - "entity": "MasterAxiIpIntegrator", - "instantiated_by_count": 16, - "instantiates_count": 1, - "path": "axi/axi4/ip_integrator/MasterAxiIpIntegrator.vhd" - }, - { - "entity": "SyncStatusVector", - "instantiated_by_count": 16, - "instantiates_count": 2, - "path": "base/sync/rtl/SyncStatusVector.vhd" - }, - { - "entity": "SynchronizerEdge", - "instantiated_by_count": 16, - "instantiates_count": 1, - "path": "base/sync/rtl/SynchronizerEdge.vhd" - }, - { - "entity": "RstPipeline", - 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"instantiates_count": 0, - "instantiated_by_count": 2, - "topological_layer": 3 - }, - { - "entity": "UartWrapper", - "paths": [ - "protocols/uart/rtl/UartWrapper.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "Fifo", - "UartBrg", - "UartRx", - "UartTx" - ], - "instantiated_by": [ - "UartAxiLiteMaster", - "UartAxiLiteMasterTb", - "UartSem" - ], - "instantiates_count": 4, - "instantiated_by_count": 3, - "topological_layer": 2 - }, - { - "entity": "UdpDebugBridge", - "paths": [ - "xilinx/xvc-udp/dcp/7Series/Impl/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/7Series/Stub/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/UltraScale/Impl/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/UltraScale/Stub/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd", - "xilinx/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd" - ], - "subsystem": "xilinx", - "instantiates": [ - "AxisJtagDebugBridge" - ], - "instantiated_by": [ - "UdpDebugBridgeWrapper" - ], - "instantiates_count": 1, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "UdpDebugBridgeWrapper", - "paths": [ - "xilinx/xvc-udp/dcp/core/UdpDebugBridgeWrapper.vhd", - "xilinx/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd" - ], - "subsystem": "xilinx", - "instantiates": [ - "UdpDebugBridge" - ], - "instantiated_by": [ - "DmaXvcWrapper", - "PgpXvcWrapper" - ], - "instantiates_count": 1, - "instantiated_by_count": 2, - "topological_layer": 1 - }, - { - "entity": "UdpEngine", - "paths": [ - "ethernet/UdpEngine/rtl/UdpEngine.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "ArpIpTable", - "AxiStreamMux", - "UdpEngineArp", - "UdpEngineDhcp", - "UdpEngineRx", - "UdpEngineTx" - ], - "instantiated_by": [ - "UdpEngineWrapper" - ], - "instantiates_count": 6, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "UdpEngineArp", - "paths": [ - "ethernet/UdpEngine/rtl/UdpEngineArp.vhd" - ], - "subsystem": "ethernet", - "instantiates": [], - "instantiated_by": [ - "UdpEngine" - ], - "instantiates_count": 0, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "UdpEngineDhcp", - "paths": [ - "ethernet/UdpEngine/rtl/UdpEngineDhcp.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "AxiStreamFifoV2" - ], - "instantiated_by": [ - "UdpEngine" - ], - "instantiates_count": 1, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "UdpEngineRx", - "paths": [ - "ethernet/UdpEngine/rtl/UdpEngineRx.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "AxiStreamDeMux", - "AxiStreamPipeline" - ], - "instantiated_by": [ - "UdpEngine" - ], - "instantiates_count": 2, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "UdpEngineTx", - "paths": [ - "ethernet/UdpEngine/rtl/UdpEngineTx.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "AxiStreamPipeline" - ], - "instantiated_by": [ - "UdpEngine" - ], - "instantiates_count": 1, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "UdpEngineWrapper", - "paths": [ - "ethernet/UdpEngine/rtl/UdpEngineWrapper.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "IpV4Engine", - "UdpEngine" - ], - "instantiated_by": [], - "instantiates_count": 2, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "WatchDogRst", - "paths": [ - "base/general/rtl/WatchDogRst.vhd" - ], - "subsystem": "base", - "instantiates": [ - "Synchronizer" - ], - "instantiated_by": [ - "GigEthReg", - "XauiGthUltraScaleWrapper", - "XauiGtyUltraScaleWrapper" - ], - "instantiates_count": 1, - "instantiated_by_count": 3, - "topological_layer": 3 - }, - { - "entity": "XadcSimpleCore", - "paths": [ - "xilinx/7Series/xadc/rtl/XadcSimpleCore.vhd" - ], - "subsystem": "xilinx", - "instantiates": [ - "AxiLiteToDrp" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "XauiGth7", - "paths": [ - "ethernet/XauiCore/gth7/rtl/XauiGth7.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "EthMacTop", - "RstSync", - "XauiGth7Core", - "XauiReg" - ], - "instantiated_by": [ - "XauiGth7Wrapper" - ], - "instantiates_count": 4, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "XauiGth7Core", - "paths": [ - "ethernet/XauiCore/gth7/rtl/XauiGth7Core.vhd" - ], - "subsystem": "ethernet", - "instantiates": [], - "instantiated_by": [ - "XauiGth7" - ], - "instantiates_count": 0, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "XauiGth7Wrapper", - "paths": [ - "ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "XauiGth7" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "XauiGthUltraScale", - "paths": [ - "ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd", - "ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "EthMacTop", - "RstSync", - "XauiReg" - ], - "instantiated_by": [ - "XauiGthUltraScaleWrapper" - ], - "instantiates_count": 3, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "XauiGthUltraScaleWrapper", - "paths": [ - "ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd", - "ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "PwrUpRst", - "WatchDogRst", - "XauiGthUltraScale" - ], - "instantiated_by": [], - "instantiates_count": 3, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "XauiGtx7", - "paths": [ - "ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "EthMacTop", - "RstSync", - "XauiGtx7Core", - "XauiReg" - ], - "instantiated_by": [ - "XauiGtx7Wrapper" - ], - "instantiates_count": 4, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "XauiGtx7Core", - "paths": [ - "ethernet/XauiCore/gtx7/rtl/XauiGtx7Core.vhd" - ], - "subsystem": "ethernet", - "instantiates": [], - "instantiated_by": [ - "XauiGtx7" - ], - "instantiates_count": 0, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "XauiGtx7Wrapper", - "paths": [ - "ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "XauiGtx7" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "XauiGtyUltraScale", - "paths": [ - "ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "EthMacTop", - "RstSync", - "XauiReg" - ], - "instantiated_by": [ - "XauiGtyUltraScaleWrapper" - ], - "instantiates_count": 3, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "XauiGtyUltraScaleWrapper", - "paths": [ - "ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "PwrUpRst", - "WatchDogRst", - "XauiGtyUltraScale" - ], - "instantiated_by": [], - "instantiates_count": 3, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "XauiReg", - "paths": [ - "ethernet/XauiCore/core/rtl/XauiReg.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "SyncStatusVector", - "SynchronizerFifo", - "SynchronizerVector" - ], - "instantiated_by": [ - "XauiGth7", - "XauiGthUltraScale", - "XauiGtx7", - "XauiGtyUltraScale" - ], - "instantiates_count": 3, - "instantiated_by_count": 4, - "topological_layer": 2 - }, - { - "entity": "adc32rf45", - "paths": [ - "devices/Ti/adc32rf45/rtl/adc32rf45.vhd" - ], - "subsystem": "devices", - "instantiates": [ - "SpiMaster" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "add3", - "paths": [ - "dsp/xilinx/fixed/Add3.vhd" - ], - "subsystem": "dsp", - "instantiates": [ - "csa3" - ], - "instantiated_by": [ - "FirAverage", - "IirSimple" - ], - "instantiates_count": 1, - "instantiated_by_count": 2, - "topological_layer": 1 - }, - { - "entity": "ads54j60", - "paths": [ - "devices/Ti/ads54j60/rtl/ads54j60.vhd" - ], - "subsystem": "devices", - "instantiates": [ - "SpiMaster" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "cfixedDelay", - "paths": [ - "dsp/xilinx/fixed/CfixedDelay.vhd" - ], - "subsystem": "dsp", - "instantiates": [ - "SlvFixedDelay" - ], - "instantiated_by": [ - "SinCosTaylor" - ], - "instantiates_count": 1, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "cfixedMult", - "paths": [ - "dsp/xilinx/fixed/CfixedMult.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [], - "instantiates_count": 0, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "cfixedMultAdd", - "paths": [ - "dsp/xilinx/fixed/CfixedMultAdd.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [], - "instantiates_count": 0, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "csa3", - "paths": [ - "dsp/xilinx/fixed/Csa3.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [ - "add3" - ], - "instantiates_count": 0, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "i2c2ahb", - "paths": [ - "protocols/i2c/rtl/orig/i2c2ahb.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "i2c2ahbx" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "i2c2ahb_apb", - "paths": [ - "protocols/i2c/rtl/orig/i2c2ahb_apb.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "i2c2ahbx" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "i2c2ahbx", - "paths": [ - "protocols/i2c/rtl/orig/i2c2ahbx.vhd" - ], - "subsystem": "protocols", - "instantiates": [], - "instantiated_by": [ - "i2c2ahb", - "i2c2ahb_apb" - ], - "instantiates_count": 0, - "instantiated_by_count": 2, - "topological_layer": 1 - }, - { - "entity": "i2c_master_bit_ctrl", - "paths": [ - "protocols/i2c/rtl/i2c_master_bit_ctrl.vhd" - ], - "subsystem": "protocols", - "instantiates": [], - "instantiated_by": [ - "i2c_master_byte_ctrl" - ], - "instantiates_count": 0, - "instantiated_by_count": 1, - "topological_layer": 6 - }, - { - "entity": "i2c_master_byte_ctrl", - "paths": [ - "protocols/i2c/rtl/i2c_master_byte_ctrl.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "i2c_master_bit_ctrl" - ], - "instantiated_by": [ - "I2cMaster", - "i2cmst" - ], - "instantiates_count": 1, - "instantiated_by_count": 2, - "topological_layer": 5 - }, - { - "entity": "i2cmst", - "paths": [ - "protocols/i2c/rtl/orig/i2cmst.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "i2c_master_byte_ctrl" - ], - "instantiated_by": [ - "i2cmst_gen" - ], - "instantiates_count": 1, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "i2cmst_gen", - "paths": [ - "protocols/i2c/rtl/orig/i2cmst_gen.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "i2cmst" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "i2cslv", - "paths": [ - "protocols/i2c/rtl/orig/i2cslv.vhd" - ], - "subsystem": "protocols", - "instantiates": [], - "instantiated_by": [], - "instantiates_count": 0, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "iq16bTo32b", - "paths": [ - "protocols/jesd204b/rtl/iq16bTo32b.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "Fifo" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "iq32bTo16b", - "paths": [ - "protocols/jesd204b/rtl/iq32bTo16b.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "Fifo" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "sfixedDelay", - "paths": [ - "dsp/xilinx/fixed/SfixedDelay.vhd" - ], - "subsystem": "dsp", - "instantiates": [ - "SlvFixedDelay" - ], - "instantiated_by": [ - "FirAverage", - "IirSimple" - ], - "instantiates_count": 1, - "instantiated_by_count": 2, - "topological_layer": 1 - }, - { - "entity": "sfixedMult", - "paths": [ - "dsp/xilinx/fixed/SfixedMult.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [ - "SinCosTaylor" - ], - "instantiates_count": 0, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "sfixedMultAdd", - "paths": [ - "dsp/xilinx/fixed/SfixedMultAdd.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [], - "instantiates_count": 0, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "sfixedPreAddMultAdd", - "paths": [ - "dsp/xilinx/fixed/SfixedPreAddMultAdd.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [], - "instantiates_count": 0, - "instantiated_by_count": 0, - "topological_layer": 0 - } - ] -} diff --git a/docs/_meta/rtl_instantiation_graph.md b/docs/_meta/rtl_instantiation_graph.md deleted file mode 100644 index 33b4e08d81..0000000000 --- a/docs/_meta/rtl_instantiation_graph.md +++ /dev/null @@ -1,270 +0,0 @@ -# SURF RTL Instantiation Graph - -## Scope -- Scan dirs: `base, axi, dsp, protocols, ethernet, devices, xilinx` -- Included files: VHDL files outside `tb/`, `build/`, and `.venv/` paths. -- Direct entity instantiations are parsed explicitly. -- Component-style instantiations are included only when the instantiated token matches a known entity name inside an architecture body. -- Packages are not graph nodes. - -## Summary -- Entities: `795` -- Edges: `1584` -- Topological layers: `12` -- Duplicate entity names: `51` - -## Top Instantiated Entities -| entity | instantiated_by_count | instantiates_count | path | -| --- | --- | --- | --- | -| RstSync | 75 | 1 | base/sync/rtl/RstSync.vhd | -| Synchronizer | 73 | 0 | base/sync/rtl/Synchronizer.vhd | -| AxiStreamFifoV2 | 41 | 5 | axi/axi-stream/rtl/AxiStreamFifoV2.vhd | -| SynchronizerVector | 41 | 0 | base/sync/rtl/SynchronizerVector.vhd | -| AxiStreamPipeline | 38 | 0 | axi/axi-stream/rtl/AxiStreamPipeline.vhd | -| MasterAxiStreamIpIntegrator | 37 | 1 | axi/axi-stream/ip_integrator/MasterAxiStreamIpIntegrator.vhd | -| SlaveAxiLiteIpIntegrator | 37 | 1 | axi/axi-lite/ip_integrator/SlaveAxiLiteIpIntegrator.vhd | -| SlaveAxiStreamIpIntegrator | 37 | 1 | axi/axi-stream/ip_integrator/SlaveAxiStreamIpIntegrator.vhd | -| SynchronizerFifo | 37 | 1 | base/sync/rtl/SynchronizerFifo.vhd | -| PwrUpRst | 36 | 1 | base/general/rtl/PwrUpRst.vhd | -| AxiLiteCrossbar | 32 | 0 | axi/axi-lite/rtl/AxiLiteCrossbar.vhd | -| AxiLiteToDrp | 28 | 1 | axi/bridge/rtl/AxiLiteToDrp.vhd | -| SynchronizerOneShot | 28 | 2 | base/sync/rtl/SynchronizerOneShot.vhd | -| AxiLiteAsync | 23 | 1 | axi/axi-lite/rtl/AxiLiteAsync.vhd | -| Fifo | 18 | 4 | base/fifo/rtl/Fifo.vhd | -| MasterAxiIpIntegrator | 16 | 1 | axi/axi4/ip_integrator/MasterAxiIpIntegrator.vhd | -| SyncStatusVector | 16 | 2 | base/sync/rtl/SyncStatusVector.vhd | -| SynchronizerEdge | 16 | 1 | base/sync/rtl/SynchronizerEdge.vhd | -| RstPipeline | 15 | 0 | base/general/rtl/RstPipeline.vhd | -| AxiLiteMaster | 14 | 0 | axi/axi-lite/rtl/AxiLiteMaster.vhd | - -## Top Assemblers -| entity | instantiates_count | instantiated_by_count | path | -| --- | --- | --- | --- | -| RssiCore | 13 | 1 | protocols/rssi/v1/rtl/RssiCore.vhd | -| EthMacRxRoCEv2 | 10 | 1 | ethernet/RoCEv2/rtl/EthMacRxRoCEv2.vhd | -| SugoiManagerCore | 10 | 0 | protocols/sugoi/rtl/SugoiManagerCore.vhd | -| Ad9681Readout | 8 | 0 | devices/AnalogDevices/ad9681/7Series/rtl/Ad9681Readout.vhd | -| CoaXPressAxiL | 8 | 1 | protocols/coaxpress/core/rtl/CoaXPressAxiL.vhd | -| EthMacTxRoCEv2 | 8 | 1 | ethernet/RoCEv2/rtl/EthMacTxRoCEv2.vhd | -| Gth7Core | 8 | 2 | xilinx/7Series/gth7/rtl/Gth7Core.vhd | -| RssiCoreWrapper | 8 | 0 | protocols/rssi/v1/rtl/RssiCoreWrapper.vhd | -| Ad9249ReadoutGroup | 7 | 0 | devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd | -| Ad9249ReadoutGroup2 | 7 | 0 | devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd | -| AxiRingBuffer | 7 | 1 | axi/axi4/rtl/AxiRingBuffer.vhd | -| AxiStreamRingBuffer | 7 | 1 | axi/axi-stream/rtl/AxiStreamRingBuffer.vhd | -| ClinkTop | 7 | 0 | protocols/clink/rtl/ClinkTop.vhd | -| CoaXPressRx | 7 | 1 | protocols/coaxpress/core/rtl/CoaXPressRx.vhd | -| FifoAsync | 7 | 8 | base/fifo/rtl/inferred/FifoAsync.vhd | -| GLinkGtx7Core | 7 | 1 | protocols/glink/gtx7/rtl/GLinkGtx7Core.vhd | -| Gtp7Core | 7 | 4 | xilinx/7Series/gtp7/rtl/Gtp7Core.vhd | -| IpV4Engine | 7 | 1 | ethernet/IpV4Engine/rtl/IpV4Engine.vhd | -| Jesd204bRx | 7 | 1 | protocols/jesd204b/rtl/Jesd204bRx.vhd | -| Jesd204bTx | 7 | 1 | protocols/jesd204b/rtl/Jesd204bTx.vhd | - -## Top Leaf Entities -| entity | instantiated_by_count | path | -| --- | --- | --- | -| Synchronizer | 73 | base/sync/rtl/Synchronizer.vhd | -| SynchronizerVector | 41 | base/sync/rtl/SynchronizerVector.vhd | -| AxiStreamPipeline | 38 | axi/axi-stream/rtl/AxiStreamPipeline.vhd | -| AxiLiteCrossbar | 32 | axi/axi-lite/rtl/AxiLiteCrossbar.vhd | -| RstPipeline | 15 | base/general/rtl/RstPipeline.vhd | -| AxiLiteMaster | 14 | axi/axi-lite/rtl/AxiLiteMaster.vhd | -| IoBufWrapper | 14 | xilinx/dummy/IoBufWrapperDummy.vhd | -| Decoder8b10b | 10 | protocols/line-codes/rtl/Decoder8b10b.vhd | -| SimpleDualPortRam | 10 | base/ram/inferred/SimpleDualPortRam.vhd | -| FifoOutputPipeline | 9 | base/fifo/rtl/FifoOutputPipeline.vhd | -| Crc32Parallel | 7 | base/crc/rtl/Crc32Parallel.vhd | -| SimpleDualPortRamXpm | 7 | base/ram/dummy/SimpleDualPortRamXpmDummy.vhd | -| SpiMaster | 7 | protocols/spi/rtl/SpiMaster.vhd | -| Gearbox | 6 | base/general/rtl/Gearbox.vhd | -| SelectIoRxGearboxAligner | 6 | xilinx/general/rtl/SelectIoRxGearboxAligner.vhd | -| ClkOutBufDiff | 5 | xilinx/dummy/ClkOutBufDiffDummy.vhd | -| Pgp3RxGearboxAligner | 5 | protocols/pgp/pgp3/core/rtl/Pgp3RxGearboxAligner.vhd | -| Scrambler | 5 | base/general/rtl/Scrambler.vhd | -| AxiStreamFlush | 4 | axi/axi-stream/rtl/AxiStreamFlush.vhd | -| CRC32Rtl | 4 | base/crc/rtl/CRC32Rtl.vhd | - -## Base Bottom-Up Candidates -| entity | instantiated_by_count | instantiates_count | path | -| --- | --- | --- | --- | -| Synchronizer | 73 | 0 | base/sync/rtl/Synchronizer.vhd | -| SynchronizerVector | 41 | 0 | base/sync/rtl/SynchronizerVector.vhd | -| RstPipeline | 15 | 0 | base/general/rtl/RstPipeline.vhd | -| SimpleDualPortRam | 10 | 0 | base/ram/inferred/SimpleDualPortRam.vhd | -| FifoOutputPipeline | 9 | 0 | base/fifo/rtl/FifoOutputPipeline.vhd | -| Crc32Parallel | 7 | 0 | base/crc/rtl/Crc32Parallel.vhd | -| SimpleDualPortRamXpm | 7 | 0 | base/ram/dummy/SimpleDualPortRamXpmDummy.vhd | -| Gearbox | 6 | 0 | base/general/rtl/Gearbox.vhd | -| Scrambler | 5 | 0 | base/general/rtl/Scrambler.vhd | -| CRC32Rtl | 4 | 0 | base/crc/rtl/CRC32Rtl.vhd | -| Crc32 | 3 | 0 | base/crc/rtl/Crc32.vhd | -| SimpleDualPortRamAlteraMf | 3 | 0 | base/ram/dummy/SimpleDualPortRamAlteraMfDummy.vhd | -| SlvDelay | 3 | 0 | base/delay/rtl/SlvDelay.vhd | -| TrueDualPortRam | 3 | 0 | base/ram/inferred/TrueDualPortRam.vhd | -| FifoRdFsm | 2 | 0 | base/fifo/rtl/inferred/FifoRdFsm.vhd | -| FifoWrFsm | 2 | 0 | base/fifo/rtl/inferred/FifoWrFsm.vhd | -| LutRam | 2 | 0 | base/ram/inferred/LutRam.vhd | -| TrueDualPortRamAlteraMf | 2 | 0 | base/ram/dummy/TrueDualPortRamXpmAlteraMfDummy.vhd | -| TrueDualPortRamXpm | 2 | 0 | base/ram/dummy/TrueDualPortRamXpmDummy.vhd | -| Arbiter | 1 | 0 | base/general/rtl/Arbiter.vhd | - -## Duplicate Entity Names -- `Ad9249Deserializer` - - `devices/AnalogDevices/ad9249/7Series/rtl/Ad9249Deserializer.vhd` - - `devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd` -- `Ad9249ReadoutGroup` - - `devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd` - - `devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd` -- `ClinkDataClk` - - `protocols/clink/7Series/ClinkDataClk.vhd` - - `protocols/clink/UltraScale/ClinkDataClk.vhd` -- `ClinkDataShift` - - `protocols/clink/7Series/ClinkDataShift.vhd` - - `protocols/clink/UltraScale/ClinkDataShift.vhd` -- `ClkOutBufDiff` - - `xilinx/dummy/ClkOutBufDiffDummy.vhd` - - `xilinx/general/rtl/ClkOutBufDiff.vhd` -- `ClkOutBufSingle` - - `xilinx/dummy/ClkOutBufSingleDummy.vhd` - - `xilinx/general/rtl/ClkOutBufSingle.vhd` -- `ClockManagerUltraScale` - - `xilinx/UltraScale/clocking/rtl/ClockManagerUltraScale.vhd` - - `xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd` -- `CoaXPressOverFiberGthUsIpWrapper` - - `protocols/coaxpress/gthUs/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd` - - `protocols/coaxpress/gthUs+/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd` -- `CoaxpressOverFiberGthUs` - - `protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUs.vhd` - - `protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUs.vhd` -- `CoaxpressOverFiberGthUsQpll` - - `protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUsQpll.vhd` - - `protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUsQpll.vhd` -- `DS2411Core` - - `devices/Maxim/dummy/DS2411CoreDummy.vhd` - - `devices/Maxim/rtl/DS2411Core.vhd` -- `DeviceDna` - - `xilinx/dummy/DeviceDnaDummy.vhd` - - `xilinx/general/rtl/DeviceDna.vhd` -- `FifoAlteraMf` - - `base/fifo/rtl/altera/FifoAlteraMf.vhd` - - `base/fifo/rtl/dummy/FifoAlteraMfDummy.vhd` -- `FifoXpm` - - `base/fifo/rtl/dummy/FifoXpmDummy.vhd` - - `base/fifo/rtl/xilinx/FifoXpm.vhd` -- `GigEthGthUltraScale` - - `ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd` - - `ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd` -- `GigEthGthUltraScaleWrapper` - - `ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd` - - `ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd` -- `GthUltraScaleQuadPll` - - `xilinx/UltraScale/gthUs/rtl/GthUltraScaleQuadPll.vhd` - - `xilinx/UltraScale+/gthUs+/rtl/GthUltraScaleQuadPll.vhd` -- `Idelaye3Wrapper` - - `xilinx/7Series/dummy/Idelaye3WrapperDummy.vhd` - - `xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd` -- `InputBufferReg` - - `xilinx/7Series/general/rtl/InputBufferReg.vhd` - - `xilinx/UltraScale/general/rtl/InputBufferReg.vhd` -- `IoBufWrapper` - - `xilinx/dummy/IoBufWrapperDummy.vhd` - - `xilinx/general/rtl/IoBufWrapper.vhd` -- `Iprog` - - `xilinx/dummy/IprogDummy.vhd` - - `xilinx/general/rtl/Iprog.vhd` -- `MicroblazeBasicCoreWrapper` - - `xilinx/general/microblaze/bypass/MicroblazeBasicCoreWrapper.vhd` - - `xilinx/general/microblaze/generate/MicroblazeBasicCoreWrapper.vhd` -- `Odelaye3Wrapper` - - `xilinx/7Series/dummy/Odelaye3WrapperDummy.vhd` - - `xilinx/UltraScale/general/rtl/Odelaye3Wrapper.vhd` -- `OutputBufferReg` - - `xilinx/7Series/general/rtl/OutputBufferReg.vhd` - - `xilinx/UltraScale/general/rtl/OutputBufferReg.vhd` - - `xilinx/dummy/OutputBufferRegDummy.vhd` -- `Pgp2bGthUltra` - - `protocols/pgp/pgp2b/gthUltraScale/rtl/Pgp2bGthUltra.vhd` - - `protocols/pgp/pgp2b/gthUltraScale+/rtl/Pgp2bGthUltra.vhd` -- `Pgp3GthUs` - - `protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUs.vhd` - - `protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUs.vhd` -- `Pgp3GthUsIpWrapper` - - `protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd` - - `protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsIpWrapper.vhd` -- `Pgp3GthUsQpll` - - `protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd` - - `protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsQpll.vhd` -- `Pgp3GthUsWrapper` - - `protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsWrapper.vhd` - - `protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsWrapper.vhd` -- `Pgp4GthUs` - - `protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUs.vhd` - - `protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUs.vhd` -- `Pgp4GthUsWrapper` - - `protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUsWrapper.vhd` - - `protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUsWrapper.vhd` -- `PgpGthCoreWrapper` - - `protocols/pgp/pgp2b/gthUltraScale/rtl/PgpGthCoreWrapper.vhd` - - `protocols/pgp/pgp2b/gthUltraScale+/rtl/PgpGthCoreWrapper.vhd` -- `RogueSideBand` - - `axi/simlink/ghdl/RogueSideBand.vhd` - - `axi/simlink/sim/RogueSideBand.vhd` -- `RogueTcpMemory` - - `axi/simlink/ghdl/RogueTcpMemory.vhd` - - `axi/simlink/sim/RogueTcpMemory.vhd` -- `RogueTcpStream` - - `axi/simlink/ghdl/RogueTcpStream.vhd` - - `axi/simlink/sim/RogueTcpStream.vhd` -- `SaltRxDeser` - - `protocols/salt/rtl/7Series/SaltRxDeser.vhd` - - `protocols/salt/rtl/UltraScale/SaltRxDeser.vhd` -- `SaltTxSer` - - `protocols/salt/rtl/7Series/SaltTxSer.vhd` - - `protocols/salt/rtl/UltraScale/SaltTxSer.vhd` -- `SimpleDualPortRamXpm` - - `base/ram/dummy/SimpleDualPortRamXpmDummy.vhd` - - `base/ram/xilinx/SimpleDualPortRamXpm.vhd` -- `SinglePortRamPrimitive` - - `base/ram/dummy/SinglePortRamPrimitiveDummy.vhd` - - `base/ram/xilinx/SinglePortRamPrimitive.vhd` -- `Srl16Delay` - - `xilinx/dummy/Srl16DelayDummy.vhd` - - `xilinx/general/rtl/Srl16Delay.vhd` -- `SugoiManagerRx7Series` - - `protocols/sugoi/rtl/7Series/SugoiManagerRx7Series.vhd` - - `protocols/sugoi/rtl/dummy/SugoiManagerRx7SeriesDummy.vhd` -- `SugoiManagerRxUltrascale` - - `protocols/sugoi/rtl/UltraScale/SugoiManagerRxUltrascale.vhd` - - `protocols/sugoi/rtl/dummy/SugoiManagerRxUltrascaleDummy.vhd` -- `TenGigEthGthUltraScale` - - `ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd` - - `ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd` -- `TenGigEthGthUltraScaleClk` - - `ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleClk.vhd` - - `ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleClk.vhd` -- `TenGigEthGthUltraScaleRst` - - `ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleRst.vhd` - - `ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleRst.vhd` -- `TenGigEthGthUltraScaleWrapper` - - `ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd` - - `ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd` -- `TrueDualPortRamXpm` - - `base/ram/dummy/TrueDualPortRamXpmDummy.vhd` - - `base/ram/xilinx/TrueDualPortRamXpm.vhd` -- `UdpDebugBridge` - - `xilinx/xvc-udp/dcp/7Series/Impl/images/UdpDebugBridge_stub.vhd` - - `xilinx/xvc-udp/dcp/7Series/Stub/images/UdpDebugBridge_stub.vhd` - - `xilinx/xvc-udp/dcp/UltraScale/Impl/images/UdpDebugBridge_stub.vhd` - - `xilinx/xvc-udp/dcp/UltraScale/Stub/images/UdpDebugBridge_stub.vhd` - - `xilinx/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd` - - `xilinx/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd` -- `UdpDebugBridgeWrapper` - - `xilinx/xvc-udp/dcp/core/UdpDebugBridgeWrapper.vhd` - - `xilinx/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd` -- `XauiGthUltraScale` - - `ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd` - - `ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd` -- `XauiGthUltraScaleWrapper` - - `ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd` - - `ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd` diff --git a/docs/_meta/rtl_phase1_queue.json b/docs/_meta/rtl_phase1_queue.json deleted file mode 100644 index a77d778b6b..0000000000 --- a/docs/_meta/rtl_phase1_queue.json +++ /dev/null @@ -1,5874 +0,0 @@ -{ - "generated_from": { - "scan_dirs": [ - "base", - "axi", - "dsp", - "protocols", - "ethernet", - "devices", - "xilinx" - ], - "source_graph_script": "scripts/build_rtl_instantiation_graph.py", - "override_file": "docs/_meta/rtl_phase1_queue_overrides.json", - "queue_policy": "Path-qualified, phase-1 filtered, bottom-up instantiation order" - }, - "summary": { - "phase1_module_count": 219, - "phase1_edge_count": 392, - "phase1_bottom_up_layers": 10, - "deferred_module_count": 632, - "unresolved_phase1_edges": 0, - "applied_order_overrides": 0 - }, - "phase1_rules": { - "force_include_entities": [], - "force_include_paths": [], - "deferred_subsystems": [ - { - "name": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "name": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "name": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "name": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - } - ], - "deferred_entities": [ - { - "entity": "LutFixedDelay", - "reason": "Depends on SinglePortRamPrimitive under the current open-source flow." - } - ], - "deferred_paths": [], - "deferred_path_substrings": [ - { - "pattern": "axi/simlink/", - "reason": "Simulation support models are not part of the synthesizable phase-1 queue." - }, - { - "pattern": "/sim/", - "reason": "Simulation-only support modules are not part of the synthesizable phase-1 queue." - }, - { - "pattern": "/dummy/", - "reason": "Dummy-backed variants are deferred from the phase-1 executable queue." - }, - { - "pattern": "/altera/", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "/xilinx/", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "7Series", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "UltraScale", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "UltraScale+", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "/gth", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gtp", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gty", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gtx", - "reason": "GT-family implementation branches are deferred in phase 1." - } - ], - "preferred_paths_by_entity": {}, - "order_overrides": [] - }, - "applied_order_overrides": [], - "queue": [ - { - "order": 1, - "bottom_up_layer": 0, - "entity": "AxiLiteCrossbar", - "path": "axi/axi-lite/rtl/AxiLiteCrossbar.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 3 - }, - { - "order": 2, - "bottom_up_layer": 0, - "entity": "AxiLiteMaster", - "path": "axi/axi-lite/rtl/AxiLiteMaster.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 6 - }, - { - "order": 3, - "bottom_up_layer": 0, - "entity": "AxiLiteRegs", - "path": "axi/axi-lite/rtl/AxiLiteRegs.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 4, - "bottom_up_layer": 0, - "entity": "AxiLiteRespTimer", - "path": "axi/axi-lite/rtl/AxiLiteRespTimer.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 5, - "bottom_up_layer": 0, - "entity": "AxiLiteSlave", - "path": "axi/axi-lite/rtl/AxiLiteSlave.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 6, - "bottom_up_layer": 0, - "entity": "AxiLiteWriteFilter", - "path": "axi/axi-lite/rtl/AxiLiteWriteFilter.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 7, - "bottom_up_layer": 0, - "entity": "AxiVersion", - "path": "axi/axi-lite/rtl/AxiVersion.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 8, - "bottom_up_layer": 0, - "entity": "AxiStreamCombiner", - "path": "axi/axi-stream/rtl/AxiStreamCombiner.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 9, - "bottom_up_layer": 0, - "entity": "AxiStreamFlush", - "path": "axi/axi-stream/rtl/AxiStreamFlush.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 10, - "bottom_up_layer": 0, - "entity": "AxiStreamGearboxPack", - "path": "axi/axi-stream/rtl/AxiStreamGearboxPack.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 11, - "bottom_up_layer": 0, - "entity": "AxiStreamGearboxUnpack", - "path": "axi/axi-stream/rtl/AxiStreamGearboxUnpack.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 12, - "bottom_up_layer": 0, - "entity": "AxiStreamPipeline", - "path": "axi/axi-stream/rtl/AxiStreamPipeline.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 18 - }, - { - "order": 13, - "bottom_up_layer": 0, - "entity": "AxiStreamSplitter", - "path": "axi/axi-stream/rtl/AxiStreamSplitter.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 14, - "bottom_up_layer": 0, - "entity": "AxiStreamPkgWrapper", - "path": "axi/axi-stream/wrappers/AxiStreamPkgWrapper.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 15, - "bottom_up_layer": 0, - "entity": "AxiReadPathMux", - "path": "axi/axi4/rtl/AxiReadPathMux.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 16, - "bottom_up_layer": 0, - "entity": "AxiResize", - "path": "axi/axi4/rtl/AxiResize.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 17, - "bottom_up_layer": 0, - "entity": "AxiWritePathMux", - "path": "axi/axi4/rtl/AxiWritePathMux.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 18, - "bottom_up_layer": 0, - "entity": "AxiToAxiLite", - "path": "axi/bridge/rtl/AxiToAxiLite.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 19, - "bottom_up_layer": 0, - "entity": "AxiStreamDmaV2WriteMux", - "path": "axi/dma/rtl/v2/AxiStreamDmaV2WriteMux.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 20, - "bottom_up_layer": 0, - "entity": "CRC32Rtl", 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vendor-heavy modules in phase 1." - }, - { - "entity": "LeapXcvrCore", - "path": "devices/Amphenol/LeapXcvr/rtl/LeapXcvrCore.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd5541Core", - "path": "devices/AnalogDevices/ad5541/rtl/AxiAd5541Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd5780Core", - "path": "devices/AnalogDevices/ad5780/rtl/AxiAd5780Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd5780Reg", - "path": "devices/AnalogDevices/ad5780/rtl/AxiAd5780Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd5780Ser", - "path": "devices/AnalogDevices/ad5780/rtl/AxiAd5780Ser.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249ConfigNoPullup", - "path": "devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ConfigNoPullup.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249Deserializer", - "path": "devices/AnalogDevices/ad9249/7Series/rtl/Ad9249Deserializer.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249ReadoutGroup", - "path": "devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249Deserializer", - "path": "devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249ReadoutGroup", - "path": "devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249ReadoutGroup2", - "path": "devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249Config", - "path": "devices/AnalogDevices/ad9249/core/Ad9249Config.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "StreamPatternTester", - "path": "devices/AnalogDevices/ad9249/core/StreamPatternTester.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467Core", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467Deser", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467Deser.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467DeserBit", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467DeserBit.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467Mon", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467Mon.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467Pll", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467Pll.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467Reg", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467Spi", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467Spi.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681Deserializer", - "path": "devices/AnalogDevices/ad9681/7Series/rtl/Ad9681Deserializer.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681Readout", - "path": "devices/AnalogDevices/ad9681/7Series/rtl/Ad9681Readout.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681ReadoutManual", - "path": "devices/AnalogDevices/ad9681/7Series/rtl/Ad9681ReadoutManual.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681Config", - "path": "devices/AnalogDevices/ad9681/core/Ad9681Config.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681", - "path": "devices/AnalogDevices/ad9681/sim/Ad9681.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681Serializer", - "path": "devices/AnalogDevices/ad9681/sim/Ad9681Serializer.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AdiConfigSlave", - "path": "devices/AnalogDevices/general/rtl/AdiConfigSlave.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiLtc2270Core", - "path": "devices/Linear/lct2270/rtl/AxiLtc2270Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiLtc2270Deser", - "path": "devices/Linear/lct2270/rtl/AxiLtc2270Deser.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiLtc2270DeserBit", - "path": "devices/Linear/lct2270/rtl/AxiLtc2270DeserBit.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiLtc2270Reg", - "path": "devices/Linear/lct2270/rtl/AxiLtc2270Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sgmii88E1111Mdio", - "path": "devices/Marvell/Sgmii88E1111/core/Sgmii88E1111Mdio.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sgmii88E1111LvdsUltraScale", - "path": "devices/Marvell/Sgmii88E1111/lvdsUltraScale/Sgmii88E1111LvdsUltraScale.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DS2411Core", - "path": "devices/Maxim/dummy/DS2411CoreDummy.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DS2411Core", - "path": "devices/Maxim/rtl/DS2411Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Max5443", - "path": "devices/Maxim/rtl/Max5443.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Max5443DacCntrl", - "path": "devices/Maxim/rtl/Max5443DacCntrl.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiSy56040Core", - "path": "devices/Microchip/sy56040/rtl/AxiSy56040Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiSy56040Reg", - "path": "devices/Microchip/sy56040/rtl/AxiSy56040Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sy89297", - "path": "devices/Microchip/sy89297/rtl/Sy89297.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronMt28ewCore", - "path": "devices/Micron/mt28ew/rtl/AxiMicronMt28ewCore.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronMt28ewReg", - "path": "devices/Micron/mt28ew/rtl/AxiMicronMt28ewReg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronN25QCore", - "path": "devices/Micron/n25q/rtl/AxiMicronN25QCore.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronN25QReg", - "path": "devices/Micron/n25q/rtl/AxiMicronN25QReg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronP30Core", - "path": "devices/Micron/p30/rtl/AxiMicronP30Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronP30Reg", - "path": "devices/Micron/p30/rtl/AxiMicronP30Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sc18Is602", - "path": "devices/Nxp/Sc18Is602/rtl/Sc18Is602.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sc18Is602Core", - "path": "devices/Nxp/Sc18Is602/rtl/Sc18Is602Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Si5324", - "path": "devices/Silabs/si5324/rtl/Si5324.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Si5345", - "path": "devices/Silabs/si5345/rtl/Si5345.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Si5394I2c", - "path": "devices/Silabs/si5394/rtl/Si5394I2c.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Si5394I2cCore", - "path": "devices/Silabs/si5394/rtl/Si5394I2cCore.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Lmk048Base", - "path": "devices/Ti/Lmk048Base/rtl/Lmk048Base.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "adc32rf45", - "path": "devices/Ti/adc32rf45/rtl/adc32rf45.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAds42lb69Core", - "path": "devices/Ti/ads42lb69/rtl/AxiAds42lb69Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAds42lb69Deser", - "path": "devices/Ti/ads42lb69/rtl/AxiAds42lb69Deser.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAds42lb69DeserBit", - "path": "devices/Ti/ads42lb69/rtl/AxiAds42lb69DeserBit.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAds42lb69Pll", - "path": "devices/Ti/ads42lb69/rtl/AxiAds42lb69Pll.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAds42lb69Reg", - "path": "devices/Ti/ads42lb69/rtl/AxiAds42lb69Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ads54j60", - "path": "devices/Ti/ads54j60/rtl/ads54j60.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiDac7654Core", - "path": "devices/Ti/dac7654/rtl/AxiDac7654Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiDac7654Reg", - "path": "devices/Ti/dac7654/rtl/AxiDac7654Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiDac7654Spi", - "path": "devices/Ti/dac7654/rtl/AxiDac7654Spi.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SgmiiDp83867Mdio", - "path": "devices/Ti/dp83867/core/SgmiiDp83867Mdio.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SgmiiDp83867LvdsUltraScale", - "path": "devices/Ti/dp83867/lvdsUltraScale/SgmiiDp83867LvdsUltraScale.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiXcf128Core", - "path": "devices/Xilinx/xcf128/rtl/AxiXcf128Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiXcf128Reg", - "path": "devices/Xilinx/xcf128/rtl/AxiXcf128Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "QsfpCdrDisable", - "path": "devices/transceivers/rtl/QsfpCdrDisable.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sff8472", - "path": "devices/transceivers/rtl/Sff8472.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sff8472Core", - "path": "devices/transceivers/rtl/Sff8472Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "add3", - "path": "dsp/xilinx/fixed/Add3.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "CfixedAccumulator", - "path": "dsp/xilinx/fixed/CfixedAccumulator.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "cfixedDelay", - "path": "dsp/xilinx/fixed/CfixedDelay.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "cfixedMult", - "path": "dsp/xilinx/fixed/CfixedMult.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "cfixedMultAdd", - "path": "dsp/xilinx/fixed/CfixedMultAdd.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "CfixedPreAddMult", - "path": "dsp/xilinx/fixed/CfixedPreAddMult.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "csa3", - "path": "dsp/xilinx/fixed/Csa3.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "FirAverage", - "path": "dsp/xilinx/fixed/FirAverage.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "IirSimple", - "path": "dsp/xilinx/fixed/IirSimple.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "SfixedAccumulator", - "path": "dsp/xilinx/fixed/SfixedAccumulator.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "sfixedDelay", - "path": "dsp/xilinx/fixed/SfixedDelay.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "sfixedMult", - "path": "dsp/xilinx/fixed/SfixedMult.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "sfixedMultAdd", - "path": "dsp/xilinx/fixed/SfixedMultAdd.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "sfixedPreAddMultAdd", - "path": "dsp/xilinx/fixed/SfixedPreAddMultAdd.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "SinCosLut", - "path": "dsp/xilinx/fixed/SinCosLut.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "SinCosTaylor", - "path": "dsp/xilinx/fixed/SinCosTaylor.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "DspXor", - "path": "dsp/xilinx/logic/DspXor.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "Caui4GtyIpWrapper", - "path": "ethernet/Caui4Core/gtyUltraScale+/rtl/Caui4GtyIpWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthCrc32Parallel", - "path": "ethernet/EthMacCore/rtl/EthCrc32Parallel.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacFlowCtrl", - "path": "ethernet/EthMacCore/rtl/EthMacFlowCtrl.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRx", - "path": "ethernet/EthMacCore/rtl/EthMacRx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxBypass", - "path": "ethernet/EthMacCore/rtl/EthMacRxBypass.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxCsum", - "path": "ethernet/EthMacCore/rtl/EthMacRxCsum.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxFifo", - "path": "ethernet/EthMacCore/rtl/EthMacRxFifo.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxFilter", - "path": "ethernet/EthMacCore/rtl/EthMacRxFilter.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxImport", - "path": "ethernet/EthMacCore/rtl/EthMacRxImport.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxImportGmii", - "path": "ethernet/EthMacCore/rtl/EthMacRxImportGmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxImportXgmii", - "path": "ethernet/EthMacCore/rtl/EthMacRxImportXgmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxImportXlgmii", - "path": "ethernet/EthMacCore/rtl/EthMacRxImportXlgmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxPause", - "path": "ethernet/EthMacCore/rtl/EthMacRxPause.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxShift", - "path": "ethernet/EthMacCore/rtl/EthMacRxShift.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTop", - "path": "ethernet/EthMacCore/rtl/EthMacTop.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTx", - "path": "ethernet/EthMacCore/rtl/EthMacTx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxBypass", - "path": "ethernet/EthMacCore/rtl/EthMacTxBypass.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxCsum", - "path": "ethernet/EthMacCore/rtl/EthMacTxCsum.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxExport", - "path": "ethernet/EthMacCore/rtl/EthMacTxExport.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxExportGmii", - "path": "ethernet/EthMacCore/rtl/EthMacTxExportGmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxExportXgmii", - "path": "ethernet/EthMacCore/rtl/EthMacTxExportXgmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxExportXlgmii", - "path": "ethernet/EthMacCore/rtl/EthMacTxExportXlgmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxFifo", - "path": "ethernet/EthMacCore/rtl/EthMacTxFifo.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxPause", - "path": "ethernet/EthMacCore/rtl/EthMacTxPause.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxShift", - "path": "ethernet/EthMacCore/rtl/EthMacTxShift.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthReg", - "path": "ethernet/GigEthCore/core/rtl/GigEthReg.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGth7", - "path": "ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGth7Wrapper", - "path": "ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGthUltraScale", - "path": "ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGthUltraScaleWrapper", - "path": "ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGthUltraScale", - "path": "ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGthUltraScaleWrapper", - "path": "ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtp7", - "path": "ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtp7Wrapper", - "path": "ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtx7", - "path": "ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtx7Wrapper", - "path": "ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtyUltraScale", - "path": "ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtyUltraScaleWrapper", - "path": "ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthLvdsUltraScale", - "path": "ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ArpEngine", - "path": "ethernet/IpV4Engine/rtl/ArpEngine.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IcmpEngine", - "path": "ethernet/IpV4Engine/rtl/IcmpEngine.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IgmpV2Engine", - "path": "ethernet/IpV4Engine/rtl/IgmpV2Engine.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IpV4Engine", - "path": "ethernet/IpV4Engine/rtl/IpV4Engine.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IpV4EngineDeMux", - "path": "ethernet/IpV4Engine/rtl/IpV4EngineDeMux.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IpV4EngineRx", - "path": "ethernet/IpV4Engine/rtl/IpV4EngineRx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IpV4EngineTx", - "path": "ethernet/IpV4Engine/rtl/IpV4EngineTx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RawEthFramer", - "path": "ethernet/RawEthFramer/rtl/RawEthFramer.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RawEthFramerRx", - "path": "ethernet/RawEthFramer/rtl/RawEthFramerRx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RawEthFramerTx", - "path": "ethernet/RawEthFramer/rtl/RawEthFramerTx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RawEthFramerWrapper", - "path": "ethernet/RawEthFramer/rtl/RawEthFramerWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacCrcAxiStreamWrapperRecv", - "path": "ethernet/RoCEv2/rtl/EthMacCrcAxiStreamWrapperRecv.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacCrcAxiStreamWrapperSend", - "path": "ethernet/RoCEv2/rtl/EthMacCrcAxiStreamWrapperSend.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacPrepareForICrc", - "path": "ethernet/RoCEv2/rtl/EthMacPrepareForICrc.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxCheckICrc", - "path": "ethernet/RoCEv2/rtl/EthMacRxCheckICrc.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxRoCEv2", - "path": "ethernet/RoCEv2/rtl/EthMacRxRoCEv2.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxRoCEv2", - "path": "ethernet/RoCEv2/rtl/EthMacTxRoCEv2.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RoceConfigurator", - "path": "ethernet/RoCEv2/rtl/RoceConfigurator.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RoceEngineWrapper", - "path": "ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RoceResizeAndSwap", - "path": "ethernet/RoCEv2/rtl/RoceResizeAndSwap.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthReg", - "path": "ethernet/TenGigEthCore/core/rtl/TenGigEthReg.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthRst", - "path": "ethernet/TenGigEthCore/core/rtl/TenGigEthRst.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGth7", - "path": "ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGth7Clk", - "path": "ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Clk.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGth7Wrapper", - "path": "ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScale", - "path": "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleClk", - "path": "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleClk.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleRst", - "path": "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleRst.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleWrapper", - "path": "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScale", - "path": "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleClk", - "path": "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleClk.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleRst", - "path": "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleRst.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleWrapper", - "path": "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtx7", - "path": "ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtx7Clk", - "path": "ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Clk.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtx7Wrapper", - "path": "ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtyUltraScale", - "path": "ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtyUltraScaleClk", - "path": "ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleClk.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtyUltraScaleRst", - "path": "ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleRst.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtyUltraScaleWrapper", - "path": "ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ArpIpTable", - "path": "ethernet/UdpEngine/rtl/ArpIpTable.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngine", - "path": "ethernet/UdpEngine/rtl/UdpEngine.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngineArp", - "path": "ethernet/UdpEngine/rtl/UdpEngineArp.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngineDhcp", - "path": "ethernet/UdpEngine/rtl/UdpEngineDhcp.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngineRx", - "path": "ethernet/UdpEngine/rtl/UdpEngineRx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngineTx", - "path": "ethernet/UdpEngine/rtl/UdpEngineTx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngineWrapper", - "path": "ethernet/UdpEngine/rtl/UdpEngineWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiReg", - "path": "ethernet/XauiCore/core/rtl/XauiReg.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGth7", - "path": "ethernet/XauiCore/gth7/rtl/XauiGth7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGth7Core", - "path": "ethernet/XauiCore/gth7/rtl/XauiGth7Core.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGth7Wrapper", - "path": "ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGthUltraScale", - "path": "ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGthUltraScaleWrapper", - "path": "ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGthUltraScale", - "path": "ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGthUltraScaleWrapper", - "path": "ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGtx7", - "path": "ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGtx7Core", - "path": "ethernet/XauiCore/gtx7/rtl/XauiGtx7Core.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGtx7Wrapper", - "path": "ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGtyUltraScale", - "path": "ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGtyUltraScaleWrapper", - "path": "ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamBatcher", - "path": "protocols/batcher/rtl/AxiStreamBatcher.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamBatcherAxil", - "path": "protocols/batcher/rtl/AxiStreamBatcherAxil.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamBatcherEventBuilder", - "path": "protocols/batcher/rtl/AxiStreamBatcherEventBuilder.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkDataClk", - "path": "protocols/clink/7Series/ClinkDataClk.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkDataShift", - "path": "protocols/clink/7Series/ClinkDataShift.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkDataClk", - "path": "protocols/clink/UltraScale/ClinkDataClk.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkDataShift", - "path": "protocols/clink/UltraScale/ClinkDataShift.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkCtrl", - "path": "protocols/clink/rtl/ClinkCtrl.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkData", - "path": "protocols/clink/rtl/ClinkData.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkFraming", - "path": "protocols/clink/rtl/ClinkFraming.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkReg", - "path": "protocols/clink/rtl/ClinkReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkTop", - "path": "protocols/clink/rtl/ClinkTop.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkUart", - "path": "protocols/clink/rtl/ClinkUart.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkUartThrottle", - "path": "protocols/clink/rtl/ClinkUartThrottle.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressAxiL", - "path": "protocols/coaxpress/core/rtl/CoaXPressAxiL.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressConfig", - "path": "protocols/coaxpress/core/rtl/CoaXPressConfig.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressCore", - "path": "protocols/coaxpress/core/rtl/CoaXPressCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressEventAckMsg", - "path": "protocols/coaxpress/core/rtl/CoaXPressEventAckMsg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberBridge", - "path": "protocols/coaxpress/core/rtl/CoaXPressOverFiberBridge.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberBridgeRx", - "path": "protocols/coaxpress/core/rtl/CoaXPressOverFiberBridgeRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberBridgeTx", - "path": "protocols/coaxpress/core/rtl/CoaXPressOverFiberBridgeTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressRx", - "path": "protocols/coaxpress/core/rtl/CoaXPressRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressRxHsFsm", - "path": "protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressRxLane", - "path": "protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressRxLaneMux", - "path": "protocols/coaxpress/core/rtl/CoaXPressRxLaneMux.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressRxWordPacker", - "path": "protocols/coaxpress/core/rtl/CoaXPressRxWordPacker.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressTx", - "path": "protocols/coaxpress/core/rtl/CoaXPressTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressTxLsFsm", - "path": "protocols/coaxpress/core/rtl/CoaXPressTxLsFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberGthUsIpWrapper", - "path": "protocols/coaxpress/gthUs+/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGthUs", - "path": "protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGthUsQpll", - "path": "protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberGthUsIpWrapper", - "path": "protocols/coaxpress/gthUs/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGthUs", - "path": "protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGthUsQpll", - "path": "protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberGtyUsIpWrapper", - "path": "protocols/coaxpress/gtyUs+/rtl/CoaXPressOverFiberGtyUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGtyUs", - "path": "protocols/coaxpress/gtyUs+/rtl/CoaxpressOverFiberGtyUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGtyUsQpll", - "path": "protocols/coaxpress/gtyUs+/rtl/CoaxpressOverFiberGtyUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EventFrameSequencerDemux", - "path": "protocols/event-frame-sequencer/rtl/EventFrameSequencerDemux.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EventFrameSequencerMux", - "path": "protocols/event-frame-sequencer/rtl/EventFrameSequencerMux.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EventFrameSequencerWrapper", - "path": "protocols/event-frame-sequencer/wrappers/EventFrameSequencerWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkDecoder", - "path": "protocols/glink/core/rtl/GLinkDecoder.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkEncoder", - "path": "protocols/glink/core/rtl/GLinkEncoder.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkTxToRx", - "path": "protocols/glink/core/rtl/GLinkTxToRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkGtp7FixedLat", - "path": "protocols/glink/gtp7/rtl/GLinkGtp7FixedLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkGtx7Core", - "path": "protocols/glink/gtx7/rtl/GLinkGtx7Core.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkGtx7FixedLat", - "path": "protocols/glink/gtx7/rtl/GLinkGtx7FixedLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkGtx7RxRst", - "path": "protocols/glink/gtx7/rtl/GLinkGtx7RxRst.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HammingEccDecoder", - "path": "protocols/hamming-ecc/rtl/HammingEccDecoder.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HammingEccEncoder", - "path": "protocols/hamming-ecc/rtl/HammingEccEncoder.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HammingEccWrapper", - "path": "protocols/hamming-ecc/wrappers/HammingEccWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspAxiL", - "path": "protocols/htsp/core/rtl/HtspAxiL.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspCore", - "path": "protocols/htsp/core/rtl/HtspCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspRx", - "path": "protocols/htsp/core/rtl/HtspRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspRxFifo", - "path": "protocols/htsp/core/rtl/HtspRxFifo.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspTx", - "path": "protocols/htsp/core/rtl/HtspTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspTxFifo", - "path": "protocols/htsp/core/rtl/HtspTxFifo.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspCaui4Gty", - "path": "protocols/htsp/gtyUs+/rtl/HtspCaui4Gty.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiI2cEeprom", - "path": "protocols/i2c/axi/AxiI2cEeprom.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiI2cEepromCore", - "path": "protocols/i2c/axi/AxiI2cEepromCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiI2cRegMaster", - "path": "protocols/i2c/axi/AxiI2cRegMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiI2cRegMasterCore", - "path": "protocols/i2c/axi/AxiI2cRegMasterCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLiteCrossbarI2cMux", - "path": "protocols/i2c/axi/AxiLiteCrossbarI2cMux.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cMaster", - "path": "protocols/i2c/rtl/I2cMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRegMaster", - "path": "protocols/i2c/rtl/I2cRegMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRegMasterAxiBridge", - "path": "protocols/i2c/rtl/I2cRegMasterAxiBridge.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRegMasterMux", - "path": "protocols/i2c/rtl/I2cRegMasterMux.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRegSlave", - "path": "protocols/i2c/rtl/I2cRegSlave.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cSlave", - "path": "protocols/i2c/rtl/I2cSlave.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2c_master_bit_ctrl", - "path": "protocols/i2c/rtl/i2c_master_bit_ctrl.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2c_master_byte_ctrl", - "path": "protocols/i2c/rtl/i2c_master_byte_ctrl.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2c2ahb", - "path": "protocols/i2c/rtl/orig/i2c2ahb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2c2ahb_apb", - "path": "protocols/i2c/rtl/orig/i2c2ahb_apb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2c2ahbx", - "path": "protocols/i2c/rtl/orig/i2c2ahbx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2cmst", - "path": "protocols/i2c/rtl/orig/i2cmst.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2cmst_gen", - "path": "protocols/i2c/rtl/orig/i2cmst_gen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2cslv", - "path": "protocols/i2c/rtl/orig/i2cslv.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRamSlave", - "path": "protocols/i2c/sim/I2cRamSlave.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRegTb", - "path": "protocols/i2c/sim/I2cRegTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd16bTo32b", - "path": "protocols/jesd204b/rtl/Jesd16bTo32b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd204bRx", - "path": "protocols/jesd204b/rtl/Jesd204bRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd204bTx", - "path": "protocols/jesd204b/rtl/Jesd204bTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd32bTo16b", - "path": "protocols/jesd204b/rtl/Jesd32bTo16b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd32bTo64b", - "path": "protocols/jesd204b/rtl/Jesd32bTo64b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd64bTo32b", - "path": "protocols/jesd204b/rtl/Jesd64bTo32b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdAlignChGen", - "path": "protocols/jesd204b/rtl/JesdAlignChGen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdAlignFrRepCh", - "path": "protocols/jesd204b/rtl/JesdAlignFrRepCh.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdIlasGen", - "path": "protocols/jesd204b/rtl/JesdIlasGen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdLmfcGen", - "path": "protocols/jesd204b/rtl/JesdLmfcGen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdRxLane", - "path": "protocols/jesd204b/rtl/JesdRxLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdRxReg", - "path": "protocols/jesd204b/rtl/JesdRxReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdSyncFsmRx", - "path": "protocols/jesd204b/rtl/JesdSyncFsmRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdSyncFsmTx", - "path": "protocols/jesd204b/rtl/JesdSyncFsmTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdSyncFsmTxTest", - "path": "protocols/jesd204b/rtl/JesdSyncFsmTxTest.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdSysrefMon", - "path": "protocols/jesd204b/rtl/JesdSysrefMon.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdTestSigGen", - "path": "protocols/jesd204b/rtl/JesdTestSigGen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdTestStreamTx", - "path": "protocols/jesd204b/rtl/JesdTestStreamTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdTxLane", - "path": "protocols/jesd204b/rtl/JesdTxLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdTxReg", - "path": "protocols/jesd204b/rtl/JesdTxReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdTxTest", - "path": "protocols/jesd204b/rtl/JesdTxTest.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "iq16bTo32b", - "path": "protocols/jesd204b/rtl/iq16bTo32b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "iq32bTo16b", - "path": "protocols/jesd204b/rtl/iq32bTo16b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "DescrambleTb", - "path": "protocols/jesd204b/sim/DescrambleTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd204bTb", - "path": "protocols/jesd204b/sim/Jesd204bTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ScramblerTb", - "path": "protocols/jesd204b/sim/ScramblerTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Decoder10b12b", - "path": "protocols/line-codes/rtl/Decoder10b12b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Decoder12b14b", - "path": "protocols/line-codes/rtl/Decoder12b14b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Decoder8b10b", - "path": "protocols/line-codes/rtl/Decoder8b10b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Encoder10b12b", - "path": "protocols/line-codes/rtl/Encoder10b12b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Encoder12b14b", - "path": "protocols/line-codes/rtl/Encoder12b14b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Encoder8b10b", - "path": "protocols/line-codes/rtl/Encoder8b10b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Code10b12bPkgWrapper", - "path": "protocols/line-codes/wrappers/Code10b12bPkgWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Code12b14bPkgWrapper", - "path": "protocols/line-codes/wrappers/Code12b14bPkgWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Code8b10bPkgWrapper", - "path": "protocols/line-codes/wrappers/Code8b10bPkgWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "MdioCore", - "path": "protocols/mdio/rtl/MdioCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "MdioLinkIrqHandler", - "path": "protocols/mdio/rtl/MdioLinkIrqHandler.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "MdioSeqCore", - "path": "protocols/mdio/rtl/MdioSeqCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamBytePacker", - "path": "protocols/packetizer/rtl/AxiStreamBytePacker.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamDepacketizer", - "path": "protocols/packetizer/rtl/AxiStreamDepacketizer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamDepacketizer2", - "path": "protocols/packetizer/rtl/AxiStreamDepacketizer2.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamPacketizer", - "path": "protocols/packetizer/rtl/AxiStreamPacketizer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamPacketizer2", - "path": "protocols/packetizer/rtl/AxiStreamPacketizer2.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bAxi", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bLane", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bRx", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bRxCell", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bRxCell.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bRxPhy", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bRxPhy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bTx", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bTxCell", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bTxPhy", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bTxPhy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bTxSched", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGth7Fixedlat", - "path": "protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7FixedLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGth7FixedLatWrapper", - "path": "protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7FixedLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGth7MultiLane", - "path": "protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7MultiLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGth7VarLat", - "path": "protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7VarLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGth7VarLatWrapper", - "path": "protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7VarLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGthUltra", - "path": "protocols/pgp/pgp2b/gthUltraScale+/rtl/Pgp2bGthUltra.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpGthCoreWrapper", - "path": "protocols/pgp/pgp2b/gthUltraScale+/rtl/PgpGthCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGthUltra", - "path": "protocols/pgp/pgp2b/gthUltraScale/rtl/Pgp2bGthUltra.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpGthCoreWrapper", - "path": "protocols/pgp/pgp2b/gthUltraScale/rtl/PgpGthCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtp7FixedLat", - "path": "protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7FixedLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtp7FixedLatWrapper", - "path": "protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7FixedLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtp7MultiLane", - "path": "protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7MultiLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtp7VarLat", - "path": "protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7VarLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtp7VarLatWrapper", - "path": "protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7VarLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtx7Fixedlat", - "path": "protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtx7FixedLatWrapper", - "path": "protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtx7MultiLane", - "path": "protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7MultiLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtx7VarLat", - "path": "protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7VarLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtx7VarLatWrapper", - "path": "protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7VarLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtyUltra", - "path": "protocols/pgp/pgp2b/gtyUltraScale+/rtl/Pgp2bGtyUltra.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpGtyCoreWrapper", - "path": "protocols/pgp/pgp2b/gtyUltraScale+/rtl/PgpGtyCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CRC7Rtl", - "path": "protocols/pgp/pgp2fc/core/rtl/CRC7Rtl.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcAlignmentChecker", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcAlignmentChecker.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcAlignmentController", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcAlignmentController.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcAxi", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcLane", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcRx", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcRxCell", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxCell.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcRxPhy", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxPhy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcTx", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcTxCell", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxCell.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcTxPhy", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcTxSched", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxSched.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGthCoreWrapper", - "path": "protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGthUltra", - "path": "protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGtp7", - "path": "protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGtp7Wrapper", - "path": "protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7Wrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGtyCoreWrapper", - "path": "protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGtyUltra", - "path": "protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3AxiL", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3AxiL.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Core", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3Core.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Rx", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3Rx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3RxEb", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3RxEb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3RxGearboxAligner", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3RxGearboxAligner.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3RxProtocol", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3RxProtocol.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Tx", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3Tx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3TxProtocol", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3TxProtocol.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUs", - "path": "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsIpWrapper", - "path": "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsQpll", - "path": "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsWrapper", - "path": "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUs", - "path": "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsIpWrapper", - "path": "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsQpll", - "path": "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsWrapper", - "path": "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7IpWrapper", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7IpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7Qpll", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7Qpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7RxGearbox", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7RxGearbox.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7TxGearbox", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7TxGearbox.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7Wrapper", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7Wrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtx7", - "path": "protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtx7IpWrapper", - "path": "protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7IpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtx7Qpll", - "path": "protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Qpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtx7Wrapper", - "path": "protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Wrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GtyUs", - "path": "protocols/pgp/pgp3/gtyUs+/rtl/Pgp3GtyUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GtyUsIpWrapper", - "path": "protocols/pgp/pgp3/gtyUs+/rtl/Pgp3GtyUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GtyUsQpll", - "path": "protocols/pgp/pgp3/gtyUs+/rtl/Pgp3GtyUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GtyUsWrapper", - "path": "protocols/pgp/pgp3/gtyUs+/rtl/Pgp3GtyUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4AxiL", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4AxiL.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Core", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4Core.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4CoreLite", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4CoreLite.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Rx", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4RxEb", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4LiteRxLowSpeed", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4RxLiteLowSpeed.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4RxLiteLowSpeedLane", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4RxLiteLowSpeedLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4RxLiteLowSpeedReg", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4RxLiteLowSpeedReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4RxProtocol", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4RxProtocol.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Tx", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4Tx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4TxLite", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4TxLite.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4TxLiteProtocol", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4TxLiteProtocol.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4TxLiteWrapper", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4TxProtocol", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4TxProtocol.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4CoreLiteWrapper", - "path": "protocols/pgp/pgp4/core/wrappers/Pgp4CoreLiteWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4CoreWrapper", - "path": "protocols/pgp/pgp4/core/wrappers/Pgp4CoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GthUs", - "path": "protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GthUsWrapper", - "path": "protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GthUs", - "path": "protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GthUsWrapper", - "path": "protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Gtp7", - "path": "protocols/pgp/pgp4/gtp7/rtl/Pgp4Gtp7.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Gtp7Wrapper", - "path": "protocols/pgp/pgp4/gtp7/rtl/Pgp4Gtp7Wrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Gtx7", - "path": "protocols/pgp/pgp4/gtx7/rtl/Pgp4Gtx7.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Gtx7Wrapper", - "path": "protocols/pgp/pgp4/gtx7/rtl/Pgp4Gtx7Wrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GtyUs", - "path": "protocols/pgp/pgp4/gtyUs+/rtl/Pgp4GtyUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GtyUsIpFecWrapper", - "path": "protocols/pgp/pgp4/gtyUs+/rtl/Pgp4GtyUsIpFecWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GtyUsWrapper", - "path": "protocols/pgp/pgp4/gtyUs+/rtl/Pgp4GtyUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpRxVcFifo", - "path": "protocols/pgp/shared/PgpRxVcFifo.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpTxVcFifo", - "path": "protocols/pgp/shared/PgpTxVcFifo.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpXvcWrapper", - "path": "protocols/pgp/shared/xilinx/PgpXvcWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLitePMbusMaster", - "path": "protocols/pmbus/rtl/AxiLitePMbusMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLitePMbusMasterCore", - "path": "protocols/pmbus/rtl/AxiLitePMbusMasterCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiAxiLiteRegItf", - "path": "protocols/rssi/v1/rtl/RssiAxiLiteRegItf.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiChksum", - "path": "protocols/rssi/v1/rtl/RssiChksum.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiConnFsm", - "path": "protocols/rssi/v1/rtl/RssiConnFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiCore", - "path": "protocols/rssi/v1/rtl/RssiCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiCoreWrapper", - "path": "protocols/rssi/v1/rtl/RssiCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiHeaderReg", - "path": "protocols/rssi/v1/rtl/RssiHeaderReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiMonitor", - "path": "protocols/rssi/v1/rtl/RssiMonitor.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiParamSync", - "path": "protocols/rssi/v1/rtl/RssiParamSync.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiRxFsm", - "path": "protocols/rssi/v1/rtl/RssiRxFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiTxFsm", - "path": "protocols/rssi/v1/rtl/RssiTxFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLiteSaciMaster", - "path": "protocols/saci/saci1/rtl/AxiLiteSaciMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciAxiLiteMaster", - "path": "protocols/saci/saci1/rtl/SaciAxiLiteMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciMaster", - "path": "protocols/saci/saci1/rtl/SaciMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciMaster2", - "path": "protocols/saci/saci1/rtl/SaciMaster2.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciMasterSync", - "path": "protocols/saci/saci1/rtl/SaciMasterSync.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciMultiPixel", - "path": "protocols/saci/saci1/rtl/SaciMultiPixel.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciPrepRdout", - "path": "protocols/saci/saci1/rtl/SaciPrepRdout.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciSlave", - "path": "protocols/saci/saci1/rtl/SaciSlave.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciSlaveOld", - "path": "protocols/saci/saci1/rtl/SaciSlaveOld.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLiteSaciMasterTb", - "path": "protocols/saci/saci1/sim/AxiLiteSaciMasterTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciAxiLiteMasterTb", - "path": "protocols/saci/saci1/sim/SaciAxiLiteMasterTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciAxiLiteMasterTbWrapper", - "path": "protocols/saci/saci1/sim/SaciAxiLiteMasterTbWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciSlaveRam", - "path": "protocols/saci/saci1/sim/SaciSlaveRam.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciSlaveWrapper", - "path": "protocols/saci/saci1/sim/SaciSlaveWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciAxiLiteMasterWrapper", - "path": "protocols/saci/saci1/wrappers/SaciAxiLiteMasterWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLiteToSaci2", - "path": "protocols/saci/saci2/rtl/AxiLiteToSaci2.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Saci2Coordinator", - "path": "protocols/saci/saci2/rtl/Saci2Coordinator.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Saci2Subordinate", - "path": "protocols/saci/saci2/rtl/Saci2Subordinate.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Saci2ToAxiLite", - "path": "protocols/saci/saci2/rtl/Saci2ToAxiLite.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Saci2ToAxiLiteTb", - "path": "protocols/saci/saci2/sim/Saci2ToAxiLiteTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Saci2ToAxiLiteWrapper", - "path": "protocols/saci/saci2/wrappers/Saci2ToAxiLiteWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltRxDeser", - "path": "protocols/salt/rtl/7Series/SaltRxDeser.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltTxSer", - "path": "protocols/salt/rtl/7Series/SaltTxSer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltCore", - "path": "protocols/salt/rtl/SaltCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltDelayCtrl", - "path": "protocols/salt/rtl/SaltDelayCtrl.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltRx", - "path": "protocols/salt/rtl/SaltRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltRxLvds", - "path": "protocols/salt/rtl/SaltRxLvds.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltTx", - "path": "protocols/salt/rtl/SaltTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltTxLvds", - "path": "protocols/salt/rtl/SaltTxLvds.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltTxResize", - "path": "protocols/salt/rtl/SaltTxResize.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltRxDeser", - "path": "protocols/salt/rtl/UltraScale/SaltRxDeser.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltTxSer", - "path": "protocols/salt/rtl/UltraScale/SaltTxSer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiSpiMaster", - "path": "protocols/spi/rtl/AxiSpiMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SpiMaster", - "path": "protocols/spi/rtl/SpiMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SpiSlave", - "path": "protocols/spi/rtl/SpiSlave.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLiteSrpV0", - "path": "protocols/srp/rtl/AxiLiteSrpV0.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV0AxiLite", - "path": "protocols/srp/rtl/SrpV0AxiLite.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV3Axi", - "path": "protocols/srp/rtl/SrpV3Axi.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV3AxiLite", - "path": "protocols/srp/rtl/SrpV3AxiLite.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV3AxiLiteFull", - "path": "protocols/srp/rtl/SrpV3AxiLiteFull.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV3Core", - "path": "protocols/srp/rtl/SrpV3Core.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV3AxiWrapper", - "path": "protocols/srp/wrappers/SrpV3AxiWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiAxiLiteMaster", - "path": "protocols/ssi/rtl/SsiAxiLiteMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiCmdMaster", - "path": "protocols/ssi/rtl/SsiCmdMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiCmdMasterPulser", - "path": "protocols/ssi/rtl/SsiCmdMasterPulser.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiDbgTap", - "path": "protocols/ssi/rtl/SsiDbgTap.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiFifo", - "path": "protocols/ssi/rtl/SsiFifo.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiFrameLimiter", - "path": "protocols/ssi/rtl/SsiFrameLimiter.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiIbFrameFilter", - "path": "protocols/ssi/rtl/SsiIbFrameFilter.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiIncrementingTx", - "path": "protocols/ssi/rtl/SsiIncrementingTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiInsertSof", - "path": "protocols/ssi/rtl/SsiInsertSof.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiObFrameFilter", - "path": "protocols/ssi/rtl/SsiObFrameFilter.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiPrbsRateGen", - "path": "protocols/ssi/rtl/SsiPrbsRateGen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiPrbsRx", - "path": "protocols/ssi/rtl/SsiPrbsRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiPrbsTx", - "path": "protocols/ssi/rtl/SsiPrbsTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiPrbsWrapper", - "path": "protocols/ssi/wrappers/SsiPrbsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiResizeFifoEofeWrapper", - "path": "protocols/ssi/wrappers/SsiResizeFifoEofeWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspDecoder10b12b", - "path": "protocols/ssp/rtl/SspDecoder10b12b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspDecoder12b14b", - "path": "protocols/ssp/rtl/SspDecoder12b14b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspDecoder8b10b", - "path": "protocols/ssp/rtl/SspDecoder8b10b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspDeframer", - "path": "protocols/ssp/rtl/SspDeframer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspEncoder10b12b", - "path": "protocols/ssp/rtl/SspEncoder10b12b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspEncoder12b14b", - "path": "protocols/ssp/rtl/SspEncoder12b14b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspEncoder8b10b", - "path": "protocols/ssp/rtl/SspEncoder8b10b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspFramer", - "path": "protocols/ssp/rtl/SspFramer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspLowSpeedDecoder10b12bWrapper", - "path": "protocols/ssp/rtl/SspLowSpeedDecoder10b12bWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspLowSpeedDecoder12b14bWrapper", - "path": "protocols/ssp/rtl/SspLowSpeedDecoder12b14bWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspLowSpeedDecoder8b10bWrapper", - "path": "protocols/ssp/rtl/SspLowSpeedDecoder8b10bWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspLowSpeedDecoderLane", - "path": "protocols/ssp/rtl/SspLowSpeedDecoderLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspLowSpeedDecoderReg", - "path": "protocols/ssp/rtl/SspLowSpeedDecoderReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerRx7Series", - "path": "protocols/sugoi/rtl/7Series/SugoiManagerRx7Series.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiAxiLitePixelMatrixConfig", - "path": "protocols/sugoi/rtl/SugoiAxiLitePixelMatrixConfig.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerCore", - "path": "protocols/sugoi/rtl/SugoiManagerCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerFsm", - "path": "protocols/sugoi/rtl/SugoiManagerFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerRx", - "path": "protocols/sugoi/rtl/SugoiManagerRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiSubordinateCore", - "path": "protocols/sugoi/rtl/SugoiSubordinateCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiSubordinateFsm", - "path": "protocols/sugoi/rtl/SugoiSubordinateFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerRxUltrascale", - "path": "protocols/sugoi/rtl/UltraScale/SugoiManagerRxUltrascale.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerRx7Series", - "path": "protocols/sugoi/rtl/dummy/SugoiManagerRx7SeriesDummy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerRxUltrascale", - "path": "protocols/sugoi/rtl/dummy/SugoiManagerRxUltrascaleDummy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartAxiLiteMaster", - "path": "protocols/uart/rtl/UartAxiLiteMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartAxiLiteMasterFsm", - "path": "protocols/uart/rtl/UartAxiLiteMasterFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartBrg", - "path": "protocols/uart/rtl/UartBrg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartRx", - "path": "protocols/uart/rtl/UartRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartTx", - "path": "protocols/uart/rtl/UartTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartWrapper", - "path": "protocols/uart/rtl/UartWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartAxiLiteMasterTb", - "path": "protocols/uart/sim/UartAxiLiteMasterTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Idelaye3Wrapper", - "path": "xilinx/7Series/dummy/Idelaye3WrapperDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Odelaye3Wrapper", - "path": "xilinx/7Series/dummy/Odelaye3WrapperDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClockManager7", - "path": "xilinx/7Series/general/rtl/ClockManager7.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DeviceDna7Series", - "path": "xilinx/7Series/general/rtl/DeviceDna7Series.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Dsp48Comparator4x12b", - "path": "xilinx/7Series/general/rtl/Dsp48Comparator4x12b.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "InputBufferReg", - "path": "xilinx/7Series/general/rtl/InputBufferReg.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Iprog7Series", - "path": "xilinx/7Series/general/rtl/Iprog7Series.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Iprog7SeriesCore", - "path": "xilinx/7Series/general/rtl/Iprog7SeriesCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "OutputBufferReg", - "path": "xilinx/7Series/general/rtl/OutputBufferReg.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SelectioDeser7Series", - "path": "xilinx/7Series/general/rtl/SelectioDeser7Series.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SelectioDeserLane7Series", - "path": "xilinx/7Series/general/rtl/SelectioDeserLane7Series.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7AutoPhaseAligner", - "path": "xilinx/7Series/gth7/rtl/Gth7AutoPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7Core", - "path": "xilinx/7Series/gth7/rtl/Gth7Core.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7QuadPll", - "path": "xilinx/7Series/gth7/rtl/Gth7QuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7RecClkMonitor", - "path": "xilinx/7Series/gth7/rtl/Gth7RecClkMonitor.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7RxFixedLatPhaseAligner", - "path": "xilinx/7Series/gth7/rtl/Gth7RxFixedLatPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7RxRst", - "path": "xilinx/7Series/gth7/rtl/Gth7RxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7RxRstSeq", - "path": "xilinx/7Series/gth7/rtl/Gth7RxRstSeq.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7TxManualPhaseAligner", - "path": "xilinx/7Series/gth7/rtl/Gth7TxManualPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7TxRst", - "path": "xilinx/7Series/gth7/rtl/Gth7TxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7AutoPhaseAligner", - "path": "xilinx/7Series/gtp7/rtl/Gtp7AutoPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7Core", - "path": "xilinx/7Series/gtp7/rtl/Gtp7Core.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7QuadPll", - "path": "xilinx/7Series/gtp7/rtl/Gtp7QuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7RecClkMonitor", - "path": "xilinx/7Series/gtp7/rtl/Gtp7RecClkMonitor.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7RxFixedLatPhaseAligner", - "path": "xilinx/7Series/gtp7/rtl/Gtp7RxFixedLatPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7RxRst", - "path": "xilinx/7Series/gtp7/rtl/Gtp7RxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7RxRstSeq", - "path": "xilinx/7Series/gtp7/rtl/Gtp7RxRstSeq.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7TxManualPhaseAligner", - "path": "xilinx/7Series/gtp7/rtl/Gtp7TxManualPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7TxRst", - "path": "xilinx/7Series/gtp7/rtl/Gtp7TxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtpe2ChannelDummy", - "path": "xilinx/7Series/gtp7/rtl/Gtpe2ChannelDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7AutoPhaseAligner", - "path": "xilinx/7Series/gtx7/rtl/Gtx7AutoPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7Core", - "path": "xilinx/7Series/gtx7/rtl/Gtx7Core.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7QuadPll", - "path": "xilinx/7Series/gtx7/rtl/Gtx7QuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7RecClkMonitor", - "path": "xilinx/7Series/gtx7/rtl/Gtx7RecClkMonitor.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7RxFixedLatPhaseAligner", - "path": "xilinx/7Series/gtx7/rtl/Gtx7RxFixedLatPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7RxRst", - "path": "xilinx/7Series/gtx7/rtl/Gtx7RxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7TxManualPhaseAligner", - "path": "xilinx/7Series/gtx7/rtl/Gtx7TxManualPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7TxRst", - "path": "xilinx/7Series/gtx7/rtl/Gtx7TxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtxe2ChannelDummy", - "path": "xilinx/7Series/gtx7/rtl/Gtxe2ChannelDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SemWrapper", - "path": "xilinx/7Series/sem/rtl/SemWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SsiSem", - "path": "xilinx/7Series/sem/rtl/SsiSem.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UartSem", - "path": "xilinx/7Series/sem/rtl/UartSem.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiXadcMinimumCore", - "path": "xilinx/7Series/xadc/rtl/AxiXadcMinimumCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "XadcSimpleCore", - "path": "xilinx/7Series/xadc/rtl/XadcSimpleCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClockManagerUltraScale", - "path": "xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GthUltraScaleQuadPll", - "path": "xilinx/UltraScale+/gthUs+/rtl/GthUltraScaleQuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gthe4ChannelDummy", - "path": "xilinx/UltraScale+/gthUs+/rtl/Gthe4ChannelDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GtyUltraScaleQuadPll", - "path": "xilinx/UltraScale+/gtyUs+/rtl/GtyUltraScaleQuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtye4ChannelDummy", - "path": "xilinx/UltraScale+/gtyUs+/rtl/Gtye4ChannelDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClockManagerUltraScale", - "path": "xilinx/UltraScale/clocking/rtl/ClockManagerUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Delaye3PatchFsm", - "path": "xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DeviceDnaUltraScale", - "path": "xilinx/UltraScale/general/rtl/DeviceDnaUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Idelaye3Wrapper", - "path": "xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "InputBufferReg", - "path": "xilinx/UltraScale/general/rtl/InputBufferReg.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "IprogUltraScale", - "path": "xilinx/UltraScale/general/rtl/IprogUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Odelaye3Wrapper", - "path": "xilinx/UltraScale/general/rtl/Odelaye3Wrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "OutputBufferReg", - "path": "xilinx/UltraScale/general/rtl/OutputBufferReg.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SelectioDeserLaneUltraScale", - "path": "xilinx/UltraScale/general/rtl/SelectioDeserLaneUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SelectioDeserUltraScale", - "path": "xilinx/UltraScale/general/rtl/SelectioDeserUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GthUltraScaleQuadPll", - "path": "xilinx/UltraScale/gthUs/rtl/GthUltraScaleQuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gthe3ChannelDummy", - "path": "xilinx/UltraScale/gthUs/rtl/Gthe3ChannelDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClockManagerVersal", - "path": "xilinx/Versal/clocking/rtl/ClockManagerVersal.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp16FixedLatCore", - "path": "xilinx/Virtex5/gtp/rtl/Gtp16FixedLatCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GtpDualFixedLatCore", - "path": "xilinx/Virtex5/gtp/rtl/GtpDualFixedLatCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GtpRxCommaAligner", - "path": "xilinx/Virtex5/gtp/rtl/GtpRxCommaAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GtpTxPhaseAligner", - "path": "xilinx/Virtex5/gtp/rtl/GtpTxPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClkOutBufDiff", - "path": "xilinx/dummy/ClkOutBufDiffDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClkOutBufSingle", - "path": "xilinx/dummy/ClkOutBufSingleDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DeviceDna", - "path": "xilinx/dummy/DeviceDnaDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "IoBufWrapper", - "path": "xilinx/dummy/IoBufWrapperDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Iprog", - "path": "xilinx/dummy/IprogDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "OutputBufferReg", - "path": "xilinx/dummy/OutputBufferRegDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Srl16Delay", - "path": "xilinx/dummy/Srl16DelayDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "MicroblazeBasicCoreWrapper", - "path": "xilinx/general/microblaze/bypass/MicroblazeBasicCoreWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "MicroblazeBasicCoreWrapper", - "path": "xilinx/general/microblaze/generate/MicroblazeBasicCoreWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClkOutBufDiff", - "path": "xilinx/general/rtl/ClkOutBufDiff.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClkOutBufSingle", - "path": "xilinx/general/rtl/ClkOutBufSingle.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DeviceDna", - "path": "xilinx/general/rtl/DeviceDna.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GtRxAlignCheck", - "path": "xilinx/general/rtl/GtRxAlignCheck.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "IoBufWrapper", - "path": "xilinx/general/rtl/IoBufWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Iprog", - "path": "xilinx/general/rtl/Iprog.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SelectIoRxGearboxAligner", - "path": "xilinx/general/rtl/SelectIoRxGearboxAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Srl16Delay", - "path": "xilinx/general/rtl/Srl16Delay.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/7Series/Impl/images/UdpDebugBridge_stub.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/7Series/Stub/images/UdpDebugBridge_stub.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/UltraScale/Impl/images/UdpDebugBridge_stub.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/UltraScale/Stub/images/UdpDebugBridge_stub.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridgeWrapper", - "path": "xilinx/xvc-udp/dcp/core/UdpDebugBridgeWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiStreamSelector", - "path": "xilinx/xvc-udp/jtag/rtl/AxiStreamSelector.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxisJtagDebugBridge", - "path": "xilinx/xvc-udp/jtag/rtl/AxisJtagDebugBridge.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxisToJtag", - "path": "xilinx/xvc-udp/jtag/rtl/AxisToJtag.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxisToJtagCore", - "path": "xilinx/xvc-udp/jtag/rtl/AxisToJtagCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "JtagSerDesCore", - "path": "xilinx/xvc-udp/jtag/rtl/JtagSerDesCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DmaXvcWrapper", - "path": "xilinx/xvc-udp/rtl/DmaXvcWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridgeWrapper", - "path": "xilinx/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - } - ], - "unresolved_phase1_edges": [] -} diff --git a/docs/_meta/rtl_phase1_queue.md b/docs/_meta/rtl_phase1_queue.md deleted file mode 100644 index 6b39ac00f6..0000000000 --- a/docs/_meta/rtl_phase1_queue.md +++ /dev/null @@ -1,272 +0,0 @@ -# SURF RTL Phase-1 Queue - -## Scope -- Scan dirs: `base, axi, dsp, protocols, ethernet, devices, xilinx` -- Queue nodes are path-qualified RTL entity definitions, not bare entity names. -- Queue order is bottom-up: leaves first, higher-level assemblies later. -- Manual phase-1 deferrals and order overrides live in `docs/_meta/rtl_phase1_queue_overrides.json`. - -## Summary -- Phase-1 modules: `219` -- Phase-1 dependency edges: `392` -- Bottom-up layers: `10` -- Deferred modules: `632` -- Unresolved duplicate-name phase-1 edges: `0` -- Applied order overrides: `0` - -## Phase-1 Filters -- Force-included entities: - - None -- Force-included paths: - - None -- Deferred subsystems: - - `ethernet`: Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first. - - `protocols`: Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first. - - `devices`: Subsystem is currently dominated by vendor-heavy modules in phase 1. - - `xilinx`: Subsystem is currently dominated by vendor-heavy modules in phase 1. -- Deferred entities: - - `LutFixedDelay`: Depends on SinglePortRamPrimitive under the current open-source flow. -- Deferred exact paths: - - None -- Deferred path substrings: - - `axi/simlink/`: Simulation support models are not part of the synthesizable phase-1 queue. - - `/sim/`: Simulation-only support modules are not part of the synthesizable phase-1 queue. - - `/dummy/`: Dummy-backed variants are deferred from the phase-1 executable queue. - - `/altera/`: Vendor-specific implementation branches are deferred in phase 1. - - `/xilinx/`: Vendor-specific implementation branches are deferred in phase 1. - - `7Series`: Family-specific implementation branches are deferred in phase 1. - - `UltraScale`: Family-specific implementation branches are deferred in phase 1. - - `UltraScale+`: Family-specific implementation branches are deferred in phase 1. - - `/gth`: GT-family implementation branches are deferred in phase 1. - - `/gtp`: GT-family implementation branches are deferred in phase 1. - - `/gty`: GT-family implementation branches are deferred in phase 1. - - `/gtx`: GT-family implementation branches are deferred in phase 1. - -## Manual Order Overrides -- None - -## Unresolved Duplicate-Name Phase-1 Edges -- None - -## Flat Bottom-Up Order -| order | layer | entity | subsystem | path | instantiated_by_count | -| --- | --- | --- | --- | --- | --- | -| 1 | 0 | AxiLiteCrossbar | axi | axi/axi-lite/rtl/AxiLiteCrossbar.vhd | 3 | -| 2 | 0 | AxiLiteMaster | axi | axi/axi-lite/rtl/AxiLiteMaster.vhd | 6 | -| 3 | 0 | AxiLiteRegs | axi | axi/axi-lite/rtl/AxiLiteRegs.vhd | 2 | -| 4 | 0 | AxiLiteRespTimer | axi | axi/axi-lite/rtl/AxiLiteRespTimer.vhd | 1 | -| 5 | 0 | AxiLiteSlave | axi | axi/axi-lite/rtl/AxiLiteSlave.vhd | 2 | -| 6 | 0 | AxiLiteWriteFilter | axi | axi/axi-lite/rtl/AxiLiteWriteFilter.vhd | 1 | -| 7 | 0 | AxiVersion | axi | axi/axi-lite/rtl/AxiVersion.vhd | 1 | -| 8 | 0 | AxiStreamCombiner | axi | axi/axi-stream/rtl/AxiStreamCombiner.vhd | 1 | -| 9 | 0 | AxiStreamFlush | axi | axi/axi-stream/rtl/AxiStreamFlush.vhd | 1 | -| 10 | 0 | AxiStreamGearboxPack | axi | axi/axi-stream/rtl/AxiStreamGearboxPack.vhd | 1 | -| 11 | 0 | AxiStreamGearboxUnpack | axi | axi/axi-stream/rtl/AxiStreamGearboxUnpack.vhd | 1 | -| 12 | 0 | AxiStreamPipeline | axi | axi/axi-stream/rtl/AxiStreamPipeline.vhd | 18 | -| 13 | 0 | AxiStreamSplitter | axi | axi/axi-stream/rtl/AxiStreamSplitter.vhd | 1 | -| 14 | 0 | AxiStreamPkgWrapper | axi | axi/axi-stream/wrappers/AxiStreamPkgWrapper.vhd | 0 | -| 15 | 0 | AxiReadPathMux | axi | axi/axi4/rtl/AxiReadPathMux.vhd | 1 | -| 16 | 0 | AxiResize | axi | axi/axi4/rtl/AxiResize.vhd | 1 | -| 17 | 0 | AxiWritePathMux | axi | axi/axi4/rtl/AxiWritePathMux.vhd | 1 | -| 18 | 0 | AxiToAxiLite | axi | axi/bridge/rtl/AxiToAxiLite.vhd | 1 | -| 19 | 0 | AxiStreamDmaV2WriteMux | axi | axi/dma/rtl/v2/AxiStreamDmaV2WriteMux.vhd | 2 | -| 20 | 0 | CRC32Rtl | base | base/crc/rtl/CRC32Rtl.vhd | 0 | -| 21 | 0 | Crc32 | base | base/crc/rtl/Crc32.vhd | 1 | -| 22 | 0 | Crc32Parallel | base | base/crc/rtl/Crc32Parallel.vhd | 0 | -| 23 | 0 | SlvDelay | base | base/delay/rtl/SlvDelay.vhd | 0 | -| 24 | 0 | SlvDelayRam | base | base/delay/rtl/SlvDelayRam.vhd | 0 | -| 25 | 0 | SlvFixedDelay | base | base/delay/rtl/SlvFixedDelay.vhd | 0 | -| 26 | 0 | FifoOutputPipeline | base | base/fifo/rtl/FifoOutputPipeline.vhd | 7 | -| 27 | 0 | FifoRdFsm | base | base/fifo/rtl/inferred/FifoRdFsm.vhd | 2 | -| 28 | 0 | FifoWrFsm | base | base/fifo/rtl/inferred/FifoWrFsm.vhd | 2 | -| 29 | 0 | MasterRamIpIntegrator | base | base/general/ip_integrator/MasterRamIpIntegrator.vhd | 0 | -| 30 | 0 | SlaveRamIpIntegrator | base | base/general/ip_integrator/SlaveRamIpIntegrator.vhd | 0 | -| 31 | 0 | Arbiter | base | base/general/rtl/Arbiter.vhd | 0 | -| 32 | 0 | ClockDivider | base | base/general/rtl/ClockDivider.vhd | 0 | -| 33 | 0 | Gearbox | base | base/general/rtl/Gearbox.vhd | 1 | -| 34 | 0 | Heartbeat | base | base/general/rtl/Heartbeat.vhd | 1 | -| 35 | 0 | Mux | base | base/general/rtl/Mux.vhd | 0 | -| 36 | 0 | OneShot | base | base/general/rtl/OneShot.vhd | 0 | -| 37 | 0 | RegisterVector | base | base/general/rtl/RegisterVector.vhd | 0 | -| 38 | 0 | RstPipeline | base | base/general/rtl/RstPipeline.vhd | 3 | -| 39 | 0 | Scrambler | base | base/general/rtl/Scrambler.vhd | 0 | -| 40 | 0 | LutRam | base | base/ram/inferred/LutRam.vhd | 1 | -| 41 | 0 | SimpleDualPortRam | base | base/ram/inferred/SimpleDualPortRam.vhd | 6 | -| 42 | 0 | TrueDualPortRam | base | base/ram/inferred/TrueDualPortRam.vhd | 3 | -| 43 | 0 | Synchronizer | base | base/sync/rtl/Synchronizer.vhd | 13 | -| 44 | 0 | SynchronizerVector | base | base/sync/rtl/SynchronizerVector.vhd | 7 | -| 45 | 0 | FirFilterTap | dsp | dsp/generic/fixed/FirFilterTap.vhd | 2 | -| 46 | 1 | AxiLiteMasterProxy | axi | axi/axi-lite/rtl/AxiLiteMasterProxy.vhd | 1 | -| 47 | 1 | AxiLiteSequencerRam | axi | axi/axi-lite/rtl/AxiLiteSequencerRam.vhd | 1 | -| 48 | 1 | AxiStreamCompact | axi | axi/axi-stream/rtl/AxiStreamCompact.vhd | 1 | -| 49 | 1 | AxiStreamConcat | axi | axi/axi-stream/rtl/AxiStreamConcat.vhd | 1 | -| 50 | 1 | AxiStreamDeMux | axi | axi/axi-stream/rtl/AxiStreamDeMux.vhd | 2 | -| 51 | 1 | AxiStreamFrameRateLimiter | axi | axi/axi-stream/rtl/AxiStreamFrameRateLimiter.vhd | 1 | -| 52 | 1 | AxiStreamMux | axi | axi/axi-stream/rtl/AxiStreamMux.vhd | 2 | -| 53 | 1 | AxiStreamRepeater | axi | axi/axi-stream/rtl/AxiStreamRepeater.vhd | 1 | -| 54 | 1 | AxiStreamResize | axi | axi/axi-stream/rtl/AxiStreamResize.vhd | 2 | -| 55 | 1 | AxiStreamShift | axi | axi/axi-stream/rtl/AxiStreamShift.vhd | 3 | -| 56 | 1 | AxiStreamTrailerAppend | axi | axi/axi-stream/rtl/AxiStreamTrailerAppend.vhd | 1 | -| 57 | 1 | AxiStreamTrailerRemove | axi | axi/axi-stream/rtl/AxiStreamTrailerRemove.vhd | 1 | -| 58 | 1 | AxiRam | axi | axi/axi4/rtl/AxiRam.vhd | 1 | -| 59 | 1 | AxiLiteToIpBus | axi | axi/bridge/rtl/AxiLiteToIpBus.vhd | 1 | -| 60 | 1 | IpBusToAxiLite | axi | axi/bridge/rtl/IpBusToAxiLite.vhd | 1 | -| 61 | 1 | AxiStreamDmaV2WriteMuxIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2WriteMuxIpIntegrator.vhd | 0 | -| 62 | 1 | Crc32PolyWrapper | base | base/crc/wrappers/Crc32PolyWrapper.vhd | 0 | -| 63 | 1 | FifoSync | base | base/fifo/rtl/inferred/FifoSync.vhd | 2 | -| 64 | 1 | RstPipelineVector | base | base/general/rtl/RstPipelineVector.vhd | 0 | -| 65 | 1 | WatchDogRst | base | base/general/rtl/WatchDogRst.vhd | 0 | -| 66 | 1 | HeartbeatWrapper | base | base/general/wrappers/HeartbeatWrapper.vhd | 0 | -| 67 | 1 | DualPortRam | base | base/ram/inferred/DualPortRam.vhd | 4 | -| 68 | 1 | RstSync | base | base/sync/rtl/RstSync.vhd | 15 | -| 69 | 1 | SynchronizerEdge | base | base/sync/rtl/SynchronizerEdge.vhd | 1 | -| 70 | 1 | BoxcarIntegrator | dsp | dsp/generic/fixed/BoxcarIntegrator.vhd | 1 | -| 71 | 1 | DspAddSub | dsp | dsp/generic/fixed/DspAddSub.vhd | 1 | -| 72 | 1 | DspComparator | dsp | dsp/generic/fixed/DspComparator.vhd | 4 | -| 73 | 1 | DspPreSubMult | dsp | dsp/generic/fixed/DspPreSubMult.vhd | 0 | -| 74 | 1 | DspSquareDiffMult | dsp | dsp/generic/fixed/DspSquareDiffMult.vhd | 0 | -| 75 | 2 | MasterAxiLiteIpIntegrator | axi | axi/axi-lite/ip_integrator/MasterAxiLiteIpIntegrator.vhd | 9 | -| 76 | 2 | SlaveAxiLiteIpIntegrator | axi | axi/axi-lite/ip_integrator/SlaveAxiLiteIpIntegrator.vhd | 32 | -| 77 | 2 | AxiLiteAsync | axi | axi/axi-lite/rtl/AxiLiteAsync.vhd | 7 | -| 78 | 2 | MasterAxiStreamIpIntegrator | axi | axi/axi-stream/ip_integrator/MasterAxiStreamIpIntegrator.vhd | 30 | -| 79 | 2 | SlaveAxiStreamIpIntegrator | axi | axi/axi-stream/ip_integrator/SlaveAxiStreamIpIntegrator.vhd | 30 | -| 80 | 2 | AxiStreamGearbox | axi | axi/axi-stream/rtl/AxiStreamGearbox.vhd | 2 | -| 81 | 2 | AxiStreamPrbsFlowCtrl | axi | axi/axi-stream/rtl/AxiStreamPrbsFlowCtrl.vhd | 1 | -| 82 | 2 | AxiStreamTap | axi | axi/axi-stream/rtl/AxiStreamTap.vhd | 1 | -| 83 | 2 | MasterAxiIpIntegrator | axi | axi/axi4/ip_integrator/MasterAxiIpIntegrator.vhd | 16 | -| 84 | 2 | SlaveAxiIpIntegrator | axi | axi/axi4/ip_integrator/SlaveAxiIpIntegrator.vhd | 9 | -| 85 | 2 | AxiStreamDmaRead | axi | axi/dma/rtl/v1/AxiStreamDmaRead.vhd | 4 | -| 86 | 2 | AxiStreamDmaV2Read | axi | axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd | 3 | -| 87 | 2 | AxiStreamDmaV2Write | axi | axi/dma/rtl/v2/AxiStreamDmaV2Write.vhd | 3 | -| 88 | 2 | FifoAsync | base | base/fifo/rtl/inferred/FifoAsync.vhd | 4 | -| 89 | 2 | Debouncer | base | base/general/rtl/Debouncer.vhd | 1 | -| 90 | 2 | PwrUpRst | base | base/general/rtl/PwrUpRst.vhd | 0 | -| 91 | 2 | SynchronizerOneShot | base | base/sync/rtl/SynchronizerOneShot.vhd | 8 | -| 92 | 2 | BoxcarFilter | dsp | dsp/generic/fixed/BoxcarFilter.vhd | 0 | -| 93 | 3 | AxiLiteAsyncIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteAsyncIpIntegrator.vhd | 0 | -| 94 | 3 | AxiLiteMasterIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteMasterIpIntegrator.vhd | 0 | -| 95 | 3 | AxiLiteMasterProxyIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteMasterProxyIpIntegrator.vhd | 0 | -| 96 | 3 | AxiLiteRegsIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteRegsIpIntegrator.vhd | 0 | -| 97 | 3 | AxiLiteRespTimerIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteRespTimerIpIntegrator.vhd | 0 | -| 98 | 3 | AxiLiteSequencerRamIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteSequencerRamIpIntegrator.vhd | 0 | -| 99 | 3 | AxiLiteSlaveIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteSlaveIpIntegrator.vhd | 0 | -| 100 | 3 | AxiLiteWriteFilterIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteWriteFilterIpIntegrator.vhd | 0 | -| 101 | 3 | AxiVersionIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiVersionIpIntegrator.vhd | 0 | -| 102 | 3 | AxiStreamCombinerIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamCombinerIpIntegrator.vhd | 0 | -| 103 | 3 | AxiStreamCompactIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamCompactIpIntegrator.vhd | 0 | -| 104 | 3 | AxiStreamConcatIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamConcatIpIntegrator.vhd | 0 | -| 105 | 3 | AxiStreamDeMuxIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd | 0 | -| 106 | 3 | AxiStreamFlushIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamFlushIpIntegrator.vhd | 0 | -| 107 | 3 | AxiStreamFrameRateLimiterIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamFrameRateLimiterIpIntegrator.vhd | 0 | -| 108 | 3 | AxiStreamGearboxIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamGearboxIpIntegrator.vhd | 0 | -| 109 | 3 | AxiStreamGearboxPackIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamGearboxPackIpIntegrator.vhd | 0 | -| 110 | 3 | AxiStreamGearboxUnpackIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamGearboxUnpackIpIntegrator.vhd | 0 | -| 111 | 3 | AxiStreamMuxIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd | 0 | -| 112 | 3 | AxiStreamPipelineIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd | 0 | -| 113 | 3 | AxiStreamPrbsFlowCtrlIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamPrbsFlowCtrlIpIntegrator.vhd | 0 | -| 114 | 3 | AxiStreamRepeaterIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamRepeaterIpIntegrator.vhd | 0 | -| 115 | 3 | AxiStreamResizeIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamResizeIpIntegrator.vhd | 0 | -| 116 | 3 | AxiStreamShiftIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamShiftIpIntegrator.vhd | 0 | -| 117 | 3 | AxiStreamSplitterIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamSplitterIpIntegrator.vhd | 0 | -| 118 | 3 | AxiStreamTapIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamTapIpIntegrator.vhd | 0 | -| 119 | 3 | AxiStreamTrailerAppendIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamTrailerAppendIpIntegrator.vhd | 0 | -| 120 | 3 | AxiStreamTrailerRemoveIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamTrailerRemoveIpIntegrator.vhd | 0 | -| 121 | 3 | MasterAxiStreamTerminateIpIntegrator | axi | axi/axi-stream/ip_integrator/MasterAxiStreamTerminateIpIntegrator.vhd | 0 | -| 122 | 3 | SlaveAxiStreamTerminateIpIntegrator | axi | axi/axi-stream/ip_integrator/SlaveAxiStreamTerminateIpIntegrator.vhd | 0 | -| 123 | 3 | AxiStreamTimer | axi | axi/axi-stream/rtl/AxiStreamTimer.vhd | 1 | -| 124 | 3 | AxiRamIpIntegrator | axi | axi/axi4/ip_integrator/AxiRamIpIntegrator.vhd | 0 | -| 125 | 3 | AxiReadPathMuxIpIntegrator | axi | axi/axi4/ip_integrator/AxiReadPathMuxIpIntegrator.vhd | 0 | -| 126 | 3 | AxiResizeIpIntegrator | axi | axi/axi4/ip_integrator/AxiResizeIpIntegrator.vhd | 0 | -| 127 | 3 | AxiWritePathMuxIpIntegrator | axi | axi/axi4/ip_integrator/AxiWritePathMuxIpIntegrator.vhd | 0 | -| 128 | 3 | AxiRateGen | axi | axi/axi4/rtl/AxiRateGen.vhd | 1 | -| 129 | 3 | AxiLiteToIpBusIpIntegrator | axi | axi/bridge/ip_integrator/AxiLiteToIpBusIpIntegrator.vhd | 0 | -| 130 | 3 | AxiToAxiLiteIpIntegrator | axi | axi/bridge/ip_integrator/AxiToAxiLiteIpIntegrator.vhd | 0 | -| 131 | 3 | IpBusToAxiLiteIpIntegrator | axi | axi/bridge/ip_integrator/IpBusToAxiLiteIpIntegrator.vhd | 0 | -| 132 | 3 | AxiLiteToDrp | axi | axi/bridge/rtl/AxiLiteToDrp.vhd | 1 | -| 133 | 3 | AxiStreamDmaReadIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaReadIpIntegrator.vhd | 0 | -| 134 | 3 | AxiStreamDmaV2ReadIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2ReadIpIntegrator.vhd | 0 | -| 135 | 3 | AxiStreamDmaV2WriteIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2WriteIpIntegrator.vhd | 0 | -| 136 | 3 | Fifo | base | base/fifo/rtl/Fifo.vhd | 6 | -| 137 | 3 | AsyncGearbox | base | base/general/rtl/AsyncGearbox.vhd | 0 | -| 138 | 3 | DebouncerWrapper | base | base/general/wrappers/DebouncerWrapper.vhd | 0 | -| 139 | 3 | SyncTrigPeriod | base | base/sync/rtl/SyncTrigPeriod.vhd | 0 | -| 140 | 3 | SynchronizerFifo | base | base/sync/rtl/SynchronizerFifo.vhd | 11 | -| 141 | 3 | SynchronizerOneShotVector | base | base/sync/rtl/SynchronizerOneShotVector.vhd | 0 | -| 142 | 3 | FirFilterSingleChannel | dsp | dsp/generic/fixed/FirFilterSingleChannel.vhd | 0 | -| 143 | 4 | AxiDualPortRam | axi | axi/axi-lite/rtl/AxiDualPortRam.vhd | 6 | -| 144 | 4 | AxiLiteRingBuffer | axi | axi/axi-lite/rtl/AxiLiteRingBuffer.vhd | 1 | -| 145 | 4 | AxiStreamTimerIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamTimerIpIntegrator.vhd | 0 | -| 146 | 4 | AxiStreamScatterGather | axi | axi/axi-stream/rtl/AxiStreamScatterGather.vhd | 1 | -| 147 | 4 | AxiRateGenIpIntegrator | axi | axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd | 0 | -| 148 | 4 | AxiMemTester | axi | axi/axi4/rtl/AxiMemTester.vhd | 1 | -| 149 | 4 | AxiLiteToDrpIpIntegrator | axi | axi/bridge/ip_integrator/AxiLiteToDrpIpIntegrator.vhd | 0 | -| 150 | 4 | SlvArraytoAxiLite | axi | axi/bridge/rtl/SlvArraytoAxiLite.vhd | 1 | -| 151 | 4 | AxiStreamDmaV2Desc | axi | axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd | 2 | -| 152 | 4 | AxiStreamDmaV2Fifo | axi | axi/dma/rtl/v2/AxiStreamDmaV2Fifo.vhd | 1 | -| 153 | 4 | SlvDelayFifo | base | base/delay/rtl/SlvDelayFifo.vhd | 0 | -| 154 | 4 | FifoCascade | base | base/fifo/rtl/FifoCascade.vhd | 8 | -| 155 | 4 | FwftCntWrapper | base | base/fifo/wrappers/FwftCntWrapper.vhd | 0 | -| 156 | 4 | SyncClockFreq | base | base/sync/rtl/SyncClockFreq.vhd | 1 | -| 157 | 4 | SyncMinMax | base | base/sync/rtl/SyncMinMax.vhd | 2 | -| 158 | 4 | SynchronizerOneShotCnt | base | base/sync/rtl/SynchronizerOneShotCnt.vhd | 1 | -| 159 | 5 | AxiDualPortRamIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd | 0 | -| 160 | 5 | AxiLiteCrossbarIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteCrossbarIpIntegrator.vhd | 0 | -| 161 | 5 | AxiLiteRingBufferIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteRingBufferIpIntegrator.vhd | 0 | -| 162 | 5 | AxiLiteFifoPop | axi | axi/axi-lite/rtl/AxiLiteFifoPop.vhd | 1 | -| 163 | 5 | AxiLiteFifoPush | axi | axi/axi-lite/rtl/AxiLiteFifoPush.vhd | 1 | -| 164 | 5 | AxiLiteFifoPushPop | axi | axi/axi-lite/rtl/AxiLiteFifoPushPop.vhd | 2 | -| 165 | 5 | AxiStreamScatterGatherIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamScatterGatherIpIntegrator.vhd | 0 | -| 166 | 5 | AxiStreamFifoV2 | axi | axi/axi-stream/rtl/AxiStreamFifoV2.vhd | 7 | -| 167 | 5 | AxiMemTesterIpIntegrator | axi | axi/axi4/ip_integrator/AxiMemTesterIpIntegrator.vhd | 0 | -| 168 | 5 | AxiReadPathFifo | axi | axi/axi4/rtl/AxiReadPathFifo.vhd | 3 | -| 169 | 5 | AxiWritePathFifo | axi | axi/axi4/rtl/AxiWritePathFifo.vhd | 3 | -| 170 | 5 | SlvArraytoAxiLiteIpIntegrator | axi | axi/bridge/ip_integrator/SlvArraytoAxiLiteIpIntegrator.vhd | 0 | -| 171 | 5 | AxiStreamDmaV2DescIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2DescIpIntegrator.vhd | 0 | -| 172 | 5 | AxiStreamDmaV2FifoIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2FifoIpIntegrator.vhd | 0 | -| 173 | 5 | AxiStreamDmaV2 | axi | axi/dma/rtl/v2/AxiStreamDmaV2.vhd | 1 | -| 174 | 5 | FifoMux | base | base/fifo/rtl/FifoMux.vhd | 0 | -| 175 | 5 | SyncTrigRate | base | base/sync/rtl/SyncTrigRate.vhd | 3 | -| 176 | 5 | SynchronizerOneShotCntVector | base | base/sync/rtl/SynchronizerOneShotCntVector.vhd | 2 | -| 177 | 5 | SyncClockFreqWrapper | base | base/sync/wrappers/SyncClockFreqWrapper.vhd | 0 | -| 178 | 5 | FirFilterMultiChannel | dsp | dsp/generic/fixed/FirFilterMultiChannel.vhd | 0 | -| 179 | 6 | AxiLiteFifoPopIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteFifoPopIpIntegrator.vhd | 0 | -| 180 | 6 | AxiLiteFifoPushIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteFifoPushIpIntegrator.vhd | 0 | -| 181 | 6 | AxiLiteFifoPushPopIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteFifoPushPopIpIntegrator.vhd | 0 | -| 182 | 6 | AxiStreamFifoV2IpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd | 0 | -| 183 | 6 | AxiStreamBatchingFifo | axi | axi/axi-stream/rtl/AxiStreamBatchingFifo.vhd | 1 | -| 184 | 6 | AxiStreamMon | axi | axi/axi-stream/rtl/AxiStreamMon.vhd | 2 | -| 185 | 6 | AxiStreamRingBuffer | axi | axi/axi-stream/rtl/AxiStreamRingBuffer.vhd | 1 | -| 186 | 6 | AxiReadPathFifoIpIntegrator | axi | axi/axi4/ip_integrator/AxiReadPathFifoIpIntegrator.vhd | 0 | -| 187 | 6 | AxiWritePathFifoIpIntegrator | axi | axi/axi4/ip_integrator/AxiWritePathFifoIpIntegrator.vhd | 0 | -| 188 | 6 | AxiReadEmulate | axi | axi/axi4/rtl/AxiReadEmulate.vhd | 1 | -| 189 | 6 | AxiRingBuffer | axi | axi/axi4/rtl/AxiRingBuffer.vhd | 1 | -| 190 | 6 | AxiWriteEmulate | axi | axi/axi4/rtl/AxiWriteEmulate.vhd | 1 | -| 191 | 6 | AxiStreamDmaV2IpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2IpIntegrator.vhd | 0 | -| 192 | 6 | AxiStreamDmaRingRead | axi | axi/dma/rtl/v1/AxiStreamDmaRingRead.vhd | 1 | -| 193 | 6 | AxiStreamDmaWrite | axi | axi/dma/rtl/v1/AxiStreamDmaWrite.vhd | 4 | -| 194 | 6 | SyncStatusVector | base | base/sync/rtl/SyncStatusVector.vhd | 2 | -| 195 | 6 | SyncTrigRateVector | base | base/sync/rtl/SyncTrigRateVector.vhd | 1 | -| 196 | 6 | SyncTrigRateWrapper | base | base/sync/wrappers/SyncTrigRateWrapper.vhd | 0 | -| 197 | 6 | SynchronizerOneShotCntVectorFlatWrapper | base | base/sync/wrappers/SynchronizerOneShotCntVectorFlatWrapper.vhd | 0 | -| 198 | 7 | AxiLiteRamSyncStatusVector | axi | axi/axi-lite/rtl/AxiLiteRamSyncStatusVector.vhd | 1 | -| 199 | 7 | AxiStreamBatchingFifoIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamBatchingFifoIpIntegrator.vhd | 0 | -| 200 | 7 | AxiStreamMonIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamMonIpIntegrator.vhd | 0 | -| 201 | 7 | AxiStreamRingBufferIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamRingBufferIpIntegrator.vhd | 0 | -| 202 | 7 | AxiStreamMonAxiL | axi | axi/axi-stream/rtl/AxiStreamMonAxiL.vhd | 2 | -| 203 | 7 | AxiReadEmulateIpIntegrator | axi | axi/axi4/ip_integrator/AxiReadEmulateIpIntegrator.vhd | 0 | -| 204 | 7 | AxiRingBufferIpIntegrator | axi | axi/axi4/ip_integrator/AxiRingBufferIpIntegrator.vhd | 0 | -| 205 | 7 | AxiWriteEmulateIpIntegrator | axi | axi/axi4/ip_integrator/AxiWriteEmulateIpIntegrator.vhd | 0 | -| 206 | 7 | AxiStreamDmaRingReadIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaRingReadIpIntegrator.vhd | 0 | -| 207 | 7 | AxiStreamDmaWriteIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaWriteIpIntegrator.vhd | 0 | -| 208 | 7 | AxiStreamDma | axi | axi/dma/rtl/v1/AxiStreamDma.vhd | 1 | -| 209 | 7 | AxiStreamDmaFifo | axi | axi/dma/rtl/v1/AxiStreamDmaFifo.vhd | 1 | -| 210 | 7 | AxiStreamDmaRingWrite | axi | axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd | 1 | -| 211 | 7 | SyncStatusVectorFlatWrapper | base | base/sync/wrappers/SyncStatusVectorFlatWrapper.vhd | 0 | -| 212 | 7 | SyncTrigRateVectorFlatWrapper | base | base/sync/wrappers/SyncTrigRateVectorFlatWrapper.vhd | 0 | -| 213 | 8 | AxiLiteRamSyncStatusVectorIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteRamSyncStatusVectorIpIntegrator.vhd | 0 | -| 214 | 8 | AxiStreamMonAxiLIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamMonAxiLIpIntegrator.vhd | 0 | -| 215 | 8 | AxiMonAxiL | axi | axi/axi4/rtl/AxiMonAxiL.vhd | 1 | -| 216 | 8 | AxiStreamDmaFifoIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaFifoIpIntegrator.vhd | 0 | -| 217 | 8 | AxiStreamDmaIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaIpIntegrator.vhd | 0 | -| 218 | 8 | AxiStreamDmaRingWriteIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaRingWriteIpIntegrator.vhd | 0 | -| 219 | 9 | AxiMonAxiLIpIntegrator | axi | axi/axi4/ip_integrator/AxiMonAxiLIpIntegrator.vhd | 0 | diff --git a/docs/_meta/rtl_phase1_queue_overrides.json b/docs/_meta/rtl_phase1_queue_overrides.json deleted file mode 100644 index 474d21dbc1..0000000000 --- a/docs/_meta/rtl_phase1_queue_overrides.json +++ /dev/null @@ -1,85 +0,0 @@ -{ - "force_include_entities": [], - "force_include_paths": [], - "deferred_subsystems": [ - { - "name": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "name": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "name": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "name": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - } - ], - "deferred_entities": [ - { - "entity": "LutFixedDelay", - "reason": "Depends on SinglePortRamPrimitive under the current open-source flow." - } - ], - "deferred_paths": [], - "deferred_path_substrings": [ - { - "pattern": "protocols/pgp/pgp3/", - "reason": "PGP3 is intentionally deferred for now so current protocol work stays on pgp2b/pgp2fc/pgp4 and shared PGP blocks." - }, - { - "pattern": "axi/simlink/", - "reason": "Simulation support models are not part of the synthesizable phase-1 queue." - }, - { - "pattern": "/sim/", - "reason": "Simulation-only support modules are not part of the synthesizable phase-1 queue." - }, - { - "pattern": "/dummy/", - "reason": "Dummy-backed variants are deferred from the phase-1 executable queue." - }, - { - "pattern": "/altera/", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "/xilinx/", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "7Series", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "UltraScale", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "UltraScale+", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "/gth", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gtp", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gty", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gtx", - "reason": "GT-family implementation branches are deferred in phase 1." - } - ], - "preferred_paths_by_entity": {}, - "order_overrides": [] -} diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md deleted file mode 100644 index d8a94c7a21..0000000000 --- a/docs/_meta/rtl_regression_handoff.md +++ /dev/null @@ -1,203 +0,0 @@ -# SURF RTL Regression Handoff - -## Objective -- Build a repo-wide regression system for synthesizable SURF RTL. -- Keep all executable test logic in Python. -- Use `pytest + cocotb + GHDL + ruckus`. -- Keep VHDL only for wrappers, shims, and required simulation models. - -## Chosen Constraints -- Python-only test logic -- VHDL wrappers allowed -- Whole-repo target -- Vendor-heavy modules deferred in phase 1 -- Comment new Python regression code at a tutorial level, assuming the reader may be new to cocotb -- Give each Python regression the normal SURF/SLAC file header and two distinct comment layers: a module-specific `Test methodology` block under that header and tutorial-style comments in the executable code body -- Give each checked-in cocotb-facing `*IpIntegrator.vhd` wrapper the normal SURF file banner plus section comments for shim setup, DUT instantiation, and any flattening/status wiring -- For any VHDL file created or edited during this work, run `./.venv/bin/vsg` with `vsg-linter.yml`, the same config CI uses, and use `--fix`/autofix on fixable issues before moving on -- Treat VHDL packages as transitively covered unless a behavioral function/procedure needs a dedicated wrapper -- Treat stale simulator cleanup as part of task completion: after any `pytest`, cocotb, GHDL, or similar launched verification step, sweep for leftover child processes and kill them before moving on - -## Quick Resume Snapshot -- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, and the current Ethernet coverage now spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, and `IpV4Engine`, including the recent thin-area cleanup across direct bypass leaves, broader top-level UDP/IPv4 paths, and deeper ICMP negatives. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. -- Current axi frontier: complete for the intended simulator-friendly pass in this branch snapshot; do not resume from the older stale `AxiResize` note. -- Current validated-open issues: - - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, `Caui4Core`, and `RoCEv2` remain untouched in phase 1. - - `EthMacRxImportXlgmii` and `EthMacTxExportXlgmii` are still placeholder no-op RTL; the checked-in tests now lock down that inert contract instead of claiming functional XLGMII support. -- Current planning discipline: - - Use manual user-directed area selection as the active source of truth for what to work on next. - - Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the actual validated branch frontier. - - Keep the graph and queue artifacts only as historical provenance or optional analysis context; do not use them as the next-module selector unless the user explicitly opts back into queue-driven planning. -- Current wrapper discipline: - - Prefer the existing subsystem `ip_integrator/` shim layers over bespoke record flattening. - - Keep first-pass wrapper benches intentionally narrow and document any omitted branches explicitly. - - Use `start_lockstep_clocks()` when a DUT depends on truly shared clock edges. - - Prefer explicit short sim-build keys for generated-wrapper benches when case metadata would otherwise create fragile build paths. - - When a wrapper is checked in, write it like the surrounding repo HDL: include the SLAC/SURF banner and enough section comments that a new session can identify the shim, DUT, and flattening regions quickly. - - For the current Ethernet slice, the checked-in wrappers under `ethernet/EthMacCore/wrappers/`, `ethernet/RawEthFramer/wrappers/`, `ethernet/UdpEngine/wrappers/`, and `ethernet/IpV4Engine/wrappers/` are the expected cocotb surfaces. Keep using those subsystem-local wrappers rather than rebuilding record-packing logic in Python. -- Current cocotb-file discipline: - - New test files should start with the standard SURF/SLAC header block. - - The `Test methodology` block belongs directly under that header. - - In-body tutorial comments are still required; the methodology block does not replace them. - -## Session Learnings To Preserve -- Start with the smallest stable wrapper that exposes the DUT cleanly to cocotb. Reuse the existing subsystem `ip_integrator/` shims before inventing bespoke flattening or a new subsystem-local wrapper. -- Prefer checked-in subsystem-local wrappers for durable integration patterns, including simulator-hostile generic adapters. -- If a Python cocotb file is permanent enough to check in, do not leave it with a custom or abbreviated header. Use the standard repo header immediately, then add the methodology block and tutorial comments in the same first pass. -- If a wrapper is permanent enough to check in, do not leave it as a bare anonymous adapter. Add the standard SURF banner and short section comments immediately, not as a cleanup pass later. -- For AXI and AXI-Lite benches, the practical first-pass shape is usually: - - cocotb protocol master on the control/request side, - - cocotb RAM or simple protocol model on the generated/response side, - - lightweight monitors on accepted handshakes when timing or burst shape matters. -- Do not rely on final memory contents alone when the contract includes timing-visible behavior. Record accepted handshakes if the bench is supposed to prove spacing, burst length, sideband propagation, partial-last-beat strobes, or arbitration order. -- For `COMMON_CLK_G` style wrappers, use one shared clock coroutine via `start_lockstep_clocks()` when the RTL expects true shared edges rather than merely equal nominal periods. -- For first-pass wrapper benches, prove the externally visible stable path first and defer shakier simulator-sensitive branches explicitly in the docs instead of stretching one bench to cover everything. -- `AxiStreamDmaV2Read` needed a real RTL/runtime fix rather than a bench workaround: keep the bounded byte-count conversion fix in `axi/axi4/rtl/AxiPkg.vhd` and the direct terminal-mask generation in `axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd`. The current wrapper only exposes an 8-bit `TUSER`, so the observable contract in the checked-in bench is first-user propagation plus payload/keep/id/dest and descriptor return fields. -- `tests/dsp/generic/dsp_test_utils.py` is now the shared home for DSP-specific signed helpers, rolling reference models, cocotb clock-settle timing, and generated FIR wrappers. Reuse it instead of cloning DSP arithmetic or wrapper boilerplate. -- `tests/ethernet/EthMacCore/ethmac_test_utils.py` is now the shared home for the current Ethernet MAC slice: flat EMAC beat helpers, Ethernet/IPv4/UDP packet builders, checksum reference code, MAC-config byte-order helpers, and minimum-frame padding helpers. Reuse it instead of cloning packet or sideband plumbing across `EthMacCore` benches. -- `tests/ethernet/RawEthFramer/raw_eth_test_utils.py` now holds the shared raw-Ethernet helper pieces: flat app-side beat helpers, raw-Ethernet header/frame builders, and lookup-handshake utilities reused by the `RawEthFramer`, `RawEthFramerRx`, and `RawEthFramerTx` benches. -- `tests/ethernet/UdpEngine/udp_test_utils.py` is now the shared home for the UDP slice: legacy-address constants, pseudo-frame builders, DHCP option helpers, and the common cocotb bench setup for the `ArpIpTable`, `UdpEngine*`, and `UdpEngineWrapper*` wrappers. Reuse it instead of rebuilding IPv4/UDP helper glue in each test module. -- `tests/ethernet/IpV4Engine/ipv4_test_utils.py` is now the shared home for the IPv4 slice: packet/header builders and common cocotb bench setup for the `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, and `IpV4Engine*` wrappers. Reuse it instead of cloning IPv4 framing helpers across that directory. -- The current `EthMacCore` slice is intentionally a checked-in-wrapper-first rollout, not a cocotb-generated-wrapper experiment. Keep new Ethernet work on that same pattern unless the simulator forces a very local generic adapter. -- The XGMII import/export loopback behavior differs from the GMII path when `phyReady` drops mid-traffic: the blocked frame is retained and drains after link recovery, padded to Ethernet's minimum frame size if it was short. The GMII path drops that blocked frame. Future import/export coverage should preserve that distinction instead of forcing one common expectation. -- The current `EthMacRxImportXlgmii.vhd` and `EthMacTxExportXlgmii.vhd` leaves are placeholders: they drive no data-path activity and never pulse the count/status outputs. Future work should treat functional XLGMII support as an RTL gap, not as a missing bench. -- `EthMacRxCsum` reliably raises `IPERR` on a bad IPv4 header checksum, but the checked-in wrapper contract does not currently require `EOFE` for that case. Keep the negative test aligned to the real observable contract rather than to a stronger assumption. -- The RX/TX shift benches need a small idle-plus-settle gap before changing runtime shift controls because the underlying `AxiStreamShift` samples those controls while idle. Preserve that guardrail if those benches are refactored or expanded. -- `EthMacRxBypass` compares the EtherType field in the flattened EMAC byte-lane order, not normal wire-order host integer order. In practice that means a wire EtherType like `0x9000` must be compared as `x"0090"` at the wrapper/DUT generic boundary, just as `0x88B5` appears as `x"B588"` in the existing wrappers. -- Do not leave stale simulation trees behind between tasks. If a verification command launched `pytest`, cocotb, GHDL, or wrapper executables, treat post-run process cleanup as mandatory before the next edit or test cycle. - -## Current Status -Planning is complete and implementation is well underway. The agreed direction is a Python-only executable regression framework with tiered `smoke` and `functional` coverage. Existing VHDL TBs are reference material only and should be rewritten in Python when migrated, unless a thin wrapper is still useful for cocotb access. - -The repo now has the initial handoff artifacts, a checked-in inventory scaffold at `docs/_meta/rtl_regression_inventory.yaml`, and local bootstrap helpers in `scripts/setup_regression_env.sh` plus `.vscode/tasks.json`. The first pilot modules were `FifoAsync`, `AxiStreamFifoV2`, and `AxiLiteAsync`, and the work has since moved into a graph-guided bottom-up rollout across `base/`. - -The local machine now has `ghdl`, a working `.venv`, the Python regression packages, a repo-local `ruckus` link to `~/ruckus`, and a successful `make MODULES="$PWD" import` run. Local environment bootstrap is no longer the blocker. The first shared-helper-based pilot regression now exists in `tests/base/fifo/test_FifoAsync.py` and passes locally. - -New regressions are now being organized by subsystem under `tests/`, with shared helpers in `tests/common/`. The `FifoAsync` pilot lives in `tests/base/fifo/test_FifoAsync.py`, and `AxiStreamFifoV2` now lives in `tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py`. New work should follow that package layout instead of adding more flat files under `tests/`. - -`FifoAsync` now has a validated expanded 12-case matrix, `FifoSync` has a validated expanded 11-case matrix, `Synchronizer` and `SynchronizerVector` now each have validated 6-case matrices under `tests/base/sync/`, `RstPipeline` has a validated 4-case matrix under `tests/base/general/`, `SimpleDualPortRam` has a validated 5-case matrix under `tests/base/ram/`, `FifoOutputPipeline` has a validated 5-case matrix under `tests/base/fifo/`, and `FifoWrFsm` has a validated 4-case matrix under `tests/base/fifo/`. - -The next graph-guided 10-module follow-on is also now in place: `Crc32Parallel`, `Crc32`, `CRC32Rtl`, `RstSync`, `PwrUpRst`, `SynchronizerEdge`, `SynchronizerOneShot`, `TrueDualPortRam`, `LutRam`, and `FifoRdFsm`. The combined validation command for that batch is `./.venv/bin/python -m pytest -v tests/base/crc/test_Crc32Parallel.py tests/base/crc/test_Crc32.py tests/base/crc/test_CRC32Rtl.py tests/base/sync/test_RstSync.py tests/base/general/test_PwrUpRst.py tests/base/sync/test_SynchronizerEdge.py tests/base/sync/test_SynchronizerOneShot.py tests/base/ram/test_TrueDualPortRam.py tests/base/ram/test_LutRam.py tests/base/fifo/test_FifoRdFsm.py`, and it currently passes with `38 passed`. - -The next 15-module `base/` general/delay/sync batch is now also implemented and validated: `Arbiter`, `ClockDivider`, `Debouncer`, `Gearbox`, `Heartbeat`, `Mux`, `OneShot`, `RegisterVector`, `RstPipelineVector`, `Scrambler`, `WatchDogRst`, `SlvDelay`, `SlvFixedDelay`, `SynchronizerFifo`, and `SynchronizerOneShotCnt`. The combined validation command for that batch is `./.venv/bin/python -m pytest -n 0 -q tests/base/general/test_Arbiter.py tests/base/general/test_ClockDivider.py tests/base/general/test_Debouncer.py tests/base/general/test_Gearbox.py tests/base/general/test_Heartbeat.py tests/base/general/test_Mux.py tests/base/general/test_OneShot.py tests/base/general/test_RegisterVector.py tests/base/general/test_RstPipelineVector.py tests/base/general/test_Scrambler.py tests/base/general/test_WatchDogRst.py tests/base/delay/test_SlvDelay.py tests/base/delay/test_SlvFixedDelay.py tests/base/sync/test_SynchronizerFifo.py tests/base/sync/test_SynchronizerOneShotCnt.py`, and it currently passes with `41 passed`. - -The next 10-module wrapper/integration batch is now also implemented and validated: `DspComparator`, `Fifo`, `FifoCascade`, `FifoMux`, `AsyncGearbox`, `SynchronizerOneShotVector`, `SynchronizerOneShotCntVector`, `SyncStatusVector`, `SyncTrigPeriod`, and `SyncMinMax`. The combined validation command for that batch is `./.venv/bin/python -m pytest -n 0 -q tests/dsp/generic/test_DspComparator.py tests/base/fifo/test_Fifo.py tests/base/fifo/test_FifoCascade.py tests/base/fifo/test_FifoMux.py tests/base/general/test_AsyncGearbox.py tests/base/sync/test_SynchronizerOneShotVector.py tests/base/sync/test_SynchronizerOneShotCntVector.py tests/base/sync/test_SyncStatusVector.py tests/base/sync/test_SyncTrigPeriod.py tests/base/sync/test_SyncMinMax.py`, and it currently passes with `18 passed`. - -The remaining practical non-vendor, non-dummy `base/` modules are now also implemented and validated: `MasterRamIpIntegrator`, `SlaveRamIpIntegrator`, `DualPortRam`, `SlvDelayRam`, `SlvDelayFifo`, `SyncClockFreq`, `SyncTrigRate`, and `SyncTrigRateVector`. The combined validation command for that batch is `./.venv/bin/python -m pytest -n 0 -q tests/base/general/test_MasterRamIpIntegrator.py tests/base/general/test_SlaveRamIpIntegrator.py tests/base/ram/test_DualPortRam.py tests/base/delay/test_SlvDelayRam.py tests/base/delay/test_SlvDelayFifo.py tests/base/sync/test_SyncClockFreq.py tests/base/sync/test_SyncTrigRate.py tests/base/sync/test_SyncTrigRateVector.py`, and it currently passes with `15 passed`. - -`Crc32` now covers multiple common 32-bit polynomials instead of only the default IEEE CRC-32 polynomial. That test uses a thin wrapper at `base/crc/wrappers/Crc32PolyWrapper.vhd` because the local GHDL flow rejects direct command-line overrides of the `CRC_POLY_G : slv(31 downto 0)` generic. Pytest still defaults to `-n auto --dist=worksteal` through `pytest.ini` so parameterized regressions fan out across worker processes by default. - -The project now also has a shared helper path in `tests/common/regression_utils.py` for test scaffolding, but the wrapper policy is to keep durable cocotb-facing HDL shims checked in under subsystem-local `wrappers/` or `ip_integrator/` folders. `Heartbeat` and `Debouncer` remain useful examples of very small wrappers, but new permanent generic-adapter shims should follow the checked-in subsystem-local pattern. - -`tests/common/regression_utils.py` now also includes `start_lockstep_clocks()` for DUTs whose generics assume truly common clocks in both ports. Use that helper instead of launching two same-period clocks independently when the RTL assumes shared edge identity. - -`ethernet/EthMacCore/` now has checked-in regression coverage under `tests/ethernet/EthMacCore/` for both the original leaf slice and the deeper assembly layer. The current benches cover `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, `EthMacTop`, `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, `EthMacTxFifo`, `EthMacRxBypass`, and `EthMacTxBypass`. The import/export benches now also explicitly encode the current placeholder `XLGMII` contract so future functional XLGMII RTL work will show up as a deliberate expectation change instead of an accidental gap. The current Ethernet wrappers live under `ethernet/EthMacCore/wrappers/` and should be treated as the stable cocotb-facing surfaces for further `EthMacCore` work. - -`ethernet/UdpEngine/` and `ethernet/IpV4Engine/` also received a thin-area cleanup pass on this branch. The `UdpEngine` top/wrapper benches now cover additional client/server routing paths beyond the earlier single happy-path smoke, while `IpV4Engine` now has a top-level protocol-TX path and deeper `IcmpEngine` negative/recovery coverage. The combined local validation command for that focused follow-up is `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/EthMacCore/test_EthMacRxImport.py tests/ethernet/EthMacCore/test_EthMacTxExport.py tests/ethernet/EthMacCore/test_EthMacRxBypass.py tests/ethernet/EthMacCore/test_EthMacTxBypass.py tests/ethernet/UdpEngine/test_UdpEngine.py tests/ethernet/UdpEngine/test_UdpEngineWrapper.py tests/ethernet/IpV4Engine/test_IpV4Engine.py tests/ethernet/IpV4Engine/test_IcmpEngine.py`, and it passes locally with `14 passed`. - -`ethernet/RawEthFramer/` now also has checked-in regression coverage under `tests/ethernet/RawEthFramer/`. The earlier top-level `RawEthFramer` wrapper bench is joined by direct leaf benches for `RawEthFramerRx` and `RawEthFramerTx`, plus a `RawEthFramerPair` integration bench whose wrapper cross-connects two `RawEthFramer` instances to mirror the legacy `ethernet/RawEthFramer/tb/RawEthFramerTb.vhd` topology. The validated RX leaf bench covers lookup-gated unicast decode, short-frame trim behavior, broadcast bypass, and representative reject cases. The validated TX leaf bench now covers lookup-request exposure before forwarding, successful multi-beat unicast forwarding after lookup resolution, broadcast bypass with the observed padded wire image, and zero-MAC lookup-miss drop. The successful unicast leaf case intentionally models the nonzero lookup latency that the integrated `RawEthFramer` wrapper inserts before `ack`, so keep that timing assumption if the TX bench is expanded further. - -`ethernet/UdpEngine/` now has checked-in regression coverage under `tests/ethernet/UdpEngine/` as well. The current validated set covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, all backed by checked-in wrappers under `ethernet/UdpEngine/wrappers/` and the shared helper layer in `tests/ethernet/UdpEngine/udp_test_utils.py`. - -`ethernet/IpV4Engine/` now also has checked-in regression coverage under `tests/ethernet/IpV4Engine/`. The current validated set covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, all backed by checked-in wrappers under `ethernet/IpV4Engine/wrappers/` and the shared helper layer in `tests/ethernet/IpV4Engine/ipv4_test_utils.py`. The `IgmpV2Engine` leaf bench covers power-up reports, general-query re-arming, and report suppression on matching inbound membership reports; it also documents the leaf-level stale pseudo-header bytes that are ignored by downstream `IpV4EngineTx` assembly. - -The wrapper coverage policy is now more explicit in practice: test the wrapper-specific behavior, not the full leaf matrix again. `Fifo` validated both inferred sync/async selection branches, `FifoCascade` validated public stage-vector mapping plus a curated output smoke, and `FifoMux` is currently validated only on the stable split-to-narrow path. The pack-to-wide `FifoMux` path should be treated as still open rather than silently assumed covered. - -That same wrapper-policy lesson now applies to the late `base/sync` wrappers as well. `SyncClockFreq` is stable with a checked-in subsystem wrapper, but its common-clock measurement quantizes one count above the abstract target under the current GHDL flow, so the regression checks a bounded expected range rather than an exact integer. `SyncTrigRate` is intentionally covered as a wrapper/integration bench only: it proves aligned update publication, denser-window rate growth, reset-path liveness, and strobe pulse behavior, while exact min/max pipeline semantics remain the responsibility of the dedicated `SyncMinMax` leaf test. - -At this point the practical phase-1 `base/` rollout is effectively complete. The only uncovered non-dummy `base/` module is `LutFixedDelay`, and it remains deferred because it still depends on the vendor-backed `SinglePortRamPrimitive` path. The other remaining `base/` gaps are vendor-heavy or dummy-backed variants. - -The first post-`base/` `axi/` follow-on is now in place as well. `AxiStreamPipeline` is validated under `tests/axi/axi_stream/test_AxiStreamPipeline.py` using a thin flat-port adapter at `axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd`, and `AxiLiteCrossbar` is validated under `tests/axi/axi_lite/test_AxiLiteCrossbar.py` using the existing `axi/axi-lite/tb/AxiLiteCrossbarTb.vhd` harness as a cocotb-facing shell. The combined validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamPipeline.py tests/axi/axi_lite/test_AxiLiteCrossbar.py`, and it currently passes with `4 passed`. - -For `AxiStreamPipeline`, treat the zero-stage case as a true combinational pass-through and the staged cases as wrapper-visible buffered paths. The stable expectation under the current wrapper is sink-handshake latency of `PIPE_STAGES_G + 2` clocks plus bounded reset flush behavior, not a naive one-to-one mapping from the user generic name. For `AxiLiteCrossbar`, the useful regression surface is region routing, decode-miss `DECERR` handling, and concurrent traffic through the existing cascaded harness topology rather than a broad generic sweep. - -`AxiStreamMux` is now validated under `tests/axi/axi_stream/test_AxiStreamMux.py` using a thin two-input adapter at `axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd`. The module-local validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamMux.py`, and it currently passes with `3 passed`. A small follow-on sanity run across `tests/axi/axi_stream/test_AxiStreamPipeline.py`, `tests/axi/axi_stream/test_AxiStreamMux.py`, and `tests/axi/axi_lite/test_AxiLiteCrossbar.py` also passes with `7 passed`. Keep the validated subset intentionally narrow: indexed arbitration with explicit priority plus `disableSel`, routed `TDEST`/`TID` remap under backpressure, and staged asynchronous active-low reset recovery in passthrough mode. Interleave and explicit rearbitrate branches remain open for later work. Also note the mux-specific nuance from this bench: `disableSel` is applied before the separate priority-mask generation, so a disabled higher-priority source can still suppress lower-priority requesters. - -`AxiStreamDeMux` is now validated under `tests/axi/axi_stream/test_AxiStreamDeMux.py` using a thin one-input/two-output adapter at `axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd`. The module-local validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamDeMux.py`, and it currently passes with `3 passed`. A small follow-on sanity run across `tests/axi/axi_stream/test_AxiStreamPipeline.py`, `tests/axi/axi_stream/test_AxiStreamMux.py`, `tests/axi/axi_stream/test_AxiStreamDeMux.py`, and `tests/axi/axi_lite/test_AxiLiteCrossbar.py` passes with `10 passed`. Keep the validated subset intentionally narrow: indexed decode to both outputs, exact-match routed decode under output backpressure, and dynamic-route table behavior including unmatched-destination drop plus staged asynchronous active-low reset flush. Wildcard-route patterns and larger fanout counts remain open for later work. - -The next five flat-queue modules are now also in place and validated. `AxiStreamResize` uses `axi/axi-stream/ip_integrator/AxiStreamResizeIpIntegrator.vhd` plus `tests/axi/axi_stream/test_AxiStreamResize.py`; `AxiLiteAsync` uses `axi/axi-lite/ip_integrator/AxiLiteAsyncIpIntegrator.vhd` plus `tests/axi/axi_lite/test_AxiLiteAsync.py`; `AxiLiteMaster` uses `axi/axi-lite/ip_integrator/AxiLiteMasterIpIntegrator.vhd` plus `tests/axi/axi_lite/test_AxiLiteMaster.py`; `AxiLiteToDrp` uses `axi/bridge/ip_integrator/AxiLiteToDrpIpIntegrator.vhd` plus `tests/axi/bridge/test_AxiLiteToDrp.py`; and `AxiDualPortRam` is validated through the existing `axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd` wrapper plus `tests/axi/axi_lite/test_AxiDualPortRam.py`. The five-module validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamResize.py tests/axi/axi_lite/test_AxiLiteAsync.py tests/axi/axi_lite/test_AxiLiteMaster.py tests/axi/bridge/test_AxiLiteToDrp.py tests/axi/axi_lite/test_AxiDualPortRam.py`, and it currently passes with `10 passed`. A broader AXI follow-on sanity run across pipeline, mux, demux, resize, crossbar, async, master, DRP bridge, and dual-port RAM also passes with `20 passed`. - -The next 10 generated-queue AXI modules are now also in place and validated. `AxiLiteRegs`, `AxiLiteRespTimer`, `AxiLiteSlave`, `AxiLiteWriteFilter`, and `AxiVersion` are covered under `tests/axi/axi_lite/` with thin subsystem-local wrappers in `axi/axi-lite/ip_integrator/`. `AxiStreamCombiner`, `AxiStreamFlush`, `AxiStreamGearboxPack`, `AxiStreamGearboxUnpack`, and `AxiStreamSplitter` are covered under `tests/axi/axi_stream/` with thin subsystem-local wrappers in `axi/axi-stream/ip_integrator/`. The combined validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_lite/test_AxiLiteRegs.py tests/axi/axi_lite/test_AxiLiteRespTimer.py tests/axi/axi_lite/test_AxiLiteSlave.py tests/axi/axi_lite/test_AxiLiteWriteFilter.py tests/axi/axi_lite/test_AxiVersion.py tests/axi/axi_stream/test_AxiStreamCombiner.py tests/axi/axi_stream/test_AxiStreamFlush.py tests/axi/axi_stream/test_AxiStreamGearboxPack.py tests/axi/axi_stream/test_AxiStreamGearboxUnpack.py tests/axi/axi_stream/test_AxiStreamSplitter.py`, and it currently passes with `14 passed`. - -Keep the validated subset intentionally narrow for the two most timing-sensitive wrappers. `AxiStreamResize` covers equal-width pass-through plus curated upsize/downsize cases with sideband alignment and staged reset flush. `AxiLiteMaster` covers request/ack sequencing, staggered AXI ready/valid handshakes, propagated `SLVERR` responses, and reset return to idle. `AxiDualPortRam` covers AXI round-trips, system-port visibility, byte-masked system writes, and AXI write-disable error responses through the existing wrapper. `AxiLiteAsync` is currently validated only on the stable `COMMON_CLK_G=true` wrapper path; the asynchronous reset-crossing branches remain open for later work. `AxiLiteToDrp` is currently validated only on the stable common-clock non-arbitrated path with timeout recovery; the async arbitration branch remains open for later work. - -`AxiRateGen` is now also validated under `tests/axi/axi4/test_AxiRateGen.py` using `axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd`. The module-local validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiRateGen.py`, and it currently passes with `1 passed`. Keep the validated subset intentionally narrow here too: the stable `COMMON_CLK_G=true` path covers AXI-Lite register programming, timer-spaced generated AXI writes, and generated-read completion through a cocotb AXI RAM model, while the asynchronous AXI-Lite crossing branches remain open for later work. - -The remaining final 11 `axi/` modules from the axi-first pass are now also implemented and validated. The new checked-in benches are: -- `tests/axi/axi4/test_AxiReadEmulate.py` -- `tests/axi/axi4/test_AxiWriteEmulate.py` -- `tests/axi/axi4/test_AxiRingBuffer.py` -- `tests/axi/axi4/test_AxiMonAxiL.py` -- `tests/axi/axi_lite/test_AxiLiteRamSyncStatusVector.py` -- `tests/axi/axi_stream/test_AxiStreamMonAxiL.py` -- `tests/axi/dma/test_AxiStreamDmaWrite.py` -- `tests/axi/dma/test_AxiStreamDma.py` -- `tests/axi/dma/test_AxiStreamDmaFifo.py` -- `tests/axi/dma/test_AxiStreamDmaRingRead.py` -- `tests/axi/dma/test_AxiStreamDmaRingWrite.py` - -The supporting wrappers added for that batch are: -- `axi/axi4/ip_integrator/AxiReadEmulateIpIntegrator.vhd` -- `axi/axi4/ip_integrator/AxiWriteEmulateIpIntegrator.vhd` -- `axi/axi4/ip_integrator/AxiRingBufferIpIntegrator.vhd` -- `axi/axi4/ip_integrator/AxiMonAxiLIpIntegrator.vhd` -- `axi/axi-lite/ip_integrator/AxiLiteRamSyncStatusVectorIpIntegrator.vhd` -- `axi/axi-stream/ip_integrator/AxiStreamMonAxiLIpIntegrator.vhd` -- `axi/dma/ip_integrator/AxiStreamDmaWriteIpIntegrator.vhd` -- `axi/dma/ip_integrator/AxiStreamDmaFifoIpIntegrator.vhd` -- `axi/dma/ip_integrator/AxiStreamDmaIpIntegrator.vhd` -- `axi/dma/ip_integrator/AxiStreamDmaRingReadIpIntegrator.vhd` -- `axi/dma/ip_integrator/AxiStreamDmaRingWriteIpIntegrator.vhd` - -The combined validation command for that batch is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiReadEmulate.py tests/axi/axi4/test_AxiWriteEmulate.py tests/axi/axi4/test_AxiRingBuffer.py tests/axi/axi4/test_AxiMonAxiL.py tests/axi/axi_lite/test_AxiLiteRamSyncStatusVector.py tests/axi/axi_stream/test_AxiStreamMonAxiL.py tests/axi/dma/test_AxiStreamDmaWrite.py tests/axi/dma/test_AxiStreamDma.py tests/axi/dma/test_AxiStreamDmaFifo.py tests/axi/dma/test_AxiStreamDmaRingRead.py tests/axi/dma/test_AxiStreamDmaRingWrite.py`, and it passes locally with `11 passed`. - -One small RTL fix landed during that validation pass because the new `AxiStreamDmaRingWrite` test exposed a real simulation-width hazard: `axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd` now slices `dmaAck.size` back to `RAM_DATA_WIDTH_C` before incrementing `nextAddr`. Keep that change; it is what allows the checked-in narrow wrapper to simulate cleanly under GHDL. - -A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instantiation_graph.md` and `docs/_meta/rtl_instantiation_graph.json`, and the same generator now also emits a path-qualified bottom-up phase-1 queue at `docs/_meta/rtl_phase1_queue.md` and `docs/_meta/rtl_phase1_queue.json`. Keep the graph and queue for provenance, but treat them as historical context rather than as the default source of truth for what to implement next. - -## Immediate Next Task -Wait for the next user-directed area selection, then keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with whatever lands in the tree. The immediate documentation priority is accuracy of the real done/open frontier, not regeneration of the historical queue artifacts. - -## Read Order -1. `docs/_meta/rtl_regression_handoff.md` -2. `docs/_meta/rtl_regression_progress.md` -3. `docs/_meta/rtl_regression_plan.md` -4. `docs/_meta/rtl_phase1_queue.md` only if historical graph output is useful for context; it is no longer the active planning driver. - -Before writing code in a fresh session: -1. Re-read the Python comment rules and the checked-in wrapper comment/header rules above. -2. If adding a permanent `*IpIntegrator.vhd`, include the standard SURF banner and section comments in the first edit, not as an afterthought. -3. If adding a Python regression, include the standard SURF/SLAC header, the `Test methodology` header block, and in-body tutorial comments in the first draft. -4. If creating or editing any VHDL file, run `./.venv/bin/vsg -c vsg-linter.yml ...` on that file set, use `--fix` when possible, and rerun the same lint command until it is clean. -5. After any step that launches `pytest`, cocotb, GHDL, or another simulator process, sweep for stale child processes and kill any leftovers before starting the next step. - -## Important Repo Facts -- New Python regressions should be organized under subsystem packages in `tests/` -- Shared Python regression helper lives in `tests/common/regression_utils.py` -- `tests/common/regression_utils.py` now supports both test-local extra VHDL source lists and generated test-local wrapper emission for wrapper-based cases -- `tests/common/regression_utils.py` also now provides `start_lockstep_clocks()` for `COMMON_CLK_G` style benches that require truly shared edges -- Default comment style for new cocotb tests has two parts: a wrapped four-bullet `Test methodology` header (`Sweep`, `Stimulus`, `Checks`, `Timing`) plus tutorial-style in-body comments that explain what each coroutine step is doing and why -- New cocotb tests should also use the standard SURF/SLAC file header, not a shortened local variant -- The methodology header should be module-specific and describe the real curated sweep, driven sequence, expected outputs/state changes, and timing checks; avoid generic boilerplate -- Keep methodology comment lines to a normal readable width in the source file -- Checked-in cocotb-facing `*IpIntegrator.vhd` files should also follow repo style: standard SLAC/SURF banner at the top and short section comments marking shim setup, DUT hookup, and flattening/status export logic -- For AXI Stream and AXI-Lite record ports, prefer the existing IP-integrator shim entities to flatten record interfaces for cocotb instead of hand-writing record packing in each wrapper -- If an AXI wrapper needs DUT-specific extra signals, keep the standard shim pair for the bus itself and only wire the extra signals manually -- More generally, if any module needs a VHDL shim layer to fit cleanly into the cocotb flow, that shim belongs in the nearest real subsystem `ip_integrator/` tree rather than under `tests/` -- Do not use generic `hdl/` buckets for cocotb-facing adapter layers; reserve those locations for genuinely different kinds of HDL support -- Many VHDL wrappers live under `*/tb/` -- The initial regression inventory lives in `docs/_meta/rtl_regression_inventory.yaml` -- The RTL instantiation graph lives in `docs/_meta/rtl_instantiation_graph.{md,json}` -- The generated path-qualified phase-1 queue lives in `docs/_meta/rtl_phase1_queue.{md,json}`, but it is now historical context only rather than the next-module source of truth -- Manual phase-1 queue deferrals and order overrides still live in `docs/_meta/rtl_phase1_queue_overrides.json`, but that file is not the active task-selection mechanism anymore -- Use `./.venv/bin/python ...` for repo-local Python commands unless the virtualenv has already been activated in the current shell; do not assume a `python` shim exists on `PATH` -- If GHDL rejects a direct command-line override for a non-scalar or real generic, prefer a generated thin test-only wrapper over simulator-specific literal workarounds or another checked-in one-off HDL shim -- If a wrapper branch is unstable under the current open-source flow, keep the validated subset narrow and record the omitted branch explicitly in the docs instead of over-claiming wrapper coverage -- Use `ps -Ao pid,ppid,stat,time,command` when needed to find stale simulation children, then terminate only the leftover run trees instead of broad process classes -- `LutFixedDelay` remains intentionally deferred because it depends on `SinglePortRamPrimitive`; do not accidentally treat the now-small remaining `base/` set as phase-1 work that still needs to be forced through -- Regenerate the graph and the phase-1 queue with `./.venv/bin/python scripts/build_rtl_instantiation_graph.py` only when historical analysis is useful or the user explicitly asks for it -- Local bootstrap entrypoint: `scripts/setup_regression_env.sh` -- Local `ruckus` is linked from `~/ruckus` - -## Resume Rule -If resuming implementation, update `docs/_meta/rtl_regression_progress.md` first. diff --git a/docs/_meta/rtl_regression_inventory.yaml b/docs/_meta/rtl_regression_inventory.yaml deleted file mode 100644 index 7b84471fd9..0000000000 --- a/docs/_meta/rtl_regression_inventory.yaml +++ /dev/null @@ -1,700 +0,0 @@ -version: 1 -last_updated: 2026-03-21 - -field_guide: - entity: "Synthesizable RTL entity name" - path: "Path to the synthesizable RTL source file" - subsystem: "High-level repo grouping used for rollout and sharding" - tier: "One of functional_python, smoke_python, wrapper_required, deferred_vendor_heavy" - status: "Implementation state for this inventory row" - priority: "Rollout priority; pilot marks the initial implementation set" - wrapper_path: "Optional VHDL wrapper/shim used for cocotb access" - python_test: "Planned or implemented Python regression entrypoint" - reference_assets: "Legacy assets worth mining for intent, not preserving as execution requirements" - notes: "Short implementation notes" - deferred_reason: "Required when tier is deferred_vendor_heavy" - -inventory_rules: - - "Every synthesizable RTL entity should eventually appear exactly once in this inventory." - - "Executable regression logic must live in Python." - - "VHDL may remain only as thin wrappers, shims, or required simulation models." - - "Legacy VHDL testbenches are reference material, not a preservation target." - - "Generic-heavy modules should prefer functional_python over smoke_python when actively implemented." - -modules: - - entity: Crc32Parallel - path: base/crc/rtl/Crc32Parallel.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/crc/test_Crc32Parallel.py - reference_assets: [] - notes: "Graph-guided CRC leaf with validated coverage for byte-width variation, registered vs direct input handling, and reset polarity/style variants against a shared Python CRC model." - deferred_reason: "" - - - entity: Crc32 - path: base/crc/rtl/Crc32.vhd - subsystem: base - tier: functional_python - status: implemented_validated_expanded - priority: phase1_low_level - wrapper_path: base/crc/wrappers/Crc32PolyWrapper.vhd - python_test: tests/base/crc/test_Crc32.py - reference_assets: [] - notes: "Graph-guided generic CRC leaf with validated coverage for IEEE CRC-32, Castagnoli, and Koopman-style 32-bit polynomial cases plus byte-width, input-register, and reset polarity/style variation. Uses a thin test-only wrapper because the local GHDL flow rejects direct command-line overrides of the 32-bit `CRC_POLY_G` `slv` generic." - deferred_reason: "" - - - entity: CRC32Rtl - path: base/crc/rtl/CRC32Rtl.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/crc/test_CRC32Rtl.py - reference_assets: [] - notes: "Legacy-compatible fixed-polynomial CRC leaf with validated baseline behavioral coverage for synchronous and asynchronous reset handling and reset polarity variation." - deferred_reason: "" - - - entity: RstSync - path: base/sync/rtl/RstSync.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_RstSync.py - reference_assets: [] - notes: "High-fanout reset synchronizer from the graph-guided leaf set. Validated coverage includes release-delay behavior, active-high vs active-low reset polarity, asynchronous vs synchronous power-on reset handling, and bypass/no-output configurations." - deferred_reason: "" - - - entity: PwrUpRst - path: base/general/rtl/PwrUpRst.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/general/test_PwrUpRst.py - reference_assets: [] - notes: "Reusable reset-generator primitive with validated coverage for counter-based startup stretch behavior, synchronous vs asynchronous reset handling, and reset polarity variation." - deferred_reason: "" - - - entity: SynchronizerEdge - path: base/sync/rtl/SynchronizerEdge.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SynchronizerEdge.py - reference_assets: [] - notes: "Graph-guided edge-detect synchronizer with validated coverage for rising/falling pulse detection through different sync depths, reset polarity/style variation, and bypass handling." - deferred_reason: "" - - - entity: SynchronizerOneShot - path: base/sync/rtl/SynchronizerOneShot.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SynchronizerOneShot.py - reference_assets: [] - notes: "Graph-guided one-shot synchronizer with validated coverage for single-pulse capture, stretched output behavior, reset polarity/style variation, active-low output mode, and bypass operation." - deferred_reason: "" - - - entity: TrueDualPortRam - path: base/ram/inferred/TrueDualPortRam.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/ram/test_TrueDualPortRam.py - reference_assets: [] - notes: "Reusable dual-port RAM primitive with validated direct cocotb coverage for read-first, write-first, and no-change modes, registered output behavior, byte-write masking, and reset polarity/style variants." - deferred_reason: "" - - - entity: LutRam - path: base/ram/inferred/LutRam.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/ram/test_LutRam.py - reference_assets: [] - notes: "Reusable LUTRAM primitive with validated coverage for combinational and registered variants, read-first/write-first/no-change behavior, multiport access, byte-write masking, and reset polarity/style variants." - deferred_reason: "" - - - entity: FifoRdFsm - path: base/fifo/rtl/inferred/FifoRdFsm.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/fifo/test_FifoRdFsm.py - reference_assets: [] - notes: "Graph-guided FIFO read-side primitive with validated coverage for standard vs FWFT behavior, block vs distributed memory modes, count progression, visible prefetch behavior, underflow-safe idle behavior, and reset polarity/style variants." - deferred_reason: "" - - - entity: SynchronizerVector - path: base/sync/rtl/SynchronizerVector.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SynchronizerVector.py - reference_assets: [] - notes: "High-reuse `base/sync` vector leaf selected from the instantiation graph. Validated curated matrix covers width variation, stage-depth latency, synchronous vs asynchronous reset handling, active-high vs active-low reset polarity, output inversion, and bypass behavior." - deferred_reason: "" - - - entity: RstPipeline - path: base/general/rtl/RstPipeline.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/general/test_RstPipeline.py - reference_assets: [] - notes: "High-reuse `base/general` reset-distribution leaf selected from the instantiation graph. Validated matrix covers stage-depth latency and `INV_RST_G` behavior; timing-only and synthesis-only generics remain intentionally out of scope." - deferred_reason: "" - - - entity: SimpleDualPortRam - path: base/ram/inferred/SimpleDualPortRam.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/ram/test_SimpleDualPortRam.py - reference_assets: [] - notes: "Graph-guided shared RAM primitive with validated direct cocotb coverage for baseline port-A write/port-B read operation, optional output register behavior, byte-write masking, and synchronous/asynchronous reset polarity variants on the read side." - deferred_reason: "" - - - entity: FifoOutputPipeline - path: base/fifo/rtl/FifoOutputPipeline.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/fifo/test_FifoOutputPipeline.py - reference_assets: [] - notes: "Graph-guided FIFO leaf with validated coverage for zero-latency passthrough, pipelined ordering, backpressure holding behavior, and synchronous/asynchronous reset polarity variants using a small FWFT-style source model." - deferred_reason: "" - - - entity: FifoWrFsm - path: base/fifo/rtl/inferred/FifoWrFsm.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/fifo/test_FifoWrFsm.py - reference_assets: [] - notes: "Graph-guided FIFO write-side primitive with validated coverage for startup readiness, count/index progression, full and overflow behavior, programmable-full threshold behavior, gray-coded async mode, and reset polarity/style variants." - deferred_reason: "" - - - entity: Synchronizer - path: base/sync/rtl/Synchronizer.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_Synchronizer.py - reference_assets: [] - notes: "High-reuse `base/sync` leaf selected from the instantiation graph. Validated curated matrix covers synchronous vs asynchronous reset handling, active-high vs active-low reset polarity, stage-depth latency, output inversion, and bypass behavior without introducing a wrapper." - deferred_reason: "" - - - entity: FifoSync - path: base/fifo/rtl/inferred/FifoSync.vhd - subsystem: base - tier: functional_python - status: implemented_validated_expanded - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/fifo/test_FifoSync.py - reference_assets: - - base/fifo/tb/FifoFwftTb.vhd - - base/fifo/tb/FwftCntTb.vhd - notes: "Bottom-up follow-on to FifoAsync. Expanded validated matrix covers FWFT vs standard mode, block vs distributed RAM, reset polarity/style variants, wider/deeper sizing, FWFT pipeline behavior, and threshold-focused cases for the synchronous implementation path." - deferred_reason: "" - - - entity: FifoAsync - path: base/fifo/rtl/inferred/FifoAsync.vhd - subsystem: base - tier: functional_python - status: implemented_validated_expanded - priority: pilot - wrapper_path: "" - python_test: tests/base/fifo/test_FifoAsync.py - reference_assets: - - base/sync/tb/SynchronizerFifoTb.vhd - notes: "Low-level async FIFO pilot. Expanded validated matrix covers FWFT vs standard mode, block vs distributed RAM, reset polarity/style variants, wider/deeper sizing, non-default sync depth, pipeline behavior, and threshold-focused cases. The matrix intentionally excludes TPD_G and INIT_G as non-behavioral here, and BYP_RAM_G because the current implementation does not exercise a separate bypass-RAM path." - deferred_reason: "" - - - entity: DspComparator - path: dsp/generic/fixed/DspComparator.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/dsp/generic/test_DspComparator.py - reference_assets: [] - notes: "First validated `dsp/` leaf in the new cocotb flow. Coverage focuses on comparator truth behavior and pipeline/reset variation rather than a large DSP-generic sweep." - deferred_reason: "" - - - entity: DspAddSub - path: dsp/generic/fixed/DspAddSub.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/dsp/generic/test_DspAddSub.py - reference_assets: - - dsp/generic/tb/DspAddSubTb.vhd - notes: "Validated signed add and subtract behavior with direct and pipelined output paths, including backpressure hold and reset clearing. The legacy VHDL bench only provided free-running stimulus, so the cocotb bench replaces it with explicit arithmetic and interface assertions." - deferred_reason: "" - - - entity: FirFilterTap - path: dsp/generic/fixed/FirFilterTap.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: generated_test_local - python_test: tests/dsp/generic/test_FirFilterTap.py - reference_assets: [] - notes: "Validated signed multiply-accumulate behavior for both generic coefficient initialization and runtime coefficient updates through a generated wrapper. The bench also checks that disabled cycles hold the previous cascade output." - deferred_reason: "" - - - entity: DspPreSubMult - path: dsp/generic/fixed/DspPreSubMult.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/dsp/generic/test_DspPreSubMult.py - reference_assets: [] - notes: "Validated signed pre-subtract multiply behavior, output hold under backpressure, and reset recovery with a direct arithmetic reference model." - deferred_reason: "" - - - entity: DspSquareDiffMult - path: dsp/generic/fixed/DspSquareDiffMult.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/dsp/generic/test_DspSquareDiffMult.py - reference_assets: [] - notes: "Validated signed square-difference multiplication, output hold under backpressure, and reset recovery with explicit Python arithmetic checks." - deferred_reason: "" - - - entity: BoxcarIntegrator - path: dsp/generic/fixed/BoxcarIntegrator.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/dsp/generic/test_BoxcarIntegrator.py - reference_assets: - - dsp/generic/tb/BoxcarIntegratorTb.vhd - notes: "Validated unsigned and signed modes, direct and registered output paths, `obAck` hold behavior, and `intCount` reconfiguration. The cocotb bench keeps the useful rolling-sum intent from the legacy bench but adds explicit interface assertions." - deferred_reason: "" - - - entity: BoxcarFilter - path: dsp/generic/fixed/BoxcarFilter.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/dsp/generic/test_BoxcarFilter.py - reference_assets: - - dsp/generic/tb/BoxcarFilterTb.vhd - notes: "Validated the integrated boxcar filter output scaling and hold behavior with a Python rolling-average model, replacing the legacy demo-style ramp-only bench with explicit output checks." - deferred_reason: "" - - - entity: FirFilterSingleChannel - path: dsp/generic/fixed/FirFilterSingleChannel.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/dsp/generic/test_FirFilterSingleChannel.py - reference_assets: - - dsp/generic/tb/FirFilterSingleChannelTb.vhd - notes: "Validated common-clock FIR data flow, sideband alignment, and AXI-Lite coefficient programming through a generated wrapper. The new bench keeps the useful coefficient-programming intent from the legacy environment but replaces its unasserted waveform stimulus with explicit filtered-output checks." - deferred_reason: "" - - - entity: FirFilterMultiChannel - path: dsp/generic/fixed/FirFilterMultiChannel.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/dsp/generic/test_FirFilterMultiChannel.py - reference_assets: [] - notes: "Validated common-clock parallel multichannel FIR frame flow and AXI-Lite coefficient updates through a generated wrapper, using a per-channel Python FIR reference model and cocotbext-axi stream endpoints." - deferred_reason: "" - - - entity: Fifo - path: base/fifo/rtl/Fifo.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/fifo/test_Fifo.py - reference_assets: [] - notes: "Validated wrapper-focused coverage for the inferred backend only. The regression checks sync-vs-async branch selection, wrapper-level data flow, `INIT_G` forwarding, and the sync-mode `wr_data_count`/`rd_data_count` aliasing rule instead of replaying the full FIFO primitive matrix." - deferred_reason: "" - - - entity: FifoCascade - path: base/fifo/rtl/FifoCascade.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/fifo/test_FifoCascade.py - reference_assets: [] - notes: "Validated wrapper-specific coverage for inferred FWFT paths. The regression checks public `progFullVec`/`progEmptyVec` stage mapping plus a curated output smoke; it intentionally does not claim full multi-stage drain ordering under the current GHDL flow." - deferred_reason: "" - - - entity: FifoMux - path: base/fifo/rtl/FifoMux.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/fifo/test_FifoMux.py - reference_assets: [] - notes: "Validated wrapper-specific coverage currently targets the stable split-to-narrow path, including endian-aware slicing and reset-safe drain behavior. The pack-to-wide branch remains intentionally unclaimed in phase 1 because it did not surface a stable visible output in the current open-source flow." - deferred_reason: "" - - - entity: AsyncGearbox - path: base/general/rtl/AsyncGearbox.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/general/test_AsyncGearbox.py - reference_assets: [] - notes: "Validated asynchronous gearbox wrapper with a Python bit-level reference model, covering representative width conversion and reset behavior without trying to exhaust the full ratio space." - deferred_reason: "" - - - entity: SynchronizerOneShotVector - path: base/sync/rtl/SynchronizerOneShotVector.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SynchronizerOneShotVector.py - reference_assets: [] - notes: "Validated vectorized one-shot synchronizer coverage for lane independence and bypass behavior using a small curated lane matrix." - deferred_reason: "" - - - entity: SynchronizerOneShotCntVector - path: base/sync/rtl/SynchronizerOneShotCntVector.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: generated_test_local - python_test: tests/base/sync/test_SynchronizerOneShotCntVector.py - reference_assets: [] - notes: "Validated counted vector one-shot coverage using a generated test-local wrapper to flatten the array-typed output into a cocotb-friendly interface." - deferred_reason: "" - - - entity: SyncStatusVector - path: base/sync/rtl/SyncStatusVector.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/base/sync/test_SyncStatusVector.py - reference_assets: [] - notes: "Validated status-vector coverage for count/IRQ snapshot behavior. Uses a generated test-local wrapper for the vectorized count output and a lockstep shared-clock helper when `COMMON_CLK_G=true`." - deferred_reason: "" - - - entity: SyncTrigPeriod - path: base/sync/rtl/SyncTrigPeriod.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SyncTrigPeriod.py - reference_assets: [] - notes: "Validated trigger-period monitor with curated common-clock coverage for period accumulation and reset behavior." - deferred_reason: "" - - - entity: SyncMinMax - path: base/sync/rtl/SyncMinMax.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SyncMinMax.py - reference_assets: [] - notes: "Validated common-clock min/max snapshot behavior, including `rstStat` reseeding. Current phase-1 coverage is intentionally limited to the stable common-clock path." - deferred_reason: "" - - - entity: MasterRamIpIntegrator - path: base/general/ip_integrator/MasterRamIpIntegrator.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/general/test_MasterRamIpIntegrator.py - reference_assets: [] - notes: "Validated IP-integrator wrapper coverage for master-side write and read request forwarding, including handshake-safe addressing and shared comment-rich cocotb sequencing." - deferred_reason: "" - - - entity: SlaveRamIpIntegrator - path: base/general/ip_integrator/SlaveRamIpIntegrator.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/general/test_SlaveRamIpIntegrator.py - reference_assets: [] - notes: "Validated IP-integrator wrapper coverage for slave-side data return and write acceptance behavior using direct cocotb handshakes against the exported RAM-style ports." - deferred_reason: "" - - - entity: DualPortRam - path: base/ram/inferred/DualPortRam.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/ram/test_DualPortRam.py - reference_assets: [] - notes: "Validated inferred dual-port RAM wrapper with curated coverage for independent port readback, write-mode semantics, registered-output behavior, byte-write masking, and reset polarity variation." - deferred_reason: "" - - - entity: SlvDelayRam - path: base/delay/rtl/SlvDelayRam.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/delay/test_SlvDelayRam.py - reference_assets: [] - notes: "Validated RAM-backed delay line for configured latency, enable-hold behavior, and reset handling. The bench documents the observed GHDL-visible latency offset instead of pretending the comment-level ideal is cycle-exact." - deferred_reason: "" - - - entity: SlvDelayFifo - path: base/delay/rtl/SlvDelayFifo.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/delay/test_SlvDelayFifo.py - reference_assets: [] - notes: "Validated FIFO-backed delay line with curated coverage for timestamp-ordered delayed delivery and a short-delay smoke that stays inside the stable visible behavior under the current GHDL flow." - deferred_reason: "" - - - entity: SyncClockFreq - path: base/sync/rtl/SyncClockFreq.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/base/sync/test_SyncClockFreq.py - reference_assets: [] - notes: "Validated frequency-monitor wrapper using a generated real-generic shim and lockstep shared-clock helper. The common-clock case is checked against a bounded expected range because the current GHDL-visible quantization lands one count above the abstract target." - deferred_reason: "" - - - entity: SyncTrigRate - path: base/sync/rtl/SyncTrigRate.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/base/sync/test_SyncTrigRate.py - reference_assets: [] - notes: "Validated wrapper/integration coverage for aligned update publication, denser-window rate growth, reset-path liveness, and update-strobe pulse behavior. Exact min/max pipeline semantics remain intentionally covered by the dedicated `SyncMinMax` leaf regression." - deferred_reason: "" - - - entity: SyncTrigRateVector - path: base/sync/rtl/SyncTrigRateVector.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/base/sync/test_SyncTrigRateVector.py - reference_assets: [] - notes: "Validated vectorized trigger-rate wrapper with a generated flattening shim, per-lane rate independence checks, and shared update-strobe pulse behavior on the stable common-clock path." - deferred_reason: "" - - - entity: LutFixedDelay - path: base/delay/rtl/LutFixedDelay.vhd - subsystem: base - tier: deferred_vendor_heavy - status: deferred_phase1 - priority: phase1_deferred - wrapper_path: "" - python_test: "" - reference_assets: [] - notes: "Single remaining non-dummy `base/` gap after the phase-1 practical rollout." - deferred_reason: "Depends on `SinglePortRamPrimitive`, so the current implementation path still drags vendor-specific infrastructure back into the open-source simulation flow." - - - entity: AxiStreamFifoV2 - path: axi/axi-stream/rtl/AxiStreamFifoV2.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: pilot - wrapper_path: axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd - python_test: tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py - reference_assets: - - tests/test_AxiStreamFifoV2IpIntegrator.py - notes: "Generic-heavy AXI-Stream pilot. Reused the IP integrator wrapper and migrated the Python regression into the shared package layout. Current validated sweep covers width-conversion cases plus one VALID_THOLD=0 configuration." - deferred_reason: "" - - - entity: AxiStreamPipeline - path: axi/axi-stream/rtl/AxiStreamPipeline.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd - python_test: tests/axi/axi_stream/test_AxiStreamPipeline.py - reference_assets: - - tests/test_AxiStreamPipelineTb.py - notes: "Validated AXI-Stream helper with a thin flat-port wrapper. The curated sweep covers zero-stage pass-through, staged pipeline ordering and sideband forwarding, backpressure stability, and synchronous/asynchronous reset handling. Staged cases are checked against the wrapper-visible latency of `PIPE_STAGES_G + 2` clocks plus bounded reset flush behavior." - deferred_reason: "" - - - entity: AxiStreamMux - path: axi/axi-stream/rtl/AxiStreamMux.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd - python_test: tests/axi/axi_stream/test_AxiStreamMux.py - reference_assets: - - axi/axi-stream/tb/AxiStreamMuxTb.vhd - - axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd - notes: "Validated AXI-Stream mux coverage with a thin two-input wrapper. The curated sweep covers indexed arbitration with explicit priority plus `disableSel`, routed `TDEST`/`TID` remap under backpressure, and staged asynchronous active-low reset recovery in passthrough mode. Interleave and explicit rearbitrate branches remain intentionally open for later work." - deferred_reason: "" - - - entity: AxiStreamDeMux - path: axi/axi-stream/rtl/AxiStreamDeMux.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd - python_test: tests/axi/axi_stream/test_AxiStreamDeMux.py - reference_assets: - - axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd - - tests/test_AxiStreamDemuxMuxTb.py - notes: "Validated AXI-Stream demux coverage with a thin one-input/two-output wrapper. The curated sweep covers indexed routing, exact-match routed decode under output backpressure, and dynamic-route table behavior including unmatched-destination drop and staged asynchronous active-low reset flush. Wildcard-route patterns and larger fanout counts remain intentionally open for later work." - deferred_reason: "" - - - entity: AxiLiteCrossbar - path: axi/axi-lite/rtl/AxiLiteCrossbar.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-lite/tb/AxiLiteCrossbarTb.vhd - python_test: tests/axi/axi_lite/test_AxiLiteCrossbar.py - reference_assets: - - axi/axi-lite/tb/AxiLiteCrossbarTb.vhd - notes: "Validated AXI-Lite crossbar coverage through the existing cocotb-facing harness topology. The regression checks routed read/write correctness across the local and cascaded regions, decode-miss `DECERR` responses, and concurrent traffic without region cross-coupling." - deferred_reason: "" - - - entity: AxiLiteAsync - path: axi/axi-lite/rtl/AxiLiteAsync.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-lite/ip_integrator/AxiLiteAsyncIpIntegrator.vhd - python_test: tests/axi/axi_lite/test_AxiLiteAsync.py - reference_assets: - - axi/axi-lite/tb/AxiLiteAsyncTb.vhd - notes: "Validated AXI-Lite async-wrapper coverage with a purpose-built IP-integrator adapter. The current passing subset is intentionally narrow: common-clock pass-through plus restart/recovery on the stable wrapper path. The asynchronous reset-crossing branches remain open for later work because they were not simulator-stable enough for this initial batch." - deferred_reason: "" - - - entity: AxiStreamResize - path: axi/axi-stream/rtl/AxiStreamResize.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-stream/ip_integrator/AxiStreamResizeIpIntegrator.vhd - python_test: tests/axi/axi_stream/test_AxiStreamResize.py - reference_assets: - - axi/axi-stream/tb/AxiStreamResizeTb.vhd - notes: "Validated AXI-Stream resize coverage with a thin flat-port adapter. The curated sweep covers equal-width pass-through, 2-byte to 4-byte upsize, and 4-byte to 2-byte downsize with sideband alignment checks plus staged reset flush in the resized cases." - deferred_reason: "" - - - entity: AxiLiteMaster - path: axi/axi-lite/rtl/AxiLiteMaster.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-lite/ip_integrator/AxiLiteMasterIpIntegrator.vhd - python_test: tests/axi/axi_lite/test_AxiLiteMaster.py - reference_assets: [] - notes: "Validated AXI-Lite master coverage with a thin request/ack-to-flat-port adapter and a cocotb slave model. The first bench covers write/read request sequencing, staggered AXI ready/valid handshakes, propagated `SLVERR` responses, and reset return to idle." - deferred_reason: "" - - - entity: AxiLiteToDrp - path: axi/bridge/rtl/AxiLiteToDrp.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/bridge/ip_integrator/AxiLiteToDrpIpIntegrator.vhd - python_test: tests/axi/bridge/test_AxiLiteToDrp.py - reference_assets: [] - notes: "Validated AXI-Lite-to-DRP bridge coverage with a thin flat-port wrapper. The current passing subset is intentionally narrow: common-clock non-arbitrated write/read mapping plus timeout-driven `SLVERR` and `drpUsrRst` recovery. The async arbitration branch remains open for later work." - deferred_reason: "" - - - entity: AxiDualPortRam - path: axi/axi-lite/rtl/AxiDualPortRam.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd - python_test: tests/axi/axi_lite/test_AxiDualPortRam.py - reference_assets: - - axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd - notes: "Validated AXI dual-port RAM coverage through the existing wrapper. The curated sweep covers AXI round-trips, system-port visibility of AXI writes, byte-masked system writes, and AXI write-disable `SLVERR` behavior when wrapper error responses are enabled." - deferred_reason: "" diff --git a/docs/_meta/rtl_regression_plan.md b/docs/_meta/rtl_regression_plan.md deleted file mode 100644 index 724ae44cfa..0000000000 --- a/docs/_meta/rtl_regression_plan.md +++ /dev/null @@ -1,142 +0,0 @@ -# SURF RTL Regression Plan - -## Objective -- Build a repo-wide regression system for synthesizable SURF RTL. -- Standardize on a single executable test framework so new work stays consistent. -- Make progress resumable across many context windows without re-discovery. - -## Chosen Methodology -- Python-only executable test logic. -- Primary stack: `pytest + cocotb + GHDL + ruckus`. -- Local Python commands should use the repo virtualenv interpreter (`./.venv/bin/python`) unless the virtualenv has already been explicitly activated in that shell. -- VHDL is allowed only for thin wrappers, shims, or required simulation models. -- Existing VHDL testbenches are reference material, not execution constraints. -- New Python regression code should use tutorial-style comments by default. -- New Python cocotb test files should start with the standard SURF/SLAC header block, not an ad hoc local header. -- Every Python regression should also carry a short module-specific `Test methodology` block immediately under the SLAC header comment. -- The header methodology block should use four wrapped bullets: `Sweep`, `Stimulus`, `Checks`, and `Timing`. -- The methodology bullets must describe the actual curated parameter sweep, the actual driven input sequence, the expected outputs or state changes, and the timing/latency/pulse/backpressure behavior being checked for that specific module. -- Do not use generic placeholder methodology prose; the header should tell a reader what this specific bench is proving. -- Keep methodology comment lines at a normal source width so the block is readable in the editor instead of turning into single-line paragraphs. -- Assume the reader is not already comfortable with cocotb. -- Comment the purpose of each major step in the test flow, including clock startup, reset sequencing, trigger waits, stimulus phases, and result checks. -- Treat the header methodology block and the in-body tutorial comments as separate requirements; one does not replace the other. -- Shared helpers may stay somewhat denser, but module-level tests should still explain how the Python coroutine behavior maps onto DUT behavior. -- When a DUT generic assumes truly common clocks, drive those clocks from one shared cocotb coroutine rather than starting two same-period clocks independently. -- For Python cocotb files, the minimum first-draft structure is: - - standard SURF/SLAC file header, - - module-specific `Test methodology` block, - - tutorial-style comments in the executable body. -- Checked-in cocotb-facing VHDL wrappers should follow the in-tree SURF style too: add the standard SLAC/SURF banner at the top and include brief section comments for the major adapter regions. -- For `*IpIntegrator.vhd` wrappers, the minimum expected sectioning is usually: - - bus shim section, - - DUT instantiation section, - - output/status flattening section when present. -- Do not leave permanent checked-in wrappers as uncommented bare port maps even if the logic is thin; future sessions should be able to scan the file and identify the adapter shape immediately. -- For any VHDL file you create or edit, run the `vsg` linter with the same configuration CI uses (`./.venv/bin/vsg -c vsg-linter.yml ...`) before considering the work done. -- When `vsg` reports fixable issues, use `--fix`/autofix first, then rerun the same CI-configured lint command to confirm the file is clean. - -## Scope -- Whole repo target. -- Phase 1 focuses on simulator-friendly modules. -- Vendor-heavy modules are deferred in phase 1 unless they become practical under the open-source flow. - -## Coverage Model -- `functional_python` - - Module has a Python-authored cocotb regression. -- `smoke_python` - - Module has compile/elaborate coverage only. -- `wrapper_required` - - Module needs a retained or added VHDL wrapper to expose a cocotb-friendly interface. -- `deferred_vendor_heavy` - - Module is intentionally excluded from phase 1 executable regression. - -## Package Coverage Policy -- VHDL packages are not treated as standalone executable regression targets. -- Type/constant packages are covered transitively through the modules that compile and use them. -- Behavioral package functions and procedures should be covered through DUTs that exercise them whenever practical. -- If an important package function or procedure is not well reached transitively, add a minimal VHDL wrapper and test that wrapper from Python. -- Package-helper wrappers should be tracked separately from the main synthesizable-module inventory when they are introduced. - -## Generic And Configuration Policy -- Generic-heavy modules are Python-first by default. -- Build curated configuration matrices in Python. -- Do not use naive full Cartesian products for broad generic spaces. -- Compute expected behavior dynamically in Python from the active generics. -- If simulator limitations make direct generic overrides awkward, prefer checked-in subsystem-local VHDL wrappers over ad hoc test-local copies. -- Keep checked-in wrappers thin and declarative: expose cycle-friendly or cocotb-friendly generics, map them onto the real DUT generics, and keep them beside the subsystem RTL they adapt. -- For integration wrappers, test the wrapper-specific behavior rather than replaying the full underlying leaf matrix through the wrapper. -- If only a simulator-stable subset of a wrapper is practical in phase 1, keep that subset intentionally narrow and document the unvalidated branches explicitly in the handoff/progress docs. - -## CI And Runtime Policy -- Tier-first split. -- Separate `smoke` and `functional` regression tiers. -- Shard by subsystem only if runtime requires it. -- Keep room for PR-vs-nightly expansion later if runtime and coverage needs justify it. -- Treat simulator process cleanup as part of every verification step, not as optional housekeeping. -- After any command that launches `pytest`, cocotb, GHDL, or another simulation runner, check for stale child processes and kill any leftovers before moving on to the next step. -- When cleanup is needed, prefer an explicit process sweep first (for example with `ps -Ao pid,ppid,stat,time,command`) so only the stale run trees are terminated. - -## Reuse Policy -- Legacy VHDL testbenches are reference material only. -- Rewrite executable test logic in Python when migrating a module into the new regression system. -- Keep VHDL wrappers only when they make Python stimulus materially cleaner. -- Do not preserve old benches purely for historical reasons. -- When a wrapper is needed only to adapt simulator-hostile generics, check it into the nearest subsystem-local `wrappers/` or `ip_integrator/` folder instead of hiding it under `tests/` or a generic `hdl/` bucket. -- For SURF AXI/AxiLite record ports, prefer the existing IP-integrator shim layers (`SlaveAxiStreamIpIntegrator`, `MasterAxiStreamIpIntegrator`, `SlaveAxiLiteIpIntegrator`, `MasterAxiLiteIpIntegrator`) instead of hand-writing record-to-flat unpacking in each test wrapper. -- If a DUT has extra nonstandard side signals, compose those on top of the standard AXI shim pair rather than replacing the standard flattening pattern. -- For wrapper-style protocol benches, prefer thin subsystem wrappers plus cocotb protocol masters/RAM models, and add accepted-handshake monitoring whenever timing-visible protocol behavior is part of the contract being proven. -- More generally, if a VHDL shim layer is needed to make a module practical to drive from cocotb, place that file in the nearest real subsystem `wrappers/` or `ip_integrator/` folder beside related adapter layers. -- Do not place cocotb-facing shim/adaptor VHDL under `tests/` or generic `hdl/` buckets when it is serving the same integration role as the existing `*IpIntegrator.vhd` files. -- When a wrapper is checked in under `wrappers/` or `ip_integrator/`, treat it like production repo HDL for readability purposes: keep the standard file banner and add concise section comments instead of relying on file naming alone. -- Treat checked-in Python cocotb tests the same way: use the normal repo header/comment style in the first draft instead of leaving cleanup for later. - -## Rollout Planning Policy -- Use a checked-in RTL instantiation graph to guide bottom-up rollout decisions. -- Prefer testing high-reuse leaf primitives directly before spending effort on higher-level assemblies that mostly repackage them. -- Use the graph to reduce repeated behavioral testing across adjacent hierarchy levels, not as a substitute for engineering judgment about externally visible behavior. -- Keep the graph and queue artifacts for provenance and optional analysis, but do not use them as the active day-to-day source of truth for task selection. -- The active planning driver is now manual user-directed area selection, with `docs/_meta/rtl_regression_progress.md` and `docs/_meta/rtl_regression_handoff.md` tracking what is done, what is intentionally narrow, and what remains open. -- Do not hand-maintain queue order in this plan. If the graph or queue is regenerated for analysis, treat it as secondary context unless the user explicitly switches back to queue-driven planning. - -## Historical Queue Artifacts -The phase-1 simulator-friendly queue remains available as a generated bottom-up artifact, but it is now historical context rather than the active workflow. - -Retained artifacts: -- `docs/_meta/rtl_phase1_queue.md` -- `docs/_meta/rtl_phase1_queue.json` -- `docs/_meta/rtl_phase1_queue_overrides.json` - -If they are regenerated: -1. Use `./.venv/bin/python scripts/build_rtl_instantiation_graph.py`. -2. Treat the resulting graph and queue as reference material only. -3. Keep the real done/open frontier in `docs/_meta/rtl_regression_progress.md` and `docs/_meta/rtl_regression_handoff.md`. - -## Phase Breakdown -### Phase 1 -- Create the regression inventory and artifact scaffolding. -- Generate and maintain a repo-wide RTL instantiation graph to guide bottom-up prioritization. -- Establish shared Python regression helpers. -- Add smoke coverage for simulator-friendly modules. -- Add functional Python tests for the highest-value pilot modules and reusable blocks. -- Define the migration pattern for wrappers and generic-heavy modules. -- Standardize the subsystem-local checked-in wrapper pattern for real- or vector-generic leaves that need cycle-native test knobs under GHDL. - -### Phase 2 -- Deepen randomized and adversarial coverage. -- Expand curated configuration sweeps for generic-heavy modules. -- Add stronger reusable scoreboards and protocol-specific helpers. -- Revisit deferred vendor-heavy modules after phase 1 baseline stability. - -## Acceptance Criteria For Phase 1 -- The repo has a checked-in inventory and handoff system. -- New windows can recover project state by reading the handoff artifacts only. -- The Python-only regression direction is documented and stable. -- The progress and handoff artifacts stay aligned with the actual validated branch frontier instead of lagging behind completed subsystem waves. -- The smoke/functional tier split is established in the plan and progress tracking. - -## Open Questions And Deferred Decisions -- Whether PR-vs-nightly split is needed immediately or only after runtime data. -- Exact criteria for moving a vendor-heavy module out of `deferred_vendor_heavy`. -- Which user-directed subsystem slice should be taken next after the current documented frontier. -- Whether a separate tracked list of high-risk behavioral package helpers is needed once the module inventory stabilizes. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md deleted file mode 100644 index bac63eb236..0000000000 --- a/docs/_meta/rtl_regression_progress.md +++ /dev/null @@ -1,312 +0,0 @@ -# SURF RTL Regression Progress - -## Summary -- Current phase: Phase-1 implementation active -- Current subsystem: manual user-directed rollout tracking -- Current focus module: keep the planning docs aligned with the actual validated branch frontier while waiting for the next user-directed subsystem slice after the Ethernet thin-area cleanup. -- Last updated: 2026-04-17 - -## Current Frontier Snapshot -- Active planning rule: take the next work item from the user's manual direction, not from `docs/_meta/rtl_phase1_queue.{md,json}`. -- Manual planning note: - - The axi-first pass is complete through the previously remaining final 11 `axi/` modules. - - The current `verification-2` branch already includes the merged `pre-release` state through PR #1392, so the validated `protocols/ssi`, `protocols/pgp`, and current Ethernet waves (`EthMacCore`, `RawEthFramer`, `UdpEngine`, and `IpV4Engine`) are all part of the present branch snapshot. - - The checked-in queue and override artifacts are now retained only as historical provenance and optional graph output; they are no longer the source of truth for choosing the next area. - - Keep the done/open frontier in this progress file and in `docs/_meta/rtl_regression_handoff.md` aligned to the actual tree even if the queue artifacts are stale. - - Treat stale simulator cleanup as mandatory after every launched verification command: after any `pytest`, cocotb, GHDL, or similar simulation step, sweep for leftover child processes and kill them before starting the next task. -- Known expected-open tests on this branch: - - No simulator-friendly expected-open leaf tests remain in the currently covered `ethernet/IpV4Engine` slice, and the recent `EthMacCore` / `UdpEngine` thin-area follow-up is also checked in on this branch. - - The current `EthMac*Xlgmii` import/export leaves are still placeholder no-op RTL, so the checked-in benches document that inert contract rather than claiming functional XLGMII datapath coverage. - - The remaining Ethernet work is in larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, `Caui4Core`, and `RoCEv2`. -- Most recent reusable bench pattern: - - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. - - For `ethernet`, keep using the checked-in wrappers under `ethernet/*/wrappers/` plus the shared helper layers in `tests/ethernet/EthMacCore/ethmac_test_utils.py`, `tests/ethernet/RawEthFramer/raw_eth_test_utils.py`, `tests/ethernet/UdpEngine/udp_test_utils.py`, and `tests/ethernet/IpV4Engine/ipv4_test_utils.py`. The practical first-pass shape is flat EMAC/app beat wrappers with explicit sideband bits, curated functional slices instead of exhaustive generic sweeps, and dedicated pair/integration wrappers only where an old VHDL bench contributes a topology worth preserving. - -## Status -| Subsystem | Inventory | Smoke | Functional | Notes | -| --- | --- | --- | --- | --- | -| Cross-cutting infrastructure | started | not started | started | Shared helper structure now lives in `tests/common/regression_utils.py`; pytest now defaults to `xdist` parallel execution via `pytest.ini`; the checked-in graph/queue artifacts under `docs/_meta/` are retained for provenance, while `rtl_regression_progress.md` and `rtl_regression_handoff.md` are the active planning inputs | -| `base` | started | not started | started | Validated low-level regressions now exist for `FifoAsync`, `FifoSync`, `FifoOutputPipeline`, `FifoWrFsm`, `FifoRdFsm`, `Fifo`, `FifoCascade`, `FifoMux`, `Synchronizer`, `SynchronizerVector`, `SynchronizerEdge`, `SynchronizerOneShot`, `SynchronizerFifo`, `SynchronizerOneShotCnt`, `SynchronizerOneShotVector`, `SynchronizerOneShotCntVector`, `SyncStatusVector`, `SyncTrigPeriod`, `SyncMinMax`, `SyncClockFreq`, `SyncTrigRate`, `SyncTrigRateVector`, `RstSync`, `RstPipeline`, `RstPipelineVector`, `PwrUpRst`, `Arbiter`, `ClockDivider`, `Debouncer`, `Gearbox`, `AsyncGearbox`, `Heartbeat`, `Mux`, `OneShot`, `RegisterVector`, `WatchDogRst`, `Scrambler`, `MasterRamIpIntegrator`, `SlaveRamIpIntegrator`, `SimpleDualPortRam`, `DualPortRam`, `TrueDualPortRam`, `LutRam`, `SlvDelay`, `SlvFixedDelay`, `SlvDelayRam`, `SlvDelayFifo`, `Crc32Parallel`, `Crc32`, and `CRC32Rtl` under subsystem-organized `tests/base/` packages. Remaining uncovered `base/` entities are vendor-heavy, dummy-backed, or `LutFixedDelay`, which is deferred because it depends on `SinglePortRamPrimitive`. | -| `dsp` | started | not started | started | The planned `dsp/generic/fixed` leaf batch is now validated under `tests/dsp/generic/`: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. Shared DSP helpers now live in `tests/dsp/generic/dsp_test_utils.py`, and the legacy VHDL benches under `dsp/generic/tb/` were treated as behavioral reference material rather than as execution constraints. | -| `axi` | started | not started | started | The axi-first pass is now complete for the simulator-friendly queue. The final locally validated batch adds `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`, with a combined `11 passed` validation run on 2026-03-27. Added checked-in subsystem wrappers under `axi/axi4/ip_integrator/`, `axi/axi-lite/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/` for those benches. `AxiStreamFifoV2` now has an expanded `10 passed` wrapper regression under `tests/axi/axi_stream/` covering async and sync width conversion, metadata truncation, `VALID_THOLD` frame-ready and burst-release modes, dynamic pause-threshold behavior, `CASCADE_SIZE=2`, and the `S_HAS_TREADY=0` pause-only source-side path. `AxiResize` now passes its equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` wrapper regression on this branch after the read-hold RTL fix. `AxiLiteAsync`, `AxiLiteToDrp`, and `AxiRateGen` still keep intentionally narrow common-clock subsets while the more timing-sensitive async AXI-Lite crossing branches remain open. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` still keep intentionally narrow first-pass subsets. `AxiStreamDmaV2Read` is now validated with a two-case wrapper regression covering both aligned and short terminal-beat reads after fixing bounded byte-count conversion in `AxiPkg` and terminal-mask generation in `AxiStreamDmaV2Read`. | -| `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. | -| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers both the original leaf slice and the deeper assembly benches for `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`, plus direct `EthMacRxBypass` / `EthMacTxBypass` leaf benches and import/export sweeps that now explicitly include the current placeholder `XLGMII` contract. `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, including the successful multi-beat `RawEthFramerTx` unicast-forwarding path after lookup resolution. `tests/ethernet/UdpEngine/` covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, with the top/wrapper benches now widened across client/server routing paths. `tests/ethernet/IpV4Engine/` covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, and the top/leaf benches now also include protocol-TX and deeper ICMP reject/recovery coverage. The explicit Ethernet caveats are now the larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, `Caui4Core`, and `RoCEv2`, plus the still-placeholder `EthMac*Xlgmii` RTL. | -| `devices` | not started | not started | not started | Many vendor-heavy cases | -| `xilinx` | not started | not started | not started | Many vendor-heavy cases | - -## Completed Decisions -- Use Python-only executable test logic. -- Use `pytest + cocotb + GHDL + ruckus` as the primary stack. -- Keep VHDL only for wrappers, shims, and required simulation models. -- Comment new Python regression code at a tutorial level so readers who are new to cocotb can follow the flow in-place. -- Whole repo is the long-term target. -- Phase 1 focuses on simulator-friendly modules. -- Vendor-heavy modules are deferred in phase 1. -- Generic-heavy modules are Python-first. -- Use curated configuration matrices instead of full Cartesian products. -- Keep a tier-first CI model: `smoke` and `functional`. -- Rewrite legacy VHDL TB logic in Python rather than preserving it by default. -- Keep wrappers only when they make Python interaction cleaner. -- Run the `vsg` linter with CI's `vsg-linter.yml` settings on any created or edited VHDL files, and use autofix before doing manual cleanup when possible. -- Treat VHDL packages as transitively covered unless a behavioral function/procedure needs a dedicated wrapper. -- Treat `docs/_meta/rtl_regression_progress.md` and `docs/_meta/rtl_regression_handoff.md` as the living planning inputs, and treat the checked-in queue artifacts as archival unless the user explicitly asks to resume queue-driven planning. - -## Completed Work Items -- Surveyed repo structure and existing verification flow. -- Reviewed existing Python regressions and representative VHDL testbenches. -- Merged the current `pre-release` branch into `verification-2`, bringing the already-landed `protocols/ssi` and `protocols/pgp` regression waves into the same branch line as the earlier `ethernet/EthMacCore` slice. -- Re-added `dsp/` to the generated phase-1 queue scope so DSP work is tracked by the same bottom-up planner as the other simulator-friendly subsystems. -- Implemented `tests/dsp/generic/test_DspAddSub.py`. -- Validated `tests/dsp/generic/test_DspAddSub.py` locally with `./.venv/bin/python -m pytest -n 0 -q tests/dsp/generic/test_DspAddSub.py`. -- Added shared DSP helpers in `tests/dsp/generic/dsp_test_utils.py` for signed packing/truncation, rolling reference models, cocotb clock-settle timing, and generated FIR wrappers. -- Extended `tests/common/regression_utils.py` so generated-wrapper benches can use short explicit sim-build keys instead of overloading generic/extra-env strings into fragile build paths. -- Implemented `tests/dsp/generic/test_FirFilterTap.py`, `tests/dsp/generic/test_DspPreSubMult.py`, `tests/dsp/generic/test_DspSquareDiffMult.py`, `tests/dsp/generic/test_BoxcarIntegrator.py`, `tests/dsp/generic/test_BoxcarFilter.py`, `tests/dsp/generic/test_FirFilterSingleChannel.py`, and `tests/dsp/generic/test_FirFilterMultiChannel.py`. -- Fixed DSP RTL issues exposed by the new benches in `dsp/generic/fixed/FirFilterTap.vhd`, `dsp/generic/fixed/BoxcarIntegrator.vhd`, and `dsp/generic/fixed/FirFilterSingleChannel.vhd`. -- Validated the full planned DSP leaf batch locally with `./.venv/bin/python -m pytest -n 0 -q tests/dsp/generic` (`15 passed`). -- Compared `cocotb + pytest`, `VUnit`, and `OSVVM` for SURF. -- Chose Python-only executable regression logic. -- Defined the context-handoff artifact set. -- Created the checked-in handoff artifacts under `docs/_meta/`. -- Created the initial regression inventory scaffold in `docs/_meta/rtl_regression_inventory.yaml`. -- Selected and documented the first pilot modules: `FifoAsync`, `AxiStreamFifoV2`, and `AxiLiteAsync`. -- Added `scripts/setup_regression_env.sh` to bootstrap the local regression environment. -- Added `.vscode/tasks.json` with setup, import, and regression tasks. -- Installed local `ghdl` via Homebrew. -- Created `.venv`, installed Python regression dependencies, linked `~/ruckus`, and completed `make MODULES="$PWD" import`. -- Added shared regression helpers in `tests/regression_utils.py`. -- Implemented the first Python pilot regression in `tests/base/fifo/test_FifoAsync.py`. -- Validated `tests/base/fifo/test_FifoAsync.py` locally with `./.venv/bin/python -m pytest -v tests/base/fifo/test_FifoAsync.py`. -- Reorganized new regressions into subsystem packages under `tests/` and moved shared helpers to `tests/common/`. -- Added `tests/README.md` to document the regression layout policy. -- Added the shared Ethernet MAC helper layer in `tests/ethernet/EthMacCore/ethmac_test_utils.py`, including packet builders, checksum helpers, MAC-config byte-order handling, flat EMAC beat helpers, and Ethernet minimum-frame padding support for the import/export loopback benches. -- Added checked-in cocotb-facing wrappers under `ethernet/EthMacCore/wrappers/` for the first `EthMacCore` wave, including loopback wrappers for import/export and top-level tests plus flat wrappers for the checksum, pause, filter, and shift leaves. -- Implemented and validated the first `ethernet/EthMacCore` functional wave under `tests/ethernet/EthMacCore/`: `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`. -- Expanded the first `EthMacCore` wave beyond the initial happy paths: `EthMacTop` now covers filter/backpressure/checksum/pause interactions, `EthMacRxImport` and `EthMacTxExport` now cover both GMII and XGMII plus link-not-ready recovery behavior, the RX/TX checksum benches now include negative and partial-repair cases, `EthMacRxFilter` now covers multicast/broadcast/filter-disable/multi-beat-drop behavior, the RX/TX shift benches now cover runtime shift changes and control-bit propagation, and `EthCrc32Parallel` now sweeps all byte widths `1..16`. -- Ran a quick HDL coverage spike against the local Homebrew `ghdl` build and confirmed it does not expose `--coverage` or a `coverage` subcommand. -- Migrated `AxiStreamFifoV2` into `tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py` and validated the current 10-case sweep locally. -- Expanded `tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py` into a broader 10-case `AxiStreamFifoV2` regression covering thresholded release modes, metadata truncation, multi-stage cascade buffering, and the `S_HAS_TREADY=0` pause-only path, and validated it locally with `10 passed`. -- Revalidated `tests/axi/axi4/test_AxiResize.py` after merging `verification` into `fix-axi-resize`; the equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` cases now all pass locally on this branch, so the stale upsize `xfail` was removed. -- Expanded `FifoAsync` into a curated 12-case matrix and validated it locally under parallel pytest execution. -- Added `pytest.ini` to default to `-n auto --dist=worksteal`, and aligned CI to rely on that default xdist configuration. -- Implemented `tests/base/fifo/test_FifoSync.py` and validated its 11-case matrix locally under parallel pytest execution. -- Added `scripts/build_rtl_instantiation_graph.py` and generated checked-in graph artifacts in `docs/_meta/rtl_instantiation_graph.{md,json}`. -- Implemented `tests/base/sync/test_Synchronizer.py` and validated its 6-case matrix locally under parallel pytest execution. -- Implemented `tests/base/sync/test_SynchronizerVector.py` and validated its 6-case matrix locally under parallel pytest execution. -- Implemented `tests/base/general/test_RstPipeline.py` and validated its 4-case matrix locally under parallel pytest execution. -- Implemented `tests/base/ram/test_SimpleDualPortRam.py` and validated its 5-case matrix locally under parallel pytest execution. -- Implemented `tests/base/fifo/test_FifoOutputPipeline.py` and validated its 5-case matrix locally under parallel pytest execution. -- Implemented `tests/base/fifo/test_FifoWrFsm.py` and validated its 4-case matrix locally under parallel pytest execution. -- Extended `tests/common/regression_utils.py` so regressions can add test-local VHDL wrapper sources when simulator limitations make a thin shim cleaner than direct generic overrides. -- Implemented `tests/base/crc/test_Crc32Parallel.py`, `tests/base/crc/test_Crc32.py`, and `tests/base/crc/test_CRC32Rtl.py` and validated their combined 9-case CRC batch locally under parallel pytest execution. -- Implemented `tests/base/sync/test_RstSync.py`, `tests/base/sync/test_SynchronizerEdge.py`, and `tests/base/sync/test_SynchronizerOneShot.py` and validated their combined 11-case sync/reset batch locally under parallel pytest execution. -- Implemented `tests/base/general/test_PwrUpRst.py` and validated its 3-case matrix locally under parallel pytest execution. -- Implemented `tests/base/ram/test_TrueDualPortRam.py` and `tests/base/ram/test_LutRam.py` and validated their combined 9-case RAM batch locally under parallel pytest execution. -- Implemented `tests/base/fifo/test_FifoRdFsm.py` and validated its 4-case matrix locally under parallel pytest execution. -- Validated the full 10-module follow-on subset in one run with `./.venv/bin/python -m pytest -v tests/base/crc/test_Crc32Parallel.py tests/base/crc/test_Crc32.py tests/base/crc/test_CRC32Rtl.py tests/base/sync/test_RstSync.py tests/base/general/test_PwrUpRst.py tests/base/sync/test_SynchronizerEdge.py tests/base/sync/test_SynchronizerOneShot.py tests/base/ram/test_TrueDualPortRam.py tests/base/ram/test_LutRam.py tests/base/fifo/test_FifoRdFsm.py` (`38 passed`). -- Implemented `tests/base/general/test_Arbiter.py`, `tests/base/general/test_ClockDivider.py`, `tests/base/general/test_Debouncer.py`, `tests/base/general/test_Gearbox.py`, `tests/base/general/test_Heartbeat.py`, `tests/base/general/test_Mux.py`, `tests/base/general/test_OneShot.py`, `tests/base/general/test_RegisterVector.py`, `tests/base/general/test_RstPipelineVector.py`, `tests/base/general/test_Scrambler.py`, `tests/base/general/test_WatchDogRst.py`, `tests/base/delay/test_SlvDelay.py`, `tests/base/delay/test_SlvFixedDelay.py`, `tests/base/sync/test_SynchronizerFifo.py`, and `tests/base/sync/test_SynchronizerOneShotCnt.py`. -- Implemented `tests/axi/axi_stream/test_AxiStreamScatterGather.py`, `tests/axi/axi4/test_AxiMemTester.py`, `tests/axi/dma/test_AxiStreamDmaV2Desc.py`, `tests/axi/dma/test_AxiStreamDmaV2Fifo.py`, `tests/axi/axi4/test_AxiReadPathFifo.py`, `tests/axi/axi4/test_AxiWritePathFifo.py`, `tests/axi/dma/test_AxiStreamDmaV2.py`, `tests/axi/axi_stream/test_AxiStreamBatchingFifo.py`, `tests/axi/axi_stream/test_AxiStreamMon.py`, and `tests/axi/axi_stream/test_AxiStreamRingBuffer.py`, plus the supporting `*IpIntegrator.vhd` wrappers needed for the new AXI4/AXIS/DMA benches. -- Validated the full 15-module follow-on subset in one run with `./.venv/bin/python -m pytest -n 0 -q tests/base/general/test_Arbiter.py tests/base/general/test_ClockDivider.py tests/base/general/test_Debouncer.py tests/base/general/test_Gearbox.py tests/base/general/test_Heartbeat.py tests/base/general/test_Mux.py tests/base/general/test_OneShot.py tests/base/general/test_RegisterVector.py tests/base/general/test_RstPipelineVector.py tests/base/general/test_Scrambler.py tests/base/general/test_WatchDogRst.py tests/base/delay/test_SlvDelay.py tests/base/delay/test_SlvFixedDelay.py tests/base/sync/test_SynchronizerFifo.py tests/base/sync/test_SynchronizerOneShotCnt.py` (`41 passed`). -- Added a shared generated-wrapper path in `tests/common/regression_utils.py` and migrated the `Heartbeat` and `Debouncer` regressions away from checked-in one-off VHDL wrappers. -- Revalidated the generated-wrapper migration locally with `./.venv/bin/python -m pytest -n 0 -q tests/base/general/test_Heartbeat.py tests/base/general/test_Debouncer.py` (`6 passed`) and then revalidated the full 15-module batch (`41 passed`). -- Implemented `tests/dsp/generic/test_DspComparator.py`, `tests/base/fifo/test_Fifo.py`, `tests/base/fifo/test_FifoCascade.py`, `tests/base/fifo/test_FifoMux.py`, `tests/base/general/test_AsyncGearbox.py`, `tests/base/sync/test_SynchronizerOneShotVector.py`, `tests/base/sync/test_SynchronizerOneShotCntVector.py`, `tests/base/sync/test_SyncStatusVector.py`, `tests/base/sync/test_SyncTrigPeriod.py`, and `tests/base/sync/test_SyncMinMax.py`. -- Validated the combined 10-module wrapper/integration batch with `./.venv/bin/python -m pytest -n 0 -q tests/dsp/generic/test_DspComparator.py tests/base/fifo/test_Fifo.py tests/base/fifo/test_FifoCascade.py tests/base/fifo/test_FifoMux.py tests/base/general/test_AsyncGearbox.py tests/base/sync/test_SynchronizerOneShotVector.py tests/base/sync/test_SynchronizerOneShotCntVector.py tests/base/sync/test_SyncStatusVector.py tests/base/sync/test_SyncTrigPeriod.py tests/base/sync/test_SyncMinMax.py` (`18 passed`). -- Implemented `tests/base/general/test_MasterRamIpIntegrator.py`, `tests/base/general/test_SlaveRamIpIntegrator.py`, `tests/base/ram/test_DualPortRam.py`, `tests/base/delay/test_SlvDelayRam.py`, `tests/base/delay/test_SlvDelayFifo.py`, `tests/base/sync/test_SyncClockFreq.py`, `tests/base/sync/test_SyncTrigRate.py`, and `tests/base/sync/test_SyncTrigRateVector.py`. -- Validated the combined remaining non-vendor, non-dummy `base/` batch with `./.venv/bin/python -m pytest -n 0 -q tests/base/general/test_MasterRamIpIntegrator.py tests/base/general/test_SlaveRamIpIntegrator.py tests/base/ram/test_DualPortRam.py tests/base/delay/test_SlvDelayRam.py tests/base/delay/test_SlvDelayFifo.py tests/base/sync/test_SyncClockFreq.py tests/base/sync/test_SyncTrigRate.py tests/base/sync/test_SyncTrigRateVector.py` (`15 passed`). -- Implemented `tests/axi/axi_stream/test_AxiStreamPipeline.py` with a thin flat-port adapter at `axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd`, and validated its curated 3-case sweep locally. -- Implemented `tests/axi/axi_lite/test_AxiLiteCrossbar.py` with a cocotb-facing crossbar wrapper and validated its routed-region, decode-error, and concurrent-traffic coverage locally. -- Validated the first post-`base/` `axi/` pair with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamPipeline.py tests/axi/axi_lite/test_AxiLiteCrossbar.py` (`4 passed`). -- Implemented `tests/axi/axi_stream/test_AxiStreamMux.py` with a thin two-input adapter at `axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd`, and validated its curated indexed-priority, routed-remap, and asynchronous reset/recovery sweep locally (`3 passed`). -- Revalidated the small post-`base/` `axi/` follow-on set with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamPipeline.py tests/axi/axi_stream/test_AxiStreamMux.py tests/axi/axi_lite/test_AxiLiteCrossbar.py` (`7 passed`). -- Implemented `tests/axi/axi_stream/test_AxiStreamDeMux.py` with a thin two-output adapter at `axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd`, and validated its curated indexed-routing, routed-backpressure, and dynamic-route/drop/reset sweep locally (`3 passed`). -- Revalidated the current small `axi/` follow-on subset with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamPipeline.py tests/axi/axi_stream/test_AxiStreamMux.py tests/axi/axi_stream/test_AxiStreamDeMux.py tests/axi/axi_lite/test_AxiLiteCrossbar.py` (`10 passed`). -- Replaced the hand-curated flat phase-1 list with a generated path-qualified queue emitted by `scripts/build_rtl_instantiation_graph.py` into `docs/_meta/rtl_phase1_queue.{md,json}`, backed by explicit filters and manual-order inputs in `docs/_meta/rtl_phase1_queue_overrides.json`. -- Implemented `tests/axi/axi_lite/test_AxiLiteRegs.py`, `tests/axi/axi_lite/test_AxiLiteRespTimer.py`, `tests/axi/axi_lite/test_AxiLiteSlave.py`, `tests/axi/axi_lite/test_AxiLiteWriteFilter.py`, `tests/axi/axi_lite/test_AxiVersion.py`, `tests/axi/axi_stream/test_AxiStreamCombiner.py`, `tests/axi/axi_stream/test_AxiStreamFlush.py`, `tests/axi/axi_stream/test_AxiStreamGearboxPack.py`, `tests/axi/axi_stream/test_AxiStreamGearboxUnpack.py`, and `tests/axi/axi_stream/test_AxiStreamSplitter.py` with thin subsystem-local adapters under `axi/axi-lite/ip_integrator/` and `axi/axi-stream/ip_integrator/`. -- Validated the generated-queue 10-module AXI batch with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_lite/test_AxiLiteRegs.py tests/axi/axi_lite/test_AxiLiteRespTimer.py tests/axi/axi_lite/test_AxiLiteSlave.py tests/axi/axi_lite/test_AxiLiteWriteFilter.py tests/axi/axi_lite/test_AxiVersion.py tests/axi/axi_stream/test_AxiStreamCombiner.py tests/axi/axi_stream/test_AxiStreamFlush.py tests/axi/axi_stream/test_AxiStreamGearboxPack.py tests/axi/axi_stream/test_AxiStreamGearboxUnpack.py tests/axi/axi_stream/test_AxiStreamSplitter.py` (`14 passed`). -- Implemented `tests/axi/axi4/test_AxiReadPathMux.py`, `tests/axi/axi4/test_AxiWritePathMux.py`, `tests/axi/axi4/test_AxiResize.py`, and `tests/axi/bridge/test_AxiToAxiLite.py` with thin subsystem-local adapters at `axi/axi4/ip_integrator/AxiReadPathMuxIpIntegrator.vhd`, `axi/axi4/ip_integrator/AxiWritePathMuxIpIntegrator.vhd`, `axi/axi4/ip_integrator/AxiResizeIpIntegrator.vhd`, and `axi/bridge/ip_integrator/AxiToAxiLiteIpIntegrator.vhd`. -- Validated the stable AXI4/bridge follow-on subset with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiReadPathMux.py tests/axi/axi4/test_AxiWritePathMux.py tests/axi/bridge/test_AxiToAxiLite.py` (`3 passed`). `tests/axi/axi4/test_AxiResize.py` is present on this branch with the restored upsize case, but that case is expected to fail until the separate `AxiResize` RTL-fix branch is merged. -- Implemented `tests/axi/axi_stream/test_AxiStreamTrailerRemove.py`, `tests/axi/axi4/test_AxiRam.py`, `tests/axi/bridge/test_AxiLiteToIpBus.py`, `tests/axi/bridge/test_IpBusToAxiLite.py`, `tests/axi/dma/test_AxiStreamDmaV2Read.py`, `tests/axi/axi_stream/test_AxiStreamGearbox.py`, `tests/axi/axi_stream/test_AxiStreamTap.py`, `tests/axi/dma/test_AxiStreamDmaRead.py`, `tests/axi/dma/test_AxiStreamDmaV2Write.py`, and `tests/axi/axi_stream/test_AxiStreamTimer.py` with subsystem-local adapters under `axi/axi-stream/ip_integrator/`, `axi/bridge/ip_integrator/`, and `axi/dma/ip_integrator/`. -- Validated the stable 9-module subset of that generated-queue window with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiRam.py tests/axi/bridge/test_AxiLiteToIpBus.py tests/axi/bridge/test_IpBusToAxiLite.py tests/axi/dma/test_AxiStreamDmaRead.py tests/axi/dma/test_AxiStreamDmaV2Write.py tests/axi/axi_stream/test_AxiStreamGearbox.py tests/axi/axi_stream/test_AxiStreamTap.py tests/axi/axi_stream/test_AxiStreamTimer.py tests/axi/axi_stream/test_AxiStreamTrailerRemove.py` (`9 passed`). `tests/axi/dma/test_AxiStreamDmaV2Read.py` is present on this branch as a minimal one-beat aligned reproducer, but it still fails immediately inside `AxiStreamDmaV2Read` at `31 ns` with `std_logic_arith.vhdl:2014:9: ARG is too large in CONV_INTEGER`, so `AxiStreamDmaV2Read` remains open rather than counted as validated. -- Implemented `tests/axi/axi4/test_AxiRateGen.py` with a thin subsystem-local adapter at `axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd`. -- Validated `AxiRateGen` locally with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiRateGen.py` (`1 passed`) and revalidated the nearby AXI4 subset with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiReadPathMux.py tests/axi/axi4/test_AxiWritePathMux.py tests/axi/axi4/test_AxiRam.py tests/axi/axi4/test_AxiRateGen.py` (`4 passed`). -- Refactored `protocols/line-codes` into a clean three-layer cocotb layout backed by a shared helper in `tests/protocols/line_codes/line_code_test_utils.py`: direct package benches via checked-in `Code*PkgWrapper.vhd` adapters, direct `Encoder*`/`Decoder*` entity benches, and small end-to-end integration smokes that reuse the legacy `protocols/line-codes/tb/LineCode*Tb.vhd` shells instead of duplicated wrapper HDL. -- Added permanent checked-in package adapters at `protocols/line-codes/wrappers/Code8b10bPkgWrapper.vhd`, `protocols/line-codes/wrappers/Code10b12bPkgWrapper.vhd`, and `protocols/line-codes/wrappers/Code12b14bPkgWrapper.vhd`, then removed the duplicated `protocols/line-codes/wrappers/LineCode*Wrapper.vhd` files and their matching `test_LineCode*Wrapper.py` benches. -- The direct-entity benches now cover clock-enable gating, flow-control hold behavior, malformed decoder inputs, dual-byte 8b10b lane coverage, and 12b14b debug-disparity handoff through `test_Encoder*.py` and `test_Decoder*.py`. -- The current line-code validation command is `./.venv/bin/python -m pytest -n 0 -q tests/protocols/line_codes`, and it passes locally with `23 passed`. -- The new package-surface coverage exposed a real `Code12b14bPkg` invalid-K disparity bug; `protocols/line-codes/rtl/Code12b14bPkg.vhd` now leaves `dispOut` unchanged on illegal K requests instead of tripping a GHDL bound-check failure. - -## Current In-Progress Item -- Decide the next non-`pgp3` `protocols/pgp` target now that the shared VC FIFOs and the remaining non-vendor `pgp4/core/rtl` leaves are covered. -- Keep `pgp2b`, `pgp2fc`, `pgp3`, and `pgp4` organized as separate family subpackages with checked-in wrappers rather than falling back to generated shim HDL, but treat `pgp3` as deferred for now. -- Preserve the recent `pgp4` lesson: when the simulation wrapper only exposes stable lock/config surfaces, write the bench around those explicit contracts instead of claiming recovered payload coverage. -- Phase-2 follow-on for `protocols/pgp/pgp4`: broaden the current single payload-bitflip negative test into a small corruption-location matrix that separately covers SOF/header metadata corruption, EOF/tail corruption (including transmitted CRC-field corruption), and 66b header-side framing errors instead of treating all of those cases as equivalent to payload CRC failure. - -## Next 3 Concrete Tasks -- Decide whether the next family pass is deeper directed coverage for the existing `pgp2b`/`pgp2fc` RX and alignment benches or a move into another non-deferred protocol area. -- Keep the `protocols/pgp/pgp4` low-speed leaves on their dedicated lock/config guardrail benches unless a later wrapper explicitly proves the serialized payload path end to end. -- Reuse the new `tests/protocols/pgp/shared/` helper and wrappers if later shared PGP utilities need direct cocotb coverage. - -## Blockers And Risks -- Runtime may grow quickly once configuration-heavy modules are added without careful tiering. -- Wrapper policy must stay narrow or VHDL cruft will accumulate again. -- HDL source coverage is not immediately available with the current local `ghdl` LLVM build; it needs a separate tooling decision if we want it later. - -## Findings Worth Preserving -- For a quick resume, read this file’s `Current Frontier Snapshot`, `Current In-Progress Item`, `Next 3 Concrete Tasks`, and `Findings Worth Preserving` sections before digging through the full log. -- Existing Python regressions are generally the best reusable verification assets. -- Existing VHDL TBs contain useful behavioral intent but are inconsistent as a scalable execution framework. -- Generic-heavy modules strongly favor Python-authored tests. -- Broad repo coverage will require tiering and likely later sharding. -- The initial inventory file should remain small and explicit rather than auto-generated until the schema stabilizes. -- `AxiStreamFifoV2` already has a useful wrapper-plus-Python pattern, and the same shim-first approach works well for later AXI wrappers when the DUT-specific extra signals are kept thin. -- AXI Stream leaves with partially driven sideband fields can upset `cocotbext.axi` sinks under GHDL when those fields stay `U`; for first-pass benches, prefer either wrappers that drive those sidebands deterministically or hand-monitored payload checks when the sidebands are not part of the behavior under test. -- Real-generic overrides are still awkward under the local open-source stack; if a module only needs a small non-default real-generic operating point, prefer baking the stable value into the thin subsystem wrapper over fighting simulator-specific override syntax. -- Some wrapper benches need to stay intentionally narrow on this branch to avoid conflating simulator limitations with RTL failures. In this batch that applies to `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux`. -- The local machine needs a reproducible one-command bootstrap path before test implementation work can move efficiently. -- The bootstrap path is now working locally with `~/ruckus` linked into the repo. -- Bare `python` should not be assumed to exist on `PATH` in this repo's shell environment; use `./.venv/bin/python` for local pytest and helper-script invocations unless the virtualenv is already activated. -- The first shared-helper-based pilot is working; start simple and grow coverage incrementally rather than front-loading every edge case. -- New regressions need to live in subsystem packages from the start; do not add more flat `tests/test_*.py` files. -- The current Homebrew `ghdl` install is sufficient for cocotb regressions but not for a simple built-in HDL coverage flow. -- The existing `AxiLiteAsyncTb.vhd` is useful as intent/reference, but it is not an appropriate long-term wrapper because it embeds clocks, memories, and transaction logic; `AxiLiteAsyncIpIntegrator.vhd` is now the cleaner cocotb-facing adapter. -- Future Python regression code should follow the user's preferred two-layer comment style: keep a module-specific `Test methodology` header block under the SLAC banner and also explain major coroutine steps, waits, stimulus phases, and checks in-place for readers who are not already comfortable with cocotb. -- Future Python regression code should also keep the standard SURF/SLAC file header itself; do not treat the methodology block as a substitute for the normal repo banner. -- The methodology block should use wrapped `Sweep`, `Stimulus`, `Checks`, and `Timing` bullets and describe the real bench behavior, not generic filler text. -- The same “write it readable on the first pass” rule applies to permanent cocotb-facing VHDL wrappers: checked-in `*IpIntegrator.vhd` files should carry the standard SURF banner and short section comments for shim setup, DUT hookup, and flattening/status wiring. -- `FifoAsync` needed a curated matrix rather than a naive Cartesian sweep: standard FIFO mode, FWFT mode, and pipelined FWFT do not share identical read/full semantics. -- VHDL packages should not become top-level test targets by default; only high-value behavioral helpers warrant dedicated wrapper tests. -- `FifoSync` benefits from the same curated-matrix approach as `FifoAsync`, but its threshold checks needed event-driven flag handling because `prog_full`/`prog_empty` timing did not line up with fixed write-count assumptions. -- The instantiation graph is useful for rollout planning because it exposes both high-reuse leaves and likely duplicated coverage paths; it should guide prioritization, not dictate exact test depth. -- The generated path-qualified queue in `rtl_phase1_queue.{md,json}` is now the operational phase-1 order. Use the graph for provenance and regeneration, and use `rtl_phase1_queue_overrides.json` for justified defer/reorder exceptions instead of hand-maintaining queue text in the plan doc. -- The first graph pass surfaced `Synchronizer`, `SynchronizerVector`, `SimpleDualPortRam`, `FifoOutputPipeline`, `FifoRdFsm`, and `FifoWrFsm` as concrete `base/` bottom-up candidates after the FIFO pilots. -- Duplicate entity names are common in SURF due to dummy/vendor variants, so graph consumers need to read path context rather than rely on entity names alone. -- A generated path-qualified queue is practical under the current graph parser: the first pass yields `411` phase-1 modules with `0` unresolved duplicate-name phase-1 edges under the checked-in filter set. -- Keep `docs/_meta/rtl_phase1_queue_overrides.json` small and explicit. It should record only real phase-1 scope decisions or blocker-driven order exceptions, not day-to-day queue churn. -- Direct cocotb tests for simple SURF leaf modules still need to account for `TPD_G` when sampling outputs after clock or reset events; sampling exactly at the nominal edge can create false negatives. -- Simple RAM tests benefit from a small startup warm-up and conservative read sampling so direct and registered output configurations share one stable helper. -- For leaf modules with combinational outputs derived from current request inputs, pulse-based tests should drop the request before sampling post-edge state or they may observe the next pending transaction instead of the one just accepted. -- The local GHDL flow rejects direct command-line overrides of a 32-bit `slv` generic in `Crc32`; when a parameterized leaf still needs expanded coverage, prefer a thin test-only wrapper over simulator-specific literal hacks. -- For repeated real-generic shim cases, generated test-local wrappers are a better default than checking in one VHDL file per module; they keep the workaround explicit without growing permanent HDL debris. -- `COMMON_CLK_G` style benches need truly shared edges, not just same-period clocks. A single cocotb coroutine that drives both clocks in lockstep is the safer default for those wrappers. -- Integration-wrapper tests should stay narrow and wrapper-specific. `Fifo` validated both inferred sync/async wrapper branches, `FifoCascade` validated public stage-vector plumbing plus a curated output smoke, and `FifoMux` is currently validated only on the stable split-to-narrow path while the packed-write branch remains deferred. -- `SyncClockFreq` is stable under the generated-wrapper approach, but the common-clock path quantizes one count above the abstract frequency target under GHDL, so the regression checks a bounded expected range instead of an over-precise exact integer. -- `SyncTrigRate` is now covered as a wrapper/integration bench: it validates aligned update publication, denser-window rate growth, reset-path liveness, and update-strobe pulse behavior. Exact min/max pipeline arithmetic remains covered by the dedicated `SyncMinMax` leaf regression rather than being re-proven through the wrapper. -- `LutFixedDelay` is the lone non-dummy `base/` entity still deferred in phase 1 because it depends on `SinglePortRamPrimitive`, which is currently only available through the vendor/dummy-backed path. -- `AxiStreamPipeline` is stable with a thin flat-port wrapper. The zero-stage case should be checked as true pass-through, while staged cases should be checked against the wrapper-visible latency of `PIPE_STAGES_G + 2` clocks and a bounded reset flush rather than an over-precise internal-stage assumption. -- `AxiStreamMux` is stable with a thin two-input adapter, but its `disableSel` handling composes with the separate priority-masking step in a non-obvious order: a disabled higher-priority source can still suppress lower-priority requesters. Disable-focused benches should either use equal priorities or mask the lower-priority source instead. -- `AxiStreamMux` interleave and explicit rearbitrate branches remain intentionally out of scope for the first wrapper bench; the validated subset is indexed arbitration plus `disableSel`, routed `TDEST`/`TID` remap under backpressure, and staged reset/recovery in passthrough mode. -- `AxiStreamDeMux` is stable with a thin one-input/two-output adapter. The first bench covers indexed decode, exact-match routed decode under output backpressure, and dynamic-route table behavior including unmatched-destination drop and staged reset flush. Broader wildcard-route patterns and larger fanout counts remain intentionally unproven in this first wrapper bench. -- `AxiLiteCrossbar` is practical under the current open-source flow with a thin cocotb-facing wrapper around the cascaded topology. The useful regression surface is routed-region correctness, decode-miss `DECERR` handling, and concurrent traffic through the cascaded topology, not a giant generic sweep. -- SURF already has reusable AXI record-flattening shims. New AXI Stream and AXI-Lite wrappers should prefer the existing IP-integrator shim layers over hand-written record packing, and only custom-wire the DUT-specific extra side signals on top. -- More generally, any VHDL shim layer added only to make a module fit cleanly into cocotb should live in the nearest real subsystem `ip_integrator/` tree, not under `tests/` and not under generic `hdl/` directories. -- If that shim layer is checked in instead of generated locally, treat it like normal repo HDL rather than disposable glue: add the standard header and enough section comments that the adapter structure is obvious during a later resume. -- Apply the same “first-draft readability” rule to checked-in cocotb tests: standard header first, methodology block second, tutorial comments in the body. -- `AxiReadPathMux` and `AxiWritePathMux` are more stable with tiny source-side pin drivers than with `cocotbext.axi` masters because the muxes rewrite IDs internally; the downstream shared-port checks can still use the library RAM models. -- `protocols/line-codes` is cleaner when split into three layers: direct package benches for exhaustive legal-space and explicit disparity-seed checks, direct `Encoder*`/`Decoder*` entity benches for clock/reset/flow-control behavior, and one small family-level integration smoke that proves the encoder-to-decoder chain still matches the legacy shell. -- For the line-code families, keep the shared Python harness generic and keep legality decisions local to each module bench. `8b10b` varies by byte-lane width, `10b12b` uses the curated `x & 28` K-symbol subset from the legacy bench, and `12b14b` also preserves its historical mixed training pattern plus explicit malformed-decode and illegal-K checks. -- For line-code package coverage, prefer checked-in subsystem wrappers only where the package surface truly needs explicit disparity seeding or direct encode/decode visibility. `Code8b10bPkg`, `Code10b12bPkg`, and `Code12b14bPkg` all follow that pattern now; the family integration layer should reuse existing `tb/LineCode*Tb.vhd` shells rather than cloning them into new wrapper HDL. -- The new package-surface tests are strong enough to expose latent package bugs. In this batch they caught an illegal-K path defect in `Code12b14bPkg` where the package could drive an out-of-range disparity sum; that path is now fixed and should stay covered. -- The current `Code12b14b` cocotb coverage preserves the legacy explicit disparity seeds plus the training/transition sequences, but it still does not carry forward the old VHDL bench's stateful run-length monitor as a passing assertion. Treat that run-length monitor as a known follow-up gap rather than silently assuming it is covered. -- `AxiToAxiLite` is practical with a thin bridge-local adapter, but mixed-width checks need to stay single-beat on the AXI side when the downstream response path is fundamentally AXI-Lite-like. -- `AxiResize` still has an expected verification-branch gap: the restored `32-bit -> 64-bit` upsize case in `tests/axi/axi4/test_AxiResize.py` should keep failing here until the separate RTL-fix branch is merged. -- `AxiRateGen` is practical with the existing AXI4 and AXI-Lite IP-integrator shim pair plus a cocotb AXI RAM model, and the stable first-pass subset is the `COMMON_CLK_G=true` path with timer spacing, zero-fill writes, and generated-read completion rather than the asynchronous AXI-Lite crossing branches. -- For protocol-generator or wrapper-style benches, pair end-state checks with explicit accepted-handshake monitoring whenever the externally visible contract includes timing, burst shape, sideband propagation, or arbitration order. -- The SSI helper layer is now broad enough to justify reuse across the whole subsystem: `FlatSsiEndpoint`, `SsiBeat`, `recv_frame`, contiguous frame driving, optional `TID` handling, and no-output checks cover the current flattened SSI wrappers without each bench re-implementing handshake plumbing. -- `SsiInsertSof` is practical with a small SSI-local wrapper that exposes semantic SOF/EOFE controls instead of treating raw `TUSER` layout as the cocotb API. The currently validated subset keeps `COMMON_CLK_G=true` and FIFO-backed paths enabled; raw `TUSER_MASK_G` bit-level expectations are still a follow-up item if we want to pin down SSI user-bit indexing more aggressively. -- `SsiIbFrameFilter` is practical with the same semantic-wrapper approach, but the wrapper should use native SSI `TUSER_FIRST_LAST_C` encoding rather than a generic normal-user layout so cocotb can drive `SOF`/`EOFE` directly and the DUT sees the expected first/last byte markers. -- `SsiObFrameFilter` is practical with the same native-SSI wrapper contract. The checked-in bench now covers good-frame pass-through, missing-SOF drop, repeated-`SOF` termination, mid-frame `TDEST` termination, the cached-last-user `VALID_THOLD_G=0` `EOFE` drop path with exported drop-flag pulses, and one pipelined `PIPE_STAGES_G=2` pass-through case without relying on fixed latency assumptions. -- `SsiFifo` is practical with the same flat SSI wrapper pattern, but contiguous multi-beat checks need handshake-based observation rather than late frame collection. The earlier apparent middle-beat loss on a 3-beat `SsiFifoWrapper` probe turned out to be a receive-helper artifact; once the helper was corrected to capture accepted handshakes, both `SsiIbFrameFilter` and `SsiFifo` preserved the full frame and the checked-in `SsiFifo` regression could safely add real 3-beat pass-through assertions on the default, frame-ready, and thresholded paths plus a repeated-`SOF` termination check on the composite FIFO wrapper. -- The first reusable SSI Python helper can now absorb whole-frame receive and metadata-extension commonality, but it should still stop short of becoming a golden protocol model. Module-specific policy such as header injection, command decode rules, or filter-drop counters should remain in each bench. -- `AxiStreamDmaV2Read` is stable with a thin IP-integrator wrapper once the read-path byte-count conversions stay bounded to the burst-size window. The checked-in bench proves both aligned and short terminal-beat reads; because the wrapper exports only an 8-bit `TUSER`, the observable contract is first-user propagation rather than separate first/last byte tagging. -- The `axi/dma/rtl/v2/` benches are now intentionally split by behavior instead of repeatedly re-proving the same path through the top-level DMA stack: `AxiStreamDmaV2` and `AxiStreamDmaV2Desc` stay focused on descriptor-manager register/control surfaces, `AxiStreamDmaV2Read` owns aligned and short terminal-beat readout, `AxiStreamDmaV2Write` owns descriptor-return integrity plus burst splitting, `AxiStreamDmaV2WriteMux` owns arbitration ordering, and `AxiStreamDmaV2Fifo` owns the integrated FIFO register/count/pause-threshold surface. -- For checked-in VHDL changes, use the repo virtualenv's `vsg` with `vsg-linter.yml` so local lint matches CI, and prefer `--fix` before manual spacing/alignment cleanup. -- The current `EthMacCore` wave has a few wrapper-visible behavior details worth preserving in the docs instead of rediscovering later: the XGMII import/export loopback retains a frame presented during `phyReady=0` and drains it after link recovery with Ethernet minimum-size padding applied, while the GMII path drops it; `EthMacRxCsum` reliably asserts `IPERR` on a bad IPv4 header checksum but the checked-in wrapper contract does not require `EOFE` on that case; and the RX/TX shift benches need a small idle-plus-settle gap before changing runtime shift controls because the underlying `AxiStreamShift` samples those controls from its IDLE state. -- Verification hygiene now includes process cleanup: if a `pytest`/cocotb/GHDL step leaves stale run trees behind, kill those leftovers immediately before starting another compile or simulation command. - -## Log -- 2026-03-20: Agreed on Python-only executable regression logic and wrapper-only VHDL retention. -- 2026-03-20: Agreed on whole-repo scope with simulator-friendly phase 1 and vendor-heavy deferral. -- 2026-03-20: Agreed to add stable handoff artifacts under `docs/_meta/` before deeper implementation work. -- 2026-03-20: Added `docs/_meta/rtl_regression_inventory.yaml` and seeded it with the first three pilot modules. -- 2026-03-20: Added local bootstrap helpers in `scripts/setup_regression_env.sh` and `.vscode/tasks.json`. -- 2026-03-20: Installed local toolchain and completed the first successful `make MODULES="$PWD" import`. -- 2026-03-20: Added `tests/regression_utils.py` and landed the first passing pilot regression for `FifoAsync`. -- 2026-03-20: Moved new regression infrastructure to `tests/common/`, relocated `FifoAsync` to `tests/base/fifo/`, and documented the subsystem-organized test layout. -- 2026-03-20: Checked local HDL coverage viability; the installed LLVM-backed `ghdl` rejects `--coverage`, so HDL coverage is deferred pending a different simulator/backend decision. -- 2026-03-20: Migrated `AxiStreamFifoV2` into `tests/axi/axi_stream/` and validated the full current 10-case sweep in 146s. -- 2026-04-02: Expanded `tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py` to cover `VALID_THOLD` release behavior, burst gating, dynamic pause control, `CASCADE_SIZE=2`, and `S_HAS_TREADY=0`, and revalidated it locally with `10 passed`. -- 2026-04-02: Merged `verification` into `fix-axi-resize`, reran `tests/axi/axi4/test_AxiResize.py`, and confirmed the previous `32-bit -> 64-bit` upsize `xfail` now passes on this branch; removed the stale `xfail`. -- 2026-04-02: Expanded the `axi/dma/rtl/v2/` regression split without broad overlap. `tests/axi/dma/test_AxiStreamDmaV2Write.py` now covers both single-frame and multi-burst writes, `tests/axi/dma/test_AxiStreamDmaV2WriteMux.py` now covers descriptor-first, simultaneous-launch, and data-first arbitration cases, and `tests/axi/dma/test_AxiStreamDmaV2Fifo.py` now covers the integrated FIFO register map plus dynamic pause-threshold behavior against the live write-buffer count. The combined validation run across `tests/axi/dma/test_AxiStreamDmaV2.py`, `tests/axi/dma/test_AxiStreamDmaV2Desc.py`, `tests/axi/dma/test_AxiStreamDmaV2Read.py`, `tests/axi/dma/test_AxiStreamDmaV2Write.py`, `tests/axi/dma/test_AxiStreamDmaV2WriteMux.py`, and `tests/axi/dma/test_AxiStreamDmaV2Fifo.py` passes locally with `9 passed`. -- 2026-04-02: Started the `protocols/line-codes` refactor by moving the family benches onto a shared helper in `tests/protocols/line_codes/line_code_test_utils.py` and by adding checked-in package-surface wrappers for `Code8b10bPkg`, `Code10b12bPkg`, and `Code12b14bPkg`. -- 2026-04-02: Compared the cocotb line-code coverage against the legacy VHDL benches under `protocols/line-codes/tb/`, preserved the legacy disparity-seed and training-pattern intent in the `Code*Pkg` Python benches, and noted the old `Code12b14bTb.vhd` run-length monitor as the only still-unported legacy assertion. -- 2026-04-02: Completed the clean-slate line-code redesign: deleted the duplicated `LineCode*Wrapper.vhd` and `test_LineCode*Wrapper.py` layer, added direct `test_Encoder*.py` and `test_Decoder*.py` benches against the real RTL entities, reused `protocols/line-codes/tb/LineCode*Tb.vhd` as the thin integration shells, fixed an illegal-K disparity bug in `protocols/line-codes/rtl/Code12b14bPkg.vhd`, and validated the full `tests/protocols/line_codes` directory locally with `23 passed`. -- 2026-04-03: Added `dsp/` back into `scripts/build_rtl_instantiation_graph.py` so the regenerated `docs/_meta/rtl_instantiation_graph.{md,json}` and `docs/_meta/rtl_phase1_queue.{md,json}` artifacts now track `dsp/generic/fixed` alongside the other phase-1 subsystems. -- 2026-04-03: Implemented `tests/dsp/generic/test_DspAddSub.py` as the first post-resume DSP leaf bench, replacing the old free-running `dsp/generic/tb/DspAddSubTb.vhd` stimulus with explicit signed add/sub arithmetic checks plus backpressure-hold and reset-clearing assertions. The module-local validation run passes locally with `2 passed`. -- 2026-04-03: Completed the planned `dsp/generic/fixed` cocotb leaf batch. Added new benches for `FirFilterTap`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`; centralized shared DSP timing/model/wrapper helpers in `tests/dsp/generic/dsp_test_utils.py`; added explicit sim-build-key support for generated wrappers in `tests/common/regression_utils.py`; fixed RTL issues in `FirFilterTap`, `BoxcarIntegrator`, and `FirFilterSingleChannel`; and validated the full directory with `15 passed`. -- 2026-04-06: Started the manual `protocols/ssi` rollout with `SsiInsertSof`. Added the checked-in wrapper `protocols/ssi/wrappers/SsiInsertSofWrapper.vhd`, implemented `tests/protocols/ssi/test_SsiInsertSof.py`, validated the three-case FIFO-backed sweep locally with `3 passed`, and linted the wrapper cleanly with `vsg -c vsg-linter.yml -f`. -- 2026-04-06: Validated the narrow next SSI step with `SsiIbFrameFilter`. Added the checked-in native-SSI wrapper `protocols/ssi/wrappers/SsiIbFrameFilterWrapper.vhd`, implemented `tests/protocols/ssi/test_SsiIbFrameFilter.py`, validated the first-pass same-clock sweep locally with `1 passed`, linted the wrapper cleanly with `vsg --fix -c vsg-linter.yml -f`, and then consolidated shared flat SSI driver/sink timing into `tests/protocols/ssi/ssi_test_utils.py` so `test_SsiInsertSof.py` and `test_SsiIbFrameFilter.py` use the same basic endpoint helper layer. -- 2026-04-06: Added the next outbound SSI step with `SsiObFrameFilter`. Added the checked-in native-SSI wrapper `protocols/ssi/wrappers/SsiObFrameFilterWrapper.vhd`, implemented `tests/protocols/ssi/test_SsiObFrameFilter.py`, validated the narrowed default-mode regression locally with `1 passed`, revalidated the current SSI trio with `5 passed`, and linted the wrapper cleanly with `vsg --fix -c vsg-linter.yml -f`. The stable checked-in subset covers good-frame pass-through plus repeated-`SOF` termination with `PIPE_STAGES_G=0`; the cached-last-user `EOFE` branch for `VALID_THOLD_G=0` remains a follow-up item. -- 2026-04-06: Added the next composite SSI step with `SsiFifo`. Added the checked-in wrapper `protocols/ssi/wrappers/SsiFifoWrapper.vhd`, implemented `tests/protocols/ssi/test_SsiFifo.py`, validated the narrowed smoke regression locally with `1 passed`, and linted the wrapper cleanly with `vsg --fix -c vsg-linter.yml -f`. The stable checked-in subset keeps one physical clock and currently proves valid single-beat pass-through plus missing-SOF drop; multi-beat good-frame integrity, buffered occupancy behavior, and the sync-output gearbox branch remain follow-up items. -- 2026-04-06: Completed the remaining manual `protocols/ssi` leaf batch. Added checked-in wrappers `protocols/ssi/wrappers/SsiCmdMasterPulserWrapper.vhd`, `protocols/ssi/wrappers/SsiCmdMasterWrapper.vhd`, `protocols/ssi/wrappers/SsiFrameLimiterWrapper.vhd`, `protocols/ssi/wrappers/SsiIncrementingTxWrapper.vhd`, `protocols/ssi/wrappers/SsiAxiLiteMasterWrapper.vhd`, and `protocols/ssi/wrappers/SsiDbgTapWrapper.vhd`; added `tests/protocols/ssi/test_SsiCmdMasterPulser.py`, `tests/protocols/ssi/test_SsiCmdMaster.py`, `tests/protocols/ssi/test_SsiFrameLimiter.py`, `tests/protocols/ssi/test_SsiIncrementingTx.py`, `tests/protocols/ssi/test_SsiAxiLiteMaster.py`, and `tests/protocols/ssi/test_SsiDbgTap.py`; extended `tests/protocols/ssi/ssi_test_utils.py` with optional `TID` handling plus shared frame-receive helpers; validated the new six-test batch locally with `6 passed`; and kept wrapper lint clean under `vsg --fix -c vsg-linter.yml -f` plus a clean follow-up lint pass. The current scope is intentionally uneven: `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiIncrementingTx`, and `SsiAxiLiteMaster` have functional first-pass checks, `SsiFrameLimiter` is currently a narrowed single-beat/missing-SOF subset, and `SsiDbgTap` is traffic smoke only because the RTL exposes no externally visible state. -- 2026-04-07: Tightened the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` so flat SSI sources wait for a real handshake edge and shared frame receivers capture accepted handshakes instead of inferring contiguous traffic from post-send snapshots. Revalidated the existing SSI slice locally with `19 passed`. A focused follow-up on `SsiIbFrameFilter` and `SsiFifo` showed the earlier apparent 3-beat middle-word loss was a bench observation bug rather than an RTL bug, after which the checked-in `SsiFifo` regression added a real contiguous 3-beat pass-through assertion and the `SsiAxiLiteMaster` / `SsiIncrementingTx` benches were updated to assert the full emitted frame shapes. -- 2026-04-07: Expanded `tests/protocols/ssi/test_SsiFifo.py` beyond the earlier single-beat subset. The checked-in FIFO bench now proves contiguous 3-beat frame preservation on the default, `VALID_THOLD_G=0`, and `VALID_THOLD_G=2` wrapper paths; exercises repeated-`SOF` malformed-frame handling across the buffered modes; and keeps the existing missing-`SOF` drop plus `SLAVE_READY_EN_G=false` overflow checks. The buffered malformed-frame result is mode-specific at the wrapper boundary: `VALID_THOLD_G=0` drops the malformed repeated-`SOF` frame outright, while `VALID_THOLD_G=2` emits the expected two-beat terminated `EOFE` frame. A follow-up backpressure pass also added explicit drain-side ready toggling on a good 5-beat frame, malformed termination under toggled ready, and thresholded release under intermittent drain stalls so SSI frame policy is now checked under nontrivial sink backpressure without duplicating the full `AxiStreamFifoV2` transport matrix. Revalidated the full touched SSI slice locally with `19 passed`. -- 2026-04-10: Landed the first manual `ethernet/EthMacCore` bench wave under `tests/ethernet/EthMacCore/`, added the required checked-in wrappers under `ethernet/EthMacCore/wrappers/`, and validated the baseline 12-module slice covering `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`. -- 2026-04-10: Expanded that same `EthMacCore` slice beyond the initial happy paths. The checked-in Ethernet MAC suite now covers `EthMacTop` filter/backpressure/checksum/pause interactions, GMII and XGMII import/export plus link-not-ready recovery behavior, checksum negative cases, filter multicast/broadcast/filter-disable/multi-beat-drop behavior, shift runtime-control and control-bit propagation edges, and full byte-width `1..16` logic-path coverage for `EthCrc32Parallel`. The full `tests/ethernet/EthMacCore` directory currently passes locally with `32 passed`. -- 2026-04-17: Expanded the `ethernet/EthMacCore` slice into the deeper assembly layer. The checked-in Ethernet MAC benches now also cover `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo` through the existing subsystem-local wrappers under `ethernet/EthMacCore/wrappers/`. -- 2026-04-17: Added the manual `ethernet/UdpEngine` wave under `tests/ethernet/UdpEngine/`. The checked-in helper layer now lives in `tests/ethernet/UdpEngine/udp_test_utils.py`, the new checked-in wrappers live under `ethernet/UdpEngine/wrappers/`, and the locally validated benches cover `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`. The current local validation command `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/UdpEngine/test_ArpIpTable.py tests/ethernet/UdpEngine/test_UdpEngineArp.py tests/ethernet/UdpEngine/test_UdpEngineDhcp.py tests/ethernet/UdpEngine/test_UdpEngineRx.py tests/ethernet/UdpEngine/test_UdpEngineTx.py tests/ethernet/UdpEngine/test_UdpEngine.py tests/ethernet/UdpEngine/test_UdpEngineWrapper.py` passes with `7 passed`. -- 2026-04-17: Added the manual `ethernet/IpV4Engine` wave under `tests/ethernet/IpV4Engine/`. The checked-in helper layer now lives in `tests/ethernet/IpV4Engine/ipv4_test_utils.py`, the checked-in wrappers live under `ethernet/IpV4Engine/wrappers/`, and the validated benches cover `ArpEngine`, `IcmpEngine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`. -- 2026-04-17: Added `ethernet/IpV4Engine/wrappers/IgmpV2EngineWrapper.vhd` plus `tests/ethernet/IpV4Engine/test_IgmpV2Engine.py`, extending the IPv4 helper layer with IGMP packet builders in `tests/ethernet/IpV4Engine/ipv4_test_utils.py`. The new leaf bench covers power-up membership reports, general-query re-arming, and suppression of a pending local report when a matching inbound membership report is observed, while documenting the two leaf-boundary stale-field quirks that `IpV4EngineTx` ignores. -- 2026-04-16: Merged the current `pre-release` branch into `verification-2`, so this branch line now contains the already-landed SSI and PGP waves from PR #1391 and PR #1392 in addition to the manual Ethernet slice. -- 2026-04-16: Refreshed the planning docs to move the active frontier from “continue Ethernet next” to “refresh the stale queue/override inputs, then resume from the real merged-branch frontier.” -- 2026-04-17: Switched the planning docs from queue-driven task selection to user-directed frontier tracking. The graph and queue artifacts remain checked in for provenance, but `rtl_regression_progress.md` and `rtl_regression_handoff.md` are now the active done/open source of truth. -- 2026-04-17: Expanded `tests/ethernet/RawEthFramer/test_RawEthFramerTx.py` to cover the successful multi-beat unicast forwarding path after lookup resolution. The new leaf test holds the source frame through the exported request phase, models the same nonzero lookup latency the integrated `RawEthFramer` wrapper inserts before `ack`, and validates the full MAC-side wire image alongside the existing request, broadcast-bypass, and zero-MAC drop checks. -- 2026-04-17: Completed the Ethernet thin-area follow-up across `EthMacCore`, `UdpEngine`, and `IpV4Engine`. Added checked-in wrappers `ethernet/EthMacCore/wrappers/EthMacRxBypassWrapper.vhd` and `ethernet/EthMacCore/wrappers/EthMacTxBypassWrapper.vhd`, added `tests/ethernet/EthMacCore/test_EthMacRxBypass.py` and `tests/ethernet/EthMacCore/test_EthMacTxBypass.py`, widened `test_EthMacRxImport.py` / `test_EthMacTxExport.py` to cover the current placeholder `XLGMII` contract, widened `tests/ethernet/UdpEngine/test_UdpEngine.py` and `tests/ethernet/UdpEngine/test_UdpEngineWrapper.py` across additional client/server routing paths, widened `tests/ethernet/IpV4Engine/test_IpV4Engine.py` with a top-level protocol-TX path, and deepened `tests/ethernet/IpV4Engine/test_IcmpEngine.py` with truncated-request rejection, EOFE preservation, and post-reject recovery checks. The combined local validation command `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/EthMacCore/test_EthMacRxImport.py tests/ethernet/EthMacCore/test_EthMacTxExport.py tests/ethernet/EthMacCore/test_EthMacRxBypass.py tests/ethernet/EthMacCore/test_EthMacTxBypass.py tests/ethernet/UdpEngine/test_UdpEngine.py tests/ethernet/UdpEngine/test_UdpEngineWrapper.py tests/ethernet/IpV4Engine/test_IpV4Engine.py tests/ethernet/IpV4Engine/test_IcmpEngine.py` passes locally with `14 passed`. -- 2026-03-20: Added an explicit project rule to comment new Python regression code where intent or runner behavior is not self-evident. -- 2026-03-20: Expanded `FifoAsync` to a validated 12-case parameter matrix and enabled default pytest xdist parallelization with `pytest.ini`. -- 2026-03-20: Added package-coverage policy: packages are covered transitively unless a behavioral helper warrants a dedicated wrapper test. -- 2026-03-20: Switched from pilot-only work to the bottom-up rollout and selected `FifoSync` as the next low-level target. -- 2026-03-20: Implemented and validated an 11-case `FifoSync` matrix under `tests/base/fifo/test_FifoSync.py`. -- 2026-03-20: Added and generated the first-pass RTL instantiation graph to guide bottom-up rollout decisions and reduce repeated test effort across the hierarchy. -- 2026-03-20: Implemented and validated a 6-case `Synchronizer` matrix under `tests/base/sync/test_Synchronizer.py` as the next graph-guided `base` leaf. -- 2026-03-20: Documented that local Python commands should use `./.venv/bin/python` unless the virtualenv is already activated, after a bare `python` invocation failed due to a missing shell shim. -- 2026-03-20: Implemented and validated the next five graph-guided `base` regressions: `SynchronizerVector`, `RstPipeline`, `SimpleDualPortRam`, `FifoOutputPipeline`, and `FifoWrFsm`. -- 2026-03-20: Updated the planning and handoff docs to preserve the user's tutorial-style cocotb comment preference for future regressions. -- 2026-03-20: Implemented and validated the next 10 graph-guided `base` regressions: `Crc32Parallel`, `Crc32`, `CRC32Rtl`, `RstSync`, `PwrUpRst`, `SynchronizerEdge`, `SynchronizerOneShot`, `TrueDualPortRam`, `LutRam`, and `FifoRdFsm`. -- 2026-03-20: Expanded `Crc32` coverage beyond the default IEEE polynomial to include Castagnoli and Koopman-style cases, using a thin test-only VHDL wrapper because local GHDL rejected direct runtime overrides of the 32-bit `CRC_POLY_G` vector generic. -- 2026-03-20: Implemented and validated the next 15 graph-guided `base` regressions: `Arbiter`, `ClockDivider`, `Debouncer`, `Gearbox`, `Heartbeat`, `Mux`, `OneShot`, `RegisterVector`, `RstPipelineVector`, `Scrambler`, `WatchDogRst`, `SlvDelay`, `SlvFixedDelay`, `SynchronizerFifo`, and `SynchronizerOneShotCnt` (`41 passed`). -- 2026-03-21: Replaced the checked-in `Heartbeat`/`Debouncer` wrapper files with a shared generated-wrapper helper in `tests/common/regression_utils.py` and revalidated both the targeted tests (`6 passed`) and the full 15-module batch (`41 passed`). -- 2026-03-21: Implemented and validated the next 10-module wrapper/integration batch: `DspComparator`, `Fifo`, `FifoCascade`, `FifoMux`, `AsyncGearbox`, `SynchronizerOneShotVector`, `SynchronizerOneShotCntVector`, `SyncStatusVector`, `SyncTrigPeriod`, and `SyncMinMax` (`18 passed`). -- 2026-03-21: Added `start_lockstep_clocks()` in `tests/common/regression_utils.py` for `COMMON_CLK_G` style benches and recorded that `FifoCascade`/`FifoMux` should keep intentionally narrow wrapper coverage under the current GHDL flow instead of forcing unstable branches. -- 2026-03-21: Implemented and validated the remaining non-vendor, non-dummy `base/` batch: `MasterRamIpIntegrator`, `SlaveRamIpIntegrator`, `DualPortRam`, `SlvDelayRam`, `SlvDelayFifo`, `SyncClockFreq`, `SyncTrigRate`, and `SyncTrigRateVector` (`15 passed`). `LutFixedDelay` remains deferred because it still depends on `SinglePortRamPrimitive`. -- 2026-03-21: Tightened the comment policy for Python regressions: header-level methodology comments and in-body tutorial comments are both required, the methodology block should use wrapped `Sweep`/`Stimulus`/`Checks`/`Timing` bullets, and the text should stay module-specific and editor-readable. -- 2026-03-21: Started the first post-`base/` simulator-friendly `axi/` follow-on with `AxiStreamPipeline` and `AxiLiteCrossbar` as the next migration targets, using the legacy flat Python benches only as intent/reference while keeping the new work under subsystem-packaged tests. -- 2026-03-21: Implemented and validated `AxiStreamPipeline` and `AxiLiteCrossbar` as the first post-`base/` `axi/` follow-on. `AxiStreamPipeline` uses a thin flat-port wrapper plus a curated pass-through/staged/reset sweep, and `AxiLiteCrossbar` uses a cocotb-facing wrapper for routed-region, decode-error, and concurrent-traffic checks (`4 passed` combined). -- 2026-03-21: Refactored the `AxiStreamPipeline` test adapter to reuse the existing `SlaveAxiStreamIpIntegrator`/`MasterAxiStreamIpIntegrator` shim pair for standard AXIS flattening, preserving only the pipeline-specific sideband wiring in the adapter (`3 passed` on the pipeline regression after the refactor). -- 2026-03-21: Moved and renamed the `AxiStreamPipeline` adapter to `axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd` so its path and name match the existing AXI IP-integrator adapter conventions and live with the rest of the AXI adapter layer. -- 2026-03-21: Tightened the planning rule for cocotb-facing shim placement: if a VHDL adapter is needed to fit a module into cocotb, place it in the nearest real subsystem `ip_integrator/` tree alongside the existing integration shims rather than under `tests/`. -- 2026-03-21: Collapsed the large instantiation-graph output into a reviewed flat phase-1 module build order in `rtl_regression_plan.md` so future windows can take the next queued module directly instead of re-analyzing the JSON graph before every step. -- 2026-03-21: Resumed the flat `axi/` queue at `AxiStreamMux` and chose a dedicated IP-integrator adapter over the existing combined DeMux/Mux harness so the new cocotb bench can stay mux-specific and exercise arbitration plus `TDEST`/`TID` remap behavior directly. -- 2026-03-21: Implemented and validated `AxiStreamMux` with `axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd` plus `tests/axi/axi_stream/test_AxiStreamMux.py`. The validated 3-case sweep covers indexed arbitration with explicit priority and `disableSel`, routed `TDEST`/`TID` remap under backpressure, and staged asynchronous active-low reset recovery (`3 passed`). -- 2026-03-21: Revalidated the current small `axi/` follow-on subset with `tests/axi/axi_stream/test_AxiStreamPipeline.py`, `tests/axi/axi_stream/test_AxiStreamMux.py`, and `tests/axi/axi_lite/test_AxiLiteCrossbar.py` in one run (`7 passed`). -- 2026-03-21: Started the next flat-queue `axi/` item, `AxiStreamDeMux`, and began evaluating whether a dedicated cocotb-facing adapter is cleaner than reusing the older combined DeMux/Mux harness for the first narrow wrapper bench. -- 2026-03-21: Implemented and validated `AxiStreamDeMux` with `axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd` plus `tests/axi/axi_stream/test_AxiStreamDeMux.py`. The validated 3-case sweep covers indexed routing, exact-match routed decode under output backpressure, and dynamic-route/drop/reset behavior (`3 passed`). -- 2026-03-21: Revalidated the current small `axi/` follow-on subset with `tests/axi/axi_stream/test_AxiStreamPipeline.py`, `tests/axi/axi_stream/test_AxiStreamMux.py`, `tests/axi/axi_stream/test_AxiStreamDeMux.py`, and `tests/axi/axi_lite/test_AxiLiteCrossbar.py` in one run (`10 passed`). -- 2026-03-21: Started scoping the next five flat-queue modules after `AxiStreamDeMux`: `AxiStreamResize`, `AxiLiteAsync`, `AxiLiteMaster`, `AxiLiteToDrp`, and `AxiDualPortRam`, beginning with a wrapper/reference-asset pass to separate straightforward benches from blocks that still need adapter cleanup. -- 2026-03-21: Implemented and validated the next five flat-queue modules: `AxiStreamResize`, `AxiLiteAsync`, `AxiLiteMaster`, `AxiLiteToDrp`, and `AxiDualPortRam`. The five-module batch passes with `10 passed`, and a broader AXI follow-on sanity run across pipeline, mux, demux, resize, crossbar, async, master, DRP bridge, and dual-port RAM passes with `20 passed`. `AxiLiteAsync` and `AxiLiteToDrp` intentionally keep only the stable common-clock subsets in this first batch; the async CDC/arbitration branches remain open. -- 2026-03-21: Replaced the hand-maintained flat phase-1 list in the plan with a generated path-qualified bottom-up queue emitted by `scripts/build_rtl_instantiation_graph.py` into `docs/_meta/rtl_phase1_queue.{md,json}`. Checked in `docs/_meta/rtl_phase1_queue_overrides.json` as the only supported input for manual phase-1 deferrals and ordering exceptions; the initial generated queue contains `411` phase-1 modules with `0` unresolved duplicate-name phase-1 edges under the current filter set. -- 2026-03-21: Implemented and validated the next 10 generated-queue AXI modules: `AxiLiteRegs`, `AxiLiteRespTimer`, `AxiLiteSlave`, `AxiLiteWriteFilter`, `AxiVersion`, `AxiStreamCombiner`, `AxiStreamFlush`, `AxiStreamGearboxPack`, `AxiStreamGearboxUnpack`, and `AxiStreamSplitter`. The combined validation command across those 10 module files passes with `14 passed`. -- 2026-03-26: Implemented and validated `AxiReadPathMux`, `AxiWritePathMux`, and `AxiToAxiLite` with subsystem-local IP-integrator adapters plus new `tests/axi/axi4/` and `tests/axi/bridge/` cocotb benches. `tests/axi/axi4/test_AxiResize.py` is also present on this branch, including the restored `32-bit -> 64-bit` upsize case, but that case is expected to fail here until the separate `AxiResize` RTL-fix branch is merged. -- 2026-03-26: Implemented and validated the next 10 generated-queue AXI modules: `AxiStreamDmaV2WriteMux`, `AxiLiteMasterProxy`, `AxiLiteSequencerRam`, `AxiStreamCompact`, `AxiStreamConcat`, `AxiStreamFrameRateLimiter`, `AxiStreamPrbsFlowCtrl`, `AxiStreamRepeater`, `AxiStreamShift`, and `AxiStreamTrailerAppend`. Added subsystem-local wrappers under `axi/dma/ip_integrator/`, `axi/axi-lite/ip_integrator/`, and `axi/axi-stream/ip_integrator/`, plus new cocotb benches under `tests/axi/`. The combined validation run across those 10 module files passes with `10 passed`. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` currently keep intentionally narrow first-pass checks on this branch instead of forcing the less stable simulator corners. -- 2026-03-26: Implemented the next 10 generated-queue AXI module benches: `AxiStreamTrailerRemove`, `AxiRam`, `AxiLiteToIpBus`, `IpBusToAxiLite`, `AxiStreamDmaV2Read`, `AxiStreamGearbox`, `AxiStreamTap`, `AxiStreamDmaRead`, `AxiStreamDmaV2Write`, and `AxiStreamTimer`. The stable 9-module subset passes with `9 passed`, while `AxiStreamDmaV2Read` remains an expected open failure on this branch because the new minimal aligned one-beat reproducer still aborts at `31 ns` inside the DUT with `std_logic_arith.vhdl:2014:9: ARG is too large in CONV_INTEGER`. -- 2026-04-02: Fixed the remaining `AxiStreamDmaV2Read` open issue by bounding the byte-count `conv_integer()` paths in `axi/axi4/rtl/AxiPkg.vhd`, replacing terminal-beat `tKeep`/`tStrb` generation in `axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd` with direct `slv` mask construction, and expanding `tests/axi/dma/test_AxiStreamDmaV2Read.py` into aligned and short-terminal-beat cases. Local validation now passes with `./.venv/bin/python -m pytest -n 0 -q tests/axi/dma/test_AxiStreamDmaV2Read.py` (`2 passed`). -- 2026-03-26: Replaced the temporary legacy-harness `AxiStreamDmaRead` smoke with a cocotb-owned bench plus `AxiStreamDmaReadIpIntegrator.vhd`. The new test drives the DMA request directly, uses a cocotb AXI RAM model, applies output backpressure, and checks payload plus sideband fields without delegating pass/fail to the old VHDL testbench shell (`1 passed`). -- 2026-03-26: Retargeted the remaining legacy-entity holdouts in the current validated set. `AxiRam` now uses `AxiRamIpIntegrator.vhd` plus a cocotb AXI master round-trip bench, `AxiStreamGearbox` now targets `AxiStreamGearboxIpIntegrator.vhd` instead of the old `tb/` shell, and `AxiLiteCrossbar` now targets `AxiLiteCrossbarIpIntegrator.vhd` instead of `AxiLiteCrossbarTb.vhd` (`3 passed` across the retargeted tests). -- 2026-03-26: Resumed the generated queue at `AxiRateGen` and started scoping the cocotb-facing AXI4/IP-integrator pattern for the next `axi/axi4/` regression. -- 2026-03-26: Implemented and validated `AxiRateGen` with `axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd` plus `tests/axi/axi4/test_AxiRateGen.py`. The stable common-clock subset passes with `1 passed`, and a nearby AXI4 sanity run across `AxiReadPathMux`, `AxiWritePathMux`, `AxiRam`, and `AxiRateGen` passes with `4 passed`. -- 2026-03-26: Tightened the planning docs so wrapper readability is explicit instead of implicit: permanent cocotb-facing `*IpIntegrator.vhd` files should include the standard SURF banner and brief section comments in the first edit, just like the Python benches are required to carry their methodology and tutorial comments. -- 2026-03-26: Tightened the planning docs again so the Python-side header rule is explicit too: checked-in cocotb tests should keep the standard SURF/SLAC banner in addition to the required methodology block and tutorial comments; this is now documented as a first-draft requirement rather than an implied cleanup step. -- 2026-03-26: Corrected the queue frontier after noticing the prior resume notes had jumped ahead to `IpV4Engine`. The real next unfinished non-deferred queue entry is `EthMacRxShift`, followed by `EthMacTxExportGmii`, `EthMacTxShift`, `IpV4EngineRx`, `IpV4EngineTx`, `RawEthFramer`, `UdpEngineRx`, `GLinkTxToRx`, `HtspRx`, and `HtspTx`. -- 2026-03-26: Changed the rollout policy to finish `axi/` first before returning to other subsystems. Recorded temporary `ethernet` and `protocols` subsystem deferrals in `docs/_meta/rtl_phase1_queue_overrides.json`, regenerated the queue, and set the active axi frontier to `AxiResize`. -- 2026-03-27: Implemented and validated the final 11 pending `axi/` benches: `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`. Added the required subsystem-local `*IpIntegrator.vhd` wrappers, kept the new Python tests fully commented with the standard SURF header plus methodology/tutorial notes, and validated the final batch with `./.venv/bin/python -m pytest -n 0 -q ...` across the 11 files (`11 passed`). -- 2026-03-27: The new `AxiStreamDmaRingWrite` regression exposed a width-safety issue in the DUT pointer update under GHDL. Fixed `axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd` so `dmaAck.size` is sliced back to the local pointer width before incrementing `nextAddr`, which keeps the logic behavior unchanged for narrower address maps while making the testbench-safe wrapper configuration simulate cleanly. -- 2026-03-26: Implemented and validated the next 10 generated-queue AXI modules after the two known expected-open skips (`AxiResize` and `AxiStreamDmaV2Read`): `AxiStreamScatterGather`, `AxiMemTester`, `AxiStreamDmaV2Desc`, `AxiStreamDmaV2Fifo`, `AxiReadPathFifo`, `AxiWritePathFifo`, `AxiStreamDmaV2`, `AxiStreamBatchingFifo`, `AxiStreamMon`, and `AxiStreamRingBuffer`. Added the required new wrapper files under `axi/axi4/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/`, fixed `tests/common/regression_utils.py` to stringify simulator env values before dispatch, and validated the combined batch with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamScatterGather.py tests/axi/axi4/test_AxiMemTester.py tests/axi/dma/test_AxiStreamDmaV2Desc.py tests/axi/dma/test_AxiStreamDmaV2Fifo.py tests/axi/axi4/test_AxiReadPathFifo.py tests/axi/axi4/test_AxiWritePathFifo.py tests/axi/dma/test_AxiStreamDmaV2.py tests/axi/axi_stream/test_AxiStreamBatchingFifo.py tests/axi/axi_stream/test_AxiStreamMon.py tests/axi/axi_stream/test_AxiStreamRingBuffer.py` (`10 passed`). From 6beb57482ffe2361735f557792b1bd709ebcb40b Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 17 Apr 2026 15:40:53 -0700 Subject: [PATCH 22/92] Fix CI errors. --- tests/ethernet/IpV4Engine/test_IcmpEngine.py | 1 - tests/ethernet/RawEthFramer/test_RawEthFramer.py | 1 - tests/ethernet/RawEthFramer/test_RawEthFramerRx.py | 1 - tests/ethernet/UdpEngine/udp_test_utils.py | 1 - tests/protocols/pgp/pgp4/test_Pgp4RxEb.py | 1 + 5 files changed, 1 insertion(+), 4 deletions(-) diff --git a/tests/ethernet/IpV4Engine/test_IcmpEngine.py b/tests/ethernet/IpV4Engine/test_IcmpEngine.py index bcdad8845b..dbbdb416b2 100644 --- a/tests/ethernet/IpV4Engine/test_IcmpEngine.py +++ b/tests/ethernet/IpV4Engine/test_IcmpEngine.py @@ -37,7 +37,6 @@ setup_flat_emac_testbench, ) from tests.ethernet.IpV4Engine.ipv4_test_utils import ( - ICMP_ECHO_REQUEST, IP_PROTOCOL_ICMP, IPV4_RTL_SOURCES, build_icmp_echo_packet, diff --git a/tests/ethernet/RawEthFramer/test_RawEthFramer.py b/tests/ethernet/RawEthFramer/test_RawEthFramer.py index 028b09be58..b1bb7f7b69 100644 --- a/tests/ethernet/RawEthFramer/test_RawEthFramer.py +++ b/tests/ethernet/RawEthFramer/test_RawEthFramer.py @@ -38,7 +38,6 @@ ) from tests.ethernet.RawEthFramer.raw_eth_test_utils import ( ALT_REMOTE_MAC_WIRE, - ETH_TYPE_CFG, LOCAL_MAC_WIRE, RAWETH_BEAT_BYTES, RAWETH_RTL_SOURCES, diff --git a/tests/ethernet/RawEthFramer/test_RawEthFramerRx.py b/tests/ethernet/RawEthFramer/test_RawEthFramerRx.py index a0c9378020..e79e2779f0 100644 --- a/tests/ethernet/RawEthFramer/test_RawEthFramerRx.py +++ b/tests/ethernet/RawEthFramer/test_RawEthFramerRx.py @@ -37,7 +37,6 @@ ) from tests.ethernet.RawEthFramer.raw_eth_test_utils import ( ETH_TYPE_CFG, - LOCAL_MAC_CFG, LOCAL_MAC_WIRE, REMOTE_MAC_CFG, REMOTE_MAC_WIRE, diff --git a/tests/ethernet/UdpEngine/udp_test_utils.py b/tests/ethernet/UdpEngine/udp_test_utils.py index 397f1cc4f2..b937c2fe33 100644 --- a/tests/ethernet/UdpEngine/udp_test_utils.py +++ b/tests/ethernet/UdpEngine/udp_test_utils.py @@ -23,7 +23,6 @@ cycle, frame_beats_from_bytes, mac_config_word_from_wire, - payload_from_beats, setup_flat_emac_testbench, ) from tests.ethernet.IpV4Engine.ipv4_test_utils import ipv4_config_word diff --git a/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py b/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py index a3df632b35..bd22093869 100644 --- a/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py +++ b/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py @@ -34,6 +34,7 @@ from tests.common.regression_utils import env_flag, env_float, parameter_case from tests.protocols.pgp.pgp4.pgp4_test_utils import ( + PGP4_D_HEADER, PGP4_K_HEADER, initialize_signals, pgp4_idle_word, From 5a8638abd95feff0c3cbc27e485800933ae817f2 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 20 Apr 2026 09:21:36 -0700 Subject: [PATCH 23/92] RoCEv2 tests first pass. --- docs/_meta/rtl_regression_handoff.md | 16 +- docs/_meta/rtl_regression_plan.md | 5 + docs/_meta/rtl_regression_progress.md | 11 +- .../wrappers/EthMacPrepareForICrcWrapper.vhd | 121 ++++++++++++++ .../wrappers/EthMacRxCheckICrcWrapper.vhd | 141 ++++++++++++++++ tests/ethernet/RoCEv2/__init__.py | 9 ++ .../RoCEv2/test_EthMacPrepareForICrc.py | 149 +++++++++++++++++ .../ethernet/RoCEv2/test_EthMacRxCheckICrc.py | 153 ++++++++++++++++++ 8 files changed, 596 insertions(+), 9 deletions(-) create mode 100644 ethernet/RoCEv2/wrappers/EthMacPrepareForICrcWrapper.vhd create mode 100644 ethernet/RoCEv2/wrappers/EthMacRxCheckICrcWrapper.vhd create mode 100644 tests/ethernet/RoCEv2/__init__.py create mode 100644 tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py create mode 100644 tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index d8a94c7a21..df3332a434 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -19,10 +19,10 @@ - Treat stale simulator cleanup as part of task completion: after any `pytest`, cocotb, GHDL, or similar launched verification step, sweep for leftover child processes and kill them before moving on ## Quick Resume Snapshot -- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, and the current Ethernet coverage now spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, and `IpV4Engine`, including the recent thin-area cleanup across direct bypass leaves, broader top-level UDP/IPv4 paths, and deeper ICMP negatives. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. +- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, and the current Ethernet coverage now spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the first `RoCEv2` VHDL-only helper pair, including the recent thin-area cleanup across direct bypass leaves, broader top-level UDP/IPv4 paths, and deeper ICMP negatives. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. - Current axi frontier: complete for the intended simulator-friendly pass in this branch snapshot; do not resume from the older stale `AxiResize` note. - Current validated-open issues: - - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, `Caui4Core`, and `RoCEv2` remain untouched in phase 1. + - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core` remain untouched in phase 1, while `RoCEv2` is only partially covered through the VHDL-only `EthMacPrepareForICrc` and `EthMacRxCheckICrc` leaves. - `EthMacRxImportXlgmii` and `EthMacTxExportXlgmii` are still placeholder no-op RTL; the checked-in tests now lock down that inert contract instead of claiming functional XLGMII support. - Current planning discipline: - Use manual user-directed area selection as the active source of truth for what to work on next. @@ -34,7 +34,7 @@ - Use `start_lockstep_clocks()` when a DUT depends on truly shared clock edges. - Prefer explicit short sim-build keys for generated-wrapper benches when case metadata would otherwise create fragile build paths. - When a wrapper is checked in, write it like the surrounding repo HDL: include the SLAC/SURF banner and enough section comments that a new session can identify the shim, DUT, and flattening regions quickly. - - For the current Ethernet slice, the checked-in wrappers under `ethernet/EthMacCore/wrappers/`, `ethernet/RawEthFramer/wrappers/`, `ethernet/UdpEngine/wrappers/`, and `ethernet/IpV4Engine/wrappers/` are the expected cocotb surfaces. Keep using those subsystem-local wrappers rather than rebuilding record-packing logic in Python. + - For the current Ethernet slice, the checked-in wrappers under `ethernet/EthMacCore/wrappers/`, `ethernet/RawEthFramer/wrappers/`, `ethernet/UdpEngine/wrappers/`, `ethernet/IpV4Engine/wrappers/`, and the new `ethernet/RoCEv2/wrappers/` leaf adapters are the expected cocotb surfaces. Keep using those subsystem-local wrappers rather than rebuilding record-packing logic in Python. - Current cocotb-file discipline: - New test files should start with the standard SURF/SLAC header block. - The `Test methodology` block belongs directly under that header. @@ -54,10 +54,14 @@ - For first-pass wrapper benches, prove the externally visible stable path first and defer shakier simulator-sensitive branches explicitly in the docs instead of stretching one bench to cover everything. - `AxiStreamDmaV2Read` needed a real RTL/runtime fix rather than a bench workaround: keep the bounded byte-count conversion fix in `axi/axi4/rtl/AxiPkg.vhd` and the direct terminal-mask generation in `axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd`. The current wrapper only exposes an 8-bit `TUSER`, so the observable contract in the checked-in bench is first-user propagation plus payload/keep/id/dest and descriptor return fields. - `tests/dsp/generic/dsp_test_utils.py` is now the shared home for DSP-specific signed helpers, rolling reference models, cocotb clock-settle timing, and generated FIR wrappers. Reuse it instead of cloning DSP arithmetic or wrapper boilerplate. +- Before writing new AXI-Lite, AXI Stream, SSI, or ethernet transaction code, search the nearest subsystem `tests/` package for an existing helper module first. Future sessions should assume that a reusable helper probably already exists and should only write new transaction plumbing after confirming the local helper layer is insufficient. - `tests/ethernet/EthMacCore/ethmac_test_utils.py` is now the shared home for the current Ethernet MAC slice: flat EMAC beat helpers, Ethernet/IPv4/UDP packet builders, checksum reference code, MAC-config byte-order helpers, and minimum-frame padding helpers. Reuse it instead of cloning packet or sideband plumbing across `EthMacCore` benches. +- `ethernet/RoCEv2/rtl/EthMacTxRoCEv2.vhd` and `EthMacRxRoCEv2.vhd` are not the practical first phase-1 targets under the current GHDL flow because they pull in the Bluespec-generated CRC/RDMA Verilog path. Start the RoCEv2 slice from the stable VHDL-only helper leaves (`EthMacPrepareForICrc` and `EthMacRxCheckICrc`) and treat the mixed-language wrappers as an explicit follow-on. - `tests/ethernet/RawEthFramer/raw_eth_test_utils.py` now holds the shared raw-Ethernet helper pieces: flat app-side beat helpers, raw-Ethernet header/frame builders, and lookup-handshake utilities reused by the `RawEthFramer`, `RawEthFramerRx`, and `RawEthFramerTx` benches. - `tests/ethernet/UdpEngine/udp_test_utils.py` is now the shared home for the UDP slice: legacy-address constants, pseudo-frame builders, DHCP option helpers, and the common cocotb bench setup for the `ArpIpTable`, `UdpEngine*`, and `UdpEngineWrapper*` wrappers. Reuse it instead of rebuilding IPv4/UDP helper glue in each test module. - `tests/ethernet/IpV4Engine/ipv4_test_utils.py` is now the shared home for the IPv4 slice: packet/header builders and common cocotb bench setup for the `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, and `IpV4Engine*` wrappers. Reuse it instead of cloning IPv4 framing helpers across that directory. +- `tests/protocols/ssi/ssi_test_utils.py` is the shared home for SSI transaction work: flat SSI endpoints, beat/frame helpers, contiguous-frame send, receive/no-output utilities, and `SOF`/`EOFE`-aware assertions. Use it instead of open-coding SSI handshake loops or terminal-flag checks. +- Across the AXI slices, prefer the subsystem helper paths that already exist for register transactions, frame movement, and setup. In practice that means reusing helpers such as `tests/common/regression_utils.py`, the AXI/ethernet subsystem utility modules, and any nearby module-family helpers before inventing a one-off local transaction wrapper. - The current `EthMacCore` slice is intentionally a checked-in-wrapper-first rollout, not a cocotb-generated-wrapper experiment. Keep new Ethernet work on that same pattern unless the simulator forces a very local generic adapter. - The XGMII import/export loopback behavior differs from the GMII path when `phyReady` drops mid-traffic: the blocked frame is retained and drains after link recovery, padded to Ethernet's minimum frame size if it was short. The GMII path drops that blocked frame. Future import/export coverage should preserve that distinction instead of forcing one common expectation. - The current `EthMacRxImportXlgmii.vhd` and `EthMacTxExportXlgmii.vhd` leaves are placeholders: they drive no data-path activity and never pulse the count/status outputs. Future work should treat functional XLGMII support as an RTL gap, not as a missing bench. @@ -156,7 +160,7 @@ One small RTL fix landed during that validation pass because the new `AxiStreamD A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instantiation_graph.md` and `docs/_meta/rtl_instantiation_graph.json`, and the same generator now also emits a path-qualified bottom-up phase-1 queue at `docs/_meta/rtl_phase1_queue.md` and `docs/_meta/rtl_phase1_queue.json`. Keep the graph and queue for provenance, but treat them as historical context rather than as the default source of truth for what to implement next. ## Immediate Next Task -Wait for the next user-directed area selection, then keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with whatever lands in the tree. The immediate documentation priority is accuracy of the real done/open frontier, not regeneration of the historical queue artifacts. +If the user keeps the focus on `ethernet/RoCEv2`, decide whether to stay in the current phase-1 lane and add more VHDL-only helper coverage or to invest in mixed-language support for the top-level TX/RX wrappers and `RoceEngineWrapper`. In either case, keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the real validated subset instead of over-claiming full-family RoCEv2 coverage. ## Read Order 1. `docs/_meta/rtl_regression_handoff.md` @@ -176,6 +180,10 @@ Before writing code in a fresh session: - Shared Python regression helper lives in `tests/common/regression_utils.py` - `tests/common/regression_utils.py` now supports both test-local extra VHDL source lists and generated test-local wrapper emission for wrapper-based cases - `tests/common/regression_utils.py` also now provides `start_lockstep_clocks()` for `COMMON_CLK_G` style benches that require truly shared edges +- When starting a new test, check for nearby shared helper modules before writing any new transaction boilerplate. The expected search order is: `tests/common/`, then the current subsystem package, then closely related subsystem packages that already cover the same protocol family. +- For AXI-Lite benches, prefer existing helpers for repeated register reads/writes, environment decoding, and common bench setup rather than spelling out raw transactions in every file. +- For AXI Stream benches, prefer existing helpers for beat/frame packing, contiguous-frame driving, whole-frame receive, no-output checks, and handshake observation rather than writing custom ready/valid loops unless the DUT exposes a genuinely new contract. +- For SSI benches, prefer `tests/protocols/ssi/ssi_test_utils.py` for beat models, frame helpers, `EOFE`/`SOF` handling, and sink/source setup instead of duplicating SSI transaction utilities in a local test file. - Default comment style for new cocotb tests has two parts: a wrapped four-bullet `Test methodology` header (`Sweep`, `Stimulus`, `Checks`, `Timing`) plus tutorial-style in-body comments that explain what each coroutine step is doing and why - New cocotb tests should also use the standard SURF/SLAC file header, not a shortened local variant - The methodology header should be module-specific and describe the real curated sweep, driven sequence, expected outputs/state changes, and timing checks; avoid generic boilerplate diff --git a/docs/_meta/rtl_regression_plan.md b/docs/_meta/rtl_regression_plan.md index 724ae44cfa..109e162eaa 100644 --- a/docs/_meta/rtl_regression_plan.md +++ b/docs/_meta/rtl_regression_plan.md @@ -82,6 +82,11 @@ - Rewrite executable test logic in Python when migrating a module into the new regression system. - Keep VHDL wrappers only when they make Python stimulus materially cleaner. - Do not preserve old benches purely for historical reasons. +- Before writing new cocotb transaction code, search the nearest subsystem `tests/` package for an existing `*_test_utils.py` or equivalent shared helper module and reuse it when possible. +- Prefer extending an existing helper with one more narrowly useful utility over cloning handshake loops, packet builders, frame receivers, or register-access boilerplate into each new test file. +- For AXI-Lite work, look for existing read/write helpers, setup helpers, and protocol-master wrappers first; do not hand-code repeated register transactions if the subsystem already has a stable helper path. +- For AXI Stream work, look for existing frame/beat helpers, contiguous-send helpers, receive helpers, keep-mask helpers, and handshake monitors before writing custom ready/valid loops. +- For SSI work, prefer the existing SSI helper layer for flat endpoint setup, beat modeling, frame send/receive, no-output checks, and `EOFE`/`SOF`-aware assertions instead of rebuilding SSI transaction plumbing in each bench. - When a wrapper is needed only to adapt simulator-hostile generics, check it into the nearest subsystem-local `wrappers/` or `ip_integrator/` folder instead of hiding it under `tests/` or a generic `hdl/` bucket. - For SURF AXI/AxiLite record ports, prefer the existing IP-integrator shim layers (`SlaveAxiStreamIpIntegrator`, `MasterAxiStreamIpIntegrator`, `SlaveAxiLiteIpIntegrator`, `MasterAxiLiteIpIntegrator`) instead of hand-writing record-to-flat unpacking in each test wrapper. - If a DUT has extra nonstandard side signals, compose those on top of the standard AXI shim pair rather than replacing the standard flattening pattern. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index bac63eb236..a9857d7398 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -3,21 +3,21 @@ ## Summary - Current phase: Phase-1 implementation active - Current subsystem: manual user-directed rollout tracking -- Current focus module: keep the planning docs aligned with the actual validated branch frontier while waiting for the next user-directed subsystem slice after the Ethernet thin-area cleanup. -- Last updated: 2026-04-17 +- Current focus module: the first `ethernet/RoCEv2` phase-1 leaf slice is now validated through the stable VHDL-only helpers, with the larger mixed-language wrapper assemblies still open. +- Last updated: 2026-04-20 ## Current Frontier Snapshot - Active planning rule: take the next work item from the user's manual direction, not from `docs/_meta/rtl_phase1_queue.{md,json}`. - Manual planning note: - The axi-first pass is complete through the previously remaining final 11 `axi/` modules. - - The current `verification-2` branch already includes the merged `pre-release` state through PR #1392, so the validated `protocols/ssi`, `protocols/pgp`, and current Ethernet waves (`EthMacCore`, `RawEthFramer`, `UdpEngine`, and `IpV4Engine`) are all part of the present branch snapshot. + - The current `verification-2` branch already includes the merged `pre-release` state through PR #1392, so the validated `protocols/ssi`, `protocols/pgp`, and current Ethernet waves (`EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the first `RoCEv2` VHDL-only leaf pair) are all part of the present branch snapshot. - The checked-in queue and override artifacts are now retained only as historical provenance and optional graph output; they are no longer the source of truth for choosing the next area. - Keep the done/open frontier in this progress file and in `docs/_meta/rtl_regression_handoff.md` aligned to the actual tree even if the queue artifacts are stale. - Treat stale simulator cleanup as mandatory after every launched verification command: after any `pytest`, cocotb, GHDL, or similar simulation step, sweep for leftover child processes and kill them before starting the next task. - Known expected-open tests on this branch: - No simulator-friendly expected-open leaf tests remain in the currently covered `ethernet/IpV4Engine` slice, and the recent `EthMacCore` / `UdpEngine` thin-area follow-up is also checked in on this branch. - The current `EthMac*Xlgmii` import/export leaves are still placeholder no-op RTL, so the checked-in benches document that inert contract rather than claiming functional XLGMII datapath coverage. - - The remaining Ethernet work is in larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, `Caui4Core`, and `RoCEv2`. + - The remaining Ethernet work is in the larger untouched families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core`, plus the still-open mixed-language `RoCEv2` wrapper/integration path beyond the newly covered VHDL-only helper leaves. - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. @@ -31,7 +31,7 @@ | `dsp` | started | not started | started | The planned `dsp/generic/fixed` leaf batch is now validated under `tests/dsp/generic/`: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. Shared DSP helpers now live in `tests/dsp/generic/dsp_test_utils.py`, and the legacy VHDL benches under `dsp/generic/tb/` were treated as behavioral reference material rather than as execution constraints. | | `axi` | started | not started | started | The axi-first pass is now complete for the simulator-friendly queue. The final locally validated batch adds `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`, with a combined `11 passed` validation run on 2026-03-27. Added checked-in subsystem wrappers under `axi/axi4/ip_integrator/`, `axi/axi-lite/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/` for those benches. `AxiStreamFifoV2` now has an expanded `10 passed` wrapper regression under `tests/axi/axi_stream/` covering async and sync width conversion, metadata truncation, `VALID_THOLD` frame-ready and burst-release modes, dynamic pause-threshold behavior, `CASCADE_SIZE=2`, and the `S_HAS_TREADY=0` pause-only source-side path. `AxiResize` now passes its equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` wrapper regression on this branch after the read-hold RTL fix. `AxiLiteAsync`, `AxiLiteToDrp`, and `AxiRateGen` still keep intentionally narrow common-clock subsets while the more timing-sensitive async AXI-Lite crossing branches remain open. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` still keep intentionally narrow first-pass subsets. `AxiStreamDmaV2Read` is now validated with a two-case wrapper regression covering both aligned and short terminal-beat reads after fixing bounded byte-count conversion in `AxiPkg` and terminal-mask generation in `AxiStreamDmaV2Read`. | | `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. | -| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers both the original leaf slice and the deeper assembly benches for `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`, plus direct `EthMacRxBypass` / `EthMacTxBypass` leaf benches and import/export sweeps that now explicitly include the current placeholder `XLGMII` contract. `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, including the successful multi-beat `RawEthFramerTx` unicast-forwarding path after lookup resolution. `tests/ethernet/UdpEngine/` covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, with the top/wrapper benches now widened across client/server routing paths. `tests/ethernet/IpV4Engine/` covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, and the top/leaf benches now also include protocol-TX and deeper ICMP reject/recovery coverage. The explicit Ethernet caveats are now the larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, `Caui4Core`, and `RoCEv2`, plus the still-placeholder `EthMac*Xlgmii` RTL. | +| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers both the original leaf slice and the deeper assembly benches for `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`, plus direct `EthMacRxBypass` / `EthMacTxBypass` leaf benches and import/export sweeps that now explicitly include the current placeholder `XLGMII` contract. `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, including the successful multi-beat `RawEthFramerTx` unicast-forwarding path after lookup resolution. `tests/ethernet/UdpEngine/` covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, with the top/wrapper benches now widened across client/server routing paths. `tests/ethernet/IpV4Engine/` covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, and the top/leaf benches now also include protocol-TX and deeper ICMP reject/recovery coverage. `tests/ethernet/RoCEv2/` now covers the VHDL-only helper leaves `EthMacPrepareForICrc` and `EthMacRxCheckICrc` through checked-in wrappers under `ethernet/RoCEv2/wrappers/`. The explicit Ethernet caveats are now the larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core`, the still-open mixed-language `RoCEv2` assembly path (`EthMacTxRoCEv2`, `EthMacRxRoCEv2`, the CRC wrapper leaves, and `RoceEngineWrapper`), plus the still-placeholder `EthMac*Xlgmii` RTL. | | `devices` | not started | not started | not started | Many vendor-heavy cases | | `xilinx` | not started | not started | not started | Many vendor-heavy cases | @@ -310,3 +310,4 @@ - 2026-03-27: Implemented and validated the final 11 pending `axi/` benches: `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`. Added the required subsystem-local `*IpIntegrator.vhd` wrappers, kept the new Python tests fully commented with the standard SURF header plus methodology/tutorial notes, and validated the final batch with `./.venv/bin/python -m pytest -n 0 -q ...` across the 11 files (`11 passed`). - 2026-03-27: The new `AxiStreamDmaRingWrite` regression exposed a width-safety issue in the DUT pointer update under GHDL. Fixed `axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd` so `dmaAck.size` is sliced back to the local pointer width before incrementing `nextAddr`, which keeps the logic behavior unchanged for narrower address maps while making the testbench-safe wrapper configuration simulate cleanly. - 2026-03-26: Implemented and validated the next 10 generated-queue AXI modules after the two known expected-open skips (`AxiResize` and `AxiStreamDmaV2Read`): `AxiStreamScatterGather`, `AxiMemTester`, `AxiStreamDmaV2Desc`, `AxiStreamDmaV2Fifo`, `AxiReadPathFifo`, `AxiWritePathFifo`, `AxiStreamDmaV2`, `AxiStreamBatchingFifo`, `AxiStreamMon`, and `AxiStreamRingBuffer`. Added the required new wrapper files under `axi/axi4/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/`, fixed `tests/common/regression_utils.py` to stringify simulator env values before dispatch, and validated the combined batch with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamScatterGather.py tests/axi/axi4/test_AxiMemTester.py tests/axi/dma/test_AxiStreamDmaV2Desc.py tests/axi/dma/test_AxiStreamDmaV2Fifo.py tests/axi/axi4/test_AxiReadPathFifo.py tests/axi/axi4/test_AxiWritePathFifo.py tests/axi/dma/test_AxiStreamDmaV2.py tests/axi/axi_stream/test_AxiStreamBatchingFifo.py tests/axi/axi_stream/test_AxiStreamMon.py tests/axi/axi_stream/test_AxiStreamRingBuffer.py` (`10 passed`). +- 2026-04-20: Started the first `ethernet/RoCEv2` phase-1 slice with the stable VHDL-only helper leaves instead of the mixed-language top wrappers. Added `ethernet/RoCEv2/wrappers/EthMacPrepareForICrcWrapper.vhd` and `ethernet/RoCEv2/wrappers/EthMacRxCheckICrcWrapper.vhd`, implemented `tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py` and `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, linted both wrappers cleanly with `./.venv/bin/vsg -c vsg-linter.yml -f ...`, validated the pair with `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py` (`2 passed`), and recorded the remaining open RoCEv2 work as the mixed-language wrapper/assembly path rather than claiming full-family coverage. diff --git a/ethernet/RoCEv2/wrappers/EthMacPrepareForICrcWrapper.vhd b/ethernet/RoCEv2/wrappers/EthMacPrepareForICrcWrapper.vhd new file mode 100644 index 0000000000..afd1fc05ff --- /dev/null +++ b/ethernet/RoCEv2/wrappers/EthMacPrepareForICrcWrapper.vhd @@ -0,0 +1,121 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for EthMacPrepareForICrc +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity EthMacPrepareForICrcWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + PIPE_STAGES_G : natural := 0); + port ( + ethClk : in sl; + ethRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTDest : in slv(7 downto 0); + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTDest : out slv(7 downto 0); + mAxisTReady : in sl; + mAxisSof : out sl; + mAxisFrag : out sl; + mAxisEofe : out sl); +end entity EthMacPrepareForICrcWrapper; + +architecture rtl of EthMacPrepareForICrcWrapper is + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + ---------------------------------------------------------------------------- + -- Flat cocotb input shim + ---------------------------------------------------------------------------- + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTDest, sAxisTKeep, sAxisTLast, sAxisTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(127 downto 0) := sAxisTData; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + v.tDest(7 downto 0) := sAxisTDest; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); + sAxisMaster <= v; + end process sAxisComb; + + sAxisTReady <= sAxisSlave.tReady; + + mAxisReadyComb : process (mAxisTReady) is + variable v : AxiStreamSlaveType; + begin + v := AXI_STREAM_SLAVE_INIT_C; + v.tReady := mAxisTReady; + mAxisSlave <= v; + end process mAxisReadyComb; + + ---------------------------------------------------------------------------- + -- Flat cocotb output view + ---------------------------------------------------------------------------- + mAxisView : process (mAxisMaster) is + begin + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisTDest <= mAxisMaster.tDest(7 downto 0); + mAxisSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + end process mAxisView; + + ---------------------------------------------------------------------------- + -- DUT hookup + ---------------------------------------------------------------------------- + U_DUT : entity surf.EthMacPrepareForICrc + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + PIPE_STAGES_G => PIPE_STAGES_G) + port map ( + ethClk => ethClk, + ethRst => ethRst, + sAxisMaster => sAxisMaster, + sAxisSlave => sAxisSlave, + mAxisMaster => mAxisMaster, + mAxisSlave => mAxisSlave); + +end architecture rtl; diff --git a/ethernet/RoCEv2/wrappers/EthMacRxCheckICrcWrapper.vhd b/ethernet/RoCEv2/wrappers/EthMacRxCheckICrcWrapper.vhd new file mode 100644 index 0000000000..abae121bd9 --- /dev/null +++ b/ethernet/RoCEv2/wrappers/EthMacRxCheckICrcWrapper.vhd @@ -0,0 +1,141 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for EthMacRxCheckICrc +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity EthMacRxCheckICrcWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false); + port ( + ethClk : in sl; + ethRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTDest : in slv(7 downto 0); + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + sCrcTValid : in sl; + sCrcTData : in slv(31 downto 0); + sCrcTReady : out sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTDest : out slv(7 downto 0); + mAxisTReady : in sl; + mAxisSof : out sl; + mAxisFrag : out sl; + mAxisEofe : out sl; + mAxisCrcError : out sl); +end entity EthMacRxCheckICrcWrapper; + +architecture rtl of EthMacRxCheckICrcWrapper is + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal sCrcMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sCrcSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + ---------------------------------------------------------------------------- + -- Flat cocotb input shims + ---------------------------------------------------------------------------- + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTDest, sAxisTKeep, sAxisTLast, sAxisTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(127 downto 0) := sAxisTData; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + v.tDest(7 downto 0) := sAxisTDest; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); + sAxisMaster <= v; + end process sAxisComb; + + sAxisTReady <= sAxisSlave.tReady; + + sCrcComb : process (sCrcTData, sCrcTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sCrcTValid; + v.tData(31 downto 0) := sCrcTData; + v.tKeep(3 downto 0) := x"F"; + v.tLast := '1'; + sCrcMaster <= v; + end process sCrcComb; + + sCrcTReady <= sCrcSlave.tReady; + + mAxisReadyComb : process (mAxisTReady) is + variable v : AxiStreamSlaveType; + begin + v := AXI_STREAM_SLAVE_INIT_C; + v.tReady := mAxisTReady; + mAxisSlave <= v; + end process mAxisReadyComb; + + ---------------------------------------------------------------------------- + -- Flat cocotb output view + ---------------------------------------------------------------------------- + mAxisView : process (mAxisMaster) is + begin + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisTDest <= mAxisMaster.tDest(7 downto 0); + mAxisSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + mAxisCrcError <= mAxisMaster.tUser(2); + end process mAxisView; + + ---------------------------------------------------------------------------- + -- DUT hookup + ---------------------------------------------------------------------------- + U_DUT : entity surf.EthMacRxCheckICrc + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G) + port map ( + ethClk => ethClk, + ethRst => ethRst, + sAxisMaster => sAxisMaster, + sAxisSlave => sAxisSlave, + sAxisCrcCheckMaster => sCrcMaster, + sAxisCrcCheckSlave => sCrcSlave, + mAxisMaster => mAxisMaster, + mAxisSlave => mAxisSlave); + +end architecture rtl; diff --git a/tests/ethernet/RoCEv2/__init__.py b/tests/ethernet/RoCEv2/__init__.py new file mode 100644 index 0000000000..b0085f1a17 --- /dev/null +++ b/tests/ethernet/RoCEv2/__init__.py @@ -0,0 +1,9 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## diff --git a/tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py b/tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py new file mode 100644 index 0000000000..6dbf9e6703 --- /dev/null +++ b/tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py @@ -0,0 +1,149 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Cover the VHDL-only `EthMacPrepareForICrc` leaf with one multi-beat +# frame that exercises each beat-local rewrite stage and one follow-on frame +# that proves the internal beat counter resets on `TLAST`. +# - Stimulus: Drive flattened EMAC beats through a thin checked-in wrapper, +# using realistic SOF/FRAG/EOFE sideband bits and handshake-driven frame +# transfer rather than fixed delays. +# - Checks: The first frame must mask the MAC, IP, UDP, and BTH fields exactly +# as the RTL specifies on beats 0, 1, and 2 while preserving the remaining +# payload bytes and sideband signals. The second frame must re-enter the +# beat-0 rewrite pattern instead of continuing the previous frame count. +# - Timing: The bench waits on visible stream handshakes and whole-frame +# capture because the leaf is a registered single-stage transformer. + +from __future__ import annotations + +from dataclasses import replace + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + ETHMAC_RTL_SOURCES, + EmacBeat, + assert_beat_list, + frame_beats_from_bytes, + keep_mask, + pack_bytes, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, +) + + +WRAPPER_PATH = "ethernet/RoCEv2/wrappers/EthMacPrepareForICrcWrapper.vhd" +DUT_PATH = "ethernet/RoCEv2/rtl/EthMacPrepareForICrc.vhd" + + +def expected_prepare_beats(beats: list[EmacBeat]) -> list[EmacBeat]: + expected = [] + beat_index = 0 + + for beat in beats: + lanes = bytearray((beat.data >> (8 * lane)) & 0xFF for lane in range(16)) + keep = beat.keep + + if beat_index == 0: + version_ihl = lanes[14] + lanes[0:8] = b"\xFF" * 8 + lanes[8] = version_ihl + lanes[9] = 0xFF + lanes[10:16] = b"\x00" * 6 + keep = keep_mask(10) + elif beat_index == 1: + lanes[6] = 0xFF + lanes[8] = 0xFF + lanes[9] = 0xFF + elif beat_index == 2: + lanes[8] = 0xFF + lanes[9] = 0xFF + lanes[14] = 0xFF + + expected.append( + replace( + beat, + data=pack_bytes(bytes(lanes), lane_bytes=16), + keep=keep, + ) + ) + + if beat.last == 1: + beat_index = 0 + elif beat_index != 3: + beat_index += 1 + + return expected + + +@cocotb.test() +async def eth_mac_prepare_for_icrc_masks_selected_header_fields_test(dut): + bench = await setup_flat_emac_testbench( + dut, + source_prefix="sAxis", + sink_prefix="mAxis", + initial_values={"mAxisTReady": 0}, + ) + source = bench.source + sink = bench.sink + assert source is not None + assert sink is not None + + # Start with a three-beat frame so the bench sees every rewrite stage that + # the leaf applies before the counter saturates. + first_frame = frame_beats_from_bytes( + bytes(range(48)), + dest=0x23, + frag=1, + eofe=1, + ) + first_send = cocotb.start_soon(send_contiguous_frame(source, first_frame, clk=bench.clk)) + first_observed = await recv_frame( + sink, + clk=bench.clk, + ready_signal=dut.mAxisTReady, + timeout_cycles=128, + ) + await first_send + + assert_beat_list(first_observed, expected_prepare_beats(first_frame)) + + # Follow with a fresh two-beat frame to prove the internal beat counter + # resets on `TLAST` instead of carrying the previous frame's state. + second_frame = frame_beats_from_bytes( + bytes(range(0x40, 0x54)), + dest=0x7A, + eofe=1, + ) + second_send = cocotb.start_soon(send_contiguous_frame(source, second_frame, clk=bench.clk)) + second_observed = await recv_frame( + sink, + clk=bench.clk, + ready_signal=dut.mAxisTReady, + timeout_cycles=64, + ) + await second_send + + assert_beat_list(second_observed, expected_prepare_beats(second_frame)) + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="eth_mac_prepare_for_icrc_wrapper")]) +def test_EthMacPrepareForICrc(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ethmacprepareforicrcwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES + [DUT_PATH, WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py b/tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py new file mode 100644 index 0000000000..1565b8c61f --- /dev/null +++ b/tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py @@ -0,0 +1,153 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Cover the VHDL-only `EthMacRxCheckICrc` leaf with one zero-CRC frame +# and one non-zero-CRC frame so the bench proves both the good and bad frame +# markers plus frame-to-frame CRC-state reset. +# - Stimulus: Drive flattened EMAC beats on the main stream and a single-beat +# CRC word on the side stream through a thin checked-in wrapper, keeping the +# CRC payload stable after the one accepted CRC handshake so later beats see +# the same sampled result. +# - Checks: The main stream must pass through unchanged, the CRC side stream +# must only be consumed once per frame, zero CRC must clear the exported +# error flag on every beat, non-zero CRC must assert the exported error flag +# on every beat, and a second frame must accept a fresh CRC word after the +# previous frame's `TLAST`. +# - Timing: The bench waits on visible ready/valid handshakes and whole-frame +# capture because the leaf is a registered stream joiner with one CRC sample +# per frame. + +from __future__ import annotations + +import cocotb +import pytest +from cocotb.triggers import RisingEdge, Timer + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.EthMacCore.ethmac_test_utils import ( + ETHMAC_RTL_SOURCES, + assert_beat_list, + frame_beats_from_bytes, + recv_frame, + send_contiguous_frame, + setup_flat_emac_testbench, + wait_signal_pulse, +) + + +WRAPPER_PATH = "ethernet/RoCEv2/wrappers/EthMacRxCheckICrcWrapper.vhd" +DUT_PATH = "ethernet/RoCEv2/rtl/EthMacRxCheckICrc.vhd" + + +async def send_crc_word(dut, *, data: int, clk) -> None: + dut.sCrcTData.value = data + dut.sCrcTValid.value = 1 + + while True: + await RisingEdge(clk) + await Timer(1, unit="ns") + if int(dut.sCrcTReady.value) == 1: + dut.sCrcTValid.value = 0 + return + + +async def capture_crc_errors(dut, *, clk, timeout_cycles: int = 64) -> list[int]: + errors = [] + + for _ in range(timeout_cycles): + await RisingEdge(clk) + await Timer(1, unit="ns") + if int(dut.mAxisTValid.value) == 1 and int(dut.mAxisTReady.value) == 1: + errors.append(int(dut.mAxisCrcError.value)) + if int(dut.mAxisTLast.value) == 1: + return errors + + raise AssertionError("Timed out waiting for end of checked EMAC frame") + + +@cocotb.test() +async def eth_mac_rx_check_icrc_flags_good_and_bad_frames_test(dut): + bench = await setup_flat_emac_testbench( + dut, + source_prefix="sAxis", + sink_prefix="mAxis", + initial_values={ + "mAxisTReady": 0, + "sCrcTValid": 0, + "sCrcTData": 0, + }, + ) + source = bench.source + sink = bench.sink + assert source is not None + assert sink is not None + + # First prove the good-frame path: the CRC sideband should be consumed + # once, the payload should pass through untouched, and the exported error + # marker must stay clear for the whole frame. + good_frame = frame_beats_from_bytes( + bytes(range(0x20)), + dest=0x11, + frag=1, + eofe=1, + ) + good_crc_send = cocotb.start_soon(send_crc_word(dut, data=0x00000000, clk=bench.clk)) + good_frame_send = cocotb.start_soon(send_contiguous_frame(source, good_frame, clk=bench.clk)) + good_error_task = cocotb.start_soon(capture_crc_errors(dut, clk=bench.clk, timeout_cycles=128)) + await wait_signal_pulse(dut.sCrcTReady, clk=bench.clk, timeout_cycles=64) + good_observed = await recv_frame( + sink, + clk=bench.clk, + ready_signal=dut.mAxisTReady, + timeout_cycles=128, + ) + good_errors = await good_error_task + await good_crc_send + await good_frame_send + + assert_beat_list(good_observed, good_frame) + assert good_errors == [0] * len(good_observed) + + # Then send a second frame with a non-zero CRC word. This proves both the + # bad-frame marker and the fact that `TLAST` resets the one-CRC-per-frame + # internal state so the leaf accepts a fresh CRC word on the next frame. + bad_frame = frame_beats_from_bytes( + bytes(range(0x40, 0x60)), + dest=0x41, + eofe=1, + ) + bad_crc_send = cocotb.start_soon(send_crc_word(dut, data=0xDEADBEEF, clk=bench.clk)) + bad_frame_send = cocotb.start_soon(send_contiguous_frame(source, bad_frame, clk=bench.clk)) + bad_error_task = cocotb.start_soon(capture_crc_errors(dut, clk=bench.clk, timeout_cycles=128)) + await wait_signal_pulse(dut.sCrcTReady, clk=bench.clk, timeout_cycles=64) + bad_observed = await recv_frame( + sink, + clk=bench.clk, + ready_signal=dut.mAxisTReady, + timeout_cycles=128, + ) + bad_errors = await bad_error_task + await bad_crc_send + await bad_frame_send + + assert_beat_list(bad_observed, bad_frame) + assert bad_errors == [1] * len(bad_observed) + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="eth_mac_rx_check_icrc_wrapper")]) +def test_EthMacRxCheckICrc(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ethmacrxcheckicrcwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ETHMAC_RTL_SOURCES + [DUT_PATH, WRAPPER_PATH]}, + ) From 50101f6d1a19264259837be7890cfa592a5d7723 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 20 Apr 2026 09:53:27 -0700 Subject: [PATCH 24/92] More RoCEv2 coverage. --- docs/_meta/rtl_regression_handoff.md | 11 +- docs/_meta/rtl_regression_progress.md | 13 +- .../RoCEv2/wrappers/EthMacRxRoCEv2Wrapper.vhd | 104 +++++++++++ .../RoCEv2/wrappers/EthMacTxRoCEv2Wrapper.vhd | 115 ++++++++++++ .../wrappers/RoceConfiguratorWrapper.vhd | 152 ++++++++++++++++ .../RoceResizeAndSwapIpIntegrator.vhd | 169 ++++++++++++++++++ tests/ethernet/RoCEv2/roce_test_utils.py | 104 +++++++++++ .../ethernet/RoCEv2/test_RoceConfigurator.py | 137 ++++++++++++++ .../ethernet/RoCEv2/test_RoceResizeAndSwap.py | 168 +++++++++++++++++ 9 files changed, 965 insertions(+), 8 deletions(-) create mode 100644 ethernet/RoCEv2/wrappers/EthMacRxRoCEv2Wrapper.vhd create mode 100644 ethernet/RoCEv2/wrappers/EthMacTxRoCEv2Wrapper.vhd create mode 100644 ethernet/RoCEv2/wrappers/RoceConfiguratorWrapper.vhd create mode 100644 ethernet/RoCEv2/wrappers/RoceResizeAndSwapIpIntegrator.vhd create mode 100644 tests/ethernet/RoCEv2/roce_test_utils.py create mode 100644 tests/ethernet/RoCEv2/test_RoceConfigurator.py create mode 100644 tests/ethernet/RoCEv2/test_RoceResizeAndSwap.py diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index df3332a434..50da460dc1 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -19,10 +19,10 @@ - Treat stale simulator cleanup as part of task completion: after any `pytest`, cocotb, GHDL, or similar launched verification step, sweep for leftover child processes and kill them before moving on ## Quick Resume Snapshot -- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, and the current Ethernet coverage now spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the first `RoCEv2` VHDL-only helper pair, including the recent thin-area cleanup across direct bypass leaves, broader top-level UDP/IPv4 paths, and deeper ICMP negatives. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. +- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, and the current Ethernet coverage now spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the pure-VHDL RoCEv2 quartet (`EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator`). The remaining RoCEv2 requirement is still one cocotb test module per entity in `ethernet/RoCEv2/rtl`, but the last five entities depend on real `blue-*` submodules and therefore need a mixed-language simulator path rather than local stand-ins. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. - Current axi frontier: complete for the intended simulator-friendly pass in this branch snapshot; do not resume from the older stale `AxiResize` note. - Current validated-open issues: - - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core` remain untouched in phase 1, while `RoCEv2` is only partially covered through the VHDL-only `EthMacPrepareForICrc` and `EthMacRxCheckICrc` leaves. + - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core` remain untouched in phase 1, while the remaining RoCEv2 gap is the mixed-language bench path for the five RTL entities that instantiate generated submodules: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`. - `EthMacRxImportXlgmii` and `EthMacTxExportXlgmii` are still placeholder no-op RTL; the checked-in tests now lock down that inert contract instead of claiming functional XLGMII support. - Current planning discipline: - Use manual user-directed area selection as the active source of truth for what to work on next. @@ -56,7 +56,10 @@ - `tests/dsp/generic/dsp_test_utils.py` is now the shared home for DSP-specific signed helpers, rolling reference models, cocotb clock-settle timing, and generated FIR wrappers. Reuse it instead of cloning DSP arithmetic or wrapper boilerplate. - Before writing new AXI-Lite, AXI Stream, SSI, or ethernet transaction code, search the nearest subsystem `tests/` package for an existing helper module first. Future sessions should assume that a reusable helper probably already exists and should only write new transaction plumbing after confirming the local helper layer is insufficient. - `tests/ethernet/EthMacCore/ethmac_test_utils.py` is now the shared home for the current Ethernet MAC slice: flat EMAC beat helpers, Ethernet/IPv4/UDP packet builders, checksum reference code, MAC-config byte-order helpers, and minimum-frame padding helpers. Reuse it instead of cloning packet or sideband plumbing across `EthMacCore` benches. -- `ethernet/RoCEv2/rtl/EthMacTxRoCEv2.vhd` and `EthMacRxRoCEv2.vhd` are not the practical first phase-1 targets under the current GHDL flow because they pull in the Bluespec-generated CRC/RDMA Verilog path. Start the RoCEv2 slice from the stable VHDL-only helper leaves (`EthMacPrepareForICrc` and `EthMacRxCheckICrc`) and treat the mixed-language wrappers as an explicit follow-on. +- Do not replace `ethernet/RoCEv2/blue-*` with local test doubles when the target boundary is `ethernet/RoCEv2/rtl`. The intended shape is one cocotb bench per RTL entity in `ethernet/RoCEv2/rtl`, with `blue-crc`, `blue-rdma`, and `blue-lib` used as real transitive dependencies where instantiated. Under the current local toolchain only `ghdl` is available, so the pure-VHDL quartet is covered now and the remaining five mixed-language entities stay open until the runner supports real VHDL+Verilog simulation. +- RoCEv2 RTL entity matrix for the next session: + - Covered now with the current GHDL-only flow: `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, `RoceConfigurator` + - Still required, but must use real generated dependencies: `EthMacCrcAxiStreamWrapperSend` -> `blue-crc/mkCrcRawAxiStreamCustomSend.v`, `EthMacCrcAxiStreamWrapperRecv` -> `blue-crc/mkCrcRawAxiStreamCustomRecv.v`, `EthMacTxRoCEv2` -> send CRC wrapper, `EthMacRxRoCEv2` -> recv CRC wrapper, `RoceEngineWrapper` -> `blue-rdma/mkAxisTransportLayer.v` plus `blue-lib/` - `tests/ethernet/RawEthFramer/raw_eth_test_utils.py` now holds the shared raw-Ethernet helper pieces: flat app-side beat helpers, raw-Ethernet header/frame builders, and lookup-handshake utilities reused by the `RawEthFramer`, `RawEthFramerRx`, and `RawEthFramerTx` benches. - `tests/ethernet/UdpEngine/udp_test_utils.py` is now the shared home for the UDP slice: legacy-address constants, pseudo-frame builders, DHCP option helpers, and the common cocotb bench setup for the `ArpIpTable`, `UdpEngine*`, and `UdpEngineWrapper*` wrappers. Reuse it instead of rebuilding IPv4/UDP helper glue in each test module. - `tests/ethernet/IpV4Engine/ipv4_test_utils.py` is now the shared home for the IPv4 slice: packet/header builders and common cocotb bench setup for the `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, and `IpV4Engine*` wrappers. Reuse it instead of cloning IPv4 framing helpers across that directory. @@ -160,7 +163,7 @@ One small RTL fix landed during that validation pass because the new `AxiStreamD A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instantiation_graph.md` and `docs/_meta/rtl_instantiation_graph.json`, and the same generator now also emits a path-qualified bottom-up phase-1 queue at `docs/_meta/rtl_phase1_queue.md` and `docs/_meta/rtl_phase1_queue.json`. Keep the graph and queue for provenance, but treat them as historical context rather than as the default source of truth for what to implement next. ## Immediate Next Task -If the user keeps the focus on `ethernet/RoCEv2`, decide whether to stay in the current phase-1 lane and add more VHDL-only helper coverage or to invest in mixed-language support for the top-level TX/RX wrappers and `RoceEngineWrapper`. In either case, keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the real validated subset instead of over-claiming full-family RoCEv2 coverage. +If the user keeps the focus on `ethernet/RoCEv2`, the next real step is enabling a mixed-language cocotb path for the five remaining RTL entities listed above. Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the real validated subset, and do not reintroduce local stand-ins for `blue-*`. ## Read Order 1. `docs/_meta/rtl_regression_handoff.md` diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index a9857d7398..b5ed66ea17 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -3,21 +3,24 @@ ## Summary - Current phase: Phase-1 implementation active - Current subsystem: manual user-directed rollout tracking -- Current focus module: the first `ethernet/RoCEv2` phase-1 leaf slice is now validated through the stable VHDL-only helpers, with the larger mixed-language wrapper assemblies still open. +- Current focus module: keep the RoCEv2 boundary aligned to `ethernet/RoCEv2/rtl`: the current validated subset is the pure-VHDL quartet (`EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator`), while the remaining five RTL entities need real mixed-language simulation because they instantiate `blue-*` modules underneath. - Last updated: 2026-04-20 ## Current Frontier Snapshot - Active planning rule: take the next work item from the user's manual direction, not from `docs/_meta/rtl_phase1_queue.{md,json}`. - Manual planning note: - The axi-first pass is complete through the previously remaining final 11 `axi/` modules. - - The current `verification-2` branch already includes the merged `pre-release` state through PR #1392, so the validated `protocols/ssi`, `protocols/pgp`, and current Ethernet waves (`EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the first `RoCEv2` VHDL-only leaf pair) are all part of the present branch snapshot. + - The current `verification-2` branch already includes the merged `pre-release` state through PR #1392, so the validated `protocols/ssi`, `protocols/pgp`, and current Ethernet waves (`EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the current pure-VHDL RoCEv2 quartet) are all part of the present branch snapshot. - The checked-in queue and override artifacts are now retained only as historical provenance and optional graph output; they are no longer the source of truth for choosing the next area. - Keep the done/open frontier in this progress file and in `docs/_meta/rtl_regression_handoff.md` aligned to the actual tree even if the queue artifacts are stale. - Treat stale simulator cleanup as mandatory after every launched verification command: after any `pytest`, cocotb, GHDL, or similar simulation step, sweep for leftover child processes and kill them before starting the next task. - Known expected-open tests on this branch: - No simulator-friendly expected-open leaf tests remain in the currently covered `ethernet/IpV4Engine` slice, and the recent `EthMacCore` / `UdpEngine` thin-area follow-up is also checked in on this branch. - The current `EthMac*Xlgmii` import/export leaves are still placeholder no-op RTL, so the checked-in benches document that inert contract rather than claiming functional XLGMII datapath coverage. - - The remaining Ethernet work is in the larger untouched families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core`, plus the still-open mixed-language `RoCEv2` wrapper/integration path beyond the newly covered VHDL-only helper leaves. + - The remaining Ethernet work is in the larger untouched families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core`, plus the five still-open RoCEv2 RTL entities that depend on generated submodules: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`. +- RoCEv2 RTL target matrix: + - Covered now under the current GHDL-only flow: `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, `RoceConfigurator` + - Still required, but need real `blue-*` dependencies under a mixed-language simulator: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, `RoceEngineWrapper` - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. @@ -31,7 +34,7 @@ | `dsp` | started | not started | started | The planned `dsp/generic/fixed` leaf batch is now validated under `tests/dsp/generic/`: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. Shared DSP helpers now live in `tests/dsp/generic/dsp_test_utils.py`, and the legacy VHDL benches under `dsp/generic/tb/` were treated as behavioral reference material rather than as execution constraints. | | `axi` | started | not started | started | The axi-first pass is now complete for the simulator-friendly queue. The final locally validated batch adds `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`, with a combined `11 passed` validation run on 2026-03-27. Added checked-in subsystem wrappers under `axi/axi4/ip_integrator/`, `axi/axi-lite/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/` for those benches. `AxiStreamFifoV2` now has an expanded `10 passed` wrapper regression under `tests/axi/axi_stream/` covering async and sync width conversion, metadata truncation, `VALID_THOLD` frame-ready and burst-release modes, dynamic pause-threshold behavior, `CASCADE_SIZE=2`, and the `S_HAS_TREADY=0` pause-only source-side path. `AxiResize` now passes its equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` wrapper regression on this branch after the read-hold RTL fix. `AxiLiteAsync`, `AxiLiteToDrp`, and `AxiRateGen` still keep intentionally narrow common-clock subsets while the more timing-sensitive async AXI-Lite crossing branches remain open. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` still keep intentionally narrow first-pass subsets. `AxiStreamDmaV2Read` is now validated with a two-case wrapper regression covering both aligned and short terminal-beat reads after fixing bounded byte-count conversion in `AxiPkg` and terminal-mask generation in `AxiStreamDmaV2Read`. | | `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. | -| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers both the original leaf slice and the deeper assembly benches for `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`, plus direct `EthMacRxBypass` / `EthMacTxBypass` leaf benches and import/export sweeps that now explicitly include the current placeholder `XLGMII` contract. `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, including the successful multi-beat `RawEthFramerTx` unicast-forwarding path after lookup resolution. `tests/ethernet/UdpEngine/` covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, with the top/wrapper benches now widened across client/server routing paths. `tests/ethernet/IpV4Engine/` covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, and the top/leaf benches now also include protocol-TX and deeper ICMP reject/recovery coverage. `tests/ethernet/RoCEv2/` now covers the VHDL-only helper leaves `EthMacPrepareForICrc` and `EthMacRxCheckICrc` through checked-in wrappers under `ethernet/RoCEv2/wrappers/`. The explicit Ethernet caveats are now the larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core`, the still-open mixed-language `RoCEv2` assembly path (`EthMacTxRoCEv2`, `EthMacRxRoCEv2`, the CRC wrapper leaves, and `RoceEngineWrapper`), plus the still-placeholder `EthMac*Xlgmii` RTL. | +| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers both the original leaf slice and the deeper assembly benches for `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`, plus direct `EthMacRxBypass` / `EthMacTxBypass` leaf benches and import/export sweeps that now explicitly include the current placeholder `XLGMII` contract. `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, including the successful multi-beat `RawEthFramerTx` unicast-forwarding path after lookup resolution. `tests/ethernet/UdpEngine/` covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, with the top/wrapper benches now widened across client/server routing paths. `tests/ethernet/IpV4Engine/` covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, and the top/leaf benches now also include protocol-TX and deeper ICMP reject/recovery coverage. `tests/ethernet/RoCEv2/` currently covers the pure-VHDL RTL entities `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator` through checked-in wrappers under `ethernet/RoCEv2/wrappers/`. The remaining RoCEv2 RTL entities that still need cocotb benches are `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`, and those should use the real generated `blue-*` dependencies rather than local stand-ins. The explicit Ethernet caveats are now the larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core`, the mixed-language RoCEv2 bench gap listed above, plus the still-placeholder `EthMac*Xlgmii` RTL. | | `devices` | not started | not started | not started | Many vendor-heavy cases | | `xilinx` | not started | not started | not started | Many vendor-heavy cases | @@ -311,3 +314,5 @@ - 2026-03-27: The new `AxiStreamDmaRingWrite` regression exposed a width-safety issue in the DUT pointer update under GHDL. Fixed `axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd` so `dmaAck.size` is sliced back to the local pointer width before incrementing `nextAddr`, which keeps the logic behavior unchanged for narrower address maps while making the testbench-safe wrapper configuration simulate cleanly. - 2026-03-26: Implemented and validated the next 10 generated-queue AXI modules after the two known expected-open skips (`AxiResize` and `AxiStreamDmaV2Read`): `AxiStreamScatterGather`, `AxiMemTester`, `AxiStreamDmaV2Desc`, `AxiStreamDmaV2Fifo`, `AxiReadPathFifo`, `AxiWritePathFifo`, `AxiStreamDmaV2`, `AxiStreamBatchingFifo`, `AxiStreamMon`, and `AxiStreamRingBuffer`. Added the required new wrapper files under `axi/axi4/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/`, fixed `tests/common/regression_utils.py` to stringify simulator env values before dispatch, and validated the combined batch with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamScatterGather.py tests/axi/axi4/test_AxiMemTester.py tests/axi/dma/test_AxiStreamDmaV2Desc.py tests/axi/dma/test_AxiStreamDmaV2Fifo.py tests/axi/axi4/test_AxiReadPathFifo.py tests/axi/axi4/test_AxiWritePathFifo.py tests/axi/dma/test_AxiStreamDmaV2.py tests/axi/axi_stream/test_AxiStreamBatchingFifo.py tests/axi/axi_stream/test_AxiStreamMon.py tests/axi/axi_stream/test_AxiStreamRingBuffer.py` (`10 passed`). - 2026-04-20: Started the first `ethernet/RoCEv2` phase-1 slice with the stable VHDL-only helper leaves instead of the mixed-language top wrappers. Added `ethernet/RoCEv2/wrappers/EthMacPrepareForICrcWrapper.vhd` and `ethernet/RoCEv2/wrappers/EthMacRxCheckICrcWrapper.vhd`, implemented `tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py` and `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, linted both wrappers cleanly with `./.venv/bin/vsg -c vsg-linter.yml -f ...`, validated the pair with `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py` (`2 passed`), and recorded the remaining open RoCEv2 work as the mixed-language wrapper/assembly path rather than claiming full-family coverage. +- 2026-04-20: Added the pure-VHDL RoCEv2 follow-on benches `tests/ethernet/RoCEv2/test_RoceResizeAndSwap.py` and `test_RoceConfigurator.py` plus their checked-in wrappers `ethernet/RoCEv2/wrappers/RoceResizeAndSwapIpIntegrator.vhd` and `RoceConfiguratorWrapper.vhd`, and validated the pure-VHDL RoCEv2 bench set with `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py tests/ethernet/RoCEv2/test_RoceResizeAndSwap.py tests/ethernet/RoCEv2/test_RoceConfigurator.py` (`4 passed`). +- 2026-04-20: Removed the temporary local CRC stand-ins and the stub-backed `EthMacTxRoCEv2` / `EthMacRxRoCEv2` benches after clarifying the intended boundary: there should be one cocotb test module per entity in `ethernet/RoCEv2/rtl`, but `blue-*` must remain real transitive dependencies rather than being replaced with local test doubles. The current open RoCEv2 bench set is therefore `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`, all of which now require a mixed-language simulation path. diff --git a/ethernet/RoCEv2/wrappers/EthMacRxRoCEv2Wrapper.vhd b/ethernet/RoCEv2/wrappers/EthMacRxRoCEv2Wrapper.vhd new file mode 100644 index 0000000000..45d42e3839 --- /dev/null +++ b/ethernet/RoCEv2/wrappers/EthMacRxRoCEv2Wrapper.vhd @@ -0,0 +1,104 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for EthMacRxRoCEv2 +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity EthMacRxRoCEv2Wrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'); + port ( + ethClk : in sl; + ethRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTDest : in slv(7 downto 0); + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTDest : out slv(7 downto 0); + mAxisSof : out sl; + mAxisFrag : out sl; + mAxisEofe : out sl); +end entity EthMacRxRoCEv2Wrapper; + +architecture rtl of EthMacRxRoCEv2Wrapper is + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + +begin + + ---------------------------------------------------------------------------- + -- Flat cocotb input shim + ---------------------------------------------------------------------------- + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTDest, sAxisTKeep, sAxisTLast, sAxisTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(127 downto 0) := sAxisTData; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + v.tDest(7 downto 0) := sAxisTDest; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); + sAxisMaster <= v; + end process sAxisComb; + + sAxisTReady <= '1'; + + ---------------------------------------------------------------------------- + -- Flat cocotb output view + ---------------------------------------------------------------------------- + mAxisView : process (mAxisMaster) is + begin + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisTDest <= mAxisMaster.tDest(7 downto 0); + mAxisSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + end process mAxisView; + + ---------------------------------------------------------------------------- + -- DUT hookup + ---------------------------------------------------------------------------- + U_DUT : entity surf.EthMacRxRoCEv2 + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G) + port map ( + ethClk => ethClk, + ethRst => ethRst, + obCsumMaster => sAxisMaster, + ibBypassMaster => mAxisMaster); + +end architecture rtl; diff --git a/ethernet/RoCEv2/wrappers/EthMacTxRoCEv2Wrapper.vhd b/ethernet/RoCEv2/wrappers/EthMacTxRoCEv2Wrapper.vhd new file mode 100644 index 0000000000..3be75ea7b7 --- /dev/null +++ b/ethernet/RoCEv2/wrappers/EthMacTxRoCEv2Wrapper.vhd @@ -0,0 +1,115 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for EthMacTxRoCEv2 +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.EthMacPkg.all; + +entity EthMacTxRoCEv2Wrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'); + port ( + ethClk : in sl; + ethRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTDest : in slv(7 downto 0); + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTReady : in sl; + mAxisSof : out sl; + mAxisFrag : out sl; + mAxisEofe : out sl); +end entity EthMacTxRoCEv2Wrapper; + +architecture rtl of EthMacTxRoCEv2Wrapper is + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + ---------------------------------------------------------------------------- + -- Flat cocotb input shim + ---------------------------------------------------------------------------- + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTDest, sAxisTKeep, sAxisTLast, sAxisTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(127 downto 0) := sAxisTData; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + v.tDest(7 downto 0) := sAxisTDest; + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); + axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); + sAxisMaster <= v; + end process sAxisComb; + + sAxisTReady <= sAxisSlave.tReady; + + mAxisReadyComb : process (mAxisTReady) is + variable v : AxiStreamSlaveType; + begin + v := AXI_STREAM_SLAVE_INIT_C; + v.tReady := mAxisTReady; + mAxisSlave <= v; + end process mAxisReadyComb; + + ---------------------------------------------------------------------------- + -- Flat cocotb output view + ---------------------------------------------------------------------------- + mAxisView : process (mAxisMaster) is + begin + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + end process mAxisView; + + ---------------------------------------------------------------------------- + -- DUT hookup + ---------------------------------------------------------------------------- + U_DUT : entity surf.EthMacTxRoCEv2 + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G) + port map ( + ethClk => ethClk, + ethRst => ethRst, + obCsumMaster => sAxisMaster, + obCsumSlave => sAxisSlave, + ibPauseMaster => mAxisMaster, + ibPauseSlave => mAxisSlave); + +end architecture rtl; diff --git a/ethernet/RoCEv2/wrappers/RoceConfiguratorWrapper.vhd b/ethernet/RoCEv2/wrappers/RoceConfiguratorWrapper.vhd new file mode 100644 index 0000000000..2f6675472d --- /dev/null +++ b/ethernet/RoCEv2/wrappers/RoceConfiguratorWrapper.vhd @@ -0,0 +1,152 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for RoceConfigurator +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; +use surf.AxiStreamPkg.all; + +entity RoceConfiguratorWrapper is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false); + port ( + clk : in sl; + rst : in sl; + M_META_REQ_TVALID : out sl; + M_META_REQ_TDATA : out slv(302 downto 0); + M_META_REQ_TREADY : in sl; + S_META_RESP_TVALID : in sl; + S_META_RESP_TDATA : in slv(275 downto 0); + S_META_RESP_TREADY : out sl; + S_AXIL_AWADDR : in slv(31 downto 0); + S_AXIL_AWPROT : in slv(2 downto 0); + S_AXIL_AWVALID : in sl; + S_AXIL_AWREADY : out sl; + S_AXIL_WDATA : in slv(31 downto 0); + S_AXIL_WSTRB : in slv(3 downto 0); + S_AXIL_WVALID : in sl; + S_AXIL_WREADY : out sl; + S_AXIL_BRESP : out slv(1 downto 0); + S_AXIL_BVALID : out sl; + S_AXIL_BREADY : in sl; + S_AXIL_ARADDR : in slv(31 downto 0); + S_AXIL_ARPROT : in slv(2 downto 0); + S_AXIL_ARVALID : in sl; + S_AXIL_ARREADY : out sl; + S_AXIL_RDATA : out slv(31 downto 0); + S_AXIL_RRESP : out slv(1 downto 0); + S_AXIL_RVALID : out sl; + S_AXIL_RREADY : in sl); +end entity RoceConfiguratorWrapper; + +architecture rtl of RoceConfiguratorWrapper is + + signal axilClk : sl; + signal axilRst : sl; + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + signal mMetaReqMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mMetaReqSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal sMetaRespMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sMetaRespSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + ---------------------------------------------------------------------------- + -- AXI-Lite shim + ---------------------------------------------------------------------------- + U_ShimLayer : entity surf.SlaveAxiLiteIpIntegrator + generic map ( + EN_ERROR_RESP => true, + FREQ_HZ => 125000000, + ADDR_WIDTH => 32) + port map ( + S_AXI_ACLK => clk, + S_AXI_ARESETN => not rst, + S_AXI_AWADDR => S_AXIL_AWADDR, + S_AXI_AWPROT => S_AXIL_AWPROT, + S_AXI_AWVALID => S_AXIL_AWVALID, + S_AXI_AWREADY => S_AXIL_AWREADY, + S_AXI_WDATA => S_AXIL_WDATA, + S_AXI_WSTRB => S_AXIL_WSTRB, + S_AXI_WVALID => S_AXIL_WVALID, + S_AXI_WREADY => S_AXIL_WREADY, + S_AXI_BRESP => S_AXIL_BRESP, + S_AXI_BVALID => S_AXIL_BVALID, + S_AXI_BREADY => S_AXIL_BREADY, + S_AXI_ARADDR => S_AXIL_ARADDR, + S_AXI_ARPROT => S_AXIL_ARPROT, + S_AXI_ARVALID => S_AXIL_ARVALID, + S_AXI_ARREADY => S_AXIL_ARREADY, + S_AXI_RDATA => S_AXIL_RDATA, + S_AXI_RRESP => S_AXIL_RRESP, + S_AXI_RVALID => S_AXIL_RVALID, + S_AXI_RREADY => S_AXIL_RREADY, + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + + ---------------------------------------------------------------------------- + -- Metadata stream views + ---------------------------------------------------------------------------- + mMetaReqView : process (mMetaReqMaster) is + begin + M_META_REQ_TVALID <= mMetaReqMaster.tValid; + M_META_REQ_TDATA <= mMetaReqMaster.tData(302 downto 0); + end process mMetaReqView; + + mMetaReqSlave.tReady <= M_META_REQ_TREADY; + + sMetaRespComb : process (S_META_RESP_TDATA, S_META_RESP_TVALID) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := S_META_RESP_TVALID; + v.tData(275 downto 0) := S_META_RESP_TDATA; + sMetaRespMaster <= v; + end process sMetaRespComb; + + S_META_RESP_TREADY <= sMetaRespSlave.tReady; + + ---------------------------------------------------------------------------- + -- DUT hookup + ---------------------------------------------------------------------------- + U_DUT : entity surf.RoceConfigurator + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G) + port map ( + clk => clk, + rst => rst, + mAxisMetaDataReqMaster => mMetaReqMaster, + mAxisMetaDataReqSlave => mMetaReqSlave, + sAxisMetaDataRespMaster => sMetaRespMaster, + sAxisMetaDataRespSlave => sMetaRespSlave, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + +end architecture rtl; diff --git a/ethernet/RoCEv2/wrappers/RoceResizeAndSwapIpIntegrator.vhd b/ethernet/RoCEv2/wrappers/RoceResizeAndSwapIpIntegrator.vhd new file mode 100644 index 0000000000..a6863b435f --- /dev/null +++ b/ethernet/RoCEv2/wrappers/RoceResizeAndSwapIpIntegrator.vhd @@ -0,0 +1,169 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: IP integrator wrapper for surf.RoceResizeAndSwap +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; + +entity RoceResizeAndSwapIpIntegrator is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + READY_EN_G : boolean := true; + PIPE_STAGES_G : natural := 0; + SIDE_BAND_WIDTH_G : positive := 1; + SWAP_ENDIAN_G : boolean := false; + LITTLE_ENDIAN_G : boolean := true; + SLAVE_DATA_BYTES_G : positive := 16; + MASTER_DATA_BYTES_G : positive := 32); + port ( + axisClk : in sl; + axisRst : in sl; + S_AXIS_TVALID : in sl; + S_AXIS_TDATA : in slv(SLAVE_DATA_BYTES_G*8-1 downto 0); + S_AXIS_TKEEP : in slv(SLAVE_DATA_BYTES_G-1 downto 0); + S_AXIS_TLAST : in sl; + S_AXIS_TDEST : in slv(7 downto 0); + S_AXIS_TID : in slv(7 downto 0); + S_AXIS_TREADY : out sl; + S_SIDE_BAND : in slv(SIDE_BAND_WIDTH_G-1 downto 0); + M_AXIS_TVALID : out sl; + M_AXIS_TDATA : out slv(MASTER_DATA_BYTES_G*8-1 downto 0); + M_AXIS_TKEEP : out slv(MASTER_DATA_BYTES_G-1 downto 0); + M_AXIS_TLAST : out sl; + M_AXIS_TDEST : out slv(7 downto 0); + M_AXIS_TID : out slv(7 downto 0); + M_AXIS_TREADY : in sl; + M_SIDE_BAND : out slv(SIDE_BAND_WIDTH_G-1 downto 0)); +end entity RoceResizeAndSwapIpIntegrator; + +architecture rtl of RoceResizeAndSwapIpIntegrator is + + constant SLAVE_AXI_CONFIG_C : AxiStreamConfigType := ( + TSTRB_EN_C => false, + TDATA_BYTES_C => SLAVE_DATA_BYTES_G, + TDEST_BITS_C => 8, + TID_BITS_C => 8, + TKEEP_MODE_C => TKEEP_NORMAL_C, + TUSER_BITS_C => 1, + TUSER_MODE_C => TUSER_NORMAL_C); + + constant MASTER_AXI_CONFIG_C : AxiStreamConfigType := ( + TSTRB_EN_C => false, + TDATA_BYTES_C => MASTER_DATA_BYTES_G, + TDEST_BITS_C => 8, + TID_BITS_C => 8, + TKEEP_MODE_C => TKEEP_NORMAL_C, + TUSER_BITS_C => 1, + TUSER_MODE_C => TUSER_NORMAL_C); + + signal axisAResetN : sl := '1'; + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + axisAResetN <= not axisRst when (RST_POLARITY_G = '1') else axisRst; + + ---------------------------------------------------------------------------- + -- AXI Stream shims + ---------------------------------------------------------------------------- + U_ShimLayerSlave : entity surf.SlaveAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "S_AXIS", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 1, + TID_WIDTH => 8, + TDEST_WIDTH => 8, + TDATA_NUM_BYTES => SLAVE_DATA_BYTES_G) + port map ( + S_AXIS_ACLK => axisClk, + S_AXIS_ARESETN => axisAResetN, + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TSTRB => (others => '0'), + S_AXIS_TKEEP => S_AXIS_TKEEP, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TDEST => S_AXIS_TDEST, + S_AXIS_TID => S_AXIS_TID, + S_AXIS_TUSER => "0", + S_AXIS_TREADY => S_AXIS_TREADY, + axisClk => open, + axisRst => open, + axisMaster => sAxisMaster, + axisSlave => sAxisSlave); + + U_ShimLayerMaster : entity surf.MasterAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "M_AXIS", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 1, + TID_WIDTH => 8, + TDEST_WIDTH => 8, + TDATA_NUM_BYTES => MASTER_DATA_BYTES_G) + port map ( + M_AXIS_ACLK => axisClk, + M_AXIS_ARESETN => axisAResetN, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TSTRB => open, + M_AXIS_TKEEP => M_AXIS_TKEEP, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TDEST => M_AXIS_TDEST, + M_AXIS_TID => M_AXIS_TID, + M_AXIS_TUSER => open, + M_AXIS_TREADY => M_AXIS_TREADY, + axisClk => open, + axisRst => open, + axisMaster => mAxisMaster, + axisSlave => mAxisSlave); + + ---------------------------------------------------------------------------- + -- DUT hookup + ---------------------------------------------------------------------------- + U_DUT : entity surf.RoceResizeAndSwap + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + READY_EN_G => READY_EN_G, + PIPE_STAGES_G => PIPE_STAGES_G, + SIDE_BAND_WIDTH_G => SIDE_BAND_WIDTH_G, + SWAP_ENDIAN_G => SWAP_ENDIAN_G, + LITTLE_ENDIAN_G => LITTLE_ENDIAN_G, + SLAVE_AXI_CONFIG_G => SLAVE_AXI_CONFIG_C, + MASTER_AXI_CONFIG_G => MASTER_AXI_CONFIG_C) + port map ( + axisClk => axisClk, + axisRst => axisRst, + sAxisMaster => sAxisMaster, + sSideBand => S_SIDE_BAND, + sAxisSlave => sAxisSlave, + mAxisMaster => mAxisMaster, + mSideBand => M_SIDE_BAND, + mAxisSlave => mAxisSlave); + +end architecture rtl; diff --git a/tests/ethernet/RoCEv2/roce_test_utils.py b/tests/ethernet/RoCEv2/roce_test_utils.py new file mode 100644 index 0000000000..1198cd91b4 --- /dev/null +++ b/tests/ethernet/RoCEv2/roce_test_utils.py @@ -0,0 +1,104 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +from __future__ import annotations + +from pathlib import Path + +from tests.axi.utils import axil_read_u32, axil_write_u32 + + +ROCE_RTL_ROOT = Path(__file__).resolve().parents[3] / "ethernet" / "RoCEv2" / "rtl" +ROCE_PKG_SOURCE = str(ROCE_RTL_ROOT / "RocePkg.vhd") + + +def roce_rtl_sources(*filenames: str) -> list[str]: + sources = [ROCE_PKG_SOURCE] + sources.extend(str(ROCE_RTL_ROOT / filename) for filename in filenames) + return sources + + +ROCE_RTL_SOURCES = roce_rtl_sources( + *( + path.name + for path in sorted(ROCE_RTL_ROOT.glob("*.vhd")) + if path.name != "RocePkg.vhd" + ) +) + + +def range_chunks(data: bytes, *, chunk_bytes: int) -> list[bytes]: + return [data[index : index + chunk_bytes] for index in range(0, len(data), chunk_bytes)] + + +def expected_resize_and_swap_bytes( + data: bytes, + *, + slave_bytes: int, + master_bytes: int, + swap_endian: bool, + little_endian: bool, +) -> bytes: + if slave_bytes == master_bytes: + chunks = range_chunks(data, chunk_bytes=slave_bytes) + if swap_endian: + chunks = [chunk[::-1] for chunk in chunks] + return b"".join(chunks) + + output_chunks: list[bytes] = [] + + if master_bytes > slave_bytes: + ratio = master_bytes // slave_bytes + input_chunks = range_chunks(data, chunk_bytes=slave_bytes) + for index in range(0, len(input_chunks), ratio): + group = input_chunks[index : index + ratio] + if swap_endian: + group = [chunk[::-1] for chunk in group] + if not little_endian: + group = list(reversed(group)) + output_chunks.extend(group) + else: + ratio = slave_bytes // master_bytes + input_chunks = range_chunks(data, chunk_bytes=slave_bytes) + for chunk in input_chunks: + group = range_chunks(chunk, chunk_bytes=master_bytes) + if swap_endian: + group = [part[::-1] for part in group] + if not little_endian: + group = list(reversed(group)) + output_chunks.extend(group) + + return b"".join(output_chunks) + + +def split_u32_words(value: int, *, total_bits: int) -> list[int]: + word_count = (total_bits + 31) // 32 + return [(value >> (32 * index)) & 0xFFFF_FFFF for index in range(word_count)] + + +def join_u32_words(words: list[int], *, total_bits: int) -> int: + value = 0 + for index, word in enumerate(words): + value |= (word & 0xFFFF_FFFF) << (32 * index) + if total_bits % 32: + value &= (1 << total_bits) - 1 + return value + + +async def axil_write_wide(master, base_address: int, value: int, *, total_bits: int) -> None: + for index, word in enumerate(split_u32_words(value, total_bits=total_bits)): + await axil_write_u32(master, base_address + (4 * index), word) + + +async def axil_read_wide(master, base_address: int, *, total_bits: int) -> int: + words = [] + for index in range((total_bits + 31) // 32): + words.append(await axil_read_u32(master, base_address + (4 * index))) + return join_u32_words(words, total_bits=total_bits) diff --git a/tests/ethernet/RoCEv2/test_RoceConfigurator.py b/tests/ethernet/RoCEv2/test_RoceConfigurator.py new file mode 100644 index 0000000000..0014a1e146 --- /dev/null +++ b/tests/ethernet/RoCEv2/test_RoceConfigurator.py @@ -0,0 +1,137 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Keep one common-clock wrapper instance but cover two configuration +# launches so the bench proves both the request/response datapath and the +# rising-edge trigger on `metaDataIsSet`. +# - Stimulus: Program the wide metadata register over AXI-Lite, raise the set +# bit, return one metadata response beat, then hold the set bit high long +# enough to prove there is no duplicate request before clearing and setting +# it again with a second payload. +# - Checks: Each rising edge of the set bit must emit exactly one request, +# `metaDataIsReady` must raise only after the response arrives, and the wide +# response register bank must read back the returned metadata word. +# - Timing: The bench waits on visible AXI Stream request beats and AXI-Lite +# status reads instead of assuming a fixed latency through the state machine. + +from __future__ import annotations + +import cocotb +import pytest +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotbext.axi import AxiLiteBus, AxiLiteMaster + +from tests.axi.utils import axil_read_u32, axil_write_u32 +from tests.common.regression_utils import run_surf_vhdl_test +from tests.ethernet.RoCEv2.roce_test_utils import axil_read_wide, axil_write_wide, roce_rtl_sources + + +WRAPPER_PATH = "ethernet/RoCEv2/wrappers/RoceConfiguratorWrapper.vhd" +RTL_SOURCES = roce_rtl_sources("RoceConfigurator.vhd") + + +class TB: + def __init__(self, dut): + self.dut = dut + self.axil = None + + cocotb.start_soon(Clock(dut.clk, 5.0, unit="ns").start()) + + dut.rst.setimmediatevalue(1) + dut.M_META_REQ_TREADY.setimmediatevalue(0) + dut.S_META_RESP_TVALID.setimmediatevalue(0) + dut.S_META_RESP_TDATA.setimmediatevalue(0) + + async def cycle(self, count: int = 1): + for _ in range(count): + await RisingEdge(self.dut.clk) + await Timer(1, unit="ns") + + async def reset(self): + self.dut.rst.value = 1 + await self.cycle(4) + self.dut.rst.value = 0 + await self.cycle(2) + + def start_agents(self): + if self.axil is None: + self.axil = AxiLiteMaster(AxiLiteBus.from_prefix(self.dut, "S_AXIL"), self.dut.clk, self.dut.rst) + + async def wait_for_metadata_request(self, *, timeout_cycles: int = 64) -> int: + self.dut.M_META_REQ_TREADY.value = 1 + for _ in range(timeout_cycles): + await RisingEdge(self.dut.clk) + await Timer(1, unit="ns") + if int(self.dut.M_META_REQ_TVALID.value) == 1: + value = int(self.dut.M_META_REQ_TDATA.value) + await RisingEdge(self.dut.clk) + await Timer(1, unit="ns") + self.dut.M_META_REQ_TREADY.value = 0 + return value + self.dut.M_META_REQ_TREADY.value = 0 + raise AssertionError("Timed out waiting for metadata request") + + +@cocotb.test() +async def roce_configurator_axil_to_metadata_stream_test(dut): + tb = TB(dut) + await tb.reset() + tb.start_agents() + assert tb.axil is not None + + first_request = ((1 << 303) - 1) ^ 0x1234_5678_9ABC_DEF0_0123_4567 + first_response = ((1 << 276) - 1) ^ 0x0FED_CBA9_8765_4321 + + # Program the outgoing metadata register bank and prove the request only + # launches on the rising edge of `metaDataIsSet`. + await axil_write_wide(tb.axil, 0xF04, first_request, total_bits=303) + await axil_write_u32(tb.axil, 0xF00, 0x1) + observed_request = await tb.wait_for_metadata_request() + assert observed_request == first_request + assert (await axil_read_u32(tb.axil, 0xF00) >> 1) & 0x1 == 0 + + # Return one response beat and then confirm the ready flag and the + # read-only response register bank update as expected. + dut.S_META_RESP_TDATA.value = first_response + dut.S_META_RESP_TVALID.value = 1 + while True: + await RisingEdge(dut.clk) + await Timer(1, unit="ns") + if int(dut.S_META_RESP_TREADY.value) == 1: + dut.S_META_RESP_TVALID.value = 0 + break + + await tb.cycle(2) + assert (await axil_read_u32(tb.axil, 0xF00) >> 1) & 0x1 == 1 + assert await axil_read_wide(tb.axil, 0xF2C, total_bits=276) == first_response + + # Holding the set bit high must not emit another request until software + # clears and re-asserts it. + await tb.cycle(8) + assert int(dut.M_META_REQ_TVALID.value) == 0 + + second_request = 0x1357_9BDF_2468_ACE0_55AA_F00D + await axil_write_u32(tb.axil, 0xF00, 0x0) + await axil_write_wide(tb.axil, 0xF04, second_request, total_bits=303) + await axil_write_u32(tb.axil, 0xF00, 0x1) + assert await tb.wait_for_metadata_request() == second_request + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="roce_configurator_wrapper")]) +def test_RoceConfigurator(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.roceconfiguratorwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": RTL_SOURCES + [WRAPPER_PATH]}, + ) diff --git a/tests/ethernet/RoCEv2/test_RoceResizeAndSwap.py b/tests/ethernet/RoCEv2/test_RoceResizeAndSwap.py new file mode 100644 index 0000000000..b833e2c639 --- /dev/null +++ b/tests/ethernet/RoCEv2/test_RoceResizeAndSwap.py @@ -0,0 +1,168 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Keep a narrow three-case wrapper sweep covering equal-width +# pass-through, `16 -> 32` upsize with byte swapping, and `32 -> 16` +# downsize with the same byte-swapped big-lane ordering used by the RoCE +# engine wrapper. +# - Stimulus: Drive AXI Stream frames with distinct `tid`, `tdest`, and +# sideband values through a checked-in scalar-generic wrapper and stall the +# sink briefly so buffered resized output becomes visible. +# - Checks: The output byte stream must match the expected resize-and-swap +# transformation, metadata must survive unchanged, and the sideband value +# must stay aligned with each accepted output beat. +# - Timing: Equal-width traffic is treated as pass-through, while resized +# cases wait on visible output handshakes rather than assuming a fixed +# internal latency. + +from __future__ import annotations + +import os + +import cocotb +import pytest +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSink, AxiStreamSource + +from tests.common.regression_utils import env_flag, parameter_case, run_surf_vhdl_test +from tests.ethernet.RoCEv2.roce_test_utils import expected_resize_and_swap_bytes, roce_rtl_sources + + +WRAPPER_PATH = "ethernet/RoCEv2/wrappers/RoceResizeAndSwapIpIntegrator.vhd" +RTL_SOURCES = roce_rtl_sources("RoceResizeAndSwap.vhd") + + +class TB: + def __init__(self, dut): + self.dut = dut + self.slave_bytes = int(os.environ["SLAVE_DATA_BYTES_G"]) + self.master_bytes = int(os.environ["MASTER_DATA_BYTES_G"]) + self.side_band_width = int(os.environ["SIDE_BAND_WIDTH_G"]) + self.swap_endian = env_flag("SWAP_ENDIAN_G", default=False) + self.little_endian = env_flag("LITTLE_ENDIAN_G", default=True) + self.source = None + self.sink = None + self.rx_sidebands: list[int] = [] + + cocotb.start_soon(Clock(dut.axisClk, 5.0, unit="ns").start()) + + dut.axisRst.setimmediatevalue(1) + dut.S_AXIS_TVALID.setimmediatevalue(0) + dut.S_AXIS_TDATA.setimmediatevalue(0) + dut.S_AXIS_TKEEP.setimmediatevalue(0) + dut.S_AXIS_TLAST.setimmediatevalue(0) + dut.S_AXIS_TDEST.setimmediatevalue(0) + dut.S_AXIS_TID.setimmediatevalue(0) + dut.S_SIDE_BAND.setimmediatevalue(0) + dut.M_AXIS_TREADY.setimmediatevalue(0) + + cocotb.start_soon(self._monitor_sideband()) + + async def cycle(self, count: int = 1): + for _ in range(count): + await RisingEdge(self.dut.axisClk) + await Timer(1, unit="ns") + + async def _monitor_sideband(self): + while True: + await RisingEdge(self.dut.axisClk) + await Timer(1, unit="ns") + if int(self.dut.M_AXIS_TVALID.value) == 1 and int(self.dut.M_AXIS_TREADY.value) == 1: + self.rx_sidebands.append(int(self.dut.M_SIDE_BAND.value)) + + async def reset(self): + self.dut.axisRst.value = 1 + self.dut.M_AXIS_TREADY.value = 0 + await self.cycle(4) + self.dut.axisRst.value = 0 + await self.cycle(2) + + def start_agents(self): + if self.source is None: + self.source = AxiStreamSource(AxiStreamBus.from_prefix(self.dut, "S_AXIS"), self.dut.axisClk, self.dut.axisRst) + if self.sink is None: + self.sink = AxiStreamSink(AxiStreamBus.from_prefix(self.dut, "M_AXIS"), self.dut.axisClk, self.dut.axisRst) + + +@cocotb.test() +async def roce_resize_and_swap_test(dut): + tb = TB(dut) + await tb.reset() + tb.start_agents() + assert tb.source is not None + assert tb.sink is not None + + payload = bytes(range(2 * max(tb.slave_bytes, tb.master_bytes))) + frame = AxiStreamFrame(payload) + frame.tid = 0x35 + frame.tdest = 0x71 + sideband = (1 << tb.side_band_width) - 1 + + tb.dut.S_SIDE_BAND.value = sideband + tb.dut.M_AXIS_TREADY.value = 0 + send_task = cocotb.start_soon(tb.source.send(frame)) + await tb.cycle(3) + tb.dut.M_AXIS_TREADY.value = 1 + rx_frame = await tb.sink.recv() + await send_task + + assert rx_frame.tdata == expected_resize_and_swap_bytes( + payload, + slave_bytes=tb.slave_bytes, + master_bytes=tb.master_bytes, + swap_endian=tb.swap_endian, + little_endian=tb.little_endian, + ) + assert rx_frame.tid == frame.tid + assert rx_frame.tdest == frame.tdest + + assert tb.rx_sidebands + assert all(observed == sideband for observed in tb.rx_sidebands) + + +PARAMETER_SWEEP = [ + parameter_case( + "equal_width_passthrough", + SLAVE_DATA_BYTES_G="16", + MASTER_DATA_BYTES_G="16", + SIDE_BAND_WIDTH_G="2", + SWAP_ENDIAN_G="false", + LITTLE_ENDIAN_G="true", + ), + parameter_case( + "upsize_swap_big_lane", + SLAVE_DATA_BYTES_G="16", + MASTER_DATA_BYTES_G="32", + SIDE_BAND_WIDTH_G="3", + SWAP_ENDIAN_G="true", + LITTLE_ENDIAN_G="false", + ), + parameter_case( + "downsize_swap_big_lane", + SLAVE_DATA_BYTES_G="32", + MASTER_DATA_BYTES_G="16", + SIDE_BAND_WIDTH_G="3", + SWAP_ENDIAN_G="true", + LITTLE_ENDIAN_G="false", + ), +] + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +def test_RoceResizeAndSwap(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.roceresizeandswapipintegrator", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": RTL_SOURCES + [WRAPPER_PATH]}, + ) From a0c05590ed4550deeb76d2be96172d00c2e4b10e Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 20 Apr 2026 10:04:08 -0700 Subject: [PATCH 25/92] Remove planning docs again. --- docs/_meta/rtl_instantiation_graph.json | 14578 ------------------- docs/_meta/rtl_instantiation_graph.md | 270 - docs/_meta/rtl_phase1_queue.json | 5874 -------- docs/_meta/rtl_phase1_queue.md | 272 - docs/_meta/rtl_phase1_queue_overrides.json | 85 - docs/_meta/rtl_regression_handoff.md | 214 - docs/_meta/rtl_regression_inventory.yaml | 700 - docs/_meta/rtl_regression_plan.md | 147 - docs/_meta/rtl_regression_progress.md | 318 - 9 files changed, 22458 deletions(-) delete mode 100644 docs/_meta/rtl_instantiation_graph.json delete mode 100644 docs/_meta/rtl_instantiation_graph.md delete mode 100644 docs/_meta/rtl_phase1_queue.json delete mode 100644 docs/_meta/rtl_phase1_queue.md delete mode 100644 docs/_meta/rtl_phase1_queue_overrides.json delete mode 100644 docs/_meta/rtl_regression_handoff.md delete mode 100644 docs/_meta/rtl_regression_inventory.yaml delete mode 100644 docs/_meta/rtl_regression_plan.md delete mode 100644 docs/_meta/rtl_regression_progress.md diff --git a/docs/_meta/rtl_instantiation_graph.json b/docs/_meta/rtl_instantiation_graph.json deleted file mode 100644 index cac3414382..0000000000 --- a/docs/_meta/rtl_instantiation_graph.json +++ /dev/null @@ -1,14578 +0,0 @@ -{ - "generated_from": { - "scan_dirs": [ - "base", - "axi", - "dsp", - "protocols", - "ethernet", - "devices", - "xilinx" - ], - "parser_scope": "VHDL entities outside tb/build/.venv paths", - "parser_limitations": [ - "Package calls are not graph nodes.", - "Direct entity instantiations are handled explicitly.", - "Component-style instantiations are inferred only when the instantiated name matches a known entity name inside an architecture body." - ] - }, - "summary": { - "entity_count": 795, - "edge_count": 1584, - "duplicate_entity_names": { - "Ad9249Deserializer": [ - "devices/AnalogDevices/ad9249/7Series/rtl/Ad9249Deserializer.vhd", - "devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd" - ], - "Ad9249ReadoutGroup": [ - "devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd", - "devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd" - ], - "ClinkDataClk": [ - "protocols/clink/7Series/ClinkDataClk.vhd", - "protocols/clink/UltraScale/ClinkDataClk.vhd" - ], - "ClinkDataShift": [ - "protocols/clink/7Series/ClinkDataShift.vhd", - "protocols/clink/UltraScale/ClinkDataShift.vhd" - ], - "ClkOutBufDiff": [ - "xilinx/dummy/ClkOutBufDiffDummy.vhd", - "xilinx/general/rtl/ClkOutBufDiff.vhd" - ], - "ClkOutBufSingle": [ - "xilinx/dummy/ClkOutBufSingleDummy.vhd", - "xilinx/general/rtl/ClkOutBufSingle.vhd" - ], - "ClockManagerUltraScale": [ - "xilinx/UltraScale/clocking/rtl/ClockManagerUltraScale.vhd", - "xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd" - ], - "CoaXPressOverFiberGthUsIpWrapper": [ - "protocols/coaxpress/gthUs/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd", - "protocols/coaxpress/gthUs+/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd" - ], - "CoaxpressOverFiberGthUs": [ - "protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUs.vhd", - "protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUs.vhd" - ], - "CoaxpressOverFiberGthUsQpll": [ - "protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUsQpll.vhd", - "protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUsQpll.vhd" - ], - "DS2411Core": [ - "devices/Maxim/dummy/DS2411CoreDummy.vhd", - "devices/Maxim/rtl/DS2411Core.vhd" - ], - "DeviceDna": [ - "xilinx/dummy/DeviceDnaDummy.vhd", - "xilinx/general/rtl/DeviceDna.vhd" - ], - "FifoAlteraMf": [ - "base/fifo/rtl/altera/FifoAlteraMf.vhd", - "base/fifo/rtl/dummy/FifoAlteraMfDummy.vhd" - ], - "FifoXpm": [ - "base/fifo/rtl/dummy/FifoXpmDummy.vhd", - "base/fifo/rtl/xilinx/FifoXpm.vhd" - ], - "GigEthGthUltraScale": [ - "ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd", - "ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd" - ], - "GigEthGthUltraScaleWrapper": [ - "ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd", - "ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd" - ], - "GthUltraScaleQuadPll": [ - "xilinx/UltraScale/gthUs/rtl/GthUltraScaleQuadPll.vhd", - "xilinx/UltraScale+/gthUs+/rtl/GthUltraScaleQuadPll.vhd" - ], - "Idelaye3Wrapper": [ - "xilinx/7Series/dummy/Idelaye3WrapperDummy.vhd", - "xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd" - ], - "InputBufferReg": [ - "xilinx/7Series/general/rtl/InputBufferReg.vhd", - "xilinx/UltraScale/general/rtl/InputBufferReg.vhd" - ], - "IoBufWrapper": [ - "xilinx/dummy/IoBufWrapperDummy.vhd", - "xilinx/general/rtl/IoBufWrapper.vhd" - ], - "Iprog": [ - "xilinx/dummy/IprogDummy.vhd", - "xilinx/general/rtl/Iprog.vhd" - ], - "MicroblazeBasicCoreWrapper": [ - "xilinx/general/microblaze/bypass/MicroblazeBasicCoreWrapper.vhd", - "xilinx/general/microblaze/generate/MicroblazeBasicCoreWrapper.vhd" - ], - "Odelaye3Wrapper": [ - "xilinx/7Series/dummy/Odelaye3WrapperDummy.vhd", - "xilinx/UltraScale/general/rtl/Odelaye3Wrapper.vhd" - ], - "OutputBufferReg": [ - "xilinx/7Series/general/rtl/OutputBufferReg.vhd", - "xilinx/UltraScale/general/rtl/OutputBufferReg.vhd", - "xilinx/dummy/OutputBufferRegDummy.vhd" - ], - "Pgp2bGthUltra": [ - "protocols/pgp/pgp2b/gthUltraScale/rtl/Pgp2bGthUltra.vhd", - "protocols/pgp/pgp2b/gthUltraScale+/rtl/Pgp2bGthUltra.vhd" - ], - "Pgp3GthUs": [ - "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUs.vhd", - "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUs.vhd" - ], - "Pgp3GthUsIpWrapper": [ - "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd", - "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsIpWrapper.vhd" - ], - "Pgp3GthUsQpll": [ - "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd", - "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsQpll.vhd" - ], - "Pgp3GthUsWrapper": [ - "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsWrapper.vhd", - "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsWrapper.vhd" - ], - "Pgp4GthUs": [ - "protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUs.vhd", - "protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUs.vhd" - ], - "Pgp4GthUsWrapper": [ - "protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUsWrapper.vhd", - "protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUsWrapper.vhd" - ], - "PgpGthCoreWrapper": [ - "protocols/pgp/pgp2b/gthUltraScale/rtl/PgpGthCoreWrapper.vhd", - "protocols/pgp/pgp2b/gthUltraScale+/rtl/PgpGthCoreWrapper.vhd" - ], - "RogueSideBand": [ - "axi/simlink/ghdl/RogueSideBand.vhd", - "axi/simlink/sim/RogueSideBand.vhd" - ], - "RogueTcpMemory": [ - "axi/simlink/ghdl/RogueTcpMemory.vhd", - "axi/simlink/sim/RogueTcpMemory.vhd" - ], - "RogueTcpStream": [ - "axi/simlink/ghdl/RogueTcpStream.vhd", - "axi/simlink/sim/RogueTcpStream.vhd" - ], - "SaltRxDeser": [ - "protocols/salt/rtl/7Series/SaltRxDeser.vhd", - "protocols/salt/rtl/UltraScale/SaltRxDeser.vhd" - ], - "SaltTxSer": [ - "protocols/salt/rtl/7Series/SaltTxSer.vhd", - "protocols/salt/rtl/UltraScale/SaltTxSer.vhd" - ], - "SimpleDualPortRamXpm": [ - "base/ram/dummy/SimpleDualPortRamXpmDummy.vhd", - "base/ram/xilinx/SimpleDualPortRamXpm.vhd" - ], - "SinglePortRamPrimitive": [ - "base/ram/dummy/SinglePortRamPrimitiveDummy.vhd", - "base/ram/xilinx/SinglePortRamPrimitive.vhd" - ], - "Srl16Delay": [ - "xilinx/dummy/Srl16DelayDummy.vhd", - "xilinx/general/rtl/Srl16Delay.vhd" - ], - "SugoiManagerRx7Series": [ - "protocols/sugoi/rtl/7Series/SugoiManagerRx7Series.vhd", - "protocols/sugoi/rtl/dummy/SugoiManagerRx7SeriesDummy.vhd" - ], - "SugoiManagerRxUltrascale": [ - "protocols/sugoi/rtl/UltraScale/SugoiManagerRxUltrascale.vhd", - "protocols/sugoi/rtl/dummy/SugoiManagerRxUltrascaleDummy.vhd" - ], - "TenGigEthGthUltraScale": [ - "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd", - "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd" - ], - "TenGigEthGthUltraScaleClk": [ - "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleClk.vhd", - "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleClk.vhd" - ], - "TenGigEthGthUltraScaleRst": [ - "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleRst.vhd", - "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleRst.vhd" - ], - "TenGigEthGthUltraScaleWrapper": [ - "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd", - "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd" - ], - "TrueDualPortRamXpm": [ - "base/ram/dummy/TrueDualPortRamXpmDummy.vhd", - "base/ram/xilinx/TrueDualPortRamXpm.vhd" - ], - "UdpDebugBridge": [ - "xilinx/xvc-udp/dcp/7Series/Impl/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/7Series/Stub/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/UltraScale/Impl/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/UltraScale/Stub/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd", - "xilinx/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd" - ], - "UdpDebugBridgeWrapper": [ - "xilinx/xvc-udp/dcp/core/UdpDebugBridgeWrapper.vhd", - "xilinx/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd" - ], - "XauiGthUltraScale": [ - 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- "paths": [ - "base/ram/inferred/TrueDualPortRam.vhd" - ], - "subsystem": "base", - "instantiates": [], - "instantiated_by": [ - "AxiDualPortRam", - "AxiLiteSequencerRam", - "DualPortRam" - ], - "instantiates_count": 0, - "instantiated_by_count": 3, - "topological_layer": 6 - }, - { - "entity": "TrueDualPortRamAlteraMf", - "paths": [ - "base/ram/dummy/TrueDualPortRamXpmAlteraMfDummy.vhd" - ], - "subsystem": "base", - "instantiates": [], - "instantiated_by": [ - "AxiDualPortRam", - "AxiLiteSequencerRam" - ], - "instantiates_count": 0, - "instantiated_by_count": 2, - "topological_layer": 4 - }, - { - "entity": "TrueDualPortRamXpm", - "paths": [ - "base/ram/dummy/TrueDualPortRamXpmDummy.vhd", - "base/ram/xilinx/TrueDualPortRamXpm.vhd" - ], - "subsystem": "base", - "instantiates": [], - "instantiated_by": [ - "AxiDualPortRam", - "AxiLiteSequencerRam" - ], - "instantiates_count": 0, - "instantiated_by_count": 2, - "topological_layer": 4 - }, - { - "entity": "UartAxiLiteMaster", - "paths": [ - "protocols/uart/rtl/UartAxiLiteMaster.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "UartAxiLiteMasterFsm", - "UartWrapper" - ], - "instantiated_by": [ - "UartAxiLiteMasterTb" - ], - "instantiates_count": 2, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "UartAxiLiteMasterFsm", - "paths": [ - "protocols/uart/rtl/UartAxiLiteMasterFsm.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "AxiLiteMaster" - ], - "instantiated_by": [ - "UartAxiLiteMaster" - ], - "instantiates_count": 1, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "UartAxiLiteMasterTb", - "paths": [ - "protocols/uart/sim/UartAxiLiteMasterTb.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "AxiDualPortRam", - "UartAxiLiteMaster", - "UartWrapper" - ], - "instantiated_by": [], - "instantiates_count": 3, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "UartBrg", - "paths": [ - "protocols/uart/rtl/UartBrg.vhd" - ], - "subsystem": "protocols", - "instantiates": [], - "instantiated_by": [ - "UartWrapper" - ], - "instantiates_count": 0, - "instantiated_by_count": 1, - "topological_layer": 3 - }, - { - "entity": "UartRx", - "paths": [ - "protocols/uart/rtl/UartRx.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "SynchronizerEdge" - ], - "instantiated_by": [ - "ClinkUart", - "UartWrapper" - ], - "instantiates_count": 1, - "instantiated_by_count": 2, - "topological_layer": 3 - }, - { - "entity": "UartSem", - "paths": [ - "xilinx/7Series/sem/rtl/UartSem.vhd" - ], - "subsystem": "xilinx", - "instantiates": [ - "SemWrapper", - "UartWrapper" - ], - "instantiated_by": [], - "instantiates_count": 2, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "UartTx", - "paths": [ - "protocols/uart/rtl/UartTx.vhd" - ], - "subsystem": "protocols", - "instantiates": [], - "instantiated_by": [ - "ClinkUart", - "UartWrapper" - ], - "instantiates_count": 0, - "instantiated_by_count": 2, - "topological_layer": 3 - }, - { - "entity": "UartWrapper", - "paths": [ - "protocols/uart/rtl/UartWrapper.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "Fifo", - "UartBrg", - "UartRx", - "UartTx" - ], - "instantiated_by": [ - "UartAxiLiteMaster", - "UartAxiLiteMasterTb", - "UartSem" - ], - "instantiates_count": 4, - "instantiated_by_count": 3, - "topological_layer": 2 - }, - { - "entity": "UdpDebugBridge", - "paths": [ - "xilinx/xvc-udp/dcp/7Series/Impl/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/7Series/Stub/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/UltraScale/Impl/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/UltraScale/Stub/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd", - "xilinx/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd" - ], - "subsystem": "xilinx", - "instantiates": [ - "AxisJtagDebugBridge" - ], - "instantiated_by": [ - "UdpDebugBridgeWrapper" - ], - "instantiates_count": 1, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "UdpDebugBridgeWrapper", - "paths": [ - "xilinx/xvc-udp/dcp/core/UdpDebugBridgeWrapper.vhd", - "xilinx/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd" - ], - "subsystem": "xilinx", - "instantiates": [ - "UdpDebugBridge" - ], - "instantiated_by": [ - "DmaXvcWrapper", - "PgpXvcWrapper" - ], - "instantiates_count": 1, - "instantiated_by_count": 2, - "topological_layer": 1 - }, - { - "entity": "UdpEngine", - "paths": [ - "ethernet/UdpEngine/rtl/UdpEngine.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "ArpIpTable", - "AxiStreamMux", - "UdpEngineArp", - "UdpEngineDhcp", - "UdpEngineRx", - "UdpEngineTx" - ], - "instantiated_by": [ - "UdpEngineWrapper" - ], - "instantiates_count": 6, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "UdpEngineArp", - "paths": [ - "ethernet/UdpEngine/rtl/UdpEngineArp.vhd" - ], - "subsystem": "ethernet", - "instantiates": [], - "instantiated_by": [ - "UdpEngine" - ], - "instantiates_count": 0, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "UdpEngineDhcp", - "paths": [ - "ethernet/UdpEngine/rtl/UdpEngineDhcp.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "AxiStreamFifoV2" - ], - "instantiated_by": [ - "UdpEngine" - ], - "instantiates_count": 1, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "UdpEngineRx", - "paths": [ - "ethernet/UdpEngine/rtl/UdpEngineRx.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "AxiStreamDeMux", - "AxiStreamPipeline" - ], - "instantiated_by": [ - "UdpEngine" - ], - "instantiates_count": 2, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "UdpEngineTx", - "paths": [ - "ethernet/UdpEngine/rtl/UdpEngineTx.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "AxiStreamPipeline" - ], - "instantiated_by": [ - "UdpEngine" - ], - "instantiates_count": 1, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "UdpEngineWrapper", - "paths": [ - "ethernet/UdpEngine/rtl/UdpEngineWrapper.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "IpV4Engine", - "UdpEngine" - ], - "instantiated_by": [], - "instantiates_count": 2, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "WatchDogRst", - "paths": [ - "base/general/rtl/WatchDogRst.vhd" - ], - "subsystem": "base", - "instantiates": [ - "Synchronizer" - ], - "instantiated_by": [ - "GigEthReg", - "XauiGthUltraScaleWrapper", - "XauiGtyUltraScaleWrapper" - ], - "instantiates_count": 1, - "instantiated_by_count": 3, - "topological_layer": 3 - }, - { - "entity": "XadcSimpleCore", - "paths": [ - "xilinx/7Series/xadc/rtl/XadcSimpleCore.vhd" - ], - "subsystem": "xilinx", - "instantiates": [ - "AxiLiteToDrp" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "XauiGth7", - "paths": [ - "ethernet/XauiCore/gth7/rtl/XauiGth7.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "EthMacTop", - "RstSync", - "XauiGth7Core", - "XauiReg" - ], - "instantiated_by": [ - "XauiGth7Wrapper" - ], - "instantiates_count": 4, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "XauiGth7Core", - "paths": [ - "ethernet/XauiCore/gth7/rtl/XauiGth7Core.vhd" - ], - "subsystem": "ethernet", - "instantiates": [], - "instantiated_by": [ - "XauiGth7" - ], - "instantiates_count": 0, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "XauiGth7Wrapper", - "paths": [ - "ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "XauiGth7" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "XauiGthUltraScale", - "paths": [ - "ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd", - "ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "EthMacTop", - "RstSync", - "XauiReg" - ], - "instantiated_by": [ - "XauiGthUltraScaleWrapper" - ], - "instantiates_count": 3, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "XauiGthUltraScaleWrapper", - "paths": [ - "ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd", - "ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "PwrUpRst", - "WatchDogRst", - "XauiGthUltraScale" - ], - "instantiated_by": [], - "instantiates_count": 3, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "XauiGtx7", - "paths": [ - "ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "EthMacTop", - "RstSync", - "XauiGtx7Core", - "XauiReg" - ], - "instantiated_by": [ - "XauiGtx7Wrapper" - ], - "instantiates_count": 4, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "XauiGtx7Core", - "paths": [ - "ethernet/XauiCore/gtx7/rtl/XauiGtx7Core.vhd" - ], - "subsystem": "ethernet", - "instantiates": [], - "instantiated_by": [ - "XauiGtx7" - ], - "instantiates_count": 0, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "XauiGtx7Wrapper", - "paths": [ - "ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "XauiGtx7" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "XauiGtyUltraScale", - "paths": [ - "ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "EthMacTop", - "RstSync", - "XauiReg" - ], - "instantiated_by": [ - "XauiGtyUltraScaleWrapper" - ], - "instantiates_count": 3, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "XauiGtyUltraScaleWrapper", - "paths": [ - "ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "PwrUpRst", - "WatchDogRst", - "XauiGtyUltraScale" - ], - "instantiated_by": [], - "instantiates_count": 3, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "XauiReg", - "paths": [ - "ethernet/XauiCore/core/rtl/XauiReg.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "SyncStatusVector", - "SynchronizerFifo", - "SynchronizerVector" - ], - "instantiated_by": [ - "XauiGth7", - "XauiGthUltraScale", - "XauiGtx7", - "XauiGtyUltraScale" - ], - "instantiates_count": 3, - "instantiated_by_count": 4, - "topological_layer": 2 - }, - { - "entity": "adc32rf45", - "paths": [ - "devices/Ti/adc32rf45/rtl/adc32rf45.vhd" - ], - "subsystem": "devices", - "instantiates": [ - "SpiMaster" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "add3", - "paths": [ - "dsp/xilinx/fixed/Add3.vhd" - ], - "subsystem": "dsp", - "instantiates": [ - "csa3" - ], - "instantiated_by": [ - "FirAverage", - "IirSimple" - ], - "instantiates_count": 1, - "instantiated_by_count": 2, - "topological_layer": 1 - }, - { - "entity": "ads54j60", - "paths": [ - "devices/Ti/ads54j60/rtl/ads54j60.vhd" - ], - "subsystem": "devices", - "instantiates": [ - "SpiMaster" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "cfixedDelay", - "paths": [ - "dsp/xilinx/fixed/CfixedDelay.vhd" - ], - "subsystem": "dsp", - "instantiates": [ - "SlvFixedDelay" - ], - "instantiated_by": [ - "SinCosTaylor" - ], - "instantiates_count": 1, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "cfixedMult", - "paths": [ - "dsp/xilinx/fixed/CfixedMult.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [], - "instantiates_count": 0, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "cfixedMultAdd", - "paths": [ - "dsp/xilinx/fixed/CfixedMultAdd.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [], - "instantiates_count": 0, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "csa3", - "paths": [ - "dsp/xilinx/fixed/Csa3.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [ - "add3" - ], - "instantiates_count": 0, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "i2c2ahb", - "paths": [ - "protocols/i2c/rtl/orig/i2c2ahb.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "i2c2ahbx" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "i2c2ahb_apb", - "paths": [ - "protocols/i2c/rtl/orig/i2c2ahb_apb.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "i2c2ahbx" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "i2c2ahbx", - "paths": [ - "protocols/i2c/rtl/orig/i2c2ahbx.vhd" - ], - "subsystem": "protocols", - "instantiates": [], - "instantiated_by": [ - "i2c2ahb", - "i2c2ahb_apb" - ], - "instantiates_count": 0, - "instantiated_by_count": 2, - "topological_layer": 1 - }, - { - "entity": "i2c_master_bit_ctrl", - "paths": [ - "protocols/i2c/rtl/i2c_master_bit_ctrl.vhd" - ], - "subsystem": "protocols", - "instantiates": [], - "instantiated_by": [ - "i2c_master_byte_ctrl" - ], - "instantiates_count": 0, - "instantiated_by_count": 1, - "topological_layer": 6 - }, - { - "entity": "i2c_master_byte_ctrl", - "paths": [ - "protocols/i2c/rtl/i2c_master_byte_ctrl.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "i2c_master_bit_ctrl" - ], - "instantiated_by": [ - "I2cMaster", - "i2cmst" - ], - "instantiates_count": 1, - "instantiated_by_count": 2, - "topological_layer": 5 - }, - { - "entity": "i2cmst", - "paths": [ - "protocols/i2c/rtl/orig/i2cmst.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "i2c_master_byte_ctrl" - ], - "instantiated_by": [ - "i2cmst_gen" - ], - "instantiates_count": 1, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "i2cmst_gen", - "paths": [ - "protocols/i2c/rtl/orig/i2cmst_gen.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "i2cmst" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "i2cslv", - "paths": [ - "protocols/i2c/rtl/orig/i2cslv.vhd" - ], - "subsystem": "protocols", - "instantiates": [], - "instantiated_by": [], - "instantiates_count": 0, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "iq16bTo32b", - "paths": [ - "protocols/jesd204b/rtl/iq16bTo32b.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "Fifo" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "iq32bTo16b", - "paths": [ - "protocols/jesd204b/rtl/iq32bTo16b.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "Fifo" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "sfixedDelay", - "paths": [ - "dsp/xilinx/fixed/SfixedDelay.vhd" - ], - "subsystem": "dsp", - "instantiates": [ - "SlvFixedDelay" - ], - "instantiated_by": [ - "FirAverage", - "IirSimple" - ], - "instantiates_count": 1, - "instantiated_by_count": 2, - "topological_layer": 1 - }, - { - "entity": "sfixedMult", - "paths": [ - "dsp/xilinx/fixed/SfixedMult.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [ - "SinCosTaylor" - ], - "instantiates_count": 0, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "sfixedMultAdd", - "paths": [ - "dsp/xilinx/fixed/SfixedMultAdd.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [], - "instantiates_count": 0, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "sfixedPreAddMultAdd", - "paths": [ - "dsp/xilinx/fixed/SfixedPreAddMultAdd.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [], - "instantiates_count": 0, - "instantiated_by_count": 0, - "topological_layer": 0 - } - ] -} diff --git a/docs/_meta/rtl_instantiation_graph.md b/docs/_meta/rtl_instantiation_graph.md deleted file mode 100644 index 33b4e08d81..0000000000 --- a/docs/_meta/rtl_instantiation_graph.md +++ /dev/null @@ -1,270 +0,0 @@ -# SURF RTL Instantiation Graph - -## Scope -- Scan dirs: `base, axi, dsp, protocols, ethernet, devices, xilinx` -- Included files: VHDL files outside `tb/`, `build/`, and `.venv/` paths. -- Direct entity instantiations are parsed explicitly. -- Component-style instantiations are included only when the instantiated token matches a known entity name inside an architecture body. -- Packages are not graph nodes. - -## Summary -- Entities: `795` -- Edges: `1584` -- Topological layers: `12` -- Duplicate entity names: `51` - -## Top Instantiated Entities -| entity | instantiated_by_count | instantiates_count | path | -| --- | --- | --- | --- | -| RstSync | 75 | 1 | base/sync/rtl/RstSync.vhd | -| Synchronizer | 73 | 0 | base/sync/rtl/Synchronizer.vhd | -| AxiStreamFifoV2 | 41 | 5 | axi/axi-stream/rtl/AxiStreamFifoV2.vhd | -| SynchronizerVector | 41 | 0 | base/sync/rtl/SynchronizerVector.vhd | -| AxiStreamPipeline | 38 | 0 | axi/axi-stream/rtl/AxiStreamPipeline.vhd | -| MasterAxiStreamIpIntegrator | 37 | 1 | axi/axi-stream/ip_integrator/MasterAxiStreamIpIntegrator.vhd | -| SlaveAxiLiteIpIntegrator | 37 | 1 | axi/axi-lite/ip_integrator/SlaveAxiLiteIpIntegrator.vhd | -| SlaveAxiStreamIpIntegrator | 37 | 1 | axi/axi-stream/ip_integrator/SlaveAxiStreamIpIntegrator.vhd | -| SynchronizerFifo | 37 | 1 | base/sync/rtl/SynchronizerFifo.vhd | -| PwrUpRst | 36 | 1 | base/general/rtl/PwrUpRst.vhd | -| AxiLiteCrossbar | 32 | 0 | axi/axi-lite/rtl/AxiLiteCrossbar.vhd | -| AxiLiteToDrp | 28 | 1 | axi/bridge/rtl/AxiLiteToDrp.vhd | -| SynchronizerOneShot | 28 | 2 | base/sync/rtl/SynchronizerOneShot.vhd | -| AxiLiteAsync | 23 | 1 | axi/axi-lite/rtl/AxiLiteAsync.vhd | -| Fifo | 18 | 4 | base/fifo/rtl/Fifo.vhd | -| MasterAxiIpIntegrator | 16 | 1 | axi/axi4/ip_integrator/MasterAxiIpIntegrator.vhd | -| SyncStatusVector | 16 | 2 | base/sync/rtl/SyncStatusVector.vhd | -| SynchronizerEdge | 16 | 1 | base/sync/rtl/SynchronizerEdge.vhd | -| RstPipeline | 15 | 0 | base/general/rtl/RstPipeline.vhd | -| AxiLiteMaster | 14 | 0 | axi/axi-lite/rtl/AxiLiteMaster.vhd | - -## Top Assemblers -| entity | instantiates_count | instantiated_by_count | path | -| --- | --- | --- | --- | -| RssiCore | 13 | 1 | protocols/rssi/v1/rtl/RssiCore.vhd | -| EthMacRxRoCEv2 | 10 | 1 | ethernet/RoCEv2/rtl/EthMacRxRoCEv2.vhd | -| SugoiManagerCore | 10 | 0 | protocols/sugoi/rtl/SugoiManagerCore.vhd | -| Ad9681Readout | 8 | 0 | devices/AnalogDevices/ad9681/7Series/rtl/Ad9681Readout.vhd | -| CoaXPressAxiL | 8 | 1 | protocols/coaxpress/core/rtl/CoaXPressAxiL.vhd | -| EthMacTxRoCEv2 | 8 | 1 | ethernet/RoCEv2/rtl/EthMacTxRoCEv2.vhd | -| Gth7Core | 8 | 2 | xilinx/7Series/gth7/rtl/Gth7Core.vhd | -| RssiCoreWrapper | 8 | 0 | protocols/rssi/v1/rtl/RssiCoreWrapper.vhd | -| Ad9249ReadoutGroup | 7 | 0 | devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd | -| Ad9249ReadoutGroup2 | 7 | 0 | devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd | -| AxiRingBuffer | 7 | 1 | axi/axi4/rtl/AxiRingBuffer.vhd | -| AxiStreamRingBuffer | 7 | 1 | axi/axi-stream/rtl/AxiStreamRingBuffer.vhd | -| ClinkTop | 7 | 0 | protocols/clink/rtl/ClinkTop.vhd | -| CoaXPressRx | 7 | 1 | protocols/coaxpress/core/rtl/CoaXPressRx.vhd | -| FifoAsync | 7 | 8 | base/fifo/rtl/inferred/FifoAsync.vhd | -| GLinkGtx7Core | 7 | 1 | protocols/glink/gtx7/rtl/GLinkGtx7Core.vhd | -| Gtp7Core | 7 | 4 | xilinx/7Series/gtp7/rtl/Gtp7Core.vhd | -| IpV4Engine | 7 | 1 | ethernet/IpV4Engine/rtl/IpV4Engine.vhd | -| Jesd204bRx | 7 | 1 | protocols/jesd204b/rtl/Jesd204bRx.vhd | -| Jesd204bTx | 7 | 1 | protocols/jesd204b/rtl/Jesd204bTx.vhd | - -## Top Leaf Entities -| entity | instantiated_by_count | path | -| --- | --- | --- | -| Synchronizer | 73 | base/sync/rtl/Synchronizer.vhd | -| SynchronizerVector | 41 | base/sync/rtl/SynchronizerVector.vhd | -| AxiStreamPipeline | 38 | axi/axi-stream/rtl/AxiStreamPipeline.vhd | -| AxiLiteCrossbar | 32 | axi/axi-lite/rtl/AxiLiteCrossbar.vhd | -| RstPipeline | 15 | base/general/rtl/RstPipeline.vhd | -| AxiLiteMaster | 14 | axi/axi-lite/rtl/AxiLiteMaster.vhd | -| IoBufWrapper | 14 | xilinx/dummy/IoBufWrapperDummy.vhd | -| Decoder8b10b | 10 | protocols/line-codes/rtl/Decoder8b10b.vhd | -| SimpleDualPortRam | 10 | base/ram/inferred/SimpleDualPortRam.vhd | -| FifoOutputPipeline | 9 | base/fifo/rtl/FifoOutputPipeline.vhd | -| Crc32Parallel | 7 | base/crc/rtl/Crc32Parallel.vhd | -| SimpleDualPortRamXpm | 7 | base/ram/dummy/SimpleDualPortRamXpmDummy.vhd | -| SpiMaster | 7 | protocols/spi/rtl/SpiMaster.vhd | -| Gearbox | 6 | base/general/rtl/Gearbox.vhd | -| SelectIoRxGearboxAligner | 6 | xilinx/general/rtl/SelectIoRxGearboxAligner.vhd | -| ClkOutBufDiff | 5 | xilinx/dummy/ClkOutBufDiffDummy.vhd | -| Pgp3RxGearboxAligner | 5 | protocols/pgp/pgp3/core/rtl/Pgp3RxGearboxAligner.vhd | -| Scrambler | 5 | base/general/rtl/Scrambler.vhd | -| AxiStreamFlush | 4 | axi/axi-stream/rtl/AxiStreamFlush.vhd | -| CRC32Rtl | 4 | base/crc/rtl/CRC32Rtl.vhd | - -## Base Bottom-Up Candidates -| entity | instantiated_by_count | instantiates_count | path | -| --- | --- | --- | --- | -| Synchronizer | 73 | 0 | base/sync/rtl/Synchronizer.vhd | -| SynchronizerVector | 41 | 0 | base/sync/rtl/SynchronizerVector.vhd | -| RstPipeline | 15 | 0 | base/general/rtl/RstPipeline.vhd | -| SimpleDualPortRam | 10 | 0 | base/ram/inferred/SimpleDualPortRam.vhd | -| FifoOutputPipeline | 9 | 0 | base/fifo/rtl/FifoOutputPipeline.vhd | -| Crc32Parallel | 7 | 0 | base/crc/rtl/Crc32Parallel.vhd | -| SimpleDualPortRamXpm | 7 | 0 | base/ram/dummy/SimpleDualPortRamXpmDummy.vhd | -| Gearbox | 6 | 0 | base/general/rtl/Gearbox.vhd | -| Scrambler | 5 | 0 | base/general/rtl/Scrambler.vhd | -| CRC32Rtl | 4 | 0 | base/crc/rtl/CRC32Rtl.vhd | -| Crc32 | 3 | 0 | base/crc/rtl/Crc32.vhd | -| SimpleDualPortRamAlteraMf | 3 | 0 | base/ram/dummy/SimpleDualPortRamAlteraMfDummy.vhd | -| SlvDelay | 3 | 0 | base/delay/rtl/SlvDelay.vhd | -| TrueDualPortRam | 3 | 0 | base/ram/inferred/TrueDualPortRam.vhd | -| FifoRdFsm | 2 | 0 | base/fifo/rtl/inferred/FifoRdFsm.vhd | -| FifoWrFsm | 2 | 0 | base/fifo/rtl/inferred/FifoWrFsm.vhd | -| LutRam | 2 | 0 | base/ram/inferred/LutRam.vhd | -| TrueDualPortRamAlteraMf | 2 | 0 | base/ram/dummy/TrueDualPortRamXpmAlteraMfDummy.vhd | -| TrueDualPortRamXpm | 2 | 0 | base/ram/dummy/TrueDualPortRamXpmDummy.vhd | -| Arbiter | 1 | 0 | base/general/rtl/Arbiter.vhd | - -## Duplicate Entity Names -- `Ad9249Deserializer` - - `devices/AnalogDevices/ad9249/7Series/rtl/Ad9249Deserializer.vhd` - - `devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd` -- `Ad9249ReadoutGroup` - - `devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd` - - `devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd` -- `ClinkDataClk` - - `protocols/clink/7Series/ClinkDataClk.vhd` - - `protocols/clink/UltraScale/ClinkDataClk.vhd` -- `ClinkDataShift` - - `protocols/clink/7Series/ClinkDataShift.vhd` - - `protocols/clink/UltraScale/ClinkDataShift.vhd` -- `ClkOutBufDiff` - - `xilinx/dummy/ClkOutBufDiffDummy.vhd` - - `xilinx/general/rtl/ClkOutBufDiff.vhd` -- `ClkOutBufSingle` - - `xilinx/dummy/ClkOutBufSingleDummy.vhd` - - `xilinx/general/rtl/ClkOutBufSingle.vhd` -- `ClockManagerUltraScale` - - `xilinx/UltraScale/clocking/rtl/ClockManagerUltraScale.vhd` - - `xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd` -- `CoaXPressOverFiberGthUsIpWrapper` - - `protocols/coaxpress/gthUs/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd` - - `protocols/coaxpress/gthUs+/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd` -- `CoaxpressOverFiberGthUs` - - `protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUs.vhd` - - `protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUs.vhd` -- `CoaxpressOverFiberGthUsQpll` - - `protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUsQpll.vhd` - - `protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUsQpll.vhd` -- `DS2411Core` - - `devices/Maxim/dummy/DS2411CoreDummy.vhd` - - `devices/Maxim/rtl/DS2411Core.vhd` -- `DeviceDna` - - `xilinx/dummy/DeviceDnaDummy.vhd` - - `xilinx/general/rtl/DeviceDna.vhd` -- `FifoAlteraMf` - - `base/fifo/rtl/altera/FifoAlteraMf.vhd` - - `base/fifo/rtl/dummy/FifoAlteraMfDummy.vhd` -- `FifoXpm` - - `base/fifo/rtl/dummy/FifoXpmDummy.vhd` - - `base/fifo/rtl/xilinx/FifoXpm.vhd` -- `GigEthGthUltraScale` - - `ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd` - - `ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd` -- `GigEthGthUltraScaleWrapper` - - `ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd` - - `ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd` -- `GthUltraScaleQuadPll` - - `xilinx/UltraScale/gthUs/rtl/GthUltraScaleQuadPll.vhd` - - `xilinx/UltraScale+/gthUs+/rtl/GthUltraScaleQuadPll.vhd` -- `Idelaye3Wrapper` - - `xilinx/7Series/dummy/Idelaye3WrapperDummy.vhd` - - `xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd` -- `InputBufferReg` - - `xilinx/7Series/general/rtl/InputBufferReg.vhd` - - `xilinx/UltraScale/general/rtl/InputBufferReg.vhd` -- `IoBufWrapper` - - `xilinx/dummy/IoBufWrapperDummy.vhd` - - `xilinx/general/rtl/IoBufWrapper.vhd` -- `Iprog` - - `xilinx/dummy/IprogDummy.vhd` - - `xilinx/general/rtl/Iprog.vhd` -- `MicroblazeBasicCoreWrapper` - - `xilinx/general/microblaze/bypass/MicroblazeBasicCoreWrapper.vhd` - - `xilinx/general/microblaze/generate/MicroblazeBasicCoreWrapper.vhd` -- `Odelaye3Wrapper` - - `xilinx/7Series/dummy/Odelaye3WrapperDummy.vhd` - - `xilinx/UltraScale/general/rtl/Odelaye3Wrapper.vhd` -- `OutputBufferReg` - - `xilinx/7Series/general/rtl/OutputBufferReg.vhd` - - `xilinx/UltraScale/general/rtl/OutputBufferReg.vhd` - - `xilinx/dummy/OutputBufferRegDummy.vhd` -- `Pgp2bGthUltra` - - `protocols/pgp/pgp2b/gthUltraScale/rtl/Pgp2bGthUltra.vhd` - - `protocols/pgp/pgp2b/gthUltraScale+/rtl/Pgp2bGthUltra.vhd` -- `Pgp3GthUs` - - `protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUs.vhd` - - `protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUs.vhd` -- `Pgp3GthUsIpWrapper` - - `protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd` - - `protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsIpWrapper.vhd` -- `Pgp3GthUsQpll` - - `protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd` - - `protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsQpll.vhd` -- `Pgp3GthUsWrapper` - - `protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsWrapper.vhd` - - `protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsWrapper.vhd` -- `Pgp4GthUs` - - `protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUs.vhd` - - `protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUs.vhd` -- `Pgp4GthUsWrapper` - - `protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUsWrapper.vhd` - - `protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUsWrapper.vhd` -- `PgpGthCoreWrapper` - - `protocols/pgp/pgp2b/gthUltraScale/rtl/PgpGthCoreWrapper.vhd` - - `protocols/pgp/pgp2b/gthUltraScale+/rtl/PgpGthCoreWrapper.vhd` -- `RogueSideBand` - - `axi/simlink/ghdl/RogueSideBand.vhd` - - `axi/simlink/sim/RogueSideBand.vhd` -- `RogueTcpMemory` - - `axi/simlink/ghdl/RogueTcpMemory.vhd` - - `axi/simlink/sim/RogueTcpMemory.vhd` -- `RogueTcpStream` - - `axi/simlink/ghdl/RogueTcpStream.vhd` - - `axi/simlink/sim/RogueTcpStream.vhd` -- `SaltRxDeser` - - `protocols/salt/rtl/7Series/SaltRxDeser.vhd` - - `protocols/salt/rtl/UltraScale/SaltRxDeser.vhd` -- `SaltTxSer` - - `protocols/salt/rtl/7Series/SaltTxSer.vhd` - - `protocols/salt/rtl/UltraScale/SaltTxSer.vhd` -- `SimpleDualPortRamXpm` - - `base/ram/dummy/SimpleDualPortRamXpmDummy.vhd` - - `base/ram/xilinx/SimpleDualPortRamXpm.vhd` -- `SinglePortRamPrimitive` - - `base/ram/dummy/SinglePortRamPrimitiveDummy.vhd` - - `base/ram/xilinx/SinglePortRamPrimitive.vhd` -- `Srl16Delay` - - `xilinx/dummy/Srl16DelayDummy.vhd` - - `xilinx/general/rtl/Srl16Delay.vhd` -- `SugoiManagerRx7Series` - - `protocols/sugoi/rtl/7Series/SugoiManagerRx7Series.vhd` - - `protocols/sugoi/rtl/dummy/SugoiManagerRx7SeriesDummy.vhd` -- `SugoiManagerRxUltrascale` - - `protocols/sugoi/rtl/UltraScale/SugoiManagerRxUltrascale.vhd` - - `protocols/sugoi/rtl/dummy/SugoiManagerRxUltrascaleDummy.vhd` -- `TenGigEthGthUltraScale` - - `ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd` - - `ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd` -- `TenGigEthGthUltraScaleClk` - - `ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleClk.vhd` - - `ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleClk.vhd` -- `TenGigEthGthUltraScaleRst` - - `ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleRst.vhd` - - `ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleRst.vhd` -- `TenGigEthGthUltraScaleWrapper` - - `ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd` - - `ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd` -- `TrueDualPortRamXpm` - - `base/ram/dummy/TrueDualPortRamXpmDummy.vhd` - - `base/ram/xilinx/TrueDualPortRamXpm.vhd` -- `UdpDebugBridge` - - `xilinx/xvc-udp/dcp/7Series/Impl/images/UdpDebugBridge_stub.vhd` - - `xilinx/xvc-udp/dcp/7Series/Stub/images/UdpDebugBridge_stub.vhd` - - `xilinx/xvc-udp/dcp/UltraScale/Impl/images/UdpDebugBridge_stub.vhd` - - `xilinx/xvc-udp/dcp/UltraScale/Stub/images/UdpDebugBridge_stub.vhd` - - `xilinx/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd` - - `xilinx/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd` -- `UdpDebugBridgeWrapper` - - `xilinx/xvc-udp/dcp/core/UdpDebugBridgeWrapper.vhd` - - `xilinx/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd` -- `XauiGthUltraScale` - - `ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd` - - `ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd` -- `XauiGthUltraScaleWrapper` - - `ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd` - - `ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd` diff --git a/docs/_meta/rtl_phase1_queue.json b/docs/_meta/rtl_phase1_queue.json deleted file mode 100644 index a77d778b6b..0000000000 --- a/docs/_meta/rtl_phase1_queue.json +++ /dev/null @@ -1,5874 +0,0 @@ -{ - "generated_from": { - "scan_dirs": [ - "base", - "axi", - "dsp", - "protocols", - "ethernet", - "devices", - "xilinx" - ], - "source_graph_script": "scripts/build_rtl_instantiation_graph.py", - "override_file": "docs/_meta/rtl_phase1_queue_overrides.json", - "queue_policy": "Path-qualified, phase-1 filtered, bottom-up instantiation order" - }, - "summary": { - "phase1_module_count": 219, - "phase1_edge_count": 392, - "phase1_bottom_up_layers": 10, - "deferred_module_count": 632, - "unresolved_phase1_edges": 0, - "applied_order_overrides": 0 - }, - "phase1_rules": { - "force_include_entities": [], - "force_include_paths": [], - "deferred_subsystems": [ - { - "name": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "name": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "name": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "name": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - } - ], - "deferred_entities": [ - { - "entity": "LutFixedDelay", - "reason": "Depends on SinglePortRamPrimitive under the current open-source flow." - } - ], - "deferred_paths": [], - "deferred_path_substrings": [ - { - "pattern": "axi/simlink/", - "reason": "Simulation support models are not part of the synthesizable phase-1 queue." - }, - { - "pattern": "/sim/", - "reason": "Simulation-only support modules are not part of the synthesizable phase-1 queue." - }, - { - "pattern": "/dummy/", - "reason": "Dummy-backed variants are deferred from the phase-1 executable queue." - }, - { - "pattern": "/altera/", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "/xilinx/", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "7Series", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "UltraScale", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "UltraScale+", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "/gth", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gtp", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gty", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gtx", - "reason": "GT-family implementation branches are deferred in phase 1." - } - ], - "preferred_paths_by_entity": {}, - "order_overrides": [] - }, - "applied_order_overrides": [], - "queue": [ - { - "order": 1, - "bottom_up_layer": 0, - "entity": "AxiLiteCrossbar", - "path": "axi/axi-lite/rtl/AxiLiteCrossbar.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 3 - }, - { - "order": 2, - "bottom_up_layer": 0, - "entity": "AxiLiteMaster", - "path": "axi/axi-lite/rtl/AxiLiteMaster.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 6 - }, - { - "order": 3, - "bottom_up_layer": 0, - "entity": "AxiLiteRegs", - "path": "axi/axi-lite/rtl/AxiLiteRegs.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 4, - "bottom_up_layer": 0, - "entity": "AxiLiteRespTimer", - "path": "axi/axi-lite/rtl/AxiLiteRespTimer.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 5, - "bottom_up_layer": 0, - "entity": "AxiLiteSlave", - "path": "axi/axi-lite/rtl/AxiLiteSlave.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 6, - "bottom_up_layer": 0, - "entity": "AxiLiteWriteFilter", - "path": "axi/axi-lite/rtl/AxiLiteWriteFilter.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 7, - "bottom_up_layer": 0, - "entity": "AxiVersion", - "path": "axi/axi-lite/rtl/AxiVersion.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 8, - "bottom_up_layer": 0, - "entity": "AxiStreamCombiner", - "path": "axi/axi-stream/rtl/AxiStreamCombiner.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 9, - "bottom_up_layer": 0, - "entity": "AxiStreamFlush", - "path": "axi/axi-stream/rtl/AxiStreamFlush.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 10, - "bottom_up_layer": 0, - "entity": "AxiStreamGearboxPack", - "path": "axi/axi-stream/rtl/AxiStreamGearboxPack.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 11, - "bottom_up_layer": 0, - "entity": "AxiStreamGearboxUnpack", - "path": "axi/axi-stream/rtl/AxiStreamGearboxUnpack.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 12, - "bottom_up_layer": 0, - "entity": "AxiStreamPipeline", - "path": "axi/axi-stream/rtl/AxiStreamPipeline.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 18 - }, - { - "order": 13, - "bottom_up_layer": 0, - "entity": "AxiStreamSplitter", - "path": "axi/axi-stream/rtl/AxiStreamSplitter.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 14, - "bottom_up_layer": 0, - "entity": "AxiStreamPkgWrapper", - "path": "axi/axi-stream/wrappers/AxiStreamPkgWrapper.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 15, - "bottom_up_layer": 0, - "entity": "AxiReadPathMux", - "path": "axi/axi4/rtl/AxiReadPathMux.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - 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"AxiStreamScatterGatherIpIntegrator", - "path": "axi/axi-stream/ip_integrator/AxiStreamScatterGatherIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 4, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 166, - "bottom_up_layer": 5, - "entity": "AxiStreamFifoV2", - "path": "axi/axi-stream/rtl/AxiStreamFifoV2.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 5, - "instantiated_by_in_phase1_count": 7 - }, - { - "order": 167, - "bottom_up_layer": 5, - "entity": "AxiMemTesterIpIntegrator", - "path": "axi/axi4/ip_integrator/AxiMemTesterIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 168, - "bottom_up_layer": 5, - "entity": "AxiReadPathFifo", - "path": "axi/axi4/rtl/AxiReadPathFifo.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 3 - }, - { - "order": 169, - "bottom_up_layer": 5, - "entity": "AxiWritePathFifo", - "path": "axi/axi4/rtl/AxiWritePathFifo.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 3 - }, - { - "order": 170, - "bottom_up_layer": 5, - "entity": "SlvArraytoAxiLiteIpIntegrator", - "path": "axi/bridge/ip_integrator/SlvArraytoAxiLiteIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 171, - "bottom_up_layer": 5, - "entity": "AxiStreamDmaV2DescIpIntegrator", - "path": "axi/dma/ip_integrator/AxiStreamDmaV2DescIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 172, - "bottom_up_layer": 5, - "entity": "AxiStreamDmaV2FifoIpIntegrator", - "path": "axi/dma/ip_integrator/AxiStreamDmaV2FifoIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 5, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 173, - "bottom_up_layer": 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"path": "axi/axi4/rtl/AxiRingBuffer.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 6, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 190, - "bottom_up_layer": 6, - "entity": "AxiWriteEmulate", - "path": "axi/axi4/rtl/AxiWriteEmulate.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 191, - "bottom_up_layer": 6, - "entity": "AxiStreamDmaV2IpIntegrator", - "path": "axi/dma/ip_integrator/AxiStreamDmaV2IpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 192, - "bottom_up_layer": 6, - "entity": "AxiStreamDmaRingRead", - "path": "axi/dma/rtl/v1/AxiStreamDmaRingRead.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 5, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 193, - "bottom_up_layer": 6, - "entity": "AxiStreamDmaWrite", - "path": "axi/dma/rtl/v1/AxiStreamDmaWrite.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 4 - }, - { - "order": 194, - "bottom_up_layer": 6, - "entity": "SyncStatusVector", - "path": "base/sync/rtl/SyncStatusVector.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 195, - "bottom_up_layer": 6, - "entity": "SyncTrigRateVector", - "path": "base/sync/rtl/SyncTrigRateVector.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 196, - "bottom_up_layer": 6, - "entity": "SyncTrigRateWrapper", - "path": "base/sync/wrappers/SyncTrigRateWrapper.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 197, - "bottom_up_layer": 6, - "entity": "SynchronizerOneShotCntVectorFlatWrapper", - "path": "base/sync/wrappers/SynchronizerOneShotCntVectorFlatWrapper.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 198, - "bottom_up_layer": 7, - "entity": "AxiLiteRamSyncStatusVector", - "path": "axi/axi-lite/rtl/AxiLiteRamSyncStatusVector.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 199, - "bottom_up_layer": 7, - "entity": "AxiStreamBatchingFifoIpIntegrator", - "path": "axi/axi-stream/ip_integrator/AxiStreamBatchingFifoIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 4, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 200, - "bottom_up_layer": 7, - "entity": "AxiStreamMonIpIntegrator", - "path": "axi/axi-stream/ip_integrator/AxiStreamMonIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 201, - "bottom_up_layer": 7, - "entity": "AxiStreamRingBufferIpIntegrator", - "path": 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queue." - }, - { - "entity": "SimpleDualPortRamXpm", - "path": "base/ram/xilinx/SimpleDualPortRamXpm.vhd", - "subsystem": "base", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "SinglePortRamPrimitive", - "path": "base/ram/xilinx/SinglePortRamPrimitive.vhd", - "subsystem": "base", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "TrueDualPortRamXpm", - "path": "base/ram/xilinx/TrueDualPortRamXpm.vhd", - "subsystem": "base", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "LeapXcvr", - "path": "devices/Amphenol/LeapXcvr/rtl/LeapXcvr.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "LeapXcvrCdrDisable", - "path": "devices/Amphenol/LeapXcvr/rtl/LeapXcvrCdrDisable.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "LeapXcvrCore", - "path": "devices/Amphenol/LeapXcvr/rtl/LeapXcvrCore.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd5541Core", - "path": "devices/AnalogDevices/ad5541/rtl/AxiAd5541Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd5780Core", - "path": "devices/AnalogDevices/ad5780/rtl/AxiAd5780Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd5780Reg", - "path": "devices/AnalogDevices/ad5780/rtl/AxiAd5780Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd5780Ser", - "path": "devices/AnalogDevices/ad5780/rtl/AxiAd5780Ser.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249ConfigNoPullup", - "path": "devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ConfigNoPullup.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249Deserializer", - "path": "devices/AnalogDevices/ad9249/7Series/rtl/Ad9249Deserializer.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249ReadoutGroup", - "path": "devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249Deserializer", - "path": "devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249ReadoutGroup", - "path": "devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249ReadoutGroup2", - "path": "devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249Config", - "path": "devices/AnalogDevices/ad9249/core/Ad9249Config.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "StreamPatternTester", - "path": "devices/AnalogDevices/ad9249/core/StreamPatternTester.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467Core", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467Deser", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467Deser.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467DeserBit", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467DeserBit.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467Mon", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467Mon.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467Pll", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467Pll.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467Reg", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467Spi", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467Spi.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681Deserializer", - "path": "devices/AnalogDevices/ad9681/7Series/rtl/Ad9681Deserializer.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681Readout", - "path": "devices/AnalogDevices/ad9681/7Series/rtl/Ad9681Readout.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681ReadoutManual", - "path": "devices/AnalogDevices/ad9681/7Series/rtl/Ad9681ReadoutManual.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681Config", - "path": "devices/AnalogDevices/ad9681/core/Ad9681Config.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681", - "path": "devices/AnalogDevices/ad9681/sim/Ad9681.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681Serializer", - "path": "devices/AnalogDevices/ad9681/sim/Ad9681Serializer.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AdiConfigSlave", - "path": "devices/AnalogDevices/general/rtl/AdiConfigSlave.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiLtc2270Core", - "path": "devices/Linear/lct2270/rtl/AxiLtc2270Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiLtc2270Deser", - "path": "devices/Linear/lct2270/rtl/AxiLtc2270Deser.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiLtc2270DeserBit", - "path": "devices/Linear/lct2270/rtl/AxiLtc2270DeserBit.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiLtc2270Reg", - "path": "devices/Linear/lct2270/rtl/AxiLtc2270Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sgmii88E1111Mdio", - "path": "devices/Marvell/Sgmii88E1111/core/Sgmii88E1111Mdio.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sgmii88E1111LvdsUltraScale", - "path": "devices/Marvell/Sgmii88E1111/lvdsUltraScale/Sgmii88E1111LvdsUltraScale.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DS2411Core", - "path": "devices/Maxim/dummy/DS2411CoreDummy.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DS2411Core", - "path": "devices/Maxim/rtl/DS2411Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Max5443", - "path": "devices/Maxim/rtl/Max5443.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Max5443DacCntrl", - "path": "devices/Maxim/rtl/Max5443DacCntrl.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiSy56040Core", - "path": "devices/Microchip/sy56040/rtl/AxiSy56040Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiSy56040Reg", - "path": "devices/Microchip/sy56040/rtl/AxiSy56040Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sy89297", - "path": "devices/Microchip/sy89297/rtl/Sy89297.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronMt28ewCore", - "path": "devices/Micron/mt28ew/rtl/AxiMicronMt28ewCore.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronMt28ewReg", - "path": "devices/Micron/mt28ew/rtl/AxiMicronMt28ewReg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronN25QCore", - "path": "devices/Micron/n25q/rtl/AxiMicronN25QCore.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronN25QReg", - "path": "devices/Micron/n25q/rtl/AxiMicronN25QReg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronP30Core", - "path": "devices/Micron/p30/rtl/AxiMicronP30Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronP30Reg", - "path": "devices/Micron/p30/rtl/AxiMicronP30Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sc18Is602", - "path": "devices/Nxp/Sc18Is602/rtl/Sc18Is602.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sc18Is602Core", - "path": "devices/Nxp/Sc18Is602/rtl/Sc18Is602Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Si5324", - "path": "devices/Silabs/si5324/rtl/Si5324.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Si5345", - "path": "devices/Silabs/si5345/rtl/Si5345.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Si5394I2c", - "path": "devices/Silabs/si5394/rtl/Si5394I2c.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Si5394I2cCore", - "path": "devices/Silabs/si5394/rtl/Si5394I2cCore.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Lmk048Base", - "path": "devices/Ti/Lmk048Base/rtl/Lmk048Base.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "adc32rf45", - "path": "devices/Ti/adc32rf45/rtl/adc32rf45.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAds42lb69Core", - "path": "devices/Ti/ads42lb69/rtl/AxiAds42lb69Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAds42lb69Deser", - "path": "devices/Ti/ads42lb69/rtl/AxiAds42lb69Deser.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAds42lb69DeserBit", - "path": "devices/Ti/ads42lb69/rtl/AxiAds42lb69DeserBit.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAds42lb69Pll", - "path": "devices/Ti/ads42lb69/rtl/AxiAds42lb69Pll.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAds42lb69Reg", - "path": "devices/Ti/ads42lb69/rtl/AxiAds42lb69Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ads54j60", - "path": "devices/Ti/ads54j60/rtl/ads54j60.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiDac7654Core", - "path": "devices/Ti/dac7654/rtl/AxiDac7654Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiDac7654Reg", - "path": "devices/Ti/dac7654/rtl/AxiDac7654Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiDac7654Spi", - "path": "devices/Ti/dac7654/rtl/AxiDac7654Spi.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SgmiiDp83867Mdio", - "path": "devices/Ti/dp83867/core/SgmiiDp83867Mdio.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SgmiiDp83867LvdsUltraScale", - "path": "devices/Ti/dp83867/lvdsUltraScale/SgmiiDp83867LvdsUltraScale.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiXcf128Core", - "path": "devices/Xilinx/xcf128/rtl/AxiXcf128Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiXcf128Reg", - "path": "devices/Xilinx/xcf128/rtl/AxiXcf128Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "QsfpCdrDisable", - "path": "devices/transceivers/rtl/QsfpCdrDisable.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sff8472", - "path": "devices/transceivers/rtl/Sff8472.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sff8472Core", - "path": "devices/transceivers/rtl/Sff8472Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "add3", - "path": "dsp/xilinx/fixed/Add3.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "CfixedAccumulator", - "path": "dsp/xilinx/fixed/CfixedAccumulator.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "cfixedDelay", - "path": "dsp/xilinx/fixed/CfixedDelay.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "cfixedMult", - "path": "dsp/xilinx/fixed/CfixedMult.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "cfixedMultAdd", - "path": "dsp/xilinx/fixed/CfixedMultAdd.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "CfixedPreAddMult", - "path": "dsp/xilinx/fixed/CfixedPreAddMult.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "csa3", - "path": "dsp/xilinx/fixed/Csa3.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "FirAverage", - "path": "dsp/xilinx/fixed/FirAverage.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "IirSimple", - "path": "dsp/xilinx/fixed/IirSimple.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "SfixedAccumulator", - "path": "dsp/xilinx/fixed/SfixedAccumulator.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "sfixedDelay", - "path": "dsp/xilinx/fixed/SfixedDelay.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "sfixedMult", - "path": "dsp/xilinx/fixed/SfixedMult.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "sfixedMultAdd", - "path": "dsp/xilinx/fixed/SfixedMultAdd.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "sfixedPreAddMultAdd", - "path": "dsp/xilinx/fixed/SfixedPreAddMultAdd.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "SinCosLut", - "path": "dsp/xilinx/fixed/SinCosLut.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "SinCosTaylor", - "path": "dsp/xilinx/fixed/SinCosTaylor.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "DspXor", - "path": "dsp/xilinx/logic/DspXor.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "Caui4GtyIpWrapper", - "path": "ethernet/Caui4Core/gtyUltraScale+/rtl/Caui4GtyIpWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthCrc32Parallel", - "path": "ethernet/EthMacCore/rtl/EthCrc32Parallel.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacFlowCtrl", - "path": "ethernet/EthMacCore/rtl/EthMacFlowCtrl.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRx", - "path": "ethernet/EthMacCore/rtl/EthMacRx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxBypass", - "path": "ethernet/EthMacCore/rtl/EthMacRxBypass.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxCsum", - "path": "ethernet/EthMacCore/rtl/EthMacRxCsum.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxFifo", - "path": "ethernet/EthMacCore/rtl/EthMacRxFifo.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxFilter", - "path": "ethernet/EthMacCore/rtl/EthMacRxFilter.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxImport", - "path": "ethernet/EthMacCore/rtl/EthMacRxImport.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxImportGmii", - "path": "ethernet/EthMacCore/rtl/EthMacRxImportGmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxImportXgmii", - "path": "ethernet/EthMacCore/rtl/EthMacRxImportXgmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxImportXlgmii", - "path": "ethernet/EthMacCore/rtl/EthMacRxImportXlgmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxPause", - "path": "ethernet/EthMacCore/rtl/EthMacRxPause.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxShift", - "path": "ethernet/EthMacCore/rtl/EthMacRxShift.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTop", - "path": "ethernet/EthMacCore/rtl/EthMacTop.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTx", - "path": "ethernet/EthMacCore/rtl/EthMacTx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxBypass", - "path": "ethernet/EthMacCore/rtl/EthMacTxBypass.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxCsum", - "path": "ethernet/EthMacCore/rtl/EthMacTxCsum.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxExport", - "path": "ethernet/EthMacCore/rtl/EthMacTxExport.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxExportGmii", - "path": "ethernet/EthMacCore/rtl/EthMacTxExportGmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxExportXgmii", - "path": "ethernet/EthMacCore/rtl/EthMacTxExportXgmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxExportXlgmii", - "path": "ethernet/EthMacCore/rtl/EthMacTxExportXlgmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxFifo", - "path": "ethernet/EthMacCore/rtl/EthMacTxFifo.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxPause", - "path": "ethernet/EthMacCore/rtl/EthMacTxPause.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxShift", - "path": "ethernet/EthMacCore/rtl/EthMacTxShift.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthReg", - "path": "ethernet/GigEthCore/core/rtl/GigEthReg.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGth7", - "path": "ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGth7Wrapper", - "path": "ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGthUltraScale", - "path": "ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGthUltraScaleWrapper", - "path": "ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGthUltraScale", - "path": "ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGthUltraScaleWrapper", - "path": "ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtp7", - "path": "ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtp7Wrapper", - "path": "ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtx7", - "path": "ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtx7Wrapper", - "path": "ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtyUltraScale", - "path": "ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtyUltraScaleWrapper", - "path": "ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthLvdsUltraScale", - "path": "ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ArpEngine", - "path": "ethernet/IpV4Engine/rtl/ArpEngine.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IcmpEngine", - "path": "ethernet/IpV4Engine/rtl/IcmpEngine.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IgmpV2Engine", - "path": "ethernet/IpV4Engine/rtl/IgmpV2Engine.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IpV4Engine", - "path": "ethernet/IpV4Engine/rtl/IpV4Engine.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IpV4EngineDeMux", - "path": "ethernet/IpV4Engine/rtl/IpV4EngineDeMux.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IpV4EngineRx", - "path": "ethernet/IpV4Engine/rtl/IpV4EngineRx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IpV4EngineTx", - "path": "ethernet/IpV4Engine/rtl/IpV4EngineTx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RawEthFramer", - "path": "ethernet/RawEthFramer/rtl/RawEthFramer.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RawEthFramerRx", - "path": "ethernet/RawEthFramer/rtl/RawEthFramerRx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RawEthFramerTx", - "path": "ethernet/RawEthFramer/rtl/RawEthFramerTx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RawEthFramerWrapper", - "path": "ethernet/RawEthFramer/rtl/RawEthFramerWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacCrcAxiStreamWrapperRecv", - "path": "ethernet/RoCEv2/rtl/EthMacCrcAxiStreamWrapperRecv.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacCrcAxiStreamWrapperSend", - "path": "ethernet/RoCEv2/rtl/EthMacCrcAxiStreamWrapperSend.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacPrepareForICrc", - "path": "ethernet/RoCEv2/rtl/EthMacPrepareForICrc.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxCheckICrc", - "path": "ethernet/RoCEv2/rtl/EthMacRxCheckICrc.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxRoCEv2", - "path": "ethernet/RoCEv2/rtl/EthMacRxRoCEv2.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxRoCEv2", - "path": "ethernet/RoCEv2/rtl/EthMacTxRoCEv2.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RoceConfigurator", - "path": "ethernet/RoCEv2/rtl/RoceConfigurator.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RoceEngineWrapper", - "path": "ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RoceResizeAndSwap", - "path": "ethernet/RoCEv2/rtl/RoceResizeAndSwap.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthReg", - "path": "ethernet/TenGigEthCore/core/rtl/TenGigEthReg.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthRst", - "path": "ethernet/TenGigEthCore/core/rtl/TenGigEthRst.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGth7", - "path": "ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGth7Clk", - "path": "ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Clk.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGth7Wrapper", - "path": "ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScale", - "path": "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleClk", - "path": "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleClk.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleRst", - "path": "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleRst.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleWrapper", - "path": "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScale", - "path": "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleClk", - "path": "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleClk.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleRst", - "path": "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleRst.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleWrapper", - "path": "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtx7", - "path": "ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtx7Clk", - "path": "ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Clk.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtx7Wrapper", - "path": "ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtyUltraScale", - "path": "ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtyUltraScaleClk", - "path": "ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleClk.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtyUltraScaleRst", - "path": "ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleRst.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtyUltraScaleWrapper", - "path": "ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ArpIpTable", - "path": "ethernet/UdpEngine/rtl/ArpIpTable.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngine", - "path": "ethernet/UdpEngine/rtl/UdpEngine.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngineArp", - "path": "ethernet/UdpEngine/rtl/UdpEngineArp.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngineDhcp", - "path": "ethernet/UdpEngine/rtl/UdpEngineDhcp.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngineRx", - "path": "ethernet/UdpEngine/rtl/UdpEngineRx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngineTx", - "path": "ethernet/UdpEngine/rtl/UdpEngineTx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngineWrapper", - "path": "ethernet/UdpEngine/rtl/UdpEngineWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiReg", - "path": "ethernet/XauiCore/core/rtl/XauiReg.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGth7", - "path": "ethernet/XauiCore/gth7/rtl/XauiGth7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGth7Core", - "path": "ethernet/XauiCore/gth7/rtl/XauiGth7Core.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGth7Wrapper", - "path": "ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGthUltraScale", - "path": "ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGthUltraScaleWrapper", - "path": "ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGthUltraScale", - "path": "ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGthUltraScaleWrapper", - "path": "ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGtx7", - "path": "ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGtx7Core", - "path": "ethernet/XauiCore/gtx7/rtl/XauiGtx7Core.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGtx7Wrapper", - "path": "ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGtyUltraScale", - "path": "ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGtyUltraScaleWrapper", - "path": "ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamBatcher", - "path": "protocols/batcher/rtl/AxiStreamBatcher.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamBatcherAxil", - "path": "protocols/batcher/rtl/AxiStreamBatcherAxil.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamBatcherEventBuilder", - "path": "protocols/batcher/rtl/AxiStreamBatcherEventBuilder.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkDataClk", - "path": "protocols/clink/7Series/ClinkDataClk.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkDataShift", - "path": "protocols/clink/7Series/ClinkDataShift.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkDataClk", - "path": "protocols/clink/UltraScale/ClinkDataClk.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkDataShift", - "path": "protocols/clink/UltraScale/ClinkDataShift.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkCtrl", - "path": "protocols/clink/rtl/ClinkCtrl.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkData", - "path": "protocols/clink/rtl/ClinkData.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkFraming", - "path": "protocols/clink/rtl/ClinkFraming.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkReg", - "path": "protocols/clink/rtl/ClinkReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkTop", - "path": "protocols/clink/rtl/ClinkTop.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkUart", - "path": "protocols/clink/rtl/ClinkUart.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkUartThrottle", - "path": "protocols/clink/rtl/ClinkUartThrottle.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressAxiL", - "path": "protocols/coaxpress/core/rtl/CoaXPressAxiL.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressConfig", - "path": "protocols/coaxpress/core/rtl/CoaXPressConfig.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressCore", - "path": "protocols/coaxpress/core/rtl/CoaXPressCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressEventAckMsg", - "path": "protocols/coaxpress/core/rtl/CoaXPressEventAckMsg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberBridge", - "path": "protocols/coaxpress/core/rtl/CoaXPressOverFiberBridge.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberBridgeRx", - "path": "protocols/coaxpress/core/rtl/CoaXPressOverFiberBridgeRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberBridgeTx", - "path": "protocols/coaxpress/core/rtl/CoaXPressOverFiberBridgeTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressRx", - "path": "protocols/coaxpress/core/rtl/CoaXPressRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressRxHsFsm", - "path": "protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressRxLane", - "path": "protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressRxLaneMux", - "path": "protocols/coaxpress/core/rtl/CoaXPressRxLaneMux.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressRxWordPacker", - "path": "protocols/coaxpress/core/rtl/CoaXPressRxWordPacker.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressTx", - "path": "protocols/coaxpress/core/rtl/CoaXPressTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressTxLsFsm", - "path": "protocols/coaxpress/core/rtl/CoaXPressTxLsFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberGthUsIpWrapper", - "path": "protocols/coaxpress/gthUs+/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGthUs", - "path": "protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGthUsQpll", - "path": "protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberGthUsIpWrapper", - "path": "protocols/coaxpress/gthUs/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGthUs", - "path": "protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGthUsQpll", - "path": "protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberGtyUsIpWrapper", - "path": "protocols/coaxpress/gtyUs+/rtl/CoaXPressOverFiberGtyUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGtyUs", - "path": "protocols/coaxpress/gtyUs+/rtl/CoaxpressOverFiberGtyUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGtyUsQpll", - "path": "protocols/coaxpress/gtyUs+/rtl/CoaxpressOverFiberGtyUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EventFrameSequencerDemux", - "path": "protocols/event-frame-sequencer/rtl/EventFrameSequencerDemux.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EventFrameSequencerMux", - "path": "protocols/event-frame-sequencer/rtl/EventFrameSequencerMux.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EventFrameSequencerWrapper", - "path": "protocols/event-frame-sequencer/wrappers/EventFrameSequencerWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkDecoder", - "path": "protocols/glink/core/rtl/GLinkDecoder.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkEncoder", - "path": "protocols/glink/core/rtl/GLinkEncoder.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkTxToRx", - "path": "protocols/glink/core/rtl/GLinkTxToRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkGtp7FixedLat", - "path": "protocols/glink/gtp7/rtl/GLinkGtp7FixedLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkGtx7Core", - "path": "protocols/glink/gtx7/rtl/GLinkGtx7Core.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkGtx7FixedLat", - "path": "protocols/glink/gtx7/rtl/GLinkGtx7FixedLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkGtx7RxRst", - "path": "protocols/glink/gtx7/rtl/GLinkGtx7RxRst.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HammingEccDecoder", - "path": "protocols/hamming-ecc/rtl/HammingEccDecoder.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HammingEccEncoder", - "path": "protocols/hamming-ecc/rtl/HammingEccEncoder.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HammingEccWrapper", - "path": "protocols/hamming-ecc/wrappers/HammingEccWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspAxiL", - "path": "protocols/htsp/core/rtl/HtspAxiL.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspCore", - "path": "protocols/htsp/core/rtl/HtspCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspRx", - "path": "protocols/htsp/core/rtl/HtspRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspRxFifo", - "path": "protocols/htsp/core/rtl/HtspRxFifo.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspTx", - "path": "protocols/htsp/core/rtl/HtspTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspTxFifo", - "path": "protocols/htsp/core/rtl/HtspTxFifo.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspCaui4Gty", - "path": "protocols/htsp/gtyUs+/rtl/HtspCaui4Gty.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiI2cEeprom", - "path": "protocols/i2c/axi/AxiI2cEeprom.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiI2cEepromCore", - "path": "protocols/i2c/axi/AxiI2cEepromCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiI2cRegMaster", - "path": "protocols/i2c/axi/AxiI2cRegMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiI2cRegMasterCore", - "path": "protocols/i2c/axi/AxiI2cRegMasterCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLiteCrossbarI2cMux", - "path": "protocols/i2c/axi/AxiLiteCrossbarI2cMux.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cMaster", - "path": "protocols/i2c/rtl/I2cMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRegMaster", - "path": "protocols/i2c/rtl/I2cRegMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRegMasterAxiBridge", - "path": "protocols/i2c/rtl/I2cRegMasterAxiBridge.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRegMasterMux", - "path": "protocols/i2c/rtl/I2cRegMasterMux.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRegSlave", - "path": "protocols/i2c/rtl/I2cRegSlave.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cSlave", - "path": "protocols/i2c/rtl/I2cSlave.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2c_master_bit_ctrl", - "path": "protocols/i2c/rtl/i2c_master_bit_ctrl.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2c_master_byte_ctrl", - "path": "protocols/i2c/rtl/i2c_master_byte_ctrl.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2c2ahb", - "path": "protocols/i2c/rtl/orig/i2c2ahb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2c2ahb_apb", - "path": "protocols/i2c/rtl/orig/i2c2ahb_apb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2c2ahbx", - "path": "protocols/i2c/rtl/orig/i2c2ahbx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2cmst", - "path": "protocols/i2c/rtl/orig/i2cmst.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2cmst_gen", - "path": "protocols/i2c/rtl/orig/i2cmst_gen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2cslv", - "path": "protocols/i2c/rtl/orig/i2cslv.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRamSlave", - "path": "protocols/i2c/sim/I2cRamSlave.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRegTb", - "path": "protocols/i2c/sim/I2cRegTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd16bTo32b", - "path": "protocols/jesd204b/rtl/Jesd16bTo32b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd204bRx", - "path": "protocols/jesd204b/rtl/Jesd204bRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd204bTx", - "path": "protocols/jesd204b/rtl/Jesd204bTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd32bTo16b", - "path": "protocols/jesd204b/rtl/Jesd32bTo16b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd32bTo64b", - "path": "protocols/jesd204b/rtl/Jesd32bTo64b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd64bTo32b", - "path": "protocols/jesd204b/rtl/Jesd64bTo32b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdAlignChGen", - "path": "protocols/jesd204b/rtl/JesdAlignChGen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdAlignFrRepCh", - "path": "protocols/jesd204b/rtl/JesdAlignFrRepCh.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdIlasGen", - "path": "protocols/jesd204b/rtl/JesdIlasGen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdLmfcGen", - "path": "protocols/jesd204b/rtl/JesdLmfcGen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdRxLane", - "path": "protocols/jesd204b/rtl/JesdRxLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdRxReg", - "path": "protocols/jesd204b/rtl/JesdRxReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdSyncFsmRx", - "path": "protocols/jesd204b/rtl/JesdSyncFsmRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdSyncFsmTx", - "path": "protocols/jesd204b/rtl/JesdSyncFsmTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdSyncFsmTxTest", - "path": "protocols/jesd204b/rtl/JesdSyncFsmTxTest.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdSysrefMon", - "path": "protocols/jesd204b/rtl/JesdSysrefMon.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdTestSigGen", - "path": "protocols/jesd204b/rtl/JesdTestSigGen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdTestStreamTx", - "path": "protocols/jesd204b/rtl/JesdTestStreamTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdTxLane", - "path": "protocols/jesd204b/rtl/JesdTxLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdTxReg", - "path": "protocols/jesd204b/rtl/JesdTxReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdTxTest", - "path": "protocols/jesd204b/rtl/JesdTxTest.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "iq16bTo32b", - "path": "protocols/jesd204b/rtl/iq16bTo32b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "iq32bTo16b", - "path": "protocols/jesd204b/rtl/iq32bTo16b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "DescrambleTb", - "path": "protocols/jesd204b/sim/DescrambleTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd204bTb", - "path": "protocols/jesd204b/sim/Jesd204bTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ScramblerTb", - "path": "protocols/jesd204b/sim/ScramblerTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Decoder10b12b", - "path": "protocols/line-codes/rtl/Decoder10b12b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Decoder12b14b", - "path": "protocols/line-codes/rtl/Decoder12b14b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Decoder8b10b", - "path": "protocols/line-codes/rtl/Decoder8b10b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Encoder10b12b", - "path": "protocols/line-codes/rtl/Encoder10b12b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Encoder12b14b", - "path": "protocols/line-codes/rtl/Encoder12b14b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Encoder8b10b", - "path": "protocols/line-codes/rtl/Encoder8b10b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Code10b12bPkgWrapper", - "path": "protocols/line-codes/wrappers/Code10b12bPkgWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Code12b14bPkgWrapper", - "path": "protocols/line-codes/wrappers/Code12b14bPkgWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Code8b10bPkgWrapper", - "path": "protocols/line-codes/wrappers/Code8b10bPkgWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "MdioCore", - "path": "protocols/mdio/rtl/MdioCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "MdioLinkIrqHandler", - "path": "protocols/mdio/rtl/MdioLinkIrqHandler.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "MdioSeqCore", - "path": "protocols/mdio/rtl/MdioSeqCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamBytePacker", - "path": "protocols/packetizer/rtl/AxiStreamBytePacker.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamDepacketizer", - "path": "protocols/packetizer/rtl/AxiStreamDepacketizer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamDepacketizer2", - "path": "protocols/packetizer/rtl/AxiStreamDepacketizer2.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamPacketizer", - "path": "protocols/packetizer/rtl/AxiStreamPacketizer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamPacketizer2", - "path": "protocols/packetizer/rtl/AxiStreamPacketizer2.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bAxi", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bLane", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bRx", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bRxCell", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bRxCell.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bRxPhy", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bRxPhy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bTx", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bTxCell", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bTxPhy", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bTxPhy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bTxSched", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGth7Fixedlat", - "path": "protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7FixedLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGth7FixedLatWrapper", - "path": "protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7FixedLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGth7MultiLane", - "path": "protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7MultiLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGth7VarLat", - "path": "protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7VarLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGth7VarLatWrapper", - "path": "protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7VarLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGthUltra", - "path": "protocols/pgp/pgp2b/gthUltraScale+/rtl/Pgp2bGthUltra.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpGthCoreWrapper", - "path": "protocols/pgp/pgp2b/gthUltraScale+/rtl/PgpGthCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGthUltra", - "path": "protocols/pgp/pgp2b/gthUltraScale/rtl/Pgp2bGthUltra.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpGthCoreWrapper", - "path": "protocols/pgp/pgp2b/gthUltraScale/rtl/PgpGthCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtp7FixedLat", - "path": "protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7FixedLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtp7FixedLatWrapper", - "path": "protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7FixedLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtp7MultiLane", - "path": "protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7MultiLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtp7VarLat", - "path": "protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7VarLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtp7VarLatWrapper", - "path": "protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7VarLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtx7Fixedlat", - "path": "protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtx7FixedLatWrapper", - "path": "protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtx7MultiLane", - "path": "protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7MultiLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtx7VarLat", - "path": "protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7VarLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtx7VarLatWrapper", - "path": "protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7VarLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtyUltra", - "path": "protocols/pgp/pgp2b/gtyUltraScale+/rtl/Pgp2bGtyUltra.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpGtyCoreWrapper", - "path": "protocols/pgp/pgp2b/gtyUltraScale+/rtl/PgpGtyCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CRC7Rtl", - "path": "protocols/pgp/pgp2fc/core/rtl/CRC7Rtl.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcAlignmentChecker", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcAlignmentChecker.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcAlignmentController", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcAlignmentController.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcAxi", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcLane", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcRx", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcRxCell", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxCell.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcRxPhy", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxPhy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcTx", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcTxCell", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxCell.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcTxPhy", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcTxSched", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxSched.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGthCoreWrapper", - "path": "protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGthUltra", - "path": "protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGtp7", - "path": "protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGtp7Wrapper", - "path": "protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7Wrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGtyCoreWrapper", - "path": "protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGtyUltra", - "path": "protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3AxiL", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3AxiL.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Core", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3Core.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Rx", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3Rx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3RxEb", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3RxEb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3RxGearboxAligner", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3RxGearboxAligner.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3RxProtocol", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3RxProtocol.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Tx", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3Tx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3TxProtocol", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3TxProtocol.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUs", - "path": "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsIpWrapper", - "path": "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsQpll", - "path": "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsWrapper", - "path": "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUs", - "path": "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsIpWrapper", - "path": "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsQpll", - "path": "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsWrapper", - "path": "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7IpWrapper", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7IpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7Qpll", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7Qpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7RxGearbox", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7RxGearbox.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7TxGearbox", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7TxGearbox.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7Wrapper", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7Wrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtx7", - "path": "protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtx7IpWrapper", - "path": "protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7IpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtx7Qpll", - "path": "protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Qpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtx7Wrapper", - "path": "protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Wrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GtyUs", - "path": "protocols/pgp/pgp3/gtyUs+/rtl/Pgp3GtyUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GtyUsIpWrapper", - "path": "protocols/pgp/pgp3/gtyUs+/rtl/Pgp3GtyUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GtyUsQpll", - "path": "protocols/pgp/pgp3/gtyUs+/rtl/Pgp3GtyUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GtyUsWrapper", - "path": "protocols/pgp/pgp3/gtyUs+/rtl/Pgp3GtyUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4AxiL", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4AxiL.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Core", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4Core.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4CoreLite", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4CoreLite.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Rx", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4RxEb", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4LiteRxLowSpeed", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4RxLiteLowSpeed.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4RxLiteLowSpeedLane", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4RxLiteLowSpeedLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4RxLiteLowSpeedReg", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4RxLiteLowSpeedReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4RxProtocol", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4RxProtocol.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Tx", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4Tx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4TxLite", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4TxLite.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4TxLiteProtocol", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4TxLiteProtocol.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4TxLiteWrapper", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4TxProtocol", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4TxProtocol.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4CoreLiteWrapper", - "path": "protocols/pgp/pgp4/core/wrappers/Pgp4CoreLiteWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4CoreWrapper", - "path": "protocols/pgp/pgp4/core/wrappers/Pgp4CoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GthUs", - "path": "protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GthUsWrapper", - "path": "protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GthUs", - "path": "protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GthUsWrapper", - "path": "protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Gtp7", - "path": "protocols/pgp/pgp4/gtp7/rtl/Pgp4Gtp7.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Gtp7Wrapper", - "path": "protocols/pgp/pgp4/gtp7/rtl/Pgp4Gtp7Wrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Gtx7", - "path": "protocols/pgp/pgp4/gtx7/rtl/Pgp4Gtx7.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Gtx7Wrapper", - "path": "protocols/pgp/pgp4/gtx7/rtl/Pgp4Gtx7Wrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GtyUs", - "path": "protocols/pgp/pgp4/gtyUs+/rtl/Pgp4GtyUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GtyUsIpFecWrapper", - "path": "protocols/pgp/pgp4/gtyUs+/rtl/Pgp4GtyUsIpFecWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GtyUsWrapper", - "path": "protocols/pgp/pgp4/gtyUs+/rtl/Pgp4GtyUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpRxVcFifo", - "path": "protocols/pgp/shared/PgpRxVcFifo.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpTxVcFifo", - "path": "protocols/pgp/shared/PgpTxVcFifo.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpXvcWrapper", - "path": "protocols/pgp/shared/xilinx/PgpXvcWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLitePMbusMaster", - "path": "protocols/pmbus/rtl/AxiLitePMbusMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLitePMbusMasterCore", - "path": "protocols/pmbus/rtl/AxiLitePMbusMasterCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiAxiLiteRegItf", - "path": "protocols/rssi/v1/rtl/RssiAxiLiteRegItf.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiChksum", - "path": "protocols/rssi/v1/rtl/RssiChksum.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiConnFsm", - "path": "protocols/rssi/v1/rtl/RssiConnFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiCore", - "path": "protocols/rssi/v1/rtl/RssiCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiCoreWrapper", - "path": "protocols/rssi/v1/rtl/RssiCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiHeaderReg", - "path": "protocols/rssi/v1/rtl/RssiHeaderReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiMonitor", - "path": "protocols/rssi/v1/rtl/RssiMonitor.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiParamSync", - "path": "protocols/rssi/v1/rtl/RssiParamSync.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiRxFsm", - "path": "protocols/rssi/v1/rtl/RssiRxFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiTxFsm", - "path": "protocols/rssi/v1/rtl/RssiTxFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLiteSaciMaster", - "path": "protocols/saci/saci1/rtl/AxiLiteSaciMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciAxiLiteMaster", - "path": "protocols/saci/saci1/rtl/SaciAxiLiteMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciMaster", - "path": "protocols/saci/saci1/rtl/SaciMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciMaster2", - "path": "protocols/saci/saci1/rtl/SaciMaster2.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciMasterSync", - "path": "protocols/saci/saci1/rtl/SaciMasterSync.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciMultiPixel", - "path": "protocols/saci/saci1/rtl/SaciMultiPixel.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciPrepRdout", - "path": "protocols/saci/saci1/rtl/SaciPrepRdout.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciSlave", - "path": "protocols/saci/saci1/rtl/SaciSlave.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciSlaveOld", - "path": "protocols/saci/saci1/rtl/SaciSlaveOld.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLiteSaciMasterTb", - "path": "protocols/saci/saci1/sim/AxiLiteSaciMasterTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciAxiLiteMasterTb", - "path": "protocols/saci/saci1/sim/SaciAxiLiteMasterTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciAxiLiteMasterTbWrapper", - "path": "protocols/saci/saci1/sim/SaciAxiLiteMasterTbWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciSlaveRam", - "path": "protocols/saci/saci1/sim/SaciSlaveRam.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciSlaveWrapper", - "path": "protocols/saci/saci1/sim/SaciSlaveWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciAxiLiteMasterWrapper", - "path": "protocols/saci/saci1/wrappers/SaciAxiLiteMasterWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLiteToSaci2", - "path": "protocols/saci/saci2/rtl/AxiLiteToSaci2.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Saci2Coordinator", - "path": "protocols/saci/saci2/rtl/Saci2Coordinator.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Saci2Subordinate", - "path": "protocols/saci/saci2/rtl/Saci2Subordinate.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Saci2ToAxiLite", - "path": "protocols/saci/saci2/rtl/Saci2ToAxiLite.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Saci2ToAxiLiteTb", - "path": "protocols/saci/saci2/sim/Saci2ToAxiLiteTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Saci2ToAxiLiteWrapper", - "path": "protocols/saci/saci2/wrappers/Saci2ToAxiLiteWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltRxDeser", - "path": "protocols/salt/rtl/7Series/SaltRxDeser.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltTxSer", - "path": "protocols/salt/rtl/7Series/SaltTxSer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltCore", - "path": "protocols/salt/rtl/SaltCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltDelayCtrl", - "path": "protocols/salt/rtl/SaltDelayCtrl.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltRx", - "path": "protocols/salt/rtl/SaltRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltRxLvds", - "path": "protocols/salt/rtl/SaltRxLvds.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltTx", - "path": "protocols/salt/rtl/SaltTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltTxLvds", - "path": "protocols/salt/rtl/SaltTxLvds.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltTxResize", - "path": "protocols/salt/rtl/SaltTxResize.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltRxDeser", - "path": "protocols/salt/rtl/UltraScale/SaltRxDeser.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltTxSer", - "path": "protocols/salt/rtl/UltraScale/SaltTxSer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiSpiMaster", - "path": "protocols/spi/rtl/AxiSpiMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SpiMaster", - "path": "protocols/spi/rtl/SpiMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SpiSlave", - "path": "protocols/spi/rtl/SpiSlave.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLiteSrpV0", - "path": "protocols/srp/rtl/AxiLiteSrpV0.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV0AxiLite", - "path": "protocols/srp/rtl/SrpV0AxiLite.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV3Axi", - "path": "protocols/srp/rtl/SrpV3Axi.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV3AxiLite", - "path": "protocols/srp/rtl/SrpV3AxiLite.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV3AxiLiteFull", - "path": "protocols/srp/rtl/SrpV3AxiLiteFull.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV3Core", - "path": "protocols/srp/rtl/SrpV3Core.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV3AxiWrapper", - "path": "protocols/srp/wrappers/SrpV3AxiWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiAxiLiteMaster", - "path": "protocols/ssi/rtl/SsiAxiLiteMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiCmdMaster", - "path": "protocols/ssi/rtl/SsiCmdMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiCmdMasterPulser", - "path": "protocols/ssi/rtl/SsiCmdMasterPulser.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiDbgTap", - "path": "protocols/ssi/rtl/SsiDbgTap.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiFifo", - "path": "protocols/ssi/rtl/SsiFifo.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiFrameLimiter", - "path": "protocols/ssi/rtl/SsiFrameLimiter.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiIbFrameFilter", - "path": "protocols/ssi/rtl/SsiIbFrameFilter.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiIncrementingTx", - "path": "protocols/ssi/rtl/SsiIncrementingTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiInsertSof", - "path": "protocols/ssi/rtl/SsiInsertSof.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiObFrameFilter", - "path": "protocols/ssi/rtl/SsiObFrameFilter.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiPrbsRateGen", - "path": "protocols/ssi/rtl/SsiPrbsRateGen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiPrbsRx", - "path": "protocols/ssi/rtl/SsiPrbsRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiPrbsTx", - "path": "protocols/ssi/rtl/SsiPrbsTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiPrbsWrapper", - "path": "protocols/ssi/wrappers/SsiPrbsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiResizeFifoEofeWrapper", - "path": "protocols/ssi/wrappers/SsiResizeFifoEofeWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspDecoder10b12b", - "path": "protocols/ssp/rtl/SspDecoder10b12b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspDecoder12b14b", - "path": "protocols/ssp/rtl/SspDecoder12b14b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspDecoder8b10b", - "path": "protocols/ssp/rtl/SspDecoder8b10b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspDeframer", - "path": "protocols/ssp/rtl/SspDeframer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspEncoder10b12b", - "path": "protocols/ssp/rtl/SspEncoder10b12b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspEncoder12b14b", - "path": "protocols/ssp/rtl/SspEncoder12b14b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspEncoder8b10b", - "path": "protocols/ssp/rtl/SspEncoder8b10b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspFramer", - "path": "protocols/ssp/rtl/SspFramer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspLowSpeedDecoder10b12bWrapper", - "path": "protocols/ssp/rtl/SspLowSpeedDecoder10b12bWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspLowSpeedDecoder12b14bWrapper", - "path": "protocols/ssp/rtl/SspLowSpeedDecoder12b14bWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspLowSpeedDecoder8b10bWrapper", - "path": "protocols/ssp/rtl/SspLowSpeedDecoder8b10bWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspLowSpeedDecoderLane", - "path": "protocols/ssp/rtl/SspLowSpeedDecoderLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspLowSpeedDecoderReg", - "path": "protocols/ssp/rtl/SspLowSpeedDecoderReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerRx7Series", - "path": "protocols/sugoi/rtl/7Series/SugoiManagerRx7Series.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiAxiLitePixelMatrixConfig", - "path": "protocols/sugoi/rtl/SugoiAxiLitePixelMatrixConfig.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerCore", - "path": "protocols/sugoi/rtl/SugoiManagerCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerFsm", - "path": "protocols/sugoi/rtl/SugoiManagerFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerRx", - "path": "protocols/sugoi/rtl/SugoiManagerRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiSubordinateCore", - "path": "protocols/sugoi/rtl/SugoiSubordinateCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiSubordinateFsm", - "path": "protocols/sugoi/rtl/SugoiSubordinateFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerRxUltrascale", - "path": "protocols/sugoi/rtl/UltraScale/SugoiManagerRxUltrascale.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerRx7Series", - "path": "protocols/sugoi/rtl/dummy/SugoiManagerRx7SeriesDummy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerRxUltrascale", - "path": "protocols/sugoi/rtl/dummy/SugoiManagerRxUltrascaleDummy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartAxiLiteMaster", - "path": "protocols/uart/rtl/UartAxiLiteMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartAxiLiteMasterFsm", - "path": "protocols/uart/rtl/UartAxiLiteMasterFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartBrg", - "path": "protocols/uart/rtl/UartBrg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartRx", - "path": "protocols/uart/rtl/UartRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartTx", - "path": "protocols/uart/rtl/UartTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartWrapper", - "path": "protocols/uart/rtl/UartWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartAxiLiteMasterTb", - "path": "protocols/uart/sim/UartAxiLiteMasterTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Idelaye3Wrapper", - "path": "xilinx/7Series/dummy/Idelaye3WrapperDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Odelaye3Wrapper", - "path": "xilinx/7Series/dummy/Odelaye3WrapperDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClockManager7", - "path": "xilinx/7Series/general/rtl/ClockManager7.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DeviceDna7Series", - "path": "xilinx/7Series/general/rtl/DeviceDna7Series.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Dsp48Comparator4x12b", - "path": "xilinx/7Series/general/rtl/Dsp48Comparator4x12b.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "InputBufferReg", - "path": "xilinx/7Series/general/rtl/InputBufferReg.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Iprog7Series", - "path": "xilinx/7Series/general/rtl/Iprog7Series.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Iprog7SeriesCore", - "path": "xilinx/7Series/general/rtl/Iprog7SeriesCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "OutputBufferReg", - "path": "xilinx/7Series/general/rtl/OutputBufferReg.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SelectioDeser7Series", - "path": "xilinx/7Series/general/rtl/SelectioDeser7Series.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SelectioDeserLane7Series", - "path": "xilinx/7Series/general/rtl/SelectioDeserLane7Series.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7AutoPhaseAligner", - "path": "xilinx/7Series/gth7/rtl/Gth7AutoPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7Core", - "path": "xilinx/7Series/gth7/rtl/Gth7Core.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7QuadPll", - "path": "xilinx/7Series/gth7/rtl/Gth7QuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7RecClkMonitor", - "path": "xilinx/7Series/gth7/rtl/Gth7RecClkMonitor.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7RxFixedLatPhaseAligner", - "path": "xilinx/7Series/gth7/rtl/Gth7RxFixedLatPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7RxRst", - "path": "xilinx/7Series/gth7/rtl/Gth7RxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7RxRstSeq", - "path": "xilinx/7Series/gth7/rtl/Gth7RxRstSeq.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7TxManualPhaseAligner", - "path": "xilinx/7Series/gth7/rtl/Gth7TxManualPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7TxRst", - "path": "xilinx/7Series/gth7/rtl/Gth7TxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7AutoPhaseAligner", - "path": "xilinx/7Series/gtp7/rtl/Gtp7AutoPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7Core", - "path": "xilinx/7Series/gtp7/rtl/Gtp7Core.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7QuadPll", - "path": "xilinx/7Series/gtp7/rtl/Gtp7QuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7RecClkMonitor", - "path": "xilinx/7Series/gtp7/rtl/Gtp7RecClkMonitor.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7RxFixedLatPhaseAligner", - "path": "xilinx/7Series/gtp7/rtl/Gtp7RxFixedLatPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7RxRst", - "path": "xilinx/7Series/gtp7/rtl/Gtp7RxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7RxRstSeq", - "path": "xilinx/7Series/gtp7/rtl/Gtp7RxRstSeq.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7TxManualPhaseAligner", - "path": "xilinx/7Series/gtp7/rtl/Gtp7TxManualPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7TxRst", - "path": "xilinx/7Series/gtp7/rtl/Gtp7TxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtpe2ChannelDummy", - "path": "xilinx/7Series/gtp7/rtl/Gtpe2ChannelDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7AutoPhaseAligner", - "path": "xilinx/7Series/gtx7/rtl/Gtx7AutoPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7Core", - "path": "xilinx/7Series/gtx7/rtl/Gtx7Core.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7QuadPll", - "path": "xilinx/7Series/gtx7/rtl/Gtx7QuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7RecClkMonitor", - "path": "xilinx/7Series/gtx7/rtl/Gtx7RecClkMonitor.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7RxFixedLatPhaseAligner", - "path": "xilinx/7Series/gtx7/rtl/Gtx7RxFixedLatPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7RxRst", - "path": "xilinx/7Series/gtx7/rtl/Gtx7RxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7TxManualPhaseAligner", - "path": "xilinx/7Series/gtx7/rtl/Gtx7TxManualPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7TxRst", - "path": "xilinx/7Series/gtx7/rtl/Gtx7TxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtxe2ChannelDummy", - "path": "xilinx/7Series/gtx7/rtl/Gtxe2ChannelDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SemWrapper", - "path": "xilinx/7Series/sem/rtl/SemWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SsiSem", - "path": "xilinx/7Series/sem/rtl/SsiSem.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UartSem", - "path": "xilinx/7Series/sem/rtl/UartSem.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiXadcMinimumCore", - "path": "xilinx/7Series/xadc/rtl/AxiXadcMinimumCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "XadcSimpleCore", - "path": "xilinx/7Series/xadc/rtl/XadcSimpleCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClockManagerUltraScale", - "path": "xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GthUltraScaleQuadPll", - "path": "xilinx/UltraScale+/gthUs+/rtl/GthUltraScaleQuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gthe4ChannelDummy", - "path": "xilinx/UltraScale+/gthUs+/rtl/Gthe4ChannelDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GtyUltraScaleQuadPll", - "path": "xilinx/UltraScale+/gtyUs+/rtl/GtyUltraScaleQuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtye4ChannelDummy", - "path": "xilinx/UltraScale+/gtyUs+/rtl/Gtye4ChannelDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClockManagerUltraScale", - "path": "xilinx/UltraScale/clocking/rtl/ClockManagerUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Delaye3PatchFsm", - "path": "xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DeviceDnaUltraScale", - "path": "xilinx/UltraScale/general/rtl/DeviceDnaUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Idelaye3Wrapper", - "path": "xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "InputBufferReg", - "path": "xilinx/UltraScale/general/rtl/InputBufferReg.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "IprogUltraScale", - "path": "xilinx/UltraScale/general/rtl/IprogUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Odelaye3Wrapper", - "path": "xilinx/UltraScale/general/rtl/Odelaye3Wrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "OutputBufferReg", - "path": "xilinx/UltraScale/general/rtl/OutputBufferReg.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SelectioDeserLaneUltraScale", - "path": "xilinx/UltraScale/general/rtl/SelectioDeserLaneUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SelectioDeserUltraScale", - "path": "xilinx/UltraScale/general/rtl/SelectioDeserUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GthUltraScaleQuadPll", - "path": "xilinx/UltraScale/gthUs/rtl/GthUltraScaleQuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gthe3ChannelDummy", - "path": "xilinx/UltraScale/gthUs/rtl/Gthe3ChannelDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClockManagerVersal", - "path": "xilinx/Versal/clocking/rtl/ClockManagerVersal.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp16FixedLatCore", - "path": "xilinx/Virtex5/gtp/rtl/Gtp16FixedLatCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GtpDualFixedLatCore", - "path": "xilinx/Virtex5/gtp/rtl/GtpDualFixedLatCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GtpRxCommaAligner", - "path": "xilinx/Virtex5/gtp/rtl/GtpRxCommaAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GtpTxPhaseAligner", - "path": "xilinx/Virtex5/gtp/rtl/GtpTxPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClkOutBufDiff", - "path": "xilinx/dummy/ClkOutBufDiffDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClkOutBufSingle", - "path": "xilinx/dummy/ClkOutBufSingleDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DeviceDna", - "path": "xilinx/dummy/DeviceDnaDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "IoBufWrapper", - "path": "xilinx/dummy/IoBufWrapperDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Iprog", - "path": "xilinx/dummy/IprogDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "OutputBufferReg", - "path": "xilinx/dummy/OutputBufferRegDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Srl16Delay", - "path": "xilinx/dummy/Srl16DelayDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "MicroblazeBasicCoreWrapper", - "path": "xilinx/general/microblaze/bypass/MicroblazeBasicCoreWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "MicroblazeBasicCoreWrapper", - "path": "xilinx/general/microblaze/generate/MicroblazeBasicCoreWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClkOutBufDiff", - "path": "xilinx/general/rtl/ClkOutBufDiff.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClkOutBufSingle", - "path": "xilinx/general/rtl/ClkOutBufSingle.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DeviceDna", - "path": "xilinx/general/rtl/DeviceDna.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GtRxAlignCheck", - "path": "xilinx/general/rtl/GtRxAlignCheck.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "IoBufWrapper", - "path": "xilinx/general/rtl/IoBufWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Iprog", - "path": "xilinx/general/rtl/Iprog.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SelectIoRxGearboxAligner", - "path": "xilinx/general/rtl/SelectIoRxGearboxAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Srl16Delay", - "path": "xilinx/general/rtl/Srl16Delay.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/7Series/Impl/images/UdpDebugBridge_stub.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/7Series/Stub/images/UdpDebugBridge_stub.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/UltraScale/Impl/images/UdpDebugBridge_stub.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/UltraScale/Stub/images/UdpDebugBridge_stub.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridgeWrapper", - "path": "xilinx/xvc-udp/dcp/core/UdpDebugBridgeWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiStreamSelector", - "path": "xilinx/xvc-udp/jtag/rtl/AxiStreamSelector.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxisJtagDebugBridge", - "path": "xilinx/xvc-udp/jtag/rtl/AxisJtagDebugBridge.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxisToJtag", - "path": "xilinx/xvc-udp/jtag/rtl/AxisToJtag.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxisToJtagCore", - "path": "xilinx/xvc-udp/jtag/rtl/AxisToJtagCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "JtagSerDesCore", - "path": "xilinx/xvc-udp/jtag/rtl/JtagSerDesCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DmaXvcWrapper", - "path": "xilinx/xvc-udp/rtl/DmaXvcWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridgeWrapper", - "path": "xilinx/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - } - ], - "unresolved_phase1_edges": [] -} diff --git a/docs/_meta/rtl_phase1_queue.md b/docs/_meta/rtl_phase1_queue.md deleted file mode 100644 index 6b39ac00f6..0000000000 --- a/docs/_meta/rtl_phase1_queue.md +++ /dev/null @@ -1,272 +0,0 @@ -# SURF RTL Phase-1 Queue - -## Scope -- Scan dirs: `base, axi, dsp, protocols, ethernet, devices, xilinx` -- Queue nodes are path-qualified RTL entity definitions, not bare entity names. -- Queue order is bottom-up: leaves first, higher-level assemblies later. -- Manual phase-1 deferrals and order overrides live in `docs/_meta/rtl_phase1_queue_overrides.json`. - -## Summary -- Phase-1 modules: `219` -- Phase-1 dependency edges: `392` -- Bottom-up layers: `10` -- Deferred modules: `632` -- Unresolved duplicate-name phase-1 edges: `0` -- Applied order overrides: `0` - -## Phase-1 Filters -- Force-included entities: - - None -- Force-included paths: - - None -- Deferred subsystems: - - `ethernet`: Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first. - - `protocols`: Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first. - - `devices`: Subsystem is currently dominated by vendor-heavy modules in phase 1. - - `xilinx`: Subsystem is currently dominated by vendor-heavy modules in phase 1. -- Deferred entities: - - `LutFixedDelay`: Depends on SinglePortRamPrimitive under the current open-source flow. -- Deferred exact paths: - - None -- Deferred path substrings: - - `axi/simlink/`: Simulation support models are not part of the synthesizable phase-1 queue. - - `/sim/`: Simulation-only support modules are not part of the synthesizable phase-1 queue. - - `/dummy/`: Dummy-backed variants are deferred from the phase-1 executable queue. - - `/altera/`: Vendor-specific implementation branches are deferred in phase 1. - - `/xilinx/`: Vendor-specific implementation branches are deferred in phase 1. - - `7Series`: Family-specific implementation branches are deferred in phase 1. - - `UltraScale`: Family-specific implementation branches are deferred in phase 1. - - `UltraScale+`: Family-specific implementation branches are deferred in phase 1. - - `/gth`: GT-family implementation branches are deferred in phase 1. - - `/gtp`: GT-family implementation branches are deferred in phase 1. - - `/gty`: GT-family implementation branches are deferred in phase 1. - - `/gtx`: GT-family implementation branches are deferred in phase 1. - -## Manual Order Overrides -- None - -## Unresolved Duplicate-Name Phase-1 Edges -- None - -## Flat Bottom-Up Order -| order | layer | entity | subsystem | path | instantiated_by_count | -| --- | --- | --- | --- | --- | --- | -| 1 | 0 | AxiLiteCrossbar | axi | axi/axi-lite/rtl/AxiLiteCrossbar.vhd | 3 | -| 2 | 0 | AxiLiteMaster | axi | axi/axi-lite/rtl/AxiLiteMaster.vhd | 6 | -| 3 | 0 | AxiLiteRegs | axi | axi/axi-lite/rtl/AxiLiteRegs.vhd | 2 | -| 4 | 0 | AxiLiteRespTimer | axi | axi/axi-lite/rtl/AxiLiteRespTimer.vhd | 1 | -| 5 | 0 | AxiLiteSlave | axi | axi/axi-lite/rtl/AxiLiteSlave.vhd | 2 | -| 6 | 0 | AxiLiteWriteFilter | axi | axi/axi-lite/rtl/AxiLiteWriteFilter.vhd | 1 | -| 7 | 0 | AxiVersion | axi | axi/axi-lite/rtl/AxiVersion.vhd | 1 | -| 8 | 0 | AxiStreamCombiner | axi | axi/axi-stream/rtl/AxiStreamCombiner.vhd | 1 | -| 9 | 0 | AxiStreamFlush | axi | axi/axi-stream/rtl/AxiStreamFlush.vhd | 1 | -| 10 | 0 | AxiStreamGearboxPack | axi | axi/axi-stream/rtl/AxiStreamGearboxPack.vhd | 1 | -| 11 | 0 | AxiStreamGearboxUnpack | axi | axi/axi-stream/rtl/AxiStreamGearboxUnpack.vhd | 1 | -| 12 | 0 | AxiStreamPipeline | axi | axi/axi-stream/rtl/AxiStreamPipeline.vhd | 18 | -| 13 | 0 | AxiStreamSplitter | axi | axi/axi-stream/rtl/AxiStreamSplitter.vhd | 1 | -| 14 | 0 | AxiStreamPkgWrapper | axi | axi/axi-stream/wrappers/AxiStreamPkgWrapper.vhd | 0 | -| 15 | 0 | AxiReadPathMux | axi | axi/axi4/rtl/AxiReadPathMux.vhd | 1 | -| 16 | 0 | AxiResize | axi | axi/axi4/rtl/AxiResize.vhd | 1 | -| 17 | 0 | AxiWritePathMux | axi | axi/axi4/rtl/AxiWritePathMux.vhd | 1 | -| 18 | 0 | AxiToAxiLite | axi | axi/bridge/rtl/AxiToAxiLite.vhd | 1 | -| 19 | 0 | AxiStreamDmaV2WriteMux | axi | axi/dma/rtl/v2/AxiStreamDmaV2WriteMux.vhd | 2 | -| 20 | 0 | CRC32Rtl | base | base/crc/rtl/CRC32Rtl.vhd | 0 | -| 21 | 0 | Crc32 | base | base/crc/rtl/Crc32.vhd | 1 | -| 22 | 0 | Crc32Parallel | base | base/crc/rtl/Crc32Parallel.vhd | 0 | -| 23 | 0 | SlvDelay | base | base/delay/rtl/SlvDelay.vhd | 0 | -| 24 | 0 | SlvDelayRam | base | base/delay/rtl/SlvDelayRam.vhd | 0 | -| 25 | 0 | SlvFixedDelay | base | base/delay/rtl/SlvFixedDelay.vhd | 0 | -| 26 | 0 | FifoOutputPipeline | base | base/fifo/rtl/FifoOutputPipeline.vhd | 7 | -| 27 | 0 | FifoRdFsm | base | base/fifo/rtl/inferred/FifoRdFsm.vhd | 2 | -| 28 | 0 | FifoWrFsm | base | base/fifo/rtl/inferred/FifoWrFsm.vhd | 2 | -| 29 | 0 | MasterRamIpIntegrator | base | base/general/ip_integrator/MasterRamIpIntegrator.vhd | 0 | -| 30 | 0 | SlaveRamIpIntegrator | base | base/general/ip_integrator/SlaveRamIpIntegrator.vhd | 0 | -| 31 | 0 | Arbiter | base | base/general/rtl/Arbiter.vhd | 0 | -| 32 | 0 | ClockDivider | base | base/general/rtl/ClockDivider.vhd | 0 | -| 33 | 0 | Gearbox | base | base/general/rtl/Gearbox.vhd | 1 | -| 34 | 0 | Heartbeat | base | base/general/rtl/Heartbeat.vhd | 1 | -| 35 | 0 | Mux | base | base/general/rtl/Mux.vhd | 0 | -| 36 | 0 | OneShot | base | base/general/rtl/OneShot.vhd | 0 | -| 37 | 0 | RegisterVector | base | base/general/rtl/RegisterVector.vhd | 0 | -| 38 | 0 | RstPipeline | base | base/general/rtl/RstPipeline.vhd | 3 | -| 39 | 0 | Scrambler | base | base/general/rtl/Scrambler.vhd | 0 | -| 40 | 0 | LutRam | base | base/ram/inferred/LutRam.vhd | 1 | -| 41 | 0 | SimpleDualPortRam | base | base/ram/inferred/SimpleDualPortRam.vhd | 6 | -| 42 | 0 | TrueDualPortRam | base | base/ram/inferred/TrueDualPortRam.vhd | 3 | -| 43 | 0 | Synchronizer | base | base/sync/rtl/Synchronizer.vhd | 13 | -| 44 | 0 | SynchronizerVector | base | base/sync/rtl/SynchronizerVector.vhd | 7 | -| 45 | 0 | FirFilterTap | dsp | dsp/generic/fixed/FirFilterTap.vhd | 2 | -| 46 | 1 | AxiLiteMasterProxy | axi | axi/axi-lite/rtl/AxiLiteMasterProxy.vhd | 1 | -| 47 | 1 | AxiLiteSequencerRam | axi | axi/axi-lite/rtl/AxiLiteSequencerRam.vhd | 1 | -| 48 | 1 | AxiStreamCompact | axi | axi/axi-stream/rtl/AxiStreamCompact.vhd | 1 | -| 49 | 1 | AxiStreamConcat | axi | axi/axi-stream/rtl/AxiStreamConcat.vhd | 1 | -| 50 | 1 | AxiStreamDeMux | axi | axi/axi-stream/rtl/AxiStreamDeMux.vhd | 2 | -| 51 | 1 | AxiStreamFrameRateLimiter | axi | axi/axi-stream/rtl/AxiStreamFrameRateLimiter.vhd | 1 | -| 52 | 1 | AxiStreamMux | axi | axi/axi-stream/rtl/AxiStreamMux.vhd | 2 | -| 53 | 1 | AxiStreamRepeater | axi | axi/axi-stream/rtl/AxiStreamRepeater.vhd | 1 | -| 54 | 1 | AxiStreamResize | axi | axi/axi-stream/rtl/AxiStreamResize.vhd | 2 | -| 55 | 1 | AxiStreamShift | axi | axi/axi-stream/rtl/AxiStreamShift.vhd | 3 | -| 56 | 1 | AxiStreamTrailerAppend | axi | axi/axi-stream/rtl/AxiStreamTrailerAppend.vhd | 1 | -| 57 | 1 | AxiStreamTrailerRemove | axi | axi/axi-stream/rtl/AxiStreamTrailerRemove.vhd | 1 | -| 58 | 1 | AxiRam | axi | axi/axi4/rtl/AxiRam.vhd | 1 | -| 59 | 1 | AxiLiteToIpBus | axi | axi/bridge/rtl/AxiLiteToIpBus.vhd | 1 | -| 60 | 1 | IpBusToAxiLite | axi | axi/bridge/rtl/IpBusToAxiLite.vhd | 1 | -| 61 | 1 | AxiStreamDmaV2WriteMuxIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2WriteMuxIpIntegrator.vhd | 0 | -| 62 | 1 | Crc32PolyWrapper | base | base/crc/wrappers/Crc32PolyWrapper.vhd | 0 | -| 63 | 1 | FifoSync | base | base/fifo/rtl/inferred/FifoSync.vhd | 2 | -| 64 | 1 | RstPipelineVector | base | base/general/rtl/RstPipelineVector.vhd | 0 | -| 65 | 1 | WatchDogRst | base | base/general/rtl/WatchDogRst.vhd | 0 | -| 66 | 1 | HeartbeatWrapper | base | base/general/wrappers/HeartbeatWrapper.vhd | 0 | -| 67 | 1 | DualPortRam | base | base/ram/inferred/DualPortRam.vhd | 4 | -| 68 | 1 | RstSync | base | base/sync/rtl/RstSync.vhd | 15 | -| 69 | 1 | SynchronizerEdge | base | base/sync/rtl/SynchronizerEdge.vhd | 1 | -| 70 | 1 | BoxcarIntegrator | dsp | dsp/generic/fixed/BoxcarIntegrator.vhd | 1 | -| 71 | 1 | DspAddSub | dsp | dsp/generic/fixed/DspAddSub.vhd | 1 | -| 72 | 1 | DspComparator | dsp | dsp/generic/fixed/DspComparator.vhd | 4 | -| 73 | 1 | DspPreSubMult | dsp | dsp/generic/fixed/DspPreSubMult.vhd | 0 | -| 74 | 1 | DspSquareDiffMult | dsp | dsp/generic/fixed/DspSquareDiffMult.vhd | 0 | -| 75 | 2 | MasterAxiLiteIpIntegrator | axi | axi/axi-lite/ip_integrator/MasterAxiLiteIpIntegrator.vhd | 9 | -| 76 | 2 | SlaveAxiLiteIpIntegrator | axi | axi/axi-lite/ip_integrator/SlaveAxiLiteIpIntegrator.vhd | 32 | -| 77 | 2 | AxiLiteAsync | axi | axi/axi-lite/rtl/AxiLiteAsync.vhd | 7 | -| 78 | 2 | MasterAxiStreamIpIntegrator | axi | axi/axi-stream/ip_integrator/MasterAxiStreamIpIntegrator.vhd | 30 | -| 79 | 2 | SlaveAxiStreamIpIntegrator | axi | axi/axi-stream/ip_integrator/SlaveAxiStreamIpIntegrator.vhd | 30 | -| 80 | 2 | AxiStreamGearbox | axi | axi/axi-stream/rtl/AxiStreamGearbox.vhd | 2 | -| 81 | 2 | AxiStreamPrbsFlowCtrl | axi | axi/axi-stream/rtl/AxiStreamPrbsFlowCtrl.vhd | 1 | -| 82 | 2 | AxiStreamTap | axi | axi/axi-stream/rtl/AxiStreamTap.vhd | 1 | -| 83 | 2 | MasterAxiIpIntegrator | axi | axi/axi4/ip_integrator/MasterAxiIpIntegrator.vhd | 16 | -| 84 | 2 | SlaveAxiIpIntegrator | axi | axi/axi4/ip_integrator/SlaveAxiIpIntegrator.vhd | 9 | -| 85 | 2 | AxiStreamDmaRead | axi | axi/dma/rtl/v1/AxiStreamDmaRead.vhd | 4 | -| 86 | 2 | AxiStreamDmaV2Read | axi | axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd | 3 | -| 87 | 2 | AxiStreamDmaV2Write | axi | axi/dma/rtl/v2/AxiStreamDmaV2Write.vhd | 3 | -| 88 | 2 | FifoAsync | base | base/fifo/rtl/inferred/FifoAsync.vhd | 4 | -| 89 | 2 | Debouncer | base | base/general/rtl/Debouncer.vhd | 1 | -| 90 | 2 | PwrUpRst | base | base/general/rtl/PwrUpRst.vhd | 0 | -| 91 | 2 | SynchronizerOneShot | base | base/sync/rtl/SynchronizerOneShot.vhd | 8 | -| 92 | 2 | BoxcarFilter | dsp | dsp/generic/fixed/BoxcarFilter.vhd | 0 | -| 93 | 3 | AxiLiteAsyncIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteAsyncIpIntegrator.vhd | 0 | -| 94 | 3 | AxiLiteMasterIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteMasterIpIntegrator.vhd | 0 | -| 95 | 3 | AxiLiteMasterProxyIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteMasterProxyIpIntegrator.vhd | 0 | -| 96 | 3 | AxiLiteRegsIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteRegsIpIntegrator.vhd | 0 | -| 97 | 3 | AxiLiteRespTimerIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteRespTimerIpIntegrator.vhd | 0 | -| 98 | 3 | AxiLiteSequencerRamIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteSequencerRamIpIntegrator.vhd | 0 | -| 99 | 3 | AxiLiteSlaveIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteSlaveIpIntegrator.vhd | 0 | -| 100 | 3 | AxiLiteWriteFilterIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteWriteFilterIpIntegrator.vhd | 0 | -| 101 | 3 | AxiVersionIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiVersionIpIntegrator.vhd | 0 | -| 102 | 3 | AxiStreamCombinerIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamCombinerIpIntegrator.vhd | 0 | -| 103 | 3 | AxiStreamCompactIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamCompactIpIntegrator.vhd | 0 | -| 104 | 3 | AxiStreamConcatIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamConcatIpIntegrator.vhd | 0 | -| 105 | 3 | AxiStreamDeMuxIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd | 0 | -| 106 | 3 | AxiStreamFlushIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamFlushIpIntegrator.vhd | 0 | -| 107 | 3 | AxiStreamFrameRateLimiterIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamFrameRateLimiterIpIntegrator.vhd | 0 | -| 108 | 3 | AxiStreamGearboxIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamGearboxIpIntegrator.vhd | 0 | -| 109 | 3 | AxiStreamGearboxPackIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamGearboxPackIpIntegrator.vhd | 0 | -| 110 | 3 | AxiStreamGearboxUnpackIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamGearboxUnpackIpIntegrator.vhd | 0 | -| 111 | 3 | AxiStreamMuxIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd | 0 | -| 112 | 3 | AxiStreamPipelineIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd | 0 | -| 113 | 3 | AxiStreamPrbsFlowCtrlIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamPrbsFlowCtrlIpIntegrator.vhd | 0 | -| 114 | 3 | AxiStreamRepeaterIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamRepeaterIpIntegrator.vhd | 0 | -| 115 | 3 | AxiStreamResizeIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamResizeIpIntegrator.vhd | 0 | -| 116 | 3 | AxiStreamShiftIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamShiftIpIntegrator.vhd | 0 | -| 117 | 3 | AxiStreamSplitterIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamSplitterIpIntegrator.vhd | 0 | -| 118 | 3 | AxiStreamTapIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamTapIpIntegrator.vhd | 0 | -| 119 | 3 | AxiStreamTrailerAppendIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamTrailerAppendIpIntegrator.vhd | 0 | -| 120 | 3 | AxiStreamTrailerRemoveIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamTrailerRemoveIpIntegrator.vhd | 0 | -| 121 | 3 | MasterAxiStreamTerminateIpIntegrator | axi | axi/axi-stream/ip_integrator/MasterAxiStreamTerminateIpIntegrator.vhd | 0 | -| 122 | 3 | SlaveAxiStreamTerminateIpIntegrator | axi | axi/axi-stream/ip_integrator/SlaveAxiStreamTerminateIpIntegrator.vhd | 0 | -| 123 | 3 | AxiStreamTimer | axi | axi/axi-stream/rtl/AxiStreamTimer.vhd | 1 | -| 124 | 3 | AxiRamIpIntegrator | axi | axi/axi4/ip_integrator/AxiRamIpIntegrator.vhd | 0 | -| 125 | 3 | AxiReadPathMuxIpIntegrator | axi | axi/axi4/ip_integrator/AxiReadPathMuxIpIntegrator.vhd | 0 | -| 126 | 3 | AxiResizeIpIntegrator | axi | axi/axi4/ip_integrator/AxiResizeIpIntegrator.vhd | 0 | -| 127 | 3 | AxiWritePathMuxIpIntegrator | axi | axi/axi4/ip_integrator/AxiWritePathMuxIpIntegrator.vhd | 0 | -| 128 | 3 | AxiRateGen | axi | axi/axi4/rtl/AxiRateGen.vhd | 1 | -| 129 | 3 | AxiLiteToIpBusIpIntegrator | axi | axi/bridge/ip_integrator/AxiLiteToIpBusIpIntegrator.vhd | 0 | -| 130 | 3 | AxiToAxiLiteIpIntegrator | axi | axi/bridge/ip_integrator/AxiToAxiLiteIpIntegrator.vhd | 0 | -| 131 | 3 | IpBusToAxiLiteIpIntegrator | axi | axi/bridge/ip_integrator/IpBusToAxiLiteIpIntegrator.vhd | 0 | -| 132 | 3 | AxiLiteToDrp | axi | axi/bridge/rtl/AxiLiteToDrp.vhd | 1 | -| 133 | 3 | AxiStreamDmaReadIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaReadIpIntegrator.vhd | 0 | -| 134 | 3 | AxiStreamDmaV2ReadIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2ReadIpIntegrator.vhd | 0 | -| 135 | 3 | AxiStreamDmaV2WriteIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2WriteIpIntegrator.vhd | 0 | -| 136 | 3 | Fifo | base | base/fifo/rtl/Fifo.vhd | 6 | -| 137 | 3 | AsyncGearbox | base | base/general/rtl/AsyncGearbox.vhd | 0 | -| 138 | 3 | DebouncerWrapper | base | base/general/wrappers/DebouncerWrapper.vhd | 0 | -| 139 | 3 | SyncTrigPeriod | base | base/sync/rtl/SyncTrigPeriod.vhd | 0 | -| 140 | 3 | SynchronizerFifo | base | base/sync/rtl/SynchronizerFifo.vhd | 11 | -| 141 | 3 | SynchronizerOneShotVector | base | base/sync/rtl/SynchronizerOneShotVector.vhd | 0 | -| 142 | 3 | FirFilterSingleChannel | dsp | dsp/generic/fixed/FirFilterSingleChannel.vhd | 0 | -| 143 | 4 | AxiDualPortRam | axi | axi/axi-lite/rtl/AxiDualPortRam.vhd | 6 | -| 144 | 4 | AxiLiteRingBuffer | axi | axi/axi-lite/rtl/AxiLiteRingBuffer.vhd | 1 | -| 145 | 4 | AxiStreamTimerIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamTimerIpIntegrator.vhd | 0 | -| 146 | 4 | AxiStreamScatterGather | axi | axi/axi-stream/rtl/AxiStreamScatterGather.vhd | 1 | -| 147 | 4 | AxiRateGenIpIntegrator | axi | axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd | 0 | -| 148 | 4 | AxiMemTester | axi | axi/axi4/rtl/AxiMemTester.vhd | 1 | -| 149 | 4 | AxiLiteToDrpIpIntegrator | axi | axi/bridge/ip_integrator/AxiLiteToDrpIpIntegrator.vhd | 0 | -| 150 | 4 | SlvArraytoAxiLite | axi | axi/bridge/rtl/SlvArraytoAxiLite.vhd | 1 | -| 151 | 4 | AxiStreamDmaV2Desc | axi | axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd | 2 | -| 152 | 4 | AxiStreamDmaV2Fifo | axi | axi/dma/rtl/v2/AxiStreamDmaV2Fifo.vhd | 1 | -| 153 | 4 | SlvDelayFifo | base | base/delay/rtl/SlvDelayFifo.vhd | 0 | -| 154 | 4 | FifoCascade | base | base/fifo/rtl/FifoCascade.vhd | 8 | -| 155 | 4 | FwftCntWrapper | base | base/fifo/wrappers/FwftCntWrapper.vhd | 0 | -| 156 | 4 | SyncClockFreq | base | base/sync/rtl/SyncClockFreq.vhd | 1 | -| 157 | 4 | SyncMinMax | base | base/sync/rtl/SyncMinMax.vhd | 2 | -| 158 | 4 | SynchronizerOneShotCnt | base | base/sync/rtl/SynchronizerOneShotCnt.vhd | 1 | -| 159 | 5 | AxiDualPortRamIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd | 0 | -| 160 | 5 | AxiLiteCrossbarIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteCrossbarIpIntegrator.vhd | 0 | -| 161 | 5 | AxiLiteRingBufferIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteRingBufferIpIntegrator.vhd | 0 | -| 162 | 5 | AxiLiteFifoPop | axi | axi/axi-lite/rtl/AxiLiteFifoPop.vhd | 1 | -| 163 | 5 | AxiLiteFifoPush | axi | axi/axi-lite/rtl/AxiLiteFifoPush.vhd | 1 | -| 164 | 5 | AxiLiteFifoPushPop | axi | axi/axi-lite/rtl/AxiLiteFifoPushPop.vhd | 2 | -| 165 | 5 | AxiStreamScatterGatherIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamScatterGatherIpIntegrator.vhd | 0 | -| 166 | 5 | AxiStreamFifoV2 | axi | axi/axi-stream/rtl/AxiStreamFifoV2.vhd | 7 | -| 167 | 5 | AxiMemTesterIpIntegrator | axi | axi/axi4/ip_integrator/AxiMemTesterIpIntegrator.vhd | 0 | -| 168 | 5 | AxiReadPathFifo | axi | axi/axi4/rtl/AxiReadPathFifo.vhd | 3 | -| 169 | 5 | AxiWritePathFifo | axi | axi/axi4/rtl/AxiWritePathFifo.vhd | 3 | -| 170 | 5 | SlvArraytoAxiLiteIpIntegrator | axi | axi/bridge/ip_integrator/SlvArraytoAxiLiteIpIntegrator.vhd | 0 | -| 171 | 5 | AxiStreamDmaV2DescIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2DescIpIntegrator.vhd | 0 | -| 172 | 5 | AxiStreamDmaV2FifoIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2FifoIpIntegrator.vhd | 0 | -| 173 | 5 | AxiStreamDmaV2 | axi | axi/dma/rtl/v2/AxiStreamDmaV2.vhd | 1 | -| 174 | 5 | FifoMux | base | base/fifo/rtl/FifoMux.vhd | 0 | -| 175 | 5 | SyncTrigRate | base | base/sync/rtl/SyncTrigRate.vhd | 3 | -| 176 | 5 | SynchronizerOneShotCntVector | base | base/sync/rtl/SynchronizerOneShotCntVector.vhd | 2 | -| 177 | 5 | SyncClockFreqWrapper | base | base/sync/wrappers/SyncClockFreqWrapper.vhd | 0 | -| 178 | 5 | FirFilterMultiChannel | dsp | dsp/generic/fixed/FirFilterMultiChannel.vhd | 0 | -| 179 | 6 | AxiLiteFifoPopIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteFifoPopIpIntegrator.vhd | 0 | -| 180 | 6 | AxiLiteFifoPushIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteFifoPushIpIntegrator.vhd | 0 | -| 181 | 6 | AxiLiteFifoPushPopIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteFifoPushPopIpIntegrator.vhd | 0 | -| 182 | 6 | AxiStreamFifoV2IpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd | 0 | -| 183 | 6 | AxiStreamBatchingFifo | axi | axi/axi-stream/rtl/AxiStreamBatchingFifo.vhd | 1 | -| 184 | 6 | AxiStreamMon | axi | axi/axi-stream/rtl/AxiStreamMon.vhd | 2 | -| 185 | 6 | AxiStreamRingBuffer | axi | axi/axi-stream/rtl/AxiStreamRingBuffer.vhd | 1 | -| 186 | 6 | AxiReadPathFifoIpIntegrator | axi | axi/axi4/ip_integrator/AxiReadPathFifoIpIntegrator.vhd | 0 | -| 187 | 6 | AxiWritePathFifoIpIntegrator | axi | axi/axi4/ip_integrator/AxiWritePathFifoIpIntegrator.vhd | 0 | -| 188 | 6 | AxiReadEmulate | axi | axi/axi4/rtl/AxiReadEmulate.vhd | 1 | -| 189 | 6 | AxiRingBuffer | axi | axi/axi4/rtl/AxiRingBuffer.vhd | 1 | -| 190 | 6 | AxiWriteEmulate | axi | axi/axi4/rtl/AxiWriteEmulate.vhd | 1 | -| 191 | 6 | AxiStreamDmaV2IpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2IpIntegrator.vhd | 0 | -| 192 | 6 | AxiStreamDmaRingRead | axi | axi/dma/rtl/v1/AxiStreamDmaRingRead.vhd | 1 | -| 193 | 6 | AxiStreamDmaWrite | axi | axi/dma/rtl/v1/AxiStreamDmaWrite.vhd | 4 | -| 194 | 6 | SyncStatusVector | base | base/sync/rtl/SyncStatusVector.vhd | 2 | -| 195 | 6 | SyncTrigRateVector | base | base/sync/rtl/SyncTrigRateVector.vhd | 1 | -| 196 | 6 | SyncTrigRateWrapper | base | base/sync/wrappers/SyncTrigRateWrapper.vhd | 0 | -| 197 | 6 | SynchronizerOneShotCntVectorFlatWrapper | base | base/sync/wrappers/SynchronizerOneShotCntVectorFlatWrapper.vhd | 0 | -| 198 | 7 | AxiLiteRamSyncStatusVector | axi | axi/axi-lite/rtl/AxiLiteRamSyncStatusVector.vhd | 1 | -| 199 | 7 | AxiStreamBatchingFifoIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamBatchingFifoIpIntegrator.vhd | 0 | -| 200 | 7 | AxiStreamMonIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamMonIpIntegrator.vhd | 0 | -| 201 | 7 | AxiStreamRingBufferIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamRingBufferIpIntegrator.vhd | 0 | -| 202 | 7 | AxiStreamMonAxiL | axi | axi/axi-stream/rtl/AxiStreamMonAxiL.vhd | 2 | -| 203 | 7 | AxiReadEmulateIpIntegrator | axi | axi/axi4/ip_integrator/AxiReadEmulateIpIntegrator.vhd | 0 | -| 204 | 7 | AxiRingBufferIpIntegrator | axi | axi/axi4/ip_integrator/AxiRingBufferIpIntegrator.vhd | 0 | -| 205 | 7 | AxiWriteEmulateIpIntegrator | axi | axi/axi4/ip_integrator/AxiWriteEmulateIpIntegrator.vhd | 0 | -| 206 | 7 | AxiStreamDmaRingReadIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaRingReadIpIntegrator.vhd | 0 | -| 207 | 7 | AxiStreamDmaWriteIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaWriteIpIntegrator.vhd | 0 | -| 208 | 7 | AxiStreamDma | axi | axi/dma/rtl/v1/AxiStreamDma.vhd | 1 | -| 209 | 7 | AxiStreamDmaFifo | axi | axi/dma/rtl/v1/AxiStreamDmaFifo.vhd | 1 | -| 210 | 7 | AxiStreamDmaRingWrite | axi | axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd | 1 | -| 211 | 7 | SyncStatusVectorFlatWrapper | base | base/sync/wrappers/SyncStatusVectorFlatWrapper.vhd | 0 | -| 212 | 7 | SyncTrigRateVectorFlatWrapper | base | base/sync/wrappers/SyncTrigRateVectorFlatWrapper.vhd | 0 | -| 213 | 8 | AxiLiteRamSyncStatusVectorIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteRamSyncStatusVectorIpIntegrator.vhd | 0 | -| 214 | 8 | AxiStreamMonAxiLIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamMonAxiLIpIntegrator.vhd | 0 | -| 215 | 8 | AxiMonAxiL | axi | axi/axi4/rtl/AxiMonAxiL.vhd | 1 | -| 216 | 8 | AxiStreamDmaFifoIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaFifoIpIntegrator.vhd | 0 | -| 217 | 8 | AxiStreamDmaIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaIpIntegrator.vhd | 0 | -| 218 | 8 | AxiStreamDmaRingWriteIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaRingWriteIpIntegrator.vhd | 0 | -| 219 | 9 | AxiMonAxiLIpIntegrator | axi | axi/axi4/ip_integrator/AxiMonAxiLIpIntegrator.vhd | 0 | diff --git a/docs/_meta/rtl_phase1_queue_overrides.json b/docs/_meta/rtl_phase1_queue_overrides.json deleted file mode 100644 index 474d21dbc1..0000000000 --- a/docs/_meta/rtl_phase1_queue_overrides.json +++ /dev/null @@ -1,85 +0,0 @@ -{ - "force_include_entities": [], - "force_include_paths": [], - "deferred_subsystems": [ - { - "name": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "name": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "name": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "name": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - } - ], - "deferred_entities": [ - { - "entity": "LutFixedDelay", - "reason": "Depends on SinglePortRamPrimitive under the current open-source flow." - } - ], - "deferred_paths": [], - "deferred_path_substrings": [ - { - "pattern": "protocols/pgp/pgp3/", - "reason": "PGP3 is intentionally deferred for now so current protocol work stays on pgp2b/pgp2fc/pgp4 and shared PGP blocks." - }, - { - "pattern": "axi/simlink/", - "reason": "Simulation support models are not part of the synthesizable phase-1 queue." - }, - { - "pattern": "/sim/", - "reason": "Simulation-only support modules are not part of the synthesizable phase-1 queue." - }, - { - "pattern": "/dummy/", - "reason": "Dummy-backed variants are deferred from the phase-1 executable queue." - }, - { - "pattern": "/altera/", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "/xilinx/", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "7Series", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "UltraScale", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "UltraScale+", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "/gth", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gtp", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gty", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gtx", - "reason": "GT-family implementation branches are deferred in phase 1." - } - ], - "preferred_paths_by_entity": {}, - "order_overrides": [] -} diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md deleted file mode 100644 index 50da460dc1..0000000000 --- a/docs/_meta/rtl_regression_handoff.md +++ /dev/null @@ -1,214 +0,0 @@ -# SURF RTL Regression Handoff - -## Objective -- Build a repo-wide regression system for synthesizable SURF RTL. -- Keep all executable test logic in Python. -- Use `pytest + cocotb + GHDL + ruckus`. -- Keep VHDL only for wrappers, shims, and required simulation models. - -## Chosen Constraints -- Python-only test logic -- VHDL wrappers allowed -- Whole-repo target -- Vendor-heavy modules deferred in phase 1 -- Comment new Python regression code at a tutorial level, assuming the reader may be new to cocotb -- Give each Python regression the normal SURF/SLAC file header and two distinct comment layers: a module-specific `Test methodology` block under that header and tutorial-style comments in the executable code body -- Give each checked-in cocotb-facing `*IpIntegrator.vhd` wrapper the normal SURF file banner plus section comments for shim setup, DUT instantiation, and any flattening/status wiring -- For any VHDL file created or edited during this work, run `./.venv/bin/vsg` with `vsg-linter.yml`, the same config CI uses, and use `--fix`/autofix on fixable issues before moving on -- Treat VHDL packages as transitively covered unless a behavioral function/procedure needs a dedicated wrapper -- Treat stale simulator cleanup as part of task completion: after any `pytest`, cocotb, GHDL, or similar launched verification step, sweep for leftover child processes and kill them before moving on - -## Quick Resume Snapshot -- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, and the current Ethernet coverage now spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the pure-VHDL RoCEv2 quartet (`EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator`). The remaining RoCEv2 requirement is still one cocotb test module per entity in `ethernet/RoCEv2/rtl`, but the last five entities depend on real `blue-*` submodules and therefore need a mixed-language simulator path rather than local stand-ins. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. -- Current axi frontier: complete for the intended simulator-friendly pass in this branch snapshot; do not resume from the older stale `AxiResize` note. -- Current validated-open issues: - - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core` remain untouched in phase 1, while the remaining RoCEv2 gap is the mixed-language bench path for the five RTL entities that instantiate generated submodules: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`. - - `EthMacRxImportXlgmii` and `EthMacTxExportXlgmii` are still placeholder no-op RTL; the checked-in tests now lock down that inert contract instead of claiming functional XLGMII support. -- Current planning discipline: - - Use manual user-directed area selection as the active source of truth for what to work on next. - - Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the actual validated branch frontier. - - Keep the graph and queue artifacts only as historical provenance or optional analysis context; do not use them as the next-module selector unless the user explicitly opts back into queue-driven planning. -- Current wrapper discipline: - - Prefer the existing subsystem `ip_integrator/` shim layers over bespoke record flattening. - - Keep first-pass wrapper benches intentionally narrow and document any omitted branches explicitly. - - Use `start_lockstep_clocks()` when a DUT depends on truly shared clock edges. - - Prefer explicit short sim-build keys for generated-wrapper benches when case metadata would otherwise create fragile build paths. - - When a wrapper is checked in, write it like the surrounding repo HDL: include the SLAC/SURF banner and enough section comments that a new session can identify the shim, DUT, and flattening regions quickly. - - For the current Ethernet slice, the checked-in wrappers under `ethernet/EthMacCore/wrappers/`, `ethernet/RawEthFramer/wrappers/`, `ethernet/UdpEngine/wrappers/`, `ethernet/IpV4Engine/wrappers/`, and the new `ethernet/RoCEv2/wrappers/` leaf adapters are the expected cocotb surfaces. Keep using those subsystem-local wrappers rather than rebuilding record-packing logic in Python. -- Current cocotb-file discipline: - - New test files should start with the standard SURF/SLAC header block. - - The `Test methodology` block belongs directly under that header. - - In-body tutorial comments are still required; the methodology block does not replace them. - -## Session Learnings To Preserve -- Start with the smallest stable wrapper that exposes the DUT cleanly to cocotb. Reuse the existing subsystem `ip_integrator/` shims before inventing bespoke flattening or a new subsystem-local wrapper. -- Prefer checked-in subsystem-local wrappers for durable integration patterns, including simulator-hostile generic adapters. -- If a Python cocotb file is permanent enough to check in, do not leave it with a custom or abbreviated header. Use the standard repo header immediately, then add the methodology block and tutorial comments in the same first pass. -- If a wrapper is permanent enough to check in, do not leave it as a bare anonymous adapter. Add the standard SURF banner and short section comments immediately, not as a cleanup pass later. -- For AXI and AXI-Lite benches, the practical first-pass shape is usually: - - cocotb protocol master on the control/request side, - - cocotb RAM or simple protocol model on the generated/response side, - - lightweight monitors on accepted handshakes when timing or burst shape matters. -- Do not rely on final memory contents alone when the contract includes timing-visible behavior. Record accepted handshakes if the bench is supposed to prove spacing, burst length, sideband propagation, partial-last-beat strobes, or arbitration order. -- For `COMMON_CLK_G` style wrappers, use one shared clock coroutine via `start_lockstep_clocks()` when the RTL expects true shared edges rather than merely equal nominal periods. -- For first-pass wrapper benches, prove the externally visible stable path first and defer shakier simulator-sensitive branches explicitly in the docs instead of stretching one bench to cover everything. -- `AxiStreamDmaV2Read` needed a real RTL/runtime fix rather than a bench workaround: keep the bounded byte-count conversion fix in `axi/axi4/rtl/AxiPkg.vhd` and the direct terminal-mask generation in `axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd`. The current wrapper only exposes an 8-bit `TUSER`, so the observable contract in the checked-in bench is first-user propagation plus payload/keep/id/dest and descriptor return fields. -- `tests/dsp/generic/dsp_test_utils.py` is now the shared home for DSP-specific signed helpers, rolling reference models, cocotb clock-settle timing, and generated FIR wrappers. Reuse it instead of cloning DSP arithmetic or wrapper boilerplate. -- Before writing new AXI-Lite, AXI Stream, SSI, or ethernet transaction code, search the nearest subsystem `tests/` package for an existing helper module first. Future sessions should assume that a reusable helper probably already exists and should only write new transaction plumbing after confirming the local helper layer is insufficient. -- `tests/ethernet/EthMacCore/ethmac_test_utils.py` is now the shared home for the current Ethernet MAC slice: flat EMAC beat helpers, Ethernet/IPv4/UDP packet builders, checksum reference code, MAC-config byte-order helpers, and minimum-frame padding helpers. Reuse it instead of cloning packet or sideband plumbing across `EthMacCore` benches. -- Do not replace `ethernet/RoCEv2/blue-*` with local test doubles when the target boundary is `ethernet/RoCEv2/rtl`. The intended shape is one cocotb bench per RTL entity in `ethernet/RoCEv2/rtl`, with `blue-crc`, `blue-rdma`, and `blue-lib` used as real transitive dependencies where instantiated. Under the current local toolchain only `ghdl` is available, so the pure-VHDL quartet is covered now and the remaining five mixed-language entities stay open until the runner supports real VHDL+Verilog simulation. -- RoCEv2 RTL entity matrix for the next session: - - Covered now with the current GHDL-only flow: `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, `RoceConfigurator` - - Still required, but must use real generated dependencies: `EthMacCrcAxiStreamWrapperSend` -> `blue-crc/mkCrcRawAxiStreamCustomSend.v`, `EthMacCrcAxiStreamWrapperRecv` -> `blue-crc/mkCrcRawAxiStreamCustomRecv.v`, `EthMacTxRoCEv2` -> send CRC wrapper, `EthMacRxRoCEv2` -> recv CRC wrapper, `RoceEngineWrapper` -> `blue-rdma/mkAxisTransportLayer.v` plus `blue-lib/` -- `tests/ethernet/RawEthFramer/raw_eth_test_utils.py` now holds the shared raw-Ethernet helper pieces: flat app-side beat helpers, raw-Ethernet header/frame builders, and lookup-handshake utilities reused by the `RawEthFramer`, `RawEthFramerRx`, and `RawEthFramerTx` benches. -- `tests/ethernet/UdpEngine/udp_test_utils.py` is now the shared home for the UDP slice: legacy-address constants, pseudo-frame builders, DHCP option helpers, and the common cocotb bench setup for the `ArpIpTable`, `UdpEngine*`, and `UdpEngineWrapper*` wrappers. Reuse it instead of rebuilding IPv4/UDP helper glue in each test module. -- `tests/ethernet/IpV4Engine/ipv4_test_utils.py` is now the shared home for the IPv4 slice: packet/header builders and common cocotb bench setup for the `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, and `IpV4Engine*` wrappers. Reuse it instead of cloning IPv4 framing helpers across that directory. -- `tests/protocols/ssi/ssi_test_utils.py` is the shared home for SSI transaction work: flat SSI endpoints, beat/frame helpers, contiguous-frame send, receive/no-output utilities, and `SOF`/`EOFE`-aware assertions. Use it instead of open-coding SSI handshake loops or terminal-flag checks. -- Across the AXI slices, prefer the subsystem helper paths that already exist for register transactions, frame movement, and setup. In practice that means reusing helpers such as `tests/common/regression_utils.py`, the AXI/ethernet subsystem utility modules, and any nearby module-family helpers before inventing a one-off local transaction wrapper. -- The current `EthMacCore` slice is intentionally a checked-in-wrapper-first rollout, not a cocotb-generated-wrapper experiment. Keep new Ethernet work on that same pattern unless the simulator forces a very local generic adapter. -- The XGMII import/export loopback behavior differs from the GMII path when `phyReady` drops mid-traffic: the blocked frame is retained and drains after link recovery, padded to Ethernet's minimum frame size if it was short. The GMII path drops that blocked frame. Future import/export coverage should preserve that distinction instead of forcing one common expectation. -- The current `EthMacRxImportXlgmii.vhd` and `EthMacTxExportXlgmii.vhd` leaves are placeholders: they drive no data-path activity and never pulse the count/status outputs. Future work should treat functional XLGMII support as an RTL gap, not as a missing bench. -- `EthMacRxCsum` reliably raises `IPERR` on a bad IPv4 header checksum, but the checked-in wrapper contract does not currently require `EOFE` for that case. Keep the negative test aligned to the real observable contract rather than to a stronger assumption. -- The RX/TX shift benches need a small idle-plus-settle gap before changing runtime shift controls because the underlying `AxiStreamShift` samples those controls while idle. Preserve that guardrail if those benches are refactored or expanded. -- `EthMacRxBypass` compares the EtherType field in the flattened EMAC byte-lane order, not normal wire-order host integer order. In practice that means a wire EtherType like `0x9000` must be compared as `x"0090"` at the wrapper/DUT generic boundary, just as `0x88B5` appears as `x"B588"` in the existing wrappers. -- Do not leave stale simulation trees behind between tasks. If a verification command launched `pytest`, cocotb, GHDL, or wrapper executables, treat post-run process cleanup as mandatory before the next edit or test cycle. - -## Current Status -Planning is complete and implementation is well underway. The agreed direction is a Python-only executable regression framework with tiered `smoke` and `functional` coverage. Existing VHDL TBs are reference material only and should be rewritten in Python when migrated, unless a thin wrapper is still useful for cocotb access. - -The repo now has the initial handoff artifacts, a checked-in inventory scaffold at `docs/_meta/rtl_regression_inventory.yaml`, and local bootstrap helpers in `scripts/setup_regression_env.sh` plus `.vscode/tasks.json`. The first pilot modules were `FifoAsync`, `AxiStreamFifoV2`, and `AxiLiteAsync`, and the work has since moved into a graph-guided bottom-up rollout across `base/`. - -The local machine now has `ghdl`, a working `.venv`, the Python regression packages, a repo-local `ruckus` link to `~/ruckus`, and a successful `make MODULES="$PWD" import` run. Local environment bootstrap is no longer the blocker. The first shared-helper-based pilot regression now exists in `tests/base/fifo/test_FifoAsync.py` and passes locally. - -New regressions are now being organized by subsystem under `tests/`, with shared helpers in `tests/common/`. The `FifoAsync` pilot lives in `tests/base/fifo/test_FifoAsync.py`, and `AxiStreamFifoV2` now lives in `tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py`. New work should follow that package layout instead of adding more flat files under `tests/`. - -`FifoAsync` now has a validated expanded 12-case matrix, `FifoSync` has a validated expanded 11-case matrix, `Synchronizer` and `SynchronizerVector` now each have validated 6-case matrices under `tests/base/sync/`, `RstPipeline` has a validated 4-case matrix under `tests/base/general/`, `SimpleDualPortRam` has a validated 5-case matrix under `tests/base/ram/`, `FifoOutputPipeline` has a validated 5-case matrix under `tests/base/fifo/`, and `FifoWrFsm` has a validated 4-case matrix under `tests/base/fifo/`. - -The next graph-guided 10-module follow-on is also now in place: `Crc32Parallel`, `Crc32`, `CRC32Rtl`, `RstSync`, `PwrUpRst`, `SynchronizerEdge`, `SynchronizerOneShot`, `TrueDualPortRam`, `LutRam`, and `FifoRdFsm`. The combined validation command for that batch is `./.venv/bin/python -m pytest -v tests/base/crc/test_Crc32Parallel.py tests/base/crc/test_Crc32.py tests/base/crc/test_CRC32Rtl.py tests/base/sync/test_RstSync.py tests/base/general/test_PwrUpRst.py tests/base/sync/test_SynchronizerEdge.py tests/base/sync/test_SynchronizerOneShot.py tests/base/ram/test_TrueDualPortRam.py tests/base/ram/test_LutRam.py tests/base/fifo/test_FifoRdFsm.py`, and it currently passes with `38 passed`. - -The next 15-module `base/` general/delay/sync batch is now also implemented and validated: `Arbiter`, `ClockDivider`, `Debouncer`, `Gearbox`, `Heartbeat`, `Mux`, `OneShot`, `RegisterVector`, `RstPipelineVector`, `Scrambler`, `WatchDogRst`, `SlvDelay`, `SlvFixedDelay`, `SynchronizerFifo`, and `SynchronizerOneShotCnt`. The combined validation command for that batch is `./.venv/bin/python -m pytest -n 0 -q tests/base/general/test_Arbiter.py tests/base/general/test_ClockDivider.py tests/base/general/test_Debouncer.py tests/base/general/test_Gearbox.py tests/base/general/test_Heartbeat.py tests/base/general/test_Mux.py tests/base/general/test_OneShot.py tests/base/general/test_RegisterVector.py tests/base/general/test_RstPipelineVector.py tests/base/general/test_Scrambler.py tests/base/general/test_WatchDogRst.py tests/base/delay/test_SlvDelay.py tests/base/delay/test_SlvFixedDelay.py tests/base/sync/test_SynchronizerFifo.py tests/base/sync/test_SynchronizerOneShotCnt.py`, and it currently passes with `41 passed`. - -The next 10-module wrapper/integration batch is now also implemented and validated: `DspComparator`, `Fifo`, `FifoCascade`, `FifoMux`, `AsyncGearbox`, `SynchronizerOneShotVector`, `SynchronizerOneShotCntVector`, `SyncStatusVector`, `SyncTrigPeriod`, and `SyncMinMax`. The combined validation command for that batch is `./.venv/bin/python -m pytest -n 0 -q tests/dsp/generic/test_DspComparator.py tests/base/fifo/test_Fifo.py tests/base/fifo/test_FifoCascade.py tests/base/fifo/test_FifoMux.py tests/base/general/test_AsyncGearbox.py tests/base/sync/test_SynchronizerOneShotVector.py tests/base/sync/test_SynchronizerOneShotCntVector.py tests/base/sync/test_SyncStatusVector.py tests/base/sync/test_SyncTrigPeriod.py tests/base/sync/test_SyncMinMax.py`, and it currently passes with `18 passed`. - -The remaining practical non-vendor, non-dummy `base/` modules are now also implemented and validated: `MasterRamIpIntegrator`, `SlaveRamIpIntegrator`, `DualPortRam`, `SlvDelayRam`, `SlvDelayFifo`, `SyncClockFreq`, `SyncTrigRate`, and `SyncTrigRateVector`. The combined validation command for that batch is `./.venv/bin/python -m pytest -n 0 -q tests/base/general/test_MasterRamIpIntegrator.py tests/base/general/test_SlaveRamIpIntegrator.py tests/base/ram/test_DualPortRam.py tests/base/delay/test_SlvDelayRam.py tests/base/delay/test_SlvDelayFifo.py tests/base/sync/test_SyncClockFreq.py tests/base/sync/test_SyncTrigRate.py tests/base/sync/test_SyncTrigRateVector.py`, and it currently passes with `15 passed`. - -`Crc32` now covers multiple common 32-bit polynomials instead of only the default IEEE CRC-32 polynomial. That test uses a thin wrapper at `base/crc/wrappers/Crc32PolyWrapper.vhd` because the local GHDL flow rejects direct command-line overrides of the `CRC_POLY_G : slv(31 downto 0)` generic. Pytest still defaults to `-n auto --dist=worksteal` through `pytest.ini` so parameterized regressions fan out across worker processes by default. - -The project now also has a shared helper path in `tests/common/regression_utils.py` for test scaffolding, but the wrapper policy is to keep durable cocotb-facing HDL shims checked in under subsystem-local `wrappers/` or `ip_integrator/` folders. `Heartbeat` and `Debouncer` remain useful examples of very small wrappers, but new permanent generic-adapter shims should follow the checked-in subsystem-local pattern. - -`tests/common/regression_utils.py` now also includes `start_lockstep_clocks()` for DUTs whose generics assume truly common clocks in both ports. Use that helper instead of launching two same-period clocks independently when the RTL assumes shared edge identity. - -`ethernet/EthMacCore/` now has checked-in regression coverage under `tests/ethernet/EthMacCore/` for both the original leaf slice and the deeper assembly layer. The current benches cover `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, `EthMacTop`, `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, `EthMacTxFifo`, `EthMacRxBypass`, and `EthMacTxBypass`. The import/export benches now also explicitly encode the current placeholder `XLGMII` contract so future functional XLGMII RTL work will show up as a deliberate expectation change instead of an accidental gap. The current Ethernet wrappers live under `ethernet/EthMacCore/wrappers/` and should be treated as the stable cocotb-facing surfaces for further `EthMacCore` work. - -`ethernet/UdpEngine/` and `ethernet/IpV4Engine/` also received a thin-area cleanup pass on this branch. The `UdpEngine` top/wrapper benches now cover additional client/server routing paths beyond the earlier single happy-path smoke, while `IpV4Engine` now has a top-level protocol-TX path and deeper `IcmpEngine` negative/recovery coverage. The combined local validation command for that focused follow-up is `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/EthMacCore/test_EthMacRxImport.py tests/ethernet/EthMacCore/test_EthMacTxExport.py tests/ethernet/EthMacCore/test_EthMacRxBypass.py tests/ethernet/EthMacCore/test_EthMacTxBypass.py tests/ethernet/UdpEngine/test_UdpEngine.py tests/ethernet/UdpEngine/test_UdpEngineWrapper.py tests/ethernet/IpV4Engine/test_IpV4Engine.py tests/ethernet/IpV4Engine/test_IcmpEngine.py`, and it passes locally with `14 passed`. - -`ethernet/RawEthFramer/` now also has checked-in regression coverage under `tests/ethernet/RawEthFramer/`. The earlier top-level `RawEthFramer` wrapper bench is joined by direct leaf benches for `RawEthFramerRx` and `RawEthFramerTx`, plus a `RawEthFramerPair` integration bench whose wrapper cross-connects two `RawEthFramer` instances to mirror the legacy `ethernet/RawEthFramer/tb/RawEthFramerTb.vhd` topology. The validated RX leaf bench covers lookup-gated unicast decode, short-frame trim behavior, broadcast bypass, and representative reject cases. The validated TX leaf bench now covers lookup-request exposure before forwarding, successful multi-beat unicast forwarding after lookup resolution, broadcast bypass with the observed padded wire image, and zero-MAC lookup-miss drop. The successful unicast leaf case intentionally models the nonzero lookup latency that the integrated `RawEthFramer` wrapper inserts before `ack`, so keep that timing assumption if the TX bench is expanded further. - -`ethernet/UdpEngine/` now has checked-in regression coverage under `tests/ethernet/UdpEngine/` as well. The current validated set covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, all backed by checked-in wrappers under `ethernet/UdpEngine/wrappers/` and the shared helper layer in `tests/ethernet/UdpEngine/udp_test_utils.py`. - -`ethernet/IpV4Engine/` now also has checked-in regression coverage under `tests/ethernet/IpV4Engine/`. The current validated set covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, all backed by checked-in wrappers under `ethernet/IpV4Engine/wrappers/` and the shared helper layer in `tests/ethernet/IpV4Engine/ipv4_test_utils.py`. The `IgmpV2Engine` leaf bench covers power-up reports, general-query re-arming, and report suppression on matching inbound membership reports; it also documents the leaf-level stale pseudo-header bytes that are ignored by downstream `IpV4EngineTx` assembly. - -The wrapper coverage policy is now more explicit in practice: test the wrapper-specific behavior, not the full leaf matrix again. `Fifo` validated both inferred sync/async selection branches, `FifoCascade` validated public stage-vector mapping plus a curated output smoke, and `FifoMux` is currently validated only on the stable split-to-narrow path. The pack-to-wide `FifoMux` path should be treated as still open rather than silently assumed covered. - -That same wrapper-policy lesson now applies to the late `base/sync` wrappers as well. `SyncClockFreq` is stable with a checked-in subsystem wrapper, but its common-clock measurement quantizes one count above the abstract target under the current GHDL flow, so the regression checks a bounded expected range rather than an exact integer. `SyncTrigRate` is intentionally covered as a wrapper/integration bench only: it proves aligned update publication, denser-window rate growth, reset-path liveness, and strobe pulse behavior, while exact min/max pipeline semantics remain the responsibility of the dedicated `SyncMinMax` leaf test. - -At this point the practical phase-1 `base/` rollout is effectively complete. The only uncovered non-dummy `base/` module is `LutFixedDelay`, and it remains deferred because it still depends on the vendor-backed `SinglePortRamPrimitive` path. The other remaining `base/` gaps are vendor-heavy or dummy-backed variants. - -The first post-`base/` `axi/` follow-on is now in place as well. `AxiStreamPipeline` is validated under `tests/axi/axi_stream/test_AxiStreamPipeline.py` using a thin flat-port adapter at `axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd`, and `AxiLiteCrossbar` is validated under `tests/axi/axi_lite/test_AxiLiteCrossbar.py` using the existing `axi/axi-lite/tb/AxiLiteCrossbarTb.vhd` harness as a cocotb-facing shell. The combined validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamPipeline.py tests/axi/axi_lite/test_AxiLiteCrossbar.py`, and it currently passes with `4 passed`. - -For `AxiStreamPipeline`, treat the zero-stage case as a true combinational pass-through and the staged cases as wrapper-visible buffered paths. The stable expectation under the current wrapper is sink-handshake latency of `PIPE_STAGES_G + 2` clocks plus bounded reset flush behavior, not a naive one-to-one mapping from the user generic name. For `AxiLiteCrossbar`, the useful regression surface is region routing, decode-miss `DECERR` handling, and concurrent traffic through the existing cascaded harness topology rather than a broad generic sweep. - -`AxiStreamMux` is now validated under `tests/axi/axi_stream/test_AxiStreamMux.py` using a thin two-input adapter at `axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd`. The module-local validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamMux.py`, and it currently passes with `3 passed`. A small follow-on sanity run across `tests/axi/axi_stream/test_AxiStreamPipeline.py`, `tests/axi/axi_stream/test_AxiStreamMux.py`, and `tests/axi/axi_lite/test_AxiLiteCrossbar.py` also passes with `7 passed`. Keep the validated subset intentionally narrow: indexed arbitration with explicit priority plus `disableSel`, routed `TDEST`/`TID` remap under backpressure, and staged asynchronous active-low reset recovery in passthrough mode. Interleave and explicit rearbitrate branches remain open for later work. Also note the mux-specific nuance from this bench: `disableSel` is applied before the separate priority-mask generation, so a disabled higher-priority source can still suppress lower-priority requesters. - -`AxiStreamDeMux` is now validated under `tests/axi/axi_stream/test_AxiStreamDeMux.py` using a thin one-input/two-output adapter at `axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd`. The module-local validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamDeMux.py`, and it currently passes with `3 passed`. A small follow-on sanity run across `tests/axi/axi_stream/test_AxiStreamPipeline.py`, `tests/axi/axi_stream/test_AxiStreamMux.py`, `tests/axi/axi_stream/test_AxiStreamDeMux.py`, and `tests/axi/axi_lite/test_AxiLiteCrossbar.py` passes with `10 passed`. Keep the validated subset intentionally narrow: indexed decode to both outputs, exact-match routed decode under output backpressure, and dynamic-route table behavior including unmatched-destination drop plus staged asynchronous active-low reset flush. Wildcard-route patterns and larger fanout counts remain open for later work. - -The next five flat-queue modules are now also in place and validated. `AxiStreamResize` uses `axi/axi-stream/ip_integrator/AxiStreamResizeIpIntegrator.vhd` plus `tests/axi/axi_stream/test_AxiStreamResize.py`; `AxiLiteAsync` uses `axi/axi-lite/ip_integrator/AxiLiteAsyncIpIntegrator.vhd` plus `tests/axi/axi_lite/test_AxiLiteAsync.py`; `AxiLiteMaster` uses `axi/axi-lite/ip_integrator/AxiLiteMasterIpIntegrator.vhd` plus `tests/axi/axi_lite/test_AxiLiteMaster.py`; `AxiLiteToDrp` uses `axi/bridge/ip_integrator/AxiLiteToDrpIpIntegrator.vhd` plus `tests/axi/bridge/test_AxiLiteToDrp.py`; and `AxiDualPortRam` is validated through the existing `axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd` wrapper plus `tests/axi/axi_lite/test_AxiDualPortRam.py`. The five-module validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamResize.py tests/axi/axi_lite/test_AxiLiteAsync.py tests/axi/axi_lite/test_AxiLiteMaster.py tests/axi/bridge/test_AxiLiteToDrp.py tests/axi/axi_lite/test_AxiDualPortRam.py`, and it currently passes with `10 passed`. A broader AXI follow-on sanity run across pipeline, mux, demux, resize, crossbar, async, master, DRP bridge, and dual-port RAM also passes with `20 passed`. - -The next 10 generated-queue AXI modules are now also in place and validated. `AxiLiteRegs`, `AxiLiteRespTimer`, `AxiLiteSlave`, `AxiLiteWriteFilter`, and `AxiVersion` are covered under `tests/axi/axi_lite/` with thin subsystem-local wrappers in `axi/axi-lite/ip_integrator/`. `AxiStreamCombiner`, `AxiStreamFlush`, `AxiStreamGearboxPack`, `AxiStreamGearboxUnpack`, and `AxiStreamSplitter` are covered under `tests/axi/axi_stream/` with thin subsystem-local wrappers in `axi/axi-stream/ip_integrator/`. The combined validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_lite/test_AxiLiteRegs.py tests/axi/axi_lite/test_AxiLiteRespTimer.py tests/axi/axi_lite/test_AxiLiteSlave.py tests/axi/axi_lite/test_AxiLiteWriteFilter.py tests/axi/axi_lite/test_AxiVersion.py tests/axi/axi_stream/test_AxiStreamCombiner.py tests/axi/axi_stream/test_AxiStreamFlush.py tests/axi/axi_stream/test_AxiStreamGearboxPack.py tests/axi/axi_stream/test_AxiStreamGearboxUnpack.py tests/axi/axi_stream/test_AxiStreamSplitter.py`, and it currently passes with `14 passed`. - -Keep the validated subset intentionally narrow for the two most timing-sensitive wrappers. `AxiStreamResize` covers equal-width pass-through plus curated upsize/downsize cases with sideband alignment and staged reset flush. `AxiLiteMaster` covers request/ack sequencing, staggered AXI ready/valid handshakes, propagated `SLVERR` responses, and reset return to idle. `AxiDualPortRam` covers AXI round-trips, system-port visibility, byte-masked system writes, and AXI write-disable error responses through the existing wrapper. `AxiLiteAsync` is currently validated only on the stable `COMMON_CLK_G=true` wrapper path; the asynchronous reset-crossing branches remain open for later work. `AxiLiteToDrp` is currently validated only on the stable common-clock non-arbitrated path with timeout recovery; the async arbitration branch remains open for later work. - -`AxiRateGen` is now also validated under `tests/axi/axi4/test_AxiRateGen.py` using `axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd`. The module-local validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiRateGen.py`, and it currently passes with `1 passed`. Keep the validated subset intentionally narrow here too: the stable `COMMON_CLK_G=true` path covers AXI-Lite register programming, timer-spaced generated AXI writes, and generated-read completion through a cocotb AXI RAM model, while the asynchronous AXI-Lite crossing branches remain open for later work. - -The remaining final 11 `axi/` modules from the axi-first pass are now also implemented and validated. The new checked-in benches are: -- `tests/axi/axi4/test_AxiReadEmulate.py` -- `tests/axi/axi4/test_AxiWriteEmulate.py` -- `tests/axi/axi4/test_AxiRingBuffer.py` -- `tests/axi/axi4/test_AxiMonAxiL.py` -- `tests/axi/axi_lite/test_AxiLiteRamSyncStatusVector.py` -- `tests/axi/axi_stream/test_AxiStreamMonAxiL.py` -- `tests/axi/dma/test_AxiStreamDmaWrite.py` -- `tests/axi/dma/test_AxiStreamDma.py` -- `tests/axi/dma/test_AxiStreamDmaFifo.py` -- `tests/axi/dma/test_AxiStreamDmaRingRead.py` -- `tests/axi/dma/test_AxiStreamDmaRingWrite.py` - -The supporting wrappers added for that batch are: -- `axi/axi4/ip_integrator/AxiReadEmulateIpIntegrator.vhd` -- `axi/axi4/ip_integrator/AxiWriteEmulateIpIntegrator.vhd` -- `axi/axi4/ip_integrator/AxiRingBufferIpIntegrator.vhd` -- `axi/axi4/ip_integrator/AxiMonAxiLIpIntegrator.vhd` -- `axi/axi-lite/ip_integrator/AxiLiteRamSyncStatusVectorIpIntegrator.vhd` -- `axi/axi-stream/ip_integrator/AxiStreamMonAxiLIpIntegrator.vhd` -- `axi/dma/ip_integrator/AxiStreamDmaWriteIpIntegrator.vhd` -- `axi/dma/ip_integrator/AxiStreamDmaFifoIpIntegrator.vhd` -- `axi/dma/ip_integrator/AxiStreamDmaIpIntegrator.vhd` -- `axi/dma/ip_integrator/AxiStreamDmaRingReadIpIntegrator.vhd` -- `axi/dma/ip_integrator/AxiStreamDmaRingWriteIpIntegrator.vhd` - -The combined validation command for that batch is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiReadEmulate.py tests/axi/axi4/test_AxiWriteEmulate.py tests/axi/axi4/test_AxiRingBuffer.py tests/axi/axi4/test_AxiMonAxiL.py tests/axi/axi_lite/test_AxiLiteRamSyncStatusVector.py tests/axi/axi_stream/test_AxiStreamMonAxiL.py tests/axi/dma/test_AxiStreamDmaWrite.py tests/axi/dma/test_AxiStreamDma.py tests/axi/dma/test_AxiStreamDmaFifo.py tests/axi/dma/test_AxiStreamDmaRingRead.py tests/axi/dma/test_AxiStreamDmaRingWrite.py`, and it passes locally with `11 passed`. - -One small RTL fix landed during that validation pass because the new `AxiStreamDmaRingWrite` test exposed a real simulation-width hazard: `axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd` now slices `dmaAck.size` back to `RAM_DATA_WIDTH_C` before incrementing `nextAddr`. Keep that change; it is what allows the checked-in narrow wrapper to simulate cleanly under GHDL. - -A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instantiation_graph.md` and `docs/_meta/rtl_instantiation_graph.json`, and the same generator now also emits a path-qualified bottom-up phase-1 queue at `docs/_meta/rtl_phase1_queue.md` and `docs/_meta/rtl_phase1_queue.json`. Keep the graph and queue for provenance, but treat them as historical context rather than as the default source of truth for what to implement next. - -## Immediate Next Task -If the user keeps the focus on `ethernet/RoCEv2`, the next real step is enabling a mixed-language cocotb path for the five remaining RTL entities listed above. Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the real validated subset, and do not reintroduce local stand-ins for `blue-*`. - -## Read Order -1. `docs/_meta/rtl_regression_handoff.md` -2. `docs/_meta/rtl_regression_progress.md` -3. `docs/_meta/rtl_regression_plan.md` -4. `docs/_meta/rtl_phase1_queue.md` only if historical graph output is useful for context; it is no longer the active planning driver. - -Before writing code in a fresh session: -1. Re-read the Python comment rules and the checked-in wrapper comment/header rules above. -2. If adding a permanent `*IpIntegrator.vhd`, include the standard SURF banner and section comments in the first edit, not as an afterthought. -3. If adding a Python regression, include the standard SURF/SLAC header, the `Test methodology` header block, and in-body tutorial comments in the first draft. -4. If creating or editing any VHDL file, run `./.venv/bin/vsg -c vsg-linter.yml ...` on that file set, use `--fix` when possible, and rerun the same lint command until it is clean. -5. After any step that launches `pytest`, cocotb, GHDL, or another simulator process, sweep for stale child processes and kill any leftovers before starting the next step. - -## Important Repo Facts -- New Python regressions should be organized under subsystem packages in `tests/` -- Shared Python regression helper lives in `tests/common/regression_utils.py` -- `tests/common/regression_utils.py` now supports both test-local extra VHDL source lists and generated test-local wrapper emission for wrapper-based cases -- `tests/common/regression_utils.py` also now provides `start_lockstep_clocks()` for `COMMON_CLK_G` style benches that require truly shared edges -- When starting a new test, check for nearby shared helper modules before writing any new transaction boilerplate. The expected search order is: `tests/common/`, then the current subsystem package, then closely related subsystem packages that already cover the same protocol family. -- For AXI-Lite benches, prefer existing helpers for repeated register reads/writes, environment decoding, and common bench setup rather than spelling out raw transactions in every file. -- For AXI Stream benches, prefer existing helpers for beat/frame packing, contiguous-frame driving, whole-frame receive, no-output checks, and handshake observation rather than writing custom ready/valid loops unless the DUT exposes a genuinely new contract. -- For SSI benches, prefer `tests/protocols/ssi/ssi_test_utils.py` for beat models, frame helpers, `EOFE`/`SOF` handling, and sink/source setup instead of duplicating SSI transaction utilities in a local test file. -- Default comment style for new cocotb tests has two parts: a wrapped four-bullet `Test methodology` header (`Sweep`, `Stimulus`, `Checks`, `Timing`) plus tutorial-style in-body comments that explain what each coroutine step is doing and why -- New cocotb tests should also use the standard SURF/SLAC file header, not a shortened local variant -- The methodology header should be module-specific and describe the real curated sweep, driven sequence, expected outputs/state changes, and timing checks; avoid generic boilerplate -- Keep methodology comment lines to a normal readable width in the source file -- Checked-in cocotb-facing `*IpIntegrator.vhd` files should also follow repo style: standard SLAC/SURF banner at the top and short section comments marking shim setup, DUT hookup, and flattening/status export logic -- For AXI Stream and AXI-Lite record ports, prefer the existing IP-integrator shim entities to flatten record interfaces for cocotb instead of hand-writing record packing in each wrapper -- If an AXI wrapper needs DUT-specific extra signals, keep the standard shim pair for the bus itself and only wire the extra signals manually -- More generally, if any module needs a VHDL shim layer to fit cleanly into the cocotb flow, that shim belongs in the nearest real subsystem `ip_integrator/` tree rather than under `tests/` -- Do not use generic `hdl/` buckets for cocotb-facing adapter layers; reserve those locations for genuinely different kinds of HDL support -- Many VHDL wrappers live under `*/tb/` -- The initial regression inventory lives in `docs/_meta/rtl_regression_inventory.yaml` -- The RTL instantiation graph lives in `docs/_meta/rtl_instantiation_graph.{md,json}` -- The generated path-qualified phase-1 queue lives in `docs/_meta/rtl_phase1_queue.{md,json}`, but it is now historical context only rather than the next-module source of truth -- Manual phase-1 queue deferrals and order overrides still live in `docs/_meta/rtl_phase1_queue_overrides.json`, but that file is not the active task-selection mechanism anymore -- Use `./.venv/bin/python ...` for repo-local Python commands unless the virtualenv has already been activated in the current shell; do not assume a `python` shim exists on `PATH` -- If GHDL rejects a direct command-line override for a non-scalar or real generic, prefer a generated thin test-only wrapper over simulator-specific literal workarounds or another checked-in one-off HDL shim -- If a wrapper branch is unstable under the current open-source flow, keep the validated subset narrow and record the omitted branch explicitly in the docs instead of over-claiming wrapper coverage -- Use `ps -Ao pid,ppid,stat,time,command` when needed to find stale simulation children, then terminate only the leftover run trees instead of broad process classes -- `LutFixedDelay` remains intentionally deferred because it depends on `SinglePortRamPrimitive`; do not accidentally treat the now-small remaining `base/` set as phase-1 work that still needs to be forced through -- Regenerate the graph and the phase-1 queue with `./.venv/bin/python scripts/build_rtl_instantiation_graph.py` only when historical analysis is useful or the user explicitly asks for it -- Local bootstrap entrypoint: `scripts/setup_regression_env.sh` -- Local `ruckus` is linked from `~/ruckus` - -## Resume Rule -If resuming implementation, update `docs/_meta/rtl_regression_progress.md` first. diff --git a/docs/_meta/rtl_regression_inventory.yaml b/docs/_meta/rtl_regression_inventory.yaml deleted file mode 100644 index 7b84471fd9..0000000000 --- a/docs/_meta/rtl_regression_inventory.yaml +++ /dev/null @@ -1,700 +0,0 @@ -version: 1 -last_updated: 2026-03-21 - -field_guide: - entity: "Synthesizable RTL entity name" - path: "Path to the synthesizable RTL source file" - subsystem: "High-level repo grouping used for rollout and sharding" - tier: "One of functional_python, smoke_python, wrapper_required, deferred_vendor_heavy" - status: "Implementation state for this inventory row" - priority: "Rollout priority; pilot marks the initial implementation set" - wrapper_path: "Optional VHDL wrapper/shim used for cocotb access" - python_test: "Planned or implemented Python regression entrypoint" - reference_assets: "Legacy assets worth mining for intent, not preserving as execution requirements" - notes: "Short implementation notes" - deferred_reason: "Required when tier is deferred_vendor_heavy" - -inventory_rules: - - "Every synthesizable RTL entity should eventually appear exactly once in this inventory." - - "Executable regression logic must live in Python." - - "VHDL may remain only as thin wrappers, shims, or required simulation models." - - "Legacy VHDL testbenches are reference material, not a preservation target." - - "Generic-heavy modules should prefer functional_python over smoke_python when actively implemented." - -modules: - - entity: Crc32Parallel - path: base/crc/rtl/Crc32Parallel.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/crc/test_Crc32Parallel.py - reference_assets: [] - notes: "Graph-guided CRC leaf with validated coverage for byte-width variation, registered vs direct input handling, and reset polarity/style variants against a shared Python CRC model." - deferred_reason: "" - - - entity: Crc32 - path: base/crc/rtl/Crc32.vhd - subsystem: base - tier: functional_python - status: implemented_validated_expanded - priority: phase1_low_level - wrapper_path: base/crc/wrappers/Crc32PolyWrapper.vhd - python_test: tests/base/crc/test_Crc32.py - reference_assets: [] - notes: "Graph-guided generic CRC leaf with validated coverage for IEEE CRC-32, Castagnoli, and Koopman-style 32-bit polynomial cases plus byte-width, input-register, and reset polarity/style variation. Uses a thin test-only wrapper because the local GHDL flow rejects direct command-line overrides of the 32-bit `CRC_POLY_G` `slv` generic." - deferred_reason: "" - - - entity: CRC32Rtl - path: base/crc/rtl/CRC32Rtl.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/crc/test_CRC32Rtl.py - reference_assets: [] - notes: "Legacy-compatible fixed-polynomial CRC leaf with validated baseline behavioral coverage for synchronous and asynchronous reset handling and reset polarity variation." - deferred_reason: "" - - - entity: RstSync - path: base/sync/rtl/RstSync.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_RstSync.py - reference_assets: [] - notes: "High-fanout reset synchronizer from the graph-guided leaf set. Validated coverage includes release-delay behavior, active-high vs active-low reset polarity, asynchronous vs synchronous power-on reset handling, and bypass/no-output configurations." - deferred_reason: "" - - - entity: PwrUpRst - path: base/general/rtl/PwrUpRst.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/general/test_PwrUpRst.py - reference_assets: [] - notes: "Reusable reset-generator primitive with validated coverage for counter-based startup stretch behavior, synchronous vs asynchronous reset handling, and reset polarity variation." - deferred_reason: "" - - - entity: SynchronizerEdge - path: base/sync/rtl/SynchronizerEdge.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SynchronizerEdge.py - reference_assets: [] - notes: "Graph-guided edge-detect synchronizer with validated coverage for rising/falling pulse detection through different sync depths, reset polarity/style variation, and bypass handling." - deferred_reason: "" - - - entity: SynchronizerOneShot - path: base/sync/rtl/SynchronizerOneShot.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SynchronizerOneShot.py - reference_assets: [] - notes: "Graph-guided one-shot synchronizer with validated coverage for single-pulse capture, stretched output behavior, reset polarity/style variation, active-low output mode, and bypass operation." - deferred_reason: "" - - - entity: TrueDualPortRam - path: base/ram/inferred/TrueDualPortRam.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/ram/test_TrueDualPortRam.py - reference_assets: [] - notes: "Reusable dual-port RAM primitive with validated direct cocotb coverage for read-first, write-first, and no-change modes, registered output behavior, byte-write masking, and reset polarity/style variants." - deferred_reason: "" - - - entity: LutRam - path: base/ram/inferred/LutRam.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/ram/test_LutRam.py - reference_assets: [] - notes: "Reusable LUTRAM primitive with validated coverage for combinational and registered variants, read-first/write-first/no-change behavior, multiport access, byte-write masking, and reset polarity/style variants." - deferred_reason: "" - - - entity: FifoRdFsm - path: base/fifo/rtl/inferred/FifoRdFsm.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/fifo/test_FifoRdFsm.py - reference_assets: [] - notes: "Graph-guided FIFO read-side primitive with validated coverage for standard vs FWFT behavior, block vs distributed memory modes, count progression, visible prefetch behavior, underflow-safe idle behavior, and reset polarity/style variants." - deferred_reason: "" - - - entity: SynchronizerVector - path: base/sync/rtl/SynchronizerVector.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SynchronizerVector.py - reference_assets: [] - notes: "High-reuse `base/sync` vector leaf selected from the instantiation graph. Validated curated matrix covers width variation, stage-depth latency, synchronous vs asynchronous reset handling, active-high vs active-low reset polarity, output inversion, and bypass behavior." - deferred_reason: "" - - - entity: RstPipeline - path: base/general/rtl/RstPipeline.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/general/test_RstPipeline.py - reference_assets: [] - notes: "High-reuse `base/general` reset-distribution leaf selected from the instantiation graph. Validated matrix covers stage-depth latency and `INV_RST_G` behavior; timing-only and synthesis-only generics remain intentionally out of scope." - deferred_reason: "" - - - entity: SimpleDualPortRam - path: base/ram/inferred/SimpleDualPortRam.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/ram/test_SimpleDualPortRam.py - reference_assets: [] - notes: "Graph-guided shared RAM primitive with validated direct cocotb coverage for baseline port-A write/port-B read operation, optional output register behavior, byte-write masking, and synchronous/asynchronous reset polarity variants on the read side." - deferred_reason: "" - - - entity: FifoOutputPipeline - path: base/fifo/rtl/FifoOutputPipeline.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/fifo/test_FifoOutputPipeline.py - reference_assets: [] - notes: "Graph-guided FIFO leaf with validated coverage for zero-latency passthrough, pipelined ordering, backpressure holding behavior, and synchronous/asynchronous reset polarity variants using a small FWFT-style source model." - deferred_reason: "" - - - entity: FifoWrFsm - path: base/fifo/rtl/inferred/FifoWrFsm.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/fifo/test_FifoWrFsm.py - reference_assets: [] - notes: "Graph-guided FIFO write-side primitive with validated coverage for startup readiness, count/index progression, full and overflow behavior, programmable-full threshold behavior, gray-coded async mode, and reset polarity/style variants." - deferred_reason: "" - - - entity: Synchronizer - path: base/sync/rtl/Synchronizer.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_Synchronizer.py - reference_assets: [] - notes: "High-reuse `base/sync` leaf selected from the instantiation graph. Validated curated matrix covers synchronous vs asynchronous reset handling, active-high vs active-low reset polarity, stage-depth latency, output inversion, and bypass behavior without introducing a wrapper." - deferred_reason: "" - - - entity: FifoSync - path: base/fifo/rtl/inferred/FifoSync.vhd - subsystem: base - tier: functional_python - status: implemented_validated_expanded - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/fifo/test_FifoSync.py - reference_assets: - - base/fifo/tb/FifoFwftTb.vhd - - base/fifo/tb/FwftCntTb.vhd - notes: "Bottom-up follow-on to FifoAsync. Expanded validated matrix covers FWFT vs standard mode, block vs distributed RAM, reset polarity/style variants, wider/deeper sizing, FWFT pipeline behavior, and threshold-focused cases for the synchronous implementation path." - deferred_reason: "" - - - entity: FifoAsync - path: base/fifo/rtl/inferred/FifoAsync.vhd - subsystem: base - tier: functional_python - status: implemented_validated_expanded - priority: pilot - wrapper_path: "" - python_test: tests/base/fifo/test_FifoAsync.py - reference_assets: - - base/sync/tb/SynchronizerFifoTb.vhd - notes: "Low-level async FIFO pilot. Expanded validated matrix covers FWFT vs standard mode, block vs distributed RAM, reset polarity/style variants, wider/deeper sizing, non-default sync depth, pipeline behavior, and threshold-focused cases. The matrix intentionally excludes TPD_G and INIT_G as non-behavioral here, and BYP_RAM_G because the current implementation does not exercise a separate bypass-RAM path." - deferred_reason: "" - - - entity: DspComparator - path: dsp/generic/fixed/DspComparator.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/dsp/generic/test_DspComparator.py - reference_assets: [] - notes: "First validated `dsp/` leaf in the new cocotb flow. Coverage focuses on comparator truth behavior and pipeline/reset variation rather than a large DSP-generic sweep." - deferred_reason: "" - - - entity: DspAddSub - path: dsp/generic/fixed/DspAddSub.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/dsp/generic/test_DspAddSub.py - reference_assets: - - dsp/generic/tb/DspAddSubTb.vhd - notes: "Validated signed add and subtract behavior with direct and pipelined output paths, including backpressure hold and reset clearing. The legacy VHDL bench only provided free-running stimulus, so the cocotb bench replaces it with explicit arithmetic and interface assertions." - deferred_reason: "" - - - entity: FirFilterTap - path: dsp/generic/fixed/FirFilterTap.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: generated_test_local - python_test: tests/dsp/generic/test_FirFilterTap.py - reference_assets: [] - notes: "Validated signed multiply-accumulate behavior for both generic coefficient initialization and runtime coefficient updates through a generated wrapper. The bench also checks that disabled cycles hold the previous cascade output." - deferred_reason: "" - - - entity: DspPreSubMult - path: dsp/generic/fixed/DspPreSubMult.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/dsp/generic/test_DspPreSubMult.py - reference_assets: [] - notes: "Validated signed pre-subtract multiply behavior, output hold under backpressure, and reset recovery with a direct arithmetic reference model." - deferred_reason: "" - - - entity: DspSquareDiffMult - path: dsp/generic/fixed/DspSquareDiffMult.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/dsp/generic/test_DspSquareDiffMult.py - reference_assets: [] - notes: "Validated signed square-difference multiplication, output hold under backpressure, and reset recovery with explicit Python arithmetic checks." - deferred_reason: "" - - - entity: BoxcarIntegrator - path: dsp/generic/fixed/BoxcarIntegrator.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/dsp/generic/test_BoxcarIntegrator.py - reference_assets: - - dsp/generic/tb/BoxcarIntegratorTb.vhd - notes: "Validated unsigned and signed modes, direct and registered output paths, `obAck` hold behavior, and `intCount` reconfiguration. The cocotb bench keeps the useful rolling-sum intent from the legacy bench but adds explicit interface assertions." - deferred_reason: "" - - - entity: BoxcarFilter - path: dsp/generic/fixed/BoxcarFilter.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/dsp/generic/test_BoxcarFilter.py - reference_assets: - - dsp/generic/tb/BoxcarFilterTb.vhd - notes: "Validated the integrated boxcar filter output scaling and hold behavior with a Python rolling-average model, replacing the legacy demo-style ramp-only bench with explicit output checks." - deferred_reason: "" - - - entity: FirFilterSingleChannel - path: dsp/generic/fixed/FirFilterSingleChannel.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/dsp/generic/test_FirFilterSingleChannel.py - reference_assets: - - dsp/generic/tb/FirFilterSingleChannelTb.vhd - notes: "Validated common-clock FIR data flow, sideband alignment, and AXI-Lite coefficient programming through a generated wrapper. The new bench keeps the useful coefficient-programming intent from the legacy environment but replaces its unasserted waveform stimulus with explicit filtered-output checks." - deferred_reason: "" - - - entity: FirFilterMultiChannel - path: dsp/generic/fixed/FirFilterMultiChannel.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/dsp/generic/test_FirFilterMultiChannel.py - reference_assets: [] - notes: "Validated common-clock parallel multichannel FIR frame flow and AXI-Lite coefficient updates through a generated wrapper, using a per-channel Python FIR reference model and cocotbext-axi stream endpoints." - deferred_reason: "" - - - entity: Fifo - path: base/fifo/rtl/Fifo.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/fifo/test_Fifo.py - reference_assets: [] - notes: "Validated wrapper-focused coverage for the inferred backend only. The regression checks sync-vs-async branch selection, wrapper-level data flow, `INIT_G` forwarding, and the sync-mode `wr_data_count`/`rd_data_count` aliasing rule instead of replaying the full FIFO primitive matrix." - deferred_reason: "" - - - entity: FifoCascade - path: base/fifo/rtl/FifoCascade.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/fifo/test_FifoCascade.py - reference_assets: [] - notes: "Validated wrapper-specific coverage for inferred FWFT paths. The regression checks public `progFullVec`/`progEmptyVec` stage mapping plus a curated output smoke; it intentionally does not claim full multi-stage drain ordering under the current GHDL flow." - deferred_reason: "" - - - entity: FifoMux - path: base/fifo/rtl/FifoMux.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/fifo/test_FifoMux.py - reference_assets: [] - notes: "Validated wrapper-specific coverage currently targets the stable split-to-narrow path, including endian-aware slicing and reset-safe drain behavior. The pack-to-wide branch remains intentionally unclaimed in phase 1 because it did not surface a stable visible output in the current open-source flow." - deferred_reason: "" - - - entity: AsyncGearbox - path: base/general/rtl/AsyncGearbox.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/general/test_AsyncGearbox.py - reference_assets: [] - notes: "Validated asynchronous gearbox wrapper with a Python bit-level reference model, covering representative width conversion and reset behavior without trying to exhaust the full ratio space." - deferred_reason: "" - - - entity: SynchronizerOneShotVector - path: base/sync/rtl/SynchronizerOneShotVector.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SynchronizerOneShotVector.py - reference_assets: [] - notes: "Validated vectorized one-shot synchronizer coverage for lane independence and bypass behavior using a small curated lane matrix." - deferred_reason: "" - - - entity: SynchronizerOneShotCntVector - path: base/sync/rtl/SynchronizerOneShotCntVector.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: generated_test_local - python_test: tests/base/sync/test_SynchronizerOneShotCntVector.py - reference_assets: [] - notes: "Validated counted vector one-shot coverage using a generated test-local wrapper to flatten the array-typed output into a cocotb-friendly interface." - deferred_reason: "" - - - entity: SyncStatusVector - path: base/sync/rtl/SyncStatusVector.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/base/sync/test_SyncStatusVector.py - reference_assets: [] - notes: "Validated status-vector coverage for count/IRQ snapshot behavior. Uses a generated test-local wrapper for the vectorized count output and a lockstep shared-clock helper when `COMMON_CLK_G=true`." - deferred_reason: "" - - - entity: SyncTrigPeriod - path: base/sync/rtl/SyncTrigPeriod.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SyncTrigPeriod.py - reference_assets: [] - notes: "Validated trigger-period monitor with curated common-clock coverage for period accumulation and reset behavior." - deferred_reason: "" - - - entity: SyncMinMax - path: base/sync/rtl/SyncMinMax.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SyncMinMax.py - reference_assets: [] - notes: "Validated common-clock min/max snapshot behavior, including `rstStat` reseeding. Current phase-1 coverage is intentionally limited to the stable common-clock path." - deferred_reason: "" - - - entity: MasterRamIpIntegrator - path: base/general/ip_integrator/MasterRamIpIntegrator.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/general/test_MasterRamIpIntegrator.py - reference_assets: [] - notes: "Validated IP-integrator wrapper coverage for master-side write and read request forwarding, including handshake-safe addressing and shared comment-rich cocotb sequencing." - deferred_reason: "" - - - entity: SlaveRamIpIntegrator - path: base/general/ip_integrator/SlaveRamIpIntegrator.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/general/test_SlaveRamIpIntegrator.py - reference_assets: [] - notes: "Validated IP-integrator wrapper coverage for slave-side data return and write acceptance behavior using direct cocotb handshakes against the exported RAM-style ports." - deferred_reason: "" - - - entity: DualPortRam - path: base/ram/inferred/DualPortRam.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/ram/test_DualPortRam.py - reference_assets: [] - notes: "Validated inferred dual-port RAM wrapper with curated coverage for independent port readback, write-mode semantics, registered-output behavior, byte-write masking, and reset polarity variation." - deferred_reason: "" - - - entity: SlvDelayRam - path: base/delay/rtl/SlvDelayRam.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/delay/test_SlvDelayRam.py - reference_assets: [] - notes: "Validated RAM-backed delay line for configured latency, enable-hold behavior, and reset handling. The bench documents the observed GHDL-visible latency offset instead of pretending the comment-level ideal is cycle-exact." - deferred_reason: "" - - - entity: SlvDelayFifo - path: base/delay/rtl/SlvDelayFifo.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/delay/test_SlvDelayFifo.py - reference_assets: [] - notes: "Validated FIFO-backed delay line with curated coverage for timestamp-ordered delayed delivery and a short-delay smoke that stays inside the stable visible behavior under the current GHDL flow." - deferred_reason: "" - - - entity: SyncClockFreq - path: base/sync/rtl/SyncClockFreq.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/base/sync/test_SyncClockFreq.py - reference_assets: [] - notes: "Validated frequency-monitor wrapper using a generated real-generic shim and lockstep shared-clock helper. The common-clock case is checked against a bounded expected range because the current GHDL-visible quantization lands one count above the abstract target." - deferred_reason: "" - - - entity: SyncTrigRate - path: base/sync/rtl/SyncTrigRate.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/base/sync/test_SyncTrigRate.py - reference_assets: [] - notes: "Validated wrapper/integration coverage for aligned update publication, denser-window rate growth, reset-path liveness, and update-strobe pulse behavior. Exact min/max pipeline semantics remain intentionally covered by the dedicated `SyncMinMax` leaf regression." - deferred_reason: "" - - - entity: SyncTrigRateVector - path: base/sync/rtl/SyncTrigRateVector.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/base/sync/test_SyncTrigRateVector.py - reference_assets: [] - notes: "Validated vectorized trigger-rate wrapper with a generated flattening shim, per-lane rate independence checks, and shared update-strobe pulse behavior on the stable common-clock path." - deferred_reason: "" - - - entity: LutFixedDelay - path: base/delay/rtl/LutFixedDelay.vhd - subsystem: base - tier: deferred_vendor_heavy - status: deferred_phase1 - priority: phase1_deferred - wrapper_path: "" - python_test: "" - reference_assets: [] - notes: "Single remaining non-dummy `base/` gap after the phase-1 practical rollout." - deferred_reason: "Depends on `SinglePortRamPrimitive`, so the current implementation path still drags vendor-specific infrastructure back into the open-source simulation flow." - - - entity: AxiStreamFifoV2 - path: axi/axi-stream/rtl/AxiStreamFifoV2.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: pilot - wrapper_path: axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd - python_test: tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py - reference_assets: - - tests/test_AxiStreamFifoV2IpIntegrator.py - notes: "Generic-heavy AXI-Stream pilot. Reused the IP integrator wrapper and migrated the Python regression into the shared package layout. Current validated sweep covers width-conversion cases plus one VALID_THOLD=0 configuration." - deferred_reason: "" - - - entity: AxiStreamPipeline - path: axi/axi-stream/rtl/AxiStreamPipeline.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd - python_test: tests/axi/axi_stream/test_AxiStreamPipeline.py - reference_assets: - - tests/test_AxiStreamPipelineTb.py - notes: "Validated AXI-Stream helper with a thin flat-port wrapper. The curated sweep covers zero-stage pass-through, staged pipeline ordering and sideband forwarding, backpressure stability, and synchronous/asynchronous reset handling. Staged cases are checked against the wrapper-visible latency of `PIPE_STAGES_G + 2` clocks plus bounded reset flush behavior." - deferred_reason: "" - - - entity: AxiStreamMux - path: axi/axi-stream/rtl/AxiStreamMux.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd - python_test: tests/axi/axi_stream/test_AxiStreamMux.py - reference_assets: - - axi/axi-stream/tb/AxiStreamMuxTb.vhd - - axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd - notes: "Validated AXI-Stream mux coverage with a thin two-input wrapper. The curated sweep covers indexed arbitration with explicit priority plus `disableSel`, routed `TDEST`/`TID` remap under backpressure, and staged asynchronous active-low reset recovery in passthrough mode. Interleave and explicit rearbitrate branches remain intentionally open for later work." - deferred_reason: "" - - - entity: AxiStreamDeMux - path: axi/axi-stream/rtl/AxiStreamDeMux.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd - python_test: tests/axi/axi_stream/test_AxiStreamDeMux.py - reference_assets: - - axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd - - tests/test_AxiStreamDemuxMuxTb.py - notes: "Validated AXI-Stream demux coverage with a thin one-input/two-output wrapper. The curated sweep covers indexed routing, exact-match routed decode under output backpressure, and dynamic-route table behavior including unmatched-destination drop and staged asynchronous active-low reset flush. Wildcard-route patterns and larger fanout counts remain intentionally open for later work." - deferred_reason: "" - - - entity: AxiLiteCrossbar - path: axi/axi-lite/rtl/AxiLiteCrossbar.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-lite/tb/AxiLiteCrossbarTb.vhd - python_test: tests/axi/axi_lite/test_AxiLiteCrossbar.py - reference_assets: - - axi/axi-lite/tb/AxiLiteCrossbarTb.vhd - notes: "Validated AXI-Lite crossbar coverage through the existing cocotb-facing harness topology. The regression checks routed read/write correctness across the local and cascaded regions, decode-miss `DECERR` responses, and concurrent traffic without region cross-coupling." - deferred_reason: "" - - - entity: AxiLiteAsync - path: axi/axi-lite/rtl/AxiLiteAsync.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-lite/ip_integrator/AxiLiteAsyncIpIntegrator.vhd - python_test: tests/axi/axi_lite/test_AxiLiteAsync.py - reference_assets: - - axi/axi-lite/tb/AxiLiteAsyncTb.vhd - notes: "Validated AXI-Lite async-wrapper coverage with a purpose-built IP-integrator adapter. The current passing subset is intentionally narrow: common-clock pass-through plus restart/recovery on the stable wrapper path. The asynchronous reset-crossing branches remain open for later work because they were not simulator-stable enough for this initial batch." - deferred_reason: "" - - - entity: AxiStreamResize - path: axi/axi-stream/rtl/AxiStreamResize.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-stream/ip_integrator/AxiStreamResizeIpIntegrator.vhd - python_test: tests/axi/axi_stream/test_AxiStreamResize.py - reference_assets: - - axi/axi-stream/tb/AxiStreamResizeTb.vhd - notes: "Validated AXI-Stream resize coverage with a thin flat-port adapter. The curated sweep covers equal-width pass-through, 2-byte to 4-byte upsize, and 4-byte to 2-byte downsize with sideband alignment checks plus staged reset flush in the resized cases." - deferred_reason: "" - - - entity: AxiLiteMaster - path: axi/axi-lite/rtl/AxiLiteMaster.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-lite/ip_integrator/AxiLiteMasterIpIntegrator.vhd - python_test: tests/axi/axi_lite/test_AxiLiteMaster.py - reference_assets: [] - notes: "Validated AXI-Lite master coverage with a thin request/ack-to-flat-port adapter and a cocotb slave model. The first bench covers write/read request sequencing, staggered AXI ready/valid handshakes, propagated `SLVERR` responses, and reset return to idle." - deferred_reason: "" - - - entity: AxiLiteToDrp - path: axi/bridge/rtl/AxiLiteToDrp.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/bridge/ip_integrator/AxiLiteToDrpIpIntegrator.vhd - python_test: tests/axi/bridge/test_AxiLiteToDrp.py - reference_assets: [] - notes: "Validated AXI-Lite-to-DRP bridge coverage with a thin flat-port wrapper. The current passing subset is intentionally narrow: common-clock non-arbitrated write/read mapping plus timeout-driven `SLVERR` and `drpUsrRst` recovery. The async arbitration branch remains open for later work." - deferred_reason: "" - - - entity: AxiDualPortRam - path: axi/axi-lite/rtl/AxiDualPortRam.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd - python_test: tests/axi/axi_lite/test_AxiDualPortRam.py - reference_assets: - - axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd - notes: "Validated AXI dual-port RAM coverage through the existing wrapper. The curated sweep covers AXI round-trips, system-port visibility of AXI writes, byte-masked system writes, and AXI write-disable `SLVERR` behavior when wrapper error responses are enabled." - deferred_reason: "" diff --git a/docs/_meta/rtl_regression_plan.md b/docs/_meta/rtl_regression_plan.md deleted file mode 100644 index 109e162eaa..0000000000 --- a/docs/_meta/rtl_regression_plan.md +++ /dev/null @@ -1,147 +0,0 @@ -# SURF RTL Regression Plan - -## Objective -- Build a repo-wide regression system for synthesizable SURF RTL. -- Standardize on a single executable test framework so new work stays consistent. -- Make progress resumable across many context windows without re-discovery. - -## Chosen Methodology -- Python-only executable test logic. -- Primary stack: `pytest + cocotb + GHDL + ruckus`. -- Local Python commands should use the repo virtualenv interpreter (`./.venv/bin/python`) unless the virtualenv has already been explicitly activated in that shell. -- VHDL is allowed only for thin wrappers, shims, or required simulation models. -- Existing VHDL testbenches are reference material, not execution constraints. -- New Python regression code should use tutorial-style comments by default. -- New Python cocotb test files should start with the standard SURF/SLAC header block, not an ad hoc local header. -- Every Python regression should also carry a short module-specific `Test methodology` block immediately under the SLAC header comment. -- The header methodology block should use four wrapped bullets: `Sweep`, `Stimulus`, `Checks`, and `Timing`. -- The methodology bullets must describe the actual curated parameter sweep, the actual driven input sequence, the expected outputs or state changes, and the timing/latency/pulse/backpressure behavior being checked for that specific module. -- Do not use generic placeholder methodology prose; the header should tell a reader what this specific bench is proving. -- Keep methodology comment lines at a normal source width so the block is readable in the editor instead of turning into single-line paragraphs. -- Assume the reader is not already comfortable with cocotb. -- Comment the purpose of each major step in the test flow, including clock startup, reset sequencing, trigger waits, stimulus phases, and result checks. -- Treat the header methodology block and the in-body tutorial comments as separate requirements; one does not replace the other. -- Shared helpers may stay somewhat denser, but module-level tests should still explain how the Python coroutine behavior maps onto DUT behavior. -- When a DUT generic assumes truly common clocks, drive those clocks from one shared cocotb coroutine rather than starting two same-period clocks independently. -- For Python cocotb files, the minimum first-draft structure is: - - standard SURF/SLAC file header, - - module-specific `Test methodology` block, - - tutorial-style comments in the executable body. -- Checked-in cocotb-facing VHDL wrappers should follow the in-tree SURF style too: add the standard SLAC/SURF banner at the top and include brief section comments for the major adapter regions. -- For `*IpIntegrator.vhd` wrappers, the minimum expected sectioning is usually: - - bus shim section, - - DUT instantiation section, - - output/status flattening section when present. -- Do not leave permanent checked-in wrappers as uncommented bare port maps even if the logic is thin; future sessions should be able to scan the file and identify the adapter shape immediately. -- For any VHDL file you create or edit, run the `vsg` linter with the same configuration CI uses (`./.venv/bin/vsg -c vsg-linter.yml ...`) before considering the work done. -- When `vsg` reports fixable issues, use `--fix`/autofix first, then rerun the same CI-configured lint command to confirm the file is clean. - -## Scope -- Whole repo target. -- Phase 1 focuses on simulator-friendly modules. -- Vendor-heavy modules are deferred in phase 1 unless they become practical under the open-source flow. - -## Coverage Model -- `functional_python` - - Module has a Python-authored cocotb regression. -- `smoke_python` - - Module has compile/elaborate coverage only. -- `wrapper_required` - - Module needs a retained or added VHDL wrapper to expose a cocotb-friendly interface. -- `deferred_vendor_heavy` - - Module is intentionally excluded from phase 1 executable regression. - -## Package Coverage Policy -- VHDL packages are not treated as standalone executable regression targets. -- Type/constant packages are covered transitively through the modules that compile and use them. -- Behavioral package functions and procedures should be covered through DUTs that exercise them whenever practical. -- If an important package function or procedure is not well reached transitively, add a minimal VHDL wrapper and test that wrapper from Python. -- Package-helper wrappers should be tracked separately from the main synthesizable-module inventory when they are introduced. - -## Generic And Configuration Policy -- Generic-heavy modules are Python-first by default. -- Build curated configuration matrices in Python. -- Do not use naive full Cartesian products for broad generic spaces. -- Compute expected behavior dynamically in Python from the active generics. -- If simulator limitations make direct generic overrides awkward, prefer checked-in subsystem-local VHDL wrappers over ad hoc test-local copies. -- Keep checked-in wrappers thin and declarative: expose cycle-friendly or cocotb-friendly generics, map them onto the real DUT generics, and keep them beside the subsystem RTL they adapt. -- For integration wrappers, test the wrapper-specific behavior rather than replaying the full underlying leaf matrix through the wrapper. -- If only a simulator-stable subset of a wrapper is practical in phase 1, keep that subset intentionally narrow and document the unvalidated branches explicitly in the handoff/progress docs. - -## CI And Runtime Policy -- Tier-first split. -- Separate `smoke` and `functional` regression tiers. -- Shard by subsystem only if runtime requires it. -- Keep room for PR-vs-nightly expansion later if runtime and coverage needs justify it. -- Treat simulator process cleanup as part of every verification step, not as optional housekeeping. -- After any command that launches `pytest`, cocotb, GHDL, or another simulation runner, check for stale child processes and kill any leftovers before moving on to the next step. -- When cleanup is needed, prefer an explicit process sweep first (for example with `ps -Ao pid,ppid,stat,time,command`) so only the stale run trees are terminated. - -## Reuse Policy -- Legacy VHDL testbenches are reference material only. -- Rewrite executable test logic in Python when migrating a module into the new regression system. -- Keep VHDL wrappers only when they make Python stimulus materially cleaner. -- Do not preserve old benches purely for historical reasons. -- Before writing new cocotb transaction code, search the nearest subsystem `tests/` package for an existing `*_test_utils.py` or equivalent shared helper module and reuse it when possible. -- Prefer extending an existing helper with one more narrowly useful utility over cloning handshake loops, packet builders, frame receivers, or register-access boilerplate into each new test file. -- For AXI-Lite work, look for existing read/write helpers, setup helpers, and protocol-master wrappers first; do not hand-code repeated register transactions if the subsystem already has a stable helper path. -- For AXI Stream work, look for existing frame/beat helpers, contiguous-send helpers, receive helpers, keep-mask helpers, and handshake monitors before writing custom ready/valid loops. -- For SSI work, prefer the existing SSI helper layer for flat endpoint setup, beat modeling, frame send/receive, no-output checks, and `EOFE`/`SOF`-aware assertions instead of rebuilding SSI transaction plumbing in each bench. -- When a wrapper is needed only to adapt simulator-hostile generics, check it into the nearest subsystem-local `wrappers/` or `ip_integrator/` folder instead of hiding it under `tests/` or a generic `hdl/` bucket. -- For SURF AXI/AxiLite record ports, prefer the existing IP-integrator shim layers (`SlaveAxiStreamIpIntegrator`, `MasterAxiStreamIpIntegrator`, `SlaveAxiLiteIpIntegrator`, `MasterAxiLiteIpIntegrator`) instead of hand-writing record-to-flat unpacking in each test wrapper. -- If a DUT has extra nonstandard side signals, compose those on top of the standard AXI shim pair rather than replacing the standard flattening pattern. -- For wrapper-style protocol benches, prefer thin subsystem wrappers plus cocotb protocol masters/RAM models, and add accepted-handshake monitoring whenever timing-visible protocol behavior is part of the contract being proven. -- More generally, if a VHDL shim layer is needed to make a module practical to drive from cocotb, place that file in the nearest real subsystem `wrappers/` or `ip_integrator/` folder beside related adapter layers. -- Do not place cocotb-facing shim/adaptor VHDL under `tests/` or generic `hdl/` buckets when it is serving the same integration role as the existing `*IpIntegrator.vhd` files. -- When a wrapper is checked in under `wrappers/` or `ip_integrator/`, treat it like production repo HDL for readability purposes: keep the standard file banner and add concise section comments instead of relying on file naming alone. -- Treat checked-in Python cocotb tests the same way: use the normal repo header/comment style in the first draft instead of leaving cleanup for later. - -## Rollout Planning Policy -- Use a checked-in RTL instantiation graph to guide bottom-up rollout decisions. -- Prefer testing high-reuse leaf primitives directly before spending effort on higher-level assemblies that mostly repackage them. -- Use the graph to reduce repeated behavioral testing across adjacent hierarchy levels, not as a substitute for engineering judgment about externally visible behavior. -- Keep the graph and queue artifacts for provenance and optional analysis, but do not use them as the active day-to-day source of truth for task selection. -- The active planning driver is now manual user-directed area selection, with `docs/_meta/rtl_regression_progress.md` and `docs/_meta/rtl_regression_handoff.md` tracking what is done, what is intentionally narrow, and what remains open. -- Do not hand-maintain queue order in this plan. If the graph or queue is regenerated for analysis, treat it as secondary context unless the user explicitly switches back to queue-driven planning. - -## Historical Queue Artifacts -The phase-1 simulator-friendly queue remains available as a generated bottom-up artifact, but it is now historical context rather than the active workflow. - -Retained artifacts: -- `docs/_meta/rtl_phase1_queue.md` -- `docs/_meta/rtl_phase1_queue.json` -- `docs/_meta/rtl_phase1_queue_overrides.json` - -If they are regenerated: -1. Use `./.venv/bin/python scripts/build_rtl_instantiation_graph.py`. -2. Treat the resulting graph and queue as reference material only. -3. Keep the real done/open frontier in `docs/_meta/rtl_regression_progress.md` and `docs/_meta/rtl_regression_handoff.md`. - -## Phase Breakdown -### Phase 1 -- Create the regression inventory and artifact scaffolding. -- Generate and maintain a repo-wide RTL instantiation graph to guide bottom-up prioritization. -- Establish shared Python regression helpers. -- Add smoke coverage for simulator-friendly modules. -- Add functional Python tests for the highest-value pilot modules and reusable blocks. -- Define the migration pattern for wrappers and generic-heavy modules. -- Standardize the subsystem-local checked-in wrapper pattern for real- or vector-generic leaves that need cycle-native test knobs under GHDL. - -### Phase 2 -- Deepen randomized and adversarial coverage. -- Expand curated configuration sweeps for generic-heavy modules. -- Add stronger reusable scoreboards and protocol-specific helpers. -- Revisit deferred vendor-heavy modules after phase 1 baseline stability. - -## Acceptance Criteria For Phase 1 -- The repo has a checked-in inventory and handoff system. -- New windows can recover project state by reading the handoff artifacts only. -- The Python-only regression direction is documented and stable. -- The progress and handoff artifacts stay aligned with the actual validated branch frontier instead of lagging behind completed subsystem waves. -- The smoke/functional tier split is established in the plan and progress tracking. - -## Open Questions And Deferred Decisions -- Whether PR-vs-nightly split is needed immediately or only after runtime data. -- Exact criteria for moving a vendor-heavy module out of `deferred_vendor_heavy`. -- Which user-directed subsystem slice should be taken next after the current documented frontier. -- Whether a separate tracked list of high-risk behavioral package helpers is needed once the module inventory stabilizes. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md deleted file mode 100644 index b5ed66ea17..0000000000 --- a/docs/_meta/rtl_regression_progress.md +++ /dev/null @@ -1,318 +0,0 @@ -# SURF RTL Regression Progress - -## Summary -- Current phase: Phase-1 implementation active -- Current subsystem: manual user-directed rollout tracking -- Current focus module: keep the RoCEv2 boundary aligned to `ethernet/RoCEv2/rtl`: the current validated subset is the pure-VHDL quartet (`EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator`), while the remaining five RTL entities need real mixed-language simulation because they instantiate `blue-*` modules underneath. -- Last updated: 2026-04-20 - -## Current Frontier Snapshot -- Active planning rule: take the next work item from the user's manual direction, not from `docs/_meta/rtl_phase1_queue.{md,json}`. -- Manual planning note: - - The axi-first pass is complete through the previously remaining final 11 `axi/` modules. - - The current `verification-2` branch already includes the merged `pre-release` state through PR #1392, so the validated `protocols/ssi`, `protocols/pgp`, and current Ethernet waves (`EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the current pure-VHDL RoCEv2 quartet) are all part of the present branch snapshot. - - The checked-in queue and override artifacts are now retained only as historical provenance and optional graph output; they are no longer the source of truth for choosing the next area. - - Keep the done/open frontier in this progress file and in `docs/_meta/rtl_regression_handoff.md` aligned to the actual tree even if the queue artifacts are stale. - - Treat stale simulator cleanup as mandatory after every launched verification command: after any `pytest`, cocotb, GHDL, or similar simulation step, sweep for leftover child processes and kill them before starting the next task. -- Known expected-open tests on this branch: - - No simulator-friendly expected-open leaf tests remain in the currently covered `ethernet/IpV4Engine` slice, and the recent `EthMacCore` / `UdpEngine` thin-area follow-up is also checked in on this branch. - - The current `EthMac*Xlgmii` import/export leaves are still placeholder no-op RTL, so the checked-in benches document that inert contract rather than claiming functional XLGMII datapath coverage. - - The remaining Ethernet work is in the larger untouched families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core`, plus the five still-open RoCEv2 RTL entities that depend on generated submodules: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`. -- RoCEv2 RTL target matrix: - - Covered now under the current GHDL-only flow: `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, `RoceConfigurator` - - Still required, but need real `blue-*` dependencies under a mixed-language simulator: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, `RoceEngineWrapper` -- Most recent reusable bench pattern: - - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. - - For `ethernet`, keep using the checked-in wrappers under `ethernet/*/wrappers/` plus the shared helper layers in `tests/ethernet/EthMacCore/ethmac_test_utils.py`, `tests/ethernet/RawEthFramer/raw_eth_test_utils.py`, `tests/ethernet/UdpEngine/udp_test_utils.py`, and `tests/ethernet/IpV4Engine/ipv4_test_utils.py`. The practical first-pass shape is flat EMAC/app beat wrappers with explicit sideband bits, curated functional slices instead of exhaustive generic sweeps, and dedicated pair/integration wrappers only where an old VHDL bench contributes a topology worth preserving. - -## Status -| Subsystem | Inventory | Smoke | Functional | Notes | -| --- | --- | --- | --- | --- | -| Cross-cutting infrastructure | started | not started | started | Shared helper structure now lives in `tests/common/regression_utils.py`; pytest now defaults to `xdist` parallel execution via `pytest.ini`; the checked-in graph/queue artifacts under `docs/_meta/` are retained for provenance, while `rtl_regression_progress.md` and `rtl_regression_handoff.md` are the active planning inputs | -| `base` | started | not started | started | Validated low-level regressions now exist for `FifoAsync`, `FifoSync`, `FifoOutputPipeline`, `FifoWrFsm`, `FifoRdFsm`, `Fifo`, `FifoCascade`, `FifoMux`, `Synchronizer`, `SynchronizerVector`, `SynchronizerEdge`, `SynchronizerOneShot`, `SynchronizerFifo`, `SynchronizerOneShotCnt`, `SynchronizerOneShotVector`, `SynchronizerOneShotCntVector`, `SyncStatusVector`, `SyncTrigPeriod`, `SyncMinMax`, `SyncClockFreq`, `SyncTrigRate`, `SyncTrigRateVector`, `RstSync`, `RstPipeline`, `RstPipelineVector`, `PwrUpRst`, `Arbiter`, `ClockDivider`, `Debouncer`, `Gearbox`, `AsyncGearbox`, `Heartbeat`, `Mux`, `OneShot`, `RegisterVector`, `WatchDogRst`, `Scrambler`, `MasterRamIpIntegrator`, `SlaveRamIpIntegrator`, `SimpleDualPortRam`, `DualPortRam`, `TrueDualPortRam`, `LutRam`, `SlvDelay`, `SlvFixedDelay`, `SlvDelayRam`, `SlvDelayFifo`, `Crc32Parallel`, `Crc32`, and `CRC32Rtl` under subsystem-organized `tests/base/` packages. Remaining uncovered `base/` entities are vendor-heavy, dummy-backed, or `LutFixedDelay`, which is deferred because it depends on `SinglePortRamPrimitive`. | -| `dsp` | started | not started | started | The planned `dsp/generic/fixed` leaf batch is now validated under `tests/dsp/generic/`: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. Shared DSP helpers now live in `tests/dsp/generic/dsp_test_utils.py`, and the legacy VHDL benches under `dsp/generic/tb/` were treated as behavioral reference material rather than as execution constraints. | -| `axi` | started | not started | started | The axi-first pass is now complete for the simulator-friendly queue. The final locally validated batch adds `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`, with a combined `11 passed` validation run on 2026-03-27. Added checked-in subsystem wrappers under `axi/axi4/ip_integrator/`, `axi/axi-lite/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/` for those benches. `AxiStreamFifoV2` now has an expanded `10 passed` wrapper regression under `tests/axi/axi_stream/` covering async and sync width conversion, metadata truncation, `VALID_THOLD` frame-ready and burst-release modes, dynamic pause-threshold behavior, `CASCADE_SIZE=2`, and the `S_HAS_TREADY=0` pause-only source-side path. `AxiResize` now passes its equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` wrapper regression on this branch after the read-hold RTL fix. `AxiLiteAsync`, `AxiLiteToDrp`, and `AxiRateGen` still keep intentionally narrow common-clock subsets while the more timing-sensitive async AXI-Lite crossing branches remain open. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` still keep intentionally narrow first-pass subsets. `AxiStreamDmaV2Read` is now validated with a two-case wrapper regression covering both aligned and short terminal-beat reads after fixing bounded byte-count conversion in `AxiPkg` and terminal-mask generation in `AxiStreamDmaV2Read`. | -| `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. | -| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers both the original leaf slice and the deeper assembly benches for `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`, plus direct `EthMacRxBypass` / `EthMacTxBypass` leaf benches and import/export sweeps that now explicitly include the current placeholder `XLGMII` contract. `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, including the successful multi-beat `RawEthFramerTx` unicast-forwarding path after lookup resolution. `tests/ethernet/UdpEngine/` covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, with the top/wrapper benches now widened across client/server routing paths. `tests/ethernet/IpV4Engine/` covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, and the top/leaf benches now also include protocol-TX and deeper ICMP reject/recovery coverage. `tests/ethernet/RoCEv2/` currently covers the pure-VHDL RTL entities `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator` through checked-in wrappers under `ethernet/RoCEv2/wrappers/`. The remaining RoCEv2 RTL entities that still need cocotb benches are `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`, and those should use the real generated `blue-*` dependencies rather than local stand-ins. The explicit Ethernet caveats are now the larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core`, the mixed-language RoCEv2 bench gap listed above, plus the still-placeholder `EthMac*Xlgmii` RTL. | -| `devices` | not started | not started | not started | Many vendor-heavy cases | -| `xilinx` | not started | not started | not started | Many vendor-heavy cases | - -## Completed Decisions -- Use Python-only executable test logic. -- Use `pytest + cocotb + GHDL + ruckus` as the primary stack. -- Keep VHDL only for wrappers, shims, and required simulation models. -- Comment new Python regression code at a tutorial level so readers who are new to cocotb can follow the flow in-place. -- Whole repo is the long-term target. -- Phase 1 focuses on simulator-friendly modules. -- Vendor-heavy modules are deferred in phase 1. -- Generic-heavy modules are Python-first. -- Use curated configuration matrices instead of full Cartesian products. -- Keep a tier-first CI model: `smoke` and `functional`. -- Rewrite legacy VHDL TB logic in Python rather than preserving it by default. -- Keep wrappers only when they make Python interaction cleaner. -- Run the `vsg` linter with CI's `vsg-linter.yml` settings on any created or edited VHDL files, and use autofix before doing manual cleanup when possible. -- Treat VHDL packages as transitively covered unless a behavioral function/procedure needs a dedicated wrapper. -- Treat `docs/_meta/rtl_regression_progress.md` and `docs/_meta/rtl_regression_handoff.md` as the living planning inputs, and treat the checked-in queue artifacts as archival unless the user explicitly asks to resume queue-driven planning. - -## Completed Work Items -- Surveyed repo structure and existing verification flow. -- Reviewed existing Python regressions and representative VHDL testbenches. -- Merged the current `pre-release` branch into `verification-2`, bringing the already-landed `protocols/ssi` and `protocols/pgp` regression waves into the same branch line as the earlier `ethernet/EthMacCore` slice. -- Re-added `dsp/` to the generated phase-1 queue scope so DSP work is tracked by the same bottom-up planner as the other simulator-friendly subsystems. -- Implemented `tests/dsp/generic/test_DspAddSub.py`. -- Validated `tests/dsp/generic/test_DspAddSub.py` locally with `./.venv/bin/python -m pytest -n 0 -q tests/dsp/generic/test_DspAddSub.py`. -- Added shared DSP helpers in `tests/dsp/generic/dsp_test_utils.py` for signed packing/truncation, rolling reference models, cocotb clock-settle timing, and generated FIR wrappers. -- Extended `tests/common/regression_utils.py` so generated-wrapper benches can use short explicit sim-build keys instead of overloading generic/extra-env strings into fragile build paths. -- Implemented `tests/dsp/generic/test_FirFilterTap.py`, `tests/dsp/generic/test_DspPreSubMult.py`, `tests/dsp/generic/test_DspSquareDiffMult.py`, `tests/dsp/generic/test_BoxcarIntegrator.py`, `tests/dsp/generic/test_BoxcarFilter.py`, `tests/dsp/generic/test_FirFilterSingleChannel.py`, and `tests/dsp/generic/test_FirFilterMultiChannel.py`. -- Fixed DSP RTL issues exposed by the new benches in `dsp/generic/fixed/FirFilterTap.vhd`, `dsp/generic/fixed/BoxcarIntegrator.vhd`, and `dsp/generic/fixed/FirFilterSingleChannel.vhd`. -- Validated the full planned DSP leaf batch locally with `./.venv/bin/python -m pytest -n 0 -q tests/dsp/generic` (`15 passed`). -- Compared `cocotb + pytest`, `VUnit`, and `OSVVM` for SURF. -- Chose Python-only executable regression logic. -- Defined the context-handoff artifact set. -- Created the checked-in handoff artifacts under `docs/_meta/`. -- Created the initial regression inventory scaffold in `docs/_meta/rtl_regression_inventory.yaml`. -- Selected and documented the first pilot modules: `FifoAsync`, `AxiStreamFifoV2`, and `AxiLiteAsync`. -- Added `scripts/setup_regression_env.sh` to bootstrap the local regression environment. -- Added `.vscode/tasks.json` with setup, import, and regression tasks. -- Installed local `ghdl` via Homebrew. -- Created `.venv`, installed Python regression dependencies, linked `~/ruckus`, and completed `make MODULES="$PWD" import`. -- Added shared regression helpers in `tests/regression_utils.py`. -- Implemented the first Python pilot regression in `tests/base/fifo/test_FifoAsync.py`. -- Validated `tests/base/fifo/test_FifoAsync.py` locally with `./.venv/bin/python -m pytest -v tests/base/fifo/test_FifoAsync.py`. -- Reorganized new regressions into subsystem packages under `tests/` and moved shared helpers to `tests/common/`. -- Added `tests/README.md` to document the regression layout policy. -- Added the shared Ethernet MAC helper layer in `tests/ethernet/EthMacCore/ethmac_test_utils.py`, including packet builders, checksum helpers, MAC-config byte-order handling, flat EMAC beat helpers, and Ethernet minimum-frame padding support for the import/export loopback benches. -- Added checked-in cocotb-facing wrappers under `ethernet/EthMacCore/wrappers/` for the first `EthMacCore` wave, including loopback wrappers for import/export and top-level tests plus flat wrappers for the checksum, pause, filter, and shift leaves. -- Implemented and validated the first `ethernet/EthMacCore` functional wave under `tests/ethernet/EthMacCore/`: `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`. -- Expanded the first `EthMacCore` wave beyond the initial happy paths: `EthMacTop` now covers filter/backpressure/checksum/pause interactions, `EthMacRxImport` and `EthMacTxExport` now cover both GMII and XGMII plus link-not-ready recovery behavior, the RX/TX checksum benches now include negative and partial-repair cases, `EthMacRxFilter` now covers multicast/broadcast/filter-disable/multi-beat-drop behavior, the RX/TX shift benches now cover runtime shift changes and control-bit propagation, and `EthCrc32Parallel` now sweeps all byte widths `1..16`. -- Ran a quick HDL coverage spike against the local Homebrew `ghdl` build and confirmed it does not expose `--coverage` or a `coverage` subcommand. -- Migrated `AxiStreamFifoV2` into `tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py` and validated the current 10-case sweep locally. -- Expanded `tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py` into a broader 10-case `AxiStreamFifoV2` regression covering thresholded release modes, metadata truncation, multi-stage cascade buffering, and the `S_HAS_TREADY=0` pause-only path, and validated it locally with `10 passed`. -- Revalidated `tests/axi/axi4/test_AxiResize.py` after merging `verification` into `fix-axi-resize`; the equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` cases now all pass locally on this branch, so the stale upsize `xfail` was removed. -- Expanded `FifoAsync` into a curated 12-case matrix and validated it locally under parallel pytest execution. -- Added `pytest.ini` to default to `-n auto --dist=worksteal`, and aligned CI to rely on that default xdist configuration. -- Implemented `tests/base/fifo/test_FifoSync.py` and validated its 11-case matrix locally under parallel pytest execution. -- Added `scripts/build_rtl_instantiation_graph.py` and generated checked-in graph artifacts in `docs/_meta/rtl_instantiation_graph.{md,json}`. -- Implemented `tests/base/sync/test_Synchronizer.py` and validated its 6-case matrix locally under parallel pytest execution. -- Implemented `tests/base/sync/test_SynchronizerVector.py` and validated its 6-case matrix locally under parallel pytest execution. -- Implemented `tests/base/general/test_RstPipeline.py` and validated its 4-case matrix locally under parallel pytest execution. -- Implemented `tests/base/ram/test_SimpleDualPortRam.py` and validated its 5-case matrix locally under parallel pytest execution. -- Implemented `tests/base/fifo/test_FifoOutputPipeline.py` and validated its 5-case matrix locally under parallel pytest execution. -- Implemented `tests/base/fifo/test_FifoWrFsm.py` and validated its 4-case matrix locally under parallel pytest execution. -- Extended `tests/common/regression_utils.py` so regressions can add test-local VHDL wrapper sources when simulator limitations make a thin shim cleaner than direct generic overrides. -- Implemented `tests/base/crc/test_Crc32Parallel.py`, `tests/base/crc/test_Crc32.py`, and `tests/base/crc/test_CRC32Rtl.py` and validated their combined 9-case CRC batch locally under parallel pytest execution. -- Implemented `tests/base/sync/test_RstSync.py`, `tests/base/sync/test_SynchronizerEdge.py`, and `tests/base/sync/test_SynchronizerOneShot.py` and validated their combined 11-case sync/reset batch locally under parallel pytest execution. -- Implemented `tests/base/general/test_PwrUpRst.py` and validated its 3-case matrix locally under parallel pytest execution. -- Implemented `tests/base/ram/test_TrueDualPortRam.py` and `tests/base/ram/test_LutRam.py` and validated their combined 9-case RAM batch locally under parallel pytest execution. -- Implemented `tests/base/fifo/test_FifoRdFsm.py` and validated its 4-case matrix locally under parallel pytest execution. -- Validated the full 10-module follow-on subset in one run with `./.venv/bin/python -m pytest -v tests/base/crc/test_Crc32Parallel.py tests/base/crc/test_Crc32.py tests/base/crc/test_CRC32Rtl.py tests/base/sync/test_RstSync.py tests/base/general/test_PwrUpRst.py tests/base/sync/test_SynchronizerEdge.py tests/base/sync/test_SynchronizerOneShot.py tests/base/ram/test_TrueDualPortRam.py tests/base/ram/test_LutRam.py tests/base/fifo/test_FifoRdFsm.py` (`38 passed`). -- Implemented `tests/base/general/test_Arbiter.py`, `tests/base/general/test_ClockDivider.py`, `tests/base/general/test_Debouncer.py`, `tests/base/general/test_Gearbox.py`, `tests/base/general/test_Heartbeat.py`, `tests/base/general/test_Mux.py`, `tests/base/general/test_OneShot.py`, `tests/base/general/test_RegisterVector.py`, `tests/base/general/test_RstPipelineVector.py`, `tests/base/general/test_Scrambler.py`, `tests/base/general/test_WatchDogRst.py`, `tests/base/delay/test_SlvDelay.py`, `tests/base/delay/test_SlvFixedDelay.py`, `tests/base/sync/test_SynchronizerFifo.py`, and `tests/base/sync/test_SynchronizerOneShotCnt.py`. -- Implemented `tests/axi/axi_stream/test_AxiStreamScatterGather.py`, `tests/axi/axi4/test_AxiMemTester.py`, `tests/axi/dma/test_AxiStreamDmaV2Desc.py`, `tests/axi/dma/test_AxiStreamDmaV2Fifo.py`, `tests/axi/axi4/test_AxiReadPathFifo.py`, `tests/axi/axi4/test_AxiWritePathFifo.py`, `tests/axi/dma/test_AxiStreamDmaV2.py`, `tests/axi/axi_stream/test_AxiStreamBatchingFifo.py`, `tests/axi/axi_stream/test_AxiStreamMon.py`, and `tests/axi/axi_stream/test_AxiStreamRingBuffer.py`, plus the supporting `*IpIntegrator.vhd` wrappers needed for the new AXI4/AXIS/DMA benches. -- Validated the full 15-module follow-on subset in one run with `./.venv/bin/python -m pytest -n 0 -q tests/base/general/test_Arbiter.py tests/base/general/test_ClockDivider.py tests/base/general/test_Debouncer.py tests/base/general/test_Gearbox.py tests/base/general/test_Heartbeat.py tests/base/general/test_Mux.py tests/base/general/test_OneShot.py tests/base/general/test_RegisterVector.py tests/base/general/test_RstPipelineVector.py tests/base/general/test_Scrambler.py tests/base/general/test_WatchDogRst.py tests/base/delay/test_SlvDelay.py tests/base/delay/test_SlvFixedDelay.py tests/base/sync/test_SynchronizerFifo.py tests/base/sync/test_SynchronizerOneShotCnt.py` (`41 passed`). -- Added a shared generated-wrapper path in `tests/common/regression_utils.py` and migrated the `Heartbeat` and `Debouncer` regressions away from checked-in one-off VHDL wrappers. -- Revalidated the generated-wrapper migration locally with `./.venv/bin/python -m pytest -n 0 -q tests/base/general/test_Heartbeat.py tests/base/general/test_Debouncer.py` (`6 passed`) and then revalidated the full 15-module batch (`41 passed`). -- Implemented `tests/dsp/generic/test_DspComparator.py`, `tests/base/fifo/test_Fifo.py`, `tests/base/fifo/test_FifoCascade.py`, `tests/base/fifo/test_FifoMux.py`, `tests/base/general/test_AsyncGearbox.py`, `tests/base/sync/test_SynchronizerOneShotVector.py`, `tests/base/sync/test_SynchronizerOneShotCntVector.py`, `tests/base/sync/test_SyncStatusVector.py`, `tests/base/sync/test_SyncTrigPeriod.py`, and `tests/base/sync/test_SyncMinMax.py`. -- Validated the combined 10-module wrapper/integration batch with `./.venv/bin/python -m pytest -n 0 -q tests/dsp/generic/test_DspComparator.py tests/base/fifo/test_Fifo.py tests/base/fifo/test_FifoCascade.py tests/base/fifo/test_FifoMux.py tests/base/general/test_AsyncGearbox.py tests/base/sync/test_SynchronizerOneShotVector.py tests/base/sync/test_SynchronizerOneShotCntVector.py tests/base/sync/test_SyncStatusVector.py tests/base/sync/test_SyncTrigPeriod.py tests/base/sync/test_SyncMinMax.py` (`18 passed`). -- Implemented `tests/base/general/test_MasterRamIpIntegrator.py`, `tests/base/general/test_SlaveRamIpIntegrator.py`, `tests/base/ram/test_DualPortRam.py`, `tests/base/delay/test_SlvDelayRam.py`, `tests/base/delay/test_SlvDelayFifo.py`, `tests/base/sync/test_SyncClockFreq.py`, `tests/base/sync/test_SyncTrigRate.py`, and `tests/base/sync/test_SyncTrigRateVector.py`. -- Validated the combined remaining non-vendor, non-dummy `base/` batch with `./.venv/bin/python -m pytest -n 0 -q tests/base/general/test_MasterRamIpIntegrator.py tests/base/general/test_SlaveRamIpIntegrator.py tests/base/ram/test_DualPortRam.py tests/base/delay/test_SlvDelayRam.py tests/base/delay/test_SlvDelayFifo.py tests/base/sync/test_SyncClockFreq.py tests/base/sync/test_SyncTrigRate.py tests/base/sync/test_SyncTrigRateVector.py` (`15 passed`). -- Implemented `tests/axi/axi_stream/test_AxiStreamPipeline.py` with a thin flat-port adapter at `axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd`, and validated its curated 3-case sweep locally. -- Implemented `tests/axi/axi_lite/test_AxiLiteCrossbar.py` with a cocotb-facing crossbar wrapper and validated its routed-region, decode-error, and concurrent-traffic coverage locally. -- Validated the first post-`base/` `axi/` pair with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamPipeline.py tests/axi/axi_lite/test_AxiLiteCrossbar.py` (`4 passed`). -- Implemented `tests/axi/axi_stream/test_AxiStreamMux.py` with a thin two-input adapter at `axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd`, and validated its curated indexed-priority, routed-remap, and asynchronous reset/recovery sweep locally (`3 passed`). -- Revalidated the small post-`base/` `axi/` follow-on set with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamPipeline.py tests/axi/axi_stream/test_AxiStreamMux.py tests/axi/axi_lite/test_AxiLiteCrossbar.py` (`7 passed`). -- Implemented `tests/axi/axi_stream/test_AxiStreamDeMux.py` with a thin two-output adapter at `axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd`, and validated its curated indexed-routing, routed-backpressure, and dynamic-route/drop/reset sweep locally (`3 passed`). -- Revalidated the current small `axi/` follow-on subset with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamPipeline.py tests/axi/axi_stream/test_AxiStreamMux.py tests/axi/axi_stream/test_AxiStreamDeMux.py tests/axi/axi_lite/test_AxiLiteCrossbar.py` (`10 passed`). -- Replaced the hand-curated flat phase-1 list with a generated path-qualified queue emitted by `scripts/build_rtl_instantiation_graph.py` into `docs/_meta/rtl_phase1_queue.{md,json}`, backed by explicit filters and manual-order inputs in `docs/_meta/rtl_phase1_queue_overrides.json`. -- Implemented `tests/axi/axi_lite/test_AxiLiteRegs.py`, `tests/axi/axi_lite/test_AxiLiteRespTimer.py`, `tests/axi/axi_lite/test_AxiLiteSlave.py`, `tests/axi/axi_lite/test_AxiLiteWriteFilter.py`, `tests/axi/axi_lite/test_AxiVersion.py`, `tests/axi/axi_stream/test_AxiStreamCombiner.py`, `tests/axi/axi_stream/test_AxiStreamFlush.py`, `tests/axi/axi_stream/test_AxiStreamGearboxPack.py`, `tests/axi/axi_stream/test_AxiStreamGearboxUnpack.py`, and `tests/axi/axi_stream/test_AxiStreamSplitter.py` with thin subsystem-local adapters under `axi/axi-lite/ip_integrator/` and `axi/axi-stream/ip_integrator/`. -- Validated the generated-queue 10-module AXI batch with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_lite/test_AxiLiteRegs.py tests/axi/axi_lite/test_AxiLiteRespTimer.py tests/axi/axi_lite/test_AxiLiteSlave.py tests/axi/axi_lite/test_AxiLiteWriteFilter.py tests/axi/axi_lite/test_AxiVersion.py tests/axi/axi_stream/test_AxiStreamCombiner.py tests/axi/axi_stream/test_AxiStreamFlush.py tests/axi/axi_stream/test_AxiStreamGearboxPack.py tests/axi/axi_stream/test_AxiStreamGearboxUnpack.py tests/axi/axi_stream/test_AxiStreamSplitter.py` (`14 passed`). -- Implemented `tests/axi/axi4/test_AxiReadPathMux.py`, `tests/axi/axi4/test_AxiWritePathMux.py`, `tests/axi/axi4/test_AxiResize.py`, and `tests/axi/bridge/test_AxiToAxiLite.py` with thin subsystem-local adapters at `axi/axi4/ip_integrator/AxiReadPathMuxIpIntegrator.vhd`, `axi/axi4/ip_integrator/AxiWritePathMuxIpIntegrator.vhd`, `axi/axi4/ip_integrator/AxiResizeIpIntegrator.vhd`, and `axi/bridge/ip_integrator/AxiToAxiLiteIpIntegrator.vhd`. -- Validated the stable AXI4/bridge follow-on subset with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiReadPathMux.py tests/axi/axi4/test_AxiWritePathMux.py tests/axi/bridge/test_AxiToAxiLite.py` (`3 passed`). `tests/axi/axi4/test_AxiResize.py` is present on this branch with the restored upsize case, but that case is expected to fail until the separate `AxiResize` RTL-fix branch is merged. -- Implemented `tests/axi/axi_stream/test_AxiStreamTrailerRemove.py`, `tests/axi/axi4/test_AxiRam.py`, `tests/axi/bridge/test_AxiLiteToIpBus.py`, `tests/axi/bridge/test_IpBusToAxiLite.py`, `tests/axi/dma/test_AxiStreamDmaV2Read.py`, `tests/axi/axi_stream/test_AxiStreamGearbox.py`, `tests/axi/axi_stream/test_AxiStreamTap.py`, `tests/axi/dma/test_AxiStreamDmaRead.py`, `tests/axi/dma/test_AxiStreamDmaV2Write.py`, and `tests/axi/axi_stream/test_AxiStreamTimer.py` with subsystem-local adapters under `axi/axi-stream/ip_integrator/`, `axi/bridge/ip_integrator/`, and `axi/dma/ip_integrator/`. -- Validated the stable 9-module subset of that generated-queue window with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiRam.py tests/axi/bridge/test_AxiLiteToIpBus.py tests/axi/bridge/test_IpBusToAxiLite.py tests/axi/dma/test_AxiStreamDmaRead.py tests/axi/dma/test_AxiStreamDmaV2Write.py tests/axi/axi_stream/test_AxiStreamGearbox.py tests/axi/axi_stream/test_AxiStreamTap.py tests/axi/axi_stream/test_AxiStreamTimer.py tests/axi/axi_stream/test_AxiStreamTrailerRemove.py` (`9 passed`). `tests/axi/dma/test_AxiStreamDmaV2Read.py` is present on this branch as a minimal one-beat aligned reproducer, but it still fails immediately inside `AxiStreamDmaV2Read` at `31 ns` with `std_logic_arith.vhdl:2014:9: ARG is too large in CONV_INTEGER`, so `AxiStreamDmaV2Read` remains open rather than counted as validated. -- Implemented `tests/axi/axi4/test_AxiRateGen.py` with a thin subsystem-local adapter at `axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd`. -- Validated `AxiRateGen` locally with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiRateGen.py` (`1 passed`) and revalidated the nearby AXI4 subset with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiReadPathMux.py tests/axi/axi4/test_AxiWritePathMux.py tests/axi/axi4/test_AxiRam.py tests/axi/axi4/test_AxiRateGen.py` (`4 passed`). -- Refactored `protocols/line-codes` into a clean three-layer cocotb layout backed by a shared helper in `tests/protocols/line_codes/line_code_test_utils.py`: direct package benches via checked-in `Code*PkgWrapper.vhd` adapters, direct `Encoder*`/`Decoder*` entity benches, and small end-to-end integration smokes that reuse the legacy `protocols/line-codes/tb/LineCode*Tb.vhd` shells instead of duplicated wrapper HDL. -- Added permanent checked-in package adapters at `protocols/line-codes/wrappers/Code8b10bPkgWrapper.vhd`, `protocols/line-codes/wrappers/Code10b12bPkgWrapper.vhd`, and `protocols/line-codes/wrappers/Code12b14bPkgWrapper.vhd`, then removed the duplicated `protocols/line-codes/wrappers/LineCode*Wrapper.vhd` files and their matching `test_LineCode*Wrapper.py` benches. -- The direct-entity benches now cover clock-enable gating, flow-control hold behavior, malformed decoder inputs, dual-byte 8b10b lane coverage, and 12b14b debug-disparity handoff through `test_Encoder*.py` and `test_Decoder*.py`. -- The current line-code validation command is `./.venv/bin/python -m pytest -n 0 -q tests/protocols/line_codes`, and it passes locally with `23 passed`. -- The new package-surface coverage exposed a real `Code12b14bPkg` invalid-K disparity bug; `protocols/line-codes/rtl/Code12b14bPkg.vhd` now leaves `dispOut` unchanged on illegal K requests instead of tripping a GHDL bound-check failure. - -## Current In-Progress Item -- Decide the next non-`pgp3` `protocols/pgp` target now that the shared VC FIFOs and the remaining non-vendor `pgp4/core/rtl` leaves are covered. -- Keep `pgp2b`, `pgp2fc`, `pgp3`, and `pgp4` organized as separate family subpackages with checked-in wrappers rather than falling back to generated shim HDL, but treat `pgp3` as deferred for now. -- Preserve the recent `pgp4` lesson: when the simulation wrapper only exposes stable lock/config surfaces, write the bench around those explicit contracts instead of claiming recovered payload coverage. -- Phase-2 follow-on for `protocols/pgp/pgp4`: broaden the current single payload-bitflip negative test into a small corruption-location matrix that separately covers SOF/header metadata corruption, EOF/tail corruption (including transmitted CRC-field corruption), and 66b header-side framing errors instead of treating all of those cases as equivalent to payload CRC failure. - -## Next 3 Concrete Tasks -- Decide whether the next family pass is deeper directed coverage for the existing `pgp2b`/`pgp2fc` RX and alignment benches or a move into another non-deferred protocol area. -- Keep the `protocols/pgp/pgp4` low-speed leaves on their dedicated lock/config guardrail benches unless a later wrapper explicitly proves the serialized payload path end to end. -- Reuse the new `tests/protocols/pgp/shared/` helper and wrappers if later shared PGP utilities need direct cocotb coverage. - -## Blockers And Risks -- Runtime may grow quickly once configuration-heavy modules are added without careful tiering. -- Wrapper policy must stay narrow or VHDL cruft will accumulate again. -- HDL source coverage is not immediately available with the current local `ghdl` LLVM build; it needs a separate tooling decision if we want it later. - -## Findings Worth Preserving -- For a quick resume, read this file’s `Current Frontier Snapshot`, `Current In-Progress Item`, `Next 3 Concrete Tasks`, and `Findings Worth Preserving` sections before digging through the full log. -- Existing Python regressions are generally the best reusable verification assets. -- Existing VHDL TBs contain useful behavioral intent but are inconsistent as a scalable execution framework. -- Generic-heavy modules strongly favor Python-authored tests. -- Broad repo coverage will require tiering and likely later sharding. -- The initial inventory file should remain small and explicit rather than auto-generated until the schema stabilizes. -- `AxiStreamFifoV2` already has a useful wrapper-plus-Python pattern, and the same shim-first approach works well for later AXI wrappers when the DUT-specific extra signals are kept thin. -- AXI Stream leaves with partially driven sideband fields can upset `cocotbext.axi` sinks under GHDL when those fields stay `U`; for first-pass benches, prefer either wrappers that drive those sidebands deterministically or hand-monitored payload checks when the sidebands are not part of the behavior under test. -- Real-generic overrides are still awkward under the local open-source stack; if a module only needs a small non-default real-generic operating point, prefer baking the stable value into the thin subsystem wrapper over fighting simulator-specific override syntax. -- Some wrapper benches need to stay intentionally narrow on this branch to avoid conflating simulator limitations with RTL failures. In this batch that applies to `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux`. -- The local machine needs a reproducible one-command bootstrap path before test implementation work can move efficiently. -- The bootstrap path is now working locally with `~/ruckus` linked into the repo. -- Bare `python` should not be assumed to exist on `PATH` in this repo's shell environment; use `./.venv/bin/python` for local pytest and helper-script invocations unless the virtualenv is already activated. -- The first shared-helper-based pilot is working; start simple and grow coverage incrementally rather than front-loading every edge case. -- New regressions need to live in subsystem packages from the start; do not add more flat `tests/test_*.py` files. -- The current Homebrew `ghdl` install is sufficient for cocotb regressions but not for a simple built-in HDL coverage flow. -- The existing `AxiLiteAsyncTb.vhd` is useful as intent/reference, but it is not an appropriate long-term wrapper because it embeds clocks, memories, and transaction logic; `AxiLiteAsyncIpIntegrator.vhd` is now the cleaner cocotb-facing adapter. -- Future Python regression code should follow the user's preferred two-layer comment style: keep a module-specific `Test methodology` header block under the SLAC banner and also explain major coroutine steps, waits, stimulus phases, and checks in-place for readers who are not already comfortable with cocotb. -- Future Python regression code should also keep the standard SURF/SLAC file header itself; do not treat the methodology block as a substitute for the normal repo banner. -- The methodology block should use wrapped `Sweep`, `Stimulus`, `Checks`, and `Timing` bullets and describe the real bench behavior, not generic filler text. -- The same “write it readable on the first pass” rule applies to permanent cocotb-facing VHDL wrappers: checked-in `*IpIntegrator.vhd` files should carry the standard SURF banner and short section comments for shim setup, DUT hookup, and flattening/status wiring. -- `FifoAsync` needed a curated matrix rather than a naive Cartesian sweep: standard FIFO mode, FWFT mode, and pipelined FWFT do not share identical read/full semantics. -- VHDL packages should not become top-level test targets by default; only high-value behavioral helpers warrant dedicated wrapper tests. -- `FifoSync` benefits from the same curated-matrix approach as `FifoAsync`, but its threshold checks needed event-driven flag handling because `prog_full`/`prog_empty` timing did not line up with fixed write-count assumptions. -- The instantiation graph is useful for rollout planning because it exposes both high-reuse leaves and likely duplicated coverage paths; it should guide prioritization, not dictate exact test depth. -- The generated path-qualified queue in `rtl_phase1_queue.{md,json}` is now the operational phase-1 order. Use the graph for provenance and regeneration, and use `rtl_phase1_queue_overrides.json` for justified defer/reorder exceptions instead of hand-maintaining queue text in the plan doc. -- The first graph pass surfaced `Synchronizer`, `SynchronizerVector`, `SimpleDualPortRam`, `FifoOutputPipeline`, `FifoRdFsm`, and `FifoWrFsm` as concrete `base/` bottom-up candidates after the FIFO pilots. -- Duplicate entity names are common in SURF due to dummy/vendor variants, so graph consumers need to read path context rather than rely on entity names alone. -- A generated path-qualified queue is practical under the current graph parser: the first pass yields `411` phase-1 modules with `0` unresolved duplicate-name phase-1 edges under the checked-in filter set. -- Keep `docs/_meta/rtl_phase1_queue_overrides.json` small and explicit. It should record only real phase-1 scope decisions or blocker-driven order exceptions, not day-to-day queue churn. -- Direct cocotb tests for simple SURF leaf modules still need to account for `TPD_G` when sampling outputs after clock or reset events; sampling exactly at the nominal edge can create false negatives. -- Simple RAM tests benefit from a small startup warm-up and conservative read sampling so direct and registered output configurations share one stable helper. -- For leaf modules with combinational outputs derived from current request inputs, pulse-based tests should drop the request before sampling post-edge state or they may observe the next pending transaction instead of the one just accepted. -- The local GHDL flow rejects direct command-line overrides of a 32-bit `slv` generic in `Crc32`; when a parameterized leaf still needs expanded coverage, prefer a thin test-only wrapper over simulator-specific literal hacks. -- For repeated real-generic shim cases, generated test-local wrappers are a better default than checking in one VHDL file per module; they keep the workaround explicit without growing permanent HDL debris. -- `COMMON_CLK_G` style benches need truly shared edges, not just same-period clocks. A single cocotb coroutine that drives both clocks in lockstep is the safer default for those wrappers. -- Integration-wrapper tests should stay narrow and wrapper-specific. `Fifo` validated both inferred sync/async wrapper branches, `FifoCascade` validated public stage-vector plumbing plus a curated output smoke, and `FifoMux` is currently validated only on the stable split-to-narrow path while the packed-write branch remains deferred. -- `SyncClockFreq` is stable under the generated-wrapper approach, but the common-clock path quantizes one count above the abstract frequency target under GHDL, so the regression checks a bounded expected range instead of an over-precise exact integer. -- `SyncTrigRate` is now covered as a wrapper/integration bench: it validates aligned update publication, denser-window rate growth, reset-path liveness, and update-strobe pulse behavior. Exact min/max pipeline arithmetic remains covered by the dedicated `SyncMinMax` leaf regression rather than being re-proven through the wrapper. -- `LutFixedDelay` is the lone non-dummy `base/` entity still deferred in phase 1 because it depends on `SinglePortRamPrimitive`, which is currently only available through the vendor/dummy-backed path. -- `AxiStreamPipeline` is stable with a thin flat-port wrapper. The zero-stage case should be checked as true pass-through, while staged cases should be checked against the wrapper-visible latency of `PIPE_STAGES_G + 2` clocks and a bounded reset flush rather than an over-precise internal-stage assumption. -- `AxiStreamMux` is stable with a thin two-input adapter, but its `disableSel` handling composes with the separate priority-masking step in a non-obvious order: a disabled higher-priority source can still suppress lower-priority requesters. Disable-focused benches should either use equal priorities or mask the lower-priority source instead. -- `AxiStreamMux` interleave and explicit rearbitrate branches remain intentionally out of scope for the first wrapper bench; the validated subset is indexed arbitration plus `disableSel`, routed `TDEST`/`TID` remap under backpressure, and staged reset/recovery in passthrough mode. -- `AxiStreamDeMux` is stable with a thin one-input/two-output adapter. The first bench covers indexed decode, exact-match routed decode under output backpressure, and dynamic-route table behavior including unmatched-destination drop and staged reset flush. Broader wildcard-route patterns and larger fanout counts remain intentionally unproven in this first wrapper bench. -- `AxiLiteCrossbar` is practical under the current open-source flow with a thin cocotb-facing wrapper around the cascaded topology. The useful regression surface is routed-region correctness, decode-miss `DECERR` handling, and concurrent traffic through the cascaded topology, not a giant generic sweep. -- SURF already has reusable AXI record-flattening shims. New AXI Stream and AXI-Lite wrappers should prefer the existing IP-integrator shim layers over hand-written record packing, and only custom-wire the DUT-specific extra side signals on top. -- More generally, any VHDL shim layer added only to make a module fit cleanly into cocotb should live in the nearest real subsystem `ip_integrator/` tree, not under `tests/` and not under generic `hdl/` directories. -- If that shim layer is checked in instead of generated locally, treat it like normal repo HDL rather than disposable glue: add the standard header and enough section comments that the adapter structure is obvious during a later resume. -- Apply the same “first-draft readability” rule to checked-in cocotb tests: standard header first, methodology block second, tutorial comments in the body. -- `AxiReadPathMux` and `AxiWritePathMux` are more stable with tiny source-side pin drivers than with `cocotbext.axi` masters because the muxes rewrite IDs internally; the downstream shared-port checks can still use the library RAM models. -- `protocols/line-codes` is cleaner when split into three layers: direct package benches for exhaustive legal-space and explicit disparity-seed checks, direct `Encoder*`/`Decoder*` entity benches for clock/reset/flow-control behavior, and one small family-level integration smoke that proves the encoder-to-decoder chain still matches the legacy shell. -- For the line-code families, keep the shared Python harness generic and keep legality decisions local to each module bench. `8b10b` varies by byte-lane width, `10b12b` uses the curated `x & 28` K-symbol subset from the legacy bench, and `12b14b` also preserves its historical mixed training pattern plus explicit malformed-decode and illegal-K checks. -- For line-code package coverage, prefer checked-in subsystem wrappers only where the package surface truly needs explicit disparity seeding or direct encode/decode visibility. `Code8b10bPkg`, `Code10b12bPkg`, and `Code12b14bPkg` all follow that pattern now; the family integration layer should reuse existing `tb/LineCode*Tb.vhd` shells rather than cloning them into new wrapper HDL. -- The new package-surface tests are strong enough to expose latent package bugs. In this batch they caught an illegal-K path defect in `Code12b14bPkg` where the package could drive an out-of-range disparity sum; that path is now fixed and should stay covered. -- The current `Code12b14b` cocotb coverage preserves the legacy explicit disparity seeds plus the training/transition sequences, but it still does not carry forward the old VHDL bench's stateful run-length monitor as a passing assertion. Treat that run-length monitor as a known follow-up gap rather than silently assuming it is covered. -- `AxiToAxiLite` is practical with a thin bridge-local adapter, but mixed-width checks need to stay single-beat on the AXI side when the downstream response path is fundamentally AXI-Lite-like. -- `AxiResize` still has an expected verification-branch gap: the restored `32-bit -> 64-bit` upsize case in `tests/axi/axi4/test_AxiResize.py` should keep failing here until the separate RTL-fix branch is merged. -- `AxiRateGen` is practical with the existing AXI4 and AXI-Lite IP-integrator shim pair plus a cocotb AXI RAM model, and the stable first-pass subset is the `COMMON_CLK_G=true` path with timer spacing, zero-fill writes, and generated-read completion rather than the asynchronous AXI-Lite crossing branches. -- For protocol-generator or wrapper-style benches, pair end-state checks with explicit accepted-handshake monitoring whenever the externally visible contract includes timing, burst shape, sideband propagation, or arbitration order. -- The SSI helper layer is now broad enough to justify reuse across the whole subsystem: `FlatSsiEndpoint`, `SsiBeat`, `recv_frame`, contiguous frame driving, optional `TID` handling, and no-output checks cover the current flattened SSI wrappers without each bench re-implementing handshake plumbing. -- `SsiInsertSof` is practical with a small SSI-local wrapper that exposes semantic SOF/EOFE controls instead of treating raw `TUSER` layout as the cocotb API. The currently validated subset keeps `COMMON_CLK_G=true` and FIFO-backed paths enabled; raw `TUSER_MASK_G` bit-level expectations are still a follow-up item if we want to pin down SSI user-bit indexing more aggressively. -- `SsiIbFrameFilter` is practical with the same semantic-wrapper approach, but the wrapper should use native SSI `TUSER_FIRST_LAST_C` encoding rather than a generic normal-user layout so cocotb can drive `SOF`/`EOFE` directly and the DUT sees the expected first/last byte markers. -- `SsiObFrameFilter` is practical with the same native-SSI wrapper contract. The checked-in bench now covers good-frame pass-through, missing-SOF drop, repeated-`SOF` termination, mid-frame `TDEST` termination, the cached-last-user `VALID_THOLD_G=0` `EOFE` drop path with exported drop-flag pulses, and one pipelined `PIPE_STAGES_G=2` pass-through case without relying on fixed latency assumptions. -- `SsiFifo` is practical with the same flat SSI wrapper pattern, but contiguous multi-beat checks need handshake-based observation rather than late frame collection. The earlier apparent middle-beat loss on a 3-beat `SsiFifoWrapper` probe turned out to be a receive-helper artifact; once the helper was corrected to capture accepted handshakes, both `SsiIbFrameFilter` and `SsiFifo` preserved the full frame and the checked-in `SsiFifo` regression could safely add real 3-beat pass-through assertions on the default, frame-ready, and thresholded paths plus a repeated-`SOF` termination check on the composite FIFO wrapper. -- The first reusable SSI Python helper can now absorb whole-frame receive and metadata-extension commonality, but it should still stop short of becoming a golden protocol model. Module-specific policy such as header injection, command decode rules, or filter-drop counters should remain in each bench. -- `AxiStreamDmaV2Read` is stable with a thin IP-integrator wrapper once the read-path byte-count conversions stay bounded to the burst-size window. The checked-in bench proves both aligned and short terminal-beat reads; because the wrapper exports only an 8-bit `TUSER`, the observable contract is first-user propagation rather than separate first/last byte tagging. -- The `axi/dma/rtl/v2/` benches are now intentionally split by behavior instead of repeatedly re-proving the same path through the top-level DMA stack: `AxiStreamDmaV2` and `AxiStreamDmaV2Desc` stay focused on descriptor-manager register/control surfaces, `AxiStreamDmaV2Read` owns aligned and short terminal-beat readout, `AxiStreamDmaV2Write` owns descriptor-return integrity plus burst splitting, `AxiStreamDmaV2WriteMux` owns arbitration ordering, and `AxiStreamDmaV2Fifo` owns the integrated FIFO register/count/pause-threshold surface. -- For checked-in VHDL changes, use the repo virtualenv's `vsg` with `vsg-linter.yml` so local lint matches CI, and prefer `--fix` before manual spacing/alignment cleanup. -- The current `EthMacCore` wave has a few wrapper-visible behavior details worth preserving in the docs instead of rediscovering later: the XGMII import/export loopback retains a frame presented during `phyReady=0` and drains it after link recovery with Ethernet minimum-size padding applied, while the GMII path drops it; `EthMacRxCsum` reliably asserts `IPERR` on a bad IPv4 header checksum but the checked-in wrapper contract does not require `EOFE` on that case; and the RX/TX shift benches need a small idle-plus-settle gap before changing runtime shift controls because the underlying `AxiStreamShift` samples those controls from its IDLE state. -- Verification hygiene now includes process cleanup: if a `pytest`/cocotb/GHDL step leaves stale run trees behind, kill those leftovers immediately before starting another compile or simulation command. - -## Log -- 2026-03-20: Agreed on Python-only executable regression logic and wrapper-only VHDL retention. -- 2026-03-20: Agreed on whole-repo scope with simulator-friendly phase 1 and vendor-heavy deferral. -- 2026-03-20: Agreed to add stable handoff artifacts under `docs/_meta/` before deeper implementation work. -- 2026-03-20: Added `docs/_meta/rtl_regression_inventory.yaml` and seeded it with the first three pilot modules. -- 2026-03-20: Added local bootstrap helpers in `scripts/setup_regression_env.sh` and `.vscode/tasks.json`. -- 2026-03-20: Installed local toolchain and completed the first successful `make MODULES="$PWD" import`. -- 2026-03-20: Added `tests/regression_utils.py` and landed the first passing pilot regression for `FifoAsync`. -- 2026-03-20: Moved new regression infrastructure to `tests/common/`, relocated `FifoAsync` to `tests/base/fifo/`, and documented the subsystem-organized test layout. -- 2026-03-20: Checked local HDL coverage viability; the installed LLVM-backed `ghdl` rejects `--coverage`, so HDL coverage is deferred pending a different simulator/backend decision. -- 2026-03-20: Migrated `AxiStreamFifoV2` into `tests/axi/axi_stream/` and validated the full current 10-case sweep in 146s. -- 2026-04-02: Expanded `tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py` to cover `VALID_THOLD` release behavior, burst gating, dynamic pause control, `CASCADE_SIZE=2`, and `S_HAS_TREADY=0`, and revalidated it locally with `10 passed`. -- 2026-04-02: Merged `verification` into `fix-axi-resize`, reran `tests/axi/axi4/test_AxiResize.py`, and confirmed the previous `32-bit -> 64-bit` upsize `xfail` now passes on this branch; removed the stale `xfail`. -- 2026-04-02: Expanded the `axi/dma/rtl/v2/` regression split without broad overlap. `tests/axi/dma/test_AxiStreamDmaV2Write.py` now covers both single-frame and multi-burst writes, `tests/axi/dma/test_AxiStreamDmaV2WriteMux.py` now covers descriptor-first, simultaneous-launch, and data-first arbitration cases, and `tests/axi/dma/test_AxiStreamDmaV2Fifo.py` now covers the integrated FIFO register map plus dynamic pause-threshold behavior against the live write-buffer count. The combined validation run across `tests/axi/dma/test_AxiStreamDmaV2.py`, `tests/axi/dma/test_AxiStreamDmaV2Desc.py`, `tests/axi/dma/test_AxiStreamDmaV2Read.py`, `tests/axi/dma/test_AxiStreamDmaV2Write.py`, `tests/axi/dma/test_AxiStreamDmaV2WriteMux.py`, and `tests/axi/dma/test_AxiStreamDmaV2Fifo.py` passes locally with `9 passed`. -- 2026-04-02: Started the `protocols/line-codes` refactor by moving the family benches onto a shared helper in `tests/protocols/line_codes/line_code_test_utils.py` and by adding checked-in package-surface wrappers for `Code8b10bPkg`, `Code10b12bPkg`, and `Code12b14bPkg`. -- 2026-04-02: Compared the cocotb line-code coverage against the legacy VHDL benches under `protocols/line-codes/tb/`, preserved the legacy disparity-seed and training-pattern intent in the `Code*Pkg` Python benches, and noted the old `Code12b14bTb.vhd` run-length monitor as the only still-unported legacy assertion. -- 2026-04-02: Completed the clean-slate line-code redesign: deleted the duplicated `LineCode*Wrapper.vhd` and `test_LineCode*Wrapper.py` layer, added direct `test_Encoder*.py` and `test_Decoder*.py` benches against the real RTL entities, reused `protocols/line-codes/tb/LineCode*Tb.vhd` as the thin integration shells, fixed an illegal-K disparity bug in `protocols/line-codes/rtl/Code12b14bPkg.vhd`, and validated the full `tests/protocols/line_codes` directory locally with `23 passed`. -- 2026-04-03: Added `dsp/` back into `scripts/build_rtl_instantiation_graph.py` so the regenerated `docs/_meta/rtl_instantiation_graph.{md,json}` and `docs/_meta/rtl_phase1_queue.{md,json}` artifacts now track `dsp/generic/fixed` alongside the other phase-1 subsystems. -- 2026-04-03: Implemented `tests/dsp/generic/test_DspAddSub.py` as the first post-resume DSP leaf bench, replacing the old free-running `dsp/generic/tb/DspAddSubTb.vhd` stimulus with explicit signed add/sub arithmetic checks plus backpressure-hold and reset-clearing assertions. The module-local validation run passes locally with `2 passed`. -- 2026-04-03: Completed the planned `dsp/generic/fixed` cocotb leaf batch. Added new benches for `FirFilterTap`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`; centralized shared DSP timing/model/wrapper helpers in `tests/dsp/generic/dsp_test_utils.py`; added explicit sim-build-key support for generated wrappers in `tests/common/regression_utils.py`; fixed RTL issues in `FirFilterTap`, `BoxcarIntegrator`, and `FirFilterSingleChannel`; and validated the full directory with `15 passed`. -- 2026-04-06: Started the manual `protocols/ssi` rollout with `SsiInsertSof`. Added the checked-in wrapper `protocols/ssi/wrappers/SsiInsertSofWrapper.vhd`, implemented `tests/protocols/ssi/test_SsiInsertSof.py`, validated the three-case FIFO-backed sweep locally with `3 passed`, and linted the wrapper cleanly with `vsg -c vsg-linter.yml -f`. -- 2026-04-06: Validated the narrow next SSI step with `SsiIbFrameFilter`. Added the checked-in native-SSI wrapper `protocols/ssi/wrappers/SsiIbFrameFilterWrapper.vhd`, implemented `tests/protocols/ssi/test_SsiIbFrameFilter.py`, validated the first-pass same-clock sweep locally with `1 passed`, linted the wrapper cleanly with `vsg --fix -c vsg-linter.yml -f`, and then consolidated shared flat SSI driver/sink timing into `tests/protocols/ssi/ssi_test_utils.py` so `test_SsiInsertSof.py` and `test_SsiIbFrameFilter.py` use the same basic endpoint helper layer. -- 2026-04-06: Added the next outbound SSI step with `SsiObFrameFilter`. Added the checked-in native-SSI wrapper `protocols/ssi/wrappers/SsiObFrameFilterWrapper.vhd`, implemented `tests/protocols/ssi/test_SsiObFrameFilter.py`, validated the narrowed default-mode regression locally with `1 passed`, revalidated the current SSI trio with `5 passed`, and linted the wrapper cleanly with `vsg --fix -c vsg-linter.yml -f`. The stable checked-in subset covers good-frame pass-through plus repeated-`SOF` termination with `PIPE_STAGES_G=0`; the cached-last-user `EOFE` branch for `VALID_THOLD_G=0` remains a follow-up item. -- 2026-04-06: Added the next composite SSI step with `SsiFifo`. Added the checked-in wrapper `protocols/ssi/wrappers/SsiFifoWrapper.vhd`, implemented `tests/protocols/ssi/test_SsiFifo.py`, validated the narrowed smoke regression locally with `1 passed`, and linted the wrapper cleanly with `vsg --fix -c vsg-linter.yml -f`. The stable checked-in subset keeps one physical clock and currently proves valid single-beat pass-through plus missing-SOF drop; multi-beat good-frame integrity, buffered occupancy behavior, and the sync-output gearbox branch remain follow-up items. -- 2026-04-06: Completed the remaining manual `protocols/ssi` leaf batch. Added checked-in wrappers `protocols/ssi/wrappers/SsiCmdMasterPulserWrapper.vhd`, `protocols/ssi/wrappers/SsiCmdMasterWrapper.vhd`, `protocols/ssi/wrappers/SsiFrameLimiterWrapper.vhd`, `protocols/ssi/wrappers/SsiIncrementingTxWrapper.vhd`, `protocols/ssi/wrappers/SsiAxiLiteMasterWrapper.vhd`, and `protocols/ssi/wrappers/SsiDbgTapWrapper.vhd`; added `tests/protocols/ssi/test_SsiCmdMasterPulser.py`, `tests/protocols/ssi/test_SsiCmdMaster.py`, `tests/protocols/ssi/test_SsiFrameLimiter.py`, `tests/protocols/ssi/test_SsiIncrementingTx.py`, `tests/protocols/ssi/test_SsiAxiLiteMaster.py`, and `tests/protocols/ssi/test_SsiDbgTap.py`; extended `tests/protocols/ssi/ssi_test_utils.py` with optional `TID` handling plus shared frame-receive helpers; validated the new six-test batch locally with `6 passed`; and kept wrapper lint clean under `vsg --fix -c vsg-linter.yml -f` plus a clean follow-up lint pass. The current scope is intentionally uneven: `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiIncrementingTx`, and `SsiAxiLiteMaster` have functional first-pass checks, `SsiFrameLimiter` is currently a narrowed single-beat/missing-SOF subset, and `SsiDbgTap` is traffic smoke only because the RTL exposes no externally visible state. -- 2026-04-07: Tightened the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` so flat SSI sources wait for a real handshake edge and shared frame receivers capture accepted handshakes instead of inferring contiguous traffic from post-send snapshots. Revalidated the existing SSI slice locally with `19 passed`. A focused follow-up on `SsiIbFrameFilter` and `SsiFifo` showed the earlier apparent 3-beat middle-word loss was a bench observation bug rather than an RTL bug, after which the checked-in `SsiFifo` regression added a real contiguous 3-beat pass-through assertion and the `SsiAxiLiteMaster` / `SsiIncrementingTx` benches were updated to assert the full emitted frame shapes. -- 2026-04-07: Expanded `tests/protocols/ssi/test_SsiFifo.py` beyond the earlier single-beat subset. The checked-in FIFO bench now proves contiguous 3-beat frame preservation on the default, `VALID_THOLD_G=0`, and `VALID_THOLD_G=2` wrapper paths; exercises repeated-`SOF` malformed-frame handling across the buffered modes; and keeps the existing missing-`SOF` drop plus `SLAVE_READY_EN_G=false` overflow checks. The buffered malformed-frame result is mode-specific at the wrapper boundary: `VALID_THOLD_G=0` drops the malformed repeated-`SOF` frame outright, while `VALID_THOLD_G=2` emits the expected two-beat terminated `EOFE` frame. A follow-up backpressure pass also added explicit drain-side ready toggling on a good 5-beat frame, malformed termination under toggled ready, and thresholded release under intermittent drain stalls so SSI frame policy is now checked under nontrivial sink backpressure without duplicating the full `AxiStreamFifoV2` transport matrix. Revalidated the full touched SSI slice locally with `19 passed`. -- 2026-04-10: Landed the first manual `ethernet/EthMacCore` bench wave under `tests/ethernet/EthMacCore/`, added the required checked-in wrappers under `ethernet/EthMacCore/wrappers/`, and validated the baseline 12-module slice covering `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`. -- 2026-04-10: Expanded that same `EthMacCore` slice beyond the initial happy paths. The checked-in Ethernet MAC suite now covers `EthMacTop` filter/backpressure/checksum/pause interactions, GMII and XGMII import/export plus link-not-ready recovery behavior, checksum negative cases, filter multicast/broadcast/filter-disable/multi-beat-drop behavior, shift runtime-control and control-bit propagation edges, and full byte-width `1..16` logic-path coverage for `EthCrc32Parallel`. The full `tests/ethernet/EthMacCore` directory currently passes locally with `32 passed`. -- 2026-04-17: Expanded the `ethernet/EthMacCore` slice into the deeper assembly layer. The checked-in Ethernet MAC benches now also cover `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo` through the existing subsystem-local wrappers under `ethernet/EthMacCore/wrappers/`. -- 2026-04-17: Added the manual `ethernet/UdpEngine` wave under `tests/ethernet/UdpEngine/`. The checked-in helper layer now lives in `tests/ethernet/UdpEngine/udp_test_utils.py`, the new checked-in wrappers live under `ethernet/UdpEngine/wrappers/`, and the locally validated benches cover `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`. The current local validation command `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/UdpEngine/test_ArpIpTable.py tests/ethernet/UdpEngine/test_UdpEngineArp.py tests/ethernet/UdpEngine/test_UdpEngineDhcp.py tests/ethernet/UdpEngine/test_UdpEngineRx.py tests/ethernet/UdpEngine/test_UdpEngineTx.py tests/ethernet/UdpEngine/test_UdpEngine.py tests/ethernet/UdpEngine/test_UdpEngineWrapper.py` passes with `7 passed`. -- 2026-04-17: Added the manual `ethernet/IpV4Engine` wave under `tests/ethernet/IpV4Engine/`. The checked-in helper layer now lives in `tests/ethernet/IpV4Engine/ipv4_test_utils.py`, the checked-in wrappers live under `ethernet/IpV4Engine/wrappers/`, and the validated benches cover `ArpEngine`, `IcmpEngine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`. -- 2026-04-17: Added `ethernet/IpV4Engine/wrappers/IgmpV2EngineWrapper.vhd` plus `tests/ethernet/IpV4Engine/test_IgmpV2Engine.py`, extending the IPv4 helper layer with IGMP packet builders in `tests/ethernet/IpV4Engine/ipv4_test_utils.py`. The new leaf bench covers power-up membership reports, general-query re-arming, and suppression of a pending local report when a matching inbound membership report is observed, while documenting the two leaf-boundary stale-field quirks that `IpV4EngineTx` ignores. -- 2026-04-16: Merged the current `pre-release` branch into `verification-2`, so this branch line now contains the already-landed SSI and PGP waves from PR #1391 and PR #1392 in addition to the manual Ethernet slice. -- 2026-04-16: Refreshed the planning docs to move the active frontier from “continue Ethernet next” to “refresh the stale queue/override inputs, then resume from the real merged-branch frontier.” -- 2026-04-17: Switched the planning docs from queue-driven task selection to user-directed frontier tracking. The graph and queue artifacts remain checked in for provenance, but `rtl_regression_progress.md` and `rtl_regression_handoff.md` are now the active done/open source of truth. -- 2026-04-17: Expanded `tests/ethernet/RawEthFramer/test_RawEthFramerTx.py` to cover the successful multi-beat unicast forwarding path after lookup resolution. The new leaf test holds the source frame through the exported request phase, models the same nonzero lookup latency the integrated `RawEthFramer` wrapper inserts before `ack`, and validates the full MAC-side wire image alongside the existing request, broadcast-bypass, and zero-MAC drop checks. -- 2026-04-17: Completed the Ethernet thin-area follow-up across `EthMacCore`, `UdpEngine`, and `IpV4Engine`. Added checked-in wrappers `ethernet/EthMacCore/wrappers/EthMacRxBypassWrapper.vhd` and `ethernet/EthMacCore/wrappers/EthMacTxBypassWrapper.vhd`, added `tests/ethernet/EthMacCore/test_EthMacRxBypass.py` and `tests/ethernet/EthMacCore/test_EthMacTxBypass.py`, widened `test_EthMacRxImport.py` / `test_EthMacTxExport.py` to cover the current placeholder `XLGMII` contract, widened `tests/ethernet/UdpEngine/test_UdpEngine.py` and `tests/ethernet/UdpEngine/test_UdpEngineWrapper.py` across additional client/server routing paths, widened `tests/ethernet/IpV4Engine/test_IpV4Engine.py` with a top-level protocol-TX path, and deepened `tests/ethernet/IpV4Engine/test_IcmpEngine.py` with truncated-request rejection, EOFE preservation, and post-reject recovery checks. The combined local validation command `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/EthMacCore/test_EthMacRxImport.py tests/ethernet/EthMacCore/test_EthMacTxExport.py tests/ethernet/EthMacCore/test_EthMacRxBypass.py tests/ethernet/EthMacCore/test_EthMacTxBypass.py tests/ethernet/UdpEngine/test_UdpEngine.py tests/ethernet/UdpEngine/test_UdpEngineWrapper.py tests/ethernet/IpV4Engine/test_IpV4Engine.py tests/ethernet/IpV4Engine/test_IcmpEngine.py` passes locally with `14 passed`. -- 2026-03-20: Added an explicit project rule to comment new Python regression code where intent or runner behavior is not self-evident. -- 2026-03-20: Expanded `FifoAsync` to a validated 12-case parameter matrix and enabled default pytest xdist parallelization with `pytest.ini`. -- 2026-03-20: Added package-coverage policy: packages are covered transitively unless a behavioral helper warrants a dedicated wrapper test. -- 2026-03-20: Switched from pilot-only work to the bottom-up rollout and selected `FifoSync` as the next low-level target. -- 2026-03-20: Implemented and validated an 11-case `FifoSync` matrix under `tests/base/fifo/test_FifoSync.py`. -- 2026-03-20: Added and generated the first-pass RTL instantiation graph to guide bottom-up rollout decisions and reduce repeated test effort across the hierarchy. -- 2026-03-20: Implemented and validated a 6-case `Synchronizer` matrix under `tests/base/sync/test_Synchronizer.py` as the next graph-guided `base` leaf. -- 2026-03-20: Documented that local Python commands should use `./.venv/bin/python` unless the virtualenv is already activated, after a bare `python` invocation failed due to a missing shell shim. -- 2026-03-20: Implemented and validated the next five graph-guided `base` regressions: `SynchronizerVector`, `RstPipeline`, `SimpleDualPortRam`, `FifoOutputPipeline`, and `FifoWrFsm`. -- 2026-03-20: Updated the planning and handoff docs to preserve the user's tutorial-style cocotb comment preference for future regressions. -- 2026-03-20: Implemented and validated the next 10 graph-guided `base` regressions: `Crc32Parallel`, `Crc32`, `CRC32Rtl`, `RstSync`, `PwrUpRst`, `SynchronizerEdge`, `SynchronizerOneShot`, `TrueDualPortRam`, `LutRam`, and `FifoRdFsm`. -- 2026-03-20: Expanded `Crc32` coverage beyond the default IEEE polynomial to include Castagnoli and Koopman-style cases, using a thin test-only VHDL wrapper because local GHDL rejected direct runtime overrides of the 32-bit `CRC_POLY_G` vector generic. -- 2026-03-20: Implemented and validated the next 15 graph-guided `base` regressions: `Arbiter`, `ClockDivider`, `Debouncer`, `Gearbox`, `Heartbeat`, `Mux`, `OneShot`, `RegisterVector`, `RstPipelineVector`, `Scrambler`, `WatchDogRst`, `SlvDelay`, `SlvFixedDelay`, `SynchronizerFifo`, and `SynchronizerOneShotCnt` (`41 passed`). -- 2026-03-21: Replaced the checked-in `Heartbeat`/`Debouncer` wrapper files with a shared generated-wrapper helper in `tests/common/regression_utils.py` and revalidated both the targeted tests (`6 passed`) and the full 15-module batch (`41 passed`). -- 2026-03-21: Implemented and validated the next 10-module wrapper/integration batch: `DspComparator`, `Fifo`, `FifoCascade`, `FifoMux`, `AsyncGearbox`, `SynchronizerOneShotVector`, `SynchronizerOneShotCntVector`, `SyncStatusVector`, `SyncTrigPeriod`, and `SyncMinMax` (`18 passed`). -- 2026-03-21: Added `start_lockstep_clocks()` in `tests/common/regression_utils.py` for `COMMON_CLK_G` style benches and recorded that `FifoCascade`/`FifoMux` should keep intentionally narrow wrapper coverage under the current GHDL flow instead of forcing unstable branches. -- 2026-03-21: Implemented and validated the remaining non-vendor, non-dummy `base/` batch: `MasterRamIpIntegrator`, `SlaveRamIpIntegrator`, `DualPortRam`, `SlvDelayRam`, `SlvDelayFifo`, `SyncClockFreq`, `SyncTrigRate`, and `SyncTrigRateVector` (`15 passed`). `LutFixedDelay` remains deferred because it still depends on `SinglePortRamPrimitive`. -- 2026-03-21: Tightened the comment policy for Python regressions: header-level methodology comments and in-body tutorial comments are both required, the methodology block should use wrapped `Sweep`/`Stimulus`/`Checks`/`Timing` bullets, and the text should stay module-specific and editor-readable. -- 2026-03-21: Started the first post-`base/` simulator-friendly `axi/` follow-on with `AxiStreamPipeline` and `AxiLiteCrossbar` as the next migration targets, using the legacy flat Python benches only as intent/reference while keeping the new work under subsystem-packaged tests. -- 2026-03-21: Implemented and validated `AxiStreamPipeline` and `AxiLiteCrossbar` as the first post-`base/` `axi/` follow-on. `AxiStreamPipeline` uses a thin flat-port wrapper plus a curated pass-through/staged/reset sweep, and `AxiLiteCrossbar` uses a cocotb-facing wrapper for routed-region, decode-error, and concurrent-traffic checks (`4 passed` combined). -- 2026-03-21: Refactored the `AxiStreamPipeline` test adapter to reuse the existing `SlaveAxiStreamIpIntegrator`/`MasterAxiStreamIpIntegrator` shim pair for standard AXIS flattening, preserving only the pipeline-specific sideband wiring in the adapter (`3 passed` on the pipeline regression after the refactor). -- 2026-03-21: Moved and renamed the `AxiStreamPipeline` adapter to `axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd` so its path and name match the existing AXI IP-integrator adapter conventions and live with the rest of the AXI adapter layer. -- 2026-03-21: Tightened the planning rule for cocotb-facing shim placement: if a VHDL adapter is needed to fit a module into cocotb, place it in the nearest real subsystem `ip_integrator/` tree alongside the existing integration shims rather than under `tests/`. -- 2026-03-21: Collapsed the large instantiation-graph output into a reviewed flat phase-1 module build order in `rtl_regression_plan.md` so future windows can take the next queued module directly instead of re-analyzing the JSON graph before every step. -- 2026-03-21: Resumed the flat `axi/` queue at `AxiStreamMux` and chose a dedicated IP-integrator adapter over the existing combined DeMux/Mux harness so the new cocotb bench can stay mux-specific and exercise arbitration plus `TDEST`/`TID` remap behavior directly. -- 2026-03-21: Implemented and validated `AxiStreamMux` with `axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd` plus `tests/axi/axi_stream/test_AxiStreamMux.py`. The validated 3-case sweep covers indexed arbitration with explicit priority and `disableSel`, routed `TDEST`/`TID` remap under backpressure, and staged asynchronous active-low reset recovery (`3 passed`). -- 2026-03-21: Revalidated the current small `axi/` follow-on subset with `tests/axi/axi_stream/test_AxiStreamPipeline.py`, `tests/axi/axi_stream/test_AxiStreamMux.py`, and `tests/axi/axi_lite/test_AxiLiteCrossbar.py` in one run (`7 passed`). -- 2026-03-21: Started the next flat-queue `axi/` item, `AxiStreamDeMux`, and began evaluating whether a dedicated cocotb-facing adapter is cleaner than reusing the older combined DeMux/Mux harness for the first narrow wrapper bench. -- 2026-03-21: Implemented and validated `AxiStreamDeMux` with `axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd` plus `tests/axi/axi_stream/test_AxiStreamDeMux.py`. The validated 3-case sweep covers indexed routing, exact-match routed decode under output backpressure, and dynamic-route/drop/reset behavior (`3 passed`). -- 2026-03-21: Revalidated the current small `axi/` follow-on subset with `tests/axi/axi_stream/test_AxiStreamPipeline.py`, `tests/axi/axi_stream/test_AxiStreamMux.py`, `tests/axi/axi_stream/test_AxiStreamDeMux.py`, and `tests/axi/axi_lite/test_AxiLiteCrossbar.py` in one run (`10 passed`). -- 2026-03-21: Started scoping the next five flat-queue modules after `AxiStreamDeMux`: `AxiStreamResize`, `AxiLiteAsync`, `AxiLiteMaster`, `AxiLiteToDrp`, and `AxiDualPortRam`, beginning with a wrapper/reference-asset pass to separate straightforward benches from blocks that still need adapter cleanup. -- 2026-03-21: Implemented and validated the next five flat-queue modules: `AxiStreamResize`, `AxiLiteAsync`, `AxiLiteMaster`, `AxiLiteToDrp`, and `AxiDualPortRam`. The five-module batch passes with `10 passed`, and a broader AXI follow-on sanity run across pipeline, mux, demux, resize, crossbar, async, master, DRP bridge, and dual-port RAM passes with `20 passed`. `AxiLiteAsync` and `AxiLiteToDrp` intentionally keep only the stable common-clock subsets in this first batch; the async CDC/arbitration branches remain open. -- 2026-03-21: Replaced the hand-maintained flat phase-1 list in the plan with a generated path-qualified bottom-up queue emitted by `scripts/build_rtl_instantiation_graph.py` into `docs/_meta/rtl_phase1_queue.{md,json}`. Checked in `docs/_meta/rtl_phase1_queue_overrides.json` as the only supported input for manual phase-1 deferrals and ordering exceptions; the initial generated queue contains `411` phase-1 modules with `0` unresolved duplicate-name phase-1 edges under the current filter set. -- 2026-03-21: Implemented and validated the next 10 generated-queue AXI modules: `AxiLiteRegs`, `AxiLiteRespTimer`, `AxiLiteSlave`, `AxiLiteWriteFilter`, `AxiVersion`, `AxiStreamCombiner`, `AxiStreamFlush`, `AxiStreamGearboxPack`, `AxiStreamGearboxUnpack`, and `AxiStreamSplitter`. The combined validation command across those 10 module files passes with `14 passed`. -- 2026-03-26: Implemented and validated `AxiReadPathMux`, `AxiWritePathMux`, and `AxiToAxiLite` with subsystem-local IP-integrator adapters plus new `tests/axi/axi4/` and `tests/axi/bridge/` cocotb benches. `tests/axi/axi4/test_AxiResize.py` is also present on this branch, including the restored `32-bit -> 64-bit` upsize case, but that case is expected to fail here until the separate `AxiResize` RTL-fix branch is merged. -- 2026-03-26: Implemented and validated the next 10 generated-queue AXI modules: `AxiStreamDmaV2WriteMux`, `AxiLiteMasterProxy`, `AxiLiteSequencerRam`, `AxiStreamCompact`, `AxiStreamConcat`, `AxiStreamFrameRateLimiter`, `AxiStreamPrbsFlowCtrl`, `AxiStreamRepeater`, `AxiStreamShift`, and `AxiStreamTrailerAppend`. Added subsystem-local wrappers under `axi/dma/ip_integrator/`, `axi/axi-lite/ip_integrator/`, and `axi/axi-stream/ip_integrator/`, plus new cocotb benches under `tests/axi/`. The combined validation run across those 10 module files passes with `10 passed`. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` currently keep intentionally narrow first-pass checks on this branch instead of forcing the less stable simulator corners. -- 2026-03-26: Implemented the next 10 generated-queue AXI module benches: `AxiStreamTrailerRemove`, `AxiRam`, `AxiLiteToIpBus`, `IpBusToAxiLite`, `AxiStreamDmaV2Read`, `AxiStreamGearbox`, `AxiStreamTap`, `AxiStreamDmaRead`, `AxiStreamDmaV2Write`, and `AxiStreamTimer`. The stable 9-module subset passes with `9 passed`, while `AxiStreamDmaV2Read` remains an expected open failure on this branch because the new minimal aligned one-beat reproducer still aborts at `31 ns` inside the DUT with `std_logic_arith.vhdl:2014:9: ARG is too large in CONV_INTEGER`. -- 2026-04-02: Fixed the remaining `AxiStreamDmaV2Read` open issue by bounding the byte-count `conv_integer()` paths in `axi/axi4/rtl/AxiPkg.vhd`, replacing terminal-beat `tKeep`/`tStrb` generation in `axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd` with direct `slv` mask construction, and expanding `tests/axi/dma/test_AxiStreamDmaV2Read.py` into aligned and short-terminal-beat cases. Local validation now passes with `./.venv/bin/python -m pytest -n 0 -q tests/axi/dma/test_AxiStreamDmaV2Read.py` (`2 passed`). -- 2026-03-26: Replaced the temporary legacy-harness `AxiStreamDmaRead` smoke with a cocotb-owned bench plus `AxiStreamDmaReadIpIntegrator.vhd`. The new test drives the DMA request directly, uses a cocotb AXI RAM model, applies output backpressure, and checks payload plus sideband fields without delegating pass/fail to the old VHDL testbench shell (`1 passed`). -- 2026-03-26: Retargeted the remaining legacy-entity holdouts in the current validated set. `AxiRam` now uses `AxiRamIpIntegrator.vhd` plus a cocotb AXI master round-trip bench, `AxiStreamGearbox` now targets `AxiStreamGearboxIpIntegrator.vhd` instead of the old `tb/` shell, and `AxiLiteCrossbar` now targets `AxiLiteCrossbarIpIntegrator.vhd` instead of `AxiLiteCrossbarTb.vhd` (`3 passed` across the retargeted tests). -- 2026-03-26: Resumed the generated queue at `AxiRateGen` and started scoping the cocotb-facing AXI4/IP-integrator pattern for the next `axi/axi4/` regression. -- 2026-03-26: Implemented and validated `AxiRateGen` with `axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd` plus `tests/axi/axi4/test_AxiRateGen.py`. The stable common-clock subset passes with `1 passed`, and a nearby AXI4 sanity run across `AxiReadPathMux`, `AxiWritePathMux`, `AxiRam`, and `AxiRateGen` passes with `4 passed`. -- 2026-03-26: Tightened the planning docs so wrapper readability is explicit instead of implicit: permanent cocotb-facing `*IpIntegrator.vhd` files should include the standard SURF banner and brief section comments in the first edit, just like the Python benches are required to carry their methodology and tutorial comments. -- 2026-03-26: Tightened the planning docs again so the Python-side header rule is explicit too: checked-in cocotb tests should keep the standard SURF/SLAC banner in addition to the required methodology block and tutorial comments; this is now documented as a first-draft requirement rather than an implied cleanup step. -- 2026-03-26: Corrected the queue frontier after noticing the prior resume notes had jumped ahead to `IpV4Engine`. The real next unfinished non-deferred queue entry is `EthMacRxShift`, followed by `EthMacTxExportGmii`, `EthMacTxShift`, `IpV4EngineRx`, `IpV4EngineTx`, `RawEthFramer`, `UdpEngineRx`, `GLinkTxToRx`, `HtspRx`, and `HtspTx`. -- 2026-03-26: Changed the rollout policy to finish `axi/` first before returning to other subsystems. Recorded temporary `ethernet` and `protocols` subsystem deferrals in `docs/_meta/rtl_phase1_queue_overrides.json`, regenerated the queue, and set the active axi frontier to `AxiResize`. -- 2026-03-27: Implemented and validated the final 11 pending `axi/` benches: `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`. Added the required subsystem-local `*IpIntegrator.vhd` wrappers, kept the new Python tests fully commented with the standard SURF header plus methodology/tutorial notes, and validated the final batch with `./.venv/bin/python -m pytest -n 0 -q ...` across the 11 files (`11 passed`). -- 2026-03-27: The new `AxiStreamDmaRingWrite` regression exposed a width-safety issue in the DUT pointer update under GHDL. Fixed `axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd` so `dmaAck.size` is sliced back to the local pointer width before incrementing `nextAddr`, which keeps the logic behavior unchanged for narrower address maps while making the testbench-safe wrapper configuration simulate cleanly. -- 2026-03-26: Implemented and validated the next 10 generated-queue AXI modules after the two known expected-open skips (`AxiResize` and `AxiStreamDmaV2Read`): `AxiStreamScatterGather`, `AxiMemTester`, `AxiStreamDmaV2Desc`, `AxiStreamDmaV2Fifo`, `AxiReadPathFifo`, `AxiWritePathFifo`, `AxiStreamDmaV2`, `AxiStreamBatchingFifo`, `AxiStreamMon`, and `AxiStreamRingBuffer`. Added the required new wrapper files under `axi/axi4/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/`, fixed `tests/common/regression_utils.py` to stringify simulator env values before dispatch, and validated the combined batch with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamScatterGather.py tests/axi/axi4/test_AxiMemTester.py tests/axi/dma/test_AxiStreamDmaV2Desc.py tests/axi/dma/test_AxiStreamDmaV2Fifo.py tests/axi/axi4/test_AxiReadPathFifo.py tests/axi/axi4/test_AxiWritePathFifo.py tests/axi/dma/test_AxiStreamDmaV2.py tests/axi/axi_stream/test_AxiStreamBatchingFifo.py tests/axi/axi_stream/test_AxiStreamMon.py tests/axi/axi_stream/test_AxiStreamRingBuffer.py` (`10 passed`). -- 2026-04-20: Started the first `ethernet/RoCEv2` phase-1 slice with the stable VHDL-only helper leaves instead of the mixed-language top wrappers. Added `ethernet/RoCEv2/wrappers/EthMacPrepareForICrcWrapper.vhd` and `ethernet/RoCEv2/wrappers/EthMacRxCheckICrcWrapper.vhd`, implemented `tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py` and `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, linted both wrappers cleanly with `./.venv/bin/vsg -c vsg-linter.yml -f ...`, validated the pair with `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py` (`2 passed`), and recorded the remaining open RoCEv2 work as the mixed-language wrapper/assembly path rather than claiming full-family coverage. -- 2026-04-20: Added the pure-VHDL RoCEv2 follow-on benches `tests/ethernet/RoCEv2/test_RoceResizeAndSwap.py` and `test_RoceConfigurator.py` plus their checked-in wrappers `ethernet/RoCEv2/wrappers/RoceResizeAndSwapIpIntegrator.vhd` and `RoceConfiguratorWrapper.vhd`, and validated the pure-VHDL RoCEv2 bench set with `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py tests/ethernet/RoCEv2/test_RoceResizeAndSwap.py tests/ethernet/RoCEv2/test_RoceConfigurator.py` (`4 passed`). -- 2026-04-20: Removed the temporary local CRC stand-ins and the stub-backed `EthMacTxRoCEv2` / `EthMacRxRoCEv2` benches after clarifying the intended boundary: there should be one cocotb test module per entity in `ethernet/RoCEv2/rtl`, but `blue-*` must remain real transitive dependencies rather than being replaced with local test doubles. The current open RoCEv2 bench set is therefore `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`, all of which now require a mixed-language simulation path. From 2fc8d76fb5585acb9be2319f89921f7ba0bb6a12 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 20 Apr 2026 10:28:52 -0700 Subject: [PATCH 26/92] Coaxpress tests first pass. --- docs/_meta/rtl_regression_handoff.md | 10 +- docs/_meta/rtl_regression_progress.md | 8 +- .../core/wrappers/CoaXPressRxHsFsmWrapper.vhd | 96 +++++++ .../wrappers/CoaXPressRxLaneMuxWrapper.vhd | 93 +++++++ .../core/wrappers/CoaXPressRxLaneWrapper.vhd | 81 ++++++ .../wrappers/CoaXPressRxWordPackerWrapper.vhd | 74 ++++++ tests/common/regression_utils.py | 5 + tests/protocols/coaxpress/__init__.py | 9 + .../coaxpress/coaxpress_test_utils.py | 153 +++++++++++ .../coaxpress/test_CoaXPressRxHsFsm.py | 249 ++++++++++++++++++ .../coaxpress/test_CoaXPressRxLane.py | 221 ++++++++++++++++ .../coaxpress/test_CoaXPressRxLaneMux.py | 129 +++++++++ .../coaxpress/test_CoaXPressRxWordPacker.py | 198 ++++++++++++++ 13 files changed, 1322 insertions(+), 4 deletions(-) create mode 100644 protocols/coaxpress/core/wrappers/CoaXPressRxHsFsmWrapper.vhd create mode 100644 protocols/coaxpress/core/wrappers/CoaXPressRxLaneMuxWrapper.vhd create mode 100644 protocols/coaxpress/core/wrappers/CoaXPressRxLaneWrapper.vhd create mode 100644 protocols/coaxpress/core/wrappers/CoaXPressRxWordPackerWrapper.vhd create mode 100644 tests/protocols/coaxpress/__init__.py create mode 100644 tests/protocols/coaxpress/coaxpress_test_utils.py create mode 100644 tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py create mode 100644 tests/protocols/coaxpress/test_CoaXPressRxLane.py create mode 100644 tests/protocols/coaxpress/test_CoaXPressRxLaneMux.py create mode 100644 tests/protocols/coaxpress/test_CoaXPressRxWordPacker.py diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index 50da460dc1..56a16700ff 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -19,11 +19,12 @@ - Treat stale simulator cleanup as part of task completion: after any `pytest`, cocotb, GHDL, or similar launched verification step, sweep for leftover child processes and kill them before moving on ## Quick Resume Snapshot -- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, and the current Ethernet coverage now spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the pure-VHDL RoCEv2 quartet (`EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator`). The remaining RoCEv2 requirement is still one cocotb test module per entity in `ethernet/RoCEv2/rtl`, but the last five entities depend on real `blue-*` submodules and therefore need a mixed-language simulator path rather than local stand-ins. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. +- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, the current Ethernet coverage spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the pure-VHDL RoCEv2 quartet (`EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator`), and a new user-directed CoaXPress receive-path wave is now checked in under `tests/protocols/coaxpress/`. The validated CoaXPress subset is the pure-VHDL receive quartet `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, and `CoaXPressRxHsFsm`, with subsystem-local wrappers under `protocols/coaxpress/core/wrappers/`. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. - Current axi frontier: complete for the intended simulator-friendly pass in this branch snapshot; do not resume from the older stale `AxiResize` note. - Current validated-open issues: - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core` remain untouched in phase 1, while the remaining RoCEv2 gap is the mixed-language bench path for the five RTL entities that instantiate generated submodules: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`. - `EthMacRxImportXlgmii` and `EthMacTxExportXlgmii` are still placeholder no-op RTL; the checked-in tests now lock down that inert contract instead of claiming functional XLGMII support. + - The CoaXPress first pass is currently receive-only. The obvious next pure-VHDL gaps are `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressTx`, `CoaXPressRx`, `CoaXPressConfig`, `CoaXPressCore`, and the over-fiber bridge trio. The current `CoaXPressRxHsFsm` bench intentionally stays on the stable one-lane path, so deeper multi-lane stepping/alignment behavior remains open. - Current planning discipline: - Use manual user-directed area selection as the active source of truth for what to work on next. - Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the actual validated branch frontier. @@ -64,6 +65,7 @@ - `tests/ethernet/UdpEngine/udp_test_utils.py` is now the shared home for the UDP slice: legacy-address constants, pseudo-frame builders, DHCP option helpers, and the common cocotb bench setup for the `ArpIpTable`, `UdpEngine*`, and `UdpEngineWrapper*` wrappers. Reuse it instead of rebuilding IPv4/UDP helper glue in each test module. - `tests/ethernet/IpV4Engine/ipv4_test_utils.py` is now the shared home for the IPv4 slice: packet/header builders and common cocotb bench setup for the `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, and `IpV4Engine*` wrappers. Reuse it instead of cloning IPv4 framing helpers across that directory. - `tests/protocols/ssi/ssi_test_utils.py` is the shared home for SSI transaction work: flat SSI endpoints, beat/frame helpers, contiguous-frame send, receive/no-output utilities, and `SOF`/`EOFE`-aware assertions. Use it instead of open-coding SSI handshake loops or terminal-flag checks. +- `tests/protocols/coaxpress/coaxpress_test_utils.py` is now the shared home for the CoaXPress receive slice: protocol constants, repeated-byte word builders, wide-word packing helpers, basic clock/reset helpers, and simple pulse-capture utilities for the raw-word wrappers. Reuse it instead of cloning CoaXPress symbol constants or one-cycle output capture loops across future CoaXPress benches. - Across the AXI slices, prefer the subsystem helper paths that already exist for register transactions, frame movement, and setup. In practice that means reusing helpers such as `tests/common/regression_utils.py`, the AXI/ethernet subsystem utility modules, and any nearby module-family helpers before inventing a one-off local transaction wrapper. - The current `EthMacCore` slice is intentionally a checked-in-wrapper-first rollout, not a cocotb-generated-wrapper experiment. Keep new Ethernet work on that same pattern unless the simulator forces a very local generic adapter. - The XGMII import/export loopback behavior differs from the GMII path when `phyReady` drops mid-traffic: the blocked frame is retained and drains after link recovery, padded to Ethernet's minimum frame size if it was short. The GMII path drops that blocked frame. Future import/export coverage should preserve that distinction instead of forcing one common expectation. @@ -163,7 +165,11 @@ One small RTL fix landed during that validation pass because the new `AxiStreamD A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instantiation_graph.md` and `docs/_meta/rtl_instantiation_graph.json`, and the same generator now also emits a path-qualified bottom-up phase-1 queue at `docs/_meta/rtl_phase1_queue.md` and `docs/_meta/rtl_phase1_queue.json`. Keep the graph and queue for provenance, but treat them as historical context rather than as the default source of truth for what to implement next. ## Immediate Next Task -If the user keeps the focus on `ethernet/RoCEv2`, the next real step is enabling a mixed-language cocotb path for the five remaining RTL entities listed above. Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the real validated subset, and do not reintroduce local stand-ins for `blue-*`. +If the user keeps the focus on `protocols/coaxpress`, the next practical step is either: +1. finish the remaining pure-VHDL leaf/helper work (`CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressOverFiberBridgeRx`, `CoaXPressOverFiberBridgeTx`) before moving upward, or +2. deepen the current receive-path benches on the intentionally open multi-lane branches (`CoaXPressRxHsFsm` stepping/alignment and then `CoaXPressRx` integration). + +If the user switches back to `ethernet/RoCEv2`, the next real step is still enabling a mixed-language cocotb path for the five remaining RTL entities listed above. Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the real validated subset, and do not reintroduce local stand-ins for `blue-*`. ## Read Order 1. `docs/_meta/rtl_regression_handoff.md` diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index b5ed66ea17..0108735146 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -3,7 +3,7 @@ ## Summary - Current phase: Phase-1 implementation active - Current subsystem: manual user-directed rollout tracking -- Current focus module: keep the RoCEv2 boundary aligned to `ethernet/RoCEv2/rtl`: the current validated subset is the pure-VHDL quartet (`EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator`), while the remaining five RTL entities need real mixed-language simulation because they instantiate `blue-*` modules underneath. +- Current focus module: user-directed CoaXPress receive-path first pass under `protocols/coaxpress/core/rtl`, with validated cocotb coverage now checked in for `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, and `CoaXPressRxHsFsm`. - Last updated: 2026-04-20 ## Current Frontier Snapshot @@ -21,10 +21,14 @@ - RoCEv2 RTL target matrix: - Covered now under the current GHDL-only flow: `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, `RoceConfigurator` - Still required, but need real `blue-*` dependencies under a mixed-language simulator: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, `RoceEngineWrapper` +- CoaXPress RTL target matrix: + - Covered now under the current GHDL-only flow: `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, `CoaXPressRxHsFsm` + - Still open in the same pure-VHDL family: `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressTx`, `CoaXPressRx`, `CoaXPressConfig`, `CoaXPressCore`, `CoaXPressOverFiberBridgeRx`, `CoaXPressOverFiberBridgeTx`, and `CoaXPressOverFiberBridge` - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. - For `ethernet`, keep using the checked-in wrappers under `ethernet/*/wrappers/` plus the shared helper layers in `tests/ethernet/EthMacCore/ethmac_test_utils.py`, `tests/ethernet/RawEthFramer/raw_eth_test_utils.py`, `tests/ethernet/UdpEngine/udp_test_utils.py`, and `tests/ethernet/IpV4Engine/ipv4_test_utils.py`. The practical first-pass shape is flat EMAC/app beat wrappers with explicit sideband bits, curated functional slices instead of exhaustive generic sweeps, and dedicated pair/integration wrappers only where an old VHDL bench contributes a topology worth preserving. + - For `protocols/coaxpress`, the practical first-pass shape is subsystem-local wrappers under `protocols/coaxpress/core/wrappers/` plus a small helper layer in `tests/protocols/coaxpress/coaxpress_test_utils.py`. Keep the input side raw and cycle-native where the DUT already consumes protocol words directly, and only flatten the observable AXI-stream outputs or handshaked lane arrays that cocotb actually needs to inspect. ## Status | Subsystem | Inventory | Smoke | Functional | Notes | @@ -33,7 +37,7 @@ | `base` | started | not started | started | Validated low-level regressions now exist for `FifoAsync`, `FifoSync`, `FifoOutputPipeline`, `FifoWrFsm`, `FifoRdFsm`, `Fifo`, `FifoCascade`, `FifoMux`, `Synchronizer`, `SynchronizerVector`, `SynchronizerEdge`, `SynchronizerOneShot`, `SynchronizerFifo`, `SynchronizerOneShotCnt`, `SynchronizerOneShotVector`, `SynchronizerOneShotCntVector`, `SyncStatusVector`, `SyncTrigPeriod`, `SyncMinMax`, `SyncClockFreq`, `SyncTrigRate`, `SyncTrigRateVector`, `RstSync`, `RstPipeline`, `RstPipelineVector`, `PwrUpRst`, `Arbiter`, `ClockDivider`, `Debouncer`, `Gearbox`, `AsyncGearbox`, `Heartbeat`, `Mux`, `OneShot`, `RegisterVector`, `WatchDogRst`, `Scrambler`, `MasterRamIpIntegrator`, `SlaveRamIpIntegrator`, `SimpleDualPortRam`, `DualPortRam`, `TrueDualPortRam`, `LutRam`, `SlvDelay`, `SlvFixedDelay`, `SlvDelayRam`, `SlvDelayFifo`, `Crc32Parallel`, `Crc32`, and `CRC32Rtl` under subsystem-organized `tests/base/` packages. Remaining uncovered `base/` entities are vendor-heavy, dummy-backed, or `LutFixedDelay`, which is deferred because it depends on `SinglePortRamPrimitive`. | | `dsp` | started | not started | started | The planned `dsp/generic/fixed` leaf batch is now validated under `tests/dsp/generic/`: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. Shared DSP helpers now live in `tests/dsp/generic/dsp_test_utils.py`, and the legacy VHDL benches under `dsp/generic/tb/` were treated as behavioral reference material rather than as execution constraints. | | `axi` | started | not started | started | The axi-first pass is now complete for the simulator-friendly queue. The final locally validated batch adds `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`, with a combined `11 passed` validation run on 2026-03-27. Added checked-in subsystem wrappers under `axi/axi4/ip_integrator/`, `axi/axi-lite/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/` for those benches. `AxiStreamFifoV2` now has an expanded `10 passed` wrapper regression under `tests/axi/axi_stream/` covering async and sync width conversion, metadata truncation, `VALID_THOLD` frame-ready and burst-release modes, dynamic pause-threshold behavior, `CASCADE_SIZE=2`, and the `S_HAS_TREADY=0` pause-only source-side path. `AxiResize` now passes its equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` wrapper regression on this branch after the read-hold RTL fix. `AxiLiteAsync`, `AxiLiteToDrp`, and `AxiRateGen` still keep intentionally narrow common-clock subsets while the more timing-sensitive async AXI-Lite crossing branches remain open. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` still keep intentionally narrow first-pass subsets. `AxiStreamDmaV2Read` is now validated with a two-case wrapper regression covering both aligned and short terminal-beat reads after fixing bounded byte-count conversion in `AxiPkg` and terminal-mask generation in `AxiStreamDmaV2Read`. | -| `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. | +| `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. `protocols/coaxpress/` now has a first receive-path wave under `tests/protocols/coaxpress/` backed by checked-in wrappers in `protocols/coaxpress/core/wrappers/`: `CoaXPressRxWordPacker` covers offset-start packing and reset flush, `CoaXPressRxLaneMux` covers lane clipping plus frame-boundary rotation under backpressure, `CoaXPressRxLane` covers stream/config/event/heartbeat decode plus mid-packet `IO_ACK` and link-drop recovery, and `CoaXPressRxHsFsm` covers rectangular-header packing, two-line image framing, and malformed-header recovery. The current CoaXPress subset is intentionally narrow: it focuses on the pure-VHDL receive path, keeps the `CoaXPressRxHsFsm` wrapper on the stable one-lane path for now, and leaves the transmit, top-level, and over-fiber bridge blocks for a follow-on pass. | | `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers both the original leaf slice and the deeper assembly benches for `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`, plus direct `EthMacRxBypass` / `EthMacTxBypass` leaf benches and import/export sweeps that now explicitly include the current placeholder `XLGMII` contract. `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, including the successful multi-beat `RawEthFramerTx` unicast-forwarding path after lookup resolution. `tests/ethernet/UdpEngine/` covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, with the top/wrapper benches now widened across client/server routing paths. `tests/ethernet/IpV4Engine/` covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, and the top/leaf benches now also include protocol-TX and deeper ICMP reject/recovery coverage. `tests/ethernet/RoCEv2/` currently covers the pure-VHDL RTL entities `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator` through checked-in wrappers under `ethernet/RoCEv2/wrappers/`. The remaining RoCEv2 RTL entities that still need cocotb benches are `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`, and those should use the real generated `blue-*` dependencies rather than local stand-ins. The explicit Ethernet caveats are now the larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core`, the mixed-language RoCEv2 bench gap listed above, plus the still-placeholder `EthMac*Xlgmii` RTL. | | `devices` | not started | not started | not started | Many vendor-heavy cases | | `xilinx` | not started | not started | not started | Many vendor-heavy cases | diff --git a/protocols/coaxpress/core/wrappers/CoaXPressRxHsFsmWrapper.vhd b/protocols/coaxpress/core/wrappers/CoaXPressRxHsFsmWrapper.vhd new file mode 100644 index 0000000000..184b114452 --- /dev/null +++ b/protocols/coaxpress/core/wrappers/CoaXPressRxHsFsmWrapper.vhd @@ -0,0 +1,96 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for CoaXPressRxHsFsm +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.SsiPkg.all; + +entity CoaXPressRxHsFsmWrapper is + generic ( + NUM_LANES_G : positive range 1 to 8 := 1; + RX_FSM_CNT_WIDTH_G : positive range 1 to 24 := 16); + port ( + rxClk : in sl; + rxRst : in sl; + rxFsmRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(32*NUM_LANES_G-1 downto 0); + sAxisTKeep : in slv(4*NUM_LANES_G-1 downto 0); + sAxisTLast : in sl; + sAxisTReady : out sl; + hdrTValid : out sl; + hdrTData : out slv(223 downto 0); + hdrTLast : out sl; + hdrTSof : out sl; + dataTValid : out sl; + dataTData : out slv(32*NUM_LANES_G-1 downto 0); + dataTKeep : out slv(4*NUM_LANES_G-1 downto 0); + dataTLast : out sl; + rxFsmError : out sl); +end entity CoaXPressRxHsFsmWrapper; + +architecture rtl of CoaXPressRxHsFsmWrapper is + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal hdrMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal dataMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + +begin + + -- Present the flattened source beat as one wide AXI-stream record. + sAxisComb : process (sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(32*NUM_LANES_G-1 downto 0) := sAxisTData; + v.tKeep(4*NUM_LANES_G-1 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + sAxisMaster <= v; + end process sAxisComb; + + sAxisTReady <= sAxisSlave.tReady; + + -- Flatten the observable header and image-data outputs. + hdrTValid <= hdrMaster.tValid; + hdrTData <= hdrMaster.tData(223 downto 0); + hdrTLast <= hdrMaster.tLast; + hdrTSof <= hdrMaster.tUser(SSI_SOF_C); + dataTValid <= dataMaster.tValid; + dataTData <= dataMaster.tData(32*NUM_LANES_G-1 downto 0); + dataTKeep <= dataMaster.tKeep(4*NUM_LANES_G-1 downto 0); + dataTLast <= dataMaster.tLast; + + -- Instantiate the real high-speed receive FSM behind the shim. + U_DUT : entity surf.CoaXPressRxHsFsm + generic map ( + TPD_G => 1 ns, + RX_FSM_CNT_WIDTH_G => RX_FSM_CNT_WIDTH_G, + NUM_LANES_G => NUM_LANES_G) + port map ( + rxClk => rxClk, + rxRst => rxRst, + rxFsmRst => rxFsmRst, + rxFsmError => rxFsmError, + rxMaster => sAxisMaster, + rxSlave => sAxisSlave, + hdrMaster => hdrMaster, + dataMaster => dataMaster); + +end architecture rtl; diff --git a/protocols/coaxpress/core/wrappers/CoaXPressRxLaneMuxWrapper.vhd b/protocols/coaxpress/core/wrappers/CoaXPressRxLaneMuxWrapper.vhd new file mode 100644 index 0000000000..69785e1578 --- /dev/null +++ b/protocols/coaxpress/core/wrappers/CoaXPressRxLaneMuxWrapper.vhd @@ -0,0 +1,93 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for CoaXPressRxLaneMux +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; + +entity CoaXPressRxLaneMuxWrapper is + generic ( + NUM_LANES_G : positive range 1 to 8 := 1); + port ( + rxClk : in sl; + rxRst : in sl; + rxFsmRst : in sl; + numOfLane : in slv(2 downto 0); + sAxisTValid : in slv(NUM_LANES_G-1 downto 0); + sAxisTData : in slv(32*NUM_LANES_G*NUM_LANES_G-1 downto 0); + sAxisTKeep : in slv(4*NUM_LANES_G*NUM_LANES_G-1 downto 0); + sAxisTLast : in slv(NUM_LANES_G-1 downto 0); + sAxisTReady : out slv(NUM_LANES_G-1 downto 0); + mAxisTValid : out sl; + mAxisTData : out slv(32*NUM_LANES_G-1 downto 0); + mAxisTKeep : out slv(4*NUM_LANES_G-1 downto 0); + mAxisTLast : out sl; + mAxisTReady : in sl); +end entity CoaXPressRxLaneMuxWrapper; + +architecture rtl of CoaXPressRxLaneMuxWrapper is + + signal rxMasters : AxiStreamMasterArray(NUM_LANES_G-1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal rxSlaves : AxiStreamSlaveArray(NUM_LANES_G-1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + +begin + + -- Rebuild the per-lane record array from the concatenated cocotb ports. + sAxisComb : process (sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + variable masters : AxiStreamMasterArray(NUM_LANES_G-1 downto 0); + begin + masters := (others => AXI_STREAM_MASTER_INIT_C); + for i in 0 to NUM_LANES_G-1 loop + masters(i).tValid := sAxisTValid(i); + masters(i).tData(32*NUM_LANES_G-1 downto 0) := + sAxisTData(32*NUM_LANES_G*(i+1)-1 downto 32*NUM_LANES_G*i); + masters(i).tKeep(4*NUM_LANES_G-1 downto 0) := + sAxisTKeep(4*NUM_LANES_G*(i+1)-1 downto 4*NUM_LANES_G*i); + masters(i).tLast := sAxisTLast(i); + end loop; + rxMasters <= masters; + end process sAxisComb; + + sAxisReadyGen : for i in 0 to NUM_LANES_G-1 generate + sAxisTReady(i) <= rxSlaves(i).tReady; + end generate sAxisReadyGen; + + -- Flatten the mux output back to simple handshaked ports. + mAxisSlave.tReady <= mAxisTReady; + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(32*NUM_LANES_G-1 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(4*NUM_LANES_G-1 downto 0); + mAxisTLast <= mAxisMaster.tLast; + + -- Instantiate the real lane mux with the rebuilt arrays. + U_DUT : entity surf.CoaXPressRxLaneMux + generic map ( + TPD_G => 1 ns, + NUM_LANES_G => NUM_LANES_G) + port map ( + rxClk => rxClk, + rxRst => rxRst, + rxFsmRst => rxFsmRst, + numOfLane => numOfLane, + rxMasters => rxMasters, + rxSlaves => rxSlaves, + rxMaster => mAxisMaster, + rxSlave => mAxisSlave); + +end architecture rtl; diff --git a/protocols/coaxpress/core/wrappers/CoaXPressRxLaneWrapper.vhd b/protocols/coaxpress/core/wrappers/CoaXPressRxLaneWrapper.vhd new file mode 100644 index 0000000000..1da89a8fde --- /dev/null +++ b/protocols/coaxpress/core/wrappers/CoaXPressRxLaneWrapper.vhd @@ -0,0 +1,81 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for CoaXPressRxLane +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; + +entity CoaXPressRxLaneWrapper is + port ( + rxClk : in sl; + rxRst : in sl; + rxLinkUp : in sl; + rxData : in slv(31 downto 0); + rxDataK : in slv(3 downto 0); + cfgTValid : out sl; + cfgTData : out slv(63 downto 0); + dataTValid : out sl; + dataTData : out slv(31 downto 0); + dataTUser : out slv(3 downto 0); + dataTLast : out sl; + heartbeatTValid : out sl; + heartbeatTData : out slv(95 downto 0); + heartbeatTLast : out sl; + ioAck : out sl; + eventAck : out sl; + eventTag : out slv(7 downto 0)); +end entity CoaXPressRxLaneWrapper; + +architecture rtl of CoaXPressRxLaneWrapper is + + signal cfgMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal dataMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal heartbeatMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal imageHdrMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + +begin + + -- Flatten the DUT's observable stream outputs into fixed-width scalar ports. + cfgTValid <= cfgMaster.tValid; + cfgTData <= cfgMaster.tData(63 downto 0); + dataTValid <= dataMaster.tValid; + dataTData <= dataMaster.tData(31 downto 0); + dataTUser <= dataMaster.tUser(3 downto 0); + dataTLast <= dataMaster.tLast; + heartbeatTValid <= heartbeatMaster.tValid; + heartbeatTData <= heartbeatMaster.tData(95 downto 0); + heartbeatTLast <= heartbeatMaster.tLast; + + -- Instantiate the real receive-lane decoder with the flattened ports. + U_DUT : entity surf.CoaXPressRxLane + generic map ( + TPD_G => 1 ns) + port map ( + rxClk => rxClk, + rxRst => rxRst, + cfgMaster => cfgMaster, + dataMaster => dataMaster, + heatbeatMaster => heartbeatMaster, + imageHdrMaster => imageHdrMaster, + ioAck => ioAck, + eventAck => eventAck, + eventTag => eventTag, + rxData => rxData, + rxDataK => rxDataK, + rxLinkUp => rxLinkUp); + +end architecture rtl; diff --git a/protocols/coaxpress/core/wrappers/CoaXPressRxWordPackerWrapper.vhd b/protocols/coaxpress/core/wrappers/CoaXPressRxWordPackerWrapper.vhd new file mode 100644 index 0000000000..1b2d092b8c --- /dev/null +++ b/protocols/coaxpress/core/wrappers/CoaXPressRxWordPackerWrapper.vhd @@ -0,0 +1,74 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for CoaXPressRxWordPacker +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; + +entity CoaXPressRxWordPackerWrapper is + generic ( + NUM_LANES_G : positive range 1 to 8 := 1); + port ( + rxClk : in sl; + rxRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(32*NUM_LANES_G-1 downto 0); + sAxisTKeep : in slv(4*NUM_LANES_G-1 downto 0); + sAxisTLast : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(32*NUM_LANES_G-1 downto 0); + mAxisTKeep : out slv(4*NUM_LANES_G-1 downto 0); + mAxisTLast : out sl); +end entity CoaXPressRxWordPackerWrapper; + +architecture rtl of CoaXPressRxWordPackerWrapper is + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + +begin + + -- Present the flat cocotb stimulus as one AXI-stream record. + sAxisComb : process (sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; + v.tData(32*NUM_LANES_G-1 downto 0) := sAxisTData; + v.tKeep(4*NUM_LANES_G-1 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + sAxisMaster <= v; + end process sAxisComb; + + -- Flatten the packed output beat back to simple scalar ports. + mAxisTValid <= mAxisMaster.tValid; + mAxisTData <= mAxisMaster.tData(32*NUM_LANES_G-1 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(4*NUM_LANES_G-1 downto 0); + mAxisTLast <= mAxisMaster.tLast; + + -- Instantiate the real word packer behind the shim. + U_DUT : entity surf.CoaXPressRxWordPacker + generic map ( + TPD_G => 1 ns, + NUM_LANES_G => NUM_LANES_G) + port map ( + rxClk => rxClk, + rxRst => rxRst, + sAxisMaster => sAxisMaster, + mAxisMaster => mAxisMaster); + +end architecture rtl; diff --git a/tests/common/regression_utils.py b/tests/common/regression_utils.py index 2a32fd7b8b..d5dfe9a871 100644 --- a/tests/common/regression_utils.py +++ b/tests/common/regression_utils.py @@ -140,6 +140,11 @@ def env_float(name: str, *, default: float) -> float: return float(normalized) +def env_int(name: str, *, default: int) -> int: + raw = os.environ.get(name) + return default if raw is None else int(raw.strip().strip("'").strip('"')) + + def parameter_case(case_id: str, **parameters: str): return pytest.param(parameters, id=case_id) diff --git a/tests/protocols/coaxpress/__init__.py b/tests/protocols/coaxpress/__init__.py new file mode 100644 index 0000000000..b0085f1a17 --- /dev/null +++ b/tests/protocols/coaxpress/__init__.py @@ -0,0 +1,9 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## diff --git a/tests/protocols/coaxpress/coaxpress_test_utils.py b/tests/protocols/coaxpress/coaxpress_test_utils.py new file mode 100644 index 0000000000..ade19b2257 --- /dev/null +++ b/tests/protocols/coaxpress/coaxpress_test_utils.py @@ -0,0 +1,153 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +from __future__ import annotations + +from dataclasses import dataclass + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer + + +CXP_IDLE = 0xB53C3CBC +CXP_IDLE_K = 0x7 +CXP_SOP = 0xFBFBFBFB +CXP_MARKER = 0x7C7C7C7C +CXP_IO_ACK = 0xDCDCDCDC + + +@dataclass +class AxisBeat: + data: int + keep: int + last: int = 0 + user: int = 0 + + +def repeat_byte(value: int) -> int: + byte = value & 0xFF + return byte | (byte << 8) | (byte << 16) | (byte << 24) + + +def pack_words(words: list[int], *, word_bits: int = 32) -> int: + mask = (1 << word_bits) - 1 + value = 0 + for index, word in enumerate(words): + value |= (word & mask) << (index * word_bits) + return value + + +def keep_for_words(word_count: int) -> int: + return (1 << (4 * word_count)) - 1 + + +def lane_keep_mask(indices: list[int]) -> int: + keep = 0 + for index in indices: + keep |= 0xF << (4 * index) + return keep + + +def start_clock(signal, *, period_ns: float = 5.0) -> None: + cocotb.start_soon(Clock(signal, period_ns, unit="ns").start()) + + +async def cycle(clk, count: int = 1) -> None: + for _ in range(count): + await RisingEdge(clk) + await Timer(1, unit="ns") + + +async def reset_dut(dut, *, clk_name: str = "rxClk", reset_names: tuple[str, ...] = ("rxRst",)) -> None: + clk = getattr(dut, clk_name) + for reset_name in reset_names: + getattr(dut, reset_name).setimmediatevalue(1) + await cycle(clk, 4) + for reset_name in reset_names: + getattr(dut, reset_name).value = 0 + await cycle(clk, 2) + + +def pulse_snapshot(dut, *, valid_name: str, field_names: tuple[str, ...]) -> dict[str, int] | None: + if int(getattr(dut, valid_name).value) == 0: + return None + return {field_name: int(getattr(dut, field_name).value) for field_name in field_names} + + +async def send_rx_word( + dut, + *, + data: int, + data_k: int, + clk, + link_up: int = 1, + capture: list[dict[str, int]] | None = None, + valid_name: str | None = None, + field_names: tuple[str, ...] = (), +) -> None: + dut.rxLinkUp.value = link_up + dut.rxData.value = data + dut.rxDataK.value = data_k + await RisingEdge(clk) + await Timer(1, unit="ns") + if capture is not None and valid_name is not None: + snapshot = pulse_snapshot(dut, valid_name=valid_name, field_names=field_names) + if snapshot is not None: + capture.append(snapshot) + + +async def send_axis_beats_no_ready( + dut, + *, + beats: list[AxisBeat], + clk, + prefix: str = "sAxis", + capture: list[dict[str, int]] | None = None, + valid_name: str | None = None, + field_names: tuple[str, ...] = (), +) -> None: + getattr(dut, f"{prefix}TValid").value = 0 + getattr(dut, f"{prefix}TData").value = 0 + getattr(dut, f"{prefix}TKeep").value = 0 + getattr(dut, f"{prefix}TLast").value = 0 + for beat in beats: + getattr(dut, f"{prefix}TValid").value = 1 + getattr(dut, f"{prefix}TData").value = beat.data + getattr(dut, f"{prefix}TKeep").value = beat.keep + getattr(dut, f"{prefix}TLast").value = beat.last + await RisingEdge(clk) + await Timer(1, unit="ns") + if capture is not None and valid_name is not None: + snapshot = pulse_snapshot(dut, valid_name=valid_name, field_names=field_names) + if snapshot is not None: + capture.append(snapshot) + getattr(dut, f"{prefix}TValid").value = 0 + getattr(dut, f"{prefix}TData").value = 0 + getattr(dut, f"{prefix}TKeep").value = 0 + getattr(dut, f"{prefix}TLast").value = 0 + + +async def collect_pulses( + dut, + *, + clk, + cycles: int, + valid_name: str, + field_names: tuple[str, ...], +) -> list[dict[str, int]]: + observed: list[dict[str, int]] = [] + for _ in range(cycles): + await RisingEdge(clk) + await Timer(1, unit="ns") + snapshot = pulse_snapshot(dut, valid_name=valid_name, field_names=field_names) + if snapshot is not None: + observed.append(snapshot) + return observed diff --git a/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py b/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py new file mode 100644 index 0000000000..3241648f80 --- /dev/null +++ b/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py @@ -0,0 +1,249 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Start with a one-lane wrapper configuration so the first CoaXPress +# FSM regression can focus on header/line correctness before broader +# multi-lane timing branches are added. +# - Stimulus: Drive a complete rectangular-image transaction with two lines, +# then a malformed header followed by a clean retry. +# - Checks: The FSM must emit the byte-swapped packed header, forward the exact +# programmed number of data words, assert frame `TLAST` only on the final +# line, and recover cleanly after a malformed repeated-byte header word. +# - Timing: The source holds each beat until `sAxisTReady` rises so the checks +# reflect the FSM's actual per-beat acceptance rather than idealized traffic. + +import cocotb +import pytest +from cocotb.triggers import RisingEdge, Timer + +from tests.common.regression_utils import parameter_case, run_surf_vhdl_test +from tests.protocols.coaxpress.coaxpress_test_utils import ( + CXP_MARKER, + cycle, + pack_words, + repeat_byte, + reset_dut, + start_clock, +) + + +def _capture_outputs(dut, *, header_beats: list[dict[str, int]], data_beats: list[dict[str, int]]) -> None: + if int(dut.hdrTValid.value) == 1: + header_beats.append( + { + "hdrTData": int(dut.hdrTData.value), + "hdrTLast": int(dut.hdrTLast.value), + "hdrTSof": int(dut.hdrTSof.value), + } + ) + if int(dut.dataTValid.value) == 1: + data_beats.append( + { + "dataTData": int(dut.dataTData.value), + "dataTKeep": int(dut.dataTKeep.value), + "dataTLast": int(dut.dataTLast.value), + } + ) + + +async def _send_handshaked_beat(dut, *, data: int, keep: int, last: int = 0) -> None: + dut.sAxisTValid.value = 1 + dut.sAxisTData.value = data + dut.sAxisTKeep.value = keep + dut.sAxisTLast.value = last + while True: + await RisingEdge(dut.rxClk) + await Timer(1, unit="ns") + if int(dut.sAxisTReady.value) == 1: + break + dut.sAxisTValid.value = 0 + dut.sAxisTData.value = 0 + dut.sAxisTKeep.value = 0 + dut.sAxisTLast.value = 0 + + +def _header_words() -> list[int]: + return [ + repeat_byte(0x12), + repeat_byte(0x34), + repeat_byte(0x56), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x03), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x04), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x02), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x05), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x03), + repeat_byte(0x00), + repeat_byte(0x10), + repeat_byte(0x00), + repeat_byte(0x20), + repeat_byte(0xAA), + ] + + +def _expected_header_data() -> int: + return pack_words( + [ + 0x3456AA12, + 0x00000003, + 0x00000004, + 0x00000002, + 0x00000005, + 0x00000003, + 0x00200010, + ] + ) + + +@cocotb.test() +async def coaxpress_rx_hs_fsm_header_and_lines_test(dut): + start_clock(dut.rxClk) + dut.rxRst.setimmediatevalue(1) + dut.rxFsmRst.setimmediatevalue(0) + dut.sAxisTValid.setimmediatevalue(0) + dut.sAxisTData.setimmediatevalue(0) + dut.sAxisTKeep.setimmediatevalue(0) + dut.sAxisTLast.setimmediatevalue(0) + await reset_dut(dut, reset_names=("rxRst",)) + header_beats: list[dict[str, int]] = [] + data_beats: list[dict[str, int]] = [] + + # Send one header packet that declares two lines of three 32-bit words. + await _send_handshaked_beat(dut, data=CXP_MARKER, keep=0xF) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + await _send_handshaked_beat(dut, data=repeat_byte(0x01), keep=0xF) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + for word in _header_words(): + await _send_handshaked_beat(dut, data=word, keep=0xF) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + + # Follow with two line packets whose final word should close the frame. + for line_words in ([0x11111111, 0x22222222, 0x33333333], [0x44444444, 0x55555555, 0x66666666]): + await _send_handshaked_beat(dut, data=CXP_MARKER, keep=0xF) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + await _send_handshaked_beat(dut, data=repeat_byte(0x02), keep=0xF) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + for word in line_words: + await _send_handshaked_beat(dut, data=word, keep=0xF) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + + for _ in range(6): + await RisingEdge(dut.rxClk) + await Timer(1, unit="ns") + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + + assert header_beats == [{"hdrTData": _expected_header_data(), "hdrTLast": 1, "hdrTSof": 1}], ( + [] if not header_beats else [hex(header_beats[0]["hdrTData"])] + ) + assert data_beats == [ + {"dataTData": 0x11111111, "dataTKeep": 0xF, "dataTLast": 0}, + {"dataTData": 0x22222222, "dataTKeep": 0xF, "dataTLast": 0}, + {"dataTData": 0x33333333, "dataTKeep": 0xF, "dataTLast": 0}, + {"dataTData": 0x44444444, "dataTKeep": 0xF, "dataTLast": 0}, + {"dataTData": 0x55555555, "dataTKeep": 0xF, "dataTLast": 0}, + {"dataTData": 0x66666666, "dataTKeep": 0xF, "dataTLast": 1}, + ] + + +@cocotb.test() +async def coaxpress_rx_hs_fsm_malformed_header_recovery_test(dut): + start_clock(dut.rxClk) + dut.rxRst.setimmediatevalue(1) + dut.rxFsmRst.setimmediatevalue(0) + dut.sAxisTValid.setimmediatevalue(0) + dut.sAxisTData.setimmediatevalue(0) + dut.sAxisTKeep.setimmediatevalue(0) + dut.sAxisTLast.setimmediatevalue(0) + await reset_dut(dut, reset_names=("rxRst",)) + header_beats: list[dict[str, int]] = [] + data_beats: list[dict[str, int]] = [] + error_seen = False + + # Corrupt one repeated-byte header word and make sure the retry is what + # actually emits the header/data outputs. + await _send_handshaked_beat(dut, data=CXP_MARKER, keep=0xF) + error_seen |= int(dut.rxFsmError.value) == 1 + await _send_handshaked_beat(dut, data=repeat_byte(0x01), keep=0xF) + error_seen |= int(dut.rxFsmError.value) == 1 + for index, word in enumerate(_header_words()): + await _send_handshaked_beat( + dut, + data=0x01020304 if index == 5 else word, + keep=0xF, + ) + error_seen |= int(dut.rxFsmError.value) == 1 + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + await cycle(dut.rxClk, 2) + error_seen |= int(dut.rxFsmError.value) == 1 + assert error_seen + assert not header_beats + + await _send_handshaked_beat(dut, data=CXP_MARKER, keep=0xF) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + await _send_handshaked_beat(dut, data=repeat_byte(0x01), keep=0xF) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + for word in _header_words(): + await _send_handshaked_beat(dut, data=word, keep=0xF) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + await _send_handshaked_beat(dut, data=CXP_MARKER, keep=0xF) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + await _send_handshaked_beat(dut, data=repeat_byte(0x02), keep=0xF) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + await _send_handshaked_beat(dut, data=0xABCDEF00, keep=0xF) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + await _send_handshaked_beat(dut, data=0xABCDEF01, keep=0xF) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + await _send_handshaked_beat(dut, data=0xABCDEF02, keep=0xF) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + + for _ in range(6): + await RisingEdge(dut.rxClk) + await Timer(1, unit="ns") + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + + assert header_beats == [{"hdrTData": _expected_header_data(), "hdrTLast": 1, "hdrTSof": 1}], ( + [] if not header_beats else [hex(header_beats[0]["hdrTData"])] + ) + assert data_beats == [ + {"dataTData": 0xABCDEF00, "dataTKeep": 0xF, "dataTLast": 0}, + {"dataTData": 0xABCDEF01, "dataTKeep": 0xF, "dataTLast": 0}, + {"dataTData": 0xABCDEF02, "dataTKeep": 0xF, "dataTLast": 0}, + ] + + +PARAMETER_SWEEP = [parameter_case("single_lane", NUM_LANES_G="1", RX_FSM_CNT_WIDTH_G="8")] + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +def test_CoaXPressRxHsFsm(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.coaxpressrxhsfsmwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={ + "surf": [ + "protocols/coaxpress/core/rtl/CoaXPressPkg.vhd", + "protocols/coaxpress/core/rtl/CoaXPressRxWordPacker.vhd", + "protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd", + "protocols/coaxpress/core/wrappers/CoaXPressRxHsFsmWrapper.vhd", + ] + }, + ) diff --git a/tests/protocols/coaxpress/test_CoaXPressRxLane.py b/tests/protocols/coaxpress/test_CoaXPressRxLane.py new file mode 100644 index 0000000000..a8aa9870c2 --- /dev/null +++ b/tests/protocols/coaxpress/test_CoaXPressRxLane.py @@ -0,0 +1,221 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Exercise the receive-lane decoder directly without a generic sweep +# because the bug-prone surface is its packet-state logic rather than a set +# of static parameters. +# - Stimulus: Drive raw CoaXPress words for stream, control-ack, event-ack, +# heartbeat, malformed-field, and link-drop sequences, including an `IO_ACK` +# interruption in the middle of a stream packet. +# - Checks: The lane must emit the right config/data/heartbeat payloads, pulse +# `ioAck` and `eventAck` at the correct points, preserve payload `TUSER` +# bits, and reset cleanly after malformed packets or `rxLinkUp` loss. +# - Timing: The bench samples every output pulse cycle-by-cycle because the DUT +# exposes only master-side pulse semantics with no backpressure input. + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.protocols.coaxpress.coaxpress_test_utils import ( + CXP_IDLE, + CXP_IDLE_K, + CXP_IO_ACK, + CXP_SOP, + cycle, + repeat_byte, + reset_dut, + send_rx_word, + start_clock, +) + + +@cocotb.test() +async def coaxpress_rx_lane_stream_and_io_ack_test(dut): + start_clock(dut.rxClk) + dut.rxRst.setimmediatevalue(1) + dut.rxLinkUp.setimmediatevalue(1) + dut.rxData.setimmediatevalue(CXP_IDLE) + dut.rxDataK.setimmediatevalue(CXP_IDLE_K) + await reset_dut(dut) + + data_beats: list[dict[str, int]] = [] + io_ack_pulses = 0 + + async def drive(data: int, data_k: int) -> None: + nonlocal io_ack_pulses + await send_rx_word( + dut, + data=data, + data_k=data_k, + clk=dut.rxClk, + capture=data_beats, + valid_name="dataTValid", + field_names=("dataTData", "dataTUser", "dataTLast"), + ) + io_ack_pulses += int(dut.ioAck.value) + + # Build one three-word stream packet and interrupt it with an I/O ACK + # sequence before the payload starts to prove the saved-state path. + await drive(CXP_SOP, 0xF) + await drive(repeat_byte(0x01), 0x0) + await drive(repeat_byte(0x22), 0x0) + await drive(repeat_byte(0x33), 0x0) + await drive(repeat_byte(0x00), 0x0) + await drive(repeat_byte(0x03), 0x0) + await drive(CXP_IO_ACK, 0xF) + await drive(repeat_byte(0x01), 0x0) + await drive(0x11223344, 0x0) + await drive(0x55667788, 0x5) + await drive(0x99AABBCC, 0x0) + await drive(CXP_IDLE, CXP_IDLE_K) + + assert io_ack_pulses == 1 + assert data_beats == [ + {"dataTData": 0x11223344, "dataTUser": 0x0, "dataTLast": 0}, + {"dataTData": 0x55667788, "dataTUser": 0x5, "dataTLast": 0}, + {"dataTData": 0x99AABBCC, "dataTUser": 0x0, "dataTLast": 1}, + ] + + +@cocotb.test() +async def coaxpress_rx_lane_control_event_and_heartbeat_test(dut): + start_clock(dut.rxClk) + dut.rxRst.setimmediatevalue(1) + dut.rxLinkUp.setimmediatevalue(1) + dut.rxData.setimmediatevalue(CXP_IDLE) + dut.rxDataK.setimmediatevalue(CXP_IDLE_K) + await reset_dut(dut) + + cfg_beats: list[dict[str, int]] = [] + heartbeat_beats: list[dict[str, int]] = [] + event_pulses: list[tuple[int, int]] = [] + + async def drive(data: int, data_k: int, *, link_up: int = 1) -> None: + await send_rx_word( + dut, + data=data, + data_k=data_k, + clk=dut.rxClk, + link_up=link_up, + ) + if int(dut.cfgTValid.value) == 1: + cfg_beats.append({"cfgTData": int(dut.cfgTData.value)}) + if int(dut.heartbeatTValid.value) == 1: + heartbeat_beats.append( + { + "heartbeatTData": int(dut.heartbeatTData.value), + "heartbeatTLast": int(dut.heartbeatTLast.value), + } + ) + if int(dut.eventAck.value) == 1: + event_pulses.append((int(dut.eventAck.value), int(dut.eventTag.value))) + + # Successful ACK without tag should zero the status field but forward data. + await drive(CXP_SOP, 0xF) + await drive(repeat_byte(0x03), 0x0) + await drive(repeat_byte(0x01), 0x0) + await drive(0xCAFEBABE, 0x0) + await drive(0x01234567, 0x0) + + # Tagged ACK should skip the tag word and preserve the non-success status. + await drive(CXP_SOP, 0xF) + await drive(repeat_byte(0x06), 0x0) + await drive(repeat_byte(0x55), 0x0) + await drive(repeat_byte(0x02), 0x0) + await drive(0xFEEDBEEF, 0x0) + await drive(0x89ABCDEF, 0x0) + + # Event ACK fires on the fifth payload word and exports the low byte. + await drive(CXP_SOP, 0xF) + await drive(repeat_byte(0x07), 0x0) + for word in (0x10, 0x11, 0x12, 0x13): + await drive(repeat_byte(word), 0x0) + await drive(repeat_byte(0x5A), 0x0) + + # Heartbeat collects 12 bytes into one terminal beat. + await drive(CXP_SOP, 0xF) + await drive(repeat_byte(0x09), 0x0) + for word in range(0x20, 0x2C): + await drive(repeat_byte(word), 0x0) + await drive(CXP_IDLE, CXP_IDLE_K) + + assert cfg_beats == [ + {"cfgTData": (0x01234567 << 32)}, + {"cfgTData": (0x89ABCDEF << 32) | 0x02020202}, + ] + assert event_pulses == [(1, 0x5A)] + assert heartbeat_beats == [ + { + "heartbeatTData": sum((word << (8 * (word - 0x20))) for word in range(0x20, 0x2C)), + "heartbeatTLast": 1, + } + ] + + +@cocotb.test() +async def coaxpress_rx_lane_error_recovery_test(dut): + start_clock(dut.rxClk) + dut.rxRst.setimmediatevalue(1) + dut.rxLinkUp.setimmediatevalue(1) + dut.rxData.setimmediatevalue(CXP_IDLE) + dut.rxDataK.setimmediatevalue(CXP_IDLE_K) + await reset_dut(dut) + + # Corrupt the packet-tag repetition field, then drop link mid-packet and + # confirm the next clean packet is the only one that produces payload. + await send_rx_word(dut, data=CXP_SOP, data_k=0xF, clk=dut.rxClk) + await send_rx_word(dut, data=repeat_byte(0x01), data_k=0x0, clk=dut.rxClk) + await send_rx_word(dut, data=repeat_byte(0x01), data_k=0x0, clk=dut.rxClk) + await send_rx_word(dut, data=0x01020304, data_k=0x0, clk=dut.rxClk) + await send_rx_word(dut, data=CXP_SOP, data_k=0xF, clk=dut.rxClk) + await send_rx_word(dut, data=repeat_byte(0x01), data_k=0x0, clk=dut.rxClk) + await send_rx_word(dut, data=repeat_byte(0x02), data_k=0x0, clk=dut.rxClk) + await send_rx_word(dut, data=repeat_byte(0x03), data_k=0x0, clk=dut.rxClk, link_up=0) + await cycle(dut.rxClk, 2) + dut.rxLinkUp.value = 1 + + observed: list[dict[str, int]] = [] + for data, data_k in ( + (CXP_SOP, 0xF), + (repeat_byte(0x01), 0x0), + (repeat_byte(0xAA), 0x0), + (repeat_byte(0xBB), 0x0), + (repeat_byte(0x00), 0x0), + (repeat_byte(0x01), 0x0), + (0x55667788, 0x0), + (CXP_IDLE, CXP_IDLE_K), + ): + await send_rx_word( + dut, + data=data, + data_k=data_k, + clk=dut.rxClk, + capture=observed, + valid_name="dataTValid", + field_names=("dataTData", "dataTLast"), + ) + + assert observed == [{"dataTData": 0x55667788, "dataTLast": 1}] + + +def test_CoaXPressRxLane(): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.coaxpressrxlanewrapper", + extra_vhdl_sources={ + "surf": [ + "protocols/coaxpress/core/rtl/CoaXPressPkg.vhd", + "protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd", + "protocols/coaxpress/core/wrappers/CoaXPressRxLaneWrapper.vhd", + ] + }, + ) diff --git a/tests/protocols/coaxpress/test_CoaXPressRxLaneMux.py b/tests/protocols/coaxpress/test_CoaXPressRxLaneMux.py new file mode 100644 index 0000000000..220aa18635 --- /dev/null +++ b/tests/protocols/coaxpress/test_CoaXPressRxLaneMux.py @@ -0,0 +1,129 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Use one three-lane wrapper configuration because the mux behavior is +# driven mainly by frame boundaries, active-lane selection, and backpressure +# rather than by a broad generic matrix. +# - Stimulus: Hold one multi-beat frame on lane 0 while single-beat frames wait +# on lanes 1 and 2, set `numOfLane` above the generic range to exercise the +# clipping path, and stall the sink on the first visible output beat. +# - Checks: The mux must keep serving the current lane until `TLAST`, clip the +# active-lane count to the instantiated maximum, propagate payload/keep/last +# unchanged, and hold the stalled output beat stable. +# - Timing: Each source beat stays asserted until the corresponding lane-ready +# bit rises, so the bench checks the mux's real accepted-handshake order. + +import cocotb +import pytest +from cocotb.triggers import RisingEdge, Timer + +from tests.common.regression_utils import env_int, parameter_case, run_surf_vhdl_test +from tests.protocols.coaxpress.coaxpress_test_utils import cycle, pack_words, reset_dut, start_clock + + +def _set_lane_inputs(dut, lane_beats, *, num_lanes: int) -> None: + lane_width = 32 * num_lanes + keep_width = 4 * num_lanes + valid = 0 + data = 0 + keep = 0 + last = 0 + for lane, beat in enumerate(lane_beats): + if beat is None: + continue + valid |= 1 << lane + data |= beat["data"] << (lane * lane_width) + keep |= beat["keep"] << (lane * keep_width) + last |= beat["last"] << lane + dut.sAxisTValid.value = valid + dut.sAxisTData.value = data + dut.sAxisTKeep.value = keep + dut.sAxisTLast.value = last + + +@cocotb.test() +async def coaxpress_rx_lane_mux_round_robin_test(dut): + num_lanes = env_int("NUM_LANES_G", default=3) + start_clock(dut.rxClk) + dut.rxRst.setimmediatevalue(1) + dut.rxFsmRst.setimmediatevalue(0) + dut.numOfLane.setimmediatevalue(7) + dut.mAxisTReady.setimmediatevalue(0) + dut.sAxisTValid.setimmediatevalue(0) + dut.sAxisTData.setimmediatevalue(0) + dut.sAxisTKeep.setimmediatevalue(0) + dut.sAxisTLast.setimmediatevalue(0) + await reset_dut(dut, reset_names=("rxRst",)) + + lane_queues = [ + [ + {"data": pack_words([0x10, 0x11, 0x12]), "keep": 0x0FFF, "last": 0}, + {"data": pack_words([0x13, 0x14, 0x15]), "keep": 0x0FFF, "last": 1}, + ], + [{"data": pack_words([0x20, 0x21, 0x22]), "keep": 0x0FFF, "last": 1}], + [{"data": pack_words([0x30, 0x31, 0x32]), "keep": 0x0FFF, "last": 1}], + ] + + observed: list[tuple[int, int, int]] = [] + held_first: tuple[int, int, int] | None = None + + for cycle_index in range(12): + current = [queue[0] if queue else None for queue in lane_queues] + _set_lane_inputs(dut, current, num_lanes=num_lanes) + dut.mAxisTReady.value = 0 if cycle_index < 2 else 1 + + await RisingEdge(dut.rxClk) + await Timer(1, unit="ns") + + ready_bits = int(dut.sAxisTReady.value) + for lane, queue in enumerate(lane_queues): + if queue and ((ready_bits >> lane) & 0x1): + queue.pop(0) + + if int(dut.mAxisTValid.value) == 1: + beat = ( + int(dut.mAxisTData.value), + int(dut.mAxisTKeep.value), + int(dut.mAxisTLast.value), + ) + if held_first is None: + held_first = beat + if cycle_index == 1: + assert beat == held_first + if int(dut.mAxisTReady.value) == 1: + observed.append(beat) + + assert held_first is not None + assert observed == [ + (pack_words([0x10, 0x11, 0x12]), 0x0FFF, 0), + (pack_words([0x13, 0x14, 0x15]), 0x0FFF, 1), + (pack_words([0x20, 0x21, 0x22]), 0x0FFF, 1), + (pack_words([0x30, 0x31, 0x32]), 0x0FFF, 1), + ] + + +PARAMETER_SWEEP = [parameter_case("three_lane", NUM_LANES_G="3")] + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +def test_CoaXPressRxLaneMux(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.coaxpressrxlanemuxwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={ + "surf": [ + "protocols/coaxpress/core/rtl/CoaXPressRxLaneMux.vhd", + "protocols/coaxpress/core/wrappers/CoaXPressRxLaneMuxWrapper.vhd", + ] + }, + ) diff --git a/tests/protocols/coaxpress/test_CoaXPressRxWordPacker.py b/tests/protocols/coaxpress/test_CoaXPressRxWordPacker.py new file mode 100644 index 0000000000..9c48d0ca32 --- /dev/null +++ b/tests/protocols/coaxpress/test_CoaXPressRxWordPacker.py @@ -0,0 +1,198 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Cover a one-lane passthrough case and a four-lane packing case so +# both the trivial path and the multi-word assembly path are exercised. +# - Stimulus: Drive sparse and offset `TKEEP` patterns, including a frame that +# spans two input beats and a reset asserted while a partial output word is +# still buffered. +# - Checks: The packed output words must preserve order, emit the expected +# `TKEEP` mask on the short final beat, and discard any partial assembly +# state across reset. +# - Timing: The bench samples the pulsed master-only output after every clock +# edge while continuing to drive one input beat per cycle. + +import cocotb +import pytest + +from tests.common.regression_utils import env_int, parameter_case, run_surf_vhdl_test +from tests.protocols.coaxpress.coaxpress_test_utils import ( + AxisBeat, + collect_pulses, + cycle, + keep_for_words, + pack_words, + reset_dut, + send_axis_beats_no_ready, + start_clock, +) + + +@cocotb.test() +async def coaxpress_rx_word_packer_repack_test(dut): + num_lanes = env_int("NUM_LANES_G", default=1) + start_clock(dut.rxClk) + dut.rxRst.setimmediatevalue(1) + dut.sAxisTValid.setimmediatevalue(0) + dut.sAxisTData.setimmediatevalue(0) + dut.sAxisTKeep.setimmediatevalue(0) + dut.sAxisTLast.setimmediatevalue(0) + await reset_dut(dut) + + observed: list[dict[str, int]] = [] + + if num_lanes == 1: + # The one-lane case should behave like a direct passthrough. + await send_axis_beats_no_ready( + dut, + beats=[ + AxisBeat(data=0x11223344, keep=0xF, last=0), + AxisBeat(data=0x55667788, keep=0xF, last=1), + ], + clk=dut.rxClk, + capture=observed, + valid_name="mAxisTValid", + field_names=("mAxisTData", "mAxisTKeep", "mAxisTLast"), + ) + observed.extend( + await collect_pulses( + dut, + clk=dut.rxClk, + cycles=4, + valid_name="mAxisTValid", + field_names=("mAxisTData", "mAxisTKeep", "mAxisTLast"), + ) + ) + assert observed == [ + {"mAxisTData": 0x11223344, "mAxisTKeep": 0xF, "mAxisTLast": 0}, + {"mAxisTData": 0x55667788, "mAxisTKeep": 0xF, "mAxisTLast": 1}, + ] + return + + # The wider case intentionally starts on lane 1, fills one output beat, + # then spills into a short final beat on the next cycle. + await send_axis_beats_no_ready( + dut, + beats=[ + AxisBeat( + data=pack_words([0x0, 0xAAA00001, 0xBBB00002, 0xCCC00003]), + keep=0xFFF0, + last=0, + ), + AxisBeat( + data=pack_words([0xDDD00004, 0xEEE00005, 0xFFF00006]), + keep=0x0FFF, + last=1, + ), + ], + clk=dut.rxClk, + capture=observed, + valid_name="mAxisTValid", + field_names=("mAxisTData", "mAxisTKeep", "mAxisTLast"), + ) + observed.extend( + await collect_pulses( + dut, + clk=dut.rxClk, + cycles=6, + valid_name="mAxisTValid", + field_names=("mAxisTData", "mAxisTKeep", "mAxisTLast"), + ) + ) + + assert observed == [ + { + "mAxisTData": pack_words([0xAAA00001, 0xBBB00002, 0xCCC00003, 0xDDD00004]), + "mAxisTKeep": keep_for_words(4), + "mAxisTLast": 0, + }, + { + "mAxisTData": pack_words([0xEEE00005, 0xFFF00006]), + "mAxisTKeep": keep_for_words(2), + "mAxisTLast": 1, + }, + ] + + +@cocotb.test() +async def coaxpress_rx_word_packer_reset_flush_test(dut): + num_lanes = env_int("NUM_LANES_G", default=1) + start_clock(dut.rxClk) + dut.rxRst.setimmediatevalue(1) + dut.sAxisTValid.setimmediatevalue(0) + dut.sAxisTData.setimmediatevalue(0) + dut.sAxisTKeep.setimmediatevalue(0) + dut.sAxisTLast.setimmediatevalue(0) + await reset_dut(dut) + + if num_lanes == 1: + return + + # Leave a half-full packed word buffered, then reset and confirm the next + # frame starts cleanly rather than draining stale payload. + await send_axis_beats_no_ready( + dut, + beats=[AxisBeat(data=pack_words([0x11111111, 0x22222222]), keep=0x00FF, last=0)], + clk=dut.rxClk, + ) + dut.rxRst.value = 1 + await cycle(dut.rxClk, 2) + dut.rxRst.value = 0 + await cycle(dut.rxClk, 2) + + observed: list[dict[str, int]] = [] + await send_axis_beats_no_ready( + dut, + beats=[AxisBeat(data=pack_words([0xABCDEF01]), keep=0x000F, last=1)], + clk=dut.rxClk, + capture=observed, + valid_name="mAxisTValid", + field_names=("mAxisTData", "mAxisTKeep", "mAxisTLast"), + ) + observed.extend( + await collect_pulses( + dut, + clk=dut.rxClk, + cycles=4, + valid_name="mAxisTValid", + field_names=("mAxisTData", "mAxisTKeep", "mAxisTLast"), + ) + ) + + assert observed == [ + { + "mAxisTData": 0xABCDEF01, + "mAxisTKeep": keep_for_words(1), + "mAxisTLast": 1, + } + ] + + +PARAMETER_SWEEP = [ + parameter_case("single_lane", NUM_LANES_G="1"), + parameter_case("four_lane", NUM_LANES_G="4"), +] + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +def test_CoaXPressRxWordPacker(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.coaxpressrxwordpackerwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={ + "surf": [ + "protocols/coaxpress/core/rtl/CoaXPressRxWordPacker.vhd", + "protocols/coaxpress/core/wrappers/CoaXPressRxWordPackerWrapper.vhd", + ] + }, + ) From dac4c0bc54ab3b304f0797e8b5bbfec371468b45 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 20 Apr 2026 10:41:08 -0700 Subject: [PATCH 27/92] Match constants and things to the spec. --- docs/_meta/rtl_regression_handoff.md | 2 ++ docs/_meta/rtl_regression_plan.md | 8 +++++++ docs/_meta/rtl_regression_progress.md | 4 +++- .../coaxpress/coaxpress_test_utils.py | 21 ++++++++++++++++ .../coaxpress/test_CoaXPressRxHsFsm.py | 19 ++++++++------- .../coaxpress/test_CoaXPressRxLane.py | 24 ++++++++++++------- 6 files changed, 60 insertions(+), 18 deletions(-) diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index 56a16700ff..be5b160482 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -25,6 +25,7 @@ - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core` remain untouched in phase 1, while the remaining RoCEv2 gap is the mixed-language bench path for the five RTL entities that instantiate generated submodules: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`. - `EthMacRxImportXlgmii` and `EthMacTxExportXlgmii` are still placeholder no-op RTL; the checked-in tests now lock down that inert contract instead of claiming functional XLGMII support. - The CoaXPress first pass is currently receive-only. The obvious next pure-VHDL gaps are `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressTx`, `CoaXPressRx`, `CoaXPressConfig`, `CoaXPressCore`, and the over-fiber bridge trio. The current `CoaXPressRxHsFsm` bench intentionally stays on the stable one-lane path, so deeper multi-lane stepping/alignment behavior remains open. + - For future CoaXPress work, treat the named packet classes and control bytes in `tests/protocols/coaxpress/coaxpress_test_utils.py` as shared spec anchors, not as optional local style. Those constants were normalized against the same `CXP-001-2021` / `CXPR-008-2021` references cited in `CoaXPressPkg.vhd`. - Current planning discipline: - Use manual user-directed area selection as the active source of truth for what to work on next. - Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the actual validated branch frontier. @@ -66,6 +67,7 @@ - `tests/ethernet/IpV4Engine/ipv4_test_utils.py` is now the shared home for the IPv4 slice: packet/header builders and common cocotb bench setup for the `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, and `IpV4Engine*` wrappers. Reuse it instead of cloning IPv4 framing helpers across that directory. - `tests/protocols/ssi/ssi_test_utils.py` is the shared home for SSI transaction work: flat SSI endpoints, beat/frame helpers, contiguous-frame send, receive/no-output utilities, and `SOF`/`EOFE`-aware assertions. Use it instead of open-coding SSI handshake loops or terminal-flag checks. - `tests/protocols/coaxpress/coaxpress_test_utils.py` is now the shared home for the CoaXPress receive slice: protocol constants, repeated-byte word builders, wide-word packing helpers, basic clock/reset helpers, and simple pulse-capture utilities for the raw-word wrappers. Reuse it instead of cloning CoaXPress symbol constants or one-cycle output capture loops across future CoaXPress benches. +- Keep future CoaXPress benches explicit about the boundary between normative spec behavior and current RTL-contract-only coverage. For top-level and over-fiber work in particular, the governing references are the CoaXPress protocol spec (`CXP-001-2021`) and the CoaXPress-over-Fiber bridge spec (`CXPR-008-2021`); use the shared helper names for packet classes and control symbols instead of sprinkling raw byte literals through new tests. - Across the AXI slices, prefer the subsystem helper paths that already exist for register transactions, frame movement, and setup. In practice that means reusing helpers such as `tests/common/regression_utils.py`, the AXI/ethernet subsystem utility modules, and any nearby module-family helpers before inventing a one-off local transaction wrapper. - The current `EthMacCore` slice is intentionally a checked-in-wrapper-first rollout, not a cocotb-generated-wrapper experiment. Keep new Ethernet work on that same pattern unless the simulator forces a very local generic adapter. - The XGMII import/export loopback behavior differs from the GMII path when `phyReady` drops mid-traffic: the blocked frame is retained and drains after link recovery, padded to Ethernet's minimum frame size if it was short. The GMII path drops that blocked frame. Future import/export coverage should preserve that distinction instead of forcing one common expectation. diff --git a/docs/_meta/rtl_regression_plan.md b/docs/_meta/rtl_regression_plan.md index 109e162eaa..7dfc8e7fc8 100644 --- a/docs/_meta/rtl_regression_plan.md +++ b/docs/_meta/rtl_regression_plan.md @@ -104,6 +104,14 @@ - The active planning driver is now manual user-directed area selection, with `docs/_meta/rtl_regression_progress.md` and `docs/_meta/rtl_regression_handoff.md` tracking what is done, what is intentionally narrow, and what remains open. - Do not hand-maintain queue order in this plan. If the graph or queue is regenerated for analysis, treat it as secondary context unless the user explicitly switches back to queue-driven planning. +## CoaXPress Spec Discipline +- Treat the published CoaXPress specifications as normative for future `protocols/coaxpress/` work, especially for top-level receive/transmit and over-fiber bridge benches. +- The two governing references are the CoaXPress protocol spec (`CXP-001-2021`) and the CoaXPress-over-Fiber bridge spec (`CXPR-008-2021`), matching the links already called out in `protocols/coaxpress/core/rtl/CoaXPressPkg.vhd`. +- When a CoaXPress bench encodes packet classes, control symbols, or bridge control characters, derive those values from the spec-defined names first and mirror them through shared helpers such as `tests/protocols/coaxpress/coaxpress_test_utils.py` instead of scattering raw literals. +- For CoaXPress image/header benches, keep the repeated-byte field encoding, header field order, endianness conversion, line-size semantics, and end-of-frame rules explicitly tied to the spec-defined rectangular image packet layout. +- For CoaXPress-over-Fiber benches, keep `/I/`, `/Q/`, `/S/`, `/T/`, and `/E/` handling, lane-0-only start/sequence semantics, and payload-vs-housekeeping start words aligned to `CXPR-008-2021`. +- If a checked-in bench intentionally validates only the current RTL contract instead of the full normative spec behavior, document that narrowed scope explicitly in the progress and handoff docs rather than implying full spec coverage. + ## Historical Queue Artifacts The phase-1 simulator-friendly queue remains available as a generated bottom-up artifact, but it is now historical context rather than the active workflow. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 0108735146..e25967c4ec 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -24,11 +24,13 @@ - CoaXPress RTL target matrix: - Covered now under the current GHDL-only flow: `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, `CoaXPressRxHsFsm` - Still open in the same pure-VHDL family: `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressTx`, `CoaXPressRx`, `CoaXPressConfig`, `CoaXPressCore`, `CoaXPressOverFiberBridgeRx`, `CoaXPressOverFiberBridgeTx`, and `CoaXPressOverFiberBridge` + - Spec discipline for this family: use the packet/control naming and byte values from `CXP-001-2021` and `CXPR-008-2021` via shared helpers, and keep future top-level/bridge benches explicit about whether they are proving normative spec behavior or only the currently validated RTL subset. - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. - For `ethernet`, keep using the checked-in wrappers under `ethernet/*/wrappers/` plus the shared helper layers in `tests/ethernet/EthMacCore/ethmac_test_utils.py`, `tests/ethernet/RawEthFramer/raw_eth_test_utils.py`, `tests/ethernet/UdpEngine/udp_test_utils.py`, and `tests/ethernet/IpV4Engine/ipv4_test_utils.py`. The practical first-pass shape is flat EMAC/app beat wrappers with explicit sideband bits, curated functional slices instead of exhaustive generic sweeps, and dedicated pair/integration wrappers only where an old VHDL bench contributes a topology worth preserving. - For `protocols/coaxpress`, the practical first-pass shape is subsystem-local wrappers under `protocols/coaxpress/core/wrappers/` plus a small helper layer in `tests/protocols/coaxpress/coaxpress_test_utils.py`. Keep the input side raw and cycle-native where the DUT already consumes protocol words directly, and only flatten the observable AXI-stream outputs or handshaked lane arrays that cocotb actually needs to inspect. + - The checked-in CoaXPress helper now carries named spec constants for packet classes and bridge control characters. Reuse those names instead of introducing more raw `0x01`/`0x02`/`0x07`-style literals in future benches. ## Status | Subsystem | Inventory | Smoke | Functional | Notes | @@ -37,7 +39,7 @@ | `base` | started | not started | started | Validated low-level regressions now exist for `FifoAsync`, `FifoSync`, `FifoOutputPipeline`, `FifoWrFsm`, `FifoRdFsm`, `Fifo`, `FifoCascade`, `FifoMux`, `Synchronizer`, `SynchronizerVector`, `SynchronizerEdge`, `SynchronizerOneShot`, `SynchronizerFifo`, `SynchronizerOneShotCnt`, `SynchronizerOneShotVector`, `SynchronizerOneShotCntVector`, `SyncStatusVector`, `SyncTrigPeriod`, `SyncMinMax`, `SyncClockFreq`, `SyncTrigRate`, `SyncTrigRateVector`, `RstSync`, `RstPipeline`, `RstPipelineVector`, `PwrUpRst`, `Arbiter`, `ClockDivider`, `Debouncer`, `Gearbox`, `AsyncGearbox`, `Heartbeat`, `Mux`, `OneShot`, `RegisterVector`, `WatchDogRst`, `Scrambler`, `MasterRamIpIntegrator`, `SlaveRamIpIntegrator`, `SimpleDualPortRam`, `DualPortRam`, `TrueDualPortRam`, `LutRam`, `SlvDelay`, `SlvFixedDelay`, `SlvDelayRam`, `SlvDelayFifo`, `Crc32Parallel`, `Crc32`, and `CRC32Rtl` under subsystem-organized `tests/base/` packages. Remaining uncovered `base/` entities are vendor-heavy, dummy-backed, or `LutFixedDelay`, which is deferred because it depends on `SinglePortRamPrimitive`. | | `dsp` | started | not started | started | The planned `dsp/generic/fixed` leaf batch is now validated under `tests/dsp/generic/`: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. Shared DSP helpers now live in `tests/dsp/generic/dsp_test_utils.py`, and the legacy VHDL benches under `dsp/generic/tb/` were treated as behavioral reference material rather than as execution constraints. | | `axi` | started | not started | started | The axi-first pass is now complete for the simulator-friendly queue. The final locally validated batch adds `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`, with a combined `11 passed` validation run on 2026-03-27. Added checked-in subsystem wrappers under `axi/axi4/ip_integrator/`, `axi/axi-lite/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/` for those benches. `AxiStreamFifoV2` now has an expanded `10 passed` wrapper regression under `tests/axi/axi_stream/` covering async and sync width conversion, metadata truncation, `VALID_THOLD` frame-ready and burst-release modes, dynamic pause-threshold behavior, `CASCADE_SIZE=2`, and the `S_HAS_TREADY=0` pause-only source-side path. `AxiResize` now passes its equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` wrapper regression on this branch after the read-hold RTL fix. `AxiLiteAsync`, `AxiLiteToDrp`, and `AxiRateGen` still keep intentionally narrow common-clock subsets while the more timing-sensitive async AXI-Lite crossing branches remain open. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` still keep intentionally narrow first-pass subsets. `AxiStreamDmaV2Read` is now validated with a two-case wrapper regression covering both aligned and short terminal-beat reads after fixing bounded byte-count conversion in `AxiPkg` and terminal-mask generation in `AxiStreamDmaV2Read`. | -| `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. `protocols/coaxpress/` now has a first receive-path wave under `tests/protocols/coaxpress/` backed by checked-in wrappers in `protocols/coaxpress/core/wrappers/`: `CoaXPressRxWordPacker` covers offset-start packing and reset flush, `CoaXPressRxLaneMux` covers lane clipping plus frame-boundary rotation under backpressure, `CoaXPressRxLane` covers stream/config/event/heartbeat decode plus mid-packet `IO_ACK` and link-drop recovery, and `CoaXPressRxHsFsm` covers rectangular-header packing, two-line image framing, and malformed-header recovery. The current CoaXPress subset is intentionally narrow: it focuses on the pure-VHDL receive path, keeps the `CoaXPressRxHsFsm` wrapper on the stable one-lane path for now, and leaves the transmit, top-level, and over-fiber bridge blocks for a follow-on pass. | +| `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. `protocols/coaxpress/` now has a first receive-path wave under `tests/protocols/coaxpress/` backed by checked-in wrappers in `protocols/coaxpress/core/wrappers/`: `CoaXPressRxWordPacker` covers offset-start packing and reset flush, `CoaXPressRxLaneMux` covers lane clipping plus frame-boundary rotation under backpressure, `CoaXPressRxLane` covers stream/config/event/heartbeat decode plus mid-packet `IO_ACK` and link-drop recovery, and `CoaXPressRxHsFsm` covers rectangular-header packing, two-line image framing, and malformed-header recovery. The current CoaXPress subset is intentionally narrow: it focuses on the pure-VHDL receive path, keeps the `CoaXPressRxHsFsm` wrapper on the stable one-lane path for now, normalizes the checked-in packet-type literals onto named spec constants in `tests/protocols/coaxpress/coaxpress_test_utils.py`, and leaves the transmit, top-level, and over-fiber bridge blocks for a follow-on pass. | | `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers both the original leaf slice and the deeper assembly benches for `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`, plus direct `EthMacRxBypass` / `EthMacTxBypass` leaf benches and import/export sweeps that now explicitly include the current placeholder `XLGMII` contract. `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, including the successful multi-beat `RawEthFramerTx` unicast-forwarding path after lookup resolution. `tests/ethernet/UdpEngine/` covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, with the top/wrapper benches now widened across client/server routing paths. `tests/ethernet/IpV4Engine/` covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, and the top/leaf benches now also include protocol-TX and deeper ICMP reject/recovery coverage. `tests/ethernet/RoCEv2/` currently covers the pure-VHDL RTL entities `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator` through checked-in wrappers under `ethernet/RoCEv2/wrappers/`. The remaining RoCEv2 RTL entities that still need cocotb benches are `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`, and those should use the real generated `blue-*` dependencies rather than local stand-ins. The explicit Ethernet caveats are now the larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core`, the mixed-language RoCEv2 bench gap listed above, plus the still-placeholder `EthMac*Xlgmii` RTL. | | `devices` | not started | not started | not started | Many vendor-heavy cases | | `xilinx` | not started | not started | not started | Many vendor-heavy cases | diff --git a/tests/protocols/coaxpress/coaxpress_test_utils.py b/tests/protocols/coaxpress/coaxpress_test_utils.py index ade19b2257..b728c0190f 100644 --- a/tests/protocols/coaxpress/coaxpress_test_utils.py +++ b/tests/protocols/coaxpress/coaxpress_test_utils.py @@ -20,9 +20,30 @@ CXP_IDLE = 0xB53C3CBC CXP_IDLE_K = 0x7 CXP_SOP = 0xFBFBFBFB +CXP_EOP = 0xFDFDFDFD +CXP_TRIG = 0x5C5C5C5C CXP_MARKER = 0x7C7C7C7C CXP_IO_ACK = 0xDCDCDCDC +# Spec-defined CoaXPress packet-class bytes. Keep benches on these names so +# future top-level coverage stays tied to the published packet classes. +CXP_PKT_STREAM_DATA = 0x01 +CXP_PKT_IMAGE_HEADER = 0x01 +CXP_PKT_IMAGE_LINE = 0x02 +CXP_PKT_CTRL_ACK_NO_TAG = 0x03 +CXP_ACK_SUCCESS = 0x01 +CXP_ACK_SUCCESS_ALT = 0x04 +CXP_PKT_CTRL_ACK_WITH_TAG = 0x06 +CXP_PKT_EVENT_ACK = 0x07 +CXP_PKT_HEARTBEAT = 0x09 + +# CoaXPress-over-Fiber bridge control bytes. +CXPOF_IDLE = 0x07 +CXPOF_SEQ = 0x9C +CXPOF_START = 0xFB +CXPOF_TERM = 0xFD +CXPOF_ERROR = 0xFE + @dataclass class AxisBeat: diff --git a/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py b/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py index 3241648f80..7cb846a8e6 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py +++ b/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py @@ -14,9 +14,10 @@ # multi-lane timing branches are added. # - Stimulus: Drive a complete rectangular-image transaction with two lines, # then a malformed header followed by a clean retry. -# - Checks: The FSM must emit the byte-swapped packed header, forward the exact -# programmed number of data words, assert frame `TLAST` only on the final -# line, and recover cleanly after a malformed repeated-byte header word. +# - Checks: The FSM must emit the packed rectangular-image header in the same +# field order the RTL exports from the spec-defined repeated-byte header, +# forward the exact programmed number of data words, assert frame `TLAST` +# only on the final line, and recover cleanly after a malformed header word. # - Timing: The source holds each beat until `sAxisTReady` rises so the checks # reflect the FSM's actual per-beat acceptance rather than idealized traffic. @@ -27,6 +28,8 @@ from tests.common.regression_utils import parameter_case, run_surf_vhdl_test from tests.protocols.coaxpress.coaxpress_test_utils import ( CXP_MARKER, + CXP_PKT_IMAGE_HEADER, + CXP_PKT_IMAGE_LINE, cycle, pack_words, repeat_byte, @@ -128,7 +131,7 @@ async def coaxpress_rx_hs_fsm_header_and_lines_test(dut): # Send one header packet that declares two lines of three 32-bit words. await _send_handshaked_beat(dut, data=CXP_MARKER, keep=0xF) _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) - await _send_handshaked_beat(dut, data=repeat_byte(0x01), keep=0xF) + await _send_handshaked_beat(dut, data=repeat_byte(CXP_PKT_IMAGE_HEADER), keep=0xF) _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) for word in _header_words(): await _send_handshaked_beat(dut, data=word, keep=0xF) @@ -138,7 +141,7 @@ async def coaxpress_rx_hs_fsm_header_and_lines_test(dut): for line_words in ([0x11111111, 0x22222222, 0x33333333], [0x44444444, 0x55555555, 0x66666666]): await _send_handshaked_beat(dut, data=CXP_MARKER, keep=0xF) _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) - await _send_handshaked_beat(dut, data=repeat_byte(0x02), keep=0xF) + await _send_handshaked_beat(dut, data=repeat_byte(CXP_PKT_IMAGE_LINE), keep=0xF) _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) for word in line_words: await _send_handshaked_beat(dut, data=word, keep=0xF) @@ -180,7 +183,7 @@ async def coaxpress_rx_hs_fsm_malformed_header_recovery_test(dut): # actually emits the header/data outputs. await _send_handshaked_beat(dut, data=CXP_MARKER, keep=0xF) error_seen |= int(dut.rxFsmError.value) == 1 - await _send_handshaked_beat(dut, data=repeat_byte(0x01), keep=0xF) + await _send_handshaked_beat(dut, data=repeat_byte(CXP_PKT_IMAGE_HEADER), keep=0xF) error_seen |= int(dut.rxFsmError.value) == 1 for index, word in enumerate(_header_words()): await _send_handshaked_beat( @@ -197,14 +200,14 @@ async def coaxpress_rx_hs_fsm_malformed_header_recovery_test(dut): await _send_handshaked_beat(dut, data=CXP_MARKER, keep=0xF) _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) - await _send_handshaked_beat(dut, data=repeat_byte(0x01), keep=0xF) + await _send_handshaked_beat(dut, data=repeat_byte(CXP_PKT_IMAGE_HEADER), keep=0xF) _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) for word in _header_words(): await _send_handshaked_beat(dut, data=word, keep=0xF) _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) await _send_handshaked_beat(dut, data=CXP_MARKER, keep=0xF) _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) - await _send_handshaked_beat(dut, data=repeat_byte(0x02), keep=0xF) + await _send_handshaked_beat(dut, data=repeat_byte(CXP_PKT_IMAGE_LINE), keep=0xF) _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) await _send_handshaked_beat(dut, data=0xABCDEF00, keep=0xF) _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) diff --git a/tests/protocols/coaxpress/test_CoaXPressRxLane.py b/tests/protocols/coaxpress/test_CoaXPressRxLane.py index a8aa9870c2..f39ba0bb55 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRxLane.py +++ b/tests/protocols/coaxpress/test_CoaXPressRxLane.py @@ -26,9 +26,15 @@ from tests.common.regression_utils import run_surf_vhdl_test from tests.protocols.coaxpress.coaxpress_test_utils import ( + CXP_ACK_SUCCESS, CXP_IDLE, CXP_IDLE_K, CXP_IO_ACK, + CXP_PKT_CTRL_ACK_NO_TAG, + CXP_PKT_CTRL_ACK_WITH_TAG, + CXP_PKT_EVENT_ACK, + CXP_PKT_HEARTBEAT, + CXP_PKT_STREAM_DATA, CXP_SOP, cycle, repeat_byte, @@ -66,7 +72,7 @@ async def drive(data: int, data_k: int) -> None: # Build one three-word stream packet and interrupt it with an I/O ACK # sequence before the payload starts to prove the saved-state path. await drive(CXP_SOP, 0xF) - await drive(repeat_byte(0x01), 0x0) + await drive(repeat_byte(CXP_PKT_STREAM_DATA), 0x0) await drive(repeat_byte(0x22), 0x0) await drive(repeat_byte(0x33), 0x0) await drive(repeat_byte(0x00), 0x0) @@ -121,14 +127,14 @@ async def drive(data: int, data_k: int, *, link_up: int = 1) -> None: # Successful ACK without tag should zero the status field but forward data. await drive(CXP_SOP, 0xF) - await drive(repeat_byte(0x03), 0x0) - await drive(repeat_byte(0x01), 0x0) + await drive(repeat_byte(CXP_PKT_CTRL_ACK_NO_TAG), 0x0) + await drive(repeat_byte(CXP_ACK_SUCCESS), 0x0) await drive(0xCAFEBABE, 0x0) await drive(0x01234567, 0x0) # Tagged ACK should skip the tag word and preserve the non-success status. await drive(CXP_SOP, 0xF) - await drive(repeat_byte(0x06), 0x0) + await drive(repeat_byte(CXP_PKT_CTRL_ACK_WITH_TAG), 0x0) await drive(repeat_byte(0x55), 0x0) await drive(repeat_byte(0x02), 0x0) await drive(0xFEEDBEEF, 0x0) @@ -136,14 +142,14 @@ async def drive(data: int, data_k: int, *, link_up: int = 1) -> None: # Event ACK fires on the fifth payload word and exports the low byte. await drive(CXP_SOP, 0xF) - await drive(repeat_byte(0x07), 0x0) + await drive(repeat_byte(CXP_PKT_EVENT_ACK), 0x0) for word in (0x10, 0x11, 0x12, 0x13): await drive(repeat_byte(word), 0x0) await drive(repeat_byte(0x5A), 0x0) # Heartbeat collects 12 bytes into one terminal beat. await drive(CXP_SOP, 0xF) - await drive(repeat_byte(0x09), 0x0) + await drive(repeat_byte(CXP_PKT_HEARTBEAT), 0x0) for word in range(0x20, 0x2C): await drive(repeat_byte(word), 0x0) await drive(CXP_IDLE, CXP_IDLE_K) @@ -173,8 +179,8 @@ async def coaxpress_rx_lane_error_recovery_test(dut): # Corrupt the packet-tag repetition field, then drop link mid-packet and # confirm the next clean packet is the only one that produces payload. await send_rx_word(dut, data=CXP_SOP, data_k=0xF, clk=dut.rxClk) - await send_rx_word(dut, data=repeat_byte(0x01), data_k=0x0, clk=dut.rxClk) - await send_rx_word(dut, data=repeat_byte(0x01), data_k=0x0, clk=dut.rxClk) + await send_rx_word(dut, data=repeat_byte(CXP_PKT_STREAM_DATA), data_k=0x0, clk=dut.rxClk) + await send_rx_word(dut, data=repeat_byte(CXP_PKT_STREAM_DATA), data_k=0x0, clk=dut.rxClk) await send_rx_word(dut, data=0x01020304, data_k=0x0, clk=dut.rxClk) await send_rx_word(dut, data=CXP_SOP, data_k=0xF, clk=dut.rxClk) await send_rx_word(dut, data=repeat_byte(0x01), data_k=0x0, clk=dut.rxClk) @@ -186,7 +192,7 @@ async def coaxpress_rx_lane_error_recovery_test(dut): observed: list[dict[str, int]] = [] for data, data_k in ( (CXP_SOP, 0xF), - (repeat_byte(0x01), 0x0), + (repeat_byte(CXP_PKT_STREAM_DATA), 0x0), (repeat_byte(0xAA), 0x0), (repeat_byte(0xBB), 0x0), (repeat_byte(0x00), 0x0), From 3f0320370fb6f36837e69f208cf7df4427452104 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 20 Apr 2026 10:54:25 -0700 Subject: [PATCH 28/92] Coaxpress pass 2. --- docs/_meta/rtl_regression_handoff.md | 8 +- docs/_meta/rtl_regression_progress.md | 8 +- .../wrappers/CoaXPressEventAckMsgWrapper.vhd | 61 +++++++ .../core/wrappers/CoaXPressTxLsFsmWrapper.vhd | 71 ++++++++ .../coaxpress/coaxpress_test_utils.py | 12 ++ .../coaxpress/test_CoaXPressEventAckMsg.py | 146 +++++++++++++++ .../test_CoaXPressOverFiberBridgeRx.py | 105 +++++++++++ .../test_CoaXPressOverFiberBridgeTx.py | 122 +++++++++++++ .../coaxpress/test_CoaXPressTxLsFsm.py | 171 ++++++++++++++++++ 9 files changed, 696 insertions(+), 8 deletions(-) create mode 100644 protocols/coaxpress/core/wrappers/CoaXPressEventAckMsgWrapper.vhd create mode 100644 protocols/coaxpress/core/wrappers/CoaXPressTxLsFsmWrapper.vhd create mode 100644 tests/protocols/coaxpress/test_CoaXPressEventAckMsg.py create mode 100644 tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py create mode 100644 tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeTx.py create mode 100644 tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index be5b160482..9a2abf4625 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -19,12 +19,12 @@ - Treat stale simulator cleanup as part of task completion: after any `pytest`, cocotb, GHDL, or similar launched verification step, sweep for leftover child processes and kill them before moving on ## Quick Resume Snapshot -- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, the current Ethernet coverage spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the pure-VHDL RoCEv2 quartet (`EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator`), and a new user-directed CoaXPress receive-path wave is now checked in under `tests/protocols/coaxpress/`. The validated CoaXPress subset is the pure-VHDL receive quartet `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, and `CoaXPressRxHsFsm`, with subsystem-local wrappers under `protocols/coaxpress/core/wrappers/`. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. +- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, the current Ethernet coverage spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the pure-VHDL RoCEv2 quartet (`EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator`), and a broader user-directed CoaXPress pure-VHDL wave is now checked in under `tests/protocols/coaxpress/`. The validated CoaXPress subset now includes the receive quartet `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, and `CoaXPressRxHsFsm`, plus the transmit/bridge helpers `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressOverFiberBridgeRx`, and `CoaXPressOverFiberBridgeTx`, with subsystem-local wrappers under `protocols/coaxpress/core/wrappers/` where the stream-facing surfaces need flattening. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. - Current axi frontier: complete for the intended simulator-friendly pass in this branch snapshot; do not resume from the older stale `AxiResize` note. - Current validated-open issues: - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core` remain untouched in phase 1, while the remaining RoCEv2 gap is the mixed-language bench path for the five RTL entities that instantiate generated submodules: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`. - `EthMacRxImportXlgmii` and `EthMacTxExportXlgmii` are still placeholder no-op RTL; the checked-in tests now lock down that inert contract instead of claiming functional XLGMII support. - - The CoaXPress first pass is currently receive-only. The obvious next pure-VHDL gaps are `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressTx`, `CoaXPressRx`, `CoaXPressConfig`, `CoaXPressCore`, and the over-fiber bridge trio. The current `CoaXPressRxHsFsm` bench intentionally stays on the stable one-lane path, so deeper multi-lane stepping/alignment behavior remains open. + - The remaining CoaXPress pure-VHDL gaps are now the higher-level assemblies `CoaXPressTx`, `CoaXPressRx`, `CoaXPressConfig`, `CoaXPressCore`, and `CoaXPressOverFiberBridge`. The current `CoaXPressRxHsFsm` bench intentionally stays on the stable one-lane path, so deeper multi-lane stepping/alignment behavior remains open even though the surrounding pure-VHDL helper leaves are now covered. - For future CoaXPress work, treat the named packet classes and control bytes in `tests/protocols/coaxpress/coaxpress_test_utils.py` as shared spec anchors, not as optional local style. Those constants were normalized against the same `CXP-001-2021` / `CXPR-008-2021` references cited in `CoaXPressPkg.vhd`. - Current planning discipline: - Use manual user-directed area selection as the active source of truth for what to work on next. @@ -66,7 +66,7 @@ - `tests/ethernet/UdpEngine/udp_test_utils.py` is now the shared home for the UDP slice: legacy-address constants, pseudo-frame builders, DHCP option helpers, and the common cocotb bench setup for the `ArpIpTable`, `UdpEngine*`, and `UdpEngineWrapper*` wrappers. Reuse it instead of rebuilding IPv4/UDP helper glue in each test module. - `tests/ethernet/IpV4Engine/ipv4_test_utils.py` is now the shared home for the IPv4 slice: packet/header builders and common cocotb bench setup for the `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, and `IpV4Engine*` wrappers. Reuse it instead of cloning IPv4 framing helpers across that directory. - `tests/protocols/ssi/ssi_test_utils.py` is the shared home for SSI transaction work: flat SSI endpoints, beat/frame helpers, contiguous-frame send, receive/no-output utilities, and `SOF`/`EOFE`-aware assertions. Use it instead of open-coding SSI handshake loops or terminal-flag checks. -- `tests/protocols/coaxpress/coaxpress_test_utils.py` is now the shared home for the CoaXPress receive slice: protocol constants, repeated-byte word builders, wide-word packing helpers, basic clock/reset helpers, and simple pulse-capture utilities for the raw-word wrappers. Reuse it instead of cloning CoaXPress symbol constants or one-cycle output capture loops across future CoaXPress benches. +- `tests/protocols/coaxpress/coaxpress_test_utils.py` is now the shared home for the CoaXPress leaf/bridge slice: protocol constants, repeated-byte word builders, byte-splitting helpers, wide-word packing helpers, basic clock/reset helpers, and simple pulse-capture utilities for the raw-word wrappers. Reuse it instead of cloning CoaXPress symbol constants or one-cycle output capture loops across future CoaXPress benches. - Keep future CoaXPress benches explicit about the boundary between normative spec behavior and current RTL-contract-only coverage. For top-level and over-fiber work in particular, the governing references are the CoaXPress protocol spec (`CXP-001-2021`) and the CoaXPress-over-Fiber bridge spec (`CXPR-008-2021`); use the shared helper names for packet classes and control symbols instead of sprinkling raw byte literals through new tests. - Across the AXI slices, prefer the subsystem helper paths that already exist for register transactions, frame movement, and setup. In practice that means reusing helpers such as `tests/common/regression_utils.py`, the AXI/ethernet subsystem utility modules, and any nearby module-family helpers before inventing a one-off local transaction wrapper. - The current `EthMacCore` slice is intentionally a checked-in-wrapper-first rollout, not a cocotb-generated-wrapper experiment. Keep new Ethernet work on that same pattern unless the simulator forces a very local generic adapter. @@ -168,7 +168,7 @@ A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instan ## Immediate Next Task If the user keeps the focus on `protocols/coaxpress`, the next practical step is either: -1. finish the remaining pure-VHDL leaf/helper work (`CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressOverFiberBridgeRx`, `CoaXPressOverFiberBridgeTx`) before moving upward, or +1. move upward into the remaining pure-VHDL assemblies (`CoaXPressTx`, `CoaXPressRx`, and then `CoaXPressOverFiberBridge` / `CoaXPressCore`) using the now-covered helper leaves as the fixed contract surface, or 2. deepen the current receive-path benches on the intentionally open multi-lane branches (`CoaXPressRxHsFsm` stepping/alignment and then `CoaXPressRx` integration). If the user switches back to `ethernet/RoCEv2`, the next real step is still enabling a mixed-language cocotb path for the five remaining RTL entities listed above. Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the real validated subset, and do not reintroduce local stand-ins for `blue-*`. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index e25967c4ec..9d0e99cfac 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -3,7 +3,7 @@ ## Summary - Current phase: Phase-1 implementation active - Current subsystem: manual user-directed rollout tracking -- Current focus module: user-directed CoaXPress receive-path first pass under `protocols/coaxpress/core/rtl`, with validated cocotb coverage now checked in for `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, and `CoaXPressRxHsFsm`. +- Current focus module: user-directed CoaXPress pure-VHDL leaf/helper pass under `protocols/coaxpress/core/rtl`, with validated cocotb coverage now checked in for `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, `CoaXPressRxHsFsm`, `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressOverFiberBridgeRx`, and `CoaXPressOverFiberBridgeTx`. - Last updated: 2026-04-20 ## Current Frontier Snapshot @@ -22,8 +22,8 @@ - Covered now under the current GHDL-only flow: `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, `RoceConfigurator` - Still required, but need real `blue-*` dependencies under a mixed-language simulator: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, `RoceEngineWrapper` - CoaXPress RTL target matrix: - - Covered now under the current GHDL-only flow: `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, `CoaXPressRxHsFsm` - - Still open in the same pure-VHDL family: `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressTx`, `CoaXPressRx`, `CoaXPressConfig`, `CoaXPressCore`, `CoaXPressOverFiberBridgeRx`, `CoaXPressOverFiberBridgeTx`, and `CoaXPressOverFiberBridge` + - Covered now under the current GHDL-only flow: `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, `CoaXPressRxHsFsm`, `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressOverFiberBridgeRx`, and `CoaXPressOverFiberBridgeTx` + - Still open in the same pure-VHDL family: `CoaXPressTx`, `CoaXPressRx`, `CoaXPressConfig`, `CoaXPressCore`, and `CoaXPressOverFiberBridge` - Spec discipline for this family: use the packet/control naming and byte values from `CXP-001-2021` and `CXPR-008-2021` via shared helpers, and keep future top-level/bridge benches explicit about whether they are proving normative spec behavior or only the currently validated RTL subset. - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. @@ -39,7 +39,7 @@ | `base` | started | not started | started | Validated low-level regressions now exist for `FifoAsync`, `FifoSync`, `FifoOutputPipeline`, `FifoWrFsm`, `FifoRdFsm`, `Fifo`, `FifoCascade`, `FifoMux`, `Synchronizer`, `SynchronizerVector`, `SynchronizerEdge`, `SynchronizerOneShot`, `SynchronizerFifo`, `SynchronizerOneShotCnt`, `SynchronizerOneShotVector`, `SynchronizerOneShotCntVector`, `SyncStatusVector`, `SyncTrigPeriod`, `SyncMinMax`, `SyncClockFreq`, `SyncTrigRate`, `SyncTrigRateVector`, `RstSync`, `RstPipeline`, `RstPipelineVector`, `PwrUpRst`, `Arbiter`, `ClockDivider`, `Debouncer`, `Gearbox`, `AsyncGearbox`, `Heartbeat`, `Mux`, `OneShot`, `RegisterVector`, `WatchDogRst`, `Scrambler`, `MasterRamIpIntegrator`, `SlaveRamIpIntegrator`, `SimpleDualPortRam`, `DualPortRam`, `TrueDualPortRam`, `LutRam`, `SlvDelay`, `SlvFixedDelay`, `SlvDelayRam`, `SlvDelayFifo`, `Crc32Parallel`, `Crc32`, and `CRC32Rtl` under subsystem-organized `tests/base/` packages. Remaining uncovered `base/` entities are vendor-heavy, dummy-backed, or `LutFixedDelay`, which is deferred because it depends on `SinglePortRamPrimitive`. | | `dsp` | started | not started | started | The planned `dsp/generic/fixed` leaf batch is now validated under `tests/dsp/generic/`: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. Shared DSP helpers now live in `tests/dsp/generic/dsp_test_utils.py`, and the legacy VHDL benches under `dsp/generic/tb/` were treated as behavioral reference material rather than as execution constraints. | | `axi` | started | not started | started | The axi-first pass is now complete for the simulator-friendly queue. The final locally validated batch adds `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`, with a combined `11 passed` validation run on 2026-03-27. Added checked-in subsystem wrappers under `axi/axi4/ip_integrator/`, `axi/axi-lite/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/` for those benches. `AxiStreamFifoV2` now has an expanded `10 passed` wrapper regression under `tests/axi/axi_stream/` covering async and sync width conversion, metadata truncation, `VALID_THOLD` frame-ready and burst-release modes, dynamic pause-threshold behavior, `CASCADE_SIZE=2`, and the `S_HAS_TREADY=0` pause-only source-side path. `AxiResize` now passes its equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` wrapper regression on this branch after the read-hold RTL fix. `AxiLiteAsync`, `AxiLiteToDrp`, and `AxiRateGen` still keep intentionally narrow common-clock subsets while the more timing-sensitive async AXI-Lite crossing branches remain open. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` still keep intentionally narrow first-pass subsets. `AxiStreamDmaV2Read` is now validated with a two-case wrapper regression covering both aligned and short terminal-beat reads after fixing bounded byte-count conversion in `AxiPkg` and terminal-mask generation in `AxiStreamDmaV2Read`. | -| `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. `protocols/coaxpress/` now has a first receive-path wave under `tests/protocols/coaxpress/` backed by checked-in wrappers in `protocols/coaxpress/core/wrappers/`: `CoaXPressRxWordPacker` covers offset-start packing and reset flush, `CoaXPressRxLaneMux` covers lane clipping plus frame-boundary rotation under backpressure, `CoaXPressRxLane` covers stream/config/event/heartbeat decode plus mid-packet `IO_ACK` and link-drop recovery, and `CoaXPressRxHsFsm` covers rectangular-header packing, two-line image framing, and malformed-header recovery. The current CoaXPress subset is intentionally narrow: it focuses on the pure-VHDL receive path, keeps the `CoaXPressRxHsFsm` wrapper on the stable one-lane path for now, normalizes the checked-in packet-type literals onto named spec constants in `tests/protocols/coaxpress/coaxpress_test_utils.py`, and leaves the transmit, top-level, and over-fiber bridge blocks for a follow-on pass. | +| `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. `protocols/coaxpress/` now has a broader pure-VHDL leaf/helper wave under `tests/protocols/coaxpress/` backed by checked-in wrappers in `protocols/coaxpress/core/wrappers/`: the receive quartet still covers offset-start packing, lane rotation, stream/config/event/heartbeat decode, and rectangular-header framing, while the new transmit/bridge leaves add `CoaXPressEventAckMsg` serialization under backpressure, `CoaXPressTxLsFsm` idle/config/trigger cadence, `CoaXPressOverFiberBridgeTx` CXPoF start/payload/terminate formatting, and `CoaXPressOverFiberBridgeRx` CXPoF start-word decode back into CoaXPress `SOP`/type/payload/`IO_ACK`. The current CoaXPress subset remains intentionally staged: it now covers the key pure-VHDL leaves plus the bridge endpoints, keeps the `CoaXPressRxHsFsm` wrapper on the stable one-lane path, normalizes packet/control literals onto named spec constants in `tests/protocols/coaxpress/coaxpress_test_utils.py`, and leaves the higher-level `CoaXPressTx`, `CoaXPressRx`, `CoaXPressConfig`, `CoaXPressCore`, and `CoaXPressOverFiberBridge` assemblies for the next pass. | | `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers both the original leaf slice and the deeper assembly benches for `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`, plus direct `EthMacRxBypass` / `EthMacTxBypass` leaf benches and import/export sweeps that now explicitly include the current placeholder `XLGMII` contract. `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, including the successful multi-beat `RawEthFramerTx` unicast-forwarding path after lookup resolution. `tests/ethernet/UdpEngine/` covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, with the top/wrapper benches now widened across client/server routing paths. `tests/ethernet/IpV4Engine/` covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, and the top/leaf benches now also include protocol-TX and deeper ICMP reject/recovery coverage. `tests/ethernet/RoCEv2/` currently covers the pure-VHDL RTL entities `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator` through checked-in wrappers under `ethernet/RoCEv2/wrappers/`. The remaining RoCEv2 RTL entities that still need cocotb benches are `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`, and those should use the real generated `blue-*` dependencies rather than local stand-ins. The explicit Ethernet caveats are now the larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core`, the mixed-language RoCEv2 bench gap listed above, plus the still-placeholder `EthMac*Xlgmii` RTL. | | `devices` | not started | not started | not started | Many vendor-heavy cases | | `xilinx` | not started | not started | not started | Many vendor-heavy cases | diff --git a/protocols/coaxpress/core/wrappers/CoaXPressEventAckMsgWrapper.vhd b/protocols/coaxpress/core/wrappers/CoaXPressEventAckMsgWrapper.vhd new file mode 100644 index 0000000000..837829cb39 --- /dev/null +++ b/protocols/coaxpress/core/wrappers/CoaXPressEventAckMsgWrapper.vhd @@ -0,0 +1,61 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for CoaXPressEventAckMsg +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; + +entity CoaXPressEventAckMsgWrapper is + port ( + clk : in sl; + rst : in sl; + eventAck : in sl; + eventTag : in slv(7 downto 0); + eventAckTReady : in sl; + eventAckTValid : out sl; + eventAckTData : out slv(7 downto 0); + eventAckTK : out sl; + eventAckTLast : out sl); +end entity CoaXPressEventAckMsgWrapper; + +architecture rtl of CoaXPressEventAckMsgWrapper is + + signal eventAckMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal eventAckSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + +begin + + -- Flatten the byte-wide AXI stream so cocotb can monitor serialized output. + eventAckSlave.tReady <= eventAckTReady; + eventAckTValid <= eventAckMaster.tValid; + eventAckTData <= eventAckMaster.tData(7 downto 0); + eventAckTK <= eventAckMaster.tUser(0); + eventAckTLast <= eventAckMaster.tLast; + + -- Instantiate the real event-ack message generator behind the flat ports. + U_DUT : entity surf.CoaXPressEventAckMsg + generic map ( + TPD_G => 1 ns) + port map ( + clk => clk, + rst => rst, + eventAck => eventAck, + eventTag => eventTag, + eventAckMaster => eventAckMaster, + eventAckSlave => eventAckSlave); + +end architecture rtl; diff --git a/protocols/coaxpress/core/wrappers/CoaXPressTxLsFsmWrapper.vhd b/protocols/coaxpress/core/wrappers/CoaXPressTxLsFsmWrapper.vhd new file mode 100644 index 0000000000..a6dd16146a --- /dev/null +++ b/protocols/coaxpress/core/wrappers/CoaXPressTxLsFsmWrapper.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for CoaXPressTxLsFsm +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; + +entity CoaXPressTxLsFsmWrapper is + port ( + txClk : in sl; + txRst : in sl; + cfgTValid : in sl; + cfgTData : in slv(7 downto 0); + cfgTUser : in sl; + cfgTReady : out sl; + txTrig : in sl; + txTrigInv : in sl; + txPulseWidth : in slv(31 downto 0); + txRate : in sl; + txTrigDrop : out sl; + txStrobe : out sl; + txData : out slv(7 downto 0); + txDataK : out sl); +end entity CoaXPressTxLsFsmWrapper; + +architecture rtl of CoaXPressTxLsFsmWrapper is + + signal cfgMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal cfgSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + +begin + + -- Drive the DUT's byte-wide AXI-stream config input from scalar ports. + cfgMaster.tValid <= cfgTValid; + cfgMaster.tData(7 downto 0) <= cfgTData; + cfgMaster.tUser(0) <= cfgTUser; + cfgTReady <= cfgSlave.tReady; + + -- Instantiate the real low-speed transmit FSM behind the flat ports. + U_DUT : entity surf.CoaXPressTxLsFsm + generic map ( + TPD_G => 1 ns) + port map ( + txClk => txClk, + txRst => txRst, + cfgMaster => cfgMaster, + cfgSlave => cfgSlave, + txTrig => txTrig, + txTrigInv => txTrigInv, + txPulseWidth => txPulseWidth, + txTrigDrop => txTrigDrop, + txRate => txRate, + txStrobe => txStrobe, + txData => txData, + txDataK => txDataK); + +end architecture rtl; diff --git a/tests/protocols/coaxpress/coaxpress_test_utils.py b/tests/protocols/coaxpress/coaxpress_test_utils.py index b728c0190f..b51df0f483 100644 --- a/tests/protocols/coaxpress/coaxpress_test_utils.py +++ b/tests/protocols/coaxpress/coaxpress_test_utils.py @@ -35,8 +35,16 @@ CXP_ACK_SUCCESS_ALT = 0x04 CXP_PKT_CTRL_ACK_WITH_TAG = 0x06 CXP_PKT_EVENT_ACK = 0x07 +CXP_PKT_EVENT_ACK_MSG = 0x08 CXP_PKT_HEARTBEAT = 0x09 +# Low-speed symbol bytes used directly by the TX-side CoaXPress logic. +CXP_K28_1 = 0x3C +CXP_K28_2 = 0x5C +CXP_K28_4 = 0x9C +CXP_K28_5 = 0xBC +CXP_D21_5 = 0xB5 + # CoaXPress-over-Fiber bridge control bytes. CXPOF_IDLE = 0x07 CXPOF_SEQ = 0x9C @@ -58,6 +66,10 @@ def repeat_byte(value: int) -> int: return byte | (byte << 8) | (byte << 16) | (byte << 24) +def word_to_bytes(word: int, *, byte_count: int = 4) -> list[int]: + return [(word >> (8 * index)) & 0xFF for index in range(byte_count)] + + def pack_words(words: list[int], *, word_bits: int = 32) -> int: mask = (1 << word_bits) - 1 value = 0 diff --git a/tests/protocols/coaxpress/test_CoaXPressEventAckMsg.py b/tests/protocols/coaxpress/test_CoaXPressEventAckMsg.py new file mode 100644 index 0000000000..7f5a8315e0 --- /dev/null +++ b/tests/protocols/coaxpress/test_CoaXPressEventAckMsg.py @@ -0,0 +1,146 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Exercise the event-ack serializer directly with two event tags so +# the bench checks both the initial transfer and a second post-idle retry. +# - Stimulus: Pulse `eventAck`, hold `TREADY` low across the first serialized +# byte to create backpressure, then release the sink and repeat with a second +# tag while the sink stays ready. +# - Checks: The DUT must serialize the CoaXPress event-ack message as +# `SOP`, type `0x08`, repeated event tag, and `EOP`, preserve the K/data +# classification on each byte, assert `TLAST` only on the final byte, and +# hold the stalled first byte stable under backpressure. +# - Timing: The bench samples the byte output cycle-by-cycle and records only +# accepted handshakes once `TREADY` is asserted. + +import cocotb +from cocotb.triggers import RisingEdge, Timer + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.protocols.coaxpress.coaxpress_test_utils import ( + CXP_EOP, + CXP_PKT_EVENT_ACK_MSG, + CXP_SOP, + cycle, + repeat_byte, + reset_dut, + start_clock, + word_to_bytes, +) + + +def _expected_event_ack_bytes(tag: int) -> list[tuple[int, int, int]]: + expected: list[tuple[int, int, int]] = [] + for word, is_k in ( + (CXP_SOP, 1), + (repeat_byte(CXP_PKT_EVENT_ACK_MSG), 0), + (repeat_byte(tag), 0), + (CXP_EOP, 1), + ): + for byte in word_to_bytes(word): + expected.append((byte, is_k, 0)) + expected[-1] = (expected[-1][0], expected[-1][1], 1) + return expected + + +async def _pulse_event_ack(dut, tag: int) -> None: + dut.eventTag.value = tag + dut.eventAck.value = 1 + await RisingEdge(dut.clk) + await Timer(1, unit="ns") + dut.eventAck.value = 0 + + +async def _collect_handshakes(dut, *, count: int, timeout_cycles: int) -> list[tuple[int, int, int]]: + observed: list[tuple[int, int, int]] = [] + for _ in range(timeout_cycles): + await RisingEdge(dut.clk) + await Timer(1, unit="ns") + if int(dut.eventAckTValid.value) == 1 and int(dut.eventAckTReady.value) == 1: + observed.append( + ( + int(dut.eventAckTData.value), + int(dut.eventAckTK.value), + int(dut.eventAckTLast.value), + ) + ) + if len(observed) == count: + return observed + raise AssertionError(f"Timed out waiting for {count} accepted bytes, saw {len(observed)}") + + +@cocotb.test() +async def coaxpress_event_ack_msg_serialize_and_backpressure_test(dut): + # Bring the serializer into a known idle state before driving any pulses. + start_clock(dut.clk) + dut.rst.setimmediatevalue(1) + dut.eventAck.setimmediatevalue(0) + dut.eventTag.setimmediatevalue(0) + dut.eventAckTReady.setimmediatevalue(0) + await reset_dut(dut, clk_name="clk", reset_names=("rst",)) + + # Create one event-ack request while the sink is stalled so the first byte + # must remain stable until `TREADY` is released. + await _pulse_event_ack(dut, 0x5A) + + stalled_byte = None + for _ in range(8): + await RisingEdge(dut.clk) + await Timer(1, unit="ns") + if int(dut.eventAckTValid.value) == 1: + sample = ( + int(dut.eventAckTData.value), + int(dut.eventAckTK.value), + int(dut.eventAckTLast.value), + ) + if stalled_byte is None: + stalled_byte = sample + else: + assert sample == stalled_byte + break + assert stalled_byte == (word_to_bytes(CXP_SOP)[0], 1, 0) + + for _ in range(2): + await RisingEdge(dut.clk) + await Timer(1, unit="ns") + assert ( + int(dut.eventAckTData.value), + int(dut.eventAckTK.value), + int(dut.eventAckTLast.value), + ) == stalled_byte + + # Release the sink and collect the full serialized message on accepted + # handshakes only. + dut.eventAckTReady.value = 1 + first_transfer = await _collect_handshakes(dut, count=16, timeout_cycles=40) + assert first_transfer[0] == stalled_byte + + # A second idle-to-active transition should emit the next tag cleanly. + await cycle(dut.clk, 4) + await _pulse_event_ack(dut, 0xA5) + second_transfer = await _collect_handshakes(dut, count=16, timeout_cycles=40) + + assert first_transfer == _expected_event_ack_bytes(0x5A) + assert second_transfer == _expected_event_ack_bytes(0xA5) + + +def test_CoaXPressEventAckMsg(): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.coaxpresseventackmsgwrapper", + extra_vhdl_sources={ + "surf": [ + "protocols/coaxpress/core/rtl/CoaXPressPkg.vhd", + "protocols/coaxpress/core/rtl/CoaXPressEventAckMsg.vhd", + "protocols/coaxpress/core/wrappers/CoaXPressEventAckMsgWrapper.vhd", + ] + }, + ) diff --git a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py new file mode 100644 index 0000000000..e3aeb541bc --- /dev/null +++ b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py @@ -0,0 +1,105 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Exercise the bridge RX on the two CoaXPress receive-side cases the +# current RTL decodes explicitly from the start word: normal low-speed +# packets and `IO_ACK`. +# - Stimulus: Drive one CXPoF start/payload/terminate sequence that encodes a +# serialized CoaXPress packet, then drive a separate start/terminate sequence +# that encodes an `IO_ACK`. +# - Checks: The bridge must reconstruct the repeated-byte `SOP`, packet-type, +# payload, and `EOP` words for the first packet, emit the standalone +# `IO_ACK` word for the second packet, and otherwise remain in the CoaXPress +# idle state. +# - Timing: The bench samples the reconstructed CXP word stream every cycle so +# it checks the bridge's real shift-register latency and output ordering. + +import cocotb + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.protocols.coaxpress.coaxpress_test_utils import ( + CXP_EOP, + CXP_IDLE, + CXP_IDLE_K, + CXP_IO_ACK, + CXP_PKT_EVENT_ACK_MSG, + CXP_SOP, + CXPOF_START, + cycle, + repeat_byte, + reset_dut, + start_clock, +) + + +def _cxp_start_word(packet_byte: int) -> int: + return CXPOF_START | (0x80 << 8) | ((CXP_SOP & 0xFF) << 16) | (packet_byte << 24) + + +@cocotb.test() +async def coaxpress_over_fiber_bridge_rx_decode_test(dut): + # Hold the bridge in its XGMII idle state until reset completes, then feed + # one packetized CXP frame followed by a separate IO-ack indication. + start_clock(dut.clk) + dut.rst.setimmediatevalue(1) + dut.xgmiiRxd.setimmediatevalue(0x07070707) + dut.xgmiiRxc.setimmediatevalue(0xF) + await reset_dut(dut, clk_name="clk", reset_names=("rst",)) + + observed: list[tuple[int, int]] = [] + + async def drive(rxd: int, rxc: int) -> None: + dut.xgmiiRxd.value = rxd + dut.xgmiiRxc.value = rxc + await cycle(dut.clk, 1) + sample = (int(dut.rxData.value), int(dut.rxDataK.value)) + if sample != (CXP_IDLE, CXP_IDLE_K): + observed.append(sample) + + # Low-speed packet carrying a CoaXPress event-ack message byte followed by + # one 32-bit payload word and an EOP terminator. + await drive(_cxp_start_word(CXP_PKT_EVENT_ACK_MSG), 0x1) + await drive(0x11223344, 0x0) + await drive(0x07FD00FD, 0xC) + await drive(0x07070707, 0xF) + await drive(0x07070707, 0xF) + + # Separate IO_ACK indication with no terminal payload word emitted. + dut.xgmiiRxd.value = CXPOF_START | (0x80 << 8) | ((CXP_IO_ACK & 0xFF) << 16) + dut.xgmiiRxc.value = 0x1 + await cycle(dut.clk, 1) + sample = (int(dut.rxData.value), int(dut.rxDataK.value)) + if sample != (CXP_IDLE, CXP_IDLE_K): + observed.append(sample) + await drive(0x07FD0000, 0xC) + await drive(0x07070707, 0xF) + await drive(0x07070707, 0xF) + + assert observed == [ + (CXP_SOP, 0xF), + (repeat_byte(CXP_PKT_EVENT_ACK_MSG), 0x0), + (0x11223344, 0x0), + (CXP_EOP, 0xF), + (CXP_IO_ACK, 0xF), + ] + + +def test_CoaXPressOverFiberBridgeRx(): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.coaxpressoverfiberbridgerx", + extra_vhdl_sources={ + "surf": [ + "protocols/coaxpress/core/rtl/CoaXPressPkg.vhd", + "protocols/coaxpress/core/rtl/CoaXPressOverFiberBridgeRx.vhd", + ] + }, + ) diff --git a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeTx.py b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeTx.py new file mode 100644 index 0000000000..b26660437c --- /dev/null +++ b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeTx.py @@ -0,0 +1,122 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Exercise the bridge TX on two successive packets so the bench covers +# the first-packet update flag and a later rate-change update. +# - Stimulus: Send one all-data low-speed packet at `txLsRate=1`, then toggle +# the low-speed rate and send one all-K-code packet. +# - Checks: The bridge must emit the CXPoF start word with the expected control +# bits, serialize four enabled CoaXPress lanes into two XGMII payload words, +# terminate with `/T/` and `/I/`, and reflect the changed rate/update flags +# on the second packet. +# - Timing: The bench records each XGMII word cycle-by-cycle so it checks the +# actual start, payload, terminate, and return-to-idle ordering. + +import cocotb +from cocotb.triggers import RisingEdge, Timer + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.protocols.coaxpress.coaxpress_test_utils import ( + CXPOF_IDLE, + CXPOF_START, + CXPOF_TERM, + cycle, + reset_dut, + start_clock, +) + + +def _start_word(rate: int, update: int) -> int: + sop_ctrl = (update << 3) | (rate << 1) + return CXPOF_START | (sop_ctrl << 8) + + +@cocotb.test() +async def coaxpress_over_fiber_bridge_tx_packet_format_test(dut): + # Reset into the idle state, then emit two packets with different rate and + # K/data modes so both start-word flag combinations are exercised. + start_clock(dut.clk) + dut.rst.setimmediatevalue(1) + dut.txLsValid.setimmediatevalue(0) + dut.txLsData.setimmediatevalue(0) + dut.txLsDataK.setimmediatevalue(0) + dut.txLsRate.setimmediatevalue(1) + dut.txLsLaneEn.setimmediatevalue(0xF) + await reset_dut(dut, clk_name="clk", reset_names=("rst",)) + + observed: list[tuple[int, int]] = [] + + async def capture_words(count: int) -> None: + while len(observed) < count: + await RisingEdge(dut.clk) + await Timer(1, unit="ns") + observed.append((int(dut.xgmiiTxd.value), int(dut.xgmiiTxc.value))) + + capture = cocotb.start_soon(capture_words(20)) + + dut.txLsData.value = 0xA5 + dut.txLsDataK.value = 0 + dut.txLsValid.value = 1 + await RisingEdge(dut.clk) + await Timer(1, unit="ns") + dut.txLsValid.value = 0 + + await cycle(dut.clk, 6) + + dut.txLsRate.value = 0 + dut.txLsData.value = 0x5C + dut.txLsDataK.value = 1 + dut.txLsValid.value = 1 + await RisingEdge(dut.clk) + await Timer(1, unit="ns") + dut.txLsValid.value = 0 + + await capture + + first_packet = None + second_packet = None + for start in range(len(observed) - 3): + words = observed[start : start + 4] + if words[0] == (_start_word(rate=1, update=1), 0x1): + first_packet = words + if words[0] == (_start_word(rate=0, update=1), 0x1): + second_packet = words + break + + assert first_packet is not None + assert second_packet is not None + + assert first_packet[1:] == [ + (0xA501A501, 0x0), + (0xA501A501, 0x0), + ((CXPOF_IDLE << 24) | (CXPOF_TERM << 16), 0xC), + ] + assert second_packet[1:] == [ + (0x5C025C02, 0x0), + (0x5C025C02, 0x0), + ((CXPOF_IDLE << 24) | (CXPOF_TERM << 16), 0xC), + ] + + # The bridge should fall back to all-idle words once packet emission ends. + assert any(word == (int.from_bytes(bytes([CXPOF_IDLE] * 4), "little"), 0xF) for word in observed[-3:]) + + +def test_CoaXPressOverFiberBridgeTx(): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.coaxpressoverfiberbridgetx", + extra_vhdl_sources={ + "surf": [ + "protocols/coaxpress/core/rtl/CoaXPressPkg.vhd", + "protocols/coaxpress/core/rtl/CoaXPressOverFiberBridgeTx.vhd", + ] + }, + ) diff --git a/tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py b/tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py new file mode 100644 index 0000000000..25c2a1708c --- /dev/null +++ b/tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py @@ -0,0 +1,171 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Exercise the low-speed transmit FSM on the faster `txRate=1` path +# so the bench can cover idle cadence, config draining, trigger pulse-width +# handling, and trigger-drop behavior in one practical runtime. +# - Stimulus: Queue config bytes ahead of time, then pulse `txTrig` once for a +# normal trigger transaction and again while the first trigger message is +# still active to hit the drop guardrail. +# - Checks: The DUT must emit the CoaXPress idle byte pattern before draining +# config bytes, maintain the expected heartbeat spacing, serialize both the +# asserted and deasserted trigger messages with the right K/data pattern, and +# pulse `txTrigDrop` when a second trigger edge arrives mid-message. +# - Timing: The bench records every `txStrobe` pulse with its clock-cycle index +# so cadence and serialized ordering are checked on the real byte timeline. + +import cocotb +from cocotb.triggers import RisingEdge, Timer + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.protocols.coaxpress.coaxpress_test_utils import ( + CXP_D21_5, + CXP_K28_1, + CXP_K28_2, + CXP_K28_4, + CXP_K28_5, + cycle, + reset_dut, + start_clock, +) + + +IDLE_SEQUENCE = [ + (CXP_K28_5, 1), + (CXP_K28_1, 1), + (CXP_K28_1, 1), + (CXP_D21_5, 0), +] + + +async def _drive_cfg_bytes(dut, beats: list[tuple[int, int]]) -> None: + dut.cfgTValid.value = 0 + dut.cfgTData.value = 0 + dut.cfgTUser.value = 0 + for data, is_k in beats: + dut.cfgTValid.value = 1 + dut.cfgTData.value = data + dut.cfgTUser.value = is_k + while True: + await RisingEdge(dut.txClk) + await Timer(1, unit="ns") + if int(dut.cfgTReady.value) == 1: + break + dut.cfgTValid.value = 0 + dut.cfgTData.value = 0 + dut.cfgTUser.value = 0 + + +async def _collect_strobes(dut, *, count: int, timeout_cycles: int) -> list[tuple[int, int, int]]: + observed: list[tuple[int, int, int]] = [] + for cycle_index in range(timeout_cycles): + await RisingEdge(dut.txClk) + await Timer(1, unit="ns") + if int(dut.txStrobe.value) == 1: + observed.append((cycle_index, int(dut.txData.value), int(dut.txDataK.value))) + if len(observed) == count: + return observed + raise AssertionError(f"Timed out waiting for {count} strobes, saw {len(observed)}") + + +async def _pulse_trigger(dut) -> None: + dut.txTrig.value = 1 + await RisingEdge(dut.txClk) + await Timer(1, unit="ns") + dut.txTrig.value = 0 + + +@cocotb.test() +async def coaxpress_tx_ls_fsm_idle_and_config_cadence_test(dut): + # Start from reset with config bytes already queued so the FSM proves it + # inserts one complete idle word before draining queued traffic. + start_clock(dut.txClk) + dut.txRst.setimmediatevalue(1) + dut.cfgTValid.setimmediatevalue(0) + dut.cfgTData.setimmediatevalue(0) + dut.cfgTUser.setimmediatevalue(0) + dut.txTrig.setimmediatevalue(0) + dut.txTrigInv.setimmediatevalue(0) + dut.txPulseWidth.setimmediatevalue(500) + dut.txRate.setimmediatevalue(1) + await reset_dut(dut, clk_name="txClk", reset_names=("txRst",)) + + cocotb.start_soon(_drive_cfg_bytes(dut, [(0x33, 0), (0xDC, 1)])) + observed = await _collect_strobes(dut, count=6, timeout_cycles=600) + + assert [(data, is_k) for _, data, is_k in observed[:4]] == IDLE_SEQUENCE + assert [(data, is_k) for _, data, is_k in observed[4:]] == [(0x33, 0), (0xDC, 1)] + assert [observed[index + 1][0] - observed[index][0] for index in range(5)] == [75] * 5 + + +@cocotb.test() +async def coaxpress_tx_ls_fsm_trigger_width_and_drop_test(dut): + # Trigger immediately after reset so the next heartbeat starts the trigger + # message, then re-trigger mid-message to check the drop guardrail. + start_clock(dut.txClk) + dut.txRst.setimmediatevalue(1) + dut.cfgTValid.setimmediatevalue(0) + dut.cfgTData.setimmediatevalue(0) + dut.cfgTUser.setimmediatevalue(0) + dut.txTrig.setimmediatevalue(0) + dut.txTrigInv.setimmediatevalue(0) + dut.txPulseWidth.setimmediatevalue(500) + dut.txRate.setimmediatevalue(1) + await reset_dut(dut, clk_name="txClk", reset_names=("txRst",)) + + await _pulse_trigger(dut) + + async def pulse_again_mid_message() -> None: + await cycle(dut.txClk, 200) + await _pulse_trigger(dut) + + cocotb.start_soon(pulse_again_mid_message()) + + strobes: list[tuple[int, int, int]] = [] + tx_trig_drop_seen = False + for cycle_index in range(1400): + await RisingEdge(dut.txClk) + await Timer(1, unit="ns") + if int(dut.txTrigDrop.value) == 1: + tx_trig_drop_seen = True + if int(dut.txStrobe.value) == 1: + strobes.append((cycle_index, int(dut.txData.value), int(dut.txDataK.value))) + if len(strobes) >= 14 and tx_trig_drop_seen: + break + + first_trigger = None + second_trigger = None + for start in range(len(strobes) - 5): + window = strobes[start : start + 6] + payload = [(data, is_k) for _, data, is_k in window] + if payload[:3] == [(CXP_K28_2, 1), (CXP_K28_4, 1), (CXP_K28_4, 1)] and payload[3][1] == payload[4][1] == payload[5][1] == 0 and payload[3][0] == payload[4][0] == payload[5][0]: + first_trigger = payload + if payload[:3] == [(CXP_K28_4, 1), (CXP_K28_2, 1), (CXP_K28_2, 1)] and payload[3][1] == payload[4][1] == payload[5][1] == 0 and payload[3][0] == payload[4][0] == payload[5][0]: + second_trigger = payload + break + + assert tx_trig_drop_seen + assert first_trigger is not None + assert second_trigger is not None + + +def test_CoaXPressTxLsFsm(): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.coaxpresstxlsfsmwrapper", + extra_vhdl_sources={ + "surf": [ + "protocols/coaxpress/core/rtl/CoaXPressPkg.vhd", + "protocols/coaxpress/core/rtl/CoaXPressTxLsFsm.vhd", + "protocols/coaxpress/core/wrappers/CoaXPressTxLsFsmWrapper.vhd", + ] + }, + ) From 0c8e0df8a0410ac2ed17e655c09bafd83b0324ad Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 20 Apr 2026 11:48:46 -0700 Subject: [PATCH 29/92] More coaxpress tests. --- docs/_meta/rtl_regression_handoff.md | 8 +- docs/_meta/rtl_regression_progress.md | 8 +- .../core/wrappers/CoaXPressTxWrapper.vhd | 83 +++++++ .../test_CoaXPressOverFiberBridge.py | 162 +++++++++++++ tests/protocols/coaxpress/test_CoaXPressTx.py | 223 ++++++++++++++++++ 5 files changed, 476 insertions(+), 8 deletions(-) create mode 100644 protocols/coaxpress/core/wrappers/CoaXPressTxWrapper.vhd create mode 100644 tests/protocols/coaxpress/test_CoaXPressOverFiberBridge.py create mode 100644 tests/protocols/coaxpress/test_CoaXPressTx.py diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index 9a2abf4625..fce762cb11 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -19,12 +19,12 @@ - Treat stale simulator cleanup as part of task completion: after any `pytest`, cocotb, GHDL, or similar launched verification step, sweep for leftover child processes and kill them before moving on ## Quick Resume Snapshot -- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, the current Ethernet coverage spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the pure-VHDL RoCEv2 quartet (`EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator`), and a broader user-directed CoaXPress pure-VHDL wave is now checked in under `tests/protocols/coaxpress/`. The validated CoaXPress subset now includes the receive quartet `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, and `CoaXPressRxHsFsm`, plus the transmit/bridge helpers `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressOverFiberBridgeRx`, and `CoaXPressOverFiberBridgeTx`, with subsystem-local wrappers under `protocols/coaxpress/core/wrappers/` where the stream-facing surfaces need flattening. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. +- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, the current Ethernet coverage spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the pure-VHDL RoCEv2 quartet (`EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator`), and a broader user-directed CoaXPress pure-VHDL wave is now checked in under `tests/protocols/coaxpress/`. The validated CoaXPress subset now includes the receive quartet `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, and `CoaXPressRxHsFsm`, the transmit/bridge helpers `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressOverFiberBridgeRx`, and `CoaXPressOverFiberBridgeTx`, and the first higher-level assemblies `CoaXPressTx` and `CoaXPressOverFiberBridge`. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. - Current axi frontier: complete for the intended simulator-friendly pass in this branch snapshot; do not resume from the older stale `AxiResize` note. - Current validated-open issues: - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core` remain untouched in phase 1, while the remaining RoCEv2 gap is the mixed-language bench path for the five RTL entities that instantiate generated submodules: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`. - `EthMacRxImportXlgmii` and `EthMacTxExportXlgmii` are still placeholder no-op RTL; the checked-in tests now lock down that inert contract instead of claiming functional XLGMII support. - - The remaining CoaXPress pure-VHDL gaps are now the higher-level assemblies `CoaXPressTx`, `CoaXPressRx`, `CoaXPressConfig`, `CoaXPressCore`, and `CoaXPressOverFiberBridge`. The current `CoaXPressRxHsFsm` bench intentionally stays on the stable one-lane path, so deeper multi-lane stepping/alignment behavior remains open even though the surrounding pure-VHDL helper leaves are now covered. + - The remaining CoaXPress pure-VHDL gaps are now `CoaXPressRx`, `CoaXPressConfig`, and `CoaXPressCore`. The current `CoaXPressRxHsFsm` bench intentionally stays on the stable one-lane path, so deeper multi-lane stepping/alignment behavior remains open even though the surrounding pure-VHDL helper leaves and the first transmit/bridge assemblies are now covered. - For future CoaXPress work, treat the named packet classes and control bytes in `tests/protocols/coaxpress/coaxpress_test_utils.py` as shared spec anchors, not as optional local style. Those constants were normalized against the same `CXP-001-2021` / `CXPR-008-2021` references cited in `CoaXPressPkg.vhd`. - Current planning discipline: - Use manual user-directed area selection as the active source of truth for what to work on next. @@ -66,7 +66,7 @@ - `tests/ethernet/UdpEngine/udp_test_utils.py` is now the shared home for the UDP slice: legacy-address constants, pseudo-frame builders, DHCP option helpers, and the common cocotb bench setup for the `ArpIpTable`, `UdpEngine*`, and `UdpEngineWrapper*` wrappers. Reuse it instead of rebuilding IPv4/UDP helper glue in each test module. - `tests/ethernet/IpV4Engine/ipv4_test_utils.py` is now the shared home for the IPv4 slice: packet/header builders and common cocotb bench setup for the `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, and `IpV4Engine*` wrappers. Reuse it instead of cloning IPv4 framing helpers across that directory. - `tests/protocols/ssi/ssi_test_utils.py` is the shared home for SSI transaction work: flat SSI endpoints, beat/frame helpers, contiguous-frame send, receive/no-output utilities, and `SOF`/`EOFE`-aware assertions. Use it instead of open-coding SSI handshake loops or terminal-flag checks. -- `tests/protocols/coaxpress/coaxpress_test_utils.py` is now the shared home for the CoaXPress leaf/bridge slice: protocol constants, repeated-byte word builders, byte-splitting helpers, wide-word packing helpers, basic clock/reset helpers, and simple pulse-capture utilities for the raw-word wrappers. Reuse it instead of cloning CoaXPress symbol constants or one-cycle output capture loops across future CoaXPress benches. +- `tests/protocols/coaxpress/coaxpress_test_utils.py` is now the shared home for the CoaXPress leaf/assembly slice: protocol constants, repeated-byte word builders, byte-splitting helpers, wide-word packing helpers, basic clock/reset helpers, and simple pulse-capture utilities for the raw-word wrappers. Reuse it instead of cloning CoaXPress symbol constants or one-cycle output capture loops across future CoaXPress benches. - Keep future CoaXPress benches explicit about the boundary between normative spec behavior and current RTL-contract-only coverage. For top-level and over-fiber work in particular, the governing references are the CoaXPress protocol spec (`CXP-001-2021`) and the CoaXPress-over-Fiber bridge spec (`CXPR-008-2021`); use the shared helper names for packet classes and control symbols instead of sprinkling raw byte literals through new tests. - Across the AXI slices, prefer the subsystem helper paths that already exist for register transactions, frame movement, and setup. In practice that means reusing helpers such as `tests/common/regression_utils.py`, the AXI/ethernet subsystem utility modules, and any nearby module-family helpers before inventing a one-off local transaction wrapper. - The current `EthMacCore` slice is intentionally a checked-in-wrapper-first rollout, not a cocotb-generated-wrapper experiment. Keep new Ethernet work on that same pattern unless the simulator forces a very local generic adapter. @@ -168,7 +168,7 @@ A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instan ## Immediate Next Task If the user keeps the focus on `protocols/coaxpress`, the next practical step is either: -1. move upward into the remaining pure-VHDL assemblies (`CoaXPressTx`, `CoaXPressRx`, and then `CoaXPressOverFiberBridge` / `CoaXPressCore`) using the now-covered helper leaves as the fixed contract surface, or +1. move into the remaining receive/config/core assemblies (`CoaXPressRx`, then `CoaXPressConfig`, then `CoaXPressCore`) using the now-covered helper and bridge/top-level transmit surfaces as the fixed contract boundary, or 2. deepen the current receive-path benches on the intentionally open multi-lane branches (`CoaXPressRxHsFsm` stepping/alignment and then `CoaXPressRx` integration). If the user switches back to `ethernet/RoCEv2`, the next real step is still enabling a mixed-language cocotb path for the five remaining RTL entities listed above. Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the real validated subset, and do not reintroduce local stand-ins for `blue-*`. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 9d0e99cfac..4a88017a9d 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -3,7 +3,7 @@ ## Summary - Current phase: Phase-1 implementation active - Current subsystem: manual user-directed rollout tracking -- Current focus module: user-directed CoaXPress pure-VHDL leaf/helper pass under `protocols/coaxpress/core/rtl`, with validated cocotb coverage now checked in for `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, `CoaXPressRxHsFsm`, `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressOverFiberBridgeRx`, and `CoaXPressOverFiberBridgeTx`. +- Current focus module: user-directed CoaXPress pure-VHDL rollout under `protocols/coaxpress/core/rtl`, with validated cocotb coverage now checked in for `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, `CoaXPressRxHsFsm`, `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressTx`, `CoaXPressOverFiberBridgeRx`, `CoaXPressOverFiberBridgeTx`, and `CoaXPressOverFiberBridge`. - Last updated: 2026-04-20 ## Current Frontier Snapshot @@ -22,8 +22,8 @@ - Covered now under the current GHDL-only flow: `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, `RoceConfigurator` - Still required, but need real `blue-*` dependencies under a mixed-language simulator: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, `RoceEngineWrapper` - CoaXPress RTL target matrix: - - Covered now under the current GHDL-only flow: `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, `CoaXPressRxHsFsm`, `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressOverFiberBridgeRx`, and `CoaXPressOverFiberBridgeTx` - - Still open in the same pure-VHDL family: `CoaXPressTx`, `CoaXPressRx`, `CoaXPressConfig`, `CoaXPressCore`, and `CoaXPressOverFiberBridge` + - Covered now under the current GHDL-only flow: `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, `CoaXPressRxHsFsm`, `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressTx`, `CoaXPressOverFiberBridgeRx`, `CoaXPressOverFiberBridgeTx`, and `CoaXPressOverFiberBridge` + - Still open in the same pure-VHDL family: `CoaXPressRx`, `CoaXPressConfig`, and `CoaXPressCore` - Spec discipline for this family: use the packet/control naming and byte values from `CXP-001-2021` and `CXPR-008-2021` via shared helpers, and keep future top-level/bridge benches explicit about whether they are proving normative spec behavior or only the currently validated RTL subset. - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. @@ -39,7 +39,7 @@ | `base` | started | not started | started | Validated low-level regressions now exist for `FifoAsync`, `FifoSync`, `FifoOutputPipeline`, `FifoWrFsm`, `FifoRdFsm`, `Fifo`, `FifoCascade`, `FifoMux`, `Synchronizer`, `SynchronizerVector`, `SynchronizerEdge`, `SynchronizerOneShot`, `SynchronizerFifo`, `SynchronizerOneShotCnt`, `SynchronizerOneShotVector`, `SynchronizerOneShotCntVector`, `SyncStatusVector`, `SyncTrigPeriod`, `SyncMinMax`, `SyncClockFreq`, `SyncTrigRate`, `SyncTrigRateVector`, `RstSync`, `RstPipeline`, `RstPipelineVector`, `PwrUpRst`, `Arbiter`, `ClockDivider`, `Debouncer`, `Gearbox`, `AsyncGearbox`, `Heartbeat`, `Mux`, `OneShot`, `RegisterVector`, `WatchDogRst`, `Scrambler`, `MasterRamIpIntegrator`, `SlaveRamIpIntegrator`, `SimpleDualPortRam`, `DualPortRam`, `TrueDualPortRam`, `LutRam`, `SlvDelay`, `SlvFixedDelay`, `SlvDelayRam`, `SlvDelayFifo`, `Crc32Parallel`, `Crc32`, and `CRC32Rtl` under subsystem-organized `tests/base/` packages. Remaining uncovered `base/` entities are vendor-heavy, dummy-backed, or `LutFixedDelay`, which is deferred because it depends on `SinglePortRamPrimitive`. | | `dsp` | started | not started | started | The planned `dsp/generic/fixed` leaf batch is now validated under `tests/dsp/generic/`: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. Shared DSP helpers now live in `tests/dsp/generic/dsp_test_utils.py`, and the legacy VHDL benches under `dsp/generic/tb/` were treated as behavioral reference material rather than as execution constraints. | | `axi` | started | not started | started | The axi-first pass is now complete for the simulator-friendly queue. The final locally validated batch adds `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`, with a combined `11 passed` validation run on 2026-03-27. Added checked-in subsystem wrappers under `axi/axi4/ip_integrator/`, `axi/axi-lite/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/` for those benches. `AxiStreamFifoV2` now has an expanded `10 passed` wrapper regression under `tests/axi/axi_stream/` covering async and sync width conversion, metadata truncation, `VALID_THOLD` frame-ready and burst-release modes, dynamic pause-threshold behavior, `CASCADE_SIZE=2`, and the `S_HAS_TREADY=0` pause-only source-side path. `AxiResize` now passes its equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` wrapper regression on this branch after the read-hold RTL fix. `AxiLiteAsync`, `AxiLiteToDrp`, and `AxiRateGen` still keep intentionally narrow common-clock subsets while the more timing-sensitive async AXI-Lite crossing branches remain open. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` still keep intentionally narrow first-pass subsets. `AxiStreamDmaV2Read` is now validated with a two-case wrapper regression covering both aligned and short terminal-beat reads after fixing bounded byte-count conversion in `AxiPkg` and terminal-mask generation in `AxiStreamDmaV2Read`. | -| `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. `protocols/coaxpress/` now has a broader pure-VHDL leaf/helper wave under `tests/protocols/coaxpress/` backed by checked-in wrappers in `protocols/coaxpress/core/wrappers/`: the receive quartet still covers offset-start packing, lane rotation, stream/config/event/heartbeat decode, and rectangular-header framing, while the new transmit/bridge leaves add `CoaXPressEventAckMsg` serialization under backpressure, `CoaXPressTxLsFsm` idle/config/trigger cadence, `CoaXPressOverFiberBridgeTx` CXPoF start/payload/terminate formatting, and `CoaXPressOverFiberBridgeRx` CXPoF start-word decode back into CoaXPress `SOP`/type/payload/`IO_ACK`. The current CoaXPress subset remains intentionally staged: it now covers the key pure-VHDL leaves plus the bridge endpoints, keeps the `CoaXPressRxHsFsm` wrapper on the stable one-lane path, normalizes packet/control literals onto named spec constants in `tests/protocols/coaxpress/coaxpress_test_utils.py`, and leaves the higher-level `CoaXPressTx`, `CoaXPressRx`, `CoaXPressConfig`, `CoaXPressCore`, and `CoaXPressOverFiberBridge` assemblies for the next pass. | +| `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. `protocols/coaxpress/` now has a broader pure-VHDL staged rollout under `tests/protocols/coaxpress/` backed by checked-in wrappers in `protocols/coaxpress/core/wrappers/`: the receive quartet still covers offset-start packing, lane rotation, stream/config/event/heartbeat decode, and rectangular-header framing; the transmit/bridge leaf benches cover `CoaXPressEventAckMsg` serialization under backpressure, `CoaXPressTxLsFsm` idle/config/trigger cadence, `CoaXPressOverFiberBridgeTx` CXPoF start/payload/terminate formatting, and `CoaXPressOverFiberBridgeRx` CXPoF start-word decode back into CoaXPress `SOP`/type/payload/`IO_ACK`; and the new assembly benches now cover `CoaXPressTx` config/event-ack arbitration plus software-trigger injection across the cfg-to-tx clock crossing and `CoaXPressOverFiberBridge` top-level 32b/64b gearbox integration on both the TX and RX sides. The current CoaXPress subset remains intentionally staged: it keeps the `CoaXPressRxHsFsm` wrapper on the stable one-lane path, normalizes packet/control literals onto named spec constants in `tests/protocols/coaxpress/coaxpress_test_utils.py`, and leaves the remaining higher-level receive/config/core assemblies `CoaXPressRx`, `CoaXPressConfig`, and `CoaXPressCore` for the next pass. | | `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers both the original leaf slice and the deeper assembly benches for `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`, plus direct `EthMacRxBypass` / `EthMacTxBypass` leaf benches and import/export sweeps that now explicitly include the current placeholder `XLGMII` contract. `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, including the successful multi-beat `RawEthFramerTx` unicast-forwarding path after lookup resolution. `tests/ethernet/UdpEngine/` covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, with the top/wrapper benches now widened across client/server routing paths. `tests/ethernet/IpV4Engine/` covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, and the top/leaf benches now also include protocol-TX and deeper ICMP reject/recovery coverage. `tests/ethernet/RoCEv2/` currently covers the pure-VHDL RTL entities `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator` through checked-in wrappers under `ethernet/RoCEv2/wrappers/`. The remaining RoCEv2 RTL entities that still need cocotb benches are `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`, and those should use the real generated `blue-*` dependencies rather than local stand-ins. The explicit Ethernet caveats are now the larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core`, the mixed-language RoCEv2 bench gap listed above, plus the still-placeholder `EthMac*Xlgmii` RTL. | | `devices` | not started | not started | not started | Many vendor-heavy cases | | `xilinx` | not started | not started | not started | Many vendor-heavy cases | diff --git a/protocols/coaxpress/core/wrappers/CoaXPressTxWrapper.vhd b/protocols/coaxpress/core/wrappers/CoaXPressTxWrapper.vhd new file mode 100644 index 0000000000..7531e16025 --- /dev/null +++ b/protocols/coaxpress/core/wrappers/CoaXPressTxWrapper.vhd @@ -0,0 +1,83 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for CoaXPressTx +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; + +entity CoaXPressTxWrapper is + port ( + cfgClk : in sl; + cfgRst : in sl; + cfgTValid : in sl; + cfgTData : in slv(7 downto 0); + cfgTUser : in sl; + cfgTLast : in sl; + cfgTReady : out sl; + eventAck : in sl; + eventTag : in slv(7 downto 0); + txClk : in sl; + txRst : in sl; + txLsRate : in sl; + txLsValid : out sl; + txLsData : out slv(7 downto 0); + txLsDataK : out sl; + txTrigInv : in sl; + txPulseWidth : in slv(31 downto 0); + swTrig : in sl; + txTrig : in sl; + txTrigDrop : out sl); +end entity CoaXPressTxWrapper; + +architecture rtl of CoaXPressTxWrapper is + + signal cfgTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal cfgTxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + +begin + + -- Flatten the byte-wide config AXI stream onto cocotb scalar ports. + cfgTxMaster.tValid <= cfgTValid; + cfgTxMaster.tData(7 downto 0) <= cfgTData; + cfgTxMaster.tKeep(0) <= '1'; + cfgTxMaster.tUser(0) <= cfgTUser; + cfgTxMaster.tLast <= cfgTLast; + cfgTReady <= cfgTxSlave.tReady; + + U_DUT : entity surf.CoaXPressTx + generic map ( + TPD_G => 1 ns) + port map ( + cfgClk => cfgClk, + cfgRst => cfgRst, + cfgTxMaster => cfgTxMaster, + cfgTxSlave => cfgTxSlave, + eventAck => eventAck, + eventTag => eventTag, + txClk => txClk, + txRst => txRst, + txLsRate => txLsRate, + txLsValid => txLsValid, + txLsData => txLsData, + txLsDataK => txLsDataK, + txTrigInv => txTrigInv, + txPulseWidth => txPulseWidth, + swTrig => swTrig, + txTrig => txTrig, + txTrigDrop => txTrigDrop); + +end architecture rtl; diff --git a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridge.py b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridge.py new file mode 100644 index 0000000000..e71e1e63f3 --- /dev/null +++ b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridge.py @@ -0,0 +1,162 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Exercise the top-level CoaXPress-over-Fiber bridge across both its +# transmit and receive halves so the surrounding async gearboxes are covered, +# not only the inner 32-bit bridge leaves. +# - Stimulus: Inject one low-speed transmit byte on the 312 MHz CXP side and, +# separately, inject one packetized 64-bit XGMII receive sequence on the 156 +# MHz fiber side. +# - Checks: The bridge must pack the inner 32-bit TX sequence into the +# expected two 64-bit XGMII words and must unpack the RX 64-bit XGMII words +# back into the expected CoaXPress `SOP`, packet-type, payload, and `EOP` +# words. +# - Timing: The bench samples both sides on their native clocks and searches +# the resulting streams for the expected ordered windows, which keeps the +# checks robust to gearbox latency while still validating real output order. + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.protocols.coaxpress.coaxpress_test_utils import ( + CXP_EOP, + CXP_IDLE, + CXP_IDLE_K, + CXP_PKT_EVENT_ACK_MSG, + CXP_SOP, + CXPOF_IDLE, + CXPOF_START, + CXPOF_TERM, + cycle, + repeat_byte, +) + + +def _tx_start_word(rate: int, update: int) -> int: + return CXPOF_START | (((update << 3) | (rate << 1)) << 8) + + +def _rx_start_word(packet_byte: int) -> int: + return CXPOF_START | (0x80 << 8) | ((CXP_SOP & 0xFF) << 16) | (packet_byte << 24) + + +def _find_subsequence(observed: list[tuple[int, int]], expected: list[tuple[int, int]]) -> int | None: + for start in range(len(observed) - len(expected) + 1): + if observed[start : start + len(expected)] == expected: + return start + return None + + +async def _reset_domains(dut) -> None: + dut.txRst312.value = 1 + dut.rxRst312.value = 1 + await Timer(40, unit="ns") + dut.txRst312.value = 0 + dut.rxRst312.value = 0 + await Timer(20, unit="ns") + + +@cocotb.test() +async def coaxpress_over_fiber_bridge_top_level_integration_test(dut): + # Run the 312 MHz and 156 MHz domains at a 2:1 ratio so the async gearboxes + # see the intended width-conversion cadence while still operating on + # independent clocks. + cocotb.start_soon(Clock(dut.txClk312, 4, unit="ns").start()) + cocotb.start_soon(Clock(dut.txClk156, 8, unit="ns").start()) + cocotb.start_soon(Clock(dut.rxClk312, 4, unit="ns").start()) + cocotb.start_soon(Clock(dut.rxClk156, 8, unit="ns").start()) + + idle64 = int.from_bytes(bytes([CXPOF_IDLE] * 8), "little") + dut.txLsValid.setimmediatevalue(0) + dut.txLsData.setimmediatevalue(0) + dut.txLsDataK.setimmediatevalue(0) + dut.txLsLaneEn.setimmediatevalue(0xF) + dut.txLsRate.setimmediatevalue(1) + dut.xgmiiRxd.setimmediatevalue(idle64) + dut.xgmiiRxc.setimmediatevalue(0xFF) + await _reset_domains(dut) + await cycle(dut.txClk312, 6) + await cycle(dut.rxClk156, 2) + + tx_observed: list[tuple[int, int]] = [] + rx_observed: list[tuple[int, int]] = [] + + async def capture_tx_words(cycles: int) -> None: + for _ in range(cycles): + await RisingEdge(dut.txClk156) + await Timer(1, unit="ns") + tx_observed.append((int(dut.xgmiiTxd.value), int(dut.xgmiiTxc.value))) + + async def capture_rx_words(cycles: int) -> None: + for _ in range(cycles): + await RisingEdge(dut.rxClk312) + await Timer(1, unit="ns") + sample = (int(dut.rxData.value), int(dut.rxDataK.value)) + if sample != (CXP_IDLE, CXP_IDLE_K): + rx_observed.append(sample) + + tx_capture = cocotb.start_soon(capture_tx_words(32)) + rx_capture = cocotb.start_soon(capture_rx_words(32)) + + dut.txLsData.value = 0xA5 + dut.txLsDataK.value = 0 + dut.txLsValid.value = 1 + await RisingEdge(dut.txClk312) + await Timer(1, unit="ns") + await RisingEdge(dut.txClk312) + await Timer(1, unit="ns") + dut.txLsValid.value = 0 + + await cycle(dut.rxClk156, 3) + dut.xgmiiRxd.value = (_rx_start_word(CXP_PKT_EVENT_ACK_MSG) | (0x11223344 << 32)) + dut.xgmiiRxc.value = 0x01 + await RisingEdge(dut.rxClk156) + await Timer(1, unit="ns") + dut.xgmiiRxd.value = (0x07FD00FD | (repeat_byte(CXPOF_IDLE) << 32)) + dut.xgmiiRxc.value = 0xFC + await RisingEdge(dut.rxClk156) + await Timer(1, unit="ns") + dut.xgmiiRxd.value = idle64 + dut.xgmiiRxc.value = 0xFF + + await tx_capture + await rx_capture + + tx_expected = [ + ((_tx_start_word(rate=1, update=1) | (0xA501A501 << 32)), 0x01), + ((0xA501A501 | (((CXPOF_IDLE << 24) | (CXPOF_TERM << 16)) << 32)), 0xC0), + ] + rx_expected = [ + (CXP_SOP, 0xF), + (repeat_byte(CXP_PKT_EVENT_ACK_MSG), 0x0), + (0x11223344, 0x0), + (CXP_EOP, 0xF), + ] + + assert _find_subsequence(tx_observed, tx_expected) is not None, f"missing TX gearbox sequence in observed stream: {tx_observed}" + assert _find_subsequence(rx_observed, rx_expected) is not None, f"missing RX gearbox sequence in observed stream: {rx_observed}" + + +def test_CoaXPressOverFiberBridge(): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.coaxpressoverfiberbridge", + extra_vhdl_sources={ + "surf": [ + "protocols/coaxpress/core/rtl/CoaXPressPkg.vhd", + "protocols/coaxpress/core/rtl/CoaXPressOverFiberBridgeRx.vhd", + "protocols/coaxpress/core/rtl/CoaXPressOverFiberBridgeTx.vhd", + "protocols/coaxpress/core/rtl/CoaXPressOverFiberBridge.vhd", + ] + }, + ) diff --git a/tests/protocols/coaxpress/test_CoaXPressTx.py b/tests/protocols/coaxpress/test_CoaXPressTx.py new file mode 100644 index 0000000000..d2d6ba79ef --- /dev/null +++ b/tests/protocols/coaxpress/test_CoaXPressTx.py @@ -0,0 +1,223 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Exercise the first full CoaXPress transmit assembly in two modes: +# config/event-ack arbitration across the cfg-to-tx clock crossing and the +# software-trigger path into the low-speed transmit FSM. +# - Stimulus: Queue one multi-byte config packet, pulse `eventAck` while that +# packet is active, and separately pulse only `swTrig` with `txTrig` held +# low so the OR-combined trigger path is the only source of trigger traffic. +# - Checks: The transmitted low-speed stream must preserve the config bytes, +# serialize the spec-defined event-ack packet without corruption, and emit +# both trigger message polarities from a software trigger without asserting +# `txTrigDrop`. +# - Timing: The bench records each transmitted byte at the real `txClk` +# heartbeat cadence and searches the resulting stream for exact packet and +# trigger windows rather than assuming zero-latency handoff across modules. + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.protocols.coaxpress.coaxpress_test_utils import ( + CXP_D21_5, + CXP_K28_1, + CXP_K28_2, + CXP_K28_4, + CXP_K28_5, + CXP_PKT_EVENT_ACK_MSG, + CXP_EOP, + CXP_SOP, + cycle, + word_to_bytes, +) + + +IDLE_SEQUENCE = [ + (CXP_K28_5, 1), + (CXP_K28_1, 1), + (CXP_K28_1, 1), + (CXP_D21_5, 0), +] + + +async def _reset_domains(dut) -> None: + dut.cfgRst.value = 1 + dut.txRst.value = 1 + await Timer(40, unit="ns") + dut.cfgRst.value = 0 + dut.txRst.value = 0 + await Timer(20, unit="ns") + + +async def _drive_cfg_packet(dut, beats: list[tuple[int, int]]) -> None: + dut.cfgTValid.value = 0 + dut.cfgTData.value = 0 + dut.cfgTUser.value = 0 + dut.cfgTLast.value = 0 + await RisingEdge(dut.cfgClk) + for index, (data, is_k) in enumerate(beats): + dut.cfgTValid.value = 1 + dut.cfgTData.value = data + dut.cfgTUser.value = is_k + dut.cfgTLast.value = 1 if index == len(beats) - 1 else 0 + while True: + await RisingEdge(dut.cfgClk) + await Timer(1, unit="ns") + if int(dut.cfgTReady.value) == 1: + break + dut.cfgTValid.value = 0 + dut.cfgTData.value = 0 + dut.cfgTUser.value = 0 + dut.cfgTLast.value = 0 + + +async def _pulse_event_ack(dut, tag: int) -> None: + dut.eventTag.value = tag + dut.eventAck.value = 1 + await RisingEdge(dut.cfgClk) + await Timer(1, unit="ns") + dut.eventAck.value = 0 + + +async def _pulse_sw_trigger(dut) -> None: + dut.swTrig.value = 1 + await RisingEdge(dut.txClk) + await Timer(1, unit="ns") + dut.swTrig.value = 0 + + +async def _collect_tx_bytes(dut, *, count: int, timeout_cycles: int) -> tuple[list[tuple[int, int, int]], bool]: + observed: list[tuple[int, int, int]] = [] + tx_trig_drop_seen = False + for cycle_index in range(timeout_cycles): + await RisingEdge(dut.txClk) + await Timer(1, unit="ns") + if int(dut.txTrigDrop.value) == 1: + tx_trig_drop_seen = True + if int(dut.txLsValid.value) == 1: + observed.append((cycle_index, int(dut.txLsData.value), int(dut.txLsDataK.value))) + if len(observed) >= count: + return observed, tx_trig_drop_seen + raise AssertionError(f"Timed out waiting for {count} CoaXPress TX bytes, saw {len(observed)}") + + +def _find_subsequence(observed: list[tuple[int, int, int]], expected: list[tuple[int, int]]) -> int | None: + payload = [(data, is_k) for _, data, is_k in observed] + for start in range(len(payload) - len(expected) + 1): + if payload[start : start + len(expected)] == expected: + return start + return None + + +@cocotb.test() +async def coaxpress_tx_config_and_event_ack_test(dut): + # Hold the assembly in reset long enough for both domains to settle, then + # prove that a config packet already in flight is preserved ahead of a + # later event-ack packet through the mux and CDC FIFO. + cocotb.start_soon(Clock(dut.cfgClk, 6, unit="ns").start()) + cocotb.start_soon(Clock(dut.txClk, 4, unit="ns").start()) + dut.cfgTValid.setimmediatevalue(0) + dut.cfgTData.setimmediatevalue(0) + dut.cfgTUser.setimmediatevalue(0) + dut.cfgTLast.setimmediatevalue(0) + dut.eventAck.setimmediatevalue(0) + dut.eventTag.setimmediatevalue(0) + dut.txLsRate.setimmediatevalue(1) + dut.txTrigInv.setimmediatevalue(0) + dut.txPulseWidth.setimmediatevalue(500) + dut.swTrig.setimmediatevalue(0) + dut.txTrig.setimmediatevalue(0) + await _reset_domains(dut) + + cfg_bytes = [(0x12, 0), (0x9C, 1), (0x55, 0)] + event_tag = 0xA6 + cfg_driver = cocotb.start_soon(_drive_cfg_packet(dut, cfg_bytes)) + + await cycle(dut.cfgClk, 4) + await _pulse_event_ack(dut, event_tag) + + observed, tx_trig_drop_seen = await _collect_tx_bytes(dut, count=28, timeout_cycles=4000) + await cfg_driver + + assert not tx_trig_drop_seen + + cfg_start = _find_subsequence(observed, cfg_bytes) + assert cfg_start is not None, f"config bytes not found in observed stream: {observed}" + + event_ack_bytes = [ + *[(byte, 1) for byte in word_to_bytes(CXP_SOP)], + *[(CXP_PKT_EVENT_ACK_MSG, 0)] * 4, + *[(event_tag, 0)] * 4, + *[(byte, 1) for byte in word_to_bytes(CXP_EOP)], + ] + event_start = _find_subsequence(observed, event_ack_bytes) + assert event_start is not None, f"event-ack packet not found in observed stream: {observed}" + idle_after_event = _find_subsequence(observed[event_start + len(event_ack_bytes) :], IDLE_SEQUENCE) + assert cfg_start < event_start, f"unexpected config/event ordering in observed stream: {observed}" + assert idle_after_event is not None, f"idle word not restored after event-ack packet: {observed}" + + +@cocotb.test() +async def coaxpress_tx_software_trigger_path_test(dut): + # Keep the hardware trigger low and use only `swTrig` so the bench proves + # the assembly's OR-combined software trigger path end-to-end. + cocotb.start_soon(Clock(dut.cfgClk, 6, unit="ns").start()) + cocotb.start_soon(Clock(dut.txClk, 4, unit="ns").start()) + dut.cfgTValid.setimmediatevalue(0) + dut.cfgTData.setimmediatevalue(0) + dut.cfgTUser.setimmediatevalue(0) + dut.cfgTLast.setimmediatevalue(0) + dut.eventAck.setimmediatevalue(0) + dut.eventTag.setimmediatevalue(0) + dut.txLsRate.setimmediatevalue(1) + dut.txTrigInv.setimmediatevalue(1) + dut.txPulseWidth.setimmediatevalue(500) + dut.swTrig.setimmediatevalue(0) + dut.txTrig.setimmediatevalue(0) + await _reset_domains(dut) + + await _pulse_sw_trigger(dut) + await cycle(dut.txClk, 4) + await _pulse_sw_trigger(dut) + observed, tx_trig_drop_seen = await _collect_tx_bytes(dut, count=24, timeout_cycles=2200) + + first_trigger = None + second_trigger = None + for start in range(len(observed) - 5): + window = observed[start : start + 6] + payload = [(data, is_k) for _, data, is_k in window] + if payload[:3] == [(CXP_K28_4, 1), (CXP_K28_2, 1), (CXP_K28_2, 1)] and payload[3][1] == payload[4][1] == payload[5][1] == 0 and payload[3][0] == payload[4][0] == payload[5][0]: + first_trigger = payload + if payload[:3] == [(CXP_K28_2, 1), (CXP_K28_4, 1), (CXP_K28_4, 1)] and payload[3][1] == payload[4][1] == payload[5][1] == 0 and payload[3][0] == payload[4][0] == payload[5][0]: + second_trigger = payload + break + + assert first_trigger is not None, f"asserted trigger window not found in observed stream: {observed}" + assert second_trigger is not None, f"deasserted trigger window not found in observed stream: {observed}" + assert not tx_trig_drop_seen, f"unexpected txTrigDrop in observed stream: {observed}" + + +def test_CoaXPressTx(): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.coaxpresstxwrapper", + extra_vhdl_sources={ + "surf": [ + "protocols/coaxpress/core/rtl/CoaXPressPkg.vhd", + "protocols/coaxpress/core/rtl/CoaXPressEventAckMsg.vhd", + "protocols/coaxpress/core/rtl/CoaXPressTxLsFsm.vhd", + "protocols/coaxpress/core/rtl/CoaXPressTx.vhd", + "protocols/coaxpress/core/wrappers/CoaXPressTxWrapper.vhd", + ] + }, + ) From ffa0bd2053498ab1bae83bfb0a82efef932cc61b Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 20 Apr 2026 12:38:24 -0700 Subject: [PATCH 30/92] Add more tests. --- docs/_meta/rtl_regression_handoff.md | 7 +- docs/_meta/rtl_regression_plan.md | 1 + docs/_meta/rtl_regression_progress.md | 8 +- .../core/wrappers/CoaXPressConfigWrapper.vhd | 176 ++++++++++ .../core/wrappers/CoaXPressCoreWrapper.vhd | 330 ++++++++++++++++++ .../core/wrappers/CoaXPressRxWrapper.vhd | 136 ++++++++ .../coaxpress/coaxpress_test_utils.py | 13 + .../coaxpress/test_CoaXPressConfig.py | 203 +++++++++++ .../protocols/coaxpress/test_CoaXPressCore.py | 158 +++++++++ tests/protocols/coaxpress/test_CoaXPressRx.py | 241 +++++++++++++ 10 files changed, 1267 insertions(+), 6 deletions(-) create mode 100644 protocols/coaxpress/core/wrappers/CoaXPressConfigWrapper.vhd create mode 100644 protocols/coaxpress/core/wrappers/CoaXPressCoreWrapper.vhd create mode 100644 protocols/coaxpress/core/wrappers/CoaXPressRxWrapper.vhd create mode 100644 tests/protocols/coaxpress/test_CoaXPressConfig.py create mode 100644 tests/protocols/coaxpress/test_CoaXPressCore.py create mode 100644 tests/protocols/coaxpress/test_CoaXPressRx.py diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index fce762cb11..2dee091930 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -19,12 +19,13 @@ - Treat stale simulator cleanup as part of task completion: after any `pytest`, cocotb, GHDL, or similar launched verification step, sweep for leftover child processes and kill them before moving on ## Quick Resume Snapshot -- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, the current Ethernet coverage spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the pure-VHDL RoCEv2 quartet (`EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator`), and a broader user-directed CoaXPress pure-VHDL wave is now checked in under `tests/protocols/coaxpress/`. The validated CoaXPress subset now includes the receive quartet `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, and `CoaXPressRxHsFsm`, the transmit/bridge helpers `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressOverFiberBridgeRx`, and `CoaXPressOverFiberBridgeTx`, and the first higher-level assemblies `CoaXPressTx` and `CoaXPressOverFiberBridge`. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. +- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, the current Ethernet coverage spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the pure-VHDL RoCEv2 quartet (`EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator`), and a broader user-directed CoaXPress pure-VHDL wave is now checked in under `tests/protocols/coaxpress/`. The validated CoaXPress subset now includes the receive quartet `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, and `CoaXPressRxHsFsm`, the receive assembly `CoaXPressRx`, the transmit/bridge helpers `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressOverFiberBridgeRx`, and `CoaXPressOverFiberBridgeTx`, and the higher-level assemblies `CoaXPressTx`, `CoaXPressCore`, and `CoaXPressOverFiberBridge`. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. - Current axi frontier: complete for the intended simulator-friendly pass in this branch snapshot; do not resume from the older stale `AxiResize` note. - Current validated-open issues: - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core` remain untouched in phase 1, while the remaining RoCEv2 gap is the mixed-language bench path for the five RTL entities that instantiate generated submodules: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`. - `EthMacRxImportXlgmii` and `EthMacTxExportXlgmii` are still placeholder no-op RTL; the checked-in tests now lock down that inert contract instead of claiming functional XLGMII support. - - The remaining CoaXPress pure-VHDL gaps are now `CoaXPressRx`, `CoaXPressConfig`, and `CoaXPressCore`. The current `CoaXPressRxHsFsm` bench intentionally stays on the stable one-lane path, so deeper multi-lane stepping/alignment behavior remains open even though the surrounding pure-VHDL helper leaves and the first transmit/bridge assemblies are now covered. + - The remaining CoaXPress pure-VHDL gap is now `CoaXPressConfig`. The current `CoaXPressRxHsFsm` and `CoaXPressRx` benches intentionally stay on the stable one-lane path, so deeper multi-lane stepping/alignment behavior remains open even though the surrounding pure-VHDL helper leaves and the higher-level transmit/core/bridge assemblies are now covered. + - `tests/protocols/coaxpress/test_CoaXPressConfig.py` is intentionally checked in as a skipped investigation bench. When driven through the real SRP ingress, the current `CoaXPressConfig` / `SrpV3AxiLite` integration does not complete the request path within the bench timeout, so treat that as a likely RTL or integration defect to debug before re-enabling active assertions there. - For future CoaXPress work, treat the named packet classes and control bytes in `tests/protocols/coaxpress/coaxpress_test_utils.py` as shared spec anchors, not as optional local style. Those constants were normalized against the same `CXP-001-2021` / `CXPR-008-2021` references cited in `CoaXPressPkg.vhd`. - Current planning discipline: - Use manual user-directed area selection as the active source of truth for what to work on next. @@ -168,7 +169,7 @@ A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instan ## Immediate Next Task If the user keeps the focus on `protocols/coaxpress`, the next practical step is either: -1. move into the remaining receive/config/core assemblies (`CoaXPressRx`, then `CoaXPressConfig`, then `CoaXPressCore`) using the now-covered helper and bridge/top-level transmit surfaces as the fixed contract boundary, or +1. debug and re-enable the skipped `CoaXPressConfig` investigation bench, starting with the SRP-driven request path that currently fails to complete through the real `CoaXPressConfig` / `SrpV3AxiLite` integration, or 2. deepen the current receive-path benches on the intentionally open multi-lane branches (`CoaXPressRxHsFsm` stepping/alignment and then `CoaXPressRx` integration). If the user switches back to `ethernet/RoCEv2`, the next real step is still enabling a mixed-language cocotb path for the five remaining RTL entities listed above. Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the real validated subset, and do not reintroduce local stand-ins for `blue-*`. diff --git a/docs/_meta/rtl_regression_plan.md b/docs/_meta/rtl_regression_plan.md index 7dfc8e7fc8..b86a7a8ceb 100644 --- a/docs/_meta/rtl_regression_plan.md +++ b/docs/_meta/rtl_regression_plan.md @@ -111,6 +111,7 @@ - For CoaXPress image/header benches, keep the repeated-byte field encoding, header field order, endianness conversion, line-size semantics, and end-of-frame rules explicitly tied to the spec-defined rectangular image packet layout. - For CoaXPress-over-Fiber benches, keep `/I/`, `/Q/`, `/S/`, `/T/`, and `/E/` handling, lane-0-only start/sequence semantics, and payload-vs-housekeeping start words aligned to `CXPR-008-2021`. - If a checked-in bench intentionally validates only the current RTL contract instead of the full normative spec behavior, document that narrowed scope explicitly in the progress and handoff docs rather than implying full spec coverage. +- If a CoaXPress top-level bench has to be checked in as skipped because it exposes a likely RTL defect, keep the spec-shaped stimulus and the skip reason in-tree, and record the blocking symptom explicitly in the progress and handoff docs so the next pass resumes from the defect rather than from scratch. ## Historical Queue Artifacts The phase-1 simulator-friendly queue remains available as a generated bottom-up artifact, but it is now historical context rather than the active workflow. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 4a88017a9d..ce05823318 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -3,7 +3,7 @@ ## Summary - Current phase: Phase-1 implementation active - Current subsystem: manual user-directed rollout tracking -- Current focus module: user-directed CoaXPress pure-VHDL rollout under `protocols/coaxpress/core/rtl`, with validated cocotb coverage now checked in for `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, `CoaXPressRxHsFsm`, `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressTx`, `CoaXPressOverFiberBridgeRx`, `CoaXPressOverFiberBridgeTx`, and `CoaXPressOverFiberBridge`. +- Current focus module: user-directed CoaXPress pure-VHDL rollout under `protocols/coaxpress/core/rtl`, with validated cocotb coverage now checked in for `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, `CoaXPressRxHsFsm`, `CoaXPressRx`, `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressTx`, `CoaXPressCore`, `CoaXPressOverFiberBridgeRx`, `CoaXPressOverFiberBridgeTx`, and `CoaXPressOverFiberBridge`. - Last updated: 2026-04-20 ## Current Frontier Snapshot @@ -22,8 +22,9 @@ - Covered now under the current GHDL-only flow: `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, `RoceConfigurator` - Still required, but need real `blue-*` dependencies under a mixed-language simulator: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, `RoceEngineWrapper` - CoaXPress RTL target matrix: - - Covered now under the current GHDL-only flow: `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, `CoaXPressRxHsFsm`, `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressTx`, `CoaXPressOverFiberBridgeRx`, `CoaXPressOverFiberBridgeTx`, and `CoaXPressOverFiberBridge` - - Still open in the same pure-VHDL family: `CoaXPressRx`, `CoaXPressConfig`, and `CoaXPressCore` + - Covered now under the current GHDL-only flow: `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, `CoaXPressRxHsFsm`, `CoaXPressRx`, `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressTx`, `CoaXPressCore`, `CoaXPressOverFiberBridgeRx`, `CoaXPressOverFiberBridgeTx`, and `CoaXPressOverFiberBridge` + - Still open in the same pure-VHDL family: `CoaXPressConfig` + - Blocked bench note: `tests/protocols/coaxpress/test_CoaXPressConfig.py` is checked in as a skipped investigation bench because the real SRP-driven request path does not complete under the current `CoaXPressConfig`/`SrpV3AxiLite` integration. Treat that as a likely RTL or integration defect to debug before re-enabling active assertions on the config return path. - Spec discipline for this family: use the packet/control naming and byte values from `CXP-001-2021` and `CXPR-008-2021` via shared helpers, and keep future top-level/bridge benches explicit about whether they are proving normative spec behavior or only the currently validated RTL subset. - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. @@ -322,3 +323,4 @@ - 2026-04-20: Started the first `ethernet/RoCEv2` phase-1 slice with the stable VHDL-only helper leaves instead of the mixed-language top wrappers. Added `ethernet/RoCEv2/wrappers/EthMacPrepareForICrcWrapper.vhd` and `ethernet/RoCEv2/wrappers/EthMacRxCheckICrcWrapper.vhd`, implemented `tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py` and `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, linted both wrappers cleanly with `./.venv/bin/vsg -c vsg-linter.yml -f ...`, validated the pair with `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py` (`2 passed`), and recorded the remaining open RoCEv2 work as the mixed-language wrapper/assembly path rather than claiming full-family coverage. - 2026-04-20: Added the pure-VHDL RoCEv2 follow-on benches `tests/ethernet/RoCEv2/test_RoceResizeAndSwap.py` and `test_RoceConfigurator.py` plus their checked-in wrappers `ethernet/RoCEv2/wrappers/RoceResizeAndSwapIpIntegrator.vhd` and `RoceConfiguratorWrapper.vhd`, and validated the pure-VHDL RoCEv2 bench set with `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py tests/ethernet/RoCEv2/test_RoceResizeAndSwap.py tests/ethernet/RoCEv2/test_RoceConfigurator.py` (`4 passed`). - 2026-04-20: Removed the temporary local CRC stand-ins and the stub-backed `EthMacTxRoCEv2` / `EthMacRxRoCEv2` benches after clarifying the intended boundary: there should be one cocotb test module per entity in `ethernet/RoCEv2/rtl`, but `blue-*` must remain real transitive dependencies rather than being replaced with local test doubles. The current open RoCEv2 bench set is therefore `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`, all of which now require a mixed-language simulation path. +- 2026-04-20: Added the next CoaXPress assembly pass with `tests/protocols/coaxpress/test_CoaXPressRx.py`, `test_CoaXPressCore.py`, and the checked-in wrappers `protocols/coaxpress/core/wrappers/CoaXPressRxWrapper.vhd` and `CoaXPressCoreWrapper.vhd`. The validated subset now covers the one-lane `CoaXPressRx` receive assembly and the AXI-Lite-controlled `CoaXPressCore` TX/config assembly path. `tests/protocols/coaxpress/test_CoaXPressConfig.py` was kept in-tree as a skipped investigation bench because the real SRP-driven `CoaXPressConfig` request path does not complete under the current `CoaXPressConfig` / `SrpV3AxiLite` integration, which is now recorded as the remaining pure-VHDL CoaXPress blocker. diff --git a/protocols/coaxpress/core/wrappers/CoaXPressConfigWrapper.vhd b/protocols/coaxpress/core/wrappers/CoaXPressConfigWrapper.vhd new file mode 100644 index 0000000000..417d42f47d --- /dev/null +++ b/protocols/coaxpress/core/wrappers/CoaXPressConfigWrapper.vhd @@ -0,0 +1,176 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for CoaXPressConfig +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.SsiPkg.all; + +entity CoaXPressConfigWrapper is + port ( + cfgClk : in sl; + cfgRst : in sl; + configTimerSize : in slv(31 downto 0); + configErrResp : in sl; + configPktTag : in sl; + S_CFG_IB_TVALID : in sl; + S_CFG_IB_TDATA : in slv(255 downto 0); + S_CFG_IB_TKEEP : in slv(31 downto 0); + S_CFG_IB_TLAST : in sl; + S_CFG_IB_TUSER : in slv(1 downto 0); + S_CFG_IB_TREADY : out sl; + M_CFG_OB_TVALID : out sl; + M_CFG_OB_TDATA : out slv(255 downto 0); + M_CFG_OB_TKEEP : out slv(31 downto 0); + M_CFG_OB_TLAST : out sl; + M_CFG_OB_TUSER : out slv(1 downto 0); + M_CFG_OB_TREADY : in sl; + M_CFG_TX_TVALID : out sl; + M_CFG_TX_TDATA : out slv(7 downto 0); + M_CFG_TX_TKEEP : out slv(0 downto 0); + M_CFG_TX_TLAST : out sl; + M_CFG_TX_TUSER : out slv(0 downto 0); + M_CFG_TX_TREADY : in sl; + cfgRxTValid : in sl; + cfgRxTData : in slv(63 downto 0)); +end entity CoaXPressConfigWrapper; + +architecture rtl of CoaXPressConfigWrapper is + + constant CFG_AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(dataBytes => 32); + + signal cfgIbMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal cfgIbSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal cfgObMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal cfgObSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal cfgTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal cfgTxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal cfgRxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + + signal unusedClk : sl; + signal unusedRst : sl; + +begin + + U_CfgIb : entity surf.SlaveAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "S_CFG_IB", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 2, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 32) + port map ( + S_AXIS_ACLK => cfgClk, + S_AXIS_ARESETN => not cfgRst, + S_AXIS_TVALID => S_CFG_IB_TVALID, + S_AXIS_TDATA => S_CFG_IB_TDATA, + S_AXIS_TSTRB => (others => '1'), + S_AXIS_TKEEP => S_CFG_IB_TKEEP, + S_AXIS_TLAST => S_CFG_IB_TLAST, + S_AXIS_TDEST => "0", + S_AXIS_TID => "0", + S_AXIS_TUSER => S_CFG_IB_TUSER, + S_AXIS_TREADY => S_CFG_IB_TREADY, + axisClk => unusedClk, + axisRst => unusedRst, + axisMaster => cfgIbMaster, + axisSlave => cfgIbSlave); + + U_CfgOb : entity surf.MasterAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "M_CFG_OB", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 2, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 32) + port map ( + M_AXIS_ACLK => cfgClk, + M_AXIS_ARESETN => not cfgRst, + M_AXIS_TVALID => M_CFG_OB_TVALID, + M_AXIS_TDATA => M_CFG_OB_TDATA, + M_AXIS_TSTRB => open, + M_AXIS_TKEEP => M_CFG_OB_TKEEP, + M_AXIS_TLAST => M_CFG_OB_TLAST, + M_AXIS_TDEST => open, + M_AXIS_TID => open, + M_AXIS_TUSER => M_CFG_OB_TUSER, + M_AXIS_TREADY => M_CFG_OB_TREADY, + axisClk => open, + axisRst => open, + axisMaster => cfgObMaster, + axisSlave => cfgObSlave); + + U_CfgTx : entity surf.MasterAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "M_CFG_TX", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 1, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 1) + port map ( + M_AXIS_ACLK => cfgClk, + M_AXIS_ARESETN => not cfgRst, + M_AXIS_TVALID => M_CFG_TX_TVALID, + M_AXIS_TDATA => M_CFG_TX_TDATA, + M_AXIS_TSTRB => open, + M_AXIS_TKEEP => M_CFG_TX_TKEEP, + M_AXIS_TLAST => M_CFG_TX_TLAST, + M_AXIS_TDEST => open, + M_AXIS_TID => open, + M_AXIS_TUSER => M_CFG_TX_TUSER, + M_AXIS_TREADY => M_CFG_TX_TREADY, + axisClk => open, + axisRst => open, + axisMaster => cfgTxMaster, + axisSlave => cfgTxSlave); + + cfgRxMaster.tValid <= cfgRxTValid; + cfgRxMaster.tLast <= cfgRxTValid; + cfgRxMaster.tKeep(7 downto 0) <= (others => '1'); + cfgRxMaster.tData(63 downto 0) <= cfgRxTData; + + U_DUT : entity surf.CoaXPressConfig + generic map ( + TPD_G => 1 ns, + AXIS_CONFIG_G => CFG_AXIS_CONFIG_C) + port map ( + cfgClk => cfgClk, + cfgRst => cfgRst, + configTimerSize => configTimerSize, + configErrResp => configErrResp, + configPktTag => configPktTag, + cfgIbMaster => cfgIbMaster, + cfgIbSlave => cfgIbSlave, + cfgObMaster => cfgObMaster, + cfgObSlave => cfgObSlave, + cfgTxMaster => cfgTxMaster, + cfgTxSlave => cfgTxSlave, + cfgRxMaster => cfgRxMaster); + +end architecture rtl; diff --git a/protocols/coaxpress/core/wrappers/CoaXPressCoreWrapper.vhd b/protocols/coaxpress/core/wrappers/CoaXPressCoreWrapper.vhd new file mode 100644 index 0000000000..48d25b8fab --- /dev/null +++ b/protocols/coaxpress/core/wrappers/CoaXPressCoreWrapper.vhd @@ -0,0 +1,330 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for CoaXPressCore +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.AxiLitePkg.all; +use surf.SsiPkg.all; + +entity CoaXPressCoreWrapper is + port ( + dataClk : in sl; + dataRst : in sl; + cfgClk : in sl; + cfgRst : in sl; + txClk : in sl; + txRst : in sl; + rxClk : in sl; + rxRst : in sl; + axilClk : in sl; + axilRst : in sl; + txTrig : in sl; + txLinkUp : in sl; + rxData : in slv(31 downto 0); + rxDataK : in slv(3 downto 0); + rxDispErr : in sl; + rxDecErr : in sl; + rxLinkUp : in sl; + gtRstAll : out sl; + txLsValid : out sl; + txLsData : out slv(7 downto 0); + txLsDataK : out sl; + txLsRate : out sl; + txLsLaneEn : out slv(3 downto 0); + S_AXI_AWADDR : in slv(11 downto 0); + S_AXI_AWPROT : in slv(2 downto 0); + S_AXI_AWVALID : in sl; + S_AXI_AWREADY : out sl; + S_AXI_WDATA : in slv(31 downto 0); + S_AXI_WSTRB : in slv(3 downto 0); + S_AXI_WVALID : in sl; + S_AXI_WREADY : out sl; + S_AXI_BRESP : out slv(1 downto 0); + S_AXI_BVALID : out sl; + S_AXI_BREADY : in sl; + S_AXI_ARADDR : in slv(11 downto 0); + S_AXI_ARPROT : in slv(2 downto 0); + S_AXI_ARVALID : in sl; + S_AXI_ARREADY : out sl; + S_AXI_RDATA : out slv(31 downto 0); + S_AXI_RRESP : out slv(1 downto 0); + S_AXI_RVALID : out sl; + S_AXI_RREADY : in sl; + S_CFG_IB_TVALID : in sl; + S_CFG_IB_TDATA : in slv(255 downto 0); + S_CFG_IB_TKEEP : in slv(31 downto 0); + S_CFG_IB_TLAST : in sl; + S_CFG_IB_TUSER : in slv(1 downto 0); + S_CFG_IB_TREADY : out sl; + M_CFG_OB_TVALID : out sl; + M_CFG_OB_TDATA : out slv(255 downto 0); + M_CFG_OB_TKEEP : out slv(31 downto 0); + M_CFG_OB_TLAST : out sl; + M_CFG_OB_TUSER : out slv(1 downto 0); + M_CFG_OB_TREADY : in sl; + M_DATA_TVALID : out sl; + M_DATA_TDATA : out slv(31 downto 0); + M_DATA_TKEEP : out slv(3 downto 0); + M_DATA_TLAST : out sl; + M_DATA_TUSER : out slv(0 downto 0); + M_DATA_TREADY : in sl; + M_HDR_TVALID : out sl; + M_HDR_TDATA : out slv(31 downto 0); + M_HDR_TKEEP : out slv(3 downto 0); + M_HDR_TLAST : out sl; + M_HDR_TUSER : out slv(0 downto 0); + M_HDR_TREADY : in sl); +end entity CoaXPressCoreWrapper; + +architecture rtl of CoaXPressCoreWrapper is + + constant DATA_AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(dataBytes => 4); + constant CFG_AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(dataBytes => 32); + + signal cfgIbMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal cfgIbSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal cfgObMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal cfgObSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal dataMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal dataSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal hdrMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal hdrSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + + signal rxClkVec : slv(0 downto 0); + signal rxRstVec : slv(0 downto 0); + signal rxDataVec : slv32Array(0 downto 0); + signal rxDataKVec : Slv4Array(0 downto 0); + signal rxDispErrVec : slv(0 downto 0); + signal rxDecErrVec : slv(0 downto 0); + signal rxLinkUpVec : slv(0 downto 0); + + signal unusedClk : sl; + signal unusedRst : sl; + +begin + + rxClkVec(0) <= rxClk; + rxRstVec(0) <= rxRst; + rxDataVec(0) <= rxData; + rxDataKVec(0) <= rxDataK; + rxDispErrVec(0) <= rxDispErr; + rxDecErrVec(0) <= rxDecErr; + rxLinkUpVec(0) <= rxLinkUp; + + U_Axil : entity surf.SlaveAxiLiteIpIntegrator + generic map ( + INTERFACENAME => "S_AXI", + EN_ERROR_RESP => true, + HAS_PROT => 1, + HAS_WSTRB => 1, + FREQ_HZ => 100000000, + ADDR_WIDTH => 12) + port map ( + S_AXI_ACLK => axilClk, + S_AXI_ARESETN => not axilRst, + S_AXI_AWADDR => S_AXI_AWADDR, + S_AXI_AWPROT => S_AXI_AWPROT, + S_AXI_AWVALID => S_AXI_AWVALID, + S_AXI_AWREADY => S_AXI_AWREADY, + S_AXI_WDATA => S_AXI_WDATA, + S_AXI_WSTRB => S_AXI_WSTRB, + S_AXI_WVALID => S_AXI_WVALID, + S_AXI_WREADY => S_AXI_WREADY, + S_AXI_BRESP => S_AXI_BRESP, + S_AXI_BVALID => S_AXI_BVALID, + S_AXI_BREADY => S_AXI_BREADY, + S_AXI_ARADDR => S_AXI_ARADDR, + S_AXI_ARPROT => S_AXI_ARPROT, + S_AXI_ARVALID => S_AXI_ARVALID, + S_AXI_ARREADY => S_AXI_ARREADY, + S_AXI_RDATA => S_AXI_RDATA, + S_AXI_RRESP => S_AXI_RRESP, + S_AXI_RVALID => S_AXI_RVALID, + S_AXI_RREADY => S_AXI_RREADY, + axilClk => open, + axilRst => open, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + + U_CfgIb : entity surf.SlaveAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "S_CFG_IB", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 2, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 32) + port map ( + S_AXIS_ACLK => cfgClk, + S_AXIS_ARESETN => not cfgRst, + S_AXIS_TVALID => S_CFG_IB_TVALID, + S_AXIS_TDATA => S_CFG_IB_TDATA, + S_AXIS_TSTRB => (others => '1'), + S_AXIS_TKEEP => S_CFG_IB_TKEEP, + S_AXIS_TLAST => S_CFG_IB_TLAST, + S_AXIS_TDEST => "0", + S_AXIS_TID => "0", + S_AXIS_TUSER => S_CFG_IB_TUSER, + S_AXIS_TREADY => S_CFG_IB_TREADY, + axisClk => unusedClk, + axisRst => unusedRst, + axisMaster => cfgIbMaster, + axisSlave => cfgIbSlave); + + U_CfgOb : entity surf.MasterAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "M_CFG_OB", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 2, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 32) + port map ( + M_AXIS_ACLK => cfgClk, + M_AXIS_ARESETN => not cfgRst, + M_AXIS_TVALID => M_CFG_OB_TVALID, + M_AXIS_TDATA => M_CFG_OB_TDATA, + M_AXIS_TSTRB => open, + M_AXIS_TKEEP => M_CFG_OB_TKEEP, + M_AXIS_TLAST => M_CFG_OB_TLAST, + M_AXIS_TDEST => open, + M_AXIS_TID => open, + M_AXIS_TUSER => M_CFG_OB_TUSER, + M_AXIS_TREADY => M_CFG_OB_TREADY, + axisClk => open, + axisRst => open, + axisMaster => cfgObMaster, + axisSlave => cfgObSlave); + + U_Data : entity surf.MasterAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "M_DATA", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 1, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 4) + port map ( + M_AXIS_ACLK => dataClk, + M_AXIS_ARESETN => not dataRst, + M_AXIS_TVALID => M_DATA_TVALID, + M_AXIS_TDATA => M_DATA_TDATA, + M_AXIS_TSTRB => open, + M_AXIS_TKEEP => M_DATA_TKEEP, + M_AXIS_TLAST => M_DATA_TLAST, + M_AXIS_TDEST => open, + M_AXIS_TID => open, + M_AXIS_TUSER => M_DATA_TUSER, + M_AXIS_TREADY => M_DATA_TREADY, + axisClk => open, + axisRst => open, + axisMaster => dataMaster, + axisSlave => dataSlave); + + U_Hdr : entity surf.MasterAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "M_HDR", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 1, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 4) + port map ( + M_AXIS_ACLK => dataClk, + M_AXIS_ARESETN => not dataRst, + M_AXIS_TVALID => M_HDR_TVALID, + M_AXIS_TDATA => M_HDR_TDATA, + M_AXIS_TSTRB => open, + M_AXIS_TKEEP => M_HDR_TKEEP, + M_AXIS_TLAST => M_HDR_TLAST, + M_AXIS_TDEST => open, + M_AXIS_TID => open, + M_AXIS_TUSER => M_HDR_TUSER, + M_AXIS_TREADY => M_HDR_TREADY, + axisClk => open, + axisRst => open, + axisMaster => hdrMaster, + axisSlave => hdrSlave); + + U_DUT : entity surf.CoaXPressCore + generic map ( + TPD_G => 1 ns, + NUM_LANES_G => 1, + STATUS_CNT_WIDTH_G => 8, + RX_FSM_CNT_WIDTH_G => 8, + AXIL_CLK_FREQ_G => 100.0E+6, + AXIS_CLK_FREQ_G => 100.0E+6, + DATA_AXIS_CONFIG_G => DATA_AXIS_CONFIG_C, + CFG_AXIS_CONFIG_G => CFG_AXIS_CONFIG_C) + port map ( + gtRstAll => gtRstAll, + dataClk => dataClk, + dataRst => dataRst, + dataMaster => dataMaster, + dataSlave => dataSlave, + imageHdrMaster => hdrMaster, + imageHdrSlave => hdrSlave, + cfgClk => cfgClk, + cfgRst => cfgRst, + cfgIbMaster => cfgIbMaster, + cfgIbSlave => cfgIbSlave, + cfgObMaster => cfgObMaster, + cfgObSlave => cfgObSlave, + txClk => txClk, + txRst => txRst, + txLsValid => txLsValid, + txLsData => txLsData, + txLsDataK => txLsDataK, + txLsRate => txLsRate, + txLsLaneEn => txLsLaneEn, + txTrig => txTrig, + txLinkUp => txLinkUp, + rxClk => rxClkVec, + rxRst => rxRstVec, + rxData => rxDataVec, + rxDataK => rxDataKVec, + rxDispErr => rxDispErrVec, + rxDecErr => rxDecErrVec, + rxLinkUp => rxLinkUpVec, + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + +end architecture rtl; diff --git a/protocols/coaxpress/core/wrappers/CoaXPressRxWrapper.vhd b/protocols/coaxpress/core/wrappers/CoaXPressRxWrapper.vhd new file mode 100644 index 0000000000..491136ed99 --- /dev/null +++ b/protocols/coaxpress/core/wrappers/CoaXPressRxWrapper.vhd @@ -0,0 +1,136 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for CoaXPressRx +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.SsiPkg.all; + +entity CoaXPressRxWrapper is + port ( + dataClk : in sl; + dataRst : in sl; + cfgClk : in sl; + cfgRst : in sl; + txClk : in sl; + txRst : in sl; + rxClk : in sl; + rxRst : in sl; + rxData : in slv(31 downto 0); + rxDataK : in slv(3 downto 0); + rxLinkUp : in sl; + rxFsmRst : in sl; + rxNumberOfLane : in slv(2 downto 0); + dataTValid : out sl; + dataTData : out slv(31 downto 0); + dataTKeep : out slv(3 downto 0); + dataTLast : out sl; + dataTUser : out slv(0 downto 0); + dataTReady : in sl; + hdrTValid : out sl; + hdrTData : out slv(31 downto 0); + hdrTKeep : out slv(3 downto 0); + hdrTLast : out sl; + hdrTUser : out slv(0 downto 0); + hdrTReady : in sl; + cfgTValid : out sl; + cfgTData : out slv(63 downto 0); + cfgTKeep : out slv(7 downto 0); + cfgTLast : out sl; + eventAck : out sl; + eventTag : out slv(7 downto 0); + trigAck : out sl; + rxOverflow : out sl; + rxFsmError : out sl); +end entity CoaXPressRxWrapper; + +architecture rtl of CoaXPressRxWrapper is + + constant AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(dataBytes => 4); + + signal dataMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal dataSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal imageHdrMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal imageHdrSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal cfgRxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + + signal rxClkVec : slv(0 downto 0); + signal rxRstVec : slv(0 downto 0); + signal rxDataVec : slv32Array(0 downto 0); + signal rxDataKVec : Slv4Array(0 downto 0); + signal rxLinkUpVec : slv(0 downto 0); + +begin + + rxClkVec(0) <= rxClk; + rxRstVec(0) <= rxRst; + rxDataVec(0) <= rxData; + rxDataKVec(0) <= rxDataK; + rxLinkUpVec(0) <= rxLinkUp; + + dataSlave.tReady <= dataTReady; + imageHdrSlave.tReady <= hdrTReady; + + dataTValid <= dataMaster.tValid; + dataTData <= dataMaster.tData(31 downto 0); + dataTKeep <= dataMaster.tKeep(3 downto 0); + dataTLast <= dataMaster.tLast; + dataTUser <= dataMaster.tUser(0 downto 0); + + hdrTValid <= imageHdrMaster.tValid; + hdrTData <= imageHdrMaster.tData(31 downto 0); + hdrTKeep <= imageHdrMaster.tKeep(3 downto 0); + hdrTLast <= imageHdrMaster.tLast; + hdrTUser <= imageHdrMaster.tUser(0 downto 0); + + cfgTValid <= cfgRxMaster.tValid; + cfgTData <= cfgRxMaster.tData(63 downto 0); + cfgTKeep <= cfgRxMaster.tKeep(7 downto 0); + cfgTLast <= cfgRxMaster.tLast; + + U_DUT : entity surf.CoaXPressRx + generic map ( + TPD_G => 1 ns, + NUM_LANES_G => 1, + RX_FSM_CNT_WIDTH_G => 8, + AXIS_CONFIG_G => AXIS_CONFIG_C) + port map ( + dataClk => dataClk, + dataRst => dataRst, + dataMaster => dataMaster, + dataSlave => dataSlave, + imageHdrMaster => imageHdrMaster, + imageHdrSlave => imageHdrSlave, + cfgClk => cfgClk, + cfgRst => cfgRst, + cfgRxMaster => cfgRxMaster, + eventAck => eventAck, + eventTag => eventTag, + txClk => txClk, + txRst => txRst, + trigAck => trigAck, + rxClk => rxClkVec, + rxRst => rxRstVec, + rxData => rxDataVec, + rxDataK => rxDataKVec, + rxLinkUp => rxLinkUpVec, + rxOverflow => rxOverflow, + rxFsmError => rxFsmError, + rxFsmRst => rxFsmRst, + rxNumberOfLane => rxNumberOfLane); + +end architecture rtl; diff --git a/tests/protocols/coaxpress/coaxpress_test_utils.py b/tests/protocols/coaxpress/coaxpress_test_utils.py index b51df0f483..fb4dc93d87 100644 --- a/tests/protocols/coaxpress/coaxpress_test_utils.py +++ b/tests/protocols/coaxpress/coaxpress_test_utils.py @@ -70,6 +70,19 @@ def word_to_bytes(word: int, *, byte_count: int = 4) -> list[int]: return [(word >> (8 * index)) & 0xFF for index in range(byte_count)] +def pack_bytes(payload: bytes, *, width_bytes: int) -> int: + return int.from_bytes(payload.ljust(width_bytes, b"\x00"), "little") + + +def unpack_kept_bytes(data: int, keep: int, *, width_bytes: int) -> bytes: + lanes = word_to_bytes(data, byte_count=width_bytes) + return bytes(byte for index, byte in enumerate(lanes) if (keep >> index) & 0x1) + + +def endian_swap32(word: int) -> int: + return int.from_bytes((word & 0xFFFFFFFF).to_bytes(4, "little"), "big") + + def pack_words(words: list[int], *, word_bits: int = 32) -> int: mask = (1 << word_bits) - 1 value = 0 diff --git a/tests/protocols/coaxpress/test_CoaXPressConfig.py b/tests/protocols/coaxpress/test_CoaXPressConfig.py new file mode 100644 index 0000000000..4d7a86374e --- /dev/null +++ b/tests/protocols/coaxpress/test_CoaXPressConfig.py @@ -0,0 +1,203 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Cover the two request-serialization branches that are unique to +# `CoaXPressConfig`: untagged reads and tagged writes. +# - Stimulus: Drive one-beat SRPv3 request frames into `cfgIb` and capture the +# emitted CoaXPress low-speed byte stream on `cfgTx`. +# - Checks: The DUT must emit the spec-shaped request prefix/suffix, select the +# correct tagged or untagged packet type, preserve the address and write-data +# fields, and increment the tagged packet counter across transactions. +# - Timing: Requests are accepted through the real `TREADY` handshake and the +# test waits on the serialized CoaXPress bytes rather than assuming an ideal +# one-cycle transfer through the assembly. + +import cocotb +import pytest +from cocotb.triggers import RisingEdge, Timer, with_timeout + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.protocols.coaxpress.coaxpress_test_utils import ( + CXP_EOP, + CXP_SOP, + endian_swap32, + pack_bytes, + word_to_bytes, +) + +pytestmark = pytest.mark.skip( + reason=( + "Blocked by a suspected CoaXPressConfig/SrpV3AxiLite integration issue: " + "the real SRP-driven request path does not complete within the current bench timeout." + ) +) + + +READ_OPCODE = 0x0 +WRITE_OPCODE = 0x1 + + +def _srp_request_words(*, opcode: int, tid: int, addr: int, req_size: int, write_data: int | None = None) -> list[int]: + words = [0x00000003 | (opcode << 8), tid, addr & 0xFFFFFFFF, 0x00000000, req_size] + if write_data is not None: + words.append(write_data & 0xFFFFFFFF) + return words + + +def _words_to_payload(words: list[int]) -> bytes: + return b"".join((word & 0xFFFFFFFF).to_bytes(4, "little") for word in words) + + +def _payload_to_words(payload: bytes) -> list[int]: + return [int.from_bytes(payload[index : index + 4], "little") for index in range(0, len(payload), 4)] + + +async def _reset_cfg_domain(dut) -> None: + dut.cfgRst.value = 1 + await Timer(40, unit="ns") + dut.cfgRst.value = 0 + await Timer(20, unit="ns") + + +async def _send_cfg_ib_frame(dut, payload: bytes, *, tuser: int = 0x2) -> None: + dut.S_CFG_IB_TVALID.value = 1 + dut.S_CFG_IB_TDATA.value = pack_bytes(payload, width_bytes=32) + dut.S_CFG_IB_TKEEP.value = (1 << len(payload)) - 1 + dut.S_CFG_IB_TLAST.value = 1 + dut.S_CFG_IB_TUSER.value = tuser + while True: + await RisingEdge(dut.cfgClk) + await Timer(1, unit="ns") + if int(dut.S_CFG_IB_TREADY.value) == 1: + break + dut.S_CFG_IB_TVALID.value = 0 + dut.S_CFG_IB_TDATA.value = 0 + dut.S_CFG_IB_TKEEP.value = 0 + dut.S_CFG_IB_TLAST.value = 0 + dut.S_CFG_IB_TUSER.value = 0 + + +async def _collect_tx_bytes(dut, *, count: int, timeout_cycles: int = 8000) -> bytes: + payload = bytearray() + dut.M_CFG_TX_TREADY.value = 1 + for _ in range(timeout_cycles): + await RisingEdge(dut.cfgClk) + await Timer(1, unit="ns") + if int(dut.M_CFG_TX_TVALID.value) == 1: + payload.append(int(dut.M_CFG_TX_TDATA.value)) + if len(payload) >= count: + return bytes(payload) + raise AssertionError(f"Timed out waiting for {count} CoaXPress config TX bytes") + + +async def _drive_cfg_rx_completion(dut, value: int, *, hold_cycles: int = 8) -> None: + dut.cfgRxTData.value = value + dut.cfgRxTValid.value = 1 + for _ in range(hold_cycles): + await RisingEdge(dut.cfgClk) + await Timer(1, unit="ns") + dut.cfgRxTValid.value = 0 + dut.cfgRxTData.value = 0 + + +@cocotb.test() +async def coaxpress_config_untagged_read_request_test(dut): + cocotb.start_soon(cocotb.clock.Clock(dut.cfgClk, 4, unit="ns").start()) + dut.S_CFG_IB_TVALID.setimmediatevalue(0) + dut.S_CFG_IB_TDATA.setimmediatevalue(0) + dut.S_CFG_IB_TKEEP.setimmediatevalue(0) + dut.S_CFG_IB_TLAST.setimmediatevalue(0) + dut.S_CFG_IB_TUSER.setimmediatevalue(0) + dut.M_CFG_OB_TREADY.setimmediatevalue(1) + dut.M_CFG_TX_TREADY.setimmediatevalue(0) + dut.cfgRxTValid.setimmediatevalue(0) + dut.cfgRxTData.setimmediatevalue(0) + dut.configTimerSize.setimmediatevalue(4096) + dut.configErrResp.setimmediatevalue(1) + dut.configPktTag.setimmediatevalue(0) + await _reset_cfg_domain(dut) + + tid = 0x12345678 + addr = 0x00000040 + read_data = 0xDDAA5501 + request_payload = _words_to_payload(_srp_request_words(opcode=READ_OPCODE, tid=tid, addr=addr, req_size=0x00000003)) + + tx_task = cocotb.start_soon(_collect_tx_bytes(dut, count=24)) + await _send_cfg_ib_frame(dut, request_payload) + + tx_bytes = await with_timeout(tx_task, 20, "us") + + expected_prefix = ( + bytes(word_to_bytes(CXP_SOP)) + + bytes([0x02] * 4) + + bytes(word_to_bytes(0x04000000)) + + bytes(word_to_bytes(endian_swap32(addr))) + ) + assert tx_bytes.startswith(expected_prefix) + assert tx_bytes[-4:] == bytes(word_to_bytes(CXP_EOP)) + assert tx_bytes[16:20] != b"\x00\x00\x00\x00" + await _drive_cfg_rx_completion(dut, read_data << 32) + + +@cocotb.test() +async def coaxpress_config_tagged_write_tag_increment_test(dut): + cocotb.start_soon(cocotb.clock.Clock(dut.cfgClk, 4, unit="ns").start()) + dut.S_CFG_IB_TVALID.setimmediatevalue(0) + dut.S_CFG_IB_TDATA.setimmediatevalue(0) + dut.S_CFG_IB_TKEEP.setimmediatevalue(0) + dut.S_CFG_IB_TLAST.setimmediatevalue(0) + dut.S_CFG_IB_TUSER.setimmediatevalue(0) + dut.M_CFG_OB_TREADY.setimmediatevalue(1) + dut.M_CFG_TX_TREADY.setimmediatevalue(0) + dut.cfgRxTValid.setimmediatevalue(0) + dut.cfgRxTData.setimmediatevalue(0) + dut.configTimerSize.setimmediatevalue(4096) + dut.configErrResp.setimmediatevalue(1) + dut.configPktTag.setimmediatevalue(1) + await _reset_cfg_domain(dut) + + requests = [ + (0x0BADB002, 0x00000020, 0x11223344, 0x00), + (0x0BADB003, 0x00000024, 0x55667788, 0x01), + ] + + for tid, addr, write_data, expected_tag in requests: + request_payload = _words_to_payload( + _srp_request_words(opcode=WRITE_OPCODE, tid=tid, addr=addr, req_size=0x00000003, write_data=write_data) + ) + + tx_task = cocotb.start_soon(_collect_tx_bytes(dut, count=32)) + await _send_cfg_ib_frame(dut, request_payload) + + tx_bytes = await with_timeout(tx_task, 20, "us") + assert tx_bytes[:4] == bytes(word_to_bytes(CXP_SOP)) + assert tx_bytes[4:8] == bytes([0x05] * 4) + assert tx_bytes[8:12] == bytes([expected_tag] * 4) + assert tx_bytes[12:16] == bytes(word_to_bytes(0x04000001)) + assert tx_bytes[16:20] == bytes(word_to_bytes(endian_swap32(addr))) + assert tx_bytes[20:24] == bytes(word_to_bytes(write_data)) + assert tx_bytes[-4:] == bytes(word_to_bytes(CXP_EOP)) + + await _drive_cfg_rx_completion(dut, 0) + + +def test_CoaXPressConfig(): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.coaxpressconfigwrapper", + extra_vhdl_sources={ + "surf": [ + "protocols/coaxpress/core/rtl/CoaXPressPkg.vhd", + "protocols/coaxpress/core/rtl/CoaXPressConfig.vhd", + "protocols/coaxpress/core/wrappers/CoaXPressConfigWrapper.vhd", + ] + }, + ) diff --git a/tests/protocols/coaxpress/test_CoaXPressCore.py b/tests/protocols/coaxpress/test_CoaXPressCore.py new file mode 100644 index 0000000000..da0f0250a3 --- /dev/null +++ b/tests/protocols/coaxpress/test_CoaXPressCore.py @@ -0,0 +1,158 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Keep the first `CoaXPressCore` pass on the one-lane top-level path +# and focus on the unique cross-block integration that only the full core can +# exercise: AXI-Lite control of `configPktTag`/`txLsRate` into the config/TX +# assembly. +# - Stimulus: Program `configPktTag` and the fast low-speed rate over AXI-Lite, +# then send one SRPv3 read request through the core config ingress. +# - Checks: The top level must expose the programmed AXI-Lite register values +# back to software and serialize the corresponding tagged CoaXPress config +# request on the TX low-speed byte stream. +# - Timing: AXI-Lite writes, config ingress, and TX byte observation all run on +# the real module interfaces, so the bench checks the actual sequencing across +# `CoaXPressAxiL`, `CoaXPressConfig`, and `CoaXPressTx`. + +import cocotb +from cocotb.triggers import RisingEdge, Timer, with_timeout +from cocotbext.axi import AxiLiteBus, AxiLiteMaster + +from tests.common.regression_utils import run_surf_vhdl_test, start_lockstep_clocks +from tests.protocols.coaxpress.coaxpress_test_utils import CXP_SOP, endian_swap32, pack_bytes, word_to_bytes + + +def _words_to_payload(words: list[int]) -> bytes: + return b"".join((word & 0xFFFFFFFF).to_bytes(4, "little") for word in words) + + +async def _reset_all(dut) -> None: + dut.dataRst.value = 1 + dut.cfgRst.value = 1 + dut.txRst.value = 1 + dut.rxRst.value = 1 + dut.axilRst.value = 1 + await Timer(40, unit="ns") + dut.dataRst.value = 0 + dut.cfgRst.value = 0 + dut.txRst.value = 0 + dut.rxRst.value = 0 + dut.axilRst.value = 0 + await Timer(20, unit="ns") + + +async def _send_cfg_ib_frame(dut, payload: bytes) -> None: + dut.S_CFG_IB_TVALID.value = 1 + dut.S_CFG_IB_TDATA.value = pack_bytes(payload, width_bytes=32) + dut.S_CFG_IB_TKEEP.value = (1 << len(payload)) - 1 + dut.S_CFG_IB_TLAST.value = 1 + dut.S_CFG_IB_TUSER.value = 0x2 + while True: + await RisingEdge(dut.cfgClk) + await Timer(1, unit="ns") + if int(dut.S_CFG_IB_TREADY.value) == 1: + break + dut.S_CFG_IB_TVALID.value = 0 + dut.S_CFG_IB_TDATA.value = 0 + dut.S_CFG_IB_TKEEP.value = 0 + dut.S_CFG_IB_TLAST.value = 0 + dut.S_CFG_IB_TUSER.value = 0 + + +async def _collect_tx_bytes(dut, *, count: int, timeout_cycles: int = 12000) -> list[tuple[int, int]]: + observed: list[tuple[int, int]] = [] + for _ in range(timeout_cycles): + await RisingEdge(dut.txClk) + await Timer(1, unit="ns") + if int(dut.txLsValid.value) == 1: + observed.append((int(dut.txLsData.value), int(dut.txLsDataK.value))) + if len(observed) >= count: + return observed + raise AssertionError("Timed out waiting for CoaXPressCore TX bytes") + + +def _find_subsequence(payload: bytes, expected: bytes) -> int | None: + for start in range(len(payload) - len(expected) + 1): + if payload[start : start + len(expected)] == expected: + return start + return None + + +@cocotb.test() +async def coaxpress_core_tagged_config_tx_path_test(dut): + start_lockstep_clocks(dut.dataClk, dut.cfgClk, dut.txClk, dut.rxClk, dut.axilClk, period_ns=4.0) + dut.txTrig.setimmediatevalue(0) + dut.txLinkUp.setimmediatevalue(1) + dut.rxData.setimmediatevalue(0xB53C3CBC) + dut.rxDataK.setimmediatevalue(0x7) + dut.rxDispErr.setimmediatevalue(0) + dut.rxDecErr.setimmediatevalue(0) + dut.rxLinkUp.setimmediatevalue(1) + dut.S_CFG_IB_TVALID.setimmediatevalue(0) + dut.S_CFG_IB_TDATA.setimmediatevalue(0) + dut.S_CFG_IB_TKEEP.setimmediatevalue(0) + dut.S_CFG_IB_TLAST.setimmediatevalue(0) + dut.S_CFG_IB_TUSER.setimmediatevalue(0) + dut.M_CFG_OB_TREADY.setimmediatevalue(0) + dut.M_DATA_TREADY.setimmediatevalue(1) + dut.M_HDR_TREADY.setimmediatevalue(1) + await _reset_all(dut) + + axil = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "S_AXI"), dut.axilClk, dut.axilRst) + + reg_ff8 = await axil.read_dword(0xFF8) + await axil.write_dword(0xFF8, reg_ff8 | (1 << 26) | (1 << 27)) + updated_ff8 = await axil.read_dword(0xFF8) + assert (updated_ff8 >> 26) & 0x1 == 1 + assert (updated_ff8 >> 27) & 0x1 == 1 + + tid = 0x13579BDF + addr = 0x00000040 + request_payload = _words_to_payload([0x00000003, tid, addr, 0x00000000, 0x00000003]) + + tx_task = cocotb.start_soon(_collect_tx_bytes(dut, count=32)) + await _send_cfg_ib_frame(dut, request_payload) + + tx_bytes = await with_timeout(tx_task, 20, "us") + tx_payload = bytes(data for data, _ in tx_bytes) + expected_request = ( + bytes(word_to_bytes(CXP_SOP)) + + bytes([0x05] * 4) + + b"\x00\x00\x00\x00" + + bytes(word_to_bytes(0x04000000)) + + bytes(word_to_bytes(endian_swap32(addr))) + ) + request_start = _find_subsequence(tx_payload, expected_request) + assert request_start is not None, tx_payload + + +def test_CoaXPressCore(): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.coaxpresscorewrapper", + extra_vhdl_sources={ + "surf": [ + "protocols/coaxpress/core/rtl/CoaXPressPkg.vhd", + "protocols/coaxpress/core/rtl/CoaXPressEventAckMsg.vhd", + "protocols/coaxpress/core/rtl/CoaXPressTxLsFsm.vhd", + "protocols/coaxpress/core/rtl/CoaXPressTx.vhd", + "protocols/coaxpress/core/rtl/CoaXPressRxWordPacker.vhd", + "protocols/coaxpress/core/rtl/CoaXPressRxLaneMux.vhd", + "protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd", + "protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd", + "protocols/coaxpress/core/rtl/CoaXPressRx.vhd", + "protocols/coaxpress/core/rtl/CoaXPressConfig.vhd", + "protocols/coaxpress/core/rtl/CoaXPressAxiL.vhd", + "protocols/coaxpress/core/rtl/CoaXPressCore.vhd", + "protocols/coaxpress/core/wrappers/CoaXPressCoreWrapper.vhd", + ] + }, + ) diff --git a/tests/protocols/coaxpress/test_CoaXPressRx.py b/tests/protocols/coaxpress/test_CoaXPressRx.py new file mode 100644 index 0000000000..7007a0ce54 --- /dev/null +++ b/tests/protocols/coaxpress/test_CoaXPressRx.py @@ -0,0 +1,241 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Keep the first `CoaXPressRx` assembly pass on the stable one-lane +# path while still exercising all three externally visible outputs: config, +# image header/data, and the synchronized ACK/event sidebands. +# - Stimulus: Drive one control-ack packet, one event-ack packet, one `IO_ACK`, +# and one rectangular image transaction directly into the raw receive lane. +# - Checks: The assembled RX path must forward the config completion word, +# export the event tag, pulse `trigAck`, emit the seven 32-bit image-header +# words in order, and forward the programmed line payload with `SOF`/`TLAST` +# behavior preserved through the output FIFOs. +# - Timing: All DUT-visible domains are driven in lockstep so the bench checks +# the real FIFO/FSM sequencing without introducing unrelated clock skew. + +import cocotb +from cocotb.triggers import RisingEdge, Timer + +from tests.common.regression_utils import run_surf_vhdl_test, start_lockstep_clocks +from tests.protocols.coaxpress.coaxpress_test_utils import ( + CXP_IO_ACK, + CXP_MARKER, + CXP_PKT_CTRL_ACK_NO_TAG, + CXP_PKT_EVENT_ACK, + CXP_PKT_IMAGE_HEADER, + CXP_PKT_IMAGE_LINE, + CXP_SOP, + cycle, + repeat_byte, +) + + +HEADER_WORDS = [ + repeat_byte(0x12), + repeat_byte(0x34), + repeat_byte(0x56), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x03), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x04), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x01), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x05), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x03), + repeat_byte(0x00), + repeat_byte(0x10), + repeat_byte(0x00), + repeat_byte(0x20), + repeat_byte(0xAA), +] + +EXPECTED_HDR_WORDS = [ + 0x3456AA12, + 0x00000003, + 0x00000004, + 0x00000001, + 0x00000005, + 0x00000003, + 0x00200010, +] + + +async def _reset_all(dut) -> None: + dut.dataRst.value = 1 + dut.cfgRst.value = 1 + dut.txRst.value = 1 + dut.rxRst.value = 1 + await cycle(dut.rxClk, 4) + dut.dataRst.value = 0 + dut.cfgRst.value = 0 + dut.txRst.value = 0 + dut.rxRst.value = 0 + await cycle(dut.rxClk, 4) + + +async def _drive_rx_word(dut, *, data: int, data_k: int, link_up: int = 1) -> None: + dut.rxData.value = data + dut.rxDataK.value = data_k + dut.rxLinkUp.value = link_up + await RisingEdge(dut.rxClk) + await Timer(1, unit="ns") + + +def _capture_outputs( + dut, + *, + cfg_beats: list[tuple[int, int, int]], + data_beats: list[tuple[int, int, int, int]], + hdr_beats: list[tuple[int, int, int, int]], + event_tags: list[int], + trig_ack_cycles: list[int], + cycle_index: int, +) -> None: + if int(dut.cfgTValid.value) == 1: + cfg_beats.append((int(dut.cfgTData.value), int(dut.cfgTKeep.value), int(dut.cfgTLast.value))) + if int(dut.dataTValid.value) == 1: + data_beats.append( + ( + int(dut.dataTData.value), + int(dut.dataTKeep.value), + int(dut.dataTLast.value), + int(dut.dataTUser.value), + ) + ) + if int(dut.hdrTValid.value) == 1: + hdr_beats.append( + ( + int(dut.hdrTData.value), + int(dut.hdrTKeep.value), + int(dut.hdrTLast.value), + int(dut.hdrTUser.value), + ) + ) + if int(dut.eventAck.value) == 1: + event_tags.append(int(dut.eventTag.value)) + if int(dut.trigAck.value) == 1: + trig_ack_cycles.append(cycle_index) + + +@cocotb.test() +async def coaxpress_rx_one_lane_integration_test(dut): + start_lockstep_clocks(dut.dataClk, dut.cfgClk, dut.txClk, dut.rxClk, period_ns=4.0) + dut.rxData.setimmediatevalue(0) + dut.rxDataK.setimmediatevalue(0) + dut.rxLinkUp.setimmediatevalue(1) + dut.rxFsmRst.setimmediatevalue(0) + dut.rxNumberOfLane.setimmediatevalue(0) + dut.dataTReady.setimmediatevalue(1) + dut.hdrTReady.setimmediatevalue(1) + await _reset_all(dut) + + cfg_beats: list[tuple[int, int, int]] = [] + data_beats: list[tuple[int, int, int, int]] = [] + hdr_beats: list[tuple[int, int, int, int]] = [] + event_tags: list[int] = [] + trig_ack_cycles: list[int] = [] + + sequence = [ + (CXP_SOP, 0xF), + (repeat_byte(CXP_PKT_CTRL_ACK_NO_TAG), 0x0), + (repeat_byte(0x00), 0x0), + (0xCAFEBABE, 0x0), + (0x01234567, 0x0), + (CXP_SOP, 0xF), + (repeat_byte(CXP_PKT_EVENT_ACK), 0x0), + (repeat_byte(0x10), 0x0), + (repeat_byte(0x11), 0x0), + (repeat_byte(0x12), 0x0), + (repeat_byte(0x13), 0x0), + (repeat_byte(0x5A), 0x0), + (CXP_IO_ACK, 0xF), + (repeat_byte(0x01), 0x0), + (CXP_SOP, 0xF), + (repeat_byte(0x01), 0x0), + (repeat_byte(0x22), 0x0), + (repeat_byte(0x33), 0x0), + (repeat_byte(0x00), 0x0), + (repeat_byte(25), 0x0), + (CXP_MARKER, 0xF), + (repeat_byte(CXP_PKT_IMAGE_HEADER), 0x0), + *[(word, 0xF) for word in HEADER_WORDS], + (CXP_SOP, 0xF), + (repeat_byte(0x01), 0x0), + (repeat_byte(0x44), 0x0), + (repeat_byte(0x55), 0x0), + (repeat_byte(0x00), 0x0), + (repeat_byte(5), 0x0), + (CXP_MARKER, 0xF), + (repeat_byte(CXP_PKT_IMAGE_LINE), 0x0), + (0x11111111, 0x0), + (0x22222222, 0x0), + (0x33333333, 0x0), + ] + + for cycle_index, (data, data_k) in enumerate(sequence): + await _drive_rx_word(dut, data=data, data_k=data_k) + _capture_outputs( + dut, + cfg_beats=cfg_beats, + data_beats=data_beats, + hdr_beats=hdr_beats, + event_tags=event_tags, + trig_ack_cycles=trig_ack_cycles, + cycle_index=cycle_index, + ) + + for cycle_index in range(40): + await _drive_rx_word(dut, data=0xB53C3CBC, data_k=0x7) + _capture_outputs( + dut, + cfg_beats=cfg_beats, + data_beats=data_beats, + hdr_beats=hdr_beats, + event_tags=event_tags, + trig_ack_cycles=trig_ack_cycles, + cycle_index=cycle_index + len(sequence), + ) + + assert cfg_beats == [(0x0123456700000000, 0xFF, 0)] + assert event_tags == [0x5A] + assert trig_ack_cycles + assert [beat[:3] for beat in hdr_beats] == [(word, 0xF, 1 if index == len(EXPECTED_HDR_WORDS) - 1 else 0) for index, word in enumerate(EXPECTED_HDR_WORDS)] + assert [beat[0] for beat in hdr_beats] == EXPECTED_HDR_WORDS + assert data_beats == [ + (0x11111111, 0xF, 0, 0), + (0x22222222, 0xF, 0, 0), + (0x33333333, 0xF, 1, 0), + ] + + +def test_CoaXPressRx(): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.coaxpressrxwrapper", + extra_vhdl_sources={ + "surf": [ + "protocols/coaxpress/core/rtl/CoaXPressPkg.vhd", + "protocols/coaxpress/core/rtl/CoaXPressRxWordPacker.vhd", + "protocols/coaxpress/core/rtl/CoaXPressRxLaneMux.vhd", + "protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd", + "protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd", + "protocols/coaxpress/core/rtl/CoaXPressRx.vhd", + "protocols/coaxpress/core/wrappers/CoaXPressRxWrapper.vhd", + ] + }, + ) From 8ab2829a817205969deedec747058ef0a03757a5 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 20 Apr 2026 12:50:53 -0700 Subject: [PATCH 31/92] Refactor. --- .../coaxpress/coaxpress_test_utils.py | 96 ++++++++++- .../coaxpress/test_CoaXPressConfig.py | 153 +++++++++--------- .../protocols/coaxpress/test_CoaXPressCore.py | 135 +++++++--------- .../test_CoaXPressOverFiberBridge.py | 55 +++---- tests/protocols/coaxpress/test_CoaXPressRx.py | 102 ++++++------ tests/protocols/coaxpress/test_CoaXPressTx.py | 84 +++++----- 6 files changed, 333 insertions(+), 292 deletions(-) diff --git a/tests/protocols/coaxpress/coaxpress_test_utils.py b/tests/protocols/coaxpress/coaxpress_test_utils.py index fb4dc93d87..1be249f00a 100644 --- a/tests/protocols/coaxpress/coaxpress_test_utils.py +++ b/tests/protocols/coaxpress/coaxpress_test_utils.py @@ -11,9 +11,11 @@ from __future__ import annotations from dataclasses import dataclass +from typing import Sequence, TypeVar import cocotb from cocotb.clock import Clock +from cocotb.handle import Immediate from cocotb.triggers import RisingEdge, Timer @@ -74,6 +76,10 @@ def pack_bytes(payload: bytes, *, width_bytes: int) -> int: return int.from_bytes(payload.ljust(width_bytes, b"\x00"), "little") +def pack_u32_words_le(words: list[int]) -> bytes: + return b"".join((word & 0xFFFFFFFF).to_bytes(4, "little") for word in words) + + def unpack_kept_bytes(data: int, keep: int, *, width_bytes: int) -> bytes: lanes = word_to_bytes(data, byte_count=width_bytes) return bytes(byte for index, byte in enumerate(lanes) if (keep >> index) & 0x1) @@ -106,20 +112,29 @@ def start_clock(signal, *, period_ns: float = 5.0) -> None: cocotb.start_soon(Clock(signal, period_ns, unit="ns").start()) +def set_initial_values(dut, values: dict[str, int]) -> None: + for signal_name, value in values.items(): + getattr(dut, signal_name).value = Immediate(value) + + async def cycle(clk, count: int = 1) -> None: for _ in range(count): await RisingEdge(clk) await Timer(1, unit="ns") -async def reset_dut(dut, *, clk_name: str = "rxClk", reset_names: tuple[str, ...] = ("rxRst",)) -> None: - clk = getattr(dut, clk_name) +async def reset_signals(dut, *, clk, reset_names: tuple[str, ...], assert_cycles: int = 4, release_cycles: int = 2) -> None: for reset_name in reset_names: - getattr(dut, reset_name).setimmediatevalue(1) - await cycle(clk, 4) + getattr(dut, reset_name).value = Immediate(1) + await cycle(clk, assert_cycles) for reset_name in reset_names: getattr(dut, reset_name).value = 0 - await cycle(clk, 2) + await cycle(clk, release_cycles) + + +async def reset_dut(dut, *, clk_name: str = "rxClk", reset_names: tuple[str, ...] = ("rxRst",)) -> None: + clk = getattr(dut, clk_name) + await reset_signals(dut, clk=clk, reset_names=reset_names) def pulse_snapshot(dut, *, valid_name: str, field_names: tuple[str, ...]) -> dict[str, int] | None: @@ -128,6 +143,18 @@ def pulse_snapshot(dut, *, valid_name: str, field_names: tuple[str, ...]) -> dic return {field_name: int(getattr(dut, field_name).value) for field_name in field_names} +def append_snapshot_if_valid( + target: list[dict[str, int]], + dut, + *, + valid_name: str, + field_names: tuple[str, ...], +) -> None: + snapshot = pulse_snapshot(dut, valid_name=valid_name, field_names=field_names) + if snapshot is not None: + target.append(snapshot) + + async def send_rx_word( dut, *, @@ -150,6 +177,65 @@ async def send_rx_word( capture.append(snapshot) +async def send_axis_payload( + dut, + *, + clk, + prefix: str, + payload: bytes, + width_bytes: int, + tuser: int = 0, +) -> None: + getattr(dut, f"{prefix}_TVALID").value = 1 + getattr(dut, f"{prefix}_TDATA").value = pack_bytes(payload, width_bytes=width_bytes) + getattr(dut, f"{prefix}_TKEEP").value = (1 << len(payload)) - 1 + getattr(dut, f"{prefix}_TLAST").value = 1 + getattr(dut, f"{prefix}_TUSER").value = tuser + while True: + await RisingEdge(clk) + await Timer(1, unit="ns") + if int(getattr(dut, f"{prefix}_TREADY").value) == 1: + break + getattr(dut, f"{prefix}_TVALID").value = 0 + getattr(dut, f"{prefix}_TDATA").value = 0 + getattr(dut, f"{prefix}_TKEEP").value = 0 + getattr(dut, f"{prefix}_TLAST").value = 0 + getattr(dut, f"{prefix}_TUSER").value = 0 + + +async def collect_stream_bytes( + dut, + *, + clk, + valid_name: str, + data_name: str, + count: int, + timeout_cycles: int, + ready_name: str | None = None, +) -> bytes: + payload = bytearray() + if ready_name is not None: + getattr(dut, ready_name).value = 1 + for _ in range(timeout_cycles): + await RisingEdge(clk) + await Timer(1, unit="ns") + if int(getattr(dut, valid_name).value) == 1: + payload.append(int(getattr(dut, data_name).value)) + if len(payload) >= count: + return bytes(payload) + raise AssertionError(f"Timed out waiting for {count} bytes on {data_name}") + + +_T = TypeVar("_T") + + +def find_subsequence(sequence: Sequence[_T], expected: Sequence[_T]) -> int | None: + for start in range(len(sequence) - len(expected) + 1): + if list(sequence[start : start + len(expected)]) == list(expected): + return start + return None + + async def send_axis_beats_no_ready( dut, *, diff --git a/tests/protocols/coaxpress/test_CoaXPressConfig.py b/tests/protocols/coaxpress/test_CoaXPressConfig.py index 4d7a86374e..9c78aee9b5 100644 --- a/tests/protocols/coaxpress/test_CoaXPressConfig.py +++ b/tests/protocols/coaxpress/test_CoaXPressConfig.py @@ -28,8 +28,13 @@ from tests.protocols.coaxpress.coaxpress_test_utils import ( CXP_EOP, CXP_SOP, + collect_stream_bytes, endian_swap32, - pack_bytes, + pack_u32_words_le, + reset_signals, + send_axis_payload, + set_initial_values, + start_clock, word_to_bytes, ) @@ -52,52 +57,6 @@ def _srp_request_words(*, opcode: int, tid: int, addr: int, req_size: int, write return words -def _words_to_payload(words: list[int]) -> bytes: - return b"".join((word & 0xFFFFFFFF).to_bytes(4, "little") for word in words) - - -def _payload_to_words(payload: bytes) -> list[int]: - return [int.from_bytes(payload[index : index + 4], "little") for index in range(0, len(payload), 4)] - - -async def _reset_cfg_domain(dut) -> None: - dut.cfgRst.value = 1 - await Timer(40, unit="ns") - dut.cfgRst.value = 0 - await Timer(20, unit="ns") - - -async def _send_cfg_ib_frame(dut, payload: bytes, *, tuser: int = 0x2) -> None: - dut.S_CFG_IB_TVALID.value = 1 - dut.S_CFG_IB_TDATA.value = pack_bytes(payload, width_bytes=32) - dut.S_CFG_IB_TKEEP.value = (1 << len(payload)) - 1 - dut.S_CFG_IB_TLAST.value = 1 - dut.S_CFG_IB_TUSER.value = tuser - while True: - await RisingEdge(dut.cfgClk) - await Timer(1, unit="ns") - if int(dut.S_CFG_IB_TREADY.value) == 1: - break - dut.S_CFG_IB_TVALID.value = 0 - dut.S_CFG_IB_TDATA.value = 0 - dut.S_CFG_IB_TKEEP.value = 0 - dut.S_CFG_IB_TLAST.value = 0 - dut.S_CFG_IB_TUSER.value = 0 - - -async def _collect_tx_bytes(dut, *, count: int, timeout_cycles: int = 8000) -> bytes: - payload = bytearray() - dut.M_CFG_TX_TREADY.value = 1 - for _ in range(timeout_cycles): - await RisingEdge(dut.cfgClk) - await Timer(1, unit="ns") - if int(dut.M_CFG_TX_TVALID.value) == 1: - payload.append(int(dut.M_CFG_TX_TDATA.value)) - if len(payload) >= count: - return bytes(payload) - raise AssertionError(f"Timed out waiting for {count} CoaXPress config TX bytes") - - async def _drive_cfg_rx_completion(dut, value: int, *, hold_cycles: int = 8) -> None: dut.cfgRxTData.value = value dut.cfgRxTValid.value = 1 @@ -110,28 +69,45 @@ async def _drive_cfg_rx_completion(dut, value: int, *, hold_cycles: int = 8) -> @cocotb.test() async def coaxpress_config_untagged_read_request_test(dut): - cocotb.start_soon(cocotb.clock.Clock(dut.cfgClk, 4, unit="ns").start()) - dut.S_CFG_IB_TVALID.setimmediatevalue(0) - dut.S_CFG_IB_TDATA.setimmediatevalue(0) - dut.S_CFG_IB_TKEEP.setimmediatevalue(0) - dut.S_CFG_IB_TLAST.setimmediatevalue(0) - dut.S_CFG_IB_TUSER.setimmediatevalue(0) - dut.M_CFG_OB_TREADY.setimmediatevalue(1) - dut.M_CFG_TX_TREADY.setimmediatevalue(0) - dut.cfgRxTValid.setimmediatevalue(0) - dut.cfgRxTData.setimmediatevalue(0) - dut.configTimerSize.setimmediatevalue(4096) - dut.configErrResp.setimmediatevalue(1) - dut.configPktTag.setimmediatevalue(0) - await _reset_cfg_domain(dut) + start_clock(dut.cfgClk, period_ns=4.0) + set_initial_values( + dut, + { + "S_CFG_IB_TVALID": 0, + "S_CFG_IB_TDATA": 0, + "S_CFG_IB_TKEEP": 0, + "S_CFG_IB_TLAST": 0, + "S_CFG_IB_TUSER": 0, + "M_CFG_OB_TREADY": 1, + "M_CFG_TX_TREADY": 0, + "cfgRxTValid": 0, + "cfgRxTData": 0, + "configTimerSize": 4096, + "configErrResp": 1, + "configPktTag": 0, + }, + ) + await reset_signals(dut, clk=dut.cfgClk, reset_names=("cfgRst",), assert_cycles=10, release_cycles=5) tid = 0x12345678 addr = 0x00000040 read_data = 0xDDAA5501 - request_payload = _words_to_payload(_srp_request_words(opcode=READ_OPCODE, tid=tid, addr=addr, req_size=0x00000003)) + request_payload = pack_u32_words_le( + _srp_request_words(opcode=READ_OPCODE, tid=tid, addr=addr, req_size=0x00000003) + ) - tx_task = cocotb.start_soon(_collect_tx_bytes(dut, count=24)) - await _send_cfg_ib_frame(dut, request_payload) + tx_task = cocotb.start_soon( + collect_stream_bytes( + dut, + clk=dut.cfgClk, + valid_name="M_CFG_TX_TVALID", + data_name="M_CFG_TX_TDATA", + ready_name="M_CFG_TX_TREADY", + count=24, + timeout_cycles=8000, + ) + ) + await send_axis_payload(dut, clk=dut.cfgClk, prefix="S_CFG_IB", payload=request_payload, width_bytes=32, tuser=0x2) tx_bytes = await with_timeout(tx_task, 20, "us") @@ -149,20 +125,25 @@ async def coaxpress_config_untagged_read_request_test(dut): @cocotb.test() async def coaxpress_config_tagged_write_tag_increment_test(dut): - cocotb.start_soon(cocotb.clock.Clock(dut.cfgClk, 4, unit="ns").start()) - dut.S_CFG_IB_TVALID.setimmediatevalue(0) - dut.S_CFG_IB_TDATA.setimmediatevalue(0) - dut.S_CFG_IB_TKEEP.setimmediatevalue(0) - dut.S_CFG_IB_TLAST.setimmediatevalue(0) - dut.S_CFG_IB_TUSER.setimmediatevalue(0) - dut.M_CFG_OB_TREADY.setimmediatevalue(1) - dut.M_CFG_TX_TREADY.setimmediatevalue(0) - dut.cfgRxTValid.setimmediatevalue(0) - dut.cfgRxTData.setimmediatevalue(0) - dut.configTimerSize.setimmediatevalue(4096) - dut.configErrResp.setimmediatevalue(1) - dut.configPktTag.setimmediatevalue(1) - await _reset_cfg_domain(dut) + start_clock(dut.cfgClk, period_ns=4.0) + set_initial_values( + dut, + { + "S_CFG_IB_TVALID": 0, + "S_CFG_IB_TDATA": 0, + "S_CFG_IB_TKEEP": 0, + "S_CFG_IB_TLAST": 0, + "S_CFG_IB_TUSER": 0, + "M_CFG_OB_TREADY": 1, + "M_CFG_TX_TREADY": 0, + "cfgRxTValid": 0, + "cfgRxTData": 0, + "configTimerSize": 4096, + "configErrResp": 1, + "configPktTag": 1, + }, + ) + await reset_signals(dut, clk=dut.cfgClk, reset_names=("cfgRst",), assert_cycles=10, release_cycles=5) requests = [ (0x0BADB002, 0x00000020, 0x11223344, 0x00), @@ -170,12 +151,22 @@ async def coaxpress_config_tagged_write_tag_increment_test(dut): ] for tid, addr, write_data, expected_tag in requests: - request_payload = _words_to_payload( + request_payload = pack_u32_words_le( _srp_request_words(opcode=WRITE_OPCODE, tid=tid, addr=addr, req_size=0x00000003, write_data=write_data) ) - tx_task = cocotb.start_soon(_collect_tx_bytes(dut, count=32)) - await _send_cfg_ib_frame(dut, request_payload) + tx_task = cocotb.start_soon( + collect_stream_bytes( + dut, + clk=dut.cfgClk, + valid_name="M_CFG_TX_TVALID", + data_name="M_CFG_TX_TDATA", + ready_name="M_CFG_TX_TREADY", + count=32, + timeout_cycles=8000, + ) + ) + await send_axis_payload(dut, clk=dut.cfgClk, prefix="S_CFG_IB", payload=request_payload, width_bytes=32, tuser=0x2) tx_bytes = await with_timeout(tx_task, 20, "us") assert tx_bytes[:4] == bytes(word_to_bytes(CXP_SOP)) diff --git a/tests/protocols/coaxpress/test_CoaXPressCore.py b/tests/protocols/coaxpress/test_CoaXPressCore.py index da0f0250a3..31051e28be 100644 --- a/tests/protocols/coaxpress/test_CoaXPressCore.py +++ b/tests/protocols/coaxpress/test_CoaXPressCore.py @@ -23,88 +23,53 @@ # `CoaXPressAxiL`, `CoaXPressConfig`, and `CoaXPressTx`. import cocotb -from cocotb.triggers import RisingEdge, Timer, with_timeout +from cocotb.triggers import with_timeout from cocotbext.axi import AxiLiteBus, AxiLiteMaster from tests.common.regression_utils import run_surf_vhdl_test, start_lockstep_clocks -from tests.protocols.coaxpress.coaxpress_test_utils import CXP_SOP, endian_swap32, pack_bytes, word_to_bytes - - -def _words_to_payload(words: list[int]) -> bytes: - return b"".join((word & 0xFFFFFFFF).to_bytes(4, "little") for word in words) - - -async def _reset_all(dut) -> None: - dut.dataRst.value = 1 - dut.cfgRst.value = 1 - dut.txRst.value = 1 - dut.rxRst.value = 1 - dut.axilRst.value = 1 - await Timer(40, unit="ns") - dut.dataRst.value = 0 - dut.cfgRst.value = 0 - dut.txRst.value = 0 - dut.rxRst.value = 0 - dut.axilRst.value = 0 - await Timer(20, unit="ns") - - -async def _send_cfg_ib_frame(dut, payload: bytes) -> None: - dut.S_CFG_IB_TVALID.value = 1 - dut.S_CFG_IB_TDATA.value = pack_bytes(payload, width_bytes=32) - dut.S_CFG_IB_TKEEP.value = (1 << len(payload)) - 1 - dut.S_CFG_IB_TLAST.value = 1 - dut.S_CFG_IB_TUSER.value = 0x2 - while True: - await RisingEdge(dut.cfgClk) - await Timer(1, unit="ns") - if int(dut.S_CFG_IB_TREADY.value) == 1: - break - dut.S_CFG_IB_TVALID.value = 0 - dut.S_CFG_IB_TDATA.value = 0 - dut.S_CFG_IB_TKEEP.value = 0 - dut.S_CFG_IB_TLAST.value = 0 - dut.S_CFG_IB_TUSER.value = 0 - - -async def _collect_tx_bytes(dut, *, count: int, timeout_cycles: int = 12000) -> list[tuple[int, int]]: - observed: list[tuple[int, int]] = [] - for _ in range(timeout_cycles): - await RisingEdge(dut.txClk) - await Timer(1, unit="ns") - if int(dut.txLsValid.value) == 1: - observed.append((int(dut.txLsData.value), int(dut.txLsDataK.value))) - if len(observed) >= count: - return observed - raise AssertionError("Timed out waiting for CoaXPressCore TX bytes") - - -def _find_subsequence(payload: bytes, expected: bytes) -> int | None: - for start in range(len(payload) - len(expected) + 1): - if payload[start : start + len(expected)] == expected: - return start - return None +from tests.protocols.coaxpress.coaxpress_test_utils import ( + CXP_SOP, + collect_stream_bytes, + endian_swap32, + find_subsequence, + pack_u32_words_le, + reset_signals, + send_axis_payload, + set_initial_values, + word_to_bytes, +) @cocotb.test() async def coaxpress_core_tagged_config_tx_path_test(dut): start_lockstep_clocks(dut.dataClk, dut.cfgClk, dut.txClk, dut.rxClk, dut.axilClk, period_ns=4.0) - dut.txTrig.setimmediatevalue(0) - dut.txLinkUp.setimmediatevalue(1) - dut.rxData.setimmediatevalue(0xB53C3CBC) - dut.rxDataK.setimmediatevalue(0x7) - dut.rxDispErr.setimmediatevalue(0) - dut.rxDecErr.setimmediatevalue(0) - dut.rxLinkUp.setimmediatevalue(1) - dut.S_CFG_IB_TVALID.setimmediatevalue(0) - dut.S_CFG_IB_TDATA.setimmediatevalue(0) - dut.S_CFG_IB_TKEEP.setimmediatevalue(0) - dut.S_CFG_IB_TLAST.setimmediatevalue(0) - dut.S_CFG_IB_TUSER.setimmediatevalue(0) - dut.M_CFG_OB_TREADY.setimmediatevalue(0) - dut.M_DATA_TREADY.setimmediatevalue(1) - dut.M_HDR_TREADY.setimmediatevalue(1) - await _reset_all(dut) + set_initial_values( + dut, + { + "txTrig": 0, + "txLinkUp": 1, + "rxData": 0xB53C3CBC, + "rxDataK": 0x7, + "rxDispErr": 0, + "rxDecErr": 0, + "rxLinkUp": 1, + "S_CFG_IB_TVALID": 0, + "S_CFG_IB_TDATA": 0, + "S_CFG_IB_TKEEP": 0, + "S_CFG_IB_TLAST": 0, + "S_CFG_IB_TUSER": 0, + "M_CFG_OB_TREADY": 0, + "M_DATA_TREADY": 1, + "M_HDR_TREADY": 1, + }, + ) + await reset_signals( + dut, + clk=dut.rxClk, + reset_names=("dataRst", "cfgRst", "txRst", "rxRst", "axilRst"), + assert_cycles=10, + release_cycles=5, + ) axil = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "S_AXI"), dut.axilClk, dut.axilRst) @@ -116,13 +81,21 @@ async def coaxpress_core_tagged_config_tx_path_test(dut): tid = 0x13579BDF addr = 0x00000040 - request_payload = _words_to_payload([0x00000003, tid, addr, 0x00000000, 0x00000003]) - - tx_task = cocotb.start_soon(_collect_tx_bytes(dut, count=32)) - await _send_cfg_ib_frame(dut, request_payload) + request_payload = pack_u32_words_le([0x00000003, tid, addr, 0x00000000, 0x00000003]) + + tx_task = cocotb.start_soon( + collect_stream_bytes( + dut, + clk=dut.txClk, + valid_name="txLsValid", + data_name="txLsData", + count=32, + timeout_cycles=12000, + ) + ) + await send_axis_payload(dut, clk=dut.cfgClk, prefix="S_CFG_IB", payload=request_payload, width_bytes=32, tuser=0x2) tx_bytes = await with_timeout(tx_task, 20, "us") - tx_payload = bytes(data for data, _ in tx_bytes) expected_request = ( bytes(word_to_bytes(CXP_SOP)) + bytes([0x05] * 4) @@ -130,8 +103,8 @@ async def coaxpress_core_tagged_config_tx_path_test(dut): + bytes(word_to_bytes(0x04000000)) + bytes(word_to_bytes(endian_swap32(addr))) ) - request_start = _find_subsequence(tx_payload, expected_request) - assert request_start is not None, tx_payload + request_start = find_subsequence(tx_bytes, expected_request) + assert request_start is not None, tx_bytes def test_CoaXPressCore(): diff --git a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridge.py b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridge.py index e71e1e63f3..22306063e2 100644 --- a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridge.py +++ b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridge.py @@ -24,7 +24,6 @@ # checks robust to gearbox latency while still validating real output order. import cocotb -from cocotb.clock import Clock from cocotb.triggers import RisingEdge, Timer from tests.common.regression_utils import run_surf_vhdl_test @@ -38,7 +37,11 @@ CXPOF_START, CXPOF_TERM, cycle, + find_subsequence, + reset_signals, repeat_byte, + set_initial_values, + start_clock, ) @@ -49,42 +52,30 @@ def _tx_start_word(rate: int, update: int) -> int: def _rx_start_word(packet_byte: int) -> int: return CXPOF_START | (0x80 << 8) | ((CXP_SOP & 0xFF) << 16) | (packet_byte << 24) - -def _find_subsequence(observed: list[tuple[int, int]], expected: list[tuple[int, int]]) -> int | None: - for start in range(len(observed) - len(expected) + 1): - if observed[start : start + len(expected)] == expected: - return start - return None - - -async def _reset_domains(dut) -> None: - dut.txRst312.value = 1 - dut.rxRst312.value = 1 - await Timer(40, unit="ns") - dut.txRst312.value = 0 - dut.rxRst312.value = 0 - await Timer(20, unit="ns") - - @cocotb.test() async def coaxpress_over_fiber_bridge_top_level_integration_test(dut): # Run the 312 MHz and 156 MHz domains at a 2:1 ratio so the async gearboxes # see the intended width-conversion cadence while still operating on # independent clocks. - cocotb.start_soon(Clock(dut.txClk312, 4, unit="ns").start()) - cocotb.start_soon(Clock(dut.txClk156, 8, unit="ns").start()) - cocotb.start_soon(Clock(dut.rxClk312, 4, unit="ns").start()) - cocotb.start_soon(Clock(dut.rxClk156, 8, unit="ns").start()) + start_clock(dut.txClk312, period_ns=4.0) + start_clock(dut.txClk156, period_ns=8.0) + start_clock(dut.rxClk312, period_ns=4.0) + start_clock(dut.rxClk156, period_ns=8.0) idle64 = int.from_bytes(bytes([CXPOF_IDLE] * 8), "little") - dut.txLsValid.setimmediatevalue(0) - dut.txLsData.setimmediatevalue(0) - dut.txLsDataK.setimmediatevalue(0) - dut.txLsLaneEn.setimmediatevalue(0xF) - dut.txLsRate.setimmediatevalue(1) - dut.xgmiiRxd.setimmediatevalue(idle64) - dut.xgmiiRxc.setimmediatevalue(0xFF) - await _reset_domains(dut) + set_initial_values( + dut, + { + "txLsValid": 0, + "txLsData": 0, + "txLsDataK": 0, + "txLsLaneEn": 0xF, + "txLsRate": 1, + "xgmiiRxd": idle64, + "xgmiiRxc": 0xFF, + }, + ) + await reset_signals(dut, clk=dut.txClk312, reset_names=("txRst312", "rxRst312"), assert_cycles=10, release_cycles=5) await cycle(dut.txClk312, 6) await cycle(dut.rxClk156, 2) @@ -143,8 +134,8 @@ async def capture_rx_words(cycles: int) -> None: (CXP_EOP, 0xF), ] - assert _find_subsequence(tx_observed, tx_expected) is not None, f"missing TX gearbox sequence in observed stream: {tx_observed}" - assert _find_subsequence(rx_observed, rx_expected) is not None, f"missing RX gearbox sequence in observed stream: {rx_observed}" + assert find_subsequence(tx_observed, tx_expected) is not None, f"missing TX gearbox sequence in observed stream: {tx_observed}" + assert find_subsequence(rx_observed, rx_expected) is not None, f"missing RX gearbox sequence in observed stream: {rx_observed}" def test_CoaXPressOverFiberBridge(): diff --git a/tests/protocols/coaxpress/test_CoaXPressRx.py b/tests/protocols/coaxpress/test_CoaXPressRx.py index 7007a0ce54..0e19cc6ebe 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRx.py +++ b/tests/protocols/coaxpress/test_CoaXPressRx.py @@ -22,7 +22,6 @@ # the real FIFO/FSM sequencing without introducing unrelated clock skew. import cocotb -from cocotb.triggers import RisingEdge, Timer from tests.common.regression_utils import run_surf_vhdl_test, start_lockstep_clocks from tests.protocols.coaxpress.coaxpress_test_utils import ( @@ -33,8 +32,11 @@ CXP_PKT_IMAGE_HEADER, CXP_PKT_IMAGE_LINE, CXP_SOP, - cycle, + append_snapshot_if_valid, + reset_signals, repeat_byte, + send_rx_word, + set_initial_values, ) @@ -74,28 +76,6 @@ 0x00200010, ] - -async def _reset_all(dut) -> None: - dut.dataRst.value = 1 - dut.cfgRst.value = 1 - dut.txRst.value = 1 - dut.rxRst.value = 1 - await cycle(dut.rxClk, 4) - dut.dataRst.value = 0 - dut.cfgRst.value = 0 - dut.txRst.value = 0 - dut.rxRst.value = 0 - await cycle(dut.rxClk, 4) - - -async def _drive_rx_word(dut, *, data: int, data_k: int, link_up: int = 1) -> None: - dut.rxData.value = data - dut.rxDataK.value = data_k - dut.rxLinkUp.value = link_up - await RisingEdge(dut.rxClk) - await Timer(1, unit="ns") - - def _capture_outputs( dut, *, @@ -106,26 +86,29 @@ def _capture_outputs( trig_ack_cycles: list[int], cycle_index: int, ) -> None: - if int(dut.cfgTValid.value) == 1: - cfg_beats.append((int(dut.cfgTData.value), int(dut.cfgTKeep.value), int(dut.cfgTLast.value))) - if int(dut.dataTValid.value) == 1: - data_beats.append( - ( - int(dut.dataTData.value), - int(dut.dataTKeep.value), - int(dut.dataTLast.value), - int(dut.dataTUser.value), - ) - ) - if int(dut.hdrTValid.value) == 1: - hdr_beats.append( - ( - int(dut.hdrTData.value), - int(dut.hdrTKeep.value), - int(dut.hdrTLast.value), - int(dut.hdrTUser.value), - ) - ) + cfg_samples: list[dict[str, int]] = [] + data_samples: list[dict[str, int]] = [] + hdr_samples: list[dict[str, int]] = [] + append_snapshot_if_valid(cfg_samples, dut, valid_name="cfgTValid", field_names=("cfgTData", "cfgTKeep", "cfgTLast")) + append_snapshot_if_valid( + data_samples, + dut, + valid_name="dataTValid", + field_names=("dataTData", "dataTKeep", "dataTLast", "dataTUser"), + ) + append_snapshot_if_valid( + hdr_samples, + dut, + valid_name="hdrTValid", + field_names=("hdrTData", "hdrTKeep", "hdrTLast", "hdrTUser"), + ) + cfg_beats.extend((sample["cfgTData"], sample["cfgTKeep"], sample["cfgTLast"]) for sample in cfg_samples) + data_beats.extend( + (sample["dataTData"], sample["dataTKeep"], sample["dataTLast"], sample["dataTUser"]) for sample in data_samples + ) + hdr_beats.extend( + (sample["hdrTData"], sample["hdrTKeep"], sample["hdrTLast"], sample["hdrTUser"]) for sample in hdr_samples + ) if int(dut.eventAck.value) == 1: event_tags.append(int(dut.eventTag.value)) if int(dut.trigAck.value) == 1: @@ -135,14 +118,25 @@ def _capture_outputs( @cocotb.test() async def coaxpress_rx_one_lane_integration_test(dut): start_lockstep_clocks(dut.dataClk, dut.cfgClk, dut.txClk, dut.rxClk, period_ns=4.0) - dut.rxData.setimmediatevalue(0) - dut.rxDataK.setimmediatevalue(0) - dut.rxLinkUp.setimmediatevalue(1) - dut.rxFsmRst.setimmediatevalue(0) - dut.rxNumberOfLane.setimmediatevalue(0) - dut.dataTReady.setimmediatevalue(1) - dut.hdrTReady.setimmediatevalue(1) - await _reset_all(dut) + set_initial_values( + dut, + { + "rxData": 0, + "rxDataK": 0, + "rxLinkUp": 1, + "rxFsmRst": 0, + "rxNumberOfLane": 0, + "dataTReady": 1, + "hdrTReady": 1, + }, + ) + await reset_signals( + dut, + clk=dut.rxClk, + reset_names=("dataRst", "cfgRst", "txRst", "rxRst"), + assert_cycles=4, + release_cycles=4, + ) cfg_beats: list[tuple[int, int, int]] = [] data_beats: list[tuple[int, int, int, int]] = [] @@ -188,7 +182,7 @@ async def coaxpress_rx_one_lane_integration_test(dut): ] for cycle_index, (data, data_k) in enumerate(sequence): - await _drive_rx_word(dut, data=data, data_k=data_k) + await send_rx_word(dut, data=data, data_k=data_k, clk=dut.rxClk) _capture_outputs( dut, cfg_beats=cfg_beats, @@ -200,7 +194,7 @@ async def coaxpress_rx_one_lane_integration_test(dut): ) for cycle_index in range(40): - await _drive_rx_word(dut, data=0xB53C3CBC, data_k=0x7) + await send_rx_word(dut, data=0xB53C3CBC, data_k=0x7, clk=dut.rxClk) _capture_outputs( dut, cfg_beats=cfg_beats, diff --git a/tests/protocols/coaxpress/test_CoaXPressTx.py b/tests/protocols/coaxpress/test_CoaXPressTx.py index d2d6ba79ef..00dd7426f3 100644 --- a/tests/protocols/coaxpress/test_CoaXPressTx.py +++ b/tests/protocols/coaxpress/test_CoaXPressTx.py @@ -24,7 +24,6 @@ # trigger windows rather than assuming zero-latency handoff across modules. import cocotb -from cocotb.clock import Clock from cocotb.triggers import RisingEdge, Timer from tests.common.regression_utils import run_surf_vhdl_test @@ -38,6 +37,9 @@ CXP_EOP, CXP_SOP, cycle, + find_subsequence, + set_initial_values, + start_clock, word_to_bytes, ) @@ -110,33 +112,29 @@ async def _collect_tx_bytes(dut, *, count: int, timeout_cycles: int) -> tuple[li return observed, tx_trig_drop_seen raise AssertionError(f"Timed out waiting for {count} CoaXPress TX bytes, saw {len(observed)}") - -def _find_subsequence(observed: list[tuple[int, int, int]], expected: list[tuple[int, int]]) -> int | None: - payload = [(data, is_k) for _, data, is_k in observed] - for start in range(len(payload) - len(expected) + 1): - if payload[start : start + len(expected)] == expected: - return start - return None - - @cocotb.test() async def coaxpress_tx_config_and_event_ack_test(dut): # Hold the assembly in reset long enough for both domains to settle, then # prove that a config packet already in flight is preserved ahead of a # later event-ack packet through the mux and CDC FIFO. - cocotb.start_soon(Clock(dut.cfgClk, 6, unit="ns").start()) - cocotb.start_soon(Clock(dut.txClk, 4, unit="ns").start()) - dut.cfgTValid.setimmediatevalue(0) - dut.cfgTData.setimmediatevalue(0) - dut.cfgTUser.setimmediatevalue(0) - dut.cfgTLast.setimmediatevalue(0) - dut.eventAck.setimmediatevalue(0) - dut.eventTag.setimmediatevalue(0) - dut.txLsRate.setimmediatevalue(1) - dut.txTrigInv.setimmediatevalue(0) - dut.txPulseWidth.setimmediatevalue(500) - dut.swTrig.setimmediatevalue(0) - dut.txTrig.setimmediatevalue(0) + start_clock(dut.cfgClk, period_ns=6.0) + start_clock(dut.txClk, period_ns=4.0) + set_initial_values( + dut, + { + "cfgTValid": 0, + "cfgTData": 0, + "cfgTUser": 0, + "cfgTLast": 0, + "eventAck": 0, + "eventTag": 0, + "txLsRate": 1, + "txTrigInv": 0, + "txPulseWidth": 500, + "swTrig": 0, + "txTrig": 0, + }, + ) await _reset_domains(dut) cfg_bytes = [(0x12, 0), (0x9C, 1), (0x55, 0)] @@ -151,7 +149,7 @@ async def coaxpress_tx_config_and_event_ack_test(dut): assert not tx_trig_drop_seen - cfg_start = _find_subsequence(observed, cfg_bytes) + cfg_start = find_subsequence([(data, is_k) for _, data, is_k in observed], cfg_bytes) assert cfg_start is not None, f"config bytes not found in observed stream: {observed}" event_ack_bytes = [ @@ -160,9 +158,12 @@ async def coaxpress_tx_config_and_event_ack_test(dut): *[(event_tag, 0)] * 4, *[(byte, 1) for byte in word_to_bytes(CXP_EOP)], ] - event_start = _find_subsequence(observed, event_ack_bytes) + event_start = find_subsequence([(data, is_k) for _, data, is_k in observed], event_ack_bytes) assert event_start is not None, f"event-ack packet not found in observed stream: {observed}" - idle_after_event = _find_subsequence(observed[event_start + len(event_ack_bytes) :], IDLE_SEQUENCE) + idle_after_event = find_subsequence( + [(data, is_k) for _, data, is_k in observed[event_start + len(event_ack_bytes) :]], + IDLE_SEQUENCE, + ) assert cfg_start < event_start, f"unexpected config/event ordering in observed stream: {observed}" assert idle_after_event is not None, f"idle word not restored after event-ack packet: {observed}" @@ -171,19 +172,24 @@ async def coaxpress_tx_config_and_event_ack_test(dut): async def coaxpress_tx_software_trigger_path_test(dut): # Keep the hardware trigger low and use only `swTrig` so the bench proves # the assembly's OR-combined software trigger path end-to-end. - cocotb.start_soon(Clock(dut.cfgClk, 6, unit="ns").start()) - cocotb.start_soon(Clock(dut.txClk, 4, unit="ns").start()) - dut.cfgTValid.setimmediatevalue(0) - dut.cfgTData.setimmediatevalue(0) - dut.cfgTUser.setimmediatevalue(0) - dut.cfgTLast.setimmediatevalue(0) - dut.eventAck.setimmediatevalue(0) - dut.eventTag.setimmediatevalue(0) - dut.txLsRate.setimmediatevalue(1) - dut.txTrigInv.setimmediatevalue(1) - dut.txPulseWidth.setimmediatevalue(500) - dut.swTrig.setimmediatevalue(0) - dut.txTrig.setimmediatevalue(0) + start_clock(dut.cfgClk, period_ns=6.0) + start_clock(dut.txClk, period_ns=4.0) + set_initial_values( + dut, + { + "cfgTValid": 0, + "cfgTData": 0, + "cfgTUser": 0, + "cfgTLast": 0, + "eventAck": 0, + "eventTag": 0, + "txLsRate": 1, + "txTrigInv": 1, + "txPulseWidth": 500, + "swTrig": 0, + "txTrig": 0, + }, + ) await _reset_domains(dut) await _pulse_sw_trigger(dut) From 5d8d5d0e75ebd58f709730e5ef64f1a7ad70f9f8 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 20 Apr 2026 13:02:06 -0700 Subject: [PATCH 32/92] Align constant names to the spec. --- docs/_meta/rtl_regression_handoff.md | 2 +- docs/_meta/rtl_regression_plan.md | 1 + docs/_meta/rtl_regression_progress.md | 2 +- tests/protocols/coaxpress/coaxpress_test_utils.py | 4 ++-- .../coaxpress/test_CoaXPressEventAckMsg.py | 10 +++++----- .../coaxpress/test_CoaXPressOverFiberBridge.py | 6 +++--- .../coaxpress/test_CoaXPressOverFiberBridgeRx.py | 8 ++++---- tests/protocols/coaxpress/test_CoaXPressRx.py | 6 +++--- tests/protocols/coaxpress/test_CoaXPressRxLane.py | 8 ++++---- tests/protocols/coaxpress/test_CoaXPressTx.py | 14 +++++++------- 10 files changed, 31 insertions(+), 30 deletions(-) diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index 2dee091930..e838a7fad0 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -26,7 +26,7 @@ - `EthMacRxImportXlgmii` and `EthMacTxExportXlgmii` are still placeholder no-op RTL; the checked-in tests now lock down that inert contract instead of claiming functional XLGMII support. - The remaining CoaXPress pure-VHDL gap is now `CoaXPressConfig`. The current `CoaXPressRxHsFsm` and `CoaXPressRx` benches intentionally stay on the stable one-lane path, so deeper multi-lane stepping/alignment behavior remains open even though the surrounding pure-VHDL helper leaves and the higher-level transmit/core/bridge assemblies are now covered. - `tests/protocols/coaxpress/test_CoaXPressConfig.py` is intentionally checked in as a skipped investigation bench. When driven through the real SRP ingress, the current `CoaXPressConfig` / `SrpV3AxiLite` integration does not complete the request path within the bench timeout, so treat that as a likely RTL or integration defect to debug before re-enabling active assertions there. - - For future CoaXPress work, treat the named packet classes and control bytes in `tests/protocols/coaxpress/coaxpress_test_utils.py` as shared spec anchors, not as optional local style. Those constants were normalized against the same `CXP-001-2021` / `CXPR-008-2021` references cited in `CoaXPressPkg.vhd`. + - For future CoaXPress work, treat the named packet classes and control bytes in `tests/protocols/coaxpress/coaxpress_test_utils.py` as shared spec anchors, not as optional local style. Those constants were normalized against the same `CXP-001-2021` / `CXPR-008-2021` references cited in `CoaXPressPkg.vhd`. Keep the packet-layer names aligned to the spec even where current RTL ports still use legacy `eventAck` naming on the receive side: `0x07` is an event packet and `0x08` is an event acknowledgment. - Current planning discipline: - Use manual user-directed area selection as the active source of truth for what to work on next. - Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the actual validated branch frontier. diff --git a/docs/_meta/rtl_regression_plan.md b/docs/_meta/rtl_regression_plan.md index b86a7a8ceb..edb96d6e54 100644 --- a/docs/_meta/rtl_regression_plan.md +++ b/docs/_meta/rtl_regression_plan.md @@ -108,6 +108,7 @@ - Treat the published CoaXPress specifications as normative for future `protocols/coaxpress/` work, especially for top-level receive/transmit and over-fiber bridge benches. - The two governing references are the CoaXPress protocol spec (`CXP-001-2021`) and the CoaXPress-over-Fiber bridge spec (`CXPR-008-2021`), matching the links already called out in `protocols/coaxpress/core/rtl/CoaXPressPkg.vhd`. - When a CoaXPress bench encodes packet classes, control symbols, or bridge control characters, derive those values from the spec-defined names first and mirror them through shared helpers such as `tests/protocols/coaxpress/coaxpress_test_utils.py` instead of scattering raw literals. +- At the packet layer, prefer the published names even when the current RTL signal naming drifts; for example, `0x07` is an event packet and `0x08` is an event acknowledgment even though some existing RTL ports still use `eventAck` for the receive-side event indication. - For CoaXPress image/header benches, keep the repeated-byte field encoding, header field order, endianness conversion, line-size semantics, and end-of-frame rules explicitly tied to the spec-defined rectangular image packet layout. - For CoaXPress-over-Fiber benches, keep `/I/`, `/Q/`, `/S/`, `/T/`, and `/E/` handling, lane-0-only start/sequence semantics, and payload-vs-housekeeping start words aligned to `CXPR-008-2021`. - If a checked-in bench intentionally validates only the current RTL contract instead of the full normative spec behavior, document that narrowed scope explicitly in the progress and handoff docs rather than implying full spec coverage. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index ce05823318..3106d74077 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -25,7 +25,7 @@ - Covered now under the current GHDL-only flow: `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, `CoaXPressRxHsFsm`, `CoaXPressRx`, `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressTx`, `CoaXPressCore`, `CoaXPressOverFiberBridgeRx`, `CoaXPressOverFiberBridgeTx`, and `CoaXPressOverFiberBridge` - Still open in the same pure-VHDL family: `CoaXPressConfig` - Blocked bench note: `tests/protocols/coaxpress/test_CoaXPressConfig.py` is checked in as a skipped investigation bench because the real SRP-driven request path does not complete under the current `CoaXPressConfig`/`SrpV3AxiLite` integration. Treat that as a likely RTL or integration defect to debug before re-enabling active assertions on the config return path. - - Spec discipline for this family: use the packet/control naming and byte values from `CXP-001-2021` and `CXPR-008-2021` via shared helpers, and keep future top-level/bridge benches explicit about whether they are proving normative spec behavior or only the currently validated RTL subset. + - Spec discipline for this family: use the packet/control naming and byte values from `CXP-001-2021` and `CXPR-008-2021` via shared helpers, and keep future top-level/bridge benches explicit about whether they are proving normative spec behavior or only the currently validated RTL subset. At the packet layer, keep the published names even when current RTL signal names drift: `0x07` is an event packet and `0x08` is an event acknowledgment. - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. diff --git a/tests/protocols/coaxpress/coaxpress_test_utils.py b/tests/protocols/coaxpress/coaxpress_test_utils.py index 1be249f00a..5a5072f2af 100644 --- a/tests/protocols/coaxpress/coaxpress_test_utils.py +++ b/tests/protocols/coaxpress/coaxpress_test_utils.py @@ -36,8 +36,8 @@ CXP_ACK_SUCCESS = 0x01 CXP_ACK_SUCCESS_ALT = 0x04 CXP_PKT_CTRL_ACK_WITH_TAG = 0x06 -CXP_PKT_EVENT_ACK = 0x07 -CXP_PKT_EVENT_ACK_MSG = 0x08 +CXP_PKT_EVENT = 0x07 +CXP_PKT_EVENT_ACK = 0x08 CXP_PKT_HEARTBEAT = 0x09 # Low-speed symbol bytes used directly by the TX-side CoaXPress logic. diff --git a/tests/protocols/coaxpress/test_CoaXPressEventAckMsg.py b/tests/protocols/coaxpress/test_CoaXPressEventAckMsg.py index 7f5a8315e0..e37fa725a9 100644 --- a/tests/protocols/coaxpress/test_CoaXPressEventAckMsg.py +++ b/tests/protocols/coaxpress/test_CoaXPressEventAckMsg.py @@ -9,12 +9,12 @@ ############################################################################## # Test methodology: -# - Sweep: Exercise the event-ack serializer directly with two event tags so +# - Sweep: Exercise the event-acknowledgment serializer directly with two event tags so # the bench checks both the initial transfer and a second post-idle retry. # - Stimulus: Pulse `eventAck`, hold `TREADY` low across the first serialized # byte to create backpressure, then release the sink and repeat with a second # tag while the sink stays ready. -# - Checks: The DUT must serialize the CoaXPress event-ack message as +# - Checks: The DUT must serialize the CoaXPress event-acknowledgment message as # `SOP`, type `0x08`, repeated event tag, and `EOP`, preserve the K/data # classification on each byte, assert `TLAST` only on the final byte, and # hold the stalled first byte stable under backpressure. @@ -27,7 +27,7 @@ from tests.common.regression_utils import run_surf_vhdl_test from tests.protocols.coaxpress.coaxpress_test_utils import ( CXP_EOP, - CXP_PKT_EVENT_ACK_MSG, + CXP_PKT_EVENT_ACK, CXP_SOP, cycle, repeat_byte, @@ -41,7 +41,7 @@ def _expected_event_ack_bytes(tag: int) -> list[tuple[int, int, int]]: expected: list[tuple[int, int, int]] = [] for word, is_k in ( (CXP_SOP, 1), - (repeat_byte(CXP_PKT_EVENT_ACK_MSG), 0), + (repeat_byte(CXP_PKT_EVENT_ACK), 0), (repeat_byte(tag), 0), (CXP_EOP, 1), ): @@ -87,7 +87,7 @@ async def coaxpress_event_ack_msg_serialize_and_backpressure_test(dut): dut.eventAckTReady.setimmediatevalue(0) await reset_dut(dut, clk_name="clk", reset_names=("rst",)) - # Create one event-ack request while the sink is stalled so the first byte + # Create one event-acknowledgment request while the sink is stalled so the first byte # must remain stable until `TREADY` is released. await _pulse_event_ack(dut, 0x5A) diff --git a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridge.py b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridge.py index 22306063e2..247790f36a 100644 --- a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridge.py +++ b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridge.py @@ -31,7 +31,7 @@ CXP_EOP, CXP_IDLE, CXP_IDLE_K, - CXP_PKT_EVENT_ACK_MSG, + CXP_PKT_EVENT_ACK, CXP_SOP, CXPOF_IDLE, CXPOF_START, @@ -109,7 +109,7 @@ async def capture_rx_words(cycles: int) -> None: dut.txLsValid.value = 0 await cycle(dut.rxClk156, 3) - dut.xgmiiRxd.value = (_rx_start_word(CXP_PKT_EVENT_ACK_MSG) | (0x11223344 << 32)) + dut.xgmiiRxd.value = (_rx_start_word(CXP_PKT_EVENT_ACK) | (0x11223344 << 32)) dut.xgmiiRxc.value = 0x01 await RisingEdge(dut.rxClk156) await Timer(1, unit="ns") @@ -129,7 +129,7 @@ async def capture_rx_words(cycles: int) -> None: ] rx_expected = [ (CXP_SOP, 0xF), - (repeat_byte(CXP_PKT_EVENT_ACK_MSG), 0x0), + (repeat_byte(CXP_PKT_EVENT_ACK), 0x0), (0x11223344, 0x0), (CXP_EOP, 0xF), ] diff --git a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py index e3aeb541bc..eac77302ab 100644 --- a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py +++ b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py @@ -30,7 +30,7 @@ CXP_IDLE, CXP_IDLE_K, CXP_IO_ACK, - CXP_PKT_EVENT_ACK_MSG, + CXP_PKT_EVENT_ACK, CXP_SOP, CXPOF_START, cycle, @@ -64,9 +64,9 @@ async def drive(rxd: int, rxc: int) -> None: if sample != (CXP_IDLE, CXP_IDLE_K): observed.append(sample) - # Low-speed packet carrying a CoaXPress event-ack message byte followed by + # Low-speed packet carrying a CoaXPress event-acknowledgment byte followed by # one 32-bit payload word and an EOP terminator. - await drive(_cxp_start_word(CXP_PKT_EVENT_ACK_MSG), 0x1) + await drive(_cxp_start_word(CXP_PKT_EVENT_ACK), 0x1) await drive(0x11223344, 0x0) await drive(0x07FD00FD, 0xC) await drive(0x07070707, 0xF) @@ -85,7 +85,7 @@ async def drive(rxd: int, rxc: int) -> None: assert observed == [ (CXP_SOP, 0xF), - (repeat_byte(CXP_PKT_EVENT_ACK_MSG), 0x0), + (repeat_byte(CXP_PKT_EVENT_ACK), 0x0), (0x11223344, 0x0), (CXP_EOP, 0xF), (CXP_IO_ACK, 0xF), diff --git a/tests/protocols/coaxpress/test_CoaXPressRx.py b/tests/protocols/coaxpress/test_CoaXPressRx.py index 0e19cc6ebe..caa1e7b343 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRx.py +++ b/tests/protocols/coaxpress/test_CoaXPressRx.py @@ -12,7 +12,7 @@ # - Sweep: Keep the first `CoaXPressRx` assembly pass on the stable one-lane # path while still exercising all three externally visible outputs: config, # image header/data, and the synchronized ACK/event sidebands. -# - Stimulus: Drive one control-ack packet, one event-ack packet, one `IO_ACK`, +# - Stimulus: Drive one control-ack packet, one event packet, one `IO_ACK`, # and one rectangular image transaction directly into the raw receive lane. # - Checks: The assembled RX path must forward the config completion word, # export the event tag, pulse `trigAck`, emit the seven 32-bit image-header @@ -28,7 +28,7 @@ CXP_IO_ACK, CXP_MARKER, CXP_PKT_CTRL_ACK_NO_TAG, - CXP_PKT_EVENT_ACK, + CXP_PKT_EVENT, CXP_PKT_IMAGE_HEADER, CXP_PKT_IMAGE_LINE, CXP_SOP, @@ -151,7 +151,7 @@ async def coaxpress_rx_one_lane_integration_test(dut): (0xCAFEBABE, 0x0), (0x01234567, 0x0), (CXP_SOP, 0xF), - (repeat_byte(CXP_PKT_EVENT_ACK), 0x0), + (repeat_byte(CXP_PKT_EVENT), 0x0), (repeat_byte(0x10), 0x0), (repeat_byte(0x11), 0x0), (repeat_byte(0x12), 0x0), diff --git a/tests/protocols/coaxpress/test_CoaXPressRxLane.py b/tests/protocols/coaxpress/test_CoaXPressRxLane.py index f39ba0bb55..b02e17eb20 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRxLane.py +++ b/tests/protocols/coaxpress/test_CoaXPressRxLane.py @@ -12,7 +12,7 @@ # - Sweep: Exercise the receive-lane decoder directly without a generic sweep # because the bug-prone surface is its packet-state logic rather than a set # of static parameters. -# - Stimulus: Drive raw CoaXPress words for stream, control-ack, event-ack, +# - Stimulus: Drive raw CoaXPress words for stream, control-ack, event, # heartbeat, malformed-field, and link-drop sequences, including an `IO_ACK` # interruption in the middle of a stream packet. # - Checks: The lane must emit the right config/data/heartbeat payloads, pulse @@ -32,7 +32,7 @@ CXP_IO_ACK, CXP_PKT_CTRL_ACK_NO_TAG, CXP_PKT_CTRL_ACK_WITH_TAG, - CXP_PKT_EVENT_ACK, + CXP_PKT_EVENT, CXP_PKT_HEARTBEAT, CXP_PKT_STREAM_DATA, CXP_SOP, @@ -140,9 +140,9 @@ async def drive(data: int, data_k: int, *, link_up: int = 1) -> None: await drive(0xFEEDBEEF, 0x0) await drive(0x89ABCDEF, 0x0) - # Event ACK fires on the fifth payload word and exports the low byte. + # Event packet handling fires on the fifth payload word and exports the tag. await drive(CXP_SOP, 0xF) - await drive(repeat_byte(CXP_PKT_EVENT_ACK), 0x0) + await drive(repeat_byte(CXP_PKT_EVENT), 0x0) for word in (0x10, 0x11, 0x12, 0x13): await drive(repeat_byte(word), 0x0) await drive(repeat_byte(0x5A), 0x0) diff --git a/tests/protocols/coaxpress/test_CoaXPressTx.py b/tests/protocols/coaxpress/test_CoaXPressTx.py index 00dd7426f3..79f64318e2 100644 --- a/tests/protocols/coaxpress/test_CoaXPressTx.py +++ b/tests/protocols/coaxpress/test_CoaXPressTx.py @@ -10,13 +10,13 @@ # Test methodology: # - Sweep: Exercise the first full CoaXPress transmit assembly in two modes: -# config/event-ack arbitration across the cfg-to-tx clock crossing and the +# config/event-acknowledgment arbitration across the cfg-to-tx clock crossing and the # software-trigger path into the low-speed transmit FSM. # - Stimulus: Queue one multi-byte config packet, pulse `eventAck` while that # packet is active, and separately pulse only `swTrig` with `txTrig` held # low so the OR-combined trigger path is the only source of trigger traffic. # - Checks: The transmitted low-speed stream must preserve the config bytes, -# serialize the spec-defined event-ack packet without corruption, and emit +# serialize the spec-defined event-acknowledgment packet without corruption, and emit # both trigger message polarities from a software trigger without asserting # `txTrigDrop`. # - Timing: The bench records each transmitted byte at the real `txClk` @@ -33,7 +33,7 @@ CXP_K28_2, CXP_K28_4, CXP_K28_5, - CXP_PKT_EVENT_ACK_MSG, + CXP_PKT_EVENT_ACK, CXP_EOP, CXP_SOP, cycle, @@ -116,7 +116,7 @@ async def _collect_tx_bytes(dut, *, count: int, timeout_cycles: int) -> tuple[li async def coaxpress_tx_config_and_event_ack_test(dut): # Hold the assembly in reset long enough for both domains to settle, then # prove that a config packet already in flight is preserved ahead of a - # later event-ack packet through the mux and CDC FIFO. + # later event-acknowledgment packet through the mux and CDC FIFO. start_clock(dut.cfgClk, period_ns=6.0) start_clock(dut.txClk, period_ns=4.0) set_initial_values( @@ -154,18 +154,18 @@ async def coaxpress_tx_config_and_event_ack_test(dut): event_ack_bytes = [ *[(byte, 1) for byte in word_to_bytes(CXP_SOP)], - *[(CXP_PKT_EVENT_ACK_MSG, 0)] * 4, + *[(CXP_PKT_EVENT_ACK, 0)] * 4, *[(event_tag, 0)] * 4, *[(byte, 1) for byte in word_to_bytes(CXP_EOP)], ] event_start = find_subsequence([(data, is_k) for _, data, is_k in observed], event_ack_bytes) - assert event_start is not None, f"event-ack packet not found in observed stream: {observed}" + assert event_start is not None, f"event-acknowledgment packet not found in observed stream: {observed}" idle_after_event = find_subsequence( [(data, is_k) for _, data, is_k in observed[event_start + len(event_ack_bytes) :]], IDLE_SEQUENCE, ) assert cfg_start < event_start, f"unexpected config/event ordering in observed stream: {observed}" - assert idle_after_event is not None, f"idle word not restored after event-ack packet: {observed}" + assert idle_after_event is not None, f"idle word not restored after event-acknowledgment packet: {observed}" @cocotb.test() From c3b4ca6773078f47ae1e8912a6279a43e76115f5 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 20 Apr 2026 13:16:42 -0700 Subject: [PATCH 33/92] Update tests to follow specs. --- docs/_meta/rtl_regression_handoff.md | 1 + docs/_meta/rtl_regression_progress.md | 1 + tests/protocols/coaxpress/README.md | 212 ++++++++++++++++++ tests/protocols/coaxpress/test_CoaXPressRx.py | 16 +- .../coaxpress/test_CoaXPressRxLane.py | 53 +++-- 5 files changed, 265 insertions(+), 18 deletions(-) create mode 100644 tests/protocols/coaxpress/README.md diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index e838a7fad0..0c527191dc 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -27,6 +27,7 @@ - The remaining CoaXPress pure-VHDL gap is now `CoaXPressConfig`. The current `CoaXPressRxHsFsm` and `CoaXPressRx` benches intentionally stay on the stable one-lane path, so deeper multi-lane stepping/alignment behavior remains open even though the surrounding pure-VHDL helper leaves and the higher-level transmit/core/bridge assemblies are now covered. - `tests/protocols/coaxpress/test_CoaXPressConfig.py` is intentionally checked in as a skipped investigation bench. When driven through the real SRP ingress, the current `CoaXPressConfig` / `SrpV3AxiLite` integration does not complete the request path within the bench timeout, so treat that as a likely RTL or integration defect to debug before re-enabling active assertions there. - For future CoaXPress work, treat the named packet classes and control bytes in `tests/protocols/coaxpress/coaxpress_test_utils.py` as shared spec anchors, not as optional local style. Those constants were normalized against the same `CXP-001-2021` / `CXPR-008-2021` references cited in `CoaXPressPkg.vhd`. Keep the packet-layer names aligned to the spec even where current RTL ports still use legacy `eventAck` naming on the receive side: `0x07` is an event packet and `0x08` is an event acknowledgment. + - The current receive benches are intentionally mixed-depth: control-ack traffic is now driven with fuller spec-shaped framing, but the checked-in `CoaXPressRxLane` / `CoaXPressRx` event tests still only prove the current RTL contract of consuming the event prefix through the Packet Tag field. Do not describe that as full event-payload coverage until the RTL/parser is expanded and the bench follows it. - Current planning discipline: - Use manual user-directed area selection as the active source of truth for what to work on next. - Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the actual validated branch frontier. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 3106d74077..f2f30ca187 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -26,6 +26,7 @@ - Still open in the same pure-VHDL family: `CoaXPressConfig` - Blocked bench note: `tests/protocols/coaxpress/test_CoaXPressConfig.py` is checked in as a skipped investigation bench because the real SRP-driven request path does not complete under the current `CoaXPressConfig`/`SrpV3AxiLite` integration. Treat that as a likely RTL or integration defect to debug before re-enabling active assertions on the config return path. - Spec discipline for this family: use the packet/control naming and byte values from `CXP-001-2021` and `CXPR-008-2021` via shared helpers, and keep future top-level/bridge benches explicit about whether they are proving normative spec behavior or only the currently validated RTL subset. At the packet layer, keep the published names even when current RTL signal names drift: `0x07` is an event packet and `0x08` is an event acknowledgment. + - The checked-in RX benches now use more spec-shaped control-ack framing on the wire, but the current receive-side event path still only observes the event packet prefix through the Packet Tag field before returning to IDLE. Keep that limitation documented rather than implying full event-payload decode coverage. - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. diff --git a/tests/protocols/coaxpress/README.md b/tests/protocols/coaxpress/README.md new file mode 100644 index 0000000000..fefb333794 --- /dev/null +++ b/tests/protocols/coaxpress/README.md @@ -0,0 +1,212 @@ +# CoaXPress Regression Notes + +This directory holds the checked-in cocotb regressions for the pure-VHDL +CoaXPress RTL under `protocols/coaxpress/core/rtl/`. + +The intent is to keep the benches tied to the published protocol documents, +while also being explicit about places where the current RTL only exposes or +implements a narrower contract than the full normative wire protocol. + +## Governing References + +- [CoaXPress Standard Version 2.1](https://jiia.org/wp/wp-content/themes/jiia/pdf/standard_dl/coaxpress/CXP-001-2021.pdf) + - JIIA `CXP-001-2021` +- CoaXPress over Fiber - Bridge Protocol + - tests in this directory are aligned to the `CXPR-008` bridge specification family + - public JIIA bridge-guideline reference currently available online: + [CoaXPress over Fiber Bridge Protocol Version 1.1](https://jiia.org/wp/wp-content/themes/jiia/pdf/standard_dl/coaxpress/CXPR-008-2023_v1.1.pdf) + - when discussing the original bridge baseline used by the current RTL/tests, + refer to the document by name and identifier family rather than to any + local PDF path + +The shared constants in `coaxpress_test_utils.py` use the spec packet names and +symbol values directly: + +- `0x07` is an event packet +- `0x08` is an event acknowledgment +- `/I/`, `/Q/`, `/S/`, `/T/`, and `/E/` use the CXPoF bridge byte values from + `CXPR-008-2021` + +## Coverage Model + +The benches in this directory fall into three categories: + +- Normative or near-normative packet checks + - The test drives protocol-shaped traffic that matches the published packet + layout closely enough to be treated as spec coverage for the exercised + subset. +- Partial protocol checks + - The test uses spec-shaped prefixes and field ordering, but the current RTL + only consumes a prefix or a reduced subset of the full packet. +- RTL-contract checks + - The test is primarily proving local assembly, buffering, arbitration, or + transport behavior rather than full protocol legality. + +When a bench is not full normative coverage, that should be treated as an +intentional limitation, not as silent proof of complete spec compliance. + +## Bench Map + +| Test file | DUT surface | Main spec relation | Status | +| --- | --- | --- | --- | +| `test_CoaXPressRxWordPacker.py` | `CoaXPressRxWordPacker` | Internal packing helper for receive-path word assembly; not a direct protocol-surface spec bench | RTL-contract | +| `test_CoaXPressRxLaneMux.py` | `CoaXPressRxLaneMux` | Internal lane arbitration and frame-boundary behavior; not a direct protocol-surface spec bench | RTL-contract | +| `test_CoaXPressRxLane.py` | `CoaXPressRxLane` | `CXP-001-2021` packet-type decode, `IO_ACK`, control acknowledgments, heartbeat prefix handling, stream header fields | Partial protocol | +| `test_CoaXPressRxHsFsm.py` | `CoaXPressRxHsFsm` | Rectangular image header and line marker handling from section `10.4.6.2` / `10.4.6.3` | Near-normative subset | +| `test_CoaXPressRx.py` | `CoaXPressRx` | One-lane receive assembly of config completion, event tag export, `IO_ACK`, and rectangular image traffic | Partial protocol | +| `test_CoaXPressEventAckMsg.py` | `CoaXPressEventAckMsg` | Event acknowledgment wire format, section `9.8.3`, Table 30 | Near-normative subset | +| `test_CoaXPressTxLsFsm.py` | `CoaXPressTxLsFsm` | Low-speed idle cadence and default trigger serialization, section `9.3.1.1` / Table 15 | Partial protocol | +| `test_CoaXPressTx.py` | `CoaXPressTx` | Control/event-acknowledgment arbitration and software-trigger path across the TX assembly | RTL-contract with spec packet classes | +| `test_CoaXPressConfig.py` | `CoaXPressConfig` | Control command packet formatting and tag handling, section `9.6.1.2` / `9.6.2` | Checked in but skipped | +| `test_CoaXPressCore.py` | `CoaXPressCore` | AXI-Lite control of tagged config request generation into the top-level TX path | RTL-contract with spec request prefix | +| `test_CoaXPressOverFiberBridgeTx.py` | `CoaXPressOverFiberBridgeTx` | CXPoF start/control/payload/terminate words, section `6.3.1` to `6.3.6` in `CXPR-008-2021` | Near-normative subset | +| `test_CoaXPressOverFiberBridgeRx.py` | `CoaXPressOverFiberBridgeRx` | CXPoF start-word decode back into CoaXPress packet and `IO_ACK` words | Partial protocol | +| `test_CoaXPressOverFiberBridge.py` | `CoaXPressOverFiberBridge` | Top-level 32b/64b gearbox integration around the bridge leaf mapping | RTL-contract with spec framing | + +## Spec Section Notes + +### Packet classes and framing + +The benches use the packet-class values from `CXP-001-2021` section `9.2.3` +and the generic data-packet framing from Table 19: + +- `0x01` stream data +- `0x03` control acknowledge without tag +- `0x06` control acknowledge with tag +- `0x07` event packet +- `0x08` event acknowledgment +- `0x09` heartbeat + +`test_CoaXPressEventAckMsg.py` and the TX-side bridge benches are the cleanest +examples of direct packet-type usage because they serialize or decode the wire +symbols directly. + +### Trigger and I/O acknowledgment + +The low-speed trigger and `IO_ACK` behavior is covered in pieces: + +- `test_CoaXPressTxLsFsm.py` + - exercises the default low-speed trigger byte patterns from section + `9.3.1.1`, Table 15 +- `test_CoaXPressRxLane.py` + - checks that the receive lane detects `IO_ACK` and resumes the interrupted + stream state +- `test_CoaXPressTx.py` + - checks that the software-trigger path reaches the low-speed trigger FSM + +This is not yet full trigger coverage. Extra low-speed trigger modes from Table +16 and broader high-speed trigger coverage from Table 17 are still open. + +### Control command and acknowledgment traffic + +The current checked-in coverage is split: + +- `test_CoaXPressConfig.py` + - intended normative request-format coverage for section `9.6.1.2` and + `9.6.2` + - currently skipped because the real `CoaXPressConfig` / `SrpV3AxiLite` + ingress path does not complete in the bench +- `test_CoaXPressRxLane.py` and `test_CoaXPressRx.py` + - now drive fuller control-ack shapes on the wire: code, size, reply data, + CRC placeholder, and `EOP` + - these benches prove the subset the current receive RTL actually consumes + +Important limitation: + +- `CoaXPressRxLane` does not currently validate full normative acknowledgment + semantics end to end +- it consumes only the reduced subset needed by the present receive assembly + +### Heartbeat and event traffic + +Heartbeat and event handling is only partially covered today: + +- `test_CoaXPressRxLane.py` + - checks the current 12-byte heartbeat payload collector +- `test_CoaXPressEventAckMsg.py` + - covers event acknowledgment generation on the transmit side +- `test_CoaXPressRxLane.py` and `test_CoaXPressRx.py` + - drive a fuller event packet shape, but the current receive RTL only + consumes the event prefix through the `Packet Tag` field before returning to + `IDLE` + +That means these benches do not yet prove full compliance with: + +- section `9.8.1` event ordering rules +- section `9.8.2` event payload parsing +- full event-payload CRC/trailer handling + +### Stream data and rectangular image traffic + +The image-path benches are the strongest spec-aligned receive tests today: + +- `test_CoaXPressRxHsFsm.py` + - validates rectangular image header and line marker handling against section + `10.4.6.2` and `10.4.6.3` +- `test_CoaXPressRx.py` + - validates the one-lane top-level receive assembly around that same traffic + +`test_CoaXPressRxLane.py` also exercises stream packet handling using +spec-shaped stream headers, but the emphasis there is on receive-lane state +behavior rather than on a full normative stream CRC checker. + +### CoaXPress over Fiber bridge + +The bridge benches map to `CXPR-008-2021`, especially: + +- section `6.3.1` SOP +- section `6.3.2` EOP +- section `6.3.3` IT +- section `6.3.4` HDP +- section `6.3.5` HKP +- section `6.3.6` LSP + +Current checked-in coverage: + +- `test_CoaXPressOverFiberBridgeTx.py` + - start-word control bits + - low-speed rate/update handling + - payload packing + - `/T/` plus `/I/` termination +- `test_CoaXPressOverFiberBridgeRx.py` + - RX start-word decode for normal packets and `IO_ACK` +- `test_CoaXPressOverFiberBridge.py` + - top-level 32b/64b gearbox integration around the bridge leaves + +Still open on the bridge side: + +- explicit `/Q/` sequence handling +- explicit `/E/` error handling +- broader HKP coverage +- more negative tests around lane-0-only `/S/` and `/Q/` rules + +## Known Limitations + +The current checked-in CoaXPress suite should not be described as full protocol +compliance coverage. + +The most important open limits are: + +- `CoaXPressConfig` is still skipped +- multi-lane receive stepping and alignment behavior is still open +- receive-side event handling still proves only the current RTL prefix contract +- trigger coverage does not yet include the broader low-speed extra modes or + the full high-speed trigger matrix +- CXPoF bridge coverage does not yet exhaustively cover `/Q/`, `/E/`, and the + full housekeeping/data mix + +## Running The Slice + +Typical local commands: + +```bash +./.venv/bin/python -m pytest -n 0 -q tests/protocols/coaxpress +``` + +Focused receive-path rerun: + +```bash +./.venv/bin/python -m pytest -n 0 -q \ + tests/protocols/coaxpress/test_CoaXPressRxLane.py \ + tests/protocols/coaxpress/test_CoaXPressRx.py +``` diff --git a/tests/protocols/coaxpress/test_CoaXPressRx.py b/tests/protocols/coaxpress/test_CoaXPressRx.py index caa1e7b343..8b592aaf31 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRx.py +++ b/tests/protocols/coaxpress/test_CoaXPressRx.py @@ -13,7 +13,9 @@ # path while still exercising all three externally visible outputs: config, # image header/data, and the synchronized ACK/event sidebands. # - Stimulus: Drive one control-ack packet, one event packet, one `IO_ACK`, -# and one rectangular image transaction directly into the raw receive lane. +# and one rectangular image transaction directly into the raw receive lane, +# keeping the receive-side packets spec-shaped where the current RTL can +# consume that framing. # - Checks: The assembled RX path must forward the config completion word, # export the event tag, pulse `trigAck`, emit the seven 32-bit image-header # words in order, and forward the programmed line payload with `SOF`/`TLAST` @@ -25,6 +27,7 @@ from tests.common.regression_utils import run_surf_vhdl_test, start_lockstep_clocks from tests.protocols.coaxpress.coaxpress_test_utils import ( + CXP_EOP, CXP_IO_ACK, CXP_MARKER, CXP_PKT_CTRL_ACK_NO_TAG, @@ -148,8 +151,10 @@ async def coaxpress_rx_one_lane_integration_test(dut): (CXP_SOP, 0xF), (repeat_byte(CXP_PKT_CTRL_ACK_NO_TAG), 0x0), (repeat_byte(0x00), 0x0), - (0xCAFEBABE, 0x0), + (0x04000000, 0x0), (0x01234567, 0x0), + (0xCAFEBABE, 0x0), + (CXP_EOP, 0xF), (CXP_SOP, 0xF), (repeat_byte(CXP_PKT_EVENT), 0x0), (repeat_byte(0x10), 0x0), @@ -157,6 +162,11 @@ async def coaxpress_rx_one_lane_integration_test(dut): (repeat_byte(0x12), 0x0), (repeat_byte(0x13), 0x0), (repeat_byte(0x5A), 0x0), + (0x00010000, 0x0), + (repeat_byte(0x00), 0x0), + (0x11223344, 0x0), + (0xA5A5A5A5, 0x0), + (CXP_EOP, 0xF), (CXP_IO_ACK, 0xF), (repeat_byte(0x01), 0x0), (CXP_SOP, 0xF), @@ -179,6 +189,8 @@ async def coaxpress_rx_one_lane_integration_test(dut): (0x11111111, 0x0), (0x22222222, 0x0), (0x33333333, 0x0), + (0xBEEFBEEF, 0x0), + (CXP_EOP, 0xF), ] for cycle_index, (data, data_k) in enumerate(sequence): diff --git a/tests/protocols/coaxpress/test_CoaXPressRxLane.py b/tests/protocols/coaxpress/test_CoaXPressRxLane.py index b02e17eb20..b6ad1e9edb 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRxLane.py +++ b/tests/protocols/coaxpress/test_CoaXPressRxLane.py @@ -12,9 +12,9 @@ # - Sweep: Exercise the receive-lane decoder directly without a generic sweep # because the bug-prone surface is its packet-state logic rather than a set # of static parameters. -# - Stimulus: Drive raw CoaXPress words for stream, control-ack, event, -# heartbeat, malformed-field, and link-drop sequences, including an `IO_ACK` -# interruption in the middle of a stream packet. +# - Stimulus: Drive raw CoaXPress stream, control-ack, event, and heartbeat +# words using spec-shaped packet prefixes and trailers where the current RTL +# can consume them, plus malformed-field and link-drop sequences. # - Checks: The lane must emit the right config/data/heartbeat payloads, pulse # `ioAck` and `eventAck` at the correct points, preserve payload `TUSER` # bits, and reset cleanly after malformed packets or `rxLinkUp` loss. @@ -26,7 +26,7 @@ from tests.common.regression_utils import run_surf_vhdl_test from tests.protocols.coaxpress.coaxpress_test_utils import ( - CXP_ACK_SUCCESS, + CXP_EOP, CXP_IDLE, CXP_IDLE_K, CXP_IO_ACK, @@ -69,8 +69,9 @@ async def drive(data: int, data_k: int) -> None: ) io_ack_pulses += int(dut.ioAck.value) - # Build one three-word stream packet and interrupt it with an I/O ACK - # sequence before the payload starts to prove the saved-state path. + # Build one three-word stream packet with a spec-shaped header/trailer and + # interrupt it with an I/O ACK sequence before the payload starts to prove + # the saved-state path. await drive(CXP_SOP, 0xF) await drive(repeat_byte(CXP_PKT_STREAM_DATA), 0x0) await drive(repeat_byte(0x22), 0x0) @@ -82,6 +83,8 @@ async def drive(data: int, data_k: int) -> None: await drive(0x11223344, 0x0) await drive(0x55667788, 0x5) await drive(0x99AABBCC, 0x0) + await drive(0xDEADBEEF, 0x0) + await drive(CXP_EOP, 0xF) await drive(CXP_IDLE, CXP_IDLE_K) assert io_ack_pulses == 1 @@ -93,7 +96,7 @@ async def drive(data: int, data_k: int) -> None: @cocotb.test() -async def coaxpress_rx_lane_control_event_and_heartbeat_test(dut): +async def coaxpress_rx_lane_spec_prefix_control_event_and_heartbeat_test(dut): start_clock(dut.rxClk) dut.rxRst.setimmediatevalue(1) dut.rxLinkUp.setimmediatevalue(1) @@ -125,38 +128,56 @@ async def drive(data: int, data_k: int, *, link_up: int = 1) -> None: if int(dut.eventAck.value) == 1: event_pulses.append((int(dut.eventAck.value), int(dut.eventTag.value))) - # Successful ACK without tag should zero the status field but forward data. + # Drive one spec-shaped untagged read acknowledgment: + # code 0x00, size=4 bytes, one reply-data word, CRC, EOP. await drive(CXP_SOP, 0xF) await drive(repeat_byte(CXP_PKT_CTRL_ACK_NO_TAG), 0x0) - await drive(repeat_byte(CXP_ACK_SUCCESS), 0x0) - await drive(0xCAFEBABE, 0x0) + await drive(repeat_byte(0x00), 0x0) + await drive(0x04000000, 0x0) await drive(0x01234567, 0x0) + await drive(0xCAFEBABE, 0x0) + await drive(CXP_EOP, 0xF) - # Tagged ACK should skip the tag word and preserve the non-success status. + # Drive one spec-shaped tagged read acknowledgment. The current RTL skips + # the tag word, then forwards the first reply-data word with a zeroed + # success status in the low 32 bits. await drive(CXP_SOP, 0xF) await drive(repeat_byte(CXP_PKT_CTRL_ACK_WITH_TAG), 0x0) await drive(repeat_byte(0x55), 0x0) - await drive(repeat_byte(0x02), 0x0) - await drive(0xFEEDBEEF, 0x0) + await drive(repeat_byte(0x00), 0x0) + await drive(0x04000000, 0x0) await drive(0x89ABCDEF, 0x0) + await drive(0xFEEDBEEF, 0x0) + await drive(CXP_EOP, 0xF) - # Event packet handling fires on the fifth payload word and exports the tag. + # Drive a fuller event packet shape. The current RTL only consumes the + # prefix through the Packet Tag field, where it exports the tag and returns + # to IDLE; later size/data/trailer words are present to keep the on-wire + # stimulus aligned to the spec framing. await drive(CXP_SOP, 0xF) await drive(repeat_byte(CXP_PKT_EVENT), 0x0) for word in (0x10, 0x11, 0x12, 0x13): await drive(repeat_byte(word), 0x0) await drive(repeat_byte(0x5A), 0x0) + await drive(0x00010000, 0x0) + await drive(repeat_byte(0x00), 0x0) + await drive(0x11223344, 0x0) + await drive(0xA5A5A5A5, 0x0) + await drive(CXP_EOP, 0xF) - # Heartbeat collects 12 bytes into one terminal beat. + # Heartbeat still exercises the current 12-byte payload collector, followed + # by a nominal packet trailer. await drive(CXP_SOP, 0xF) await drive(repeat_byte(CXP_PKT_HEARTBEAT), 0x0) for word in range(0x20, 0x2C): await drive(repeat_byte(word), 0x0) + await drive(0xB6B6B6B6, 0x0) + await drive(CXP_EOP, 0xF) await drive(CXP_IDLE, CXP_IDLE_K) assert cfg_beats == [ {"cfgTData": (0x01234567 << 32)}, - {"cfgTData": (0x89ABCDEF << 32) | 0x02020202}, + {"cfgTData": (0x89ABCDEF << 32)}, ] assert event_pulses == [(1, 0x5A)] assert heartbeat_beats == [ From 085faee7a317ab837fa9ca2116fde1de25ba450f Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 20 Apr 2026 13:43:19 -0700 Subject: [PATCH 34/92] Deeper specification testing. --- docs/_meta/rtl_regression_handoff.md | 4 +- docs/_meta/rtl_regression_progress.md | 5 +- .../core/wrappers/CoaXPressRxWrapper.vhd | 36 +++-- tests/protocols/coaxpress/README.md | 32 ++-- .../test_CoaXPressOverFiberBridgeRx.py | 47 ++++++ .../test_CoaXPressOverFiberBridgeTx.py | 48 ++++++ tests/protocols/coaxpress/test_CoaXPressRx.py | 152 +++++++++++++++++- .../coaxpress/test_CoaXPressRxHsFsm.py | 129 ++++++++++++++- .../coaxpress/test_CoaXPressRxLane.py | 27 +++- .../coaxpress/test_CoaXPressTxLsFsm.py | 31 ++++ 10 files changed, 470 insertions(+), 41 deletions(-) diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index 0c527191dc..9b0fb46472 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -24,7 +24,7 @@ - Current validated-open issues: - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core` remain untouched in phase 1, while the remaining RoCEv2 gap is the mixed-language bench path for the five RTL entities that instantiate generated submodules: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`. - `EthMacRxImportXlgmii` and `EthMacTxExportXlgmii` are still placeholder no-op RTL; the checked-in tests now lock down that inert contract instead of claiming functional XLGMII support. - - The remaining CoaXPress pure-VHDL gap is now `CoaXPressConfig`. The current `CoaXPressRxHsFsm` and `CoaXPressRx` benches intentionally stay on the stable one-lane path, so deeper multi-lane stepping/alignment behavior remains open even though the surrounding pure-VHDL helper leaves and the higher-level transmit/core/bridge assemblies are now covered. + - The remaining CoaXPress pure-VHDL gap is now `CoaXPressConfig`. The current CoaXPress receive benches now include a dual-lane `CoaXPressRxHsFsm` step/alignment case and a dual-lane `CoaXPressRx` lane-rotation case, but the receive side is still intentionally mixed-depth: top-level event handling only proves the current packet-prefix contract, and the multi-lane assembly checks still stop short of exhaustive per-lane stress coverage. - `tests/protocols/coaxpress/test_CoaXPressConfig.py` is intentionally checked in as a skipped investigation bench. When driven through the real SRP ingress, the current `CoaXPressConfig` / `SrpV3AxiLite` integration does not complete the request path within the bench timeout, so treat that as a likely RTL or integration defect to debug before re-enabling active assertions there. - For future CoaXPress work, treat the named packet classes and control bytes in `tests/protocols/coaxpress/coaxpress_test_utils.py` as shared spec anchors, not as optional local style. Those constants were normalized against the same `CXP-001-2021` / `CXPR-008-2021` references cited in `CoaXPressPkg.vhd`. Keep the packet-layer names aligned to the spec even where current RTL ports still use legacy `eventAck` naming on the receive side: `0x07` is an event packet and `0x08` is an event acknowledgment. - The current receive benches are intentionally mixed-depth: control-ack traffic is now driven with fuller spec-shaped framing, but the checked-in `CoaXPressRxLane` / `CoaXPressRx` event tests still only prove the current RTL contract of consuming the event prefix through the Packet Tag field. Do not describe that as full event-payload coverage until the RTL/parser is expanded and the bench follows it. @@ -171,7 +171,7 @@ A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instan ## Immediate Next Task If the user keeps the focus on `protocols/coaxpress`, the next practical step is either: 1. debug and re-enable the skipped `CoaXPressConfig` investigation bench, starting with the SRP-driven request path that currently fails to complete through the real `CoaXPressConfig` / `SrpV3AxiLite` integration, or -2. deepen the current receive-path benches on the intentionally open multi-lane branches (`CoaXPressRxHsFsm` stepping/alignment and then `CoaXPressRx` integration). +2. deepen the remaining spec-level gaps around full receive-side event payload/CRC semantics and fuller CXPoF normative `/Q/`/`/E/` handling. If the user switches back to `ethernet/RoCEv2`, the next real step is still enabling a mixed-language cocotb path for the five remaining RTL entities listed above. Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the real validated subset, and do not reintroduce local stand-ins for `blue-*`. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index f2f30ca187..5ed8d60817 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -26,7 +26,7 @@ - Still open in the same pure-VHDL family: `CoaXPressConfig` - Blocked bench note: `tests/protocols/coaxpress/test_CoaXPressConfig.py` is checked in as a skipped investigation bench because the real SRP-driven request path does not complete under the current `CoaXPressConfig`/`SrpV3AxiLite` integration. Treat that as a likely RTL or integration defect to debug before re-enabling active assertions on the config return path. - Spec discipline for this family: use the packet/control naming and byte values from `CXP-001-2021` and `CXPR-008-2021` via shared helpers, and keep future top-level/bridge benches explicit about whether they are proving normative spec behavior or only the currently validated RTL subset. At the packet layer, keep the published names even when current RTL signal names drift: `0x07` is an event packet and `0x08` is an event acknowledgment. - - The checked-in RX benches now use more spec-shaped control-ack framing on the wire, but the current receive-side event path still only observes the event packet prefix through the Packet Tag field before returning to IDLE. Keep that limitation documented rather than implying full event-payload decode coverage. + - The checked-in RX benches now use more spec-shaped control-ack framing on the wire, include a dual-lane `CoaXPressRxHsFsm` step/alignment case and a dual-lane `CoaXPressRx` lane-rotation case, but the current receive-side event path still only observes the event packet prefix through the Packet Tag field before returning to IDLE. Keep that limitation documented rather than implying full event-payload decode coverage. - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. @@ -41,7 +41,7 @@ | `base` | started | not started | started | Validated low-level regressions now exist for `FifoAsync`, `FifoSync`, `FifoOutputPipeline`, `FifoWrFsm`, `FifoRdFsm`, `Fifo`, `FifoCascade`, `FifoMux`, `Synchronizer`, `SynchronizerVector`, `SynchronizerEdge`, `SynchronizerOneShot`, `SynchronizerFifo`, `SynchronizerOneShotCnt`, `SynchronizerOneShotVector`, `SynchronizerOneShotCntVector`, `SyncStatusVector`, `SyncTrigPeriod`, `SyncMinMax`, `SyncClockFreq`, `SyncTrigRate`, `SyncTrigRateVector`, `RstSync`, `RstPipeline`, `RstPipelineVector`, `PwrUpRst`, `Arbiter`, `ClockDivider`, `Debouncer`, `Gearbox`, `AsyncGearbox`, `Heartbeat`, `Mux`, `OneShot`, `RegisterVector`, `WatchDogRst`, `Scrambler`, `MasterRamIpIntegrator`, `SlaveRamIpIntegrator`, `SimpleDualPortRam`, `DualPortRam`, `TrueDualPortRam`, `LutRam`, `SlvDelay`, `SlvFixedDelay`, `SlvDelayRam`, `SlvDelayFifo`, `Crc32Parallel`, `Crc32`, and `CRC32Rtl` under subsystem-organized `tests/base/` packages. Remaining uncovered `base/` entities are vendor-heavy, dummy-backed, or `LutFixedDelay`, which is deferred because it depends on `SinglePortRamPrimitive`. | | `dsp` | started | not started | started | The planned `dsp/generic/fixed` leaf batch is now validated under `tests/dsp/generic/`: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. Shared DSP helpers now live in `tests/dsp/generic/dsp_test_utils.py`, and the legacy VHDL benches under `dsp/generic/tb/` were treated as behavioral reference material rather than as execution constraints. | | `axi` | started | not started | started | The axi-first pass is now complete for the simulator-friendly queue. The final locally validated batch adds `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`, with a combined `11 passed` validation run on 2026-03-27. Added checked-in subsystem wrappers under `axi/axi4/ip_integrator/`, `axi/axi-lite/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/` for those benches. `AxiStreamFifoV2` now has an expanded `10 passed` wrapper regression under `tests/axi/axi_stream/` covering async and sync width conversion, metadata truncation, `VALID_THOLD` frame-ready and burst-release modes, dynamic pause-threshold behavior, `CASCADE_SIZE=2`, and the `S_HAS_TREADY=0` pause-only source-side path. `AxiResize` now passes its equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` wrapper regression on this branch after the read-hold RTL fix. `AxiLiteAsync`, `AxiLiteToDrp`, and `AxiRateGen` still keep intentionally narrow common-clock subsets while the more timing-sensitive async AXI-Lite crossing branches remain open. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` still keep intentionally narrow first-pass subsets. `AxiStreamDmaV2Read` is now validated with a two-case wrapper regression covering both aligned and short terminal-beat reads after fixing bounded byte-count conversion in `AxiPkg` and terminal-mask generation in `AxiStreamDmaV2Read`. | -| `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. `protocols/coaxpress/` now has a broader pure-VHDL staged rollout under `tests/protocols/coaxpress/` backed by checked-in wrappers in `protocols/coaxpress/core/wrappers/`: the receive quartet still covers offset-start packing, lane rotation, stream/config/event/heartbeat decode, and rectangular-header framing; the transmit/bridge leaf benches cover `CoaXPressEventAckMsg` serialization under backpressure, `CoaXPressTxLsFsm` idle/config/trigger cadence, `CoaXPressOverFiberBridgeTx` CXPoF start/payload/terminate formatting, and `CoaXPressOverFiberBridgeRx` CXPoF start-word decode back into CoaXPress `SOP`/type/payload/`IO_ACK`; and the new assembly benches now cover `CoaXPressTx` config/event-ack arbitration plus software-trigger injection across the cfg-to-tx clock crossing and `CoaXPressOverFiberBridge` top-level 32b/64b gearbox integration on both the TX and RX sides. The current CoaXPress subset remains intentionally staged: it keeps the `CoaXPressRxHsFsm` wrapper on the stable one-lane path, normalizes packet/control literals onto named spec constants in `tests/protocols/coaxpress/coaxpress_test_utils.py`, and leaves the remaining higher-level receive/config/core assemblies `CoaXPressRx`, `CoaXPressConfig`, and `CoaXPressCore` for the next pass. | +| `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. `protocols/coaxpress/` now has a broader pure-VHDL staged rollout under `tests/protocols/coaxpress/` backed by checked-in wrappers in `protocols/coaxpress/core/wrappers/`: the receive leaves now cover offset-start packing, lane rotation, stream/config/event/heartbeat decode, rectangular-header framing, and a dual-lane `CoaXPressRxHsFsm` step/alignment case; the receive assembly now covers both the original one-lane integration path and a dual-lane `CoaXPressRx` lane-rotation case; the transmit/bridge leaf benches cover `CoaXPressEventAckMsg` serialization under backpressure, `CoaXPressTxLsFsm` idle/config/trigger cadence across both implemented low-speed rates, `CoaXPressOverFiberBridgeTx` CXPoF start/payload/terminate formatting plus partial-lane fill behavior, and `CoaXPressOverFiberBridgeRx` CXPoF start-word decode plus HKP and negative lane-placement guardrails; and the higher-level assembly benches cover `CoaXPressTx` config/event-ack arbitration plus software-trigger injection across the cfg-to-tx clock crossing and `CoaXPressOverFiberBridge` top-level 32b/64b gearbox integration on both the TX and RX sides. The current CoaXPress subset remains intentionally staged: it normalizes packet/control literals onto named spec constants in `tests/protocols/coaxpress/coaxpress_test_utils.py`, leaves `CoaXPressConfig` as the remaining pure-VHDL blocker, and still documents receive-side event parsing and normative CXPoF `/Q/`/`/E/` handling as open spec-depth gaps rather than claiming full protocol compliance. | | `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers both the original leaf slice and the deeper assembly benches for `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`, plus direct `EthMacRxBypass` / `EthMacTxBypass` leaf benches and import/export sweeps that now explicitly include the current placeholder `XLGMII` contract. `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, including the successful multi-beat `RawEthFramerTx` unicast-forwarding path after lookup resolution. `tests/ethernet/UdpEngine/` covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, with the top/wrapper benches now widened across client/server routing paths. `tests/ethernet/IpV4Engine/` covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, and the top/leaf benches now also include protocol-TX and deeper ICMP reject/recovery coverage. `tests/ethernet/RoCEv2/` currently covers the pure-VHDL RTL entities `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator` through checked-in wrappers under `ethernet/RoCEv2/wrappers/`. The remaining RoCEv2 RTL entities that still need cocotb benches are `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`, and those should use the real generated `blue-*` dependencies rather than local stand-ins. The explicit Ethernet caveats are now the larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core`, the mixed-language RoCEv2 bench gap listed above, plus the still-placeholder `EthMac*Xlgmii` RTL. | | `devices` | not started | not started | not started | Many vendor-heavy cases | | `xilinx` | not started | not started | not started | Many vendor-heavy cases | @@ -325,3 +325,4 @@ - 2026-04-20: Added the pure-VHDL RoCEv2 follow-on benches `tests/ethernet/RoCEv2/test_RoceResizeAndSwap.py` and `test_RoceConfigurator.py` plus their checked-in wrappers `ethernet/RoCEv2/wrappers/RoceResizeAndSwapIpIntegrator.vhd` and `RoceConfiguratorWrapper.vhd`, and validated the pure-VHDL RoCEv2 bench set with `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py tests/ethernet/RoCEv2/test_RoceResizeAndSwap.py tests/ethernet/RoCEv2/test_RoceConfigurator.py` (`4 passed`). - 2026-04-20: Removed the temporary local CRC stand-ins and the stub-backed `EthMacTxRoCEv2` / `EthMacRxRoCEv2` benches after clarifying the intended boundary: there should be one cocotb test module per entity in `ethernet/RoCEv2/rtl`, but `blue-*` must remain real transitive dependencies rather than being replaced with local test doubles. The current open RoCEv2 bench set is therefore `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`, all of which now require a mixed-language simulation path. - 2026-04-20: Added the next CoaXPress assembly pass with `tests/protocols/coaxpress/test_CoaXPressRx.py`, `test_CoaXPressCore.py`, and the checked-in wrappers `protocols/coaxpress/core/wrappers/CoaXPressRxWrapper.vhd` and `CoaXPressCoreWrapper.vhd`. The validated subset now covers the one-lane `CoaXPressRx` receive assembly and the AXI-Lite-controlled `CoaXPressCore` TX/config assembly path. `tests/protocols/coaxpress/test_CoaXPressConfig.py` was kept in-tree as a skipped investigation bench because the real SRP-driven `CoaXPressConfig` request path does not complete under the current `CoaXPressConfig` / `SrpV3AxiLite` integration, which is now recorded as the remaining pure-VHDL CoaXPress blocker. +- 2026-04-20: Deepened the CoaXPress receive/bridge coverage without changing RTL scope. `test_CoaXPressRxHsFsm.py` now includes a dual-lane step/alignment case, `test_CoaXPressRx.py` now includes a dual-lane lane-rotation integration case through a generalized `CoaXPressRxWrapper.vhd`, `test_CoaXPressRxLane.py` now covers alternate-success control acknowledgments plus truncated-event guardrails, `test_CoaXPressTxLsFsm.py` now covers the slower implemented low-speed-rate trigger cadence with inverted-trigger mapping, and the CXPoF bridge leaf benches now include HKP, negative lane-placement checks, and partial-lane low-speed fill behavior. The focused validation run across those six files passed locally with `8 passed`. diff --git a/protocols/coaxpress/core/wrappers/CoaXPressRxWrapper.vhd b/protocols/coaxpress/core/wrappers/CoaXPressRxWrapper.vhd index 491136ed99..46e79717a9 100644 --- a/protocols/coaxpress/core/wrappers/CoaXPressRxWrapper.vhd +++ b/protocols/coaxpress/core/wrappers/CoaXPressRxWrapper.vhd @@ -21,6 +21,9 @@ use surf.AxiStreamPkg.all; use surf.SsiPkg.all; entity CoaXPressRxWrapper is + generic ( + NUM_LANES_G : positive range 1 to 8 := 1; + RX_FSM_CNT_WIDTH_G : positive range 1 to 24 := 8); port ( dataClk : in sl; dataRst : in sl; @@ -30,9 +33,9 @@ entity CoaXPressRxWrapper is txRst : in sl; rxClk : in sl; rxRst : in sl; - rxData : in slv(31 downto 0); - rxDataK : in slv(3 downto 0); - rxLinkUp : in sl; + rxData : in slv(32*NUM_LANES_G-1 downto 0); + rxDataK : in slv(4*NUM_LANES_G-1 downto 0); + rxLinkUp : in slv(NUM_LANES_G-1 downto 0); rxFsmRst : in sl; rxNumberOfLane : in slv(2 downto 0); dataTValid : out sl; @@ -68,19 +71,22 @@ architecture rtl of CoaXPressRxWrapper is signal imageHdrSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; signal cfgRxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal rxClkVec : slv(0 downto 0); - signal rxRstVec : slv(0 downto 0); - signal rxDataVec : slv32Array(0 downto 0); - signal rxDataKVec : Slv4Array(0 downto 0); - signal rxLinkUpVec : slv(0 downto 0); + signal rxClkVec : slv(NUM_LANES_G-1 downto 0); + signal rxRstVec : slv(NUM_LANES_G-1 downto 0); + signal rxDataVec : slv32Array(NUM_LANES_G-1 downto 0); + signal rxDataKVec : Slv4Array(NUM_LANES_G-1 downto 0); + signal rxLinkUpVec : slv(NUM_LANES_G-1 downto 0); begin - rxClkVec(0) <= rxClk; - rxRstVec(0) <= rxRst; - rxDataVec(0) <= rxData; - rxDataKVec(0) <= rxDataK; - rxLinkUpVec(0) <= rxLinkUp; + GEN_LANE : for i in 0 to NUM_LANES_G-1 generate + begin + rxClkVec(i) <= rxClk; + rxRstVec(i) <= rxRst; + rxDataVec(i) <= rxData(32*i+31 downto 32*i); + rxDataKVec(i) <= rxDataK(4*i+3 downto 4*i); + rxLinkUpVec(i) <= rxLinkUp(i); + end generate GEN_LANE; dataSlave.tReady <= dataTReady; imageHdrSlave.tReady <= hdrTReady; @@ -105,8 +111,8 @@ begin U_DUT : entity surf.CoaXPressRx generic map ( TPD_G => 1 ns, - NUM_LANES_G => 1, - RX_FSM_CNT_WIDTH_G => 8, + NUM_LANES_G => NUM_LANES_G, + RX_FSM_CNT_WIDTH_G => RX_FSM_CNT_WIDTH_G, AXIS_CONFIG_G => AXIS_CONFIG_C) port map ( dataClk => dataClk, diff --git a/tests/protocols/coaxpress/README.md b/tests/protocols/coaxpress/README.md index fefb333794..bcdf247d7d 100644 --- a/tests/protocols/coaxpress/README.md +++ b/tests/protocols/coaxpress/README.md @@ -51,9 +51,9 @@ intentional limitation, not as silent proof of complete spec compliance. | --- | --- | --- | --- | | `test_CoaXPressRxWordPacker.py` | `CoaXPressRxWordPacker` | Internal packing helper for receive-path word assembly; not a direct protocol-surface spec bench | RTL-contract | | `test_CoaXPressRxLaneMux.py` | `CoaXPressRxLaneMux` | Internal lane arbitration and frame-boundary behavior; not a direct protocol-surface spec bench | RTL-contract | -| `test_CoaXPressRxLane.py` | `CoaXPressRxLane` | `CXP-001-2021` packet-type decode, `IO_ACK`, control acknowledgments, heartbeat prefix handling, stream header fields | Partial protocol | -| `test_CoaXPressRxHsFsm.py` | `CoaXPressRxHsFsm` | Rectangular image header and line marker handling from section `10.4.6.2` / `10.4.6.3` | Near-normative subset | -| `test_CoaXPressRx.py` | `CoaXPressRx` | One-lane receive assembly of config completion, event tag export, `IO_ACK`, and rectangular image traffic | Partial protocol | +| `test_CoaXPressRxLane.py` | `CoaXPressRxLane` | `CXP-001-2021` packet-type decode, `IO_ACK`, control acknowledgments, heartbeat prefix handling, truncated-event guardrails, stream header fields | Partial protocol | +| `test_CoaXPressRxHsFsm.py` | `CoaXPressRxHsFsm` | Rectangular image header and line marker handling from section `10.4.6.2` / `10.4.6.3`, including a dual-lane step/alignment case | Near-normative subset | +| `test_CoaXPressRx.py` | `CoaXPressRx` | One-lane control/event assembly plus dual-lane receive rotation/alignment through the lane mux and HS FSM | Partial protocol | | `test_CoaXPressEventAckMsg.py` | `CoaXPressEventAckMsg` | Event acknowledgment wire format, section `9.8.3`, Table 30 | Near-normative subset | | `test_CoaXPressTxLsFsm.py` | `CoaXPressTxLsFsm` | Low-speed idle cadence and default trigger serialization, section `9.3.1.1` / Table 15 | Partial protocol | | `test_CoaXPressTx.py` | `CoaXPressTx` | Control/event-acknowledgment arbitration and software-trigger path across the TX assembly | RTL-contract with spec packet classes | @@ -94,8 +94,11 @@ The low-speed trigger and `IO_ACK` behavior is covered in pieces: - `test_CoaXPressTx.py` - checks that the software-trigger path reaches the low-speed trigger FSM -This is not yet full trigger coverage. Extra low-speed trigger modes from Table -16 and broader high-speed trigger coverage from Table 17 are still open. +This is not yet full trigger coverage. The current RTL-facing benches now cover +both low-speed rates plus the implemented default/inverted trigger byte +patterns, but Extra-LS modes from Table 16 and the broader high-speed trigger +matrix from Table 17 are still open because that wider trigger surface is not +exposed by the current checked-in RTL. ### Control command and acknowledgment traffic @@ -144,7 +147,8 @@ The image-path benches are the strongest spec-aligned receive tests today: - validates rectangular image header and line marker handling against section `10.4.6.2` and `10.4.6.3` - `test_CoaXPressRx.py` - - validates the one-lane top-level receive assembly around that same traffic + - validates both the original one-lane top-level receive assembly and a + dual-lane lane-rotation path around the same traffic `test_CoaXPressRxLane.py` also exercises stream packet handling using spec-shaped stream headers, but the emphasis there is on receive-lane state @@ -166,19 +170,22 @@ Current checked-in coverage: - `test_CoaXPressOverFiberBridgeTx.py` - start-word control bits - low-speed rate/update handling + - partial-lane low-speed payload fill with CoaXPress idle insertion - payload packing - `/T/` plus `/I/` termination - `test_CoaXPressOverFiberBridgeRx.py` - RX start-word decode for normal packets and `IO_ACK` + - HKP forwarding + - negative lane-placement checks for `/S/` and `/Q/` - `test_CoaXPressOverFiberBridge.py` - top-level 32b/64b gearbox integration around the bridge leaves Still open on the bridge side: -- explicit `/Q/` sequence handling +- normative `/Q/` sequence handling beyond the current negative guardrails - explicit `/E/` error handling -- broader HKP coverage -- more negative tests around lane-0-only `/S/` and `/Q/` rules +- deeper HKP/data-mix coverage +- broader lane-0-only control-character sweeps ## Known Limitations @@ -188,12 +195,11 @@ compliance coverage. The most important open limits are: - `CoaXPressConfig` is still skipped -- multi-lane receive stepping and alignment behavior is still open - receive-side event handling still proves only the current RTL prefix contract -- trigger coverage does not yet include the broader low-speed extra modes or +- trigger coverage still does not include the broader low-speed extra modes or the full high-speed trigger matrix -- CXPoF bridge coverage does not yet exhaustively cover `/Q/`, `/E/`, and the - full housekeeping/data mix +- CXPoF bridge coverage still does not exhaustively cover normative `/Q/`, + `/E/`, and the full housekeeping/data mix ## Running The Slice diff --git a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py index eac77302ab..bb8370a2f1 100644 --- a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py +++ b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py @@ -92,6 +92,53 @@ async def drive(rxd: int, rxc: int) -> None: ] +@cocotb.test() +async def coaxpress_over_fiber_bridge_rx_hkp_and_invalid_control_test(dut): + # Keep the bridge idle through malformed lane placement for /S/ and /Q/, + # then verify the HKP path emits raw K-coded words and recovers to normal + # packet decode afterward. + start_clock(dut.clk) + dut.rst.setimmediatevalue(1) + dut.xgmiiRxd.setimmediatevalue(0x07070707) + dut.xgmiiRxc.setimmediatevalue(0xF) + await reset_dut(dut, clk_name="clk", reset_names=("rst",)) + + observed: list[tuple[int, int]] = [] + + async def drive(rxd: int, rxc: int) -> None: + dut.xgmiiRxd.value = rxd + dut.xgmiiRxc.value = rxc + await cycle(dut.clk, 1) + sample = (int(dut.rxData.value), int(dut.rxDataK.value)) + if sample != (CXP_IDLE, CXP_IDLE_K): + observed.append(sample) + + await drive(0x0707FB07, 0x2) + await drive(0x07079C07, 0x2) + await drive(0x07070707, 0xF) + await drive(0x07070707, 0xF) + + await drive(CXPOF_START | (0x81 << 8), 0x1) + await drive(0x5C5C5C5C, 0xF) + await drive(CXP_EOP, 0xF) + await drive(0x07070707, 0xF) + await drive(0x07070707, 0xF) + + await drive(_cxp_start_word(CXP_PKT_EVENT_ACK), 0x1) + await drive(0x55667788, 0x0) + await drive(0x07FD00FD, 0xC) + await drive(0x07070707, 0xF) + await drive(0x07070707, 0xF) + + assert observed == [ + (0x5C5C5C5C, 0xF), + (CXP_SOP, 0xF), + (repeat_byte(CXP_PKT_EVENT_ACK), 0x0), + (0x55667788, 0x0), + (CXP_EOP, 0xF), + ] + + def test_CoaXPressOverFiberBridgeRx(): run_surf_vhdl_test( test_file=__file__, diff --git a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeTx.py b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeTx.py index b26660437c..182b531387 100644 --- a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeTx.py +++ b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeTx.py @@ -25,6 +25,7 @@ from tests.common.regression_utils import run_surf_vhdl_test from tests.protocols.coaxpress.coaxpress_test_utils import ( + CXP_K28_1, CXPOF_IDLE, CXPOF_START, CXPOF_TERM, @@ -109,6 +110,53 @@ async def capture_words(count: int) -> None: assert any(word == (int.from_bytes(bytes([CXPOF_IDLE] * 4), "little"), 0xF) for word in observed[-3:]) +@cocotb.test() +async def coaxpress_over_fiber_bridge_tx_partial_lane_enable_test(dut): + # Enable only lanes 0 and 2 so the unused slots are filled with CoaXPress + # idle characters instead of extra payload copies. + start_clock(dut.clk) + dut.rst.setimmediatevalue(1) + dut.txLsValid.setimmediatevalue(0) + dut.txLsData.setimmediatevalue(0) + dut.txLsDataK.setimmediatevalue(0) + dut.txLsRate.setimmediatevalue(1) + dut.txLsLaneEn.setimmediatevalue(0x5) + await reset_dut(dut, clk_name="clk", reset_names=("rst",)) + + observed: list[tuple[int, int]] = [] + + async def capture_words(count: int) -> None: + while len(observed) < count: + await RisingEdge(dut.clk) + await Timer(1, unit="ns") + observed.append((int(dut.xgmiiTxd.value), int(dut.xgmiiTxc.value))) + + capture = cocotb.start_soon(capture_words(8)) + + dut.txLsData.value = CXP_K28_1 + dut.txLsDataK.value = 1 + dut.txLsValid.value = 1 + await RisingEdge(dut.clk) + await Timer(1, unit="ns") + dut.txLsValid.value = 0 + + await capture + + partial_packet = None + for start in range(len(observed) - 3): + words = observed[start : start + 4] + if words[0] == (_start_word(rate=1, update=1), 0x1): + partial_packet = words + break + + assert partial_packet is not None + assert partial_packet[1:] == [ + (0xBC023C02, 0x0), + (0xBC023C02, 0x0), + ((CXPOF_IDLE << 24) | (CXPOF_TERM << 16), 0xC), + ] + + def test_CoaXPressOverFiberBridgeTx(): run_surf_vhdl_test( test_file=__file__, diff --git a/tests/protocols/coaxpress/test_CoaXPressRx.py b/tests/protocols/coaxpress/test_CoaXPressRx.py index 8b592aaf31..194e890679 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRx.py +++ b/tests/protocols/coaxpress/test_CoaXPressRx.py @@ -24,10 +24,13 @@ # the real FIFO/FSM sequencing without introducing unrelated clock skew. import cocotb +import pytest -from tests.common.regression_utils import run_surf_vhdl_test, start_lockstep_clocks +from tests.common.regression_utils import env_int, parameter_case, run_surf_vhdl_test, start_lockstep_clocks from tests.protocols.coaxpress.coaxpress_test_utils import ( CXP_EOP, + CXP_IDLE, + CXP_IDLE_K, CXP_IO_ACK, CXP_MARKER, CXP_PKT_CTRL_ACK_NO_TAG, @@ -36,6 +39,7 @@ CXP_PKT_IMAGE_LINE, CXP_SOP, append_snapshot_if_valid, + pack_words, reset_signals, repeat_byte, send_rx_word, @@ -79,6 +83,13 @@ 0x00200010, ] + +def _pack_lane_nibbles(values: list[int]) -> int: + packed = 0 + for index, value in enumerate(values): + packed |= (value & 0xF) << (4 * index) + return packed + def _capture_outputs( dut, *, @@ -118,8 +129,21 @@ def _capture_outputs( trig_ack_cycles.append(cycle_index) +async def _send_multi_lane_word(dut, *, lane_words: list[int], lane_ks: list[int], link_up: int) -> None: + num_lanes = env_int("NUM_LANES_G", default=1) + await send_rx_word( + dut, + data=pack_words(lane_words + [CXP_IDLE] * (num_lanes - len(lane_words))), + data_k=_pack_lane_nibbles(lane_ks + [CXP_IDLE_K] * (num_lanes - len(lane_ks))), + clk=dut.rxClk, + link_up=link_up, + ) + + @cocotb.test() async def coaxpress_rx_one_lane_integration_test(dut): + if env_int("NUM_LANES_G", default=1) != 1: + return start_lockstep_clocks(dut.dataClk, dut.cfgClk, dut.txClk, dut.rxClk, period_ns=4.0) set_initial_values( dut, @@ -229,10 +253,134 @@ async def coaxpress_rx_one_lane_integration_test(dut): ] -def test_CoaXPressRx(): +@cocotb.test() +async def coaxpress_rx_two_lane_mux_rotation_test(dut): + if env_int("NUM_LANES_G", default=1) != 2: + return + + start_lockstep_clocks(dut.dataClk, dut.cfgClk, dut.txClk, dut.rxClk, period_ns=4.0) + set_initial_values( + dut, + { + "rxData": 0, + "rxDataK": 0, + "rxLinkUp": 0x3, + "rxFsmRst": 0, + "rxNumberOfLane": 1, + "dataTReady": 1, + "hdrTReady": 1, + }, + ) + await reset_signals( + dut, + clk=dut.rxClk, + reset_names=("dataRst", "cfgRst", "txRst", "rxRst"), + assert_cycles=4, + release_cycles=4, + ) + + data_beats: list[tuple[int, int, int, int]] = [] + hdr_beats: list[tuple[int, int, int, int]] = [] + + async def capture(cycle_index: int) -> None: + _capture_outputs( + dut, + cfg_beats=[], + data_beats=data_beats, + hdr_beats=hdr_beats, + event_tags=[], + trig_ack_cycles=[], + cycle_index=cycle_index, + ) + + lane0_sequence = [ + ([CXP_SOP, CXP_IDLE], [0xF, CXP_IDLE_K]), + ([repeat_byte(0x01), CXP_IDLE], [0x0, CXP_IDLE_K]), + ([repeat_byte(0x22), CXP_IDLE], [0x0, CXP_IDLE_K]), + ([repeat_byte(0x33), CXP_IDLE], [0x0, CXP_IDLE_K]), + ([repeat_byte(0x00), CXP_IDLE], [0x0, CXP_IDLE_K]), + ([repeat_byte(25), CXP_IDLE], [0x0, CXP_IDLE_K]), + ([CXP_MARKER, CXP_IDLE], [0xF, CXP_IDLE_K]), + ([repeat_byte(CXP_PKT_IMAGE_HEADER), CXP_IDLE], [0x0, CXP_IDLE_K]), + *[([word, CXP_IDLE], [0xF, CXP_IDLE_K]) for word in HEADER_WORDS], + ([CXP_SOP, CXP_IDLE], [0xF, CXP_IDLE_K]), + ([repeat_byte(0x01), CXP_IDLE], [0x0, CXP_IDLE_K]), + ([repeat_byte(0x44), CXP_IDLE], [0x0, CXP_IDLE_K]), + ([repeat_byte(0x55), CXP_IDLE], [0x0, CXP_IDLE_K]), + ([repeat_byte(0x00), CXP_IDLE], [0x0, CXP_IDLE_K]), + ([repeat_byte(5), CXP_IDLE], [0x0, CXP_IDLE_K]), + ([CXP_MARKER, CXP_IDLE], [0xF, CXP_IDLE_K]), + ([repeat_byte(CXP_PKT_IMAGE_LINE), CXP_IDLE], [0x0, CXP_IDLE_K]), + ([0x11111111, CXP_IDLE], [0x0, CXP_IDLE_K]), + ([0x22222222, CXP_IDLE], [0x0, CXP_IDLE_K]), + ([0x33333333, CXP_IDLE], [0x0, CXP_IDLE_K]), + ([CXP_EOP, CXP_IDLE], [0xF, CXP_IDLE_K]), + ] + lane1_sequence = [ + ([CXP_IDLE, CXP_SOP], [CXP_IDLE_K, 0xF]), + ([CXP_IDLE, repeat_byte(0x01)], [CXP_IDLE_K, 0x0]), + ([CXP_IDLE, repeat_byte(0x22)], [CXP_IDLE_K, 0x0]), + ([CXP_IDLE, repeat_byte(0x33)], [CXP_IDLE_K, 0x0]), + ([CXP_IDLE, repeat_byte(0x00)], [CXP_IDLE_K, 0x0]), + ([CXP_IDLE, repeat_byte(25)], [CXP_IDLE_K, 0x0]), + ([CXP_IDLE, CXP_MARKER], [CXP_IDLE_K, 0xF]), + ([CXP_IDLE, repeat_byte(CXP_PKT_IMAGE_HEADER)], [CXP_IDLE_K, 0x0]), + *[([CXP_IDLE, word], [CXP_IDLE_K, 0xF]) for word in HEADER_WORDS], + ([CXP_IDLE, CXP_SOP], [CXP_IDLE_K, 0xF]), + ([CXP_IDLE, repeat_byte(0x01)], [CXP_IDLE_K, 0x0]), + ([CXP_IDLE, repeat_byte(0x44)], [CXP_IDLE_K, 0x0]), + ([CXP_IDLE, repeat_byte(0x55)], [CXP_IDLE_K, 0x0]), + ([CXP_IDLE, repeat_byte(0x00)], [CXP_IDLE_K, 0x0]), + ([CXP_IDLE, repeat_byte(5)], [CXP_IDLE_K, 0x0]), + ([CXP_IDLE, CXP_MARKER], [CXP_IDLE_K, 0xF]), + ([CXP_IDLE, repeat_byte(CXP_PKT_IMAGE_LINE)], [CXP_IDLE_K, 0x0]), + ([CXP_IDLE, 0x44444444], [CXP_IDLE_K, 0x0]), + ([CXP_IDLE, 0x55555555], [CXP_IDLE_K, 0x0]), + ([CXP_IDLE, 0x66666666], [CXP_IDLE_K, 0x0]), + ([CXP_IDLE, CXP_EOP], [CXP_IDLE_K, 0xF]), + ] + + cycle_index = 0 + for lane_words, lane_ks in lane0_sequence: + await _send_multi_lane_word(dut, lane_words=lane_words, lane_ks=lane_ks, link_up=0x3) + await capture(cycle_index) + cycle_index += 1 + + for _ in range(12): + await _send_multi_lane_word(dut, lane_words=[CXP_IDLE, CXP_IDLE], lane_ks=[CXP_IDLE_K, CXP_IDLE_K], link_up=0x3) + await capture(cycle_index) + cycle_index += 1 + + for lane_words, lane_ks in lane1_sequence: + await _send_multi_lane_word(dut, lane_words=lane_words, lane_ks=lane_ks, link_up=0x3) + await capture(cycle_index) + cycle_index += 1 + + for _ in range(80): + await _send_multi_lane_word(dut, lane_words=[CXP_IDLE, CXP_IDLE], lane_ks=[CXP_IDLE_K, CXP_IDLE_K], link_up=0x3) + await capture(cycle_index) + cycle_index += 1 + + assert [beat[0] for beat in hdr_beats] == EXPECTED_HDR_WORDS * 2 + assert [beat[0] for beat in data_beats[:3]] == [0x11111111, 0x22222222, 0x33333333] + assert 0x44444444 in [beat[0] for beat in data_beats] + assert 0x55555555 in [beat[0] for beat in data_beats] + assert any(beat[2] == 1 for beat in data_beats) + + +PARAMETER_SWEEP = [ + parameter_case("single_lane", NUM_LANES_G="1", RX_FSM_CNT_WIDTH_G="8"), + parameter_case("dual_lane", NUM_LANES_G="2", RX_FSM_CNT_WIDTH_G="8"), +] + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +def test_CoaXPressRx(parameters): run_surf_vhdl_test( test_file=__file__, toplevel="surf.coaxpressrxwrapper", + parameters=parameters, + extra_env=parameters, extra_vhdl_sources={ "surf": [ "protocols/coaxpress/core/rtl/CoaXPressPkg.vhd", diff --git a/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py b/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py index 7cb846a8e6..ae46e06bb6 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py +++ b/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py @@ -25,12 +25,14 @@ import pytest from cocotb.triggers import RisingEdge, Timer -from tests.common.regression_utils import parameter_case, run_surf_vhdl_test +from tests.common.regression_utils import env_int, parameter_case, run_surf_vhdl_test from tests.protocols.coaxpress.coaxpress_test_utils import ( CXP_MARKER, CXP_PKT_IMAGE_HEADER, CXP_PKT_IMAGE_LINE, cycle, + keep_for_words, + lane_keep_mask, pack_words, repeat_byte, reset_dut, @@ -73,6 +75,10 @@ async def _send_handshaked_beat(dut, *, data: int, keep: int, last: int = 0) -> dut.sAxisTLast.value = 0 +def _beat_data(words: list[int], *, num_lanes: int) -> int: + return pack_words(words + [0] * (num_lanes - len(words))) + + def _header_words() -> list[int]: return [ repeat_byte(0x12), @@ -117,6 +123,8 @@ def _expected_header_data() -> int: @cocotb.test() async def coaxpress_rx_hs_fsm_header_and_lines_test(dut): + if env_int("NUM_LANES_G", default=1) != 1: + return start_clock(dut.rxClk) dut.rxRst.setimmediatevalue(1) dut.rxFsmRst.setimmediatevalue(0) @@ -167,6 +175,8 @@ async def coaxpress_rx_hs_fsm_header_and_lines_test(dut): @cocotb.test() async def coaxpress_rx_hs_fsm_malformed_header_recovery_test(dut): + if env_int("NUM_LANES_G", default=1) != 1: + return start_clock(dut.rxClk) dut.rxRst.setimmediatevalue(1) dut.rxFsmRst.setimmediatevalue(0) @@ -231,7 +241,122 @@ async def coaxpress_rx_hs_fsm_malformed_header_recovery_test(dut): ] -PARAMETER_SWEEP = [parameter_case("single_lane", NUM_LANES_G="1", RX_FSM_CNT_WIDTH_G="8")] +@cocotb.test() +async def coaxpress_rx_hs_fsm_two_lane_step_alignment_test(dut): + if env_int("NUM_LANES_G", default=1) != 2: + return + + start_clock(dut.rxClk) + dut.rxRst.setimmediatevalue(1) + dut.rxFsmRst.setimmediatevalue(0) + dut.sAxisTValid.setimmediatevalue(0) + dut.sAxisTData.setimmediatevalue(0) + dut.sAxisTKeep.setimmediatevalue(0) + dut.sAxisTLast.setimmediatevalue(0) + await reset_dut(dut, reset_names=("rxRst",)) + + header_beats: list[dict[str, int]] = [] + data_beats: list[dict[str, int]] = [] + header_words = [ + repeat_byte(0xA1), + repeat_byte(0x12), + repeat_byte(0x34), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x03), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x01), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x03), + repeat_byte(0x00), + repeat_byte(0x02), + repeat_byte(0x00), + repeat_byte(0x04), + repeat_byte(0x5E), + ] + + await _send_handshaked_beat( + dut, + data=_beat_data([CXP_MARKER, repeat_byte(CXP_PKT_IMAGE_HEADER)], num_lanes=2), + keep=lane_keep_mask([0, 1]), + ) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + for index in range(0, len(header_words), 2): + words = header_words[index : index + 2] + await _send_handshaked_beat( + dut, + data=_beat_data(words, num_lanes=2), + keep=lane_keep_mask(list(range(len(words)))), + ) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + + await _send_handshaked_beat( + dut, + data=_beat_data([CXP_MARKER], num_lanes=2), + keep=lane_keep_mask([0]), + ) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + await _send_handshaked_beat( + dut, + data=_beat_data([repeat_byte(CXP_PKT_IMAGE_LINE), 0x11111111], num_lanes=2), + keep=lane_keep_mask([0, 1]), + ) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + await _send_handshaked_beat( + dut, + data=_beat_data([0x22222222, 0x33333333], num_lanes=2), + keep=lane_keep_mask([0, 1]), + ) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + + for _ in range(8): + await RisingEdge(dut.rxClk) + await Timer(1, unit="ns") + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + + assert header_beats == [ + { + "hdrTData": pack_words( + [ + 0x12345EA1, + 0x00000003, + 0x00000000, + 0x00000001, + 0x00000000, + 0x00000003, + 0x00040002, + ] + ), + "hdrTLast": 1, + "hdrTSof": 1, + } + ] + assert data_beats == [ + { + "dataTData": pack_words([0x11111111, 0x22222222]), + "dataTKeep": keep_for_words(2), + "dataTLast": 0, + }, + { + "dataTData": 0x33333333, + "dataTKeep": keep_for_words(2), + "dataTLast": 1, + }, + ] + + +PARAMETER_SWEEP = [ + parameter_case("single_lane", NUM_LANES_G="1", RX_FSM_CNT_WIDTH_G="8"), + parameter_case("dual_lane", NUM_LANES_G="2", RX_FSM_CNT_WIDTH_G="8"), +] @pytest.mark.parametrize("parameters", PARAMETER_SWEEP) diff --git a/tests/protocols/coaxpress/test_CoaXPressRxLane.py b/tests/protocols/coaxpress/test_CoaXPressRxLane.py index b6ad1e9edb..732b5c3d2c 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRxLane.py +++ b/tests/protocols/coaxpress/test_CoaXPressRxLane.py @@ -138,6 +138,16 @@ async def drive(data: int, data_k: int, *, link_up: int = 1) -> None: await drive(0xCAFEBABE, 0x0) await drive(CXP_EOP, 0xF) + # Drive one alternate-success acknowledgment code. The current RTL maps + # 0x04 to the same zero-success status word as 0x01. + await drive(CXP_SOP, 0xF) + await drive(repeat_byte(CXP_PKT_CTRL_ACK_NO_TAG), 0x0) + await drive(repeat_byte(0x04), 0x0) + await drive(0x04000000, 0x0) + await drive(0x76543210, 0x0) + await drive(0x0BADCAFE, 0x0) + await drive(CXP_EOP, 0xF) + # Drive one spec-shaped tagged read acknowledgment. The current RTL skips # the tag word, then forwards the first reply-data word with a zeroed # success status in the low 32 bits. @@ -150,6 +160,14 @@ async def drive(data: int, data_k: int, *, link_up: int = 1) -> None: await drive(0xFEEDBEEF, 0x0) await drive(CXP_EOP, 0xF) + # Heartbeat first keeps the on-wire ordering consistent before the event. + await drive(CXP_SOP, 0xF) + await drive(repeat_byte(CXP_PKT_HEARTBEAT), 0x0) + for word in range(0x20, 0x2C): + await drive(repeat_byte(word), 0x0) + await drive(0xB6B6B6B6, 0x0) + await drive(CXP_EOP, 0xF) + # Drive a fuller event packet shape. The current RTL only consumes the # prefix through the Packet Tag field, where it exports the tag and returns # to IDLE; later size/data/trailer words are present to keep the on-wire @@ -165,18 +183,17 @@ async def drive(data: int, data_k: int, *, link_up: int = 1) -> None: await drive(0xA5A5A5A5, 0x0) await drive(CXP_EOP, 0xF) - # Heartbeat still exercises the current 12-byte payload collector, followed - # by a nominal packet trailer. + # A truncated event prefix must not raise a second event pulse. await drive(CXP_SOP, 0xF) - await drive(repeat_byte(CXP_PKT_HEARTBEAT), 0x0) - for word in range(0x20, 0x2C): + await drive(repeat_byte(CXP_PKT_EVENT), 0x0) + for word in (0xAA, 0xBB, 0xCC, 0xDD): await drive(repeat_byte(word), 0x0) - await drive(0xB6B6B6B6, 0x0) await drive(CXP_EOP, 0xF) await drive(CXP_IDLE, CXP_IDLE_K) assert cfg_beats == [ {"cfgTData": (0x01234567 << 32)}, + {"cfgTData": (0x76543210 << 32)}, {"cfgTData": (0x89ABCDEF << 32)}, ] assert event_pulses == [(1, 0x5A)] diff --git a/tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py b/tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py index 25c2a1708c..e6d9ec3d43 100644 --- a/tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py +++ b/tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py @@ -157,6 +157,37 @@ async def pulse_again_mid_message() -> None: assert second_trigger is not None +@cocotb.test() +async def coaxpress_tx_ls_fsm_rate0_inverted_trigger_test(dut): + # Exercise the slower heartbeat cadence plus the inverted trigger mapping + # the current RTL implements on the rising edge. + start_clock(dut.txClk) + dut.txRst.setimmediatevalue(1) + dut.cfgTValid.setimmediatevalue(0) + dut.cfgTData.setimmediatevalue(0) + dut.cfgTUser.setimmediatevalue(0) + dut.txTrig.setimmediatevalue(0) + dut.txTrigInv.setimmediatevalue(1) + dut.txPulseWidth.setimmediatevalue(120) + dut.txRate.setimmediatevalue(0) + await reset_dut(dut, clk_name="txClk", reset_names=("txRst",)) + + await _pulse_trigger(dut) + strobes = await _collect_strobes(dut, count=24, timeout_cycles=5200) + + assert [strobes[index + 1][0] - strobes[index][0] for index in range(23)] == [150] * 23 + assert [(data, is_k) for _, data, is_k in strobes[:6]] == [ + (CXP_K28_4, 1), + (CXP_K28_2, 1), + (CXP_K28_2, 1), + (0x03, 0), + (0x03, 0), + (0x03, 0), + ] + + assert any((data, is_k) == IDLE_SEQUENCE[0] for _, data, is_k in strobes[6:]) + + def test_CoaXPressTxLsFsm(): run_surf_vhdl_test( test_file=__file__, From 8521e02fdd1c4f3e205fca7dec101e97f31ceb7a Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 21 Apr 2026 11:39:52 -0700 Subject: [PATCH 35/92] More coaxpress tests. --- docs/_meta/rtl_regression_handoff.md | 1 + docs/_meta/rtl_regression_progress.md | 1 + .../coaxpress/core/rtl/CoaXPressAxiL.vhd | 1 - .../coaxpress/core/rtl/CoaXPressCore.vhd | 2 +- .../wrappers/CoaXPressCoreDebugWrapper.vhd | 462 ++++++++++++++++ .../wrappers/CoaXPressRxCorePathWrapper.vhd | 188 +++++++ tests/protocols/coaxpress/README.md | 31 +- .../protocols/coaxpress/test_CoaXPressCore.py | 382 ++++++++++++- tests/protocols/coaxpress/test_CoaXPressRx.py | 502 +++++++++++++++++- .../coaxpress/test_CoaXPressRxHsFsm.py | 67 +++ 10 files changed, 1605 insertions(+), 32 deletions(-) create mode 100644 protocols/coaxpress/core/wrappers/CoaXPressCoreDebugWrapper.vhd create mode 100644 protocols/coaxpress/core/wrappers/CoaXPressRxCorePathWrapper.vhd diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index 9b0fb46472..67ca69e84f 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -26,6 +26,7 @@ - `EthMacRxImportXlgmii` and `EthMacTxExportXlgmii` are still placeholder no-op RTL; the checked-in tests now lock down that inert contract instead of claiming functional XLGMII support. - The remaining CoaXPress pure-VHDL gap is now `CoaXPressConfig`. The current CoaXPress receive benches now include a dual-lane `CoaXPressRxHsFsm` step/alignment case and a dual-lane `CoaXPressRx` lane-rotation case, but the receive side is still intentionally mixed-depth: top-level event handling only proves the current packet-prefix contract, and the multi-lane assembly checks still stop short of exhaustive per-lane stress coverage. - `tests/protocols/coaxpress/test_CoaXPressConfig.py` is intentionally checked in as a skipped investigation bench. When driven through the real SRP ingress, the current `CoaXPressConfig` / `SrpV3AxiLite` integration does not complete the request path within the bench timeout, so treat that as a likely RTL or integration defect to debug before re-enabling active assertions there. + - `tests/protocols/coaxpress/test_CoaXPressCore.py` now also carries an opt-in skipped known-issue bench for RX backpressure vs. FSM-error behavior. Enable it with `RUN_KNOWN_ISSUE_TESTS=1` and optionally shrink the load with `CXP_RX_OVERFLOW_STORM_FRAME_COUNT=`. The current local reproduction under sustained `M_DATA_TREADY=0` and repeated one-line image frames observed `RxFsmErrorCnt=2` while `RxOverflowCnt=0` at `96` frames, and a narrowing sweep showed no repro at `48` frames but a repro by `72` frames with `RxFsmErrorCnt=1` while `RxOverflowCnt=0`. That is closer to the user report than the earlier directed single-error tests and should be treated as a likely RTL defect under investigation. - For future CoaXPress work, treat the named packet classes and control bytes in `tests/protocols/coaxpress/coaxpress_test_utils.py` as shared spec anchors, not as optional local style. Those constants were normalized against the same `CXP-001-2021` / `CXPR-008-2021` references cited in `CoaXPressPkg.vhd`. Keep the packet-layer names aligned to the spec even where current RTL ports still use legacy `eventAck` naming on the receive side: `0x07` is an event packet and `0x08` is an event acknowledgment. - The current receive benches are intentionally mixed-depth: control-ack traffic is now driven with fuller spec-shaped framing, but the checked-in `CoaXPressRxLane` / `CoaXPressRx` event tests still only prove the current RTL contract of consuming the event prefix through the Packet Tag field. Do not describe that as full event-payload coverage until the RTL/parser is expanded and the bench follows it. - Current planning discipline: diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 5ed8d60817..816baeefc6 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -25,6 +25,7 @@ - Covered now under the current GHDL-only flow: `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, `CoaXPressRxHsFsm`, `CoaXPressRx`, `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressTx`, `CoaXPressCore`, `CoaXPressOverFiberBridgeRx`, `CoaXPressOverFiberBridgeTx`, and `CoaXPressOverFiberBridge` - Still open in the same pure-VHDL family: `CoaXPressConfig` - Blocked bench note: `tests/protocols/coaxpress/test_CoaXPressConfig.py` is checked in as a skipped investigation bench because the real SRP-driven request path does not complete under the current `CoaXPressConfig`/`SrpV3AxiLite` integration. Treat that as a likely RTL or integration defect to debug before re-enabling active assertions on the config return path. + - Known-issue bench note: `tests/protocols/coaxpress/test_CoaXPressCore.py` now also carries an opt-in skipped investigation bench for the user-reported RX backpressure path. When enabled with `RUN_KNOWN_ISSUE_TESTS=1`, the bench drives sustained `M_DATA_TREADY=0` pressure with repeated one-line image frames and encodes the expected software-facing behavior that `RxOverflowCnt` should rise before `RxFsmErrorCnt`. The current local reproduction showed `RxFsmErrorCnt=2` while `RxOverflowCnt=0` at `96` frames, and a narrowing sweep showed no repro at `48` frames but a repro by `72` frames (`RxFsmErrorCnt=1`, `RxOverflowCnt=0`), so treat that as a likely RTL defect until narrowed or disproved. - Spec discipline for this family: use the packet/control naming and byte values from `CXP-001-2021` and `CXPR-008-2021` via shared helpers, and keep future top-level/bridge benches explicit about whether they are proving normative spec behavior or only the currently validated RTL subset. At the packet layer, keep the published names even when current RTL signal names drift: `0x07` is an event packet and `0x08` is an event acknowledgment. - The checked-in RX benches now use more spec-shaped control-ack framing on the wire, include a dual-lane `CoaXPressRxHsFsm` step/alignment case and a dual-lane `CoaXPressRx` lane-rotation case, but the current receive-side event path still only observes the event packet prefix through the Packet Tag field before returning to IDLE. Keep that limitation documented rather than implying full event-payload decode coverage. - Most recent reusable bench pattern: diff --git a/protocols/coaxpress/core/rtl/CoaXPressAxiL.vhd b/protocols/coaxpress/core/rtl/CoaXPressAxiL.vhd index d4ee2db49b..a2235272b3 100755 --- a/protocols/coaxpress/core/rtl/CoaXPressAxiL.vhd +++ b/protocols/coaxpress/core/rtl/CoaXPressAxiL.vhd @@ -561,4 +561,3 @@ begin dataOut => dataReset); end rtl; - diff --git a/protocols/coaxpress/core/rtl/CoaXPressCore.vhd b/protocols/coaxpress/core/rtl/CoaXPressCore.vhd index 0bf3b4db0c..204e2405c1 100755 --- a/protocols/coaxpress/core/rtl/CoaXPressCore.vhd +++ b/protocols/coaxpress/core/rtl/CoaXPressCore.vhd @@ -230,7 +230,7 @@ begin rxFsmError => rxFsmError, -- Config Interface (cfgClk domain) cfgClk => cfgClk, - cfgRst => cfgClk, + cfgRst => cfgRst, configTimerSize => configTimerSize, configErrResp => configErrResp, configPktTag => configPktTag, diff --git a/protocols/coaxpress/core/wrappers/CoaXPressCoreDebugWrapper.vhd b/protocols/coaxpress/core/wrappers/CoaXPressCoreDebugWrapper.vhd new file mode 100644 index 0000000000..2d0d583bf7 --- /dev/null +++ b/protocols/coaxpress/core/wrappers/CoaXPressCoreDebugWrapper.vhd @@ -0,0 +1,462 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Debug cocotb-facing wrapper for CoaXPressCore issue triage +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.AxiLitePkg.all; +use surf.SsiPkg.all; + +entity CoaXPressCoreDebugWrapper is + generic ( + FORCE_RX_CTRL_G : boolean := false); + port ( + dataClk : in sl; + dataRst : in sl; + cfgClk : in sl; + cfgRst : in sl; + txClk : in sl; + txRst : in sl; + rxClk : in sl; + rxRst : in sl; + axilClk : in sl; + axilRst : in sl; + txTrig : in sl; + txLinkUp : in sl; + rxData : in slv(31 downto 0); + rxDataK : in slv(3 downto 0); + rxDispErr : in sl; + rxDecErr : in sl; + rxLinkUp : in sl; + gtRstAll : out sl; + txLsValid : out sl; + txLsData : out slv(7 downto 0); + txLsDataK : out sl; + txLsRate : out sl; + txLsLaneEn : out slv(3 downto 0); + DBG_RX_FSM_RST : out sl; + DBG_RX_NUM_OF_LANE : out slv(2 downto 0); + DBG_RX_OVERFLOW : out sl; + DBG_RX_FSM_ERROR : out sl; + DBG_AXIL_OVERFLOW : out sl; + DBG_AXIL_FSM_ERROR : out sl; + S_AXI_AWADDR : in slv(11 downto 0); + S_AXI_AWPROT : in slv(2 downto 0); + S_AXI_AWVALID : in sl; + S_AXI_AWREADY : out sl; + S_AXI_WDATA : in slv(31 downto 0); + S_AXI_WSTRB : in slv(3 downto 0); + S_AXI_WVALID : in sl; + S_AXI_WREADY : out sl; + S_AXI_BRESP : out slv(1 downto 0); + S_AXI_BVALID : out sl; + S_AXI_BREADY : in sl; + S_AXI_ARADDR : in slv(11 downto 0); + S_AXI_ARPROT : in slv(2 downto 0); + S_AXI_ARVALID : in sl; + S_AXI_ARREADY : out sl; + S_AXI_RDATA : out slv(31 downto 0); + S_AXI_RRESP : out slv(1 downto 0); + S_AXI_RVALID : out sl; + S_AXI_RREADY : in sl; + S_CFG_IB_TVALID : in sl; + S_CFG_IB_TDATA : in slv(255 downto 0); + S_CFG_IB_TKEEP : in slv(31 downto 0); + S_CFG_IB_TLAST : in sl; + S_CFG_IB_TUSER : in slv(1 downto 0); + S_CFG_IB_TREADY : out sl; + M_CFG_OB_TVALID : out sl; + M_CFG_OB_TDATA : out slv(255 downto 0); + M_CFG_OB_TKEEP : out slv(31 downto 0); + M_CFG_OB_TLAST : out sl; + M_CFG_OB_TUSER : out slv(1 downto 0); + M_CFG_OB_TREADY : in sl; + M_DATA_TVALID : out sl; + M_DATA_TDATA : out slv(31 downto 0); + M_DATA_TKEEP : out slv(3 downto 0); + M_DATA_TLAST : out sl; + M_DATA_TUSER : out slv(0 downto 0); + M_DATA_TREADY : in sl; + M_HDR_TVALID : out sl; + M_HDR_TDATA : out slv(31 downto 0); + M_HDR_TKEEP : out slv(3 downto 0); + M_HDR_TLAST : out sl; + M_HDR_TUSER : out slv(0 downto 0); + M_HDR_TREADY : in sl); +end entity CoaXPressCoreDebugWrapper; + +architecture rtl of CoaXPressCoreDebugWrapper is + + constant DATA_AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(dataBytes => 4); + constant CFG_AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(dataBytes => 32); + + signal cfgIbMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal cfgIbSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal cfgObMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal cfgObSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal dataMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal dataSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal hdrMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal hdrSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + + signal rxClkVec : slv(0 downto 0); + signal rxRstVec : slv(0 downto 0); + signal rxDataVec : slv32Array(0 downto 0); + signal rxDataKVec : Slv4Array(0 downto 0); + signal rxDispErrVec : slv(0 downto 0); + signal rxDecErrVec : slv(0 downto 0); + signal rxLinkUpVec : slv(0 downto 0); + + signal unusedClk : sl; + signal unusedRst : sl; + + signal cfgTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal cfgTxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal cfgRxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + + signal configTimerSize : slv(31 downto 0); + signal configErrResp : sl; + signal configPktTag : sl; + + signal txTrigInv : sl; + signal txPulseWidth : slv(31 downto 0); + signal swTrig : sl; + signal txTrigDrop : sl; + + signal eventAck : sl; + signal eventTag : slv(7 downto 0); + + signal trigAck : sl; + signal txLsRateInt : sl; + + signal rxOverflow : sl; + signal rxFsmError : sl; + signal rxFsmRst : sl; + signal rxFsmRstAxil : sl; + signal rxNumberOfLane : slv(2 downto 0); + signal rxNumberOfLaneAxil : slv(2 downto 0); + +begin + + txLsRate <= txLsRateInt; + DBG_RX_FSM_RST <= rxFsmRst; + DBG_RX_NUM_OF_LANE <= rxNumberOfLane; + DBG_RX_OVERFLOW <= rxOverflow; + DBG_RX_FSM_ERROR <= rxFsmError; + + rxFsmRst <= '0' when FORCE_RX_CTRL_G else rxFsmRstAxil; + rxNumberOfLane <= (others => '0') when FORCE_RX_CTRL_G else rxNumberOfLaneAxil; + + rxClkVec(0) <= rxClk; + rxRstVec(0) <= rxRst; + rxDataVec(0) <= rxData; + rxDataKVec(0) <= rxDataK; + rxDispErrVec(0) <= rxDispErr; + rxDecErrVec(0) <= rxDecErr; + rxLinkUpVec(0) <= rxLinkUp; + + U_Axil : entity surf.SlaveAxiLiteIpIntegrator + generic map ( + INTERFACENAME => "S_AXI", + EN_ERROR_RESP => true, + HAS_PROT => 1, + HAS_WSTRB => 1, + FREQ_HZ => 100000000, + ADDR_WIDTH => 12) + port map ( + S_AXI_ACLK => axilClk, + S_AXI_ARESETN => not axilRst, + S_AXI_AWADDR => S_AXI_AWADDR, + S_AXI_AWPROT => S_AXI_AWPROT, + S_AXI_AWVALID => S_AXI_AWVALID, + S_AXI_AWREADY => S_AXI_AWREADY, + S_AXI_WDATA => S_AXI_WDATA, + S_AXI_WSTRB => S_AXI_WSTRB, + S_AXI_WVALID => S_AXI_WVALID, + S_AXI_WREADY => S_AXI_WREADY, + S_AXI_BRESP => S_AXI_BRESP, + S_AXI_BVALID => S_AXI_BVALID, + S_AXI_BREADY => S_AXI_BREADY, + S_AXI_ARADDR => S_AXI_ARADDR, + S_AXI_ARPROT => S_AXI_ARPROT, + S_AXI_ARVALID => S_AXI_ARVALID, + S_AXI_ARREADY => S_AXI_ARREADY, + S_AXI_RDATA => S_AXI_RDATA, + S_AXI_RRESP => S_AXI_RRESP, + S_AXI_RVALID => S_AXI_RVALID, + S_AXI_RREADY => S_AXI_RREADY, + axilClk => open, + axilRst => open, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + + U_CfgIb : entity surf.SlaveAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "S_CFG_IB", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 2, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 32) + port map ( + S_AXIS_ACLK => cfgClk, + S_AXIS_ARESETN => not cfgRst, + S_AXIS_TVALID => S_CFG_IB_TVALID, + S_AXIS_TDATA => S_CFG_IB_TDATA, + S_AXIS_TSTRB => (others => '1'), + S_AXIS_TKEEP => S_CFG_IB_TKEEP, + S_AXIS_TLAST => S_CFG_IB_TLAST, + S_AXIS_TDEST => "0", + S_AXIS_TID => "0", + S_AXIS_TUSER => S_CFG_IB_TUSER, + S_AXIS_TREADY => S_CFG_IB_TREADY, + axisClk => unusedClk, + axisRst => unusedRst, + axisMaster => cfgIbMaster, + axisSlave => cfgIbSlave); + + U_CfgOb : entity surf.MasterAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "M_CFG_OB", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 2, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 32) + port map ( + M_AXIS_ACLK => cfgClk, + M_AXIS_ARESETN => not cfgRst, + M_AXIS_TVALID => M_CFG_OB_TVALID, + M_AXIS_TDATA => M_CFG_OB_TDATA, + M_AXIS_TSTRB => open, + M_AXIS_TKEEP => M_CFG_OB_TKEEP, + M_AXIS_TLAST => M_CFG_OB_TLAST, + M_AXIS_TDEST => open, + M_AXIS_TID => open, + M_AXIS_TUSER => M_CFG_OB_TUSER, + M_AXIS_TREADY => M_CFG_OB_TREADY, + axisClk => open, + axisRst => open, + axisMaster => cfgObMaster, + axisSlave => cfgObSlave); + + U_Data : entity surf.MasterAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "M_DATA", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 1, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 4) + port map ( + M_AXIS_ACLK => dataClk, + M_AXIS_ARESETN => not dataRst, + M_AXIS_TVALID => M_DATA_TVALID, + M_AXIS_TDATA => M_DATA_TDATA, + M_AXIS_TSTRB => open, + M_AXIS_TKEEP => M_DATA_TKEEP, + M_AXIS_TLAST => M_DATA_TLAST, + M_AXIS_TDEST => open, + M_AXIS_TID => open, + M_AXIS_TUSER => M_DATA_TUSER, + M_AXIS_TREADY => M_DATA_TREADY, + axisClk => open, + axisRst => open, + axisMaster => dataMaster, + axisSlave => dataSlave); + + U_Hdr : entity surf.MasterAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "M_HDR", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 1, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 4) + port map ( + M_AXIS_ACLK => dataClk, + M_AXIS_ARESETN => not dataRst, + M_AXIS_TVALID => M_HDR_TVALID, + M_AXIS_TDATA => M_HDR_TDATA, + M_AXIS_TSTRB => open, + M_AXIS_TKEEP => M_HDR_TKEEP, + M_AXIS_TLAST => M_HDR_TLAST, + M_AXIS_TDEST => open, + M_AXIS_TID => open, + M_AXIS_TUSER => M_HDR_TUSER, + M_AXIS_TREADY => M_HDR_TREADY, + axisClk => open, + axisRst => open, + axisMaster => hdrMaster, + axisSlave => hdrSlave); + + U_Config : entity surf.CoaXPressConfig + generic map ( + TPD_G => 1 ns, + AXIS_CONFIG_G => CFG_AXIS_CONFIG_C) + port map ( + cfgClk => cfgClk, + cfgRst => cfgRst, + configTimerSize => configTimerSize, + configErrResp => configErrResp, + configPktTag => configPktTag, + cfgIbMaster => cfgIbMaster, + cfgIbSlave => cfgIbSlave, + cfgObMaster => cfgObMaster, + cfgObSlave => cfgObSlave, + cfgTxMaster => cfgTxMaster, + cfgTxSlave => cfgTxSlave, + cfgRxMaster => cfgRxMaster); + + U_Tx : entity surf.CoaXPressTx + generic map ( + TPD_G => 1 ns) + port map ( + cfgClk => cfgClk, + cfgRst => cfgRst, + cfgTxMaster => cfgTxMaster, + cfgTxSlave => cfgTxSlave, + eventAck => eventAck, + eventTag => eventTag, + txClk => txClk, + txRst => txRst, + txLsRate => txLsRateInt, + txLsValid => txLsValid, + txLsData => txLsData, + txLsDataK => txLsDataK, + txTrigInv => txTrigInv, + txPulseWidth => txPulseWidth, + swTrig => swTrig, + txTrig => txTrig, + txTrigDrop => txTrigDrop); + + U_Rx : entity surf.CoaXPressRx + generic map ( + TPD_G => 1 ns, + NUM_LANES_G => 1, + RX_FSM_CNT_WIDTH_G => 8, + AXIS_CONFIG_G => DATA_AXIS_CONFIG_C) + port map ( + dataClk => dataClk, + dataRst => dataRst, + dataMaster => dataMaster, + dataSlave => dataSlave, + imageHdrMaster => hdrMaster, + imageHdrSlave => hdrSlave, + cfgClk => cfgClk, + cfgRst => cfgRst, + cfgRxMaster => cfgRxMaster, + eventAck => eventAck, + eventTag => eventTag, + txClk => txClk, + txRst => txRst, + trigAck => trigAck, + rxClk => rxClkVec, + rxRst => rxRstVec, + rxData => rxDataVec, + rxDataK => rxDataKVec, + rxLinkUp => rxLinkUpVec, + rxOverflow => rxOverflow, + rxFsmError => rxFsmError, + rxFsmRst => rxFsmRst, + rxNumberOfLane => rxNumberOfLane); + + U_AxilCore : entity surf.CoaXPressAxiL + generic map ( + TPD_G => 1 ns, + NUM_LANES_G => 1, + STATUS_CNT_WIDTH_G => 8, + RX_FSM_CNT_WIDTH_G => 8, + AXIL_CLK_FREQ_G => 100.0E+6, + AXIS_CLK_FREQ_G => 100.0E+6, + AXIS_CONFIG_G => DATA_AXIS_CONFIG_C) + port map ( + gtRstAll => gtRstAll, + txClk => txClk, + txRst => txRst, + txTrigInv => txTrigInv, + txPulseWidth => txPulseWidth, + txTrig => txTrig, + swTrig => swTrig, + txTrigDrop => txTrigDrop, + trigAck => trigAck, + txLinkUp => txLinkUp, + txLsRate => txLsRateInt, + txLsLaneEn => txLsLaneEn, + rxClk => rxClkVec, + rxRst => rxRstVec, + rxDispErr => rxDispErrVec, + rxDecErr => rxDecErrVec, + rxLinkUp => rxLinkUpVec, + rxFsmRst => rxFsmRstAxil, + rxNumberOfLane => rxNumberOfLaneAxil, + rxOverflow => rxOverflow, + rxFsmError => rxFsmError, + cfgClk => cfgClk, + cfgRst => cfgRst, + configTimerSize => configTimerSize, + configErrResp => configErrResp, + configPktTag => configPktTag, + dataClk => dataClk, + dataRst => dataRst, + dataMaster => dataMaster, + dataSlave => dataSlave, + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + + U_DbgRxOverflow : entity surf.SynchronizerOneShot + generic map ( + TPD_G => 1 ns) + port map ( + clk => axilClk, + rst => axilRst, + dataIn => rxOverflow, + dataOut => DBG_AXIL_OVERFLOW); + + U_DbgRxFsmError : entity surf.SynchronizerOneShot + generic map ( + TPD_G => 1 ns) + port map ( + clk => axilClk, + rst => axilRst, + dataIn => rxFsmError, + dataOut => DBG_AXIL_FSM_ERROR); + +end architecture rtl; diff --git a/protocols/coaxpress/core/wrappers/CoaXPressRxCorePathWrapper.vhd b/protocols/coaxpress/core/wrappers/CoaXPressRxCorePathWrapper.vhd new file mode 100644 index 0000000000..f8b49f1a28 --- /dev/null +++ b/protocols/coaxpress/core/wrappers/CoaXPressRxCorePathWrapper.vhd @@ -0,0 +1,188 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing CoaXPressRx wrapper using the core output path +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.SsiPkg.all; + +entity CoaXPressRxCorePathWrapper is + generic ( + NUM_LANES_G : positive range 1 to 8 := 1; + RX_FSM_CNT_WIDTH_G : positive range 1 to 24 := 8); + port ( + dataClk : in sl; + dataRst : in sl; + cfgClk : in sl; + cfgRst : in sl; + txClk : in sl; + txRst : in sl; + rxClk : in sl; + rxRst : in sl; + rxData : in slv(32*NUM_LANES_G-1 downto 0); + rxDataK : in slv(4*NUM_LANES_G-1 downto 0); + rxLinkUp : in slv(NUM_LANES_G-1 downto 0); + rxFsmRst : in sl; + rxNumberOfLane : in slv(2 downto 0); + dataTValid : out sl; + dataTData : out slv(31 downto 0); + dataTKeep : out slv(3 downto 0); + dataTLast : out sl; + dataTUser : out slv(0 downto 0); + dataTReady : in sl; + hdrTValid : out sl; + hdrTData : out slv(31 downto 0); + hdrTKeep : out slv(3 downto 0); + hdrTLast : out sl; + hdrTUser : out slv(0 downto 0); + hdrTReady : in sl; + cfgTValid : out sl; + cfgTData : out slv(63 downto 0); + cfgTKeep : out slv(7 downto 0); + cfgTLast : out sl; + eventAck : out sl; + eventTag : out slv(7 downto 0); + trigAck : out sl; + rxOverflow : out sl; + rxFsmError : out sl); +end entity CoaXPressRxCorePathWrapper; + +architecture rtl of CoaXPressRxCorePathWrapper is + + constant AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(dataBytes => 4); + + signal dataMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal dataSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal imageHdrMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal imageHdrSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal cfgRxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + + signal rxClkVec : slv(NUM_LANES_G-1 downto 0); + signal rxRstVec : slv(NUM_LANES_G-1 downto 0); + signal rxDataVec : slv32Array(NUM_LANES_G-1 downto 0); + signal rxDataKVec : Slv4Array(NUM_LANES_G-1 downto 0); + signal rxLinkUpVec : slv(NUM_LANES_G-1 downto 0); + + signal unusedDataClk : sl; + signal unusedDataRst : sl; + signal unusedHdrClk : sl; + signal unusedHdrRst : sl; + +begin + + GEN_LANE : for i in 0 to NUM_LANES_G-1 generate + begin + rxClkVec(i) <= rxClk; + rxRstVec(i) <= rxRst; + rxDataVec(i) <= rxData(32*i+31 downto 32*i); + rxDataKVec(i) <= rxDataK(4*i+3 downto 4*i); + rxLinkUpVec(i) <= rxLinkUp(i); + end generate GEN_LANE; + + cfgTValid <= cfgRxMaster.tValid; + cfgTData <= cfgRxMaster.tData(63 downto 0); + cfgTKeep <= cfgRxMaster.tKeep(7 downto 0); + cfgTLast <= cfgRxMaster.tLast; + + U_Data : entity surf.MasterAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "M_DATA", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 1, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 4) + port map ( + M_AXIS_ACLK => dataClk, + M_AXIS_ARESETN => not dataRst, + M_AXIS_TVALID => dataTValid, + M_AXIS_TDATA => dataTData, + M_AXIS_TSTRB => open, + M_AXIS_TKEEP => dataTKeep, + M_AXIS_TLAST => dataTLast, + M_AXIS_TDEST => open, + M_AXIS_TID => open, + M_AXIS_TUSER => dataTUser, + M_AXIS_TREADY => dataTReady, + axisClk => unusedDataClk, + axisRst => unusedDataRst, + axisMaster => dataMaster, + axisSlave => dataSlave); + + U_Hdr : entity surf.MasterAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "M_HDR", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 1, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 4) + port map ( + M_AXIS_ACLK => dataClk, + M_AXIS_ARESETN => not dataRst, + M_AXIS_TVALID => hdrTValid, + M_AXIS_TDATA => hdrTData, + M_AXIS_TSTRB => open, + M_AXIS_TKEEP => hdrTKeep, + M_AXIS_TLAST => hdrTLast, + M_AXIS_TDEST => open, + M_AXIS_TID => open, + M_AXIS_TUSER => hdrTUser, + M_AXIS_TREADY => hdrTReady, + axisClk => unusedHdrClk, + axisRst => unusedHdrRst, + axisMaster => imageHdrMaster, + axisSlave => imageHdrSlave); + + U_DUT : entity surf.CoaXPressRx + generic map ( + TPD_G => 1 ns, + NUM_LANES_G => NUM_LANES_G, + RX_FSM_CNT_WIDTH_G => RX_FSM_CNT_WIDTH_G, + AXIS_CONFIG_G => AXIS_CONFIG_C) + port map ( + dataClk => dataClk, + dataRst => dataRst, + dataMaster => dataMaster, + dataSlave => dataSlave, + imageHdrMaster => imageHdrMaster, + imageHdrSlave => imageHdrSlave, + cfgClk => cfgClk, + cfgRst => cfgRst, + cfgRxMaster => cfgRxMaster, + eventAck => eventAck, + eventTag => eventTag, + txClk => txClk, + txRst => txRst, + trigAck => trigAck, + rxClk => rxClkVec, + rxRst => rxRstVec, + rxData => rxDataVec, + rxDataK => rxDataKVec, + rxLinkUp => rxLinkUpVec, + rxOverflow => rxOverflow, + rxFsmError => rxFsmError, + rxFsmRst => rxFsmRst, + rxNumberOfLane => rxNumberOfLane); + +end architecture rtl; diff --git a/tests/protocols/coaxpress/README.md b/tests/protocols/coaxpress/README.md index bcdf247d7d..dbe33c0ec8 100644 --- a/tests/protocols/coaxpress/README.md +++ b/tests/protocols/coaxpress/README.md @@ -58,7 +58,7 @@ intentional limitation, not as silent proof of complete spec compliance. | `test_CoaXPressTxLsFsm.py` | `CoaXPressTxLsFsm` | Low-speed idle cadence and default trigger serialization, section `9.3.1.1` / Table 15 | Partial protocol | | `test_CoaXPressTx.py` | `CoaXPressTx` | Control/event-acknowledgment arbitration and software-trigger path across the TX assembly | RTL-contract with spec packet classes | | `test_CoaXPressConfig.py` | `CoaXPressConfig` | Control command packet formatting and tag handling, section `9.6.1.2` / `9.6.2` | Checked in but skipped | -| `test_CoaXPressCore.py` | `CoaXPressCore` | AXI-Lite control of tagged config request generation into the top-level TX path | RTL-contract with spec request prefix | +| `test_CoaXPressCore.py` | `CoaXPressCore` | AXI-Lite control of tagged config request generation plus software-visible `RxOverflowCnt` / `RxFsmErrorCnt` status behavior at the full-core boundary | RTL-contract with spec request prefix and top-level error-status checks | | `test_CoaXPressOverFiberBridgeTx.py` | `CoaXPressOverFiberBridgeTx` | CXPoF start/control/payload/terminate words, section `6.3.1` to `6.3.6` in `CXPR-008-2021` | Near-normative subset | | `test_CoaXPressOverFiberBridgeRx.py` | `CoaXPressOverFiberBridgeRx` | CXPoF start-word decode back into CoaXPress packet and `IO_ACK` words | Partial protocol | | `test_CoaXPressOverFiberBridge.py` | `CoaXPressOverFiberBridge` | Top-level 32b/64b gearbox integration around the bridge leaf mapping | RTL-contract with spec framing | @@ -154,6 +154,32 @@ The image-path benches are the strongest spec-aligned receive tests today: spec-shaped stream headers, but the emphasis there is on receive-lane state behavior rather than on a full normative stream CRC checker. +### Software-visible overflow and FSM-error status + +`test_CoaXPressCore.py` now covers the two receive-status counters exposed to +software through `CoaXPressAxiL`: + +- `RxOverflowCnt` + - holds the image-header output path stalled until the top-level receive + assembly overflows, then checks that the AXI-Lite counter increments and + the path drains once backpressure is released +- `RxFsmErrorCnt` + - injects a full image-header packet with one corrupted repeated-byte field, + checks that the top-level counter increments, then verifies the count + stays stable during idle cycles and that a later clean image transaction is + still accepted +- `coaxpress_core_rx_overflow_does_not_trigger_fsm_error_storm_known_issue_test` + - checked in as an opt-in skipped investigation bench + - drives sustained receive-data backpressure with repeated one-line image + frames and encodes the expected software-facing behavior: overflow should + count first, `RxFsmErrorCnt` should stay at zero, idle should not create an + error storm, and a later clean frame should still pass + - enable locally with `RUN_KNOWN_ISSUE_TESTS=1` and optionally narrow the + stress volume with `CXP_RX_OVERFLOW_STORM_FRAME_COUNT` + +This is intentionally a top-level software-facing check, not a replacement for +the lower-level malformed-header coverage in `test_CoaXPressRxHsFsm.py`. + ### CoaXPress over Fiber bridge The bridge benches map to `CXPR-008-2021`, especially: @@ -195,6 +221,9 @@ compliance coverage. The most important open limits are: - `CoaXPressConfig` is still skipped +- the checked-in known-issue core bench for overflow-vs-FSM-error behavior is + skipped by default until the receive-side backpressure interaction is + understood and fixed - receive-side event handling still proves only the current RTL prefix contract - trigger coverage still does not include the broader low-speed extra modes or the full high-speed trigger matrix diff --git a/tests/protocols/coaxpress/test_CoaXPressCore.py b/tests/protocols/coaxpress/test_CoaXPressCore.py index 31051e28be..3770cb0b80 100644 --- a/tests/protocols/coaxpress/test_CoaXPressCore.py +++ b/tests/protocols/coaxpress/test_CoaXPressCore.py @@ -9,47 +9,98 @@ ############################################################################## # Test methodology: -# - Sweep: Keep the first `CoaXPressCore` pass on the one-lane top-level path -# and focus on the unique cross-block integration that only the full core can -# exercise: AXI-Lite control of `configPktTag`/`txLsRate` into the config/TX -# assembly. +# - Sweep: Keep the current `CoaXPressCore` coverage on the one-lane top-level +# path, but extend it across the three core-only integration surfaces that +# software cares about: AXI-Lite control into TX/config, RX overflow status, +# and RX FSM-error counting/recovery. # - Stimulus: Program `configPktTag` and the fast low-speed rate over AXI-Lite, -# then send one SRPv3 read request through the core config ingress. -# - Checks: The top level must expose the programmed AXI-Lite register values -# back to software and serialize the corresponding tagged CoaXPress config -# request on the TX low-speed byte stream. -# - Timing: AXI-Lite writes, config ingress, and TX byte observation all run on -# the real module interfaces, so the bench checks the actual sequencing across -# `CoaXPressAxiL`, `CoaXPressConfig`, and `CoaXPressTx`. +# send one SRPv3 read request through the config ingress, then drive raw RX +# image-header traffic once with sustained software backpressure and once with +# a malformed header followed by a clean retry. +# - Checks: The core must expose the programmed AXI-Lite values back to +# software, serialize the matching tagged config request on TX, increment +# `RxOverflowCnt` when the output path cannot drain, increment +# `RxFsmErrorCnt` on malformed receive traffic, and still accept a later good +# image frame instead of remaining in a stuck error state. +# - Timing: AXI-Lite, config ingress, and the raw RX/data/header paths all run +# on the real top-level interfaces, so the bench checks the actual sequencing +# across `CoaXPressAxiL`, `CoaXPressConfig`, `CoaXPressRx`, and `CoaXPressTx`. + +import os import cocotb -from cocotb.triggers import with_timeout +from cocotb.triggers import Event, RisingEdge, Timer, with_timeout +from cocotb.utils import get_sim_time from cocotbext.axi import AxiLiteBus, AxiLiteMaster -from tests.common.regression_utils import run_surf_vhdl_test, start_lockstep_clocks +from tests.common.regression_utils import env_flag, env_int, run_surf_vhdl_test, start_lockstep_clocks from tests.protocols.coaxpress.coaxpress_test_utils import ( + CXP_IDLE, + CXP_IDLE_K, + CXP_MARKER, + CXP_PKT_IMAGE_HEADER, + CXP_PKT_IMAGE_LINE, CXP_SOP, + cycle, collect_stream_bytes, endian_swap32, find_subsequence, pack_u32_words_le, reset_signals, + repeat_byte, + send_rx_word, send_axis_payload, set_initial_values, word_to_bytes, ) -@cocotb.test() -async def coaxpress_core_tagged_config_tx_path_test(dut): - start_lockstep_clocks(dut.dataClk, dut.cfgClk, dut.txClk, dut.rxClk, dut.axilClk, period_ns=4.0) +def _image_header_words( + *, + stream_id: int = 0x12, + source_tag: int = 0x3456, + x_size: int = 3, + x_offs: int = 4, + y_size: int = 1, + y_offs: int = 5, + dsize_l: int = 1, + pixel_f: int = 0x0010, + tap_g: int = 0x0020, + flags: int = 0xAA, +) -> list[int]: + def rep24(value: int) -> list[int]: + return [ + repeat_byte((value >> 16) & 0xFF), + repeat_byte((value >> 8) & 0xFF), + repeat_byte(value & 0xFF), + ] + + return [ + repeat_byte(stream_id), + repeat_byte((source_tag >> 8) & 0xFF), + repeat_byte(source_tag & 0xFF), + *rep24(x_size), + *rep24(x_offs), + *rep24(y_size), + *rep24(y_offs), + *rep24(dsize_l), + repeat_byte((pixel_f >> 8) & 0xFF), + repeat_byte(pixel_f & 0xFF), + repeat_byte((tap_g >> 8) & 0xFF), + repeat_byte(tap_g & 0xFF), + repeat_byte(flags), + ] + + +async def _setup_core(axil_dut, *, data_ready: int = 1, hdr_ready: int = 1) -> AxiLiteMaster: + start_lockstep_clocks(axil_dut.dataClk, axil_dut.cfgClk, axil_dut.txClk, axil_dut.rxClk, axil_dut.axilClk, period_ns=4.0) set_initial_values( - dut, + axil_dut, { "txTrig": 0, "txLinkUp": 1, - "rxData": 0xB53C3CBC, - "rxDataK": 0x7, + "rxData": CXP_IDLE, + "rxDataK": CXP_IDLE_K, "rxDispErr": 0, "rxDecErr": 0, "rxLinkUp": 1, @@ -59,19 +110,114 @@ async def coaxpress_core_tagged_config_tx_path_test(dut): "S_CFG_IB_TLAST": 0, "S_CFG_IB_TUSER": 0, "M_CFG_OB_TREADY": 0, - "M_DATA_TREADY": 1, - "M_HDR_TREADY": 1, + "M_DATA_TREADY": data_ready, + "M_HDR_TREADY": hdr_ready, }, ) await reset_signals( - dut, - clk=dut.rxClk, + axil_dut, + clk=axil_dut.rxClk, reset_names=("dataRst", "cfgRst", "txRst", "rxRst", "axilRst"), assert_cycles=10, release_cycles=5, ) + axil = AxiLiteMaster(AxiLiteBus.from_prefix(axil_dut, "S_AXI"), axil_dut.axilClk, axil_dut.axilRst) + await axil.write_dword(0xFFC, 1) + await cycle(axil_dut.axilClk, 8) + return axil + + +async def _read_counter(axil: AxiLiteMaster, dut, offset: int) -> int: + await cycle(dut.axilClk, 8) + return await axil.read_dword(offset) + + +async def _send_stream_packet_words(dut, payload_words: list[int], *, stream_id: int = 0x22, packet_tag: int = 0x33) -> None: + words = [ + CXP_SOP, + repeat_byte(0x01), + repeat_byte(stream_id), + repeat_byte(packet_tag), + repeat_byte((len(payload_words) >> 8) & 0xFF), + repeat_byte(len(payload_words) & 0xFF), + *payload_words, + ] + for word in words: + await send_rx_word(dut, data=word, data_k=0xF if word == CXP_SOP else 0x0, clk=dut.rxClk) + + +async def _collect_core_outputs(dut, *, cycles: int) -> tuple[list[int], list[int]]: + hdr_words: list[int] = [] + data_words: list[int] = [] + for _ in range(cycles): + await send_rx_word(dut, data=CXP_IDLE, data_k=CXP_IDLE_K, clk=dut.rxClk) + if int(dut.M_HDR_TVALID.value) == 1: + hdr_words.append(int(dut.M_HDR_TDATA.value)) + if int(dut.M_DATA_TVALID.value) == 1: + data_words.append(int(dut.M_DATA_TDATA.value)) + return hdr_words, data_words + + +async def _drive_idle_rx(dut, *, cycles: int) -> None: + for _ in range(cycles): + await send_rx_word(dut, data=CXP_IDLE, data_k=CXP_IDLE_K, clk=dut.rxClk) + + +def _header_payload(**kwargs) -> list[int]: + return [CXP_MARKER, repeat_byte(CXP_PKT_IMAGE_HEADER), *_image_header_words(**kwargs)] + + +def _line_payload(*line_words: int) -> list[int]: + return [CXP_MARKER, repeat_byte(CXP_PKT_IMAGE_LINE), *line_words] + + +async def _send_image_frame( + dut, + *, + stream_id: int, + packet_tag: int, + y_size: int, + dsize_l: int, + line_words: list[int], +) -> None: + await _send_stream_packet_words( + dut, + _header_payload(stream_id=stream_id, y_size=y_size, dsize_l=dsize_l), + stream_id=stream_id, + packet_tag=packet_tag, + ) + await _send_stream_packet_words( + dut, + _line_payload(*line_words), + stream_id=(stream_id + 1) & 0xFF, + packet_tag=(packet_tag + 1) & 0xFF, + ) - axil = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "S_AXI"), dut.axilClk, dut.axilRst) + +async def _count_signal_high_cycles(signal, clk, stop_event: Event, counts: dict[str, int], key: str) -> None: + while True: + await RisingEdge(clk) + await Timer(2, unit="ns") + if stop_event.is_set(): + return + counts[key] += int(signal.value) + + +async def _trace_first_signal_high(signal, clk, stop_event: Event, trace: dict[str, object], capture) -> None: + while True: + await RisingEdge(clk) + await Timer(2, unit="ns") + if stop_event.is_set(): + return + if trace["seen"] or int(signal.value) == 0: + continue + trace["seen"] = True + trace.update(capture()) + + +@cocotb.test() +async def coaxpress_core_tagged_config_tx_path_test(dut): + axil = await _setup_core(dut) reg_ff8 = await axil.read_dword(0xFF8) await axil.write_dword(0xFF8, reg_ff8 | (1 << 26) | (1 << 27)) @@ -107,10 +253,194 @@ async def coaxpress_core_tagged_config_tx_path_test(dut): assert request_start is not None, tx_bytes +@cocotb.test() +async def coaxpress_core_rx_overflow_counter_under_backpressure_test(dut): + axil = await _setup_core(dut, data_ready=1, hdr_ready=0) + + assert await _read_counter(axil, dut, 0x820) == 0 + + header_payload = _header_payload(y_size=0, dsize_l=1) + for index in range(24): + await _send_stream_packet_words(dut, header_payload, stream_id=(0x30 + index) & 0xFF, packet_tag=0x55) + + overflow_count = await _read_counter(axil, dut, 0x820) + assert overflow_count > 0 + + dut.M_HDR_TREADY.value = 1 + hdr_words, _ = await _collect_core_outputs(dut, cycles=64) + assert hdr_words + + +@cocotb.test() +async def coaxpress_core_rx_fsm_error_counter_and_recovery_test(dut): + axil = await _setup_core(dut) + + malformed_header_words = _image_header_words(y_size=1, dsize_l=1) + malformed_header_words[5] = 0x01020304 + malformed_payload = [CXP_MARKER, repeat_byte(CXP_PKT_IMAGE_HEADER), *malformed_header_words] + await _send_stream_packet_words(dut, malformed_payload, stream_id=0x41, packet_tag=0x66) + + first_error_count = await _read_counter(axil, dut, 0x824) + assert first_error_count > 0 + + await _collect_core_outputs(dut, cycles=32) + stable_error_count = await _read_counter(axil, dut, 0x824) + assert stable_error_count == first_error_count + + await _send_image_frame( + dut, + stream_id=0x42, + packet_tag=0x67, + y_size=1, + dsize_l=1, + line_words=[0xAABBCCDD], + ) + + hdr_words, data_words = await _collect_core_outputs(dut, cycles=64) + assert hdr_words + assert 0xAABBCCDD in data_words + assert await _read_counter(axil, dut, 0x824) == first_error_count + + +@cocotb.test(skip=os.getenv("RUN_KNOWN_ISSUE_TESTS") != "1") +async def coaxpress_core_rx_overflow_does_not_trigger_fsm_error_storm_known_issue_test(dut): + axil = await _setup_core(dut, data_ready=0, hdr_ready=1) + + assert await _read_counter(axil, dut, 0x820) == 0 + assert await _read_counter(axil, dut, 0x824) == 0 + + frame_count = env_int("CXP_RX_OVERFLOW_STORM_FRAME_COUNT", default=96) + # Hold opaque stream metadata constant to separate a true backpressure issue + # from metadata-sensitive parsing behavior in the exploratory bench. + fixed_packet_fields = env_flag("CXP_CORE_KNOWN_ISSUE_FIXED_PACKET_FIELDS", default=False) + signal_counts = { + "core_rx_fsm_error": 0, + "core_rx_overflow": 0, + "core_rx_fsm_rst": 0, + "axil_rx_fsm_error": 0, + "axil_rx_overflow": 0, + } + signal_found = { + "core_rx_fsm_error": False, + "core_rx_overflow": False, + "core_rx_fsm_rst": False, + "axil_rx_fsm_error": False, + "axil_rx_overflow": False, + } + phase_trace = {"label": "frame_drive", "frame_index": -1} + first_core_error = {"seen": False} + stop_event = Event() + monitor_tasks = [] + for signal, clk, key in ( + (getattr(dut, "DBG_RX_FSM_ERROR", None), dut.rxClk, "core_rx_fsm_error"), + (getattr(dut, "DBG_RX_OVERFLOW", None), dut.rxClk, "core_rx_overflow"), + (getattr(dut, "DBG_RX_FSM_RST", None), dut.rxClk, "core_rx_fsm_rst"), + (getattr(dut, "DBG_AXIL_FSM_ERROR", None), dut.axilClk, "axil_rx_fsm_error"), + (getattr(dut, "DBG_AXIL_OVERFLOW", None), dut.axilClk, "axil_rx_overflow"), + ): + if signal is not None: + signal_found[key] = True + monitor_tasks.append(cocotb.start_soon(_count_signal_high_cycles(signal, clk, stop_event, signal_counts, key))) + if getattr(dut, "DBG_RX_FSM_ERROR", None) is not None: + monitor_tasks.append( + cocotb.start_soon( + _trace_first_signal_high( + dut.DBG_RX_FSM_ERROR, + dut.rxClk, + stop_event, + first_core_error, + lambda: { + "time_ns": get_sim_time(unit="ns"), + "phase": phase_trace["label"], + "frame_index": phase_trace["frame_index"], + "rx_data": int(dut.rxData.value), + "rx_data_k": int(dut.rxDataK.value), + "m_data_tvalid": int(dut.M_DATA_TVALID.value), + "m_data_tready": int(dut.M_DATA_TREADY.value), + "m_hdr_tvalid": int(dut.M_HDR_TVALID.value), + }, + ) + ) + ) + + for index in range(frame_count): + phase_trace["frame_index"] = index + stream_id = 0x50 if fixed_packet_fields else (0x50 + (2 * index)) & 0xFF + packet_tag = 0x70 if fixed_packet_fields else (0x70 + (2 * index)) & 0xFF + await _send_image_frame( + dut, + stream_id=stream_id, + packet_tag=packet_tag, + y_size=1, + dsize_l=1, + line_words=[0x10000000 + index], + ) + + phase_trace["label"] = "idle_quiesce" + phase_trace["frame_index"] = frame_count + await _drive_idle_rx(dut, cycles=32) + phase_trace["label"] = "axil_read" + overflow_count = await _read_counter(axil, dut, 0x820) + first_error_count = await _read_counter(axil, dut, 0x824) + + stop_event.set() + for task in monitor_tasks: + await task + + # Known issue under investigation: + # with the current 72-frame workload the realistic core path still shows no + # RX overflow. The remaining anomaly is a late lone RxFsmError pulse that + # only appears when the bench sweeps packet stream/tag fields. + assert overflow_count > 0, ( + f"overflow_count={overflow_count} first_error_count={first_error_count} " + f"core_overflow={signal_counts['core_rx_overflow']} core_error={signal_counts['core_rx_fsm_error']} " + f"core_rx_fsm_rst={signal_counts['core_rx_fsm_rst']} " + f"axil_overflow={signal_counts['axil_rx_overflow']} axil_error={signal_counts['axil_rx_fsm_error']} " + f"first_core_error={first_core_error} " + f"found_overflow={signal_found['core_rx_overflow']} found_error={signal_found['core_rx_fsm_error']} " + f"found_rx_fsm_rst={signal_found['core_rx_fsm_rst']} " + f"found_axil_overflow={signal_found['axil_rx_overflow']} found_axil_error={signal_found['axil_rx_fsm_error']}" + ) + assert first_error_count == 0, ( + f"overflow_count={overflow_count} first_error_count={first_error_count} " + f"core_overflow={signal_counts['core_rx_overflow']} core_error={signal_counts['core_rx_fsm_error']} " + f"core_rx_fsm_rst={signal_counts['core_rx_fsm_rst']} " + f"axil_overflow={signal_counts['axil_rx_overflow']} axil_error={signal_counts['axil_rx_fsm_error']} " + f"first_core_error={first_core_error} " + f"found_overflow={signal_found['core_rx_overflow']} found_error={signal_found['core_rx_fsm_error']} " + f"found_rx_fsm_rst={signal_found['core_rx_fsm_rst']} " + f"found_axil_overflow={signal_found['axil_rx_overflow']} found_axil_error={signal_found['axil_rx_fsm_error']}" + ) + + await _collect_core_outputs(dut, cycles=128) + idle_error_count = await _read_counter(axil, dut, 0x824) + assert idle_error_count == first_error_count + + dut.M_DATA_TREADY.value = 1 + await _collect_core_outputs(dut, cycles=256) + released_error_count = await _read_counter(axil, dut, 0x824) + assert released_error_count == first_error_count + + await _send_image_frame( + dut, + stream_id=0xE0, + packet_tag=0xE1, + y_size=1, + dsize_l=1, + line_words=[0xDEADBEEF], + ) + _, data_words = await _collect_core_outputs(dut, cycles=128) + assert 0xDEADBEEF in data_words + assert await _read_counter(axil, dut, 0x824) == first_error_count + + def test_CoaXPressCore(): + use_debug_wrapper = os.getenv("CXP_CORE_DEBUG_WRAPPER") == "1" + parameters = {"FORCE_RX_CTRL_G": "true"} if use_debug_wrapper and os.getenv("CXP_CORE_FORCE_RX_CTRL") == "1" else None run_surf_vhdl_test( test_file=__file__, - toplevel="surf.coaxpresscorewrapper", + toplevel="surf.coaxpresscoredebugwrapper" if use_debug_wrapper else "surf.coaxpresscorewrapper", + parameters=parameters, extra_vhdl_sources={ "surf": [ "protocols/coaxpress/core/rtl/CoaXPressPkg.vhd", @@ -125,7 +455,7 @@ def test_CoaXPressCore(): "protocols/coaxpress/core/rtl/CoaXPressConfig.vhd", "protocols/coaxpress/core/rtl/CoaXPressAxiL.vhd", "protocols/coaxpress/core/rtl/CoaXPressCore.vhd", - "protocols/coaxpress/core/wrappers/CoaXPressCoreWrapper.vhd", + "protocols/coaxpress/core/wrappers/CoaXPressCoreDebugWrapper.vhd" if use_debug_wrapper else "protocols/coaxpress/core/wrappers/CoaXPressCoreWrapper.vhd", ] }, ) diff --git a/tests/protocols/coaxpress/test_CoaXPressRx.py b/tests/protocols/coaxpress/test_CoaXPressRx.py index 194e890679..bd775009e3 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRx.py +++ b/tests/protocols/coaxpress/test_CoaXPressRx.py @@ -23,10 +23,13 @@ # - Timing: All DUT-visible domains are driven in lockstep so the bench checks # the real FIFO/FSM sequencing without introducing unrelated clock skew. +import os + import cocotb +from cocotb.triggers import Event, RisingEdge, Timer import pytest -from tests.common.regression_utils import env_int, parameter_case, run_surf_vhdl_test, start_lockstep_clocks +from tests.common.regression_utils import env_flag, env_int, parameter_case, run_surf_vhdl_test, start_lockstep_clocks from tests.protocols.coaxpress.coaxpress_test_utils import ( CXP_EOP, CXP_IDLE, @@ -39,6 +42,7 @@ CXP_PKT_IMAGE_LINE, CXP_SOP, append_snapshot_if_valid, + find_subsequence, pack_words, reset_signals, repeat_byte, @@ -73,6 +77,32 @@ repeat_byte(0xAA), ] +SINGLE_LINE_HEADER_WORDS = [ + repeat_byte(0x12), + repeat_byte(0x34), + repeat_byte(0x56), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x01), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x01), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x01), + repeat_byte(0x00), + repeat_byte(0x10), + repeat_byte(0x00), + repeat_byte(0x20), + repeat_byte(0xAA), +] + EXPECTED_HDR_WORDS = [ 0x3456AA12, 0x00000003, @@ -90,6 +120,43 @@ def _pack_lane_nibbles(values: list[int]) -> int: packed |= (value & 0xF) << (4 * index) return packed + +def _image_header_words( + *, + stream_id: int = 0x12, + source_tag: int = 0x3456, + x_size: int = 3, + x_offs: int = 4, + y_size: int = 1, + y_offs: int = 5, + dsize_l: int = 3, + pixel_f: int = 0x0010, + tap_g: int = 0x0020, + flags: int = 0xAA, +) -> list[int]: + def rep24(value: int) -> list[int]: + return [ + repeat_byte((value >> 16) & 0xFF), + repeat_byte((value >> 8) & 0xFF), + repeat_byte(value & 0xFF), + ] + + return [ + repeat_byte(stream_id), + repeat_byte((source_tag >> 8) & 0xFF), + repeat_byte(source_tag & 0xFF), + *rep24(x_size), + *rep24(x_offs), + *rep24(y_size), + *rep24(y_offs), + *rep24(dsize_l), + repeat_byte((pixel_f >> 8) & 0xFF), + repeat_byte(pixel_f & 0xFF), + repeat_byte((tap_g >> 8) & 0xFF), + repeat_byte(tap_g & 0xFF), + repeat_byte(flags), + ] + def _capture_outputs( dut, *, @@ -140,6 +207,192 @@ async def _send_multi_lane_word(dut, *, lane_words: list[int], lane_ks: list[int ) +def _active_link_mask() -> int: + return (1 << env_int("NUM_LANES_G", default=1)) - 1 + + +async def _send_isolated_lane_word( + dut, + *, + lane: int, + data: int, + data_k: int, + link_up: int | None = None, +) -> None: + num_lanes = env_int("NUM_LANES_G", default=1) + lane_words = [CXP_IDLE] * num_lanes + lane_ks = [CXP_IDLE_K] * num_lanes + lane_words[lane] = data + lane_ks[lane] = data_k + await _send_multi_lane_word(dut, lane_words=lane_words, lane_ks=lane_ks, link_up=_active_link_mask() if link_up is None else link_up) + + +def _isolated_lane_frame_sequence( + *, + line_words: list[int], + header_words: list[int] | None = None, + stream_id: int = 0x22, + packet_tag: int = 0x33, + corrupt_header_index: int | None = None, + corrupt_header_word: int = 0x01020304, +) -> list[tuple[int, int]]: + header_payload_words = list(header_words if header_words is not None else HEADER_WORDS) + if corrupt_header_index is not None: + header_payload_words[corrupt_header_index] = corrupt_header_word + + return [ + (CXP_SOP, 0xF), + (repeat_byte(0x01), 0x0), + (repeat_byte(stream_id), 0x0), + (repeat_byte(packet_tag), 0x0), + (repeat_byte((len(header_payload_words) + 2) >> 8), 0x0), + (repeat_byte((len(header_payload_words) + 2) & 0xFF), 0x0), + (CXP_MARKER, 0xF), + (repeat_byte(CXP_PKT_IMAGE_HEADER), 0x0), + *[(word, 0xF) for word in header_payload_words], + (CXP_SOP, 0xF), + (repeat_byte(0x01), 0x0), + (repeat_byte((stream_id + 1) & 0xFF), 0x0), + (repeat_byte((packet_tag + 1) & 0xFF), 0x0), + (repeat_byte((len(line_words) + 2) >> 8), 0x0), + (repeat_byte((len(line_words) + 2) & 0xFF), 0x0), + (CXP_MARKER, 0xF), + (repeat_byte(CXP_PKT_IMAGE_LINE), 0x0), + *[(word, 0x0) for word in line_words], + ] + + +async def _send_isolated_lane_frame( + dut, + *, + lane: int, + line_words: list[int], + header_words: list[int] | None = None, + stream_id: int = 0x22, + packet_tag: int = 0x33, + corrupt_header_index: int | None = None, + corrupt_header_word: int = 0x01020304, +) -> None: + sequence = _isolated_lane_frame_sequence( + line_words=line_words, + header_words=header_words, + stream_id=stream_id, + packet_tag=packet_tag, + corrupt_header_index=corrupt_header_index, + corrupt_header_word=corrupt_header_word, + ) + for data, data_k in sequence: + await _send_isolated_lane_word(dut, lane=lane, data=data, data_k=data_k) + + +async def _send_isolated_lane_frame_and_capture( + dut, + *, + lane: int, + line_words: list[int], + data_beats: list[tuple[int, int, int, int]], + hdr_beats: list[tuple[int, int, int, int]], + header_words: list[int] | None = None, + stream_id: int = 0x22, + packet_tag: int = 0x33, + corrupt_header_index: int | None = None, + corrupt_header_word: int = 0x01020304, + start_cycle_index: int = 0, +) -> int: + sequence = _isolated_lane_frame_sequence( + line_words=line_words, + header_words=header_words, + stream_id=stream_id, + packet_tag=packet_tag, + corrupt_header_index=corrupt_header_index, + corrupt_header_word=corrupt_header_word, + ) + cycle_index = start_cycle_index + for data, data_k in sequence: + await _send_isolated_lane_word(dut, lane=lane, data=data, data_k=data_k) + _capture_outputs( + dut, + cfg_beats=[], + data_beats=data_beats, + hdr_beats=hdr_beats, + event_tags=[], + trig_ack_cycles=[], + cycle_index=cycle_index, + ) + cycle_index += 1 + + return cycle_index + + +async def _send_one_lane_frame( + dut, + *, + line_word: int, + header_stream_id: int = 0x22, + header_packet_tag: int = 0x33, + line_stream_id: int = 0x44, + line_packet_tag: int = 0x55, +) -> None: + sequence = [ + (CXP_SOP, 0xF), + (repeat_byte(0x01), 0x0), + (repeat_byte(header_stream_id), 0x0), + (repeat_byte(header_packet_tag), 0x0), + (repeat_byte(0x00), 0x0), + (repeat_byte(25), 0x0), + (CXP_MARKER, 0xF), + (repeat_byte(CXP_PKT_IMAGE_HEADER), 0x0), + *[(word, 0xF) for word in SINGLE_LINE_HEADER_WORDS], + (CXP_SOP, 0xF), + (repeat_byte(0x01), 0x0), + (repeat_byte(line_stream_id), 0x0), + (repeat_byte(line_packet_tag), 0x0), + (repeat_byte(0x00), 0x0), + (repeat_byte(3), 0x0), + (CXP_MARKER, 0xF), + (repeat_byte(CXP_PKT_IMAGE_LINE), 0x0), + (line_word, 0x0), + ] + for data, data_k in sequence: + await send_rx_word(dut, data=data, data_k=data_k, clk=dut.rxClk) + + +async def _count_signal_high_cycles(signal, clk, stop_event: Event, counts: dict[str, int], key: str) -> None: + while True: + await RisingEdge(clk) + await Timer(2, unit="ns") + if stop_event.is_set(): + return + counts[key] += int(signal.value) + + +async def _drive_idle_and_capture( + dut, + *, + cycles: int, + data_beats: list[tuple[int, int, int, int]], + hdr_beats: list[tuple[int, int, int, int]], + start_cycle_index: int = 0, +) -> None: + num_lanes = env_int("NUM_LANES_G", default=1) + for cycle_index in range(start_cycle_index, start_cycle_index + cycles): + await _send_multi_lane_word( + dut, + lane_words=[CXP_IDLE] * num_lanes, + lane_ks=[CXP_IDLE_K] * num_lanes, + link_up=_active_link_mask(), + ) + _capture_outputs( + dut, + cfg_beats=[], + data_beats=data_beats, + hdr_beats=hdr_beats, + event_tags=[], + trig_ack_cycles=[], + cycle_index=cycle_index, + ) + + @cocotb.test() async def coaxpress_rx_one_lane_integration_test(dut): if env_int("NUM_LANES_G", default=1) != 1: @@ -368,17 +621,260 @@ async def capture(cycle_index: int) -> None: assert any(beat[2] == 1 for beat in data_beats) +@cocotb.test(skip=os.getenv("RUN_KNOWN_ISSUE_TESTS") != "1") +async def coaxpress_rx_four_lane_fsm_error_recovery_known_issue_test(dut): + if env_int("NUM_LANES_G", default=1) != 4: + return + + start_lockstep_clocks(dut.dataClk, dut.cfgClk, dut.txClk, dut.rxClk, period_ns=4.0) + set_initial_values( + dut, + { + "rxData": 0, + "rxDataK": 0, + "rxLinkUp": 0xF, + "rxFsmRst": 0, + "rxNumberOfLane": 3, + "dataTReady": 1, + "hdrTReady": 1, + }, + ) + await reset_signals( + dut, + clk=dut.rxClk, + reset_names=("dataRst", "cfgRst", "txRst", "rxRst"), + assert_cycles=4, + release_cycles=4, + ) + + signal_counts = {"error_pulses": 0} + stop_event = Event() + monitor_task = cocotb.start_soon(_count_signal_high_cycles(dut.rxFsmError, dut.rxClk, stop_event, signal_counts, "error_pulses")) + + data_beats: list[tuple[int, int, int, int]] = [] + hdr_beats: list[tuple[int, int, int, int]] = [] + cycle_index = 0 + malformed_header = _image_header_words(dsize_l=3) + cycle_index = await _send_isolated_lane_frame_and_capture( + dut, + lane=0, + line_words=[0x0BAD0000, 0x0BAD0001, 0x0BAD0002], + data_beats=data_beats, + hdr_beats=hdr_beats, + header_words=malformed_header, + stream_id=0x40, + packet_tag=0x50, + corrupt_header_index=5, + start_cycle_index=cycle_index, + ) + + recovery_lane_order = [1, 2, 3, 0] + expected_recovery_words: list[int] = [] + for lane in recovery_lane_order: + recovery_words = [ + 0xD1000000 | (lane << 8) | word_index + for word_index in range(3) + ] + expected_recovery_words.extend(recovery_words) + cycle_index = await _send_isolated_lane_frame_and_capture( + dut, + lane=lane, + line_words=recovery_words, + data_beats=data_beats, + hdr_beats=hdr_beats, + stream_id=0x60 + lane, + packet_tag=0x70 + lane, + start_cycle_index=cycle_index, + ) + + await _drive_idle_and_capture(dut, cycles=256, data_beats=data_beats, hdr_beats=hdr_beats, start_cycle_index=cycle_index) + + stop_event.set() + await monitor_task + + observed_data_words = [beat[0] for beat in data_beats] + observed_header_words = [beat[0] for beat in hdr_beats] + assert signal_counts["error_pulses"] > 0 + assert find_subsequence(observed_header_words, EXPECTED_HDR_WORDS) is not None, observed_header_words + subseq_start = find_subsequence(observed_data_words, expected_recovery_words) + # Known issue under investigation: + # a malformed 4-lane header does raise rxFsmError, but the current RTL does + # not fully recover the expected post-error lane rotation and line payloads. + assert subseq_start is not None, data_beats + observed_recovery_last = [beat[2] for beat in data_beats[subseq_start : subseq_start + len(expected_recovery_words)]] + assert observed_recovery_last == [0, 0, 1] * 4, observed_recovery_last + + +@cocotb.test(skip=os.getenv("RUN_KNOWN_ISSUE_TESTS") != "1") +async def coaxpress_rx_four_lane_overflow_recovery_known_issue_test(dut): + if env_int("NUM_LANES_G", default=1) != 4: + return + + start_lockstep_clocks(dut.dataClk, dut.cfgClk, dut.txClk, dut.rxClk, period_ns=4.0) + set_initial_values( + dut, + { + "rxData": 0, + "rxDataK": 0, + "rxLinkUp": 0xF, + "rxFsmRst": 0, + "rxNumberOfLane": 3, + "dataTReady": 0, + "hdrTReady": 1, + }, + ) + await reset_signals( + dut, + clk=dut.rxClk, + reset_names=("dataRst", "cfgRst", "txRst", "rxRst"), + assert_cycles=4, + release_cycles=4, + ) + + signal_counts = {"error_pulses": 0, "overflow_pulses": 0} + stop_event = Event() + monitor_tasks = [ + cocotb.start_soon(_count_signal_high_cycles(dut.rxFsmError, dut.rxClk, stop_event, signal_counts, "error_pulses")), + cocotb.start_soon(_count_signal_high_cycles(dut.rxOverflow, dut.rxClk, stop_event, signal_counts, "overflow_pulses")), + ] + + stress_line_words = [0xA0000000 + word_index for word_index in range(80)] + stress_header_words = _image_header_words(dsize_l=len(stress_line_words)) + stress_frame_count = env_int("CXP_RX_FOUR_LANE_OVERFLOW_FRAME_COUNT", default=32) + idle_cycles = env_int("CXP_RX_FOUR_LANE_OVERFLOW_IDLE_CYCLES", default=3200) + cycle_index = 0 + for index in range(stress_frame_count): + lane = index % 4 + await _send_isolated_lane_frame( + dut, + lane=lane, + line_words=stress_line_words, + header_words=stress_header_words, + stream_id=0x20 + lane, + packet_tag=0x30 + lane, + ) + cycle_index += len(_isolated_lane_frame_sequence(line_words=stress_line_words, header_words=stress_header_words, stream_id=0x20 + lane, packet_tag=0x30 + lane)) + + dut.dataTReady.value = 1 + + data_beats: list[tuple[int, int, int, int]] = [] + hdr_beats: list[tuple[int, int, int, int]] = [] + recovery_line_words_by_lane = { + lane: [0xE1000000 | (lane << 8) | word_index for word_index in range(3)] + for lane in range(4) + } + expected_recovery_words = [word for lane in range(4) for word in recovery_line_words_by_lane[lane]] + for lane in range(4): + cycle_index = await _send_isolated_lane_frame_and_capture( + dut, + lane=lane, + line_words=recovery_line_words_by_lane[lane], + data_beats=data_beats, + hdr_beats=hdr_beats, + stream_id=0x80 + lane, + packet_tag=0x90 + lane, + start_cycle_index=cycle_index, + ) + + await _drive_idle_and_capture( + dut, + cycles=idle_cycles, + data_beats=data_beats, + hdr_beats=hdr_beats, + start_cycle_index=cycle_index, + ) + + stop_event.set() + for task in monitor_tasks: + await task + + observed_data_words = [beat[0] for beat in data_beats] + # Known issue under investigation: + # with 4 bonded lanes, sustained sink backpressure can emit rxFsmError + # pulses before or alongside the expected overflow indication. The desired + # behavior is overflow-only, followed by clean post-stall recovery data. + assert signal_counts["error_pulses"] == 0, signal_counts + assert signal_counts["overflow_pulses"] > 0, signal_counts + assert find_subsequence(observed_data_words, expected_recovery_words) is not None, observed_data_words[-64:] + subseq_start = find_subsequence(observed_data_words, expected_recovery_words) + assert subseq_start is not None + observed_recovery_last = [beat[2] for beat in data_beats[subseq_start : subseq_start + len(expected_recovery_words)]] + assert observed_recovery_last == [0, 0, 1] * 4, observed_recovery_last + + +@cocotb.test(skip=os.getenv("RUN_KNOWN_ISSUE_TESTS") != "1") +async def coaxpress_rx_repeated_single_line_frame_known_issue_test(dut): + if env_int("NUM_LANES_G", default=1) != 1: + return + + start_lockstep_clocks(dut.dataClk, dut.cfgClk, dut.txClk, dut.rxClk, period_ns=4.0) + set_initial_values( + dut, + { + "rxData": 0, + "rxDataK": 0, + "rxLinkUp": 1, + "rxFsmRst": 0, + "rxNumberOfLane": 0, + "dataTReady": env_int("CXP_RX_KNOWN_ISSUE_DATA_READY", default=0), + "hdrTReady": 1, + }, + ) + await reset_signals( + dut, + clk=dut.rxClk, + reset_names=("dataRst", "cfgRst", "txRst", "rxRst"), + assert_cycles=4, + release_cycles=4, + ) + + frame_count = env_int("CXP_RX_REPEATED_FRAME_COUNT", default=72) + vary_packet_fields = env_flag("CXP_RX_KNOWN_ISSUE_VARY_PACKET_FIELDS", default=False) + signal_counts = {"error_pulses": 0, "overflow_pulses": 0} + stop_event = Event() + monitor_tasks = [ + cocotb.start_soon(_count_signal_high_cycles(dut.rxFsmError, dut.rxClk, stop_event, signal_counts, "error_pulses")), + cocotb.start_soon(_count_signal_high_cycles(dut.rxOverflow, dut.rxClk, stop_event, signal_counts, "overflow_pulses")), + ] + for index in range(frame_count): + header_stream_id = (0x50 + (2 * index)) & 0xFF if vary_packet_fields else 0x22 + header_packet_tag = (0x70 + (2 * index)) & 0xFF if vary_packet_fields else 0x33 + await _send_one_lane_frame( + dut, + line_word=0xA0000000 + index, + header_stream_id=header_stream_id, + header_packet_tag=header_packet_tag, + line_stream_id=(header_stream_id + 1) & 0xFF if vary_packet_fields else 0x44, + line_packet_tag=(header_packet_tag + 1) & 0xFF if vary_packet_fields else 0x55, + ) + + for _ in range(32): + await send_rx_word(dut, data=CXP_IDLE, data_k=CXP_IDLE_K, clk=dut.rxClk) + stop_event.set() + for task in monitor_tasks: + await task + + assert signal_counts["overflow_pulses"] > 0, ( + f"overflow_pulses={signal_counts['overflow_pulses']} error_pulses={signal_counts['error_pulses']}" + ) + assert signal_counts["error_pulses"] == 0, ( + f"overflow_pulses={signal_counts['overflow_pulses']} error_pulses={signal_counts['error_pulses']}" + ) + + PARAMETER_SWEEP = [ parameter_case("single_lane", NUM_LANES_G="1", RX_FSM_CNT_WIDTH_G="8"), parameter_case("dual_lane", NUM_LANES_G="2", RX_FSM_CNT_WIDTH_G="8"), + parameter_case("quad_lane", NUM_LANES_G="4", RX_FSM_CNT_WIDTH_G="8"), ] @pytest.mark.parametrize("parameters", PARAMETER_SWEEP) def test_CoaXPressRx(parameters): + use_core_path_wrapper = os.getenv("CXP_RX_CORE_PATH_WRAPPER") == "1" run_surf_vhdl_test( test_file=__file__, - toplevel="surf.coaxpressrxwrapper", + toplevel="surf.coaxpressrxcorepathwrapper" if use_core_path_wrapper else "surf.coaxpressrxwrapper", parameters=parameters, extra_env=parameters, extra_vhdl_sources={ @@ -389,7 +885,7 @@ def test_CoaXPressRx(parameters): "protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd", "protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd", "protocols/coaxpress/core/rtl/CoaXPressRx.vhd", - "protocols/coaxpress/core/wrappers/CoaXPressRxWrapper.vhd", + "protocols/coaxpress/core/wrappers/CoaXPressRxCorePathWrapper.vhd" if use_core_path_wrapper else "protocols/coaxpress/core/wrappers/CoaXPressRxWrapper.vhd", ] }, ) diff --git a/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py b/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py index ae46e06bb6..c6a325a6bb 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py +++ b/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py @@ -21,6 +21,8 @@ # - Timing: The source holds each beat until `sAxisTReady` rises so the checks # reflect the FSM's actual per-beat acceptance rather than idealized traffic. +import os + import cocotb import pytest from cocotb.triggers import RisingEdge, Timer @@ -121,6 +123,34 @@ def _expected_header_data() -> int: ) +def _single_line_header_words() -> list[int]: + return [ + repeat_byte(0x12), + repeat_byte(0x34), + repeat_byte(0x56), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x01), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x01), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x00), + repeat_byte(0x01), + repeat_byte(0x00), + repeat_byte(0x10), + repeat_byte(0x00), + repeat_byte(0x20), + repeat_byte(0xAA), + ] + + @cocotb.test() async def coaxpress_rx_hs_fsm_header_and_lines_test(dut): if env_int("NUM_LANES_G", default=1) != 1: @@ -353,6 +383,43 @@ async def coaxpress_rx_hs_fsm_two_lane_step_alignment_test(dut): ] +@cocotb.test(skip=os.getenv("RUN_KNOWN_ISSUE_TESTS") != "1") +async def coaxpress_rx_hs_fsm_repeated_single_line_frame_known_issue_test(dut): + if env_int("NUM_LANES_G", default=1) != 1: + return + + start_clock(dut.rxClk) + dut.rxRst.setimmediatevalue(1) + dut.rxFsmRst.setimmediatevalue(0) + dut.sAxisTValid.setimmediatevalue(0) + dut.sAxisTData.setimmediatevalue(0) + dut.sAxisTKeep.setimmediatevalue(0) + dut.sAxisTLast.setimmediatevalue(0) + await reset_dut(dut, reset_names=("rxRst",)) + + frame_count = env_int("CXP_RX_HSFSM_FRAME_COUNT", default=72) + error_pulses = 0 + + for index in range(frame_count): + await _send_handshaked_beat(dut, data=CXP_MARKER, keep=0xF) + error_pulses += int(dut.rxFsmError.value) + await _send_handshaked_beat(dut, data=repeat_byte(CXP_PKT_IMAGE_HEADER), keep=0xF) + error_pulses += int(dut.rxFsmError.value) + for word in _single_line_header_words(): + await _send_handshaked_beat(dut, data=word, keep=0xF) + error_pulses += int(dut.rxFsmError.value) + await _send_handshaked_beat(dut, data=CXP_MARKER, keep=0xF) + error_pulses += int(dut.rxFsmError.value) + await _send_handshaked_beat(dut, data=repeat_byte(CXP_PKT_IMAGE_LINE), keep=0xF) + error_pulses += int(dut.rxFsmError.value) + await _send_handshaked_beat(dut, data=0xA0000000 + index, keep=0xF) + error_pulses += int(dut.rxFsmError.value) + + await cycle(dut.rxClk, 8) + error_pulses += sum(int(dut.rxFsmError.value) for _ in range(1)) + assert error_pulses == 0 + + PARAMETER_SWEEP = [ parameter_case("single_lane", NUM_LANES_G="1", RX_FSM_CNT_WIDTH_G="8"), parameter_case("dual_lane", NUM_LANES_G="2", RX_FSM_CNT_WIDTH_G="8"), From 76b37f4921be83e57788f9ca6ed7d75b0c25a244 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 21 Apr 2026 12:57:07 -0700 Subject: [PATCH 36/92] Add hdrValid gating so a LINE packet is only accepted after a full header has completed, and that state is clear on malformed/new headers. Also add regression test for this. --- .../coaxpress/core/rtl/CoaXPressRxHsFsm.vhd | 27 +++++-- .../coaxpress/test_CoaXPressRxHsFsm.py | 80 +++++++++++++++++++ 2 files changed, 101 insertions(+), 6 deletions(-) diff --git a/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd b/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd index ee862dd7cb..3ffd47a6bf 100644 --- a/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd +++ b/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd @@ -93,6 +93,7 @@ architecture rtl of CoaXPressRxHsFsm is type RegType is record endOfLine : sl; + hdrValid : sl; yCnt : slv(RX_FSM_CNT_WIDTH_G-1 downto 0); dCnt : slv(RX_FSM_CNT_WIDTH_G-1 downto 0); hdrCnt : natural range 0 to 25; @@ -106,6 +107,7 @@ architecture rtl of CoaXPressRxHsFsm is end record RegType; constant REG_INIT_C : RegType := ( endOfLine => '0', + hdrValid => '0', yCnt => (others => '0'), dCnt => (others => '0'), hdrCnt => 0, @@ -191,10 +193,12 @@ begin v.hdrCnt := 3; -- Reset counters - v.yCnt := (others => '0'); + v.endOfLine := '0'; + v.hdrValid := '0'; + v.yCnt := (others => '0'); -- Check for out of sync header - if (r.yCnt /= r.hdr.ySize(RX_FSM_CNT_WIDTH_G-1 downto 0)) then + if (r.hdrValid = '1') and (r.yCnt /= r.hdr.ySize(RX_FSM_CNT_WIDTH_G-1 downto 0)) then -- Set the flag v.dbg.errDet := '1'; end if; @@ -204,8 +208,16 @@ begin -- Check for "Rectangular line marker" elsif (tData = x"02_02_02_02") then - -- Next State - v.state := LINE_S; + if (r.hdrValid = '1') then + -- Next State + v.state := LINE_S; + else + -- Set the flag + v.dbg.errDet := '1'; + + -- Next State + v.state := IDLE_S; + end if; else -- Set the flag @@ -221,7 +233,9 @@ begin or (tData(7 downto 0) /= tData(31 downto 24)) then -- Reset counter - v.hdrCnt := 0; + v.endOfLine := '0'; + v.hdrCnt := 0; + v.hdrValid := '0'; -- Set the flag v.dbg.errDet := '1'; @@ -233,7 +247,8 @@ begin elsif (r.hdrCnt = 25) then -- Reset counter - v.hdrCnt := 0; + v.hdrCnt := 0; + v.hdrValid := '1'; -- Forward the image header v.hdrMaster.tValid := '1'; diff --git a/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py b/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py index c6a325a6bb..cff28c1d35 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py +++ b/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py @@ -271,6 +271,86 @@ async def coaxpress_rx_hs_fsm_malformed_header_recovery_test(dut): ] +@cocotb.test() +async def coaxpress_rx_hs_fsm_malformed_header_drops_following_line_test(dut): + if env_int("NUM_LANES_G", default=1) != 1: + return + + start_clock(dut.rxClk) + dut.rxRst.setimmediatevalue(1) + dut.rxFsmRst.setimmediatevalue(0) + dut.sAxisTValid.setimmediatevalue(0) + dut.sAxisTData.setimmediatevalue(0) + dut.sAxisTKeep.setimmediatevalue(0) + dut.sAxisTLast.setimmediatevalue(0) + await reset_dut(dut, reset_names=("rxRst",)) + + header_beats: list[dict[str, int]] = [] + data_beats: list[dict[str, int]] = [] + error_seen = False + + await _send_handshaked_beat(dut, data=CXP_MARKER, keep=0xF) + error_seen |= int(dut.rxFsmError.value) == 1 + await _send_handshaked_beat(dut, data=repeat_byte(CXP_PKT_IMAGE_HEADER), keep=0xF) + error_seen |= int(dut.rxFsmError.value) == 1 + for index, word in enumerate(_header_words()): + await _send_handshaked_beat( + dut, + data=0x01020304 if index == 5 else word, + keep=0xF, + ) + error_seen |= int(dut.rxFsmError.value) == 1 + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + + # A line packet arriving after a malformed header must be discarded until a + # clean header has been accepted. + await _send_handshaked_beat(dut, data=CXP_MARKER, keep=0xF) + error_seen |= int(dut.rxFsmError.value) == 1 + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + await _send_handshaked_beat(dut, data=repeat_byte(CXP_PKT_IMAGE_LINE), keep=0xF) + error_seen |= int(dut.rxFsmError.value) == 1 + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + for word in (0x0BAD0000, 0x0BAD0001, 0x0BAD0002): + await _send_handshaked_beat(dut, data=word, keep=0xF) + error_seen |= int(dut.rxFsmError.value) == 1 + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + + await cycle(dut.rxClk, 2) + error_seen |= int(dut.rxFsmError.value) == 1 + assert error_seen + assert not header_beats + assert not data_beats + + await _send_handshaked_beat(dut, data=CXP_MARKER, keep=0xF) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + await _send_handshaked_beat(dut, data=repeat_byte(CXP_PKT_IMAGE_HEADER), keep=0xF) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + for word in _header_words(): + await _send_handshaked_beat(dut, data=word, keep=0xF) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + await _send_handshaked_beat(dut, data=CXP_MARKER, keep=0xF) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + await _send_handshaked_beat(dut, data=repeat_byte(CXP_PKT_IMAGE_LINE), keep=0xF) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + for word in (0xABCDEF00, 0xABCDEF01, 0xABCDEF02): + await _send_handshaked_beat(dut, data=word, keep=0xF) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + + for _ in range(6): + await RisingEdge(dut.rxClk) + await Timer(1, unit="ns") + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + + assert header_beats == [{"hdrTData": _expected_header_data(), "hdrTLast": 1, "hdrTSof": 1}], ( + [] if not header_beats else [hex(header_beats[0]["hdrTData"])] + ) + assert data_beats == [ + {"dataTData": 0xABCDEF00, "dataTKeep": 0xF, "dataTLast": 0}, + {"dataTData": 0xABCDEF01, "dataTKeep": 0xF, "dataTLast": 0}, + {"dataTData": 0xABCDEF02, "dataTKeep": 0xF, "dataTLast": 0}, + ] + + @cocotb.test() async def coaxpress_rx_hs_fsm_two_lane_step_alignment_test(dut): if env_int("NUM_LANES_G", default=1) != 2: From 80ab4fece26c38a44e856c785f54efd0a650591b Mon Sep 17 00:00:00 2001 From: Luca Scomparin Date: Tue, 21 Apr 2026 14:09:36 -0700 Subject: [PATCH 37/92] Fixing disconnected signal --- protocols/coaxpress/core/rtl/CoaXPressAxiL.vhd | 3 +++ protocols/coaxpress/core/rtl/CoaXPressCore.vhd | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/protocols/coaxpress/core/rtl/CoaXPressAxiL.vhd b/protocols/coaxpress/core/rtl/CoaXPressAxiL.vhd index d4ee2db49b..3c792be3a0 100755 --- a/protocols/coaxpress/core/rtl/CoaXPressAxiL.vhd +++ b/protocols/coaxpress/core/rtl/CoaXPressAxiL.vhd @@ -500,6 +500,7 @@ begin WIDTH_G => 32) port map ( clk => cfgClk, + rst => cfgRst, dataIn => r.configTimerSize, dataOut => configTimerSize); @@ -508,6 +509,7 @@ begin TPD_G => TPD_G) port map ( clk => cfgClk, + rst => cfgRst, dataIn => r.configErrResp, dataOut => configErrResp); @@ -516,6 +518,7 @@ begin TPD_G => TPD_G) port map ( clk => cfgClk, + rst => cfgRst, dataIn => r.configPktTag, dataOut => configPktTag); diff --git a/protocols/coaxpress/core/rtl/CoaXPressCore.vhd b/protocols/coaxpress/core/rtl/CoaXPressCore.vhd index 0bf3b4db0c..204e2405c1 100755 --- a/protocols/coaxpress/core/rtl/CoaXPressCore.vhd +++ b/protocols/coaxpress/core/rtl/CoaXPressCore.vhd @@ -230,7 +230,7 @@ begin rxFsmError => rxFsmError, -- Config Interface (cfgClk domain) cfgClk => cfgClk, - cfgRst => cfgClk, + cfgRst => cfgRst, configTimerSize => configTimerSize, configErrResp => configErrResp, configPktTag => configPktTag, From dd508770e6bef39443807a295b9982624fe5189c Mon Sep 17 00:00:00 2001 From: Luca Scomparin Date: Thu, 16 Apr 2026 16:29:45 -0700 Subject: [PATCH 38/92] Added support for PhantomS711 camera --- .../surf/protocols/coaxpress/_PhantomS711.py | 627 ++++++++++++++++++ python/surf/protocols/coaxpress/__init__.py | 1 + 2 files changed, 628 insertions(+) create mode 100644 python/surf/protocols/coaxpress/_PhantomS711.py diff --git a/python/surf/protocols/coaxpress/_PhantomS711.py b/python/surf/protocols/coaxpress/_PhantomS711.py new file mode 100644 index 0000000000..f343dfddb3 --- /dev/null +++ b/python/surf/protocols/coaxpress/_PhantomS711.py @@ -0,0 +1,627 @@ +#----------------------------------------------------------------------------- +# This file is part of the 'SLAC Firmware Standard Library'. It is subject to +# the license terms in the LICENSE.txt file found in the top-level directory +# of this distribution and at: +# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +# No part of the 'SLAC Firmware Standard Library', including this file, may be +# copied, modified, propagated, or distributed except according to the terms +# contained in the LICENSE.txt file. +#----------------------------------------------------------------------------- + +import pyrogue as pr + +class PhantomS711(pr.Device): + def __init__(self, **kwargs): + super().__init__(**kwargs) + ############################################################# + # Start of manufacturer-specific register space at 0x00006000 + ############################################################# + + self.add(pr.RemoteVariable( + name = 'DevicePhfwVersionReg', + description = 'Version of the firmware in the device.', + offset = 0x8174, + base = pr.UIntBE, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'DeviceSerialNumberReg', + description = 'Serial Number of device.', + offset = 0x8158, + base = pr.UIntBE, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'DeviceIPAddress', + description = 'This feature provides the static IP address of the device', + offset = 0x8300, + base = pr.String, + bitSize = 8*32, + mode = 'RO', + # hidden = True, + )) + + self.add(pr.RemoteVariable( + name = 'DeviceNetmask', + description = 'This feature provides the Netmask address of the device', + offset = 0x8320, + base = pr.String, + bitSize = 8*32, + mode = 'RO', + # hidden = True, + )) + + self.add(pr.RemoteVariable( + name = 'pDeviceTemperatureSelectorReg', + description = 'Selects the location within the device, where the temperature will be measured.', + offset = 0x8168, + base = pr.UIntBE, + bitSize = 16, + bitOffset = 0, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'pDeviceTemperatureReg', + description = 'Device temperature in degrees Celsius (C).', + offset = 0x8168, + base = pr.IntBE, + bitSize = 16, + bitOffset = 16, + mode = 'RO', + units = 'degC', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'WidthMaxReg', + description = 'Maximum width (in pixels) of the image. The dimension is calculated after horizontal binning, decimation or any other function changing the horizontal dimension of the image.', + offset = 0x8010, + base = pr.UIntBE, + mode = 'RO', + units = 'pixels', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'WidthReg', + description = 'This feature represents the actual image width expelled by the camera (in pixels).', + offset = 0x8000, + base = pr.UIntBE, + mode = 'RW', + units = 'pixels', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'HeightMaxReg', + description = 'Maximum height (in pixels) of the image. This dimension is calculated after vertical binning, decimation or any other function changing the vertical dimension of the image.', + offset = 0x8014, + base = pr.UIntBE, + mode = 'RO', + units = 'pixels', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'HeightReg', + description = 'This feature represents the actual image height expelled by the camera (in pixels).', + offset = 0x8004, + base = pr.UIntBE, + mode = 'RW', + units = 'pixels', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'PixelFormatReg', + description = 'This feature indicates the format of the pixel to use during the acquisition.', + offset = 0x8008, + base = pr.UIntBE, + mode = 'RW', + enum = { + 0x00000000: 'Undefined', + 0x01080001: 'Mono8', + 0x010C0006: 'Mono12', + 0x01100007: 'Mono16', + 0x0108000A: 'BayerGB8', + 0x010C0055: 'BayerGB12', + }, + )) + + self.add(pr.RemoteVariable( + name = 'ImageSourceReg', + description = 'This feature controls the image source.', + offset = 0x8120, + base = pr.UIntBE, + mode = 'RW', + enum = { + 0: 'LiveImage', + 1: 'OffsetTableRolling', + 2: 'GainTableAtRolling', + 3: 'OffsetTableGlobal', + 4: 'GainTableAtGlobal', + }, + )) + + self.add(pr.RemoteVariable( + name = 'ImageSourceGrabReg', + description = 'Grab Gain and Offset from camera.', + offset = 0x8124, + base = pr.UIntBE, + mode = 'WO', + )) + + self.add(pr.RemoteVariable( + name = 'AcquisitionModeReg', + description = 'This feature controls the acquisition mode of the device.', + offset = 0x8018, + base = pr.UIntBE, + mode = 'RW', + enum = { + 0: 'undefined', + 2: 'Continuous', + }, + )) + + self.add(pr.RemoteCommand( + name = 'AcquisitionStart', + description = 'This feature starts the Acquisition of the device.', + offset = 0x801C, + base = pr.UIntBE, + bitSize = 8, + bitOffset = 24, + function = lambda cmd: cmd.post(1), + )) + + self.add(pr.RemoteCommand( + name = 'AcquisitionStop', + description = 'This feature stops the Acquisition of the device at the end of the current Frame.', + offset = 0x8020, + base = pr.UIntBE, + bitSize = 8, + bitOffset = 24, + function = lambda cmd: cmd.post(0), + )) + + self.add(pr.RemoteVariable( + name = 'pFrameRateReg', + description = 'Frame rate in Hz', + offset = 0x80C0, + base = pr.UIntBE, + mode = 'RW', + minimum = 30, + units = 'Hz', + disp = '{:d}', + # pollInterval = 1, + )) + + self.add(pr.RemoteVariable( + name = 'pFrameRateRegMax', + description = 'Maximum value for pFrameRateReg', + offset = 0x80C4, + base = pr.UIntBE, + mode = 'RO', + units = 'Hz', + disp = '{:d}', + # pollInterval = 1, + )) + + self.add(pr.RemoteVariable( + name = 'ExposureTimeReg', + description = 'Sets the Exposure time (in microseconds). This controls the duration where the photosensitive cells are exposed to light.', + offset = 0x80C8, + base = pr.FloatBE, + mode = 'RW', + units = '\u03BCs', + )) + + self.add(pr.RemoteVariable( + name = 'pExposureTimeRegMax', + description = 'Maximum value for ExposureTimeReg', + offset = 0x80CC, + base = pr.FloatBE, + mode = 'RO', + units = '\u03BCs', + # disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'SensorShutterModeReg', + description = 'Select Global or Rolling shutter mode.', + offset = 0x817C, + base = pr.UIntBE, + mode = 'RW', + enum = { + 0: 'Rolling', + 1: 'Global', + }, + )) + + self.add(pr.RemoteVariable( + name = 'TriggerModeReg', + description = 'Select camera sync mode.', + offset = 0x8128, + base = pr.UIntBE, + bitSize = 8, + bitOffset = 24, + mode = 'RW', + enum = { + 0: 'TriggerModeOff', + 1: 'TriggerModeOn', + }, + )) + + self.add(pr.RemoteVariable( + name = 'TriggerSelectorReg', + description = 'Selects the type of trigger to configure.', + offset = 0x8128, + base = pr.UIntBE, + bitSize = 8, + bitOffset = 16, + mode = 'RW', + enum = { + 0: 'ExposureStart', + 1: 'ExposureActive', + }, + )) + + self.add(pr.RemoteVariable( + name = 'TriggerSourceReg', + description = 'Specifies the internal signal or physical input Line to use as the trigger source. The selected trigger must have its TriggerMode set to On.', + offset = 0x8128, + base = pr.UIntBE, + bitSize = 8, + bitOffset = 8, + mode = 'RW', + enum = { + 0: 'GPIO0', + 1: 'GPIO1', + 2: 'GPIO2', + 5: 'SWTRIGGER', + }, + )) + + self.add(pr.RemoteVariable( + name = 'CTRLReg_fan', + description = 'Turn camera fan on/off.', + offset = 0x8180, + base = pr.UIntBE, + bitSize = 8, + bitOffset = 16, + mode = 'RW', + enum = { + 0: 'FanOff', + 1: 'FanOn', + }, + )) + + self.add(pr.RemoteVariable( + name = 'CTRLReg_led', + description = 'Turn CXP LEDs on/off.', + offset = 0x8180, + base = pr.UIntBE, + bitSize = 8, + bitOffset = 8, + mode = 'RW', + enum = { + 0: 'LEDOff', + 1: 'LEDOn', + }, + )) + + self.add(pr.RemoteVariable( + name = 'TimeStampSetReg', + description = 'Set camera time by entering current time in seconds since January 1st, 1970.', + offset = 0x8188, + base = pr.UIntBE, + mode = 'WO', + hidden = True, + )) + + self.add(pr.RemoteVariable( + name = 'LensApertureReg', + description = 'Lens Aperture.', + offset = 0x81A0, + base = pr.UIntBE, + mode = 'RW', + enum = { + 0: 'undefined', + 10: 'f10', + 12: 'f12', + 14: 'f14', + 18: 'f18', + 20: 'f20', + 24: 'f24', + 28: 'f28', + 33: 'f33', + 40: 'f40', + 48: 'f48', + 56: 'f56', + 67: 'f67', + 80: 'f80', + 96: 'f96', + 110: 'f110', + 132: 'f132', + 160: 'f160', + 192: 'f192', + 220: 'f220', + 264: 'f264', + 320: 'f320', + 384: 'f384', + 480: 'f480', + 576: 'f576', + 640: 'f640', + }, + )) + + self.add(pr.RemoteVariable( + name = 'LensApertureMinReg', + description = 'Minimum value for LensApertureReg', + offset = 0x81A4, + base = pr.UIntBE, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'LensApertureMaxReg', + description = 'Maximum value for LensApertureReg', + offset = 0x81A8, + base = pr.UIntBE, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'LensFocusReg', + description = 'Set Lens Focus', + offset = 0x81AC, + base = pr.UIntBE, + mode = 'WO', + )) + + self.add(pr.RemoteVariable( + name = 'LensFocusStepReg', + description = 'Set Lens Focus Step', + offset = 0x81B0, + base = pr.UIntBE, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'LensShutterReg', + description = 'Camera Shutter Open/Close', + offset = 0x81B4, + base = pr.UIntBE, + mode = 'RW', + enum = { + 0: 'Open', + 1: 'Close', + }, + )) + + self.add(pr.RemoteVariable( + name = 'GainSelectorReg', + description = 'Selects which Gain is controlled by the various Gain features', + offset = 0x80E4, + base = pr.UIntBE, + mode = 'RW', + enum = { + 0: 'undefined', + 20: 'DigitalAll', + 21: 'DigitalRed', + 22: 'DigitalGreen', + 23: 'DigitalBlue', + }, + )) + + self.add(pr.RemoteVariable( + name = 'GainReg', + description = 'Controls the selected gain as an absolute physical value. This is an amplification factor applied to the video signal.', + offset = 0x80E8, + base = pr.FloatBE, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'BlackLevelSelectorReg', + description = 'Selects which Black Level is controlled by the various Black Level features.', + offset = 0x80F8, + base = pr.UIntBE, + mode = 'RW', + enum = { + 0: 'All', + 1: 'Red', + 2: 'Green', + 3: 'Blue', + }, + )) + + self.add(pr.RemoteVariable( + name = 'BlackLevelReg', + description = 'Controls the analog black level as an absolute physical value. This represents a DC offset applied to the video signal.', + offset = 0x80FC, + base = pr.FloatBE, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'BalanceWhiteAutoReg', + description = 'Controls the mode for automatic white balancing between the color channels.', + offset = 0x80DC, + base = pr.UIntBE, + mode = 'RW', + enum = { + 0: 'Off', + 1: 'Once', + }, + )) + + self.add(pr.RemoteVariable( + name = 'BalanceWhiteMarkerReg', + description = 'Auto White Balance Marker.', + offset = 0x80E0, + base = pr.UIntBE, + mode = 'RW', + enum = { + 0: 'Off', + 1: 'On', + }, + )) + + self.add(pr.RemoteCommand( + name = 'GainBlackLevelResetReg', + description = 'Set camera gain and black level to default.', + offset = 0x8208, + base = pr.UIntBE, + function = lambda cmd: cmd.post(1), + )) + + self.add(pr.RemoteVariable( + name = 'OutputRawImageReg', + description = 'Grab raw images', + offset = 0x820C, + base = pr.UIntBE, + mode = 'RW', + enum = { + 0: 'Off', + 1: 'Once', + }, + )) + + for i in range(3): + self.add(pr.RemoteVariable( + name = f'DigitalIOReg[{i}]', + description = 'Selects the physical line (or pin) of the external device connector or the virtual line of the Transport Layer to configure.', + offset = 0x8198, + base = pr.UIntBE, + bitSize = 8, + bitOffset = 24-(i*8), + mode = 'RW', + enum = { + 0: 'EventIn', + 3: 'MemGate', + 6: 'UserIn', + 16: 'Strobe', + 17: 'TriggerOut', + 18: 'Ready', + 21: 'SWTrigger', + 22: 'TimecodeOut', + 31: 'UserOut', + }, + )) + + self.add(pr.RemoteVariable( + name = 'UserOutputSetReg', + description = 'Set user output high/low.', + offset = 0x8200, + base = pr.UIntBE, + mode = 'RW', + enum = { + 0: 'Low', + 1: 'High', + }, + )) + + self.add(pr.RemoteVariable( + name = 'UserInputStatusReg', + description = 'Displays state of user input GPIO line.', + offset = 0x8204, + base = pr.UIntBE, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'LinkNumberReg', + description = 'Bootstrap register Banks.', + offset = 0x8184, + base = pr.UIntBE, + mode = 'RW', + enum = { + 0: 'Banks_A', + 1: 'Banks_AB', + }, + )) + + self.add(pr.RemoteVariable( + name = 'ConnectedBankIDReg', + description = 'Connected Bank ID', + offset = 0x80D8, + base = pr.UIntBE, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'EventRefreshReg', + description = 'Refresh rate (ms) of CXP events. 0 = Events Off', + offset = 0x827C, + base = pr.UIntBE, + mode = 'RW', + units = 'ms', + )) + + self.add(pr.RemoteVariable( + name = 'DeviceTapGeometryReg', + description = 'This device tap geometry feature describes the geometrical properties characterizing the taps of a camera as presented at the output of the device.', + offset = 0x800C, + base = pr.UIntBE, + mode = 'RW', + enum = { + 0: 'Geometry_1X_1Y', + }, + )) + + # self.add(pr.RemoteVariable( + # name = 'UserSerialTxReg', + # description = 'FOR User Serial Rx/Tx', + # offset = 0x8148, + # base = pr.UIntBE, + # mode = 'RW', + # hidden = True, + # )) + + # self.add(pr.RemoteVariable( + # name = 'UserSerialRxReg', + # description = 'FOR User Serial Rx/Tx', + # offset = 0x8154, + # base = pr.UIntBE, + # mode = 'RO', + # hidden = True, + # )) + + # self.add(pr.RemoteVariable( + # name = 'UserSerialBaudRateReg', + # description = 'FOR User Serial Rx/Tx', + # offset = 0x8164, + # base = pr.UIntBE, + # mode = 'RW', + # hidden = True, + # )) + + # self.add(pr.RemoteVariable( + # name = 'FactorySerialTxReg', + # description = 'FOR Factory Serial Rx/Tx', + # offset = 0x8140, + # base = pr.UIntBE, + # mode = 'RW', + # hidden = True, + # )) + + # self.add(pr.RemoteVariable( + # name = 'FactorySerialRxReg', + # description = 'FOR Factory Serial Rx/Tx', + # offset = 0x8144, + # base = pr.UIntBE, + # mode = 'RO', + # hidden = True, + # )) + + # self.add(pr.RemoteVariable( + # name = 'FactorySerialUpdateReg', + # description = 'FOR Factory Serial Rx/Tx', + # offset = 0x8130, + # base = pr.UIntBE, + # mode = 'RW', + # hidden = True, + # )) diff --git a/python/surf/protocols/coaxpress/__init__.py b/python/surf/protocols/coaxpress/__init__.py index f1306a7a4a..d90f51e984 100644 --- a/python/surf/protocols/coaxpress/__init__.py +++ b/python/surf/protocols/coaxpress/__init__.py @@ -12,3 +12,4 @@ from surf.protocols.coaxpress._PhantomS991 import * from surf.protocols.coaxpress._PhantomS641 import * +from surf.protocols.coaxpress._PhantomS711 import * From add2a8510c4a5aadd88b17c124fabf4fa707e7a6 Mon Sep 17 00:00:00 2001 From: Luca Scomparin Date: Wed, 22 Apr 2026 14:25:46 -0700 Subject: [PATCH 39/92] Fixed bug when line and CXP marker were provided in the same transaction as line data --- .../coaxpress/core/rtl/CoaXPressRxHsFsm.vhd | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd b/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd index ee862dd7cb..090c14150a 100644 --- a/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd +++ b/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd @@ -254,12 +254,18 @@ begin v.dCnt := r.dCnt + 1; ---------------------------------------------------------------------- when LINE_S => - -- Accept the data - v.rxSlave.tReady := '1'; - -- Write the data v.dataMasters(0).tValid := '1'; + -- Accept the data + -- Don't send TREADY if we have the marker in the + -- current transaction + if (v.dCnt+NUM_LANES_G > r.hdr.dsizeL(RX_FSM_CNT_WIDTH_G-1 downto 0)) then + v.rxSlave.tReady := '0'; + else + v.rxSlave.tReady := '1'; + end if; + -- Loop the number of 32-bit words for i in 0 to NUM_LANES_G-1 loop @@ -281,6 +287,11 @@ begin -- Next State v.state := IDLE_S; + -- Starting point for next cycle IDLE state + if (i /= NUM_LANES_G-1) then + v.wrd := i+1; + end if; + end if; end if; From 24c14e2ef9302f7ce132df0f9a942ebe2c0326e7 Mon Sep 17 00:00:00 2001 From: Luca Scomparin Date: Wed, 22 Apr 2026 16:29:38 -0700 Subject: [PATCH 40/92] Adapted S641 register map to S711 --- .../surf/protocols/coaxpress/_PhantomS641.py | 18 +- .../surf/protocols/coaxpress/_PhantomS711.py | 627 ------------------ python/surf/protocols/coaxpress/__init__.py | 1 - 3 files changed, 9 insertions(+), 637 deletions(-) delete mode 100644 python/surf/protocols/coaxpress/_PhantomS711.py diff --git a/python/surf/protocols/coaxpress/_PhantomS641.py b/python/surf/protocols/coaxpress/_PhantomS641.py index 2ab7b7424a..3f5b135645 100755 --- a/python/surf/protocols/coaxpress/_PhantomS641.py +++ b/python/surf/protocols/coaxpress/_PhantomS641.py @@ -11,7 +11,7 @@ import pyrogue as pr class PhantomS641(pr.Device): - def __init__(self, **kwargs): + def __init__(self, isPhantomS711=False, **kwargs): super().__init__(**kwargs) ############################################################# # Start of manufacturer-specific register space at 0x00006000 @@ -274,7 +274,7 @@ def __init__(self, **kwargs): offset = 0x80C0, base = pr.UIntBE, mode = 'RW', - minimum = 24, + minimum = 24 , units = 'Hz', disp = '{:d}', # pollInterval = 1, @@ -295,21 +295,21 @@ def __init__(self, **kwargs): name = 'ExposureTimeReg', description = 'Sets the Exposure time (in microseconds). This controls the duration where the photosensitive cells are exposed to light.', offset = 0x80C8, - base = pr.UIntBE, + base = pr.UIntBE if not isPhantomS711 else pr.FloatBE, mode = 'RW', minimum = 1, units = '\u03BCs', - disp = '{:d}', + disp = '{:d}' if not isPhantomS711 else '', )) self.add(pr.RemoteVariable( name = 'pExposureTimeRegMax', description = 'Maximum value for ExposureTimeReg', offset = 0x80CC, - base = pr.UIntBE, + base = pr.UIntBE if not isPhantomS711 else pr.FloatBE, mode = 'RO', units = '\u03BCs', - disp = '{:d}', + disp = '{:d}' if not isPhantomS711 else '', )) self.add(pr.RemoteVariable( @@ -320,7 +320,7 @@ def __init__(self, **kwargs): mode = 'RW', minimum = 0, units = '\u03BCs', - disp = '{:d}', + disp = '{:d}' if not isPhantomS711 else '', )) self.add(pr.RemoteVariable( @@ -551,7 +551,7 @@ def __init__(self, **kwargs): name = 'GainReg', description = 'Controls the selected gain as an absolute physical value. This is an amplification factor applied to the video signal.', offset = 0x80E8, - base = pr.UIntBE, + base = pr.UIntBE if not isPhantomS711 else pr.FloatBE, mode = 'RW', )) @@ -573,7 +573,7 @@ def __init__(self, **kwargs): name = 'BlackLevelReg', description = 'Controls the analog black level as an absolute physical value. This represents a DC offset applied to the video signal.', offset = 0x80FC, - base = pr.UIntBE, + base = pr.UIntBE if not isPhantomS711 else pr.FloatBE, mode = 'RW', )) diff --git a/python/surf/protocols/coaxpress/_PhantomS711.py b/python/surf/protocols/coaxpress/_PhantomS711.py deleted file mode 100644 index f343dfddb3..0000000000 --- a/python/surf/protocols/coaxpress/_PhantomS711.py +++ /dev/null @@ -1,627 +0,0 @@ -#----------------------------------------------------------------------------- -# This file is part of the 'SLAC Firmware Standard Library'. It is subject to -# the license terms in the LICENSE.txt file found in the top-level directory -# of this distribution and at: -# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -# No part of the 'SLAC Firmware Standard Library', including this file, may be -# copied, modified, propagated, or distributed except according to the terms -# contained in the LICENSE.txt file. -#----------------------------------------------------------------------------- - -import pyrogue as pr - -class PhantomS711(pr.Device): - def __init__(self, **kwargs): - super().__init__(**kwargs) - ############################################################# - # Start of manufacturer-specific register space at 0x00006000 - ############################################################# - - self.add(pr.RemoteVariable( - name = 'DevicePhfwVersionReg', - description = 'Version of the firmware in the device.', - offset = 0x8174, - base = pr.UIntBE, - mode = 'RO', - )) - - self.add(pr.RemoteVariable( - name = 'DeviceSerialNumberReg', - description = 'Serial Number of device.', - offset = 0x8158, - base = pr.UIntBE, - mode = 'RO', - )) - - self.add(pr.RemoteVariable( - name = 'DeviceIPAddress', - description = 'This feature provides the static IP address of the device', - offset = 0x8300, - base = pr.String, - bitSize = 8*32, - mode = 'RO', - # hidden = True, - )) - - self.add(pr.RemoteVariable( - name = 'DeviceNetmask', - description = 'This feature provides the Netmask address of the device', - offset = 0x8320, - base = pr.String, - bitSize = 8*32, - mode = 'RO', - # hidden = True, - )) - - self.add(pr.RemoteVariable( - name = 'pDeviceTemperatureSelectorReg', - description = 'Selects the location within the device, where the temperature will be measured.', - offset = 0x8168, - base = pr.UIntBE, - bitSize = 16, - bitOffset = 0, - mode = 'RW', - )) - - self.add(pr.RemoteVariable( - name = 'pDeviceTemperatureReg', - description = 'Device temperature in degrees Celsius (C).', - offset = 0x8168, - base = pr.IntBE, - bitSize = 16, - bitOffset = 16, - mode = 'RO', - units = 'degC', - disp = '{:d}', - )) - - self.add(pr.RemoteVariable( - name = 'WidthMaxReg', - description = 'Maximum width (in pixels) of the image. The dimension is calculated after horizontal binning, decimation or any other function changing the horizontal dimension of the image.', - offset = 0x8010, - base = pr.UIntBE, - mode = 'RO', - units = 'pixels', - disp = '{:d}', - )) - - self.add(pr.RemoteVariable( - name = 'WidthReg', - description = 'This feature represents the actual image width expelled by the camera (in pixels).', - offset = 0x8000, - base = pr.UIntBE, - mode = 'RW', - units = 'pixels', - disp = '{:d}', - )) - - self.add(pr.RemoteVariable( - name = 'HeightMaxReg', - description = 'Maximum height (in pixels) of the image. This dimension is calculated after vertical binning, decimation or any other function changing the vertical dimension of the image.', - offset = 0x8014, - base = pr.UIntBE, - mode = 'RO', - units = 'pixels', - disp = '{:d}', - )) - - self.add(pr.RemoteVariable( - name = 'HeightReg', - description = 'This feature represents the actual image height expelled by the camera (in pixels).', - offset = 0x8004, - base = pr.UIntBE, - mode = 'RW', - units = 'pixels', - disp = '{:d}', - )) - - self.add(pr.RemoteVariable( - name = 'PixelFormatReg', - description = 'This feature indicates the format of the pixel to use during the acquisition.', - offset = 0x8008, - base = pr.UIntBE, - mode = 'RW', - enum = { - 0x00000000: 'Undefined', - 0x01080001: 'Mono8', - 0x010C0006: 'Mono12', - 0x01100007: 'Mono16', - 0x0108000A: 'BayerGB8', - 0x010C0055: 'BayerGB12', - }, - )) - - self.add(pr.RemoteVariable( - name = 'ImageSourceReg', - description = 'This feature controls the image source.', - offset = 0x8120, - base = pr.UIntBE, - mode = 'RW', - enum = { - 0: 'LiveImage', - 1: 'OffsetTableRolling', - 2: 'GainTableAtRolling', - 3: 'OffsetTableGlobal', - 4: 'GainTableAtGlobal', - }, - )) - - self.add(pr.RemoteVariable( - name = 'ImageSourceGrabReg', - description = 'Grab Gain and Offset from camera.', - offset = 0x8124, - base = pr.UIntBE, - mode = 'WO', - )) - - self.add(pr.RemoteVariable( - name = 'AcquisitionModeReg', - description = 'This feature controls the acquisition mode of the device.', - offset = 0x8018, - base = pr.UIntBE, - mode = 'RW', - enum = { - 0: 'undefined', - 2: 'Continuous', - }, - )) - - self.add(pr.RemoteCommand( - name = 'AcquisitionStart', - description = 'This feature starts the Acquisition of the device.', - offset = 0x801C, - base = pr.UIntBE, - bitSize = 8, - bitOffset = 24, - function = lambda cmd: cmd.post(1), - )) - - self.add(pr.RemoteCommand( - name = 'AcquisitionStop', - description = 'This feature stops the Acquisition of the device at the end of the current Frame.', - offset = 0x8020, - base = pr.UIntBE, - bitSize = 8, - bitOffset = 24, - function = lambda cmd: cmd.post(0), - )) - - self.add(pr.RemoteVariable( - name = 'pFrameRateReg', - description = 'Frame rate in Hz', - offset = 0x80C0, - base = pr.UIntBE, - mode = 'RW', - minimum = 30, - units = 'Hz', - disp = '{:d}', - # pollInterval = 1, - )) - - self.add(pr.RemoteVariable( - name = 'pFrameRateRegMax', - description = 'Maximum value for pFrameRateReg', - offset = 0x80C4, - base = pr.UIntBE, - mode = 'RO', - units = 'Hz', - disp = '{:d}', - # pollInterval = 1, - )) - - self.add(pr.RemoteVariable( - name = 'ExposureTimeReg', - description = 'Sets the Exposure time (in microseconds). This controls the duration where the photosensitive cells are exposed to light.', - offset = 0x80C8, - base = pr.FloatBE, - mode = 'RW', - units = '\u03BCs', - )) - - self.add(pr.RemoteVariable( - name = 'pExposureTimeRegMax', - description = 'Maximum value for ExposureTimeReg', - offset = 0x80CC, - base = pr.FloatBE, - mode = 'RO', - units = '\u03BCs', - # disp = '{:d}', - )) - - self.add(pr.RemoteVariable( - name = 'SensorShutterModeReg', - description = 'Select Global or Rolling shutter mode.', - offset = 0x817C, - base = pr.UIntBE, - mode = 'RW', - enum = { - 0: 'Rolling', - 1: 'Global', - }, - )) - - self.add(pr.RemoteVariable( - name = 'TriggerModeReg', - description = 'Select camera sync mode.', - offset = 0x8128, - base = pr.UIntBE, - bitSize = 8, - bitOffset = 24, - mode = 'RW', - enum = { - 0: 'TriggerModeOff', - 1: 'TriggerModeOn', - }, - )) - - self.add(pr.RemoteVariable( - name = 'TriggerSelectorReg', - description = 'Selects the type of trigger to configure.', - offset = 0x8128, - base = pr.UIntBE, - bitSize = 8, - bitOffset = 16, - mode = 'RW', - enum = { - 0: 'ExposureStart', - 1: 'ExposureActive', - }, - )) - - self.add(pr.RemoteVariable( - name = 'TriggerSourceReg', - description = 'Specifies the internal signal or physical input Line to use as the trigger source. The selected trigger must have its TriggerMode set to On.', - offset = 0x8128, - base = pr.UIntBE, - bitSize = 8, - bitOffset = 8, - mode = 'RW', - enum = { - 0: 'GPIO0', - 1: 'GPIO1', - 2: 'GPIO2', - 5: 'SWTRIGGER', - }, - )) - - self.add(pr.RemoteVariable( - name = 'CTRLReg_fan', - description = 'Turn camera fan on/off.', - offset = 0x8180, - base = pr.UIntBE, - bitSize = 8, - bitOffset = 16, - mode = 'RW', - enum = { - 0: 'FanOff', - 1: 'FanOn', - }, - )) - - self.add(pr.RemoteVariable( - name = 'CTRLReg_led', - description = 'Turn CXP LEDs on/off.', - offset = 0x8180, - base = pr.UIntBE, - bitSize = 8, - bitOffset = 8, - mode = 'RW', - enum = { - 0: 'LEDOff', - 1: 'LEDOn', - }, - )) - - self.add(pr.RemoteVariable( - name = 'TimeStampSetReg', - description = 'Set camera time by entering current time in seconds since January 1st, 1970.', - offset = 0x8188, - base = pr.UIntBE, - mode = 'WO', - hidden = True, - )) - - self.add(pr.RemoteVariable( - name = 'LensApertureReg', - description = 'Lens Aperture.', - offset = 0x81A0, - base = pr.UIntBE, - mode = 'RW', - enum = { - 0: 'undefined', - 10: 'f10', - 12: 'f12', - 14: 'f14', - 18: 'f18', - 20: 'f20', - 24: 'f24', - 28: 'f28', - 33: 'f33', - 40: 'f40', - 48: 'f48', - 56: 'f56', - 67: 'f67', - 80: 'f80', - 96: 'f96', - 110: 'f110', - 132: 'f132', - 160: 'f160', - 192: 'f192', - 220: 'f220', - 264: 'f264', - 320: 'f320', - 384: 'f384', - 480: 'f480', - 576: 'f576', - 640: 'f640', - }, - )) - - self.add(pr.RemoteVariable( - name = 'LensApertureMinReg', - description = 'Minimum value for LensApertureReg', - offset = 0x81A4, - base = pr.UIntBE, - mode = 'RO', - )) - - self.add(pr.RemoteVariable( - name = 'LensApertureMaxReg', - description = 'Maximum value for LensApertureReg', - offset = 0x81A8, - base = pr.UIntBE, - mode = 'RO', - )) - - self.add(pr.RemoteVariable( - name = 'LensFocusReg', - description = 'Set Lens Focus', - offset = 0x81AC, - base = pr.UIntBE, - mode = 'WO', - )) - - self.add(pr.RemoteVariable( - name = 'LensFocusStepReg', - description = 'Set Lens Focus Step', - offset = 0x81B0, - base = pr.UIntBE, - mode = 'RW', - )) - - self.add(pr.RemoteVariable( - name = 'LensShutterReg', - description = 'Camera Shutter Open/Close', - offset = 0x81B4, - base = pr.UIntBE, - mode = 'RW', - enum = { - 0: 'Open', - 1: 'Close', - }, - )) - - self.add(pr.RemoteVariable( - name = 'GainSelectorReg', - description = 'Selects which Gain is controlled by the various Gain features', - offset = 0x80E4, - base = pr.UIntBE, - mode = 'RW', - enum = { - 0: 'undefined', - 20: 'DigitalAll', - 21: 'DigitalRed', - 22: 'DigitalGreen', - 23: 'DigitalBlue', - }, - )) - - self.add(pr.RemoteVariable( - name = 'GainReg', - description = 'Controls the selected gain as an absolute physical value. This is an amplification factor applied to the video signal.', - offset = 0x80E8, - base = pr.FloatBE, - mode = 'RW', - )) - - self.add(pr.RemoteVariable( - name = 'BlackLevelSelectorReg', - description = 'Selects which Black Level is controlled by the various Black Level features.', - offset = 0x80F8, - base = pr.UIntBE, - mode = 'RW', - enum = { - 0: 'All', - 1: 'Red', - 2: 'Green', - 3: 'Blue', - }, - )) - - self.add(pr.RemoteVariable( - name = 'BlackLevelReg', - description = 'Controls the analog black level as an absolute physical value. This represents a DC offset applied to the video signal.', - offset = 0x80FC, - base = pr.FloatBE, - mode = 'RW', - )) - - self.add(pr.RemoteVariable( - name = 'BalanceWhiteAutoReg', - description = 'Controls the mode for automatic white balancing between the color channels.', - offset = 0x80DC, - base = pr.UIntBE, - mode = 'RW', - enum = { - 0: 'Off', - 1: 'Once', - }, - )) - - self.add(pr.RemoteVariable( - name = 'BalanceWhiteMarkerReg', - description = 'Auto White Balance Marker.', - offset = 0x80E0, - base = pr.UIntBE, - mode = 'RW', - enum = { - 0: 'Off', - 1: 'On', - }, - )) - - self.add(pr.RemoteCommand( - name = 'GainBlackLevelResetReg', - description = 'Set camera gain and black level to default.', - offset = 0x8208, - base = pr.UIntBE, - function = lambda cmd: cmd.post(1), - )) - - self.add(pr.RemoteVariable( - name = 'OutputRawImageReg', - description = 'Grab raw images', - offset = 0x820C, - base = pr.UIntBE, - mode = 'RW', - enum = { - 0: 'Off', - 1: 'Once', - }, - )) - - for i in range(3): - self.add(pr.RemoteVariable( - name = f'DigitalIOReg[{i}]', - description = 'Selects the physical line (or pin) of the external device connector or the virtual line of the Transport Layer to configure.', - offset = 0x8198, - base = pr.UIntBE, - bitSize = 8, - bitOffset = 24-(i*8), - mode = 'RW', - enum = { - 0: 'EventIn', - 3: 'MemGate', - 6: 'UserIn', - 16: 'Strobe', - 17: 'TriggerOut', - 18: 'Ready', - 21: 'SWTrigger', - 22: 'TimecodeOut', - 31: 'UserOut', - }, - )) - - self.add(pr.RemoteVariable( - name = 'UserOutputSetReg', - description = 'Set user output high/low.', - offset = 0x8200, - base = pr.UIntBE, - mode = 'RW', - enum = { - 0: 'Low', - 1: 'High', - }, - )) - - self.add(pr.RemoteVariable( - name = 'UserInputStatusReg', - description = 'Displays state of user input GPIO line.', - offset = 0x8204, - base = pr.UIntBE, - mode = 'RO', - )) - - self.add(pr.RemoteVariable( - name = 'LinkNumberReg', - description = 'Bootstrap register Banks.', - offset = 0x8184, - base = pr.UIntBE, - mode = 'RW', - enum = { - 0: 'Banks_A', - 1: 'Banks_AB', - }, - )) - - self.add(pr.RemoteVariable( - name = 'ConnectedBankIDReg', - description = 'Connected Bank ID', - offset = 0x80D8, - base = pr.UIntBE, - mode = 'RO', - )) - - self.add(pr.RemoteVariable( - name = 'EventRefreshReg', - description = 'Refresh rate (ms) of CXP events. 0 = Events Off', - offset = 0x827C, - base = pr.UIntBE, - mode = 'RW', - units = 'ms', - )) - - self.add(pr.RemoteVariable( - name = 'DeviceTapGeometryReg', - description = 'This device tap geometry feature describes the geometrical properties characterizing the taps of a camera as presented at the output of the device.', - offset = 0x800C, - base = pr.UIntBE, - mode = 'RW', - enum = { - 0: 'Geometry_1X_1Y', - }, - )) - - # self.add(pr.RemoteVariable( - # name = 'UserSerialTxReg', - # description = 'FOR User Serial Rx/Tx', - # offset = 0x8148, - # base = pr.UIntBE, - # mode = 'RW', - # hidden = True, - # )) - - # self.add(pr.RemoteVariable( - # name = 'UserSerialRxReg', - # description = 'FOR User Serial Rx/Tx', - # offset = 0x8154, - # base = pr.UIntBE, - # mode = 'RO', - # hidden = True, - # )) - - # self.add(pr.RemoteVariable( - # name = 'UserSerialBaudRateReg', - # description = 'FOR User Serial Rx/Tx', - # offset = 0x8164, - # base = pr.UIntBE, - # mode = 'RW', - # hidden = True, - # )) - - # self.add(pr.RemoteVariable( - # name = 'FactorySerialTxReg', - # description = 'FOR Factory Serial Rx/Tx', - # offset = 0x8140, - # base = pr.UIntBE, - # mode = 'RW', - # hidden = True, - # )) - - # self.add(pr.RemoteVariable( - # name = 'FactorySerialRxReg', - # description = 'FOR Factory Serial Rx/Tx', - # offset = 0x8144, - # base = pr.UIntBE, - # mode = 'RO', - # hidden = True, - # )) - - # self.add(pr.RemoteVariable( - # name = 'FactorySerialUpdateReg', - # description = 'FOR Factory Serial Rx/Tx', - # offset = 0x8130, - # base = pr.UIntBE, - # mode = 'RW', - # hidden = True, - # )) diff --git a/python/surf/protocols/coaxpress/__init__.py b/python/surf/protocols/coaxpress/__init__.py index d90f51e984..f1306a7a4a 100644 --- a/python/surf/protocols/coaxpress/__init__.py +++ b/python/surf/protocols/coaxpress/__init__.py @@ -12,4 +12,3 @@ from surf.protocols.coaxpress._PhantomS991 import * from surf.protocols.coaxpress._PhantomS641 import * -from surf.protocols.coaxpress._PhantomS711 import * From c77598549fe943573943803fbd92bfaa8196b494 Mon Sep 17 00:00:00 2001 From: Luca Scomparin Date: Wed, 22 Apr 2026 16:50:56 -0700 Subject: [PATCH 41/92] Removed register not present in S711 --- .../surf/protocols/coaxpress/_PhantomS641.py | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/python/surf/protocols/coaxpress/_PhantomS641.py b/python/surf/protocols/coaxpress/_PhantomS641.py index 3f5b135645..b49fe46e3a 100755 --- a/python/surf/protocols/coaxpress/_PhantomS641.py +++ b/python/surf/protocols/coaxpress/_PhantomS641.py @@ -170,15 +170,16 @@ def __init__(self, isPhantomS711=False, **kwargs): maximum = 2560, )) - self.add(pr.RemoteVariable( - name = 'OffsetYReg', - description = 'This feature represents the OffsetY', - offset = 0x807C, - base = pr.UIntBE, - mode = 'RW', - minimum = 0, - maximum = 1600, - )) + if not isPhantomS711: + self.add(pr.RemoteVariable( + name = 'OffsetYReg', + description = 'This feature represents the OffsetY', + offset = 0x807C, + base = pr.UIntBE, + mode = 'RW', + minimum = 0, + maximum = 1600, + )) self.add(pr.RemoteVariable( name = 'ActiveWidthReg', From 04d41b7a24e6714ba5ba084b3e3791e97c767497 Mon Sep 17 00:00:00 2001 From: Luca Scomparin Date: Wed, 22 Apr 2026 16:58:37 -0700 Subject: [PATCH 42/92] Created PhantomS711 class to follow device name convention --- python/surf/protocols/coaxpress/_PhantomS711.py | 16 ++++++++++++++++ python/surf/protocols/coaxpress/__init__.py | 1 + 2 files changed, 17 insertions(+) create mode 100644 python/surf/protocols/coaxpress/_PhantomS711.py diff --git a/python/surf/protocols/coaxpress/_PhantomS711.py b/python/surf/protocols/coaxpress/_PhantomS711.py new file mode 100644 index 0000000000..0b48d0c10b --- /dev/null +++ b/python/surf/protocols/coaxpress/_PhantomS711.py @@ -0,0 +1,16 @@ +#----------------------------------------------------------------------------- +# This file is part of the 'SLAC Firmware Standard Library'. It is subject to +# the license terms in the LICENSE.txt file found in the top-level directory +# of this distribution and at: +# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +# No part of the 'SLAC Firmware Standard Library', including this file, may be +# copied, modified, propagated, or distributed except according to the terms +# contained in the LICENSE.txt file. +#----------------------------------------------------------------------------- + +import pyrogue as pr +from surf.protocols.coaxpress._PhantomS641 import PhantomS641 + +class PhantomS711(PhantomS641): + def __init__(self, **kwargs): + super().__init__(isPhantomS711=True, **kwargs) \ No newline at end of file diff --git a/python/surf/protocols/coaxpress/__init__.py b/python/surf/protocols/coaxpress/__init__.py index f1306a7a4a..d90f51e984 100644 --- a/python/surf/protocols/coaxpress/__init__.py +++ b/python/surf/protocols/coaxpress/__init__.py @@ -12,3 +12,4 @@ from surf.protocols.coaxpress._PhantomS991 import * from surf.protocols.coaxpress._PhantomS641 import * +from surf.protocols.coaxpress._PhantomS711 import * From b99d131c18f3672330bc79b5e63a420f33b67bdc Mon Sep 17 00:00:00 2001 From: Luca Scomparin Date: Wed, 22 Apr 2026 17:00:19 -0700 Subject: [PATCH 43/92] Fixed linting --- python/surf/protocols/coaxpress/_PhantomS711.py | 1 - 1 file changed, 1 deletion(-) diff --git a/python/surf/protocols/coaxpress/_PhantomS711.py b/python/surf/protocols/coaxpress/_PhantomS711.py index 0b48d0c10b..051bff056e 100644 --- a/python/surf/protocols/coaxpress/_PhantomS711.py +++ b/python/surf/protocols/coaxpress/_PhantomS711.py @@ -8,7 +8,6 @@ # contained in the LICENSE.txt file. #----------------------------------------------------------------------------- -import pyrogue as pr from surf.protocols.coaxpress._PhantomS641 import PhantomS641 class PhantomS711(PhantomS641): From bc4f6219cbfee5a7ca4cb16bc7c050311057c78e Mon Sep 17 00:00:00 2001 From: Luca Scomparin Date: Wed, 22 Apr 2026 17:20:47 -0700 Subject: [PATCH 44/92] Linting fix --- python/surf/protocols/coaxpress/_PhantomS711.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/python/surf/protocols/coaxpress/_PhantomS711.py b/python/surf/protocols/coaxpress/_PhantomS711.py index 051bff056e..33d187ebb0 100644 --- a/python/surf/protocols/coaxpress/_PhantomS711.py +++ b/python/surf/protocols/coaxpress/_PhantomS711.py @@ -12,4 +12,4 @@ class PhantomS711(PhantomS641): def __init__(self, **kwargs): - super().__init__(isPhantomS711=True, **kwargs) \ No newline at end of file + super().__init__(isPhantomS711=True, **kwargs) From 1f3a101f939f7a8383de2d932bad59d898a09393 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 22 Apr 2026 17:29:44 -0700 Subject: [PATCH 45/92] More coaxpress tests. One small RTL fix. --- .../coaxpress/core/rtl/CoaXPressRxHsFsm.vhd | 10 +- tests/protocols/coaxpress/README.md | 9 + tests/protocols/coaxpress/test_CoaXPressRx.py | 275 +++++++++++++++++- .../coaxpress/test_CoaXPressRxHsFsm.py | 3 +- .../coaxpress/test_CoaXPressRxWordPacker.py | 219 ++++++++++++++ 5 files changed, 509 insertions(+), 7 deletions(-) diff --git a/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd b/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd index 3ffd47a6bf..fd28099b03 100644 --- a/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd +++ b/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd @@ -119,14 +119,17 @@ architecture rtl of CoaXPressRxHsFsm is dataMasters => (others => AXI_STREAM_MASTER_INIT_C), state => IDLE_S); - signal r : RegType := REG_INIT_C; - signal rin : RegType; + signal r : RegType := REG_INIT_C; + signal rin : RegType; + signal packRst : sl; -- attribute dont_touch : string; -- attribute dont_touch of r : signal is "TRUE"; begin + packRst <= rxRst or rxFsmRst; + comb : process (r, rxFsmRst, rxMaster, rxRst) is variable v : RegType; variable tData : slv(31 downto 0); @@ -295,6 +298,7 @@ begin -- Next State v.state := IDLE_S; + v.wrd := 0; end if; @@ -484,7 +488,7 @@ begin NUM_LANES_G => NUM_LANES_G) port map ( rxClk => rxClk, - rxRst => rxFsmRst, + rxRst => packRst, sAxisMaster => r.dataMasters(1), mAxisMaster => dataMaster); diff --git a/tests/protocols/coaxpress/README.md b/tests/protocols/coaxpress/README.md index dbe33c0ec8..a8f1a0d24d 100644 --- a/tests/protocols/coaxpress/README.md +++ b/tests/protocols/coaxpress/README.md @@ -149,6 +149,9 @@ The image-path benches are the strongest spec-aligned receive tests today: - `test_CoaXPressRx.py` - validates both the original one-lane top-level receive assembly and a dual-lane lane-rotation path around the same traffic + - also carries opt-in four-lane investigation benches behind + `RUN_KNOWN_ISSUE_TESTS=1`; those are intentionally not part of the + merge-ready passing slice yet `test_CoaXPressRxLane.py` also exercises stream packet handling using spec-shaped stream headers, but the emphasis there is on receive-lane state @@ -221,6 +224,12 @@ compliance coverage. The most important open limits are: - `CoaXPressConfig` is still skipped +- `CoaXPressRxHsFsm` still has an open bonded-receive issue on back-to-back + short four-lane image frames: later one-word tails can miss `TLAST`, which + merges or truncates adjacent frames +- the gated four-lane `CoaXPressRx` investigation benches are therefore still + opt-in only; they exist to track clean-rotation, malformed-header recovery, + and backpressure/overflow recovery once the short-tail boundary bug is fixed - the checked-in known-issue core bench for overflow-vs-FSM-error behavior is skipped by default until the receive-side backpressure interaction is understood and fixed diff --git a/tests/protocols/coaxpress/test_CoaXPressRx.py b/tests/protocols/coaxpress/test_CoaXPressRx.py index bd775009e3..5567e1e5a4 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRx.py +++ b/tests/protocols/coaxpress/test_CoaXPressRx.py @@ -157,6 +157,11 @@ def rep24(value: int) -> list[int]: repeat_byte(flags), ] + +def _logic_value_to_int(value, *, default: int = 0) -> int: + return int(value) if value.is_resolvable else default + + def _capture_outputs( dut, *, @@ -393,6 +398,31 @@ async def _drive_idle_and_capture( ) +async def _drive_idle_rx(dut, *, cycles: int) -> None: + num_lanes = env_int("NUM_LANES_G", default=1) + for _ in range(cycles): + await _send_multi_lane_word( + dut, + lane_words=[CXP_IDLE] * num_lanes, + lane_ks=[CXP_IDLE_K] * num_lanes, + link_up=_active_link_mask(), + ) + + +async def _drive_idle_until_signal_high(dut, *, signal, max_cycles: int) -> bool: + for _ in range(max_cycles): + await _drive_idle_rx(dut, cycles=1) + if _logic_value_to_int(signal.value) == 1: + return True + return False + + +async def _pulse_rx_fsm_reset(dut, *, cycles: int = 4) -> None: + dut.rxFsmRst.value = 1 + await _drive_idle_rx(dut, cycles=cycles) + dut.rxFsmRst.value = 0 + + @cocotb.test() async def coaxpress_rx_one_lane_integration_test(dut): if env_int("NUM_LANES_G", default=1) != 1: @@ -621,6 +651,138 @@ async def capture(cycle_index: int) -> None: assert any(beat[2] == 1 for beat in data_beats) +# +# Opt-in investigation benches. These stay behind RUN_KNOWN_ISSUE_TESTS until +# the remaining 4-lane short-frame boundary issue in CoaXPressRxHsFsm is fixed. +# +@cocotb.test(skip=os.getenv("RUN_KNOWN_ISSUE_TESTS") != "1") +async def coaxpress_rx_four_lane_fsm_error_reset_recovery_known_issue_test(dut): + if env_int("NUM_LANES_G", default=1) != 4: + return + + start_lockstep_clocks(dut.dataClk, dut.cfgClk, dut.txClk, dut.rxClk, period_ns=4.0) + set_initial_values( + dut, + { + "rxData": 0, + "rxDataK": 0, + "rxLinkUp": 0xF, + "rxFsmRst": 0, + "rxNumberOfLane": 3, + "dataTReady": 1, + "hdrTReady": 1, + }, + ) + await reset_signals( + dut, + clk=dut.rxClk, + reset_names=("dataRst", "cfgRst", "txRst", "rxRst"), + assert_cycles=4, + release_cycles=4, + ) + + await _send_isolated_lane_frame( + dut, + lane=0, + line_words=[0x0BAD0000, 0x0BAD0001, 0x0BAD0002], + header_words=_image_header_words(dsize_l=3), + stream_id=0x40, + packet_tag=0x50, + corrupt_header_index=5, + ) + assert await _drive_idle_until_signal_high( + dut, + signal=dut.rxFsmError, + max_cycles=env_int("CXP_RX_FOUR_LANE_ERROR_WAIT_CYCLES", default=64), + ) + await _pulse_rx_fsm_reset(dut) + + data_beats: list[tuple[int, int, int, int]] = [] + hdr_beats: list[tuple[int, int, int, int]] = [] + cycle_index = 0 + expected_recovery_words: list[int] = [] + for lane in range(4): + recovery_words = [0xD1000000 | (lane << 8) | word_index for word_index in range(3)] + expected_recovery_words.extend(recovery_words) + cycle_index = await _send_isolated_lane_frame_and_capture( + dut, + lane=lane, + line_words=recovery_words, + data_beats=data_beats, + hdr_beats=hdr_beats, + stream_id=0x60 + lane, + packet_tag=0x70 + lane, + start_cycle_index=cycle_index, + ) + + await _drive_idle_and_capture(dut, cycles=256, data_beats=data_beats, hdr_beats=hdr_beats, start_cycle_index=cycle_index) + + assert [beat[0] for beat in hdr_beats] == EXPECTED_HDR_WORDS * 4, hdr_beats + observed_data_words = [beat[0] for beat in data_beats] + subseq_start = find_subsequence(observed_data_words, expected_recovery_words) + assert subseq_start is not None, data_beats + observed_recovery_last = [beat[2] for beat in data_beats[subseq_start : subseq_start + len(expected_recovery_words)]] + assert observed_recovery_last == [0, 0, 1] * 4, observed_recovery_last + + +@cocotb.test(skip=os.getenv("RUN_KNOWN_ISSUE_TESTS") != "1") +async def coaxpress_rx_four_lane_clean_rotation_known_issue_test(dut): + if env_int("NUM_LANES_G", default=1) != 4: + return + + start_lockstep_clocks(dut.dataClk, dut.cfgClk, dut.txClk, dut.rxClk, period_ns=4.0) + set_initial_values( + dut, + { + "rxData": 0, + "rxDataK": 0, + "rxLinkUp": 0xF, + "rxFsmRst": 0, + "rxNumberOfLane": 3, + "dataTReady": 1, + "hdrTReady": 1, + }, + ) + await reset_signals( + dut, + clk=dut.rxClk, + reset_names=("dataRst", "cfgRst", "txRst", "rxRst"), + assert_cycles=4, + release_cycles=4, + ) + + data_beats: list[tuple[int, int, int, int]] = [] + hdr_beats: list[tuple[int, int, int, int]] = [] + cycle_index = 0 + expected_data_words: list[int] = [] + for lane in range(4): + line_words = [0xC1000000 | (lane << 8) | word_index for word_index in range(3)] + expected_data_words.extend(line_words) + cycle_index = await _send_isolated_lane_frame_and_capture( + dut, + lane=lane, + line_words=line_words, + data_beats=data_beats, + hdr_beats=hdr_beats, + stream_id=0x30 + lane, + packet_tag=0x40 + lane, + start_cycle_index=cycle_index, + ) + + await _drive_idle_and_capture( + dut, + cycles=256, + data_beats=data_beats, + hdr_beats=hdr_beats, + start_cycle_index=cycle_index, + ) + + assert [beat[0] for beat in hdr_beats] == EXPECTED_HDR_WORDS * 4, hdr_beats + observed_data_words = [beat[0] for beat in data_beats] + assert observed_data_words == expected_data_words, observed_data_words + assert [beat[2] for beat in data_beats] == [0, 0, 1] * 4, data_beats + + @cocotb.test(skip=os.getenv("RUN_KNOWN_ISSUE_TESTS") != "1") async def coaxpress_rx_four_lane_fsm_error_recovery_known_issue_test(dut): if env_int("NUM_LANES_G", default=1) != 4: @@ -687,7 +849,13 @@ async def coaxpress_rx_four_lane_fsm_error_recovery_known_issue_test(dut): start_cycle_index=cycle_index, ) - await _drive_idle_and_capture(dut, cycles=256, data_beats=data_beats, hdr_beats=hdr_beats, start_cycle_index=cycle_index) + await _drive_idle_and_capture( + dut, + cycles=256, + data_beats=data_beats, + hdr_beats=hdr_beats, + start_cycle_index=cycle_index, + ) stop_event.set() await monitor_task @@ -705,6 +873,101 @@ async def coaxpress_rx_four_lane_fsm_error_recovery_known_issue_test(dut): assert observed_recovery_last == [0, 0, 1] * 4, observed_recovery_last +@cocotb.test(skip=os.getenv("RUN_KNOWN_ISSUE_TESTS") != "1") +async def coaxpress_rx_four_lane_overflow_reset_recovery_known_issue_test(dut): + if env_int("NUM_LANES_G", default=1) != 4: + return + + start_lockstep_clocks(dut.dataClk, dut.cfgClk, dut.txClk, dut.rxClk, period_ns=4.0) + set_initial_values( + dut, + { + "rxData": 0, + "rxDataK": 0, + "rxLinkUp": 0xF, + "rxFsmRst": 0, + "rxNumberOfLane": 3, + "dataTReady": 0, + "hdrTReady": 1, + }, + ) + await reset_signals( + dut, + clk=dut.rxClk, + reset_names=("dataRst", "cfgRst", "txRst", "rxRst"), + assert_cycles=4, + release_cycles=4, + ) + + signal_counts = {"error_pulses": 0, "overflow_pulses": 0} + stop_event = Event() + monitor_tasks = [ + cocotb.start_soon(_count_signal_high_cycles(dut.rxFsmError, dut.rxClk, stop_event, signal_counts, "error_pulses")), + cocotb.start_soon(_count_signal_high_cycles(dut.rxOverflow, dut.rxClk, stop_event, signal_counts, "overflow_pulses")), + ] + + stress_line_words = [0xA0000000 + word_index for word_index in range(80)] + stress_header_words = _image_header_words(dsize_l=len(stress_line_words)) + stress_frame_count = env_int("CXP_RX_FOUR_LANE_OVERFLOW_FRAME_COUNT", default=32) + for index in range(stress_frame_count): + lane = index % 4 + await _send_isolated_lane_frame( + dut, + lane=lane, + line_words=stress_line_words, + header_words=stress_header_words, + stream_id=0x20 + lane, + packet_tag=0x30 + lane, + ) + + overflow_seen = await _drive_idle_until_signal_high( + dut, + signal=dut.rxOverflow, + max_cycles=env_int("CXP_RX_FOUR_LANE_OVERFLOW_WAIT_CYCLES", default=4096), + ) + dut.dataTReady.value = 1 + await _drive_idle_rx(dut, cycles=env_int("CXP_RX_FOUR_LANE_DRAIN_IDLE_CYCLES", default=512)) + await _pulse_rx_fsm_reset(dut) + + data_beats: list[tuple[int, int, int, int]] = [] + hdr_beats: list[tuple[int, int, int, int]] = [] + cycle_index = 0 + expected_recovery_words: list[int] = [] + for lane in range(4): + recovery_words = [0xE1000000 | (lane << 8) | word_index for word_index in range(3)] + expected_recovery_words.extend(recovery_words) + cycle_index = await _send_isolated_lane_frame_and_capture( + dut, + lane=lane, + line_words=recovery_words, + data_beats=data_beats, + hdr_beats=hdr_beats, + stream_id=0x80 + lane, + packet_tag=0x90 + lane, + start_cycle_index=cycle_index, + ) + + await _drive_idle_and_capture( + dut, + cycles=env_int("CXP_RX_FOUR_LANE_RECOVERY_IDLE_CYCLES", default=512), + data_beats=data_beats, + hdr_beats=hdr_beats, + start_cycle_index=cycle_index, + ) + + stop_event.set() + for task in monitor_tasks: + await task + + assert overflow_seen or signal_counts["overflow_pulses"] > 0, signal_counts + assert [beat[0] for beat in hdr_beats] == EXPECTED_HDR_WORDS * 4, hdr_beats + observed_data_words = [beat[0] for beat in data_beats] + subseq_start = find_subsequence(observed_data_words, expected_recovery_words) + assert subseq_start is not None, (signal_counts, observed_data_words[-64:]) + observed_recovery_last = [beat[2] for beat in data_beats[subseq_start : subseq_start + len(expected_recovery_words)]] + assert observed_recovery_last == [0, 0, 1] * 4, (signal_counts, observed_recovery_last) + + @cocotb.test(skip=os.getenv("RUN_KNOWN_ISSUE_TESTS") != "1") async def coaxpress_rx_four_lane_overflow_recovery_known_issue_test(dut): if env_int("NUM_LANES_G", default=1) != 4: @@ -872,9 +1135,15 @@ async def coaxpress_rx_repeated_single_line_frame_known_issue_test(dut): @pytest.mark.parametrize("parameters", PARAMETER_SWEEP) def test_CoaXPressRx(parameters): use_core_path_wrapper = os.getenv("CXP_RX_CORE_PATH_WRAPPER") == "1" + if use_core_path_wrapper: + toplevel = "surf.coaxpressrxcorepathwrapper" + wrapper = "protocols/coaxpress/core/wrappers/CoaXPressRxCorePathWrapper.vhd" + else: + toplevel = "surf.coaxpressrxwrapper" + wrapper = "protocols/coaxpress/core/wrappers/CoaXPressRxWrapper.vhd" run_surf_vhdl_test( test_file=__file__, - toplevel="surf.coaxpressrxcorepathwrapper" if use_core_path_wrapper else "surf.coaxpressrxwrapper", + toplevel=toplevel, parameters=parameters, extra_env=parameters, extra_vhdl_sources={ @@ -885,7 +1154,7 @@ def test_CoaXPressRx(parameters): "protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd", "protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd", "protocols/coaxpress/core/rtl/CoaXPressRx.vhd", - "protocols/coaxpress/core/wrappers/CoaXPressRxCorePathWrapper.vhd" if use_core_path_wrapper else "protocols/coaxpress/core/wrappers/CoaXPressRxWrapper.vhd", + wrapper, ] }, ) diff --git a/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py b/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py index cff28c1d35..5f6c3f0c24 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py +++ b/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py @@ -457,7 +457,7 @@ async def coaxpress_rx_hs_fsm_two_lane_step_alignment_test(dut): }, { "dataTData": 0x33333333, - "dataTKeep": keep_for_words(2), + "dataTKeep": keep_for_words(1), "dataTLast": 1, }, ] @@ -503,6 +503,7 @@ async def coaxpress_rx_hs_fsm_repeated_single_line_frame_known_issue_test(dut): PARAMETER_SWEEP = [ parameter_case("single_lane", NUM_LANES_G="1", RX_FSM_CNT_WIDTH_G="8"), parameter_case("dual_lane", NUM_LANES_G="2", RX_FSM_CNT_WIDTH_G="8"), + parameter_case("quad_lane", NUM_LANES_G="4", RX_FSM_CNT_WIDTH_G="8"), ] diff --git a/tests/protocols/coaxpress/test_CoaXPressRxWordPacker.py b/tests/protocols/coaxpress/test_CoaXPressRxWordPacker.py index 9c48d0ca32..b3e3e6d69f 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRxWordPacker.py +++ b/tests/protocols/coaxpress/test_CoaXPressRxWordPacker.py @@ -29,6 +29,7 @@ collect_pulses, cycle, keep_for_words, + lane_keep_mask, pack_words, reset_dut, send_axis_beats_no_ready, @@ -176,6 +177,224 @@ async def coaxpress_rx_word_packer_reset_flush_test(dut): ] +@cocotb.test() +async def coaxpress_rx_word_packer_three_word_last_beat_test(dut): + if env_int("NUM_LANES_G", default=1) != 4: + return + + start_clock(dut.rxClk) + dut.rxRst.setimmediatevalue(1) + dut.sAxisTValid.setimmediatevalue(0) + dut.sAxisTData.setimmediatevalue(0) + dut.sAxisTKeep.setimmediatevalue(0) + dut.sAxisTLast.setimmediatevalue(0) + await reset_dut(dut) + + observed: list[dict[str, int]] = [] + await send_axis_beats_no_ready( + dut, + beats=[ + AxisBeat( + data=pack_words([0x11111111, 0x22222222, 0x33333333]), + keep=keep_for_words(3), + last=1, + ) + ], + clk=dut.rxClk, + capture=observed, + valid_name="mAxisTValid", + field_names=("mAxisTData", "mAxisTKeep", "mAxisTLast"), + ) + observed.extend( + await collect_pulses( + dut, + clk=dut.rxClk, + cycles=4, + valid_name="mAxisTValid", + field_names=("mAxisTData", "mAxisTKeep", "mAxisTLast"), + ) + ) + + assert observed == [ + { + "mAxisTData": pack_words([0x11111111, 0x22222222, 0x33333333]), + "mAxisTKeep": keep_for_words(3), + "mAxisTLast": 1, + } + ] + + +@cocotb.test() +async def coaxpress_rx_word_packer_two_plus_one_last_beat_test(dut): + if env_int("NUM_LANES_G", default=1) != 4: + return + + start_clock(dut.rxClk) + dut.rxRst.setimmediatevalue(1) + dut.sAxisTValid.setimmediatevalue(0) + dut.sAxisTData.setimmediatevalue(0) + dut.sAxisTKeep.setimmediatevalue(0) + dut.sAxisTLast.setimmediatevalue(0) + await reset_dut(dut) + + observed: list[dict[str, int]] = [] + await send_axis_beats_no_ready( + dut, + beats=[ + AxisBeat( + data=pack_words([0x11111111, 0x22222222]), + keep=keep_for_words(2), + last=0, + ), + AxisBeat( + data=pack_words([0x33333333]), + keep=keep_for_words(1), + last=1, + ), + ], + clk=dut.rxClk, + capture=observed, + valid_name="mAxisTValid", + field_names=("mAxisTData", "mAxisTKeep", "mAxisTLast"), + ) + observed.extend( + await collect_pulses( + dut, + clk=dut.rxClk, + cycles=4, + valid_name="mAxisTValid", + field_names=("mAxisTData", "mAxisTKeep", "mAxisTLast"), + ) + ) + + assert observed == [ + { + "mAxisTData": pack_words([0x11111111, 0x22222222, 0x33333333]), + "mAxisTKeep": keep_for_words(3), + "mAxisTLast": 1, + } + ] + + +@cocotb.test() +async def coaxpress_rx_word_packer_offset_two_plus_one_last_beat_test(dut): + if env_int("NUM_LANES_G", default=1) != 4: + return + + start_clock(dut.rxClk) + dut.rxRst.setimmediatevalue(1) + dut.sAxisTValid.setimmediatevalue(0) + dut.sAxisTData.setimmediatevalue(0) + dut.sAxisTKeep.setimmediatevalue(0) + dut.sAxisTLast.setimmediatevalue(0) + await reset_dut(dut) + + observed: list[dict[str, int]] = [] + await send_axis_beats_no_ready( + dut, + beats=[ + AxisBeat( + data=pack_words([0xAAAAAAAA, 0xBBBBBBBB, 0x11111111, 0x22222222]), + keep=lane_keep_mask([2, 3]), + last=0, + ), + AxisBeat( + data=pack_words([0x33333333]), + keep=lane_keep_mask([0]), + last=1, + ), + ], + clk=dut.rxClk, + capture=observed, + valid_name="mAxisTValid", + field_names=("mAxisTData", "mAxisTKeep", "mAxisTLast"), + ) + observed.extend( + await collect_pulses( + dut, + clk=dut.rxClk, + cycles=4, + valid_name="mAxisTValid", + field_names=("mAxisTData", "mAxisTKeep", "mAxisTLast"), + ) + ) + + assert observed == [ + { + "mAxisTData": pack_words([0x11111111, 0x22222222, 0x33333333]), + "mAxisTKeep": keep_for_words(3), + "mAxisTLast": 1, + } + ] + + +@cocotb.test() +async def coaxpress_rx_word_packer_back_to_back_offset_short_frames_test(dut): + if env_int("NUM_LANES_G", default=1) != 4: + return + + start_clock(dut.rxClk) + dut.rxRst.setimmediatevalue(1) + dut.sAxisTValid.setimmediatevalue(0) + dut.sAxisTData.setimmediatevalue(0) + dut.sAxisTKeep.setimmediatevalue(0) + dut.sAxisTLast.setimmediatevalue(0) + await reset_dut(dut) + + observed: list[dict[str, int]] = [] + await send_axis_beats_no_ready( + dut, + beats=[ + AxisBeat( + data=pack_words([0xAAAAAAAA, 0xBBBBBBBB, 0x11111111, 0x22222222]), + keep=lane_keep_mask([2, 3]), + last=0, + ), + AxisBeat( + data=pack_words([0x33333333]), + keep=lane_keep_mask([0]), + last=1, + ), + AxisBeat( + data=pack_words([0xCCCCCCCC, 0xDDDDDDDD, 0x44444444, 0x55555555]), + keep=lane_keep_mask([2, 3]), + last=0, + ), + AxisBeat( + data=pack_words([0x66666666]), + keep=lane_keep_mask([0]), + last=1, + ), + ], + clk=dut.rxClk, + capture=observed, + valid_name="mAxisTValid", + field_names=("mAxisTData", "mAxisTKeep", "mAxisTLast"), + ) + observed.extend( + await collect_pulses( + dut, + clk=dut.rxClk, + cycles=6, + valid_name="mAxisTValid", + field_names=("mAxisTData", "mAxisTKeep", "mAxisTLast"), + ) + ) + + assert observed == [ + { + "mAxisTData": pack_words([0x11111111, 0x22222222, 0x33333333]), + "mAxisTKeep": keep_for_words(3), + "mAxisTLast": 1, + }, + { + "mAxisTData": pack_words([0x44444444, 0x55555555, 0x66666666]), + "mAxisTKeep": keep_for_words(3), + "mAxisTLast": 1, + }, + ] + + PARAMETER_SWEEP = [ parameter_case("single_lane", NUM_LANES_G="1"), parameter_case("four_lane", NUM_LANES_G="4"), From a1872493f142661e5f4e4b30f0af7d4a13526d6e Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 23 Apr 2026 12:22:01 -0700 Subject: [PATCH 46/92] Expand HsFsm coverage and fix RTL issues. --- .../coaxpress/core/rtl/CoaXPressRxHsFsm.vhd | 34 +-- .../coaxpress/test_CoaXPressRxHsFsm.py | 210 ++++++++++++++++++ 2 files changed, 231 insertions(+), 13 deletions(-) diff --git a/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd b/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd index 44afcd2613..b95f207830 100644 --- a/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd +++ b/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd @@ -133,6 +133,8 @@ begin comb : process (r, rxFsmRst, rxMaster, rxRst) is variable v : RegType; variable tData : slv(31 downto 0); + variable more : sl; + variable idx : natural range 0 to NUM_LANES_G-1; begin -- Latch the current value v := r; @@ -275,14 +277,11 @@ begin -- Write the data v.dataMasters(0).tValid := '1'; - -- Accept the data - -- Don't send TREADY if we have the marker in the - -- current transaction - if (v.dCnt+NUM_LANES_G > r.hdr.dsizeL(RX_FSM_CNT_WIDTH_G-1 downto 0)) then - v.rxSlave.tReady := '0'; - else - v.rxSlave.tReady := '1'; - end if; + -- Accept the data unless a later valid word in this same beat + -- must be reparsed as the next marker/type sequence. + v.rxSlave.tReady := '1'; + more := '0'; + idx := 0; -- Loop the number of 32-bit words for i in 0 to NUM_LANES_G-1 loop @@ -302,13 +301,22 @@ begin -- Set the "end of line" flag v.endOfLine := '1'; + -- Hold the current beat only when additional valid + -- words remain after the line tail. + for j in i+1 to NUM_LANES_G-1 loop + if (rxMaster.tKeep(4*j) = '1') and (more = '0') then + more := '1'; + idx := j; + end if; + end loop; + -- Next State v.state := IDLE_S; - v.wrd := 0; - - -- Starting point for next cycle IDLE state - if (i /= NUM_LANES_G-1) then - v.wrd := i+1; + if (more = '1') then + v.rxSlave.tReady := '0'; + v.wrd := idx; + else + v.wrd := 0; end if; end if; diff --git a/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py b/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py index 5f6c3f0c24..f7dabc67f1 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py +++ b/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py @@ -151,6 +151,72 @@ def _single_line_header_words() -> list[int]: ] +def _image_header_words_from_fields( + *, + stream_id: int, + source_tag: int, + x_size: int, + x_offs: int, + y_size: int, + y_offs: int, + dsize_l: int, + pixel_f: int, + tap_g: int, + flags: int, +) -> list[int]: + def rep24(value: int) -> list[int]: + return [ + repeat_byte((value >> 16) & 0xFF), + repeat_byte((value >> 8) & 0xFF), + repeat_byte(value & 0xFF), + ] + + return [ + repeat_byte(stream_id), + repeat_byte((source_tag >> 8) & 0xFF), + repeat_byte(source_tag & 0xFF), + *rep24(x_size), + *rep24(x_offs), + *rep24(y_size), + *rep24(y_offs), + *rep24(dsize_l), + repeat_byte((pixel_f >> 8) & 0xFF), + repeat_byte(pixel_f & 0xFF), + repeat_byte((tap_g >> 8) & 0xFF), + repeat_byte(tap_g & 0xFF), + repeat_byte(flags), + ] + + +def _expected_header_data_from_fields( + *, + stream_id: int, + source_tag: int, + x_size: int, + x_offs: int, + y_size: int, + y_offs: int, + dsize_l: int, + pixel_f: int, + tap_g: int, + flags: int, +) -> int: + return pack_words( + [ + (((source_tag >> 8) & 0xFF) << 24) + | ((source_tag & 0xFF) << 16) + | ((flags & 0xFF) << 8) + | (stream_id & 0xFF), + x_size & 0x00FF_FFFF, + x_offs & 0x00FF_FFFF, + y_size & 0x00FF_FFFF, + y_offs & 0x00FF_FFFF, + dsize_l & 0x00FF_FFFF, + ((tap_g & 0xFFFF) << 16) | (pixel_f & 0xFFFF), + ] + ) + + @cocotb.test() async def coaxpress_rx_hs_fsm_header_and_lines_test(dut): if env_int("NUM_LANES_G", default=1) != 1: @@ -463,6 +529,150 @@ async def coaxpress_rx_hs_fsm_two_lane_step_alignment_test(dut): ] +@cocotb.test() +async def coaxpress_rx_hs_fsm_quad_lane_tail_marker_type_same_beat_test(dut): + if env_int("NUM_LANES_G", default=1) != 4: + return + + start_clock(dut.rxClk) + dut.rxRst.setimmediatevalue(1) + dut.rxFsmRst.setimmediatevalue(0) + dut.sAxisTValid.setimmediatevalue(0) + dut.sAxisTData.setimmediatevalue(0) + dut.sAxisTKeep.setimmediatevalue(0) + dut.sAxisTLast.setimmediatevalue(0) + await reset_dut(dut, reset_names=("rxRst",)) + + stream_id = 0xB2 + source_tag = 0x3456 + x_size = 2 + x_offs = 0 + y_size = 2 + y_offs = 0 + dsize_l = 2 + pixel_f = 0x0010 + tap_g = 0x0020 + flags = 0x5E + + header_words = _image_header_words_from_fields( + stream_id=stream_id, + source_tag=source_tag, + x_size=x_size, + x_offs=x_offs, + y_size=y_size, + y_offs=y_offs, + dsize_l=dsize_l, + pixel_f=pixel_f, + tap_g=tap_g, + flags=flags, + ) + expected_header = _expected_header_data_from_fields( + stream_id=stream_id, + source_tag=source_tag, + x_size=x_size, + x_offs=x_offs, + y_size=y_size, + y_offs=y_offs, + dsize_l=dsize_l, + pixel_f=pixel_f, + tap_g=tap_g, + flags=flags, + ) + + header_beats: list[dict[str, int]] = [] + data_beats: list[dict[str, int]] = [] + error_seen = False + trace: list[str] = [] + + await _send_handshaked_beat( + dut, + data=_beat_data([CXP_MARKER], num_lanes=4), + keep=lane_keep_mask([0]), + ) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + await _send_handshaked_beat( + dut, + data=_beat_data([repeat_byte(CXP_PKT_IMAGE_HEADER)], num_lanes=4), + keep=lane_keep_mask([0]), + ) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + for word in header_words: + await _send_handshaked_beat( + dut, + data=_beat_data([word], num_lanes=4), + keep=lane_keep_mask([0]), + ) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + + await _send_handshaked_beat( + dut, + data=_beat_data([CXP_MARKER], num_lanes=4), + keep=lane_keep_mask([0]), + ) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + await _send_handshaked_beat( + dut, + data=_beat_data([repeat_byte(CXP_PKT_IMAGE_LINE)], num_lanes=4), + keep=lane_keep_mask([0]), + ) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + + # Cover the merged corner case: the first line ends while the remaining + # words in the same 4-lane beat already contain the next line marker/type. + dut.sAxisTValid.value = 1 + dut.sAxisTData.value = _beat_data( + [0x11111111, 0x22222222, CXP_MARKER, repeat_byte(CXP_PKT_IMAGE_LINE)], + num_lanes=4, + ) + dut.sAxisTKeep.value = lane_keep_mask([0, 1, 2, 3]) + dut.sAxisTLast.value = 0 + shared_beat_cycles = 0 + while True: + await RisingEdge(dut.rxClk) + await Timer(1, unit="ns") + shared_beat_cycles += 1 + error_seen |= int(dut.rxFsmError.value) == 1 + trace.append( + f"shared[{shared_beat_cycles}] ready={int(dut.sAxisTReady.value)} " + f"err={int(dut.rxFsmError.value)} data={len(data_beats)} hdr={len(header_beats)}" + ) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + if int(dut.sAxisTReady.value) == 1: + break + dut.sAxisTValid.value = 0 + dut.sAxisTData.value = 0 + dut.sAxisTKeep.value = 0 + dut.sAxisTLast.value = 0 + + await _send_handshaked_beat( + dut, + data=_beat_data([0x33333333, 0x44444444], num_lanes=4), + keep=lane_keep_mask([0, 1]), + ) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + + for _ in range(8): + await RisingEdge(dut.rxClk) + await Timer(1, unit="ns") + error_seen |= int(dut.rxFsmError.value) == 1 + trace.append( + f"idle ready={int(dut.sAxisTReady.value)} err={int(dut.rxFsmError.value)} " + f"data={len(data_beats)} hdr={len(header_beats)}" + ) + _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) + + assert shared_beat_cycles > 1, trace + assert not error_seen, f"{trace}\nheaders={header_beats}\ndata={data_beats}" + assert header_beats == [{"hdrTData": expected_header, "hdrTLast": 1, "hdrTSof": 1}], trace + assert data_beats == [ + { + "dataTData": pack_words([0x11111111, 0x22222222, 0x33333333, 0x44444444]), + "dataTKeep": keep_for_words(4), + "dataTLast": 1, + } + ], trace + + @cocotb.test(skip=os.getenv("RUN_KNOWN_ISSUE_TESTS") != "1") async def coaxpress_rx_hs_fsm_repeated_single_line_frame_known_issue_test(dut): if env_int("NUM_LANES_G", default=1) != 1: From 2b318e68bfc9bf38533c644d80970cf13d1687a9 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 23 Apr 2026 12:24:32 -0700 Subject: [PATCH 47/92] coaxpress: port RxHsFsm fixes from verification-2 --- .../coaxpress/core/rtl/CoaXPressRxHsFsm.vhd | 69 +++++++++++++------ 1 file changed, 48 insertions(+), 21 deletions(-) diff --git a/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd b/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd index 090c14150a..b95f207830 100644 --- a/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd +++ b/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd @@ -93,6 +93,7 @@ architecture rtl of CoaXPressRxHsFsm is type RegType is record endOfLine : sl; + hdrValid : sl; yCnt : slv(RX_FSM_CNT_WIDTH_G-1 downto 0); dCnt : slv(RX_FSM_CNT_WIDTH_G-1 downto 0); hdrCnt : natural range 0 to 25; @@ -106,6 +107,7 @@ architecture rtl of CoaXPressRxHsFsm is end record RegType; constant REG_INIT_C : RegType := ( endOfLine => '0', + hdrValid => '0', yCnt => (others => '0'), dCnt => (others => '0'), hdrCnt => 0, @@ -117,17 +119,22 @@ architecture rtl of CoaXPressRxHsFsm is dataMasters => (others => AXI_STREAM_MASTER_INIT_C), state => IDLE_S); - signal r : RegType := REG_INIT_C; - signal rin : RegType; + signal r : RegType := REG_INIT_C; + signal rin : RegType; + signal packRst : sl; -- attribute dont_touch : string; -- attribute dont_touch of r : signal is "TRUE"; begin + packRst <= rxRst or rxFsmRst; + comb : process (r, rxFsmRst, rxMaster, rxRst) is variable v : RegType; variable tData : slv(31 downto 0); + variable more : sl; + variable idx : natural range 0 to NUM_LANES_G-1; begin -- Latch the current value v := r; @@ -191,10 +198,12 @@ begin v.hdrCnt := 3; -- Reset counters - v.yCnt := (others => '0'); + v.endOfLine := '0'; + v.hdrValid := '0'; + v.yCnt := (others => '0'); -- Check for out of sync header - if (r.yCnt /= r.hdr.ySize(RX_FSM_CNT_WIDTH_G-1 downto 0)) then + if (r.hdrValid = '1') and (r.yCnt /= r.hdr.ySize(RX_FSM_CNT_WIDTH_G-1 downto 0)) then -- Set the flag v.dbg.errDet := '1'; end if; @@ -204,8 +213,16 @@ begin -- Check for "Rectangular line marker" elsif (tData = x"02_02_02_02") then - -- Next State - v.state := LINE_S; + if (r.hdrValid = '1') then + -- Next State + v.state := LINE_S; + else + -- Set the flag + v.dbg.errDet := '1'; + + -- Next State + v.state := IDLE_S; + end if; else -- Set the flag @@ -221,7 +238,9 @@ begin or (tData(7 downto 0) /= tData(31 downto 24)) then -- Reset counter - v.hdrCnt := 0; + v.endOfLine := '0'; + v.hdrCnt := 0; + v.hdrValid := '0'; -- Set the flag v.dbg.errDet := '1'; @@ -233,7 +252,8 @@ begin elsif (r.hdrCnt = 25) then -- Reset counter - v.hdrCnt := 0; + v.hdrCnt := 0; + v.hdrValid := '1'; -- Forward the image header v.hdrMaster.tValid := '1'; @@ -257,14 +277,11 @@ begin -- Write the data v.dataMasters(0).tValid := '1'; - -- Accept the data - -- Don't send TREADY if we have the marker in the - -- current transaction - if (v.dCnt+NUM_LANES_G > r.hdr.dsizeL(RX_FSM_CNT_WIDTH_G-1 downto 0)) then - v.rxSlave.tReady := '0'; - else - v.rxSlave.tReady := '1'; - end if; + -- Accept the data unless a later valid word in this same beat + -- must be reparsed as the next marker/type sequence. + v.rxSlave.tReady := '1'; + more := '0'; + idx := 0; -- Loop the number of 32-bit words for i in 0 to NUM_LANES_G-1 loop @@ -284,12 +301,22 @@ begin -- Set the "end of line" flag v.endOfLine := '1'; + -- Hold the current beat only when additional valid + -- words remain after the line tail. + for j in i+1 to NUM_LANES_G-1 loop + if (rxMaster.tKeep(4*j) = '1') and (more = '0') then + more := '1'; + idx := j; + end if; + end loop; + -- Next State v.state := IDLE_S; - - -- Starting point for next cycle IDLE state - if (i /= NUM_LANES_G-1) then - v.wrd := i+1; + if (more = '1') then + v.rxSlave.tReady := '0'; + v.wrd := idx; + else + v.wrd := 0; end if; end if; @@ -480,7 +507,7 @@ begin NUM_LANES_G => NUM_LANES_G) port map ( rxClk => rxClk, - rxRst => rxFsmRst, + rxRst => packRst, sAxisMaster => r.dataMasters(1), mAxisMaster => dataMaster); From 02fccbc313a7976975c8f1e70fc551f68ba48efc Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 23 Apr 2026 14:32:25 -0700 Subject: [PATCH 48/92] Remove planning docs. --- docs/_meta/rtl_instantiation_graph.json | 14578 ------------------- docs/_meta/rtl_instantiation_graph.md | 270 - docs/_meta/rtl_phase1_queue.json | 5874 -------- docs/_meta/rtl_phase1_queue.md | 272 - docs/_meta/rtl_phase1_queue_overrides.json | 85 - docs/_meta/rtl_regression_handoff.md | 225 - docs/_meta/rtl_regression_inventory.yaml | 700 - docs/_meta/rtl_regression_plan.md | 157 - docs/_meta/rtl_regression_progress.md | 329 - 9 files changed, 22490 deletions(-) delete mode 100644 docs/_meta/rtl_instantiation_graph.json delete mode 100644 docs/_meta/rtl_instantiation_graph.md delete mode 100644 docs/_meta/rtl_phase1_queue.json delete mode 100644 docs/_meta/rtl_phase1_queue.md delete mode 100644 docs/_meta/rtl_phase1_queue_overrides.json delete mode 100644 docs/_meta/rtl_regression_handoff.md delete mode 100644 docs/_meta/rtl_regression_inventory.yaml delete mode 100644 docs/_meta/rtl_regression_plan.md delete mode 100644 docs/_meta/rtl_regression_progress.md diff --git a/docs/_meta/rtl_instantiation_graph.json b/docs/_meta/rtl_instantiation_graph.json deleted file mode 100644 index cac3414382..0000000000 --- a/docs/_meta/rtl_instantiation_graph.json +++ /dev/null @@ -1,14578 +0,0 @@ -{ - "generated_from": { - "scan_dirs": [ - "base", - "axi", - "dsp", - "protocols", - "ethernet", - "devices", - "xilinx" - ], - "parser_scope": "VHDL entities outside tb/build/.venv paths", - "parser_limitations": [ - "Package calls are not graph nodes.", - "Direct entity instantiations are handled explicitly.", - "Component-style instantiations are inferred only when the instantiated name matches a known entity name inside an architecture body." - ] - }, - "summary": { - "entity_count": 795, - "edge_count": 1584, - "duplicate_entity_names": { - "Ad9249Deserializer": [ - "devices/AnalogDevices/ad9249/7Series/rtl/Ad9249Deserializer.vhd", - "devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd" - ], - "Ad9249ReadoutGroup": [ - "devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd", - "devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd" - ], - "ClinkDataClk": [ - "protocols/clink/7Series/ClinkDataClk.vhd", - "protocols/clink/UltraScale/ClinkDataClk.vhd" - ], - "ClinkDataShift": [ - "protocols/clink/7Series/ClinkDataShift.vhd", - "protocols/clink/UltraScale/ClinkDataShift.vhd" - ], - "ClkOutBufDiff": [ - "xilinx/dummy/ClkOutBufDiffDummy.vhd", - "xilinx/general/rtl/ClkOutBufDiff.vhd" - ], - "ClkOutBufSingle": [ - "xilinx/dummy/ClkOutBufSingleDummy.vhd", - "xilinx/general/rtl/ClkOutBufSingle.vhd" - ], - "ClockManagerUltraScale": [ - "xilinx/UltraScale/clocking/rtl/ClockManagerUltraScale.vhd", - "xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd" - ], - "CoaXPressOverFiberGthUsIpWrapper": [ - "protocols/coaxpress/gthUs/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd", - "protocols/coaxpress/gthUs+/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd" - ], - "CoaxpressOverFiberGthUs": [ - "protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUs.vhd", - "protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUs.vhd" - ], - "CoaxpressOverFiberGthUsQpll": [ - "protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUsQpll.vhd", - "protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUsQpll.vhd" - ], - "DS2411Core": [ - "devices/Maxim/dummy/DS2411CoreDummy.vhd", - "devices/Maxim/rtl/DS2411Core.vhd" - ], - "DeviceDna": [ - "xilinx/dummy/DeviceDnaDummy.vhd", - "xilinx/general/rtl/DeviceDna.vhd" - ], - "FifoAlteraMf": [ - "base/fifo/rtl/altera/FifoAlteraMf.vhd", - "base/fifo/rtl/dummy/FifoAlteraMfDummy.vhd" - ], - "FifoXpm": [ - "base/fifo/rtl/dummy/FifoXpmDummy.vhd", - "base/fifo/rtl/xilinx/FifoXpm.vhd" - ], - "GigEthGthUltraScale": [ - "ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd", - "ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd" - ], - "GigEthGthUltraScaleWrapper": [ - "ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd", - "ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd" - ], - "GthUltraScaleQuadPll": [ - "xilinx/UltraScale/gthUs/rtl/GthUltraScaleQuadPll.vhd", - "xilinx/UltraScale+/gthUs+/rtl/GthUltraScaleQuadPll.vhd" - ], - "Idelaye3Wrapper": [ - "xilinx/7Series/dummy/Idelaye3WrapperDummy.vhd", - "xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd" - ], - "InputBufferReg": [ - "xilinx/7Series/general/rtl/InputBufferReg.vhd", - "xilinx/UltraScale/general/rtl/InputBufferReg.vhd" - ], - "IoBufWrapper": [ - "xilinx/dummy/IoBufWrapperDummy.vhd", - "xilinx/general/rtl/IoBufWrapper.vhd" - ], - "Iprog": [ - "xilinx/dummy/IprogDummy.vhd", - "xilinx/general/rtl/Iprog.vhd" - ], - "MicroblazeBasicCoreWrapper": [ - "xilinx/general/microblaze/bypass/MicroblazeBasicCoreWrapper.vhd", - "xilinx/general/microblaze/generate/MicroblazeBasicCoreWrapper.vhd" - ], - "Odelaye3Wrapper": [ - "xilinx/7Series/dummy/Odelaye3WrapperDummy.vhd", - "xilinx/UltraScale/general/rtl/Odelaye3Wrapper.vhd" - ], - "OutputBufferReg": [ - "xilinx/7Series/general/rtl/OutputBufferReg.vhd", - "xilinx/UltraScale/general/rtl/OutputBufferReg.vhd", - "xilinx/dummy/OutputBufferRegDummy.vhd" - ], - "Pgp2bGthUltra": [ - "protocols/pgp/pgp2b/gthUltraScale/rtl/Pgp2bGthUltra.vhd", - "protocols/pgp/pgp2b/gthUltraScale+/rtl/Pgp2bGthUltra.vhd" - ], - "Pgp3GthUs": [ - "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUs.vhd", - "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUs.vhd" - ], - "Pgp3GthUsIpWrapper": [ - "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd", - "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsIpWrapper.vhd" - ], - "Pgp3GthUsQpll": [ - "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd", - "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsQpll.vhd" - ], - "Pgp3GthUsWrapper": [ - "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsWrapper.vhd", - "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsWrapper.vhd" - ], - "Pgp4GthUs": [ - "protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUs.vhd", - "protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUs.vhd" - ], - "Pgp4GthUsWrapper": [ - "protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUsWrapper.vhd", - "protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUsWrapper.vhd" - ], - "PgpGthCoreWrapper": [ - "protocols/pgp/pgp2b/gthUltraScale/rtl/PgpGthCoreWrapper.vhd", - "protocols/pgp/pgp2b/gthUltraScale+/rtl/PgpGthCoreWrapper.vhd" - ], - "RogueSideBand": [ - "axi/simlink/ghdl/RogueSideBand.vhd", - "axi/simlink/sim/RogueSideBand.vhd" - ], - "RogueTcpMemory": [ - "axi/simlink/ghdl/RogueTcpMemory.vhd", - "axi/simlink/sim/RogueTcpMemory.vhd" - ], - "RogueTcpStream": [ - "axi/simlink/ghdl/RogueTcpStream.vhd", - "axi/simlink/sim/RogueTcpStream.vhd" - ], - "SaltRxDeser": [ - "protocols/salt/rtl/7Series/SaltRxDeser.vhd", - "protocols/salt/rtl/UltraScale/SaltRxDeser.vhd" - ], - "SaltTxSer": [ - "protocols/salt/rtl/7Series/SaltTxSer.vhd", - "protocols/salt/rtl/UltraScale/SaltTxSer.vhd" - ], - "SimpleDualPortRamXpm": [ - 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"ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleClk.vhd" - ], - "TenGigEthGthUltraScaleRst": [ - "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleRst.vhd", - "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleRst.vhd" - ], - "TenGigEthGthUltraScaleWrapper": [ - "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd", - "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd" - ], - "TrueDualPortRamXpm": [ - "base/ram/dummy/TrueDualPortRamXpmDummy.vhd", - "base/ram/xilinx/TrueDualPortRamXpm.vhd" - ], - "UdpDebugBridge": [ - "xilinx/xvc-udp/dcp/7Series/Impl/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/7Series/Stub/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/UltraScale/Impl/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/UltraScale/Stub/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd", - "xilinx/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd" - ], - "UdpDebugBridgeWrapper": [ - "xilinx/xvc-udp/dcp/core/UdpDebugBridgeWrapper.vhd", - "xilinx/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd" - ], - "XauiGthUltraScale": [ - "ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd", - "ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd" - ], - "XauiGthUltraScaleWrapper": [ - "ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd", - "ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd" - ] - }, - "top_instantiated_entities": [ - { - "entity": "RstSync", - "instantiated_by_count": 75, - "instantiates_count": 1, - "path": "base/sync/rtl/RstSync.vhd" - }, - { - "entity": "Synchronizer", - "instantiated_by_count": 73, - "instantiates_count": 0, - "path": "base/sync/rtl/Synchronizer.vhd" - }, - { - "entity": "AxiStreamFifoV2", - "instantiated_by_count": 41, - "instantiates_count": 5, - "path": "axi/axi-stream/rtl/AxiStreamFifoV2.vhd" - }, - { - "entity": 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"ethernet/UdpEngine/rtl/UdpEngine.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "ArpIpTable", - "AxiStreamMux", - "UdpEngineArp", - "UdpEngineDhcp", - "UdpEngineRx", - "UdpEngineTx" - ], - "instantiated_by": [ - "UdpEngineWrapper" - ], - "instantiates_count": 6, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "UdpEngineArp", - "paths": [ - "ethernet/UdpEngine/rtl/UdpEngineArp.vhd" - ], - "subsystem": "ethernet", - "instantiates": [], - "instantiated_by": [ - "UdpEngine" - ], - "instantiates_count": 0, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "UdpEngineDhcp", - "paths": [ - "ethernet/UdpEngine/rtl/UdpEngineDhcp.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "AxiStreamFifoV2" - ], - "instantiated_by": [ - "UdpEngine" - ], - "instantiates_count": 1, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "UdpEngineRx", - "paths": [ - "ethernet/UdpEngine/rtl/UdpEngineRx.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "AxiStreamDeMux", - "AxiStreamPipeline" - ], - "instantiated_by": [ - "UdpEngine" - ], - "instantiates_count": 2, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "UdpEngineTx", - "paths": [ - "ethernet/UdpEngine/rtl/UdpEngineTx.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "AxiStreamPipeline" - ], - "instantiated_by": [ - "UdpEngine" - ], - "instantiates_count": 1, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "UdpEngineWrapper", - "paths": [ - "ethernet/UdpEngine/rtl/UdpEngineWrapper.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "IpV4Engine", - "UdpEngine" - ], - "instantiated_by": [], - "instantiates_count": 2, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "WatchDogRst", - "paths": [ - "base/general/rtl/WatchDogRst.vhd" - ], - "subsystem": "base", - "instantiates": [ - "Synchronizer" - ], - "instantiated_by": [ - "GigEthReg", - "XauiGthUltraScaleWrapper", - "XauiGtyUltraScaleWrapper" - ], - "instantiates_count": 1, - "instantiated_by_count": 3, - "topological_layer": 3 - }, - { - "entity": "XadcSimpleCore", - "paths": [ - "xilinx/7Series/xadc/rtl/XadcSimpleCore.vhd" - ], - "subsystem": "xilinx", - "instantiates": [ - "AxiLiteToDrp" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "XauiGth7", - "paths": [ - "ethernet/XauiCore/gth7/rtl/XauiGth7.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "EthMacTop", - "RstSync", - "XauiGth7Core", - "XauiReg" - ], - "instantiated_by": [ - "XauiGth7Wrapper" - ], - "instantiates_count": 4, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "XauiGth7Core", - "paths": [ - "ethernet/XauiCore/gth7/rtl/XauiGth7Core.vhd" - ], - "subsystem": "ethernet", - "instantiates": [], - "instantiated_by": [ - "XauiGth7" - ], - "instantiates_count": 0, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "XauiGth7Wrapper", - "paths": [ - "ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "XauiGth7" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "XauiGthUltraScale", - "paths": [ - "ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd", - "ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "EthMacTop", - "RstSync", - "XauiReg" - ], - "instantiated_by": [ - "XauiGthUltraScaleWrapper" - ], - "instantiates_count": 3, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "XauiGthUltraScaleWrapper", - "paths": [ - "ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd", - "ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "PwrUpRst", - "WatchDogRst", - "XauiGthUltraScale" - ], - "instantiated_by": [], - "instantiates_count": 3, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "XauiGtx7", - "paths": [ - "ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "EthMacTop", - "RstSync", - "XauiGtx7Core", - "XauiReg" - ], - "instantiated_by": [ - "XauiGtx7Wrapper" - ], - "instantiates_count": 4, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "XauiGtx7Core", - "paths": [ - "ethernet/XauiCore/gtx7/rtl/XauiGtx7Core.vhd" - ], - "subsystem": "ethernet", - "instantiates": [], - "instantiated_by": [ - "XauiGtx7" - ], - "instantiates_count": 0, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "XauiGtx7Wrapper", - "paths": [ - "ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "XauiGtx7" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "XauiGtyUltraScale", - "paths": [ - "ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "EthMacTop", - "RstSync", - "XauiReg" - ], - "instantiated_by": [ - "XauiGtyUltraScaleWrapper" - ], - "instantiates_count": 3, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "XauiGtyUltraScaleWrapper", - "paths": [ - "ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "PwrUpRst", - "WatchDogRst", - "XauiGtyUltraScale" - ], - "instantiated_by": [], - "instantiates_count": 3, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "XauiReg", - "paths": [ - "ethernet/XauiCore/core/rtl/XauiReg.vhd" - ], - "subsystem": "ethernet", - "instantiates": [ - "SyncStatusVector", - "SynchronizerFifo", - "SynchronizerVector" - ], - "instantiated_by": [ - "XauiGth7", - "XauiGthUltraScale", - "XauiGtx7", - "XauiGtyUltraScale" - ], - "instantiates_count": 3, - "instantiated_by_count": 4, - "topological_layer": 2 - }, - { - "entity": "adc32rf45", - "paths": [ - "devices/Ti/adc32rf45/rtl/adc32rf45.vhd" - ], - "subsystem": "devices", - "instantiates": [ - "SpiMaster" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "add3", - "paths": [ - "dsp/xilinx/fixed/Add3.vhd" - ], - "subsystem": "dsp", - "instantiates": [ - "csa3" - ], - "instantiated_by": [ - "FirAverage", - "IirSimple" - ], - "instantiates_count": 1, - "instantiated_by_count": 2, - "topological_layer": 1 - }, - { - "entity": "ads54j60", - "paths": [ - "devices/Ti/ads54j60/rtl/ads54j60.vhd" - ], - "subsystem": "devices", - "instantiates": [ - "SpiMaster" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "cfixedDelay", - "paths": [ - "dsp/xilinx/fixed/CfixedDelay.vhd" - ], - "subsystem": "dsp", - "instantiates": [ - "SlvFixedDelay" - ], - "instantiated_by": [ - "SinCosTaylor" - ], - "instantiates_count": 1, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "cfixedMult", - "paths": [ - "dsp/xilinx/fixed/CfixedMult.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [], - "instantiates_count": 0, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "cfixedMultAdd", - "paths": [ - "dsp/xilinx/fixed/CfixedMultAdd.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [], - "instantiates_count": 0, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "csa3", - "paths": [ - "dsp/xilinx/fixed/Csa3.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [ - "add3" - ], - "instantiates_count": 0, - "instantiated_by_count": 1, - "topological_layer": 2 - }, - { - "entity": "i2c2ahb", - "paths": [ - "protocols/i2c/rtl/orig/i2c2ahb.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "i2c2ahbx" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "i2c2ahb_apb", - "paths": [ - "protocols/i2c/rtl/orig/i2c2ahb_apb.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "i2c2ahbx" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "i2c2ahbx", - "paths": [ - "protocols/i2c/rtl/orig/i2c2ahbx.vhd" - ], - "subsystem": "protocols", - "instantiates": [], - "instantiated_by": [ - "i2c2ahb", - "i2c2ahb_apb" - ], - "instantiates_count": 0, - "instantiated_by_count": 2, - "topological_layer": 1 - }, - { - "entity": "i2c_master_bit_ctrl", - "paths": [ - "protocols/i2c/rtl/i2c_master_bit_ctrl.vhd" - ], - "subsystem": "protocols", - "instantiates": [], - "instantiated_by": [ - "i2c_master_byte_ctrl" - ], - "instantiates_count": 0, - "instantiated_by_count": 1, - "topological_layer": 6 - }, - { - "entity": "i2c_master_byte_ctrl", - "paths": [ - "protocols/i2c/rtl/i2c_master_byte_ctrl.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "i2c_master_bit_ctrl" - ], - "instantiated_by": [ - "I2cMaster", - "i2cmst" - ], - "instantiates_count": 1, - "instantiated_by_count": 2, - "topological_layer": 5 - }, - { - "entity": "i2cmst", - "paths": [ - "protocols/i2c/rtl/orig/i2cmst.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "i2c_master_byte_ctrl" - ], - "instantiated_by": [ - "i2cmst_gen" - ], - "instantiates_count": 1, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "i2cmst_gen", - "paths": [ - "protocols/i2c/rtl/orig/i2cmst_gen.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "i2cmst" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "i2cslv", - "paths": [ - "protocols/i2c/rtl/orig/i2cslv.vhd" - ], - "subsystem": "protocols", - "instantiates": [], - "instantiated_by": [], - "instantiates_count": 0, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "iq16bTo32b", - "paths": [ - "protocols/jesd204b/rtl/iq16bTo32b.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "Fifo" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "iq32bTo16b", - "paths": [ - "protocols/jesd204b/rtl/iq32bTo16b.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "Fifo" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "sfixedDelay", - "paths": [ - "dsp/xilinx/fixed/SfixedDelay.vhd" - ], - "subsystem": "dsp", - "instantiates": [ - "SlvFixedDelay" - ], - "instantiated_by": [ - "FirAverage", - "IirSimple" - ], - "instantiates_count": 1, - "instantiated_by_count": 2, - "topological_layer": 1 - }, - { - "entity": "sfixedMult", - "paths": [ - "dsp/xilinx/fixed/SfixedMult.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [ - "SinCosTaylor" - ], - "instantiates_count": 0, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "sfixedMultAdd", - "paths": [ - "dsp/xilinx/fixed/SfixedMultAdd.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [], - "instantiates_count": 0, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "sfixedPreAddMultAdd", - "paths": [ - "dsp/xilinx/fixed/SfixedPreAddMultAdd.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [], - "instantiates_count": 0, - "instantiated_by_count": 0, - "topological_layer": 0 - } - ] -} diff --git a/docs/_meta/rtl_instantiation_graph.md b/docs/_meta/rtl_instantiation_graph.md deleted file mode 100644 index 33b4e08d81..0000000000 --- a/docs/_meta/rtl_instantiation_graph.md +++ /dev/null @@ -1,270 +0,0 @@ -# SURF RTL Instantiation Graph - -## Scope -- Scan dirs: `base, axi, dsp, protocols, ethernet, devices, xilinx` -- Included files: VHDL files outside `tb/`, `build/`, and `.venv/` paths. -- Direct entity instantiations are parsed explicitly. -- Component-style instantiations are included only when the instantiated token matches a known entity name inside an architecture body. -- Packages are not graph nodes. - -## Summary -- Entities: `795` -- Edges: `1584` -- Topological layers: `12` -- Duplicate entity names: `51` - -## Top Instantiated Entities -| entity | instantiated_by_count | instantiates_count | path | -| --- | --- | --- | --- | -| RstSync | 75 | 1 | base/sync/rtl/RstSync.vhd | -| Synchronizer | 73 | 0 | base/sync/rtl/Synchronizer.vhd | -| AxiStreamFifoV2 | 41 | 5 | axi/axi-stream/rtl/AxiStreamFifoV2.vhd | -| SynchronizerVector | 41 | 0 | base/sync/rtl/SynchronizerVector.vhd | -| AxiStreamPipeline | 38 | 0 | axi/axi-stream/rtl/AxiStreamPipeline.vhd | -| MasterAxiStreamIpIntegrator | 37 | 1 | axi/axi-stream/ip_integrator/MasterAxiStreamIpIntegrator.vhd | -| SlaveAxiLiteIpIntegrator | 37 | 1 | axi/axi-lite/ip_integrator/SlaveAxiLiteIpIntegrator.vhd | -| SlaveAxiStreamIpIntegrator | 37 | 1 | axi/axi-stream/ip_integrator/SlaveAxiStreamIpIntegrator.vhd | -| SynchronizerFifo | 37 | 1 | base/sync/rtl/SynchronizerFifo.vhd | -| PwrUpRst | 36 | 1 | base/general/rtl/PwrUpRst.vhd | -| AxiLiteCrossbar | 32 | 0 | axi/axi-lite/rtl/AxiLiteCrossbar.vhd | -| AxiLiteToDrp | 28 | 1 | axi/bridge/rtl/AxiLiteToDrp.vhd | -| SynchronizerOneShot | 28 | 2 | base/sync/rtl/SynchronizerOneShot.vhd | -| AxiLiteAsync | 23 | 1 | axi/axi-lite/rtl/AxiLiteAsync.vhd | -| Fifo | 18 | 4 | base/fifo/rtl/Fifo.vhd | -| MasterAxiIpIntegrator | 16 | 1 | axi/axi4/ip_integrator/MasterAxiIpIntegrator.vhd | -| SyncStatusVector | 16 | 2 | base/sync/rtl/SyncStatusVector.vhd | -| SynchronizerEdge | 16 | 1 | base/sync/rtl/SynchronizerEdge.vhd | -| RstPipeline | 15 | 0 | base/general/rtl/RstPipeline.vhd | -| AxiLiteMaster | 14 | 0 | axi/axi-lite/rtl/AxiLiteMaster.vhd | - -## Top Assemblers -| entity | instantiates_count | instantiated_by_count | path | -| --- | --- | --- | --- | -| RssiCore | 13 | 1 | protocols/rssi/v1/rtl/RssiCore.vhd | -| EthMacRxRoCEv2 | 10 | 1 | ethernet/RoCEv2/rtl/EthMacRxRoCEv2.vhd | -| SugoiManagerCore | 10 | 0 | protocols/sugoi/rtl/SugoiManagerCore.vhd | -| Ad9681Readout | 8 | 0 | devices/AnalogDevices/ad9681/7Series/rtl/Ad9681Readout.vhd | -| CoaXPressAxiL | 8 | 1 | protocols/coaxpress/core/rtl/CoaXPressAxiL.vhd | -| EthMacTxRoCEv2 | 8 | 1 | ethernet/RoCEv2/rtl/EthMacTxRoCEv2.vhd | -| Gth7Core | 8 | 2 | xilinx/7Series/gth7/rtl/Gth7Core.vhd | -| RssiCoreWrapper | 8 | 0 | protocols/rssi/v1/rtl/RssiCoreWrapper.vhd | -| Ad9249ReadoutGroup | 7 | 0 | devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd | -| Ad9249ReadoutGroup2 | 7 | 0 | devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd | -| AxiRingBuffer | 7 | 1 | axi/axi4/rtl/AxiRingBuffer.vhd | -| AxiStreamRingBuffer | 7 | 1 | axi/axi-stream/rtl/AxiStreamRingBuffer.vhd | -| ClinkTop | 7 | 0 | protocols/clink/rtl/ClinkTop.vhd | -| CoaXPressRx | 7 | 1 | protocols/coaxpress/core/rtl/CoaXPressRx.vhd | -| FifoAsync | 7 | 8 | base/fifo/rtl/inferred/FifoAsync.vhd | -| GLinkGtx7Core | 7 | 1 | protocols/glink/gtx7/rtl/GLinkGtx7Core.vhd | -| Gtp7Core | 7 | 4 | xilinx/7Series/gtp7/rtl/Gtp7Core.vhd | -| IpV4Engine | 7 | 1 | ethernet/IpV4Engine/rtl/IpV4Engine.vhd | -| Jesd204bRx | 7 | 1 | protocols/jesd204b/rtl/Jesd204bRx.vhd | -| Jesd204bTx | 7 | 1 | protocols/jesd204b/rtl/Jesd204bTx.vhd | - -## Top Leaf Entities -| entity | instantiated_by_count | path | -| --- | --- | --- | -| Synchronizer | 73 | base/sync/rtl/Synchronizer.vhd | -| SynchronizerVector | 41 | base/sync/rtl/SynchronizerVector.vhd | -| AxiStreamPipeline | 38 | axi/axi-stream/rtl/AxiStreamPipeline.vhd | -| AxiLiteCrossbar | 32 | axi/axi-lite/rtl/AxiLiteCrossbar.vhd | -| RstPipeline | 15 | base/general/rtl/RstPipeline.vhd | -| AxiLiteMaster | 14 | axi/axi-lite/rtl/AxiLiteMaster.vhd | -| IoBufWrapper | 14 | xilinx/dummy/IoBufWrapperDummy.vhd | -| Decoder8b10b | 10 | protocols/line-codes/rtl/Decoder8b10b.vhd | -| SimpleDualPortRam | 10 | base/ram/inferred/SimpleDualPortRam.vhd | -| FifoOutputPipeline | 9 | base/fifo/rtl/FifoOutputPipeline.vhd | -| Crc32Parallel | 7 | base/crc/rtl/Crc32Parallel.vhd | -| SimpleDualPortRamXpm | 7 | base/ram/dummy/SimpleDualPortRamXpmDummy.vhd | -| SpiMaster | 7 | protocols/spi/rtl/SpiMaster.vhd | -| Gearbox | 6 | base/general/rtl/Gearbox.vhd | -| SelectIoRxGearboxAligner | 6 | xilinx/general/rtl/SelectIoRxGearboxAligner.vhd | -| ClkOutBufDiff | 5 | xilinx/dummy/ClkOutBufDiffDummy.vhd | -| Pgp3RxGearboxAligner | 5 | protocols/pgp/pgp3/core/rtl/Pgp3RxGearboxAligner.vhd | -| Scrambler | 5 | base/general/rtl/Scrambler.vhd | -| AxiStreamFlush | 4 | axi/axi-stream/rtl/AxiStreamFlush.vhd | -| CRC32Rtl | 4 | base/crc/rtl/CRC32Rtl.vhd | - -## Base Bottom-Up Candidates -| entity | instantiated_by_count | instantiates_count | path | -| --- | --- | --- | --- | -| Synchronizer | 73 | 0 | base/sync/rtl/Synchronizer.vhd | -| SynchronizerVector | 41 | 0 | base/sync/rtl/SynchronizerVector.vhd | -| RstPipeline | 15 | 0 | base/general/rtl/RstPipeline.vhd | -| SimpleDualPortRam | 10 | 0 | base/ram/inferred/SimpleDualPortRam.vhd | -| FifoOutputPipeline | 9 | 0 | base/fifo/rtl/FifoOutputPipeline.vhd | -| Crc32Parallel | 7 | 0 | base/crc/rtl/Crc32Parallel.vhd | -| SimpleDualPortRamXpm | 7 | 0 | base/ram/dummy/SimpleDualPortRamXpmDummy.vhd | -| Gearbox | 6 | 0 | base/general/rtl/Gearbox.vhd | -| Scrambler | 5 | 0 | base/general/rtl/Scrambler.vhd | -| CRC32Rtl | 4 | 0 | base/crc/rtl/CRC32Rtl.vhd | -| Crc32 | 3 | 0 | base/crc/rtl/Crc32.vhd | -| SimpleDualPortRamAlteraMf | 3 | 0 | base/ram/dummy/SimpleDualPortRamAlteraMfDummy.vhd | -| SlvDelay | 3 | 0 | base/delay/rtl/SlvDelay.vhd | -| TrueDualPortRam | 3 | 0 | base/ram/inferred/TrueDualPortRam.vhd | -| FifoRdFsm | 2 | 0 | base/fifo/rtl/inferred/FifoRdFsm.vhd | -| FifoWrFsm | 2 | 0 | base/fifo/rtl/inferred/FifoWrFsm.vhd | -| LutRam | 2 | 0 | base/ram/inferred/LutRam.vhd | -| TrueDualPortRamAlteraMf | 2 | 0 | base/ram/dummy/TrueDualPortRamXpmAlteraMfDummy.vhd | -| TrueDualPortRamXpm | 2 | 0 | base/ram/dummy/TrueDualPortRamXpmDummy.vhd | -| Arbiter | 1 | 0 | base/general/rtl/Arbiter.vhd | - -## Duplicate Entity Names -- `Ad9249Deserializer` - - `devices/AnalogDevices/ad9249/7Series/rtl/Ad9249Deserializer.vhd` - - `devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd` -- `Ad9249ReadoutGroup` - - `devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd` - - `devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd` -- `ClinkDataClk` - - `protocols/clink/7Series/ClinkDataClk.vhd` - - `protocols/clink/UltraScale/ClinkDataClk.vhd` -- `ClinkDataShift` - - `protocols/clink/7Series/ClinkDataShift.vhd` - - `protocols/clink/UltraScale/ClinkDataShift.vhd` -- `ClkOutBufDiff` - - `xilinx/dummy/ClkOutBufDiffDummy.vhd` - - `xilinx/general/rtl/ClkOutBufDiff.vhd` -- `ClkOutBufSingle` - - `xilinx/dummy/ClkOutBufSingleDummy.vhd` - - `xilinx/general/rtl/ClkOutBufSingle.vhd` -- `ClockManagerUltraScale` - - `xilinx/UltraScale/clocking/rtl/ClockManagerUltraScale.vhd` - - `xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd` -- `CoaXPressOverFiberGthUsIpWrapper` - - `protocols/coaxpress/gthUs/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd` - - `protocols/coaxpress/gthUs+/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd` -- `CoaxpressOverFiberGthUs` - - `protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUs.vhd` - - `protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUs.vhd` -- `CoaxpressOverFiberGthUsQpll` - - `protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUsQpll.vhd` - - `protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUsQpll.vhd` -- `DS2411Core` - - `devices/Maxim/dummy/DS2411CoreDummy.vhd` - - `devices/Maxim/rtl/DS2411Core.vhd` -- `DeviceDna` - - `xilinx/dummy/DeviceDnaDummy.vhd` - - `xilinx/general/rtl/DeviceDna.vhd` -- `FifoAlteraMf` - - `base/fifo/rtl/altera/FifoAlteraMf.vhd` - - `base/fifo/rtl/dummy/FifoAlteraMfDummy.vhd` -- `FifoXpm` - - `base/fifo/rtl/dummy/FifoXpmDummy.vhd` - - `base/fifo/rtl/xilinx/FifoXpm.vhd` -- `GigEthGthUltraScale` - - `ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd` - - `ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd` -- `GigEthGthUltraScaleWrapper` - - `ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd` - - `ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd` -- `GthUltraScaleQuadPll` - - `xilinx/UltraScale/gthUs/rtl/GthUltraScaleQuadPll.vhd` - - `xilinx/UltraScale+/gthUs+/rtl/GthUltraScaleQuadPll.vhd` -- `Idelaye3Wrapper` - - `xilinx/7Series/dummy/Idelaye3WrapperDummy.vhd` - - `xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd` -- `InputBufferReg` - - `xilinx/7Series/general/rtl/InputBufferReg.vhd` - - `xilinx/UltraScale/general/rtl/InputBufferReg.vhd` -- `IoBufWrapper` - - `xilinx/dummy/IoBufWrapperDummy.vhd` - - `xilinx/general/rtl/IoBufWrapper.vhd` -- `Iprog` - - `xilinx/dummy/IprogDummy.vhd` - - `xilinx/general/rtl/Iprog.vhd` -- `MicroblazeBasicCoreWrapper` - - `xilinx/general/microblaze/bypass/MicroblazeBasicCoreWrapper.vhd` - - `xilinx/general/microblaze/generate/MicroblazeBasicCoreWrapper.vhd` -- `Odelaye3Wrapper` - - `xilinx/7Series/dummy/Odelaye3WrapperDummy.vhd` - - `xilinx/UltraScale/general/rtl/Odelaye3Wrapper.vhd` -- `OutputBufferReg` - - `xilinx/7Series/general/rtl/OutputBufferReg.vhd` - - `xilinx/UltraScale/general/rtl/OutputBufferReg.vhd` - - `xilinx/dummy/OutputBufferRegDummy.vhd` -- `Pgp2bGthUltra` - - `protocols/pgp/pgp2b/gthUltraScale/rtl/Pgp2bGthUltra.vhd` - - `protocols/pgp/pgp2b/gthUltraScale+/rtl/Pgp2bGthUltra.vhd` -- `Pgp3GthUs` - - `protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUs.vhd` - - `protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUs.vhd` -- `Pgp3GthUsIpWrapper` - - `protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd` - - `protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsIpWrapper.vhd` -- `Pgp3GthUsQpll` - - `protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd` - - `protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsQpll.vhd` -- `Pgp3GthUsWrapper` - - `protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsWrapper.vhd` - - `protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsWrapper.vhd` -- `Pgp4GthUs` - - `protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUs.vhd` - - `protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUs.vhd` -- `Pgp4GthUsWrapper` - - `protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUsWrapper.vhd` - - `protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUsWrapper.vhd` -- `PgpGthCoreWrapper` - - `protocols/pgp/pgp2b/gthUltraScale/rtl/PgpGthCoreWrapper.vhd` - - `protocols/pgp/pgp2b/gthUltraScale+/rtl/PgpGthCoreWrapper.vhd` -- `RogueSideBand` - - `axi/simlink/ghdl/RogueSideBand.vhd` - - `axi/simlink/sim/RogueSideBand.vhd` -- `RogueTcpMemory` - - `axi/simlink/ghdl/RogueTcpMemory.vhd` - - `axi/simlink/sim/RogueTcpMemory.vhd` -- `RogueTcpStream` - - `axi/simlink/ghdl/RogueTcpStream.vhd` - - `axi/simlink/sim/RogueTcpStream.vhd` -- `SaltRxDeser` - - `protocols/salt/rtl/7Series/SaltRxDeser.vhd` - - `protocols/salt/rtl/UltraScale/SaltRxDeser.vhd` -- `SaltTxSer` - - `protocols/salt/rtl/7Series/SaltTxSer.vhd` - - `protocols/salt/rtl/UltraScale/SaltTxSer.vhd` -- `SimpleDualPortRamXpm` - - `base/ram/dummy/SimpleDualPortRamXpmDummy.vhd` - - `base/ram/xilinx/SimpleDualPortRamXpm.vhd` -- `SinglePortRamPrimitive` - - `base/ram/dummy/SinglePortRamPrimitiveDummy.vhd` - - `base/ram/xilinx/SinglePortRamPrimitive.vhd` -- `Srl16Delay` - - `xilinx/dummy/Srl16DelayDummy.vhd` - - `xilinx/general/rtl/Srl16Delay.vhd` -- `SugoiManagerRx7Series` - - `protocols/sugoi/rtl/7Series/SugoiManagerRx7Series.vhd` - - `protocols/sugoi/rtl/dummy/SugoiManagerRx7SeriesDummy.vhd` -- `SugoiManagerRxUltrascale` - - `protocols/sugoi/rtl/UltraScale/SugoiManagerRxUltrascale.vhd` - - `protocols/sugoi/rtl/dummy/SugoiManagerRxUltrascaleDummy.vhd` -- `TenGigEthGthUltraScale` - - `ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd` - - `ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd` -- `TenGigEthGthUltraScaleClk` - - `ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleClk.vhd` - - `ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleClk.vhd` -- `TenGigEthGthUltraScaleRst` - - `ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleRst.vhd` - - `ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleRst.vhd` -- `TenGigEthGthUltraScaleWrapper` - - `ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd` - - `ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd` -- `TrueDualPortRamXpm` - - `base/ram/dummy/TrueDualPortRamXpmDummy.vhd` - - `base/ram/xilinx/TrueDualPortRamXpm.vhd` -- `UdpDebugBridge` - - `xilinx/xvc-udp/dcp/7Series/Impl/images/UdpDebugBridge_stub.vhd` - - `xilinx/xvc-udp/dcp/7Series/Stub/images/UdpDebugBridge_stub.vhd` - - `xilinx/xvc-udp/dcp/UltraScale/Impl/images/UdpDebugBridge_stub.vhd` - - `xilinx/xvc-udp/dcp/UltraScale/Stub/images/UdpDebugBridge_stub.vhd` - - `xilinx/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd` - - `xilinx/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd` -- `UdpDebugBridgeWrapper` - - `xilinx/xvc-udp/dcp/core/UdpDebugBridgeWrapper.vhd` - - `xilinx/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd` -- `XauiGthUltraScale` - - `ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd` - - `ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd` -- `XauiGthUltraScaleWrapper` - - `ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd` - - `ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd` diff --git a/docs/_meta/rtl_phase1_queue.json b/docs/_meta/rtl_phase1_queue.json deleted file mode 100644 index a77d778b6b..0000000000 --- a/docs/_meta/rtl_phase1_queue.json +++ /dev/null @@ -1,5874 +0,0 @@ -{ - "generated_from": { - "scan_dirs": [ - "base", - "axi", - "dsp", - "protocols", - "ethernet", - "devices", - "xilinx" - ], - "source_graph_script": "scripts/build_rtl_instantiation_graph.py", - "override_file": "docs/_meta/rtl_phase1_queue_overrides.json", - "queue_policy": "Path-qualified, phase-1 filtered, bottom-up instantiation order" - }, - "summary": { - "phase1_module_count": 219, - "phase1_edge_count": 392, - "phase1_bottom_up_layers": 10, - "deferred_module_count": 632, - "unresolved_phase1_edges": 0, - "applied_order_overrides": 0 - }, - "phase1_rules": { - "force_include_entities": [], - "force_include_paths": [], - "deferred_subsystems": [ - { - "name": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "name": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "name": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "name": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - } - ], - "deferred_entities": [ - { - "entity": "LutFixedDelay", - "reason": "Depends on SinglePortRamPrimitive under the current open-source flow." - } - ], - "deferred_paths": [], - "deferred_path_substrings": [ - { - "pattern": "axi/simlink/", - "reason": "Simulation support models are not part of the synthesizable phase-1 queue." - }, - { - "pattern": "/sim/", - "reason": "Simulation-only support modules are not part of the synthesizable phase-1 queue." - }, - { - "pattern": "/dummy/", - "reason": "Dummy-backed variants are deferred from the phase-1 executable queue." - }, - { - "pattern": "/altera/", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "/xilinx/", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "7Series", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "UltraScale", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "UltraScale+", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "/gth", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gtp", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gty", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gtx", - "reason": "GT-family implementation branches are deferred in phase 1." - } - ], - "preferred_paths_by_entity": {}, - "order_overrides": [] - }, - "applied_order_overrides": [], - "queue": [ - { - "order": 1, - "bottom_up_layer": 0, - "entity": "AxiLiteCrossbar", - "path": "axi/axi-lite/rtl/AxiLiteCrossbar.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 3 - }, - { - "order": 2, - "bottom_up_layer": 0, - "entity": "AxiLiteMaster", - "path": "axi/axi-lite/rtl/AxiLiteMaster.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 6 - }, - { - "order": 3, - "bottom_up_layer": 0, - "entity": "AxiLiteRegs", - "path": "axi/axi-lite/rtl/AxiLiteRegs.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 4, - "bottom_up_layer": 0, - "entity": "AxiLiteRespTimer", - "path": "axi/axi-lite/rtl/AxiLiteRespTimer.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 5, - "bottom_up_layer": 0, - "entity": "AxiLiteSlave", - "path": "axi/axi-lite/rtl/AxiLiteSlave.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 6, - "bottom_up_layer": 0, - "entity": "AxiLiteWriteFilter", - "path": "axi/axi-lite/rtl/AxiLiteWriteFilter.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 7, - "bottom_up_layer": 0, - "entity": "AxiVersion", - "path": "axi/axi-lite/rtl/AxiVersion.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 8, - "bottom_up_layer": 0, - "entity": "AxiStreamCombiner", - "path": "axi/axi-stream/rtl/AxiStreamCombiner.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 9, - "bottom_up_layer": 0, - "entity": "AxiStreamFlush", - "path": "axi/axi-stream/rtl/AxiStreamFlush.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 10, - "bottom_up_layer": 0, - "entity": "AxiStreamGearboxPack", - "path": "axi/axi-stream/rtl/AxiStreamGearboxPack.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 11, - "bottom_up_layer": 0, - "entity": "AxiStreamGearboxUnpack", - "path": "axi/axi-stream/rtl/AxiStreamGearboxUnpack.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 12, - "bottom_up_layer": 0, - "entity": "AxiStreamPipeline", - "path": "axi/axi-stream/rtl/AxiStreamPipeline.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 18 - }, - { - "order": 13, - "bottom_up_layer": 0, - "entity": "AxiStreamSplitter", - "path": "axi/axi-stream/rtl/AxiStreamSplitter.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 14, - "bottom_up_layer": 0, - "entity": "AxiStreamPkgWrapper", - "path": "axi/axi-stream/wrappers/AxiStreamPkgWrapper.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 15, - "bottom_up_layer": 0, - "entity": "AxiReadPathMux", - "path": "axi/axi4/rtl/AxiReadPathMux.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 16, - "bottom_up_layer": 0, - "entity": "AxiResize", - "path": "axi/axi4/rtl/AxiResize.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 17, - "bottom_up_layer": 0, - "entity": "AxiWritePathMux", - "path": "axi/axi4/rtl/AxiWritePathMux.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 18, - "bottom_up_layer": 0, - "entity": "AxiToAxiLite", - "path": "axi/bridge/rtl/AxiToAxiLite.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 19, - "bottom_up_layer": 0, - "entity": "AxiStreamDmaV2WriteMux", - "path": "axi/dma/rtl/v2/AxiStreamDmaV2WriteMux.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 20, - "bottom_up_layer": 0, - "entity": "CRC32Rtl", - "path": "base/crc/rtl/CRC32Rtl.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 21, - "bottom_up_layer": 0, - "entity": "Crc32", - "path": "base/crc/rtl/Crc32.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 22, - "bottom_up_layer": 0, - "entity": "Crc32Parallel", - "path": "base/crc/rtl/Crc32Parallel.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 23, - "bottom_up_layer": 0, - "entity": "SlvDelay", - "path": "base/delay/rtl/SlvDelay.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 24, - "bottom_up_layer": 0, - "entity": "SlvDelayRam", - "path": "base/delay/rtl/SlvDelayRam.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 25, - "bottom_up_layer": 0, - "entity": "SlvFixedDelay", - "path": "base/delay/rtl/SlvFixedDelay.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 26, - "bottom_up_layer": 0, - "entity": "FifoOutputPipeline", - "path": "base/fifo/rtl/FifoOutputPipeline.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 7 - }, - { - "order": 27, - "bottom_up_layer": 0, - "entity": "FifoRdFsm", - "path": "base/fifo/rtl/inferred/FifoRdFsm.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 28, - "bottom_up_layer": 0, - "entity": "FifoWrFsm", - "path": "base/fifo/rtl/inferred/FifoWrFsm.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 29, - "bottom_up_layer": 0, - "entity": "MasterRamIpIntegrator", - "path": "base/general/ip_integrator/MasterRamIpIntegrator.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 30, - "bottom_up_layer": 0, - "entity": "SlaveRamIpIntegrator", - "path": "base/general/ip_integrator/SlaveRamIpIntegrator.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 31, - "bottom_up_layer": 0, - "entity": "Arbiter", - "path": "base/general/rtl/Arbiter.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 32, - "bottom_up_layer": 0, - "entity": "ClockDivider", - "path": "base/general/rtl/ClockDivider.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 33, - "bottom_up_layer": 0, - "entity": "Gearbox", - "path": "base/general/rtl/Gearbox.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 34, - "bottom_up_layer": 0, - "entity": "Heartbeat", - "path": "base/general/rtl/Heartbeat.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 35, - "bottom_up_layer": 0, - "entity": "Mux", - "path": "base/general/rtl/Mux.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 36, - "bottom_up_layer": 0, - "entity": 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"axi/axi4/ip_integrator/AxiWritePathFifoIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 188, - "bottom_up_layer": 6, - "entity": "AxiReadEmulate", - "path": "axi/axi4/rtl/AxiReadEmulate.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 189, - "bottom_up_layer": 6, - "entity": "AxiRingBuffer", - "path": "axi/axi4/rtl/AxiRingBuffer.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 6, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 190, - "bottom_up_layer": 6, - "entity": "AxiWriteEmulate", - "path": "axi/axi4/rtl/AxiWriteEmulate.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 191, - "bottom_up_layer": 6, - "entity": "AxiStreamDmaV2IpIntegrator", - "path": "axi/dma/ip_integrator/AxiStreamDmaV2IpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 192, - "bottom_up_layer": 6, - "entity": "AxiStreamDmaRingRead", - "path": "axi/dma/rtl/v1/AxiStreamDmaRingRead.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 5, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 193, - "bottom_up_layer": 6, - "entity": "AxiStreamDmaWrite", - "path": "axi/dma/rtl/v1/AxiStreamDmaWrite.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 4 - }, - { - "order": 194, - "bottom_up_layer": 6, - "entity": "SyncStatusVector", - "path": "base/sync/rtl/SyncStatusVector.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 195, - "bottom_up_layer": 6, - "entity": "SyncTrigRateVector", - "path": "base/sync/rtl/SyncTrigRateVector.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 196, - "bottom_up_layer": 6, - "entity": "SyncTrigRateWrapper", - "path": "base/sync/wrappers/SyncTrigRateWrapper.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 197, - "bottom_up_layer": 6, - "entity": "SynchronizerOneShotCntVectorFlatWrapper", - "path": "base/sync/wrappers/SynchronizerOneShotCntVectorFlatWrapper.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 198, - "bottom_up_layer": 7, - "entity": "AxiLiteRamSyncStatusVector", - "path": "axi/axi-lite/rtl/AxiLiteRamSyncStatusVector.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 199, - "bottom_up_layer": 7, - "entity": "AxiStreamBatchingFifoIpIntegrator", - "path": "axi/axi-stream/ip_integrator/AxiStreamBatchingFifoIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 4, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 200, - "bottom_up_layer": 7, - "entity": "AxiStreamMonIpIntegrator", - "path": "axi/axi-stream/ip_integrator/AxiStreamMonIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 201, - "bottom_up_layer": 7, - "entity": "AxiStreamRingBufferIpIntegrator", - "path": "axi/axi-stream/ip_integrator/AxiStreamRingBufferIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 202, - "bottom_up_layer": 7, - "entity": "AxiStreamMonAxiL", - "path": "axi/axi-stream/rtl/AxiStreamMonAxiL.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 203, - "bottom_up_layer": 7, - "entity": "AxiReadEmulateIpIntegrator", - "path": "axi/axi4/ip_integrator/AxiReadEmulateIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 204, - "bottom_up_layer": 7, - "entity": "AxiRingBufferIpIntegrator", - "path": "axi/axi4/ip_integrator/AxiRingBufferIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 205, - "bottom_up_layer": 7, - "entity": "AxiWriteEmulateIpIntegrator", - "path": "axi/axi4/ip_integrator/AxiWriteEmulateIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 206, - "bottom_up_layer": 7, - "entity": "AxiStreamDmaRingReadIpIntegrator", - "path": "axi/dma/ip_integrator/AxiStreamDmaRingReadIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 5, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 207, - "bottom_up_layer": 7, - "entity": "AxiStreamDmaWriteIpIntegrator", - "path": "axi/dma/ip_integrator/AxiStreamDmaWriteIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 208, - "bottom_up_layer": 7, - "entity": "AxiStreamDma", - "path": "axi/dma/rtl/v1/AxiStreamDma.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 4, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 209, - "bottom_up_layer": 7, - "entity": "AxiStreamDmaFifo", - "path": "axi/dma/rtl/v1/AxiStreamDmaFifo.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 4, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 210, - "bottom_up_layer": 7, - "entity": "AxiStreamDmaRingWrite", - "path": "axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 4, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 211, - "bottom_up_layer": 7, - "entity": "SyncStatusVectorFlatWrapper", - "path": "base/sync/wrappers/SyncStatusVectorFlatWrapper.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 212, - "bottom_up_layer": 7, - "entity": "SyncTrigRateVectorFlatWrapper", - "path": "base/sync/wrappers/SyncTrigRateVectorFlatWrapper.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 213, - "bottom_up_layer": 8, - "entity": "AxiLiteRamSyncStatusVectorIpIntegrator", - "path": "axi/axi-lite/ip_integrator/AxiLiteRamSyncStatusVectorIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 214, - "bottom_up_layer": 8, - "entity": "AxiStreamMonAxiLIpIntegrator", - "path": "axi/axi-stream/ip_integrator/AxiStreamMonAxiLIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 215, - "bottom_up_layer": 8, - "entity": "AxiMonAxiL", - "path": "axi/axi4/rtl/AxiMonAxiL.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 216, - "bottom_up_layer": 8, - "entity": "AxiStreamDmaFifoIpIntegrator", - "path": "axi/dma/ip_integrator/AxiStreamDmaFifoIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 217, - "bottom_up_layer": 8, - "entity": "AxiStreamDmaIpIntegrator", - "path": "axi/dma/ip_integrator/AxiStreamDmaIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 218, - "bottom_up_layer": 8, - "entity": "AxiStreamDmaRingWriteIpIntegrator", - "path": "axi/dma/ip_integrator/AxiStreamDmaRingWriteIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 5, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 219, - "bottom_up_layer": 9, - "entity": "AxiMonAxiLIpIntegrator", - "path": "axi/axi4/ip_integrator/AxiMonAxiLIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - } - ], - "deferred": [ - { - "entity": "RogueSideBand", - "path": "axi/simlink/ghdl/RogueSideBand.vhd", - "subsystem": "axi", - "reason": "Simulation support models are not part of the synthesizable phase-1 queue." - }, - { - "entity": "RogueTcpMemory", - "path": "axi/simlink/ghdl/RogueTcpMemory.vhd", - "subsystem": "axi", - "reason": "Simulation support models are not part of the synthesizable phase-1 queue." - }, - { - "entity": "RogueTcpStream", - "path": "axi/simlink/ghdl/RogueTcpStream.vhd", - "subsystem": "axi", - "reason": "Simulation support models are not part of the synthesizable phase-1 queue." - }, - { - "entity": "RogueSideBand", - "path": "axi/simlink/sim/RogueSideBand.vhd", - "subsystem": "axi", - "reason": "Simulation support models are not part of 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the phase-1 executable queue." - }, - { - "entity": "TrueDualPortRamAlteraMf", - "path": "base/ram/dummy/TrueDualPortRamXpmAlteraMfDummy.vhd", - "subsystem": "base", - "reason": "Dummy-backed variants are deferred from the phase-1 executable queue." - }, - { - "entity": "TrueDualPortRamXpm", - "path": "base/ram/dummy/TrueDualPortRamXpmDummy.vhd", - "subsystem": "base", - "reason": "Dummy-backed variants are deferred from the phase-1 executable queue." - }, - { - "entity": "SimpleDualPortRamXpm", - "path": "base/ram/xilinx/SimpleDualPortRamXpm.vhd", - "subsystem": "base", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "SinglePortRamPrimitive", - "path": "base/ram/xilinx/SinglePortRamPrimitive.vhd", - "subsystem": "base", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "TrueDualPortRamXpm", - "path": "base/ram/xilinx/TrueDualPortRamXpm.vhd", - "subsystem": "base", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "LeapXcvr", - "path": "devices/Amphenol/LeapXcvr/rtl/LeapXcvr.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "LeapXcvrCdrDisable", - "path": "devices/Amphenol/LeapXcvr/rtl/LeapXcvrCdrDisable.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "LeapXcvrCore", - "path": "devices/Amphenol/LeapXcvr/rtl/LeapXcvrCore.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd5541Core", - "path": "devices/AnalogDevices/ad5541/rtl/AxiAd5541Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd5780Core", - "path": "devices/AnalogDevices/ad5780/rtl/AxiAd5780Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd5780Reg", - "path": "devices/AnalogDevices/ad5780/rtl/AxiAd5780Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd5780Ser", - "path": "devices/AnalogDevices/ad5780/rtl/AxiAd5780Ser.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249ConfigNoPullup", - "path": "devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ConfigNoPullup.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249Deserializer", - "path": "devices/AnalogDevices/ad9249/7Series/rtl/Ad9249Deserializer.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249ReadoutGroup", - "path": "devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249Deserializer", - "path": "devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249ReadoutGroup", - "path": "devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249ReadoutGroup2", - "path": "devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249Config", - "path": "devices/AnalogDevices/ad9249/core/Ad9249Config.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "StreamPatternTester", - "path": "devices/AnalogDevices/ad9249/core/StreamPatternTester.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467Core", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467Deser", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467Deser.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467DeserBit", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467DeserBit.vhd", - "subsystem": "devices", - "reason": "Subsystem is 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"devices/AnalogDevices/ad9681/7Series/rtl/Ad9681Deserializer.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681Readout", - "path": "devices/AnalogDevices/ad9681/7Series/rtl/Ad9681Readout.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681ReadoutManual", - "path": "devices/AnalogDevices/ad9681/7Series/rtl/Ad9681ReadoutManual.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681Config", - "path": "devices/AnalogDevices/ad9681/core/Ad9681Config.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681", - "path": "devices/AnalogDevices/ad9681/sim/Ad9681.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681Serializer", - "path": "devices/AnalogDevices/ad9681/sim/Ad9681Serializer.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AdiConfigSlave", - "path": "devices/AnalogDevices/general/rtl/AdiConfigSlave.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiLtc2270Core", - "path": "devices/Linear/lct2270/rtl/AxiLtc2270Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiLtc2270Deser", - "path": "devices/Linear/lct2270/rtl/AxiLtc2270Deser.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiLtc2270DeserBit", - "path": "devices/Linear/lct2270/rtl/AxiLtc2270DeserBit.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiLtc2270Reg", - "path": "devices/Linear/lct2270/rtl/AxiLtc2270Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sgmii88E1111Mdio", - "path": "devices/Marvell/Sgmii88E1111/core/Sgmii88E1111Mdio.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sgmii88E1111LvdsUltraScale", - "path": "devices/Marvell/Sgmii88E1111/lvdsUltraScale/Sgmii88E1111LvdsUltraScale.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DS2411Core", - "path": "devices/Maxim/dummy/DS2411CoreDummy.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DS2411Core", - "path": "devices/Maxim/rtl/DS2411Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Max5443", - "path": "devices/Maxim/rtl/Max5443.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Max5443DacCntrl", - "path": "devices/Maxim/rtl/Max5443DacCntrl.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiSy56040Core", - "path": "devices/Microchip/sy56040/rtl/AxiSy56040Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiSy56040Reg", - "path": "devices/Microchip/sy56040/rtl/AxiSy56040Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sy89297", - "path": "devices/Microchip/sy89297/rtl/Sy89297.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronMt28ewCore", - "path": "devices/Micron/mt28ew/rtl/AxiMicronMt28ewCore.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronMt28ewReg", - "path": "devices/Micron/mt28ew/rtl/AxiMicronMt28ewReg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronN25QCore", - "path": "devices/Micron/n25q/rtl/AxiMicronN25QCore.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronN25QReg", - "path": "devices/Micron/n25q/rtl/AxiMicronN25QReg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronP30Core", - "path": "devices/Micron/p30/rtl/AxiMicronP30Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronP30Reg", - "path": "devices/Micron/p30/rtl/AxiMicronP30Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sc18Is602", - "path": "devices/Nxp/Sc18Is602/rtl/Sc18Is602.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sc18Is602Core", - "path": "devices/Nxp/Sc18Is602/rtl/Sc18Is602Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Si5324", - "path": "devices/Silabs/si5324/rtl/Si5324.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Si5345", - "path": "devices/Silabs/si5345/rtl/Si5345.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Si5394I2c", - "path": "devices/Silabs/si5394/rtl/Si5394I2c.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Si5394I2cCore", - "path": "devices/Silabs/si5394/rtl/Si5394I2cCore.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Lmk048Base", - "path": "devices/Ti/Lmk048Base/rtl/Lmk048Base.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "adc32rf45", - "path": "devices/Ti/adc32rf45/rtl/adc32rf45.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAds42lb69Core", - "path": "devices/Ti/ads42lb69/rtl/AxiAds42lb69Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAds42lb69Deser", - "path": "devices/Ti/ads42lb69/rtl/AxiAds42lb69Deser.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAds42lb69DeserBit", - "path": "devices/Ti/ads42lb69/rtl/AxiAds42lb69DeserBit.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAds42lb69Pll", - "path": "devices/Ti/ads42lb69/rtl/AxiAds42lb69Pll.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAds42lb69Reg", - "path": "devices/Ti/ads42lb69/rtl/AxiAds42lb69Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ads54j60", - "path": "devices/Ti/ads54j60/rtl/ads54j60.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiDac7654Core", - "path": "devices/Ti/dac7654/rtl/AxiDac7654Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiDac7654Reg", - "path": "devices/Ti/dac7654/rtl/AxiDac7654Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiDac7654Spi", - "path": "devices/Ti/dac7654/rtl/AxiDac7654Spi.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SgmiiDp83867Mdio", - "path": "devices/Ti/dp83867/core/SgmiiDp83867Mdio.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SgmiiDp83867LvdsUltraScale", - "path": "devices/Ti/dp83867/lvdsUltraScale/SgmiiDp83867LvdsUltraScale.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiXcf128Core", - "path": "devices/Xilinx/xcf128/rtl/AxiXcf128Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiXcf128Reg", - "path": "devices/Xilinx/xcf128/rtl/AxiXcf128Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "QsfpCdrDisable", - "path": "devices/transceivers/rtl/QsfpCdrDisable.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sff8472", - "path": "devices/transceivers/rtl/Sff8472.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sff8472Core", - "path": "devices/transceivers/rtl/Sff8472Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "add3", - "path": "dsp/xilinx/fixed/Add3.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "CfixedAccumulator", - "path": "dsp/xilinx/fixed/CfixedAccumulator.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "cfixedDelay", - "path": "dsp/xilinx/fixed/CfixedDelay.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "cfixedMult", - "path": "dsp/xilinx/fixed/CfixedMult.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "cfixedMultAdd", - "path": "dsp/xilinx/fixed/CfixedMultAdd.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "CfixedPreAddMult", - "path": "dsp/xilinx/fixed/CfixedPreAddMult.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "csa3", - "path": "dsp/xilinx/fixed/Csa3.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "FirAverage", - "path": "dsp/xilinx/fixed/FirAverage.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "IirSimple", - "path": "dsp/xilinx/fixed/IirSimple.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "SfixedAccumulator", - "path": "dsp/xilinx/fixed/SfixedAccumulator.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "sfixedDelay", - "path": "dsp/xilinx/fixed/SfixedDelay.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "sfixedMult", - "path": "dsp/xilinx/fixed/SfixedMult.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "sfixedMultAdd", - "path": "dsp/xilinx/fixed/SfixedMultAdd.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "sfixedPreAddMultAdd", - "path": "dsp/xilinx/fixed/SfixedPreAddMultAdd.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "SinCosLut", - "path": "dsp/xilinx/fixed/SinCosLut.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "SinCosTaylor", - "path": "dsp/xilinx/fixed/SinCosTaylor.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "DspXor", - "path": "dsp/xilinx/logic/DspXor.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "Caui4GtyIpWrapper", - "path": "ethernet/Caui4Core/gtyUltraScale+/rtl/Caui4GtyIpWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthCrc32Parallel", - "path": "ethernet/EthMacCore/rtl/EthCrc32Parallel.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacFlowCtrl", - "path": "ethernet/EthMacCore/rtl/EthMacFlowCtrl.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRx", - "path": "ethernet/EthMacCore/rtl/EthMacRx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxBypass", - "path": "ethernet/EthMacCore/rtl/EthMacRxBypass.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxCsum", - "path": "ethernet/EthMacCore/rtl/EthMacRxCsum.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxFifo", - "path": "ethernet/EthMacCore/rtl/EthMacRxFifo.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxFilter", - "path": "ethernet/EthMacCore/rtl/EthMacRxFilter.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxImport", - "path": "ethernet/EthMacCore/rtl/EthMacRxImport.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxImportGmii", - "path": "ethernet/EthMacCore/rtl/EthMacRxImportGmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxImportXgmii", - "path": "ethernet/EthMacCore/rtl/EthMacRxImportXgmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxImportXlgmii", - "path": "ethernet/EthMacCore/rtl/EthMacRxImportXlgmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxPause", - "path": "ethernet/EthMacCore/rtl/EthMacRxPause.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxShift", - "path": "ethernet/EthMacCore/rtl/EthMacRxShift.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTop", - "path": "ethernet/EthMacCore/rtl/EthMacTop.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTx", - "path": "ethernet/EthMacCore/rtl/EthMacTx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxBypass", - "path": "ethernet/EthMacCore/rtl/EthMacTxBypass.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxCsum", - "path": "ethernet/EthMacCore/rtl/EthMacTxCsum.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxExport", - "path": "ethernet/EthMacCore/rtl/EthMacTxExport.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxExportGmii", - "path": "ethernet/EthMacCore/rtl/EthMacTxExportGmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxExportXgmii", - "path": "ethernet/EthMacCore/rtl/EthMacTxExportXgmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxExportXlgmii", - "path": "ethernet/EthMacCore/rtl/EthMacTxExportXlgmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxFifo", - "path": "ethernet/EthMacCore/rtl/EthMacTxFifo.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxPause", - "path": "ethernet/EthMacCore/rtl/EthMacTxPause.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxShift", - "path": "ethernet/EthMacCore/rtl/EthMacTxShift.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthReg", - "path": "ethernet/GigEthCore/core/rtl/GigEthReg.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGth7", - "path": "ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGth7Wrapper", - "path": "ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGthUltraScale", - "path": "ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGthUltraScaleWrapper", - "path": "ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGthUltraScale", - "path": "ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGthUltraScaleWrapper", - "path": "ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtp7", - "path": "ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtp7Wrapper", - "path": "ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtx7", - "path": "ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtx7Wrapper", - "path": "ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtyUltraScale", - "path": "ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtyUltraScaleWrapper", - "path": "ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthLvdsUltraScale", - "path": "ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ArpEngine", - "path": "ethernet/IpV4Engine/rtl/ArpEngine.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IcmpEngine", - "path": "ethernet/IpV4Engine/rtl/IcmpEngine.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IgmpV2Engine", - "path": "ethernet/IpV4Engine/rtl/IgmpV2Engine.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IpV4Engine", - "path": "ethernet/IpV4Engine/rtl/IpV4Engine.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IpV4EngineDeMux", - "path": "ethernet/IpV4Engine/rtl/IpV4EngineDeMux.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IpV4EngineRx", - "path": "ethernet/IpV4Engine/rtl/IpV4EngineRx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IpV4EngineTx", - "path": "ethernet/IpV4Engine/rtl/IpV4EngineTx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RawEthFramer", - "path": "ethernet/RawEthFramer/rtl/RawEthFramer.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RawEthFramerRx", - "path": "ethernet/RawEthFramer/rtl/RawEthFramerRx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RawEthFramerTx", - "path": "ethernet/RawEthFramer/rtl/RawEthFramerTx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RawEthFramerWrapper", - "path": "ethernet/RawEthFramer/rtl/RawEthFramerWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacCrcAxiStreamWrapperRecv", - "path": "ethernet/RoCEv2/rtl/EthMacCrcAxiStreamWrapperRecv.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacCrcAxiStreamWrapperSend", - "path": "ethernet/RoCEv2/rtl/EthMacCrcAxiStreamWrapperSend.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacPrepareForICrc", - "path": "ethernet/RoCEv2/rtl/EthMacPrepareForICrc.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxCheckICrc", - "path": "ethernet/RoCEv2/rtl/EthMacRxCheckICrc.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxRoCEv2", - "path": "ethernet/RoCEv2/rtl/EthMacRxRoCEv2.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxRoCEv2", - "path": "ethernet/RoCEv2/rtl/EthMacTxRoCEv2.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RoceConfigurator", - "path": "ethernet/RoCEv2/rtl/RoceConfigurator.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RoceEngineWrapper", - "path": "ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RoceResizeAndSwap", - "path": "ethernet/RoCEv2/rtl/RoceResizeAndSwap.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthReg", - "path": "ethernet/TenGigEthCore/core/rtl/TenGigEthReg.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthRst", - "path": "ethernet/TenGigEthCore/core/rtl/TenGigEthRst.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGth7", - "path": "ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGth7Clk", - "path": "ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Clk.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGth7Wrapper", - "path": "ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScale", - "path": "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleClk", - "path": "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleClk.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleRst", - "path": "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleRst.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleWrapper", - "path": "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScale", - "path": "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleClk", - "path": "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleClk.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleRst", - "path": "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleRst.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleWrapper", - "path": "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtx7", - "path": "ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtx7Clk", - "path": "ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Clk.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtx7Wrapper", - "path": "ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtyUltraScale", - "path": "ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtyUltraScaleClk", - "path": "ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleClk.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtyUltraScaleRst", - "path": "ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleRst.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtyUltraScaleWrapper", - "path": "ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ArpIpTable", - "path": "ethernet/UdpEngine/rtl/ArpIpTable.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngine", - "path": "ethernet/UdpEngine/rtl/UdpEngine.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngineArp", - "path": "ethernet/UdpEngine/rtl/UdpEngineArp.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngineDhcp", - "path": "ethernet/UdpEngine/rtl/UdpEngineDhcp.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngineRx", - "path": "ethernet/UdpEngine/rtl/UdpEngineRx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngineTx", - "path": "ethernet/UdpEngine/rtl/UdpEngineTx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngineWrapper", - "path": "ethernet/UdpEngine/rtl/UdpEngineWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiReg", - "path": "ethernet/XauiCore/core/rtl/XauiReg.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGth7", - "path": "ethernet/XauiCore/gth7/rtl/XauiGth7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGth7Core", - "path": "ethernet/XauiCore/gth7/rtl/XauiGth7Core.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGth7Wrapper", - "path": "ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGthUltraScale", - "path": "ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGthUltraScaleWrapper", - "path": "ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGthUltraScale", - "path": "ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGthUltraScaleWrapper", - "path": "ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGtx7", - "path": "ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGtx7Core", - "path": "ethernet/XauiCore/gtx7/rtl/XauiGtx7Core.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGtx7Wrapper", - "path": "ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGtyUltraScale", - "path": "ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGtyUltraScaleWrapper", - "path": "ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamBatcher", - "path": "protocols/batcher/rtl/AxiStreamBatcher.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamBatcherAxil", - "path": "protocols/batcher/rtl/AxiStreamBatcherAxil.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamBatcherEventBuilder", - "path": "protocols/batcher/rtl/AxiStreamBatcherEventBuilder.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkDataClk", - "path": "protocols/clink/7Series/ClinkDataClk.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkDataShift", - "path": "protocols/clink/7Series/ClinkDataShift.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkDataClk", - "path": "protocols/clink/UltraScale/ClinkDataClk.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkDataShift", - "path": "protocols/clink/UltraScale/ClinkDataShift.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkCtrl", - "path": "protocols/clink/rtl/ClinkCtrl.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkData", - "path": "protocols/clink/rtl/ClinkData.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkFraming", - "path": "protocols/clink/rtl/ClinkFraming.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkReg", - "path": "protocols/clink/rtl/ClinkReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkTop", - "path": "protocols/clink/rtl/ClinkTop.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkUart", - "path": "protocols/clink/rtl/ClinkUart.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkUartThrottle", - "path": "protocols/clink/rtl/ClinkUartThrottle.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressAxiL", - "path": "protocols/coaxpress/core/rtl/CoaXPressAxiL.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressConfig", - "path": "protocols/coaxpress/core/rtl/CoaXPressConfig.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressCore", - "path": "protocols/coaxpress/core/rtl/CoaXPressCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressEventAckMsg", - "path": "protocols/coaxpress/core/rtl/CoaXPressEventAckMsg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberBridge", - "path": "protocols/coaxpress/core/rtl/CoaXPressOverFiberBridge.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberBridgeRx", - "path": "protocols/coaxpress/core/rtl/CoaXPressOverFiberBridgeRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberBridgeTx", - "path": "protocols/coaxpress/core/rtl/CoaXPressOverFiberBridgeTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressRx", - "path": "protocols/coaxpress/core/rtl/CoaXPressRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressRxHsFsm", - "path": "protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressRxLane", - "path": "protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressRxLaneMux", - "path": "protocols/coaxpress/core/rtl/CoaXPressRxLaneMux.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressRxWordPacker", - "path": "protocols/coaxpress/core/rtl/CoaXPressRxWordPacker.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressTx", - "path": "protocols/coaxpress/core/rtl/CoaXPressTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressTxLsFsm", - "path": "protocols/coaxpress/core/rtl/CoaXPressTxLsFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberGthUsIpWrapper", - "path": "protocols/coaxpress/gthUs+/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGthUs", - "path": "protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGthUsQpll", - "path": "protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberGthUsIpWrapper", - "path": "protocols/coaxpress/gthUs/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGthUs", - "path": "protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGthUsQpll", - "path": "protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberGtyUsIpWrapper", - "path": "protocols/coaxpress/gtyUs+/rtl/CoaXPressOverFiberGtyUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGtyUs", - "path": "protocols/coaxpress/gtyUs+/rtl/CoaxpressOverFiberGtyUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGtyUsQpll", - "path": "protocols/coaxpress/gtyUs+/rtl/CoaxpressOverFiberGtyUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EventFrameSequencerDemux", - "path": "protocols/event-frame-sequencer/rtl/EventFrameSequencerDemux.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EventFrameSequencerMux", - "path": "protocols/event-frame-sequencer/rtl/EventFrameSequencerMux.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EventFrameSequencerWrapper", - "path": "protocols/event-frame-sequencer/wrappers/EventFrameSequencerWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkDecoder", - "path": "protocols/glink/core/rtl/GLinkDecoder.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkEncoder", - "path": "protocols/glink/core/rtl/GLinkEncoder.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkTxToRx", - "path": "protocols/glink/core/rtl/GLinkTxToRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkGtp7FixedLat", - "path": "protocols/glink/gtp7/rtl/GLinkGtp7FixedLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkGtx7Core", - "path": "protocols/glink/gtx7/rtl/GLinkGtx7Core.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkGtx7FixedLat", - "path": "protocols/glink/gtx7/rtl/GLinkGtx7FixedLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkGtx7RxRst", - "path": "protocols/glink/gtx7/rtl/GLinkGtx7RxRst.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HammingEccDecoder", - "path": "protocols/hamming-ecc/rtl/HammingEccDecoder.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HammingEccEncoder", - "path": "protocols/hamming-ecc/rtl/HammingEccEncoder.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HammingEccWrapper", - "path": "protocols/hamming-ecc/wrappers/HammingEccWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspAxiL", - "path": "protocols/htsp/core/rtl/HtspAxiL.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspCore", - "path": "protocols/htsp/core/rtl/HtspCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspRx", - "path": "protocols/htsp/core/rtl/HtspRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspRxFifo", - "path": "protocols/htsp/core/rtl/HtspRxFifo.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspTx", - "path": "protocols/htsp/core/rtl/HtspTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspTxFifo", - "path": "protocols/htsp/core/rtl/HtspTxFifo.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspCaui4Gty", - "path": "protocols/htsp/gtyUs+/rtl/HtspCaui4Gty.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiI2cEeprom", - "path": "protocols/i2c/axi/AxiI2cEeprom.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiI2cEepromCore", - "path": "protocols/i2c/axi/AxiI2cEepromCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiI2cRegMaster", - "path": "protocols/i2c/axi/AxiI2cRegMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiI2cRegMasterCore", - "path": "protocols/i2c/axi/AxiI2cRegMasterCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLiteCrossbarI2cMux", - "path": "protocols/i2c/axi/AxiLiteCrossbarI2cMux.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cMaster", - "path": "protocols/i2c/rtl/I2cMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRegMaster", - "path": "protocols/i2c/rtl/I2cRegMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRegMasterAxiBridge", - "path": "protocols/i2c/rtl/I2cRegMasterAxiBridge.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRegMasterMux", - "path": "protocols/i2c/rtl/I2cRegMasterMux.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRegSlave", - "path": "protocols/i2c/rtl/I2cRegSlave.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cSlave", - "path": "protocols/i2c/rtl/I2cSlave.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2c_master_bit_ctrl", - "path": "protocols/i2c/rtl/i2c_master_bit_ctrl.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2c_master_byte_ctrl", - "path": "protocols/i2c/rtl/i2c_master_byte_ctrl.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2c2ahb", - "path": "protocols/i2c/rtl/orig/i2c2ahb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2c2ahb_apb", - "path": "protocols/i2c/rtl/orig/i2c2ahb_apb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2c2ahbx", - "path": "protocols/i2c/rtl/orig/i2c2ahbx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2cmst", - "path": "protocols/i2c/rtl/orig/i2cmst.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2cmst_gen", - "path": "protocols/i2c/rtl/orig/i2cmst_gen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2cslv", - "path": "protocols/i2c/rtl/orig/i2cslv.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRamSlave", - "path": "protocols/i2c/sim/I2cRamSlave.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRegTb", - "path": "protocols/i2c/sim/I2cRegTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd16bTo32b", - "path": "protocols/jesd204b/rtl/Jesd16bTo32b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd204bRx", - "path": "protocols/jesd204b/rtl/Jesd204bRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd204bTx", - "path": "protocols/jesd204b/rtl/Jesd204bTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd32bTo16b", - "path": "protocols/jesd204b/rtl/Jesd32bTo16b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd32bTo64b", - "path": "protocols/jesd204b/rtl/Jesd32bTo64b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd64bTo32b", - "path": "protocols/jesd204b/rtl/Jesd64bTo32b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdAlignChGen", - "path": "protocols/jesd204b/rtl/JesdAlignChGen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdAlignFrRepCh", - "path": "protocols/jesd204b/rtl/JesdAlignFrRepCh.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdIlasGen", - "path": "protocols/jesd204b/rtl/JesdIlasGen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdLmfcGen", - "path": "protocols/jesd204b/rtl/JesdLmfcGen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdRxLane", - "path": "protocols/jesd204b/rtl/JesdRxLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdRxReg", - "path": "protocols/jesd204b/rtl/JesdRxReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdSyncFsmRx", - "path": "protocols/jesd204b/rtl/JesdSyncFsmRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdSyncFsmTx", - "path": "protocols/jesd204b/rtl/JesdSyncFsmTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdSyncFsmTxTest", - "path": "protocols/jesd204b/rtl/JesdSyncFsmTxTest.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdSysrefMon", - "path": "protocols/jesd204b/rtl/JesdSysrefMon.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdTestSigGen", - "path": "protocols/jesd204b/rtl/JesdTestSigGen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdTestStreamTx", - "path": "protocols/jesd204b/rtl/JesdTestStreamTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdTxLane", - "path": "protocols/jesd204b/rtl/JesdTxLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdTxReg", - "path": "protocols/jesd204b/rtl/JesdTxReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdTxTest", - "path": "protocols/jesd204b/rtl/JesdTxTest.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "iq16bTo32b", - "path": "protocols/jesd204b/rtl/iq16bTo32b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "iq32bTo16b", - "path": "protocols/jesd204b/rtl/iq32bTo16b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "DescrambleTb", - "path": "protocols/jesd204b/sim/DescrambleTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd204bTb", - "path": "protocols/jesd204b/sim/Jesd204bTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ScramblerTb", - "path": "protocols/jesd204b/sim/ScramblerTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Decoder10b12b", - "path": "protocols/line-codes/rtl/Decoder10b12b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Decoder12b14b", - "path": "protocols/line-codes/rtl/Decoder12b14b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Decoder8b10b", - "path": "protocols/line-codes/rtl/Decoder8b10b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Encoder10b12b", - "path": "protocols/line-codes/rtl/Encoder10b12b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Encoder12b14b", - "path": "protocols/line-codes/rtl/Encoder12b14b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Encoder8b10b", - "path": "protocols/line-codes/rtl/Encoder8b10b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Code10b12bPkgWrapper", - "path": "protocols/line-codes/wrappers/Code10b12bPkgWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Code12b14bPkgWrapper", - "path": "protocols/line-codes/wrappers/Code12b14bPkgWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Code8b10bPkgWrapper", - "path": "protocols/line-codes/wrappers/Code8b10bPkgWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "MdioCore", - "path": "protocols/mdio/rtl/MdioCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "MdioLinkIrqHandler", - "path": "protocols/mdio/rtl/MdioLinkIrqHandler.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "MdioSeqCore", - "path": "protocols/mdio/rtl/MdioSeqCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamBytePacker", - "path": "protocols/packetizer/rtl/AxiStreamBytePacker.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamDepacketizer", - "path": "protocols/packetizer/rtl/AxiStreamDepacketizer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamDepacketizer2", - "path": "protocols/packetizer/rtl/AxiStreamDepacketizer2.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamPacketizer", - "path": "protocols/packetizer/rtl/AxiStreamPacketizer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamPacketizer2", - "path": "protocols/packetizer/rtl/AxiStreamPacketizer2.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bAxi", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bLane", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bRx", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bRxCell", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bRxCell.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bRxPhy", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bRxPhy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bTx", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bTxCell", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bTxPhy", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bTxPhy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bTxSched", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGth7Fixedlat", - "path": "protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7FixedLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGth7FixedLatWrapper", - "path": "protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7FixedLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGth7MultiLane", - "path": "protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7MultiLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGth7VarLat", - "path": "protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7VarLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGth7VarLatWrapper", - "path": "protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7VarLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGthUltra", - "path": "protocols/pgp/pgp2b/gthUltraScale+/rtl/Pgp2bGthUltra.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpGthCoreWrapper", - "path": "protocols/pgp/pgp2b/gthUltraScale+/rtl/PgpGthCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGthUltra", - "path": "protocols/pgp/pgp2b/gthUltraScale/rtl/Pgp2bGthUltra.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpGthCoreWrapper", - "path": "protocols/pgp/pgp2b/gthUltraScale/rtl/PgpGthCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtp7FixedLat", - "path": "protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7FixedLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtp7FixedLatWrapper", - "path": "protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7FixedLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtp7MultiLane", - "path": "protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7MultiLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtp7VarLat", - "path": "protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7VarLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtp7VarLatWrapper", - "path": "protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7VarLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtx7Fixedlat", - "path": "protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtx7FixedLatWrapper", - "path": "protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtx7MultiLane", - "path": "protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7MultiLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtx7VarLat", - "path": "protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7VarLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtx7VarLatWrapper", - "path": "protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7VarLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtyUltra", - "path": "protocols/pgp/pgp2b/gtyUltraScale+/rtl/Pgp2bGtyUltra.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpGtyCoreWrapper", - "path": "protocols/pgp/pgp2b/gtyUltraScale+/rtl/PgpGtyCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CRC7Rtl", - "path": "protocols/pgp/pgp2fc/core/rtl/CRC7Rtl.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcAlignmentChecker", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcAlignmentChecker.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcAlignmentController", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcAlignmentController.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcAxi", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcLane", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcRx", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcRxCell", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxCell.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcRxPhy", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxPhy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcTx", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcTxCell", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxCell.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcTxPhy", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcTxSched", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxSched.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGthCoreWrapper", - "path": "protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGthUltra", - "path": "protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGtp7", - "path": "protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGtp7Wrapper", - "path": "protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7Wrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGtyCoreWrapper", - "path": "protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGtyUltra", - "path": "protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3AxiL", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3AxiL.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Core", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3Core.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Rx", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3Rx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3RxEb", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3RxEb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3RxGearboxAligner", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3RxGearboxAligner.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3RxProtocol", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3RxProtocol.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Tx", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3Tx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3TxProtocol", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3TxProtocol.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUs", - "path": "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsIpWrapper", - "path": "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsQpll", - "path": "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsWrapper", - "path": "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUs", - "path": "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsIpWrapper", - "path": "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsQpll", - "path": "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsWrapper", - "path": "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7IpWrapper", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7IpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7Qpll", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7Qpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7RxGearbox", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7RxGearbox.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7TxGearbox", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7TxGearbox.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7Wrapper", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7Wrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtx7", - "path": "protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtx7IpWrapper", - "path": "protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7IpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtx7Qpll", - "path": "protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Qpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtx7Wrapper", - "path": "protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Wrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GtyUs", - "path": "protocols/pgp/pgp3/gtyUs+/rtl/Pgp3GtyUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GtyUsIpWrapper", - "path": "protocols/pgp/pgp3/gtyUs+/rtl/Pgp3GtyUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GtyUsQpll", - "path": "protocols/pgp/pgp3/gtyUs+/rtl/Pgp3GtyUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GtyUsWrapper", - "path": "protocols/pgp/pgp3/gtyUs+/rtl/Pgp3GtyUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4AxiL", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4AxiL.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Core", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4Core.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4CoreLite", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4CoreLite.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Rx", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4RxEb", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4LiteRxLowSpeed", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4RxLiteLowSpeed.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4RxLiteLowSpeedLane", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4RxLiteLowSpeedLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4RxLiteLowSpeedReg", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4RxLiteLowSpeedReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4RxProtocol", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4RxProtocol.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Tx", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4Tx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4TxLite", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4TxLite.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4TxLiteProtocol", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4TxLiteProtocol.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4TxLiteWrapper", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4TxProtocol", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4TxProtocol.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4CoreLiteWrapper", - "path": "protocols/pgp/pgp4/core/wrappers/Pgp4CoreLiteWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4CoreWrapper", - "path": "protocols/pgp/pgp4/core/wrappers/Pgp4CoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GthUs", - "path": "protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GthUsWrapper", - "path": "protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GthUs", - "path": "protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GthUsWrapper", - "path": "protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Gtp7", - "path": "protocols/pgp/pgp4/gtp7/rtl/Pgp4Gtp7.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Gtp7Wrapper", - "path": "protocols/pgp/pgp4/gtp7/rtl/Pgp4Gtp7Wrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Gtx7", - "path": "protocols/pgp/pgp4/gtx7/rtl/Pgp4Gtx7.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Gtx7Wrapper", - "path": "protocols/pgp/pgp4/gtx7/rtl/Pgp4Gtx7Wrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GtyUs", - "path": "protocols/pgp/pgp4/gtyUs+/rtl/Pgp4GtyUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GtyUsIpFecWrapper", - "path": "protocols/pgp/pgp4/gtyUs+/rtl/Pgp4GtyUsIpFecWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GtyUsWrapper", - "path": "protocols/pgp/pgp4/gtyUs+/rtl/Pgp4GtyUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpRxVcFifo", - "path": "protocols/pgp/shared/PgpRxVcFifo.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpTxVcFifo", - "path": "protocols/pgp/shared/PgpTxVcFifo.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpXvcWrapper", - "path": "protocols/pgp/shared/xilinx/PgpXvcWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLitePMbusMaster", - "path": "protocols/pmbus/rtl/AxiLitePMbusMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLitePMbusMasterCore", - "path": "protocols/pmbus/rtl/AxiLitePMbusMasterCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiAxiLiteRegItf", - "path": "protocols/rssi/v1/rtl/RssiAxiLiteRegItf.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiChksum", - "path": "protocols/rssi/v1/rtl/RssiChksum.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiConnFsm", - "path": "protocols/rssi/v1/rtl/RssiConnFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiCore", - "path": "protocols/rssi/v1/rtl/RssiCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiCoreWrapper", - "path": "protocols/rssi/v1/rtl/RssiCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiHeaderReg", - "path": "protocols/rssi/v1/rtl/RssiHeaderReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiMonitor", - "path": "protocols/rssi/v1/rtl/RssiMonitor.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiParamSync", - "path": "protocols/rssi/v1/rtl/RssiParamSync.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiRxFsm", - "path": "protocols/rssi/v1/rtl/RssiRxFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiTxFsm", - "path": "protocols/rssi/v1/rtl/RssiTxFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLiteSaciMaster", - "path": "protocols/saci/saci1/rtl/AxiLiteSaciMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciAxiLiteMaster", - "path": "protocols/saci/saci1/rtl/SaciAxiLiteMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciMaster", - "path": "protocols/saci/saci1/rtl/SaciMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciMaster2", - "path": "protocols/saci/saci1/rtl/SaciMaster2.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciMasterSync", - "path": "protocols/saci/saci1/rtl/SaciMasterSync.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciMultiPixel", - "path": "protocols/saci/saci1/rtl/SaciMultiPixel.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciPrepRdout", - "path": "protocols/saci/saci1/rtl/SaciPrepRdout.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciSlave", - "path": "protocols/saci/saci1/rtl/SaciSlave.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciSlaveOld", - "path": "protocols/saci/saci1/rtl/SaciSlaveOld.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLiteSaciMasterTb", - "path": "protocols/saci/saci1/sim/AxiLiteSaciMasterTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciAxiLiteMasterTb", - "path": "protocols/saci/saci1/sim/SaciAxiLiteMasterTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciAxiLiteMasterTbWrapper", - "path": "protocols/saci/saci1/sim/SaciAxiLiteMasterTbWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciSlaveRam", - "path": "protocols/saci/saci1/sim/SaciSlaveRam.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciSlaveWrapper", - "path": "protocols/saci/saci1/sim/SaciSlaveWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciAxiLiteMasterWrapper", - "path": "protocols/saci/saci1/wrappers/SaciAxiLiteMasterWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLiteToSaci2", - "path": "protocols/saci/saci2/rtl/AxiLiteToSaci2.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Saci2Coordinator", - "path": "protocols/saci/saci2/rtl/Saci2Coordinator.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Saci2Subordinate", - "path": "protocols/saci/saci2/rtl/Saci2Subordinate.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Saci2ToAxiLite", - "path": "protocols/saci/saci2/rtl/Saci2ToAxiLite.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Saci2ToAxiLiteTb", - "path": "protocols/saci/saci2/sim/Saci2ToAxiLiteTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Saci2ToAxiLiteWrapper", - "path": "protocols/saci/saci2/wrappers/Saci2ToAxiLiteWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltRxDeser", - "path": "protocols/salt/rtl/7Series/SaltRxDeser.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltTxSer", - "path": "protocols/salt/rtl/7Series/SaltTxSer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltCore", - "path": "protocols/salt/rtl/SaltCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltDelayCtrl", - "path": "protocols/salt/rtl/SaltDelayCtrl.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltRx", - "path": "protocols/salt/rtl/SaltRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltRxLvds", - "path": "protocols/salt/rtl/SaltRxLvds.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltTx", - "path": "protocols/salt/rtl/SaltTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltTxLvds", - "path": "protocols/salt/rtl/SaltTxLvds.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltTxResize", - "path": "protocols/salt/rtl/SaltTxResize.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltRxDeser", - "path": "protocols/salt/rtl/UltraScale/SaltRxDeser.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltTxSer", - "path": "protocols/salt/rtl/UltraScale/SaltTxSer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiSpiMaster", - "path": "protocols/spi/rtl/AxiSpiMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SpiMaster", - "path": "protocols/spi/rtl/SpiMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SpiSlave", - "path": "protocols/spi/rtl/SpiSlave.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLiteSrpV0", - "path": "protocols/srp/rtl/AxiLiteSrpV0.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV0AxiLite", - "path": "protocols/srp/rtl/SrpV0AxiLite.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV3Axi", - "path": "protocols/srp/rtl/SrpV3Axi.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV3AxiLite", - "path": "protocols/srp/rtl/SrpV3AxiLite.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV3AxiLiteFull", - "path": "protocols/srp/rtl/SrpV3AxiLiteFull.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV3Core", - "path": "protocols/srp/rtl/SrpV3Core.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV3AxiWrapper", - "path": "protocols/srp/wrappers/SrpV3AxiWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiAxiLiteMaster", - "path": "protocols/ssi/rtl/SsiAxiLiteMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiCmdMaster", - "path": "protocols/ssi/rtl/SsiCmdMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiCmdMasterPulser", - "path": "protocols/ssi/rtl/SsiCmdMasterPulser.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiDbgTap", - "path": "protocols/ssi/rtl/SsiDbgTap.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiFifo", - "path": "protocols/ssi/rtl/SsiFifo.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiFrameLimiter", - "path": "protocols/ssi/rtl/SsiFrameLimiter.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiIbFrameFilter", - "path": "protocols/ssi/rtl/SsiIbFrameFilter.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiIncrementingTx", - "path": "protocols/ssi/rtl/SsiIncrementingTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiInsertSof", - "path": "protocols/ssi/rtl/SsiInsertSof.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiObFrameFilter", - "path": "protocols/ssi/rtl/SsiObFrameFilter.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiPrbsRateGen", - "path": "protocols/ssi/rtl/SsiPrbsRateGen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiPrbsRx", - "path": "protocols/ssi/rtl/SsiPrbsRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiPrbsTx", - "path": "protocols/ssi/rtl/SsiPrbsTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiPrbsWrapper", - "path": "protocols/ssi/wrappers/SsiPrbsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiResizeFifoEofeWrapper", - "path": "protocols/ssi/wrappers/SsiResizeFifoEofeWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspDecoder10b12b", - "path": "protocols/ssp/rtl/SspDecoder10b12b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspDecoder12b14b", - "path": "protocols/ssp/rtl/SspDecoder12b14b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspDecoder8b10b", - "path": "protocols/ssp/rtl/SspDecoder8b10b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspDeframer", - "path": "protocols/ssp/rtl/SspDeframer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspEncoder10b12b", - "path": "protocols/ssp/rtl/SspEncoder10b12b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspEncoder12b14b", - "path": "protocols/ssp/rtl/SspEncoder12b14b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspEncoder8b10b", - "path": "protocols/ssp/rtl/SspEncoder8b10b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspFramer", - "path": "protocols/ssp/rtl/SspFramer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspLowSpeedDecoder10b12bWrapper", - "path": "protocols/ssp/rtl/SspLowSpeedDecoder10b12bWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspLowSpeedDecoder12b14bWrapper", - "path": "protocols/ssp/rtl/SspLowSpeedDecoder12b14bWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspLowSpeedDecoder8b10bWrapper", - "path": "protocols/ssp/rtl/SspLowSpeedDecoder8b10bWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspLowSpeedDecoderLane", - "path": "protocols/ssp/rtl/SspLowSpeedDecoderLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspLowSpeedDecoderReg", - "path": "protocols/ssp/rtl/SspLowSpeedDecoderReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerRx7Series", - "path": "protocols/sugoi/rtl/7Series/SugoiManagerRx7Series.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiAxiLitePixelMatrixConfig", - "path": "protocols/sugoi/rtl/SugoiAxiLitePixelMatrixConfig.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerCore", - "path": "protocols/sugoi/rtl/SugoiManagerCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerFsm", - "path": "protocols/sugoi/rtl/SugoiManagerFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerRx", - "path": "protocols/sugoi/rtl/SugoiManagerRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiSubordinateCore", - "path": "protocols/sugoi/rtl/SugoiSubordinateCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiSubordinateFsm", - "path": "protocols/sugoi/rtl/SugoiSubordinateFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerRxUltrascale", - "path": "protocols/sugoi/rtl/UltraScale/SugoiManagerRxUltrascale.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerRx7Series", - "path": "protocols/sugoi/rtl/dummy/SugoiManagerRx7SeriesDummy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerRxUltrascale", - "path": "protocols/sugoi/rtl/dummy/SugoiManagerRxUltrascaleDummy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartAxiLiteMaster", - "path": "protocols/uart/rtl/UartAxiLiteMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartAxiLiteMasterFsm", - "path": "protocols/uart/rtl/UartAxiLiteMasterFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartBrg", - "path": "protocols/uart/rtl/UartBrg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartRx", - "path": "protocols/uart/rtl/UartRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartTx", - "path": "protocols/uart/rtl/UartTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartWrapper", - "path": "protocols/uart/rtl/UartWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartAxiLiteMasterTb", - "path": "protocols/uart/sim/UartAxiLiteMasterTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Idelaye3Wrapper", - "path": "xilinx/7Series/dummy/Idelaye3WrapperDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Odelaye3Wrapper", - "path": "xilinx/7Series/dummy/Odelaye3WrapperDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClockManager7", - "path": "xilinx/7Series/general/rtl/ClockManager7.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DeviceDna7Series", - "path": "xilinx/7Series/general/rtl/DeviceDna7Series.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Dsp48Comparator4x12b", - "path": "xilinx/7Series/general/rtl/Dsp48Comparator4x12b.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "InputBufferReg", - "path": "xilinx/7Series/general/rtl/InputBufferReg.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Iprog7Series", - "path": "xilinx/7Series/general/rtl/Iprog7Series.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Iprog7SeriesCore", - "path": "xilinx/7Series/general/rtl/Iprog7SeriesCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "OutputBufferReg", - "path": "xilinx/7Series/general/rtl/OutputBufferReg.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SelectioDeser7Series", - "path": "xilinx/7Series/general/rtl/SelectioDeser7Series.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SelectioDeserLane7Series", - "path": "xilinx/7Series/general/rtl/SelectioDeserLane7Series.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7AutoPhaseAligner", - "path": "xilinx/7Series/gth7/rtl/Gth7AutoPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7Core", - "path": "xilinx/7Series/gth7/rtl/Gth7Core.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7QuadPll", - "path": "xilinx/7Series/gth7/rtl/Gth7QuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7RecClkMonitor", - "path": "xilinx/7Series/gth7/rtl/Gth7RecClkMonitor.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7RxFixedLatPhaseAligner", - "path": "xilinx/7Series/gth7/rtl/Gth7RxFixedLatPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7RxRst", - "path": "xilinx/7Series/gth7/rtl/Gth7RxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7RxRstSeq", - "path": "xilinx/7Series/gth7/rtl/Gth7RxRstSeq.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7TxManualPhaseAligner", - "path": "xilinx/7Series/gth7/rtl/Gth7TxManualPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7TxRst", - "path": "xilinx/7Series/gth7/rtl/Gth7TxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7AutoPhaseAligner", - "path": "xilinx/7Series/gtp7/rtl/Gtp7AutoPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7Core", - "path": "xilinx/7Series/gtp7/rtl/Gtp7Core.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7QuadPll", - "path": "xilinx/7Series/gtp7/rtl/Gtp7QuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7RecClkMonitor", - "path": "xilinx/7Series/gtp7/rtl/Gtp7RecClkMonitor.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7RxFixedLatPhaseAligner", - "path": "xilinx/7Series/gtp7/rtl/Gtp7RxFixedLatPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7RxRst", - "path": "xilinx/7Series/gtp7/rtl/Gtp7RxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7RxRstSeq", - "path": "xilinx/7Series/gtp7/rtl/Gtp7RxRstSeq.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7TxManualPhaseAligner", - "path": "xilinx/7Series/gtp7/rtl/Gtp7TxManualPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7TxRst", - "path": "xilinx/7Series/gtp7/rtl/Gtp7TxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtpe2ChannelDummy", - "path": "xilinx/7Series/gtp7/rtl/Gtpe2ChannelDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7AutoPhaseAligner", - "path": "xilinx/7Series/gtx7/rtl/Gtx7AutoPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7Core", - "path": "xilinx/7Series/gtx7/rtl/Gtx7Core.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7QuadPll", - "path": "xilinx/7Series/gtx7/rtl/Gtx7QuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7RecClkMonitor", - "path": "xilinx/7Series/gtx7/rtl/Gtx7RecClkMonitor.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7RxFixedLatPhaseAligner", - "path": "xilinx/7Series/gtx7/rtl/Gtx7RxFixedLatPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7RxRst", - "path": "xilinx/7Series/gtx7/rtl/Gtx7RxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7TxManualPhaseAligner", - "path": "xilinx/7Series/gtx7/rtl/Gtx7TxManualPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7TxRst", - "path": "xilinx/7Series/gtx7/rtl/Gtx7TxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtxe2ChannelDummy", - "path": "xilinx/7Series/gtx7/rtl/Gtxe2ChannelDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SemWrapper", - "path": "xilinx/7Series/sem/rtl/SemWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SsiSem", - "path": "xilinx/7Series/sem/rtl/SsiSem.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UartSem", - "path": "xilinx/7Series/sem/rtl/UartSem.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiXadcMinimumCore", - "path": "xilinx/7Series/xadc/rtl/AxiXadcMinimumCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "XadcSimpleCore", - "path": "xilinx/7Series/xadc/rtl/XadcSimpleCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClockManagerUltraScale", - "path": "xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GthUltraScaleQuadPll", - "path": "xilinx/UltraScale+/gthUs+/rtl/GthUltraScaleQuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gthe4ChannelDummy", - "path": "xilinx/UltraScale+/gthUs+/rtl/Gthe4ChannelDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GtyUltraScaleQuadPll", - "path": "xilinx/UltraScale+/gtyUs+/rtl/GtyUltraScaleQuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtye4ChannelDummy", - "path": "xilinx/UltraScale+/gtyUs+/rtl/Gtye4ChannelDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClockManagerUltraScale", - "path": "xilinx/UltraScale/clocking/rtl/ClockManagerUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Delaye3PatchFsm", - "path": "xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DeviceDnaUltraScale", - "path": "xilinx/UltraScale/general/rtl/DeviceDnaUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Idelaye3Wrapper", - "path": "xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "InputBufferReg", - "path": "xilinx/UltraScale/general/rtl/InputBufferReg.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "IprogUltraScale", - "path": "xilinx/UltraScale/general/rtl/IprogUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Odelaye3Wrapper", - "path": "xilinx/UltraScale/general/rtl/Odelaye3Wrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "OutputBufferReg", - "path": "xilinx/UltraScale/general/rtl/OutputBufferReg.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SelectioDeserLaneUltraScale", - "path": "xilinx/UltraScale/general/rtl/SelectioDeserLaneUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SelectioDeserUltraScale", - "path": "xilinx/UltraScale/general/rtl/SelectioDeserUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GthUltraScaleQuadPll", - "path": "xilinx/UltraScale/gthUs/rtl/GthUltraScaleQuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gthe3ChannelDummy", - "path": "xilinx/UltraScale/gthUs/rtl/Gthe3ChannelDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClockManagerVersal", - "path": "xilinx/Versal/clocking/rtl/ClockManagerVersal.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp16FixedLatCore", - "path": "xilinx/Virtex5/gtp/rtl/Gtp16FixedLatCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GtpDualFixedLatCore", - "path": "xilinx/Virtex5/gtp/rtl/GtpDualFixedLatCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GtpRxCommaAligner", - "path": "xilinx/Virtex5/gtp/rtl/GtpRxCommaAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GtpTxPhaseAligner", - "path": "xilinx/Virtex5/gtp/rtl/GtpTxPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClkOutBufDiff", - "path": "xilinx/dummy/ClkOutBufDiffDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClkOutBufSingle", - "path": "xilinx/dummy/ClkOutBufSingleDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DeviceDna", - "path": "xilinx/dummy/DeviceDnaDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "IoBufWrapper", - "path": "xilinx/dummy/IoBufWrapperDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Iprog", - "path": "xilinx/dummy/IprogDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "OutputBufferReg", - "path": "xilinx/dummy/OutputBufferRegDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Srl16Delay", - "path": "xilinx/dummy/Srl16DelayDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "MicroblazeBasicCoreWrapper", - "path": "xilinx/general/microblaze/bypass/MicroblazeBasicCoreWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "MicroblazeBasicCoreWrapper", - "path": "xilinx/general/microblaze/generate/MicroblazeBasicCoreWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClkOutBufDiff", - "path": "xilinx/general/rtl/ClkOutBufDiff.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClkOutBufSingle", - "path": "xilinx/general/rtl/ClkOutBufSingle.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DeviceDna", - "path": "xilinx/general/rtl/DeviceDna.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GtRxAlignCheck", - "path": "xilinx/general/rtl/GtRxAlignCheck.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "IoBufWrapper", - "path": "xilinx/general/rtl/IoBufWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Iprog", - "path": "xilinx/general/rtl/Iprog.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SelectIoRxGearboxAligner", - "path": "xilinx/general/rtl/SelectIoRxGearboxAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Srl16Delay", - "path": "xilinx/general/rtl/Srl16Delay.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/7Series/Impl/images/UdpDebugBridge_stub.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/7Series/Stub/images/UdpDebugBridge_stub.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/UltraScale/Impl/images/UdpDebugBridge_stub.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/UltraScale/Stub/images/UdpDebugBridge_stub.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridgeWrapper", - "path": "xilinx/xvc-udp/dcp/core/UdpDebugBridgeWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiStreamSelector", - "path": "xilinx/xvc-udp/jtag/rtl/AxiStreamSelector.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxisJtagDebugBridge", - "path": "xilinx/xvc-udp/jtag/rtl/AxisJtagDebugBridge.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxisToJtag", - "path": "xilinx/xvc-udp/jtag/rtl/AxisToJtag.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxisToJtagCore", - "path": "xilinx/xvc-udp/jtag/rtl/AxisToJtagCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "JtagSerDesCore", - "path": "xilinx/xvc-udp/jtag/rtl/JtagSerDesCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DmaXvcWrapper", - "path": "xilinx/xvc-udp/rtl/DmaXvcWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridgeWrapper", - "path": "xilinx/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - } - ], - "unresolved_phase1_edges": [] -} diff --git a/docs/_meta/rtl_phase1_queue.md b/docs/_meta/rtl_phase1_queue.md deleted file mode 100644 index 6b39ac00f6..0000000000 --- a/docs/_meta/rtl_phase1_queue.md +++ /dev/null @@ -1,272 +0,0 @@ -# SURF RTL Phase-1 Queue - -## Scope -- Scan dirs: `base, axi, dsp, protocols, ethernet, devices, xilinx` -- Queue nodes are path-qualified RTL entity definitions, not bare entity names. -- Queue order is bottom-up: leaves first, higher-level assemblies later. -- Manual phase-1 deferrals and order overrides live in `docs/_meta/rtl_phase1_queue_overrides.json`. - -## Summary -- Phase-1 modules: `219` -- Phase-1 dependency edges: `392` -- Bottom-up layers: `10` -- Deferred modules: `632` -- Unresolved duplicate-name phase-1 edges: `0` -- Applied order overrides: `0` - -## Phase-1 Filters -- Force-included entities: - - None -- Force-included paths: - - None -- Deferred subsystems: - - `ethernet`: Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first. - - `protocols`: Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first. - - `devices`: Subsystem is currently dominated by vendor-heavy modules in phase 1. - - `xilinx`: Subsystem is currently dominated by vendor-heavy modules in phase 1. -- Deferred entities: - - `LutFixedDelay`: Depends on SinglePortRamPrimitive under the current open-source flow. -- Deferred exact paths: - - None -- Deferred path substrings: - - `axi/simlink/`: Simulation support models are not part of the synthesizable phase-1 queue. - - `/sim/`: Simulation-only support modules are not part of the synthesizable phase-1 queue. - - `/dummy/`: Dummy-backed variants are deferred from the phase-1 executable queue. - - `/altera/`: Vendor-specific implementation branches are deferred in phase 1. - - `/xilinx/`: Vendor-specific implementation branches are deferred in phase 1. - - `7Series`: Family-specific implementation branches are deferred in phase 1. - - `UltraScale`: Family-specific implementation branches are deferred in phase 1. - - `UltraScale+`: Family-specific implementation branches are deferred in phase 1. - - `/gth`: GT-family implementation branches are deferred in phase 1. - - `/gtp`: GT-family implementation branches are deferred in phase 1. - - `/gty`: GT-family implementation branches are deferred in phase 1. - - `/gtx`: GT-family implementation branches are deferred in phase 1. - -## Manual Order Overrides -- None - -## Unresolved Duplicate-Name Phase-1 Edges -- None - -## Flat Bottom-Up Order -| order | layer | entity | subsystem | path | instantiated_by_count | -| --- | --- | --- | --- | --- | --- | -| 1 | 0 | AxiLiteCrossbar | axi | axi/axi-lite/rtl/AxiLiteCrossbar.vhd | 3 | -| 2 | 0 | AxiLiteMaster | axi | axi/axi-lite/rtl/AxiLiteMaster.vhd | 6 | -| 3 | 0 | AxiLiteRegs | axi | axi/axi-lite/rtl/AxiLiteRegs.vhd | 2 | -| 4 | 0 | AxiLiteRespTimer | axi | axi/axi-lite/rtl/AxiLiteRespTimer.vhd | 1 | -| 5 | 0 | AxiLiteSlave | axi | axi/axi-lite/rtl/AxiLiteSlave.vhd | 2 | -| 6 | 0 | AxiLiteWriteFilter | axi | axi/axi-lite/rtl/AxiLiteWriteFilter.vhd | 1 | -| 7 | 0 | AxiVersion | axi | axi/axi-lite/rtl/AxiVersion.vhd | 1 | -| 8 | 0 | AxiStreamCombiner | axi | axi/axi-stream/rtl/AxiStreamCombiner.vhd | 1 | -| 9 | 0 | AxiStreamFlush | axi | axi/axi-stream/rtl/AxiStreamFlush.vhd | 1 | -| 10 | 0 | AxiStreamGearboxPack | axi | axi/axi-stream/rtl/AxiStreamGearboxPack.vhd | 1 | -| 11 | 0 | AxiStreamGearboxUnpack | axi | axi/axi-stream/rtl/AxiStreamGearboxUnpack.vhd | 1 | -| 12 | 0 | AxiStreamPipeline | axi | axi/axi-stream/rtl/AxiStreamPipeline.vhd | 18 | -| 13 | 0 | AxiStreamSplitter | axi | axi/axi-stream/rtl/AxiStreamSplitter.vhd | 1 | -| 14 | 0 | AxiStreamPkgWrapper | axi | axi/axi-stream/wrappers/AxiStreamPkgWrapper.vhd | 0 | -| 15 | 0 | AxiReadPathMux | axi | axi/axi4/rtl/AxiReadPathMux.vhd | 1 | -| 16 | 0 | AxiResize | axi | axi/axi4/rtl/AxiResize.vhd | 1 | -| 17 | 0 | AxiWritePathMux | axi | axi/axi4/rtl/AxiWritePathMux.vhd | 1 | -| 18 | 0 | AxiToAxiLite | axi | axi/bridge/rtl/AxiToAxiLite.vhd | 1 | -| 19 | 0 | AxiStreamDmaV2WriteMux | axi | axi/dma/rtl/v2/AxiStreamDmaV2WriteMux.vhd | 2 | -| 20 | 0 | CRC32Rtl | base | base/crc/rtl/CRC32Rtl.vhd | 0 | -| 21 | 0 | Crc32 | base | base/crc/rtl/Crc32.vhd | 1 | -| 22 | 0 | Crc32Parallel | base | base/crc/rtl/Crc32Parallel.vhd | 0 | -| 23 | 0 | SlvDelay | base | base/delay/rtl/SlvDelay.vhd | 0 | -| 24 | 0 | SlvDelayRam | base | base/delay/rtl/SlvDelayRam.vhd | 0 | -| 25 | 0 | SlvFixedDelay | base | base/delay/rtl/SlvFixedDelay.vhd | 0 | -| 26 | 0 | FifoOutputPipeline | base | base/fifo/rtl/FifoOutputPipeline.vhd | 7 | -| 27 | 0 | FifoRdFsm | base | base/fifo/rtl/inferred/FifoRdFsm.vhd | 2 | -| 28 | 0 | FifoWrFsm | base | base/fifo/rtl/inferred/FifoWrFsm.vhd | 2 | -| 29 | 0 | MasterRamIpIntegrator | base | base/general/ip_integrator/MasterRamIpIntegrator.vhd | 0 | -| 30 | 0 | SlaveRamIpIntegrator | base | base/general/ip_integrator/SlaveRamIpIntegrator.vhd | 0 | -| 31 | 0 | Arbiter | base | base/general/rtl/Arbiter.vhd | 0 | -| 32 | 0 | ClockDivider | base | base/general/rtl/ClockDivider.vhd | 0 | -| 33 | 0 | Gearbox | base | base/general/rtl/Gearbox.vhd | 1 | -| 34 | 0 | Heartbeat | base | base/general/rtl/Heartbeat.vhd | 1 | -| 35 | 0 | Mux | base | base/general/rtl/Mux.vhd | 0 | -| 36 | 0 | OneShot | base | base/general/rtl/OneShot.vhd | 0 | -| 37 | 0 | RegisterVector | base | base/general/rtl/RegisterVector.vhd | 0 | -| 38 | 0 | RstPipeline | base | base/general/rtl/RstPipeline.vhd | 3 | -| 39 | 0 | Scrambler | base | base/general/rtl/Scrambler.vhd | 0 | -| 40 | 0 | LutRam | base | base/ram/inferred/LutRam.vhd | 1 | -| 41 | 0 | SimpleDualPortRam | base | base/ram/inferred/SimpleDualPortRam.vhd | 6 | -| 42 | 0 | TrueDualPortRam | base | base/ram/inferred/TrueDualPortRam.vhd | 3 | -| 43 | 0 | Synchronizer | base | base/sync/rtl/Synchronizer.vhd | 13 | -| 44 | 0 | SynchronizerVector | base | base/sync/rtl/SynchronizerVector.vhd | 7 | -| 45 | 0 | FirFilterTap | dsp | dsp/generic/fixed/FirFilterTap.vhd | 2 | -| 46 | 1 | AxiLiteMasterProxy | axi | axi/axi-lite/rtl/AxiLiteMasterProxy.vhd | 1 | -| 47 | 1 | AxiLiteSequencerRam | axi | axi/axi-lite/rtl/AxiLiteSequencerRam.vhd | 1 | -| 48 | 1 | AxiStreamCompact | axi | axi/axi-stream/rtl/AxiStreamCompact.vhd | 1 | -| 49 | 1 | AxiStreamConcat | axi | axi/axi-stream/rtl/AxiStreamConcat.vhd | 1 | -| 50 | 1 | AxiStreamDeMux | axi | axi/axi-stream/rtl/AxiStreamDeMux.vhd | 2 | -| 51 | 1 | AxiStreamFrameRateLimiter | axi | axi/axi-stream/rtl/AxiStreamFrameRateLimiter.vhd | 1 | -| 52 | 1 | AxiStreamMux | axi | axi/axi-stream/rtl/AxiStreamMux.vhd | 2 | -| 53 | 1 | AxiStreamRepeater | axi | axi/axi-stream/rtl/AxiStreamRepeater.vhd | 1 | -| 54 | 1 | AxiStreamResize | axi | axi/axi-stream/rtl/AxiStreamResize.vhd | 2 | -| 55 | 1 | AxiStreamShift | axi | axi/axi-stream/rtl/AxiStreamShift.vhd | 3 | -| 56 | 1 | AxiStreamTrailerAppend | axi | axi/axi-stream/rtl/AxiStreamTrailerAppend.vhd | 1 | -| 57 | 1 | AxiStreamTrailerRemove | axi | axi/axi-stream/rtl/AxiStreamTrailerRemove.vhd | 1 | -| 58 | 1 | AxiRam | axi | axi/axi4/rtl/AxiRam.vhd | 1 | -| 59 | 1 | AxiLiteToIpBus | axi | axi/bridge/rtl/AxiLiteToIpBus.vhd | 1 | -| 60 | 1 | IpBusToAxiLite | axi | axi/bridge/rtl/IpBusToAxiLite.vhd | 1 | -| 61 | 1 | AxiStreamDmaV2WriteMuxIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2WriteMuxIpIntegrator.vhd | 0 | -| 62 | 1 | Crc32PolyWrapper | base | base/crc/wrappers/Crc32PolyWrapper.vhd | 0 | -| 63 | 1 | FifoSync | base | base/fifo/rtl/inferred/FifoSync.vhd | 2 | -| 64 | 1 | RstPipelineVector | base | base/general/rtl/RstPipelineVector.vhd | 0 | -| 65 | 1 | WatchDogRst | base | base/general/rtl/WatchDogRst.vhd | 0 | -| 66 | 1 | HeartbeatWrapper | base | base/general/wrappers/HeartbeatWrapper.vhd | 0 | -| 67 | 1 | DualPortRam | base | base/ram/inferred/DualPortRam.vhd | 4 | -| 68 | 1 | RstSync | base | base/sync/rtl/RstSync.vhd | 15 | -| 69 | 1 | SynchronizerEdge | base | base/sync/rtl/SynchronizerEdge.vhd | 1 | -| 70 | 1 | BoxcarIntegrator | dsp | dsp/generic/fixed/BoxcarIntegrator.vhd | 1 | -| 71 | 1 | DspAddSub | dsp | dsp/generic/fixed/DspAddSub.vhd | 1 | -| 72 | 1 | DspComparator | dsp | dsp/generic/fixed/DspComparator.vhd | 4 | -| 73 | 1 | DspPreSubMult | dsp | dsp/generic/fixed/DspPreSubMult.vhd | 0 | -| 74 | 1 | DspSquareDiffMult | dsp | dsp/generic/fixed/DspSquareDiffMult.vhd | 0 | -| 75 | 2 | MasterAxiLiteIpIntegrator | axi | axi/axi-lite/ip_integrator/MasterAxiLiteIpIntegrator.vhd | 9 | -| 76 | 2 | SlaveAxiLiteIpIntegrator | axi | axi/axi-lite/ip_integrator/SlaveAxiLiteIpIntegrator.vhd | 32 | -| 77 | 2 | AxiLiteAsync | axi | axi/axi-lite/rtl/AxiLiteAsync.vhd | 7 | -| 78 | 2 | MasterAxiStreamIpIntegrator | axi | axi/axi-stream/ip_integrator/MasterAxiStreamIpIntegrator.vhd | 30 | -| 79 | 2 | SlaveAxiStreamIpIntegrator | axi | axi/axi-stream/ip_integrator/SlaveAxiStreamIpIntegrator.vhd | 30 | -| 80 | 2 | AxiStreamGearbox | axi | axi/axi-stream/rtl/AxiStreamGearbox.vhd | 2 | -| 81 | 2 | AxiStreamPrbsFlowCtrl | axi | axi/axi-stream/rtl/AxiStreamPrbsFlowCtrl.vhd | 1 | -| 82 | 2 | AxiStreamTap | axi | axi/axi-stream/rtl/AxiStreamTap.vhd | 1 | -| 83 | 2 | MasterAxiIpIntegrator | axi | axi/axi4/ip_integrator/MasterAxiIpIntegrator.vhd | 16 | -| 84 | 2 | SlaveAxiIpIntegrator | axi | axi/axi4/ip_integrator/SlaveAxiIpIntegrator.vhd | 9 | -| 85 | 2 | AxiStreamDmaRead | axi | axi/dma/rtl/v1/AxiStreamDmaRead.vhd | 4 | -| 86 | 2 | AxiStreamDmaV2Read | axi | axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd | 3 | -| 87 | 2 | AxiStreamDmaV2Write | axi | axi/dma/rtl/v2/AxiStreamDmaV2Write.vhd | 3 | -| 88 | 2 | FifoAsync | base | base/fifo/rtl/inferred/FifoAsync.vhd | 4 | -| 89 | 2 | Debouncer | base | base/general/rtl/Debouncer.vhd | 1 | -| 90 | 2 | PwrUpRst | base | base/general/rtl/PwrUpRst.vhd | 0 | -| 91 | 2 | SynchronizerOneShot | base | base/sync/rtl/SynchronizerOneShot.vhd | 8 | -| 92 | 2 | BoxcarFilter | dsp | dsp/generic/fixed/BoxcarFilter.vhd | 0 | -| 93 | 3 | AxiLiteAsyncIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteAsyncIpIntegrator.vhd | 0 | -| 94 | 3 | AxiLiteMasterIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteMasterIpIntegrator.vhd | 0 | -| 95 | 3 | AxiLiteMasterProxyIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteMasterProxyIpIntegrator.vhd | 0 | -| 96 | 3 | AxiLiteRegsIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteRegsIpIntegrator.vhd | 0 | -| 97 | 3 | AxiLiteRespTimerIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteRespTimerIpIntegrator.vhd | 0 | -| 98 | 3 | AxiLiteSequencerRamIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteSequencerRamIpIntegrator.vhd | 0 | -| 99 | 3 | AxiLiteSlaveIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteSlaveIpIntegrator.vhd | 0 | -| 100 | 3 | AxiLiteWriteFilterIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteWriteFilterIpIntegrator.vhd | 0 | -| 101 | 3 | AxiVersionIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiVersionIpIntegrator.vhd | 0 | -| 102 | 3 | AxiStreamCombinerIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamCombinerIpIntegrator.vhd | 0 | -| 103 | 3 | AxiStreamCompactIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamCompactIpIntegrator.vhd | 0 | -| 104 | 3 | AxiStreamConcatIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamConcatIpIntegrator.vhd | 0 | -| 105 | 3 | AxiStreamDeMuxIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd | 0 | -| 106 | 3 | AxiStreamFlushIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamFlushIpIntegrator.vhd | 0 | -| 107 | 3 | AxiStreamFrameRateLimiterIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamFrameRateLimiterIpIntegrator.vhd | 0 | -| 108 | 3 | AxiStreamGearboxIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamGearboxIpIntegrator.vhd | 0 | -| 109 | 3 | AxiStreamGearboxPackIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamGearboxPackIpIntegrator.vhd | 0 | -| 110 | 3 | AxiStreamGearboxUnpackIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamGearboxUnpackIpIntegrator.vhd | 0 | -| 111 | 3 | AxiStreamMuxIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd | 0 | -| 112 | 3 | AxiStreamPipelineIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd | 0 | -| 113 | 3 | AxiStreamPrbsFlowCtrlIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamPrbsFlowCtrlIpIntegrator.vhd | 0 | -| 114 | 3 | AxiStreamRepeaterIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamRepeaterIpIntegrator.vhd | 0 | -| 115 | 3 | AxiStreamResizeIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamResizeIpIntegrator.vhd | 0 | -| 116 | 3 | AxiStreamShiftIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamShiftIpIntegrator.vhd | 0 | -| 117 | 3 | AxiStreamSplitterIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamSplitterIpIntegrator.vhd | 0 | -| 118 | 3 | AxiStreamTapIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamTapIpIntegrator.vhd | 0 | -| 119 | 3 | AxiStreamTrailerAppendIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamTrailerAppendIpIntegrator.vhd | 0 | -| 120 | 3 | AxiStreamTrailerRemoveIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamTrailerRemoveIpIntegrator.vhd | 0 | -| 121 | 3 | MasterAxiStreamTerminateIpIntegrator | axi | axi/axi-stream/ip_integrator/MasterAxiStreamTerminateIpIntegrator.vhd | 0 | -| 122 | 3 | SlaveAxiStreamTerminateIpIntegrator | axi | axi/axi-stream/ip_integrator/SlaveAxiStreamTerminateIpIntegrator.vhd | 0 | -| 123 | 3 | AxiStreamTimer | axi | axi/axi-stream/rtl/AxiStreamTimer.vhd | 1 | -| 124 | 3 | AxiRamIpIntegrator | axi | axi/axi4/ip_integrator/AxiRamIpIntegrator.vhd | 0 | -| 125 | 3 | AxiReadPathMuxIpIntegrator | axi | axi/axi4/ip_integrator/AxiReadPathMuxIpIntegrator.vhd | 0 | -| 126 | 3 | AxiResizeIpIntegrator | axi | axi/axi4/ip_integrator/AxiResizeIpIntegrator.vhd | 0 | -| 127 | 3 | AxiWritePathMuxIpIntegrator | axi | axi/axi4/ip_integrator/AxiWritePathMuxIpIntegrator.vhd | 0 | -| 128 | 3 | AxiRateGen | axi | axi/axi4/rtl/AxiRateGen.vhd | 1 | -| 129 | 3 | AxiLiteToIpBusIpIntegrator | axi | axi/bridge/ip_integrator/AxiLiteToIpBusIpIntegrator.vhd | 0 | -| 130 | 3 | AxiToAxiLiteIpIntegrator | axi | axi/bridge/ip_integrator/AxiToAxiLiteIpIntegrator.vhd | 0 | -| 131 | 3 | IpBusToAxiLiteIpIntegrator | axi | axi/bridge/ip_integrator/IpBusToAxiLiteIpIntegrator.vhd | 0 | -| 132 | 3 | AxiLiteToDrp | axi | axi/bridge/rtl/AxiLiteToDrp.vhd | 1 | -| 133 | 3 | AxiStreamDmaReadIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaReadIpIntegrator.vhd | 0 | -| 134 | 3 | AxiStreamDmaV2ReadIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2ReadIpIntegrator.vhd | 0 | -| 135 | 3 | AxiStreamDmaV2WriteIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2WriteIpIntegrator.vhd | 0 | -| 136 | 3 | Fifo | base | base/fifo/rtl/Fifo.vhd | 6 | -| 137 | 3 | AsyncGearbox | base | base/general/rtl/AsyncGearbox.vhd | 0 | -| 138 | 3 | DebouncerWrapper | base | base/general/wrappers/DebouncerWrapper.vhd | 0 | -| 139 | 3 | SyncTrigPeriod | base | base/sync/rtl/SyncTrigPeriod.vhd | 0 | -| 140 | 3 | SynchronizerFifo | base | base/sync/rtl/SynchronizerFifo.vhd | 11 | -| 141 | 3 | SynchronizerOneShotVector | base | base/sync/rtl/SynchronizerOneShotVector.vhd | 0 | -| 142 | 3 | FirFilterSingleChannel | dsp | dsp/generic/fixed/FirFilterSingleChannel.vhd | 0 | -| 143 | 4 | AxiDualPortRam | axi | axi/axi-lite/rtl/AxiDualPortRam.vhd | 6 | -| 144 | 4 | AxiLiteRingBuffer | axi | axi/axi-lite/rtl/AxiLiteRingBuffer.vhd | 1 | -| 145 | 4 | AxiStreamTimerIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamTimerIpIntegrator.vhd | 0 | -| 146 | 4 | AxiStreamScatterGather | axi | axi/axi-stream/rtl/AxiStreamScatterGather.vhd | 1 | -| 147 | 4 | AxiRateGenIpIntegrator | axi | axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd | 0 | -| 148 | 4 | AxiMemTester | axi | axi/axi4/rtl/AxiMemTester.vhd | 1 | -| 149 | 4 | AxiLiteToDrpIpIntegrator | axi | axi/bridge/ip_integrator/AxiLiteToDrpIpIntegrator.vhd | 0 | -| 150 | 4 | SlvArraytoAxiLite | axi | axi/bridge/rtl/SlvArraytoAxiLite.vhd | 1 | -| 151 | 4 | AxiStreamDmaV2Desc | axi | axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd | 2 | -| 152 | 4 | AxiStreamDmaV2Fifo | axi | axi/dma/rtl/v2/AxiStreamDmaV2Fifo.vhd | 1 | -| 153 | 4 | SlvDelayFifo | base | base/delay/rtl/SlvDelayFifo.vhd | 0 | -| 154 | 4 | FifoCascade | base | base/fifo/rtl/FifoCascade.vhd | 8 | -| 155 | 4 | FwftCntWrapper | base | base/fifo/wrappers/FwftCntWrapper.vhd | 0 | -| 156 | 4 | SyncClockFreq | base | base/sync/rtl/SyncClockFreq.vhd | 1 | -| 157 | 4 | SyncMinMax | base | base/sync/rtl/SyncMinMax.vhd | 2 | -| 158 | 4 | SynchronizerOneShotCnt | base | base/sync/rtl/SynchronizerOneShotCnt.vhd | 1 | -| 159 | 5 | AxiDualPortRamIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd | 0 | -| 160 | 5 | AxiLiteCrossbarIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteCrossbarIpIntegrator.vhd | 0 | -| 161 | 5 | AxiLiteRingBufferIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteRingBufferIpIntegrator.vhd | 0 | -| 162 | 5 | AxiLiteFifoPop | axi | axi/axi-lite/rtl/AxiLiteFifoPop.vhd | 1 | -| 163 | 5 | AxiLiteFifoPush | axi | axi/axi-lite/rtl/AxiLiteFifoPush.vhd | 1 | -| 164 | 5 | AxiLiteFifoPushPop | axi | axi/axi-lite/rtl/AxiLiteFifoPushPop.vhd | 2 | -| 165 | 5 | AxiStreamScatterGatherIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamScatterGatherIpIntegrator.vhd | 0 | -| 166 | 5 | AxiStreamFifoV2 | axi | axi/axi-stream/rtl/AxiStreamFifoV2.vhd | 7 | -| 167 | 5 | AxiMemTesterIpIntegrator | axi | axi/axi4/ip_integrator/AxiMemTesterIpIntegrator.vhd | 0 | -| 168 | 5 | AxiReadPathFifo | axi | axi/axi4/rtl/AxiReadPathFifo.vhd | 3 | -| 169 | 5 | AxiWritePathFifo | axi | axi/axi4/rtl/AxiWritePathFifo.vhd | 3 | -| 170 | 5 | SlvArraytoAxiLiteIpIntegrator | axi | axi/bridge/ip_integrator/SlvArraytoAxiLiteIpIntegrator.vhd | 0 | -| 171 | 5 | AxiStreamDmaV2DescIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2DescIpIntegrator.vhd | 0 | -| 172 | 5 | AxiStreamDmaV2FifoIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2FifoIpIntegrator.vhd | 0 | -| 173 | 5 | AxiStreamDmaV2 | axi | axi/dma/rtl/v2/AxiStreamDmaV2.vhd | 1 | -| 174 | 5 | FifoMux | base | base/fifo/rtl/FifoMux.vhd | 0 | -| 175 | 5 | SyncTrigRate | base | base/sync/rtl/SyncTrigRate.vhd | 3 | -| 176 | 5 | SynchronizerOneShotCntVector | base | base/sync/rtl/SynchronizerOneShotCntVector.vhd | 2 | -| 177 | 5 | SyncClockFreqWrapper | base | base/sync/wrappers/SyncClockFreqWrapper.vhd | 0 | -| 178 | 5 | FirFilterMultiChannel | dsp | dsp/generic/fixed/FirFilterMultiChannel.vhd | 0 | -| 179 | 6 | AxiLiteFifoPopIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteFifoPopIpIntegrator.vhd | 0 | -| 180 | 6 | AxiLiteFifoPushIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteFifoPushIpIntegrator.vhd | 0 | -| 181 | 6 | AxiLiteFifoPushPopIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteFifoPushPopIpIntegrator.vhd | 0 | -| 182 | 6 | AxiStreamFifoV2IpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd | 0 | -| 183 | 6 | AxiStreamBatchingFifo | axi | axi/axi-stream/rtl/AxiStreamBatchingFifo.vhd | 1 | -| 184 | 6 | AxiStreamMon | axi | axi/axi-stream/rtl/AxiStreamMon.vhd | 2 | -| 185 | 6 | AxiStreamRingBuffer | axi | axi/axi-stream/rtl/AxiStreamRingBuffer.vhd | 1 | -| 186 | 6 | AxiReadPathFifoIpIntegrator | axi | axi/axi4/ip_integrator/AxiReadPathFifoIpIntegrator.vhd | 0 | -| 187 | 6 | AxiWritePathFifoIpIntegrator | axi | axi/axi4/ip_integrator/AxiWritePathFifoIpIntegrator.vhd | 0 | -| 188 | 6 | AxiReadEmulate | axi | axi/axi4/rtl/AxiReadEmulate.vhd | 1 | -| 189 | 6 | AxiRingBuffer | axi | axi/axi4/rtl/AxiRingBuffer.vhd | 1 | -| 190 | 6 | AxiWriteEmulate | axi | axi/axi4/rtl/AxiWriteEmulate.vhd | 1 | -| 191 | 6 | AxiStreamDmaV2IpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2IpIntegrator.vhd | 0 | -| 192 | 6 | AxiStreamDmaRingRead | axi | axi/dma/rtl/v1/AxiStreamDmaRingRead.vhd | 1 | -| 193 | 6 | AxiStreamDmaWrite | axi | axi/dma/rtl/v1/AxiStreamDmaWrite.vhd | 4 | -| 194 | 6 | SyncStatusVector | base | base/sync/rtl/SyncStatusVector.vhd | 2 | -| 195 | 6 | SyncTrigRateVector | base | base/sync/rtl/SyncTrigRateVector.vhd | 1 | -| 196 | 6 | SyncTrigRateWrapper | base | base/sync/wrappers/SyncTrigRateWrapper.vhd | 0 | -| 197 | 6 | SynchronizerOneShotCntVectorFlatWrapper | base | base/sync/wrappers/SynchronizerOneShotCntVectorFlatWrapper.vhd | 0 | -| 198 | 7 | AxiLiteRamSyncStatusVector | axi | axi/axi-lite/rtl/AxiLiteRamSyncStatusVector.vhd | 1 | -| 199 | 7 | AxiStreamBatchingFifoIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamBatchingFifoIpIntegrator.vhd | 0 | -| 200 | 7 | AxiStreamMonIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamMonIpIntegrator.vhd | 0 | -| 201 | 7 | AxiStreamRingBufferIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamRingBufferIpIntegrator.vhd | 0 | -| 202 | 7 | AxiStreamMonAxiL | axi | axi/axi-stream/rtl/AxiStreamMonAxiL.vhd | 2 | -| 203 | 7 | AxiReadEmulateIpIntegrator | axi | axi/axi4/ip_integrator/AxiReadEmulateIpIntegrator.vhd | 0 | -| 204 | 7 | AxiRingBufferIpIntegrator | axi | axi/axi4/ip_integrator/AxiRingBufferIpIntegrator.vhd | 0 | -| 205 | 7 | AxiWriteEmulateIpIntegrator | axi | axi/axi4/ip_integrator/AxiWriteEmulateIpIntegrator.vhd | 0 | -| 206 | 7 | AxiStreamDmaRingReadIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaRingReadIpIntegrator.vhd | 0 | -| 207 | 7 | AxiStreamDmaWriteIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaWriteIpIntegrator.vhd | 0 | -| 208 | 7 | AxiStreamDma | axi | axi/dma/rtl/v1/AxiStreamDma.vhd | 1 | -| 209 | 7 | AxiStreamDmaFifo | axi | axi/dma/rtl/v1/AxiStreamDmaFifo.vhd | 1 | -| 210 | 7 | AxiStreamDmaRingWrite | axi | axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd | 1 | -| 211 | 7 | SyncStatusVectorFlatWrapper | base | base/sync/wrappers/SyncStatusVectorFlatWrapper.vhd | 0 | -| 212 | 7 | SyncTrigRateVectorFlatWrapper | base | base/sync/wrappers/SyncTrigRateVectorFlatWrapper.vhd | 0 | -| 213 | 8 | AxiLiteRamSyncStatusVectorIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteRamSyncStatusVectorIpIntegrator.vhd | 0 | -| 214 | 8 | AxiStreamMonAxiLIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamMonAxiLIpIntegrator.vhd | 0 | -| 215 | 8 | AxiMonAxiL | axi | axi/axi4/rtl/AxiMonAxiL.vhd | 1 | -| 216 | 8 | AxiStreamDmaFifoIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaFifoIpIntegrator.vhd | 0 | -| 217 | 8 | AxiStreamDmaIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaIpIntegrator.vhd | 0 | -| 218 | 8 | AxiStreamDmaRingWriteIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaRingWriteIpIntegrator.vhd | 0 | -| 219 | 9 | AxiMonAxiLIpIntegrator | axi | axi/axi4/ip_integrator/AxiMonAxiLIpIntegrator.vhd | 0 | diff --git a/docs/_meta/rtl_phase1_queue_overrides.json b/docs/_meta/rtl_phase1_queue_overrides.json deleted file mode 100644 index 474d21dbc1..0000000000 --- a/docs/_meta/rtl_phase1_queue_overrides.json +++ /dev/null @@ -1,85 +0,0 @@ -{ - "force_include_entities": [], - "force_include_paths": [], - "deferred_subsystems": [ - { - "name": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "name": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "name": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "name": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - } - ], - "deferred_entities": [ - { - "entity": "LutFixedDelay", - "reason": "Depends on SinglePortRamPrimitive under the current open-source flow." - } - ], - "deferred_paths": [], - "deferred_path_substrings": [ - { - "pattern": "protocols/pgp/pgp3/", - "reason": "PGP3 is intentionally deferred for now so current protocol work stays on pgp2b/pgp2fc/pgp4 and shared PGP blocks." - }, - { - "pattern": "axi/simlink/", - "reason": "Simulation support models are not part of the synthesizable phase-1 queue." - }, - { - "pattern": "/sim/", - "reason": "Simulation-only support modules are not part of the synthesizable phase-1 queue." - }, - { - "pattern": "/dummy/", - "reason": "Dummy-backed variants are deferred from the phase-1 executable queue." - }, - { - "pattern": "/altera/", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "/xilinx/", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "7Series", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "UltraScale", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "UltraScale+", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "/gth", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gtp", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gty", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gtx", - "reason": "GT-family implementation branches are deferred in phase 1." - } - ], - "preferred_paths_by_entity": {}, - "order_overrides": [] -} diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md deleted file mode 100644 index 67ca69e84f..0000000000 --- a/docs/_meta/rtl_regression_handoff.md +++ /dev/null @@ -1,225 +0,0 @@ -# SURF RTL Regression Handoff - -## Objective -- Build a repo-wide regression system for synthesizable SURF RTL. -- Keep all executable test logic in Python. -- Use `pytest + cocotb + GHDL + ruckus`. -- Keep VHDL only for wrappers, shims, and required simulation models. - -## Chosen Constraints -- Python-only test logic -- VHDL wrappers allowed -- Whole-repo target -- Vendor-heavy modules deferred in phase 1 -- Comment new Python regression code at a tutorial level, assuming the reader may be new to cocotb -- Give each Python regression the normal SURF/SLAC file header and two distinct comment layers: a module-specific `Test methodology` block under that header and tutorial-style comments in the executable code body -- Give each checked-in cocotb-facing `*IpIntegrator.vhd` wrapper the normal SURF file banner plus section comments for shim setup, DUT instantiation, and any flattening/status wiring -- For any VHDL file created or edited during this work, run `./.venv/bin/vsg` with `vsg-linter.yml`, the same config CI uses, and use `--fix`/autofix on fixable issues before moving on -- Treat VHDL packages as transitively covered unless a behavioral function/procedure needs a dedicated wrapper -- Treat stale simulator cleanup as part of task completion: after any `pytest`, cocotb, GHDL, or similar launched verification step, sweep for leftover child processes and kill them before moving on - -## Quick Resume Snapshot -- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, the current Ethernet coverage spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the pure-VHDL RoCEv2 quartet (`EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator`), and a broader user-directed CoaXPress pure-VHDL wave is now checked in under `tests/protocols/coaxpress/`. The validated CoaXPress subset now includes the receive quartet `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, and `CoaXPressRxHsFsm`, the receive assembly `CoaXPressRx`, the transmit/bridge helpers `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressOverFiberBridgeRx`, and `CoaXPressOverFiberBridgeTx`, and the higher-level assemblies `CoaXPressTx`, `CoaXPressCore`, and `CoaXPressOverFiberBridge`. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. -- Current axi frontier: complete for the intended simulator-friendly pass in this branch snapshot; do not resume from the older stale `AxiResize` note. -- Current validated-open issues: - - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core` remain untouched in phase 1, while the remaining RoCEv2 gap is the mixed-language bench path for the five RTL entities that instantiate generated submodules: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`. - - `EthMacRxImportXlgmii` and `EthMacTxExportXlgmii` are still placeholder no-op RTL; the checked-in tests now lock down that inert contract instead of claiming functional XLGMII support. - - The remaining CoaXPress pure-VHDL gap is now `CoaXPressConfig`. The current CoaXPress receive benches now include a dual-lane `CoaXPressRxHsFsm` step/alignment case and a dual-lane `CoaXPressRx` lane-rotation case, but the receive side is still intentionally mixed-depth: top-level event handling only proves the current packet-prefix contract, and the multi-lane assembly checks still stop short of exhaustive per-lane stress coverage. - - `tests/protocols/coaxpress/test_CoaXPressConfig.py` is intentionally checked in as a skipped investigation bench. When driven through the real SRP ingress, the current `CoaXPressConfig` / `SrpV3AxiLite` integration does not complete the request path within the bench timeout, so treat that as a likely RTL or integration defect to debug before re-enabling active assertions there. - - `tests/protocols/coaxpress/test_CoaXPressCore.py` now also carries an opt-in skipped known-issue bench for RX backpressure vs. FSM-error behavior. Enable it with `RUN_KNOWN_ISSUE_TESTS=1` and optionally shrink the load with `CXP_RX_OVERFLOW_STORM_FRAME_COUNT=`. The current local reproduction under sustained `M_DATA_TREADY=0` and repeated one-line image frames observed `RxFsmErrorCnt=2` while `RxOverflowCnt=0` at `96` frames, and a narrowing sweep showed no repro at `48` frames but a repro by `72` frames with `RxFsmErrorCnt=1` while `RxOverflowCnt=0`. That is closer to the user report than the earlier directed single-error tests and should be treated as a likely RTL defect under investigation. - - For future CoaXPress work, treat the named packet classes and control bytes in `tests/protocols/coaxpress/coaxpress_test_utils.py` as shared spec anchors, not as optional local style. Those constants were normalized against the same `CXP-001-2021` / `CXPR-008-2021` references cited in `CoaXPressPkg.vhd`. Keep the packet-layer names aligned to the spec even where current RTL ports still use legacy `eventAck` naming on the receive side: `0x07` is an event packet and `0x08` is an event acknowledgment. - - The current receive benches are intentionally mixed-depth: control-ack traffic is now driven with fuller spec-shaped framing, but the checked-in `CoaXPressRxLane` / `CoaXPressRx` event tests still only prove the current RTL contract of consuming the event prefix through the Packet Tag field. Do not describe that as full event-payload coverage until the RTL/parser is expanded and the bench follows it. -- Current planning discipline: - - Use manual user-directed area selection as the active source of truth for what to work on next. - - Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the actual validated branch frontier. - - Keep the graph and queue artifacts only as historical provenance or optional analysis context; do not use them as the next-module selector unless the user explicitly opts back into queue-driven planning. -- Current wrapper discipline: - - Prefer the existing subsystem `ip_integrator/` shim layers over bespoke record flattening. - - Keep first-pass wrapper benches intentionally narrow and document any omitted branches explicitly. - - Use `start_lockstep_clocks()` when a DUT depends on truly shared clock edges. - - Prefer explicit short sim-build keys for generated-wrapper benches when case metadata would otherwise create fragile build paths. - - When a wrapper is checked in, write it like the surrounding repo HDL: include the SLAC/SURF banner and enough section comments that a new session can identify the shim, DUT, and flattening regions quickly. - - For the current Ethernet slice, the checked-in wrappers under `ethernet/EthMacCore/wrappers/`, `ethernet/RawEthFramer/wrappers/`, `ethernet/UdpEngine/wrappers/`, `ethernet/IpV4Engine/wrappers/`, and the new `ethernet/RoCEv2/wrappers/` leaf adapters are the expected cocotb surfaces. Keep using those subsystem-local wrappers rather than rebuilding record-packing logic in Python. -- Current cocotb-file discipline: - - New test files should start with the standard SURF/SLAC header block. - - The `Test methodology` block belongs directly under that header. - - In-body tutorial comments are still required; the methodology block does not replace them. - -## Session Learnings To Preserve -- Start with the smallest stable wrapper that exposes the DUT cleanly to cocotb. Reuse the existing subsystem `ip_integrator/` shims before inventing bespoke flattening or a new subsystem-local wrapper. -- Prefer checked-in subsystem-local wrappers for durable integration patterns, including simulator-hostile generic adapters. -- If a Python cocotb file is permanent enough to check in, do not leave it with a custom or abbreviated header. Use the standard repo header immediately, then add the methodology block and tutorial comments in the same first pass. -- If a wrapper is permanent enough to check in, do not leave it as a bare anonymous adapter. Add the standard SURF banner and short section comments immediately, not as a cleanup pass later. -- For AXI and AXI-Lite benches, the practical first-pass shape is usually: - - cocotb protocol master on the control/request side, - - cocotb RAM or simple protocol model on the generated/response side, - - lightweight monitors on accepted handshakes when timing or burst shape matters. -- Do not rely on final memory contents alone when the contract includes timing-visible behavior. Record accepted handshakes if the bench is supposed to prove spacing, burst length, sideband propagation, partial-last-beat strobes, or arbitration order. -- For `COMMON_CLK_G` style wrappers, use one shared clock coroutine via `start_lockstep_clocks()` when the RTL expects true shared edges rather than merely equal nominal periods. -- For first-pass wrapper benches, prove the externally visible stable path first and defer shakier simulator-sensitive branches explicitly in the docs instead of stretching one bench to cover everything. -- `AxiStreamDmaV2Read` needed a real RTL/runtime fix rather than a bench workaround: keep the bounded byte-count conversion fix in `axi/axi4/rtl/AxiPkg.vhd` and the direct terminal-mask generation in `axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd`. The current wrapper only exposes an 8-bit `TUSER`, so the observable contract in the checked-in bench is first-user propagation plus payload/keep/id/dest and descriptor return fields. -- `tests/dsp/generic/dsp_test_utils.py` is now the shared home for DSP-specific signed helpers, rolling reference models, cocotb clock-settle timing, and generated FIR wrappers. Reuse it instead of cloning DSP arithmetic or wrapper boilerplate. -- Before writing new AXI-Lite, AXI Stream, SSI, or ethernet transaction code, search the nearest subsystem `tests/` package for an existing helper module first. Future sessions should assume that a reusable helper probably already exists and should only write new transaction plumbing after confirming the local helper layer is insufficient. -- `tests/ethernet/EthMacCore/ethmac_test_utils.py` is now the shared home for the current Ethernet MAC slice: flat EMAC beat helpers, Ethernet/IPv4/UDP packet builders, checksum reference code, MAC-config byte-order helpers, and minimum-frame padding helpers. Reuse it instead of cloning packet or sideband plumbing across `EthMacCore` benches. -- Do not replace `ethernet/RoCEv2/blue-*` with local test doubles when the target boundary is `ethernet/RoCEv2/rtl`. The intended shape is one cocotb bench per RTL entity in `ethernet/RoCEv2/rtl`, with `blue-crc`, `blue-rdma`, and `blue-lib` used as real transitive dependencies where instantiated. Under the current local toolchain only `ghdl` is available, so the pure-VHDL quartet is covered now and the remaining five mixed-language entities stay open until the runner supports real VHDL+Verilog simulation. -- RoCEv2 RTL entity matrix for the next session: - - Covered now with the current GHDL-only flow: `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, `RoceConfigurator` - - Still required, but must use real generated dependencies: `EthMacCrcAxiStreamWrapperSend` -> `blue-crc/mkCrcRawAxiStreamCustomSend.v`, `EthMacCrcAxiStreamWrapperRecv` -> `blue-crc/mkCrcRawAxiStreamCustomRecv.v`, `EthMacTxRoCEv2` -> send CRC wrapper, `EthMacRxRoCEv2` -> recv CRC wrapper, `RoceEngineWrapper` -> `blue-rdma/mkAxisTransportLayer.v` plus `blue-lib/` -- `tests/ethernet/RawEthFramer/raw_eth_test_utils.py` now holds the shared raw-Ethernet helper pieces: flat app-side beat helpers, raw-Ethernet header/frame builders, and lookup-handshake utilities reused by the `RawEthFramer`, `RawEthFramerRx`, and `RawEthFramerTx` benches. -- `tests/ethernet/UdpEngine/udp_test_utils.py` is now the shared home for the UDP slice: legacy-address constants, pseudo-frame builders, DHCP option helpers, and the common cocotb bench setup for the `ArpIpTable`, `UdpEngine*`, and `UdpEngineWrapper*` wrappers. Reuse it instead of rebuilding IPv4/UDP helper glue in each test module. -- `tests/ethernet/IpV4Engine/ipv4_test_utils.py` is now the shared home for the IPv4 slice: packet/header builders and common cocotb bench setup for the `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, and `IpV4Engine*` wrappers. Reuse it instead of cloning IPv4 framing helpers across that directory. -- `tests/protocols/ssi/ssi_test_utils.py` is the shared home for SSI transaction work: flat SSI endpoints, beat/frame helpers, contiguous-frame send, receive/no-output utilities, and `SOF`/`EOFE`-aware assertions. Use it instead of open-coding SSI handshake loops or terminal-flag checks. -- `tests/protocols/coaxpress/coaxpress_test_utils.py` is now the shared home for the CoaXPress leaf/assembly slice: protocol constants, repeated-byte word builders, byte-splitting helpers, wide-word packing helpers, basic clock/reset helpers, and simple pulse-capture utilities for the raw-word wrappers. Reuse it instead of cloning CoaXPress symbol constants or one-cycle output capture loops across future CoaXPress benches. -- Keep future CoaXPress benches explicit about the boundary between normative spec behavior and current RTL-contract-only coverage. For top-level and over-fiber work in particular, the governing references are the CoaXPress protocol spec (`CXP-001-2021`) and the CoaXPress-over-Fiber bridge spec (`CXPR-008-2021`); use the shared helper names for packet classes and control symbols instead of sprinkling raw byte literals through new tests. -- Across the AXI slices, prefer the subsystem helper paths that already exist for register transactions, frame movement, and setup. In practice that means reusing helpers such as `tests/common/regression_utils.py`, the AXI/ethernet subsystem utility modules, and any nearby module-family helpers before inventing a one-off local transaction wrapper. -- The current `EthMacCore` slice is intentionally a checked-in-wrapper-first rollout, not a cocotb-generated-wrapper experiment. Keep new Ethernet work on that same pattern unless the simulator forces a very local generic adapter. -- The XGMII import/export loopback behavior differs from the GMII path when `phyReady` drops mid-traffic: the blocked frame is retained and drains after link recovery, padded to Ethernet's minimum frame size if it was short. The GMII path drops that blocked frame. Future import/export coverage should preserve that distinction instead of forcing one common expectation. -- The current `EthMacRxImportXlgmii.vhd` and `EthMacTxExportXlgmii.vhd` leaves are placeholders: they drive no data-path activity and never pulse the count/status outputs. Future work should treat functional XLGMII support as an RTL gap, not as a missing bench. -- `EthMacRxCsum` reliably raises `IPERR` on a bad IPv4 header checksum, but the checked-in wrapper contract does not currently require `EOFE` for that case. Keep the negative test aligned to the real observable contract rather than to a stronger assumption. -- The RX/TX shift benches need a small idle-plus-settle gap before changing runtime shift controls because the underlying `AxiStreamShift` samples those controls while idle. Preserve that guardrail if those benches are refactored or expanded. -- `EthMacRxBypass` compares the EtherType field in the flattened EMAC byte-lane order, not normal wire-order host integer order. In practice that means a wire EtherType like `0x9000` must be compared as `x"0090"` at the wrapper/DUT generic boundary, just as `0x88B5` appears as `x"B588"` in the existing wrappers. -- Do not leave stale simulation trees behind between tasks. If a verification command launched `pytest`, cocotb, GHDL, or wrapper executables, treat post-run process cleanup as mandatory before the next edit or test cycle. - -## Current Status -Planning is complete and implementation is well underway. The agreed direction is a Python-only executable regression framework with tiered `smoke` and `functional` coverage. Existing VHDL TBs are reference material only and should be rewritten in Python when migrated, unless a thin wrapper is still useful for cocotb access. - -The repo now has the initial handoff artifacts, a checked-in inventory scaffold at `docs/_meta/rtl_regression_inventory.yaml`, and local bootstrap helpers in `scripts/setup_regression_env.sh` plus `.vscode/tasks.json`. The first pilot modules were `FifoAsync`, `AxiStreamFifoV2`, and `AxiLiteAsync`, and the work has since moved into a graph-guided bottom-up rollout across `base/`. - -The local machine now has `ghdl`, a working `.venv`, the Python regression packages, a repo-local `ruckus` link to `~/ruckus`, and a successful `make MODULES="$PWD" import` run. Local environment bootstrap is no longer the blocker. The first shared-helper-based pilot regression now exists in `tests/base/fifo/test_FifoAsync.py` and passes locally. - -New regressions are now being organized by subsystem under `tests/`, with shared helpers in `tests/common/`. The `FifoAsync` pilot lives in `tests/base/fifo/test_FifoAsync.py`, and `AxiStreamFifoV2` now lives in `tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py`. New work should follow that package layout instead of adding more flat files under `tests/`. - -`FifoAsync` now has a validated expanded 12-case matrix, `FifoSync` has a validated expanded 11-case matrix, `Synchronizer` and `SynchronizerVector` now each have validated 6-case matrices under `tests/base/sync/`, `RstPipeline` has a validated 4-case matrix under `tests/base/general/`, `SimpleDualPortRam` has a validated 5-case matrix under `tests/base/ram/`, `FifoOutputPipeline` has a validated 5-case matrix under `tests/base/fifo/`, and `FifoWrFsm` has a validated 4-case matrix under `tests/base/fifo/`. - -The next graph-guided 10-module follow-on is also now in place: `Crc32Parallel`, `Crc32`, `CRC32Rtl`, `RstSync`, `PwrUpRst`, `SynchronizerEdge`, `SynchronizerOneShot`, `TrueDualPortRam`, `LutRam`, and `FifoRdFsm`. The combined validation command for that batch is `./.venv/bin/python -m pytest -v tests/base/crc/test_Crc32Parallel.py tests/base/crc/test_Crc32.py tests/base/crc/test_CRC32Rtl.py tests/base/sync/test_RstSync.py tests/base/general/test_PwrUpRst.py tests/base/sync/test_SynchronizerEdge.py tests/base/sync/test_SynchronizerOneShot.py tests/base/ram/test_TrueDualPortRam.py tests/base/ram/test_LutRam.py tests/base/fifo/test_FifoRdFsm.py`, and it currently passes with `38 passed`. - -The next 15-module `base/` general/delay/sync batch is now also implemented and validated: `Arbiter`, `ClockDivider`, `Debouncer`, `Gearbox`, `Heartbeat`, `Mux`, `OneShot`, `RegisterVector`, `RstPipelineVector`, `Scrambler`, `WatchDogRst`, `SlvDelay`, `SlvFixedDelay`, `SynchronizerFifo`, and `SynchronizerOneShotCnt`. The combined validation command for that batch is `./.venv/bin/python -m pytest -n 0 -q tests/base/general/test_Arbiter.py tests/base/general/test_ClockDivider.py tests/base/general/test_Debouncer.py tests/base/general/test_Gearbox.py tests/base/general/test_Heartbeat.py tests/base/general/test_Mux.py tests/base/general/test_OneShot.py tests/base/general/test_RegisterVector.py tests/base/general/test_RstPipelineVector.py tests/base/general/test_Scrambler.py tests/base/general/test_WatchDogRst.py tests/base/delay/test_SlvDelay.py tests/base/delay/test_SlvFixedDelay.py tests/base/sync/test_SynchronizerFifo.py tests/base/sync/test_SynchronizerOneShotCnt.py`, and it currently passes with `41 passed`. - -The next 10-module wrapper/integration batch is now also implemented and validated: `DspComparator`, `Fifo`, `FifoCascade`, `FifoMux`, `AsyncGearbox`, `SynchronizerOneShotVector`, `SynchronizerOneShotCntVector`, `SyncStatusVector`, `SyncTrigPeriod`, and `SyncMinMax`. The combined validation command for that batch is `./.venv/bin/python -m pytest -n 0 -q tests/dsp/generic/test_DspComparator.py tests/base/fifo/test_Fifo.py tests/base/fifo/test_FifoCascade.py tests/base/fifo/test_FifoMux.py tests/base/general/test_AsyncGearbox.py tests/base/sync/test_SynchronizerOneShotVector.py tests/base/sync/test_SynchronizerOneShotCntVector.py tests/base/sync/test_SyncStatusVector.py tests/base/sync/test_SyncTrigPeriod.py tests/base/sync/test_SyncMinMax.py`, and it currently passes with `18 passed`. - -The remaining practical non-vendor, non-dummy `base/` modules are now also implemented and validated: `MasterRamIpIntegrator`, `SlaveRamIpIntegrator`, `DualPortRam`, `SlvDelayRam`, `SlvDelayFifo`, `SyncClockFreq`, `SyncTrigRate`, and `SyncTrigRateVector`. The combined validation command for that batch is `./.venv/bin/python -m pytest -n 0 -q tests/base/general/test_MasterRamIpIntegrator.py tests/base/general/test_SlaveRamIpIntegrator.py tests/base/ram/test_DualPortRam.py tests/base/delay/test_SlvDelayRam.py tests/base/delay/test_SlvDelayFifo.py tests/base/sync/test_SyncClockFreq.py tests/base/sync/test_SyncTrigRate.py tests/base/sync/test_SyncTrigRateVector.py`, and it currently passes with `15 passed`. - -`Crc32` now covers multiple common 32-bit polynomials instead of only the default IEEE CRC-32 polynomial. That test uses a thin wrapper at `base/crc/wrappers/Crc32PolyWrapper.vhd` because the local GHDL flow rejects direct command-line overrides of the `CRC_POLY_G : slv(31 downto 0)` generic. Pytest still defaults to `-n auto --dist=worksteal` through `pytest.ini` so parameterized regressions fan out across worker processes by default. - -The project now also has a shared helper path in `tests/common/regression_utils.py` for test scaffolding, but the wrapper policy is to keep durable cocotb-facing HDL shims checked in under subsystem-local `wrappers/` or `ip_integrator/` folders. `Heartbeat` and `Debouncer` remain useful examples of very small wrappers, but new permanent generic-adapter shims should follow the checked-in subsystem-local pattern. - -`tests/common/regression_utils.py` now also includes `start_lockstep_clocks()` for DUTs whose generics assume truly common clocks in both ports. Use that helper instead of launching two same-period clocks independently when the RTL assumes shared edge identity. - -`ethernet/EthMacCore/` now has checked-in regression coverage under `tests/ethernet/EthMacCore/` for both the original leaf slice and the deeper assembly layer. The current benches cover `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, `EthMacTop`, `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, `EthMacTxFifo`, `EthMacRxBypass`, and `EthMacTxBypass`. The import/export benches now also explicitly encode the current placeholder `XLGMII` contract so future functional XLGMII RTL work will show up as a deliberate expectation change instead of an accidental gap. The current Ethernet wrappers live under `ethernet/EthMacCore/wrappers/` and should be treated as the stable cocotb-facing surfaces for further `EthMacCore` work. - -`ethernet/UdpEngine/` and `ethernet/IpV4Engine/` also received a thin-area cleanup pass on this branch. The `UdpEngine` top/wrapper benches now cover additional client/server routing paths beyond the earlier single happy-path smoke, while `IpV4Engine` now has a top-level protocol-TX path and deeper `IcmpEngine` negative/recovery coverage. The combined local validation command for that focused follow-up is `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/EthMacCore/test_EthMacRxImport.py tests/ethernet/EthMacCore/test_EthMacTxExport.py tests/ethernet/EthMacCore/test_EthMacRxBypass.py tests/ethernet/EthMacCore/test_EthMacTxBypass.py tests/ethernet/UdpEngine/test_UdpEngine.py tests/ethernet/UdpEngine/test_UdpEngineWrapper.py tests/ethernet/IpV4Engine/test_IpV4Engine.py tests/ethernet/IpV4Engine/test_IcmpEngine.py`, and it passes locally with `14 passed`. - -`ethernet/RawEthFramer/` now also has checked-in regression coverage under `tests/ethernet/RawEthFramer/`. The earlier top-level `RawEthFramer` wrapper bench is joined by direct leaf benches for `RawEthFramerRx` and `RawEthFramerTx`, plus a `RawEthFramerPair` integration bench whose wrapper cross-connects two `RawEthFramer` instances to mirror the legacy `ethernet/RawEthFramer/tb/RawEthFramerTb.vhd` topology. The validated RX leaf bench covers lookup-gated unicast decode, short-frame trim behavior, broadcast bypass, and representative reject cases. The validated TX leaf bench now covers lookup-request exposure before forwarding, successful multi-beat unicast forwarding after lookup resolution, broadcast bypass with the observed padded wire image, and zero-MAC lookup-miss drop. The successful unicast leaf case intentionally models the nonzero lookup latency that the integrated `RawEthFramer` wrapper inserts before `ack`, so keep that timing assumption if the TX bench is expanded further. - -`ethernet/UdpEngine/` now has checked-in regression coverage under `tests/ethernet/UdpEngine/` as well. The current validated set covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, all backed by checked-in wrappers under `ethernet/UdpEngine/wrappers/` and the shared helper layer in `tests/ethernet/UdpEngine/udp_test_utils.py`. - -`ethernet/IpV4Engine/` now also has checked-in regression coverage under `tests/ethernet/IpV4Engine/`. The current validated set covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, all backed by checked-in wrappers under `ethernet/IpV4Engine/wrappers/` and the shared helper layer in `tests/ethernet/IpV4Engine/ipv4_test_utils.py`. The `IgmpV2Engine` leaf bench covers power-up reports, general-query re-arming, and report suppression on matching inbound membership reports; it also documents the leaf-level stale pseudo-header bytes that are ignored by downstream `IpV4EngineTx` assembly. - -The wrapper coverage policy is now more explicit in practice: test the wrapper-specific behavior, not the full leaf matrix again. `Fifo` validated both inferred sync/async selection branches, `FifoCascade` validated public stage-vector mapping plus a curated output smoke, and `FifoMux` is currently validated only on the stable split-to-narrow path. The pack-to-wide `FifoMux` path should be treated as still open rather than silently assumed covered. - -That same wrapper-policy lesson now applies to the late `base/sync` wrappers as well. `SyncClockFreq` is stable with a checked-in subsystem wrapper, but its common-clock measurement quantizes one count above the abstract target under the current GHDL flow, so the regression checks a bounded expected range rather than an exact integer. `SyncTrigRate` is intentionally covered as a wrapper/integration bench only: it proves aligned update publication, denser-window rate growth, reset-path liveness, and strobe pulse behavior, while exact min/max pipeline semantics remain the responsibility of the dedicated `SyncMinMax` leaf test. - -At this point the practical phase-1 `base/` rollout is effectively complete. The only uncovered non-dummy `base/` module is `LutFixedDelay`, and it remains deferred because it still depends on the vendor-backed `SinglePortRamPrimitive` path. The other remaining `base/` gaps are vendor-heavy or dummy-backed variants. - -The first post-`base/` `axi/` follow-on is now in place as well. `AxiStreamPipeline` is validated under `tests/axi/axi_stream/test_AxiStreamPipeline.py` using a thin flat-port adapter at `axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd`, and `AxiLiteCrossbar` is validated under `tests/axi/axi_lite/test_AxiLiteCrossbar.py` using the existing `axi/axi-lite/tb/AxiLiteCrossbarTb.vhd` harness as a cocotb-facing shell. The combined validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamPipeline.py tests/axi/axi_lite/test_AxiLiteCrossbar.py`, and it currently passes with `4 passed`. - -For `AxiStreamPipeline`, treat the zero-stage case as a true combinational pass-through and the staged cases as wrapper-visible buffered paths. The stable expectation under the current wrapper is sink-handshake latency of `PIPE_STAGES_G + 2` clocks plus bounded reset flush behavior, not a naive one-to-one mapping from the user generic name. For `AxiLiteCrossbar`, the useful regression surface is region routing, decode-miss `DECERR` handling, and concurrent traffic through the existing cascaded harness topology rather than a broad generic sweep. - -`AxiStreamMux` is now validated under `tests/axi/axi_stream/test_AxiStreamMux.py` using a thin two-input adapter at `axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd`. The module-local validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamMux.py`, and it currently passes with `3 passed`. A small follow-on sanity run across `tests/axi/axi_stream/test_AxiStreamPipeline.py`, `tests/axi/axi_stream/test_AxiStreamMux.py`, and `tests/axi/axi_lite/test_AxiLiteCrossbar.py` also passes with `7 passed`. Keep the validated subset intentionally narrow: indexed arbitration with explicit priority plus `disableSel`, routed `TDEST`/`TID` remap under backpressure, and staged asynchronous active-low reset recovery in passthrough mode. Interleave and explicit rearbitrate branches remain open for later work. Also note the mux-specific nuance from this bench: `disableSel` is applied before the separate priority-mask generation, so a disabled higher-priority source can still suppress lower-priority requesters. - -`AxiStreamDeMux` is now validated under `tests/axi/axi_stream/test_AxiStreamDeMux.py` using a thin one-input/two-output adapter at `axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd`. The module-local validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamDeMux.py`, and it currently passes with `3 passed`. A small follow-on sanity run across `tests/axi/axi_stream/test_AxiStreamPipeline.py`, `tests/axi/axi_stream/test_AxiStreamMux.py`, `tests/axi/axi_stream/test_AxiStreamDeMux.py`, and `tests/axi/axi_lite/test_AxiLiteCrossbar.py` passes with `10 passed`. Keep the validated subset intentionally narrow: indexed decode to both outputs, exact-match routed decode under output backpressure, and dynamic-route table behavior including unmatched-destination drop plus staged asynchronous active-low reset flush. Wildcard-route patterns and larger fanout counts remain open for later work. - -The next five flat-queue modules are now also in place and validated. `AxiStreamResize` uses `axi/axi-stream/ip_integrator/AxiStreamResizeIpIntegrator.vhd` plus `tests/axi/axi_stream/test_AxiStreamResize.py`; `AxiLiteAsync` uses `axi/axi-lite/ip_integrator/AxiLiteAsyncIpIntegrator.vhd` plus `tests/axi/axi_lite/test_AxiLiteAsync.py`; `AxiLiteMaster` uses `axi/axi-lite/ip_integrator/AxiLiteMasterIpIntegrator.vhd` plus `tests/axi/axi_lite/test_AxiLiteMaster.py`; `AxiLiteToDrp` uses `axi/bridge/ip_integrator/AxiLiteToDrpIpIntegrator.vhd` plus `tests/axi/bridge/test_AxiLiteToDrp.py`; and `AxiDualPortRam` is validated through the existing `axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd` wrapper plus `tests/axi/axi_lite/test_AxiDualPortRam.py`. The five-module validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamResize.py tests/axi/axi_lite/test_AxiLiteAsync.py tests/axi/axi_lite/test_AxiLiteMaster.py tests/axi/bridge/test_AxiLiteToDrp.py tests/axi/axi_lite/test_AxiDualPortRam.py`, and it currently passes with `10 passed`. A broader AXI follow-on sanity run across pipeline, mux, demux, resize, crossbar, async, master, DRP bridge, and dual-port RAM also passes with `20 passed`. - -The next 10 generated-queue AXI modules are now also in place and validated. `AxiLiteRegs`, `AxiLiteRespTimer`, `AxiLiteSlave`, `AxiLiteWriteFilter`, and `AxiVersion` are covered under `tests/axi/axi_lite/` with thin subsystem-local wrappers in `axi/axi-lite/ip_integrator/`. `AxiStreamCombiner`, `AxiStreamFlush`, `AxiStreamGearboxPack`, `AxiStreamGearboxUnpack`, and `AxiStreamSplitter` are covered under `tests/axi/axi_stream/` with thin subsystem-local wrappers in `axi/axi-stream/ip_integrator/`. The combined validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_lite/test_AxiLiteRegs.py tests/axi/axi_lite/test_AxiLiteRespTimer.py tests/axi/axi_lite/test_AxiLiteSlave.py tests/axi/axi_lite/test_AxiLiteWriteFilter.py tests/axi/axi_lite/test_AxiVersion.py tests/axi/axi_stream/test_AxiStreamCombiner.py tests/axi/axi_stream/test_AxiStreamFlush.py tests/axi/axi_stream/test_AxiStreamGearboxPack.py tests/axi/axi_stream/test_AxiStreamGearboxUnpack.py tests/axi/axi_stream/test_AxiStreamSplitter.py`, and it currently passes with `14 passed`. - -Keep the validated subset intentionally narrow for the two most timing-sensitive wrappers. `AxiStreamResize` covers equal-width pass-through plus curated upsize/downsize cases with sideband alignment and staged reset flush. `AxiLiteMaster` covers request/ack sequencing, staggered AXI ready/valid handshakes, propagated `SLVERR` responses, and reset return to idle. `AxiDualPortRam` covers AXI round-trips, system-port visibility, byte-masked system writes, and AXI write-disable error responses through the existing wrapper. `AxiLiteAsync` is currently validated only on the stable `COMMON_CLK_G=true` wrapper path; the asynchronous reset-crossing branches remain open for later work. `AxiLiteToDrp` is currently validated only on the stable common-clock non-arbitrated path with timeout recovery; the async arbitration branch remains open for later work. - -`AxiRateGen` is now also validated under `tests/axi/axi4/test_AxiRateGen.py` using `axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd`. The module-local validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiRateGen.py`, and it currently passes with `1 passed`. Keep the validated subset intentionally narrow here too: the stable `COMMON_CLK_G=true` path covers AXI-Lite register programming, timer-spaced generated AXI writes, and generated-read completion through a cocotb AXI RAM model, while the asynchronous AXI-Lite crossing branches remain open for later work. - -The remaining final 11 `axi/` modules from the axi-first pass are now also implemented and validated. The new checked-in benches are: -- `tests/axi/axi4/test_AxiReadEmulate.py` -- `tests/axi/axi4/test_AxiWriteEmulate.py` -- `tests/axi/axi4/test_AxiRingBuffer.py` -- `tests/axi/axi4/test_AxiMonAxiL.py` -- `tests/axi/axi_lite/test_AxiLiteRamSyncStatusVector.py` -- `tests/axi/axi_stream/test_AxiStreamMonAxiL.py` -- `tests/axi/dma/test_AxiStreamDmaWrite.py` -- `tests/axi/dma/test_AxiStreamDma.py` -- `tests/axi/dma/test_AxiStreamDmaFifo.py` -- `tests/axi/dma/test_AxiStreamDmaRingRead.py` -- `tests/axi/dma/test_AxiStreamDmaRingWrite.py` - -The supporting wrappers added for that batch are: -- `axi/axi4/ip_integrator/AxiReadEmulateIpIntegrator.vhd` -- `axi/axi4/ip_integrator/AxiWriteEmulateIpIntegrator.vhd` -- `axi/axi4/ip_integrator/AxiRingBufferIpIntegrator.vhd` -- `axi/axi4/ip_integrator/AxiMonAxiLIpIntegrator.vhd` -- `axi/axi-lite/ip_integrator/AxiLiteRamSyncStatusVectorIpIntegrator.vhd` -- `axi/axi-stream/ip_integrator/AxiStreamMonAxiLIpIntegrator.vhd` -- `axi/dma/ip_integrator/AxiStreamDmaWriteIpIntegrator.vhd` -- `axi/dma/ip_integrator/AxiStreamDmaFifoIpIntegrator.vhd` -- `axi/dma/ip_integrator/AxiStreamDmaIpIntegrator.vhd` -- `axi/dma/ip_integrator/AxiStreamDmaRingReadIpIntegrator.vhd` -- `axi/dma/ip_integrator/AxiStreamDmaRingWriteIpIntegrator.vhd` - -The combined validation command for that batch is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiReadEmulate.py tests/axi/axi4/test_AxiWriteEmulate.py tests/axi/axi4/test_AxiRingBuffer.py tests/axi/axi4/test_AxiMonAxiL.py tests/axi/axi_lite/test_AxiLiteRamSyncStatusVector.py tests/axi/axi_stream/test_AxiStreamMonAxiL.py tests/axi/dma/test_AxiStreamDmaWrite.py tests/axi/dma/test_AxiStreamDma.py tests/axi/dma/test_AxiStreamDmaFifo.py tests/axi/dma/test_AxiStreamDmaRingRead.py tests/axi/dma/test_AxiStreamDmaRingWrite.py`, and it passes locally with `11 passed`. - -One small RTL fix landed during that validation pass because the new `AxiStreamDmaRingWrite` test exposed a real simulation-width hazard: `axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd` now slices `dmaAck.size` back to `RAM_DATA_WIDTH_C` before incrementing `nextAddr`. Keep that change; it is what allows the checked-in narrow wrapper to simulate cleanly under GHDL. - -A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instantiation_graph.md` and `docs/_meta/rtl_instantiation_graph.json`, and the same generator now also emits a path-qualified bottom-up phase-1 queue at `docs/_meta/rtl_phase1_queue.md` and `docs/_meta/rtl_phase1_queue.json`. Keep the graph and queue for provenance, but treat them as historical context rather than as the default source of truth for what to implement next. - -## Immediate Next Task -If the user keeps the focus on `protocols/coaxpress`, the next practical step is either: -1. debug and re-enable the skipped `CoaXPressConfig` investigation bench, starting with the SRP-driven request path that currently fails to complete through the real `CoaXPressConfig` / `SrpV3AxiLite` integration, or -2. deepen the remaining spec-level gaps around full receive-side event payload/CRC semantics and fuller CXPoF normative `/Q/`/`/E/` handling. - -If the user switches back to `ethernet/RoCEv2`, the next real step is still enabling a mixed-language cocotb path for the five remaining RTL entities listed above. Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the real validated subset, and do not reintroduce local stand-ins for `blue-*`. - -## Read Order -1. `docs/_meta/rtl_regression_handoff.md` -2. `docs/_meta/rtl_regression_progress.md` -3. `docs/_meta/rtl_regression_plan.md` -4. `docs/_meta/rtl_phase1_queue.md` only if historical graph output is useful for context; it is no longer the active planning driver. - -Before writing code in a fresh session: -1. Re-read the Python comment rules and the checked-in wrapper comment/header rules above. -2. If adding a permanent `*IpIntegrator.vhd`, include the standard SURF banner and section comments in the first edit, not as an afterthought. -3. If adding a Python regression, include the standard SURF/SLAC header, the `Test methodology` header block, and in-body tutorial comments in the first draft. -4. If creating or editing any VHDL file, run `./.venv/bin/vsg -c vsg-linter.yml ...` on that file set, use `--fix` when possible, and rerun the same lint command until it is clean. -5. After any step that launches `pytest`, cocotb, GHDL, or another simulator process, sweep for stale child processes and kill any leftovers before starting the next step. - -## Important Repo Facts -- New Python regressions should be organized under subsystem packages in `tests/` -- Shared Python regression helper lives in `tests/common/regression_utils.py` -- `tests/common/regression_utils.py` now supports both test-local extra VHDL source lists and generated test-local wrapper emission for wrapper-based cases -- `tests/common/regression_utils.py` also now provides `start_lockstep_clocks()` for `COMMON_CLK_G` style benches that require truly shared edges -- When starting a new test, check for nearby shared helper modules before writing any new transaction boilerplate. The expected search order is: `tests/common/`, then the current subsystem package, then closely related subsystem packages that already cover the same protocol family. -- For AXI-Lite benches, prefer existing helpers for repeated register reads/writes, environment decoding, and common bench setup rather than spelling out raw transactions in every file. -- For AXI Stream benches, prefer existing helpers for beat/frame packing, contiguous-frame driving, whole-frame receive, no-output checks, and handshake observation rather than writing custom ready/valid loops unless the DUT exposes a genuinely new contract. -- For SSI benches, prefer `tests/protocols/ssi/ssi_test_utils.py` for beat models, frame helpers, `EOFE`/`SOF` handling, and sink/source setup instead of duplicating SSI transaction utilities in a local test file. -- Default comment style for new cocotb tests has two parts: a wrapped four-bullet `Test methodology` header (`Sweep`, `Stimulus`, `Checks`, `Timing`) plus tutorial-style in-body comments that explain what each coroutine step is doing and why -- New cocotb tests should also use the standard SURF/SLAC file header, not a shortened local variant -- The methodology header should be module-specific and describe the real curated sweep, driven sequence, expected outputs/state changes, and timing checks; avoid generic boilerplate -- Keep methodology comment lines to a normal readable width in the source file -- Checked-in cocotb-facing `*IpIntegrator.vhd` files should also follow repo style: standard SLAC/SURF banner at the top and short section comments marking shim setup, DUT hookup, and flattening/status export logic -- For AXI Stream and AXI-Lite record ports, prefer the existing IP-integrator shim entities to flatten record interfaces for cocotb instead of hand-writing record packing in each wrapper -- If an AXI wrapper needs DUT-specific extra signals, keep the standard shim pair for the bus itself and only wire the extra signals manually -- More generally, if any module needs a VHDL shim layer to fit cleanly into the cocotb flow, that shim belongs in the nearest real subsystem `ip_integrator/` tree rather than under `tests/` -- Do not use generic `hdl/` buckets for cocotb-facing adapter layers; reserve those locations for genuinely different kinds of HDL support -- Many VHDL wrappers live under `*/tb/` -- The initial regression inventory lives in `docs/_meta/rtl_regression_inventory.yaml` -- The RTL instantiation graph lives in `docs/_meta/rtl_instantiation_graph.{md,json}` -- The generated path-qualified phase-1 queue lives in `docs/_meta/rtl_phase1_queue.{md,json}`, but it is now historical context only rather than the next-module source of truth -- Manual phase-1 queue deferrals and order overrides still live in `docs/_meta/rtl_phase1_queue_overrides.json`, but that file is not the active task-selection mechanism anymore -- Use `./.venv/bin/python ...` for repo-local Python commands unless the virtualenv has already been activated in the current shell; do not assume a `python` shim exists on `PATH` -- If GHDL rejects a direct command-line override for a non-scalar or real generic, prefer a generated thin test-only wrapper over simulator-specific literal workarounds or another checked-in one-off HDL shim -- If a wrapper branch is unstable under the current open-source flow, keep the validated subset narrow and record the omitted branch explicitly in the docs instead of over-claiming wrapper coverage -- Use `ps -Ao pid,ppid,stat,time,command` when needed to find stale simulation children, then terminate only the leftover run trees instead of broad process classes -- `LutFixedDelay` remains intentionally deferred because it depends on `SinglePortRamPrimitive`; do not accidentally treat the now-small remaining `base/` set as phase-1 work that still needs to be forced through -- Regenerate the graph and the phase-1 queue with `./.venv/bin/python scripts/build_rtl_instantiation_graph.py` only when historical analysis is useful or the user explicitly asks for it -- Local bootstrap entrypoint: `scripts/setup_regression_env.sh` -- Local `ruckus` is linked from `~/ruckus` - -## Resume Rule -If resuming implementation, update `docs/_meta/rtl_regression_progress.md` first. diff --git a/docs/_meta/rtl_regression_inventory.yaml b/docs/_meta/rtl_regression_inventory.yaml deleted file mode 100644 index 7b84471fd9..0000000000 --- a/docs/_meta/rtl_regression_inventory.yaml +++ /dev/null @@ -1,700 +0,0 @@ -version: 1 -last_updated: 2026-03-21 - -field_guide: - entity: "Synthesizable RTL entity name" - path: "Path to the synthesizable RTL source file" - subsystem: "High-level repo grouping used for rollout and sharding" - tier: "One of functional_python, smoke_python, wrapper_required, deferred_vendor_heavy" - status: "Implementation state for this inventory row" - priority: "Rollout priority; pilot marks the initial implementation set" - wrapper_path: "Optional VHDL wrapper/shim used for cocotb access" - python_test: "Planned or implemented Python regression entrypoint" - reference_assets: "Legacy assets worth mining for intent, not preserving as execution requirements" - notes: "Short implementation notes" - deferred_reason: "Required when tier is deferred_vendor_heavy" - -inventory_rules: - - "Every synthesizable RTL entity should eventually appear exactly once in this inventory." - - "Executable regression logic must live in Python." - - "VHDL may remain only as thin wrappers, shims, or required simulation models." - - "Legacy VHDL testbenches are reference material, not a preservation target." - - "Generic-heavy modules should prefer functional_python over smoke_python when actively implemented." - -modules: - - entity: Crc32Parallel - path: base/crc/rtl/Crc32Parallel.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/crc/test_Crc32Parallel.py - reference_assets: [] - notes: "Graph-guided CRC leaf with validated coverage for byte-width variation, registered vs direct input handling, and reset polarity/style variants against a shared Python CRC model." - deferred_reason: "" - - - entity: Crc32 - path: base/crc/rtl/Crc32.vhd - subsystem: base - tier: functional_python - status: implemented_validated_expanded - priority: phase1_low_level - wrapper_path: base/crc/wrappers/Crc32PolyWrapper.vhd - python_test: tests/base/crc/test_Crc32.py - reference_assets: [] - notes: "Graph-guided generic CRC leaf with validated coverage for IEEE CRC-32, Castagnoli, and Koopman-style 32-bit polynomial cases plus byte-width, input-register, and reset polarity/style variation. Uses a thin test-only wrapper because the local GHDL flow rejects direct command-line overrides of the 32-bit `CRC_POLY_G` `slv` generic." - deferred_reason: "" - - - entity: CRC32Rtl - path: base/crc/rtl/CRC32Rtl.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/crc/test_CRC32Rtl.py - reference_assets: [] - notes: "Legacy-compatible fixed-polynomial CRC leaf with validated baseline behavioral coverage for synchronous and asynchronous reset handling and reset polarity variation." - deferred_reason: "" - - - entity: RstSync - path: base/sync/rtl/RstSync.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_RstSync.py - reference_assets: [] - notes: "High-fanout reset synchronizer from the graph-guided leaf set. Validated coverage includes release-delay behavior, active-high vs active-low reset polarity, asynchronous vs synchronous power-on reset handling, and bypass/no-output configurations." - deferred_reason: "" - - - entity: PwrUpRst - path: base/general/rtl/PwrUpRst.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/general/test_PwrUpRst.py - reference_assets: [] - notes: "Reusable reset-generator primitive with validated coverage for counter-based startup stretch behavior, synchronous vs asynchronous reset handling, and reset polarity variation." - deferred_reason: "" - - - entity: SynchronizerEdge - path: base/sync/rtl/SynchronizerEdge.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SynchronizerEdge.py - reference_assets: [] - notes: "Graph-guided edge-detect synchronizer with validated coverage for rising/falling pulse detection through different sync depths, reset polarity/style variation, and bypass handling." - deferred_reason: "" - - - entity: SynchronizerOneShot - path: base/sync/rtl/SynchronizerOneShot.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SynchronizerOneShot.py - reference_assets: [] - notes: "Graph-guided one-shot synchronizer with validated coverage for single-pulse capture, stretched output behavior, reset polarity/style variation, active-low output mode, and bypass operation." - deferred_reason: "" - - - entity: TrueDualPortRam - path: base/ram/inferred/TrueDualPortRam.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/ram/test_TrueDualPortRam.py - reference_assets: [] - notes: "Reusable dual-port RAM primitive with validated direct cocotb coverage for read-first, write-first, and no-change modes, registered output behavior, byte-write masking, and reset polarity/style variants." - deferred_reason: "" - - - entity: LutRam - path: base/ram/inferred/LutRam.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/ram/test_LutRam.py - reference_assets: [] - notes: "Reusable LUTRAM primitive with validated coverage for combinational and registered variants, read-first/write-first/no-change behavior, multiport access, byte-write masking, and reset polarity/style variants." - deferred_reason: "" - - - entity: FifoRdFsm - path: base/fifo/rtl/inferred/FifoRdFsm.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/fifo/test_FifoRdFsm.py - reference_assets: [] - notes: "Graph-guided FIFO read-side primitive with validated coverage for standard vs FWFT behavior, block vs distributed memory modes, count progression, visible prefetch behavior, underflow-safe idle behavior, and reset polarity/style variants." - deferred_reason: "" - - - entity: SynchronizerVector - path: base/sync/rtl/SynchronizerVector.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SynchronizerVector.py - reference_assets: [] - notes: "High-reuse `base/sync` vector leaf selected from the instantiation graph. Validated curated matrix covers width variation, stage-depth latency, synchronous vs asynchronous reset handling, active-high vs active-low reset polarity, output inversion, and bypass behavior." - deferred_reason: "" - - - entity: RstPipeline - path: base/general/rtl/RstPipeline.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/general/test_RstPipeline.py - reference_assets: [] - notes: "High-reuse `base/general` reset-distribution leaf selected from the instantiation graph. Validated matrix covers stage-depth latency and `INV_RST_G` behavior; timing-only and synthesis-only generics remain intentionally out of scope." - deferred_reason: "" - - - entity: SimpleDualPortRam - path: base/ram/inferred/SimpleDualPortRam.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/ram/test_SimpleDualPortRam.py - reference_assets: [] - notes: "Graph-guided shared RAM primitive with validated direct cocotb coverage for baseline port-A write/port-B read operation, optional output register behavior, byte-write masking, and synchronous/asynchronous reset polarity variants on the read side." - deferred_reason: "" - - - entity: FifoOutputPipeline - path: base/fifo/rtl/FifoOutputPipeline.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/fifo/test_FifoOutputPipeline.py - reference_assets: [] - notes: "Graph-guided FIFO leaf with validated coverage for zero-latency passthrough, pipelined ordering, backpressure holding behavior, and synchronous/asynchronous reset polarity variants using a small FWFT-style source model." - deferred_reason: "" - - - entity: FifoWrFsm - path: base/fifo/rtl/inferred/FifoWrFsm.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/fifo/test_FifoWrFsm.py - reference_assets: [] - notes: "Graph-guided FIFO write-side primitive with validated coverage for startup readiness, count/index progression, full and overflow behavior, programmable-full threshold behavior, gray-coded async mode, and reset polarity/style variants." - deferred_reason: "" - - - entity: Synchronizer - path: base/sync/rtl/Synchronizer.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_Synchronizer.py - reference_assets: [] - notes: "High-reuse `base/sync` leaf selected from the instantiation graph. Validated curated matrix covers synchronous vs asynchronous reset handling, active-high vs active-low reset polarity, stage-depth latency, output inversion, and bypass behavior without introducing a wrapper." - deferred_reason: "" - - - entity: FifoSync - path: base/fifo/rtl/inferred/FifoSync.vhd - subsystem: base - tier: functional_python - status: implemented_validated_expanded - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/fifo/test_FifoSync.py - reference_assets: - - base/fifo/tb/FifoFwftTb.vhd - - base/fifo/tb/FwftCntTb.vhd - notes: "Bottom-up follow-on to FifoAsync. Expanded validated matrix covers FWFT vs standard mode, block vs distributed RAM, reset polarity/style variants, wider/deeper sizing, FWFT pipeline behavior, and threshold-focused cases for the synchronous implementation path." - deferred_reason: "" - - - entity: FifoAsync - path: base/fifo/rtl/inferred/FifoAsync.vhd - subsystem: base - tier: functional_python - status: implemented_validated_expanded - priority: pilot - wrapper_path: "" - python_test: tests/base/fifo/test_FifoAsync.py - reference_assets: - - base/sync/tb/SynchronizerFifoTb.vhd - notes: "Low-level async FIFO pilot. Expanded validated matrix covers FWFT vs standard mode, block vs distributed RAM, reset polarity/style variants, wider/deeper sizing, non-default sync depth, pipeline behavior, and threshold-focused cases. The matrix intentionally excludes TPD_G and INIT_G as non-behavioral here, and BYP_RAM_G because the current implementation does not exercise a separate bypass-RAM path." - deferred_reason: "" - - - entity: DspComparator - path: dsp/generic/fixed/DspComparator.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/dsp/generic/test_DspComparator.py - reference_assets: [] - notes: "First validated `dsp/` leaf in the new cocotb flow. Coverage focuses on comparator truth behavior and pipeline/reset variation rather than a large DSP-generic sweep." - deferred_reason: "" - - - entity: DspAddSub - path: dsp/generic/fixed/DspAddSub.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/dsp/generic/test_DspAddSub.py - reference_assets: - - dsp/generic/tb/DspAddSubTb.vhd - notes: "Validated signed add and subtract behavior with direct and pipelined output paths, including backpressure hold and reset clearing. The legacy VHDL bench only provided free-running stimulus, so the cocotb bench replaces it with explicit arithmetic and interface assertions." - deferred_reason: "" - - - entity: FirFilterTap - path: dsp/generic/fixed/FirFilterTap.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: generated_test_local - python_test: tests/dsp/generic/test_FirFilterTap.py - reference_assets: [] - notes: "Validated signed multiply-accumulate behavior for both generic coefficient initialization and runtime coefficient updates through a generated wrapper. The bench also checks that disabled cycles hold the previous cascade output." - deferred_reason: "" - - - entity: DspPreSubMult - path: dsp/generic/fixed/DspPreSubMult.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/dsp/generic/test_DspPreSubMult.py - reference_assets: [] - notes: "Validated signed pre-subtract multiply behavior, output hold under backpressure, and reset recovery with a direct arithmetic reference model." - deferred_reason: "" - - - entity: DspSquareDiffMult - path: dsp/generic/fixed/DspSquareDiffMult.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/dsp/generic/test_DspSquareDiffMult.py - reference_assets: [] - notes: "Validated signed square-difference multiplication, output hold under backpressure, and reset recovery with explicit Python arithmetic checks." - deferred_reason: "" - - - entity: BoxcarIntegrator - path: dsp/generic/fixed/BoxcarIntegrator.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/dsp/generic/test_BoxcarIntegrator.py - reference_assets: - - dsp/generic/tb/BoxcarIntegratorTb.vhd - notes: "Validated unsigned and signed modes, direct and registered output paths, `obAck` hold behavior, and `intCount` reconfiguration. The cocotb bench keeps the useful rolling-sum intent from the legacy bench but adds explicit interface assertions." - deferred_reason: "" - - - entity: BoxcarFilter - path: dsp/generic/fixed/BoxcarFilter.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/dsp/generic/test_BoxcarFilter.py - reference_assets: - - dsp/generic/tb/BoxcarFilterTb.vhd - notes: "Validated the integrated boxcar filter output scaling and hold behavior with a Python rolling-average model, replacing the legacy demo-style ramp-only bench with explicit output checks." - deferred_reason: "" - - - entity: FirFilterSingleChannel - path: dsp/generic/fixed/FirFilterSingleChannel.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/dsp/generic/test_FirFilterSingleChannel.py - reference_assets: - - dsp/generic/tb/FirFilterSingleChannelTb.vhd - notes: "Validated common-clock FIR data flow, sideband alignment, and AXI-Lite coefficient programming through a generated wrapper. The new bench keeps the useful coefficient-programming intent from the legacy environment but replaces its unasserted waveform stimulus with explicit filtered-output checks." - deferred_reason: "" - - - entity: FirFilterMultiChannel - path: dsp/generic/fixed/FirFilterMultiChannel.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/dsp/generic/test_FirFilterMultiChannel.py - reference_assets: [] - notes: "Validated common-clock parallel multichannel FIR frame flow and AXI-Lite coefficient updates through a generated wrapper, using a per-channel Python FIR reference model and cocotbext-axi stream endpoints." - deferred_reason: "" - - - entity: Fifo - path: base/fifo/rtl/Fifo.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/fifo/test_Fifo.py - reference_assets: [] - notes: "Validated wrapper-focused coverage for the inferred backend only. The regression checks sync-vs-async branch selection, wrapper-level data flow, `INIT_G` forwarding, and the sync-mode `wr_data_count`/`rd_data_count` aliasing rule instead of replaying the full FIFO primitive matrix." - deferred_reason: "" - - - entity: FifoCascade - path: base/fifo/rtl/FifoCascade.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/fifo/test_FifoCascade.py - reference_assets: [] - notes: "Validated wrapper-specific coverage for inferred FWFT paths. The regression checks public `progFullVec`/`progEmptyVec` stage mapping plus a curated output smoke; it intentionally does not claim full multi-stage drain ordering under the current GHDL flow." - deferred_reason: "" - - - entity: FifoMux - path: base/fifo/rtl/FifoMux.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/fifo/test_FifoMux.py - reference_assets: [] - notes: "Validated wrapper-specific coverage currently targets the stable split-to-narrow path, including endian-aware slicing and reset-safe drain behavior. The pack-to-wide branch remains intentionally unclaimed in phase 1 because it did not surface a stable visible output in the current open-source flow." - deferred_reason: "" - - - entity: AsyncGearbox - path: base/general/rtl/AsyncGearbox.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/general/test_AsyncGearbox.py - reference_assets: [] - notes: "Validated asynchronous gearbox wrapper with a Python bit-level reference model, covering representative width conversion and reset behavior without trying to exhaust the full ratio space." - deferred_reason: "" - - - entity: SynchronizerOneShotVector - path: base/sync/rtl/SynchronizerOneShotVector.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SynchronizerOneShotVector.py - reference_assets: [] - notes: "Validated vectorized one-shot synchronizer coverage for lane independence and bypass behavior using a small curated lane matrix." - deferred_reason: "" - - - entity: SynchronizerOneShotCntVector - path: base/sync/rtl/SynchronizerOneShotCntVector.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: generated_test_local - python_test: tests/base/sync/test_SynchronizerOneShotCntVector.py - reference_assets: [] - notes: "Validated counted vector one-shot coverage using a generated test-local wrapper to flatten the array-typed output into a cocotb-friendly interface." - deferred_reason: "" - - - entity: SyncStatusVector - path: base/sync/rtl/SyncStatusVector.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/base/sync/test_SyncStatusVector.py - reference_assets: [] - notes: "Validated status-vector coverage for count/IRQ snapshot behavior. Uses a generated test-local wrapper for the vectorized count output and a lockstep shared-clock helper when `COMMON_CLK_G=true`." - deferred_reason: "" - - - entity: SyncTrigPeriod - path: base/sync/rtl/SyncTrigPeriod.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SyncTrigPeriod.py - reference_assets: [] - notes: "Validated trigger-period monitor with curated common-clock coverage for period accumulation and reset behavior." - deferred_reason: "" - - - entity: SyncMinMax - path: base/sync/rtl/SyncMinMax.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SyncMinMax.py - reference_assets: [] - notes: "Validated common-clock min/max snapshot behavior, including `rstStat` reseeding. Current phase-1 coverage is intentionally limited to the stable common-clock path." - deferred_reason: "" - - - entity: MasterRamIpIntegrator - path: base/general/ip_integrator/MasterRamIpIntegrator.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/general/test_MasterRamIpIntegrator.py - reference_assets: [] - notes: "Validated IP-integrator wrapper coverage for master-side write and read request forwarding, including handshake-safe addressing and shared comment-rich cocotb sequencing." - deferred_reason: "" - - - entity: SlaveRamIpIntegrator - path: base/general/ip_integrator/SlaveRamIpIntegrator.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/general/test_SlaveRamIpIntegrator.py - reference_assets: [] - notes: "Validated IP-integrator wrapper coverage for slave-side data return and write acceptance behavior using direct cocotb handshakes against the exported RAM-style ports." - deferred_reason: "" - - - entity: DualPortRam - path: base/ram/inferred/DualPortRam.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/ram/test_DualPortRam.py - reference_assets: [] - notes: "Validated inferred dual-port RAM wrapper with curated coverage for independent port readback, write-mode semantics, registered-output behavior, byte-write masking, and reset polarity variation." - deferred_reason: "" - - - entity: SlvDelayRam - path: base/delay/rtl/SlvDelayRam.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/delay/test_SlvDelayRam.py - reference_assets: [] - notes: "Validated RAM-backed delay line for configured latency, enable-hold behavior, and reset handling. The bench documents the observed GHDL-visible latency offset instead of pretending the comment-level ideal is cycle-exact." - deferred_reason: "" - - - entity: SlvDelayFifo - path: base/delay/rtl/SlvDelayFifo.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/delay/test_SlvDelayFifo.py - reference_assets: [] - notes: "Validated FIFO-backed delay line with curated coverage for timestamp-ordered delayed delivery and a short-delay smoke that stays inside the stable visible behavior under the current GHDL flow." - deferred_reason: "" - - - entity: SyncClockFreq - path: base/sync/rtl/SyncClockFreq.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/base/sync/test_SyncClockFreq.py - reference_assets: [] - notes: "Validated frequency-monitor wrapper using a generated real-generic shim and lockstep shared-clock helper. The common-clock case is checked against a bounded expected range because the current GHDL-visible quantization lands one count above the abstract target." - deferred_reason: "" - - - entity: SyncTrigRate - path: base/sync/rtl/SyncTrigRate.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/base/sync/test_SyncTrigRate.py - reference_assets: [] - notes: "Validated wrapper/integration coverage for aligned update publication, denser-window rate growth, reset-path liveness, and update-strobe pulse behavior. Exact min/max pipeline semantics remain intentionally covered by the dedicated `SyncMinMax` leaf regression." - deferred_reason: "" - - - entity: SyncTrigRateVector - path: base/sync/rtl/SyncTrigRateVector.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/base/sync/test_SyncTrigRateVector.py - reference_assets: [] - notes: "Validated vectorized trigger-rate wrapper with a generated flattening shim, per-lane rate independence checks, and shared update-strobe pulse behavior on the stable common-clock path." - deferred_reason: "" - - - entity: LutFixedDelay - path: base/delay/rtl/LutFixedDelay.vhd - subsystem: base - tier: deferred_vendor_heavy - status: deferred_phase1 - priority: phase1_deferred - wrapper_path: "" - python_test: "" - reference_assets: [] - notes: "Single remaining non-dummy `base/` gap after the phase-1 practical rollout." - deferred_reason: "Depends on `SinglePortRamPrimitive`, so the current implementation path still drags vendor-specific infrastructure back into the open-source simulation flow." - - - entity: AxiStreamFifoV2 - path: axi/axi-stream/rtl/AxiStreamFifoV2.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: pilot - wrapper_path: axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd - python_test: tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py - reference_assets: - - tests/test_AxiStreamFifoV2IpIntegrator.py - notes: "Generic-heavy AXI-Stream pilot. Reused the IP integrator wrapper and migrated the Python regression into the shared package layout. Current validated sweep covers width-conversion cases plus one VALID_THOLD=0 configuration." - deferred_reason: "" - - - entity: AxiStreamPipeline - path: axi/axi-stream/rtl/AxiStreamPipeline.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd - python_test: tests/axi/axi_stream/test_AxiStreamPipeline.py - reference_assets: - - tests/test_AxiStreamPipelineTb.py - notes: "Validated AXI-Stream helper with a thin flat-port wrapper. The curated sweep covers zero-stage pass-through, staged pipeline ordering and sideband forwarding, backpressure stability, and synchronous/asynchronous reset handling. Staged cases are checked against the wrapper-visible latency of `PIPE_STAGES_G + 2` clocks plus bounded reset flush behavior." - deferred_reason: "" - - - entity: AxiStreamMux - path: axi/axi-stream/rtl/AxiStreamMux.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd - python_test: tests/axi/axi_stream/test_AxiStreamMux.py - reference_assets: - - axi/axi-stream/tb/AxiStreamMuxTb.vhd - - axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd - notes: "Validated AXI-Stream mux coverage with a thin two-input wrapper. The curated sweep covers indexed arbitration with explicit priority plus `disableSel`, routed `TDEST`/`TID` remap under backpressure, and staged asynchronous active-low reset recovery in passthrough mode. Interleave and explicit rearbitrate branches remain intentionally open for later work." - deferred_reason: "" - - - entity: AxiStreamDeMux - path: axi/axi-stream/rtl/AxiStreamDeMux.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd - python_test: tests/axi/axi_stream/test_AxiStreamDeMux.py - reference_assets: - - axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd - - tests/test_AxiStreamDemuxMuxTb.py - notes: "Validated AXI-Stream demux coverage with a thin one-input/two-output wrapper. The curated sweep covers indexed routing, exact-match routed decode under output backpressure, and dynamic-route table behavior including unmatched-destination drop and staged asynchronous active-low reset flush. Wildcard-route patterns and larger fanout counts remain intentionally open for later work." - deferred_reason: "" - - - entity: AxiLiteCrossbar - path: axi/axi-lite/rtl/AxiLiteCrossbar.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-lite/tb/AxiLiteCrossbarTb.vhd - python_test: tests/axi/axi_lite/test_AxiLiteCrossbar.py - reference_assets: - - axi/axi-lite/tb/AxiLiteCrossbarTb.vhd - notes: "Validated AXI-Lite crossbar coverage through the existing cocotb-facing harness topology. The regression checks routed read/write correctness across the local and cascaded regions, decode-miss `DECERR` responses, and concurrent traffic without region cross-coupling." - deferred_reason: "" - - - entity: AxiLiteAsync - path: axi/axi-lite/rtl/AxiLiteAsync.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-lite/ip_integrator/AxiLiteAsyncIpIntegrator.vhd - python_test: tests/axi/axi_lite/test_AxiLiteAsync.py - reference_assets: - - axi/axi-lite/tb/AxiLiteAsyncTb.vhd - notes: "Validated AXI-Lite async-wrapper coverage with a purpose-built IP-integrator adapter. The current passing subset is intentionally narrow: common-clock pass-through plus restart/recovery on the stable wrapper path. The asynchronous reset-crossing branches remain open for later work because they were not simulator-stable enough for this initial batch." - deferred_reason: "" - - - entity: AxiStreamResize - path: axi/axi-stream/rtl/AxiStreamResize.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-stream/ip_integrator/AxiStreamResizeIpIntegrator.vhd - python_test: tests/axi/axi_stream/test_AxiStreamResize.py - reference_assets: - - axi/axi-stream/tb/AxiStreamResizeTb.vhd - notes: "Validated AXI-Stream resize coverage with a thin flat-port adapter. The curated sweep covers equal-width pass-through, 2-byte to 4-byte upsize, and 4-byte to 2-byte downsize with sideband alignment checks plus staged reset flush in the resized cases." - deferred_reason: "" - - - entity: AxiLiteMaster - path: axi/axi-lite/rtl/AxiLiteMaster.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-lite/ip_integrator/AxiLiteMasterIpIntegrator.vhd - python_test: tests/axi/axi_lite/test_AxiLiteMaster.py - reference_assets: [] - notes: "Validated AXI-Lite master coverage with a thin request/ack-to-flat-port adapter and a cocotb slave model. The first bench covers write/read request sequencing, staggered AXI ready/valid handshakes, propagated `SLVERR` responses, and reset return to idle." - deferred_reason: "" - - - entity: AxiLiteToDrp - path: axi/bridge/rtl/AxiLiteToDrp.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/bridge/ip_integrator/AxiLiteToDrpIpIntegrator.vhd - python_test: tests/axi/bridge/test_AxiLiteToDrp.py - reference_assets: [] - notes: "Validated AXI-Lite-to-DRP bridge coverage with a thin flat-port wrapper. The current passing subset is intentionally narrow: common-clock non-arbitrated write/read mapping plus timeout-driven `SLVERR` and `drpUsrRst` recovery. The async arbitration branch remains open for later work." - deferred_reason: "" - - - entity: AxiDualPortRam - path: axi/axi-lite/rtl/AxiDualPortRam.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd - python_test: tests/axi/axi_lite/test_AxiDualPortRam.py - reference_assets: - - axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd - notes: "Validated AXI dual-port RAM coverage through the existing wrapper. The curated sweep covers AXI round-trips, system-port visibility of AXI writes, byte-masked system writes, and AXI write-disable `SLVERR` behavior when wrapper error responses are enabled." - deferred_reason: "" diff --git a/docs/_meta/rtl_regression_plan.md b/docs/_meta/rtl_regression_plan.md deleted file mode 100644 index edb96d6e54..0000000000 --- a/docs/_meta/rtl_regression_plan.md +++ /dev/null @@ -1,157 +0,0 @@ -# SURF RTL Regression Plan - -## Objective -- Build a repo-wide regression system for synthesizable SURF RTL. -- Standardize on a single executable test framework so new work stays consistent. -- Make progress resumable across many context windows without re-discovery. - -## Chosen Methodology -- Python-only executable test logic. -- Primary stack: `pytest + cocotb + GHDL + ruckus`. -- Local Python commands should use the repo virtualenv interpreter (`./.venv/bin/python`) unless the virtualenv has already been explicitly activated in that shell. -- VHDL is allowed only for thin wrappers, shims, or required simulation models. -- Existing VHDL testbenches are reference material, not execution constraints. -- New Python regression code should use tutorial-style comments by default. -- New Python cocotb test files should start with the standard SURF/SLAC header block, not an ad hoc local header. -- Every Python regression should also carry a short module-specific `Test methodology` block immediately under the SLAC header comment. -- The header methodology block should use four wrapped bullets: `Sweep`, `Stimulus`, `Checks`, and `Timing`. -- The methodology bullets must describe the actual curated parameter sweep, the actual driven input sequence, the expected outputs or state changes, and the timing/latency/pulse/backpressure behavior being checked for that specific module. -- Do not use generic placeholder methodology prose; the header should tell a reader what this specific bench is proving. -- Keep methodology comment lines at a normal source width so the block is readable in the editor instead of turning into single-line paragraphs. -- Assume the reader is not already comfortable with cocotb. -- Comment the purpose of each major step in the test flow, including clock startup, reset sequencing, trigger waits, stimulus phases, and result checks. -- Treat the header methodology block and the in-body tutorial comments as separate requirements; one does not replace the other. -- Shared helpers may stay somewhat denser, but module-level tests should still explain how the Python coroutine behavior maps onto DUT behavior. -- When a DUT generic assumes truly common clocks, drive those clocks from one shared cocotb coroutine rather than starting two same-period clocks independently. -- For Python cocotb files, the minimum first-draft structure is: - - standard SURF/SLAC file header, - - module-specific `Test methodology` block, - - tutorial-style comments in the executable body. -- Checked-in cocotb-facing VHDL wrappers should follow the in-tree SURF style too: add the standard SLAC/SURF banner at the top and include brief section comments for the major adapter regions. -- For `*IpIntegrator.vhd` wrappers, the minimum expected sectioning is usually: - - bus shim section, - - DUT instantiation section, - - output/status flattening section when present. -- Do not leave permanent checked-in wrappers as uncommented bare port maps even if the logic is thin; future sessions should be able to scan the file and identify the adapter shape immediately. -- For any VHDL file you create or edit, run the `vsg` linter with the same configuration CI uses (`./.venv/bin/vsg -c vsg-linter.yml ...`) before considering the work done. -- When `vsg` reports fixable issues, use `--fix`/autofix first, then rerun the same CI-configured lint command to confirm the file is clean. - -## Scope -- Whole repo target. -- Phase 1 focuses on simulator-friendly modules. -- Vendor-heavy modules are deferred in phase 1 unless they become practical under the open-source flow. - -## Coverage Model -- `functional_python` - - Module has a Python-authored cocotb regression. -- `smoke_python` - - Module has compile/elaborate coverage only. -- `wrapper_required` - - Module needs a retained or added VHDL wrapper to expose a cocotb-friendly interface. -- `deferred_vendor_heavy` - - Module is intentionally excluded from phase 1 executable regression. - -## Package Coverage Policy -- VHDL packages are not treated as standalone executable regression targets. -- Type/constant packages are covered transitively through the modules that compile and use them. -- Behavioral package functions and procedures should be covered through DUTs that exercise them whenever practical. -- If an important package function or procedure is not well reached transitively, add a minimal VHDL wrapper and test that wrapper from Python. -- Package-helper wrappers should be tracked separately from the main synthesizable-module inventory when they are introduced. - -## Generic And Configuration Policy -- Generic-heavy modules are Python-first by default. -- Build curated configuration matrices in Python. -- Do not use naive full Cartesian products for broad generic spaces. -- Compute expected behavior dynamically in Python from the active generics. -- If simulator limitations make direct generic overrides awkward, prefer checked-in subsystem-local VHDL wrappers over ad hoc test-local copies. -- Keep checked-in wrappers thin and declarative: expose cycle-friendly or cocotb-friendly generics, map them onto the real DUT generics, and keep them beside the subsystem RTL they adapt. -- For integration wrappers, test the wrapper-specific behavior rather than replaying the full underlying leaf matrix through the wrapper. -- If only a simulator-stable subset of a wrapper is practical in phase 1, keep that subset intentionally narrow and document the unvalidated branches explicitly in the handoff/progress docs. - -## CI And Runtime Policy -- Tier-first split. -- Separate `smoke` and `functional` regression tiers. -- Shard by subsystem only if runtime requires it. -- Keep room for PR-vs-nightly expansion later if runtime and coverage needs justify it. -- Treat simulator process cleanup as part of every verification step, not as optional housekeeping. -- After any command that launches `pytest`, cocotb, GHDL, or another simulation runner, check for stale child processes and kill any leftovers before moving on to the next step. -- When cleanup is needed, prefer an explicit process sweep first (for example with `ps -Ao pid,ppid,stat,time,command`) so only the stale run trees are terminated. - -## Reuse Policy -- Legacy VHDL testbenches are reference material only. -- Rewrite executable test logic in Python when migrating a module into the new regression system. -- Keep VHDL wrappers only when they make Python stimulus materially cleaner. -- Do not preserve old benches purely for historical reasons. -- Before writing new cocotb transaction code, search the nearest subsystem `tests/` package for an existing `*_test_utils.py` or equivalent shared helper module and reuse it when possible. -- Prefer extending an existing helper with one more narrowly useful utility over cloning handshake loops, packet builders, frame receivers, or register-access boilerplate into each new test file. -- For AXI-Lite work, look for existing read/write helpers, setup helpers, and protocol-master wrappers first; do not hand-code repeated register transactions if the subsystem already has a stable helper path. -- For AXI Stream work, look for existing frame/beat helpers, contiguous-send helpers, receive helpers, keep-mask helpers, and handshake monitors before writing custom ready/valid loops. -- For SSI work, prefer the existing SSI helper layer for flat endpoint setup, beat modeling, frame send/receive, no-output checks, and `EOFE`/`SOF`-aware assertions instead of rebuilding SSI transaction plumbing in each bench. -- When a wrapper is needed only to adapt simulator-hostile generics, check it into the nearest subsystem-local `wrappers/` or `ip_integrator/` folder instead of hiding it under `tests/` or a generic `hdl/` bucket. -- For SURF AXI/AxiLite record ports, prefer the existing IP-integrator shim layers (`SlaveAxiStreamIpIntegrator`, `MasterAxiStreamIpIntegrator`, `SlaveAxiLiteIpIntegrator`, `MasterAxiLiteIpIntegrator`) instead of hand-writing record-to-flat unpacking in each test wrapper. -- If a DUT has extra nonstandard side signals, compose those on top of the standard AXI shim pair rather than replacing the standard flattening pattern. -- For wrapper-style protocol benches, prefer thin subsystem wrappers plus cocotb protocol masters/RAM models, and add accepted-handshake monitoring whenever timing-visible protocol behavior is part of the contract being proven. -- More generally, if a VHDL shim layer is needed to make a module practical to drive from cocotb, place that file in the nearest real subsystem `wrappers/` or `ip_integrator/` folder beside related adapter layers. -- Do not place cocotb-facing shim/adaptor VHDL under `tests/` or generic `hdl/` buckets when it is serving the same integration role as the existing `*IpIntegrator.vhd` files. -- When a wrapper is checked in under `wrappers/` or `ip_integrator/`, treat it like production repo HDL for readability purposes: keep the standard file banner and add concise section comments instead of relying on file naming alone. -- Treat checked-in Python cocotb tests the same way: use the normal repo header/comment style in the first draft instead of leaving cleanup for later. - -## Rollout Planning Policy -- Use a checked-in RTL instantiation graph to guide bottom-up rollout decisions. -- Prefer testing high-reuse leaf primitives directly before spending effort on higher-level assemblies that mostly repackage them. -- Use the graph to reduce repeated behavioral testing across adjacent hierarchy levels, not as a substitute for engineering judgment about externally visible behavior. -- Keep the graph and queue artifacts for provenance and optional analysis, but do not use them as the active day-to-day source of truth for task selection. -- The active planning driver is now manual user-directed area selection, with `docs/_meta/rtl_regression_progress.md` and `docs/_meta/rtl_regression_handoff.md` tracking what is done, what is intentionally narrow, and what remains open. -- Do not hand-maintain queue order in this plan. If the graph or queue is regenerated for analysis, treat it as secondary context unless the user explicitly switches back to queue-driven planning. - -## CoaXPress Spec Discipline -- Treat the published CoaXPress specifications as normative for future `protocols/coaxpress/` work, especially for top-level receive/transmit and over-fiber bridge benches. -- The two governing references are the CoaXPress protocol spec (`CXP-001-2021`) and the CoaXPress-over-Fiber bridge spec (`CXPR-008-2021`), matching the links already called out in `protocols/coaxpress/core/rtl/CoaXPressPkg.vhd`. -- When a CoaXPress bench encodes packet classes, control symbols, or bridge control characters, derive those values from the spec-defined names first and mirror them through shared helpers such as `tests/protocols/coaxpress/coaxpress_test_utils.py` instead of scattering raw literals. -- At the packet layer, prefer the published names even when the current RTL signal naming drifts; for example, `0x07` is an event packet and `0x08` is an event acknowledgment even though some existing RTL ports still use `eventAck` for the receive-side event indication. -- For CoaXPress image/header benches, keep the repeated-byte field encoding, header field order, endianness conversion, line-size semantics, and end-of-frame rules explicitly tied to the spec-defined rectangular image packet layout. -- For CoaXPress-over-Fiber benches, keep `/I/`, `/Q/`, `/S/`, `/T/`, and `/E/` handling, lane-0-only start/sequence semantics, and payload-vs-housekeeping start words aligned to `CXPR-008-2021`. -- If a checked-in bench intentionally validates only the current RTL contract instead of the full normative spec behavior, document that narrowed scope explicitly in the progress and handoff docs rather than implying full spec coverage. -- If a CoaXPress top-level bench has to be checked in as skipped because it exposes a likely RTL defect, keep the spec-shaped stimulus and the skip reason in-tree, and record the blocking symptom explicitly in the progress and handoff docs so the next pass resumes from the defect rather than from scratch. - -## Historical Queue Artifacts -The phase-1 simulator-friendly queue remains available as a generated bottom-up artifact, but it is now historical context rather than the active workflow. - -Retained artifacts: -- `docs/_meta/rtl_phase1_queue.md` -- `docs/_meta/rtl_phase1_queue.json` -- `docs/_meta/rtl_phase1_queue_overrides.json` - -If they are regenerated: -1. Use `./.venv/bin/python scripts/build_rtl_instantiation_graph.py`. -2. Treat the resulting graph and queue as reference material only. -3. Keep the real done/open frontier in `docs/_meta/rtl_regression_progress.md` and `docs/_meta/rtl_regression_handoff.md`. - -## Phase Breakdown -### Phase 1 -- Create the regression inventory and artifact scaffolding. -- Generate and maintain a repo-wide RTL instantiation graph to guide bottom-up prioritization. -- Establish shared Python regression helpers. -- Add smoke coverage for simulator-friendly modules. -- Add functional Python tests for the highest-value pilot modules and reusable blocks. -- Define the migration pattern for wrappers and generic-heavy modules. -- Standardize the subsystem-local checked-in wrapper pattern for real- or vector-generic leaves that need cycle-native test knobs under GHDL. - -### Phase 2 -- Deepen randomized and adversarial coverage. -- Expand curated configuration sweeps for generic-heavy modules. -- Add stronger reusable scoreboards and protocol-specific helpers. -- Revisit deferred vendor-heavy modules after phase 1 baseline stability. - -## Acceptance Criteria For Phase 1 -- The repo has a checked-in inventory and handoff system. -- New windows can recover project state by reading the handoff artifacts only. -- The Python-only regression direction is documented and stable. -- The progress and handoff artifacts stay aligned with the actual validated branch frontier instead of lagging behind completed subsystem waves. -- The smoke/functional tier split is established in the plan and progress tracking. - -## Open Questions And Deferred Decisions -- Whether PR-vs-nightly split is needed immediately or only after runtime data. -- Exact criteria for moving a vendor-heavy module out of `deferred_vendor_heavy`. -- Which user-directed subsystem slice should be taken next after the current documented frontier. -- Whether a separate tracked list of high-risk behavioral package helpers is needed once the module inventory stabilizes. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md deleted file mode 100644 index 816baeefc6..0000000000 --- a/docs/_meta/rtl_regression_progress.md +++ /dev/null @@ -1,329 +0,0 @@ -# SURF RTL Regression Progress - -## Summary -- Current phase: Phase-1 implementation active -- Current subsystem: manual user-directed rollout tracking -- Current focus module: user-directed CoaXPress pure-VHDL rollout under `protocols/coaxpress/core/rtl`, with validated cocotb coverage now checked in for `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, `CoaXPressRxHsFsm`, `CoaXPressRx`, `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressTx`, `CoaXPressCore`, `CoaXPressOverFiberBridgeRx`, `CoaXPressOverFiberBridgeTx`, and `CoaXPressOverFiberBridge`. -- Last updated: 2026-04-20 - -## Current Frontier Snapshot -- Active planning rule: take the next work item from the user's manual direction, not from `docs/_meta/rtl_phase1_queue.{md,json}`. -- Manual planning note: - - The axi-first pass is complete through the previously remaining final 11 `axi/` modules. - - The current `verification-2` branch already includes the merged `pre-release` state through PR #1392, so the validated `protocols/ssi`, `protocols/pgp`, and current Ethernet waves (`EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the current pure-VHDL RoCEv2 quartet) are all part of the present branch snapshot. - - The checked-in queue and override artifacts are now retained only as historical provenance and optional graph output; they are no longer the source of truth for choosing the next area. - - Keep the done/open frontier in this progress file and in `docs/_meta/rtl_regression_handoff.md` aligned to the actual tree even if the queue artifacts are stale. - - Treat stale simulator cleanup as mandatory after every launched verification command: after any `pytest`, cocotb, GHDL, or similar simulation step, sweep for leftover child processes and kill them before starting the next task. -- Known expected-open tests on this branch: - - No simulator-friendly expected-open leaf tests remain in the currently covered `ethernet/IpV4Engine` slice, and the recent `EthMacCore` / `UdpEngine` thin-area follow-up is also checked in on this branch. - - The current `EthMac*Xlgmii` import/export leaves are still placeholder no-op RTL, so the checked-in benches document that inert contract rather than claiming functional XLGMII datapath coverage. - - The remaining Ethernet work is in the larger untouched families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core`, plus the five still-open RoCEv2 RTL entities that depend on generated submodules: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`. -- RoCEv2 RTL target matrix: - - Covered now under the current GHDL-only flow: `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, `RoceConfigurator` - - Still required, but need real `blue-*` dependencies under a mixed-language simulator: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, `RoceEngineWrapper` -- CoaXPress RTL target matrix: - - Covered now under the current GHDL-only flow: `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, `CoaXPressRxHsFsm`, `CoaXPressRx`, `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressTx`, `CoaXPressCore`, `CoaXPressOverFiberBridgeRx`, `CoaXPressOverFiberBridgeTx`, and `CoaXPressOverFiberBridge` - - Still open in the same pure-VHDL family: `CoaXPressConfig` - - Blocked bench note: `tests/protocols/coaxpress/test_CoaXPressConfig.py` is checked in as a skipped investigation bench because the real SRP-driven request path does not complete under the current `CoaXPressConfig`/`SrpV3AxiLite` integration. Treat that as a likely RTL or integration defect to debug before re-enabling active assertions on the config return path. - - Known-issue bench note: `tests/protocols/coaxpress/test_CoaXPressCore.py` now also carries an opt-in skipped investigation bench for the user-reported RX backpressure path. When enabled with `RUN_KNOWN_ISSUE_TESTS=1`, the bench drives sustained `M_DATA_TREADY=0` pressure with repeated one-line image frames and encodes the expected software-facing behavior that `RxOverflowCnt` should rise before `RxFsmErrorCnt`. The current local reproduction showed `RxFsmErrorCnt=2` while `RxOverflowCnt=0` at `96` frames, and a narrowing sweep showed no repro at `48` frames but a repro by `72` frames (`RxFsmErrorCnt=1`, `RxOverflowCnt=0`), so treat that as a likely RTL defect until narrowed or disproved. - - Spec discipline for this family: use the packet/control naming and byte values from `CXP-001-2021` and `CXPR-008-2021` via shared helpers, and keep future top-level/bridge benches explicit about whether they are proving normative spec behavior or only the currently validated RTL subset. At the packet layer, keep the published names even when current RTL signal names drift: `0x07` is an event packet and `0x08` is an event acknowledgment. - - The checked-in RX benches now use more spec-shaped control-ack framing on the wire, include a dual-lane `CoaXPressRxHsFsm` step/alignment case and a dual-lane `CoaXPressRx` lane-rotation case, but the current receive-side event path still only observes the event packet prefix through the Packet Tag field before returning to IDLE. Keep that limitation documented rather than implying full event-payload decode coverage. -- Most recent reusable bench pattern: - - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. - - For `ethernet`, keep using the checked-in wrappers under `ethernet/*/wrappers/` plus the shared helper layers in `tests/ethernet/EthMacCore/ethmac_test_utils.py`, `tests/ethernet/RawEthFramer/raw_eth_test_utils.py`, `tests/ethernet/UdpEngine/udp_test_utils.py`, and `tests/ethernet/IpV4Engine/ipv4_test_utils.py`. The practical first-pass shape is flat EMAC/app beat wrappers with explicit sideband bits, curated functional slices instead of exhaustive generic sweeps, and dedicated pair/integration wrappers only where an old VHDL bench contributes a topology worth preserving. - - For `protocols/coaxpress`, the practical first-pass shape is subsystem-local wrappers under `protocols/coaxpress/core/wrappers/` plus a small helper layer in `tests/protocols/coaxpress/coaxpress_test_utils.py`. Keep the input side raw and cycle-native where the DUT already consumes protocol words directly, and only flatten the observable AXI-stream outputs or handshaked lane arrays that cocotb actually needs to inspect. - - The checked-in CoaXPress helper now carries named spec constants for packet classes and bridge control characters. Reuse those names instead of introducing more raw `0x01`/`0x02`/`0x07`-style literals in future benches. - -## Status -| Subsystem | Inventory | Smoke | Functional | Notes | -| --- | --- | --- | --- | --- | -| Cross-cutting infrastructure | started | not started | started | Shared helper structure now lives in `tests/common/regression_utils.py`; pytest now defaults to `xdist` parallel execution via `pytest.ini`; the checked-in graph/queue artifacts under `docs/_meta/` are retained for provenance, while `rtl_regression_progress.md` and `rtl_regression_handoff.md` are the active planning inputs | -| `base` | started | not started | started | Validated low-level regressions now exist for `FifoAsync`, `FifoSync`, `FifoOutputPipeline`, `FifoWrFsm`, `FifoRdFsm`, `Fifo`, `FifoCascade`, `FifoMux`, `Synchronizer`, `SynchronizerVector`, `SynchronizerEdge`, `SynchronizerOneShot`, `SynchronizerFifo`, `SynchronizerOneShotCnt`, `SynchronizerOneShotVector`, `SynchronizerOneShotCntVector`, `SyncStatusVector`, `SyncTrigPeriod`, `SyncMinMax`, `SyncClockFreq`, `SyncTrigRate`, `SyncTrigRateVector`, `RstSync`, `RstPipeline`, `RstPipelineVector`, `PwrUpRst`, `Arbiter`, `ClockDivider`, `Debouncer`, `Gearbox`, `AsyncGearbox`, `Heartbeat`, `Mux`, `OneShot`, `RegisterVector`, `WatchDogRst`, `Scrambler`, `MasterRamIpIntegrator`, `SlaveRamIpIntegrator`, `SimpleDualPortRam`, `DualPortRam`, `TrueDualPortRam`, `LutRam`, `SlvDelay`, `SlvFixedDelay`, `SlvDelayRam`, `SlvDelayFifo`, `Crc32Parallel`, `Crc32`, and `CRC32Rtl` under subsystem-organized `tests/base/` packages. Remaining uncovered `base/` entities are vendor-heavy, dummy-backed, or `LutFixedDelay`, which is deferred because it depends on `SinglePortRamPrimitive`. | -| `dsp` | started | not started | started | The planned `dsp/generic/fixed` leaf batch is now validated under `tests/dsp/generic/`: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. Shared DSP helpers now live in `tests/dsp/generic/dsp_test_utils.py`, and the legacy VHDL benches under `dsp/generic/tb/` were treated as behavioral reference material rather than as execution constraints. | -| `axi` | started | not started | started | The axi-first pass is now complete for the simulator-friendly queue. The final locally validated batch adds `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`, with a combined `11 passed` validation run on 2026-03-27. Added checked-in subsystem wrappers under `axi/axi4/ip_integrator/`, `axi/axi-lite/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/` for those benches. `AxiStreamFifoV2` now has an expanded `10 passed` wrapper regression under `tests/axi/axi_stream/` covering async and sync width conversion, metadata truncation, `VALID_THOLD` frame-ready and burst-release modes, dynamic pause-threshold behavior, `CASCADE_SIZE=2`, and the `S_HAS_TREADY=0` pause-only source-side path. `AxiResize` now passes its equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` wrapper regression on this branch after the read-hold RTL fix. `AxiLiteAsync`, `AxiLiteToDrp`, and `AxiRateGen` still keep intentionally narrow common-clock subsets while the more timing-sensitive async AXI-Lite crossing branches remain open. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` still keep intentionally narrow first-pass subsets. `AxiStreamDmaV2Read` is now validated with a two-case wrapper regression covering both aligned and short terminal-beat reads after fixing bounded byte-count conversion in `AxiPkg` and terminal-mask generation in `AxiStreamDmaV2Read`. | -| `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. `protocols/coaxpress/` now has a broader pure-VHDL staged rollout under `tests/protocols/coaxpress/` backed by checked-in wrappers in `protocols/coaxpress/core/wrappers/`: the receive leaves now cover offset-start packing, lane rotation, stream/config/event/heartbeat decode, rectangular-header framing, and a dual-lane `CoaXPressRxHsFsm` step/alignment case; the receive assembly now covers both the original one-lane integration path and a dual-lane `CoaXPressRx` lane-rotation case; the transmit/bridge leaf benches cover `CoaXPressEventAckMsg` serialization under backpressure, `CoaXPressTxLsFsm` idle/config/trigger cadence across both implemented low-speed rates, `CoaXPressOverFiberBridgeTx` CXPoF start/payload/terminate formatting plus partial-lane fill behavior, and `CoaXPressOverFiberBridgeRx` CXPoF start-word decode plus HKP and negative lane-placement guardrails; and the higher-level assembly benches cover `CoaXPressTx` config/event-ack arbitration plus software-trigger injection across the cfg-to-tx clock crossing and `CoaXPressOverFiberBridge` top-level 32b/64b gearbox integration on both the TX and RX sides. The current CoaXPress subset remains intentionally staged: it normalizes packet/control literals onto named spec constants in `tests/protocols/coaxpress/coaxpress_test_utils.py`, leaves `CoaXPressConfig` as the remaining pure-VHDL blocker, and still documents receive-side event parsing and normative CXPoF `/Q/`/`/E/` handling as open spec-depth gaps rather than claiming full protocol compliance. | -| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers both the original leaf slice and the deeper assembly benches for `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`, plus direct `EthMacRxBypass` / `EthMacTxBypass` leaf benches and import/export sweeps that now explicitly include the current placeholder `XLGMII` contract. `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, including the successful multi-beat `RawEthFramerTx` unicast-forwarding path after lookup resolution. `tests/ethernet/UdpEngine/` covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, with the top/wrapper benches now widened across client/server routing paths. `tests/ethernet/IpV4Engine/` covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, and the top/leaf benches now also include protocol-TX and deeper ICMP reject/recovery coverage. `tests/ethernet/RoCEv2/` currently covers the pure-VHDL RTL entities `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator` through checked-in wrappers under `ethernet/RoCEv2/wrappers/`. The remaining RoCEv2 RTL entities that still need cocotb benches are `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`, and those should use the real generated `blue-*` dependencies rather than local stand-ins. The explicit Ethernet caveats are now the larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core`, the mixed-language RoCEv2 bench gap listed above, plus the still-placeholder `EthMac*Xlgmii` RTL. | -| `devices` | not started | not started | not started | Many vendor-heavy cases | -| `xilinx` | not started | not started | not started | Many vendor-heavy cases | - -## Completed Decisions -- Use Python-only executable test logic. -- Use `pytest + cocotb + GHDL + ruckus` as the primary stack. -- Keep VHDL only for wrappers, shims, and required simulation models. -- Comment new Python regression code at a tutorial level so readers who are new to cocotb can follow the flow in-place. -- Whole repo is the long-term target. -- Phase 1 focuses on simulator-friendly modules. -- Vendor-heavy modules are deferred in phase 1. -- Generic-heavy modules are Python-first. -- Use curated configuration matrices instead of full Cartesian products. -- Keep a tier-first CI model: `smoke` and `functional`. -- Rewrite legacy VHDL TB logic in Python rather than preserving it by default. -- Keep wrappers only when they make Python interaction cleaner. -- Run the `vsg` linter with CI's `vsg-linter.yml` settings on any created or edited VHDL files, and use autofix before doing manual cleanup when possible. -- Treat VHDL packages as transitively covered unless a behavioral function/procedure needs a dedicated wrapper. -- Treat `docs/_meta/rtl_regression_progress.md` and `docs/_meta/rtl_regression_handoff.md` as the living planning inputs, and treat the checked-in queue artifacts as archival unless the user explicitly asks to resume queue-driven planning. - -## Completed Work Items -- Surveyed repo structure and existing verification flow. -- Reviewed existing Python regressions and representative VHDL testbenches. -- Merged the current `pre-release` branch into `verification-2`, bringing the already-landed `protocols/ssi` and `protocols/pgp` regression waves into the same branch line as the earlier `ethernet/EthMacCore` slice. -- Re-added `dsp/` to the generated phase-1 queue scope so DSP work is tracked by the same bottom-up planner as the other simulator-friendly subsystems. -- Implemented `tests/dsp/generic/test_DspAddSub.py`. -- Validated `tests/dsp/generic/test_DspAddSub.py` locally with `./.venv/bin/python -m pytest -n 0 -q tests/dsp/generic/test_DspAddSub.py`. -- Added shared DSP helpers in `tests/dsp/generic/dsp_test_utils.py` for signed packing/truncation, rolling reference models, cocotb clock-settle timing, and generated FIR wrappers. -- Extended `tests/common/regression_utils.py` so generated-wrapper benches can use short explicit sim-build keys instead of overloading generic/extra-env strings into fragile build paths. -- Implemented `tests/dsp/generic/test_FirFilterTap.py`, `tests/dsp/generic/test_DspPreSubMult.py`, `tests/dsp/generic/test_DspSquareDiffMult.py`, `tests/dsp/generic/test_BoxcarIntegrator.py`, `tests/dsp/generic/test_BoxcarFilter.py`, `tests/dsp/generic/test_FirFilterSingleChannel.py`, and `tests/dsp/generic/test_FirFilterMultiChannel.py`. -- Fixed DSP RTL issues exposed by the new benches in `dsp/generic/fixed/FirFilterTap.vhd`, `dsp/generic/fixed/BoxcarIntegrator.vhd`, and `dsp/generic/fixed/FirFilterSingleChannel.vhd`. -- Validated the full planned DSP leaf batch locally with `./.venv/bin/python -m pytest -n 0 -q tests/dsp/generic` (`15 passed`). -- Compared `cocotb + pytest`, `VUnit`, and `OSVVM` for SURF. -- Chose Python-only executable regression logic. -- Defined the context-handoff artifact set. -- Created the checked-in handoff artifacts under `docs/_meta/`. -- Created the initial regression inventory scaffold in `docs/_meta/rtl_regression_inventory.yaml`. -- Selected and documented the first pilot modules: `FifoAsync`, `AxiStreamFifoV2`, and `AxiLiteAsync`. -- Added `scripts/setup_regression_env.sh` to bootstrap the local regression environment. -- Added `.vscode/tasks.json` with setup, import, and regression tasks. -- Installed local `ghdl` via Homebrew. -- Created `.venv`, installed Python regression dependencies, linked `~/ruckus`, and completed `make MODULES="$PWD" import`. -- Added shared regression helpers in `tests/regression_utils.py`. -- Implemented the first Python pilot regression in `tests/base/fifo/test_FifoAsync.py`. -- Validated `tests/base/fifo/test_FifoAsync.py` locally with `./.venv/bin/python -m pytest -v tests/base/fifo/test_FifoAsync.py`. -- Reorganized new regressions into subsystem packages under `tests/` and moved shared helpers to `tests/common/`. -- Added `tests/README.md` to document the regression layout policy. -- Added the shared Ethernet MAC helper layer in `tests/ethernet/EthMacCore/ethmac_test_utils.py`, including packet builders, checksum helpers, MAC-config byte-order handling, flat EMAC beat helpers, and Ethernet minimum-frame padding support for the import/export loopback benches. -- Added checked-in cocotb-facing wrappers under `ethernet/EthMacCore/wrappers/` for the first `EthMacCore` wave, including loopback wrappers for import/export and top-level tests plus flat wrappers for the checksum, pause, filter, and shift leaves. -- Implemented and validated the first `ethernet/EthMacCore` functional wave under `tests/ethernet/EthMacCore/`: `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`. -- Expanded the first `EthMacCore` wave beyond the initial happy paths: `EthMacTop` now covers filter/backpressure/checksum/pause interactions, `EthMacRxImport` and `EthMacTxExport` now cover both GMII and XGMII plus link-not-ready recovery behavior, the RX/TX checksum benches now include negative and partial-repair cases, `EthMacRxFilter` now covers multicast/broadcast/filter-disable/multi-beat-drop behavior, the RX/TX shift benches now cover runtime shift changes and control-bit propagation, and `EthCrc32Parallel` now sweeps all byte widths `1..16`. -- Ran a quick HDL coverage spike against the local Homebrew `ghdl` build and confirmed it does not expose `--coverage` or a `coverage` subcommand. -- Migrated `AxiStreamFifoV2` into `tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py` and validated the current 10-case sweep locally. -- Expanded `tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py` into a broader 10-case `AxiStreamFifoV2` regression covering thresholded release modes, metadata truncation, multi-stage cascade buffering, and the `S_HAS_TREADY=0` pause-only path, and validated it locally with `10 passed`. -- Revalidated `tests/axi/axi4/test_AxiResize.py` after merging `verification` into `fix-axi-resize`; the equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` cases now all pass locally on this branch, so the stale upsize `xfail` was removed. -- Expanded `FifoAsync` into a curated 12-case matrix and validated it locally under parallel pytest execution. -- Added `pytest.ini` to default to `-n auto --dist=worksteal`, and aligned CI to rely on that default xdist configuration. -- Implemented `tests/base/fifo/test_FifoSync.py` and validated its 11-case matrix locally under parallel pytest execution. -- Added `scripts/build_rtl_instantiation_graph.py` and generated checked-in graph artifacts in `docs/_meta/rtl_instantiation_graph.{md,json}`. -- Implemented `tests/base/sync/test_Synchronizer.py` and validated its 6-case matrix locally under parallel pytest execution. -- Implemented `tests/base/sync/test_SynchronizerVector.py` and validated its 6-case matrix locally under parallel pytest execution. -- Implemented `tests/base/general/test_RstPipeline.py` and validated its 4-case matrix locally under parallel pytest execution. -- Implemented `tests/base/ram/test_SimpleDualPortRam.py` and validated its 5-case matrix locally under parallel pytest execution. -- Implemented `tests/base/fifo/test_FifoOutputPipeline.py` and validated its 5-case matrix locally under parallel pytest execution. -- Implemented `tests/base/fifo/test_FifoWrFsm.py` and validated its 4-case matrix locally under parallel pytest execution. -- Extended `tests/common/regression_utils.py` so regressions can add test-local VHDL wrapper sources when simulator limitations make a thin shim cleaner than direct generic overrides. -- Implemented `tests/base/crc/test_Crc32Parallel.py`, `tests/base/crc/test_Crc32.py`, and `tests/base/crc/test_CRC32Rtl.py` and validated their combined 9-case CRC batch locally under parallel pytest execution. -- Implemented `tests/base/sync/test_RstSync.py`, `tests/base/sync/test_SynchronizerEdge.py`, and `tests/base/sync/test_SynchronizerOneShot.py` and validated their combined 11-case sync/reset batch locally under parallel pytest execution. -- Implemented `tests/base/general/test_PwrUpRst.py` and validated its 3-case matrix locally under parallel pytest execution. -- Implemented `tests/base/ram/test_TrueDualPortRam.py` and `tests/base/ram/test_LutRam.py` and validated their combined 9-case RAM batch locally under parallel pytest execution. -- Implemented `tests/base/fifo/test_FifoRdFsm.py` and validated its 4-case matrix locally under parallel pytest execution. -- Validated the full 10-module follow-on subset in one run with `./.venv/bin/python -m pytest -v tests/base/crc/test_Crc32Parallel.py tests/base/crc/test_Crc32.py tests/base/crc/test_CRC32Rtl.py tests/base/sync/test_RstSync.py tests/base/general/test_PwrUpRst.py tests/base/sync/test_SynchronizerEdge.py tests/base/sync/test_SynchronizerOneShot.py tests/base/ram/test_TrueDualPortRam.py tests/base/ram/test_LutRam.py tests/base/fifo/test_FifoRdFsm.py` (`38 passed`). -- Implemented `tests/base/general/test_Arbiter.py`, `tests/base/general/test_ClockDivider.py`, `tests/base/general/test_Debouncer.py`, `tests/base/general/test_Gearbox.py`, `tests/base/general/test_Heartbeat.py`, `tests/base/general/test_Mux.py`, `tests/base/general/test_OneShot.py`, `tests/base/general/test_RegisterVector.py`, `tests/base/general/test_RstPipelineVector.py`, `tests/base/general/test_Scrambler.py`, `tests/base/general/test_WatchDogRst.py`, `tests/base/delay/test_SlvDelay.py`, `tests/base/delay/test_SlvFixedDelay.py`, `tests/base/sync/test_SynchronizerFifo.py`, and `tests/base/sync/test_SynchronizerOneShotCnt.py`. -- Implemented `tests/axi/axi_stream/test_AxiStreamScatterGather.py`, `tests/axi/axi4/test_AxiMemTester.py`, `tests/axi/dma/test_AxiStreamDmaV2Desc.py`, `tests/axi/dma/test_AxiStreamDmaV2Fifo.py`, `tests/axi/axi4/test_AxiReadPathFifo.py`, `tests/axi/axi4/test_AxiWritePathFifo.py`, `tests/axi/dma/test_AxiStreamDmaV2.py`, `tests/axi/axi_stream/test_AxiStreamBatchingFifo.py`, `tests/axi/axi_stream/test_AxiStreamMon.py`, and `tests/axi/axi_stream/test_AxiStreamRingBuffer.py`, plus the supporting `*IpIntegrator.vhd` wrappers needed for the new AXI4/AXIS/DMA benches. -- Validated the full 15-module follow-on subset in one run with `./.venv/bin/python -m pytest -n 0 -q tests/base/general/test_Arbiter.py tests/base/general/test_ClockDivider.py tests/base/general/test_Debouncer.py tests/base/general/test_Gearbox.py tests/base/general/test_Heartbeat.py tests/base/general/test_Mux.py tests/base/general/test_OneShot.py tests/base/general/test_RegisterVector.py tests/base/general/test_RstPipelineVector.py tests/base/general/test_Scrambler.py tests/base/general/test_WatchDogRst.py tests/base/delay/test_SlvDelay.py tests/base/delay/test_SlvFixedDelay.py tests/base/sync/test_SynchronizerFifo.py tests/base/sync/test_SynchronizerOneShotCnt.py` (`41 passed`). -- Added a shared generated-wrapper path in `tests/common/regression_utils.py` and migrated the `Heartbeat` and `Debouncer` regressions away from checked-in one-off VHDL wrappers. -- Revalidated the generated-wrapper migration locally with `./.venv/bin/python -m pytest -n 0 -q tests/base/general/test_Heartbeat.py tests/base/general/test_Debouncer.py` (`6 passed`) and then revalidated the full 15-module batch (`41 passed`). -- Implemented `tests/dsp/generic/test_DspComparator.py`, `tests/base/fifo/test_Fifo.py`, `tests/base/fifo/test_FifoCascade.py`, `tests/base/fifo/test_FifoMux.py`, `tests/base/general/test_AsyncGearbox.py`, `tests/base/sync/test_SynchronizerOneShotVector.py`, `tests/base/sync/test_SynchronizerOneShotCntVector.py`, `tests/base/sync/test_SyncStatusVector.py`, `tests/base/sync/test_SyncTrigPeriod.py`, and `tests/base/sync/test_SyncMinMax.py`. -- Validated the combined 10-module wrapper/integration batch with `./.venv/bin/python -m pytest -n 0 -q tests/dsp/generic/test_DspComparator.py tests/base/fifo/test_Fifo.py tests/base/fifo/test_FifoCascade.py tests/base/fifo/test_FifoMux.py tests/base/general/test_AsyncGearbox.py tests/base/sync/test_SynchronizerOneShotVector.py tests/base/sync/test_SynchronizerOneShotCntVector.py tests/base/sync/test_SyncStatusVector.py tests/base/sync/test_SyncTrigPeriod.py tests/base/sync/test_SyncMinMax.py` (`18 passed`). -- Implemented `tests/base/general/test_MasterRamIpIntegrator.py`, `tests/base/general/test_SlaveRamIpIntegrator.py`, `tests/base/ram/test_DualPortRam.py`, `tests/base/delay/test_SlvDelayRam.py`, `tests/base/delay/test_SlvDelayFifo.py`, `tests/base/sync/test_SyncClockFreq.py`, `tests/base/sync/test_SyncTrigRate.py`, and `tests/base/sync/test_SyncTrigRateVector.py`. -- Validated the combined remaining non-vendor, non-dummy `base/` batch with `./.venv/bin/python -m pytest -n 0 -q tests/base/general/test_MasterRamIpIntegrator.py tests/base/general/test_SlaveRamIpIntegrator.py tests/base/ram/test_DualPortRam.py tests/base/delay/test_SlvDelayRam.py tests/base/delay/test_SlvDelayFifo.py tests/base/sync/test_SyncClockFreq.py tests/base/sync/test_SyncTrigRate.py tests/base/sync/test_SyncTrigRateVector.py` (`15 passed`). -- Implemented `tests/axi/axi_stream/test_AxiStreamPipeline.py` with a thin flat-port adapter at `axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd`, and validated its curated 3-case sweep locally. -- Implemented `tests/axi/axi_lite/test_AxiLiteCrossbar.py` with a cocotb-facing crossbar wrapper and validated its routed-region, decode-error, and concurrent-traffic coverage locally. -- Validated the first post-`base/` `axi/` pair with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamPipeline.py tests/axi/axi_lite/test_AxiLiteCrossbar.py` (`4 passed`). -- Implemented `tests/axi/axi_stream/test_AxiStreamMux.py` with a thin two-input adapter at `axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd`, and validated its curated indexed-priority, routed-remap, and asynchronous reset/recovery sweep locally (`3 passed`). -- Revalidated the small post-`base/` `axi/` follow-on set with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamPipeline.py tests/axi/axi_stream/test_AxiStreamMux.py tests/axi/axi_lite/test_AxiLiteCrossbar.py` (`7 passed`). -- Implemented `tests/axi/axi_stream/test_AxiStreamDeMux.py` with a thin two-output adapter at `axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd`, and validated its curated indexed-routing, routed-backpressure, and dynamic-route/drop/reset sweep locally (`3 passed`). -- Revalidated the current small `axi/` follow-on subset with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamPipeline.py tests/axi/axi_stream/test_AxiStreamMux.py tests/axi/axi_stream/test_AxiStreamDeMux.py tests/axi/axi_lite/test_AxiLiteCrossbar.py` (`10 passed`). -- Replaced the hand-curated flat phase-1 list with a generated path-qualified queue emitted by `scripts/build_rtl_instantiation_graph.py` into `docs/_meta/rtl_phase1_queue.{md,json}`, backed by explicit filters and manual-order inputs in `docs/_meta/rtl_phase1_queue_overrides.json`. -- Implemented `tests/axi/axi_lite/test_AxiLiteRegs.py`, `tests/axi/axi_lite/test_AxiLiteRespTimer.py`, `tests/axi/axi_lite/test_AxiLiteSlave.py`, `tests/axi/axi_lite/test_AxiLiteWriteFilter.py`, `tests/axi/axi_lite/test_AxiVersion.py`, `tests/axi/axi_stream/test_AxiStreamCombiner.py`, `tests/axi/axi_stream/test_AxiStreamFlush.py`, `tests/axi/axi_stream/test_AxiStreamGearboxPack.py`, `tests/axi/axi_stream/test_AxiStreamGearboxUnpack.py`, and `tests/axi/axi_stream/test_AxiStreamSplitter.py` with thin subsystem-local adapters under `axi/axi-lite/ip_integrator/` and `axi/axi-stream/ip_integrator/`. -- Validated the generated-queue 10-module AXI batch with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_lite/test_AxiLiteRegs.py tests/axi/axi_lite/test_AxiLiteRespTimer.py tests/axi/axi_lite/test_AxiLiteSlave.py tests/axi/axi_lite/test_AxiLiteWriteFilter.py tests/axi/axi_lite/test_AxiVersion.py tests/axi/axi_stream/test_AxiStreamCombiner.py tests/axi/axi_stream/test_AxiStreamFlush.py tests/axi/axi_stream/test_AxiStreamGearboxPack.py tests/axi/axi_stream/test_AxiStreamGearboxUnpack.py tests/axi/axi_stream/test_AxiStreamSplitter.py` (`14 passed`). -- Implemented `tests/axi/axi4/test_AxiReadPathMux.py`, `tests/axi/axi4/test_AxiWritePathMux.py`, `tests/axi/axi4/test_AxiResize.py`, and `tests/axi/bridge/test_AxiToAxiLite.py` with thin subsystem-local adapters at `axi/axi4/ip_integrator/AxiReadPathMuxIpIntegrator.vhd`, `axi/axi4/ip_integrator/AxiWritePathMuxIpIntegrator.vhd`, `axi/axi4/ip_integrator/AxiResizeIpIntegrator.vhd`, and `axi/bridge/ip_integrator/AxiToAxiLiteIpIntegrator.vhd`. -- Validated the stable AXI4/bridge follow-on subset with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiReadPathMux.py tests/axi/axi4/test_AxiWritePathMux.py tests/axi/bridge/test_AxiToAxiLite.py` (`3 passed`). `tests/axi/axi4/test_AxiResize.py` is present on this branch with the restored upsize case, but that case is expected to fail until the separate `AxiResize` RTL-fix branch is merged. -- Implemented `tests/axi/axi_stream/test_AxiStreamTrailerRemove.py`, `tests/axi/axi4/test_AxiRam.py`, `tests/axi/bridge/test_AxiLiteToIpBus.py`, `tests/axi/bridge/test_IpBusToAxiLite.py`, `tests/axi/dma/test_AxiStreamDmaV2Read.py`, `tests/axi/axi_stream/test_AxiStreamGearbox.py`, `tests/axi/axi_stream/test_AxiStreamTap.py`, `tests/axi/dma/test_AxiStreamDmaRead.py`, `tests/axi/dma/test_AxiStreamDmaV2Write.py`, and `tests/axi/axi_stream/test_AxiStreamTimer.py` with subsystem-local adapters under `axi/axi-stream/ip_integrator/`, `axi/bridge/ip_integrator/`, and `axi/dma/ip_integrator/`. -- Validated the stable 9-module subset of that generated-queue window with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiRam.py tests/axi/bridge/test_AxiLiteToIpBus.py tests/axi/bridge/test_IpBusToAxiLite.py tests/axi/dma/test_AxiStreamDmaRead.py tests/axi/dma/test_AxiStreamDmaV2Write.py tests/axi/axi_stream/test_AxiStreamGearbox.py tests/axi/axi_stream/test_AxiStreamTap.py tests/axi/axi_stream/test_AxiStreamTimer.py tests/axi/axi_stream/test_AxiStreamTrailerRemove.py` (`9 passed`). `tests/axi/dma/test_AxiStreamDmaV2Read.py` is present on this branch as a minimal one-beat aligned reproducer, but it still fails immediately inside `AxiStreamDmaV2Read` at `31 ns` with `std_logic_arith.vhdl:2014:9: ARG is too large in CONV_INTEGER`, so `AxiStreamDmaV2Read` remains open rather than counted as validated. -- Implemented `tests/axi/axi4/test_AxiRateGen.py` with a thin subsystem-local adapter at `axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd`. -- Validated `AxiRateGen` locally with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiRateGen.py` (`1 passed`) and revalidated the nearby AXI4 subset with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiReadPathMux.py tests/axi/axi4/test_AxiWritePathMux.py tests/axi/axi4/test_AxiRam.py tests/axi/axi4/test_AxiRateGen.py` (`4 passed`). -- Refactored `protocols/line-codes` into a clean three-layer cocotb layout backed by a shared helper in `tests/protocols/line_codes/line_code_test_utils.py`: direct package benches via checked-in `Code*PkgWrapper.vhd` adapters, direct `Encoder*`/`Decoder*` entity benches, and small end-to-end integration smokes that reuse the legacy `protocols/line-codes/tb/LineCode*Tb.vhd` shells instead of duplicated wrapper HDL. -- Added permanent checked-in package adapters at `protocols/line-codes/wrappers/Code8b10bPkgWrapper.vhd`, `protocols/line-codes/wrappers/Code10b12bPkgWrapper.vhd`, and `protocols/line-codes/wrappers/Code12b14bPkgWrapper.vhd`, then removed the duplicated `protocols/line-codes/wrappers/LineCode*Wrapper.vhd` files and their matching `test_LineCode*Wrapper.py` benches. -- The direct-entity benches now cover clock-enable gating, flow-control hold behavior, malformed decoder inputs, dual-byte 8b10b lane coverage, and 12b14b debug-disparity handoff through `test_Encoder*.py` and `test_Decoder*.py`. -- The current line-code validation command is `./.venv/bin/python -m pytest -n 0 -q tests/protocols/line_codes`, and it passes locally with `23 passed`. -- The new package-surface coverage exposed a real `Code12b14bPkg` invalid-K disparity bug; `protocols/line-codes/rtl/Code12b14bPkg.vhd` now leaves `dispOut` unchanged on illegal K requests instead of tripping a GHDL bound-check failure. - -## Current In-Progress Item -- Decide the next non-`pgp3` `protocols/pgp` target now that the shared VC FIFOs and the remaining non-vendor `pgp4/core/rtl` leaves are covered. -- Keep `pgp2b`, `pgp2fc`, `pgp3`, and `pgp4` organized as separate family subpackages with checked-in wrappers rather than falling back to generated shim HDL, but treat `pgp3` as deferred for now. -- Preserve the recent `pgp4` lesson: when the simulation wrapper only exposes stable lock/config surfaces, write the bench around those explicit contracts instead of claiming recovered payload coverage. -- Phase-2 follow-on for `protocols/pgp/pgp4`: broaden the current single payload-bitflip negative test into a small corruption-location matrix that separately covers SOF/header metadata corruption, EOF/tail corruption (including transmitted CRC-field corruption), and 66b header-side framing errors instead of treating all of those cases as equivalent to payload CRC failure. - -## Next 3 Concrete Tasks -- Decide whether the next family pass is deeper directed coverage for the existing `pgp2b`/`pgp2fc` RX and alignment benches or a move into another non-deferred protocol area. -- Keep the `protocols/pgp/pgp4` low-speed leaves on their dedicated lock/config guardrail benches unless a later wrapper explicitly proves the serialized payload path end to end. -- Reuse the new `tests/protocols/pgp/shared/` helper and wrappers if later shared PGP utilities need direct cocotb coverage. - -## Blockers And Risks -- Runtime may grow quickly once configuration-heavy modules are added without careful tiering. -- Wrapper policy must stay narrow or VHDL cruft will accumulate again. -- HDL source coverage is not immediately available with the current local `ghdl` LLVM build; it needs a separate tooling decision if we want it later. - -## Findings Worth Preserving -- For a quick resume, read this file’s `Current Frontier Snapshot`, `Current In-Progress Item`, `Next 3 Concrete Tasks`, and `Findings Worth Preserving` sections before digging through the full log. -- Existing Python regressions are generally the best reusable verification assets. -- Existing VHDL TBs contain useful behavioral intent but are inconsistent as a scalable execution framework. -- Generic-heavy modules strongly favor Python-authored tests. -- Broad repo coverage will require tiering and likely later sharding. -- The initial inventory file should remain small and explicit rather than auto-generated until the schema stabilizes. -- `AxiStreamFifoV2` already has a useful wrapper-plus-Python pattern, and the same shim-first approach works well for later AXI wrappers when the DUT-specific extra signals are kept thin. -- AXI Stream leaves with partially driven sideband fields can upset `cocotbext.axi` sinks under GHDL when those fields stay `U`; for first-pass benches, prefer either wrappers that drive those sidebands deterministically or hand-monitored payload checks when the sidebands are not part of the behavior under test. -- Real-generic overrides are still awkward under the local open-source stack; if a module only needs a small non-default real-generic operating point, prefer baking the stable value into the thin subsystem wrapper over fighting simulator-specific override syntax. -- Some wrapper benches need to stay intentionally narrow on this branch to avoid conflating simulator limitations with RTL failures. In this batch that applies to `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux`. -- The local machine needs a reproducible one-command bootstrap path before test implementation work can move efficiently. -- The bootstrap path is now working locally with `~/ruckus` linked into the repo. -- Bare `python` should not be assumed to exist on `PATH` in this repo's shell environment; use `./.venv/bin/python` for local pytest and helper-script invocations unless the virtualenv is already activated. -- The first shared-helper-based pilot is working; start simple and grow coverage incrementally rather than front-loading every edge case. -- New regressions need to live in subsystem packages from the start; do not add more flat `tests/test_*.py` files. -- The current Homebrew `ghdl` install is sufficient for cocotb regressions but not for a simple built-in HDL coverage flow. -- The existing `AxiLiteAsyncTb.vhd` is useful as intent/reference, but it is not an appropriate long-term wrapper because it embeds clocks, memories, and transaction logic; `AxiLiteAsyncIpIntegrator.vhd` is now the cleaner cocotb-facing adapter. -- Future Python regression code should follow the user's preferred two-layer comment style: keep a module-specific `Test methodology` header block under the SLAC banner and also explain major coroutine steps, waits, stimulus phases, and checks in-place for readers who are not already comfortable with cocotb. -- Future Python regression code should also keep the standard SURF/SLAC file header itself; do not treat the methodology block as a substitute for the normal repo banner. -- The methodology block should use wrapped `Sweep`, `Stimulus`, `Checks`, and `Timing` bullets and describe the real bench behavior, not generic filler text. -- The same “write it readable on the first pass” rule applies to permanent cocotb-facing VHDL wrappers: checked-in `*IpIntegrator.vhd` files should carry the standard SURF banner and short section comments for shim setup, DUT hookup, and flattening/status wiring. -- `FifoAsync` needed a curated matrix rather than a naive Cartesian sweep: standard FIFO mode, FWFT mode, and pipelined FWFT do not share identical read/full semantics. -- VHDL packages should not become top-level test targets by default; only high-value behavioral helpers warrant dedicated wrapper tests. -- `FifoSync` benefits from the same curated-matrix approach as `FifoAsync`, but its threshold checks needed event-driven flag handling because `prog_full`/`prog_empty` timing did not line up with fixed write-count assumptions. -- The instantiation graph is useful for rollout planning because it exposes both high-reuse leaves and likely duplicated coverage paths; it should guide prioritization, not dictate exact test depth. -- The generated path-qualified queue in `rtl_phase1_queue.{md,json}` is now the operational phase-1 order. Use the graph for provenance and regeneration, and use `rtl_phase1_queue_overrides.json` for justified defer/reorder exceptions instead of hand-maintaining queue text in the plan doc. -- The first graph pass surfaced `Synchronizer`, `SynchronizerVector`, `SimpleDualPortRam`, `FifoOutputPipeline`, `FifoRdFsm`, and `FifoWrFsm` as concrete `base/` bottom-up candidates after the FIFO pilots. -- Duplicate entity names are common in SURF due to dummy/vendor variants, so graph consumers need to read path context rather than rely on entity names alone. -- A generated path-qualified queue is practical under the current graph parser: the first pass yields `411` phase-1 modules with `0` unresolved duplicate-name phase-1 edges under the checked-in filter set. -- Keep `docs/_meta/rtl_phase1_queue_overrides.json` small and explicit. It should record only real phase-1 scope decisions or blocker-driven order exceptions, not day-to-day queue churn. -- Direct cocotb tests for simple SURF leaf modules still need to account for `TPD_G` when sampling outputs after clock or reset events; sampling exactly at the nominal edge can create false negatives. -- Simple RAM tests benefit from a small startup warm-up and conservative read sampling so direct and registered output configurations share one stable helper. -- For leaf modules with combinational outputs derived from current request inputs, pulse-based tests should drop the request before sampling post-edge state or they may observe the next pending transaction instead of the one just accepted. -- The local GHDL flow rejects direct command-line overrides of a 32-bit `slv` generic in `Crc32`; when a parameterized leaf still needs expanded coverage, prefer a thin test-only wrapper over simulator-specific literal hacks. -- For repeated real-generic shim cases, generated test-local wrappers are a better default than checking in one VHDL file per module; they keep the workaround explicit without growing permanent HDL debris. -- `COMMON_CLK_G` style benches need truly shared edges, not just same-period clocks. A single cocotb coroutine that drives both clocks in lockstep is the safer default for those wrappers. -- Integration-wrapper tests should stay narrow and wrapper-specific. `Fifo` validated both inferred sync/async wrapper branches, `FifoCascade` validated public stage-vector plumbing plus a curated output smoke, and `FifoMux` is currently validated only on the stable split-to-narrow path while the packed-write branch remains deferred. -- `SyncClockFreq` is stable under the generated-wrapper approach, but the common-clock path quantizes one count above the abstract frequency target under GHDL, so the regression checks a bounded expected range instead of an over-precise exact integer. -- `SyncTrigRate` is now covered as a wrapper/integration bench: it validates aligned update publication, denser-window rate growth, reset-path liveness, and update-strobe pulse behavior. Exact min/max pipeline arithmetic remains covered by the dedicated `SyncMinMax` leaf regression rather than being re-proven through the wrapper. -- `LutFixedDelay` is the lone non-dummy `base/` entity still deferred in phase 1 because it depends on `SinglePortRamPrimitive`, which is currently only available through the vendor/dummy-backed path. -- `AxiStreamPipeline` is stable with a thin flat-port wrapper. The zero-stage case should be checked as true pass-through, while staged cases should be checked against the wrapper-visible latency of `PIPE_STAGES_G + 2` clocks and a bounded reset flush rather than an over-precise internal-stage assumption. -- `AxiStreamMux` is stable with a thin two-input adapter, but its `disableSel` handling composes with the separate priority-masking step in a non-obvious order: a disabled higher-priority source can still suppress lower-priority requesters. Disable-focused benches should either use equal priorities or mask the lower-priority source instead. -- `AxiStreamMux` interleave and explicit rearbitrate branches remain intentionally out of scope for the first wrapper bench; the validated subset is indexed arbitration plus `disableSel`, routed `TDEST`/`TID` remap under backpressure, and staged reset/recovery in passthrough mode. -- `AxiStreamDeMux` is stable with a thin one-input/two-output adapter. The first bench covers indexed decode, exact-match routed decode under output backpressure, and dynamic-route table behavior including unmatched-destination drop and staged reset flush. Broader wildcard-route patterns and larger fanout counts remain intentionally unproven in this first wrapper bench. -- `AxiLiteCrossbar` is practical under the current open-source flow with a thin cocotb-facing wrapper around the cascaded topology. The useful regression surface is routed-region correctness, decode-miss `DECERR` handling, and concurrent traffic through the cascaded topology, not a giant generic sweep. -- SURF already has reusable AXI record-flattening shims. New AXI Stream and AXI-Lite wrappers should prefer the existing IP-integrator shim layers over hand-written record packing, and only custom-wire the DUT-specific extra side signals on top. -- More generally, any VHDL shim layer added only to make a module fit cleanly into cocotb should live in the nearest real subsystem `ip_integrator/` tree, not under `tests/` and not under generic `hdl/` directories. -- If that shim layer is checked in instead of generated locally, treat it like normal repo HDL rather than disposable glue: add the standard header and enough section comments that the adapter structure is obvious during a later resume. -- Apply the same “first-draft readability” rule to checked-in cocotb tests: standard header first, methodology block second, tutorial comments in the body. -- `AxiReadPathMux` and `AxiWritePathMux` are more stable with tiny source-side pin drivers than with `cocotbext.axi` masters because the muxes rewrite IDs internally; the downstream shared-port checks can still use the library RAM models. -- `protocols/line-codes` is cleaner when split into three layers: direct package benches for exhaustive legal-space and explicit disparity-seed checks, direct `Encoder*`/`Decoder*` entity benches for clock/reset/flow-control behavior, and one small family-level integration smoke that proves the encoder-to-decoder chain still matches the legacy shell. -- For the line-code families, keep the shared Python harness generic and keep legality decisions local to each module bench. `8b10b` varies by byte-lane width, `10b12b` uses the curated `x & 28` K-symbol subset from the legacy bench, and `12b14b` also preserves its historical mixed training pattern plus explicit malformed-decode and illegal-K checks. -- For line-code package coverage, prefer checked-in subsystem wrappers only where the package surface truly needs explicit disparity seeding or direct encode/decode visibility. `Code8b10bPkg`, `Code10b12bPkg`, and `Code12b14bPkg` all follow that pattern now; the family integration layer should reuse existing `tb/LineCode*Tb.vhd` shells rather than cloning them into new wrapper HDL. -- The new package-surface tests are strong enough to expose latent package bugs. In this batch they caught an illegal-K path defect in `Code12b14bPkg` where the package could drive an out-of-range disparity sum; that path is now fixed and should stay covered. -- The current `Code12b14b` cocotb coverage preserves the legacy explicit disparity seeds plus the training/transition sequences, but it still does not carry forward the old VHDL bench's stateful run-length monitor as a passing assertion. Treat that run-length monitor as a known follow-up gap rather than silently assuming it is covered. -- `AxiToAxiLite` is practical with a thin bridge-local adapter, but mixed-width checks need to stay single-beat on the AXI side when the downstream response path is fundamentally AXI-Lite-like. -- `AxiResize` still has an expected verification-branch gap: the restored `32-bit -> 64-bit` upsize case in `tests/axi/axi4/test_AxiResize.py` should keep failing here until the separate RTL-fix branch is merged. -- `AxiRateGen` is practical with the existing AXI4 and AXI-Lite IP-integrator shim pair plus a cocotb AXI RAM model, and the stable first-pass subset is the `COMMON_CLK_G=true` path with timer spacing, zero-fill writes, and generated-read completion rather than the asynchronous AXI-Lite crossing branches. -- For protocol-generator or wrapper-style benches, pair end-state checks with explicit accepted-handshake monitoring whenever the externally visible contract includes timing, burst shape, sideband propagation, or arbitration order. -- The SSI helper layer is now broad enough to justify reuse across the whole subsystem: `FlatSsiEndpoint`, `SsiBeat`, `recv_frame`, contiguous frame driving, optional `TID` handling, and no-output checks cover the current flattened SSI wrappers without each bench re-implementing handshake plumbing. -- `SsiInsertSof` is practical with a small SSI-local wrapper that exposes semantic SOF/EOFE controls instead of treating raw `TUSER` layout as the cocotb API. The currently validated subset keeps `COMMON_CLK_G=true` and FIFO-backed paths enabled; raw `TUSER_MASK_G` bit-level expectations are still a follow-up item if we want to pin down SSI user-bit indexing more aggressively. -- `SsiIbFrameFilter` is practical with the same semantic-wrapper approach, but the wrapper should use native SSI `TUSER_FIRST_LAST_C` encoding rather than a generic normal-user layout so cocotb can drive `SOF`/`EOFE` directly and the DUT sees the expected first/last byte markers. -- `SsiObFrameFilter` is practical with the same native-SSI wrapper contract. The checked-in bench now covers good-frame pass-through, missing-SOF drop, repeated-`SOF` termination, mid-frame `TDEST` termination, the cached-last-user `VALID_THOLD_G=0` `EOFE` drop path with exported drop-flag pulses, and one pipelined `PIPE_STAGES_G=2` pass-through case without relying on fixed latency assumptions. -- `SsiFifo` is practical with the same flat SSI wrapper pattern, but contiguous multi-beat checks need handshake-based observation rather than late frame collection. The earlier apparent middle-beat loss on a 3-beat `SsiFifoWrapper` probe turned out to be a receive-helper artifact; once the helper was corrected to capture accepted handshakes, both `SsiIbFrameFilter` and `SsiFifo` preserved the full frame and the checked-in `SsiFifo` regression could safely add real 3-beat pass-through assertions on the default, frame-ready, and thresholded paths plus a repeated-`SOF` termination check on the composite FIFO wrapper. -- The first reusable SSI Python helper can now absorb whole-frame receive and metadata-extension commonality, but it should still stop short of becoming a golden protocol model. Module-specific policy such as header injection, command decode rules, or filter-drop counters should remain in each bench. -- `AxiStreamDmaV2Read` is stable with a thin IP-integrator wrapper once the read-path byte-count conversions stay bounded to the burst-size window. The checked-in bench proves both aligned and short terminal-beat reads; because the wrapper exports only an 8-bit `TUSER`, the observable contract is first-user propagation rather than separate first/last byte tagging. -- The `axi/dma/rtl/v2/` benches are now intentionally split by behavior instead of repeatedly re-proving the same path through the top-level DMA stack: `AxiStreamDmaV2` and `AxiStreamDmaV2Desc` stay focused on descriptor-manager register/control surfaces, `AxiStreamDmaV2Read` owns aligned and short terminal-beat readout, `AxiStreamDmaV2Write` owns descriptor-return integrity plus burst splitting, `AxiStreamDmaV2WriteMux` owns arbitration ordering, and `AxiStreamDmaV2Fifo` owns the integrated FIFO register/count/pause-threshold surface. -- For checked-in VHDL changes, use the repo virtualenv's `vsg` with `vsg-linter.yml` so local lint matches CI, and prefer `--fix` before manual spacing/alignment cleanup. -- The current `EthMacCore` wave has a few wrapper-visible behavior details worth preserving in the docs instead of rediscovering later: the XGMII import/export loopback retains a frame presented during `phyReady=0` and drains it after link recovery with Ethernet minimum-size padding applied, while the GMII path drops it; `EthMacRxCsum` reliably asserts `IPERR` on a bad IPv4 header checksum but the checked-in wrapper contract does not require `EOFE` on that case; and the RX/TX shift benches need a small idle-plus-settle gap before changing runtime shift controls because the underlying `AxiStreamShift` samples those controls from its IDLE state. -- Verification hygiene now includes process cleanup: if a `pytest`/cocotb/GHDL step leaves stale run trees behind, kill those leftovers immediately before starting another compile or simulation command. - -## Log -- 2026-03-20: Agreed on Python-only executable regression logic and wrapper-only VHDL retention. -- 2026-03-20: Agreed on whole-repo scope with simulator-friendly phase 1 and vendor-heavy deferral. -- 2026-03-20: Agreed to add stable handoff artifacts under `docs/_meta/` before deeper implementation work. -- 2026-03-20: Added `docs/_meta/rtl_regression_inventory.yaml` and seeded it with the first three pilot modules. -- 2026-03-20: Added local bootstrap helpers in `scripts/setup_regression_env.sh` and `.vscode/tasks.json`. -- 2026-03-20: Installed local toolchain and completed the first successful `make MODULES="$PWD" import`. -- 2026-03-20: Added `tests/regression_utils.py` and landed the first passing pilot regression for `FifoAsync`. -- 2026-03-20: Moved new regression infrastructure to `tests/common/`, relocated `FifoAsync` to `tests/base/fifo/`, and documented the subsystem-organized test layout. -- 2026-03-20: Checked local HDL coverage viability; the installed LLVM-backed `ghdl` rejects `--coverage`, so HDL coverage is deferred pending a different simulator/backend decision. -- 2026-03-20: Migrated `AxiStreamFifoV2` into `tests/axi/axi_stream/` and validated the full current 10-case sweep in 146s. -- 2026-04-02: Expanded `tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py` to cover `VALID_THOLD` release behavior, burst gating, dynamic pause control, `CASCADE_SIZE=2`, and `S_HAS_TREADY=0`, and revalidated it locally with `10 passed`. -- 2026-04-02: Merged `verification` into `fix-axi-resize`, reran `tests/axi/axi4/test_AxiResize.py`, and confirmed the previous `32-bit -> 64-bit` upsize `xfail` now passes on this branch; removed the stale `xfail`. -- 2026-04-02: Expanded the `axi/dma/rtl/v2/` regression split without broad overlap. `tests/axi/dma/test_AxiStreamDmaV2Write.py` now covers both single-frame and multi-burst writes, `tests/axi/dma/test_AxiStreamDmaV2WriteMux.py` now covers descriptor-first, simultaneous-launch, and data-first arbitration cases, and `tests/axi/dma/test_AxiStreamDmaV2Fifo.py` now covers the integrated FIFO register map plus dynamic pause-threshold behavior against the live write-buffer count. The combined validation run across `tests/axi/dma/test_AxiStreamDmaV2.py`, `tests/axi/dma/test_AxiStreamDmaV2Desc.py`, `tests/axi/dma/test_AxiStreamDmaV2Read.py`, `tests/axi/dma/test_AxiStreamDmaV2Write.py`, `tests/axi/dma/test_AxiStreamDmaV2WriteMux.py`, and `tests/axi/dma/test_AxiStreamDmaV2Fifo.py` passes locally with `9 passed`. -- 2026-04-02: Started the `protocols/line-codes` refactor by moving the family benches onto a shared helper in `tests/protocols/line_codes/line_code_test_utils.py` and by adding checked-in package-surface wrappers for `Code8b10bPkg`, `Code10b12bPkg`, and `Code12b14bPkg`. -- 2026-04-02: Compared the cocotb line-code coverage against the legacy VHDL benches under `protocols/line-codes/tb/`, preserved the legacy disparity-seed and training-pattern intent in the `Code*Pkg` Python benches, and noted the old `Code12b14bTb.vhd` run-length monitor as the only still-unported legacy assertion. -- 2026-04-02: Completed the clean-slate line-code redesign: deleted the duplicated `LineCode*Wrapper.vhd` and `test_LineCode*Wrapper.py` layer, added direct `test_Encoder*.py` and `test_Decoder*.py` benches against the real RTL entities, reused `protocols/line-codes/tb/LineCode*Tb.vhd` as the thin integration shells, fixed an illegal-K disparity bug in `protocols/line-codes/rtl/Code12b14bPkg.vhd`, and validated the full `tests/protocols/line_codes` directory locally with `23 passed`. -- 2026-04-03: Added `dsp/` back into `scripts/build_rtl_instantiation_graph.py` so the regenerated `docs/_meta/rtl_instantiation_graph.{md,json}` and `docs/_meta/rtl_phase1_queue.{md,json}` artifacts now track `dsp/generic/fixed` alongside the other phase-1 subsystems. -- 2026-04-03: Implemented `tests/dsp/generic/test_DspAddSub.py` as the first post-resume DSP leaf bench, replacing the old free-running `dsp/generic/tb/DspAddSubTb.vhd` stimulus with explicit signed add/sub arithmetic checks plus backpressure-hold and reset-clearing assertions. The module-local validation run passes locally with `2 passed`. -- 2026-04-03: Completed the planned `dsp/generic/fixed` cocotb leaf batch. Added new benches for `FirFilterTap`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`; centralized shared DSP timing/model/wrapper helpers in `tests/dsp/generic/dsp_test_utils.py`; added explicit sim-build-key support for generated wrappers in `tests/common/regression_utils.py`; fixed RTL issues in `FirFilterTap`, `BoxcarIntegrator`, and `FirFilterSingleChannel`; and validated the full directory with `15 passed`. -- 2026-04-06: Started the manual `protocols/ssi` rollout with `SsiInsertSof`. Added the checked-in wrapper `protocols/ssi/wrappers/SsiInsertSofWrapper.vhd`, implemented `tests/protocols/ssi/test_SsiInsertSof.py`, validated the three-case FIFO-backed sweep locally with `3 passed`, and linted the wrapper cleanly with `vsg -c vsg-linter.yml -f`. -- 2026-04-06: Validated the narrow next SSI step with `SsiIbFrameFilter`. Added the checked-in native-SSI wrapper `protocols/ssi/wrappers/SsiIbFrameFilterWrapper.vhd`, implemented `tests/protocols/ssi/test_SsiIbFrameFilter.py`, validated the first-pass same-clock sweep locally with `1 passed`, linted the wrapper cleanly with `vsg --fix -c vsg-linter.yml -f`, and then consolidated shared flat SSI driver/sink timing into `tests/protocols/ssi/ssi_test_utils.py` so `test_SsiInsertSof.py` and `test_SsiIbFrameFilter.py` use the same basic endpoint helper layer. -- 2026-04-06: Added the next outbound SSI step with `SsiObFrameFilter`. Added the checked-in native-SSI wrapper `protocols/ssi/wrappers/SsiObFrameFilterWrapper.vhd`, implemented `tests/protocols/ssi/test_SsiObFrameFilter.py`, validated the narrowed default-mode regression locally with `1 passed`, revalidated the current SSI trio with `5 passed`, and linted the wrapper cleanly with `vsg --fix -c vsg-linter.yml -f`. The stable checked-in subset covers good-frame pass-through plus repeated-`SOF` termination with `PIPE_STAGES_G=0`; the cached-last-user `EOFE` branch for `VALID_THOLD_G=0` remains a follow-up item. -- 2026-04-06: Added the next composite SSI step with `SsiFifo`. Added the checked-in wrapper `protocols/ssi/wrappers/SsiFifoWrapper.vhd`, implemented `tests/protocols/ssi/test_SsiFifo.py`, validated the narrowed smoke regression locally with `1 passed`, and linted the wrapper cleanly with `vsg --fix -c vsg-linter.yml -f`. The stable checked-in subset keeps one physical clock and currently proves valid single-beat pass-through plus missing-SOF drop; multi-beat good-frame integrity, buffered occupancy behavior, and the sync-output gearbox branch remain follow-up items. -- 2026-04-06: Completed the remaining manual `protocols/ssi` leaf batch. Added checked-in wrappers `protocols/ssi/wrappers/SsiCmdMasterPulserWrapper.vhd`, `protocols/ssi/wrappers/SsiCmdMasterWrapper.vhd`, `protocols/ssi/wrappers/SsiFrameLimiterWrapper.vhd`, `protocols/ssi/wrappers/SsiIncrementingTxWrapper.vhd`, `protocols/ssi/wrappers/SsiAxiLiteMasterWrapper.vhd`, and `protocols/ssi/wrappers/SsiDbgTapWrapper.vhd`; added `tests/protocols/ssi/test_SsiCmdMasterPulser.py`, `tests/protocols/ssi/test_SsiCmdMaster.py`, `tests/protocols/ssi/test_SsiFrameLimiter.py`, `tests/protocols/ssi/test_SsiIncrementingTx.py`, `tests/protocols/ssi/test_SsiAxiLiteMaster.py`, and `tests/protocols/ssi/test_SsiDbgTap.py`; extended `tests/protocols/ssi/ssi_test_utils.py` with optional `TID` handling plus shared frame-receive helpers; validated the new six-test batch locally with `6 passed`; and kept wrapper lint clean under `vsg --fix -c vsg-linter.yml -f` plus a clean follow-up lint pass. The current scope is intentionally uneven: `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiIncrementingTx`, and `SsiAxiLiteMaster` have functional first-pass checks, `SsiFrameLimiter` is currently a narrowed single-beat/missing-SOF subset, and `SsiDbgTap` is traffic smoke only because the RTL exposes no externally visible state. -- 2026-04-07: Tightened the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` so flat SSI sources wait for a real handshake edge and shared frame receivers capture accepted handshakes instead of inferring contiguous traffic from post-send snapshots. Revalidated the existing SSI slice locally with `19 passed`. A focused follow-up on `SsiIbFrameFilter` and `SsiFifo` showed the earlier apparent 3-beat middle-word loss was a bench observation bug rather than an RTL bug, after which the checked-in `SsiFifo` regression added a real contiguous 3-beat pass-through assertion and the `SsiAxiLiteMaster` / `SsiIncrementingTx` benches were updated to assert the full emitted frame shapes. -- 2026-04-07: Expanded `tests/protocols/ssi/test_SsiFifo.py` beyond the earlier single-beat subset. The checked-in FIFO bench now proves contiguous 3-beat frame preservation on the default, `VALID_THOLD_G=0`, and `VALID_THOLD_G=2` wrapper paths; exercises repeated-`SOF` malformed-frame handling across the buffered modes; and keeps the existing missing-`SOF` drop plus `SLAVE_READY_EN_G=false` overflow checks. The buffered malformed-frame result is mode-specific at the wrapper boundary: `VALID_THOLD_G=0` drops the malformed repeated-`SOF` frame outright, while `VALID_THOLD_G=2` emits the expected two-beat terminated `EOFE` frame. A follow-up backpressure pass also added explicit drain-side ready toggling on a good 5-beat frame, malformed termination under toggled ready, and thresholded release under intermittent drain stalls so SSI frame policy is now checked under nontrivial sink backpressure without duplicating the full `AxiStreamFifoV2` transport matrix. Revalidated the full touched SSI slice locally with `19 passed`. -- 2026-04-10: Landed the first manual `ethernet/EthMacCore` bench wave under `tests/ethernet/EthMacCore/`, added the required checked-in wrappers under `ethernet/EthMacCore/wrappers/`, and validated the baseline 12-module slice covering `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`. -- 2026-04-10: Expanded that same `EthMacCore` slice beyond the initial happy paths. The checked-in Ethernet MAC suite now covers `EthMacTop` filter/backpressure/checksum/pause interactions, GMII and XGMII import/export plus link-not-ready recovery behavior, checksum negative cases, filter multicast/broadcast/filter-disable/multi-beat-drop behavior, shift runtime-control and control-bit propagation edges, and full byte-width `1..16` logic-path coverage for `EthCrc32Parallel`. The full `tests/ethernet/EthMacCore` directory currently passes locally with `32 passed`. -- 2026-04-17: Expanded the `ethernet/EthMacCore` slice into the deeper assembly layer. The checked-in Ethernet MAC benches now also cover `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo` through the existing subsystem-local wrappers under `ethernet/EthMacCore/wrappers/`. -- 2026-04-17: Added the manual `ethernet/UdpEngine` wave under `tests/ethernet/UdpEngine/`. The checked-in helper layer now lives in `tests/ethernet/UdpEngine/udp_test_utils.py`, the new checked-in wrappers live under `ethernet/UdpEngine/wrappers/`, and the locally validated benches cover `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`. The current local validation command `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/UdpEngine/test_ArpIpTable.py tests/ethernet/UdpEngine/test_UdpEngineArp.py tests/ethernet/UdpEngine/test_UdpEngineDhcp.py tests/ethernet/UdpEngine/test_UdpEngineRx.py tests/ethernet/UdpEngine/test_UdpEngineTx.py tests/ethernet/UdpEngine/test_UdpEngine.py tests/ethernet/UdpEngine/test_UdpEngineWrapper.py` passes with `7 passed`. -- 2026-04-17: Added the manual `ethernet/IpV4Engine` wave under `tests/ethernet/IpV4Engine/`. The checked-in helper layer now lives in `tests/ethernet/IpV4Engine/ipv4_test_utils.py`, the checked-in wrappers live under `ethernet/IpV4Engine/wrappers/`, and the validated benches cover `ArpEngine`, `IcmpEngine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`. -- 2026-04-17: Added `ethernet/IpV4Engine/wrappers/IgmpV2EngineWrapper.vhd` plus `tests/ethernet/IpV4Engine/test_IgmpV2Engine.py`, extending the IPv4 helper layer with IGMP packet builders in `tests/ethernet/IpV4Engine/ipv4_test_utils.py`. The new leaf bench covers power-up membership reports, general-query re-arming, and suppression of a pending local report when a matching inbound membership report is observed, while documenting the two leaf-boundary stale-field quirks that `IpV4EngineTx` ignores. -- 2026-04-16: Merged the current `pre-release` branch into `verification-2`, so this branch line now contains the already-landed SSI and PGP waves from PR #1391 and PR #1392 in addition to the manual Ethernet slice. -- 2026-04-16: Refreshed the planning docs to move the active frontier from “continue Ethernet next” to “refresh the stale queue/override inputs, then resume from the real merged-branch frontier.” -- 2026-04-17: Switched the planning docs from queue-driven task selection to user-directed frontier tracking. The graph and queue artifacts remain checked in for provenance, but `rtl_regression_progress.md` and `rtl_regression_handoff.md` are now the active done/open source of truth. -- 2026-04-17: Expanded `tests/ethernet/RawEthFramer/test_RawEthFramerTx.py` to cover the successful multi-beat unicast forwarding path after lookup resolution. The new leaf test holds the source frame through the exported request phase, models the same nonzero lookup latency the integrated `RawEthFramer` wrapper inserts before `ack`, and validates the full MAC-side wire image alongside the existing request, broadcast-bypass, and zero-MAC drop checks. -- 2026-04-17: Completed the Ethernet thin-area follow-up across `EthMacCore`, `UdpEngine`, and `IpV4Engine`. Added checked-in wrappers `ethernet/EthMacCore/wrappers/EthMacRxBypassWrapper.vhd` and `ethernet/EthMacCore/wrappers/EthMacTxBypassWrapper.vhd`, added `tests/ethernet/EthMacCore/test_EthMacRxBypass.py` and `tests/ethernet/EthMacCore/test_EthMacTxBypass.py`, widened `test_EthMacRxImport.py` / `test_EthMacTxExport.py` to cover the current placeholder `XLGMII` contract, widened `tests/ethernet/UdpEngine/test_UdpEngine.py` and `tests/ethernet/UdpEngine/test_UdpEngineWrapper.py` across additional client/server routing paths, widened `tests/ethernet/IpV4Engine/test_IpV4Engine.py` with a top-level protocol-TX path, and deepened `tests/ethernet/IpV4Engine/test_IcmpEngine.py` with truncated-request rejection, EOFE preservation, and post-reject recovery checks. The combined local validation command `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/EthMacCore/test_EthMacRxImport.py tests/ethernet/EthMacCore/test_EthMacTxExport.py tests/ethernet/EthMacCore/test_EthMacRxBypass.py tests/ethernet/EthMacCore/test_EthMacTxBypass.py tests/ethernet/UdpEngine/test_UdpEngine.py tests/ethernet/UdpEngine/test_UdpEngineWrapper.py tests/ethernet/IpV4Engine/test_IpV4Engine.py tests/ethernet/IpV4Engine/test_IcmpEngine.py` passes locally with `14 passed`. -- 2026-03-20: Added an explicit project rule to comment new Python regression code where intent or runner behavior is not self-evident. -- 2026-03-20: Expanded `FifoAsync` to a validated 12-case parameter matrix and enabled default pytest xdist parallelization with `pytest.ini`. -- 2026-03-20: Added package-coverage policy: packages are covered transitively unless a behavioral helper warrants a dedicated wrapper test. -- 2026-03-20: Switched from pilot-only work to the bottom-up rollout and selected `FifoSync` as the next low-level target. -- 2026-03-20: Implemented and validated an 11-case `FifoSync` matrix under `tests/base/fifo/test_FifoSync.py`. -- 2026-03-20: Added and generated the first-pass RTL instantiation graph to guide bottom-up rollout decisions and reduce repeated test effort across the hierarchy. -- 2026-03-20: Implemented and validated a 6-case `Synchronizer` matrix under `tests/base/sync/test_Synchronizer.py` as the next graph-guided `base` leaf. -- 2026-03-20: Documented that local Python commands should use `./.venv/bin/python` unless the virtualenv is already activated, after a bare `python` invocation failed due to a missing shell shim. -- 2026-03-20: Implemented and validated the next five graph-guided `base` regressions: `SynchronizerVector`, `RstPipeline`, `SimpleDualPortRam`, `FifoOutputPipeline`, and `FifoWrFsm`. -- 2026-03-20: Updated the planning and handoff docs to preserve the user's tutorial-style cocotb comment preference for future regressions. -- 2026-03-20: Implemented and validated the next 10 graph-guided `base` regressions: `Crc32Parallel`, `Crc32`, `CRC32Rtl`, `RstSync`, `PwrUpRst`, `SynchronizerEdge`, `SynchronizerOneShot`, `TrueDualPortRam`, `LutRam`, and `FifoRdFsm`. -- 2026-03-20: Expanded `Crc32` coverage beyond the default IEEE polynomial to include Castagnoli and Koopman-style cases, using a thin test-only VHDL wrapper because local GHDL rejected direct runtime overrides of the 32-bit `CRC_POLY_G` vector generic. -- 2026-03-20: Implemented and validated the next 15 graph-guided `base` regressions: `Arbiter`, `ClockDivider`, `Debouncer`, `Gearbox`, `Heartbeat`, `Mux`, `OneShot`, `RegisterVector`, `RstPipelineVector`, `Scrambler`, `WatchDogRst`, `SlvDelay`, `SlvFixedDelay`, `SynchronizerFifo`, and `SynchronizerOneShotCnt` (`41 passed`). -- 2026-03-21: Replaced the checked-in `Heartbeat`/`Debouncer` wrapper files with a shared generated-wrapper helper in `tests/common/regression_utils.py` and revalidated both the targeted tests (`6 passed`) and the full 15-module batch (`41 passed`). -- 2026-03-21: Implemented and validated the next 10-module wrapper/integration batch: `DspComparator`, `Fifo`, `FifoCascade`, `FifoMux`, `AsyncGearbox`, `SynchronizerOneShotVector`, `SynchronizerOneShotCntVector`, `SyncStatusVector`, `SyncTrigPeriod`, and `SyncMinMax` (`18 passed`). -- 2026-03-21: Added `start_lockstep_clocks()` in `tests/common/regression_utils.py` for `COMMON_CLK_G` style benches and recorded that `FifoCascade`/`FifoMux` should keep intentionally narrow wrapper coverage under the current GHDL flow instead of forcing unstable branches. -- 2026-03-21: Implemented and validated the remaining non-vendor, non-dummy `base/` batch: `MasterRamIpIntegrator`, `SlaveRamIpIntegrator`, `DualPortRam`, `SlvDelayRam`, `SlvDelayFifo`, `SyncClockFreq`, `SyncTrigRate`, and `SyncTrigRateVector` (`15 passed`). `LutFixedDelay` remains deferred because it still depends on `SinglePortRamPrimitive`. -- 2026-03-21: Tightened the comment policy for Python regressions: header-level methodology comments and in-body tutorial comments are both required, the methodology block should use wrapped `Sweep`/`Stimulus`/`Checks`/`Timing` bullets, and the text should stay module-specific and editor-readable. -- 2026-03-21: Started the first post-`base/` simulator-friendly `axi/` follow-on with `AxiStreamPipeline` and `AxiLiteCrossbar` as the next migration targets, using the legacy flat Python benches only as intent/reference while keeping the new work under subsystem-packaged tests. -- 2026-03-21: Implemented and validated `AxiStreamPipeline` and `AxiLiteCrossbar` as the first post-`base/` `axi/` follow-on. `AxiStreamPipeline` uses a thin flat-port wrapper plus a curated pass-through/staged/reset sweep, and `AxiLiteCrossbar` uses a cocotb-facing wrapper for routed-region, decode-error, and concurrent-traffic checks (`4 passed` combined). -- 2026-03-21: Refactored the `AxiStreamPipeline` test adapter to reuse the existing `SlaveAxiStreamIpIntegrator`/`MasterAxiStreamIpIntegrator` shim pair for standard AXIS flattening, preserving only the pipeline-specific sideband wiring in the adapter (`3 passed` on the pipeline regression after the refactor). -- 2026-03-21: Moved and renamed the `AxiStreamPipeline` adapter to `axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd` so its path and name match the existing AXI IP-integrator adapter conventions and live with the rest of the AXI adapter layer. -- 2026-03-21: Tightened the planning rule for cocotb-facing shim placement: if a VHDL adapter is needed to fit a module into cocotb, place it in the nearest real subsystem `ip_integrator/` tree alongside the existing integration shims rather than under `tests/`. -- 2026-03-21: Collapsed the large instantiation-graph output into a reviewed flat phase-1 module build order in `rtl_regression_plan.md` so future windows can take the next queued module directly instead of re-analyzing the JSON graph before every step. -- 2026-03-21: Resumed the flat `axi/` queue at `AxiStreamMux` and chose a dedicated IP-integrator adapter over the existing combined DeMux/Mux harness so the new cocotb bench can stay mux-specific and exercise arbitration plus `TDEST`/`TID` remap behavior directly. -- 2026-03-21: Implemented and validated `AxiStreamMux` with `axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd` plus `tests/axi/axi_stream/test_AxiStreamMux.py`. The validated 3-case sweep covers indexed arbitration with explicit priority and `disableSel`, routed `TDEST`/`TID` remap under backpressure, and staged asynchronous active-low reset recovery (`3 passed`). -- 2026-03-21: Revalidated the current small `axi/` follow-on subset with `tests/axi/axi_stream/test_AxiStreamPipeline.py`, `tests/axi/axi_stream/test_AxiStreamMux.py`, and `tests/axi/axi_lite/test_AxiLiteCrossbar.py` in one run (`7 passed`). -- 2026-03-21: Started the next flat-queue `axi/` item, `AxiStreamDeMux`, and began evaluating whether a dedicated cocotb-facing adapter is cleaner than reusing the older combined DeMux/Mux harness for the first narrow wrapper bench. -- 2026-03-21: Implemented and validated `AxiStreamDeMux` with `axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd` plus `tests/axi/axi_stream/test_AxiStreamDeMux.py`. The validated 3-case sweep covers indexed routing, exact-match routed decode under output backpressure, and dynamic-route/drop/reset behavior (`3 passed`). -- 2026-03-21: Revalidated the current small `axi/` follow-on subset with `tests/axi/axi_stream/test_AxiStreamPipeline.py`, `tests/axi/axi_stream/test_AxiStreamMux.py`, `tests/axi/axi_stream/test_AxiStreamDeMux.py`, and `tests/axi/axi_lite/test_AxiLiteCrossbar.py` in one run (`10 passed`). -- 2026-03-21: Started scoping the next five flat-queue modules after `AxiStreamDeMux`: `AxiStreamResize`, `AxiLiteAsync`, `AxiLiteMaster`, `AxiLiteToDrp`, and `AxiDualPortRam`, beginning with a wrapper/reference-asset pass to separate straightforward benches from blocks that still need adapter cleanup. -- 2026-03-21: Implemented and validated the next five flat-queue modules: `AxiStreamResize`, `AxiLiteAsync`, `AxiLiteMaster`, `AxiLiteToDrp`, and `AxiDualPortRam`. The five-module batch passes with `10 passed`, and a broader AXI follow-on sanity run across pipeline, mux, demux, resize, crossbar, async, master, DRP bridge, and dual-port RAM passes with `20 passed`. `AxiLiteAsync` and `AxiLiteToDrp` intentionally keep only the stable common-clock subsets in this first batch; the async CDC/arbitration branches remain open. -- 2026-03-21: Replaced the hand-maintained flat phase-1 list in the plan with a generated path-qualified bottom-up queue emitted by `scripts/build_rtl_instantiation_graph.py` into `docs/_meta/rtl_phase1_queue.{md,json}`. Checked in `docs/_meta/rtl_phase1_queue_overrides.json` as the only supported input for manual phase-1 deferrals and ordering exceptions; the initial generated queue contains `411` phase-1 modules with `0` unresolved duplicate-name phase-1 edges under the current filter set. -- 2026-03-21: Implemented and validated the next 10 generated-queue AXI modules: `AxiLiteRegs`, `AxiLiteRespTimer`, `AxiLiteSlave`, `AxiLiteWriteFilter`, `AxiVersion`, `AxiStreamCombiner`, `AxiStreamFlush`, `AxiStreamGearboxPack`, `AxiStreamGearboxUnpack`, and `AxiStreamSplitter`. The combined validation command across those 10 module files passes with `14 passed`. -- 2026-03-26: Implemented and validated `AxiReadPathMux`, `AxiWritePathMux`, and `AxiToAxiLite` with subsystem-local IP-integrator adapters plus new `tests/axi/axi4/` and `tests/axi/bridge/` cocotb benches. `tests/axi/axi4/test_AxiResize.py` is also present on this branch, including the restored `32-bit -> 64-bit` upsize case, but that case is expected to fail here until the separate `AxiResize` RTL-fix branch is merged. -- 2026-03-26: Implemented and validated the next 10 generated-queue AXI modules: `AxiStreamDmaV2WriteMux`, `AxiLiteMasterProxy`, `AxiLiteSequencerRam`, `AxiStreamCompact`, `AxiStreamConcat`, `AxiStreamFrameRateLimiter`, `AxiStreamPrbsFlowCtrl`, `AxiStreamRepeater`, `AxiStreamShift`, and `AxiStreamTrailerAppend`. Added subsystem-local wrappers under `axi/dma/ip_integrator/`, `axi/axi-lite/ip_integrator/`, and `axi/axi-stream/ip_integrator/`, plus new cocotb benches under `tests/axi/`. The combined validation run across those 10 module files passes with `10 passed`. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` currently keep intentionally narrow first-pass checks on this branch instead of forcing the less stable simulator corners. -- 2026-03-26: Implemented the next 10 generated-queue AXI module benches: `AxiStreamTrailerRemove`, `AxiRam`, `AxiLiteToIpBus`, `IpBusToAxiLite`, `AxiStreamDmaV2Read`, `AxiStreamGearbox`, `AxiStreamTap`, `AxiStreamDmaRead`, `AxiStreamDmaV2Write`, and `AxiStreamTimer`. The stable 9-module subset passes with `9 passed`, while `AxiStreamDmaV2Read` remains an expected open failure on this branch because the new minimal aligned one-beat reproducer still aborts at `31 ns` inside the DUT with `std_logic_arith.vhdl:2014:9: ARG is too large in CONV_INTEGER`. -- 2026-04-02: Fixed the remaining `AxiStreamDmaV2Read` open issue by bounding the byte-count `conv_integer()` paths in `axi/axi4/rtl/AxiPkg.vhd`, replacing terminal-beat `tKeep`/`tStrb` generation in `axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd` with direct `slv` mask construction, and expanding `tests/axi/dma/test_AxiStreamDmaV2Read.py` into aligned and short-terminal-beat cases. Local validation now passes with `./.venv/bin/python -m pytest -n 0 -q tests/axi/dma/test_AxiStreamDmaV2Read.py` (`2 passed`). -- 2026-03-26: Replaced the temporary legacy-harness `AxiStreamDmaRead` smoke with a cocotb-owned bench plus `AxiStreamDmaReadIpIntegrator.vhd`. The new test drives the DMA request directly, uses a cocotb AXI RAM model, applies output backpressure, and checks payload plus sideband fields without delegating pass/fail to the old VHDL testbench shell (`1 passed`). -- 2026-03-26: Retargeted the remaining legacy-entity holdouts in the current validated set. `AxiRam` now uses `AxiRamIpIntegrator.vhd` plus a cocotb AXI master round-trip bench, `AxiStreamGearbox` now targets `AxiStreamGearboxIpIntegrator.vhd` instead of the old `tb/` shell, and `AxiLiteCrossbar` now targets `AxiLiteCrossbarIpIntegrator.vhd` instead of `AxiLiteCrossbarTb.vhd` (`3 passed` across the retargeted tests). -- 2026-03-26: Resumed the generated queue at `AxiRateGen` and started scoping the cocotb-facing AXI4/IP-integrator pattern for the next `axi/axi4/` regression. -- 2026-03-26: Implemented and validated `AxiRateGen` with `axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd` plus `tests/axi/axi4/test_AxiRateGen.py`. The stable common-clock subset passes with `1 passed`, and a nearby AXI4 sanity run across `AxiReadPathMux`, `AxiWritePathMux`, `AxiRam`, and `AxiRateGen` passes with `4 passed`. -- 2026-03-26: Tightened the planning docs so wrapper readability is explicit instead of implicit: permanent cocotb-facing `*IpIntegrator.vhd` files should include the standard SURF banner and brief section comments in the first edit, just like the Python benches are required to carry their methodology and tutorial comments. -- 2026-03-26: Tightened the planning docs again so the Python-side header rule is explicit too: checked-in cocotb tests should keep the standard SURF/SLAC banner in addition to the required methodology block and tutorial comments; this is now documented as a first-draft requirement rather than an implied cleanup step. -- 2026-03-26: Corrected the queue frontier after noticing the prior resume notes had jumped ahead to `IpV4Engine`. The real next unfinished non-deferred queue entry is `EthMacRxShift`, followed by `EthMacTxExportGmii`, `EthMacTxShift`, `IpV4EngineRx`, `IpV4EngineTx`, `RawEthFramer`, `UdpEngineRx`, `GLinkTxToRx`, `HtspRx`, and `HtspTx`. -- 2026-03-26: Changed the rollout policy to finish `axi/` first before returning to other subsystems. Recorded temporary `ethernet` and `protocols` subsystem deferrals in `docs/_meta/rtl_phase1_queue_overrides.json`, regenerated the queue, and set the active axi frontier to `AxiResize`. -- 2026-03-27: Implemented and validated the final 11 pending `axi/` benches: `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`. Added the required subsystem-local `*IpIntegrator.vhd` wrappers, kept the new Python tests fully commented with the standard SURF header plus methodology/tutorial notes, and validated the final batch with `./.venv/bin/python -m pytest -n 0 -q ...` across the 11 files (`11 passed`). -- 2026-03-27: The new `AxiStreamDmaRingWrite` regression exposed a width-safety issue in the DUT pointer update under GHDL. Fixed `axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd` so `dmaAck.size` is sliced back to the local pointer width before incrementing `nextAddr`, which keeps the logic behavior unchanged for narrower address maps while making the testbench-safe wrapper configuration simulate cleanly. -- 2026-03-26: Implemented and validated the next 10 generated-queue AXI modules after the two known expected-open skips (`AxiResize` and `AxiStreamDmaV2Read`): `AxiStreamScatterGather`, `AxiMemTester`, `AxiStreamDmaV2Desc`, `AxiStreamDmaV2Fifo`, `AxiReadPathFifo`, `AxiWritePathFifo`, `AxiStreamDmaV2`, `AxiStreamBatchingFifo`, `AxiStreamMon`, and `AxiStreamRingBuffer`. Added the required new wrapper files under `axi/axi4/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/`, fixed `tests/common/regression_utils.py` to stringify simulator env values before dispatch, and validated the combined batch with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamScatterGather.py tests/axi/axi4/test_AxiMemTester.py tests/axi/dma/test_AxiStreamDmaV2Desc.py tests/axi/dma/test_AxiStreamDmaV2Fifo.py tests/axi/axi4/test_AxiReadPathFifo.py tests/axi/axi4/test_AxiWritePathFifo.py tests/axi/dma/test_AxiStreamDmaV2.py tests/axi/axi_stream/test_AxiStreamBatchingFifo.py tests/axi/axi_stream/test_AxiStreamMon.py tests/axi/axi_stream/test_AxiStreamRingBuffer.py` (`10 passed`). -- 2026-04-20: Started the first `ethernet/RoCEv2` phase-1 slice with the stable VHDL-only helper leaves instead of the mixed-language top wrappers. Added `ethernet/RoCEv2/wrappers/EthMacPrepareForICrcWrapper.vhd` and `ethernet/RoCEv2/wrappers/EthMacRxCheckICrcWrapper.vhd`, implemented `tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py` and `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, linted both wrappers cleanly with `./.venv/bin/vsg -c vsg-linter.yml -f ...`, validated the pair with `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py` (`2 passed`), and recorded the remaining open RoCEv2 work as the mixed-language wrapper/assembly path rather than claiming full-family coverage. -- 2026-04-20: Added the pure-VHDL RoCEv2 follow-on benches `tests/ethernet/RoCEv2/test_RoceResizeAndSwap.py` and `test_RoceConfigurator.py` plus their checked-in wrappers `ethernet/RoCEv2/wrappers/RoceResizeAndSwapIpIntegrator.vhd` and `RoceConfiguratorWrapper.vhd`, and validated the pure-VHDL RoCEv2 bench set with `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py tests/ethernet/RoCEv2/test_RoceResizeAndSwap.py tests/ethernet/RoCEv2/test_RoceConfigurator.py` (`4 passed`). -- 2026-04-20: Removed the temporary local CRC stand-ins and the stub-backed `EthMacTxRoCEv2` / `EthMacRxRoCEv2` benches after clarifying the intended boundary: there should be one cocotb test module per entity in `ethernet/RoCEv2/rtl`, but `blue-*` must remain real transitive dependencies rather than being replaced with local test doubles. The current open RoCEv2 bench set is therefore `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`, all of which now require a mixed-language simulation path. -- 2026-04-20: Added the next CoaXPress assembly pass with `tests/protocols/coaxpress/test_CoaXPressRx.py`, `test_CoaXPressCore.py`, and the checked-in wrappers `protocols/coaxpress/core/wrappers/CoaXPressRxWrapper.vhd` and `CoaXPressCoreWrapper.vhd`. The validated subset now covers the one-lane `CoaXPressRx` receive assembly and the AXI-Lite-controlled `CoaXPressCore` TX/config assembly path. `tests/protocols/coaxpress/test_CoaXPressConfig.py` was kept in-tree as a skipped investigation bench because the real SRP-driven `CoaXPressConfig` request path does not complete under the current `CoaXPressConfig` / `SrpV3AxiLite` integration, which is now recorded as the remaining pure-VHDL CoaXPress blocker. -- 2026-04-20: Deepened the CoaXPress receive/bridge coverage without changing RTL scope. `test_CoaXPressRxHsFsm.py` now includes a dual-lane step/alignment case, `test_CoaXPressRx.py` now includes a dual-lane lane-rotation integration case through a generalized `CoaXPressRxWrapper.vhd`, `test_CoaXPressRxLane.py` now covers alternate-success control acknowledgments plus truncated-event guardrails, `test_CoaXPressTxLsFsm.py` now covers the slower implemented low-speed-rate trigger cadence with inverted-trigger mapping, and the CXPoF bridge leaf benches now include HKP, negative lane-placement checks, and partial-lane low-speed fill behavior. The focused validation run across those six files passed locally with `8 passed`. From e8ec168cbdf6c59efba22934af72a86f1d8f14fb Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 24 Apr 2026 08:41:08 -0700 Subject: [PATCH 49/92] Expand coaxpress tests. --- docs/_meta/rtl_regression_handoff.md | 4 +- docs/_meta/rtl_regression_progress.md | 2 +- tests/protocols/coaxpress/README.md | 13 ++- .../test_CoaXPressOverFiberBridgeRx.py | 52 ++++++++++++ .../test_CoaXPressOverFiberBridgeTx.py | 80 +++++++++++++++++++ .../coaxpress/test_CoaXPressRxLane.py | 65 +++++++++++++++ .../coaxpress/test_CoaXPressTxLsFsm.py | 67 ++++++++++++++++ 7 files changed, 277 insertions(+), 6 deletions(-) diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index 67ca69e84f..4bebfc2181 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -28,7 +28,7 @@ - `tests/protocols/coaxpress/test_CoaXPressConfig.py` is intentionally checked in as a skipped investigation bench. When driven through the real SRP ingress, the current `CoaXPressConfig` / `SrpV3AxiLite` integration does not complete the request path within the bench timeout, so treat that as a likely RTL or integration defect to debug before re-enabling active assertions there. - `tests/protocols/coaxpress/test_CoaXPressCore.py` now also carries an opt-in skipped known-issue bench for RX backpressure vs. FSM-error behavior. Enable it with `RUN_KNOWN_ISSUE_TESTS=1` and optionally shrink the load with `CXP_RX_OVERFLOW_STORM_FRAME_COUNT=`. The current local reproduction under sustained `M_DATA_TREADY=0` and repeated one-line image frames observed `RxFsmErrorCnt=2` while `RxOverflowCnt=0` at `96` frames, and a narrowing sweep showed no repro at `48` frames but a repro by `72` frames with `RxFsmErrorCnt=1` while `RxOverflowCnt=0`. That is closer to the user report than the earlier directed single-error tests and should be treated as a likely RTL defect under investigation. - For future CoaXPress work, treat the named packet classes and control bytes in `tests/protocols/coaxpress/coaxpress_test_utils.py` as shared spec anchors, not as optional local style. Those constants were normalized against the same `CXP-001-2021` / `CXPR-008-2021` references cited in `CoaXPressPkg.vhd`. Keep the packet-layer names aligned to the spec even where current RTL ports still use legacy `eventAck` naming on the receive side: `0x07` is an event packet and `0x08` is an event acknowledgment. - - The current receive benches are intentionally mixed-depth: control-ack traffic is now driven with fuller spec-shaped framing, but the checked-in `CoaXPressRxLane` / `CoaXPressRx` event tests still only prove the current RTL contract of consuming the event prefix through the Packet Tag field. Do not describe that as full event-payload coverage until the RTL/parser is expanded and the bench follows it. + - The current receive benches are intentionally mixed-depth: control-ack traffic is now driven with fuller spec-shaped framing, and `CoaXPressRxLane` now also guards that event payload/CRC/trailer words after the Packet Tag do not leak into unrelated outputs. The checked-in `CoaXPressRxLane` / `CoaXPressRx` event tests still only prove the current RTL contract of consuming the event prefix through the Packet Tag field. Do not describe that as full event-payload coverage until the RTL/parser is expanded and the bench follows it. - Current planning discipline: - Use manual user-directed area selection as the active source of truth for what to work on next. - Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the actual validated branch frontier. @@ -172,7 +172,7 @@ A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instan ## Immediate Next Task If the user keeps the focus on `protocols/coaxpress`, the next practical step is either: 1. debug and re-enable the skipped `CoaXPressConfig` investigation bench, starting with the SRP-driven request path that currently fails to complete through the real `CoaXPressConfig` / `SrpV3AxiLite` integration, or -2. deepen the remaining spec-level gaps around full receive-side event payload/CRC semantics and fuller CXPoF normative `/Q/`/`/E/` handling. +2. deepen the remaining spec-level gaps around full receive-side event payload/CRC semantics, normative CXPoF `/Q/` sequence handling, and fuller `/E/` / housekeeping-data interaction semantics. If the user switches back to `ethernet/RoCEv2`, the next real step is still enabling a mixed-language cocotb path for the five remaining RTL entities listed above. Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the real validated subset, and do not reintroduce local stand-ins for `blue-*`. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 816baeefc6..314218271f 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -27,7 +27,7 @@ - Blocked bench note: `tests/protocols/coaxpress/test_CoaXPressConfig.py` is checked in as a skipped investigation bench because the real SRP-driven request path does not complete under the current `CoaXPressConfig`/`SrpV3AxiLite` integration. Treat that as a likely RTL or integration defect to debug before re-enabling active assertions on the config return path. - Known-issue bench note: `tests/protocols/coaxpress/test_CoaXPressCore.py` now also carries an opt-in skipped investigation bench for the user-reported RX backpressure path. When enabled with `RUN_KNOWN_ISSUE_TESTS=1`, the bench drives sustained `M_DATA_TREADY=0` pressure with repeated one-line image frames and encodes the expected software-facing behavior that `RxOverflowCnt` should rise before `RxFsmErrorCnt`. The current local reproduction showed `RxFsmErrorCnt=2` while `RxOverflowCnt=0` at `96` frames, and a narrowing sweep showed no repro at `48` frames but a repro by `72` frames (`RxFsmErrorCnt=1`, `RxOverflowCnt=0`), so treat that as a likely RTL defect until narrowed or disproved. - Spec discipline for this family: use the packet/control naming and byte values from `CXP-001-2021` and `CXPR-008-2021` via shared helpers, and keep future top-level/bridge benches explicit about whether they are proving normative spec behavior or only the currently validated RTL subset. At the packet layer, keep the published names even when current RTL signal names drift: `0x07` is an event packet and `0x08` is an event acknowledgment. - - The checked-in RX benches now use more spec-shaped control-ack framing on the wire, include a dual-lane `CoaXPressRxHsFsm` step/alignment case and a dual-lane `CoaXPressRx` lane-rotation case, but the current receive-side event path still only observes the event packet prefix through the Packet Tag field before returning to IDLE. Keep that limitation documented rather than implying full event-payload decode coverage. + - The checked-in RX benches now use more spec-shaped control-ack framing on the wire, include a dual-lane `CoaXPressRxHsFsm` step/alignment case and a dual-lane `CoaXPressRx` lane-rotation case, and guard that receive-lane event payload/CRC/trailer words after the Packet Tag do not leak into unrelated outputs. The current receive-side event path still only observes the event packet prefix through the Packet Tag field before returning to IDLE. Keep that limitation documented rather than implying full event-payload decode coverage. - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. diff --git a/tests/protocols/coaxpress/README.md b/tests/protocols/coaxpress/README.md index a8f1a0d24d..584d3ce5da 100644 --- a/tests/protocols/coaxpress/README.md +++ b/tests/protocols/coaxpress/README.md @@ -132,6 +132,9 @@ Heartbeat and event handling is only partially covered today: - drive a fuller event packet shape, but the current receive RTL only consumes the event prefix through the `Packet Tag` field before returning to `IDLE` + - `test_CoaXPressRxLane.py` also keeps payload, CRC, and `EOP` words in the + stimulus after the tag and checks that they do not leak into config, data, + heartbeat, or extra event outputs before a later clean event is accepted That means these benches do not yet prove full compliance with: @@ -200,20 +203,23 @@ Current checked-in coverage: - start-word control bits - low-speed rate/update handling - partial-lane low-speed payload fill with CoaXPress idle insertion + - single-lane-enable sweeps with rotating idle fill in the disabled slots - payload packing - `/T/` plus `/I/` termination - `test_CoaXPressOverFiberBridgeRx.py` - RX start-word decode for normal packets and `IO_ACK` - HKP forwarding - negative lane-placement checks for `/S/` and `/Q/` + - lane-0 `/Q/` no-output guardrail, `/E/` packet abort behavior, and recovery + to a following valid low-speed packet - `test_CoaXPressOverFiberBridge.py` - top-level 32b/64b gearbox integration around the bridge leaves Still open on the bridge side: - normative `/Q/` sequence handling beyond the current negative guardrails -- explicit `/E/` error handling -- deeper HKP/data-mix coverage +- fuller `/E/` error semantics beyond the current abort-and-recover guardrail +- deeper HKP/data-mix coverage beyond the current HKP forwarding path - broader lane-0-only control-character sweeps ## Known Limitations @@ -235,7 +241,8 @@ The most important open limits are: understood and fixed - receive-side event handling still proves only the current RTL prefix contract - trigger coverage still does not include the broader low-speed extra modes or - the full high-speed trigger matrix + the full high-speed trigger matrix, though the low-speed FSM now covers + active-pulse shortening through a runtime `txPulseWidth` update - CXPoF bridge coverage still does not exhaustively cover normative `/Q/`, `/E/`, and the full housekeeping/data mix diff --git a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py index bb8370a2f1..9176897361 100644 --- a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py +++ b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py @@ -32,6 +32,9 @@ CXP_IO_ACK, CXP_PKT_EVENT_ACK, CXP_SOP, + CXPOF_ERROR, + CXPOF_IDLE, + CXPOF_SEQ, CXPOF_START, cycle, repeat_byte, @@ -139,6 +142,55 @@ async def drive(rxd: int, rxc: int) -> None: ] +@cocotb.test() +async def coaxpress_over_fiber_bridge_rx_sequence_error_and_recovery_test(dut): + # The current bridge RX does not implement a normative /Q/ ordered-set path; + # lock it down as a no-output guardrail, then prove an explicit /E/ in a + # payload aborts the packet without emitting a synthetic CXP EOP and the next + # packet still decodes cleanly. + start_clock(dut.clk) + dut.rst.setimmediatevalue(1) + dut.xgmiiRxd.setimmediatevalue(0x07070707) + dut.xgmiiRxc.setimmediatevalue(0xF) + await reset_dut(dut, clk_name="clk", reset_names=("rst",)) + + observed: list[tuple[int, int]] = [] + + async def drive(rxd: int, rxc: int) -> None: + dut.xgmiiRxd.value = rxd + dut.xgmiiRxc.value = rxc + await cycle(dut.clk, 1) + sample = (int(dut.rxData.value), int(dut.rxDataK.value)) + if sample != (CXP_IDLE, CXP_IDLE_K): + observed.append(sample) + + await drive(CXPOF_SEQ | (0x00 << 8) | (0x12 << 16) | (0x34 << 24), 0x1) + await drive(0x07070707, 0xF) + await drive(0x07070707, 0xF) + + await drive(_cxp_start_word(CXP_PKT_EVENT_ACK), 0x1) + await drive(0x11223344, 0x0) + await drive(CXPOF_ERROR | (CXPOF_IDLE << 8) | (CXPOF_IDLE << 16) | (CXPOF_IDLE << 24), 0x1) + await drive(0x07070707, 0xF) + await drive(0x07070707, 0xF) + + await drive(_cxp_start_word(CXP_PKT_EVENT_ACK), 0x1) + await drive(0x55667788, 0x0) + await drive(0x07FD00FD, 0xC) + await drive(0x07070707, 0xF) + await drive(0x07070707, 0xF) + + assert observed == [ + (CXP_SOP, 0xF), + (repeat_byte(CXP_PKT_EVENT_ACK), 0x0), + (0x11223344, 0x0), + (CXP_SOP, 0xF), + (repeat_byte(CXP_PKT_EVENT_ACK), 0x0), + (0x55667788, 0x0), + (CXP_EOP, 0xF), + ] + + def test_CoaXPressOverFiberBridgeRx(): run_surf_vhdl_test( test_file=__file__, diff --git a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeTx.py b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeTx.py index 182b531387..3ae2b30e85 100644 --- a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeTx.py +++ b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeTx.py @@ -25,7 +25,9 @@ from tests.common.regression_utils import run_surf_vhdl_test from tests.protocols.coaxpress.coaxpress_test_utils import ( + CXP_D21_5, CXP_K28_1, + CXP_K28_5, CXPOF_IDLE, CXPOF_START, CXPOF_TERM, @@ -40,6 +42,24 @@ def _start_word(rate: int, update: int) -> int: return CXPOF_START | (sop_ctrl << 8) +IDLE_BYTES = [CXP_K28_5, CXP_K28_1, CXP_K28_1, CXP_D21_5] +IDLE_IS_K = [1, 1, 1, 0] + + +def _ls_slot(byte: int, is_k: int) -> int: + return (byte << 8) | (0x02 if is_k else 0x01) + + +def _bridge_payload_words(byte: int, is_k: int, lane_enable: int, idle_index: int) -> list[int]: + slots: list[int] = [] + for lane in range(4): + if (lane_enable >> lane) & 0x1: + slots.append(_ls_slot(byte, is_k)) + else: + slots.append(_ls_slot(IDLE_BYTES[idle_index], IDLE_IS_K[idle_index])) + return [slots[0] | (slots[1] << 16), slots[2] | (slots[3] << 16)] + + @cocotb.test() async def coaxpress_over_fiber_bridge_tx_packet_format_test(dut): # Reset into the idle state, then emit two packets with different rate and @@ -157,6 +177,66 @@ async def capture_words(count: int) -> None: ] +@cocotb.test() +async def coaxpress_over_fiber_bridge_tx_lane_enable_idle_rotation_test(dut): + # Sweep each single active low-speed lane over consecutive packets. Disabled + # lanes should be filled with the rotating CoaXPress idle sequence, and the + # update bit should only be set on the first same-rate packet after reset. + start_clock(dut.clk) + dut.rst.setimmediatevalue(1) + dut.txLsValid.setimmediatevalue(0) + dut.txLsData.setimmediatevalue(0) + dut.txLsDataK.setimmediatevalue(0) + dut.txLsRate.setimmediatevalue(1) + dut.txLsLaneEn.setimmediatevalue(0x1) + await reset_dut(dut, clk_name="clk", reset_names=("rst",)) + + observed: list[tuple[int, int]] = [] + + async def capture_words(count: int) -> None: + while len(observed) < count: + await RisingEdge(dut.clk) + await Timer(1, unit="ns") + observed.append((int(dut.xgmiiTxd.value), int(dut.xgmiiTxc.value))) + + async def send_byte(byte: int, lane_enable: int) -> None: + dut.txLsLaneEn.value = lane_enable + dut.txLsData.value = byte + dut.txLsDataK.value = 0 + dut.txLsValid.value = 1 + await RisingEdge(dut.clk) + await Timer(1, unit="ns") + dut.txLsValid.value = 0 + await cycle(dut.clk, 4) + + capture = cocotb.start_soon(capture_words(32)) + for index, lane_enable in enumerate((0x1, 0x2, 0x4, 0x8)): + await send_byte(0xA0 + index, lane_enable) + await capture + + starts: list[tuple[int, list[tuple[int, int]]]] = [] + for index in range(len(observed) - 3): + word, control = observed[index] + if control == 0x1 and (word & 0xFF) == CXPOF_START: + starts.append((word, observed[index : index + 4])) + + assert len(starts) >= 4, observed + for packet_index, (start_word, packet) in enumerate(starts[:4]): + expected_update = 1 if packet_index == 0 else 0 + expected_payload = _bridge_payload_words( + 0xA0 + packet_index, + 0, + 1 << packet_index, + packet_index, + ) + assert start_word == _start_word(rate=1, update=expected_update) + assert packet[1:] == [ + (expected_payload[0], 0x0), + (expected_payload[1], 0x0), + ((CXPOF_IDLE << 24) | (CXPOF_TERM << 16), 0xC), + ] + + def test_CoaXPressOverFiberBridgeTx(): run_surf_vhdl_test( test_file=__file__, diff --git a/tests/protocols/coaxpress/test_CoaXPressRxLane.py b/tests/protocols/coaxpress/test_CoaXPressRxLane.py index 732b5c3d2c..5fd433010b 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRxLane.py +++ b/tests/protocols/coaxpress/test_CoaXPressRxLane.py @@ -205,6 +205,71 @@ async def drive(data: int, data_k: int, *, link_up: int = 1) -> None: ] +@cocotb.test() +async def coaxpress_rx_lane_event_payload_crc_guardrail_test(dut): + start_clock(dut.rxClk) + dut.rxRst.setimmediatevalue(1) + dut.rxLinkUp.setimmediatevalue(1) + dut.rxData.setimmediatevalue(CXP_IDLE) + dut.rxDataK.setimmediatevalue(CXP_IDLE_K) + await reset_dut(dut) + + cfg_beats: list[dict[str, int]] = [] + data_beats: list[dict[str, int]] = [] + heartbeat_beats: list[dict[str, int]] = [] + event_tags: list[int] = [] + + async def drive(data: int, data_k: int) -> None: + await send_rx_word(dut, data=data, data_k=data_k, clk=dut.rxClk) + if int(dut.cfgTValid.value) == 1: + cfg_beats.append({"cfgTData": int(dut.cfgTData.value)}) + if int(dut.dataTValid.value) == 1: + data_beats.append( + { + "dataTData": int(dut.dataTData.value), + "dataTUser": int(dut.dataTUser.value), + "dataTLast": int(dut.dataTLast.value), + } + ) + if int(dut.heartbeatTValid.value) == 1: + heartbeat_beats.append({"heartbeatTData": int(dut.heartbeatTData.value)}) + if int(dut.eventAck.value) == 1: + event_tags.append(int(dut.eventTag.value)) + + # The current receive-lane RTL recognizes an event once it reaches the Packet + # Tag byte, then returns to IDLE. Keep the rest of this packet spec-shaped so + # payload, CRC, and EOP words are proven not to leak into any other output. + await drive(CXP_SOP, 0xF) + await drive(repeat_byte(CXP_PKT_EVENT), 0x0) + for byte in (0xA0, 0xA1, 0xA2, 0xA3): + await drive(repeat_byte(byte), 0x0) + await drive(repeat_byte(0x6D), 0x0) + await drive(repeat_byte(0x00), 0x0) + await drive(repeat_byte(0x08), 0x0) + await drive(0x11223344, 0x0) + await drive(0x55667788, 0x0) + await drive(0xDEADBEEF, 0x0) + await drive(CXP_EOP, 0xF) + + # A later clean event must still be accepted, proving the ignored payload and + # CRC/trailer words did not leave stale parser state behind. + await drive(CXP_SOP, 0xF) + await drive(repeat_byte(CXP_PKT_EVENT), 0x0) + for byte in (0xB0, 0xB1, 0xB2, 0xB3): + await drive(repeat_byte(byte), 0x0) + await drive(repeat_byte(0x7E), 0x0) + await drive(repeat_byte(0x00), 0x0) + await drive(repeat_byte(0x00), 0x0) + await drive(0xA5A5A5A5, 0x0) + await drive(CXP_EOP, 0xF) + await drive(CXP_IDLE, CXP_IDLE_K) + + assert event_tags == [0x6D, 0x7E] + assert cfg_beats == [] + assert data_beats == [] + assert heartbeat_beats == [] + + @cocotb.test() async def coaxpress_rx_lane_error_recovery_test(dut): start_clock(dut.rxClk) diff --git a/tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py b/tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py index e6d9ec3d43..bdddc6ada7 100644 --- a/tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py +++ b/tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py @@ -83,6 +83,19 @@ async def _pulse_trigger(dut) -> None: dut.txTrig.value = 0 +def _trigger_window(payload: list[tuple[int, int]], *, asserted: bool, inverted: bool) -> bool: + if len(payload) != 6: + return False + link_trigger0 = [(CXP_K28_2, 1), (CXP_K28_4, 1), (CXP_K28_4, 1)] + link_trigger1 = [(CXP_K28_4, 1), (CXP_K28_2, 1), (CXP_K28_2, 1)] + expected_prefix = link_trigger1 if asserted == inverted else link_trigger0 + return ( + payload[:3] == expected_prefix + and payload[3][1] == payload[4][1] == payload[5][1] == 0 + and payload[3][0] == payload[4][0] == payload[5][0] + ) + + @cocotb.test() async def coaxpress_tx_ls_fsm_idle_and_config_cadence_test(dut): # Start from reset with config bytes already queued so the FSM proves it @@ -188,6 +201,60 @@ async def coaxpress_tx_ls_fsm_rate0_inverted_trigger_test(dut): assert any((data, is_k) == IDLE_SEQUENCE[0] for _, data, is_k in strobes[6:]) +@cocotb.test() +async def coaxpress_tx_ls_fsm_pulse_width_update_terminates_active_trigger_test(dut): + # Start with a long trigger pulse, then shorten txPulseWidth after the assert + # message has completed. The RTL should force the active pulse to terminate + # quickly instead of waiting for the original long timeout. + start_clock(dut.txClk) + dut.txRst.setimmediatevalue(1) + dut.cfgTValid.setimmediatevalue(0) + dut.cfgTData.setimmediatevalue(0) + dut.cfgTUser.setimmediatevalue(0) + dut.txTrig.setimmediatevalue(0) + dut.txTrigInv.setimmediatevalue(0) + dut.txPulseWidth.setimmediatevalue(1000) + dut.txRate.setimmediatevalue(1) + await reset_dut(dut, clk_name="txClk", reset_names=("txRst",)) + + await _pulse_trigger(dut) + + strobes: list[tuple[int, int, int]] = [] + pulse_width_update_cycle = None + asserted_start = None + deasserted_start = None + tx_trig_drop_seen = False + + for cycle_index in range(1800): + await RisingEdge(dut.txClk) + await Timer(1, unit="ns") + if int(dut.txTrigDrop.value) == 1: + tx_trig_drop_seen = True + if int(dut.txStrobe.value) == 1: + strobes.append((cycle_index, int(dut.txData.value), int(dut.txDataK.value))) + + for start in range(max(0, len(strobes) - 6), len(strobes) - 5): + payload = [(data, is_k) for _, data, is_k in strobes[start : start + 6]] + if asserted_start is None and _trigger_window(payload, asserted=True, inverted=False): + asserted_start = strobes[start][0] + elif pulse_width_update_cycle is not None and _trigger_window(payload, asserted=False, inverted=False): + deasserted_start = strobes[start][0] + break + + if asserted_start is not None and pulse_width_update_cycle is None and len(strobes) >= 6: + dut.txPulseWidth.value = 20 + pulse_width_update_cycle = cycle_index + + if deasserted_start is not None: + break + + assert asserted_start is not None, strobes + assert pulse_width_update_cycle is not None + assert deasserted_start is not None, strobes + assert deasserted_start - pulse_width_update_cycle < 200 + assert not tx_trig_drop_seen + + def test_CoaXPressTxLsFsm(): run_surf_vhdl_test( test_file=__file__, From dd638576e83a89d46485addc97bb36265c5db5a3 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 27 Apr 2026 10:57:14 -0700 Subject: [PATCH 50/92] Check payload size and crc. --- .../coaxpress/core/rtl/CoaXPressRxLane.vhd | 143 +++++++++++++++++- 1 file changed, 138 insertions(+), 5 deletions(-) diff --git a/protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd b/protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd index 0f246e83ec..3e71fcb11d 100644 --- a/protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd +++ b/protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd @@ -25,6 +25,7 @@ use surf.AxiStreamPkg.all; use surf.SsiPkg.all; use surf.CoaXPressPkg.all; use surf.Code8b10bPkg.all; +use surf.CrcPkg.all; entity CoaXPressRxLane is generic ( @@ -61,6 +62,11 @@ architecture rtl of CoaXPressRxLane is CTRL_ACK_S, HEARTBEAT_S, EVENT_ACK_S, + EVENT_DSIZE_UPPER_S, + EVENT_DSIZE_LOWER_S, + EVENT_PAYLOAD_S, + EVENT_CRC_S, + EVENT_EOP_S, STREAM_ID_S, PACKET_TAG_S, DSIZE_UPPER_S, @@ -80,6 +86,7 @@ architecture rtl of CoaXPressRxLane is dsize : slv(15 downto 0); dcnt : slv(15 downto 0); dbgCnt : slv(31 downto 0); + crc : slv(31 downto 0); -- AXIS Interfaces cfgMaster : AxiStreamMasterType; dataMaster : AxiStreamMasterType; @@ -101,6 +108,7 @@ architecture rtl of CoaXPressRxLane is dsize => (others => '0'), dcnt => (others => '0'), dbgCnt => (others => '0'), + crc => (others => '1'), -- AXIS Interfaces cfgMaster => AXI_STREAM_MASTER_INIT_C, dataMaster => AXI_STREAM_MASTER_INIT_C, @@ -112,6 +120,34 @@ architecture rtl of CoaXPressRxLane is signal r : RegType := REG_INIT_C; signal rin : RegType; + function cxpCrcUpdate ( + crcIn : slv(31 downto 0); + data : slv(31 downto 0)) + return slv is + variable crc : slv(31 downto 0); + variable byteXor : slv(7 downto 0); + begin + crc := crcIn; + byteXor := (others => '0'); + for i in 0 to 3 loop + byteXor := crc(31 downto 24) xor bitReverse(data(8*i+7 downto 8*i)); + crc := (crc(23 downto 0) & x"00") xor crcByteLookup(byteXor, CXP_CRC_POLY_C); + end loop; + return crc; + end function cxpCrcUpdate; + + function cxpCrcFinal ( + crcIn : slv(31 downto 0)) + return slv is + variable retVar : slv(31 downto 0); + begin + retVar := (others => '0'); + for i in 0 to 3 loop + retVar(8*i+7 downto 8*i) := bitReverse(crcIn(8*i+7 downto 8*i)); + end loop; + return endianSwap(retVar); + end function cxpCrcFinal; + -- attribute dont_touch : string; -- attribute dont_touch of r : signal is "TRUE"; @@ -189,6 +225,11 @@ begin -- Check for "control acknowledge with tag" elsif (rxData = x"07_07_07_07") then + -- Reset event parser counters + v.ackCnt := 0; + v.dcnt := (others => '0'); + v.dsize := (others => '0'); + v.crc := x"FFFFFFFF"; -- Next State v.state := EVENT_ACK_S; @@ -265,20 +306,26 @@ begin ---------------------------------------------------------------------- when EVENT_ACK_S => -- Check for non-k word - if (rxDataK = x"0") then + if (rxDataK = x"0") + and ((r.ackCnt < 4) + or ((rxData(7 downto 0) = rxData(15 downto 8)) + and (rxData(7 downto 0) = rxData(23 downto 16)) + and (rxData(7 downto 0) = rxData(31 downto 24)))) then + + -- Include event ID and packet tag words in the CRC. + v.crc := cxpCrcUpdate(r.crc, rxData); -- Increment the counter v.ackCnt := r.ackCnt + 1; - -- "Acknowledgment code" index + -- Packet Tag index if (r.ackCnt = 4) then - -- Generate the ACK message w/ package tag - v.eventAck := '1'; + -- Save the packet tag v.eventTag := rxData(7 downto 0); -- Next State - v.state := IDLE_S; + v.state := EVENT_DSIZE_UPPER_S; end if; @@ -289,6 +336,92 @@ begin v.state := IDLE_S; end if; ---------------------------------------------------------------------- + when EVENT_DSIZE_UPPER_S => + -- Check for repeated-byte size upper word + if (rxDataK = x"0") + and (rxData(7 downto 0) = rxData(15 downto 8)) + and (rxData(7 downto 0) = rxData(23 downto 16)) + and (rxData(7 downto 0) = rxData(31 downto 24)) then + -- Save the upper byte of the event payload word count + v.dsize(15 downto 8) := rxData(7 downto 0); + v.crc := cxpCrcUpdate(r.crc, rxData); + -- Next State + v.state := EVENT_DSIZE_LOWER_S; + else + -- Set the flag + v.errDet := '1'; + -- Next State + v.state := IDLE_S; + end if; + ---------------------------------------------------------------------- + when EVENT_DSIZE_LOWER_S => + -- Check for repeated-byte size lower word + if (rxDataK = x"0") + and (rxData(7 downto 0) = rxData(15 downto 8)) + and (rxData(7 downto 0) = rxData(23 downto 16)) + and (rxData(7 downto 0) = rxData(31 downto 24)) then + -- Save the lower byte of the event payload word count + v.dsize(7 downto 0) := rxData(7 downto 0); + v.dcnt := (others => '0'); + v.crc := cxpCrcUpdate(r.crc, rxData); + -- Next State + if (r.dsize(15 downto 8) = 0) and (rxData(7 downto 0) = 0) then + v.state := EVENT_CRC_S; + else + v.state := EVENT_PAYLOAD_S; + end if; + else + -- Set the flag + v.errDet := '1'; + -- Next State + v.state := IDLE_S; + end if; + ---------------------------------------------------------------------- + when EVENT_PAYLOAD_S => + -- Check for event payload word + if (rxDataK = x"0") then + v.crc := cxpCrcUpdate(r.crc, rxData); + -- Check the counter + if (r.dcnt = (r.dsize-1)) then + -- Next State + v.state := EVENT_CRC_S; + else + -- Increment counter + v.dcnt := r.dcnt + 1; + end if; + else + -- Set the flag + v.errDet := '1'; + -- Next State + v.state := IDLE_S; + end if; + ---------------------------------------------------------------------- + when EVENT_CRC_S => + -- Check for CRC word + if (rxDataK = x"0") and (rxData = cxpCrcFinal(r.crc)) then + -- Next State + v.state := EVENT_EOP_S; + else + -- Set the flag + v.errDet := '1'; + -- Next State + v.state := IDLE_S; + end if; + ---------------------------------------------------------------------- + when EVENT_EOP_S => + -- Check for end of packet indication + if (rxDataK = x"F") and (rxData = CXP_EOP_C) then + -- Generate the ACK message w/ packet tag + v.eventAck := '1'; + -- Next State + v.state := IDLE_S; + else + -- Set the flag + v.errDet := '1'; + -- Next State + v.state := IDLE_S; + end if; + ---------------------------------------------------------------------- when HEARTBEAT_S => -- Check for non-k word if (rxDataK = x"0") then From 0c9ad503398a06c3c3d2426b8e9583c6b2d98eb8 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 27 Apr 2026 10:57:33 -0700 Subject: [PATCH 51/92] More regression testing. --- docs/_meta/rtl_regression_handoff.md | 6 +- docs/_meta/rtl_regression_progress.md | 2 +- tests/protocols/coaxpress/README.md | 25 ++++--- .../coaxpress/coaxpress_test_utils.py | 37 ++++++++++ tests/protocols/coaxpress/test_CoaXPressRx.py | 32 ++++++--- .../coaxpress/test_CoaXPressRxLane.py | 69 +++++++++++-------- 6 files changed, 119 insertions(+), 52 deletions(-) diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index 4bebfc2181..f4f9e83666 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -24,11 +24,11 @@ - Current validated-open issues: - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core` remain untouched in phase 1, while the remaining RoCEv2 gap is the mixed-language bench path for the five RTL entities that instantiate generated submodules: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`. - `EthMacRxImportXlgmii` and `EthMacTxExportXlgmii` are still placeholder no-op RTL; the checked-in tests now lock down that inert contract instead of claiming functional XLGMII support. - - The remaining CoaXPress pure-VHDL gap is now `CoaXPressConfig`. The current CoaXPress receive benches now include a dual-lane `CoaXPressRxHsFsm` step/alignment case and a dual-lane `CoaXPressRx` lane-rotation case, but the receive side is still intentionally mixed-depth: top-level event handling only proves the current packet-prefix contract, and the multi-lane assembly checks still stop short of exhaustive per-lane stress coverage. + - The remaining CoaXPress pure-VHDL gap is now `CoaXPressConfig`. The current CoaXPress receive benches now include a dual-lane `CoaXPressRxHsFsm` step/alignment case, a dual-lane `CoaXPressRx` lane-rotation case, and event packet validation through payload size, payload words, CRC, and `EOP` before `eventAck`. The receive side is still intentionally mixed-depth: event payload is validated for parser/CRC behavior but is not exported through an application-facing payload interface, and the multi-lane assembly checks still stop short of exhaustive per-lane stress coverage. - `tests/protocols/coaxpress/test_CoaXPressConfig.py` is intentionally checked in as a skipped investigation bench. When driven through the real SRP ingress, the current `CoaXPressConfig` / `SrpV3AxiLite` integration does not complete the request path within the bench timeout, so treat that as a likely RTL or integration defect to debug before re-enabling active assertions there. - `tests/protocols/coaxpress/test_CoaXPressCore.py` now also carries an opt-in skipped known-issue bench for RX backpressure vs. FSM-error behavior. Enable it with `RUN_KNOWN_ISSUE_TESTS=1` and optionally shrink the load with `CXP_RX_OVERFLOW_STORM_FRAME_COUNT=`. The current local reproduction under sustained `M_DATA_TREADY=0` and repeated one-line image frames observed `RxFsmErrorCnt=2` while `RxOverflowCnt=0` at `96` frames, and a narrowing sweep showed no repro at `48` frames but a repro by `72` frames with `RxFsmErrorCnt=1` while `RxOverflowCnt=0`. That is closer to the user report than the earlier directed single-error tests and should be treated as a likely RTL defect under investigation. - For future CoaXPress work, treat the named packet classes and control bytes in `tests/protocols/coaxpress/coaxpress_test_utils.py` as shared spec anchors, not as optional local style. Those constants were normalized against the same `CXP-001-2021` / `CXPR-008-2021` references cited in `CoaXPressPkg.vhd`. Keep the packet-layer names aligned to the spec even where current RTL ports still use legacy `eventAck` naming on the receive side: `0x07` is an event packet and `0x08` is an event acknowledgment. - - The current receive benches are intentionally mixed-depth: control-ack traffic is now driven with fuller spec-shaped framing, and `CoaXPressRxLane` now also guards that event payload/CRC/trailer words after the Packet Tag do not leak into unrelated outputs. The checked-in `CoaXPressRxLane` / `CoaXPressRx` event tests still only prove the current RTL contract of consuming the event prefix through the Packet Tag field. Do not describe that as full event-payload coverage until the RTL/parser is expanded and the bench follows it. + - The current receive benches are intentionally mixed-depth: control-ack traffic is now driven with fuller spec-shaped framing, and `CoaXPressRxLane` now validates event payload size, payload words, CRC, and `EOP` before pulsing `eventAck`. Do not describe that as full application-facing event-payload coverage unless a payload output contract is added and covered. - Current planning discipline: - Use manual user-directed area selection as the active source of truth for what to work on next. - Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the actual validated branch frontier. @@ -172,7 +172,7 @@ A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instan ## Immediate Next Task If the user keeps the focus on `protocols/coaxpress`, the next practical step is either: 1. debug and re-enable the skipped `CoaXPressConfig` investigation bench, starting with the SRP-driven request path that currently fails to complete through the real `CoaXPressConfig` / `SrpV3AxiLite` integration, or -2. deepen the remaining spec-level gaps around full receive-side event payload/CRC semantics, normative CXPoF `/Q/` sequence handling, and fuller `/E/` / housekeeping-data interaction semantics. +2. deepen the remaining spec-level gaps around application-facing receive-side event payload delivery, normative CXPoF `/Q/` sequence handling, and fuller `/E/` / housekeeping-data interaction semantics. If the user switches back to `ethernet/RoCEv2`, the next real step is still enabling a mixed-language cocotb path for the five remaining RTL entities listed above. Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the real validated subset, and do not reintroduce local stand-ins for `blue-*`. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 314218271f..0255161490 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -27,7 +27,7 @@ - Blocked bench note: `tests/protocols/coaxpress/test_CoaXPressConfig.py` is checked in as a skipped investigation bench because the real SRP-driven request path does not complete under the current `CoaXPressConfig`/`SrpV3AxiLite` integration. Treat that as a likely RTL or integration defect to debug before re-enabling active assertions on the config return path. - Known-issue bench note: `tests/protocols/coaxpress/test_CoaXPressCore.py` now also carries an opt-in skipped investigation bench for the user-reported RX backpressure path. When enabled with `RUN_KNOWN_ISSUE_TESTS=1`, the bench drives sustained `M_DATA_TREADY=0` pressure with repeated one-line image frames and encodes the expected software-facing behavior that `RxOverflowCnt` should rise before `RxFsmErrorCnt`. The current local reproduction showed `RxFsmErrorCnt=2` while `RxOverflowCnt=0` at `96` frames, and a narrowing sweep showed no repro at `48` frames but a repro by `72` frames (`RxFsmErrorCnt=1`, `RxOverflowCnt=0`), so treat that as a likely RTL defect until narrowed or disproved. - Spec discipline for this family: use the packet/control naming and byte values from `CXP-001-2021` and `CXPR-008-2021` via shared helpers, and keep future top-level/bridge benches explicit about whether they are proving normative spec behavior or only the currently validated RTL subset. At the packet layer, keep the published names even when current RTL signal names drift: `0x07` is an event packet and `0x08` is an event acknowledgment. - - The checked-in RX benches now use more spec-shaped control-ack framing on the wire, include a dual-lane `CoaXPressRxHsFsm` step/alignment case and a dual-lane `CoaXPressRx` lane-rotation case, and guard that receive-lane event payload/CRC/trailer words after the Packet Tag do not leak into unrelated outputs. The current receive-side event path still only observes the event packet prefix through the Packet Tag field before returning to IDLE. Keep that limitation documented rather than implying full event-payload decode coverage. + - The checked-in RX benches now use more spec-shaped control-ack framing on the wire, include a dual-lane `CoaXPressRxHsFsm` step/alignment case and a dual-lane `CoaXPressRx` lane-rotation case, and validate receive-lane event payload size, payload words, CRC, and `EOP` before `eventAck`. Keep the remaining limitation documented: event payload is validated for parser/CRC behavior, but the current RTL still exposes only `eventAck/eventTag` rather than an application-facing payload stream. - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. diff --git a/tests/protocols/coaxpress/README.md b/tests/protocols/coaxpress/README.md index 584d3ce5da..0f660eb562 100644 --- a/tests/protocols/coaxpress/README.md +++ b/tests/protocols/coaxpress/README.md @@ -122,25 +122,29 @@ Important limitation: ### Heartbeat and event traffic -Heartbeat and event handling is only partially covered today: +Heartbeat and event handling is still intentionally narrow, but the receive +event parser now checks complete packet framing before acknowledging: - `test_CoaXPressRxLane.py` - checks the current 12-byte heartbeat payload collector - `test_CoaXPressEventAckMsg.py` - covers event acknowledgment generation on the transmit side - `test_CoaXPressRxLane.py` and `test_CoaXPressRx.py` - - drive a fuller event packet shape, but the current receive RTL only - consumes the event prefix through the `Packet Tag` field before returning to - `IDLE` - - `test_CoaXPressRxLane.py` also keeps payload, CRC, and `EOP` words in the - stimulus after the tag and checks that they do not leak into config, data, - heartbeat, or extra event outputs before a later clean event is accepted + - drive full event packet framing through event ID, Packet Tag, payload size, + payload words, CRC, and `EOP` + - `CoaXPressRxLane` now acknowledges an event only after the CRC and `EOP` + pass, suppresses bad-CRC events, and recovers for a later clean event + - event payload is validated for framing/CRC but is not exported through a + receive-side payload interface -That means these benches do not yet prove full compliance with: +That means these benches now cover the parser/acknowledgment subset of: - section `9.8.1` event ordering rules - section `9.8.2` event payload parsing -- full event-payload CRC/trailer handling +- event-payload CRC/trailer handling + +They still do not prove an application-facing event-payload delivery contract, +because the current RTL exposes only `eventAck` and `eventTag`. ### Stream data and rectangular image traffic @@ -239,7 +243,8 @@ The most important open limits are: - the checked-in known-issue core bench for overflow-vs-FSM-error behavior is skipped by default until the receive-side backpressure interaction is understood and fixed -- receive-side event handling still proves only the current RTL prefix contract +- receive-side event payload is validated for framing/CRC before ACK, but is not + exposed through an application-facing payload interface - trigger coverage still does not include the broader low-speed extra modes or the full high-speed trigger matrix, though the low-speed FSM now covers active-pulse shortening through a runtime `txPulseWidth` update diff --git a/tests/protocols/coaxpress/coaxpress_test_utils.py b/tests/protocols/coaxpress/coaxpress_test_utils.py index 5a5072f2af..94052d82e8 100644 --- a/tests/protocols/coaxpress/coaxpress_test_utils.py +++ b/tests/protocols/coaxpress/coaxpress_test_utils.py @@ -54,6 +54,8 @@ CXPOF_TERM = 0xFD CXPOF_ERROR = 0xFE +CXP_CRC32_POLY = 0x04C11DB7 + @dataclass class AxisBeat: @@ -89,6 +91,41 @@ def endian_swap32(word: int) -> int: return int.from_bytes((word & 0xFFFFFFFF).to_bytes(4, "little"), "big") +def reverse_bits(value: int, width: int) -> int: + result = 0 + for bit in range(width): + if value & (1 << bit): + result |= 1 << (width - 1 - bit) + return result + + +def _crc_byte_lookup(byte_value: int, *, poly: int = CXP_CRC32_POLY) -> int: + crc = (byte_value & 0xFF) << 24 + for _ in range(8): + if crc & 0x80000000: + crc = ((crc << 1) & 0xFFFFFFFF) ^ poly + else: + crc = (crc << 1) & 0xFFFFFFFF + return crc + + +def cxp_crc_word(words: Sequence[int]) -> int: + # Mirrors the CoaXPressConfig/CoaXPressRxLane CRC convention: initialize the + # CRC to all ones, bit-reverse each byte before lookup, bit-reverse each final + # CRC byte, then endian-swap the driven 32-bit word. + crc = 0xFFFFFFFF + for word in words: + for byte_index in range(4): + byte_value = (word >> (8 * byte_index)) & 0xFF + byte_xor = ((crc >> 24) & 0xFF) ^ reverse_bits(byte_value, 8) + crc = ((crc << 8) & 0xFFFFFFFF) ^ _crc_byte_lookup(byte_xor) + + ret = 0 + for byte_index in range(4): + ret |= reverse_bits((crc >> (8 * byte_index)) & 0xFF, 8) << (8 * byte_index) + return endian_swap32(ret) + + def pack_words(words: list[int], *, word_bits: int = 32) -> int: mask = (1 << word_bits) - 1 value = 0 diff --git a/tests/protocols/coaxpress/test_CoaXPressRx.py b/tests/protocols/coaxpress/test_CoaXPressRx.py index 5567e1e5a4..fcef05d0e0 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRx.py +++ b/tests/protocols/coaxpress/test_CoaXPressRx.py @@ -42,6 +42,7 @@ CXP_PKT_IMAGE_LINE, CXP_SOP, append_snapshot_if_valid, + cxp_crc_word, find_subsequence, pack_words, reset_signals, @@ -114,6 +115,20 @@ ] +def _event_crc_words(*, event_bytes: tuple[int, int, int, int], packet_tag: int, payload_words: list[int]) -> list[int]: + crc_inputs = [ + *[repeat_byte(byte) for byte in event_bytes], + repeat_byte(packet_tag), + repeat_byte((len(payload_words) >> 8) & 0xFF), + repeat_byte(len(payload_words) & 0xFF), + *payload_words, + ] + return [ + *crc_inputs, + cxp_crc_word(crc_inputs), + ] + + def _pack_lane_nibbles(values: list[int]) -> int: packed = 0 for index, value in enumerate(values): @@ -464,15 +479,14 @@ async def coaxpress_rx_one_lane_integration_test(dut): (CXP_EOP, 0xF), (CXP_SOP, 0xF), (repeat_byte(CXP_PKT_EVENT), 0x0), - (repeat_byte(0x10), 0x0), - (repeat_byte(0x11), 0x0), - (repeat_byte(0x12), 0x0), - (repeat_byte(0x13), 0x0), - (repeat_byte(0x5A), 0x0), - (0x00010000, 0x0), - (repeat_byte(0x00), 0x0), - (0x11223344, 0x0), - (0xA5A5A5A5, 0x0), + *[ + (word, 0x0) + for word in _event_crc_words( + event_bytes=(0x10, 0x11, 0x12, 0x13), + packet_tag=0x5A, + payload_words=[0x11223344], + ) + ], (CXP_EOP, 0xF), (CXP_IO_ACK, 0xF), (repeat_byte(0x01), 0x0), diff --git a/tests/protocols/coaxpress/test_CoaXPressRxLane.py b/tests/protocols/coaxpress/test_CoaXPressRxLane.py index 5fd433010b..44bcf16e3d 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRxLane.py +++ b/tests/protocols/coaxpress/test_CoaXPressRxLane.py @@ -37,6 +37,7 @@ CXP_PKT_STREAM_DATA, CXP_SOP, cycle, + cxp_crc_word, repeat_byte, reset_dut, send_rx_word, @@ -44,6 +45,20 @@ ) +def _event_crc_words(*, event_bytes: tuple[int, int, int, int], packet_tag: int, payload_words: list[int]) -> list[int]: + crc_inputs = [ + *[repeat_byte(byte) for byte in event_bytes], + repeat_byte(packet_tag), + repeat_byte((len(payload_words) >> 8) & 0xFF), + repeat_byte(len(payload_words) & 0xFF), + *payload_words, + ] + return [ + *crc_inputs, + cxp_crc_word(crc_inputs), + ] + + @cocotb.test() async def coaxpress_rx_lane_stream_and_io_ack_test(dut): start_clock(dut.rxClk) @@ -169,18 +184,12 @@ async def drive(data: int, data_k: int, *, link_up: int = 1) -> None: await drive(CXP_EOP, 0xF) # Drive a fuller event packet shape. The current RTL only consumes the - # prefix through the Packet Tag field, where it exports the tag and returns - # to IDLE; later size/data/trailer words are present to keep the on-wire - # stimulus aligned to the spec framing. + # prefix and payload internally, then exports the tag only after the CRC and + # EOP trailer have been validated. await drive(CXP_SOP, 0xF) await drive(repeat_byte(CXP_PKT_EVENT), 0x0) - for word in (0x10, 0x11, 0x12, 0x13): - await drive(repeat_byte(word), 0x0) - await drive(repeat_byte(0x5A), 0x0) - await drive(0x00010000, 0x0) - await drive(repeat_byte(0x00), 0x0) - await drive(0x11223344, 0x0) - await drive(0xA5A5A5A5, 0x0) + for word in _event_crc_words(event_bytes=(0x10, 0x11, 0x12, 0x13), packet_tag=0x5A, payload_words=[0x11223344]): + await drive(word, 0x0) await drive(CXP_EOP, 0xF) # A truncated event prefix must not raise a second event pulse. @@ -236,31 +245,33 @@ async def drive(data: int, data_k: int) -> None: if int(dut.eventAck.value) == 1: event_tags.append(int(dut.eventTag.value)) - # The current receive-lane RTL recognizes an event once it reaches the Packet - # Tag byte, then returns to IDLE. Keep the rest of this packet spec-shaped so - # payload, CRC, and EOP words are proven not to leak into any other output. + # The receive-lane RTL validates the event payload count, CRC, and EOP before + # acknowledging the tag. The payload is intentionally not forwarded anywhere. await drive(CXP_SOP, 0xF) await drive(repeat_byte(CXP_PKT_EVENT), 0x0) - for byte in (0xA0, 0xA1, 0xA2, 0xA3): - await drive(repeat_byte(byte), 0x0) - await drive(repeat_byte(0x6D), 0x0) - await drive(repeat_byte(0x00), 0x0) - await drive(repeat_byte(0x08), 0x0) - await drive(0x11223344, 0x0) - await drive(0x55667788, 0x0) - await drive(0xDEADBEEF, 0x0) + for word in _event_crc_words( + event_bytes=(0xA0, 0xA1, 0xA2, 0xA3), + packet_tag=0x6D, + payload_words=[0x11223344, 0x55667788], + ): + await drive(word, 0x0) await drive(CXP_EOP, 0xF) - # A later clean event must still be accepted, proving the ignored payload and - # CRC/trailer words did not leave stale parser state behind. + # A bad CRC must suppress the acknowledgment and still leave the parser ready + # for a later clean event. await drive(CXP_SOP, 0xF) await drive(repeat_byte(CXP_PKT_EVENT), 0x0) - for byte in (0xB0, 0xB1, 0xB2, 0xB3): - await drive(repeat_byte(byte), 0x0) - await drive(repeat_byte(0x7E), 0x0) - await drive(repeat_byte(0x00), 0x0) - await drive(repeat_byte(0x00), 0x0) - await drive(0xA5A5A5A5, 0x0) + bad_crc_words = _event_crc_words(event_bytes=(0x90, 0x91, 0x92, 0x93), packet_tag=0x55, payload_words=[0x0BADCAFE]) + for word in [*bad_crc_words[:-1], bad_crc_words[-1] ^ 0x00000001]: + await drive(word, 0x0) + await drive(CXP_EOP, 0xF) + + # A later zero-payload event must still be accepted, proving the ignored + # bad-CRC packet did not leave stale parser state behind. + await drive(CXP_SOP, 0xF) + await drive(repeat_byte(CXP_PKT_EVENT), 0x0) + for word in _event_crc_words(event_bytes=(0xB0, 0xB1, 0xB2, 0xB3), packet_tag=0x7E, payload_words=[]): + await drive(word, 0x0) await drive(CXP_EOP, 0xF) await drive(CXP_IDLE, CXP_IDLE_K) From 91c78972a9a04cd717b0b28d7505fe57b692f0e4 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 27 Apr 2026 11:11:11 -0700 Subject: [PATCH 52/92] Expand SrpV3Axi tests. --- docs/_meta/rtl_regression_handoff.md | 3 +- docs/_meta/rtl_regression_progress.md | 8 +- tests/protocols/srp/test_SrpV3Axi.py | 301 ++++++++++++++++++++++---- 3 files changed, 272 insertions(+), 40 deletions(-) diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index f4f9e83666..48eb2cf1d8 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -19,13 +19,14 @@ - Treat stale simulator cleanup as part of task completion: after any `pytest`, cocotb, GHDL, or similar launched verification step, sweep for leftover child processes and kill them before moving on ## Quick Resume Snapshot -- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, the current Ethernet coverage spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the pure-VHDL RoCEv2 quartet (`EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator`), and a broader user-directed CoaXPress pure-VHDL wave is now checked in under `tests/protocols/coaxpress/`. The validated CoaXPress subset now includes the receive quartet `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, and `CoaXPressRxHsFsm`, the receive assembly `CoaXPressRx`, the transmit/bridge helpers `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressOverFiberBridgeRx`, and `CoaXPressOverFiberBridgeTx`, and the higher-level assemblies `CoaXPressTx`, `CoaXPressCore`, and `CoaXPressOverFiberBridge`. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. +- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, the current Ethernet coverage spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the pure-VHDL RoCEv2 quartet (`EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator`), and a broader user-directed CoaXPress pure-VHDL wave is now checked in under `tests/protocols/coaxpress/`. The validated CoaXPress subset now includes the receive quartet `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, and `CoaXPressRxHsFsm`, the receive assembly `CoaXPressRx`, the transmit/bridge helpers `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressOverFiberBridgeRx`, and `CoaXPressOverFiberBridgeTx`, and the higher-level assemblies `CoaXPressTx`, `CoaXPressCore`, and `CoaXPressOverFiberBridge`. `protocols/srp` now has a widened SRPv3 AXI protocol matrix in `tests/protocols/srp/test_SrpV3Axi.py` covering read/write/post/null flows, response backpressure, TDEST propagation, and representative protocol-error footers through the checked-in `SrpV3AxiWrapper`. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. - Current axi frontier: complete for the intended simulator-friendly pass in this branch snapshot; do not resume from the older stale `AxiResize` note. - Current validated-open issues: - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core` remain untouched in phase 1, while the remaining RoCEv2 gap is the mixed-language bench path for the five RTL entities that instantiate generated submodules: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`. - `EthMacRxImportXlgmii` and `EthMacTxExportXlgmii` are still placeholder no-op RTL; the checked-in tests now lock down that inert contract instead of claiming functional XLGMII support. - The remaining CoaXPress pure-VHDL gap is now `CoaXPressConfig`. The current CoaXPress receive benches now include a dual-lane `CoaXPressRxHsFsm` step/alignment case, a dual-lane `CoaXPressRx` lane-rotation case, and event packet validation through payload size, payload words, CRC, and `EOP` before `eventAck`. The receive side is still intentionally mixed-depth: event payload is validated for parser/CRC behavior but is not exported through an application-facing payload interface, and the multi-lane assembly checks still stop short of exhaustive per-lane stress coverage. - `tests/protocols/coaxpress/test_CoaXPressConfig.py` is intentionally checked in as a skipped investigation bench. When driven through the real SRP ingress, the current `CoaXPressConfig` / `SrpV3AxiLite` integration does not complete the request path within the bench timeout, so treat that as a likely RTL or integration defect to debug before re-enabling active assertions there. + - `tests/protocols/srp/test_SrpV3Axi.py` is now the active SRPv3 AXI regression, not just the old legacy-style posted-write/readback smoke. It validates non-posted write echo/readback, posted-write no-response behavior, NULL responses, response backpressure, TDEST propagation, full-word `TKEEP`, and footer bits for version mismatch, malformed write framing, invalid alignment, invalid request size, and downstream address error. Remaining SRP work should move next to `SrpV3AxiLite` / `SrpV3AxiLiteFull` or to a direct `SrpV3Core` fault-injection wrapper if ack/read-data timing needs more control. - `tests/protocols/coaxpress/test_CoaXPressCore.py` now also carries an opt-in skipped known-issue bench for RX backpressure vs. FSM-error behavior. Enable it with `RUN_KNOWN_ISSUE_TESTS=1` and optionally shrink the load with `CXP_RX_OVERFLOW_STORM_FRAME_COUNT=`. The current local reproduction under sustained `M_DATA_TREADY=0` and repeated one-line image frames observed `RxFsmErrorCnt=2` while `RxOverflowCnt=0` at `96` frames, and a narrowing sweep showed no repro at `48` frames but a repro by `72` frames with `RxFsmErrorCnt=1` while `RxOverflowCnt=0`. That is closer to the user report than the earlier directed single-error tests and should be treated as a likely RTL defect under investigation. - For future CoaXPress work, treat the named packet classes and control bytes in `tests/protocols/coaxpress/coaxpress_test_utils.py` as shared spec anchors, not as optional local style. Those constants were normalized against the same `CXP-001-2021` / `CXPR-008-2021` references cited in `CoaXPressPkg.vhd`. Keep the packet-layer names aligned to the spec even where current RTL ports still use legacy `eventAck` naming on the receive side: `0x07` is an event packet and `0x08` is an event acknowledgment. - The current receive benches are intentionally mixed-depth: control-ack traffic is now driven with fuller spec-shaped framing, and `CoaXPressRxLane` now validates event payload size, payload words, CRC, and `EOP` before pulsing `eventAck`. Do not describe that as full application-facing event-payload coverage unless a payload output contract is added and covered. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 0255161490..420992bf60 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -3,8 +3,8 @@ ## Summary - Current phase: Phase-1 implementation active - Current subsystem: manual user-directed rollout tracking -- Current focus module: user-directed CoaXPress pure-VHDL rollout under `protocols/coaxpress/core/rtl`, with validated cocotb coverage now checked in for `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, `CoaXPressRxHsFsm`, `CoaXPressRx`, `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressTx`, `CoaXPressCore`, `CoaXPressOverFiberBridgeRx`, `CoaXPressOverFiberBridgeTx`, and `CoaXPressOverFiberBridge`. -- Last updated: 2026-04-20 +- Current focus module: user-directed SRP regression work under `protocols/srp`, with the existing `SrpV3AxiWrapper` cocotb bench widened into a directed SRPv3 protocol matrix covering reads, non-posted writes, posted writes, null requests, response backpressure, TDEST propagation, and representative error footers. +- Last updated: 2026-04-27 ## Current Frontier Snapshot - Active planning rule: take the next work item from the user's manual direction, not from `docs/_meta/rtl_phase1_queue.{md,json}`. @@ -28,6 +28,10 @@ - Known-issue bench note: `tests/protocols/coaxpress/test_CoaXPressCore.py` now also carries an opt-in skipped investigation bench for the user-reported RX backpressure path. When enabled with `RUN_KNOWN_ISSUE_TESTS=1`, the bench drives sustained `M_DATA_TREADY=0` pressure with repeated one-line image frames and encodes the expected software-facing behavior that `RxOverflowCnt` should rise before `RxFsmErrorCnt`. The current local reproduction showed `RxFsmErrorCnt=2` while `RxOverflowCnt=0` at `96` frames, and a narrowing sweep showed no repro at `48` frames but a repro by `72` frames (`RxFsmErrorCnt=1`, `RxOverflowCnt=0`), so treat that as a likely RTL defect until narrowed or disproved. - Spec discipline for this family: use the packet/control naming and byte values from `CXP-001-2021` and `CXPR-008-2021` via shared helpers, and keep future top-level/bridge benches explicit about whether they are proving normative spec behavior or only the currently validated RTL subset. At the packet layer, keep the published names even when current RTL signal names drift: `0x07` is an event packet and `0x08` is an event acknowledgment. - The checked-in RX benches now use more spec-shaped control-ack framing on the wire, include a dual-lane `CoaXPressRxHsFsm` step/alignment case and a dual-lane `CoaXPressRx` lane-rotation case, and validate receive-lane event payload size, payload words, CRC, and `EOP` before `eventAck`. Keep the remaining limitation documented: event payload is validated for parser/CRC behavior, but the current RTL still exposes only `eventAck/eventTag` rather than an application-facing payload stream. +- SRP RTL target matrix: + - Covered now under the current GHDL-only flow: `SrpV3Axi` through the checked-in `protocols/srp/wrappers/SrpV3AxiWrapper.vhd` wrapper and `tests/protocols/srp/test_SrpV3Axi.py`. + - The current SRPv3 AXI bench now validates non-posted write echo/readback, posted-write no-response behavior followed by readback, NULL header/footer behavior, response backpressure hold, TDEST propagation, full-word `TKEEP`, and footer bits for version mismatch, malformed write framing, invalid alignment, invalid request size, and downstream address error. + - Still open in `protocols/srp`: dedicated cocotb coverage for `SrpV3AxiLite`, `SrpV3AxiLiteFull`, and the older SRPv0 bridges. `SrpV3Core` is covered transitively through `SrpV3Axi`, but a direct core wrapper could still be useful later for ack/read-data timing fault injection that is hard to force through the AXI DMA wrapper. - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. diff --git a/tests/protocols/srp/test_SrpV3Axi.py b/tests/protocols/srp/test_SrpV3Axi.py index 71013b61cf..573bc43c15 100644 --- a/tests/protocols/srp/test_SrpV3Axi.py +++ b/tests/protocols/srp/test_SrpV3Axi.py @@ -9,12 +9,20 @@ ############################################################################## # Test methodology: -# - Sweep: Exercise the default SRPv3 AXI bridge with the same posted-write -# then non-posted-read flow as the legacy bench. -# - Stimulus: Drive SRPv3 request frames on the 32-bit SSI-side stream. -# - Checks: The read response header and payload must match the written RAM -# contents and request metadata. -# - Timing: Transfer is handshake-driven with a bounded receive timeout. +# - Sweep: Exercise one checked-in SRPv3 AXI bridge wrapper in a directed +# matrix covering reads, non-posted writes, posted writes, null requests, and +# representative protocol-error footers. +# - Stimulus: Drive 32-bit SRPv3 request frames into the SSI-side stream with +# varied transaction IDs, TDEST values, addresses, payload lengths, and +# malformed header fields. +# - Checks: Scoreboard echoed headers, write echoes, read payloads from the +# attached AXI RAM, posted-write silence, TDEST propagation, and footer bits +# for version, framing, request-size/alignment, and downstream address errors. +# - Timing: All transfers are ready/valid driven, one read response is held +# under output backpressure before release, and every expected or forbidden +# response is bounded by an explicit timeout. + +from dataclasses import dataclass import cocotb import pytest @@ -24,8 +32,59 @@ from tests.common.regression_utils import run_surf_vhdl_test -REQ_BYTE_SIZE = 2**12 -REQ_WORD_SIZE = REQ_BYTE_SIZE // 4 +SRP_VERSION = 0x03 +SRP_READ = 0x0 +SRP_WRITE = 0x1 +SRP_POSTED_WRITE = 0x2 +SRP_NULL = 0x3 + +FOOTER_FRAME_ERROR = 1 << 10 +FOOTER_VERSION_MISMATCH = 1 << 11 +FOOTER_REQUEST_ERROR = 1 << 12 +FOOTER_ADDRESS_ERROR = 1 << 7 + + +@dataclass(frozen=True) +class SrpRequest: + opcode: int + tid: int + address: int + byte_count: int + version: int = SRP_VERSION + timeout: int = 0 + prot: int = 0 + spare: int = 0 + + @property + def req_size(self) -> int: + return self.byte_count - 1 + + @property + def response_header(self) -> list[int]: + # The response reports the local SRPv3 version while echoing the rest + # of the request metadata that software uses to match transactions. + return request_header( + opcode=self.opcode, + tid=self.tid, + address=self.address, + req_size=self.req_size, + version=SRP_VERSION, + timeout=self.timeout, + prot=self.prot, + spare=self.spare, + ) + + +@dataclass(frozen=True) +class SrpResponse: + words: list[int] + tdest: list[int] + tuser: list[int] + tkeep: list[int] + + @property + def footer(self) -> int: + return self.words[-1] class TB: @@ -34,6 +93,8 @@ def __init__(self, dut): cocotb.start_soon(Clock(dut.AXIS_ACLK, 10.0, unit="ns").start()) async def reset(self): + # Initialize every driven bus field before the first clock edge so the + # DUT never sees unknown stimulus during reset release. self.dut.AXIS_ARESETN.setimmediatevalue(0) self.dut.S_AXIS_TVALID.setimmediatevalue(0) self.dut.S_AXIS_TDATA.setimmediatevalue(0) @@ -43,73 +104,239 @@ async def reset(self): self.dut.S_AXIS_TID.setimmediatevalue(0) self.dut.S_AXIS_TUSER.setimmediatevalue(0) self.dut.M_AXIS_TREADY.setimmediatevalue(1) + + # Match the legacy benches by holding reset long enough for the SRP + # FIFOs and attached RAM model to settle before the first frame. for _ in range(110): await RisingEdge(self.dut.AXIS_ACLK) self.dut.AXIS_ARESETN.value = 1 - for _ in range(4): + for _ in range(8): await RisingEdge(self.dut.AXIS_ACLK) - async def send_words(self, words): + async def send_words(self, words: list[int], *, tdest: int = 0): + # Present one 32-bit SSI beat at a time and only advance after the DUT + # accepts it. The first beat carries SOF in the flattened SSI TUSER bit. for index, word in enumerate(words): self.dut.S_AXIS_TVALID.value = 1 - self.dut.S_AXIS_TDATA.value = word + self.dut.S_AXIS_TDATA.value = word & 0xFFFF_FFFF self.dut.S_AXIS_TKEEP.value = 0xF - self.dut.S_AXIS_TLAST.value = 1 if index == len(words) - 1 else 0 - self.dut.S_AXIS_TUSER.value = 0x2 if index == 0 else 0x0 + self.dut.S_AXIS_TLAST.value = int(index == len(words) - 1) + self.dut.S_AXIS_TDEST.value = tdest self.dut.S_AXIS_TID.value = 0 + self.dut.S_AXIS_TUSER.value = 0x2 if index == 0 else 0x0 + while int(self.dut.S_AXIS_TREADY.value) != 1: await RisingEdge(self.dut.AXIS_ACLK) await RisingEdge(self.dut.AXIS_ACLK) + self.dut.S_AXIS_TVALID.value = 0 self.dut.S_AXIS_TLAST.value = 0 self.dut.S_AXIS_TUSER.value = 0 - async def recv_words(self): + async def wait_for_output_valid(self): + # Used by the backpressure check: wait until the DUT has a response + # pending while the sink is deliberately not ready. + while int(self.dut.M_AXIS_TVALID.value) != 1: + await with_timeout(RisingEdge(self.dut.AXIS_ACLK), 2, "ms") + + async def recv_response(self) -> SrpResponse: words = [] + tdest = [] + tuser = [] + tkeep = [] + self.dut.M_AXIS_TREADY.value = 1 + + # Capture exactly the beats that complete a ready/valid handshake. while True: await with_timeout(RisingEdge(self.dut.AXIS_ACLK), 2, "ms") if int(self.dut.M_AXIS_TVALID.value) != 1: continue + words.append(int(self.dut.M_AXIS_TDATA.value)) + tdest.append(int(self.dut.M_AXIS_TDEST.value)) + tuser.append(int(self.dut.M_AXIS_TUSER.value)) + tkeep.append(int(self.dut.M_AXIS_TKEEP.value)) if int(self.dut.M_AXIS_TLAST.value) == 1: - return words + return SrpResponse(words=words, tdest=tdest, tuser=tuser, tkeep=tkeep) + async def expect_no_response(self, *, cycles: int = 80): + # Posted writes are expected to update memory without producing any + # outbound SRP frame. Keep the sink ready so a surprise response cannot + # hide behind backpressure. + self.dut.M_AXIS_TREADY.value = 1 + for _ in range(cycles): + await RisingEdge(self.dut.AXIS_ACLK) + assert int(self.dut.M_AXIS_TVALID.value) == 0 -def request_header(opcode, tid, address): + +def request_header( + *, + opcode: int, + tid: int, + address: int, + req_size: int, + version: int = SRP_VERSION, + timeout: int = 0, + prot: int = 0, + spare: int = 0, +) -> list[int]: + word0 = ( + (version & 0xFF) + | ((opcode & 0x3) << 8) + | ((spare & 0x7FF) << 10) + | ((prot & 0x7) << 21) + | ((timeout & 0xFF) << 24) + ) return [ - ((opcode & 0xFF) << 8) | 0x03, - tid, + word0, + tid & 0xFFFF_FFFF, address & 0xFFFF_FFFF, - 0, - REQ_BYTE_SIZE - 1, + (address >> 32) & 0xFFFF_FFFF, + req_size & 0xFFFF_FFFF, ] +def request_frame(request: SrpRequest, payload: list[int] | None = None) -> list[int]: + payload = [] if payload is None else payload + return request_header( + opcode=request.opcode, + tid=request.tid, + address=request.address, + req_size=request.req_size, + version=request.version, + timeout=request.timeout, + prot=request.prot, + spare=request.spare, + ) + payload + + +def assert_response( + response: SrpResponse, + request: SrpRequest, + payload: list[int], + *, + footer_mask: int = 0, + footer_value: int = 0, + expected_tdest: int | None = None, +): + assert response.words[:5] == request.response_header + assert response.words[5:-1] == [word & 0xFFFF_FFFF for word in payload] + assert response.footer & footer_mask == footer_value + + if expected_tdest is not None: + assert response.tdest == [expected_tdest] * len(response.words) + + # All curated responses are full 32-bit words, including the footer. + assert response.tkeep == [0xF] * len(response.words) + assert response.tuser[0] & 0x2 == 0x2 + + +async def issue_and_check_error( + tb: TB, + request: SrpRequest, + payload: list[int], + *, + expected_footer_bits: int, +): + await tb.send_words(request_frame(request, payload)) + response = await tb.recv_response() + assert_response( + response, + request, + payload=payload, + footer_mask=expected_footer_bits, + footer_value=expected_footer_bits, + ) + + @cocotb.test() -async def srpv3_axi_round_trip_test(dut): +async def srpv3_axi_directed_protocol_matrix_test(dut): tb = TB(dut) await tb.reset() - write_tid = 0x1234_0000 - address = 0 - write_words = request_header(0x02, write_tid, address) + list(range(REQ_WORD_SIZE)) - await tb.send_words(write_words) + # A non-posted write must echo the accepted data, complete with a clean + # footer, and the same bytes must be readable from the attached AXI RAM. + write_payload = [0x11223344, 0x55667788, 0xA5A55A5A] + write_req = SrpRequest(SRP_WRITE, 0x1000_0001, 0x40, 4 * len(write_payload)) + await tb.send_words(request_frame(write_req, write_payload), tdest=0x3) + assert_response(await tb.recv_response(), write_req, write_payload, expected_tdest=0x3) + + # Hold the response sink not-ready until the first read beat is pending. + # The first header beat must remain stable until the sink accepts it. + read_req = SrpRequest(SRP_READ, 0x1000_0002, 0x40, 4 * len(write_payload), prot=0x5) + tb.dut.M_AXIS_TREADY.value = 0 + await tb.send_words(request_frame(read_req), tdest=0x5) + await tb.wait_for_output_valid() + held_word = int(tb.dut.M_AXIS_TDATA.value) + for _ in range(5): + await RisingEdge(tb.dut.AXIS_ACLK) + assert int(tb.dut.M_AXIS_TVALID.value) == 1 + assert int(tb.dut.M_AXIS_TDATA.value) == held_word + tb.dut.M_AXIS_TREADY.value = 1 + assert_response(await tb.recv_response(), read_req, write_payload, expected_tdest=0x5) + + # Posted writes are common in applications: they must not return a frame, + # but a later read still has to observe the memory update. + posted_payload = [0x01020304, 0xAABBCCDD, 0x0BADF00D, 0xCAFEBABE] + posted_req = SrpRequest(SRP_POSTED_WRITE, 0x2000_0001, 0x80, 4 * len(posted_payload)) + await tb.send_words(request_frame(posted_req, posted_payload), tdest=0x7) + await tb.expect_no_response() - read_tid = write_tid + 1 - read_words = request_header(0x00, read_tid, address) - await tb.send_words(read_words) + posted_read_req = SrpRequest(SRP_READ, 0x2000_0002, 0x80, 4 * len(posted_payload)) + await tb.send_words(request_frame(posted_read_req), tdest=0x7) + assert_response(await tb.recv_response(), posted_read_req, posted_payload, expected_tdest=0x7) - response = await tb.recv_words() - assert response[0] == ((0x00 << 8) | 0x03) - assert response[1] == read_tid - assert response[2] == address - assert response[4] == REQ_BYTE_SIZE - 1 - payload = response[5:] - assert payload[:-1] == list(range(REQ_WORD_SIZE)) - assert payload[-1] == 0 + # NULL requests exercise the header/footer-only path without touching the + # AXI RAM. The request size is still echoed so software can correlate it. + null_req = SrpRequest(SRP_NULL, 0x3000_0001, 0x0000, 1) + await tb.send_words(request_frame(null_req), tdest=0x1) + assert_response(await tb.recv_response(), null_req, [], expected_tdest=0x1) + + # The footer matrix locks down common software-visible failure reporting: + # bad version, malformed write framing, invalid alignment/size, and an AXI + # address-range error returned from the bridge layer. + bad_version_req = SrpRequest(SRP_READ, 0x4000_0001, 0x40, 4, version=0x02) + await issue_and_check_error( + tb, + bad_version_req, + [], + expected_footer_bits=FOOTER_VERSION_MISMATCH, + ) + + truncated_write_req = SrpRequest(SRP_WRITE, 0x4000_0002, 0x40, 4) + await issue_and_check_error( + tb, + truncated_write_req, + [], + expected_footer_bits=FOOTER_FRAME_ERROR, + ) + + unaligned_read_req = SrpRequest(SRP_READ, 0x4000_0003, 0x42, 4) + await issue_and_check_error( + tb, + unaligned_read_req, + [], + expected_footer_bits=FOOTER_REQUEST_ERROR, + ) + + short_read_req = SrpRequest(SRP_READ, 0x4000_0004, 0x40, 2) + await issue_and_check_error( + tb, + short_read_req, + [], + expected_footer_bits=FOOTER_REQUEST_ERROR, + ) + + out_of_range_write_req = SrpRequest(SRP_WRITE, 0x4000_0005, 0x1000, 4) + await issue_and_check_error( + tb, + out_of_range_write_req, + [0xDEADBEEF], + expected_footer_bits=FOOTER_ADDRESS_ERROR, + ) -PARAMETER_SWEEP = [pytest.param({}, id="default_request_window")] +PARAMETER_SWEEP = [pytest.param({}, id="default_protocol_matrix")] @pytest.mark.parametrize("parameters", PARAMETER_SWEEP) From 2402ebcc1a145ef6cc333bc6c0352eb3a9b11a40 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 27 Apr 2026 13:20:06 -0700 Subject: [PATCH 53/92] First SRP tests. --- docs/_meta/rtl_regression_handoff.md | 6 +- docs/_meta/rtl_regression_progress.md | 17 +- .../srp/wrappers/SrpV0LoopbackWrapper.vhd | 178 ++++++++++ .../srp/wrappers/SrpV3AxiLiteFullWrapper.vhd | 172 ++++++++++ .../srp/wrappers/SrpV3AxiLiteWideWrapper.vhd | 173 ++++++++++ .../srp/wrappers/SrpV3AxiLiteWrapper.vhd | 174 ++++++++++ protocols/srp/wrappers/SrpV3CoreWrapper.vhd | 298 +++++++++++++++++ tests/protocols/srp/srp_test_utils.py | 258 +++++++++++++++ tests/protocols/srp/test_SrpV0Loopback.py | 83 +++++ tests/protocols/srp/test_SrpV3AxiLite.py | 309 ++++++++++++++++++ tests/protocols/srp/test_SrpV3Core.py | 72 ++++ 11 files changed, 1730 insertions(+), 10 deletions(-) create mode 100644 protocols/srp/wrappers/SrpV0LoopbackWrapper.vhd create mode 100644 protocols/srp/wrappers/SrpV3AxiLiteFullWrapper.vhd create mode 100644 protocols/srp/wrappers/SrpV3AxiLiteWideWrapper.vhd create mode 100644 protocols/srp/wrappers/SrpV3AxiLiteWrapper.vhd create mode 100644 protocols/srp/wrappers/SrpV3CoreWrapper.vhd create mode 100644 tests/protocols/srp/srp_test_utils.py create mode 100644 tests/protocols/srp/test_SrpV0Loopback.py create mode 100644 tests/protocols/srp/test_SrpV3AxiLite.py create mode 100644 tests/protocols/srp/test_SrpV3Core.py diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index 48eb2cf1d8..62578a8422 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -26,7 +26,7 @@ - `EthMacRxImportXlgmii` and `EthMacTxExportXlgmii` are still placeholder no-op RTL; the checked-in tests now lock down that inert contract instead of claiming functional XLGMII support. - The remaining CoaXPress pure-VHDL gap is now `CoaXPressConfig`. The current CoaXPress receive benches now include a dual-lane `CoaXPressRxHsFsm` step/alignment case, a dual-lane `CoaXPressRx` lane-rotation case, and event packet validation through payload size, payload words, CRC, and `EOP` before `eventAck`. The receive side is still intentionally mixed-depth: event payload is validated for parser/CRC behavior but is not exported through an application-facing payload interface, and the multi-lane assembly checks still stop short of exhaustive per-lane stress coverage. - `tests/protocols/coaxpress/test_CoaXPressConfig.py` is intentionally checked in as a skipped investigation bench. When driven through the real SRP ingress, the current `CoaXPressConfig` / `SrpV3AxiLite` integration does not complete the request path within the bench timeout, so treat that as a likely RTL or integration defect to debug before re-enabling active assertions there. - - `tests/protocols/srp/test_SrpV3Axi.py` is now the active SRPv3 AXI regression, not just the old legacy-style posted-write/readback smoke. It validates non-posted write echo/readback, posted-write no-response behavior, NULL responses, response backpressure, TDEST propagation, full-word `TKEEP`, and footer bits for version mismatch, malformed write framing, invalid alignment, invalid request size, and downstream address error. Remaining SRP work should move next to `SrpV3AxiLite` / `SrpV3AxiLiteFull` or to a direct `SrpV3Core` fault-injection wrapper if ack/read-data timing needs more control. + - `tests/protocols/srp/test_SrpV3Axi.py` is now the active SRPv3 AXI regression, not just the old legacy-style posted-write/readback smoke. It validates non-posted write echo/readback, posted-write no-response behavior, NULL responses, response backpressure, TDEST propagation, full-word `TKEEP`, and footer bits for version mismatch, malformed write framing, invalid alignment, invalid request size, and downstream address error. `tests/protocols/srp/test_SrpV3Core.py` adds direct reset/idle smoke for `SrpV3Core`, while functional core behavior remains covered transitively through `SrpV3Axi`. `tests/protocols/srp/test_SrpV0Loopback.py` covers `AxiLiteSrpV0` and `SrpV0AxiLite` together through the checked-in SRPv0 stream loopback wrapper. `tests/protocols/srp/test_SrpV3AxiLite.py` carries active reset/idle smoke for direct, full, and legacy-wide wrappers, plus an active directed `SrpV3AxiLite` regression using the legacy 256-bit single-beat SRP framing. The remaining expected-open path is narrower: 32-bit multi-beat direct read frames are accepted and simulation time advances to the bench timeout, but no AXI-Lite AR or response frame appears; `SrpV3AxiLiteFull` also remains under investigation for the current narrow probes. Enable the skipped probes with `RUN_KNOWN_ISSUE_TESTS=1` only while debugging. - `tests/protocols/coaxpress/test_CoaXPressCore.py` now also carries an opt-in skipped known-issue bench for RX backpressure vs. FSM-error behavior. Enable it with `RUN_KNOWN_ISSUE_TESTS=1` and optionally shrink the load with `CXP_RX_OVERFLOW_STORM_FRAME_COUNT=`. The current local reproduction under sustained `M_DATA_TREADY=0` and repeated one-line image frames observed `RxFsmErrorCnt=2` while `RxOverflowCnt=0` at `96` frames, and a narrowing sweep showed no repro at `48` frames but a repro by `72` frames with `RxFsmErrorCnt=1` while `RxOverflowCnt=0`. That is closer to the user report than the earlier directed single-error tests and should be treated as a likely RTL defect under investigation. - For future CoaXPress work, treat the named packet classes and control bytes in `tests/protocols/coaxpress/coaxpress_test_utils.py` as shared spec anchors, not as optional local style. Those constants were normalized against the same `CXP-001-2021` / `CXPR-008-2021` references cited in `CoaXPressPkg.vhd`. Keep the packet-layer names aligned to the spec even where current RTL ports still use legacy `eventAck` naming on the receive side: `0x07` is an event packet and `0x08` is an event acknowledgment. - The current receive benches are intentionally mixed-depth: control-ack traffic is now driven with fuller spec-shaped framing, and `CoaXPressRxLane` now validates event payload size, payload words, CRC, and `EOP` before pulsing `eventAck`. Do not describe that as full application-facing event-payload coverage unless a payload output contract is added and covered. @@ -171,7 +171,9 @@ One small RTL fix landed during that validation pass because the new `AxiStreamD A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instantiation_graph.md` and `docs/_meta/rtl_instantiation_graph.json`, and the same generator now also emits a path-qualified bottom-up phase-1 queue at `docs/_meta/rtl_phase1_queue.md` and `docs/_meta/rtl_phase1_queue.json`. Keep the graph and queue for provenance, but treat them as historical context rather than as the default source of truth for what to implement next. ## Immediate Next Task -If the user keeps the focus on `protocols/coaxpress`, the next practical step is either: +If the user keeps the focus on `protocols/srp`, the next practical step is to debug the 32-bit multi-beat `SrpV3AxiLite` ingress path now that the legacy 256-bit single-beat framing is proven through AXI-Lite read/write/post/error traffic. Start at the RX limiter/FIFO boundary and compare how the 32-bit request is released to the internal 32-bit state machine versus the 256-bit request that passes. + +If the user switches back to `protocols/coaxpress`, the next practical step is either: 1. debug and re-enable the skipped `CoaXPressConfig` investigation bench, starting with the SRP-driven request path that currently fails to complete through the real `CoaXPressConfig` / `SrpV3AxiLite` integration, or 2. deepen the remaining spec-level gaps around application-facing receive-side event payload delivery, normative CXPoF `/Q/` sequence handling, and fuller `/E/` / housekeeping-data interaction semantics. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 420992bf60..57f7a10880 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -31,7 +31,9 @@ - SRP RTL target matrix: - Covered now under the current GHDL-only flow: `SrpV3Axi` through the checked-in `protocols/srp/wrappers/SrpV3AxiWrapper.vhd` wrapper and `tests/protocols/srp/test_SrpV3Axi.py`. - The current SRPv3 AXI bench now validates non-posted write echo/readback, posted-write no-response behavior followed by readback, NULL header/footer behavior, response backpressure hold, TDEST propagation, full-word `TKEEP`, and footer bits for version mismatch, malformed write framing, invalid alignment, invalid request size, and downstream address error. - - Still open in `protocols/srp`: dedicated cocotb coverage for `SrpV3AxiLite`, `SrpV3AxiLiteFull`, and the older SRPv0 bridges. `SrpV3Core` is covered transitively through `SrpV3Axi`, but a direct core wrapper could still be useful later for ack/read-data timing fault injection that is hard to force through the AXI DMA wrapper. + - `SrpV3Core` now has a direct checked-in wrapper and reset/idle smoke test, while functional decode/data/ack behavior remains covered through the stronger `SrpV3Axi` matrix. A later direct-core fault-injection bench can revisit ack/read-data timing if needed. + - `AxiLiteSrpV0` and `SrpV0AxiLite` are now covered together by `protocols/srp/wrappers/SrpV0LoopbackWrapper.vhd` and `tests/protocols/srp/test_SrpV0Loopback.py`, which uses cocotb AXI-Lite master helpers to write/read through the old SRPv0 stream loopback and attached RAM. + - SRPv3 AXI-Lite status: `tests/protocols/srp/test_SrpV3AxiLite.py` now has active reset/idle coverage for the direct, full, and legacy-wide wrappers, plus an active directed regression for `SrpV3AxiLite` using the same 256-bit single-beat framing as the legacy VHDL testbench. The 32-bit multi-beat direct request path remains expected-open: malformed one-beat frames return, valid read frames are fully accepted, and simulation time advances to the bench timeout, but no `M_AXIL_ARVALID` or response frame appears. `SrpV3AxiLiteFull` remains expected-open for the current narrow probes and returns a different malformed-frame header. Enable skipped probes with `RUN_KNOWN_ISSUE_TESTS=1` only while debugging. - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. @@ -152,15 +154,14 @@ - The new package-surface coverage exposed a real `Code12b14bPkg` invalid-K disparity bug; `protocols/line-codes/rtl/Code12b14bPkg.vhd` now leaves `dispOut` unchanged on illegal K requests instead of tripping a GHDL bound-check failure. ## Current In-Progress Item -- Decide the next non-`pgp3` `protocols/pgp` target now that the shared VC FIFOs and the remaining non-vendor `pgp4/core/rtl` leaves are covered. -- Keep `pgp2b`, `pgp2fc`, `pgp3`, and `pgp4` organized as separate family subpackages with checked-in wrappers rather than falling back to generated shim HDL, but treat `pgp3` as deferred for now. -- Preserve the recent `pgp4` lesson: when the simulation wrapper only exposes stable lock/config surfaces, write the bench around those explicit contracts instead of claiming recovered payload coverage. -- Phase-2 follow-on for `protocols/pgp/pgp4`: broaden the current single payload-bitflip negative test into a small corruption-location matrix that separately covers SOF/header metadata corruption, EOF/tail corruption (including transmitted CRC-field corruption), and 66b header-side framing errors instead of treating all of those cases as equivalent to payload CRC failure. +- User-directed SRP regression work is active. The current passing SRP package covers `SrpV3Axi`, `SrpV3Core` reset/idle, SRPv0 AXI-Lite loopback, and `SrpV3AxiLite` through the legacy 256-bit single-beat framing. +- The main unresolved SRP debug item is the 32-bit multi-beat `SrpV3AxiLite` ingress path: the request is accepted, but no AXI-Lite AR or response appears before timeout. +- Keep the skipped `SrpV3AxiLiteFull` probes as expected-open until the direct 32-bit multi-beat path is understood, then revisit whether the full bridge has a separate protocol expectation or shares the same root cause. ## Next 3 Concrete Tasks -- Decide whether the next family pass is deeper directed coverage for the existing `pgp2b`/`pgp2fc` RX and alignment benches or a move into another non-deferred protocol area. -- Keep the `protocols/pgp/pgp4` low-speed leaves on their dedicated lock/config guardrail benches unless a later wrapper explicitly proves the serialized payload path end to end. -- Reuse the new `tests/protocols/pgp/shared/` helper and wrappers if later shared PGP utilities need direct cocotb coverage. +- Instrument or wrap the `SrpV3AxiLite` RX limiter/FIFO boundary to compare the passing 256-bit single-beat request against the failing 32-bit multi-beat request. +- Once the 32-bit direct path is understood, re-run and either re-enable or tighten the skipped `single_read` and directed probes for the narrow direct wrapper. +- Revisit `SrpV3AxiLiteFull` after the direct-path result, because its malformed-frame response header already differs from the direct implementation under the current narrow probe. ## Blockers And Risks - Runtime may grow quickly once configuration-heavy modules are added without careful tiering. diff --git a/protocols/srp/wrappers/SrpV0LoopbackWrapper.vhd b/protocols/srp/wrappers/SrpV0LoopbackWrapper.vhd new file mode 100644 index 0000000000..12f171a795 --- /dev/null +++ b/protocols/srp/wrappers/SrpV0LoopbackWrapper.vhd @@ -0,0 +1,178 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing loopback wrapper for the two SRPv0 AXI-Lite bridges +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; +use surf.AxiStreamPkg.all; +use surf.SsiPkg.all; + +entity SrpV0LoopbackWrapper is + port ( + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(11 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(31 downto 0); + S_AXI_WSTRB : in std_logic_vector(3 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(11 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(31 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic); +end entity SrpV0LoopbackWrapper; + +architecture rtl of SrpV0LoopbackWrapper is + + constant TPD_C : time := 10 ns / 4; + constant AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(4); + + signal axilClk : sl := '0'; + signal axilRst : sl := '1'; + + signal uutAxilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal uutAxilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + signal uutAxilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal uutAxilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal srpAxilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal srpAxilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + signal srpAxilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal srpAxilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + + signal txAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal txAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal rxAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal rxAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + +begin + + -- AXI-Lite shim layer for cocotb. + U_ShimLayerSlave : entity surf.SlaveAxiLiteIpIntegrator + generic map ( + INTERFACENAME => "S_AXI", + EN_ERROR_RESP => true, + HAS_PROT => 1, + HAS_WSTRB => 1, + ADDR_WIDTH => 12) + port map ( + S_AXI_ACLK => S_AXI_ACLK, + S_AXI_ARESETN => S_AXI_ARESETN, + S_AXI_AWADDR => S_AXI_AWADDR, + S_AXI_AWPROT => S_AXI_AWPROT, + S_AXI_AWVALID => S_AXI_AWVALID, + S_AXI_AWREADY => S_AXI_AWREADY, + S_AXI_WDATA => S_AXI_WDATA, + S_AXI_WSTRB => S_AXI_WSTRB, + S_AXI_WVALID => S_AXI_WVALID, + S_AXI_WREADY => S_AXI_WREADY, + S_AXI_BRESP => S_AXI_BRESP, + S_AXI_BVALID => S_AXI_BVALID, + S_AXI_BREADY => S_AXI_BREADY, + S_AXI_ARADDR => S_AXI_ARADDR, + S_AXI_ARPROT => S_AXI_ARPROT, + S_AXI_ARVALID => S_AXI_ARVALID, + S_AXI_ARREADY => S_AXI_ARREADY, + S_AXI_RDATA => S_AXI_RDATA, + S_AXI_RRESP => S_AXI_RRESP, + S_AXI_RVALID => S_AXI_RVALID, + S_AXI_RREADY => S_AXI_RREADY, + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => uutAxilReadMaster, + axilReadSlave => uutAxilReadSlave, + axilWriteMaster => uutAxilWriteMaster, + axilWriteSlave => uutAxilWriteSlave); + + -- SRPv0 bridge pair under test. + U_AxiLiteSrpV0 : entity surf.AxiLiteSrpV0 + generic map ( + TPD_G => TPD_C, + RESP_THOLD_G => 1, + SLAVE_READY_EN_G => true, + GEN_SYNC_FIFO_G => true, + FIFO_ADDR_WIDTH_G => 9, + FIFO_PAUSE_THRESH_G => 256, + AXI_STREAM_CONFIG_G => AXIS_CONFIG_C) + port map ( + mAxisClk => axilClk, + mAxisRst => axilRst, + mAxisMaster => txAxisMaster, + mAxisSlave => txAxisSlave, + sAxisClk => axilClk, + sAxisRst => axilRst, + sAxisMaster => rxAxisMaster, + sAxisSlave => rxAxisSlave, + sAxisCtrl => open, + axilClk => axilClk, + axilRst => axilRst, + sAxilWriteMaster => uutAxilWriteMaster, + sAxilWriteSlave => uutAxilWriteSlave, + sAxilReadMaster => uutAxilReadMaster, + sAxilReadSlave => uutAxilReadSlave); + + U_SrpV0AxiLite : entity surf.SrpV0AxiLite + generic map ( + TPD_G => TPD_C, + RESP_THOLD_G => 1, + SLAVE_READY_EN_G => true, + EN_32BIT_ADDR_G => true, + GEN_SYNC_FIFO_G => true, + FIFO_ADDR_WIDTH_G => 9, + FIFO_PAUSE_THRESH_G => 256, + AXI_STREAM_CONFIG_G => AXIS_CONFIG_C) + port map ( + sAxisClk => axilClk, + sAxisRst => axilRst, + sAxisMaster => txAxisMaster, + sAxisSlave => txAxisSlave, + sAxisCtrl => open, + mAxisClk => axilClk, + mAxisRst => axilRst, + mAxisMaster => rxAxisMaster, + mAxisSlave => rxAxisSlave, + axiLiteClk => axilClk, + axiLiteRst => axilRst, + mAxiLiteWriteMaster => srpAxilWriteMaster, + mAxiLiteWriteSlave => srpAxilWriteSlave, + mAxiLiteReadMaster => srpAxilReadMaster, + mAxiLiteReadSlave => srpAxilReadSlave); + + U_MEM : entity surf.AxiDualPortRam + generic map ( + TPD_G => TPD_C, + COMMON_CLK_G => true, + ADDR_WIDTH_G => 12, + DATA_WIDTH_G => 32) + port map ( + axiClk => axilClk, + axiRst => axilRst, + axiReadMaster => srpAxilReadMaster, + axiReadSlave => srpAxilReadSlave, + axiWriteMaster => srpAxilWriteMaster, + axiWriteSlave => srpAxilWriteSlave); + +end architecture rtl; diff --git a/protocols/srp/wrappers/SrpV3AxiLiteFullWrapper.vhd b/protocols/srp/wrappers/SrpV3AxiLiteFullWrapper.vhd new file mode 100644 index 0000000000..4a9e4b794d --- /dev/null +++ b/protocols/srp/wrappers/SrpV3AxiLiteFullWrapper.vhd @@ -0,0 +1,172 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for SrpV3AxiLiteFull regression testing +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; +use surf.AxiStreamPkg.all; +use surf.SsiPkg.all; + +entity SrpV3AxiLiteFullWrapper is + port ( + AXIS_ACLK : in std_logic; + AXIS_ARESETN : in std_logic; + S_AXIS_TVALID : in std_logic; + S_AXIS_TDATA : in std_logic_vector(31 downto 0); + S_AXIS_TKEEP : in std_logic_vector(3 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TDEST : in std_logic_vector(3 downto 0); + S_AXIS_TID : in std_logic_vector(0 downto 0); + S_AXIS_TUSER : in std_logic_vector(1 downto 0); + S_AXIS_TREADY : out std_logic; + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector(31 downto 0); + M_AXIS_TKEEP : out std_logic_vector(3 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TDEST : out std_logic_vector(3 downto 0); + M_AXIS_TID : out std_logic_vector(0 downto 0); + M_AXIS_TUSER : out std_logic_vector(1 downto 0); + M_AXIS_TREADY : in std_logic; + M_AXIL_AWADDR : out std_logic_vector(11 downto 0); + M_AXIL_AWPROT : out std_logic_vector(2 downto 0); + M_AXIL_AWVALID : out std_logic; + M_AXIL_AWREADY : in std_logic; + M_AXIL_WDATA : out std_logic_vector(31 downto 0); + M_AXIL_WSTRB : out std_logic_vector(3 downto 0); + M_AXIL_WVALID : out std_logic; + M_AXIL_WREADY : in std_logic; + M_AXIL_BRESP : in std_logic_vector(1 downto 0); + M_AXIL_BVALID : in std_logic; + M_AXIL_BREADY : out std_logic; + M_AXIL_ARADDR : out std_logic_vector(11 downto 0); + M_AXIL_ARPROT : out std_logic_vector(2 downto 0); + M_AXIL_ARVALID : out std_logic; + M_AXIL_ARREADY : in std_logic; + M_AXIL_RDATA : in std_logic_vector(31 downto 0); + M_AXIL_RRESP : in std_logic_vector(1 downto 0); + M_AXIL_RVALID : in std_logic; + M_AXIL_RREADY : out std_logic); +end entity SrpV3AxiLiteFullWrapper; + +architecture rtl of SrpV3AxiLiteFullWrapper is + + constant TPD_C : time := 10 ns / 4; + constant AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(4); + + signal axisRst : sl := '0'; + + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + +begin + + axisRst <= not AXIS_ARESETN; + + sAxisComb : process (S_AXIS_TDATA, S_AXIS_TDEST, S_AXIS_TKEEP, S_AXIS_TLAST, S_AXIS_TUSER, S_AXIS_TVALID) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := S_AXIS_TVALID; + v.tData(31 downto 0) := S_AXIS_TDATA; + v.tKeep(3 downto 0) := S_AXIS_TKEEP; + v.tLast := S_AXIS_TLAST; + v.tDest(3 downto 0) := S_AXIS_TDEST; + ssiSetUserEofe(AXIS_CONFIG_C, v, S_AXIS_TUSER(SSI_EOFE_C)); + ssiSetUserSof(AXIS_CONFIG_C, v, S_AXIS_TUSER(SSI_SOF_C)); + sAxisMaster <= v; + end process sAxisComb; + + S_AXIS_TREADY <= sAxisSlave.tReady; + + mAxisSlave.tReady <= M_AXIS_TREADY; + + M_AXIS_TVALID <= mAxisMaster.tValid; + M_AXIS_TDATA <= mAxisMaster.tData(31 downto 0); + M_AXIS_TKEEP <= mAxisMaster.tKeep(3 downto 0); + M_AXIS_TLAST <= mAxisMaster.tLast; + M_AXIS_TDEST <= mAxisMaster.tDest(3 downto 0); + M_AXIS_TID <= (others => '0'); + M_AXIS_TUSER <= ssiGetUserSof(AXIS_CONFIG_C, mAxisMaster) & ssiGetUserEofe(AXIS_CONFIG_C, mAxisMaster); + + -- DUT and cocotb-facing AXI-Lite master interface. + U_SRPv3 : entity surf.SrpV3AxiLiteFull + generic map ( + TPD_G => TPD_C, + SLAVE_READY_EN_G => true, + GEN_SYNC_FIFO_G => true, + AXI_STREAM_CONFIG_G => AXIS_CONFIG_C) + port map ( + sAxisClk => AXIS_ACLK, + sAxisRst => axisRst, + sAxisMaster => sAxisMaster, + sAxisSlave => sAxisSlave, + sAxisCtrl => open, + mAxisClk => AXIS_ACLK, + mAxisRst => axisRst, + mAxisMaster => mAxisMaster, + mAxisSlave => mAxisSlave, + axilClk => AXIS_ACLK, + axilRst => axisRst, + mAxilWriteMaster => axilWriteMaster, + mAxilWriteSlave => axilWriteSlave, + mAxilReadMaster => axilReadMaster, + mAxilReadSlave => axilReadSlave); + + U_AxiLiteMaster : entity surf.MasterAxiLiteIpIntegrator + generic map ( + INTERFACENAME => "M_AXIL", + EN_ERROR_RESP => true, + HAS_PROT => 1, + HAS_WSTRB => 1, + ADDR_WIDTH => 12) + port map ( + M_AXI_ACLK => AXIS_ACLK, + M_AXI_ARESETN => AXIS_ARESETN, + M_AXI_AWADDR => M_AXIL_AWADDR, + M_AXI_AWPROT => M_AXIL_AWPROT, + M_AXI_AWVALID => M_AXIL_AWVALID, + M_AXI_AWREADY => M_AXIL_AWREADY, + M_AXI_WDATA => M_AXIL_WDATA, + M_AXI_WSTRB => M_AXIL_WSTRB, + M_AXI_WVALID => M_AXIL_WVALID, + M_AXI_WREADY => M_AXIL_WREADY, + M_AXI_BRESP => M_AXIL_BRESP, + M_AXI_BVALID => M_AXIL_BVALID, + M_AXI_BREADY => M_AXIL_BREADY, + M_AXI_ARADDR => M_AXIL_ARADDR, + M_AXI_ARPROT => M_AXIL_ARPROT, + M_AXI_ARVALID => M_AXIL_ARVALID, + M_AXI_ARREADY => M_AXIL_ARREADY, + M_AXI_RDATA => M_AXIL_RDATA, + M_AXI_RRESP => M_AXIL_RRESP, + M_AXI_RVALID => M_AXIL_RVALID, + M_AXI_RREADY => M_AXIL_RREADY, + axilClk => open, + axilRst => open, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + +end architecture rtl; diff --git a/protocols/srp/wrappers/SrpV3AxiLiteWideWrapper.vhd b/protocols/srp/wrappers/SrpV3AxiLiteWideWrapper.vhd new file mode 100644 index 0000000000..aec6320799 --- /dev/null +++ b/protocols/srp/wrappers/SrpV3AxiLiteWideWrapper.vhd @@ -0,0 +1,173 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: 256-bit cocotb-facing wrapper for SrpV3AxiLite regression testing +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; +use surf.AxiStreamPkg.all; +use surf.SsiPkg.all; + +entity SrpV3AxiLiteWideWrapper is + port ( + AXIS_ACLK : in std_logic; + AXIS_ARESETN : in std_logic; + S_AXIS_TVALID : in std_logic; + S_AXIS_TDATA : in std_logic_vector(255 downto 0); + S_AXIS_TKEEP : in std_logic_vector(31 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TDEST : in std_logic_vector(3 downto 0); + S_AXIS_TID : in std_logic_vector(0 downto 0); + S_AXIS_TUSER : in std_logic_vector(1 downto 0); + S_AXIS_TREADY : out std_logic; + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector(255 downto 0); + M_AXIS_TKEEP : out std_logic_vector(31 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TDEST : out std_logic_vector(3 downto 0); + M_AXIS_TID : out std_logic_vector(0 downto 0); + M_AXIS_TUSER : out std_logic_vector(1 downto 0); + M_AXIS_TREADY : in std_logic; + M_AXIL_AWADDR : out std_logic_vector(11 downto 0); + M_AXIL_AWPROT : out std_logic_vector(2 downto 0); + M_AXIL_AWVALID : out std_logic; + M_AXIL_AWREADY : in std_logic; + M_AXIL_WDATA : out std_logic_vector(31 downto 0); + M_AXIL_WSTRB : out std_logic_vector(3 downto 0); + M_AXIL_WVALID : out std_logic; + M_AXIL_WREADY : in std_logic; + M_AXIL_BRESP : in std_logic_vector(1 downto 0); + M_AXIL_BVALID : in std_logic; + M_AXIL_BREADY : out std_logic; + M_AXIL_ARADDR : out std_logic_vector(11 downto 0); + M_AXIL_ARPROT : out std_logic_vector(2 downto 0); + M_AXIL_ARVALID : out std_logic; + M_AXIL_ARREADY : in std_logic; + M_AXIL_RDATA : in std_logic_vector(31 downto 0); + M_AXIL_RRESP : in std_logic_vector(1 downto 0); + M_AXIL_RVALID : in std_logic; + M_AXIL_RREADY : out std_logic); +end entity SrpV3AxiLiteWideWrapper; + +architecture rtl of SrpV3AxiLiteWideWrapper is + + constant TPD_C : time := 10 ns / 4; + constant AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(32); + + signal axisRst : sl := '0'; + + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + +begin + + axisRst <= not AXIS_ARESETN; + + sAxisComb : process (S_AXIS_TDATA, S_AXIS_TDEST, S_AXIS_TKEEP, S_AXIS_TLAST, S_AXIS_TUSER, S_AXIS_TVALID) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := S_AXIS_TVALID; + v.tData(255 downto 0) := S_AXIS_TDATA; + v.tKeep(31 downto 0) := S_AXIS_TKEEP; + v.tLast := S_AXIS_TLAST; + v.tDest(3 downto 0) := S_AXIS_TDEST; + ssiSetUserEofe(AXIS_CONFIG_C, v, S_AXIS_TUSER(SSI_EOFE_C)); + ssiSetUserSof(AXIS_CONFIG_C, v, S_AXIS_TUSER(SSI_SOF_C)); + sAxisMaster <= v; + end process sAxisComb; + + S_AXIS_TREADY <= sAxisSlave.tReady; + + mAxisSlave.tReady <= M_AXIS_TREADY; + + M_AXIS_TVALID <= mAxisMaster.tValid; + M_AXIS_TDATA <= mAxisMaster.tData(255 downto 0); + M_AXIS_TKEEP <= mAxisMaster.tKeep(31 downto 0); + M_AXIS_TLAST <= mAxisMaster.tLast; + M_AXIS_TDEST <= mAxisMaster.tDest(3 downto 0); + M_AXIS_TID <= (others => '0'); + M_AXIS_TUSER <= ssiGetUserSof(AXIS_CONFIG_C, mAxisMaster) & ssiGetUserEofe(AXIS_CONFIG_C, mAxisMaster); + + U_SRPv3 : entity surf.SrpV3AxiLite + generic map ( + TPD_G => TPD_C, + TX_VALID_THOLD_G => 1, + SLAVE_READY_EN_G => true, + GEN_SYNC_FIFO_G => true, + ENABLE_TIMER_G => false, + AXI_STREAM_CONFIG_G => AXIS_CONFIG_C) + port map ( + sAxisClk => AXIS_ACLK, + sAxisRst => axisRst, + sAxisMaster => sAxisMaster, + sAxisSlave => sAxisSlave, + sAxisCtrl => open, + mAxisClk => AXIS_ACLK, + mAxisRst => axisRst, + mAxisMaster => mAxisMaster, + mAxisSlave => mAxisSlave, + axilClk => AXIS_ACLK, + axilRst => axisRst, + mAxilWriteMaster => axilWriteMaster, + mAxilWriteSlave => axilWriteSlave, + mAxilReadMaster => axilReadMaster, + mAxilReadSlave => axilReadSlave); + + U_AxiLiteMaster : entity surf.MasterAxiLiteIpIntegrator + generic map ( + INTERFACENAME => "M_AXIL", + EN_ERROR_RESP => true, + HAS_PROT => 1, + HAS_WSTRB => 1, + ADDR_WIDTH => 12) + port map ( + M_AXI_ACLK => AXIS_ACLK, + M_AXI_ARESETN => AXIS_ARESETN, + M_AXI_AWADDR => M_AXIL_AWADDR, + M_AXI_AWPROT => M_AXIL_AWPROT, + M_AXI_AWVALID => M_AXIL_AWVALID, + M_AXI_AWREADY => M_AXIL_AWREADY, + M_AXI_WDATA => M_AXIL_WDATA, + M_AXI_WSTRB => M_AXIL_WSTRB, + M_AXI_WVALID => M_AXIL_WVALID, + M_AXI_WREADY => M_AXIL_WREADY, + M_AXI_BRESP => M_AXIL_BRESP, + M_AXI_BVALID => M_AXIL_BVALID, + M_AXI_BREADY => M_AXIL_BREADY, + M_AXI_ARADDR => M_AXIL_ARADDR, + M_AXI_ARPROT => M_AXIL_ARPROT, + M_AXI_ARVALID => M_AXIL_ARVALID, + M_AXI_ARREADY => M_AXIL_ARREADY, + M_AXI_RDATA => M_AXIL_RDATA, + M_AXI_RRESP => M_AXIL_RRESP, + M_AXI_RVALID => M_AXIL_RVALID, + M_AXI_RREADY => M_AXIL_RREADY, + axilClk => open, + axilRst => open, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + +end architecture rtl; diff --git a/protocols/srp/wrappers/SrpV3AxiLiteWrapper.vhd b/protocols/srp/wrappers/SrpV3AxiLiteWrapper.vhd new file mode 100644 index 0000000000..8ec2fd4dae --- /dev/null +++ b/protocols/srp/wrappers/SrpV3AxiLiteWrapper.vhd @@ -0,0 +1,174 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for SrpV3AxiLite regression testing +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; +use surf.AxiStreamPkg.all; +use surf.SsiPkg.all; + +entity SrpV3AxiLiteWrapper is + port ( + AXIS_ACLK : in std_logic; + AXIS_ARESETN : in std_logic; + S_AXIS_TVALID : in std_logic; + S_AXIS_TDATA : in std_logic_vector(31 downto 0); + S_AXIS_TKEEP : in std_logic_vector(3 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TDEST : in std_logic_vector(3 downto 0); + S_AXIS_TID : in std_logic_vector(0 downto 0); + S_AXIS_TUSER : in std_logic_vector(1 downto 0); + S_AXIS_TREADY : out std_logic; + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector(31 downto 0); + M_AXIS_TKEEP : out std_logic_vector(3 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TDEST : out std_logic_vector(3 downto 0); + M_AXIS_TID : out std_logic_vector(0 downto 0); + M_AXIS_TUSER : out std_logic_vector(1 downto 0); + M_AXIS_TREADY : in std_logic; + M_AXIL_AWADDR : out std_logic_vector(11 downto 0); + M_AXIL_AWPROT : out std_logic_vector(2 downto 0); + M_AXIL_AWVALID : out std_logic; + M_AXIL_AWREADY : in std_logic; + M_AXIL_WDATA : out std_logic_vector(31 downto 0); + M_AXIL_WSTRB : out std_logic_vector(3 downto 0); + M_AXIL_WVALID : out std_logic; + M_AXIL_WREADY : in std_logic; + M_AXIL_BRESP : in std_logic_vector(1 downto 0); + M_AXIL_BVALID : in std_logic; + M_AXIL_BREADY : out std_logic; + M_AXIL_ARADDR : out std_logic_vector(11 downto 0); + M_AXIL_ARPROT : out std_logic_vector(2 downto 0); + M_AXIL_ARVALID : out std_logic; + M_AXIL_ARREADY : in std_logic; + M_AXIL_RDATA : in std_logic_vector(31 downto 0); + M_AXIL_RRESP : in std_logic_vector(1 downto 0); + M_AXIL_RVALID : in std_logic; + M_AXIL_RREADY : out std_logic); +end entity SrpV3AxiLiteWrapper; + +architecture rtl of SrpV3AxiLiteWrapper is + + constant TPD_C : time := 10 ns / 4; + constant AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(4); + + signal axisRst : sl := '0'; + + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + +begin + + axisRst <= not AXIS_ARESETN; + + sAxisComb : process (S_AXIS_TDATA, S_AXIS_TDEST, S_AXIS_TKEEP, S_AXIS_TLAST, S_AXIS_TUSER, S_AXIS_TVALID) is + variable v : AxiStreamMasterType; + begin + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := S_AXIS_TVALID; + v.tData(31 downto 0) := S_AXIS_TDATA; + v.tKeep(3 downto 0) := S_AXIS_TKEEP; + v.tLast := S_AXIS_TLAST; + v.tDest(3 downto 0) := S_AXIS_TDEST; + ssiSetUserEofe(AXIS_CONFIG_C, v, S_AXIS_TUSER(SSI_EOFE_C)); + ssiSetUserSof(AXIS_CONFIG_C, v, S_AXIS_TUSER(SSI_SOF_C)); + sAxisMaster <= v; + end process sAxisComb; + + S_AXIS_TREADY <= sAxisSlave.tReady; + + mAxisSlave.tReady <= M_AXIS_TREADY; + + M_AXIS_TVALID <= mAxisMaster.tValid; + M_AXIS_TDATA <= mAxisMaster.tData(31 downto 0); + M_AXIS_TKEEP <= mAxisMaster.tKeep(3 downto 0); + M_AXIS_TLAST <= mAxisMaster.tLast; + M_AXIS_TDEST <= mAxisMaster.tDest(3 downto 0); + M_AXIS_TID <= (others => '0'); + M_AXIS_TUSER <= ssiGetUserSof(AXIS_CONFIG_C, mAxisMaster) & ssiGetUserEofe(AXIS_CONFIG_C, mAxisMaster); + + -- DUT and cocotb-facing AXI-Lite master interface. + U_SRPv3 : entity surf.SrpV3AxiLite + generic map ( + TPD_G => TPD_C, + TX_VALID_THOLD_G => 1, + SLAVE_READY_EN_G => true, + GEN_SYNC_FIFO_G => true, + ENABLE_TIMER_G => false, + AXI_STREAM_CONFIG_G => AXIS_CONFIG_C) + port map ( + sAxisClk => AXIS_ACLK, + sAxisRst => axisRst, + sAxisMaster => sAxisMaster, + sAxisSlave => sAxisSlave, + sAxisCtrl => open, + mAxisClk => AXIS_ACLK, + mAxisRst => axisRst, + mAxisMaster => mAxisMaster, + mAxisSlave => mAxisSlave, + axilClk => AXIS_ACLK, + axilRst => axisRst, + mAxilWriteMaster => axilWriteMaster, + mAxilWriteSlave => axilWriteSlave, + mAxilReadMaster => axilReadMaster, + mAxilReadSlave => axilReadSlave); + + U_AxiLiteMaster : entity surf.MasterAxiLiteIpIntegrator + generic map ( + INTERFACENAME => "M_AXIL", + EN_ERROR_RESP => true, + HAS_PROT => 1, + HAS_WSTRB => 1, + ADDR_WIDTH => 12) + port map ( + M_AXI_ACLK => AXIS_ACLK, + M_AXI_ARESETN => AXIS_ARESETN, + M_AXI_AWADDR => M_AXIL_AWADDR, + M_AXI_AWPROT => M_AXIL_AWPROT, + M_AXI_AWVALID => M_AXIL_AWVALID, + M_AXI_AWREADY => M_AXIL_AWREADY, + M_AXI_WDATA => M_AXIL_WDATA, + M_AXI_WSTRB => M_AXIL_WSTRB, + M_AXI_WVALID => M_AXIL_WVALID, + M_AXI_WREADY => M_AXIL_WREADY, + M_AXI_BRESP => M_AXIL_BRESP, + M_AXI_BVALID => M_AXIL_BVALID, + M_AXI_BREADY => M_AXIL_BREADY, + M_AXI_ARADDR => M_AXIL_ARADDR, + M_AXI_ARPROT => M_AXIL_ARPROT, + M_AXI_ARVALID => M_AXIL_ARVALID, + M_AXI_ARREADY => M_AXIL_ARREADY, + M_AXI_RDATA => M_AXIL_RDATA, + M_AXI_RRESP => M_AXIL_RRESP, + M_AXI_RVALID => M_AXIL_RVALID, + M_AXI_RREADY => M_AXIL_RREADY, + axilClk => open, + axilRst => open, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + +end architecture rtl; diff --git a/protocols/srp/wrappers/SrpV3CoreWrapper.vhd b/protocols/srp/wrappers/SrpV3CoreWrapper.vhd new file mode 100644 index 0000000000..f97f056105 --- /dev/null +++ b/protocols/srp/wrappers/SrpV3CoreWrapper.vhd @@ -0,0 +1,298 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for direct SrpV3Core regression testing +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.SsiPkg.all; +use surf.SrpV3Pkg.all; + +entity SrpV3CoreWrapper is + port ( + AXIS_ACLK : in std_logic; + AXIS_ARESETN : in std_logic; + S_AXIS_TVALID : in std_logic; + S_AXIS_TDATA : in std_logic_vector(31 downto 0); + S_AXIS_TKEEP : in std_logic_vector(3 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TDEST : in std_logic_vector(3 downto 0); + S_AXIS_TID : in std_logic_vector(0 downto 0); + S_AXIS_TUSER : in std_logic_vector(1 downto 0); + S_AXIS_TREADY : out std_logic; + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector(31 downto 0); + M_AXIS_TKEEP : out std_logic_vector(3 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TDEST : out std_logic_vector(3 downto 0); + M_AXIS_TID : out std_logic_vector(0 downto 0); + M_AXIS_TUSER : out std_logic_vector(1 downto 0); + M_AXIS_TREADY : in std_logic; + RD_AXIS_TVALID : in std_logic; + RD_AXIS_TDATA : in std_logic_vector(31 downto 0); + RD_AXIS_TKEEP : in std_logic_vector(3 downto 0); + RD_AXIS_TLAST : in std_logic; + RD_AXIS_TUSER : in std_logic_vector(1 downto 0); + RD_AXIS_TREADY : out std_logic; + WR_AXIS_TVALID : out std_logic; + WR_AXIS_TDATA : out std_logic_vector(31 downto 0); + WR_AXIS_TKEEP : out std_logic_vector(3 downto 0); + WR_AXIS_TLAST : out std_logic; + WR_AXIS_TUSER : out std_logic_vector(1 downto 0); + WR_AXIS_TREADY : in std_logic; + SRP_REQ_REQUEST : out std_logic; + SRP_REQ_REM_VER : out std_logic_vector(7 downto 0); + SRP_REQ_OPCODE : out std_logic_vector(1 downto 0); + SRP_REQ_PROT : out std_logic_vector(2 downto 0); + SRP_REQ_TID : out std_logic_vector(31 downto 0); + SRP_REQ_ADDR : out std_logic_vector(63 downto 0); + SRP_REQ_REQ_SIZE : out std_logic_vector(31 downto 0); + SRP_ACK_DONE : in std_logic; + SRP_ACK_RESP : in std_logic_vector(7 downto 0)); +end entity SrpV3CoreWrapper; + +architecture rtl of SrpV3CoreWrapper is + + constant TPD_C : time := 10 ns / 4; + constant AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(4); + constant CORE_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(8); + + signal axisRst : sl := '0'; + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal rdAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal rdAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal wrAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal wrAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal coreIbMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal coreIbSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal coreObMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal coreObSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal coreRdMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal coreRdSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal coreWrMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal coreWrSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + + signal srpReq : SrpV3ReqType := SRPV3_REQ_INIT_C; + signal srpAck : SrpV3AckType := SRPV3_ACK_INIT_C; + +begin + + axisRst <= not AXIS_ARESETN; + + srpAck.done <= SRP_ACK_DONE; + srpAck.respCode <= SRP_ACK_RESP; + + SRP_REQ_REQUEST <= srpReq.request; + SRP_REQ_REM_VER <= srpReq.remVer; + SRP_REQ_OPCODE <= srpReq.opCode; + SRP_REQ_PROT <= srpReq.prot; + SRP_REQ_TID <= srpReq.tid; + SRP_REQ_ADDR <= srpReq.addr; + SRP_REQ_REQ_SIZE <= srpReq.reqSize; + + -- AXI Stream shim layer. + U_ShimLayerSlave : entity surf.SlaveAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "S_AXIS", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 2, + TID_WIDTH => 1, + TDEST_WIDTH => 4, + TDATA_NUM_BYTES => 4) + port map ( + S_AXIS_ACLK => AXIS_ACLK, + S_AXIS_ARESETN => AXIS_ARESETN, + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TKEEP => S_AXIS_TKEEP, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TDEST => S_AXIS_TDEST, + S_AXIS_TID => S_AXIS_TID, + S_AXIS_TUSER => S_AXIS_TUSER, + S_AXIS_TREADY => S_AXIS_TREADY, + axisClk => open, + axisRst => open, + axisMaster => sAxisMaster, + axisSlave => sAxisSlave); + + U_ShimLayerMaster : entity surf.MasterAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "M_AXIS", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 2, + TID_WIDTH => 1, + TDEST_WIDTH => 4, + TDATA_NUM_BYTES => 4) + port map ( + M_AXIS_ACLK => AXIS_ACLK, + M_AXIS_ARESETN => AXIS_ARESETN, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TKEEP => M_AXIS_TKEEP, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TDEST => M_AXIS_TDEST, + M_AXIS_TID => M_AXIS_TID, + M_AXIS_TUSER => M_AXIS_TUSER, + M_AXIS_TREADY => M_AXIS_TREADY, + axisClk => open, + axisRst => open, + axisMaster => mAxisMaster, + axisSlave => mAxisSlave); + + U_ReadShim : entity surf.SlaveAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "RD_AXIS", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 2, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 4) + port map ( + S_AXIS_ACLK => AXIS_ACLK, + S_AXIS_ARESETN => AXIS_ARESETN, + S_AXIS_TVALID => RD_AXIS_TVALID, + S_AXIS_TDATA => RD_AXIS_TDATA, + S_AXIS_TKEEP => RD_AXIS_TKEEP, + S_AXIS_TLAST => RD_AXIS_TLAST, + S_AXIS_TDEST => "0", + S_AXIS_TID => "0", + S_AXIS_TUSER => RD_AXIS_TUSER, + S_AXIS_TREADY => RD_AXIS_TREADY, + axisClk => open, + axisRst => open, + axisMaster => rdAxisMaster, + axisSlave => rdAxisSlave); + + U_WriteShim : entity surf.MasterAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "WR_AXIS", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 2, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 4) + port map ( + M_AXIS_ACLK => AXIS_ACLK, + M_AXIS_ARESETN => AXIS_ARESETN, + M_AXIS_TVALID => WR_AXIS_TVALID, + M_AXIS_TDATA => WR_AXIS_TDATA, + M_AXIS_TKEEP => WR_AXIS_TKEEP, + M_AXIS_TLAST => WR_AXIS_TLAST, + M_AXIS_TDEST => open, + M_AXIS_TID => open, + M_AXIS_TUSER => WR_AXIS_TUSER, + M_AXIS_TREADY => WR_AXIS_TREADY, + axisClk => open, + axisRst => open, + axisMaster => wrAxisMaster, + axisSlave => wrAxisSlave); + + -- Width adapters around the 64-bit SRPv3 core-facing stream configuration. + U_InputResize : entity surf.AxiStreamResize + generic map ( + TPD_G => TPD_C, + SLAVE_AXI_CONFIG_G => AXIS_CONFIG_C, + MASTER_AXI_CONFIG_G => CORE_CONFIG_C) + port map ( + axisClk => AXIS_ACLK, + axisRst => axisRst, + sAxisMaster => sAxisMaster, + sAxisSlave => sAxisSlave, + mAxisMaster => coreIbMaster, + mAxisSlave => coreIbSlave); + + U_OutputResize : entity surf.AxiStreamResize + generic map ( + TPD_G => TPD_C, + SLAVE_AXI_CONFIG_G => CORE_CONFIG_C, + MASTER_AXI_CONFIG_G => AXIS_CONFIG_C) + port map ( + axisClk => AXIS_ACLK, + axisRst => axisRst, + sAxisMaster => coreObMaster, + sAxisSlave => coreObSlave, + mAxisMaster => mAxisMaster, + mAxisSlave => mAxisSlave); + + U_ReadResize : entity surf.AxiStreamResize + generic map ( + TPD_G => TPD_C, + SLAVE_AXI_CONFIG_G => AXIS_CONFIG_C, + MASTER_AXI_CONFIG_G => CORE_CONFIG_C) + port map ( + axisClk => AXIS_ACLK, + axisRst => axisRst, + sAxisMaster => rdAxisMaster, + sAxisSlave => rdAxisSlave, + mAxisMaster => coreRdMaster, + mAxisSlave => coreRdSlave); + + U_WriteResize : entity surf.AxiStreamResize + generic map ( + TPD_G => TPD_C, + SLAVE_AXI_CONFIG_G => CORE_CONFIG_C, + MASTER_AXI_CONFIG_G => AXIS_CONFIG_C) + port map ( + axisClk => AXIS_ACLK, + axisRst => axisRst, + sAxisMaster => coreWrMaster, + sAxisSlave => coreWrSlave, + mAxisMaster => wrAxisMaster, + mAxisSlave => wrAxisSlave); + + -- DUT. + U_DUT : entity surf.SrpV3Core + generic map ( + TPD_G => TPD_C, + SLAVE_READY_EN_G => true, + GEN_SYNC_FIFO_G => true, + AXI_STREAM_CONFIG_G => CORE_CONFIG_C) + port map ( + sAxisClk => AXIS_ACLK, + sAxisRst => axisRst, + sAxisMaster => coreIbMaster, + sAxisSlave => coreIbSlave, + sAxisCtrl => open, + mAxisClk => AXIS_ACLK, + mAxisRst => axisRst, + mAxisMaster => coreObMaster, + mAxisSlave => coreObSlave, + srpClk => AXIS_ACLK, + srpRst => axisRst, + srpReq => srpReq, + srpAck => srpAck, + srpWrMaster => coreWrMaster, + srpWrSlave => coreWrSlave, + srpRdMaster => coreRdMaster, + srpRdSlave => coreRdSlave); + +end architecture rtl; diff --git a/tests/protocols/srp/srp_test_utils.py b/tests/protocols/srp/srp_test_utils.py new file mode 100644 index 0000000000..a9be0edf67 --- /dev/null +++ b/tests/protocols/srp/srp_test_utils.py @@ -0,0 +1,258 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +from __future__ import annotations + +from dataclasses import dataclass + +from cocotb.triggers import RisingEdge, with_timeout + + +SRP_VERSION = 0x03 +SRP_READ = 0x0 +SRP_WRITE = 0x1 +SRP_POSTED_WRITE = 0x2 +SRP_NULL = 0x3 + +FOOTER_FRAME_ERROR = 1 << 10 +FOOTER_VERSION_MISMATCH = 1 << 11 +FOOTER_REQUEST_ERROR = 1 << 12 +FOOTER_ADDRESS_ERROR = 1 << 7 + + +@dataclass(frozen=True) +class SrpV3Request: + opcode: int + tid: int + address: int + byte_count: int + version: int = SRP_VERSION + timeout: int = 0 + prot: int = 0 + spare: int = 0 + ignore_mem_resp: int = 0 + + @property + def req_size(self) -> int: + return self.byte_count - 1 + + @property + def response_header(self) -> list[int]: + return srpv3_header( + opcode=self.opcode, + tid=self.tid, + address=self.address, + req_size=self.req_size, + version=SRP_VERSION, + timeout=self.timeout, + prot=self.prot, + spare=self.spare, + ignore_mem_resp=self.ignore_mem_resp, + ) + + +@dataclass(frozen=True) +class AxisResponse: + words: list[int] + tdest: list[int] + tuser: list[int] + tkeep: list[int] + + @property + def footer(self) -> int: + return self.words[-1] + + +class FlatSrpAxis: + def __init__( + self, + dut, + *, + clk, + source_prefix: str = "S_AXIS", + sink_prefix: str = "M_AXIS", + data_bytes: int = 4, + ): + self.dut = dut + self.clk = clk + self.source_prefix = source_prefix + self.sink_prefix = sink_prefix + self.data_bytes = data_bytes + + def _sig(self, prefix: str, suffix: str): + return getattr(self.dut, f"{prefix}_{suffix}") + + def init_source(self, *, prefix: str | None = None): + prefix = self.source_prefix if prefix is None else prefix + self._sig(prefix, "TVALID").setimmediatevalue(0) + self._sig(prefix, "TDATA").setimmediatevalue(0) + self._sig(prefix, "TKEEP").setimmediatevalue((1 << self.data_bytes) - 1) + self._sig(prefix, "TLAST").setimmediatevalue(0) + if hasattr(self.dut, f"{prefix}_TDEST"): + self._sig(prefix, "TDEST").setimmediatevalue(0) + if hasattr(self.dut, f"{prefix}_TID"): + self._sig(prefix, "TID").setimmediatevalue(0) + self._sig(prefix, "TUSER").setimmediatevalue(0) + + def init_sink(self, *, prefix: str | None = None, ready: int = 1): + prefix = self.sink_prefix if prefix is None else prefix + self._sig(prefix, "TREADY").setimmediatevalue(ready) + + async def send_words(self, words: list[int], *, tdest: int = 0, prefix: str | None = None): + await self.send_packed_words(words, tdest=tdest, prefix=prefix) + + async def send_packed_words(self, words: list[int], *, tdest: int = 0, prefix: str | None = None): + prefix = self.source_prefix if prefix is None else prefix + words_per_beat = self.data_bytes // 4 + if words_per_beat < 1: + raise ValueError("SRP helpers require at least one 32-bit word per stream beat") + + chunks = [ + words[index : index + words_per_beat] + for index in range(0, len(words), words_per_beat) + ] + + for index, chunk in enumerate(chunks): + data = 0 + for word_index, word in enumerate(chunk): + data |= (word & 0xFFFF_FFFF) << (32 * word_index) + + self._sig(prefix, "TVALID").value = 1 + self._sig(prefix, "TDATA").value = data + self._sig(prefix, "TKEEP").value = (1 << (4 * len(chunk))) - 1 + self._sig(prefix, "TLAST").value = int(index == len(chunks) - 1) + if hasattr(self.dut, f"{prefix}_TDEST"): + self._sig(prefix, "TDEST").value = tdest + if hasattr(self.dut, f"{prefix}_TID"): + self._sig(prefix, "TID").value = 0 + self._sig(prefix, "TUSER").value = 0x2 if index == 0 else 0x0 + + for _ in range(1024): + if int(self._sig(prefix, "TREADY").value) == 1: + break + await RisingEdge(self.clk) + else: + raise AssertionError(f"Timed out waiting for {prefix}_TREADY") + await RisingEdge(self.clk) + + self._sig(prefix, "TVALID").value = 0 + self._sig(prefix, "TLAST").value = 0 + self._sig(prefix, "TUSER").value = 0 + + async def _recv_response_unbounded(self, *, prefix: str) -> AxisResponse: + prefix = self.sink_prefix if prefix is None else prefix + self._sig(prefix, "TREADY").value = 1 + words = [] + tdest = [] + tuser = [] + tkeep = [] + + while True: + await RisingEdge(self.clk) + if int(self._sig(prefix, "TVALID").value) != 1: + continue + + data = int(self._sig(prefix, "TDATA").value) + keep = int(self._sig(prefix, "TKEEP").value) if hasattr(self.dut, f"{prefix}_TKEEP") else (1 << self.data_bytes) - 1 + active_bytes = keep.bit_count() + active_words = max(1, (active_bytes + 3) // 4) + + for word_index in range(active_words): + words.append((data >> (32 * word_index)) & 0xFFFF_FFFF) + if hasattr(self.dut, f"{prefix}_TDEST"): + tdest.append(int(self._sig(prefix, "TDEST").value)) + if hasattr(self.dut, f"{prefix}_TKEEP"): + tkeep.append(0xF) + + if hasattr(self.dut, f"{prefix}_TUSER"): + tuser.append(int(self._sig(prefix, "TUSER").value)) + if int(self._sig(prefix, "TLAST").value) == 1: + return AxisResponse(words=words, tdest=tdest, tuser=tuser, tkeep=tkeep) + + async def recv_response(self, *, prefix: str | None = None, timeout_time: int = 20) -> AxisResponse: + prefix = self.sink_prefix if prefix is None else prefix + return await with_timeout( + self._recv_response_unbounded(prefix=prefix), + timeout_time, + "us", + ) + + async def expect_no_response(self, *, cycles: int = 80, prefix: str | None = None): + prefix = self.sink_prefix if prefix is None else prefix + self._sig(prefix, "TREADY").value = 1 + for _ in range(cycles): + await RisingEdge(self.clk) + assert int(self._sig(prefix, "TVALID").value) == 0 + + +def srpv3_header( + *, + opcode: int, + tid: int, + address: int, + req_size: int, + version: int = SRP_VERSION, + timeout: int = 0, + prot: int = 0, + spare: int = 0, + ignore_mem_resp: int = 0, +) -> list[int]: + word0 = ( + (version & 0xFF) + | ((opcode & 0x3) << 8) + | ((spare & 0x7FF) << 10) + | ((ignore_mem_resp & 0x1) << 14) + | ((prot & 0x7) << 21) + | ((timeout & 0xFF) << 24) + ) + return [ + word0, + tid & 0xFFFF_FFFF, + address & 0xFFFF_FFFF, + (address >> 32) & 0xFFFF_FFFF, + req_size & 0xFFFF_FFFF, + ] + + +def srpv3_frame(request: SrpV3Request, payload: list[int] | None = None) -> list[int]: + payload = [] if payload is None else payload + return srpv3_header( + opcode=request.opcode, + tid=request.tid, + address=request.address, + req_size=request.req_size, + version=request.version, + timeout=request.timeout, + prot=request.prot, + spare=request.spare, + ignore_mem_resp=request.ignore_mem_resp, + ) + payload + + +def assert_srpv3_response( + response: AxisResponse, + request: SrpV3Request, + payload: list[int], + *, + footer_mask: int = 0, + footer_value: int = 0, + expected_tdest: int | None = None, +): + assert response.words[:5] == request.response_header + assert response.words[5:-1] == [word & 0xFFFF_FFFF for word in payload] + assert response.footer & footer_mask == footer_value + + if expected_tdest is not None: + assert response.tdest == [expected_tdest] * len(response.words) + + if response.tkeep: + assert response.tkeep == [0xF] * len(response.words) + if response.tuser: + assert response.tuser[0] & 0x2 == 0x2 diff --git a/tests/protocols/srp/test_SrpV0Loopback.py b/tests/protocols/srp/test_SrpV0Loopback.py new file mode 100644 index 0000000000..93a2592ed5 --- /dev/null +++ b/tests/protocols/srp/test_SrpV0Loopback.py @@ -0,0 +1,83 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Exercise the SRPv0 AXI-Lite loopback wrapper that connects +# `AxiLiteSrpV0` to `SrpV0AxiLite` and an AXI-Lite RAM backend. +# - Stimulus: Use a cocotb AXI-Lite master, matching the existing tests/axi +# helper style, to issue aligned writes and reads through the SRPv0 stream. +# - Checks: Returned read data must match the written RAM contents across +# several addresses, proving both SRPv0 bridge directions and the stream +# framing between them. +# - Timing: AXI-Lite transactions wait on the real bus handshakes, and a few +# idle cycles are inserted after reset and each write/read pair. + +import cocotb +import pytest +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotbext.axi import AxiLiteBus, AxiLiteMaster + +from tests.axi.utils import axil_read_u32, axil_write_u32 +from tests.common.regression_utils import run_surf_vhdl_test + + +class TB: + def __init__(self, dut): + self.dut = dut + cocotb.start_soon(Clock(dut.S_AXI_ACLK, 8.0, unit="ns").start()) + dut.S_AXI_ARESETN.setimmediatevalue(0) + self.axil = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "S_AXI"), dut.S_AXI_ACLK, dut.S_AXI_ARESETN, reset_active_level=False) + + async def cycle(self, count=1): + for _ in range(count): + await RisingEdge(self.dut.S_AXI_ACLK) + await Timer(1, unit="ns") + + async def reset(self): + # The wrapper uses the standard active-low AXI-Lite reset exposed by + # the IP-integrator shim. + self.dut.S_AXI_ARESETN.value = 0 + await self.cycle(12) + self.dut.S_AXI_ARESETN.value = 1 + await self.cycle(12) + + +@cocotb.test() +async def srpv0_axilite_loopback_round_trip_test(dut): + tb = TB(dut) + await tb.reset() + + # Drive several aligned addresses so the test proves that the old SRPv0 + # address packing survives the bridge-to-bridge stream path. + expected = { + 0x000: 0x10203040, + 0x004: 0x55667788, + 0x040: 0xA5A55A5A, + 0x100: 0xCAFEBABE, + } + for address, value in expected.items(): + await axil_write_u32(tb.axil, address, value) + await tb.cycle(2) + + for address, value in expected.items(): + assert await axil_read_u32(tb.axil, address) == value + await tb.cycle(2) + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="srpv0_axilite_loopback")]) +def test_SrpV0Loopback(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.srpv0loopbackwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ["protocols/srp/wrappers/SrpV0LoopbackWrapper.vhd"]}, + ) diff --git a/tests/protocols/srp/test_SrpV3AxiLite.py b/tests/protocols/srp/test_SrpV3AxiLite.py new file mode 100644 index 0000000000..b1f3a293c2 --- /dev/null +++ b/tests/protocols/srp/test_SrpV3AxiLite.py @@ -0,0 +1,309 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Keep reset coverage on the direct, full, and legacy-wide wrappers, +# and run active transactions through the direct 256-bit legacy framing that +# matches the existing VHDL testbench. +# - Stimulus: Drive SRPv3 write, read, posted-write, and malformed request +# frames into each wrapper's SSI-side AXI Stream port. +# - Checks: Non-posted writes echo data and update the RAM, posted writes remain +# silent but are readable later, invalid requests set the expected footer bits +# without returning payload data, and known-issue probes preserve the narrowed +# 32-bit multi-beat failure mode. +# - Timing: The bench uses ready/valid handshakes on every AXI Stream beat and +# bounded response waits so a stalled SRP request fails deterministically. + +import cocotb +import os +import pytest +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotbext.axi import AxiLiteBus, AxiLiteRam + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.protocols.srp.srp_test_utils import ( + FOOTER_ADDRESS_ERROR, + FOOTER_VERSION_MISMATCH, + FOOTER_FRAME_ERROR, + SRP_POSTED_WRITE, + SRP_NULL, + SRP_READ, + SRP_WRITE, + FlatSrpAxis, + SrpV3Request, + assert_srpv3_response, + srpv3_frame, +) + + +class TB: + def __init__(self, dut): + self.dut = dut + cocotb.start_soon(Clock(dut.AXIS_ACLK, 10.0, unit="ns").start()) + self.axis = FlatSrpAxis( + dut, + clk=dut.AXIS_ACLK, + data_bytes=int(os.environ.get("SRP_AXIS_BYTES", "4")), + ) + self.axil_ram = AxiLiteRam( + AxiLiteBus.from_prefix(dut, "M_AXIL"), + dut.AXIS_ACLK, + dut.AXIS_ARESETN, + reset_active_level=False, + size=2**12, + ) + + async def reset(self): + # Reset the wrapper and initialize both stream directions before any + # SRPv3 frame is allowed onto the input FIFO. + self.dut.AXIS_ARESETN.setimmediatevalue(0) + self.axis.init_source() + self.axis.init_sink() + for _ in range(80): + await RisingEdge(self.dut.AXIS_ACLK) + self.dut.AXIS_ARESETN.value = 1 + for _ in range(8): + await RisingEdge(self.dut.AXIS_ACLK) + + +def _selected_cocotb_test(name: str) -> bool: + return os.environ.get("SRP_AXI_LITE_COCOTB_TEST", "directed") == name + + +async def log_single_read_pins(dut, *, cycles: int = 32): + for index in range(cycles): + await RisingEdge(dut.AXIS_ACLK) + await Timer(1, unit="ns") + dut._log.info( + "single read monitor[%02d] tvalid=%s tlast=%s tdata=%s arvalid=%s arready=%s rvalid=%s rready=%s", + index, + dut.M_AXIS_TVALID.value, + dut.M_AXIS_TLAST.value, + dut.M_AXIS_TDATA.value, + dut.M_AXIL_ARVALID.value, + dut.M_AXIL_ARREADY.value, + dut.M_AXIL_RVALID.value, + dut.M_AXIL_RREADY.value, + ) + + +async def issue_and_check_error(tb: TB, request: SrpV3Request, *, expected_footer_bits: int): + await tb.axis.send_words(srpv3_frame(request)) + response = await tb.axis.recv_response() + assert_srpv3_response( + response, + request, + payload=[], + footer_mask=expected_footer_bits, + footer_value=expected_footer_bits, + ) + + +@cocotb.test(skip=not _selected_cocotb_test("reset_idle")) +async def srpv3_axilite_reset_idle_smoke_test(dut): + tb = TB(dut) + await tb.reset() + + # The reset-only test is intentionally active while the full directed test + # remains gated. It catches elaboration/reset issues without driving the + # request path that is under investigation. + await tb.axis.expect_no_response(cycles=32) + + +@cocotb.test(skip=not _selected_cocotb_test("short_frame")) +async def srpv3_axilite_short_frame_probe_test(dut): + tb = TB(dut) + await tb.reset() + + # A one-beat frame exercises the RX framing path without reaching the + # AXI-Lite master. It narrows failures before the memory backend is involved. + await tb.axis.send_words([0x0000_0003]) + assert_srpv3_response( + await tb.axis.recv_response(), + SrpV3Request(SRP_READ, 0, 0, 1), + [], + footer_mask=FOOTER_FRAME_ERROR, + footer_value=FOOTER_FRAME_ERROR, + ) + + +@cocotb.test(skip=not _selected_cocotb_test("single_read")) +async def srpv3_axilite_single_read_probe_test(dut): + tb = TB(dut) + await tb.reset() + + # First valid AXI-Lite-backed read. If this stalls, the failure is after + # header parsing and in the AXI-Lite transaction or response path. + read_req = SrpV3Request(SRP_READ, 0x5100_0100, 0x20, 4) + cocotb.start_soon(log_single_read_pins(dut)) + dut._log.info("single read probe: sending request") + await tb.axis.send_words(srpv3_frame(read_req), tdest=0x1) + dut._log.info("single read probe: request accepted") + dut._log.info( + "single read probe: post-request pins " + "M_AXIS_TVALID=%s M_AXIS_TREADY=%s M_AXIL_ARVALID=%s M_AXIL_ARREADY=%s M_AXIL_RREADY=%s", + dut.M_AXIS_TVALID.value, + dut.M_AXIS_TREADY.value, + dut.M_AXIL_ARVALID.value, + dut.M_AXIL_ARREADY.value, + dut.M_AXIL_RREADY.value, + ) + assert_srpv3_response( + await tb.axis.recv_response(), + read_req, + [0], + expected_tdest=0x1, + ) + + +@cocotb.test(skip=not _selected_cocotb_test("directed")) +async def srpv3_axilite_read_write_and_error_paths_test(dut): + tb = TB(dut) + await tb.reset() + + # Non-posted writes should echo the written words and commit them to the + # attached AXI-Lite RAM one aligned word at a time. + write_payload = [0x10203040, 0x55667788] + write_req = SrpV3Request(SRP_WRITE, 0x5100_0001, 0x20, 4 * len(write_payload)) + await tb.axis.send_words(srpv3_frame(write_req, write_payload), tdest=0x4) + assert_srpv3_response( + await tb.axis.recv_response(), + write_req, + write_payload, + expected_tdest=0x4, + ) + + read_req = SrpV3Request(SRP_READ, 0x5100_0002, 0x20, 4 * len(write_payload)) + await tb.axis.send_words(srpv3_frame(read_req), tdest=0x4) + assert_srpv3_response( + await tb.axis.recv_response(), + read_req, + write_payload, + expected_tdest=0x4, + ) + + # Posted writes are heavily used by software. They must update RAM without + # producing an outbound response frame. + posted_payload = [0xCAFEBABE] + posted_req = SrpV3Request(SRP_POSTED_WRITE, 0x5100_0003, 0x34, 4) + await tb.axis.send_words(srpv3_frame(posted_req, posted_payload), tdest=0x2) + await tb.axis.expect_no_response(cycles=80) + + posted_read_req = SrpV3Request(SRP_READ, 0x5100_0004, 0x34, 4) + await tb.axis.send_words(srpv3_frame(posted_read_req), tdest=0x2) + assert_srpv3_response( + await tb.axis.recv_response(), + posted_read_req, + posted_payload, + expected_tdest=0x2, + ) + + # Lock down the software-visible footer bits for the common reject paths + # that do not require a slow timeout-oriented test. + await issue_and_check_error( + tb, + SrpV3Request(SRP_READ, 0x5100_0005, 0x20, 4, version=0x02), + expected_footer_bits=FOOTER_VERSION_MISMATCH, + ) + await issue_and_check_error( + tb, + SrpV3Request(SRP_READ, 0x5100_0006, 0x1_0000_0000, 4), + expected_footer_bits=FOOTER_ADDRESS_ERROR, + ) + + +PARAMETER_SWEEP = [ + pytest.param( + { + "TOPLEVEL": "surf.srpv3axilitewrapper", + "WRAPPER_SOURCE": "protocols/srp/wrappers/SrpV3AxiLiteWrapper.vhd", + }, + id="srpv3_axilite_direct", + ), + pytest.param( + { + "TOPLEVEL": "surf.srpv3axilitefullwrapper", + "WRAPPER_SOURCE": "protocols/srp/wrappers/SrpV3AxiLiteFullWrapper.vhd", + }, + id="srpv3_axilite_full", + ), + pytest.param( + { + "TOPLEVEL": "surf.srpv3axilitewidewrapper", + "WRAPPER_SOURCE": "protocols/srp/wrappers/SrpV3AxiLiteWideWrapper.vhd", + "SRP_AXIS_BYTES": 32, + }, + id="srpv3_axilite_direct_wide", + ), +] + +LEGACY_WIDE_DIRECT_PARAMETERS = { + "TOPLEVEL": "surf.srpv3axilitewidewrapper", + "WRAPPER_SOURCE": "protocols/srp/wrappers/SrpV3AxiLiteWideWrapper.vhd", + "SRP_AXIS_BYTES": 32, +} + + +def _run_srpv3_axilite_case(parameters, cocotb_test: str, build_label: str): + extra_env = dict(parameters) + extra_env["SRP_AXI_LITE_COCOTB_TEST"] = cocotb_test + run_surf_vhdl_test( + test_file=__file__, + toplevel=parameters["TOPLEVEL"], + parameters={}, + extra_env=extra_env, + extra_vhdl_sources={"surf": [parameters["WRAPPER_SOURCE"]]}, + sim_build_key=f"tests/sim_build/protocols/srp/test_SrpV3AxiLite.{build_label}.{parameters['TOPLEVEL'].split('.')[-1]}", + ) + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +def test_SrpV3AxiLite_reset_idle(parameters): + _run_srpv3_axilite_case(parameters, "reset_idle", "reset_idle") + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +@pytest.mark.skipif( + os.environ.get("RUN_KNOWN_ISSUE_TESTS", "0") != "1", + reason="Expected-open SRPv3 AXI-Lite request-path probe.", +) +def test_SrpV3AxiLite_short_frame_probe(parameters): + _run_srpv3_axilite_case(parameters, "short_frame", "short_frame") + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +@pytest.mark.skipif( + os.environ.get("RUN_KNOWN_ISSUE_TESTS", "0") != "1", + reason="Expected-open SRPv3 AXI-Lite request-path probe.", +) +def test_SrpV3AxiLite_single_read_probe(parameters): + _run_srpv3_axilite_case(parameters, "single_read", "single_read") + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +@pytest.mark.skipif( + os.environ.get("RUN_KNOWN_ISSUE_TESTS", "0") != "1", + reason=( + "Expected-open SRPv3 AXI-Lite investigation: the 32-bit multi-beat " + "SrpV3AxiLite request path and SrpV3AxiLiteFull probes are still under " + "debug. Set RUN_KNOWN_ISSUE_TESTS=1 to reproduce while debugging." + ), +) +def test_SrpV3AxiLite(parameters): + _run_srpv3_axilite_case(parameters, "directed", "directed") + + +def test_SrpV3AxiLite_legacy_wide_directed(): + _run_srpv3_axilite_case( + LEGACY_WIDE_DIRECT_PARAMETERS, + "directed", + "legacy_wide_directed", + ) diff --git a/tests/protocols/srp/test_SrpV3Core.py b/tests/protocols/srp/test_SrpV3Core.py new file mode 100644 index 0000000000..caf551b7cb --- /dev/null +++ b/tests/protocols/srp/test_SrpV3Core.py @@ -0,0 +1,72 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Keep one direct `SrpV3Core` wrapper smoke case while functional +# SRPv3Core behavior is exercised transitively through the `SrpV3Axi` matrix. +# - Stimulus: Reset the wrapper with all exposed SRP, read-data, and stream +# inputs held idle. +# - Checks: The direct wrapper must elaborate, leave downstream request and +# write-output strobes idle after reset, and keep the response stream idle. +# - Timing: The bench samples after multiple post-reset clock edges so reset +# release and wrapper resize pipelines have time to settle. + +import cocotb +import pytest +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.protocols.srp.srp_test_utils import FlatSrpAxis + + +class TB: + def __init__(self, dut): + self.dut = dut + cocotb.start_soon(Clock(dut.AXIS_ACLK, 10.0, unit="ns").start()) + self.axis = FlatSrpAxis(dut, clk=dut.AXIS_ACLK) + self.read_axis = FlatSrpAxis(dut, clk=dut.AXIS_ACLK, source_prefix="RD_AXIS", sink_prefix="WR_AXIS") + + async def reset(self): + # Hold every exposed stimulus side idle so this direct-core smoke is + # only checking reset/elaboration behavior, not a duplicated AXI matrix. + self.dut.AXIS_ARESETN.setimmediatevalue(0) + self.axis.init_source() + self.axis.init_sink() + self.read_axis.init_source(prefix="RD_AXIS") + self.read_axis.init_sink(prefix="WR_AXIS") + self.dut.SRP_ACK_DONE.setimmediatevalue(0) + self.dut.SRP_ACK_RESP.setimmediatevalue(0) + for _ in range(80): + await RisingEdge(self.dut.AXIS_ACLK) + self.dut.AXIS_ARESETN.value = 1 + for _ in range(32): + await RisingEdge(self.dut.AXIS_ACLK) + + +@cocotb.test() +async def srpv3_core_reset_idle_smoke_test(dut): + tb = TB(dut) + await tb.reset() + + assert int(dut.SRP_REQ_REQUEST.value) == 0 + assert int(dut.M_AXIS_TVALID.value) == 0 + assert int(dut.WR_AXIS_TVALID.value) == 0 + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="direct_core_reset_idle")]) +def test_SrpV3Core(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.srpv3corewrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ["protocols/srp/wrappers/SrpV3CoreWrapper.vhd"]}, + ) From 7d3ebd818a780ee4ed1b77ec33ac76b9668e7ab6 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 27 Apr 2026 23:50:31 -0700 Subject: [PATCH 54/92] Fix SrpV3Core bug and add regression tests. Some SSI tests got created as well when chasing a phantom bug. But they are worth keeping. --- docs/_meta/rtl_regression_handoff.md | 4 +- docs/_meta/rtl_regression_progress.md | 15 +- protocols/srp/rtl/SrpV3Core.vhd | 9 +- .../srp/wrappers/SrpV3CoreNarrowWrapper.vhd | 234 ++++++++++++++++++ .../ssi/wrappers/SsiFrameLimiterWrapper.vhd | 16 +- tests/protocols/srp/srp_test_utils.py | 11 +- tests/protocols/srp/test_SrpV3Axi.py | 8 + tests/protocols/srp/test_SrpV3AxiLite.py | 87 ++++--- tests/protocols/srp/test_SrpV3CoreNarrow.py | 154 ++++++++++++ tests/protocols/ssi/test_SsiFrameLimiter.py | 2 +- .../ssi/test_SsiFrameLimiterPreserve.py | 104 ++++++++ 11 files changed, 588 insertions(+), 56 deletions(-) create mode 100644 protocols/srp/wrappers/SrpV3CoreNarrowWrapper.vhd create mode 100644 tests/protocols/srp/test_SrpV3CoreNarrow.py create mode 100644 tests/protocols/ssi/test_SsiFrameLimiterPreserve.py diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index 62578a8422..f811805a5f 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -26,7 +26,7 @@ - `EthMacRxImportXlgmii` and `EthMacTxExportXlgmii` are still placeholder no-op RTL; the checked-in tests now lock down that inert contract instead of claiming functional XLGMII support. - The remaining CoaXPress pure-VHDL gap is now `CoaXPressConfig`. The current CoaXPress receive benches now include a dual-lane `CoaXPressRxHsFsm` step/alignment case, a dual-lane `CoaXPressRx` lane-rotation case, and event packet validation through payload size, payload words, CRC, and `EOP` before `eventAck`. The receive side is still intentionally mixed-depth: event payload is validated for parser/CRC behavior but is not exported through an application-facing payload interface, and the multi-lane assembly checks still stop short of exhaustive per-lane stress coverage. - `tests/protocols/coaxpress/test_CoaXPressConfig.py` is intentionally checked in as a skipped investigation bench. When driven through the real SRP ingress, the current `CoaXPressConfig` / `SrpV3AxiLite` integration does not complete the request path within the bench timeout, so treat that as a likely RTL or integration defect to debug before re-enabling active assertions there. - - `tests/protocols/srp/test_SrpV3Axi.py` is now the active SRPv3 AXI regression, not just the old legacy-style posted-write/readback smoke. It validates non-posted write echo/readback, posted-write no-response behavior, NULL responses, response backpressure, TDEST propagation, full-word `TKEEP`, and footer bits for version mismatch, malformed write framing, invalid alignment, invalid request size, and downstream address error. `tests/protocols/srp/test_SrpV3Core.py` adds direct reset/idle smoke for `SrpV3Core`, while functional core behavior remains covered transitively through `SrpV3Axi`. `tests/protocols/srp/test_SrpV0Loopback.py` covers `AxiLiteSrpV0` and `SrpV0AxiLite` together through the checked-in SRPv0 stream loopback wrapper. `tests/protocols/srp/test_SrpV3AxiLite.py` carries active reset/idle smoke for direct, full, and legacy-wide wrappers, plus an active directed `SrpV3AxiLite` regression using the legacy 256-bit single-beat SRP framing. The remaining expected-open path is narrower: 32-bit multi-beat direct read frames are accepted and simulation time advances to the bench timeout, but no AXI-Lite AR or response frame appears; `SrpV3AxiLiteFull` also remains under investigation for the current narrow probes. Enable the skipped probes with `RUN_KNOWN_ISSUE_TESTS=1` only while debugging. + - `tests/protocols/srp/test_SrpV3Axi.py` is now the active SRPv3 AXI regression, not just the old legacy-style posted-write/readback smoke. It validates non-posted write echo/readback, posted-write no-response behavior, NULL responses, response backpressure, TDEST propagation, full-word `TKEEP`, and footer bits for version mismatch, malformed write framing, invalid alignment, invalid request size, downstream write address error, and downstream read address error. `tests/protocols/srp/test_SrpV3Core.py` adds direct reset/idle smoke for `SrpV3Core`, and the new `tests/protocols/srp/test_SrpV3CoreNarrow.py` bench adds direct 32-bit malformed-header and immediate-read-error fault injection. That narrow bench exposed and now covers two real `SrpV3Core` bugs: the response-header counter was not reset when emitting an error response from a truncated request header, and `READ_S` could miss an immediate downstream read error before any payload beat arrived. `tests/protocols/srp/test_SrpV0Loopback.py` covers `AxiLiteSrpV0` and `SrpV0AxiLite` together through the checked-in SRPv0 stream loopback wrapper. `tests/protocols/srp/test_SrpV3AxiLite.py` now carries active reset/idle smoke for direct, full, and legacy-wide wrappers, active narrow probes for the direct and full wrappers, active directed regressions for the direct and full wrappers, and the existing active legacy-wide directed regression. The direct narrow `SrpV3AxiLite` issue turned out to be a bench artifact, not an RTL defect: `tests/protocols/srp/srp_test_utils.py` now holds each source beat until a sampled clock edge confirms `TREADY`, which fixes the false failure on the original `SsiFrameLimiter` bypass configuration (`SLAVE_FIFO_G => false`). The focused `tests/protocols/ssi/test_SsiFrameLimiter.py` isolation regressions remain green in both limiter modes. The only remaining opt-in SRP coverage is now the duplicate wide-wrapper probe/direct slice under `RUN_KNOWN_ISSUE_TESTS=1`. - `tests/protocols/coaxpress/test_CoaXPressCore.py` now also carries an opt-in skipped known-issue bench for RX backpressure vs. FSM-error behavior. Enable it with `RUN_KNOWN_ISSUE_TESTS=1` and optionally shrink the load with `CXP_RX_OVERFLOW_STORM_FRAME_COUNT=`. The current local reproduction under sustained `M_DATA_TREADY=0` and repeated one-line image frames observed `RxFsmErrorCnt=2` while `RxOverflowCnt=0` at `96` frames, and a narrowing sweep showed no repro at `48` frames but a repro by `72` frames with `RxFsmErrorCnt=1` while `RxOverflowCnt=0`. That is closer to the user report than the earlier directed single-error tests and should be treated as a likely RTL defect under investigation. - For future CoaXPress work, treat the named packet classes and control bytes in `tests/protocols/coaxpress/coaxpress_test_utils.py` as shared spec anchors, not as optional local style. Those constants were normalized against the same `CXP-001-2021` / `CXPR-008-2021` references cited in `CoaXPressPkg.vhd`. Keep the packet-layer names aligned to the spec even where current RTL ports still use legacy `eventAck` naming on the receive side: `0x07` is an event packet and `0x08` is an event acknowledgment. - The current receive benches are intentionally mixed-depth: control-ack traffic is now driven with fuller spec-shaped framing, and `CoaXPressRxLane` now validates event payload size, payload words, CRC, and `EOP` before pulsing `eventAck`. Do not describe that as full application-facing event-payload coverage unless a payload output contract is added and covered. @@ -171,7 +171,7 @@ One small RTL fix landed during that validation pass because the new `AxiStreamD A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instantiation_graph.md` and `docs/_meta/rtl_instantiation_graph.json`, and the same generator now also emits a path-qualified bottom-up phase-1 queue at `docs/_meta/rtl_phase1_queue.md` and `docs/_meta/rtl_phase1_queue.json`. Keep the graph and queue for provenance, but treat them as historical context rather than as the default source of truth for what to implement next. ## Immediate Next Task -If the user keeps the focus on `protocols/srp`, the next practical step is to debug the 32-bit multi-beat `SrpV3AxiLite` ingress path now that the legacy 256-bit single-beat framing is proven through AXI-Lite read/write/post/error traffic. Start at the RX limiter/FIFO boundary and compare how the 32-bit request is released to the internal 32-bit state machine versus the 256-bit request that passes. +If the user keeps the focus on `protocols/srp`, the next practical step is cleanup rather than rescue work: decide whether the duplicate wide-wrapper opt-in cases in `tests/protocols/srp/test_SrpV3AxiLite.py` should be deleted, collapsed into the active legacy-wide directed test, or kept as explicit opt-in reproductions, and consider renaming `RUN_KNOWN_ISSUE_TESTS` now that it no longer refers to `SrpV3AxiLiteFull`. If the user switches back to `protocols/coaxpress`, the next practical step is either: 1. debug and re-enable the skipped `CoaXPressConfig` investigation bench, starting with the SRP-driven request path that currently fails to complete through the real `CoaXPressConfig` / `SrpV3AxiLite` integration, or diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 57f7a10880..c4fd51e3f0 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -31,9 +31,9 @@ - SRP RTL target matrix: - Covered now under the current GHDL-only flow: `SrpV3Axi` through the checked-in `protocols/srp/wrappers/SrpV3AxiWrapper.vhd` wrapper and `tests/protocols/srp/test_SrpV3Axi.py`. - The current SRPv3 AXI bench now validates non-posted write echo/readback, posted-write no-response behavior followed by readback, NULL header/footer behavior, response backpressure hold, TDEST propagation, full-word `TKEEP`, and footer bits for version mismatch, malformed write framing, invalid alignment, invalid request size, and downstream address error. - - `SrpV3Core` now has a direct checked-in wrapper and reset/idle smoke test, while functional decode/data/ack behavior remains covered through the stronger `SrpV3Axi` matrix. A later direct-core fault-injection bench can revisit ack/read-data timing if needed. + - `SrpV3Core` now has a direct checked-in wrapper and reset/idle smoke test plus a new narrow 32-bit fault-injection bench for malformed-header and immediate-read-error behavior. That bench exposed and now covers two core-side bugs: the response-header counter was not reset when emitting an error response from a truncated request header, and `READ_S` could miss an immediate downstream read error before any payload beat arrived. - `AxiLiteSrpV0` and `SrpV0AxiLite` are now covered together by `protocols/srp/wrappers/SrpV0LoopbackWrapper.vhd` and `tests/protocols/srp/test_SrpV0Loopback.py`, which uses cocotb AXI-Lite master helpers to write/read through the old SRPv0 stream loopback and attached RAM. - - SRPv3 AXI-Lite status: `tests/protocols/srp/test_SrpV3AxiLite.py` now has active reset/idle coverage for the direct, full, and legacy-wide wrappers, plus an active directed regression for `SrpV3AxiLite` using the same 256-bit single-beat framing as the legacy VHDL testbench. The 32-bit multi-beat direct request path remains expected-open: malformed one-beat frames return, valid read frames are fully accepted, and simulation time advances to the bench timeout, but no `M_AXIL_ARVALID` or response frame appears. `SrpV3AxiLiteFull` remains expected-open for the current narrow probes and returns a different malformed-frame header. Enable skipped probes with `RUN_KNOWN_ISSUE_TESTS=1` only while debugging. + - SRPv3 AXI-Lite status: `tests/protocols/srp/test_SrpV3AxiLite.py` now has active reset/idle coverage for the direct, full, and legacy-wide wrappers, active narrow probes (`short_frame`, `four_beat_header`, and `single_read`) for both the direct and full wrappers, active directed regressions for the direct and full wrappers, and the existing legacy-wide directed regression with duplicate wide probe/direct cases still opt-in. The earlier direct-wrapper failure was not an `SrpV3AxiLite` ingress RTL defect after all: the real issue was in `tests/protocols/srp/srp_test_utils.py`, where `FlatSrpAxis.send_packed_words()` treated combinational `TREADY` as immediate acceptance instead of holding each beat until a sampled clock edge confirmed the handshake. With that helper fixed and the two `SrpV3Core` fixes in place, the direct and full `SrpV3AxiLite` paths now pass on the original `SsiFrameLimiter` bypass configuration (`SLAVE_FIFO_G => false`), and the focused standalone `tests/protocols/ssi/test_SsiFrameLimiter.py` regressions remain green in both limiter modes. The current default SRP file run is `14 passed, 4 skipped`. - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. @@ -154,14 +154,13 @@ - The new package-surface coverage exposed a real `Code12b14bPkg` invalid-K disparity bug; `protocols/line-codes/rtl/Code12b14bPkg.vhd` now leaves `dispOut` unchanged on illegal K requests instead of tripping a GHDL bound-check failure. ## Current In-Progress Item -- User-directed SRP regression work is active. The current passing SRP package covers `SrpV3Axi`, `SrpV3Core` reset/idle, SRPv0 AXI-Lite loopback, and `SrpV3AxiLite` through the legacy 256-bit single-beat framing. -- The main unresolved SRP debug item is the 32-bit multi-beat `SrpV3AxiLite` ingress path: the request is accepted, but no AXI-Lite AR or response appears before timeout. -- Keep the skipped `SrpV3AxiLiteFull` probes as expected-open until the direct 32-bit multi-beat path is understood, then revisit whether the full bridge has a separate protocol expectation or shares the same root cause. +- User-directed SRP regression work is active. The current passing SRP package covers `SrpV3Axi`, `SrpV3Core` reset/idle plus narrow fault-injection, SRPv0 AXI-Lite loopback, the restored narrow direct `SrpV3AxiLite` path, the re-enabled `SrpV3AxiLiteFull` path, and the existing legacy-wide `SrpV3AxiLite` directed framing. +- The remaining SRP gating is now only the duplicate wide-wrapper probe/direct coverage in `tests/protocols/srp/test_SrpV3AxiLite.py`. Those cases can stay opt-in because the dedicated active legacy-wide directed test already covers the working wide non-bridge implementation. ## Next 3 Concrete Tasks -- Instrument or wrap the `SrpV3AxiLite` RX limiter/FIFO boundary to compare the passing 256-bit single-beat request against the failing 32-bit multi-beat request. -- Once the 32-bit direct path is understood, re-run and either re-enable or tighten the skipped `single_read` and directed probes for the narrow direct wrapper. -- Revisit `SrpV3AxiLiteFull` after the direct-path result, because its malformed-frame response header already differs from the direct implementation under the current narrow probe. +- Decide whether the duplicate wide-wrapper probe/direct cases should be deleted, collapsed into the legacy-wide active test, or kept only as explicit opt-in debug reproductions. +- Consider whether the new `tests/protocols/srp/test_SrpV3CoreNarrow.py` fault-injection bench should absorb more of the protocol-error matrix that is currently only covered transitively through `SrpV3Axi` and `SrpV3AxiLite`. +- If SRP stays in focus, the next useful cleanup is simplifying the `RUN_KNOWN_ISSUE_TESTS` naming now that the remaining opt-in coverage is just the duplicate wide-wrapper slice. ## Blockers And Risks - Runtime may grow quickly once configuration-heavy modules are added without careful tiering. diff --git a/protocols/srp/rtl/SrpV3Core.vhd b/protocols/srp/rtl/SrpV3Core.vhd index e5aa4515ab..57d1f2f91e 100755 --- a/protocols/srp/rtl/SrpV3Core.vhd +++ b/protocols/srp/rtl/SrpV3Core.vhd @@ -300,7 +300,6 @@ begin if rxMaster.tValid = '1' then -- Accept the data v.rxSlave.tReady := '1'; - -- Increment the header count v.hdrCnt := r.hdrCnt + 1; @@ -309,6 +308,7 @@ begin if rxMaster.tLast = '1' then -- Set the flags v.frameError := '1'; + v.hdrCnt := (others => '0'); -- Next State v.state := HDR_RESP_S; end if; @@ -506,6 +506,13 @@ begin end if; end if; + -- Some downstream implementations can reject a read immediately + -- without producing any read-data beats. In that case the request + -- still needs to complete through the ack/footer path. + if (srpAck.done = '1' and srpRdMasterInt.tValid = '0' and r.txnCnt = 0 and srpAck.respCode /= 0) then + v.state := WAIT_ACK_S; + end if; + -- Check if timer enabled if r.timeoutSize /= 0 then diff --git a/protocols/srp/wrappers/SrpV3CoreNarrowWrapper.vhd b/protocols/srp/wrappers/SrpV3CoreNarrowWrapper.vhd new file mode 100644 index 0000000000..91f9c05f84 --- /dev/null +++ b/protocols/srp/wrappers/SrpV3CoreNarrowWrapper.vhd @@ -0,0 +1,234 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: 32-bit cocotb-facing wrapper for direct SrpV3Core regressions +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.SsiPkg.all; +use surf.SrpV3Pkg.all; + +entity SrpV3CoreNarrowWrapper is + port ( + AXIS_ACLK : in std_logic; + AXIS_ARESETN : in std_logic; + S_AXIS_TVALID : in std_logic; + S_AXIS_TDATA : in std_logic_vector(31 downto 0); + S_AXIS_TKEEP : in std_logic_vector(3 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TDEST : in std_logic_vector(3 downto 0); + S_AXIS_TID : in std_logic_vector(0 downto 0); + S_AXIS_TUSER : in std_logic_vector(1 downto 0); + S_AXIS_TREADY : out std_logic; + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector(31 downto 0); + M_AXIS_TKEEP : out std_logic_vector(3 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TDEST : out std_logic_vector(3 downto 0); + M_AXIS_TID : out std_logic_vector(0 downto 0); + M_AXIS_TUSER : out std_logic_vector(1 downto 0); + M_AXIS_TREADY : in std_logic; + RD_AXIS_TVALID : in std_logic; + RD_AXIS_TDATA : in std_logic_vector(31 downto 0); + RD_AXIS_TKEEP : in std_logic_vector(3 downto 0); + RD_AXIS_TLAST : in std_logic; + RD_AXIS_TUSER : in std_logic_vector(1 downto 0); + RD_AXIS_TREADY : out std_logic; + WR_AXIS_TVALID : out std_logic; + WR_AXIS_TDATA : out std_logic_vector(31 downto 0); + WR_AXIS_TKEEP : out std_logic_vector(3 downto 0); + WR_AXIS_TLAST : out std_logic; + WR_AXIS_TUSER : out std_logic_vector(1 downto 0); + WR_AXIS_TREADY : in std_logic; + SRP_REQ_REQUEST : out std_logic; + SRP_REQ_REM_VER : out std_logic_vector(7 downto 0); + SRP_REQ_OPCODE : out std_logic_vector(1 downto 0); + SRP_REQ_PROT : out std_logic_vector(2 downto 0); + SRP_REQ_TID : out std_logic_vector(31 downto 0); + SRP_REQ_ADDR : out std_logic_vector(63 downto 0); + SRP_REQ_REQ_SIZE : out std_logic_vector(31 downto 0); + SRP_ACK_DONE : in std_logic; + SRP_ACK_RESP : in std_logic_vector(7 downto 0)); +end entity SrpV3CoreNarrowWrapper; + +architecture rtl of SrpV3CoreNarrowWrapper is + + constant TPD_C : time := 10 ns / 4; + constant AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(4); + + signal axisRst : sl := '0'; + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal rdAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal rdAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal wrAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal wrAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + + signal srpReq : SrpV3ReqType := SRPV3_REQ_INIT_C; + signal srpAck : SrpV3AckType := SRPV3_ACK_INIT_C; + +begin + + axisRst <= not AXIS_ARESETN; + + srpAck.done <= SRP_ACK_DONE; + srpAck.respCode <= SRP_ACK_RESP; + + SRP_REQ_REQUEST <= srpReq.request; + SRP_REQ_REM_VER <= srpReq.remVer; + SRP_REQ_OPCODE <= srpReq.opCode; + SRP_REQ_PROT <= srpReq.prot; + SRP_REQ_TID <= srpReq.tid; + SRP_REQ_ADDR <= srpReq.addr; + SRP_REQ_REQ_SIZE <= srpReq.reqSize; + + U_ShimLayerSlave : entity surf.SlaveAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "S_AXIS", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 2, + TID_WIDTH => 1, + TDEST_WIDTH => 4, + TDATA_NUM_BYTES => 4) + port map ( + S_AXIS_ACLK => AXIS_ACLK, + S_AXIS_ARESETN => AXIS_ARESETN, + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TKEEP => S_AXIS_TKEEP, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TDEST => S_AXIS_TDEST, + S_AXIS_TID => S_AXIS_TID, + S_AXIS_TUSER => S_AXIS_TUSER, + S_AXIS_TREADY => S_AXIS_TREADY, + axisClk => open, + axisRst => open, + axisMaster => sAxisMaster, + axisSlave => sAxisSlave); + + U_ShimLayerMaster : entity surf.MasterAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "M_AXIS", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 2, + TID_WIDTH => 1, + TDEST_WIDTH => 4, + TDATA_NUM_BYTES => 4) + port map ( + M_AXIS_ACLK => AXIS_ACLK, + M_AXIS_ARESETN => AXIS_ARESETN, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TKEEP => M_AXIS_TKEEP, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TDEST => M_AXIS_TDEST, + M_AXIS_TID => M_AXIS_TID, + M_AXIS_TUSER => M_AXIS_TUSER, + M_AXIS_TREADY => M_AXIS_TREADY, + axisClk => open, + axisRst => open, + axisMaster => mAxisMaster, + axisSlave => mAxisSlave); + + U_ReadShim : entity surf.SlaveAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "RD_AXIS", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 2, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 4) + port map ( + S_AXIS_ACLK => AXIS_ACLK, + S_AXIS_ARESETN => AXIS_ARESETN, + S_AXIS_TVALID => RD_AXIS_TVALID, + S_AXIS_TDATA => RD_AXIS_TDATA, + S_AXIS_TKEEP => RD_AXIS_TKEEP, + S_AXIS_TLAST => RD_AXIS_TLAST, + S_AXIS_TDEST => "0", + S_AXIS_TID => "0", + S_AXIS_TUSER => RD_AXIS_TUSER, + S_AXIS_TREADY => RD_AXIS_TREADY, + axisClk => open, + axisRst => open, + axisMaster => rdAxisMaster, + axisSlave => rdAxisSlave); + + U_WriteShim : entity surf.MasterAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "WR_AXIS", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 2, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 4) + port map ( + M_AXIS_ACLK => AXIS_ACLK, + M_AXIS_ARESETN => AXIS_ARESETN, + M_AXIS_TVALID => WR_AXIS_TVALID, + M_AXIS_TDATA => WR_AXIS_TDATA, + M_AXIS_TKEEP => WR_AXIS_TKEEP, + M_AXIS_TLAST => WR_AXIS_TLAST, + M_AXIS_TDEST => open, + M_AXIS_TID => open, + M_AXIS_TUSER => WR_AXIS_TUSER, + M_AXIS_TREADY => WR_AXIS_TREADY, + axisClk => open, + axisRst => open, + axisMaster => wrAxisMaster, + axisSlave => wrAxisSlave); + + U_DUT : entity surf.SrpV3Core + generic map ( + TPD_G => TPD_C, + SLAVE_READY_EN_G => true, + GEN_SYNC_FIFO_G => true, + AXI_STREAM_CONFIG_G => AXIS_CONFIG_C) + port map ( + sAxisClk => AXIS_ACLK, + sAxisRst => axisRst, + sAxisMaster => sAxisMaster, + sAxisSlave => sAxisSlave, + sAxisCtrl => open, + mAxisClk => AXIS_ACLK, + mAxisRst => axisRst, + mAxisMaster => mAxisMaster, + mAxisSlave => mAxisSlave, + srpClk => AXIS_ACLK, + srpRst => axisRst, + srpReq => srpReq, + srpAck => srpAck, + srpWrMaster => wrAxisMaster, + srpWrSlave => wrAxisSlave, + srpRdMaster => rdAxisMaster, + srpRdSlave => rdAxisSlave); + +end architecture rtl; diff --git a/protocols/ssi/wrappers/SsiFrameLimiterWrapper.vhd b/protocols/ssi/wrappers/SsiFrameLimiterWrapper.vhd index b465d0d7de..7ed1275a14 100644 --- a/protocols/ssi/wrappers/SsiFrameLimiterWrapper.vhd +++ b/protocols/ssi/wrappers/SsiFrameLimiterWrapper.vhd @@ -22,8 +22,12 @@ use surf.SsiPkg.all; entity SsiFrameLimiterWrapper is generic ( - DATA_BYTES_G : positive := 2; - FRAME_LIMIT_G : positive := 2); + DATA_BYTES_G : positive := 2; + FRAME_LIMIT_G : positive := 2; + EN_TIMEOUT_G : boolean := true; + SLAVE_FIFO_G : boolean := false; + MASTER_FIFO_G : boolean := true; + SLAVE_READY_G : boolean := true); port ( axisClk : in sl; axisRst : in sl; @@ -101,14 +105,14 @@ begin U_DUT : entity surf.SsiFrameLimiter generic map ( TPD_G => 1 ns, - EN_TIMEOUT_G => true, + EN_TIMEOUT_G => EN_TIMEOUT_G, MAXIS_CLK_FREQ_G => 200.0E+06, TIMEOUT_G => 25.0E-9, FRAME_LIMIT_G => FRAME_LIMIT_G, COMMON_CLK_G => true, - SLAVE_FIFO_G => false, - MASTER_FIFO_G => true, - SLAVE_READY_EN_G => true, + SLAVE_FIFO_G => SLAVE_FIFO_G, + MASTER_FIFO_G => MASTER_FIFO_G, + SLAVE_READY_EN_G => SLAVE_READY_G, SLAVE_AXI_CONFIG_G => AXIS_CONFIG_C, MASTER_AXI_CONFIG_G => AXIS_CONFIG_C) port map ( diff --git a/tests/protocols/srp/srp_test_utils.py b/tests/protocols/srp/srp_test_utils.py index a9be0edf67..9b0e16d014 100644 --- a/tests/protocols/srp/srp_test_utils.py +++ b/tests/protocols/srp/srp_test_utils.py @@ -12,7 +12,7 @@ from dataclasses import dataclass -from cocotb.triggers import RisingEdge, with_timeout +from cocotb.triggers import RisingEdge, Timer, with_timeout SRP_VERSION = 0x03 @@ -134,13 +134,18 @@ async def send_packed_words(self, words: list[int], *, tdest: int = 0, prefix: s self._sig(prefix, "TID").value = 0 self._sig(prefix, "TUSER").value = 0x2 if index == 0 else 0x0 + # Hold each beat until a sampled clock edge confirms that the DUT + # raised TREADY. The direct SRPv3 AXI-Lite wrappers expose a more + # combinational ingress path than the SSI helper benches, and + # consuming "instantaneous" ready before a clock edge can make the + # source outrun what the DUT actually sampled. for _ in range(1024): + await RisingEdge(self.clk) + await Timer(1, unit="ns") if int(self._sig(prefix, "TREADY").value) == 1: break - await RisingEdge(self.clk) else: raise AssertionError(f"Timed out waiting for {prefix}_TREADY") - await RisingEdge(self.clk) self._sig(prefix, "TVALID").value = 0 self._sig(prefix, "TLAST").value = 0 diff --git a/tests/protocols/srp/test_SrpV3Axi.py b/tests/protocols/srp/test_SrpV3Axi.py index 573bc43c15..1ae26a64d5 100644 --- a/tests/protocols/srp/test_SrpV3Axi.py +++ b/tests/protocols/srp/test_SrpV3Axi.py @@ -335,6 +335,14 @@ async def srpv3_axi_directed_protocol_matrix_test(dut): expected_footer_bits=FOOTER_ADDRESS_ERROR, ) + out_of_range_read_req = SrpRequest(SRP_READ, 0x4000_0006, 0x1_0000_0000, 4) + await issue_and_check_error( + tb, + out_of_range_read_req, + [], + expected_footer_bits=FOOTER_ADDRESS_ERROR, + ) + PARAMETER_SWEEP = [pytest.param({}, id="default_protocol_matrix")] diff --git a/tests/protocols/srp/test_SrpV3AxiLite.py b/tests/protocols/srp/test_SrpV3AxiLite.py index b1f3a293c2..8897f1adc4 100644 --- a/tests/protocols/srp/test_SrpV3AxiLite.py +++ b/tests/protocols/srp/test_SrpV3AxiLite.py @@ -25,7 +25,7 @@ import os import pytest from cocotb.clock import Clock -from cocotb.triggers import RisingEdge, Timer +from cocotb.triggers import RisingEdge from cocotbext.axi import AxiLiteBus, AxiLiteRam from tests.common.regression_utils import run_surf_vhdl_test @@ -78,23 +78,6 @@ def _selected_cocotb_test(name: str) -> bool: return os.environ.get("SRP_AXI_LITE_COCOTB_TEST", "directed") == name -async def log_single_read_pins(dut, *, cycles: int = 32): - for index in range(cycles): - await RisingEdge(dut.AXIS_ACLK) - await Timer(1, unit="ns") - dut._log.info( - "single read monitor[%02d] tvalid=%s tlast=%s tdata=%s arvalid=%s arready=%s rvalid=%s rready=%s", - index, - dut.M_AXIS_TVALID.value, - dut.M_AXIS_TLAST.value, - dut.M_AXIS_TDATA.value, - dut.M_AXIL_ARVALID.value, - dut.M_AXIL_ARREADY.value, - dut.M_AXIL_RVALID.value, - dut.M_AXIL_RREADY.value, - ) - - async def issue_and_check_error(tb: TB, request: SrpV3Request, *, expected_footer_bits: int): await tb.axis.send_words(srpv3_frame(request)) response = await tb.axis.recv_response() @@ -135,6 +118,32 @@ async def srpv3_axilite_short_frame_probe_test(dut): ) +@cocotb.test(skip=not _selected_cocotb_test("four_beat_header")) +async def srpv3_axilite_four_beat_header_probe_test(dut): + tb = TB(dut) + await tb.reset() + + # A four-beat frame proves the first packed 16-byte block is parsed and + # that the DUT can return a framing error before the final reqSize word. + await tb.axis.send_words( + [ + 0x0000_0003, + 0x5100_0200, + 0x0000_0020, + 0x0000_0000, + ], + tdest=0x3, + ) + assert_srpv3_response( + await tb.axis.recv_response(), + SrpV3Request(SRP_READ, 0x5100_0200, 0x20, 1), + [], + footer_mask=FOOTER_FRAME_ERROR, + footer_value=FOOTER_FRAME_ERROR, + expected_tdest=0x3, + ) + + @cocotb.test(skip=not _selected_cocotb_test("single_read")) async def srpv3_axilite_single_read_probe_test(dut): tb = TB(dut) @@ -143,7 +152,6 @@ async def srpv3_axilite_single_read_probe_test(dut): # First valid AXI-Lite-backed read. If this stalls, the failure is after # header parsing and in the AXI-Lite transaction or response path. read_req = SrpV3Request(SRP_READ, 0x5100_0100, 0x20, 4) - cocotb.start_soon(log_single_read_pins(dut)) dut._log.info("single read probe: sending request") await tb.axis.send_words(srpv3_frame(read_req), tdest=0x1) dut._log.info("single read probe: request accepted") @@ -265,39 +273,48 @@ def _run_srpv3_axilite_case(parameters, cocotb_test: str, build_label: str): ) +def _known_issue_opt_in_enabled() -> bool: + return os.environ.get("RUN_KNOWN_ISSUE_TESTS", "0") == "1" + + +def _skip_opt_in_probe(parameters): + if parameters["TOPLEVEL"] == "surf.srpv3axilitewidewrapper" and not _known_issue_opt_in_enabled(): + pytest.skip("Direct and Full SRPv3AxiLite probes are active; duplicate wide-wrapper probes stay opt-in.") + + +def _skip_opt_in_directed(parameters): + if parameters["TOPLEVEL"] == "surf.srpv3axilitewidewrapper" and not _known_issue_opt_in_enabled(): + pytest.skip( + "Direct and Full SRPv3AxiLite directed coverage are active; duplicate wide-wrapper cases stay opt-in." + ) + + @pytest.mark.parametrize("parameters", PARAMETER_SWEEP) def test_SrpV3AxiLite_reset_idle(parameters): _run_srpv3_axilite_case(parameters, "reset_idle", "reset_idle") @pytest.mark.parametrize("parameters", PARAMETER_SWEEP) -@pytest.mark.skipif( - os.environ.get("RUN_KNOWN_ISSUE_TESTS", "0") != "1", - reason="Expected-open SRPv3 AXI-Lite request-path probe.", -) def test_SrpV3AxiLite_short_frame_probe(parameters): + _skip_opt_in_probe(parameters) _run_srpv3_axilite_case(parameters, "short_frame", "short_frame") @pytest.mark.parametrize("parameters", PARAMETER_SWEEP) -@pytest.mark.skipif( - os.environ.get("RUN_KNOWN_ISSUE_TESTS", "0") != "1", - reason="Expected-open SRPv3 AXI-Lite request-path probe.", -) +def test_SrpV3AxiLite_four_beat_header_probe(parameters): + _skip_opt_in_probe(parameters) + _run_srpv3_axilite_case(parameters, "four_beat_header", "four_beat_header") + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) def test_SrpV3AxiLite_single_read_probe(parameters): + _skip_opt_in_probe(parameters) _run_srpv3_axilite_case(parameters, "single_read", "single_read") @pytest.mark.parametrize("parameters", PARAMETER_SWEEP) -@pytest.mark.skipif( - os.environ.get("RUN_KNOWN_ISSUE_TESTS", "0") != "1", - reason=( - "Expected-open SRPv3 AXI-Lite investigation: the 32-bit multi-beat " - "SrpV3AxiLite request path and SrpV3AxiLiteFull probes are still under " - "debug. Set RUN_KNOWN_ISSUE_TESTS=1 to reproduce while debugging." - ), -) def test_SrpV3AxiLite(parameters): + _skip_opt_in_directed(parameters) _run_srpv3_axilite_case(parameters, "directed", "directed") diff --git a/tests/protocols/srp/test_SrpV3CoreNarrow.py b/tests/protocols/srp/test_SrpV3CoreNarrow.py new file mode 100644 index 0000000000..d2047d3e3a --- /dev/null +++ b/tests/protocols/srp/test_SrpV3CoreNarrow.py @@ -0,0 +1,154 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Keep one direct 32-bit `SrpV3Core` bench focused on core-local +# failure modes that are awkward to inject cleanly through the larger AXI and +# AXI-Lite wrappers. +# - Stimulus: Drive malformed or valid narrow SRPv3 request headers into the +# core-facing stream while directly controlling the downstream ack/read-data +# return signals. +# - Checks: A truncated request header must still produce a correctly aligned +# error response header, and an immediate downstream read rejection must +# complete with the expected footer bit even when no read-data beat arrives. +# - Timing: The source and sink obey ready/valid sampling, while the downstream +# ack path is pulsed cycle-accurately to exercise the `READ_S` to `WAIT_ACK_S` +# corner case directly. + +import cocotb +import pytest +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.protocols.srp.srp_test_utils import ( + FOOTER_ADDRESS_ERROR, + FOOTER_FRAME_ERROR, + FlatSrpAxis, + SRP_READ, + SrpV3Request, + assert_srpv3_response, +) + + +class TB: + def __init__(self, dut): + self.dut = dut + cocotb.start_soon(Clock(dut.AXIS_ACLK, 10.0, unit="ns").start()) + self.axis = FlatSrpAxis(dut, clk=dut.AXIS_ACLK) + self.read_axis = FlatSrpAxis(dut, clk=dut.AXIS_ACLK, source_prefix="RD_AXIS", sink_prefix="WR_AXIS") + + async def reset(self): + self.dut.AXIS_ARESETN.setimmediatevalue(0) + self.axis.init_source() + self.axis.init_sink() + self.read_axis.init_source(prefix="RD_AXIS") + self.read_axis.init_sink(prefix="WR_AXIS") + self.dut.SRP_ACK_DONE.setimmediatevalue(0) + self.dut.SRP_ACK_RESP.setimmediatevalue(0) + for _ in range(80): + await RisingEdge(self.dut.AXIS_ACLK) + self.dut.AXIS_ARESETN.value = 1 + for _ in range(8): + await RisingEdge(self.dut.AXIS_ACLK) + + +@cocotb.test() +async def srpv3_core_narrow_header_error_probes_test(dut): + tb = TB(dut) + await tb.reset() + + await tb.axis.send_words([0x0000_0003]) + short_response = await tb.axis.recv_response() + assert_srpv3_response( + short_response, + SrpV3Request(SRP_READ, 0, 0, 1), + payload=[], + footer_mask=FOOTER_FRAME_ERROR, + footer_value=FOOTER_FRAME_ERROR, + ) + assert int(dut.SRP_REQ_REQUEST.value) == 0 + + await tb.axis.send_words( + [ + 0x0000_0003, + 0x5100_0200, + 0x0000_0020, + 0x0000_0000, + ], + tdest=0x3, + ) + four_beat_response = await tb.axis.recv_response() + assert_srpv3_response( + four_beat_response, + SrpV3Request(SRP_READ, 0x5100_0200, 0x20, 1), + payload=[], + footer_mask=FOOTER_FRAME_ERROR, + footer_value=FOOTER_FRAME_ERROR, + expected_tdest=0x3, + ) + assert int(dut.SRP_REQ_REQUEST.value) == 0 + + +@cocotb.test() +async def srpv3_core_narrow_immediate_read_error_test(dut): + tb = TB(dut) + await tb.reset() + dut.M_AXIS_TREADY.value = 0 + + request = SrpV3Request(SRP_READ, 0x6100_0001, 0x1_0000_0000, 4) + await tb.axis.send_words(request.response_header, tdest=0x5) + + for _ in range(64): + await RisingEdge(dut.AXIS_ACLK) + if int(dut.SRP_REQ_REQUEST.value) == 1: + break + else: + raise AssertionError("Timed out waiting for SRP_REQ_REQUEST") + + dut.SRP_ACK_RESP.value = FOOTER_ADDRESS_ERROR + dut.SRP_ACK_DONE.value = 1 + for _ in range(8): + await RisingEdge(dut.AXIS_ACLK) + if int(dut.SRP_REQ_REQUEST.value) == 0: + break + else: + raise AssertionError("Timed out waiting for SRP_REQ_REQUEST to release") + dut.SRP_ACK_DONE.value = 0 + dut.SRP_ACK_RESP.value = 0 + + for _ in range(64): + await RisingEdge(dut.AXIS_ACLK) + if int(dut.M_AXIS_TVALID.value) == 1: + break + else: + raise AssertionError("Timed out waiting for response header to become visible") + + response = await tb.axis.recv_response() + assert_srpv3_response( + response, + request, + payload=[], + footer_mask=FOOTER_ADDRESS_ERROR, + footer_value=FOOTER_ADDRESS_ERROR, + expected_tdest=0x5, + ) + assert int(dut.RD_AXIS_TREADY.value) == 0 + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="direct_core_narrow")]) +def test_SrpV3CoreNarrow(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.srpv3corenarrowwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ["protocols/srp/wrappers/SrpV3CoreNarrowWrapper.vhd"]}, + ) diff --git a/tests/protocols/ssi/test_SsiFrameLimiter.py b/tests/protocols/ssi/test_SsiFrameLimiter.py index 171ffb23d6..74366ec1c2 100644 --- a/tests/protocols/ssi/test_SsiFrameLimiter.py +++ b/tests/protocols/ssi/test_SsiFrameLimiter.py @@ -54,7 +54,7 @@ async def enforces_frame_limit_and_timeout_policy(dut): dut, source_prefix="sAxis", sink_prefix="mAxis", - initial_values={"mAxisTReady": 1}, + initial_values={"mAxisTReady": 0}, ) source = bench.source sink = bench.sink diff --git a/tests/protocols/ssi/test_SsiFrameLimiterPreserve.py b/tests/protocols/ssi/test_SsiFrameLimiterPreserve.py new file mode 100644 index 0000000000..46bcc2f844 --- /dev/null +++ b/tests/protocols/ssi/test_SsiFrameLimiterPreserve.py @@ -0,0 +1,104 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Exercise the narrow multi-beat frame-preservation regression through +# both common-clock `SsiFrameLimiter` ingress modes: the slave FIFO path and +# the bypass path. +# - Stimulus: Drive the five-beat 32-bit SSI frame shape that the SRPv3 +# AXI-Lite wrapper depends on, with `SOF` only on the first beat and `TLAST` +# only on the final beat. +# - Checks: The limiter must preserve beat count, payload, `SOF`, `TLAST`, +# `EOFE`, and `TDEST` exactly in both topologies. +# - Timing: The sink capture is whole-frame and bounded, so the checks do not +# depend on any fixed internal latency or specific ready polarity. + +import cocotb +import pytest + +from tests.common.regression_utils import run_surf_vhdl_test +from tests.protocols.ssi.ssi_test_utils import ( + assert_beat_list, + keep_mask, + recv_frame, + SsiBeat, + send_contiguous_frame, + setup_flat_ssi_testbench, + wait_output_clear, +) + + +@cocotb.test() +async def preserves_multi_beat_shape(dut): + keep = keep_mask(4) + + bench = await setup_flat_ssi_testbench( + dut, + source_prefix="sAxis", + sink_prefix="mAxis", + initial_values={"mAxisTReady": 0}, + ) + source = bench.source + sink = bench.sink + assert source is not None + assert sink is not None + + expected = [ + SsiBeat(data=0x0000_0003, keep=keep, last=0, dest=0x3, sof=1, eofe=0), + SsiBeat(data=0x5100_0200, keep=keep, last=0, dest=0x3, sof=0, eofe=0), + SsiBeat(data=0x0000_0020, keep=keep, last=0, dest=0x3, sof=0, eofe=0), + SsiBeat(data=0x0000_0000, keep=keep, last=0, dest=0x3, sof=0, eofe=0), + SsiBeat(data=0x0000_0000, keep=keep, last=1, dest=0x3, sof=0, eofe=0), + ] + send_task = cocotb.start_soon(send_contiguous_frame(source, expected, clk=bench.clk)) + frame = await recv_frame( + sink, + clk=bench.clk, + ready_signal=dut.mAxisTReady, + timeout_cycles=64, + ) + await send_task + assert_beat_list(frame, expected) + await wait_output_clear(sink, clk=bench.clk, ready_signal=dut.mAxisTReady) + + +PARAMETER_SWEEP = [ + pytest.param( + { + "DATA_BYTES_G": "4", + "FRAME_LIMIT_G": "8", + "EN_TIMEOUT_G": "false", + "SLAVE_FIFO_G": "true", + "MASTER_FIFO_G": "false", + }, + id="fifo_preserve", + ), + pytest.param( + { + "DATA_BYTES_G": "4", + "FRAME_LIMIT_G": "8", + "EN_TIMEOUT_G": "false", + "SLAVE_FIFO_G": "false", + "MASTER_FIFO_G": "false", + }, + id="bypass_preserve", + ), +] + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +def test_SsiFrameLimiterPreserve(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.ssiframelimiterwrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ["protocols/ssi/wrappers/SsiFrameLimiterWrapper.vhd"]}, + ) From c37ec503f705dc28a7b6ad0c8ba2385673a9a569 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 28 Apr 2026 00:09:31 -0700 Subject: [PATCH 55/92] Refactor. --- tests/axi/utils.py | 24 +++++++++++++++++++ .../ethernet/EthMacCore/ethmac_test_utils.py | 15 ++++++------ .../RawEthFramer/raw_eth_test_utils.py | 11 ++++----- .../coaxpress/coaxpress_test_utils.py | 11 +++++---- tests/protocols/srp/srp_test_utils.py | 20 ++++++---------- tests/protocols/ssi/ssi_test_utils.py | 14 ++++++----- 6 files changed, 58 insertions(+), 37 deletions(-) diff --git a/tests/axi/utils.py b/tests/axi/utils.py index 0fd53545d6..0c17184993 100644 --- a/tests/axi/utils.py +++ b/tests/axi/utils.py @@ -8,6 +8,8 @@ ## the terms contained in the LICENSE.txt file. ############################################################################## +from cocotb.triggers import RisingEdge, Timer + def ring_buffer_axil_addr(bus_index: int, buf: int = 0, high: int = 0) -> int: # The ring-buffer register maps pack MODE/STATUS more tightly than the @@ -31,3 +33,25 @@ async def axil_write_u32(master, address: int, value: int) -> None: txn = await master.write(address, value.to_bytes(4, "little")) assert txn.resp == AxiResp.OKAY + + +async def wait_sampled_ready( + ready_signal, + *, + clk, + timeout_cycles: int = 1024, + settle_time_ns: float = 1.0, +) -> None: + # AXI-style ready/valid transfers complete on a sampling clock edge, so a + # source must hold its current beat stable until a clock edge confirms that + # the sink presented `TREADY`. + for _ in range(timeout_cycles): + await RisingEdge(clk) + await Timer(settle_time_ns, unit="ns") + if int(ready_signal.value) == 1: + return + + label = getattr(ready_signal, "_name", None) + if label is None: + label = str(ready_signal) + raise AssertionError(f"Timed out waiting for sampled handshake on {label}") diff --git a/tests/ethernet/EthMacCore/ethmac_test_utils.py b/tests/ethernet/EthMacCore/ethmac_test_utils.py index efe1c8dfc0..0b6cb9ae55 100644 --- a/tests/ethernet/EthMacCore/ethmac_test_utils.py +++ b/tests/ethernet/EthMacCore/ethmac_test_utils.py @@ -18,6 +18,8 @@ from cocotb.clock import Clock from cocotb.triggers import RisingEdge, Timer +from tests.axi.utils import wait_sampled_ready + # Shared EMAC helpers centralize the flattened lane ordering and the common # packet builders used throughout `tests/ethernet/`. @@ -115,13 +117,12 @@ def drive(self, beat: EmacBeat) -> None: self._sig("UdpErr").value = beat.udperr async def wait_ready(self, *, clk) -> None: - # A source-side driver must hold the current beat until the DUT raises - # `TREADY`, even when that takes multiple cycles. - while True: - await RisingEdge(clk) - await Timer(1, unit="ns") - if int(self._sig("TReady").value) == 1: - return + # A source-side driver must hold the current beat until a sampled edge + # confirms that the DUT raised `TREADY`. + await wait_sampled_ready( + self._sig("TReady"), + clk=clk, + ) async def send(self, beat: EmacBeat, *, clk) -> None: # `send()` is the simple one-beat helper: drive, wait for acceptance, diff --git a/tests/ethernet/RawEthFramer/raw_eth_test_utils.py b/tests/ethernet/RawEthFramer/raw_eth_test_utils.py index f0ff29fe35..344b675bcb 100644 --- a/tests/ethernet/RawEthFramer/raw_eth_test_utils.py +++ b/tests/ethernet/RawEthFramer/raw_eth_test_utils.py @@ -16,7 +16,7 @@ from cocotbext.axi import AxiLiteBus, AxiLiteMaster from cocotb.triggers import RisingEdge, Timer -from tests.axi.utils import axil_read_u32, axil_write_u32 +from tests.axi.utils import axil_read_u32, axil_write_u32, wait_sampled_ready from tests.ethernet.EthMacCore.ethmac_test_utils import ( FlatEmacEndpoint, cycle, @@ -91,11 +91,10 @@ def drive(self, beat: RawAppBeat) -> None: self._sig("Eofe").value = beat.eofe async def wait_ready(self, *, clk) -> None: - while True: - await RisingEdge(clk) - await Timer(1, unit="ns") - if int(self._sig("TReady").value) == 1: - return + await wait_sampled_ready( + self._sig("TReady"), + clk=clk, + ) def snapshot(self) -> RawAppBeat: return RawAppBeat( diff --git a/tests/protocols/coaxpress/coaxpress_test_utils.py b/tests/protocols/coaxpress/coaxpress_test_utils.py index 94052d82e8..fc0d6ce969 100644 --- a/tests/protocols/coaxpress/coaxpress_test_utils.py +++ b/tests/protocols/coaxpress/coaxpress_test_utils.py @@ -18,6 +18,8 @@ from cocotb.handle import Immediate from cocotb.triggers import RisingEdge, Timer +from tests.axi.utils import wait_sampled_ready + CXP_IDLE = 0xB53C3CBC CXP_IDLE_K = 0x7 @@ -228,11 +230,10 @@ async def send_axis_payload( getattr(dut, f"{prefix}_TKEEP").value = (1 << len(payload)) - 1 getattr(dut, f"{prefix}_TLAST").value = 1 getattr(dut, f"{prefix}_TUSER").value = tuser - while True: - await RisingEdge(clk) - await Timer(1, unit="ns") - if int(getattr(dut, f"{prefix}_TREADY").value) == 1: - break + await wait_sampled_ready( + getattr(dut, f"{prefix}_TREADY"), + clk=clk, + ) getattr(dut, f"{prefix}_TVALID").value = 0 getattr(dut, f"{prefix}_TDATA").value = 0 getattr(dut, f"{prefix}_TKEEP").value = 0 diff --git a/tests/protocols/srp/srp_test_utils.py b/tests/protocols/srp/srp_test_utils.py index 9b0e16d014..c4da932a7d 100644 --- a/tests/protocols/srp/srp_test_utils.py +++ b/tests/protocols/srp/srp_test_utils.py @@ -12,7 +12,9 @@ from dataclasses import dataclass -from cocotb.triggers import RisingEdge, Timer, with_timeout +from cocotb.triggers import RisingEdge, with_timeout + +from tests.axi.utils import wait_sampled_ready SRP_VERSION = 0x03 @@ -134,18 +136,10 @@ async def send_packed_words(self, words: list[int], *, tdest: int = 0, prefix: s self._sig(prefix, "TID").value = 0 self._sig(prefix, "TUSER").value = 0x2 if index == 0 else 0x0 - # Hold each beat until a sampled clock edge confirms that the DUT - # raised TREADY. The direct SRPv3 AXI-Lite wrappers expose a more - # combinational ingress path than the SSI helper benches, and - # consuming "instantaneous" ready before a clock edge can make the - # source outrun what the DUT actually sampled. - for _ in range(1024): - await RisingEdge(self.clk) - await Timer(1, unit="ns") - if int(self._sig(prefix, "TREADY").value) == 1: - break - else: - raise AssertionError(f"Timed out waiting for {prefix}_TREADY") + await wait_sampled_ready( + self._sig(prefix, "TREADY"), + clk=self.clk, + ) self._sig(prefix, "TVALID").value = 0 self._sig(prefix, "TLAST").value = 0 diff --git a/tests/protocols/ssi/ssi_test_utils.py b/tests/protocols/ssi/ssi_test_utils.py index b135a87851..3abfd15448 100644 --- a/tests/protocols/ssi/ssi_test_utils.py +++ b/tests/protocols/ssi/ssi_test_utils.py @@ -17,6 +17,8 @@ from cocotb.clock import Clock from cocotb.triggers import FallingEdge, RisingEdge, Timer +from tests.axi.utils import wait_sampled_ready + @dataclass class SsiBeat: @@ -81,12 +83,12 @@ def drive(self, beat: SsiBeat): self._sig("Eofe").value = beat.eofe async def wait_ready(self, *, clk): - # A source keeps its beat stable until the sink raises `TREADY`. - while True: - await RisingEdge(clk) - await Timer(1, unit="ns") - if int(self._sig("TReady").value) == 1: - return + # A source keeps its beat stable until a sampled edge confirms that + # the sink raised `TREADY`. + await wait_sampled_ready( + self._sig("TReady"), + clk=clk, + ) async def send(self, beat: SsiBeat, *, clk): # `send()` is the simplest source-side helper: drive one beat, wait for From e9da281af861e1bda8fcb443450201e8c56df1e8 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 28 Apr 2026 09:03:21 -0700 Subject: [PATCH 56/92] More wait_sampled_ready consolidation. --- docs/_meta/rtl_regression_handoff.md | 8 +++++++- docs/_meta/rtl_regression_progress.md | 8 +++++++- .../ethernet/RoCEv2/test_EthMacRxCheckICrc.py | 10 +++------- .../coaxpress/test_CoaXPressRxHsFsm.py | 7 ++----- tests/protocols/coaxpress/test_CoaXPressTx.py | 7 ++----- .../coaxpress/test_CoaXPressTxLsFsm.py | 7 ++----- tests/protocols/pgp/pgp4/pgp4_test_utils.py | 18 ++++++++++++++++-- tests/protocols/srp/test_SrpV3Axi.py | 5 ++--- tests/protocols/ssi/test_SsiResizeFifoEofe.py | 5 ++--- 9 files changed, 43 insertions(+), 32 deletions(-) diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index f811805a5f..a78835c374 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -27,6 +27,10 @@ - The remaining CoaXPress pure-VHDL gap is now `CoaXPressConfig`. The current CoaXPress receive benches now include a dual-lane `CoaXPressRxHsFsm` step/alignment case, a dual-lane `CoaXPressRx` lane-rotation case, and event packet validation through payload size, payload words, CRC, and `EOP` before `eventAck`. The receive side is still intentionally mixed-depth: event payload is validated for parser/CRC behavior but is not exported through an application-facing payload interface, and the multi-lane assembly checks still stop short of exhaustive per-lane stress coverage. - `tests/protocols/coaxpress/test_CoaXPressConfig.py` is intentionally checked in as a skipped investigation bench. When driven through the real SRP ingress, the current `CoaXPressConfig` / `SrpV3AxiLite` integration does not complete the request path within the bench timeout, so treat that as a likely RTL or integration defect to debug before re-enabling active assertions there. - `tests/protocols/srp/test_SrpV3Axi.py` is now the active SRPv3 AXI regression, not just the old legacy-style posted-write/readback smoke. It validates non-posted write echo/readback, posted-write no-response behavior, NULL responses, response backpressure, TDEST propagation, full-word `TKEEP`, and footer bits for version mismatch, malformed write framing, invalid alignment, invalid request size, downstream write address error, and downstream read address error. `tests/protocols/srp/test_SrpV3Core.py` adds direct reset/idle smoke for `SrpV3Core`, and the new `tests/protocols/srp/test_SrpV3CoreNarrow.py` bench adds direct 32-bit malformed-header and immediate-read-error fault injection. That narrow bench exposed and now covers two real `SrpV3Core` bugs: the response-header counter was not reset when emitting an error response from a truncated request header, and `READ_S` could miss an immediate downstream read error before any payload beat arrived. `tests/protocols/srp/test_SrpV0Loopback.py` covers `AxiLiteSrpV0` and `SrpV0AxiLite` together through the checked-in SRPv0 stream loopback wrapper. `tests/protocols/srp/test_SrpV3AxiLite.py` now carries active reset/idle smoke for direct, full, and legacy-wide wrappers, active narrow probes for the direct and full wrappers, active directed regressions for the direct and full wrappers, and the existing active legacy-wide directed regression. The direct narrow `SrpV3AxiLite` issue turned out to be a bench artifact, not an RTL defect: `tests/protocols/srp/srp_test_utils.py` now holds each source beat until a sampled clock edge confirms `TREADY`, which fixes the false failure on the original `SsiFrameLimiter` bypass configuration (`SLAVE_FIFO_G => false`). The focused `tests/protocols/ssi/test_SsiFrameLimiter.py` isolation regressions remain green in both limiter modes. The only remaining opt-in SRP coverage is now the duplicate wide-wrapper probe/direct slice under `RUN_KNOWN_ISSUE_TESTS=1`. + - The broader flat-stream helper cleanup is now partially checked in beyond SRP. `tests/axi/utils.py` owns the shared `wait_sampled_ready()` primitive, and the flattened helper layers in `tests/protocols/ssi/ssi_test_utils.py`, `tests/protocols/srp/srp_test_utils.py`, `tests/protocols/pgp/pgp4/pgp4_test_utils.py`, `tests/protocols/coaxpress/coaxpress_test_utils.py`, `tests/ethernet/EthMacCore/ethmac_test_utils.py`, and `tests/ethernet/RawEthFramer/raw_eth_test_utils.py` now use it where appropriate instead of open-coded sampled-ready loops. Direct one-off benches that were good fits for the same cleanup now include `tests/protocols/srp/test_SrpV3Axi.py`, `tests/protocols/ssi/test_SsiResizeFifoEofe.py`, `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, `tests/protocols/coaxpress/test_CoaXPressTx.py`, `tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py`, and `tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py`. + - One subtle point from that cleanup is important for future edits: `wait_sampled_ready()` returns after the accepting clock edge has already occurred. A source must therefore advance or deassert immediately after the helper returns; leaving an extra post-handshake clock in place can create duplicate transfers or malformed streams. The current checked-in cleanup already corrected the false regressions that came from that mistake. + - The current validation subset for the flat-driver cleanup is `174 passed` across `tests/protocols/srp/test_SrpV3Axi.py`, `tests/protocols/ssi/test_SsiResizeFifoEofe.py`, the active PGP4 flat-wrapper subset, `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, `tests/protocols/coaxpress/test_CoaXPressTx.py`, `tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py`, and `tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py`. + - Remaining intentionally manual AXI-style cases after the static sweep are `tests/protocols/pgp/pgp4/test_Pgp4Rx.py`, the interleaved protocol-word capture helper in `tests/protocols/pgp/pgp4/pgp4_test_utils.py`, and the manual stress path in `tests/axi/axi_stream/test_AxiStreamScatterGather.py`. Those should only be refactored if a richer shared helper is added that can observe outputs while a source beat is still in flight. - `tests/protocols/coaxpress/test_CoaXPressCore.py` now also carries an opt-in skipped known-issue bench for RX backpressure vs. FSM-error behavior. Enable it with `RUN_KNOWN_ISSUE_TESTS=1` and optionally shrink the load with `CXP_RX_OVERFLOW_STORM_FRAME_COUNT=`. The current local reproduction under sustained `M_DATA_TREADY=0` and repeated one-line image frames observed `RxFsmErrorCnt=2` while `RxOverflowCnt=0` at `96` frames, and a narrowing sweep showed no repro at `48` frames but a repro by `72` frames with `RxFsmErrorCnt=1` while `RxOverflowCnt=0`. That is closer to the user report than the earlier directed single-error tests and should be treated as a likely RTL defect under investigation. - For future CoaXPress work, treat the named packet classes and control bytes in `tests/protocols/coaxpress/coaxpress_test_utils.py` as shared spec anchors, not as optional local style. Those constants were normalized against the same `CXP-001-2021` / `CXPR-008-2021` references cited in `CoaXPressPkg.vhd`. Keep the packet-layer names aligned to the spec even where current RTL ports still use legacy `eventAck` naming on the receive side: `0x07` is an event packet and `0x08` is an event acknowledgment. - The current receive benches are intentionally mixed-depth: control-ack traffic is now driven with fuller spec-shaped framing, and `CoaXPressRxLane` now validates event payload size, payload words, CRC, and `EOP` before pulsing `eventAck`. Do not describe that as full application-facing event-payload coverage unless a payload output contract is added and covered. @@ -171,7 +175,9 @@ One small RTL fix landed during that validation pass because the new `AxiStreamD A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instantiation_graph.md` and `docs/_meta/rtl_instantiation_graph.json`, and the same generator now also emits a path-qualified bottom-up phase-1 queue at `docs/_meta/rtl_phase1_queue.md` and `docs/_meta/rtl_phase1_queue.json`. Keep the graph and queue for provenance, but treat them as historical context rather than as the default source of truth for what to implement next. ## Immediate Next Task -If the user keeps the focus on `protocols/srp`, the next practical step is cleanup rather than rescue work: decide whether the duplicate wide-wrapper opt-in cases in `tests/protocols/srp/test_SrpV3AxiLite.py` should be deleted, collapsed into the active legacy-wide directed test, or kept as explicit opt-in reproductions, and consider renaming `RUN_KNOWN_ISSUE_TESTS` now that it no longer refers to `SrpV3AxiLiteFull`. +If the user keeps the focus on stream-helper cleanup rather than resuming a new subsystem, the next practical step is the remaining PGP interleaved source/capture helpers: decide whether `tests/protocols/pgp/pgp4/test_Pgp4Rx.py` and the protocol-word collector in `tests/protocols/pgp/pgp4/pgp4_test_utils.py` should stay intentionally manual or be folded into a richer shared helper that can hold a source beat through acceptance while concurrently capturing narrow output pulses. + +If the user keeps the focus on `protocols/srp`, the next practical step inside that subsystem is now mostly cleanup rather than rescue work: decide whether the duplicate wide-wrapper opt-in cases in `tests/protocols/srp/test_SrpV3AxiLite.py` should be deleted, collapsed into the active legacy-wide directed test, or kept as explicit opt-in reproductions, and consider renaming `RUN_KNOWN_ISSUE_TESTS` now that it no longer refers to `SrpV3AxiLiteFull`. If the user switches back to `protocols/coaxpress`, the next practical step is either: 1. debug and re-enable the skipped `CoaXPressConfig` investigation bench, starting with the SRP-driven request path that currently fails to complete through the real `CoaXPressConfig` / `SrpV3AxiLite` integration, or diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index c4fd51e3f0..fe2e05aacb 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -4,7 +4,7 @@ - Current phase: Phase-1 implementation active - Current subsystem: manual user-directed rollout tracking - Current focus module: user-directed SRP regression work under `protocols/srp`, with the existing `SrpV3AxiWrapper` cocotb bench widened into a directed SRPv3 protocol matrix covering reads, non-posted writes, posted writes, null requests, response backpressure, TDEST propagation, and representative error footers. -- Last updated: 2026-04-27 +- Last updated: 2026-04-28 ## Current Frontier Snapshot - Active planning rule: take the next work item from the user's manual direction, not from `docs/_meta/rtl_phase1_queue.{md,json}`. @@ -34,6 +34,12 @@ - `SrpV3Core` now has a direct checked-in wrapper and reset/idle smoke test plus a new narrow 32-bit fault-injection bench for malformed-header and immediate-read-error behavior. That bench exposed and now covers two core-side bugs: the response-header counter was not reset when emitting an error response from a truncated request header, and `READ_S` could miss an immediate downstream read error before any payload beat arrived. - `AxiLiteSrpV0` and `SrpV0AxiLite` are now covered together by `protocols/srp/wrappers/SrpV0LoopbackWrapper.vhd` and `tests/protocols/srp/test_SrpV0Loopback.py`, which uses cocotb AXI-Lite master helpers to write/read through the old SRPv0 stream loopback and attached RAM. - SRPv3 AXI-Lite status: `tests/protocols/srp/test_SrpV3AxiLite.py` now has active reset/idle coverage for the direct, full, and legacy-wide wrappers, active narrow probes (`short_frame`, `four_beat_header`, and `single_read`) for both the direct and full wrappers, active directed regressions for the direct and full wrappers, and the existing legacy-wide directed regression with duplicate wide probe/direct cases still opt-in. The earlier direct-wrapper failure was not an `SrpV3AxiLite` ingress RTL defect after all: the real issue was in `tests/protocols/srp/srp_test_utils.py`, where `FlatSrpAxis.send_packed_words()` treated combinational `TREADY` as immediate acceptance instead of holding each beat until a sampled clock edge confirmed the handshake. With that helper fixed and the two `SrpV3Core` fixes in place, the direct and full `SrpV3AxiLite` paths now pass on the original `SsiFrameLimiter` bypass configuration (`SLAVE_FIFO_G => false`), and the focused standalone `tests/protocols/ssi/test_SsiFrameLimiter.py` regressions remain green in both limiter modes. The current default SRP file run is `14 passed, 4 skipped`. +- Flat AXI/SSI helper cleanup status: + - `tests/axi/utils.py` now owns the shared `wait_sampled_ready()` primitive for flattened ready/valid sources that cannot use `cocotbext.axi.AxiStreamSource` directly. + - The current flat-driver users are `tests/protocols/ssi/ssi_test_utils.py`, `tests/protocols/srp/srp_test_utils.py`, `tests/protocols/pgp/pgp4/pgp4_test_utils.py`, `tests/protocols/coaxpress/coaxpress_test_utils.py`, `tests/ethernet/EthMacCore/ethmac_test_utils.py`, and `tests/ethernet/RawEthFramer/raw_eth_test_utils.py`, plus direct one-off benches in `tests/protocols/srp/test_SrpV3Axi.py`, `tests/protocols/ssi/test_SsiResizeFifoEofe.py`, `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, `tests/protocols/coaxpress/test_CoaXPressTx.py`, `tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py`, and `tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py`. + - One important cleanup correction landed during that pass: when a source now waits with `wait_sampled_ready()`, the handshake already completed on the sampled edge, so the source must advance or deassert immediately after the helper returns. The first draft left extra post-handshake clock edges in a few benches and caused false regressions; those benches were corrected before the current validation run. + - Current validation for that cleanup pass is green on `tests/protocols/srp/test_SrpV3Axi.py`, `tests/protocols/ssi/test_SsiResizeFifoEofe.py`, the PGP4 subset (`test_Pgp4Tx.py`, `test_Pgp4LiteRxLowSpeed.py`, `test_Pgp4RxCrcError.py`, `test_Pgp4RxLiteLowSpeedLane.py`, `test_Pgp4TxProtocol.py`, `test_Pgp4TxLiteProtocol.py`, `test_Pgp4TxLite.py`), `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, `tests/protocols/coaxpress/test_CoaXPressTx.py`, `tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py`, and `tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py` with `174 passed`. + - Remaining intentionally manual cases after the static sweep are `tests/protocols/pgp/pgp4/test_Pgp4Rx.py`, the interleaved capture helper in `tests/protocols/pgp/pgp4/pgp4_test_utils.py`, and the manual stress path in `tests/axi/axi_stream/test_AxiStreamScatterGather.py`. Those were left alone because they interleave input acceptance with concurrent output observation or deliberately spell out handshake timing inside the test body. - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. diff --git a/tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py b/tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py index 1565b8c61f..993b8d4bf8 100644 --- a/tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py +++ b/tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py @@ -31,6 +31,7 @@ import pytest from cocotb.triggers import RisingEdge, Timer +from tests.axi.utils import wait_sampled_ready from tests.common.regression_utils import run_surf_vhdl_test from tests.ethernet.EthMacCore.ethmac_test_utils import ( ETHMAC_RTL_SOURCES, @@ -50,13 +51,8 @@ async def send_crc_word(dut, *, data: int, clk) -> None: dut.sCrcTData.value = data dut.sCrcTValid.value = 1 - - while True: - await RisingEdge(clk) - await Timer(1, unit="ns") - if int(dut.sCrcTReady.value) == 1: - dut.sCrcTValid.value = 0 - return + await wait_sampled_ready(dut.sCrcTReady, clk=clk) + dut.sCrcTValid.value = 0 async def capture_crc_errors(dut, *, clk, timeout_cycles: int = 64) -> list[int]: diff --git a/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py b/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py index f7dabc67f1..6e382a2310 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py +++ b/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py @@ -27,6 +27,7 @@ import pytest from cocotb.triggers import RisingEdge, Timer +from tests.axi.utils import wait_sampled_ready from tests.common.regression_utils import env_int, parameter_case, run_surf_vhdl_test from tests.protocols.coaxpress.coaxpress_test_utils import ( CXP_MARKER, @@ -66,11 +67,7 @@ async def _send_handshaked_beat(dut, *, data: int, keep: int, last: int = 0) -> dut.sAxisTData.value = data dut.sAxisTKeep.value = keep dut.sAxisTLast.value = last - while True: - await RisingEdge(dut.rxClk) - await Timer(1, unit="ns") - if int(dut.sAxisTReady.value) == 1: - break + await wait_sampled_ready(dut.sAxisTReady, clk=dut.rxClk) dut.sAxisTValid.value = 0 dut.sAxisTData.value = 0 dut.sAxisTKeep.value = 0 diff --git a/tests/protocols/coaxpress/test_CoaXPressTx.py b/tests/protocols/coaxpress/test_CoaXPressTx.py index 79f64318e2..8bf428bd1d 100644 --- a/tests/protocols/coaxpress/test_CoaXPressTx.py +++ b/tests/protocols/coaxpress/test_CoaXPressTx.py @@ -26,6 +26,7 @@ import cocotb from cocotb.triggers import RisingEdge, Timer +from tests.axi.utils import wait_sampled_ready from tests.common.regression_utils import run_surf_vhdl_test from tests.protocols.coaxpress.coaxpress_test_utils import ( CXP_D21_5, @@ -72,11 +73,7 @@ async def _drive_cfg_packet(dut, beats: list[tuple[int, int]]) -> None: dut.cfgTData.value = data dut.cfgTUser.value = is_k dut.cfgTLast.value = 1 if index == len(beats) - 1 else 0 - while True: - await RisingEdge(dut.cfgClk) - await Timer(1, unit="ns") - if int(dut.cfgTReady.value) == 1: - break + await wait_sampled_ready(dut.cfgTReady, clk=dut.cfgClk) dut.cfgTValid.value = 0 dut.cfgTData.value = 0 dut.cfgTUser.value = 0 diff --git a/tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py b/tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py index bdddc6ada7..cc8918333a 100644 --- a/tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py +++ b/tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py @@ -25,6 +25,7 @@ import cocotb from cocotb.triggers import RisingEdge, Timer +from tests.axi.utils import wait_sampled_ready from tests.common.regression_utils import run_surf_vhdl_test from tests.protocols.coaxpress.coaxpress_test_utils import ( CXP_D21_5, @@ -54,11 +55,7 @@ async def _drive_cfg_bytes(dut, beats: list[tuple[int, int]]) -> None: dut.cfgTValid.value = 1 dut.cfgTData.value = data dut.cfgTUser.value = is_k - while True: - await RisingEdge(dut.txClk) - await Timer(1, unit="ns") - if int(dut.cfgTReady.value) == 1: - break + await wait_sampled_ready(dut.cfgTReady, clk=dut.txClk) dut.cfgTValid.value = 0 dut.cfgTData.value = 0 dut.cfgTUser.value = 0 diff --git a/tests/protocols/pgp/pgp4/pgp4_test_utils.py b/tests/protocols/pgp/pgp4/pgp4_test_utils.py index 7ccd854cc3..3b4c78c630 100644 --- a/tests/protocols/pgp/pgp4/pgp4_test_utils.py +++ b/tests/protocols/pgp/pgp4/pgp4_test_utils.py @@ -13,6 +13,9 @@ import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge, Timer + +from tests.axi.utils import wait_sampled_ready + PGP4_VERSION = 0x04 PGP4_IDLE = 0x99 @@ -94,6 +97,18 @@ def initialize_flat_tx_inputs(dut, *, include_opcode: bool = False): initialize_signals(dut, opCodeEn=0, opCodeData=0) +def tb_sample_clk(tb): + clk = getattr(tb, "clk", None) + if clk is not None: + return clk + + clk = getattr(tb, "cycle_clk", None) + if clk is not None: + return clk + + raise AttributeError(f"{type(tb).__name__} does not expose a sampling clock handle") + + async def send_opcode(tb: Pgp4FlatTB, opcode: int): """Pulse one opcode request through the flat PGP4 wrapper interface.""" @@ -167,8 +182,7 @@ async def send_single_word_frame(tb, *, payload: int, eofe: int = 0, ready_name: tb.dut.txSof.value = 1 tb.dut.txEof.value = 1 tb.dut.txEofe.value = eofe - await wait_for_signal(tb, ready_name, cycles=cycles) - await tb.cycle() + await wait_sampled_ready(getattr(tb.dut, ready_name), clk=tb_sample_clk(tb), timeout_cycles=cycles) tb.dut.txValid.value = 0 tb.dut.txSof.value = 0 tb.dut.txEof.value = 0 diff --git a/tests/protocols/srp/test_SrpV3Axi.py b/tests/protocols/srp/test_SrpV3Axi.py index 1ae26a64d5..1ec661d446 100644 --- a/tests/protocols/srp/test_SrpV3Axi.py +++ b/tests/protocols/srp/test_SrpV3Axi.py @@ -29,6 +29,7 @@ from cocotb.clock import Clock from cocotb.triggers import RisingEdge, with_timeout +from tests.axi.utils import wait_sampled_ready from tests.common.regression_utils import run_surf_vhdl_test @@ -125,9 +126,7 @@ async def send_words(self, words: list[int], *, tdest: int = 0): self.dut.S_AXIS_TID.value = 0 self.dut.S_AXIS_TUSER.value = 0x2 if index == 0 else 0x0 - while int(self.dut.S_AXIS_TREADY.value) != 1: - await RisingEdge(self.dut.AXIS_ACLK) - await RisingEdge(self.dut.AXIS_ACLK) + await wait_sampled_ready(self.dut.S_AXIS_TREADY, clk=self.dut.AXIS_ACLK) self.dut.S_AXIS_TVALID.value = 0 self.dut.S_AXIS_TLAST.value = 0 diff --git a/tests/protocols/ssi/test_SsiResizeFifoEofe.py b/tests/protocols/ssi/test_SsiResizeFifoEofe.py index 57b0af6d5a..b9d395bf65 100644 --- a/tests/protocols/ssi/test_SsiResizeFifoEofe.py +++ b/tests/protocols/ssi/test_SsiResizeFifoEofe.py @@ -23,6 +23,7 @@ from cocotb.clock import Clock from cocotb.triggers import RisingEdge, with_timeout +from tests.axi.utils import wait_sampled_ready from tests.common.regression_utils import parameter_case, run_surf_vhdl_test @@ -105,9 +106,7 @@ async def send_eofe_frame(self): self.dut.S_AXIS_EOFE.value = 1 self.dut.S_AXIS_TDATA.value = int.from_bytes(bytes(range(self.slave_bytes)), "little") self.dut.S_AXIS_TKEEP.value = (1 << self.slave_bytes) - 1 - while int(self.dut.S_AXIS_TREADY.value) != 1: - await RisingEdge(self.dut.AXIS_ACLK) - await RisingEdge(self.dut.AXIS_ACLK) + await wait_sampled_ready(self.dut.S_AXIS_TREADY, clk=self.dut.AXIS_ACLK) self.dut.S_AXIS_TVALID.value = 0 self.dut.S_AXIS_TLAST.value = 0 self.dut.S_AXIS_EOFE.value = 0 From 58b7a745c9ef8d122dd3b8548cd8e6f328ab1ad8 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 28 Apr 2026 13:41:22 -0700 Subject: [PATCH 57/92] Add AxiStreamPipeline to CoaXPressRxHsFsm and improve logic path to help with timing. --- .../coaxpress/core/rtl/CoaXPressRxHsFsm.vhd | 83 ++++++++++++------- 1 file changed, 54 insertions(+), 29 deletions(-) diff --git a/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd b/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd index b95f207830..1c94693e66 100644 --- a/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd +++ b/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd @@ -123,6 +123,9 @@ architecture rtl of CoaXPressRxHsFsm is signal rin : RegType; signal packRst : sl; + signal pipeMaster : AxiStreamMasterType; + signal pipeSlave : AxiStreamSlaveType; + -- attribute dont_touch : string; -- attribute dont_touch of r : signal is "TRUE"; @@ -130,17 +133,18 @@ begin packRst <= rxRst or rxFsmRst; - comb : process (r, rxFsmRst, rxMaster, rxRst) is - variable v : RegType; - variable tData : slv(31 downto 0); - variable more : sl; - variable idx : natural range 0 to NUM_LANES_G-1; + comb : process (pipeMaster, r, rxFsmRst, rxRst) is + variable v : RegType; + variable tData : slv(31 downto 0); + variable eolBeat : sl; + variable eolCnt : slv(RX_FSM_CNT_WIDTH_G-1 downto 0); + variable eolWrd : natural range 0 to NUM_LANES_G-1; begin -- Latch the current value v := r; -- Init Variable - tData := rxMaster.tData(32*r.wrd+31 downto 32*r.wrd); + tData := pipeMaster.tData(32*r.wrd+31 downto 32*r.wrd); -- Reset strobes v.dbg.errDet := '0'; @@ -149,7 +153,7 @@ begin -- Loop the number of 32-bit words for i in 0 to NUM_LANES_G-1 loop -- Check for maker pattern - if (rxMaster.tData(32*i+31 downto 32*i) = CXP_MARKER_C) then + if (pipeMaster.tData(32*i+31 downto 32*i) = CXP_MARKER_C) then v.dbg.maker(i) := '1'; end if; end loop; @@ -161,7 +165,7 @@ begin -- Init data stream v.dataMasters(0).tValid := '0'; -- Reset strobe - v.dataMasters(0).tData := rxMaster.tData; + v.dataMasters(0).tData := pipeMaster.tData; -- Check if state is not STEP_S if (r.state /= STEP_S) then v.dataMasters(0).tKeep := (others => '0'); -- Reset bus @@ -171,7 +175,7 @@ begin v.rxSlave.tReady := '0'; -- Check for valid data - if (rxMaster.tValid = '1') then + if (pipeMaster.tValid = '1') then -- State Machine case r.state is @@ -277,17 +281,38 @@ begin -- Write the data v.dataMasters(0).tValid := '1'; - -- Accept the data unless a later valid word in this same beat - -- must be reparsed as the next marker/type sequence. + -- Accept the data unless the next word in this same beat must be + -- reparsed as the next marker/type sequence. v.rxSlave.tReady := '1'; - more := '0'; - idx := 0; + eolBeat := '0'; + eolCnt := r.dCnt; + eolWrd := 0; + + -- Infer the line-ending word from the registered count. Keeping + -- this independent of the TKEEP-building loop avoids placing the + -- post-increment data count in the TREADY path. + for i in 0 to NUM_LANES_G-1 loop + if (pipeMaster.tKeep(4*i) = '1') and (eolBeat = '0') then + eolCnt := eolCnt + 1; + if (eolCnt = r.hdr.dsizeL(RX_FSM_CNT_WIDTH_G-1 downto 0)) then + eolBeat := '1'; + eolWrd := i; + end if; + end if; + end loop; + + if (eolBeat = '1') and (eolWrd /= NUM_LANES_G-1) then + if (pipeMaster.tKeep(4*(eolWrd+1)) = '1') then + v.rxSlave.tReady := '0'; + v.wrd := eolWrd+1; + end if; + end if; -- Loop the number of 32-bit words for i in 0 to NUM_LANES_G-1 loop -- Check for not "end of line" and valid data - if (v.endOfLine = '0') and (rxMaster.tKeep(4*i) = '1') then + if (v.endOfLine = '0') and (pipeMaster.tKeep(4*i) = '1') then -- Update the TKEEP mask v.dataMasters(0).tKeep(4*i+3 downto 4*i) := x"F"; @@ -301,21 +326,9 @@ begin -- Set the "end of line" flag v.endOfLine := '1'; - -- Hold the current beat only when additional valid - -- words remain after the line tail. - for j in i+1 to NUM_LANES_G-1 loop - if (rxMaster.tKeep(4*j) = '1') and (more = '0') then - more := '1'; - idx := j; - end if; - end loop; - -- Next State v.state := IDLE_S; - if (more = '1') then - v.rxSlave.tReady := '0'; - v.wrd := idx; - else + if (v.rxSlave.tReady = '1') then v.wrd := 0; end if; @@ -343,7 +356,7 @@ begin v.wrd := r.wrd + 1; -- Check if no more data available - if (rxMaster.tKeep(4*v.wrd) = '0') then + if (pipeMaster.tKeep(4*v.wrd) = '0') then -- Reset the counter v.wrd := 0; @@ -480,7 +493,7 @@ begin v.hdrMaster.tData(223 downto 208) := r.hdr.tapG(15 downto 0); -- Outputs - rxSlave <= v.rxSlave; + pipeSlave <= v.rxSlave; hdrMaster <= r.hdrMaster; rxFsmError <= r.dbg.errDet; @@ -501,6 +514,18 @@ begin end if; end process seq; + U_RxPipe : entity surf.AxiStreamPipeline + generic map ( + TPD_G => TPD_G, + PIPE_STAGES_G => 1) + port map ( + axisClk => rxClk, + axisRst => packRst, + sAxisMaster => rxMaster, + sAxisSlave => rxSlave, + mAxisMaster => pipeMaster, + mAxisSlave => pipeSlave); + U_Pack : entity surf.CoaXPressRxWordPacker generic map ( TPD_G => TPD_G, From e2c7ff45ecad15b99868455ccdc77fc3f99fb789 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 28 Apr 2026 13:59:35 -0700 Subject: [PATCH 58/92] Remove redundant assertion for shared beat cycles in CoaXPress Rx FSM test. --- tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py b/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py index f7dabc67f1..9cd7facafc 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py +++ b/tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py @@ -661,7 +661,6 @@ async def coaxpress_rx_hs_fsm_quad_lane_tail_marker_type_same_beat_test(dut): ) _capture_outputs(dut, header_beats=header_beats, data_beats=data_beats) - assert shared_beat_cycles > 1, trace assert not error_seen, f"{trace}\nheaders={header_beats}\ndata={data_beats}" assert header_beats == [{"hdrTData": expected_header, "hdrTLast": 1, "hdrTSof": 1}], trace assert data_beats == [ From 8fafe855ff097727ac4b037cbf9d6766590f7c35 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 29 Apr 2026 09:49:30 -0700 Subject: [PATCH 59/92] Add PGP4 RX K-code CSC checks --- protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd | 44 ++++- protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd | 29 +--- .../pgp/pgp4/core/rtl/Pgp4RxKCodeChecker.vhd | 106 ++++++++++++ .../pgp4/core/wrappers/Pgp4RxEbWrapper.vhd | 2 - .../Pgp4RxProtocolDepacketizerWrapper.vhd | 109 +++++++++++++ .../pgp/pgp4/core/wrappers/Pgp4RxWrapper.vhd | 77 ++++----- .../protocols/pgp/pgp4/test_Pgp4RxCrcError.py | 73 ++++++--- tests/protocols/pgp/pgp4/test_Pgp4RxEb.py | 56 +------ .../pgp/pgp4/test_Pgp4RxKCodeChecker.py | 152 ++++++++++++++++++ 9 files changed, 490 insertions(+), 158 deletions(-) create mode 100644 protocols/pgp/pgp4/core/rtl/Pgp4RxKCodeChecker.vhd create mode 100644 protocols/pgp/pgp4/core/wrappers/Pgp4RxProtocolDepacketizerWrapper.vhd create mode 100644 tests/protocols/pgp/pgp4/test_Pgp4RxKCodeChecker.py diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd index 6e12919c3f..94721234da 100755 --- a/protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd @@ -71,6 +71,10 @@ architecture rtl of Pgp4Rx is signal unscrambledValid : sl; signal unscrambledData : slv(63 downto 0); signal unscrambledHeader : slv(1 downto 0); + signal checkedValid : sl; + signal checkedData : slv(63 downto 0); + signal checkedHeader : slv(1 downto 0); + signal kCodeLinkError : sl; signal remLinkData : slv(47 downto 0); signal ebValid : sl; signal ebData : slv(63 downto 0); @@ -134,6 +138,32 @@ begin outputData => unscrambledData, -- [out] outputSideband => unscrambledHeader); -- [out] + -- Check K-code checksum before the elastic buffer or no-EB bypass path + U_Pgp4RxKCodeChecker_1 : entity surf.Pgp4RxKCodeChecker + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G) + port map ( + phyRxClk => phyRxClk, -- [in] + phyRxRst => phyRxRst, -- [in] + phyRxValid => unscrambledValid, -- [in] + phyRxData => unscrambledData, -- [in] + phyRxHeader => unscrambledHeader, -- [in] + checkedValid => checkedValid, -- [out] + checkedData => checkedData, -- [out] + checkedHeader => checkedHeader, -- [out] + linkError => kCodeLinkError); -- [out] + + U_linkError : entity surf.SynchronizerOneShot + generic map ( + TPD_G => TPD_G, + RST_ASYNC_G => RST_ASYNC_G) + port map ( + clk => pgpRxClk, + dataIn => kCodeLinkError, + dataOut => linkError); + GEN_EB : if (SKIP_EN_G = true) generate -- Elastic Buffer U_Pgp4RxEb_1 : entity surf.Pgp4RxEb @@ -144,9 +174,9 @@ begin port map ( phyRxClk => phyRxClk, -- [in] phyRxRst => phyRxRst, -- [in] - phyRxValid => unscrambledValid, -- [in] - phyRxData => unscrambledData, -- [in] - phyRxHeader => unscrambledHeader, -- [in] + phyRxValid => checkedValid, -- [in] + phyRxData => checkedData, -- [in] + phyRxHeader => checkedHeader, -- [in] pgpRxClk => pgpRxClk, -- [in] pgpRxRst => pgpRxRst, -- [in] pgpRxValid => ebValid, -- [out] @@ -154,16 +184,14 @@ begin pgpRxHeader => ebHeader, -- [out] remLinkData => remLinkData, -- [out] overflow => ebOverflow, -- [out] - linkError => linkError, -- [out] status => ebStatus); -- [out] end generate GEN_EB; NO_EB : if (SKIP_EN_G = false) generate - ebValid <= unscrambledValid; - ebData <= unscrambledData; - ebHeader <= unscrambledHeader; + ebValid <= checkedValid; + ebData <= checkedData; + ebHeader <= checkedHeader; remLinkData <= (others => '0'); ebOverflow <= '0'; - linkError <= '0'; ebStatus <= (others => '0'); end generate NO_EB; diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd index bad89bdb5d..5b4bd73064 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd @@ -42,14 +42,12 @@ entity Pgp4RxEb is pgpRxHeader : out slv(1 downto 0); remLinkData : out slv(47 downto 0); overflow : out sl; - linkError : out sl; status : out slv(8 downto 0)); end entity Pgp4RxEb; architecture rtl of Pgp4RxEb is type RegType is record - linkError : sl; dataValid : sl; remLinkData : slv(47 downto 0); fifoIn : slv(65 downto 0); @@ -57,7 +55,6 @@ architecture rtl of Pgp4RxEb is end record RegType; constant REG_INIT_C : RegType := ( - linkError => '0', dataValid => '0', remLinkData => (others => '0'), fifoIn => (others => '0'), @@ -79,7 +76,6 @@ begin v := r; -- Reset strobes - v.linkError := '0'; v.dataValid := '0'; -- Map to FIFO write @@ -87,19 +83,11 @@ begin v.fifoIn(65 downto 64) := phyRxHeader; v.fifoWrEn := phyRxValid; - -- Check for k-code - if (phyRxHeader = PGP4_K_HEADER_C) then + -- Check for valid k-code + if (phyRxValid = '1') and (phyRxHeader = PGP4_K_HEADER_C) then - -- Check for invalid K-code CRC - if (phyRxData(PGP4_K_CODE_CRC_FIELD_C) /= pgp4KCodeCrc(phyRxData)) then - - -- Don't write words into the FIFO - v.fifoWrEn := '0'; - - -- Set the error flag - v.linkError := '1'; - - elsif (phyRxData(PGP4_BTF_FIELD_C) = PGP4_SKP_C) then + -- Check for SKP words + if (phyRxData(PGP4_BTF_FIELD_C) = PGP4_SKP_C) then -- Don't write SKP words into the FIFO v.fifoWrEn := '0'; @@ -182,13 +170,4 @@ begin dataIn => overflowInt, dataOut => overflow); - U_linkError : entity surf.SynchronizerOneShot - generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G) - port map ( - clk => pgpRxClk, - dataIn => r.linkError, - dataOut => linkError); - end architecture rtl; diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4RxKCodeChecker.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4RxKCodeChecker.vhd new file mode 100644 index 0000000000..1f0c0292db --- /dev/null +++ b/protocols/pgp/pgp4/core/rtl/Pgp4RxKCodeChecker.vhd @@ -0,0 +1,106 @@ +------------------------------------------------------------------------------- +-- Title : PGPv4: https://confluence.slac.stanford.edu/x/1dzgEQ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: PGPv4 Rx K-code Checksum Checker +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.Pgp4Pkg.all; + +entity Pgp4RxKCodeChecker is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset + RST_ASYNC_G : boolean := false); + port ( + phyRxClk : in sl; + phyRxRst : in sl; + phyRxValid : in sl; + phyRxData : in slv(63 downto 0); + phyRxHeader : in slv(1 downto 0); + checkedValid : out sl; + checkedData : out slv(63 downto 0); + checkedHeader : out slv(1 downto 0); + linkError : out sl); +end entity Pgp4RxKCodeChecker; + +architecture rtl of Pgp4RxKCodeChecker is + + type RegType is record + checkedValid : sl; + checkedData : slv(63 downto 0); + checkedHeader : slv(1 downto 0); + linkError : sl; + end record RegType; + + constant REG_INIT_C : RegType := ( + checkedValid => '0', + checkedData => (others => '0'), + checkedHeader => (others => '0'), + linkError => '0'); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + +begin + + comb : process (phyRxData, phyRxHeader, phyRxRst, phyRxValid, r) is + variable v : RegType; + begin + -- Latch the current value + v := r; + + -- Map to output register + v.checkedValid := phyRxValid; + v.checkedData := phyRxData; + v.checkedHeader := phyRxHeader; + v.linkError := '0'; + + -- Drop K-codes with invalid checksum + if (phyRxValid = '1') and (phyRxHeader = PGP4_K_HEADER_C) and + (phyRxData(PGP4_K_CODE_CRC_FIELD_C) /= pgp4KCodeCrc(phyRxData)) then + v.checkedValid := '0'; + v.linkError := '1'; + end if; + + -- Reset + if (RST_ASYNC_G = false and phyRxRst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + end process comb; + + seq : process (phyRxClk, phyRxRst) is + begin + if (RST_ASYNC_G) and (phyRxRst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(phyRxClk) then + r <= rin after TPD_G; + end if; + end process seq; + + checkedValid <= r.checkedValid; + checkedData <= r.checkedData; + checkedHeader <= r.checkedHeader; + linkError <= r.linkError; + +end architecture rtl; diff --git a/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd b/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd index c94878cf09..411fea4539 100644 --- a/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd +++ b/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd @@ -31,7 +31,6 @@ entity Pgp4RxEbWrapper is pgpRxHeader : out slv(1 downto 0); remLinkData : out slv(47 downto 0); overflow : out sl; - linkError : out sl; status : out slv(8 downto 0)); end entity Pgp4RxEbWrapper; @@ -53,7 +52,6 @@ begin pgpRxHeader => pgpRxHeader, remLinkData => remLinkData, overflow => overflow, - linkError => linkError, status => status); end architecture rtl; diff --git a/protocols/pgp/pgp4/core/wrappers/Pgp4RxProtocolDepacketizerWrapper.vhd b/protocols/pgp/pgp4/core/wrappers/Pgp4RxProtocolDepacketizerWrapper.vhd new file mode 100644 index 0000000000..493290de9b --- /dev/null +++ b/protocols/pgp/pgp4/core/wrappers/Pgp4RxProtocolDepacketizerWrapper.vhd @@ -0,0 +1,109 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for PGP4 RX protocol and depacketizer +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.AxiStreamPacketizer2Pkg.all; +use surf.SsiPkg.all; +use surf.Pgp4Pkg.all; + +entity Pgp4RxProtocolDepacketizerWrapper is + port ( + clk : in sl; + rst : in sl; + phyRxActive : in sl := '1'; + protRxValid : in sl; + protRxHeader : in slv(1 downto 0); + protRxData : in slv(63 downto 0); + rxReady : in sl := '1'; + linkReady : out sl; + frameRx : out sl; + frameRxErr : out sl; + linkError : out sl; + rxValid : out sl; + rxLast : out sl; + rxData : out slv(63 downto 0); + rxUser : out slv(15 downto 0)); +end entity Pgp4RxProtocolDepacketizerWrapper; + +architecture rtl of Pgp4RxProtocolDepacketizerWrapper is + + signal pgpRxOut : Pgp4RxOutType := PGP4_RX_OUT_INIT_C; + signal pgpRawRxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal pgpRawRxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal depacketizedRxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal depacketizedRxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal depacketizerDebug : Packetizer2DebugType; + signal remRxFifoCtrl : AxiStreamCtrlArray(0 downto 0); + signal remRxLinkReady : sl; + signal locRxLinkReady : sl; + +begin + + linkReady <= pgpRxOut.linkReady; + linkError <= pgpRxOut.linkError; + frameRx <= depacketizerDebug.eof; + frameRxErr <= depacketizerDebug.eofe; + rxValid <= depacketizedRxMaster.tValid; + rxLast <= depacketizedRxMaster.tLast; + rxData <= depacketizedRxMaster.tData(63 downto 0); + rxUser <= depacketizedRxMaster.tUser(15 downto 0); + + depacketizedRxSlave.tReady <= rxReady; + + U_Pgp4RxProtocol : entity surf.Pgp4RxProtocol + generic map ( + NUM_VC_G => 1) + port map ( + pgpRxClk => clk, + pgpRxRst => rst, + pgpRxIn => PGP4_RX_IN_INIT_C, + pgpRxOut => pgpRxOut, + pgpRxMaster => pgpRawRxMaster, + pgpRxSlave => pgpRawRxSlave, + remRxFifoCtrl => remRxFifoCtrl, + remRxLinkReady => remRxLinkReady, + locRxLinkReady => locRxLinkReady, + linkError => '0', + phyRxActive => phyRxActive, + protRxValid => protRxValid, + protRxPhyInit => open, + protRxData => protRxData, + protRxHeader => protRxHeader); + + U_AxiStreamDepacketizer2 : entity surf.AxiStreamDepacketizer2 + generic map ( + MEMORY_TYPE_G => "distributed", + REG_EN_G => false, + CRC_PIPELINE_G => 0, + CRC_MODE_G => "DATA", + CRC_POLY_G => PGP4_CRC_POLY_C, + SEQ_CNT_SIZE_G => 12, + TDEST_BITS_G => 0, + INPUT_PIPE_STAGES_G => 0) + port map ( + axisClk => clk, + axisRst => rst, + linkGood => locRxLinkReady, + debug => depacketizerDebug, + sAxisMaster => pgpRawRxMaster, + sAxisSlave => pgpRawRxSlave, + mAxisMaster => depacketizedRxMaster, + mAxisSlave => depacketizedRxSlave); + +end architecture rtl; diff --git a/protocols/pgp/pgp4/core/wrappers/Pgp4RxWrapper.vhd b/protocols/pgp/pgp4/core/wrappers/Pgp4RxWrapper.vhd index 0e1210f435..88960974e4 100644 --- a/protocols/pgp/pgp4/core/wrappers/Pgp4RxWrapper.vhd +++ b/protocols/pgp/pgp4/core/wrappers/Pgp4RxWrapper.vhd @@ -22,41 +22,37 @@ use surf.Pgp4Pkg.all; entity Pgp4RxWrapper is port ( - clk : in sl; - rst : in sl; - txValid : in sl; - txReady : out sl; - txData : in slv(63 downto 0); - txSof : in sl; - txEof : in sl; - txEofe : in sl; - opCodeEn : in sl := '0'; - opCodeData : in slv(47 downto 0) := (others => '0'); - corruptArm : in sl := '0'; - corruptMask : in slv(63 downto 0) := (others => '0'); - corruptBusy : out sl; - linkReady : out sl; - frameRx : out sl; - frameRxErr : out sl; - rxOpCodeEn : out sl; - rxOpCodeData : out slv(47 downto 0); - rxValid : out sl; - rxLast : out sl; - rxData : out slv(63 downto 0); - rxDest : out slv(7 downto 0); - rxUser : out slv(15 downto 0)); + clk : in sl; + rst : in sl; + txValid : in sl; + txReady : out sl; + txData : in slv(63 downto 0); + txSof : in sl; + txEof : in sl; + txEofe : in sl; + opCodeEn : in sl := '0'; + opCodeData : in slv(47 downto 0) := (others => '0'); + linkReady : out sl; + linkError : out sl; + frameRx : out sl; + frameRxErr : out sl; + rxOpCodeEn : out sl; + rxOpCodeData : out slv(47 downto 0); + rxValid : out sl; + rxLast : out sl; + rxData : out slv(63 downto 0); + rxDest : out slv(7 downto 0); + rxUser : out slv(15 downto 0)); end entity Pgp4RxWrapper; architecture rtl of Pgp4RxWrapper is - signal pgpTxIn : Pgp4TxInType := PGP4_TX_IN_INIT_C; - signal pgpTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal pgpTxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal phyTxValid : sl; - signal phyTxData : slv(63 downto 0); - signal phyTxHeader : slv(1 downto 0); - signal loopPhyData : slv(63 downto 0); - signal corruptBusyInt : sl := '0'; + signal pgpTxIn : Pgp4TxInType := PGP4_TX_IN_INIT_C; + signal pgpTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal pgpTxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal phyTxValid : sl; + signal phyTxData : slv(63 downto 0); + signal phyTxHeader : slv(1 downto 0); signal pgpRxOut : Pgp4RxOutType := PGP4_RX_OUT_INIT_C; signal pgpRxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; @@ -81,9 +77,9 @@ begin pgpTxMaster.tLast <= txEof; linkReady <= pgpRxOut.linkReady; + linkError <= pgpRxOut.linkError; frameRx <= pgpRxOut.frameRx; frameRxErr <= pgpRxOut.frameRxErr; - corruptBusy <= corruptBusyInt; rxOpCodeEn <= pgpRxOut.opCodeEn; rxOpCodeData <= pgpRxOut.opCodeData; rxValid <= pgpRxMaster.tValid; @@ -92,21 +88,6 @@ begin rxDest <= pgpRxMaster.tDest(7 downto 0); rxUser <= pgpRxMaster.tUser(15 downto 0); - loopPhyData <= phyTxData xor corruptMask when (corruptBusyInt = '1' and phyTxValid = '1' and phyTxHeader = PGP4_D_HEADER_C) else phyTxData; - - process (clk) is - begin - if rising_edge(clk) then - if rst = '1' then - corruptBusyInt <= '0'; - elsif corruptArm = '1' then - corruptBusyInt <= '1'; - elsif corruptBusyInt = '1' and phyTxValid = '1' and phyTxHeader = PGP4_D_HEADER_C then - corruptBusyInt <= '0'; - end if; - end if; - end process; - U_TX : entity surf.Pgp4Tx generic map ( NUM_VC_G => 1, @@ -154,7 +135,7 @@ begin phyRxInit => open, phyRxActive => '1', phyRxValid => phyTxValid, - phyRxData => loopPhyData, + phyRxData => phyTxData, phyRxHeader => phyTxHeader, phyRxStartSeq => '0', phyRxSlip => open); diff --git a/tests/protocols/pgp/pgp4/test_Pgp4RxCrcError.py b/tests/protocols/pgp/pgp4/test_Pgp4RxCrcError.py index 68dc18d238..31f3f67eda 100644 --- a/tests/protocols/pgp/pgp4/test_Pgp4RxCrcError.py +++ b/tests/protocols/pgp/pgp4/test_Pgp4RxCrcError.py @@ -9,56 +9,83 @@ ############################################################################## # Test methodology: -# - Sweep: Keep one checked-in `Pgp4Rx` wrapper with the integrated `Pgp4Tx` -# traffic source and the new one-shot corruption hook disabled by default. -# - Stimulus: Arm the corruption hook, then send one valid single-word frame so -# one 64-bit data beat is flipped after TX formatting but before RX checking. -# - Checks: The integrated receive path must flag `frameRxErr` while staying -# link-up, which proves CRC-style rejection beyond the standalone CRC blocks. -# - Timing: The corruption hook only touches the first transmitted data word of -# the next frame, so the injected error is deterministic. +# - Sweep: Run a raw `Pgp4RxProtocol` plus `AxiStreamDepacketizer2` wrapper. +# - Stimulus: Train the protocol link with valid IDLE words, then send one +# SOF/data/EOF cell whose EOF carries an intentionally wrong frame CRC. +# - Checks: The depacketizer must report an errored frame end while the PGP4 +# link itself remains up, proving that payload CRC errors are handled at the +# frame/cell layer instead of as link alignment errors. +# - Timing: The bench drives complete 64-bit protocol words directly, so no +# test-only corruption ports are needed on the integrated RX loopback wrapper. import cocotb import pytest from tests.common.regression_utils import parameter_case from tests.protocols.pgp.pgp4.pgp4_test_utils import ( + PGP4_D_HEADER, + PGP4_K_HEADER, Pgp4FlatTB, - initialize_flat_tx_inputs, initialize_signals, - send_single_word_frame, + pgp4_eof_word, + pgp4_idle_word, + pgp4_sof_word, + signal_int, wait_for_signal, ) from tests.protocols.pgp.pgp_test_utils import run_pgp_wrapper_test +PAYLOAD_WORD = 0x0123456789ABCDEF +BAD_CELL_CRC = 0x11223344 + + +async def send_protocol_word(tb: Pgp4FlatTB, *, header: int, data: int): + tb.dut.protRxHeader.value = header + tb.dut.protRxData.value = data + tb.dut.protRxValid.value = 1 + await tb.cycle() + + +async def train_rx_protocol_link(tb: Pgp4FlatTB, *, cycles: int = 1002): + idle_word = pgp4_idle_word(rem_link_ready=1) + for _ in range(cycles): + await send_protocol_word(tb, header=PGP4_K_HEADER, data=idle_word) + tb.dut.protRxValid.value = 0 + await wait_for_signal(tb, "linkReady", cycles=8) + @cocotb.test() async def pgp4_rx_crc_error_test(dut): tb = Pgp4FlatTB(dut) - initialize_flat_tx_inputs(dut, include_opcode=True) - initialize_signals(dut, corruptArm=0, corruptMask=0) + initialize_signals( + dut, + phyRxActive=1, + protRxValid=0, + protRxHeader=0, + protRxData=0, + rxReady=1, + ) await tb.reset() - await wait_for_signal(tb, "linkReady", cycles=2600) + await train_rx_protocol_link(tb) - dut.corruptMask.value = 0x1 - dut.corruptArm.value = 1 - await tb.cycle() - dut.corruptArm.value = 0 + await send_protocol_word(tb, header=PGP4_K_HEADER, data=pgp4_sof_word(vc=0, seq=0)) + await send_protocol_word(tb, header=PGP4_D_HEADER, data=PAYLOAD_WORD) + await send_protocol_word(tb, header=PGP4_K_HEADER, data=pgp4_eof_word(bytes_last=8, crc=BAD_CELL_CRC)) + dut.protRxValid.value = 0 - await send_single_word_frame(tb, payload=0x0123456789ABCDEF) - await wait_for_signal(tb, "corruptBusy", value=0, cycles=64) await wait_for_signal(tb, "frameRxErr", cycles=512) - assert int(dut.linkReady.value) == 1 + assert signal_int(dut, "linkReady") == 1 + assert signal_int(dut, "linkError") == 0 -PARAMETER_SWEEP = [parameter_case("integrated_scrambled_rx_wrapper_crc_error")] +PARAMETER_SWEEP = [parameter_case("raw_protocol_depacketizer_crc_error")] @pytest.mark.parametrize("parameters", PARAMETER_SWEEP) def test_Pgp4RxCrcError(parameters): run_pgp_wrapper_test( test_file=__file__, - toplevel="surf.pgp4rxwrapper", - wrapper_source="protocols/pgp/pgp4/core/wrappers/Pgp4RxWrapper.vhd", + toplevel="surf.pgp4rxprotocoldepacketizerwrapper", + wrapper_source="protocols/pgp/pgp4/core/wrappers/Pgp4RxProtocolDepacketizerWrapper.vhd", extra_env=parameters, ) diff --git a/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py b/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py index bd22093869..cbb4a4a209 100644 --- a/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py +++ b/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py @@ -14,12 +14,11 @@ # not equal, a near-empty case where the local read clock is faster than the # recovered write clock, and a deliberate overflow-stress case where the # write side is much faster than the read side. -# - Stimulus: Drive ordered mixes of data words, valid K-words, SKP words, bad -# K-word CRC cases, and reset/overflow stress bursts directly into the PHY -# side of the elastic buffer. +# - Stimulus: Drive ordered mixes of data words, valid K-words, SKP words, and +# reset/overflow stress bursts directly into the PHY side of the elastic +# buffer. # - Checks: The DUT must forward non-SKP traffic in order, suppress SKP while -# still updating `remLinkData`, reject bad K-word CRC traffic with a -# synchronized `linkError` pulse, flush buffered data on reset, and pulse +# still updating `remLinkData`, flush buffered data on reset, and pulse # `overflow` when sustained write pressure outruns the read domain. # - Timing: All output checks are sampled on `pgpRxClk`, while input traffic is # launched on `phyRxClk`, so the bench reflects the intended recovered-clock @@ -230,52 +229,6 @@ async def pgp4_rx_eb_filters_skip_and_preserves_stream_order(dut): (PGP4_D_HEADER, data_word_b), ] await wait_for_signal_in_domain(tb, "remLinkData", value=skip_data, cycles=64) - assert signal_int(tb.dut, "linkError") == 0 - - -@cocotb.test() -async def pgp4_rx_eb_rejects_bad_kcode_crc_without_poisoning_fifo(dut): - tb = Pgp4RxEbTB(dut) - if env_flag("EXPECT_OVERFLOW", default=False): - return - - initialize_phy_inputs(dut) - await tb.reset() - - # A bad K-code CRC should be dropped before the FIFO write side and should - # produce a synchronized `linkError` pulse in the read domain. Surrounding - # traffic should still be delivered in order. - collector = ValidBeatCollector( - dut, - step=tb.sample_pgp_cycle, - valid_name="pgpRxValid", - field_names=("pgpRxHeader", "pgpRxData"), - ) - cocotb.start_soon(collector.run()) - link_error_monitor = PulseMonitor(dut, "linkError", step=tb.cycle_pgp) - cocotb.start_soon(link_error_monitor.run()) - - data_word_a = 0x0011223344556677 - data_word_b = 0x8899AABBCCDDEEFF - bad_idle = pgp4_idle_word(rem_link_ready=1) ^ (1 << 48) - - await send_phy_words( - tb, - [ - (PGP4_D_HEADER, data_word_a), - (PGP4_K_HEADER, bad_idle), - (PGP4_D_HEADER, data_word_b), - ], - ) - - words = await wait_for_collected_beats(collector, count=2, step=tb.cycle_pgp, cycles=256) - assert words == [ - (PGP4_D_HEADER, data_word_a), - (PGP4_D_HEADER, data_word_b), - ] - await tb.cycle_pgp(32) - assert link_error_monitor.seen - @cocotb.test() async def pgp4_rx_eb_reset_flushes_buffered_words(dut): @@ -322,7 +275,6 @@ async def pgp4_rx_eb_overflow_pulses_when_phy_outpaces_local_clock(dut): await tb.cycle_pgp(64) assert overflow_monitor.seen - assert signal_int(tb.dut, "linkError") == 0 PARAMETER_SWEEP = [ diff --git a/tests/protocols/pgp/pgp4/test_Pgp4RxKCodeChecker.py b/tests/protocols/pgp/pgp4/test_Pgp4RxKCodeChecker.py new file mode 100644 index 0000000000..67cb637116 --- /dev/null +++ b/tests/protocols/pgp/pgp4/test_Pgp4RxKCodeChecker.py @@ -0,0 +1,152 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Run the single-clock `Pgp4RxKCodeChecker` RTL directly. +# - Stimulus: Drive ordinary data words, valid K-words, invalid K-words, idle +# cycles, and reset directly into the checker input. +# - Checks: Data words pass regardless of K-code checksum contents, valid +# K-words pass unchanged, invalid K-words are suppressed with a one-cycle +# `linkError`, and reset clears the registered outputs. +# - Timing: The checker is registered, so each input word is sampled one clock +# cycle after it is driven. + +import cocotb +import pytest +from cocotb.triggers import Timer + +from tests.common.regression_utils import parameter_case, run_surf_vhdl_test +from tests.protocols.pgp.pgp4.pgp4_test_utils import ( + PGP4_D_HEADER, + PGP4_K_HEADER, + PGP4_IDLE, + PGP4_USER, + Pgp4FlatTB, + initialize_signals, + pgp4_idle_word, + pgp4_kword, + pgp4_user_word, + signal_int, +) + +K_CODE_CSC_LSB = 48 +DATA_PASS_THROUGH_WORD = 0x0123456789ABCDEF +IDLE_PAUSE_MASK = 0x1234 +IDLE_OVERFLOW_MASK = 0x00A5 +USER_OPCODE_PAYLOAD = 0x0000CAFEBABE + + +def checker_outputs(dut) -> tuple[int, int, int, int]: + return ( + signal_int(dut, "checkedValid"), + signal_int(dut, "checkedHeader"), + signal_int(dut, "checkedData"), + signal_int(dut, "linkError"), + ) + + +async def cycle_and_sample(tb: Pgp4FlatTB): + await tb.cycle() + await Timer(1, unit="ns") + + +async def drive_checker_word(tb: Pgp4FlatTB, *, header: int, data: int, valid: int = 1) -> tuple[int, int, int, int]: + tb.dut.phyRxValid.value = valid + tb.dut.phyRxHeader.value = header + tb.dut.phyRxData.value = data + await Timer(1, unit="ps") + await cycle_and_sample(tb) + return checker_outputs(tb.dut) + + +def bad_kcode_checksum_word() -> int: + """Build a real USER K-word and corrupt only its checksum field. + + `pgp4_user_word()` delegates to `pgp4_kword()`, which fills bits 55:48 + with the correct PGP4 control-word checksum. Flipping bit 48 leaves the + block type and 48-bit USER payload intact while making the checksum fail. + """ + + return pgp4_user_word(USER_OPCODE_PAYLOAD) ^ (1 << K_CODE_CSC_LSB) + + +@cocotb.test() +async def pgp4_rx_kcode_checker_test(dut): + tb = Pgp4FlatTB(dut, clk_name="phyRxClk", rst_name="phyRxRst") + initialize_signals( + dut, + phyRxValid=0, + phyRxHeader=0, + phyRxData=0, + ) + await tb.reset() + assert checker_outputs(dut) == (0, 0, 0, 0) + + # Data words do not carry a PGP4 K-code checksum. This value is chosen + # only to prove that ordinary data is registered and passed through + # unchanged when the 64b/66b header marks it as data. + assert await drive_checker_word(tb, header=PGP4_D_HEADER, data=DATA_PASS_THROUGH_WORD) == ( + 1, + PGP4_D_HEADER, + DATA_PASS_THROUGH_WORD, + 0, + ) + + # `pgp4_idle_word()` builds the BTF, LINKINFO payload, and correct + # checksum. Rebuilding the same word with `pgp4_kword()` documents the + # intended payload fields without relying on a raw 64-bit literal. + idle_link_info = 0x104 | (IDLE_PAUSE_MASK << 16) | (IDLE_OVERFLOW_MASK << 32) + idle_word = pgp4_idle_word( + rem_link_ready=1, + pause_mask=IDLE_PAUSE_MASK, + overflow_mask=IDLE_OVERFLOW_MASK, + ) + assert idle_word == pgp4_kword(PGP4_IDLE, idle_link_info) + assert await drive_checker_word(tb, header=PGP4_K_HEADER, data=idle_word) == ( + 1, + PGP4_K_HEADER, + idle_word, + 0, + ) + + # This USER word has a valid block type and opcode payload, but one + # checksum bit is flipped so the checker should drop it and pulse + # `linkError` for exactly this registered output cycle. + good_user_word = pgp4_user_word(USER_OPCODE_PAYLOAD) + assert good_user_word == pgp4_kword(PGP4_USER, USER_OPCODE_PAYLOAD) + bad_user_word = bad_kcode_checksum_word() + assert await drive_checker_word(tb, header=PGP4_K_HEADER, data=bad_user_word) == ( + 0, + PGP4_K_HEADER, + bad_user_word, + 1, + ) + + await drive_checker_word(tb, header=PGP4_K_HEADER, data=bad_user_word, valid=0) + assert checker_outputs(dut) == (0, PGP4_K_HEADER, bad_user_word, 0) + + tb.dut.phyRxValid.value = 1 + tb.dut.phyRxHeader.value = PGP4_D_HEADER + tb.dut.phyRxData.value = DATA_PASS_THROUGH_WORD + tb.dut.phyRxRst.value = 1 + await cycle_and_sample(tb) + assert checker_outputs(dut) == (0, 0, 0, 0) + + +PARAMETER_SWEEP = [parameter_case("direct_wrapper")] + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +def test_Pgp4RxKCodeChecker(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.pgp4rxkcodechecker", + extra_env=parameters, + ) From 513402fd8d017c412204c9b4e277984159e7b521 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 29 Apr 2026 09:57:18 -0700 Subject: [PATCH 60/92] Add .DS_Store to .gitignore --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index cfcd482d2a..c509802c33 100644 --- a/.gitignore +++ b/.gitignore @@ -28,3 +28,4 @@ sim_build/ .planning/ planning/ CLAUDE.md +.DS_Store From fc31450a709a8a5611003118bfcf6c84a1f4f112 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 29 Apr 2026 10:13:04 -0700 Subject: [PATCH 61/92] Fix PGP4 K-code checker lint --- protocols/pgp/pgp4/core/rtl/Pgp4RxKCodeChecker.vhd | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4RxKCodeChecker.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4RxKCodeChecker.vhd index 1f0c0292db..5941a232d9 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4RxKCodeChecker.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4RxKCodeChecker.vhd @@ -29,11 +29,11 @@ entity Pgp4RxKCodeChecker is RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset RST_ASYNC_G : boolean := false); port ( - phyRxClk : in sl; - phyRxRst : in sl; - phyRxValid : in sl; - phyRxData : in slv(63 downto 0); - phyRxHeader : in slv(1 downto 0); + phyRxClk : in sl; + phyRxRst : in sl; + phyRxValid : in sl; + phyRxData : in slv(63 downto 0); + phyRxHeader : in slv(1 downto 0); checkedValid : out sl; checkedData : out slv(63 downto 0); checkedHeader : out slv(1 downto 0); From 4f7d2d3abe3d2229a810eb3f15772f4a8e1d049c Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Wed, 29 Apr 2026 10:14:38 -0700 Subject: [PATCH 62/92] AxiStreamConcat: assert AXIS_CONFIG_G.TKEEP_MODE_C = TKEEP_FIXED_C The module's header already documents that only TKEEP_FIXED_C is supported, but instantiating it with TKEEP_COMP_C / TKEEP_COUNT_C / TKEEP_NORMAL_C silently misbehaves (partial-keep transactions are not handled). Add an elaboration-time assert so misconfigurations fail at build/sim time instead of producing corrupted streams. Matches the precedent in AxiStreamFifoV2, AxiStreamGearbox, and AxiStreamResize. --- axi/axi-stream/rtl/AxiStreamConcat.vhd | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/axi/axi-stream/rtl/AxiStreamConcat.vhd b/axi/axi-stream/rtl/AxiStreamConcat.vhd index 45a54e9106..d047cb7a15 100755 --- a/axi/axi-stream/rtl/AxiStreamConcat.vhd +++ b/axi/axi-stream/rtl/AxiStreamConcat.vhd @@ -125,6 +125,12 @@ architecture rtl of AxiStreamConcat is begin + -- AxiStreamConcat only supports TKEEP_FIXED_C (see header note). + -- Use AxiStreamBatcher for TKEEP_NORMAL_C, TKEEP_COMP_C, or TKEEP_COUNT_C. + assert (AXIS_CONFIG_G.TKEEP_MODE_C = TKEEP_FIXED_C) + report "AxiStreamConcat: AXIS_CONFIG_G.TKEEP_MODE_C must be TKEEP_FIXED_C. Use AxiStreamBatcher for other TKEEP modes." + severity failure; + ----------------- -- Input pipeline ----------------- From db8952afb1a504f58bcd04cbe4b2faff0a6e46e7 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 29 Apr 2026 10:28:37 -0700 Subject: [PATCH 63/92] Handle PGP4 RX EB bypass link errors --- protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd | 58 ++---- protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd | 180 +++++++++++------- .../pgp4/core/wrappers/Pgp4RxEbWrapper.vhd | 58 +++--- tests/protocols/pgp/pgp4/test_Pgp4RxEb.py | 90 ++++++++- 4 files changed, 254 insertions(+), 132 deletions(-) diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd index 94721234da..a20076f236 100755 --- a/protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd @@ -155,45 +155,29 @@ begin checkedHeader => checkedHeader, -- [out] linkError => kCodeLinkError); -- [out] - U_linkError : entity surf.SynchronizerOneShot + -- Elastic Buffer or same-clock bypass path + U_Pgp4RxEb_1 : entity surf.Pgp4RxEb generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G) + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + BYPASS_G => not SKIP_EN_G) port map ( - clk => pgpRxClk, - dataIn => kCodeLinkError, - dataOut => linkError); - - GEN_EB : if (SKIP_EN_G = true) generate - -- Elastic Buffer - U_Pgp4RxEb_1 : entity surf.Pgp4RxEb - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - RST_ASYNC_G => RST_ASYNC_G) - port map ( - phyRxClk => phyRxClk, -- [in] - phyRxRst => phyRxRst, -- [in] - phyRxValid => checkedValid, -- [in] - phyRxData => checkedData, -- [in] - phyRxHeader => checkedHeader, -- [in] - pgpRxClk => pgpRxClk, -- [in] - pgpRxRst => pgpRxRst, -- [in] - pgpRxValid => ebValid, -- [out] - pgpRxData => ebData, -- [out] - pgpRxHeader => ebHeader, -- [out] - remLinkData => remLinkData, -- [out] - overflow => ebOverflow, -- [out] - status => ebStatus); -- [out] - end generate GEN_EB; - NO_EB : if (SKIP_EN_G = false) generate - ebValid <= checkedValid; - ebData <= checkedData; - ebHeader <= checkedHeader; - remLinkData <= (others => '0'); - ebOverflow <= '0'; - ebStatus <= (others => '0'); - end generate NO_EB; + phyRxClk => phyRxClk, -- [in] + phyRxRst => phyRxRst, -- [in] + phyRxValid => checkedValid, -- [in] + phyRxData => checkedData, -- [in] + phyRxHeader => checkedHeader, -- [in] + phyRxLinkError => kCodeLinkError, -- [in] + pgpRxClk => pgpRxClk, -- [in] + pgpRxRst => pgpRxRst, -- [in] + pgpRxValid => ebValid, -- [out] + pgpRxData => ebData, -- [out] + pgpRxHeader => ebHeader, -- [out] + remLinkData => remLinkData, -- [out] + overflow => ebOverflow, -- [out] + linkError => linkError, -- [out] + status => ebStatus); -- [out] -- Main RX protocol logic U_Pgp4RxProtocol_1 : entity surf.Pgp4RxProtocol diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd index 5b4bd73064..56934ccecd 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd @@ -27,38 +27,51 @@ entity Pgp4RxEb is generic ( TPD_G : time := 1 ns; RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset - RST_ASYNC_G : boolean := false); + RST_ASYNC_G : boolean := false; + BYPASS_G : boolean := false); port ( - phyRxClk : in sl; - phyRxRst : in sl; - phyRxValid : in sl; - phyRxData : in slv(63 downto 0); -- Unscrambled data from the PHY - phyRxHeader : in slv(1 downto 0); + phyRxClk : in sl; + phyRxRst : in sl; + phyRxValid : in sl; + phyRxData : in slv(63 downto 0); -- Unscrambled data from the PHY + phyRxHeader : in slv(1 downto 0); + phyRxLinkError : in sl := '0'; -- User Transmit interface - pgpRxClk : in sl; - pgpRxRst : in sl; - pgpRxValid : out sl; - pgpRxData : out slv(63 downto 0); - pgpRxHeader : out slv(1 downto 0); - remLinkData : out slv(47 downto 0); - overflow : out sl; - status : out slv(8 downto 0)); + pgpRxClk : in sl; + pgpRxRst : in sl; + pgpRxValid : out sl; + pgpRxData : out slv(63 downto 0); + pgpRxHeader : out slv(1 downto 0); + remLinkData : out slv(47 downto 0); + overflow : out sl; + linkError : out sl; + status : out slv(8 downto 0)); end entity Pgp4RxEb; architecture rtl of Pgp4RxEb is type RegType is record + holdoff : sl; dataValid : sl; remLinkData : slv(47 downto 0); fifoIn : slv(65 downto 0); fifoWrEn : sl; + pgpRxValid : sl; + pgpRxData : slv(63 downto 0); + pgpRxHeader : slv(1 downto 0); + linkError : sl; end record RegType; constant REG_INIT_C : RegType := ( + holdoff => '0', dataValid => '0', remLinkData => (others => '0'), fifoIn => (others => '0'), - fifoWrEn => '0'); + fifoWrEn => '0', + pgpRxValid => '0', + pgpRxData => (others => '0'), + pgpRxHeader => (others => '0'), + linkError => '0'); signal r : RegType := REG_INIT_C; signal rin : RegType; @@ -69,7 +82,7 @@ architecture rtl of Pgp4RxEb is begin - comb : process (phyRxData, phyRxHeader, phyRxRst, phyRxValid, r) is + comb : process (phyRxData, phyRxHeader, phyRxLinkError, phyRxRst, phyRxValid, r) is variable v : RegType; begin -- Latch the current value @@ -83,6 +96,13 @@ begin v.fifoIn(65 downto 64) := phyRxHeader; v.fifoWrEn := phyRxValid; + -- Map to same-clock bypass output + v.pgpRxValid := phyRxValid and not r.holdoff and not phyRxLinkError; + v.pgpRxData := phyRxData; + v.pgpRxHeader := phyRxHeader; + v.linkError := phyRxLinkError; + v.holdoff := phyRxLinkError; + -- Check for valid k-code if (phyRxValid = '1') and (phyRxHeader = PGP4_K_HEADER_C) then @@ -104,6 +124,11 @@ begin if (RST_ASYNC_G = false and phyRxRst = RST_POLARITY_G) then -- Maintain save behavior before the remLinkData update (not reseting fifoIn or fifoWrEn) v.remLinkData := (others => '0'); + v.holdoff := '0'; + v.pgpRxValid := '0'; + v.pgpRxData := (others => '0'); + v.pgpRxHeader := (others => '0'); + v.linkError := '0'; end if; -- Register the variable for next clock cycle @@ -120,54 +145,79 @@ begin end if; end process seq; - U_remLinkData : entity surf.SynchronizerFifo - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - RST_ASYNC_G => RST_ASYNC_G, - DATA_WIDTH_G => 48) - port map ( - rst => phyRxRst, - wr_clk => phyRxClk, - wr_en => r.dataValid, - din => r.remLinkData, - rd_clk => pgpRxClk, - dout => remLinkData); - - U_FifoAsync_1 : entity surf.FifoAsync - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - RST_ASYNC_G => RST_ASYNC_G, - MEMORY_TYPE_G => "block", - FWFT_EN_G => true, - PIPE_STAGES_G => 0, - DATA_WIDTH_G => 66, - ADDR_WIDTH_G => 9) - port map ( - rst => phyRxRst, - -- Write Interface - wr_clk => phyRxClk, - wr_en => r.fifoWrEn, - din => r.fifoIn, - overflow => overflowInt, - -- Read Interface - rd_clk => pgpRxClk, - rd_en => valid, - dout(63 downto 0) => pgpRxData, - dout(65 downto 64) => pgpRxHeader, - rd_data_count => status, - valid => valid); - - pgpRxValid <= valid; - - U_overflow : entity surf.SynchronizerOneShot - generic map ( - TPD_G => TPD_G, - RST_ASYNC_G => RST_ASYNC_G) - port map ( - clk => pgpRxClk, - dataIn => overflowInt, - dataOut => overflow); + GEN_EB : if (BYPASS_G = false) generate + + U_remLinkData : entity surf.SynchronizerFifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + DATA_WIDTH_G => 48) + port map ( + rst => phyRxRst, + wr_clk => phyRxClk, + wr_en => r.dataValid, + din => r.remLinkData, + rd_clk => pgpRxClk, + dout => remLinkData); + + U_FifoAsync_1 : entity surf.FifoAsync + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + MEMORY_TYPE_G => "block", + FWFT_EN_G => true, + PIPE_STAGES_G => 0, + DATA_WIDTH_G => 66, + ADDR_WIDTH_G => 9) + port map ( + rst => phyRxRst, + -- Write Interface + wr_clk => phyRxClk, + wr_en => r.fifoWrEn, + din => r.fifoIn, + overflow => overflowInt, + -- Read Interface + rd_clk => pgpRxClk, + rd_en => valid, + dout(63 downto 0) => pgpRxData, + dout(65 downto 64) => pgpRxHeader, + rd_data_count => status, + valid => valid); + + pgpRxValid <= valid; + + U_overflow : entity surf.SynchronizerOneShot + generic map ( + TPD_G => TPD_G, + RST_ASYNC_G => RST_ASYNC_G) + port map ( + clk => pgpRxClk, + dataIn => overflowInt, + dataOut => overflow); + + U_linkError : entity surf.SynchronizerOneShot + generic map ( + TPD_G => TPD_G, + RST_ASYNC_G => RST_ASYNC_G) + port map ( + clk => pgpRxClk, + dataIn => phyRxLinkError, + dataOut => linkError); + + end generate GEN_EB; + + GEN_BYPASS : if (BYPASS_G = true) generate + + pgpRxValid <= r.pgpRxValid; + pgpRxData <= r.pgpRxData; + pgpRxHeader <= r.pgpRxHeader; + remLinkData <= (others => '0'); + overflow <= '0'; + linkError <= r.linkError; + status <= (others => '0'); + + end generate GEN_BYPASS; end architecture rtl; diff --git a/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd b/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd index 411fea4539..840c1b9133 100644 --- a/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd +++ b/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd @@ -19,19 +19,23 @@ library surf; use surf.StdRtlPkg.all; entity Pgp4RxEbWrapper is + generic ( + BYPASS_G : boolean := false); port ( - phyClk : in sl; - pgpClk : in sl; - rst : in sl; - phyRxValid : in sl; - phyRxData : in slv(63 downto 0); - phyRxHeader : in slv(1 downto 0); - pgpRxValid : out sl; - pgpRxData : out slv(63 downto 0); - pgpRxHeader : out slv(1 downto 0); - remLinkData : out slv(47 downto 0); - overflow : out sl; - status : out slv(8 downto 0)); + phyClk : in sl; + pgpClk : in sl; + rst : in sl; + phyRxValid : in sl; + phyRxData : in slv(63 downto 0); + phyRxHeader : in slv(1 downto 0); + phyRxLinkError : in sl := '0'; + pgpRxValid : out sl; + pgpRxData : out slv(63 downto 0); + pgpRxHeader : out slv(1 downto 0); + remLinkData : out slv(47 downto 0); + overflow : out sl; + linkError : out sl; + status : out slv(8 downto 0)); end entity Pgp4RxEbWrapper; architecture rtl of Pgp4RxEbWrapper is @@ -39,19 +43,23 @@ architecture rtl of Pgp4RxEbWrapper is begin U_DUT : entity surf.Pgp4RxEb + generic map ( + BYPASS_G => BYPASS_G) port map ( - phyRxClk => phyClk, - phyRxRst => rst, - phyRxValid => phyRxValid, - phyRxData => phyRxData, - phyRxHeader => phyRxHeader, - pgpRxClk => pgpClk, - pgpRxRst => rst, - pgpRxValid => pgpRxValid, - pgpRxData => pgpRxData, - pgpRxHeader => pgpRxHeader, - remLinkData => remLinkData, - overflow => overflow, - status => status); + phyRxClk => phyClk, + phyRxRst => rst, + phyRxValid => phyRxValid, + phyRxData => phyRxData, + phyRxHeader => phyRxHeader, + phyRxLinkError => phyRxLinkError, + pgpRxClk => pgpClk, + pgpRxRst => rst, + pgpRxValid => pgpRxValid, + pgpRxData => pgpRxData, + pgpRxHeader => pgpRxHeader, + remLinkData => remLinkData, + overflow => overflow, + linkError => linkError, + status => status); end architecture rtl; diff --git a/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py b/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py index cbb4a4a209..4419311865 100644 --- a/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py +++ b/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py @@ -31,7 +31,7 @@ from cocotb.clock import Clock from cocotb.triggers import FallingEdge, RisingEdge, Timer -from tests.common.regression_utils import env_flag, env_float, parameter_case +from tests.common.regression_utils import env_flag, env_float, parameter_case, start_lockstep_clocks from tests.protocols.pgp.pgp4.pgp4_test_utils import ( PGP4_D_HEADER, PGP4_K_HEADER, @@ -54,8 +54,11 @@ def __init__(self, dut): self.dut = dut self.phy_period_ns = env_float("PHY_CLK_PERIOD_NS", default=4.0) self.pgp_period_ns = env_float("PGP_CLK_PERIOD_NS", default=4.125) - cocotb.start_soon(Clock(dut.phyClk, self.phy_period_ns, unit="ns").start()) - cocotb.start_soon(Clock(dut.pgpClk, self.pgp_period_ns, unit="ns").start()) + if env_flag("COMMON_CLK", default=False): + start_lockstep_clocks(dut.phyClk, dut.pgpClk, period_ns=self.phy_period_ns) + else: + cocotb.start_soon(Clock(dut.phyClk, self.phy_period_ns, unit="ns").start()) + cocotb.start_soon(Clock(dut.pgpClk, self.pgp_period_ns, unit="ns").start()) async def cycle_phy(self, count: int = 1): for _ in range(count): @@ -140,7 +143,7 @@ async def wait_for_collected_beats(collector: ValidBeatCollector, *, count: int, def initialize_phy_inputs(dut): """Drive the direct PHY-side wrapper inputs to a known idle state.""" - initialize_signals(dut, phyRxValid=0, phyRxData=0, phyRxHeader=0) + initialize_signals(dut, phyRxValid=0, phyRxData=0, phyRxHeader=0, phyRxLinkError=0) async def send_phy_word(tb: Pgp4RxEbTB, *, header: int, data: int): @@ -158,6 +161,15 @@ async def send_phy_words(tb: Pgp4RxEbTB, words: list[tuple[int, int]]): await send_phy_word(tb, header=header, data=data) +async def send_phy_link_error(tb: Pgp4RxEbTB): + """Pulse the checker-to-EB link error without presenting a valid word.""" + + tb.dut.phyRxValid.value = 0 + tb.dut.phyRxLinkError.value = 1 + await tb.cycle_phy() + tb.dut.phyRxLinkError.value = 0 + + async def collect_output_words(tb: Pgp4RxEbTB, *, count: int, cycles: int = 256) -> list[tuple[int, int]]: """Capture visible FIFO output words on the `pgpRxClk` side. @@ -190,7 +202,7 @@ async def assert_no_output_words(tb: Pgp4RxEbTB, *, cycles: int): @cocotb.test() async def pgp4_rx_eb_filters_skip_and_preserves_stream_order(dut): tb = Pgp4RxEbTB(dut) - if env_flag("EXPECT_OVERFLOW", default=False): + if env_flag("EXPECT_BYPASS", default=False) or env_flag("EXPECT_OVERFLOW", default=False): return initialize_phy_inputs(dut) @@ -233,6 +245,9 @@ async def pgp4_rx_eb_filters_skip_and_preserves_stream_order(dut): @cocotb.test() async def pgp4_rx_eb_reset_flushes_buffered_words(dut): tb = Pgp4RxEbTB(dut) + if env_flag("EXPECT_BYPASS", default=False): + return + initialize_phy_inputs(dut) await tb.reset() @@ -255,6 +270,9 @@ async def pgp4_rx_eb_reset_flushes_buffered_words(dut): @cocotb.test() async def pgp4_rx_eb_overflow_pulses_when_phy_outpaces_local_clock(dut): tb = Pgp4RxEbTB(dut) + if env_flag("EXPECT_BYPASS", default=False): + return + initialize_phy_inputs(dut) await tb.reset() @@ -277,6 +295,42 @@ async def pgp4_rx_eb_overflow_pulses_when_phy_outpaces_local_clock(dut): assert overflow_monitor.seen +@cocotb.test() +async def pgp4_rx_eb_bypass_bubbles_after_link_error(dut): + tb = Pgp4RxEbTB(dut) + if not env_flag("EXPECT_BYPASS", default=False): + return + + initialize_phy_inputs(dut) + await tb.reset() + + collector = ValidBeatCollector( + dut, + step=tb.sample_pgp_cycle, + valid_name="pgpRxValid", + field_names=("pgpRxHeader", "pgpRxData"), + ) + link_error_monitor = PulseMonitor(dut, "linkError", step=tb.sample_pgp_cycle) + cocotb.start_soon(collector.run()) + cocotb.start_soon(link_error_monitor.run()) + + data_word_a = 0x1111222233334444 + suppressed_word = 0x5555666677778888 + data_word_b = 0x9999AAAABBBBCCCC + + await send_phy_word(tb, header=PGP4_D_HEADER, data=data_word_a) + await send_phy_link_error(tb) + await send_phy_word(tb, header=PGP4_D_HEADER, data=suppressed_word) + await send_phy_word(tb, header=PGP4_D_HEADER, data=data_word_b) + + words = await wait_for_collected_beats(collector, count=2, step=tb.cycle_pgp, cycles=64) + assert words == [ + (PGP4_D_HEADER, data_word_a), + (PGP4_D_HEADER, data_word_b), + ] + assert link_error_monitor.seen + + PARAMETER_SWEEP = [ parameter_case( "async_drift_direct_wrapper", @@ -307,3 +361,29 @@ def test_Pgp4RxEb(parameters): wrapper_source="protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd", extra_env=parameters, ) + + +BYPASS_PARAMETER_SWEEP = [ + pytest.param( + {"BYPASS_G": True}, + { + "PHY_CLK_PERIOD_NS": "4.000", + "PGP_CLK_PERIOD_NS": "4.000", + "COMMON_CLK": "1", + "EXPECT_BYPASS": "1", + "EXPECT_OVERFLOW": "0", + }, + id="same_clock_bypass", + ), +] + + +@pytest.mark.parametrize("parameters, extra_env", BYPASS_PARAMETER_SWEEP) +def test_Pgp4RxEbBypass(parameters, extra_env): + run_pgp_wrapper_test( + test_file=__file__, + toplevel="surf.pgp4rxebwrapper", + wrapper_source="protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd", + parameters=parameters, + extra_env=extra_env, + ) From eddc20d4544644c240c3ab768b2f7317a712cb2c Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 29 Apr 2026 10:32:23 -0700 Subject: [PATCH 64/92] Rename PGP4 RX EB skip generic --- protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd | 2 +- protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd | 6 ++--- .../pgp4/core/wrappers/Pgp4RxEbWrapper.vhd | 4 ++-- tests/protocols/pgp/pgp4/test_Pgp4RxEb.py | 22 +++++++++---------- 4 files changed, 17 insertions(+), 17 deletions(-) diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd index a20076f236..a10a1621a7 100755 --- a/protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd @@ -161,7 +161,7 @@ begin TPD_G => TPD_G, RST_POLARITY_G => RST_POLARITY_G, RST_ASYNC_G => RST_ASYNC_G, - BYPASS_G => not SKIP_EN_G) + SKIP_EN_G => SKIP_EN_G) port map ( phyRxClk => phyRxClk, -- [in] phyRxRst => phyRxRst, -- [in] diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd index 56934ccecd..f6394582cf 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd @@ -28,7 +28,7 @@ entity Pgp4RxEb is TPD_G : time := 1 ns; RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset RST_ASYNC_G : boolean := false; - BYPASS_G : boolean := false); + SKIP_EN_G : boolean := true); port ( phyRxClk : in sl; phyRxRst : in sl; @@ -145,7 +145,7 @@ begin end if; end process seq; - GEN_EB : if (BYPASS_G = false) generate + GEN_EB : if (SKIP_EN_G = true) generate U_remLinkData : entity surf.SynchronizerFifo generic map ( @@ -208,7 +208,7 @@ begin end generate GEN_EB; - GEN_BYPASS : if (BYPASS_G = true) generate + GEN_BYPASS : if (SKIP_EN_G = false) generate pgpRxValid <= r.pgpRxValid; pgpRxData <= r.pgpRxData; diff --git a/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd b/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd index 840c1b9133..b659146b37 100644 --- a/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd +++ b/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd @@ -20,7 +20,7 @@ use surf.StdRtlPkg.all; entity Pgp4RxEbWrapper is generic ( - BYPASS_G : boolean := false); + SKIP_EN_G : boolean := true); port ( phyClk : in sl; pgpClk : in sl; @@ -44,7 +44,7 @@ begin U_DUT : entity surf.Pgp4RxEb generic map ( - BYPASS_G => BYPASS_G) + SKIP_EN_G => SKIP_EN_G) port map ( phyRxClk => phyClk, phyRxRst => rst, diff --git a/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py b/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py index 4419311865..750fe2a6b5 100644 --- a/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py +++ b/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py @@ -202,7 +202,7 @@ async def assert_no_output_words(tb: Pgp4RxEbTB, *, cycles: int): @cocotb.test() async def pgp4_rx_eb_filters_skip_and_preserves_stream_order(dut): tb = Pgp4RxEbTB(dut) - if env_flag("EXPECT_BYPASS", default=False) or env_flag("EXPECT_OVERFLOW", default=False): + if env_flag("EXPECT_SKIP_DISABLED", default=False) or env_flag("EXPECT_OVERFLOW", default=False): return initialize_phy_inputs(dut) @@ -245,7 +245,7 @@ async def pgp4_rx_eb_filters_skip_and_preserves_stream_order(dut): @cocotb.test() async def pgp4_rx_eb_reset_flushes_buffered_words(dut): tb = Pgp4RxEbTB(dut) - if env_flag("EXPECT_BYPASS", default=False): + if env_flag("EXPECT_SKIP_DISABLED", default=False): return initialize_phy_inputs(dut) @@ -270,7 +270,7 @@ async def pgp4_rx_eb_reset_flushes_buffered_words(dut): @cocotb.test() async def pgp4_rx_eb_overflow_pulses_when_phy_outpaces_local_clock(dut): tb = Pgp4RxEbTB(dut) - if env_flag("EXPECT_BYPASS", default=False): + if env_flag("EXPECT_SKIP_DISABLED", default=False): return initialize_phy_inputs(dut) @@ -296,9 +296,9 @@ async def pgp4_rx_eb_overflow_pulses_when_phy_outpaces_local_clock(dut): @cocotb.test() -async def pgp4_rx_eb_bypass_bubbles_after_link_error(dut): +async def pgp4_rx_eb_skip_disabled_bubbles_after_link_error(dut): tb = Pgp4RxEbTB(dut) - if not env_flag("EXPECT_BYPASS", default=False): + if not env_flag("EXPECT_SKIP_DISABLED", default=False): return initialize_phy_inputs(dut) @@ -363,23 +363,23 @@ def test_Pgp4RxEb(parameters): ) -BYPASS_PARAMETER_SWEEP = [ +SKIP_DISABLED_PARAMETER_SWEEP = [ pytest.param( - {"BYPASS_G": True}, + {"SKIP_EN_G": False}, { "PHY_CLK_PERIOD_NS": "4.000", "PGP_CLK_PERIOD_NS": "4.000", "COMMON_CLK": "1", - "EXPECT_BYPASS": "1", + "EXPECT_SKIP_DISABLED": "1", "EXPECT_OVERFLOW": "0", }, - id="same_clock_bypass", + id="same_clock_skip_disabled", ), ] -@pytest.mark.parametrize("parameters, extra_env", BYPASS_PARAMETER_SWEEP) -def test_Pgp4RxEbBypass(parameters, extra_env): +@pytest.mark.parametrize("parameters, extra_env", SKIP_DISABLED_PARAMETER_SWEEP) +def test_Pgp4RxEbSkipDisabled(parameters, extra_env): run_pgp_wrapper_test( test_file=__file__, toplevel="surf.pgp4rxebwrapper", From 65759eafcd30c4c45c11d3b27a7b3eabf6dd813a Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 29 Apr 2026 11:49:54 -0700 Subject: [PATCH 65/92] Refactor PGP4 RX components to enhance K-code handling and validation --- protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd | 6 +- .../pgp/pgp4/core/rtl/Pgp4RxKCodeChecker.vhd | 18 +++- .../pgp4/core/wrappers/Pgp4RxEbWrapper.vhd | 37 ++++++-- tests/protocols/pgp/pgp4/test_Pgp4RxEb.py | 85 ++++++++++--------- .../pgp/pgp4/test_Pgp4RxKCodeChecker.py | 22 ++++- 5 files changed, 110 insertions(+), 58 deletions(-) diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd index f6394582cf..e1b140f937 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd @@ -51,7 +51,6 @@ end entity Pgp4RxEb; architecture rtl of Pgp4RxEb is type RegType is record - holdoff : sl; dataValid : sl; remLinkData : slv(47 downto 0); fifoIn : slv(65 downto 0); @@ -63,7 +62,6 @@ architecture rtl of Pgp4RxEb is end record RegType; constant REG_INIT_C : RegType := ( - holdoff => '0', dataValid => '0', remLinkData => (others => '0'), fifoIn => (others => '0'), @@ -97,11 +95,10 @@ begin v.fifoWrEn := phyRxValid; -- Map to same-clock bypass output - v.pgpRxValid := phyRxValid and not r.holdoff and not phyRxLinkError; + v.pgpRxValid := phyRxValid; v.pgpRxData := phyRxData; v.pgpRxHeader := phyRxHeader; v.linkError := phyRxLinkError; - v.holdoff := phyRxLinkError; -- Check for valid k-code if (phyRxValid = '1') and (phyRxHeader = PGP4_K_HEADER_C) then @@ -124,7 +121,6 @@ begin if (RST_ASYNC_G = false and phyRxRst = RST_POLARITY_G) then -- Maintain save behavior before the remLinkData update (not reseting fifoIn or fifoWrEn) v.remLinkData := (others => '0'); - v.holdoff := '0'; v.pgpRxValid := '0'; v.pgpRxData := (others => '0'); v.pgpRxHeader := (others => '0'); diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4RxKCodeChecker.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4RxKCodeChecker.vhd index 5941a232d9..fe45cae4a0 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4RxKCodeChecker.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4RxKCodeChecker.vhd @@ -43,6 +43,7 @@ end entity Pgp4RxKCodeChecker; architecture rtl of Pgp4RxKCodeChecker is type RegType is record + holdoff : sl; checkedValid : sl; checkedData : slv(63 downto 0); checkedHeader : slv(1 downto 0); @@ -50,6 +51,7 @@ architecture rtl of Pgp4RxKCodeChecker is end record RegType; constant REG_INIT_C : RegType := ( + holdoff => '0', checkedValid => '0', checkedData => (others => '0'), checkedHeader => (others => '0'), @@ -61,22 +63,30 @@ architecture rtl of Pgp4RxKCodeChecker is begin comb : process (phyRxData, phyRxHeader, phyRxRst, phyRxValid, r) is - variable v : RegType; + variable v : RegType; + variable badKCode : sl; begin -- Latch the current value v := r; + badKCode := '0'; + if (phyRxValid = '1') and (phyRxHeader = PGP4_K_HEADER_C) and + (phyRxData(PGP4_K_CODE_CRC_FIELD_C) /= pgp4KCodeCrc(phyRxData)) then + badKCode := '1'; + end if; + -- Map to output register - v.checkedValid := phyRxValid; + v.checkedValid := phyRxValid and not r.holdoff; v.checkedData := phyRxData; v.checkedHeader := phyRxHeader; v.linkError := '0'; + v.holdoff := '0'; -- Drop K-codes with invalid checksum - if (phyRxValid = '1') and (phyRxHeader = PGP4_K_HEADER_C) and - (phyRxData(PGP4_K_CODE_CRC_FIELD_C) /= pgp4KCodeCrc(phyRxData)) then + if (badKCode = '1') then v.checkedValid := '0'; v.linkError := '1'; + v.holdoff := '1'; end if; -- Reset diff --git a/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd b/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd index b659146b37..b3ef4bb98c 100644 --- a/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd +++ b/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd @@ -20,7 +20,8 @@ use surf.StdRtlPkg.all; entity Pgp4RxEbWrapper is generic ( - SKIP_EN_G : boolean := true); + SKIP_EN_G : boolean := true; + CHECK_K_CODE_G : boolean := false); port ( phyClk : in sl; pgpClk : in sl; @@ -40,18 +41,44 @@ end entity Pgp4RxEbWrapper; architecture rtl of Pgp4RxEbWrapper is + signal checkedValid : sl; + signal checkedData : slv(63 downto 0); + signal checkedHeader : slv(1 downto 0); + signal checkedError : sl; + begin + GEN_CHECK_K_CODE : if (CHECK_K_CODE_G = true) generate + U_Checker : entity surf.Pgp4RxKCodeChecker + port map ( + phyRxClk => phyClk, + phyRxRst => rst, + phyRxValid => phyRxValid, + phyRxData => phyRxData, + phyRxHeader => phyRxHeader, + checkedValid => checkedValid, + checkedData => checkedData, + checkedHeader => checkedHeader, + linkError => checkedError); + end generate GEN_CHECK_K_CODE; + + GEN_NO_CHECK_K_CODE : if (CHECK_K_CODE_G = false) generate + checkedValid <= phyRxValid; + checkedData <= phyRxData; + checkedHeader <= phyRxHeader; + checkedError <= phyRxLinkError; + end generate GEN_NO_CHECK_K_CODE; + U_DUT : entity surf.Pgp4RxEb generic map ( SKIP_EN_G => SKIP_EN_G) port map ( phyRxClk => phyClk, phyRxRst => rst, - phyRxValid => phyRxValid, - phyRxData => phyRxData, - phyRxHeader => phyRxHeader, - phyRxLinkError => phyRxLinkError, + phyRxValid => checkedValid, + phyRxData => checkedData, + phyRxHeader => checkedHeader, + phyRxLinkError => checkedError, pgpRxClk => pgpClk, pgpRxRst => rst, pgpRxValid => pgpRxValid, diff --git a/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py b/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py index 750fe2a6b5..4e7f71f419 100644 --- a/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py +++ b/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py @@ -9,14 +9,12 @@ ############################################################################## # Test methodology: -# - Sweep: Run the direct `Pgp4RxEb` wrapper in three asynchronous clock modes: -# a realistic slight-drift case where `phyRxClk` and `pgpRxClk` are close but -# not equal, a near-empty case where the local read clock is faster than the -# recovered write clock, and a deliberate overflow-stress case where the -# write side is much faster than the read side. +# - Sweep: Run the direct `Pgp4RxEb` wrapper in three asynchronous clock modes +# plus one same-clock, skip-disabled mode with the K-code checker enabled. # - Stimulus: Drive ordered mixes of data words, valid K-words, SKP words, and # reset/overflow stress bursts directly into the PHY side of the elastic -# buffer. +# buffer. The skip-disabled mode drives a malformed K-word followed +# immediately by data to cover the no-elastic-buffer link-error corner case. # - Checks: The DUT must forward non-SKP traffic in order, suppress SKP while # still updating `remLinkData`, flush buffered data on reset, and pulse # `overflow` when sustained write pressure outruns the read domain. @@ -31,17 +29,29 @@ from cocotb.clock import Clock from cocotb.triggers import FallingEdge, RisingEdge, Timer -from tests.common.regression_utils import env_flag, env_float, parameter_case, start_lockstep_clocks +from tests.common.regression_utils import ( + env_flag, + env_float, + hdl_parameters_from, + parameter_case, + start_lockstep_clocks, +) from tests.protocols.pgp.pgp4.pgp4_test_utils import ( PGP4_D_HEADER, PGP4_K_HEADER, + PGP4_USER, initialize_signals, pgp4_idle_word, + pgp4_kword, pgp4_skip_word, + pgp4_user_word, signal_int, ) from tests.protocols.pgp.pgp_test_utils import run_pgp_wrapper_test +K_CODE_CSC_LSB = 48 +USER_OPCODE_PAYLOAD = 0x0000CAFEBABE + class Pgp4RxEbTB: """Dual-clock harness for the elastic-buffer wrapper. @@ -161,13 +171,20 @@ async def send_phy_words(tb: Pgp4RxEbTB, words: list[tuple[int, int]]): await send_phy_word(tb, header=header, data=data) -async def send_phy_link_error(tb: Pgp4RxEbTB): - """Pulse the checker-to-EB link error without presenting a valid word.""" +def bad_kcode_checksum_word() -> int: + """Build a real USER K-word and corrupt only its checksum field.""" - tb.dut.phyRxValid.value = 0 - tb.dut.phyRxLinkError.value = 1 - await tb.cycle_phy() - tb.dut.phyRxLinkError.value = 0 + good_user_word = pgp4_user_word(USER_OPCODE_PAYLOAD) + assert good_user_word == pgp4_kword(PGP4_USER, USER_OPCODE_PAYLOAD) + return good_user_word ^ (1 << K_CODE_CSC_LSB) + + +def env_parameters_from(parameters: dict[str, object]) -> dict[str, object]: + return { + key: value + for key, value in parameters.items() + if not key.endswith("_G") + } async def collect_output_words(tb: Pgp4RxEbTB, *, count: int, cycles: int = 256) -> list[tuple[int, int]]: @@ -315,11 +332,12 @@ async def pgp4_rx_eb_skip_disabled_bubbles_after_link_error(dut): cocotb.start_soon(link_error_monitor.run()) data_word_a = 0x1111222233334444 + bad_user_word = bad_kcode_checksum_word() suppressed_word = 0x5555666677778888 data_word_b = 0x9999AAAABBBBCCCC await send_phy_word(tb, header=PGP4_D_HEADER, data=data_word_a) - await send_phy_link_error(tb) + await send_phy_word(tb, header=PGP4_K_HEADER, data=bad_user_word) await send_phy_word(tb, header=PGP4_D_HEADER, data=suppressed_word) await send_phy_word(tb, header=PGP4_D_HEADER, data=data_word_b) @@ -350,6 +368,16 @@ async def pgp4_rx_eb_skip_disabled_bubbles_after_link_error(dut): PGP_CLK_PERIOD_NS="12.000", EXPECT_OVERFLOW="1", ), + parameter_case( + "same_clock_skip_disabled", + SKIP_EN_G=False, + CHECK_K_CODE_G=True, + PHY_CLK_PERIOD_NS="4.000", + PGP_CLK_PERIOD_NS="4.000", + COMMON_CLK="1", + EXPECT_SKIP_DISABLED="1", + EXPECT_OVERFLOW="0", + ), ] @@ -359,31 +387,6 @@ def test_Pgp4RxEb(parameters): test_file=__file__, toplevel="surf.pgp4rxebwrapper", wrapper_source="protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd", - extra_env=parameters, - ) - - -SKIP_DISABLED_PARAMETER_SWEEP = [ - pytest.param( - {"SKIP_EN_G": False}, - { - "PHY_CLK_PERIOD_NS": "4.000", - "PGP_CLK_PERIOD_NS": "4.000", - "COMMON_CLK": "1", - "EXPECT_SKIP_DISABLED": "1", - "EXPECT_OVERFLOW": "0", - }, - id="same_clock_skip_disabled", - ), -] - - -@pytest.mark.parametrize("parameters, extra_env", SKIP_DISABLED_PARAMETER_SWEEP) -def test_Pgp4RxEbSkipDisabled(parameters, extra_env): - run_pgp_wrapper_test( - test_file=__file__, - toplevel="surf.pgp4rxebwrapper", - wrapper_source="protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd", - parameters=parameters, - extra_env=extra_env, + parameters=hdl_parameters_from(parameters), + extra_env=env_parameters_from(parameters), ) diff --git a/tests/protocols/pgp/pgp4/test_Pgp4RxKCodeChecker.py b/tests/protocols/pgp/pgp4/test_Pgp4RxKCodeChecker.py index 67cb637116..816365f700 100644 --- a/tests/protocols/pgp/pgp4/test_Pgp4RxKCodeChecker.py +++ b/tests/protocols/pgp/pgp4/test_Pgp4RxKCodeChecker.py @@ -14,7 +14,8 @@ # cycles, and reset directly into the checker input. # - Checks: Data words pass regardless of K-code checksum contents, valid # K-words pass unchanged, invalid K-words are suppressed with a one-cycle -# `linkError`, and reset clears the registered outputs. +# `linkError`, the word immediately following an invalid K-word is also +# suppressed, and reset clears the registered outputs. # - Timing: The checker is registered, so each input word is sampled one clock # cycle after it is driven. @@ -38,6 +39,8 @@ K_CODE_CSC_LSB = 48 DATA_PASS_THROUGH_WORD = 0x0123456789ABCDEF +DATA_AFTER_ERROR_WORD = 0xFEDCBA9876543210 +DATA_RECOVERY_WORD = 0x55AA55AA55AA55AA IDLE_PAUSE_MASK = 0x1234 IDLE_OVERFLOW_MASK = 0x00A5 USER_OPCODE_PAYLOAD = 0x0000CAFEBABE @@ -129,8 +132,21 @@ async def pgp4_rx_kcode_checker_test(dut): 1, ) - await drive_checker_word(tb, header=PGP4_K_HEADER, data=bad_user_word, valid=0) - assert checker_outputs(dut) == (0, PGP4_K_HEADER, bad_user_word, 0) + # The checker also suppresses the immediately following word so downstream + # link-error state can take effect before any more protocol words arrive. + assert await drive_checker_word(tb, header=PGP4_D_HEADER, data=DATA_AFTER_ERROR_WORD) == ( + 0, + PGP4_D_HEADER, + DATA_AFTER_ERROR_WORD, + 0, + ) + + assert await drive_checker_word(tb, header=PGP4_D_HEADER, data=DATA_RECOVERY_WORD) == ( + 1, + PGP4_D_HEADER, + DATA_RECOVERY_WORD, + 0, + ) tb.dut.phyRxValid.value = 1 tb.dut.phyRxHeader.value = PGP4_D_HEADER From e0cc269abbbbd696f02773aba913d1bb8b27d577 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 29 Apr 2026 13:37:42 -0700 Subject: [PATCH 66/92] Refactor output assignments in Pgp4RxKCodeChecker process for clarity --- protocols/pgp/pgp4/core/rtl/Pgp4RxKCodeChecker.vhd | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4RxKCodeChecker.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4RxKCodeChecker.vhd index fe45cae4a0..674ad1c193 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4RxKCodeChecker.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4RxKCodeChecker.vhd @@ -97,6 +97,12 @@ begin -- Register the variable for next clock cycle rin <= v; + -- Drive outputs + checkedValid <= r.checkedValid; + checkedData <= r.checkedData; + checkedHeader <= r.checkedHeader; + linkError <= r.linkError; + end process comb; seq : process (phyRxClk, phyRxRst) is @@ -108,9 +114,4 @@ begin end if; end process seq; - checkedValid <= r.checkedValid; - checkedData <= r.checkedData; - checkedHeader <= r.checkedHeader; - linkError <= r.linkError; - end architecture rtl; From 1691aae9ebac4e179e63e4b4b2d9a78ffaa5c58b Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 29 Apr 2026 14:02:29 -0700 Subject: [PATCH 67/92] Refactor Pgp4RxEb to streamline signal handling and remove unused variables --- protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd | 58 +++++++++--------------- 1 file changed, 22 insertions(+), 36 deletions(-) diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd index e1b140f937..826ba2461d 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd @@ -55,21 +55,13 @@ architecture rtl of Pgp4RxEb is remLinkData : slv(47 downto 0); fifoIn : slv(65 downto 0); fifoWrEn : sl; - pgpRxValid : sl; - pgpRxData : slv(63 downto 0); - pgpRxHeader : slv(1 downto 0); - linkError : sl; end record RegType; constant REG_INIT_C : RegType := ( dataValid => '0', remLinkData => (others => '0'), fifoIn => (others => '0'), - fifoWrEn => '0', - pgpRxValid => '0', - pgpRxData => (others => '0'), - pgpRxHeader => (others => '0'), - linkError => '0'); + fifoWrEn => '0'); signal r : RegType := REG_INIT_C; signal rin : RegType; @@ -80,7 +72,7 @@ architecture rtl of Pgp4RxEb is begin - comb : process (phyRxData, phyRxHeader, phyRxLinkError, phyRxRst, phyRxValid, r) is + comb : process (phyRxData, phyRxHeader, phyRxRst, phyRxValid, r) is variable v : RegType; begin -- Latch the current value @@ -89,29 +81,27 @@ begin -- Reset strobes v.dataValid := '0'; - -- Map to FIFO write - v.fifoIn(63 downto 0) := phyRxData; - v.fifoIn(65 downto 64) := phyRxHeader; - v.fifoWrEn := phyRxValid; + if (SKIP_EN_G = true) then - -- Map to same-clock bypass output - v.pgpRxValid := phyRxValid; - v.pgpRxData := phyRxData; - v.pgpRxHeader := phyRxHeader; - v.linkError := phyRxLinkError; + -- Map to FIFO write + v.fifoIn(63 downto 0) := phyRxData; + v.fifoIn(65 downto 64) := phyRxHeader; + v.fifoWrEn := phyRxValid; - -- Check for valid k-code - if (phyRxValid = '1') and (phyRxHeader = PGP4_K_HEADER_C) then + -- Check for valid k-code + if (phyRxValid = '1') and (phyRxHeader = PGP4_K_HEADER_C) then - -- Check for SKP words - if (phyRxData(PGP4_BTF_FIELD_C) = PGP4_SKP_C) then + -- Check for SKP words + if (phyRxData(PGP4_BTF_FIELD_C) = PGP4_SKP_C) then - -- Don't write SKP words into the FIFO - v.fifoWrEn := '0'; + -- Don't write SKP words into the FIFO + v.fifoWrEn := '0'; - -- Save the remote data bus - v.dataValid := '1'; - v.remLinkData := phyRxData(PGP4_SKIP_DATA_FIELD_C); + -- Save the remote data bus + v.dataValid := '1'; + v.remLinkData := phyRxData(PGP4_SKIP_DATA_FIELD_C); + + end if; end if; @@ -121,10 +111,6 @@ begin if (RST_ASYNC_G = false and phyRxRst = RST_POLARITY_G) then -- Maintain save behavior before the remLinkData update (not reseting fifoIn or fifoWrEn) v.remLinkData := (others => '0'); - v.pgpRxValid := '0'; - v.pgpRxData := (others => '0'); - v.pgpRxHeader := (others => '0'); - v.linkError := '0'; end if; -- Register the variable for next clock cycle @@ -206,12 +192,12 @@ begin GEN_BYPASS : if (SKIP_EN_G = false) generate - pgpRxValid <= r.pgpRxValid; - pgpRxData <= r.pgpRxData; - pgpRxHeader <= r.pgpRxHeader; + pgpRxValid <= phyRxValid; + pgpRxData <= phyRxData; + pgpRxHeader <= phyRxHeader; remLinkData <= (others => '0'); overflow <= '0'; - linkError <= r.linkError; + linkError <= phyRxLinkError; status <= (others => '0'); end generate GEN_BYPASS; From edb4ba65ba4a9d2a9373115440212cf3e2f315fd Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 30 Apr 2026 09:03:00 -0700 Subject: [PATCH 68/92] Refactor Pgp4RxWrapper entity and architecture for improved readability and consistency --- .../pgp/pgp4/core/wrappers/Pgp4RxWrapper.vhd | 92 +++++++++---------- 1 file changed, 46 insertions(+), 46 deletions(-) diff --git a/protocols/pgp/pgp4/core/wrappers/Pgp4RxWrapper.vhd b/protocols/pgp/pgp4/core/wrappers/Pgp4RxWrapper.vhd index 88960974e4..c5b0003349 100644 --- a/protocols/pgp/pgp4/core/wrappers/Pgp4RxWrapper.vhd +++ b/protocols/pgp/pgp4/core/wrappers/Pgp4RxWrapper.vhd @@ -22,40 +22,40 @@ use surf.Pgp4Pkg.all; entity Pgp4RxWrapper is port ( - clk : in sl; - rst : in sl; - txValid : in sl; - txReady : out sl; - txData : in slv(63 downto 0); - txSof : in sl; - txEof : in sl; - txEofe : in sl; - opCodeEn : in sl := '0'; - opCodeData : in slv(47 downto 0) := (others => '0'); - linkReady : out sl; - linkError : out sl; - frameRx : out sl; - frameRxErr : out sl; - rxOpCodeEn : out sl; - rxOpCodeData : out slv(47 downto 0); - rxValid : out sl; - rxLast : out sl; - rxData : out slv(63 downto 0); - rxDest : out slv(7 downto 0); - rxUser : out slv(15 downto 0)); + clk : in sl; + rst : in sl; + txValid : in sl; + txReady : out sl; + txData : in slv(63 downto 0); + txSof : in sl; + txEof : in sl; + txEofe : in sl; + opCodeEn : in sl := '0'; + opCodeData : in slv(47 downto 0) := (others => '0'); + linkReady : out sl; + linkError : out sl; + frameRx : out sl; + frameRxErr : out sl; + rxOpCodeEn : out sl; + rxOpCodeData : out slv(47 downto 0); + rxValid : out sl; + rxLast : out sl; + rxData : out slv(63 downto 0); + rxDest : out slv(7 downto 0); + rxUser : out slv(15 downto 0)); end entity Pgp4RxWrapper; architecture rtl of Pgp4RxWrapper is - signal pgpTxIn : Pgp4TxInType := PGP4_TX_IN_INIT_C; - signal pgpTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal pgpTxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal phyTxValid : sl; - signal phyTxData : slv(63 downto 0); - signal phyTxHeader : slv(1 downto 0); + signal pgpTxIn : Pgp4TxInType := PGP4_TX_IN_INIT_C; + signal pgpTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal pgpTxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal phyTxValid : sl; + signal phyTxData : slv(63 downto 0); + signal phyTxHeader : slv(1 downto 0); - signal pgpRxOut : Pgp4RxOutType := PGP4_RX_OUT_INIT_C; - signal pgpRxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal pgpRxOut : Pgp4RxOutType := PGP4_RX_OUT_INIT_C; + signal pgpRxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; begin @@ -121,23 +121,23 @@ begin SKIP_EN_G => false, RX_CRC_PIPELINE_G => 0) port map ( - pgpRxClk => clk, - pgpRxRst => rst, - pgpRxIn => PGP4_RX_IN_INIT_C, - pgpRxOut => pgpRxOut, + pgpRxClk => clk, + pgpRxRst => rst, + pgpRxIn => PGP4_RX_IN_INIT_C, + pgpRxOut => pgpRxOut, pgpRxMasters(0) => pgpRxMaster, - pgpRxCtrl(0) => AXI_STREAM_CTRL_UNUSED_C, - remRxFifoCtrl => open, - remRxLinkReady => open, - locRxLinkReady => open, - phyRxClk => clk, - phyRxRst => rst, - phyRxInit => open, - phyRxActive => '1', - phyRxValid => phyTxValid, - phyRxData => phyTxData, - phyRxHeader => phyTxHeader, - phyRxStartSeq => '0', - phyRxSlip => open); + pgpRxCtrl(0) => AXI_STREAM_CTRL_UNUSED_C, + remRxFifoCtrl => open, + remRxLinkReady => open, + locRxLinkReady => open, + phyRxClk => clk, + phyRxRst => rst, + phyRxInit => open, + phyRxActive => '1', + phyRxValid => phyTxValid, + phyRxData => phyTxData, + phyRxHeader => phyTxHeader, + phyRxStartSeq => '0', + phyRxSlip => open); end architecture rtl; From 89fd0d5629f6bf16554036be5bc186fe373e3aec Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 30 Apr 2026 09:03:45 -0700 Subject: [PATCH 69/92] Refactor signal declarations in Pgp4CoreWrapper, Pgp4RxEbWrapper, and Pgp4RxProtocolDepacketizerWrapper for improved alignment and readability --- .../pgp4/core/wrappers/Pgp4CoreWrapper.vhd | 42 +++++++++---------- .../pgp4/core/wrappers/Pgp4RxEbWrapper.vhd | 4 +- .../Pgp4RxProtocolDepacketizerWrapper.vhd | 18 ++++---- 3 files changed, 32 insertions(+), 32 deletions(-) diff --git a/protocols/pgp/pgp4/core/wrappers/Pgp4CoreWrapper.vhd b/protocols/pgp/pgp4/core/wrappers/Pgp4CoreWrapper.vhd index afe30010b5..f453fea636 100644 --- a/protocols/pgp/pgp4/core/wrappers/Pgp4CoreWrapper.vhd +++ b/protocols/pgp/pgp4/core/wrappers/Pgp4CoreWrapper.vhd @@ -49,27 +49,27 @@ end entity Pgp4CoreWrapper; architecture rtl of Pgp4CoreWrapper is - constant TUSER_WIDTH_C : positive := 1; - constant TID_WIDTH_C : positive := 1; - constant TDEST_WIDTH_C : positive := 1; - constant TDATA_NUM_BYTES_C : positive := 8; - signal axisClk : sl := '0'; - signal axisRst : sl := '0'; - signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal pgpTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal pgpTxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal pgpTxIn : Pgp4TxInType := PGP4_TX_IN_INIT_C; - signal pgpTxOut : Pgp4TxOutType; - signal phyValid : sl := '0'; - signal phyData : slv(63 downto 0) := (others => '0'); - signal phyHeader : slv(1 downto 0) := (others => '0'); - signal pgpRxIn : Pgp4RxInType := PGP4_RX_IN_INIT_C; - signal pgpRxOut : Pgp4RxOutType; - signal pgpRxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal pgpRxCtrl : AxiStreamCtrlType := AXI_STREAM_CTRL_INIT_C; - signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + constant TUSER_WIDTH_C : positive := 1; + constant TID_WIDTH_C : positive := 1; + constant TDEST_WIDTH_C : positive := 1; + constant TDATA_NUM_BYTES_C : positive := 8; + signal axisClk : sl := '0'; + signal axisRst : sl := '0'; + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal pgpTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal pgpTxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal pgpTxIn : Pgp4TxInType := PGP4_TX_IN_INIT_C; + signal pgpTxOut : Pgp4TxOutType; + signal phyValid : sl := '0'; + signal phyData : slv(63 downto 0) := (others => '0'); + signal phyHeader : slv(1 downto 0) := (others => '0'); + signal pgpRxIn : Pgp4RxInType := PGP4_RX_IN_INIT_C; + signal pgpRxOut : Pgp4RxOutType; + signal pgpRxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal pgpRxCtrl : AxiStreamCtrlType := AXI_STREAM_CTRL_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; begin diff --git a/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd b/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd index b3ef4bb98c..71ca3bcad0 100644 --- a/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd +++ b/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd @@ -20,8 +20,8 @@ use surf.StdRtlPkg.all; entity Pgp4RxEbWrapper is generic ( - SKIP_EN_G : boolean := true; - CHECK_K_CODE_G : boolean := false); + SKIP_EN_G : boolean := true; + CHECK_K_CODE_G : boolean := false); port ( phyClk : in sl; pgpClk : in sl; diff --git a/protocols/pgp/pgp4/core/wrappers/Pgp4RxProtocolDepacketizerWrapper.vhd b/protocols/pgp/pgp4/core/wrappers/Pgp4RxProtocolDepacketizerWrapper.vhd index 493290de9b..3c8800b1ba 100644 --- a/protocols/pgp/pgp4/core/wrappers/Pgp4RxProtocolDepacketizerWrapper.vhd +++ b/protocols/pgp/pgp4/core/wrappers/Pgp4RxProtocolDepacketizerWrapper.vhd @@ -43,15 +43,15 @@ end entity Pgp4RxProtocolDepacketizerWrapper; architecture rtl of Pgp4RxProtocolDepacketizerWrapper is - signal pgpRxOut : Pgp4RxOutType := PGP4_RX_OUT_INIT_C; - signal pgpRawRxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal pgpRawRxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal depacketizedRxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal depacketizedRxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal depacketizerDebug : Packetizer2DebugType; - signal remRxFifoCtrl : AxiStreamCtrlArray(0 downto 0); - signal remRxLinkReady : sl; - signal locRxLinkReady : sl; + signal pgpRxOut : Pgp4RxOutType := PGP4_RX_OUT_INIT_C; + signal pgpRawRxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal pgpRawRxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal depacketizedRxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal depacketizedRxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal depacketizerDebug : Packetizer2DebugType; + signal remRxFifoCtrl : AxiStreamCtrlArray(0 downto 0); + signal remRxLinkReady : sl; + signal locRxLinkReady : sl; begin From ab0487907ba7edda7bb3adeb8fd84016e125c516 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 30 Apr 2026 09:10:36 -0700 Subject: [PATCH 70/92] Whitespace cleanup. --- protocols/pgp/pgp4/core/rtl/Pgp4AxiL.vhd | 10 ++-- protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd | 30 +++++------ .../core/wrappers/Pgp4AxiLDirectWrapper.vhd | 52 +++++++++---------- .../core/wrappers/Pgp4CoreLiteWrapper.vhd | 42 +++++++-------- .../wrappers/Pgp4LiteRxLowSpeedWrapper.vhd | 22 ++++---- .../Pgp4RxLiteLowSpeedLaneWrapper.vhd | 52 +++++++++---------- .../wrappers/Pgp4RxLiteLowSpeedRegWrapper.vhd | 4 +- .../core/wrappers/Pgp4RxProtocolWrapper.vhd | 12 ++--- 8 files changed, 112 insertions(+), 112 deletions(-) diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4AxiL.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4AxiL.vhd index 23f10e64b6..e1bea5d2fb 100755 --- a/protocols/pgp/pgp4/core/rtl/Pgp4AxiL.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4AxiL.vhd @@ -198,11 +198,11 @@ begin --------------------- -- AXI-Lite Registers --------------------- - comb : process (axilReadMaster, axilRst, axilWriteMaster, locData, locOverflowCnt, - locPause, locPauseCnt, phyFec, phyFecCnt, r, remLinkData, - remRxOverflowCnt, remRxPause, remRxPauseCnt, rxClkFreq, rxError, - rxErrorCnt, rxOpCodeData, rxStatusCnt, txClkFreq, txError, - txErrorCnt, txOpCodeData, txStatusCnt) is + comb : process (axilReadMaster, axilRst, axilWriteMaster, locData, + locOverflowCnt, locPause, locPauseCnt, phyFec, phyFecCnt, r, + remLinkData, remRxOverflowCnt, remRxPause, remRxPauseCnt, + rxClkFreq, rxError, rxErrorCnt, rxOpCodeData, rxStatusCnt, + txClkFreq, txError, txErrorCnt, txOpCodeData, txStatusCnt) is variable v : RegType; variable axilEp : AxiLiteEndpointType; begin diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd index a10a1621a7..abf7a581e3 100755 --- a/protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd @@ -163,21 +163,21 @@ begin RST_ASYNC_G => RST_ASYNC_G, SKIP_EN_G => SKIP_EN_G) port map ( - phyRxClk => phyRxClk, -- [in] - phyRxRst => phyRxRst, -- [in] - phyRxValid => checkedValid, -- [in] - phyRxData => checkedData, -- [in] - phyRxHeader => checkedHeader, -- [in] - phyRxLinkError => kCodeLinkError, -- [in] - pgpRxClk => pgpRxClk, -- [in] - pgpRxRst => pgpRxRst, -- [in] - pgpRxValid => ebValid, -- [out] - pgpRxData => ebData, -- [out] - pgpRxHeader => ebHeader, -- [out] - remLinkData => remLinkData, -- [out] - overflow => ebOverflow, -- [out] - linkError => linkError, -- [out] - status => ebStatus); -- [out] + phyRxClk => phyRxClk, -- [in] + phyRxRst => phyRxRst, -- [in] + phyRxValid => checkedValid, -- [in] + phyRxData => checkedData, -- [in] + phyRxHeader => checkedHeader, -- [in] + phyRxLinkError => kCodeLinkError, -- [in] + pgpRxClk => pgpRxClk, -- [in] + pgpRxRst => pgpRxRst, -- [in] + pgpRxValid => ebValid, -- [out] + pgpRxData => ebData, -- [out] + pgpRxHeader => ebHeader, -- [out] + remLinkData => remLinkData, -- [out] + overflow => ebOverflow, -- [out] + linkError => linkError, -- [out] + status => ebStatus); -- [out] -- Main RX protocol logic U_Pgp4RxProtocol_1 : entity surf.Pgp4RxProtocol diff --git a/protocols/pgp/pgp4/core/wrappers/Pgp4AxiLDirectWrapper.vhd b/protocols/pgp/pgp4/core/wrappers/Pgp4AxiLDirectWrapper.vhd index 170f048d58..d84d21f890 100644 --- a/protocols/pgp/pgp4/core/wrappers/Pgp4AxiLDirectWrapper.vhd +++ b/protocols/pgp/pgp4/core/wrappers/Pgp4AxiLDirectWrapper.vhd @@ -22,32 +22,32 @@ use surf.Pgp4Pkg.all; entity Pgp4AxiLDirectWrapper is port ( - S_AXI_ACLK : in std_logic := '0'; - S_AXI_ARESETN : in std_logic := '0'; - S_AXI_AWADDR : in std_logic_vector(11 downto 0) := (others => '0'); - S_AXI_AWPROT : in std_logic_vector(2 downto 0) := (others => '0'); - S_AXI_AWVALID : in std_logic := '0'; - S_AXI_AWREADY : out std_logic; - S_AXI_WDATA : in std_logic_vector(31 downto 0) := (others => '0'); - S_AXI_WSTRB : in std_logic_vector(3 downto 0) := (others => '1'); - S_AXI_WVALID : in std_logic := '0'; - S_AXI_WREADY : out std_logic; - S_AXI_BRESP : out std_logic_vector(1 downto 0); - S_AXI_BVALID : out std_logic; - S_AXI_BREADY : in std_logic := '0'; - S_AXI_ARADDR : in std_logic_vector(11 downto 0) := (others => '0'); - S_AXI_ARPROT : in std_logic_vector(2 downto 0) := (others => '0'); - S_AXI_ARVALID : in std_logic := '0'; - S_AXI_ARREADY : out std_logic; - S_AXI_RDATA : out std_logic_vector(31 downto 0); - S_AXI_RRESP : out std_logic_vector(1 downto 0); - S_AXI_RVALID : out std_logic; - S_AXI_RREADY : in std_logic := '0'; - txDisableOut : out std_logic; - flowCntlDisOut : out std_logic; - resetTxOut : out std_logic; - resetRxOut : out std_logic; - loopbackOut : out std_logic_vector(2 downto 0)); + S_AXI_ACLK : in std_logic := '0'; + S_AXI_ARESETN : in std_logic := '0'; + S_AXI_AWADDR : in std_logic_vector(11 downto 0) := (others => '0'); + S_AXI_AWPROT : in std_logic_vector(2 downto 0) := (others => '0'); + S_AXI_AWVALID : in std_logic := '0'; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(31 downto 0) := (others => '0'); + S_AXI_WSTRB : in std_logic_vector(3 downto 0) := (others => '1'); + S_AXI_WVALID : in std_logic := '0'; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic := '0'; + S_AXI_ARADDR : in std_logic_vector(11 downto 0) := (others => '0'); + S_AXI_ARPROT : in std_logic_vector(2 downto 0) := (others => '0'); + S_AXI_ARVALID : in std_logic := '0'; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(31 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic := '0'; + txDisableOut : out std_logic; + flowCntlDisOut : out std_logic; + resetTxOut : out std_logic; + resetRxOut : out std_logic; + loopbackOut : out std_logic_vector(2 downto 0)); end entity Pgp4AxiLDirectWrapper; architecture rtl of Pgp4AxiLDirectWrapper is diff --git a/protocols/pgp/pgp4/core/wrappers/Pgp4CoreLiteWrapper.vhd b/protocols/pgp/pgp4/core/wrappers/Pgp4CoreLiteWrapper.vhd index 1ab7564f2e..8cdb9620d7 100644 --- a/protocols/pgp/pgp4/core/wrappers/Pgp4CoreLiteWrapper.vhd +++ b/protocols/pgp/pgp4/core/wrappers/Pgp4CoreLiteWrapper.vhd @@ -49,27 +49,27 @@ end entity Pgp4CoreLiteWrapper; architecture rtl of Pgp4CoreLiteWrapper is - constant TUSER_WIDTH_C : positive := 1; - constant TID_WIDTH_C : positive := 1; - constant TDEST_WIDTH_C : positive := 1; - constant TDATA_NUM_BYTES_C : positive := 8; - signal axisClk : sl := '0'; - signal axisRst : sl := '0'; - signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal pgpTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal pgpTxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal pgpTxIn : Pgp4TxInType := PGP4_TX_IN_INIT_C; - signal pgpTxOut : Pgp4TxOutType; - signal phyValid : sl := '0'; - signal phyData : slv(63 downto 0) := (others => '0'); - signal phyHeader : slv(1 downto 0) := (others => '0'); - signal pgpRxIn : Pgp4RxInType := PGP4_RX_IN_INIT_C; - signal pgpRxOut : Pgp4RxOutType; - signal pgpRxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal pgpRxCtrl : AxiStreamCtrlType := AXI_STREAM_CTRL_INIT_C; - signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + constant TUSER_WIDTH_C : positive := 1; + constant TID_WIDTH_C : positive := 1; + constant TDEST_WIDTH_C : positive := 1; + constant TDATA_NUM_BYTES_C : positive := 8; + signal axisClk : sl := '0'; + signal axisRst : sl := '0'; + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal pgpTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal pgpTxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal pgpTxIn : Pgp4TxInType := PGP4_TX_IN_INIT_C; + signal pgpTxOut : Pgp4TxOutType; + signal phyValid : sl := '0'; + signal phyData : slv(63 downto 0) := (others => '0'); + signal phyHeader : slv(1 downto 0) := (others => '0'); + signal pgpRxIn : Pgp4RxInType := PGP4_RX_IN_INIT_C; + signal pgpRxOut : Pgp4RxOutType; + signal pgpRxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal pgpRxCtrl : AxiStreamCtrlType := AXI_STREAM_CTRL_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; begin diff --git a/protocols/pgp/pgp4/core/wrappers/Pgp4LiteRxLowSpeedWrapper.vhd b/protocols/pgp/pgp4/core/wrappers/Pgp4LiteRxLowSpeedWrapper.vhd index 59cf6a2d64..b2843b683e 100644 --- a/protocols/pgp/pgp4/core/wrappers/Pgp4LiteRxLowSpeedWrapper.vhd +++ b/protocols/pgp/pgp4/core/wrappers/Pgp4LiteRxLowSpeedWrapper.vhd @@ -70,17 +70,17 @@ architecture rtl of Pgp4LiteRxLowSpeedWrapper is signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; - signal pgpTxIn : Pgp4TxInType := PGP4_TX_IN_INIT_C; - signal pgpTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal pgpTxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal phyTxValid : sl; - signal phyTxData : slv(63 downto 0); - signal phyTxHeader : slv(1 downto 0); - signal serWord : slv(65 downto 0); - signal deserData : Slv8Array(0 downto 0); - signal dlyLoads : slv(0 downto 0); - signal dlyCfgs : Slv9Array(0 downto 0); - signal rxMasters : AxiStreamMasterArray(0 downto 0); + signal pgpTxIn : Pgp4TxInType := PGP4_TX_IN_INIT_C; + signal pgpTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal pgpTxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal phyTxValid : sl; + signal phyTxData : slv(63 downto 0); + signal phyTxHeader : slv(1 downto 0); + signal serWord : slv(65 downto 0); + signal deserData : Slv8Array(0 downto 0); + signal dlyLoads : slv(0 downto 0); + signal dlyCfgs : Slv9Array(0 downto 0); + signal rxMasters : AxiStreamMasterArray(0 downto 0); begin diff --git a/protocols/pgp/pgp4/core/wrappers/Pgp4RxLiteLowSpeedLaneWrapper.vhd b/protocols/pgp/pgp4/core/wrappers/Pgp4RxLiteLowSpeedLaneWrapper.vhd index b2a4e0b0ee..3e66ef3760 100644 --- a/protocols/pgp/pgp4/core/wrappers/Pgp4RxLiteLowSpeedLaneWrapper.vhd +++ b/protocols/pgp/pgp4/core/wrappers/Pgp4RxLiteLowSpeedLaneWrapper.vhd @@ -23,36 +23,36 @@ use surf.Pgp4Pkg.all; entity Pgp4RxLiteLowSpeedLaneWrapper is port ( - clk : in sl; - rst : in sl; - txValid : in sl; - txReady : out sl; - txData : in slv(63 downto 0); - txSof : in sl; - txEof : in sl; - txEofe : in sl; - locked : out sl; - bitSlip : out sl; - dlyLoad : out sl; - dlyCfg : out slv(8 downto 0); - rxValid : out sl; - rxLast : out sl; - rxData : out slv(63 downto 0); - rxDest : out slv(7 downto 0); - rxUser : out slv(15 downto 0)); + clk : in sl; + rst : in sl; + txValid : in sl; + txReady : out sl; + txData : in slv(63 downto 0); + txSof : in sl; + txEof : in sl; + txEofe : in sl; + locked : out sl; + bitSlip : out sl; + dlyLoad : out sl; + dlyCfg : out slv(8 downto 0); + rxValid : out sl; + rxLast : out sl; + rxData : out slv(63 downto 0); + rxDest : out slv(7 downto 0); + rxUser : out slv(15 downto 0)); end entity Pgp4RxLiteLowSpeedLaneWrapper; architecture rtl of Pgp4RxLiteLowSpeedLaneWrapper is - signal pgpTxIn : Pgp4TxInType := PGP4_TX_IN_INIT_C; - signal pgpTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal pgpTxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal phyTxValid : sl; - signal phyTxData : slv(63 downto 0); - signal phyTxHeader : slv(1 downto 0); - signal serWord : slv(65 downto 0); - signal deserData : slv(7 downto 0); - signal rxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal pgpTxIn : Pgp4TxInType := PGP4_TX_IN_INIT_C; + signal pgpTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal pgpTxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal phyTxValid : sl; + signal phyTxData : slv(63 downto 0); + signal phyTxHeader : slv(1 downto 0); + signal serWord : slv(65 downto 0); + signal deserData : slv(7 downto 0); + signal rxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; begin diff --git a/protocols/pgp/pgp4/core/wrappers/Pgp4RxLiteLowSpeedRegWrapper.vhd b/protocols/pgp/pgp4/core/wrappers/Pgp4RxLiteLowSpeedRegWrapper.vhd index fb5af62108..39a50332fd 100644 --- a/protocols/pgp/pgp4/core/wrappers/Pgp4RxLiteLowSpeedRegWrapper.vhd +++ b/protocols/pgp/pgp4/core/wrappers/Pgp4RxLiteLowSpeedRegWrapper.vhd @@ -56,8 +56,8 @@ end entity Pgp4RxLiteLowSpeedRegWrapper; architecture rtl of Pgp4RxLiteLowSpeedRegWrapper is - signal eyeWidth : Slv9Array(1 downto 0) := (others => (others => '0')); - signal dlyConfig : Slv9Array(1 downto 0) := (others => (others => '0')); + signal eyeWidth : Slv9Array(1 downto 0) := (others => (others => '0')); + signal dlyConfig : Slv9Array(1 downto 0) := (others => (others => '0')); signal usrDlyCfg : Slv9Array(1 downto 0); signal axilClk : sl; signal axilRst : sl; diff --git a/protocols/pgp/pgp4/core/wrappers/Pgp4RxProtocolWrapper.vhd b/protocols/pgp/pgp4/core/wrappers/Pgp4RxProtocolWrapper.vhd index ffe9687537..4f221dffab 100644 --- a/protocols/pgp/pgp4/core/wrappers/Pgp4RxProtocolWrapper.vhd +++ b/protocols/pgp/pgp4/core/wrappers/Pgp4RxProtocolWrapper.vhd @@ -24,13 +24,13 @@ entity Pgp4RxProtocolWrapper is port ( clk : in sl; rst : in sl; - phyRxActive : in sl := '1'; - linkErrorIn : in sl := '0'; - resetRx : in sl := '0'; + phyRxActive : in sl := '1'; + linkErrorIn : in sl := '0'; + resetRx : in sl := '0'; protRxValid : in sl; protRxHeader : in slv(1 downto 0); protRxData : in slv(63 downto 0); - pktReady : in sl := '1'; + pktReady : in sl := '1'; linkReady : out sl; linkDown : out sl; linkErrorOut : out sl; @@ -49,8 +49,8 @@ end entity Pgp4RxProtocolWrapper; architecture rtl of Pgp4RxProtocolWrapper is - signal pgpRxIn : Pgp4RxInType := PGP4_RX_IN_INIT_C; - signal pgpRxOut : Pgp4RxOutType := PGP4_RX_OUT_INIT_C; + signal pgpRxIn : Pgp4RxInType := PGP4_RX_IN_INIT_C; + signal pgpRxOut : Pgp4RxOutType := PGP4_RX_OUT_INIT_C; signal pgpRxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal pgpRxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; signal remRxFifoCtrl : AxiStreamCtrlArray(0 downto 0); From 24066dd16fed73351d939c38cb8423d5805a7bc7 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 30 Apr 2026 09:35:55 -0700 Subject: [PATCH 71/92] Remove kcode check from eb wrapper tests. --- .../pgp4/core/wrappers/Pgp4RxEbWrapper.vhd | 38 +++------------- tests/protocols/pgp/pgp4/test_Pgp4RxEb.py | 45 +++++-------------- 2 files changed, 17 insertions(+), 66 deletions(-) diff --git a/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd b/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd index 71ca3bcad0..d52d7aca64 100644 --- a/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd +++ b/protocols/pgp/pgp4/core/wrappers/Pgp4RxEbWrapper.vhd @@ -20,8 +20,7 @@ use surf.StdRtlPkg.all; entity Pgp4RxEbWrapper is generic ( - SKIP_EN_G : boolean := true; - CHECK_K_CODE_G : boolean := false); + SKIP_EN_G : boolean := true); port ( phyClk : in sl; pgpClk : in sl; @@ -41,44 +40,19 @@ end entity Pgp4RxEbWrapper; architecture rtl of Pgp4RxEbWrapper is - signal checkedValid : sl; - signal checkedData : slv(63 downto 0); - signal checkedHeader : slv(1 downto 0); - signal checkedError : sl; - begin - GEN_CHECK_K_CODE : if (CHECK_K_CODE_G = true) generate - U_Checker : entity surf.Pgp4RxKCodeChecker - port map ( - phyRxClk => phyClk, - phyRxRst => rst, - phyRxValid => phyRxValid, - phyRxData => phyRxData, - phyRxHeader => phyRxHeader, - checkedValid => checkedValid, - checkedData => checkedData, - checkedHeader => checkedHeader, - linkError => checkedError); - end generate GEN_CHECK_K_CODE; - - GEN_NO_CHECK_K_CODE : if (CHECK_K_CODE_G = false) generate - checkedValid <= phyRxValid; - checkedData <= phyRxData; - checkedHeader <= phyRxHeader; - checkedError <= phyRxLinkError; - end generate GEN_NO_CHECK_K_CODE; - + -- DUT instantiation U_DUT : entity surf.Pgp4RxEb generic map ( SKIP_EN_G => SKIP_EN_G) port map ( phyRxClk => phyClk, phyRxRst => rst, - phyRxValid => checkedValid, - phyRxData => checkedData, - phyRxHeader => checkedHeader, - phyRxLinkError => checkedError, + phyRxValid => phyRxValid, + phyRxData => phyRxData, + phyRxHeader => phyRxHeader, + phyRxLinkError => phyRxLinkError, pgpRxClk => pgpClk, pgpRxRst => rst, pgpRxValid => pgpRxValid, diff --git a/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py b/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py index 4e7f71f419..611a962aad 100644 --- a/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py +++ b/tests/protocols/pgp/pgp4/test_Pgp4RxEb.py @@ -10,11 +10,11 @@ # Test methodology: # - Sweep: Run the direct `Pgp4RxEb` wrapper in three asynchronous clock modes -# plus one same-clock, skip-disabled mode with the K-code checker enabled. +# plus one same-clock, skip-disabled passthrough mode. # - Stimulus: Drive ordered mixes of data words, valid K-words, SKP words, and # reset/overflow stress bursts directly into the PHY side of the elastic -# buffer. The skip-disabled mode drives a malformed K-word followed -# immediately by data to cover the no-elastic-buffer link-error corner case. +# buffer. The skip-disabled mode drives a data word with an external link +# error pulse to cover the no-elastic-buffer passthrough contract. # - Checks: The DUT must forward non-SKP traffic in order, suppress SKP while # still updating `remLinkData`, flush buffered data on reset, and pulse # `overflow` when sustained write pressure outruns the read domain. @@ -39,19 +39,13 @@ from tests.protocols.pgp.pgp4.pgp4_test_utils import ( PGP4_D_HEADER, PGP4_K_HEADER, - PGP4_USER, initialize_signals, pgp4_idle_word, - pgp4_kword, pgp4_skip_word, - pgp4_user_word, signal_int, ) from tests.protocols.pgp.pgp_test_utils import run_pgp_wrapper_test -K_CODE_CSC_LSB = 48 -USER_OPCODE_PAYLOAD = 0x0000CAFEBABE - class Pgp4RxEbTB: """Dual-clock harness for the elastic-buffer wrapper. @@ -156,14 +150,16 @@ def initialize_phy_inputs(dut): initialize_signals(dut, phyRxValid=0, phyRxData=0, phyRxHeader=0, phyRxLinkError=0) -async def send_phy_word(tb: Pgp4RxEbTB, *, header: int, data: int): +async def send_phy_word(tb: Pgp4RxEbTB, *, header: int, data: int, link_error: int = 0): """Launch one PHY-side word for exactly one recovered-clock cycle.""" tb.dut.phyRxHeader.value = header tb.dut.phyRxData.value = data + tb.dut.phyRxLinkError.value = link_error tb.dut.phyRxValid.value = 1 await tb.cycle_phy() tb.dut.phyRxValid.value = 0 + tb.dut.phyRxLinkError.value = 0 async def send_phy_words(tb: Pgp4RxEbTB, words: list[tuple[int, int]]): @@ -171,14 +167,6 @@ async def send_phy_words(tb: Pgp4RxEbTB, words: list[tuple[int, int]]): await send_phy_word(tb, header=header, data=data) -def bad_kcode_checksum_word() -> int: - """Build a real USER K-word and corrupt only its checksum field.""" - - good_user_word = pgp4_user_word(USER_OPCODE_PAYLOAD) - assert good_user_word == pgp4_kword(PGP4_USER, USER_OPCODE_PAYLOAD) - return good_user_word ^ (1 << K_CODE_CSC_LSB) - - def env_parameters_from(parameters: dict[str, object]) -> dict[str, object]: return { key: value @@ -313,7 +301,7 @@ async def pgp4_rx_eb_overflow_pulses_when_phy_outpaces_local_clock(dut): @cocotb.test() -async def pgp4_rx_eb_skip_disabled_bubbles_after_link_error(dut): +async def pgp4_rx_eb_skip_disabled_passes_stream_and_link_error(dut): tb = Pgp4RxEbTB(dut) if not env_flag("EXPECT_SKIP_DISABLED", default=False): return @@ -331,21 +319,11 @@ async def pgp4_rx_eb_skip_disabled_bubbles_after_link_error(dut): cocotb.start_soon(collector.run()) cocotb.start_soon(link_error_monitor.run()) - data_word_a = 0x1111222233334444 - bad_user_word = bad_kcode_checksum_word() - suppressed_word = 0x5555666677778888 - data_word_b = 0x9999AAAABBBBCCCC - - await send_phy_word(tb, header=PGP4_D_HEADER, data=data_word_a) - await send_phy_word(tb, header=PGP4_K_HEADER, data=bad_user_word) - await send_phy_word(tb, header=PGP4_D_HEADER, data=suppressed_word) - await send_phy_word(tb, header=PGP4_D_HEADER, data=data_word_b) + data_word = 0x123456789ABCDEF0 + await send_phy_word(tb, header=PGP4_D_HEADER, data=data_word, link_error=1) - words = await wait_for_collected_beats(collector, count=2, step=tb.cycle_pgp, cycles=64) - assert words == [ - (PGP4_D_HEADER, data_word_a), - (PGP4_D_HEADER, data_word_b), - ] + words = await wait_for_collected_beats(collector, count=1, step=tb.cycle_pgp, cycles=64) + assert words == [(PGP4_D_HEADER, data_word)] assert link_error_monitor.seen @@ -371,7 +349,6 @@ async def pgp4_rx_eb_skip_disabled_bubbles_after_link_error(dut): parameter_case( "same_clock_skip_disabled", SKIP_EN_G=False, - CHECK_K_CODE_G=True, PHY_CLK_PERIOD_NS="4.000", PGP_CLK_PERIOD_NS="4.000", COMMON_CLK="1", From 49f333ba090e464d0cdd051b6b7a032df1e4fae0 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 1 May 2026 09:26:52 -0700 Subject: [PATCH 72/92] Run emacs beautify on VHDL. --- .../AxiLiteCrossbarIpIntegrator.vhd | 22 +- .../AxiLiteFifoPopIpIntegrator.vhd | 2 +- .../AxiLiteFifoPushIpIntegrator.vhd | 2 +- .../AxiLiteFifoPushPopIpIntegrator.vhd | 12 +- ...AxiLiteRamSyncStatusVectorIpIntegrator.vhd | 8 +- .../AxiLiteRingBufferIpIntegrator.vhd | 2 +- .../AxiLiteSequencerRamIpIntegrator.vhd | 2 +- .../AxiLiteWriteFilterIpIntegrator.vhd | 22 +- .../AxiStreamBatchingFifoIpIntegrator.vhd | 2 +- .../AxiStreamCombinerIpIntegrator.vhd | 8 +- .../AxiStreamCompactIpIntegrator.vhd | 2 +- .../AxiStreamConcatIpIntegrator.vhd | 2 +- .../AxiStreamDeMuxIpIntegrator.vhd | 14 +- .../AxiStreamFifoV2IpIntegrator.vhd | 68 ++-- .../AxiStreamFlushIpIntegrator.vhd | 10 +- .../AxiStreamFrameRateLimiterIpIntegrator.vhd | 16 +- .../AxiStreamGearboxIpIntegrator.vhd | 4 +- .../AxiStreamGearboxPackIpIntegrator.vhd | 2 +- .../AxiStreamGearboxUnpackIpIntegrator.vhd | 2 +- .../AxiStreamMonAxiLIpIntegrator.vhd | 74 ++-- .../AxiStreamMonIpIntegrator.vhd | 46 +-- .../AxiStreamMuxIpIntegrator.vhd | 8 +- .../AxiStreamPipelineIpIntegrator.vhd | 2 +- .../AxiStreamPrbsFlowCtrlIpIntegrator.vhd | 2 +- .../AxiStreamRepeaterIpIntegrator.vhd | 8 +- .../AxiStreamResizeIpIntegrator.vhd | 2 +- .../AxiStreamRingBufferIpIntegrator.vhd | 76 ++--- .../AxiStreamScatterGatherIpIntegrator.vhd | 82 ++--- .../AxiStreamShiftIpIntegrator.vhd | 2 +- .../AxiStreamSplitterIpIntegrator.vhd | 8 +- .../AxiStreamTapIpIntegrator.vhd | 2 +- .../AxiStreamTimerIpIntegrator.vhd | 30 +- .../AxiStreamTrailerAppendIpIntegrator.vhd | 2 +- .../AxiStreamTrailerRemoveIpIntegrator.vhd | 12 +- axi/axi-stream/rtl/AxiStreamBatchingFifo.vhd | 110 +++--- axi/axi-stream/rtl/AxiStreamTimer.vhd | 41 +-- axi/axi-stream/tb/AxiStreamBatchingFifoTb.vhd | 56 +-- .../AxiMemTesterIpIntegrator.vhd | 104 +++--- .../ip_integrator/AxiMonAxiLIpIntegrator.vhd | 76 ++--- axi/axi4/ip_integrator/AxiRamIpIntegrator.vhd | 108 +++--- .../ip_integrator/AxiRateGenIpIntegrator.vhd | 130 +++---- .../AxiReadEmulateIpIntegrator.vhd | 98 +++--- .../AxiReadPathFifoIpIntegrator.vhd | 278 +++++++-------- .../AxiReadPathMuxIpIntegrator.vhd | 290 ++++++++-------- .../ip_integrator/AxiResizeIpIntegrator.vhd | 198 +++++------ .../AxiRingBufferIpIntegrator.vhd | 112 +++--- .../AxiWriteEmulateIpIntegrator.vhd | 98 +++--- .../AxiWritePathFifoIpIntegrator.vhd | 202 +++++------ .../AxiWritePathMuxIpIntegrator.vhd | 290 ++++++++-------- axi/axi4/rtl/AxiResize.vhd | 36 +- .../AxiToAxiLiteIpIntegrator.vhd | 114 +++---- .../SlvArraytoAxiLiteIpIntegrator.vhd | 2 +- .../AxiStreamDmaFifoIpIntegrator.vhd | 44 +-- .../AxiStreamDmaIpIntegrator.vhd | 50 +-- .../AxiStreamDmaReadIpIntegrator.vhd | 106 +++--- .../AxiStreamDmaRingReadIpIntegrator.vhd | 110 +++--- .../AxiStreamDmaRingWriteIpIntegrator.vhd | 260 +++++++------- .../AxiStreamDmaV2DescIpIntegrator.vhd | 136 ++++---- .../AxiStreamDmaV2FifoIpIntegrator.vhd | 104 +++--- .../AxiStreamDmaV2IpIntegrator.vhd | 74 ++-- .../AxiStreamDmaV2ReadIpIntegrator.vhd | 112 +++--- .../AxiStreamDmaV2WriteIpIntegrator.vhd | 158 ++++----- .../AxiStreamDmaV2WriteMuxIpIntegrator.vhd | 78 ++--- .../AxiStreamDmaWriteIpIntegrator.vhd | 202 +++++------ base/general/wrappers/DebouncerWrapper.vhd | 16 +- base/general/wrappers/HeartbeatWrapper.vhd | 8 +- base/sync/wrappers/SyncClockFreqWrapper.vhd | 18 +- .../ad9249/core/StreamPatternTester.vhd | 6 +- dsp/generic/fixed/FirFilterSingleChannel.vhd | 2 +- .../FirFilterMultiChannelCacheTestWrapper.vhd | 24 +- .../FirFilterMultiChannelTestWrapper.vhd | 24 +- .../FirFilterSingleChannelWrapper.vhd | 8 +- .../wrappers/EthMacFlowCtrlWrapper.vhd | 10 +- .../EthMacImportExportLoopbackWrapper.vhd | 37 +- .../wrappers/EthMacRxBypassWrapper.vhd | 87 ++--- .../wrappers/EthMacRxCsumWrapper.vhd | 27 +- .../wrappers/EthMacRxFifoWrapper.vhd | 96 +++--- .../wrappers/EthMacRxFilterWrapper.vhd | 75 ++-- .../wrappers/EthMacRxLoopbackWrapper.vhd | 165 ++++----- .../wrappers/EthMacRxPauseWrapper.vhd | 25 +- .../wrappers/EthMacRxShiftWrapper.vhd | 63 ++-- .../wrappers/EthMacTopLoopbackWrapper.vhd | 119 +++---- .../wrappers/EthMacTxBypassWrapper.vhd | 96 +++--- .../wrappers/EthMacTxCsumLoopbackWrapper.vhd | 81 ++--- .../wrappers/EthMacTxFifoWrapper.vhd | 82 ++--- .../wrappers/EthMacTxLoopbackWrapper.vhd | 52 +-- .../wrappers/EthMacTxPauseWrapper.vhd | 27 +- .../wrappers/EthMacTxShiftWrapper.vhd | 65 ++-- .../IpV4Engine/wrappers/ArpEngineWrapper.vhd | 153 ++++----- .../IpV4Engine/wrappers/IcmpEngineWrapper.vhd | 25 +- .../wrappers/IgmpV2EngineWrapper.vhd | 25 +- .../wrappers/IpV4EngineDeMuxWrapper.vhd | 37 +- .../wrappers/IpV4EngineRxWrapper.vhd | 45 +-- .../wrappers/IpV4EngineTopWrapper.vhd | 201 +++++------ .../wrappers/IpV4EngineTxWrapper.vhd | 99 +++--- .../wrappers/RawEthFramerFlatWrapper.vhd | 76 +++-- .../wrappers/RawEthFramerPairFlatWrapper.vhd | 148 ++++---- .../wrappers/RawEthFramerRxFlatWrapper.vhd | 75 ++-- .../wrappers/RawEthFramerTxFlatWrapper.vhd | 73 ++-- .../wrappers/EthMacPrepareForICrcWrapper.vhd | 11 +- .../wrappers/EthMacRxCheckICrcWrapper.vhd | 27 +- .../RoCEv2/wrappers/EthMacRxRoCEv2Wrapper.vhd | 7 +- .../RoCEv2/wrappers/EthMacTxRoCEv2Wrapper.vhd | 11 +- .../wrappers/RoceConfiguratorWrapper.vhd | 56 +-- .../RoceResizeAndSwapIpIntegrator.vhd | 2 +- .../wrappers/UdpEngineArpFlatWrapper.vhd | 77 ++--- .../wrappers/UdpEngineDhcpFlatWrapper.vhd | 25 +- .../wrappers/UdpEngineRxFlatWrapper.vhd | 73 ++-- .../wrappers/UdpEngineTopFlatWrapper.vhd | 154 +++++---- .../wrappers/UdpEngineTxFlatWrapper.vhd | 98 +++--- .../wrappers/UdpEngineWrapperFlatWrapper.vhd | 319 +++++++++--------- .../coaxpress/core/rtl/CoaXPressRxHsFsm.vhd | 2 +- .../wrappers/EventFrameSequencerWrapper.vhd | 30 +- .../wrappers/HammingEccWrapper.vhd | 2 +- protocols/line-codes/rtl/Code12b14bPkg.vhd | 2 +- .../wrappers/Code10b12bPkgWrapper.vhd | 2 +- .../wrappers/Code12b14bPkgWrapper.vhd | 2 +- .../wrappers/Code8b10bPkgWrapper.vhd | 2 +- .../pgp2b/core/wrappers/Pgp2bAxiWrapper.vhd | 6 +- .../pgp2b/core/wrappers/Pgp2bLaneWrapper.vhd | 4 +- .../core/wrappers/Pgp2bRxCellWrapper.vhd | 32 +- .../pgp2b/core/wrappers/Pgp2bRxPhyWrapper.vhd | 44 +-- .../core/wrappers/Pgp2bTxCellWrapper.vhd | 38 +-- .../pgp2b/core/wrappers/Pgp2bTxPhyWrapper.vhd | 30 +- .../core/wrappers/Pgp2bTxSchedWrapper.vhd | 30 +- .../pgp2b/core/wrappers/Pgp2bTxWrapper.vhd | 38 +-- .../Pgp2fcAlignmentControllerWrapper.vhd | 40 +-- .../pgp2fc/core/wrappers/Pgp2fcAxiWrapper.vhd | 6 +- .../core/wrappers/Pgp2fcLaneWrapper.vhd | 16 +- .../core/wrappers/Pgp2fcRxPhyWrapper.vhd | 16 +- .../core/wrappers/Pgp2fcTxCellWrapper.vhd | 54 +-- .../core/wrappers/Pgp2fcTxPhyWrapper.vhd | 22 +- .../core/wrappers/Pgp2fcTxSchedWrapper.vhd | 32 +- .../pgp2fc/core/wrappers/Pgp2fcTxWrapper.vhd | 25 +- .../shared/wrappers/PgpRxVcFifoWrapper.vhd | 60 ++-- protocols/srp/wrappers/SrpV3AxiWrapper.vhd | 36 +- protocols/ssi/tb/SsiFifoTb.vhd | 10 +- .../ssi/wrappers/SsiAxiLiteMasterWrapper.vhd | 77 ++--- .../ssi/wrappers/SsiCmdMasterWrapper.vhd | 19 +- protocols/ssi/wrappers/SsiDbgTapWrapper.vhd | 35 +- protocols/ssi/wrappers/SsiFifoWrapper.vhd | 45 +-- .../ssi/wrappers/SsiFrameLimiterWrapper.vhd | 29 +- .../ssi/wrappers/SsiIbFrameFilterWrapper.vhd | 69 ++-- .../ssi/wrappers/SsiIncrementingTxWrapper.vhd | 16 +- .../ssi/wrappers/SsiInsertSofWrapper.vhd | 77 ++--- .../ssi/wrappers/SsiObFrameFilterWrapper.vhd | 73 ++-- protocols/ssi/wrappers/SsiPrbsWrapper.vhd | 22 +- .../ssi/wrappers/SsiResizeFifoEofeWrapper.vhd | 12 +- 148 files changed, 4242 insertions(+), 4178 deletions(-) diff --git a/axi/axi-lite/ip_integrator/AxiLiteCrossbarIpIntegrator.vhd b/axi/axi-lite/ip_integrator/AxiLiteCrossbarIpIntegrator.vhd index 0d34dd689e..ddc95f716e 100644 --- a/axi/axi-lite/ip_integrator/AxiLiteCrossbarIpIntegrator.vhd +++ b/axi/axi-lite/ip_integrator/AxiLiteCrossbarIpIntegrator.vhd @@ -46,7 +46,7 @@ end entity AxiLiteCrossbarIpIntegrator; architecture mapping of AxiLiteCrossbarIpIntegrator is - constant NUM_AXIL_MASTERS_C : positive := 2; + constant NUM_AXIL_MASTERS_C : positive := 2; constant AXIL_XBAR_CONFIG_C : AxiLiteCrossbarMasterConfigArray(NUM_AXIL_MASTERS_C-1 downto 0) := genAxiLiteConfig(NUM_AXIL_MASTERS_C, x"0000_0000", 22, 20); constant NUM_CASCADE_MASTERS_C : positive := 2; @@ -60,16 +60,16 @@ architecture mapping of AxiLiteCrossbarIpIntegrator is addrBits => 17, connectivity => X"0001")); - signal axilClk : sl; - signal axilRst : sl; - signal axilReadMaster : AxiLiteReadMasterType; - signal axilReadSlave : AxiLiteReadSlaveType; - signal axilWriteMaster : AxiLiteWriteMasterType; - signal axilWriteSlave : AxiLiteWriteSlaveType; - signal axilReadMasters : AxiLiteReadMasterArray(NUM_AXIL_MASTERS_C-1 downto 0); - signal axilReadSlaves : AxiLiteReadSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_DECERR_C); - signal axilWriteMasters : AxiLiteWriteMasterArray(NUM_AXIL_MASTERS_C-1 downto 0); - signal axilWriteSlaves : AxiLiteWriteSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C); + signal axilClk : sl; + signal axilRst : sl; + signal axilReadMaster : AxiLiteReadMasterType; + signal axilReadSlave : AxiLiteReadSlaveType; + signal axilWriteMaster : AxiLiteWriteMasterType; + signal axilWriteSlave : AxiLiteWriteSlaveType; + signal axilReadMasters : AxiLiteReadMasterArray(NUM_AXIL_MASTERS_C-1 downto 0); + signal axilReadSlaves : AxiLiteReadSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_DECERR_C); + signal axilWriteMasters : AxiLiteWriteMasterArray(NUM_AXIL_MASTERS_C-1 downto 0); + signal axilWriteSlaves : AxiLiteWriteSlaveArray(NUM_AXIL_MASTERS_C-1 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C); signal cascadeReadMasters : AxiLiteReadMasterArray(NUM_CASCADE_MASTERS_C-1 downto 0); signal cascadeReadSlaves : AxiLiteReadSlaveArray(NUM_CASCADE_MASTERS_C-1 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_DECERR_C); signal cascadeWriteMasters : AxiLiteWriteMasterArray(NUM_CASCADE_MASTERS_C-1 downto 0); diff --git a/axi/axi-lite/ip_integrator/AxiLiteFifoPopIpIntegrator.vhd b/axi/axi-lite/ip_integrator/AxiLiteFifoPopIpIntegrator.vhd index eea036792e..9b06c8f4fe 100644 --- a/axi/axi-lite/ip_integrator/AxiLiteFifoPopIpIntegrator.vhd +++ b/axi/axi-lite/ip_integrator/AxiLiteFifoPopIpIntegrator.vhd @@ -55,7 +55,7 @@ end entity AxiLiteFifoPopIpIntegrator; architecture rtl of AxiLiteFifoPopIpIntegrator is - signal axilResetN : sl := '1'; + signal axilResetN : sl := '1'; signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; diff --git a/axi/axi-lite/ip_integrator/AxiLiteFifoPushIpIntegrator.vhd b/axi/axi-lite/ip_integrator/AxiLiteFifoPushIpIntegrator.vhd index 1b46c2144d..686c0e864b 100644 --- a/axi/axi-lite/ip_integrator/AxiLiteFifoPushIpIntegrator.vhd +++ b/axi/axi-lite/ip_integrator/AxiLiteFifoPushIpIntegrator.vhd @@ -51,7 +51,7 @@ end entity AxiLiteFifoPushIpIntegrator; architecture rtl of AxiLiteFifoPushIpIntegrator is - signal axilResetN : sl := '1'; + signal axilResetN : sl := '1'; signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; diff --git a/axi/axi-lite/ip_integrator/AxiLiteFifoPushPopIpIntegrator.vhd b/axi/axi-lite/ip_integrator/AxiLiteFifoPushPopIpIntegrator.vhd index 91b94d24e4..27dff17ee2 100644 --- a/axi/axi-lite/ip_integrator/AxiLiteFifoPushPopIpIntegrator.vhd +++ b/axi/axi-lite/ip_integrator/AxiLiteFifoPushPopIpIntegrator.vhd @@ -59,7 +59,7 @@ end entity AxiLiteFifoPushPopIpIntegrator; architecture rtl of AxiLiteFifoPushPopIpIntegrator is - signal axilResetN : sl := '1'; + signal axilResetN : sl := '1'; signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; @@ -159,11 +159,11 @@ begin --------------------------------------------------------------------------- -- Flatten the single exposed FIFO lanes --------------------------------------------------------------------------- - popFifoValid <= popFifoValidVec(0); - loopFifoValid <= loopFifoValidVec(0); + popFifoValid <= popFifoValidVec(0); + loopFifoValid <= loopFifoValidVec(0); loopFifoAEmpty <= loopFifoAEmptyVec(0); - loopFifoAFull <= loopFifoAFullVec(0); - pushFifoValid <= pushFifoValidVec(0); - pushFifoDout <= pushFifoDoutVec(0); + loopFifoAFull <= loopFifoAFullVec(0); + pushFifoValid <= pushFifoValidVec(0); + pushFifoDout <= pushFifoDoutVec(0); end architecture rtl; diff --git a/axi/axi-lite/ip_integrator/AxiLiteRamSyncStatusVectorIpIntegrator.vhd b/axi/axi-lite/ip_integrator/AxiLiteRamSyncStatusVectorIpIntegrator.vhd index 8a42df122a..2649f57ffa 100644 --- a/axi/axi-lite/ip_integrator/AxiLiteRamSyncStatusVectorIpIntegrator.vhd +++ b/axi/axi-lite/ip_integrator/AxiLiteRamSyncStatusVectorIpIntegrator.vhd @@ -52,7 +52,7 @@ end entity AxiLiteRamSyncStatusVectorIpIntegrator; architecture rtl of AxiLiteRamSyncStatusVectorIpIntegrator is - signal axilResetN : sl := '1'; + signal axilResetN : sl := '1'; signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; @@ -105,9 +105,9 @@ begin --------------------------------------------------------------------------- U_DUT : entity surf.AxiLiteRamSyncStatusVector generic map ( - COMMON_CLK_G => true, - CNT_WIDTH_G => 8, - WIDTH_G => 4) + COMMON_CLK_G => true, + CNT_WIDTH_G => 8, + WIDTH_G => 4) port map ( wrClk => wrClk, wrRst => wrRst, diff --git a/axi/axi-lite/ip_integrator/AxiLiteRingBufferIpIntegrator.vhd b/axi/axi-lite/ip_integrator/AxiLiteRingBufferIpIntegrator.vhd index 12394d22e2..002066d6d6 100644 --- a/axi/axi-lite/ip_integrator/AxiLiteRingBufferIpIntegrator.vhd +++ b/axi/axi-lite/ip_integrator/AxiLiteRingBufferIpIntegrator.vhd @@ -60,7 +60,7 @@ end entity AxiLiteRingBufferIpIntegrator; architecture rtl of AxiLiteRingBufferIpIntegrator is - signal axilResetN : sl := '1'; + signal axilResetN : sl := '1'; signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; diff --git a/axi/axi-lite/ip_integrator/AxiLiteSequencerRamIpIntegrator.vhd b/axi/axi-lite/ip_integrator/AxiLiteSequencerRamIpIntegrator.vhd index 871832daab..c7f717a5f7 100644 --- a/axi/axi-lite/ip_integrator/AxiLiteSequencerRamIpIntegrator.vhd +++ b/axi/axi-lite/ip_integrator/AxiLiteSequencerRamIpIntegrator.vhd @@ -76,7 +76,7 @@ end entity AxiLiteSequencerRamIpIntegrator; architecture rtl of AxiLiteSequencerRamIpIntegrator is - signal sAxiAResetN : sl := '1'; + signal sAxiAResetN : sl := '1'; signal sAxilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; signal sAxilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; signal sAxilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; diff --git a/axi/axi-lite/ip_integrator/AxiLiteWriteFilterIpIntegrator.vhd b/axi/axi-lite/ip_integrator/AxiLiteWriteFilterIpIntegrator.vhd index 949cd17755..ce67091b7d 100644 --- a/axi/axi-lite/ip_integrator/AxiLiteWriteFilterIpIntegrator.vhd +++ b/axi/axi-lite/ip_integrator/AxiLiteWriteFilterIpIntegrator.vhd @@ -73,17 +73,17 @@ end entity AxiLiteWriteFilterIpIntegrator; architecture rtl of AxiLiteWriteFilterIpIntegrator is - constant FILTER_ADDR_C : Slv32Array(FILTER_SIZE_G-1 downto 0) := (0 => toSlv(FILTER_ADDR_0_G, 32), others => toSlv(FILTER_ADDR_0_G, 32)); - signal sAxiAResetN : sl := '1'; - signal mAxiAResetN : sl := '1'; - signal sAxilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; - signal sAxilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; - signal sAxilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; - signal sAxilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; - signal mAxilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; - signal mAxilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; - signal mAxilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; - signal mAxilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + constant FILTER_ADDR_C : Slv32Array(FILTER_SIZE_G-1 downto 0) := (0 => toSlv(FILTER_ADDR_0_G, 32), others => toSlv(FILTER_ADDR_0_G, 32)); + signal sAxiAResetN : sl := '1'; + signal mAxiAResetN : sl := '1'; + signal sAxilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal sAxilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal sAxilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal sAxilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + signal mAxilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal mAxilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal mAxilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal mAxilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; begin diff --git a/axi/axi-stream/ip_integrator/AxiStreamBatchingFifoIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamBatchingFifoIpIntegrator.vhd index aa5953a20c..28e628437d 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamBatchingFifoIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamBatchingFifoIpIntegrator.vhd @@ -74,7 +74,7 @@ architecture rtl of AxiStreamBatchingFifoIpIntegrator is TUSER_BITS_C => 1, TUSER_MODE_C => TUSER_NORMAL_C); - signal axiResetN : sl := '1'; + signal axiResetN : sl := '1'; signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; diff --git a/axi/axi-stream/ip_integrator/AxiStreamCombinerIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamCombinerIpIntegrator.vhd index 0e88ca2865..f7d1936503 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamCombinerIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamCombinerIpIntegrator.vhd @@ -75,11 +75,11 @@ architecture rtl of AxiStreamCombinerIpIntegrator is TUSER_BITS_C => TUSER_WIDTH_G, TUSER_MODE_C => TUSER_NORMAL_C); - signal axisAResetN : sl := '1'; + signal axisAResetN : sl := '1'; signal sAxisMasters : AxiStreamMasterArray(1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal sAxisSlaves : AxiStreamSlaveArray(1 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal sAxisSlaves : AxiStreamSlaveArray(1 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; begin diff --git a/axi/axi-stream/ip_integrator/AxiStreamCompactIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamCompactIpIntegrator.vhd index fe6d93b55a..699c3c2b0e 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamCompactIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamCompactIpIntegrator.vhd @@ -69,7 +69,7 @@ architecture rtl of AxiStreamCompactIpIntegrator is TUSER_BITS_C => TUSER_WIDTH_G, TUSER_MODE_C => TUSER_NORMAL_C); - signal axisAResetN : sl := '1'; + signal axisAResetN : sl := '1'; signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; diff --git a/axi/axi-stream/ip_integrator/AxiStreamConcatIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamConcatIpIntegrator.vhd index d18c715803..36ce217606 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamConcatIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamConcatIpIntegrator.vhd @@ -68,7 +68,7 @@ architecture rtl of AxiStreamConcatIpIntegrator is TUSER_BITS_C => TUSER_WIDTH_G, TUSER_MODE_C => TUSER_FIRST_LAST_C); - signal axisAResetN : sl := '1'; + signal axisAResetN : sl := '1'; signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; diff --git a/axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd index 18aa2353d0..e641476876 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd @@ -71,13 +71,13 @@ architecture rtl of AxiStreamDeMuxIpIntegrator is 0 => toSlv(TDEST_ROUTE_0_G, 8), 1 => toSlv(TDEST_ROUTE_1_G, 8)); - signal axisAResetN : sl := '1'; - signal dynamicRouteMasks : Slv8Array(1 downto 0) := (others => (others => '0')); - signal dynamicRouteDests : Slv8Array(1 downto 0) := (others => (others => '0')); - signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal mAxisMasters : AxiStreamMasterArray(1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal mAxisSlaves : AxiStreamSlaveArray(1 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal axisAResetN : sl := '1'; + signal dynamicRouteMasks : Slv8Array(1 downto 0) := (others => (others => '0')); + signal dynamicRouteDests : Slv8Array(1 downto 0) := (others => (others => '0')); + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAxisMasters : AxiStreamMasterArray(1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal mAxisSlaves : AxiStreamSlaveArray(1 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); begin diff --git a/axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd index 74027e35be..bf1eb81b7e 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd @@ -26,59 +26,59 @@ use surf.AxiStreamPkg.all; entity AxiStreamFifoV2IpIntegrator is generic ( -- IP Integrator Slave AXI Stream Configuration - S_INTERFACENAME : string := "S_AXIS"; - S_HAS_TLAST : natural range 0 to 1 := 1; - S_HAS_TKEEP : natural range 0 to 1 := 1; - S_HAS_TSTRB : natural range 0 to 1 := 0; - S_HAS_TREADY : natural range 0 to 1 := 1; - S_TUSER_WIDTH : natural range 1 to 8 := 2; - S_TID_WIDTH : natural range 1 to 8 := 1; - S_TDEST_WIDTH : natural range 1 to 8 := 1; - S_TDATA_NUM_BYTES : natural range 1 to 128 := 1; + S_INTERFACENAME : string := "S_AXIS"; + S_HAS_TLAST : natural range 0 to 1 := 1; + S_HAS_TKEEP : natural range 0 to 1 := 1; + S_HAS_TSTRB : natural range 0 to 1 := 0; + S_HAS_TREADY : natural range 0 to 1 := 1; + S_TUSER_WIDTH : natural range 1 to 8 := 2; + S_TID_WIDTH : natural range 1 to 8 := 1; + S_TDEST_WIDTH : natural range 1 to 8 := 1; + S_TDATA_NUM_BYTES : natural range 1 to 128 := 1; -- IP Integrator Master AXI Stream Configuration - M_INTERFACENAME : string := "M_AXIS"; - M_HAS_TLAST : natural range 0 to 1 := 1; - M_HAS_TKEEP : natural range 0 to 1 := 1; - M_HAS_TSTRB : natural range 0 to 1 := 0; - M_HAS_TREADY : natural range 0 to 1 := 1; - M_TUSER_WIDTH : natural range 1 to 8 := 2; - M_TID_WIDTH : natural range 1 to 8 := 1; - M_TDEST_WIDTH : natural range 1 to 8 := 1; - M_TDATA_NUM_BYTES : natural range 1 to 128 := 1; + M_INTERFACENAME : string := "M_AXIS"; + M_HAS_TLAST : natural range 0 to 1 := 1; + M_HAS_TKEEP : natural range 0 to 1 := 1; + M_HAS_TSTRB : natural range 0 to 1 := 0; + M_HAS_TREADY : natural range 0 to 1 := 1; + M_TUSER_WIDTH : natural range 1 to 8 := 2; + M_TID_WIDTH : natural range 1 to 8 := 1; + M_TDEST_WIDTH : natural range 1 to 8 := 1; + M_TDATA_NUM_BYTES : natural range 1 to 128 := 1; -- General Configurations - RST_ASYNC : boolean := false; - INT_PIPE_STAGES : natural range 0 to 16 := 0; -- Internal FIFO setting - PIPE_STAGES : natural range 0 to 16 := 1; - VALID_BURST_MODE : boolean := false; -- only used in VALID_THOLD_G>1 - VALID_THOLD : integer range 0 to (2**24) := 1; -- =1 = normal operation + RST_ASYNC : boolean := false; + INT_PIPE_STAGES : natural range 0 to 16 := 0; -- Internal FIFO setting + PIPE_STAGES : natural range 0 to 16 := 1; + VALID_BURST_MODE : boolean := false; -- only used in VALID_THOLD_G>1 + VALID_THOLD : integer range 0 to (2**24) := 1; -- =1 = normal operation -- =0 = only when frame ready -- >1 = only when frame ready or # entries -- FIFO configurations - GEN_SYNC_FIFO : boolean := false; - FIFO_ADDR_WIDTH : integer range 4 to 48 := 9; - FIFO_FIXED_THRESH : boolean := true; - FIFO_PAUSE_THRESH : integer range 1 to (2**24) := 1; - SYNTH_MODE : string := "inferred"; - MEMORY_TYPE : string := "block"; + GEN_SYNC_FIFO : boolean := false; + FIFO_ADDR_WIDTH : integer range 4 to 48 := 9; + FIFO_FIXED_THRESH : boolean := true; + FIFO_PAUSE_THRESH : integer range 1 to (2**24) := 1; + SYNTH_MODE : string := "inferred"; + MEMORY_TYPE : string := "block"; -- Internal FIFO width select, "WIDE", "NARROW" or "CUSTOM" -- WIDE uses wider of slave / master. NARROW uses narrower. -- CUSOTM uses passed FIFO_DATA_WIDTH_G - INT_WIDTH_SELECT : string := "WIDE"; - INT_DATA_WIDTH : natural range 1 to 16 := 16; + INT_WIDTH_SELECT : string := "WIDE"; + INT_DATA_WIDTH : natural range 1 to 16 := 16; -- If VALID_THOLD_G /=1, FIFO that stores on tLast txns can be smaller. -- Set to 0 for same size as primary fifo (default) -- Set >4 for custom size. -- Use at own risk. Overflow of tLast fifo is not checked - LAST_FIFO_ADDR_WIDTH : integer range 0 to 48 := 0; + LAST_FIFO_ADDR_WIDTH : integer range 0 to 48 := 0; -- Index = 0 is output, index = n is input - CASCADE_PAUSE_SEL : integer range 0 to (2**24) := 0; - CASCADE_SIZE : integer range 1 to (2**24) := 1); + CASCADE_PAUSE_SEL : integer range 0 to (2**24) := 0; + CASCADE_SIZE : integer range 1 to (2**24) := 1); port ( -- IP Integrator Slave AXI Stream Interface S_AXIS_ACLK : in std_logic := '0'; diff --git a/axi/axi-stream/ip_integrator/AxiStreamFlushIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamFlushIpIntegrator.vhd index 8b81687d05..bc6800796f 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamFlushIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamFlushIpIntegrator.vhd @@ -61,7 +61,7 @@ architecture rtl of AxiStreamFlushIpIntegrator is TUSER_BITS_C => TUSER_WIDTH_G, TUSER_MODE_C => TUSER_NORMAL_C); - signal axisAResetN : sl := '1'; + signal axisAResetN : sl := '1'; signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; @@ -133,11 +133,11 @@ begin U_DUT : entity surf.AxiStreamFlush generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, RST_POLARITY_G => RST_POLARITY_G, - RST_ASYNC_G => RST_ASYNC_G, - AXIS_CONFIG_G => AXIS_CONFIG_C, - SSI_EN_G => SSI_EN_G) + RST_ASYNC_G => RST_ASYNC_G, + AXIS_CONFIG_G => AXIS_CONFIG_C, + SSI_EN_G => SSI_EN_G) port map ( axisClk => axisClk, axisRst => axisRst, diff --git a/axi/axi-stream/ip_integrator/AxiStreamFrameRateLimiterIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamFrameRateLimiterIpIntegrator.vhd index 833c95807e..575fdd2bc8 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamFrameRateLimiterIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamFrameRateLimiterIpIntegrator.vhd @@ -88,13 +88,13 @@ architecture rtl of AxiStreamFrameRateLimiterIpIntegrator is TUSER_BITS_C => TUSER_WIDTH_G, TUSER_MODE_C => TUSER_NORMAL_C); - signal axisAResetN : sl := '1'; - signal sAxiAResetN : sl := '1'; - signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal mAxisCtrl : AxiStreamCtrlType := AXI_STREAM_CTRL_UNUSED_C; + signal axisAResetN : sl := '1'; + signal sAxiAResetN : sl := '1'; + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAxisCtrl : AxiStreamCtrlType := AXI_STREAM_CTRL_UNUSED_C; signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; @@ -105,7 +105,7 @@ begin axisAResetN <= not axisRst when (RST_POLARITY_G = '1') else axisRst; sAxiAResetN <= not axilRst when (RST_POLARITY_G = '1') else axilRst; - mAxisCtrl.pause <= M_AXIS_PAUSE; + mAxisCtrl.pause <= M_AXIS_PAUSE; mAxisCtrl.overflow <= '0'; U_ShimLayerSlave : entity surf.SlaveAxiStreamIpIntegrator diff --git a/axi/axi-stream/ip_integrator/AxiStreamGearboxIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamGearboxIpIntegrator.vhd index d783f02568..a8eb522f18 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamGearboxIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamGearboxIpIntegrator.vhd @@ -89,8 +89,8 @@ architecture mapping of AxiStreamGearboxIpIntegrator is signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; signal mAxisMaster : AxiStreamMasterType := axiStreamMasterInit(M_AXI_CONFIG_C); signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal axisClk : sl := '0'; - signal axisRst : sl := '0'; + signal axisClk : sl := '0'; + signal axisRst : sl := '0'; begin diff --git a/axi/axi-stream/ip_integrator/AxiStreamGearboxPackIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamGearboxPackIpIntegrator.vhd index d5beabcc24..96e6b61533 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamGearboxPackIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamGearboxPackIpIntegrator.vhd @@ -59,7 +59,7 @@ architecture rtl of AxiStreamGearboxPackIpIntegrator is tUserBits => TUSER_WIDTH_G, tIdBits => 8); - signal axisAResetN : sl := '1'; + signal axisAResetN : sl := '1'; signal rawAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal rawAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal packedAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; diff --git a/axi/axi-stream/ip_integrator/AxiStreamGearboxUnpackIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamGearboxUnpackIpIntegrator.vhd index 8692e23e13..beb250282f 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamGearboxUnpackIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamGearboxUnpackIpIntegrator.vhd @@ -59,7 +59,7 @@ architecture rtl of AxiStreamGearboxUnpackIpIntegrator is tUserBits => TUSER_WIDTH_G, tIdBits => 8); - signal axisAResetN : sl := '1'; + signal axisAResetN : sl := '1'; signal packedAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal packedAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal rawAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; diff --git a/axi/axi-stream/ip_integrator/AxiStreamMonAxiLIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamMonAxiLIpIntegrator.vhd index 79fa87e688..2f64484f3c 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamMonAxiLIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamMonAxiLIpIntegrator.vhd @@ -22,37 +22,37 @@ use surf.AxiStreamPkg.all; entity AxiStreamMonAxiLIpIntegrator is port ( - axisClk : in sl; - axisRst : in sl; - S_AXIS_TVALID : in sl; - S_AXIS_TDATA : in slv(31 downto 0); - S_AXIS_TKEEP : in slv(3 downto 0); - S_AXIS_TLAST : in sl; - S_AXIS_TDEST : in slv(0 downto 0); - S_AXIS_TID : in slv(0 downto 0); - S_AXIS_TUSER : in slv(0 downto 0); - S_AXIS_TREADY : out sl; - axilClk : in sl; - axilRst : in sl; - S_AXI_AWADDR : in slv(5 downto 0); - S_AXI_AWPROT : in slv(2 downto 0); - S_AXI_AWVALID : in sl; - S_AXI_AWREADY : out sl; - S_AXI_WDATA : in slv(31 downto 0); - S_AXI_WSTRB : in slv(3 downto 0); - S_AXI_WVALID : in sl; - S_AXI_WREADY : out sl; - S_AXI_BRESP : out slv(1 downto 0); - S_AXI_BVALID : out sl; - S_AXI_BREADY : in sl; - S_AXI_ARADDR : in slv(5 downto 0); - S_AXI_ARPROT : in slv(2 downto 0); - S_AXI_ARVALID : in sl; - S_AXI_ARREADY : out sl; - S_AXI_RDATA : out slv(31 downto 0); - S_AXI_RRESP : out slv(1 downto 0); - S_AXI_RVALID : out sl; - S_AXI_RREADY : in sl); + axisClk : in sl; + axisRst : in sl; + S_AXIS_TVALID : in sl; + S_AXIS_TDATA : in slv(31 downto 0); + S_AXIS_TKEEP : in slv(3 downto 0); + S_AXIS_TLAST : in sl; + S_AXIS_TDEST : in slv(0 downto 0); + S_AXIS_TID : in slv(0 downto 0); + S_AXIS_TUSER : in slv(0 downto 0); + S_AXIS_TREADY : out sl; + axilClk : in sl; + axilRst : in sl; + S_AXI_AWADDR : in slv(5 downto 0); + S_AXI_AWPROT : in slv(2 downto 0); + S_AXI_AWVALID : in sl; + S_AXI_AWREADY : out sl; + S_AXI_WDATA : in slv(31 downto 0); + S_AXI_WSTRB : in slv(3 downto 0); + S_AXI_WVALID : in sl; + S_AXI_WREADY : out sl; + S_AXI_BRESP : out slv(1 downto 0); + S_AXI_BVALID : out sl; + S_AXI_BREADY : in sl; + S_AXI_ARADDR : in slv(5 downto 0); + S_AXI_ARPROT : in slv(2 downto 0); + S_AXI_ARVALID : in sl; + S_AXI_ARREADY : out sl; + S_AXI_RDATA : out slv(31 downto 0); + S_AXI_RRESP : out slv(1 downto 0); + S_AXI_RVALID : out sl; + S_AXI_RREADY : in sl); end entity AxiStreamMonAxiLIpIntegrator; architecture rtl of AxiStreamMonAxiLIpIntegrator is @@ -66,14 +66,14 @@ architecture rtl of AxiStreamMonAxiLIpIntegrator is TUSER_BITS_C => 1, TUSER_MODE_C => TUSER_NORMAL_C); - signal axisResetN : sl := '1'; - signal axilResetN : sl := '1'; + signal axisResetN : sl := '1'; + signal axilResetN : sl := '1'; signal axisMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); signal axisSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; - signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; - signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; - signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; begin diff --git a/axi/axi-stream/ip_integrator/AxiStreamMonIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamMonIpIntegrator.vhd index 42e370de25..8054e572cf 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamMonIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamMonIpIntegrator.vhd @@ -23,27 +23,27 @@ entity AxiStreamMonIpIntegrator is generic ( TPD_G : time := 1 ns); port ( - axiClk : in sl; - axiRst : in sl; - axisReady : in sl; - S_AXIS_TVALID : in sl; - S_AXIS_TDATA : in slv(31 downto 0); - S_AXIS_TKEEP : in slv(3 downto 0); - S_AXIS_TLAST : in sl; - S_AXIS_TDEST : in slv(0 downto 0); - S_AXIS_TID : in slv(0 downto 0); - S_AXIS_TUSER : in slv(0 downto 0); - S_AXIS_TREADY : out sl; - frameCnt : out slv(63 downto 0); - frameSize : out slv(31 downto 0); - frameSizeMax : out slv(31 downto 0); - frameSizeMin : out slv(31 downto 0); - frameRate : out slv(31 downto 0); - frameRateMax : out slv(31 downto 0); - frameRateMin : out slv(31 downto 0); - bandwidth : out slv(63 downto 0); - bandwidthMax : out slv(63 downto 0); - bandwidthMin : out slv(63 downto 0)); + axiClk : in sl; + axiRst : in sl; + axisReady : in sl; + S_AXIS_TVALID : in sl; + S_AXIS_TDATA : in slv(31 downto 0); + S_AXIS_TKEEP : in slv(3 downto 0); + S_AXIS_TLAST : in sl; + S_AXIS_TDEST : in slv(0 downto 0); + S_AXIS_TID : in slv(0 downto 0); + S_AXIS_TUSER : in slv(0 downto 0); + S_AXIS_TREADY : out sl; + frameCnt : out slv(63 downto 0); + frameSize : out slv(31 downto 0); + frameSizeMax : out slv(31 downto 0); + frameSizeMin : out slv(31 downto 0); + frameRate : out slv(31 downto 0); + frameRateMax : out slv(31 downto 0); + frameRateMin : out slv(31 downto 0); + bandwidth : out slv(63 downto 0); + bandwidthMax : out slv(63 downto 0); + bandwidthMin : out slv(63 downto 0)); end entity AxiStreamMonIpIntegrator; architecture rtl of AxiStreamMonIpIntegrator is @@ -57,7 +57,7 @@ architecture rtl of AxiStreamMonIpIntegrator is TUSER_BITS_C => 1, TUSER_MODE_C => TUSER_NORMAL_C); - signal axiResetN : sl := '1'; + signal axiResetN : sl := '1'; signal axisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal axisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; @@ -66,7 +66,7 @@ begin --------------------------------------------------------------------------- -- AXI-Stream shim --------------------------------------------------------------------------- - axiResetN <= not axiRst; + axiResetN <= not axiRst; axisSlave.tReady <= axisReady; U_S_AXIS : entity surf.SlaveAxiStreamIpIntegrator diff --git a/axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd index ec417ce70b..2bdd0922ce 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd @@ -80,11 +80,11 @@ architecture rtl of AxiStreamMuxIpIntegrator is 0 => toSlv(TID_ROUTE_0_G, 8), 1 => toSlv(TID_ROUTE_1_G, 8)); - signal axisAResetN : sl := '1'; + signal axisAResetN : sl := '1'; signal sAxisMasters : AxiStreamMasterArray(1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal sAxisSlaves : AxiStreamSlaveArray(1 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal sAxisSlaves : AxiStreamSlaveArray(1 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; begin diff --git a/axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd index cb3f5c83ea..4512a34c58 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd @@ -50,7 +50,7 @@ end entity AxiStreamPipelineIpIntegrator; architecture rtl of AxiStreamPipelineIpIntegrator is - signal axisAResetN : sl := '1'; + signal axisAResetN : sl := '1'; signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; diff --git a/axi/axi-stream/ip_integrator/AxiStreamPrbsFlowCtrlIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamPrbsFlowCtrlIpIntegrator.vhd index d3f482532e..cb70d7b048 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamPrbsFlowCtrlIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamPrbsFlowCtrlIpIntegrator.vhd @@ -51,7 +51,7 @@ end entity AxiStreamPrbsFlowCtrlIpIntegrator; architecture rtl of AxiStreamPrbsFlowCtrlIpIntegrator is - signal axisAResetN : sl := '1'; + signal axisAResetN : sl := '1'; signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; diff --git a/axi/axi-stream/ip_integrator/AxiStreamRepeaterIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamRepeaterIpIntegrator.vhd index 24b6d97534..302d3ce154 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamRepeaterIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamRepeaterIpIntegrator.vhd @@ -60,11 +60,11 @@ end entity AxiStreamRepeaterIpIntegrator; architecture rtl of AxiStreamRepeaterIpIntegrator is - signal axisAResetN : sl := '1'; - signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal axisAResetN : sl := '1'; + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal mAxisMasters : AxiStreamMasterArray(1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal mAxisSlaves : AxiStreamSlaveArray(1 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal mAxisSlaves : AxiStreamSlaveArray(1 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); begin diff --git a/axi/axi-stream/ip_integrator/AxiStreamResizeIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamResizeIpIntegrator.vhd index 76a1be9fe7..d945da7539 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamResizeIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamResizeIpIntegrator.vhd @@ -70,7 +70,7 @@ architecture rtl of AxiStreamResizeIpIntegrator is TUSER_BITS_C => 1, TUSER_MODE_C => TUSER_NORMAL_C); - signal axisAResetN : sl := '1'; + signal axisAResetN : sl := '1'; signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; diff --git a/axi/axi-stream/ip_integrator/AxiStreamRingBufferIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamRingBufferIpIntegrator.vhd index a9b8e447f6..d01ead1ce4 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamRingBufferIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamRingBufferIpIntegrator.vhd @@ -25,42 +25,42 @@ entity AxiStreamRingBufferIpIntegrator is generic ( TPD_G : time := 1 ns); port ( - dataClk : in sl; - dataRst : in sl; - dataValid : in sl; - dataValue : in slv(15 downto 0); - extTrig : in sl; - axilClk : in sl; - axilRst : in sl; - axisClk : in sl; - axisRst : in sl; - S_AXI_AWADDR : in slv(7 downto 0); - S_AXI_AWPROT : in slv(2 downto 0); - S_AXI_AWVALID : in sl; - S_AXI_AWREADY : out sl; - S_AXI_WDATA : in slv(31 downto 0); - S_AXI_WSTRB : in slv(3 downto 0); - S_AXI_WVALID : in sl; - S_AXI_WREADY : out sl; - S_AXI_BRESP : out slv(1 downto 0); - S_AXI_BVALID : out sl; - S_AXI_BREADY : in sl; - S_AXI_ARADDR : in slv(7 downto 0); - S_AXI_ARPROT : in slv(2 downto 0); - S_AXI_ARVALID : in sl; - S_AXI_ARREADY : out sl; - S_AXI_RDATA : out slv(31 downto 0); - S_AXI_RRESP : out slv(1 downto 0); - S_AXI_RVALID : out sl; - S_AXI_RREADY : in sl; - M_AXIS_TVALID : out sl; - M_AXIS_TDATA : out slv(15 downto 0); - M_AXIS_TKEEP : out slv(1 downto 0); - M_AXIS_TLAST : out sl; - M_AXIS_TDEST : out slv(0 downto 0); - M_AXIS_TID : out slv(0 downto 0); - M_AXIS_TUSER : out slv(1 downto 0); - M_AXIS_TREADY : in sl); + dataClk : in sl; + dataRst : in sl; + dataValid : in sl; + dataValue : in slv(15 downto 0); + extTrig : in sl; + axilClk : in sl; + axilRst : in sl; + axisClk : in sl; + axisRst : in sl; + S_AXI_AWADDR : in slv(7 downto 0); + S_AXI_AWPROT : in slv(2 downto 0); + S_AXI_AWVALID : in sl; + S_AXI_AWREADY : out sl; + S_AXI_WDATA : in slv(31 downto 0); + S_AXI_WSTRB : in slv(3 downto 0); + S_AXI_WVALID : in sl; + S_AXI_WREADY : out sl; + S_AXI_BRESP : out slv(1 downto 0); + S_AXI_BVALID : out sl; + S_AXI_BREADY : in sl; + S_AXI_ARADDR : in slv(7 downto 0); + S_AXI_ARPROT : in slv(2 downto 0); + S_AXI_ARVALID : in sl; + S_AXI_ARREADY : out sl; + S_AXI_RDATA : out slv(31 downto 0); + S_AXI_RRESP : out slv(1 downto 0); + S_AXI_RVALID : out sl; + S_AXI_RREADY : in sl; + M_AXIS_TVALID : out sl; + M_AXIS_TDATA : out slv(15 downto 0); + M_AXIS_TKEEP : out slv(1 downto 0); + M_AXIS_TLAST : out sl; + M_AXIS_TDEST : out slv(0 downto 0); + M_AXIS_TID : out slv(0 downto 0); + M_AXIS_TUSER : out slv(1 downto 0); + M_AXIS_TREADY : in sl); end entity AxiStreamRingBufferIpIntegrator; architecture rtl of AxiStreamRingBufferIpIntegrator is @@ -71,8 +71,8 @@ architecture rtl of AxiStreamRingBufferIpIntegrator is tUserBits => 2, tIdBits => 1); - signal axilResetN : sl := '1'; - signal axisResetN : sl := '1'; + signal axilResetN : sl := '1'; + signal axisResetN : sl := '1'; signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; diff --git a/axi/axi-stream/ip_integrator/AxiStreamScatterGatherIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamScatterGatherIpIntegrator.vhd index 1c4420df8d..eb29e22b52 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamScatterGatherIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamScatterGatherIpIntegrator.vhd @@ -26,46 +26,46 @@ entity AxiStreamScatterGatherIpIntegrator is TPD_G : time := 1 ns; AXIS_SLAVE_FRAME_SIZE_G : integer := 129); port ( - axiClk : in sl; - axiRst : in sl; - sAxisPause : out sl; - sAxisOverflow : out sl; - sAxisIdle : out sl; - S_AXI_AWADDR : in slv(7 downto 0); - S_AXI_AWPROT : in slv(2 downto 0); - S_AXI_AWVALID : in sl; - S_AXI_AWREADY : out sl; - S_AXI_WDATA : in slv(31 downto 0); - S_AXI_WSTRB : in slv(3 downto 0); - S_AXI_WVALID : in sl; - S_AXI_WREADY : out sl; - S_AXI_BRESP : out slv(1 downto 0); - S_AXI_BVALID : out sl; - S_AXI_BREADY : in sl; - S_AXI_ARADDR : in slv(7 downto 0); - S_AXI_ARPROT : in slv(2 downto 0); - S_AXI_ARVALID : in sl; - S_AXI_ARREADY : out sl; - S_AXI_RDATA : out slv(31 downto 0); - S_AXI_RRESP : out slv(1 downto 0); - S_AXI_RVALID : out sl; - S_AXI_RREADY : in sl; - S_AXIS_TVALID : in sl; - S_AXIS_TDATA : in slv(15 downto 0); - S_AXIS_TKEEP : in slv(1 downto 0); - S_AXIS_TLAST : in sl; - S_AXIS_TDEST : in slv(0 downto 0); - S_AXIS_TID : in slv(0 downto 0); - S_AXIS_TUSER : in slv(1 downto 0); - S_AXIS_TREADY : out sl; - M_AXIS_TVALID : out sl; - M_AXIS_TDATA : out slv(95 downto 0); - M_AXIS_TKEEP : out slv(11 downto 0); - M_AXIS_TLAST : out sl; - M_AXIS_TDEST : out slv(0 downto 0); - M_AXIS_TID : out slv(0 downto 0); - M_AXIS_TUSER : out slv(1 downto 0); - M_AXIS_TREADY : in sl); + axiClk : in sl; + axiRst : in sl; + sAxisPause : out sl; + sAxisOverflow : out sl; + sAxisIdle : out sl; + S_AXI_AWADDR : in slv(7 downto 0); + S_AXI_AWPROT : in slv(2 downto 0); + S_AXI_AWVALID : in sl; + S_AXI_AWREADY : out sl; + S_AXI_WDATA : in slv(31 downto 0); + S_AXI_WSTRB : in slv(3 downto 0); + S_AXI_WVALID : in sl; + S_AXI_WREADY : out sl; + S_AXI_BRESP : out slv(1 downto 0); + S_AXI_BVALID : out sl; + S_AXI_BREADY : in sl; + S_AXI_ARADDR : in slv(7 downto 0); + S_AXI_ARPROT : in slv(2 downto 0); + S_AXI_ARVALID : in sl; + S_AXI_ARREADY : out sl; + S_AXI_RDATA : out slv(31 downto 0); + S_AXI_RRESP : out slv(1 downto 0); + S_AXI_RVALID : out sl; + S_AXI_RREADY : in sl; + S_AXIS_TVALID : in sl; + S_AXIS_TDATA : in slv(15 downto 0); + S_AXIS_TKEEP : in slv(1 downto 0); + S_AXIS_TLAST : in sl; + S_AXIS_TDEST : in slv(0 downto 0); + S_AXIS_TID : in slv(0 downto 0); + S_AXIS_TUSER : in slv(1 downto 0); + S_AXIS_TREADY : out sl; + M_AXIS_TVALID : out sl; + M_AXIS_TDATA : out slv(95 downto 0); + M_AXIS_TKEEP : out slv(11 downto 0); + M_AXIS_TLAST : out sl; + M_AXIS_TDEST : out slv(0 downto 0); + M_AXIS_TID : out slv(0 downto 0); + M_AXIS_TUSER : out slv(1 downto 0); + M_AXIS_TREADY : in sl); end entity AxiStreamScatterGatherIpIntegrator; architecture rtl of AxiStreamScatterGatherIpIntegrator is @@ -82,7 +82,7 @@ architecture rtl of AxiStreamScatterGatherIpIntegrator is tUserBits => 2, tIdBits => 1); - signal axiResetN : sl := '1'; + signal axiResetN : sl := '1'; signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; diff --git a/axi/axi-stream/ip_integrator/AxiStreamShiftIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamShiftIpIntegrator.vhd index a448742ad8..cb3fc0eecc 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamShiftIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamShiftIpIntegrator.vhd @@ -64,7 +64,7 @@ architecture rtl of AxiStreamShiftIpIntegrator is TUSER_BITS_C => TUSER_WIDTH_G, TUSER_MODE_C => TUSER_NORMAL_C); - signal axisAResetN : sl := '1'; + signal axisAResetN : sl := '1'; signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; diff --git a/axi/axi-stream/ip_integrator/AxiStreamSplitterIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamSplitterIpIntegrator.vhd index 7e6377ffaa..caffa28dfe 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamSplitterIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamSplitterIpIntegrator.vhd @@ -75,11 +75,11 @@ architecture rtl of AxiStreamSplitterIpIntegrator is TUSER_BITS_C => TUSER_WIDTH_G, TUSER_MODE_C => TUSER_NORMAL_C); - signal axisAResetN : sl := '1'; - signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal axisAResetN : sl := '1'; + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal mAxisMasters : AxiStreamMasterArray(1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal mAxisSlaves : AxiStreamSlaveArray(1 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal mAxisSlaves : AxiStreamSlaveArray(1 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); begin diff --git a/axi/axi-stream/ip_integrator/AxiStreamTapIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamTapIpIntegrator.vhd index 20e42b8dcd..54cd5974b4 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamTapIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamTapIpIntegrator.vhd @@ -68,7 +68,7 @@ end entity AxiStreamTapIpIntegrator; architecture rtl of AxiStreamTapIpIntegrator is - signal axisAResetN : sl := '1'; + signal axisAResetN : sl := '1'; signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal tsAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; diff --git a/axi/axi-stream/ip_integrator/AxiStreamTimerIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamTimerIpIntegrator.vhd index 6dc5ece0a2..c940285c31 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamTimerIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamTimerIpIntegrator.vhd @@ -64,29 +64,29 @@ end entity AxiStreamTimerIpIntegrator; architecture rtl of AxiStreamTimerIpIntegrator is - signal axilResetN : sl := '1'; - signal streamMasters : AxiStreamMasterArray(NUM_STREAMS_G-1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal streamSlaves : AxiStreamSlaveArray(NUM_STREAMS_G-1 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; - signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; - signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; - signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + signal axilResetN : sl := '1'; + signal streamMasters : AxiStreamMasterArray(NUM_STREAMS_G-1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal streamSlaves : AxiStreamSlaveArray(NUM_STREAMS_G-1 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; begin axilResetN <= not axilRst; - streamMasters(0).tValid <= S0_AXIS_TVALID; + streamMasters(0).tValid <= S0_AXIS_TVALID; streamMasters(0).tData(DATA_BYTES_G*8-1 downto 0) <= S0_AXIS_TDATA; - streamMasters(0).tKeep(DATA_BYTES_G-1 downto 0) <= S0_AXIS_TKEEP; - streamMasters(0).tLast <= S0_AXIS_TLAST; - streamSlaves(0).tReady <= S0_AXIS_TREADY; + streamMasters(0).tKeep(DATA_BYTES_G-1 downto 0) <= S0_AXIS_TKEEP; + streamMasters(0).tLast <= S0_AXIS_TLAST; + streamSlaves(0).tReady <= S0_AXIS_TREADY; - streamMasters(1).tValid <= S1_AXIS_TVALID; + streamMasters(1).tValid <= S1_AXIS_TVALID; streamMasters(1).tData(DATA_BYTES_G*8-1 downto 0) <= S1_AXIS_TDATA; - streamMasters(1).tKeep(DATA_BYTES_G-1 downto 0) <= S1_AXIS_TKEEP; - streamMasters(1).tLast <= S1_AXIS_TLAST; - streamSlaves(1).tReady <= S1_AXIS_TREADY; + streamMasters(1).tKeep(DATA_BYTES_G-1 downto 0) <= S1_AXIS_TKEEP; + streamMasters(1).tLast <= S1_AXIS_TLAST; + streamSlaves(1).tReady <= S1_AXIS_TREADY; U_ShimLayerSlave : entity surf.SlaveAxiLiteIpIntegrator generic map ( diff --git a/axi/axi-stream/ip_integrator/AxiStreamTrailerAppendIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamTrailerAppendIpIntegrator.vhd index df91a07e45..67bd5b7f64 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamTrailerAppendIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamTrailerAppendIpIntegrator.vhd @@ -77,7 +77,7 @@ architecture rtl of AxiStreamTrailerAppendIpIntegrator is TUSER_BITS_C => TUSER_WIDTH_G, TUSER_MODE_C => TUSER_NORMAL_C); - signal axisAResetN : sl := '1'; + signal axisAResetN : sl := '1'; signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal sAxisTrailerMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; diff --git a/axi/axi-stream/ip_integrator/AxiStreamTrailerRemoveIpIntegrator.vhd b/axi/axi-stream/ip_integrator/AxiStreamTrailerRemoveIpIntegrator.vhd index 3efe9bf29f..bd6c027ea2 100644 --- a/axi/axi-stream/ip_integrator/AxiStreamTrailerRemoveIpIntegrator.vhd +++ b/axi/axi-stream/ip_integrator/AxiStreamTrailerRemoveIpIntegrator.vhd @@ -59,7 +59,7 @@ architecture rtl of AxiStreamTrailerRemoveIpIntegrator is TUSER_BITS_C => 2, TUSER_MODE_C => TUSER_NORMAL_C); - signal axisAResetN : sl := '1'; + signal axisAResetN : sl := '1'; signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; @@ -127,12 +127,12 @@ begin U_DUT : entity surf.AxiStreamTrailerRemove generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, RST_POLARITY_G => RST_POLARITY_G, - RST_ASYNC_G => RST_ASYNC_G, - PIPE_STAGES_G => PIPE_STAGES_G, - BYTES_TO_RM_G => BYTES_TO_RM_G, - AXI_CONFIG_G => AXI_CONFIG_C) + RST_ASYNC_G => RST_ASYNC_G, + PIPE_STAGES_G => PIPE_STAGES_G, + BYTES_TO_RM_G => BYTES_TO_RM_G, + AXI_CONFIG_G => AXI_CONFIG_C) port map ( axisClk => axisClk, axisRst => axisRst, diff --git a/axi/axi-stream/rtl/AxiStreamBatchingFifo.vhd b/axi/axi-stream/rtl/AxiStreamBatchingFifo.vhd index 45ca87291d..de1198f63d 100644 --- a/axi/axi-stream/rtl/AxiStreamBatchingFifo.vhd +++ b/axi/axi-stream/rtl/AxiStreamBatchingFifo.vhd @@ -26,14 +26,14 @@ use surf.AxiLitePkg.all; entity AxiStreamBatchingFifo is generic ( - -- General Configurations + -- General Configurations TPD_G : time := 1 ns; FIFO_ADDR_WIDTH_G : integer range 4 to 48 := 9; - -- AXI Stream Port Configurations + -- AXI Stream Port Configurations SLAVE_AXI_CONFIG_G : AxiStreamConfigType; MASTER_AXI_CONFIG_G : AxiStreamConfigType); port ( - -- Control Port + -- Control Port axilClk : in sl; axilRst : in sl; sAxilWriteMaster : in AxiLiteWriteMasterType; @@ -41,17 +41,17 @@ entity AxiStreamBatchingFifo is sAxilReadMaster : in AxiLiteReadMasterType; sAxilReadSlave : out AxiLiteReadSlaveType; - -- Slave Port - sAxisClk : in sl; - sAxisRst : in sl; - sAxisMaster : in AxiStreamMasterType; - sAxisSlave : out AxiStreamSlaveType; - - -- Master Port - mAxisClk : in sl; - mAxisRst : in sl; - mAxisMaster : out AxiStreamMasterType; - mAxisSlave : in AxiStreamSlaveType); + -- Slave Port + sAxisClk : in sl; + sAxisRst : in sl; + sAxisMaster : in AxiStreamMasterType; + sAxisSlave : out AxiStreamSlaveType; + + -- Master Port + mAxisClk : in sl; + mAxisRst : in sl; + mAxisMaster : out AxiStreamMasterType; + mAxisSlave : in AxiStreamSlaveType); end AxiStreamBatchingFifo; architecture rtl of AxiStreamBatchingFifo is @@ -76,7 +76,7 @@ architecture rtl of AxiStreamBatchingFifo is frameBatched => (others => '0'), frameToSend => (others => '0'), sending => '0' - ); + ); signal r : RegType := REG_INIT_C; signal rin : RegType; @@ -91,11 +91,12 @@ architecture rtl of AxiStreamBatchingFifo is begin - ---------------------------------- - ------- CONTROL INTERFACE ------- - ---------------------------------- + ---------------------------------- + ------- CONTROL INTERFACE ------- + ---------------------------------- - comb_axil : process (sAxilReadMaster, sAxilWriteMaster, axilRst, rAxilWriteSlave, rAxilReadSlave, batchSizeAxiL) is + comb_axil : process (axilRst, batchSizeAxiL, rAxilReadSlave, + rAxilWriteSlave, sAxilReadMaster, sAxilWriteMaster) is variable vAxilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; variable vAxilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; variable regCon : AxiLiteEndPointType; @@ -111,7 +112,7 @@ begin axiSlaveWaitTxn(regCon, sAxilWriteMaster, sAxilReadMaster, vAxilWriteSlave, vAxilReadSlave); -- Read batch size - axiSlaveRegister(regCon, "0000", 0, vBatchSize); -- 2-bit wide because only one reg + axiSlaveRegister(regCon, "0000", 0, vBatchSize); -- 2-bit wide because only one reg -- Closeout the transaction axiSlaveDefault(regCon, vAxilWriteSlave, vAxilReadSlave, AXI_RESP_DECERR_C); @@ -141,25 +142,25 @@ begin end if; end process seq_axil; - ---------------------------------- - ----- END CONTROL INTERFACE ----- - ---------------------------------- + ---------------------------------- + ----- END CONTROL INTERFACE ----- + ---------------------------------- - ---------------------------------- - ----- CLOCK DOMAIN CROSSINGS ----- - ---------------------------------- - -- All control signals need to be brought into the mAxisClk domain - -- State of the main FIFO becomes more consistent + ---------------------------------- + ----- CLOCK DOMAIN CROSSINGS ----- + ---------------------------------- + -- All control signals need to be brought into the mAxisClk domain + -- State of the main FIFO becomes more consistent U_Axis_CDC : entity surf.AxiStreamFifoV2 generic map( TPD_G => TPD_G, MEMORY_TYPE_G => "auto", GEN_SYNC_FIFO_G => false, - FIFO_ADDR_WIDTH_G => 5, -- Shallow, just for sync + FIFO_ADDR_WIDTH_G => 5, -- Shallow, just for sync SLAVE_AXI_CONFIG_G => SLAVE_AXI_CONFIG_G, - MASTER_AXI_CONFIG_G => SLAVE_AXI_CONFIG_G) -- Do not change shape + MASTER_AXI_CONFIG_G => SLAVE_AXI_CONFIG_G) -- Do not change shape port map( sAxisClk => sAxisClk, sAxisRst => sAxisRst, @@ -169,7 +170,7 @@ begin mAxisClk => mAxisClk, mAxisRst => mAxisRst, mAxisMaster => axisMasterSync, - mAxisSlave => axisSlaveSync ); + mAxisSlave => axisSlaveSync); U_BatchSize_CDC : entity surf.SynchronizerFifo generic map( @@ -177,19 +178,19 @@ begin DATA_WIDTH_G => 32, INIT_G => x"0000_0001") port map( - wr_clk => axilClk, - din => batchSizeAxiL, - rd_clk => mAxisClk, - dout => batchSize); + wr_clk => axilClk, + din => batchSizeAxiL, + rd_clk => mAxisClk, + dout => batchSize); - ---------------------------------- - --- END CLOCK DOMAIN CROSSINGS --- - ---------------------------------- + ---------------------------------- + --- END CLOCK DOMAIN CROSSINGS --- + ---------------------------------- - ---------------------------------- - --------- MAIN DATA FIFO --------- - ---------------------------------- + ---------------------------------- + --------- MAIN DATA FIFO --------- + ---------------------------------- U_Data_FIFO : entity surf.AxiStreamFifoV2 generic map( @@ -199,24 +200,24 @@ begin SLAVE_AXI_CONFIG_G => SLAVE_AXI_CONFIG_G, MASTER_AXI_CONFIG_G => MASTER_AXI_CONFIG_G) port map( - -- Slave Port + -- Slave Port sAxisClk => mAxisClk, sAxisRst => mAxisRst, sAxisMaster => axisMasterSync, sAxisSlave => axisSlaveSync, - -- Master Port + -- Master Port mAxisClk => mAxisClk, mAxisRst => mAxisRst, mAxisMaster => axisMasterFifo, - mAxisSlave => axisSlaveFifo ); + mAxisSlave => axisSlaveFifo); - ---------------------------------- - ------- END MAIN DATA FIFO ------- - ---------------------------------- + ---------------------------------- + ------- END MAIN DATA FIFO ------- + ---------------------------------- - -- These signals are not responsible for hanshakes and can - -- just be forwarded + -- These signals are not responsible for hanshakes and can + -- just be forwarded combAxisMaster.tData <= axisMasterFifo.tData; combAxisMaster.tStrb <= axisMasterFifo.tStrb; combAxisMaster.tKeep <= axisMasterFifo.tKeep; @@ -225,7 +226,8 @@ begin combAxisMaster.tId <= axisMasterFifo.tId; combAxisMaster.tUser <= axisMasterFifo.tUser; - comb : process (r, axisMasterFifo, axisSlaveFifo, axisMasterSync, axisSlaveSync, batchSize, combAxisSlave) is + comb : process (axisMasterFifo, axisMasterSync, axisSlaveFifo, + axisSlaveSync, batchSize, combAxisSlave, r) is variable v : RegType; variable isAcceptedFrame : sl; variable isOutputFrame : sl; @@ -246,7 +248,7 @@ begin if isOutputFrame = '1' then v.frameBatched := v.frameBatched - 1; - v.frameToSend := r.frameToSend - 1; + v.frameToSend := r.frameToSend - 1; end if; if v.frameToSend = 0 then @@ -258,8 +260,8 @@ begin v.frameToSend := batchSize; end if; - combAxisMaster.tValid <= r.sending and axisMasterFifo.tValid; - axisSlaveFifo.tReady <= r.sending and combAxisSlave.tReady; + combAxisMaster.tValid <= r.sending and axisMasterFifo.tValid; + axisSlaveFifo.tReady <= r.sending and combAxisSlave.tReady; rin <= v; end process comb; @@ -279,7 +281,7 @@ begin -- AxiStream by adding a pipeline stage U_Output_Pipeline : entity surf.AxiStreamPipeline generic map( - TPD_G => TPD_G) + TPD_G => TPD_G) port map( axisClk => mAxisClk, axisRst => mAxisRst, diff --git a/axi/axi-stream/rtl/AxiStreamTimer.vhd b/axi/axi-stream/rtl/AxiStreamTimer.vhd index 2a37126e13..c1f93ef215 100644 --- a/axi/axi-stream/rtl/AxiStreamTimer.vhd +++ b/axi/axi-stream/rtl/AxiStreamTimer.vhd @@ -27,16 +27,16 @@ use surf.AxiStreamPkg.all; entity AxiStreamTimer is generic ( - TPD_G : time := 1 ns; - NUM_STREAMS_G : integer range 1 to 8 := 1; - NUM_EVENT_G : integer range 1 to 16 := 1 - ); + TPD_G : time := 1 ns; + NUM_STREAMS_G : integer range 1 to 8 := 1; + NUM_EVENT_G : integer range 1 to 16 := 1 + ); port ( -- AXI-Stream interfaces - axisClk : in sl; - axisRst : in sl; - streamMasters : in AxiStreamMasterArray(NUM_STREAMS_G-1 downto 0); - streamSlaves : in AxiStreamSlaveArray(NUM_STREAMS_G-1 downto 0); + axisClk : in sl; + axisRst : in sl; + streamMasters : in AxiStreamMasterArray(NUM_STREAMS_G-1 downto 0); + streamSlaves : in AxiStreamSlaveArray(NUM_STREAMS_G-1 downto 0); -- AXI-Lite Interface axilClk : in sl; @@ -45,12 +45,12 @@ entity AxiStreamTimer is axilReadSlave : out AxiLiteReadSlaveType; axilWriteMaster : in AxiLiteWriteMasterType; axilWriteSlave : out AxiLiteWriteSlaveType - ); + ); end AxiStreamTimer; architecture rtl of AxiStreamTimer is - -- Internal AXI Lite synced with axisClk + -- Internal AXI Lite synced with axisClk signal axilReadIntMaster : AxiLiteReadMasterType; signal axilReadIntSlave : AxiLiteReadSlaveType; signal axilWriteIntMaster : AxiLiteWriteMasterType; @@ -100,17 +100,17 @@ architecture rtl of AxiStreamTimer is -- Procedure used to monitor a single channel procedure monitorChannel( - timer : slv(31 downto 0); - axisMaster : in AxiStreamMasterType; - axisSlave : in AxiStreamSlaveType; - channel : in ChannelStateType; + timer : slv(31 downto 0); + axisMaster : in AxiStreamMasterType; + axisSlave : in AxiStreamSlaveType; + channel : in ChannelStateType; variable vchannel : inout ChannelStateType; variable notDoneSof : inout sl; variable notDoneEof : inout sl) is - variable handshake : sl; - variable hasSof : sl; - variable hasEof : sl; + variable handshake : sl; + variable hasSof : sl; + variable hasEof : sl; begin -- Find handshake handshake := axisMaster.tValid and axisSlave.tReady; @@ -139,18 +139,19 @@ architecture rtl of AxiStreamTimer is if (hasSof = '1' and notDoneSof = '1') then vchannel.timeSof(channel.sofIdx) := timer; - vchannel.sofIdx := channel.sofIdx + 1; + vchannel.sofIdx := channel.sofIdx + 1; end if; if (hasEof = '1' and notDoneEof = '1') then vchannel.timeEof(channel.eofIdx) := timer; - vchannel.eofIdx := channel.eofIdx + 1; + vchannel.eofIdx := channel.eofIdx + 1; end if; end procedure; begin - comb : process (streamMasters, streamSlaves, axisRst, r, axilWriteIntMaster, axilReadIntMaster) is + comb : process (axilReadIntMaster, axilWriteIntMaster, axisRst, r, + streamMasters, streamSlaves) is variable v : RegType; variable notDoneSofs : slv(NUM_STREAMS_G-1 downto 0); variable notDoneEofs : slv(NUM_STREAMS_G-1 downto 0); diff --git a/axi/axi-stream/tb/AxiStreamBatchingFifoTb.vhd b/axi/axi-stream/tb/AxiStreamBatchingFifoTb.vhd index f70437fe06..d939675d41 100644 --- a/axi/axi-stream/tb/AxiStreamBatchingFifoTb.vhd +++ b/axi/axi-stream/tb/AxiStreamBatchingFifoTb.vhd @@ -53,7 +53,7 @@ end AxiStreamBatchingFifoTb; architecture testbed of AxiStreamBatchingFifoTb is - -- Constants + -- Constants constant CLK_PERIOD_C : time := 4 ns; constant TPD_C : time := CLK_PERIOD_C/4; @@ -74,7 +74,7 @@ architecture testbed of AxiStreamBatchingFifoTb is TUSER_BITS_C => 0, TUSER_MODE_C => TUSER_NORMAL_C); - -- Signals + -- Signals signal toFifoMaster : AxiStreamMasterType; signal toFifoSlave : AxiStreamSlaveType; signal fromFifoMaster : AxiStreamMasterType; @@ -94,8 +94,8 @@ begin SLAVE_AXI_CONFIG_G => AXIS_RX_CONFIG_C, MASTER_AXI_CONFIG_G => AXIS_TX_CONFIG_C) port map ( - axilClk => clk, - axilRst => rst, + axilClk => clk, + axilRst => rst, sAxilWriteMaster => sAxilWriteMaster, sAxilWriteSlave => sAxilWriteSlave, sAxilReadMaster => sAxilReadMaster, @@ -111,32 +111,32 @@ begin mAxisMaster => fromFifoMaster, mAxisSlave => fromFifoSlave); - -- Map input AXI Stream - toFifoMaster.tValid <= s_axis_tvalid; - toFifoMaster.tLast <= s_axis_tlast; - toFifoMaster.tData(8*AXIS_RX_CONFIG_C.TDATA_BYTES_C-1 downto 0) <= s_axis_tdata; - s_axis_tready <= toFifoSlave.tReady; + -- Map input AXI Stream + toFifoMaster.tValid <= s_axis_tvalid; + toFifoMaster.tLast <= s_axis_tlast; + toFifoMaster.tData(8*AXIS_RX_CONFIG_C.TDATA_BYTES_C-1 downto 0) <= s_axis_tdata; + s_axis_tready <= toFifoSlave.tReady; - -- Continuous read of output AXI Stream + -- Continuous read of output AXI Stream fromFifoSlave.tReady <= '1'; - -- Map AXI LITE - sAxilWriteMaster.awaddr(3 downto 0) <= s_axil_AWADDR; - sAxilWriteMaster.awvalid <= s_axil_AWVALID; - sAxilWriteMaster.wdata <= s_axil_WDATA; - sAxilWriteMaster.wstrb <= s_axil_WSTRB; - sAxilWriteMaster.wvalid <= s_axil_WVALID; - sAxilWriteMaster.bready <= s_axil_BREADY; - sAxilReadMaster.araddr(3 downto 0) <= s_axil_ARADDR; - sAxilReadMaster.arvalid <= s_axil_ARVALID; - sAxilReadMaster.rready <= s_axil_RREADY; - s_axil_ARREADY <= sAxilReadSlave.arready; - s_axil_RDATA <= sAxilReadSlave.rdata; - s_axil_RRESP <= sAxilReadSlave.rresp; - s_axil_RVALID <= sAxilReadSlave.rvalid; - s_axil_AWREADY <= sAxilWriteSlave.awready; - s_axil_WREADY <= sAxilWriteSlave.wready; - s_axil_BRESP <= sAxilWriteSlave.bresp; - s_axil_BVALID <= sAxilWriteSlave.bvalid; + -- Map AXI LITE + sAxilWriteMaster.awaddr(3 downto 0) <= s_axil_AWADDR; + sAxilWriteMaster.awvalid <= s_axil_AWVALID; + sAxilWriteMaster.wdata <= s_axil_WDATA; + sAxilWriteMaster.wstrb <= s_axil_WSTRB; + sAxilWriteMaster.wvalid <= s_axil_WVALID; + sAxilWriteMaster.bready <= s_axil_BREADY; + sAxilReadMaster.araddr(3 downto 0) <= s_axil_ARADDR; + sAxilReadMaster.arvalid <= s_axil_ARVALID; + sAxilReadMaster.rready <= s_axil_RREADY; + s_axil_ARREADY <= sAxilReadSlave.arready; + s_axil_RDATA <= sAxilReadSlave.rdata; + s_axil_RRESP <= sAxilReadSlave.rresp; + s_axil_RVALID <= sAxilReadSlave.rvalid; + s_axil_AWREADY <= sAxilWriteSlave.awready; + s_axil_WREADY <= sAxilWriteSlave.wready; + s_axil_BRESP <= sAxilWriteSlave.bresp; + s_axil_BVALID <= sAxilWriteSlave.bvalid; end testbed; diff --git a/axi/axi4/ip_integrator/AxiMemTesterIpIntegrator.vhd b/axi/axi4/ip_integrator/AxiMemTesterIpIntegrator.vhd index b62d5a1236..3487407b92 100644 --- a/axi/axi4/ip_integrator/AxiMemTesterIpIntegrator.vhd +++ b/axi/axi4/ip_integrator/AxiMemTesterIpIntegrator.vhd @@ -105,10 +105,10 @@ architecture rtl of AxiMemTesterIpIntegrator is constant START_ADDR_C : slv(31 downto 0) := x"00000000"; constant STOP_ADDR_C : slv(31 downto 0) := x"00000FFF"; - signal axilResetN : sl := '1'; - signal axiResetN : sl := '1'; - signal mAxiAwLock : slv(1 downto 0) := (others => '0'); - signal mAxiArLock : slv(1 downto 0) := (others => '0'); + signal axilResetN : sl := '1'; + signal axiResetN : sl := '1'; + signal mAxiAwLock : slv(1 downto 0) := (others => '0'); + signal mAxiArLock : slv(1 downto 0) := (others => '0'); signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; @@ -171,54 +171,54 @@ begin ADDR_WIDTH => ADDR_WIDTH_G, DATA_WIDTH => DATA_BYTES_G*8) port map ( - M_AXI_ACLK => axiClk, - M_AXI_ARESETN => axiResetN, - M_AXI_AWID => M_AXI_AWID, - M_AXI_AWADDR => M_AXI_AWADDR, - M_AXI_AWLEN => M_AXI_AWLEN, - M_AXI_AWSIZE => M_AXI_AWSIZE, - M_AXI_AWBURST => M_AXI_AWBURST, - M_AXI_AWLOCK => mAxiAwLock, - M_AXI_AWCACHE => M_AXI_AWCACHE, - M_AXI_AWPROT => M_AXI_AWPROT, - M_AXI_AWREGION => M_AXI_AWREGION, - M_AXI_AWQOS => M_AXI_AWQOS, - M_AXI_AWVALID => M_AXI_AWVALID, - M_AXI_AWREADY => M_AXI_AWREADY, - M_AXI_WID => M_AXI_WID, - M_AXI_WDATA => M_AXI_WDATA, - M_AXI_WSTRB => M_AXI_WSTRB, - M_AXI_WLAST => M_AXI_WLAST, - M_AXI_WVALID => M_AXI_WVALID, - M_AXI_WREADY => M_AXI_WREADY, - M_AXI_BID => M_AXI_BID, - M_AXI_BRESP => M_AXI_BRESP, - M_AXI_BVALID => M_AXI_BVALID, - M_AXI_BREADY => M_AXI_BREADY, - M_AXI_ARID => M_AXI_ARID, - M_AXI_ARADDR => M_AXI_ARADDR, - M_AXI_ARLEN => M_AXI_ARLEN, - M_AXI_ARSIZE => M_AXI_ARSIZE, - M_AXI_ARBURST => M_AXI_ARBURST, - M_AXI_ARLOCK => mAxiArLock, - M_AXI_ARCACHE => M_AXI_ARCACHE, - M_AXI_ARPROT => M_AXI_ARPROT, - M_AXI_ARREGION => M_AXI_ARREGION, - M_AXI_ARQOS => M_AXI_ARQOS, - M_AXI_ARVALID => M_AXI_ARVALID, - M_AXI_ARREADY => M_AXI_ARREADY, - M_AXI_RID => M_AXI_RID, - M_AXI_RDATA => M_AXI_RDATA, - M_AXI_RRESP => M_AXI_RRESP, - M_AXI_RLAST => M_AXI_RLAST, - M_AXI_RVALID => M_AXI_RVALID, - M_AXI_RREADY => M_AXI_RREADY, - axiClk => open, - axiRst => open, - axiReadMaster => axiReadMaster, - axiReadSlave => axiReadSlave, - axiWriteMaster => axiWriteMaster, - axiWriteSlave => axiWriteSlave); + M_AXI_ACLK => axiClk, + M_AXI_ARESETN => axiResetN, + M_AXI_AWID => M_AXI_AWID, + M_AXI_AWADDR => M_AXI_AWADDR, + M_AXI_AWLEN => M_AXI_AWLEN, + M_AXI_AWSIZE => M_AXI_AWSIZE, + M_AXI_AWBURST => M_AXI_AWBURST, + M_AXI_AWLOCK => mAxiAwLock, + M_AXI_AWCACHE => M_AXI_AWCACHE, + M_AXI_AWPROT => M_AXI_AWPROT, + M_AXI_AWREGION => M_AXI_AWREGION, + M_AXI_AWQOS => M_AXI_AWQOS, + M_AXI_AWVALID => M_AXI_AWVALID, + M_AXI_AWREADY => M_AXI_AWREADY, + M_AXI_WID => M_AXI_WID, + M_AXI_WDATA => M_AXI_WDATA, + M_AXI_WSTRB => M_AXI_WSTRB, + M_AXI_WLAST => M_AXI_WLAST, + M_AXI_WVALID => M_AXI_WVALID, + M_AXI_WREADY => M_AXI_WREADY, + M_AXI_BID => M_AXI_BID, + M_AXI_BRESP => M_AXI_BRESP, + M_AXI_BVALID => M_AXI_BVALID, + M_AXI_BREADY => M_AXI_BREADY, + M_AXI_ARID => M_AXI_ARID, + M_AXI_ARADDR => M_AXI_ARADDR, + M_AXI_ARLEN => M_AXI_ARLEN, + M_AXI_ARSIZE => M_AXI_ARSIZE, + M_AXI_ARBURST => M_AXI_ARBURST, + M_AXI_ARLOCK => mAxiArLock, + M_AXI_ARCACHE => M_AXI_ARCACHE, + M_AXI_ARPROT => M_AXI_ARPROT, + M_AXI_ARREGION => M_AXI_ARREGION, + M_AXI_ARQOS => M_AXI_ARQOS, + M_AXI_ARVALID => M_AXI_ARVALID, + M_AXI_ARREADY => M_AXI_ARREADY, + M_AXI_RID => M_AXI_RID, + M_AXI_RDATA => M_AXI_RDATA, + M_AXI_RRESP => M_AXI_RRESP, + M_AXI_RLAST => M_AXI_RLAST, + M_AXI_RVALID => M_AXI_RVALID, + M_AXI_RREADY => M_AXI_RREADY, + axiClk => open, + axiRst => open, + axiReadMaster => axiReadMaster, + axiReadSlave => axiReadSlave, + axiWriteMaster => axiWriteMaster, + axiWriteSlave => axiWriteSlave); --------------------------------------------------------------------------- -- DUT diff --git a/axi/axi4/ip_integrator/AxiMonAxiLIpIntegrator.vhd b/axi/axi4/ip_integrator/AxiMonAxiLIpIntegrator.vhd index e3f9bf099b..ba8f2dbc63 100644 --- a/axi/axi4/ip_integrator/AxiMonAxiLIpIntegrator.vhd +++ b/axi/axi4/ip_integrator/AxiMonAxiLIpIntegrator.vhd @@ -22,36 +22,36 @@ use surf.AxiLitePkg.all; entity AxiMonAxiLIpIntegrator is port ( - axiClk : in sl; - axiRst : in sl; - wrValid : in sl; - wrLast : in sl; - wrReady : in sl; - wrStrb : in slv(3 downto 0); - rdValid : in sl; - rdLast : in sl; - rdReady : in sl; - axilClk : in sl; - axilRst : in sl; - S_AXI_AWADDR : in slv(6 downto 0); - S_AXI_AWPROT : in slv(2 downto 0); - S_AXI_AWVALID : in sl; - S_AXI_AWREADY : out sl; - S_AXI_WDATA : in slv(31 downto 0); - S_AXI_WSTRB : in slv(3 downto 0); - S_AXI_WVALID : in sl; - S_AXI_WREADY : out sl; - S_AXI_BRESP : out slv(1 downto 0); - S_AXI_BVALID : out sl; - S_AXI_BREADY : in sl; - S_AXI_ARADDR : in slv(6 downto 0); - S_AXI_ARPROT : in slv(2 downto 0); - S_AXI_ARVALID : in sl; - S_AXI_ARREADY : out sl; - S_AXI_RDATA : out slv(31 downto 0); - S_AXI_RRESP : out slv(1 downto 0); - S_AXI_RVALID : out sl; - S_AXI_RREADY : in sl); + axiClk : in sl; + axiRst : in sl; + wrValid : in sl; + wrLast : in sl; + wrReady : in sl; + wrStrb : in slv(3 downto 0); + rdValid : in sl; + rdLast : in sl; + rdReady : in sl; + axilClk : in sl; + axilRst : in sl; + S_AXI_AWADDR : in slv(6 downto 0); + S_AXI_AWPROT : in slv(2 downto 0); + S_AXI_AWVALID : in sl; + S_AXI_AWREADY : out sl; + S_AXI_WDATA : in slv(31 downto 0); + S_AXI_WSTRB : in slv(3 downto 0); + S_AXI_WVALID : in sl; + S_AXI_WREADY : out sl; + S_AXI_BRESP : out slv(1 downto 0); + S_AXI_BVALID : out sl; + S_AXI_BREADY : in sl; + S_AXI_ARADDR : in slv(6 downto 0); + S_AXI_ARPROT : in slv(2 downto 0); + S_AXI_ARVALID : in sl; + S_AXI_ARREADY : out sl; + S_AXI_RDATA : out slv(31 downto 0); + S_AXI_RRESP : out slv(1 downto 0); + S_AXI_RVALID : out sl; + S_AXI_RREADY : in sl); end entity AxiMonAxiLIpIntegrator; architecture rtl of AxiMonAxiLIpIntegrator is @@ -62,25 +62,25 @@ architecture rtl of AxiMonAxiLIpIntegrator is ID_BITS_C => 1, LEN_BITS_C => 8); - signal axilResetN : sl := '1'; + signal axilResetN : sl := '1'; signal axiWriteMasters : AxiWriteMasterArray(0 downto 0) := (others => AXI_WRITE_MASTER_INIT_C); signal axiWriteSlaves : AxiWriteSlaveArray(0 downto 0) := (others => AXI_WRITE_SLAVE_INIT_C); signal axiReadMasters : AxiReadMasterArray(0 downto 0) := (others => AXI_READ_MASTER_INIT_C); signal axiReadSlaves : AxiReadSlaveArray(0 downto 0) := (others => AXI_READ_SLAVE_INIT_C); - signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; - signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; - signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; - signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; begin --------------------------------------------------------------------------- -- Observable AXI channel wiring --------------------------------------------------------------------------- - axiWriteMasters(0).wvalid <= wrValid; - axiWriteMasters(0).wlast <= wrLast; + axiWriteMasters(0).wvalid <= wrValid; + axiWriteMasters(0).wlast <= wrLast; axiWriteMasters(0).wstrb(3 downto 0) <= wrStrb; - axiWriteSlaves(0).wready <= wrReady; + axiWriteSlaves(0).wready <= wrReady; axiReadMasters(0).rready <= rdReady; axiReadSlaves(0).rvalid <= rdValid; diff --git a/axi/axi4/ip_integrator/AxiRamIpIntegrator.vhd b/axi/axi4/ip_integrator/AxiRamIpIntegrator.vhd index 9df46ca2ba..36a71ecb38 100644 --- a/axi/axi4/ip_integrator/AxiRamIpIntegrator.vhd +++ b/axi/axi4/ip_integrator/AxiRamIpIntegrator.vhd @@ -81,17 +81,17 @@ architecture rtl of AxiRamIpIntegrator is ID_BITS_C => ID_WIDTH_G, LEN_BITS_C => 8); - signal axiResetN : sl := '1'; - signal sAxiArLock : slv(1 downto 0) := (others => '0'); - signal sAxiAwLock : slv(1 downto 0) := (others => '0'); - signal axiReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; - signal axiReadSlave : AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; + signal axiResetN : sl := '1'; + signal sAxiArLock : slv(1 downto 0) := (others => '0'); + signal sAxiAwLock : slv(1 downto 0) := (others => '0'); + signal axiReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; + signal axiReadSlave : AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; signal axiWriteMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; signal axiWriteSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C; begin - axiResetN <= not axiRst; + axiResetN <= not axiRst; sAxiArLock <= '0' & S_AXI_ARLOCK; sAxiAwLock <= '0' & S_AXI_AWLOCK; @@ -102,54 +102,54 @@ begin ADDR_WIDTH => ADDR_WIDTH_G, DATA_WIDTH => DATA_WIDTH_G) port map ( - S_AXI_ACLK => axiClk, - S_AXI_ARESETN => axiResetN, - S_AXI_AWID => S_AXI_AWID, - S_AXI_AWADDR => S_AXI_AWADDR, - S_AXI_AWLEN => S_AXI_AWLEN, - S_AXI_AWSIZE => S_AXI_AWSIZE, - S_AXI_AWBURST => S_AXI_AWBURST, - S_AXI_AWLOCK => sAxiAwLock, - S_AXI_AWCACHE => S_AXI_AWCACHE, - S_AXI_AWPROT => S_AXI_AWPROT, - S_AXI_AWREGION => S_AXI_AWREGION, - S_AXI_AWQOS => S_AXI_AWQOS, - S_AXI_AWVALID => S_AXI_AWVALID, - S_AXI_AWREADY => S_AXI_AWREADY, - S_AXI_WID => S_AXI_WID, - S_AXI_WDATA => S_AXI_WDATA, - S_AXI_WSTRB => S_AXI_WSTRB, - S_AXI_WLAST => S_AXI_WLAST, - S_AXI_WVALID => S_AXI_WVALID, - S_AXI_WREADY => S_AXI_WREADY, - S_AXI_BID => S_AXI_BID, - S_AXI_BRESP => S_AXI_BRESP, - S_AXI_BVALID => S_AXI_BVALID, - S_AXI_BREADY => S_AXI_BREADY, - S_AXI_ARID => S_AXI_ARID, - S_AXI_ARADDR => S_AXI_ARADDR, - S_AXI_ARLEN => S_AXI_ARLEN, - S_AXI_ARSIZE => S_AXI_ARSIZE, - S_AXI_ARBURST => S_AXI_ARBURST, - S_AXI_ARLOCK => sAxiArLock, - S_AXI_ARCACHE => S_AXI_ARCACHE, - S_AXI_ARPROT => S_AXI_ARPROT, - S_AXI_ARREGION => S_AXI_ARREGION, - S_AXI_ARQOS => S_AXI_ARQOS, - S_AXI_ARVALID => S_AXI_ARVALID, - S_AXI_ARREADY => S_AXI_ARREADY, - S_AXI_RID => S_AXI_RID, - S_AXI_RDATA => S_AXI_RDATA, - S_AXI_RRESP => S_AXI_RRESP, - S_AXI_RLAST => S_AXI_RLAST, - S_AXI_RVALID => S_AXI_RVALID, - S_AXI_RREADY => S_AXI_RREADY, - axiClk => open, - axiRst => open, - axiReadMaster => axiReadMaster, - axiReadSlave => axiReadSlave, - axiWriteMaster => axiWriteMaster, - axiWriteSlave => axiWriteSlave); + S_AXI_ACLK => axiClk, + S_AXI_ARESETN => axiResetN, + S_AXI_AWID => S_AXI_AWID, + S_AXI_AWADDR => S_AXI_AWADDR, + S_AXI_AWLEN => S_AXI_AWLEN, + S_AXI_AWSIZE => S_AXI_AWSIZE, + S_AXI_AWBURST => S_AXI_AWBURST, + S_AXI_AWLOCK => sAxiAwLock, + S_AXI_AWCACHE => S_AXI_AWCACHE, + S_AXI_AWPROT => S_AXI_AWPROT, + S_AXI_AWREGION => S_AXI_AWREGION, + S_AXI_AWQOS => S_AXI_AWQOS, + S_AXI_AWVALID => S_AXI_AWVALID, + S_AXI_AWREADY => S_AXI_AWREADY, + S_AXI_WID => S_AXI_WID, + S_AXI_WDATA => S_AXI_WDATA, + S_AXI_WSTRB => S_AXI_WSTRB, + S_AXI_WLAST => S_AXI_WLAST, + S_AXI_WVALID => S_AXI_WVALID, + S_AXI_WREADY => S_AXI_WREADY, + S_AXI_BID => S_AXI_BID, + S_AXI_BRESP => S_AXI_BRESP, + S_AXI_BVALID => S_AXI_BVALID, + S_AXI_BREADY => S_AXI_BREADY, + S_AXI_ARID => S_AXI_ARID, + S_AXI_ARADDR => S_AXI_ARADDR, + S_AXI_ARLEN => S_AXI_ARLEN, + S_AXI_ARSIZE => S_AXI_ARSIZE, + S_AXI_ARBURST => S_AXI_ARBURST, + S_AXI_ARLOCK => sAxiArLock, + S_AXI_ARCACHE => S_AXI_ARCACHE, + S_AXI_ARPROT => S_AXI_ARPROT, + S_AXI_ARREGION => S_AXI_ARREGION, + S_AXI_ARQOS => S_AXI_ARQOS, + S_AXI_ARVALID => S_AXI_ARVALID, + S_AXI_ARREADY => S_AXI_ARREADY, + S_AXI_RID => S_AXI_RID, + S_AXI_RDATA => S_AXI_RDATA, + S_AXI_RRESP => S_AXI_RRESP, + S_AXI_RLAST => S_AXI_RLAST, + S_AXI_RVALID => S_AXI_RVALID, + S_AXI_RREADY => S_AXI_RREADY, + axiClk => open, + axiRst => open, + axiReadMaster => axiReadMaster, + axiReadSlave => axiReadSlave, + axiWriteMaster => axiWriteMaster, + axiWriteSlave => axiWriteSlave); U_DUT : entity surf.AxiRam generic map ( diff --git a/axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd b/axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd index 3acc4d88a3..87869ed56d 100644 --- a/axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd +++ b/axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd @@ -22,11 +22,11 @@ use surf.AxiLitePkg.all; entity AxiRateGenIpIntegrator is generic ( - TPD_G : time := 1 ns; - COMMON_CLK_G : boolean := true; - AXI_ADDR_WIDTH_G : positive range 12 to 64 := 16; - AXI_DATA_WIDTH_G : positive range 32 to 1024 := 32; - AXI_ID_WIDTH_G : positive := 4); + TPD_G : time := 1 ns; + COMMON_CLK_G : boolean := true; + AXI_ADDR_WIDTH_G : positive range 12 to 64 := 16; + AXI_DATA_WIDTH_G : positive range 32 to 1024 := 32; + AXI_ID_WIDTH_G : positive := 4); port ( axiClk : in sl; axiRst : in sl; @@ -101,23 +101,23 @@ architecture rtl of AxiRateGenIpIntegrator is ID_BITS_C => AXI_ID_WIDTH_G, LEN_BITS_C => 8); - signal axiResetN : sl := '1'; - signal axilResetN : sl := '1'; - signal mAxiAwLock : slv(1 downto 0) := (others => '0'); - signal mAxiArLock : slv(1 downto 0) := (others => '0'); - signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; - signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal axiResetN : sl := '1'; + signal axilResetN : sl := '1'; + signal mAxiAwLock : slv(1 downto 0) := (others => '0'); + signal mAxiArLock : slv(1 downto 0) := (others => '0'); + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; - signal axiReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; - signal axiReadSlave : AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; - signal axiWriteMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; - signal axiWriteSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C; + signal axiReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; + signal axiReadSlave : AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; + signal axiWriteMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; + signal axiWriteSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C; begin - axiResetN <= not axiRst; - axilResetN <= not axilRst; + axiResetN <= not axiRst; + axilResetN <= not axilRst; M_AXI_AWLOCK <= mAxiAwLock(0); M_AXI_ARLOCK <= mAxiArLock(0); @@ -163,54 +163,54 @@ begin ADDR_WIDTH => AXI_ADDR_WIDTH_G, DATA_WIDTH => AXI_DATA_WIDTH_G) port map ( - M_AXI_ACLK => axiClk, - M_AXI_ARESETN => axiResetN, - M_AXI_AWID => M_AXI_AWID, - M_AXI_AWADDR => M_AXI_AWADDR, - M_AXI_AWLEN => M_AXI_AWLEN, - M_AXI_AWSIZE => M_AXI_AWSIZE, - M_AXI_AWBURST => M_AXI_AWBURST, - M_AXI_AWLOCK => mAxiAwLock, - M_AXI_AWCACHE => M_AXI_AWCACHE, - M_AXI_AWPROT => M_AXI_AWPROT, - M_AXI_AWREGION => M_AXI_AWREGION, - M_AXI_AWQOS => M_AXI_AWQOS, - M_AXI_AWVALID => M_AXI_AWVALID, - M_AXI_AWREADY => M_AXI_AWREADY, - M_AXI_WID => M_AXI_WID, - M_AXI_WDATA => M_AXI_WDATA, - M_AXI_WSTRB => M_AXI_WSTRB, - M_AXI_WLAST => M_AXI_WLAST, - M_AXI_WVALID => M_AXI_WVALID, - M_AXI_WREADY => M_AXI_WREADY, - M_AXI_BID => M_AXI_BID, - M_AXI_BRESP => M_AXI_BRESP, - M_AXI_BVALID => M_AXI_BVALID, - M_AXI_BREADY => M_AXI_BREADY, - M_AXI_ARID => M_AXI_ARID, - M_AXI_ARADDR => M_AXI_ARADDR, - M_AXI_ARLEN => M_AXI_ARLEN, - M_AXI_ARSIZE => M_AXI_ARSIZE, - M_AXI_ARBURST => M_AXI_ARBURST, - M_AXI_ARLOCK => mAxiArLock, - M_AXI_ARCACHE => M_AXI_ARCACHE, - M_AXI_ARPROT => M_AXI_ARPROT, - M_AXI_ARREGION => M_AXI_ARREGION, - M_AXI_ARQOS => M_AXI_ARQOS, - M_AXI_ARVALID => M_AXI_ARVALID, - M_AXI_ARREADY => M_AXI_ARREADY, - M_AXI_RID => M_AXI_RID, - M_AXI_RDATA => M_AXI_RDATA, - M_AXI_RRESP => M_AXI_RRESP, - M_AXI_RLAST => M_AXI_RLAST, - M_AXI_RVALID => M_AXI_RVALID, - M_AXI_RREADY => M_AXI_RREADY, - axiClk => open, - axiRst => open, - axiReadMaster => axiReadMaster, - axiReadSlave => axiReadSlave, - axiWriteMaster => axiWriteMaster, - axiWriteSlave => axiWriteSlave); + M_AXI_ACLK => axiClk, + M_AXI_ARESETN => axiResetN, + M_AXI_AWID => M_AXI_AWID, + M_AXI_AWADDR => M_AXI_AWADDR, + M_AXI_AWLEN => M_AXI_AWLEN, + M_AXI_AWSIZE => M_AXI_AWSIZE, + M_AXI_AWBURST => M_AXI_AWBURST, + M_AXI_AWLOCK => mAxiAwLock, + M_AXI_AWCACHE => M_AXI_AWCACHE, + M_AXI_AWPROT => M_AXI_AWPROT, + M_AXI_AWREGION => M_AXI_AWREGION, + M_AXI_AWQOS => M_AXI_AWQOS, + M_AXI_AWVALID => M_AXI_AWVALID, + M_AXI_AWREADY => M_AXI_AWREADY, + M_AXI_WID => M_AXI_WID, + M_AXI_WDATA => M_AXI_WDATA, + M_AXI_WSTRB => M_AXI_WSTRB, + M_AXI_WLAST => M_AXI_WLAST, + M_AXI_WVALID => M_AXI_WVALID, + M_AXI_WREADY => M_AXI_WREADY, + M_AXI_BID => M_AXI_BID, + M_AXI_BRESP => M_AXI_BRESP, + M_AXI_BVALID => M_AXI_BVALID, + M_AXI_BREADY => M_AXI_BREADY, + M_AXI_ARID => M_AXI_ARID, + M_AXI_ARADDR => M_AXI_ARADDR, + M_AXI_ARLEN => M_AXI_ARLEN, + M_AXI_ARSIZE => M_AXI_ARSIZE, + M_AXI_ARBURST => M_AXI_ARBURST, + M_AXI_ARLOCK => mAxiArLock, + M_AXI_ARCACHE => M_AXI_ARCACHE, + M_AXI_ARPROT => M_AXI_ARPROT, + M_AXI_ARREGION => M_AXI_ARREGION, + M_AXI_ARQOS => M_AXI_ARQOS, + M_AXI_ARVALID => M_AXI_ARVALID, + M_AXI_ARREADY => M_AXI_ARREADY, + M_AXI_RID => M_AXI_RID, + M_AXI_RDATA => M_AXI_RDATA, + M_AXI_RRESP => M_AXI_RRESP, + M_AXI_RLAST => M_AXI_RLAST, + M_AXI_RVALID => M_AXI_RVALID, + M_AXI_RREADY => M_AXI_RREADY, + axiClk => open, + axiRst => open, + axiReadMaster => axiReadMaster, + axiReadSlave => axiReadSlave, + axiWriteMaster => axiWriteMaster, + axiWriteSlave => axiWriteSlave); U_DUT : entity surf.AxiRateGen generic map ( diff --git a/axi/axi4/ip_integrator/AxiReadEmulateIpIntegrator.vhd b/axi/axi4/ip_integrator/AxiReadEmulateIpIntegrator.vhd index 9892091c1d..71f0ecfcbc 100644 --- a/axi/axi4/ip_integrator/AxiReadEmulateIpIntegrator.vhd +++ b/axi/axi4/ip_integrator/AxiReadEmulateIpIntegrator.vhd @@ -54,7 +54,7 @@ architecture rtl of AxiReadEmulateIpIntegrator is ID_BITS_C => 8, LEN_BITS_C => 8); - signal axiResetN : sl := '1'; + signal axiResetN : sl := '1'; signal axiReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; signal axiReadSlave : AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; @@ -72,54 +72,54 @@ begin ADDR_WIDTH => 16, DATA_WIDTH => 32) port map ( - S_AXI_ACLK => axiClk, - S_AXI_ARESETN => axiResetN, - S_AXI_AWID => (others => '0'), - S_AXI_AWADDR => (others => '0'), - S_AXI_AWLEN => (others => '0'), - S_AXI_AWSIZE => (others => '0'), - S_AXI_AWBURST => (others => '0'), - S_AXI_AWLOCK => (others => '0'), - S_AXI_AWCACHE => (others => '0'), - S_AXI_AWPROT => (others => '0'), - S_AXI_AWREGION => (others => '0'), - S_AXI_AWQOS => (others => '0'), - S_AXI_AWVALID => '0', - S_AXI_AWREADY => open, - S_AXI_WID => (others => '0'), - S_AXI_WDATA => (others => '0'), - S_AXI_WSTRB => (others => '0'), - S_AXI_WLAST => '0', - S_AXI_WVALID => '0', - S_AXI_WREADY => open, - S_AXI_BID => open, - S_AXI_BRESP => open, - S_AXI_BVALID => open, - S_AXI_BREADY => '0', - S_AXI_ARID => S_AXI_ARID, - S_AXI_ARADDR => S_AXI_ARADDR, - S_AXI_ARLEN => S_AXI_ARLEN, - S_AXI_ARSIZE => S_AXI_ARSIZE, - S_AXI_ARBURST => S_AXI_ARBURST, - S_AXI_ARLOCK => S_AXI_ARLOCK, - S_AXI_ARCACHE => S_AXI_ARCACHE, - S_AXI_ARPROT => S_AXI_ARPROT, - S_AXI_ARREGION => S_AXI_ARREGION, - S_AXI_ARQOS => S_AXI_ARQOS, - S_AXI_ARVALID => S_AXI_ARVALID, - S_AXI_ARREADY => S_AXI_ARREADY, - S_AXI_RID => S_AXI_RID, - S_AXI_RDATA => S_AXI_RDATA, - S_AXI_RRESP => S_AXI_RRESP, - S_AXI_RLAST => S_AXI_RLAST, - S_AXI_RVALID => S_AXI_RVALID, - S_AXI_RREADY => S_AXI_RREADY, - axiClk => open, - axiRst => open, - axiReadMaster => axiReadMaster, - axiReadSlave => axiReadSlave, - axiWriteMaster => open, - axiWriteSlave => AXI_WRITE_SLAVE_INIT_C); + S_AXI_ACLK => axiClk, + S_AXI_ARESETN => axiResetN, + S_AXI_AWID => (others => '0'), + S_AXI_AWADDR => (others => '0'), + S_AXI_AWLEN => (others => '0'), + S_AXI_AWSIZE => (others => '0'), + S_AXI_AWBURST => (others => '0'), + S_AXI_AWLOCK => (others => '0'), + S_AXI_AWCACHE => (others => '0'), + S_AXI_AWPROT => (others => '0'), + S_AXI_AWREGION => (others => '0'), + S_AXI_AWQOS => (others => '0'), + S_AXI_AWVALID => '0', + S_AXI_AWREADY => open, + S_AXI_WID => (others => '0'), + S_AXI_WDATA => (others => '0'), + S_AXI_WSTRB => (others => '0'), + S_AXI_WLAST => '0', + S_AXI_WVALID => '0', + S_AXI_WREADY => open, + S_AXI_BID => open, + S_AXI_BRESP => open, + S_AXI_BVALID => open, + S_AXI_BREADY => '0', + S_AXI_ARID => S_AXI_ARID, + S_AXI_ARADDR => S_AXI_ARADDR, + S_AXI_ARLEN => S_AXI_ARLEN, + S_AXI_ARSIZE => S_AXI_ARSIZE, + S_AXI_ARBURST => S_AXI_ARBURST, + S_AXI_ARLOCK => S_AXI_ARLOCK, + S_AXI_ARCACHE => S_AXI_ARCACHE, + S_AXI_ARPROT => S_AXI_ARPROT, + S_AXI_ARREGION => S_AXI_ARREGION, + S_AXI_ARQOS => S_AXI_ARQOS, + S_AXI_ARVALID => S_AXI_ARVALID, + S_AXI_ARREADY => S_AXI_ARREADY, + S_AXI_RID => S_AXI_RID, + S_AXI_RDATA => S_AXI_RDATA, + S_AXI_RRESP => S_AXI_RRESP, + S_AXI_RLAST => S_AXI_RLAST, + S_AXI_RVALID => S_AXI_RVALID, + S_AXI_RREADY => S_AXI_RREADY, + axiClk => open, + axiRst => open, + axiReadMaster => axiReadMaster, + axiReadSlave => axiReadSlave, + axiWriteMaster => open, + axiWriteSlave => AXI_WRITE_SLAVE_INIT_C); --------------------------------------------------------------------------- -- DUT diff --git a/axi/axi4/ip_integrator/AxiReadPathFifoIpIntegrator.vhd b/axi/axi4/ip_integrator/AxiReadPathFifoIpIntegrator.vhd index c4672f4737..ed694d34d6 100644 --- a/axi/axi4/ip_integrator/AxiReadPathFifoIpIntegrator.vhd +++ b/axi/axi4/ip_integrator/AxiReadPathFifoIpIntegrator.vhd @@ -26,42 +26,42 @@ entity AxiReadPathFifoIpIntegrator is DATA_WIDTH_G : positive range 32 to 1024 := 32; ID_WIDTH_G : positive := 4); port ( - sAxiClk : in sl; - sAxiRst : in sl; - mAxiClk : in sl; - mAxiRst : in sl; - S_AXI_ARID : in slv(ID_WIDTH_G-1 downto 0); - S_AXI_ARADDR : in slv(ADDR_WIDTH_G-1 downto 0); - S_AXI_ARLEN : in slv(7 downto 0); - S_AXI_ARSIZE : in slv(2 downto 0); - S_AXI_ARBURST : in slv(1 downto 0); - S_AXI_ARLOCK : in sl; - S_AXI_ARCACHE : in slv(3 downto 0); - S_AXI_ARPROT : in slv(2 downto 0); - S_AXI_ARVALID : in sl; - S_AXI_ARREADY : out sl; - S_AXI_RID : out slv(ID_WIDTH_G-1 downto 0); - S_AXI_RDATA : out slv(DATA_WIDTH_G-1 downto 0); - S_AXI_RRESP : out slv(1 downto 0); - S_AXI_RLAST : out sl; - S_AXI_RVALID : out sl; - S_AXI_RREADY : in sl; - M_AXI_ARID : out slv(ID_WIDTH_G-1 downto 0); - M_AXI_ARADDR : out slv(ADDR_WIDTH_G-1 downto 0); - M_AXI_ARLEN : out slv(7 downto 0); - M_AXI_ARSIZE : out slv(2 downto 0); - M_AXI_ARBURST : out slv(1 downto 0); - M_AXI_ARLOCK : out sl; - M_AXI_ARCACHE : out slv(3 downto 0); - M_AXI_ARPROT : out slv(2 downto 0); - M_AXI_ARVALID : out sl; - M_AXI_ARREADY : in sl; - M_AXI_RID : in slv(ID_WIDTH_G-1 downto 0); - M_AXI_RDATA : in slv(DATA_WIDTH_G-1 downto 0); - M_AXI_RRESP : in slv(1 downto 0); - M_AXI_RLAST : in sl; - M_AXI_RVALID : in sl; - M_AXI_RREADY : out sl); + sAxiClk : in sl; + sAxiRst : in sl; + mAxiClk : in sl; + mAxiRst : in sl; + S_AXI_ARID : in slv(ID_WIDTH_G-1 downto 0); + S_AXI_ARADDR : in slv(ADDR_WIDTH_G-1 downto 0); + S_AXI_ARLEN : in slv(7 downto 0); + S_AXI_ARSIZE : in slv(2 downto 0); + S_AXI_ARBURST : in slv(1 downto 0); + S_AXI_ARLOCK : in sl; + S_AXI_ARCACHE : in slv(3 downto 0); + S_AXI_ARPROT : in slv(2 downto 0); + S_AXI_ARVALID : in sl; + S_AXI_ARREADY : out sl; + S_AXI_RID : out slv(ID_WIDTH_G-1 downto 0); + S_AXI_RDATA : out slv(DATA_WIDTH_G-1 downto 0); + S_AXI_RRESP : out slv(1 downto 0); + S_AXI_RLAST : out sl; + S_AXI_RVALID : out sl; + S_AXI_RREADY : in sl; + M_AXI_ARID : out slv(ID_WIDTH_G-1 downto 0); + M_AXI_ARADDR : out slv(ADDR_WIDTH_G-1 downto 0); + M_AXI_ARLEN : out slv(7 downto 0); + M_AXI_ARSIZE : out slv(2 downto 0); + M_AXI_ARBURST : out slv(1 downto 0); + M_AXI_ARLOCK : out sl; + M_AXI_ARCACHE : out slv(3 downto 0); + M_AXI_ARPROT : out slv(2 downto 0); + M_AXI_ARVALID : out sl; + M_AXI_ARREADY : in sl; + M_AXI_RID : in slv(ID_WIDTH_G-1 downto 0); + M_AXI_RDATA : in slv(DATA_WIDTH_G-1 downto 0); + M_AXI_RRESP : in slv(1 downto 0); + M_AXI_RLAST : in sl; + M_AXI_RVALID : in sl; + M_AXI_RREADY : out sl); end entity AxiReadPathFifoIpIntegrator; architecture rtl of AxiReadPathFifoIpIntegrator is @@ -72,9 +72,9 @@ architecture rtl of AxiReadPathFifoIpIntegrator is ID_BITS_C => ID_WIDTH_G, LEN_BITS_C => 8); - signal sAxiResetN : sl := '1'; - signal mAxiResetN : sl := '1'; - signal mAxiArLock : slv(1 downto 0) := (others => '0'); + signal sAxiResetN : sl := '1'; + signal mAxiResetN : sl := '1'; + signal mAxiArLock : slv(1 downto 0) := (others => '0'); signal sAxiReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; signal sAxiReadSlave : AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; signal mAxiReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; @@ -85,8 +85,8 @@ begin --------------------------------------------------------------------------- -- AXI read shims --------------------------------------------------------------------------- - sAxiResetN <= not sAxiRst; - mAxiResetN <= not mAxiRst; + sAxiResetN <= not sAxiRst; + mAxiResetN <= not mAxiRst; M_AXI_ARLOCK <= mAxiArLock(0); U_S_AXI : entity surf.SlaveAxiIpIntegrator @@ -96,54 +96,54 @@ begin ADDR_WIDTH => ADDR_WIDTH_G, DATA_WIDTH => DATA_WIDTH_G) port map ( - S_AXI_ACLK => sAxiClk, - S_AXI_ARESETN => sAxiResetN, - S_AXI_AWID => (others => '0'), - S_AXI_AWADDR => (others => '0'), - S_AXI_AWLEN => (others => '0'), - S_AXI_AWSIZE => (others => '0'), - S_AXI_AWBURST => (others => '0'), - S_AXI_AWLOCK => (others => '0'), - S_AXI_AWCACHE => (others => '0'), - S_AXI_AWPROT => (others => '0'), - S_AXI_AWREGION => (others => '0'), - S_AXI_AWQOS => (others => '0'), - S_AXI_AWVALID => '0', - S_AXI_AWREADY => open, - S_AXI_WID => (others => '0'), - S_AXI_WDATA => (others => '0'), - S_AXI_WSTRB => (others => '0'), - S_AXI_WLAST => '0', - S_AXI_WVALID => '0', - S_AXI_WREADY => open, - S_AXI_BID => open, - S_AXI_BRESP => open, - S_AXI_BVALID => open, - S_AXI_BREADY => '0', - S_AXI_ARID => S_AXI_ARID, - S_AXI_ARADDR => S_AXI_ARADDR, - S_AXI_ARLEN => S_AXI_ARLEN, - S_AXI_ARSIZE => S_AXI_ARSIZE, - S_AXI_ARBURST => S_AXI_ARBURST, - S_AXI_ARLOCK => '0' & S_AXI_ARLOCK, - S_AXI_ARCACHE => S_AXI_ARCACHE, - S_AXI_ARPROT => S_AXI_ARPROT, - S_AXI_ARREGION => (others => '0'), - S_AXI_ARQOS => (others => '0'), - S_AXI_ARVALID => S_AXI_ARVALID, - S_AXI_ARREADY => S_AXI_ARREADY, - S_AXI_RID => S_AXI_RID, - S_AXI_RDATA => S_AXI_RDATA, - S_AXI_RRESP => S_AXI_RRESP, - S_AXI_RLAST => S_AXI_RLAST, - S_AXI_RVALID => S_AXI_RVALID, - S_AXI_RREADY => S_AXI_RREADY, - axiClk => open, - axiRst => open, - axiReadMaster => sAxiReadMaster, - axiReadSlave => sAxiReadSlave, - axiWriteMaster => open, - axiWriteSlave => AXI_WRITE_SLAVE_INIT_C); + S_AXI_ACLK => sAxiClk, + S_AXI_ARESETN => sAxiResetN, + S_AXI_AWID => (others => '0'), + S_AXI_AWADDR => (others => '0'), + S_AXI_AWLEN => (others => '0'), + S_AXI_AWSIZE => (others => '0'), + S_AXI_AWBURST => (others => '0'), + S_AXI_AWLOCK => (others => '0'), + S_AXI_AWCACHE => (others => '0'), + S_AXI_AWPROT => (others => '0'), + S_AXI_AWREGION => (others => '0'), + S_AXI_AWQOS => (others => '0'), + S_AXI_AWVALID => '0', + S_AXI_AWREADY => open, + S_AXI_WID => (others => '0'), + S_AXI_WDATA => (others => '0'), + S_AXI_WSTRB => (others => '0'), + S_AXI_WLAST => '0', + S_AXI_WVALID => '0', + S_AXI_WREADY => open, + S_AXI_BID => open, + S_AXI_BRESP => open, + S_AXI_BVALID => open, + S_AXI_BREADY => '0', + S_AXI_ARID => S_AXI_ARID, + S_AXI_ARADDR => S_AXI_ARADDR, + S_AXI_ARLEN => S_AXI_ARLEN, + S_AXI_ARSIZE => S_AXI_ARSIZE, + S_AXI_ARBURST => S_AXI_ARBURST, + S_AXI_ARLOCK => '0' & S_AXI_ARLOCK, + S_AXI_ARCACHE => S_AXI_ARCACHE, + S_AXI_ARPROT => S_AXI_ARPROT, + S_AXI_ARREGION => (others => '0'), + S_AXI_ARQOS => (others => '0'), + S_AXI_ARVALID => S_AXI_ARVALID, + S_AXI_ARREADY => S_AXI_ARREADY, + S_AXI_RID => S_AXI_RID, + S_AXI_RDATA => S_AXI_RDATA, + S_AXI_RRESP => S_AXI_RRESP, + S_AXI_RLAST => S_AXI_RLAST, + S_AXI_RVALID => S_AXI_RVALID, + S_AXI_RREADY => S_AXI_RREADY, + axiClk => open, + axiRst => open, + axiReadMaster => sAxiReadMaster, + axiReadSlave => sAxiReadSlave, + axiWriteMaster => open, + axiWriteSlave => AXI_WRITE_SLAVE_INIT_C); U_M_AXI : entity surf.MasterAxiIpIntegrator generic map ( @@ -152,63 +152,63 @@ begin ADDR_WIDTH => ADDR_WIDTH_G, DATA_WIDTH => DATA_WIDTH_G) port map ( - M_AXI_ACLK => mAxiClk, - M_AXI_ARESETN => mAxiResetN, - M_AXI_AWID => open, - M_AXI_AWADDR => open, - M_AXI_AWLEN => open, - M_AXI_AWSIZE => open, - M_AXI_AWBURST => open, - M_AXI_AWLOCK => open, - M_AXI_AWCACHE => open, - M_AXI_AWPROT => open, - M_AXI_AWREGION => open, - M_AXI_AWQOS => open, - M_AXI_AWVALID => open, - M_AXI_AWREADY => '0', - M_AXI_WID => open, - M_AXI_WDATA => open, - M_AXI_WSTRB => open, - M_AXI_WLAST => open, - M_AXI_WVALID => open, - M_AXI_WREADY => '0', - M_AXI_BID => (others => '0'), - M_AXI_BRESP => (others => '0'), - M_AXI_BVALID => '0', - M_AXI_BREADY => open, - M_AXI_ARID => M_AXI_ARID, - M_AXI_ARADDR => M_AXI_ARADDR, - M_AXI_ARLEN => M_AXI_ARLEN, - M_AXI_ARSIZE => M_AXI_ARSIZE, - M_AXI_ARBURST => M_AXI_ARBURST, - M_AXI_ARLOCK => mAxiArLock, - M_AXI_ARCACHE => M_AXI_ARCACHE, - M_AXI_ARPROT => M_AXI_ARPROT, - M_AXI_ARREGION => open, - M_AXI_ARQOS => open, - M_AXI_ARVALID => M_AXI_ARVALID, - M_AXI_ARREADY => M_AXI_ARREADY, - M_AXI_RID => M_AXI_RID, - M_AXI_RDATA => M_AXI_RDATA, - M_AXI_RRESP => M_AXI_RRESP, - M_AXI_RLAST => M_AXI_RLAST, - M_AXI_RVALID => M_AXI_RVALID, - M_AXI_RREADY => M_AXI_RREADY, - axiClk => open, - axiRst => open, - axiReadMaster => mAxiReadMaster, - axiReadSlave => mAxiReadSlave, - axiWriteMaster => AXI_WRITE_MASTER_INIT_C, - axiWriteSlave => open); + M_AXI_ACLK => mAxiClk, + M_AXI_ARESETN => mAxiResetN, + M_AXI_AWID => open, + M_AXI_AWADDR => open, + M_AXI_AWLEN => open, + M_AXI_AWSIZE => open, + M_AXI_AWBURST => open, + M_AXI_AWLOCK => open, + M_AXI_AWCACHE => open, + M_AXI_AWPROT => open, + M_AXI_AWREGION => open, + M_AXI_AWQOS => open, + M_AXI_AWVALID => open, + M_AXI_AWREADY => '0', + M_AXI_WID => open, + M_AXI_WDATA => open, + M_AXI_WSTRB => open, + M_AXI_WLAST => open, + M_AXI_WVALID => open, + M_AXI_WREADY => '0', + M_AXI_BID => (others => '0'), + M_AXI_BRESP => (others => '0'), + M_AXI_BVALID => '0', + M_AXI_BREADY => open, + M_AXI_ARID => M_AXI_ARID, + M_AXI_ARADDR => M_AXI_ARADDR, + M_AXI_ARLEN => M_AXI_ARLEN, + M_AXI_ARSIZE => M_AXI_ARSIZE, + M_AXI_ARBURST => M_AXI_ARBURST, + M_AXI_ARLOCK => mAxiArLock, + M_AXI_ARCACHE => M_AXI_ARCACHE, + M_AXI_ARPROT => M_AXI_ARPROT, + M_AXI_ARREGION => open, + M_AXI_ARQOS => open, + M_AXI_ARVALID => M_AXI_ARVALID, + M_AXI_ARREADY => M_AXI_ARREADY, + M_AXI_RID => M_AXI_RID, + M_AXI_RDATA => M_AXI_RDATA, + M_AXI_RRESP => M_AXI_RRESP, + M_AXI_RLAST => M_AXI_RLAST, + M_AXI_RVALID => M_AXI_RVALID, + M_AXI_RREADY => M_AXI_RREADY, + axiClk => open, + axiRst => open, + axiReadMaster => mAxiReadMaster, + axiReadSlave => mAxiReadSlave, + axiWriteMaster => AXI_WRITE_MASTER_INIT_C, + axiWriteSlave => open); --------------------------------------------------------------------------- -- DUT --------------------------------------------------------------------------- U_DUT : entity surf.AxiReadPathFifo generic map ( - TPD_G => TPD_G, + TPD_G => TPD_G, GEN_SYNC_FIFO_G => false, - AXI_CONFIG_G => AXI_CONFIG_C) + AXI_CONFIG_G => AXI_CONFIG_C) port map ( sAxiClk => sAxiClk, sAxiRst => sAxiRst, diff --git a/axi/axi4/ip_integrator/AxiReadPathMuxIpIntegrator.vhd b/axi/axi4/ip_integrator/AxiReadPathMuxIpIntegrator.vhd index 54e16afe3d..09706e722f 100644 --- a/axi/axi4/ip_integrator/AxiReadPathMuxIpIntegrator.vhd +++ b/axi/axi4/ip_integrator/AxiReadPathMuxIpIntegrator.vhd @@ -86,7 +86,7 @@ end entity AxiReadPathMuxIpIntegrator; architecture rtl of AxiReadPathMuxIpIntegrator is - signal axiResetN : sl := '1'; + signal axiResetN : sl := '1'; signal mAxiArLock : slv(1 downto 0) := (others => '0'); signal sAxiReadMasters : AxiReadMasterArray(1 downto 0) := (others => AXI_READ_MASTER_INIT_C); signal sAxiReadSlaves : AxiReadSlaveArray(1 downto 0) := (others => AXI_READ_SLAVE_INIT_C); @@ -106,54 +106,54 @@ begin ADDR_WIDTH => ADDR_WIDTH_G, DATA_WIDTH => DATA_WIDTH_G) port map ( - S_AXI_ACLK => axiClk, - S_AXI_ARESETN => axiResetN, - S_AXI_AWID => (others => '0'), - S_AXI_AWADDR => (others => '0'), - S_AXI_AWLEN => (others => '0'), - S_AXI_AWSIZE => (others => '0'), - S_AXI_AWBURST => (others => '0'), - S_AXI_AWLOCK => (others => '0'), - S_AXI_AWCACHE => (others => '0'), - S_AXI_AWPROT => (others => '0'), - S_AXI_AWREGION => (others => '0'), - S_AXI_AWQOS => (others => '0'), - S_AXI_AWVALID => '0', - S_AXI_AWREADY => open, - S_AXI_WID => (others => '0'), - S_AXI_WDATA => (others => '0'), - S_AXI_WSTRB => (others => '0'), - S_AXI_WLAST => '0', - S_AXI_WVALID => '0', - S_AXI_WREADY => open, - S_AXI_BID => open, - S_AXI_BRESP => open, - S_AXI_BVALID => open, - S_AXI_BREADY => '0', - S_AXI_ARID => S0_AXI_ARID, - S_AXI_ARADDR => S0_AXI_ARADDR, - S_AXI_ARLEN => S0_AXI_ARLEN, - S_AXI_ARSIZE => S0_AXI_ARSIZE, - S_AXI_ARBURST => S0_AXI_ARBURST, - S_AXI_ARLOCK => '0' & S0_AXI_ARLOCK, - S_AXI_ARCACHE => S0_AXI_ARCACHE, - S_AXI_ARPROT => S0_AXI_ARPROT, - S_AXI_ARREGION => S0_AXI_ARREGION, - S_AXI_ARQOS => S0_AXI_ARQOS, - S_AXI_ARVALID => S0_AXI_ARVALID, - S_AXI_ARREADY => S0_AXI_ARREADY, - S_AXI_RID => S0_AXI_RID, - S_AXI_RDATA => S0_AXI_RDATA, - S_AXI_RRESP => S0_AXI_RRESP, - S_AXI_RLAST => S0_AXI_RLAST, - S_AXI_RVALID => S0_AXI_RVALID, - S_AXI_RREADY => S0_AXI_RREADY, - axiClk => open, - axiRst => open, - axiReadMaster => sAxiReadMasters(0), - axiReadSlave => sAxiReadSlaves(0), - axiWriteMaster => open, - axiWriteSlave => AXI_WRITE_SLAVE_INIT_C); + S_AXI_ACLK => axiClk, + S_AXI_ARESETN => axiResetN, + S_AXI_AWID => (others => '0'), + S_AXI_AWADDR => (others => '0'), + S_AXI_AWLEN => (others => '0'), + S_AXI_AWSIZE => (others => '0'), + S_AXI_AWBURST => (others => '0'), + S_AXI_AWLOCK => (others => '0'), + S_AXI_AWCACHE => (others => '0'), + S_AXI_AWPROT => (others => '0'), + S_AXI_AWREGION => (others => '0'), + S_AXI_AWQOS => (others => '0'), + S_AXI_AWVALID => '0', + S_AXI_AWREADY => open, + S_AXI_WID => (others => '0'), + S_AXI_WDATA => (others => '0'), + S_AXI_WSTRB => (others => '0'), + S_AXI_WLAST => '0', + S_AXI_WVALID => '0', + S_AXI_WREADY => open, + S_AXI_BID => open, + S_AXI_BRESP => open, + S_AXI_BVALID => open, + S_AXI_BREADY => '0', + S_AXI_ARID => S0_AXI_ARID, + S_AXI_ARADDR => S0_AXI_ARADDR, + S_AXI_ARLEN => S0_AXI_ARLEN, + S_AXI_ARSIZE => S0_AXI_ARSIZE, + S_AXI_ARBURST => S0_AXI_ARBURST, + S_AXI_ARLOCK => '0' & S0_AXI_ARLOCK, + S_AXI_ARCACHE => S0_AXI_ARCACHE, + S_AXI_ARPROT => S0_AXI_ARPROT, + S_AXI_ARREGION => S0_AXI_ARREGION, + S_AXI_ARQOS => S0_AXI_ARQOS, + S_AXI_ARVALID => S0_AXI_ARVALID, + S_AXI_ARREADY => S0_AXI_ARREADY, + S_AXI_RID => S0_AXI_RID, + S_AXI_RDATA => S0_AXI_RDATA, + S_AXI_RRESP => S0_AXI_RRESP, + S_AXI_RLAST => S0_AXI_RLAST, + S_AXI_RVALID => S0_AXI_RVALID, + S_AXI_RREADY => S0_AXI_RREADY, + axiClk => open, + axiRst => open, + axiReadMaster => sAxiReadMasters(0), + axiReadSlave => sAxiReadSlaves(0), + axiWriteMaster => open, + axiWriteSlave => AXI_WRITE_SLAVE_INIT_C); U_S1 : entity surf.SlaveAxiIpIntegrator generic map ( @@ -162,54 +162,54 @@ begin ADDR_WIDTH => ADDR_WIDTH_G, DATA_WIDTH => DATA_WIDTH_G) port map ( - S_AXI_ACLK => axiClk, - S_AXI_ARESETN => axiResetN, - S_AXI_AWID => (others => '0'), - S_AXI_AWADDR => (others => '0'), - S_AXI_AWLEN => (others => '0'), - S_AXI_AWSIZE => (others => '0'), - S_AXI_AWBURST => (others => '0'), - S_AXI_AWLOCK => (others => '0'), - S_AXI_AWCACHE => (others => '0'), - S_AXI_AWPROT => (others => '0'), - S_AXI_AWREGION => (others => '0'), - S_AXI_AWQOS => (others => '0'), - S_AXI_AWVALID => '0', - S_AXI_AWREADY => open, - S_AXI_WID => (others => '0'), - S_AXI_WDATA => (others => '0'), - S_AXI_WSTRB => (others => '0'), - S_AXI_WLAST => '0', - S_AXI_WVALID => '0', - S_AXI_WREADY => open, - S_AXI_BID => open, - S_AXI_BRESP => open, - S_AXI_BVALID => open, - S_AXI_BREADY => '0', - S_AXI_ARID => S1_AXI_ARID, - S_AXI_ARADDR => S1_AXI_ARADDR, - S_AXI_ARLEN => S1_AXI_ARLEN, - S_AXI_ARSIZE => S1_AXI_ARSIZE, - S_AXI_ARBURST => S1_AXI_ARBURST, - S_AXI_ARLOCK => '0' & S1_AXI_ARLOCK, - S_AXI_ARCACHE => S1_AXI_ARCACHE, - S_AXI_ARPROT => S1_AXI_ARPROT, - S_AXI_ARREGION => S1_AXI_ARREGION, - S_AXI_ARQOS => S1_AXI_ARQOS, - S_AXI_ARVALID => S1_AXI_ARVALID, - S_AXI_ARREADY => S1_AXI_ARREADY, - S_AXI_RID => S1_AXI_RID, - S_AXI_RDATA => S1_AXI_RDATA, - S_AXI_RRESP => S1_AXI_RRESP, - S_AXI_RLAST => S1_AXI_RLAST, - S_AXI_RVALID => S1_AXI_RVALID, - S_AXI_RREADY => S1_AXI_RREADY, - axiClk => open, - axiRst => open, - axiReadMaster => sAxiReadMasters(1), - axiReadSlave => sAxiReadSlaves(1), - axiWriteMaster => open, - axiWriteSlave => AXI_WRITE_SLAVE_INIT_C); + S_AXI_ACLK => axiClk, + S_AXI_ARESETN => axiResetN, + S_AXI_AWID => (others => '0'), + S_AXI_AWADDR => (others => '0'), + S_AXI_AWLEN => (others => '0'), + S_AXI_AWSIZE => (others => '0'), + S_AXI_AWBURST => (others => '0'), + S_AXI_AWLOCK => (others => '0'), + S_AXI_AWCACHE => (others => '0'), + S_AXI_AWPROT => (others => '0'), + S_AXI_AWREGION => (others => '0'), + S_AXI_AWQOS => (others => '0'), + S_AXI_AWVALID => '0', + S_AXI_AWREADY => open, + S_AXI_WID => (others => '0'), + S_AXI_WDATA => (others => '0'), + S_AXI_WSTRB => (others => '0'), + S_AXI_WLAST => '0', + S_AXI_WVALID => '0', + S_AXI_WREADY => open, + S_AXI_BID => open, + S_AXI_BRESP => open, + S_AXI_BVALID => open, + S_AXI_BREADY => '0', + S_AXI_ARID => S1_AXI_ARID, + S_AXI_ARADDR => S1_AXI_ARADDR, + S_AXI_ARLEN => S1_AXI_ARLEN, + S_AXI_ARSIZE => S1_AXI_ARSIZE, + S_AXI_ARBURST => S1_AXI_ARBURST, + S_AXI_ARLOCK => '0' & S1_AXI_ARLOCK, + S_AXI_ARCACHE => S1_AXI_ARCACHE, + S_AXI_ARPROT => S1_AXI_ARPROT, + S_AXI_ARREGION => S1_AXI_ARREGION, + S_AXI_ARQOS => S1_AXI_ARQOS, + S_AXI_ARVALID => S1_AXI_ARVALID, + S_AXI_ARREADY => S1_AXI_ARREADY, + S_AXI_RID => S1_AXI_RID, + S_AXI_RDATA => S1_AXI_RDATA, + S_AXI_RRESP => S1_AXI_RRESP, + S_AXI_RLAST => S1_AXI_RLAST, + S_AXI_RVALID => S1_AXI_RVALID, + S_AXI_RREADY => S1_AXI_RREADY, + axiClk => open, + axiRst => open, + axiReadMaster => sAxiReadMasters(1), + axiReadSlave => sAxiReadSlaves(1), + axiWriteMaster => open, + axiWriteSlave => AXI_WRITE_SLAVE_INIT_C); U_M : entity surf.MasterAxiIpIntegrator generic map ( @@ -218,54 +218,54 @@ begin ADDR_WIDTH => ADDR_WIDTH_G, DATA_WIDTH => DATA_WIDTH_G) port map ( - M_AXI_ACLK => axiClk, - M_AXI_ARESETN => axiResetN, - M_AXI_AWID => open, - M_AXI_AWADDR => open, - M_AXI_AWLEN => open, - M_AXI_AWSIZE => open, - M_AXI_AWBURST => open, - M_AXI_AWLOCK => open, - M_AXI_AWCACHE => open, - M_AXI_AWPROT => open, - M_AXI_AWREGION => open, - M_AXI_AWQOS => open, - M_AXI_AWVALID => open, - M_AXI_AWREADY => '0', - M_AXI_WID => open, - M_AXI_WDATA => open, - M_AXI_WSTRB => open, - M_AXI_WLAST => open, - M_AXI_WVALID => open, - M_AXI_WREADY => '0', - M_AXI_BID => (others => '0'), - M_AXI_BRESP => (others => '0'), - M_AXI_BVALID => '0', - M_AXI_BREADY => open, - M_AXI_ARID => M_AXI_ARID, - M_AXI_ARADDR => M_AXI_ARADDR, - M_AXI_ARLEN => M_AXI_ARLEN, - M_AXI_ARSIZE => M_AXI_ARSIZE, - M_AXI_ARBURST => M_AXI_ARBURST, - M_AXI_ARLOCK => mAxiArLock, - M_AXI_ARCACHE => M_AXI_ARCACHE, - M_AXI_ARPROT => M_AXI_ARPROT, - M_AXI_ARREGION => M_AXI_ARREGION, - M_AXI_ARQOS => M_AXI_ARQOS, - M_AXI_ARVALID => M_AXI_ARVALID, - M_AXI_ARREADY => M_AXI_ARREADY, - M_AXI_RID => M_AXI_RID, - M_AXI_RDATA => M_AXI_RDATA, - M_AXI_RRESP => M_AXI_RRESP, - M_AXI_RLAST => M_AXI_RLAST, - M_AXI_RVALID => M_AXI_RVALID, - M_AXI_RREADY => M_AXI_RREADY, - axiClk => open, - axiRst => open, - axiReadMaster => mAxiReadMaster, - axiReadSlave => mAxiReadSlave, - axiWriteMaster => AXI_WRITE_MASTER_INIT_C, - axiWriteSlave => open); + M_AXI_ACLK => axiClk, + M_AXI_ARESETN => axiResetN, + M_AXI_AWID => open, + M_AXI_AWADDR => open, + M_AXI_AWLEN => open, + M_AXI_AWSIZE => open, + M_AXI_AWBURST => open, + M_AXI_AWLOCK => open, + M_AXI_AWCACHE => open, + M_AXI_AWPROT => open, + M_AXI_AWREGION => open, + M_AXI_AWQOS => open, + M_AXI_AWVALID => open, + M_AXI_AWREADY => '0', + M_AXI_WID => open, + M_AXI_WDATA => open, + M_AXI_WSTRB => open, + M_AXI_WLAST => open, + M_AXI_WVALID => open, + M_AXI_WREADY => '0', + M_AXI_BID => (others => '0'), + M_AXI_BRESP => (others => '0'), + M_AXI_BVALID => '0', + M_AXI_BREADY => open, + M_AXI_ARID => M_AXI_ARID, + M_AXI_ARADDR => M_AXI_ARADDR, + M_AXI_ARLEN => M_AXI_ARLEN, + M_AXI_ARSIZE => M_AXI_ARSIZE, + M_AXI_ARBURST => M_AXI_ARBURST, + M_AXI_ARLOCK => mAxiArLock, + M_AXI_ARCACHE => M_AXI_ARCACHE, + M_AXI_ARPROT => M_AXI_ARPROT, + M_AXI_ARREGION => M_AXI_ARREGION, + M_AXI_ARQOS => M_AXI_ARQOS, + M_AXI_ARVALID => M_AXI_ARVALID, + M_AXI_ARREADY => M_AXI_ARREADY, + M_AXI_RID => M_AXI_RID, + M_AXI_RDATA => M_AXI_RDATA, + M_AXI_RRESP => M_AXI_RRESP, + M_AXI_RLAST => M_AXI_RLAST, + M_AXI_RVALID => M_AXI_RVALID, + M_AXI_RREADY => M_AXI_RREADY, + axiClk => open, + axiRst => open, + axiReadMaster => mAxiReadMaster, + axiReadSlave => mAxiReadSlave, + axiWriteMaster => AXI_WRITE_MASTER_INIT_C, + axiWriteSlave => open); U_DUT : entity surf.AxiReadPathMux generic map ( diff --git a/axi/axi4/ip_integrator/AxiResizeIpIntegrator.vhd b/axi/axi4/ip_integrator/AxiResizeIpIntegrator.vhd index 6fafb2e139..f34fcb7759 100644 --- a/axi/axi4/ip_integrator/AxiResizeIpIntegrator.vhd +++ b/axi/axi4/ip_integrator/AxiResizeIpIntegrator.vhd @@ -116,9 +116,9 @@ architecture rtl of AxiResizeIpIntegrator is constant SLAVE_AXI_CONFIG_C : AxiConfigType := axiConfig(ADDR_WIDTH_G, SLAVE_DATA_BYTES_G, ID_WIDTH_G, 8); constant MASTER_AXI_CONFIG_C : AxiConfigType := axiConfig(ADDR_WIDTH_G, MASTER_DATA_BYTES_G, ID_WIDTH_G, 8); - signal axiResetN : sl := '1'; - signal mAxiAwLock : slv(1 downto 0) := (others => '0'); - signal mAxiArLock : slv(1 downto 0) := (others => '0'); + signal axiResetN : sl := '1'; + signal mAxiAwLock : slv(1 downto 0) := (others => '0'); + signal mAxiArLock : slv(1 downto 0) := (others => '0'); signal sAxiReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; signal sAxiReadSlave : AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; signal sAxiWriteMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; @@ -142,54 +142,54 @@ begin ADDR_WIDTH => ADDR_WIDTH_G, DATA_WIDTH => SLAVE_DATA_BYTES_G*8) port map ( - S_AXI_ACLK => axiClk, - S_AXI_ARESETN => axiResetN, - S_AXI_AWID => S_AXI_AWID, - S_AXI_AWADDR => S_AXI_AWADDR, - S_AXI_AWLEN => S_AXI_AWLEN, - S_AXI_AWSIZE => S_AXI_AWSIZE, - S_AXI_AWBURST => S_AXI_AWBURST, - S_AXI_AWLOCK => '0' & S_AXI_AWLOCK, - S_AXI_AWCACHE => S_AXI_AWCACHE, - S_AXI_AWPROT => S_AXI_AWPROT, - S_AXI_AWREGION => S_AXI_AWREGION, - S_AXI_AWQOS => S_AXI_AWQOS, - S_AXI_AWVALID => S_AXI_AWVALID, - S_AXI_AWREADY => S_AXI_AWREADY, - S_AXI_WID => S_AXI_WID, - S_AXI_WDATA => S_AXI_WDATA, - S_AXI_WSTRB => S_AXI_WSTRB, - S_AXI_WLAST => S_AXI_WLAST, - S_AXI_WVALID => S_AXI_WVALID, - S_AXI_WREADY => S_AXI_WREADY, - S_AXI_BID => S_AXI_BID, - S_AXI_BRESP => S_AXI_BRESP, - S_AXI_BVALID => S_AXI_BVALID, - S_AXI_BREADY => S_AXI_BREADY, - S_AXI_ARID => S_AXI_ARID, - S_AXI_ARADDR => S_AXI_ARADDR, - S_AXI_ARLEN => S_AXI_ARLEN, - S_AXI_ARSIZE => S_AXI_ARSIZE, - S_AXI_ARBURST => S_AXI_ARBURST, - S_AXI_ARLOCK => '0' & S_AXI_ARLOCK, - S_AXI_ARCACHE => S_AXI_ARCACHE, - S_AXI_ARPROT => S_AXI_ARPROT, - S_AXI_ARREGION => S_AXI_ARREGION, - S_AXI_ARQOS => S_AXI_ARQOS, - S_AXI_ARVALID => S_AXI_ARVALID, - S_AXI_ARREADY => S_AXI_ARREADY, - S_AXI_RID => S_AXI_RID, - S_AXI_RDATA => S_AXI_RDATA, - S_AXI_RRESP => S_AXI_RRESP, - S_AXI_RLAST => S_AXI_RLAST, - S_AXI_RVALID => S_AXI_RVALID, - S_AXI_RREADY => S_AXI_RREADY, - axiClk => open, - axiRst => open, - axiReadMaster => sAxiReadMaster, - axiReadSlave => sAxiReadSlave, - axiWriteMaster => sAxiWriteMaster, - axiWriteSlave => sAxiWriteSlave); + S_AXI_ACLK => axiClk, + S_AXI_ARESETN => axiResetN, + S_AXI_AWID => S_AXI_AWID, + S_AXI_AWADDR => S_AXI_AWADDR, + S_AXI_AWLEN => S_AXI_AWLEN, + S_AXI_AWSIZE => S_AXI_AWSIZE, + S_AXI_AWBURST => S_AXI_AWBURST, + S_AXI_AWLOCK => '0' & S_AXI_AWLOCK, + S_AXI_AWCACHE => S_AXI_AWCACHE, + S_AXI_AWPROT => S_AXI_AWPROT, + S_AXI_AWREGION => S_AXI_AWREGION, + S_AXI_AWQOS => S_AXI_AWQOS, + S_AXI_AWVALID => S_AXI_AWVALID, + S_AXI_AWREADY => S_AXI_AWREADY, + S_AXI_WID => S_AXI_WID, + S_AXI_WDATA => S_AXI_WDATA, + S_AXI_WSTRB => S_AXI_WSTRB, + S_AXI_WLAST => S_AXI_WLAST, + S_AXI_WVALID => S_AXI_WVALID, + S_AXI_WREADY => S_AXI_WREADY, + S_AXI_BID => S_AXI_BID, + S_AXI_BRESP => S_AXI_BRESP, + S_AXI_BVALID => S_AXI_BVALID, + S_AXI_BREADY => S_AXI_BREADY, + S_AXI_ARID => S_AXI_ARID, + S_AXI_ARADDR => S_AXI_ARADDR, + S_AXI_ARLEN => S_AXI_ARLEN, + S_AXI_ARSIZE => S_AXI_ARSIZE, + S_AXI_ARBURST => S_AXI_ARBURST, + S_AXI_ARLOCK => '0' & S_AXI_ARLOCK, + S_AXI_ARCACHE => S_AXI_ARCACHE, + S_AXI_ARPROT => S_AXI_ARPROT, + S_AXI_ARREGION => S_AXI_ARREGION, + S_AXI_ARQOS => S_AXI_ARQOS, + S_AXI_ARVALID => S_AXI_ARVALID, + S_AXI_ARREADY => S_AXI_ARREADY, + S_AXI_RID => S_AXI_RID, + S_AXI_RDATA => S_AXI_RDATA, + S_AXI_RRESP => S_AXI_RRESP, + S_AXI_RLAST => S_AXI_RLAST, + S_AXI_RVALID => S_AXI_RVALID, + S_AXI_RREADY => S_AXI_RREADY, + axiClk => open, + axiRst => open, + axiReadMaster => sAxiReadMaster, + axiReadSlave => sAxiReadSlave, + axiWriteMaster => sAxiWriteMaster, + axiWriteSlave => sAxiWriteSlave); U_M : entity surf.MasterAxiIpIntegrator generic map ( @@ -198,54 +198,54 @@ begin ADDR_WIDTH => ADDR_WIDTH_G, DATA_WIDTH => MASTER_DATA_BYTES_G*8) port map ( - M_AXI_ACLK => axiClk, - M_AXI_ARESETN => axiResetN, - M_AXI_AWID => M_AXI_AWID, - M_AXI_AWADDR => M_AXI_AWADDR, - M_AXI_AWLEN => M_AXI_AWLEN, - M_AXI_AWSIZE => M_AXI_AWSIZE, - M_AXI_AWBURST => M_AXI_AWBURST, - M_AXI_AWLOCK => mAxiAwLock, - M_AXI_AWCACHE => M_AXI_AWCACHE, - M_AXI_AWPROT => M_AXI_AWPROT, - M_AXI_AWREGION => M_AXI_AWREGION, - M_AXI_AWQOS => M_AXI_AWQOS, - M_AXI_AWVALID => M_AXI_AWVALID, - M_AXI_AWREADY => M_AXI_AWREADY, - M_AXI_WID => M_AXI_WID, - M_AXI_WDATA => M_AXI_WDATA, - M_AXI_WSTRB => M_AXI_WSTRB, - M_AXI_WLAST => M_AXI_WLAST, - M_AXI_WVALID => M_AXI_WVALID, - M_AXI_WREADY => M_AXI_WREADY, - M_AXI_BID => M_AXI_BID, - M_AXI_BRESP => M_AXI_BRESP, - M_AXI_BVALID => M_AXI_BVALID, - M_AXI_BREADY => M_AXI_BREADY, - M_AXI_ARID => M_AXI_ARID, - M_AXI_ARADDR => M_AXI_ARADDR, - M_AXI_ARLEN => M_AXI_ARLEN, - M_AXI_ARSIZE => M_AXI_ARSIZE, - M_AXI_ARBURST => M_AXI_ARBURST, - M_AXI_ARLOCK => mAxiArLock, - M_AXI_ARCACHE => M_AXI_ARCACHE, - M_AXI_ARPROT => M_AXI_ARPROT, - M_AXI_ARREGION => M_AXI_ARREGION, - M_AXI_ARQOS => M_AXI_ARQOS, - M_AXI_ARVALID => M_AXI_ARVALID, - M_AXI_ARREADY => M_AXI_ARREADY, - M_AXI_RID => M_AXI_RID, - M_AXI_RDATA => M_AXI_RDATA, - M_AXI_RRESP => M_AXI_RRESP, - M_AXI_RLAST => M_AXI_RLAST, - M_AXI_RVALID => M_AXI_RVALID, - M_AXI_RREADY => M_AXI_RREADY, - axiClk => open, - axiRst => open, - axiReadMaster => mAxiReadMaster, - axiReadSlave => mAxiReadSlave, - axiWriteMaster => mAxiWriteMaster, - axiWriteSlave => mAxiWriteSlave); + M_AXI_ACLK => axiClk, + M_AXI_ARESETN => axiResetN, + M_AXI_AWID => M_AXI_AWID, + M_AXI_AWADDR => M_AXI_AWADDR, + M_AXI_AWLEN => M_AXI_AWLEN, + M_AXI_AWSIZE => M_AXI_AWSIZE, + M_AXI_AWBURST => M_AXI_AWBURST, + M_AXI_AWLOCK => mAxiAwLock, + M_AXI_AWCACHE => M_AXI_AWCACHE, + M_AXI_AWPROT => M_AXI_AWPROT, + M_AXI_AWREGION => M_AXI_AWREGION, + M_AXI_AWQOS => M_AXI_AWQOS, + M_AXI_AWVALID => M_AXI_AWVALID, + M_AXI_AWREADY => M_AXI_AWREADY, + M_AXI_WID => M_AXI_WID, + M_AXI_WDATA => M_AXI_WDATA, + M_AXI_WSTRB => M_AXI_WSTRB, + M_AXI_WLAST => M_AXI_WLAST, + M_AXI_WVALID => M_AXI_WVALID, + M_AXI_WREADY => M_AXI_WREADY, + M_AXI_BID => M_AXI_BID, + M_AXI_BRESP => M_AXI_BRESP, + M_AXI_BVALID => M_AXI_BVALID, + M_AXI_BREADY => M_AXI_BREADY, + M_AXI_ARID => M_AXI_ARID, + M_AXI_ARADDR => M_AXI_ARADDR, + M_AXI_ARLEN => M_AXI_ARLEN, + M_AXI_ARSIZE => M_AXI_ARSIZE, + M_AXI_ARBURST => M_AXI_ARBURST, + M_AXI_ARLOCK => mAxiArLock, + M_AXI_ARCACHE => M_AXI_ARCACHE, + M_AXI_ARPROT => M_AXI_ARPROT, + M_AXI_ARREGION => M_AXI_ARREGION, + M_AXI_ARQOS => M_AXI_ARQOS, + M_AXI_ARVALID => M_AXI_ARVALID, + M_AXI_ARREADY => M_AXI_ARREADY, + M_AXI_RID => M_AXI_RID, + M_AXI_RDATA => M_AXI_RDATA, + M_AXI_RRESP => M_AXI_RRESP, + M_AXI_RLAST => M_AXI_RLAST, + M_AXI_RVALID => M_AXI_RVALID, + M_AXI_RREADY => M_AXI_RREADY, + axiClk => open, + axiRst => open, + axiReadMaster => mAxiReadMaster, + axiReadSlave => mAxiReadSlave, + axiWriteMaster => mAxiWriteMaster, + axiWriteSlave => mAxiWriteSlave); U_DUT : entity surf.AxiResize generic map ( diff --git a/axi/axi4/ip_integrator/AxiRingBufferIpIntegrator.vhd b/axi/axi4/ip_integrator/AxiRingBufferIpIntegrator.vhd index 823cab6286..d26470aeaf 100644 --- a/axi/axi4/ip_integrator/AxiRingBufferIpIntegrator.vhd +++ b/axi/axi4/ip_integrator/AxiRingBufferIpIntegrator.vhd @@ -93,14 +93,14 @@ architecture rtl of AxiRingBufferIpIntegrator is tUserBits => 2, tIdBits => 0); - signal axisResetN : sl := '1'; - signal axiResetN : sl := '1'; - signal axisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal axisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal axiWriteMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; - signal axiWriteSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C; - signal axiReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; - signal axiReadSlave : AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; + signal axisResetN : sl := '1'; + signal axiResetN : sl := '1'; + signal axisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal axisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal axiWriteMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; + signal axiWriteSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C; + signal axiReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; + signal axiReadSlave : AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; begin @@ -145,54 +145,54 @@ begin ADDR_WIDTH => 16, DATA_WIDTH => 32) port map ( - M_AXI_ACLK => axiClk, - M_AXI_ARESETN => axiResetN, - M_AXI_AWID => M_AXI_AWID, - M_AXI_AWADDR => M_AXI_AWADDR, - M_AXI_AWLEN => M_AXI_AWLEN, - M_AXI_AWSIZE => M_AXI_AWSIZE, - M_AXI_AWBURST => M_AXI_AWBURST, - M_AXI_AWLOCK => open, - M_AXI_AWCACHE => M_AXI_AWCACHE, - M_AXI_AWPROT => M_AXI_AWPROT, - M_AXI_AWREGION => M_AXI_AWREGION, - M_AXI_AWQOS => M_AXI_AWQOS, - M_AXI_AWVALID => M_AXI_AWVALID, - M_AXI_AWREADY => M_AXI_AWREADY, - M_AXI_WID => M_AXI_WID, - M_AXI_WDATA => M_AXI_WDATA, - M_AXI_WSTRB => M_AXI_WSTRB, - M_AXI_WLAST => M_AXI_WLAST, - M_AXI_WVALID => M_AXI_WVALID, - M_AXI_WREADY => M_AXI_WREADY, - M_AXI_BID => M_AXI_BID, - M_AXI_BRESP => M_AXI_BRESP, - M_AXI_BVALID => M_AXI_BVALID, - M_AXI_BREADY => M_AXI_BREADY, - M_AXI_ARID => M_AXI_ARID, - M_AXI_ARADDR => M_AXI_ARADDR, - M_AXI_ARLEN => M_AXI_ARLEN, - M_AXI_ARSIZE => M_AXI_ARSIZE, - M_AXI_ARBURST => M_AXI_ARBURST, - M_AXI_ARLOCK => open, - M_AXI_ARCACHE => M_AXI_ARCACHE, - M_AXI_ARPROT => M_AXI_ARPROT, - M_AXI_ARREGION => M_AXI_ARREGION, - M_AXI_ARQOS => M_AXI_ARQOS, - M_AXI_ARVALID => M_AXI_ARVALID, - M_AXI_ARREADY => M_AXI_ARREADY, - M_AXI_RID => M_AXI_RID, - M_AXI_RDATA => M_AXI_RDATA, - M_AXI_RRESP => M_AXI_RRESP, - M_AXI_RLAST => M_AXI_RLAST, - M_AXI_RVALID => M_AXI_RVALID, - M_AXI_RREADY => M_AXI_RREADY, - axiClk => open, - axiRst => open, - axiReadMaster => axiReadMaster, - axiReadSlave => axiReadSlave, - axiWriteMaster => axiWriteMaster, - axiWriteSlave => axiWriteSlave); + M_AXI_ACLK => axiClk, + M_AXI_ARESETN => axiResetN, + M_AXI_AWID => M_AXI_AWID, + M_AXI_AWADDR => M_AXI_AWADDR, + M_AXI_AWLEN => M_AXI_AWLEN, + M_AXI_AWSIZE => M_AXI_AWSIZE, + M_AXI_AWBURST => M_AXI_AWBURST, + M_AXI_AWLOCK => open, + M_AXI_AWCACHE => M_AXI_AWCACHE, + M_AXI_AWPROT => M_AXI_AWPROT, + M_AXI_AWREGION => M_AXI_AWREGION, + M_AXI_AWQOS => M_AXI_AWQOS, + M_AXI_AWVALID => M_AXI_AWVALID, + M_AXI_AWREADY => M_AXI_AWREADY, + M_AXI_WID => M_AXI_WID, + M_AXI_WDATA => M_AXI_WDATA, + M_AXI_WSTRB => M_AXI_WSTRB, + M_AXI_WLAST => M_AXI_WLAST, + M_AXI_WVALID => M_AXI_WVALID, + M_AXI_WREADY => M_AXI_WREADY, + M_AXI_BID => M_AXI_BID, + M_AXI_BRESP => M_AXI_BRESP, + M_AXI_BVALID => M_AXI_BVALID, + M_AXI_BREADY => M_AXI_BREADY, + M_AXI_ARID => M_AXI_ARID, + M_AXI_ARADDR => M_AXI_ARADDR, + M_AXI_ARLEN => M_AXI_ARLEN, + M_AXI_ARSIZE => M_AXI_ARSIZE, + M_AXI_ARBURST => M_AXI_ARBURST, + M_AXI_ARLOCK => open, + M_AXI_ARCACHE => M_AXI_ARCACHE, + M_AXI_ARPROT => M_AXI_ARPROT, + M_AXI_ARREGION => M_AXI_ARREGION, + M_AXI_ARQOS => M_AXI_ARQOS, + M_AXI_ARVALID => M_AXI_ARVALID, + M_AXI_ARREADY => M_AXI_ARREADY, + M_AXI_RID => M_AXI_RID, + M_AXI_RDATA => M_AXI_RDATA, + M_AXI_RRESP => M_AXI_RRESP, + M_AXI_RLAST => M_AXI_RLAST, + M_AXI_RVALID => M_AXI_RVALID, + M_AXI_RREADY => M_AXI_RREADY, + axiClk => open, + axiRst => open, + axiReadMaster => axiReadMaster, + axiReadSlave => axiReadSlave, + axiWriteMaster => axiWriteMaster, + axiWriteSlave => axiWriteSlave); M_AXI_AWLOCK <= '0'; M_AXI_ARLOCK <= '0'; diff --git a/axi/axi4/ip_integrator/AxiWriteEmulateIpIntegrator.vhd b/axi/axi4/ip_integrator/AxiWriteEmulateIpIntegrator.vhd index cbc8802388..82bf19a200 100644 --- a/axi/axi4/ip_integrator/AxiWriteEmulateIpIntegrator.vhd +++ b/axi/axi4/ip_integrator/AxiWriteEmulateIpIntegrator.vhd @@ -58,7 +58,7 @@ architecture rtl of AxiWriteEmulateIpIntegrator is ID_BITS_C => 8, LEN_BITS_C => 8); - signal axiResetN : sl := '1'; + signal axiResetN : sl := '1'; signal axiWriteMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; signal axiWriteSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C; @@ -76,54 +76,54 @@ begin ADDR_WIDTH => 16, DATA_WIDTH => 32) port map ( - S_AXI_ACLK => axiClk, - S_AXI_ARESETN => axiResetN, - S_AXI_AWID => S_AXI_AWID, - S_AXI_AWADDR => S_AXI_AWADDR, - S_AXI_AWLEN => S_AXI_AWLEN, - S_AXI_AWSIZE => S_AXI_AWSIZE, - S_AXI_AWBURST => S_AXI_AWBURST, - S_AXI_AWLOCK => S_AXI_AWLOCK, - S_AXI_AWCACHE => S_AXI_AWCACHE, - S_AXI_AWPROT => S_AXI_AWPROT, - S_AXI_AWREGION => S_AXI_AWREGION, - S_AXI_AWQOS => S_AXI_AWQOS, - S_AXI_AWVALID => S_AXI_AWVALID, - S_AXI_AWREADY => S_AXI_AWREADY, - S_AXI_WID => S_AXI_WID, - S_AXI_WDATA => S_AXI_WDATA, - S_AXI_WSTRB => S_AXI_WSTRB, - S_AXI_WLAST => S_AXI_WLAST, - S_AXI_WVALID => S_AXI_WVALID, - S_AXI_WREADY => S_AXI_WREADY, - S_AXI_BID => S_AXI_BID, - S_AXI_BRESP => S_AXI_BRESP, - S_AXI_BVALID => S_AXI_BVALID, - S_AXI_BREADY => S_AXI_BREADY, - S_AXI_ARID => (others => '0'), - S_AXI_ARADDR => (others => '0'), - S_AXI_ARLEN => (others => '0'), - S_AXI_ARSIZE => (others => '0'), - S_AXI_ARBURST => (others => '0'), - S_AXI_ARLOCK => (others => '0'), - S_AXI_ARCACHE => (others => '0'), - S_AXI_ARPROT => (others => '0'), - S_AXI_ARREGION => (others => '0'), - S_AXI_ARQOS => (others => '0'), - S_AXI_ARVALID => '0', - S_AXI_ARREADY => open, - S_AXI_RID => open, - S_AXI_RDATA => open, - S_AXI_RRESP => open, - S_AXI_RLAST => open, - S_AXI_RVALID => open, - S_AXI_RREADY => '0', - axiClk => open, - axiRst => open, - axiReadMaster => open, - axiReadSlave => AXI_READ_SLAVE_INIT_C, - axiWriteMaster => axiWriteMaster, - axiWriteSlave => axiWriteSlave); + S_AXI_ACLK => axiClk, + S_AXI_ARESETN => axiResetN, + S_AXI_AWID => S_AXI_AWID, + S_AXI_AWADDR => S_AXI_AWADDR, + S_AXI_AWLEN => S_AXI_AWLEN, + S_AXI_AWSIZE => S_AXI_AWSIZE, + S_AXI_AWBURST => S_AXI_AWBURST, + S_AXI_AWLOCK => S_AXI_AWLOCK, + S_AXI_AWCACHE => S_AXI_AWCACHE, + S_AXI_AWPROT => S_AXI_AWPROT, + S_AXI_AWREGION => S_AXI_AWREGION, + S_AXI_AWQOS => S_AXI_AWQOS, + S_AXI_AWVALID => S_AXI_AWVALID, + S_AXI_AWREADY => S_AXI_AWREADY, + S_AXI_WID => S_AXI_WID, + S_AXI_WDATA => S_AXI_WDATA, + S_AXI_WSTRB => S_AXI_WSTRB, + S_AXI_WLAST => S_AXI_WLAST, + S_AXI_WVALID => S_AXI_WVALID, + S_AXI_WREADY => S_AXI_WREADY, + S_AXI_BID => S_AXI_BID, + S_AXI_BRESP => S_AXI_BRESP, + S_AXI_BVALID => S_AXI_BVALID, + S_AXI_BREADY => S_AXI_BREADY, + S_AXI_ARID => (others => '0'), + S_AXI_ARADDR => (others => '0'), + S_AXI_ARLEN => (others => '0'), + S_AXI_ARSIZE => (others => '0'), + S_AXI_ARBURST => (others => '0'), + S_AXI_ARLOCK => (others => '0'), + S_AXI_ARCACHE => (others => '0'), + S_AXI_ARPROT => (others => '0'), + S_AXI_ARREGION => (others => '0'), + S_AXI_ARQOS => (others => '0'), + S_AXI_ARVALID => '0', + S_AXI_ARREADY => open, + S_AXI_RID => open, + S_AXI_RDATA => open, + S_AXI_RRESP => open, + S_AXI_RLAST => open, + S_AXI_RVALID => open, + S_AXI_RREADY => '0', + axiClk => open, + axiRst => open, + axiReadMaster => open, + axiReadSlave => AXI_READ_SLAVE_INIT_C, + axiWriteMaster => axiWriteMaster, + axiWriteSlave => axiWriteSlave); --------------------------------------------------------------------------- -- DUT diff --git a/axi/axi4/ip_integrator/AxiWritePathFifoIpIntegrator.vhd b/axi/axi4/ip_integrator/AxiWritePathFifoIpIntegrator.vhd index 25dcfa9f8b..9b25835371 100644 --- a/axi/axi4/ip_integrator/AxiWritePathFifoIpIntegrator.vhd +++ b/axi/axi4/ip_integrator/AxiWritePathFifoIpIntegrator.vhd @@ -83,8 +83,8 @@ architecture rtl of AxiWritePathFifoIpIntegrator is ID_BITS_C => ID_WIDTH_G, LEN_BITS_C => 8); - signal sAxiResetN : sl := '1'; - signal mAxiResetN : sl := '1'; + signal sAxiResetN : sl := '1'; + signal mAxiResetN : sl := '1'; signal mAxiAwLock : slv(1 downto 0) := (others => '0'); signal sAxiWriteMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; signal sAxiWriteSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C; @@ -97,10 +97,10 @@ begin --------------------------------------------------------------------------- -- AXI write shims --------------------------------------------------------------------------- - sAxiResetN <= not sAxiRst; - mAxiResetN <= not mAxiRst; + sAxiResetN <= not sAxiRst; + mAxiResetN <= not mAxiRst; M_AXI_AWLOCK <= mAxiAwLock(0); - writePause <= sAxiCtrl.pause; + writePause <= sAxiCtrl.pause; U_S_AXI : entity surf.SlaveAxiIpIntegrator generic map ( @@ -109,54 +109,54 @@ begin ADDR_WIDTH => ADDR_WIDTH_G, DATA_WIDTH => DATA_WIDTH_G) port map ( - S_AXI_ACLK => sAxiClk, - S_AXI_ARESETN => sAxiResetN, - S_AXI_AWID => S_AXI_AWID, - S_AXI_AWADDR => S_AXI_AWADDR, - S_AXI_AWLEN => S_AXI_AWLEN, - S_AXI_AWSIZE => S_AXI_AWSIZE, - S_AXI_AWBURST => S_AXI_AWBURST, - S_AXI_AWLOCK => '0' & S_AXI_AWLOCK, - S_AXI_AWCACHE => S_AXI_AWCACHE, - S_AXI_AWPROT => S_AXI_AWPROT, - S_AXI_AWREGION => (others => '0'), - S_AXI_AWQOS => (others => '0'), - S_AXI_AWVALID => S_AXI_AWVALID, - S_AXI_AWREADY => S_AXI_AWREADY, - S_AXI_WID => S_AXI_WID, - S_AXI_WDATA => S_AXI_WDATA, - S_AXI_WSTRB => S_AXI_WSTRB, - S_AXI_WLAST => S_AXI_WLAST, - S_AXI_WVALID => S_AXI_WVALID, - S_AXI_WREADY => S_AXI_WREADY, - S_AXI_BID => S_AXI_BID, - S_AXI_BRESP => S_AXI_BRESP, - S_AXI_BVALID => S_AXI_BVALID, - S_AXI_BREADY => S_AXI_BREADY, - S_AXI_ARID => (others => '0'), - S_AXI_ARADDR => (others => '0'), - S_AXI_ARLEN => (others => '0'), - S_AXI_ARSIZE => (others => '0'), - S_AXI_ARBURST => (others => '0'), - S_AXI_ARLOCK => (others => '0'), - S_AXI_ARCACHE => (others => '0'), - S_AXI_ARPROT => (others => '0'), - S_AXI_ARREGION => (others => '0'), - S_AXI_ARQOS => (others => '0'), - S_AXI_ARVALID => '0', - S_AXI_ARREADY => open, - S_AXI_RID => open, - S_AXI_RDATA => open, - S_AXI_RRESP => open, - S_AXI_RLAST => open, - S_AXI_RVALID => open, - S_AXI_RREADY => '0', - axiClk => open, - axiRst => open, - axiReadMaster => open, - axiReadSlave => AXI_READ_SLAVE_INIT_C, - axiWriteMaster => sAxiWriteMaster, - axiWriteSlave => sAxiWriteSlave); + S_AXI_ACLK => sAxiClk, + S_AXI_ARESETN => sAxiResetN, + S_AXI_AWID => S_AXI_AWID, + S_AXI_AWADDR => S_AXI_AWADDR, + S_AXI_AWLEN => S_AXI_AWLEN, + S_AXI_AWSIZE => S_AXI_AWSIZE, + S_AXI_AWBURST => S_AXI_AWBURST, + S_AXI_AWLOCK => '0' & S_AXI_AWLOCK, + S_AXI_AWCACHE => S_AXI_AWCACHE, + S_AXI_AWPROT => S_AXI_AWPROT, + S_AXI_AWREGION => (others => '0'), + S_AXI_AWQOS => (others => '0'), + S_AXI_AWVALID => S_AXI_AWVALID, + S_AXI_AWREADY => S_AXI_AWREADY, + S_AXI_WID => S_AXI_WID, + S_AXI_WDATA => S_AXI_WDATA, + S_AXI_WSTRB => S_AXI_WSTRB, + S_AXI_WLAST => S_AXI_WLAST, + S_AXI_WVALID => S_AXI_WVALID, + S_AXI_WREADY => S_AXI_WREADY, + S_AXI_BID => S_AXI_BID, + S_AXI_BRESP => S_AXI_BRESP, + S_AXI_BVALID => S_AXI_BVALID, + S_AXI_BREADY => S_AXI_BREADY, + S_AXI_ARID => (others => '0'), + S_AXI_ARADDR => (others => '0'), + S_AXI_ARLEN => (others => '0'), + S_AXI_ARSIZE => (others => '0'), + S_AXI_ARBURST => (others => '0'), + S_AXI_ARLOCK => (others => '0'), + S_AXI_ARCACHE => (others => '0'), + S_AXI_ARPROT => (others => '0'), + S_AXI_ARREGION => (others => '0'), + S_AXI_ARQOS => (others => '0'), + S_AXI_ARVALID => '0', + S_AXI_ARREADY => open, + S_AXI_RID => open, + S_AXI_RDATA => open, + S_AXI_RRESP => open, + S_AXI_RLAST => open, + S_AXI_RVALID => open, + S_AXI_RREADY => '0', + axiClk => open, + axiRst => open, + axiReadMaster => open, + axiReadSlave => AXI_READ_SLAVE_INIT_C, + axiWriteMaster => sAxiWriteMaster, + axiWriteSlave => sAxiWriteSlave); U_M_AXI : entity surf.MasterAxiIpIntegrator generic map ( @@ -165,54 +165,54 @@ begin ADDR_WIDTH => ADDR_WIDTH_G, DATA_WIDTH => DATA_WIDTH_G) port map ( - M_AXI_ACLK => mAxiClk, - M_AXI_ARESETN => mAxiResetN, - M_AXI_AWID => M_AXI_AWID, - M_AXI_AWADDR => M_AXI_AWADDR, - M_AXI_AWLEN => M_AXI_AWLEN, - M_AXI_AWSIZE => M_AXI_AWSIZE, - M_AXI_AWBURST => M_AXI_AWBURST, - M_AXI_AWLOCK => mAxiAwLock, - M_AXI_AWCACHE => M_AXI_AWCACHE, - M_AXI_AWPROT => M_AXI_AWPROT, - M_AXI_AWREGION => M_AXI_AWREGION, - M_AXI_AWQOS => M_AXI_AWQOS, - M_AXI_AWVALID => M_AXI_AWVALID, - M_AXI_AWREADY => M_AXI_AWREADY, - M_AXI_WID => M_AXI_WID, - M_AXI_WDATA => M_AXI_WDATA, - M_AXI_WSTRB => M_AXI_WSTRB, - M_AXI_WLAST => M_AXI_WLAST, - M_AXI_WVALID => M_AXI_WVALID, - M_AXI_WREADY => M_AXI_WREADY, - M_AXI_BID => M_AXI_BID, - M_AXI_BRESP => M_AXI_BRESP, - M_AXI_BVALID => M_AXI_BVALID, - M_AXI_BREADY => M_AXI_BREADY, - M_AXI_ARID => open, - M_AXI_ARADDR => open, - M_AXI_ARLEN => open, - M_AXI_ARSIZE => open, - M_AXI_ARBURST => open, - M_AXI_ARLOCK => open, - M_AXI_ARCACHE => open, - M_AXI_ARPROT => open, - M_AXI_ARREGION => open, - M_AXI_ARQOS => open, - M_AXI_ARVALID => open, - M_AXI_ARREADY => '0', - M_AXI_RID => (others => '0'), - M_AXI_RDATA => (others => '0'), - M_AXI_RRESP => (others => '0'), - M_AXI_RLAST => '0', - M_AXI_RVALID => '0', - M_AXI_RREADY => open, - axiClk => open, - axiRst => open, - axiReadMaster => AXI_READ_MASTER_INIT_C, - axiReadSlave => open, - axiWriteMaster => mAxiWriteMaster, - axiWriteSlave => mAxiWriteSlave); + M_AXI_ACLK => mAxiClk, + M_AXI_ARESETN => mAxiResetN, + M_AXI_AWID => M_AXI_AWID, + M_AXI_AWADDR => M_AXI_AWADDR, + M_AXI_AWLEN => M_AXI_AWLEN, + M_AXI_AWSIZE => M_AXI_AWSIZE, + M_AXI_AWBURST => M_AXI_AWBURST, + M_AXI_AWLOCK => mAxiAwLock, + M_AXI_AWCACHE => M_AXI_AWCACHE, + M_AXI_AWPROT => M_AXI_AWPROT, + M_AXI_AWREGION => M_AXI_AWREGION, + M_AXI_AWQOS => M_AXI_AWQOS, + M_AXI_AWVALID => M_AXI_AWVALID, + M_AXI_AWREADY => M_AXI_AWREADY, + M_AXI_WID => M_AXI_WID, + M_AXI_WDATA => M_AXI_WDATA, + M_AXI_WSTRB => M_AXI_WSTRB, + M_AXI_WLAST => M_AXI_WLAST, + M_AXI_WVALID => M_AXI_WVALID, + M_AXI_WREADY => M_AXI_WREADY, + M_AXI_BID => M_AXI_BID, + M_AXI_BRESP => M_AXI_BRESP, + M_AXI_BVALID => M_AXI_BVALID, + M_AXI_BREADY => M_AXI_BREADY, + M_AXI_ARID => open, + M_AXI_ARADDR => open, + M_AXI_ARLEN => open, + M_AXI_ARSIZE => open, + M_AXI_ARBURST => open, + M_AXI_ARLOCK => open, + M_AXI_ARCACHE => open, + M_AXI_ARPROT => open, + M_AXI_ARREGION => open, + M_AXI_ARQOS => open, + M_AXI_ARVALID => open, + M_AXI_ARREADY => '0', + M_AXI_RID => (others => '0'), + M_AXI_RDATA => (others => '0'), + M_AXI_RRESP => (others => '0'), + M_AXI_RLAST => '0', + M_AXI_RVALID => '0', + M_AXI_RREADY => open, + axiClk => open, + axiRst => open, + axiReadMaster => AXI_READ_MASTER_INIT_C, + axiReadSlave => open, + axiWriteMaster => mAxiWriteMaster, + axiWriteSlave => mAxiWriteSlave); --------------------------------------------------------------------------- -- DUT diff --git a/axi/axi4/ip_integrator/AxiWritePathMuxIpIntegrator.vhd b/axi/axi4/ip_integrator/AxiWritePathMuxIpIntegrator.vhd index 26907090e9..b9262a81b6 100644 --- a/axi/axi4/ip_integrator/AxiWritePathMuxIpIntegrator.vhd +++ b/axi/axi4/ip_integrator/AxiWritePathMuxIpIntegrator.vhd @@ -98,7 +98,7 @@ end entity AxiWritePathMuxIpIntegrator; architecture rtl of AxiWritePathMuxIpIntegrator is - signal axiResetN : sl := '1'; + signal axiResetN : sl := '1'; signal mAxiAwLock : slv(1 downto 0) := (others => '0'); signal sAxiWriteMasters : AxiWriteMasterArray(1 downto 0) := (others => AXI_WRITE_MASTER_INIT_C); signal sAxiWriteSlaves : AxiWriteSlaveArray(1 downto 0) := (others => AXI_WRITE_SLAVE_INIT_C); @@ -118,54 +118,54 @@ begin ADDR_WIDTH => ADDR_WIDTH_G, DATA_WIDTH => DATA_WIDTH_G) port map ( - S_AXI_ACLK => axiClk, - S_AXI_ARESETN => axiResetN, - S_AXI_AWID => S0_AXI_AWID, - S_AXI_AWADDR => S0_AXI_AWADDR, - S_AXI_AWLEN => S0_AXI_AWLEN, - S_AXI_AWSIZE => S0_AXI_AWSIZE, - S_AXI_AWBURST => S0_AXI_AWBURST, - S_AXI_AWLOCK => '0' & S0_AXI_AWLOCK, - S_AXI_AWCACHE => S0_AXI_AWCACHE, - S_AXI_AWPROT => S0_AXI_AWPROT, - S_AXI_AWREGION => S0_AXI_AWREGION, - S_AXI_AWQOS => S0_AXI_AWQOS, - S_AXI_AWVALID => S0_AXI_AWVALID, - S_AXI_AWREADY => S0_AXI_AWREADY, - S_AXI_WID => S0_AXI_WID, - S_AXI_WDATA => S0_AXI_WDATA, - S_AXI_WSTRB => S0_AXI_WSTRB, - S_AXI_WLAST => S0_AXI_WLAST, - S_AXI_WVALID => S0_AXI_WVALID, - S_AXI_WREADY => S0_AXI_WREADY, - S_AXI_BID => S0_AXI_BID, - S_AXI_BRESP => S0_AXI_BRESP, - S_AXI_BVALID => S0_AXI_BVALID, - S_AXI_BREADY => S0_AXI_BREADY, - S_AXI_ARID => (others => '0'), - S_AXI_ARADDR => (others => '0'), - S_AXI_ARLEN => (others => '0'), - S_AXI_ARSIZE => (others => '0'), - S_AXI_ARBURST => (others => '0'), - S_AXI_ARLOCK => (others => '0'), - S_AXI_ARCACHE => (others => '0'), - S_AXI_ARPROT => (others => '0'), - S_AXI_ARREGION => (others => '0'), - S_AXI_ARQOS => (others => '0'), - S_AXI_ARVALID => '0', - S_AXI_ARREADY => open, - S_AXI_RID => open, - S_AXI_RDATA => open, - S_AXI_RRESP => open, - S_AXI_RLAST => open, - S_AXI_RVALID => open, - S_AXI_RREADY => '0', - axiClk => open, - axiRst => open, - axiReadMaster => open, - axiReadSlave => AXI_READ_SLAVE_INIT_C, - axiWriteMaster => sAxiWriteMasters(0), - axiWriteSlave => sAxiWriteSlaves(0)); + S_AXI_ACLK => axiClk, + S_AXI_ARESETN => axiResetN, + S_AXI_AWID => S0_AXI_AWID, + S_AXI_AWADDR => S0_AXI_AWADDR, + S_AXI_AWLEN => S0_AXI_AWLEN, + S_AXI_AWSIZE => S0_AXI_AWSIZE, + S_AXI_AWBURST => S0_AXI_AWBURST, + S_AXI_AWLOCK => '0' & S0_AXI_AWLOCK, + S_AXI_AWCACHE => S0_AXI_AWCACHE, + S_AXI_AWPROT => S0_AXI_AWPROT, + S_AXI_AWREGION => S0_AXI_AWREGION, + S_AXI_AWQOS => S0_AXI_AWQOS, + S_AXI_AWVALID => S0_AXI_AWVALID, + S_AXI_AWREADY => S0_AXI_AWREADY, + S_AXI_WID => S0_AXI_WID, + S_AXI_WDATA => S0_AXI_WDATA, + S_AXI_WSTRB => S0_AXI_WSTRB, + S_AXI_WLAST => S0_AXI_WLAST, + S_AXI_WVALID => S0_AXI_WVALID, + S_AXI_WREADY => S0_AXI_WREADY, + S_AXI_BID => S0_AXI_BID, + S_AXI_BRESP => S0_AXI_BRESP, + S_AXI_BVALID => S0_AXI_BVALID, + S_AXI_BREADY => S0_AXI_BREADY, + S_AXI_ARID => (others => '0'), + S_AXI_ARADDR => (others => '0'), + S_AXI_ARLEN => (others => '0'), + S_AXI_ARSIZE => (others => '0'), + S_AXI_ARBURST => (others => '0'), + S_AXI_ARLOCK => (others => '0'), + S_AXI_ARCACHE => (others => '0'), + S_AXI_ARPROT => (others => '0'), + S_AXI_ARREGION => (others => '0'), + S_AXI_ARQOS => (others => '0'), + S_AXI_ARVALID => '0', + S_AXI_ARREADY => open, + S_AXI_RID => open, + S_AXI_RDATA => open, + S_AXI_RRESP => open, + S_AXI_RLAST => open, + S_AXI_RVALID => open, + S_AXI_RREADY => '0', + axiClk => open, + axiRst => open, + axiReadMaster => open, + axiReadSlave => AXI_READ_SLAVE_INIT_C, + axiWriteMaster => sAxiWriteMasters(0), + axiWriteSlave => sAxiWriteSlaves(0)); U_S1 : entity surf.SlaveAxiIpIntegrator generic map ( @@ -174,54 +174,54 @@ begin ADDR_WIDTH => ADDR_WIDTH_G, DATA_WIDTH => DATA_WIDTH_G) port map ( - S_AXI_ACLK => axiClk, - S_AXI_ARESETN => axiResetN, - S_AXI_AWID => S1_AXI_AWID, - S_AXI_AWADDR => S1_AXI_AWADDR, - S_AXI_AWLEN => S1_AXI_AWLEN, - S_AXI_AWSIZE => S1_AXI_AWSIZE, - S_AXI_AWBURST => S1_AXI_AWBURST, - S_AXI_AWLOCK => '0' & S1_AXI_AWLOCK, - S_AXI_AWCACHE => S1_AXI_AWCACHE, - S_AXI_AWPROT => S1_AXI_AWPROT, - S_AXI_AWREGION => S1_AXI_AWREGION, - S_AXI_AWQOS => S1_AXI_AWQOS, - S_AXI_AWVALID => S1_AXI_AWVALID, - S_AXI_AWREADY => S1_AXI_AWREADY, - S_AXI_WID => S1_AXI_WID, - S_AXI_WDATA => S1_AXI_WDATA, - S_AXI_WSTRB => S1_AXI_WSTRB, - S_AXI_WLAST => S1_AXI_WLAST, - S_AXI_WVALID => S1_AXI_WVALID, - S_AXI_WREADY => S1_AXI_WREADY, - S_AXI_BID => S1_AXI_BID, - S_AXI_BRESP => S1_AXI_BRESP, - S_AXI_BVALID => S1_AXI_BVALID, - S_AXI_BREADY => S1_AXI_BREADY, - S_AXI_ARID => (others => '0'), - S_AXI_ARADDR => (others => '0'), - S_AXI_ARLEN => (others => '0'), - S_AXI_ARSIZE => (others => '0'), - S_AXI_ARBURST => (others => '0'), - S_AXI_ARLOCK => (others => '0'), - S_AXI_ARCACHE => (others => '0'), - S_AXI_ARPROT => (others => '0'), - S_AXI_ARREGION => (others => '0'), - S_AXI_ARQOS => (others => '0'), - S_AXI_ARVALID => '0', - S_AXI_ARREADY => open, - S_AXI_RID => open, - S_AXI_RDATA => open, - S_AXI_RRESP => open, - S_AXI_RLAST => open, - S_AXI_RVALID => open, - S_AXI_RREADY => '0', - axiClk => open, - axiRst => open, - axiReadMaster => open, - axiReadSlave => AXI_READ_SLAVE_INIT_C, - axiWriteMaster => sAxiWriteMasters(1), - axiWriteSlave => sAxiWriteSlaves(1)); + S_AXI_ACLK => axiClk, + S_AXI_ARESETN => axiResetN, + S_AXI_AWID => S1_AXI_AWID, + S_AXI_AWADDR => S1_AXI_AWADDR, + S_AXI_AWLEN => S1_AXI_AWLEN, + S_AXI_AWSIZE => S1_AXI_AWSIZE, + S_AXI_AWBURST => S1_AXI_AWBURST, + S_AXI_AWLOCK => '0' & S1_AXI_AWLOCK, + S_AXI_AWCACHE => S1_AXI_AWCACHE, + S_AXI_AWPROT => S1_AXI_AWPROT, + S_AXI_AWREGION => S1_AXI_AWREGION, + S_AXI_AWQOS => S1_AXI_AWQOS, + S_AXI_AWVALID => S1_AXI_AWVALID, + S_AXI_AWREADY => S1_AXI_AWREADY, + S_AXI_WID => S1_AXI_WID, + S_AXI_WDATA => S1_AXI_WDATA, + S_AXI_WSTRB => S1_AXI_WSTRB, + S_AXI_WLAST => S1_AXI_WLAST, + S_AXI_WVALID => S1_AXI_WVALID, + S_AXI_WREADY => S1_AXI_WREADY, + S_AXI_BID => S1_AXI_BID, + S_AXI_BRESP => S1_AXI_BRESP, + S_AXI_BVALID => S1_AXI_BVALID, + S_AXI_BREADY => S1_AXI_BREADY, + S_AXI_ARID => (others => '0'), + S_AXI_ARADDR => (others => '0'), + S_AXI_ARLEN => (others => '0'), + S_AXI_ARSIZE => (others => '0'), + S_AXI_ARBURST => (others => '0'), + S_AXI_ARLOCK => (others => '0'), + S_AXI_ARCACHE => (others => '0'), + S_AXI_ARPROT => (others => '0'), + S_AXI_ARREGION => (others => '0'), + S_AXI_ARQOS => (others => '0'), + S_AXI_ARVALID => '0', + S_AXI_ARREADY => open, + S_AXI_RID => open, + S_AXI_RDATA => open, + S_AXI_RRESP => open, + S_AXI_RLAST => open, + S_AXI_RVALID => open, + S_AXI_RREADY => '0', + axiClk => open, + axiRst => open, + axiReadMaster => open, + axiReadSlave => AXI_READ_SLAVE_INIT_C, + axiWriteMaster => sAxiWriteMasters(1), + axiWriteSlave => sAxiWriteSlaves(1)); U_M : entity surf.MasterAxiIpIntegrator generic map ( @@ -230,54 +230,54 @@ begin ADDR_WIDTH => ADDR_WIDTH_G, DATA_WIDTH => DATA_WIDTH_G) port map ( - M_AXI_ACLK => axiClk, - M_AXI_ARESETN => axiResetN, - M_AXI_AWID => M_AXI_AWID, - M_AXI_AWADDR => M_AXI_AWADDR, - M_AXI_AWLEN => M_AXI_AWLEN, - M_AXI_AWSIZE => M_AXI_AWSIZE, - M_AXI_AWBURST => M_AXI_AWBURST, - M_AXI_AWLOCK => mAxiAwLock, - M_AXI_AWCACHE => M_AXI_AWCACHE, - M_AXI_AWPROT => M_AXI_AWPROT, - M_AXI_AWREGION => M_AXI_AWREGION, - M_AXI_AWQOS => M_AXI_AWQOS, - M_AXI_AWVALID => M_AXI_AWVALID, - M_AXI_AWREADY => M_AXI_AWREADY, - M_AXI_WID => M_AXI_WID, - M_AXI_WDATA => M_AXI_WDATA, - M_AXI_WSTRB => M_AXI_WSTRB, - M_AXI_WLAST => M_AXI_WLAST, - M_AXI_WVALID => M_AXI_WVALID, - M_AXI_WREADY => M_AXI_WREADY, - M_AXI_BID => M_AXI_BID, - M_AXI_BRESP => M_AXI_BRESP, - M_AXI_BVALID => M_AXI_BVALID, - M_AXI_BREADY => M_AXI_BREADY, - M_AXI_ARID => open, - M_AXI_ARADDR => open, - M_AXI_ARLEN => open, - M_AXI_ARSIZE => open, - M_AXI_ARBURST => open, - M_AXI_ARLOCK => open, - M_AXI_ARCACHE => open, - M_AXI_ARPROT => open, - M_AXI_ARREGION => open, - M_AXI_ARQOS => open, - M_AXI_ARVALID => open, - M_AXI_ARREADY => '0', - M_AXI_RID => (others => '0'), - M_AXI_RDATA => (others => '0'), - M_AXI_RRESP => (others => '0'), - M_AXI_RLAST => '0', - M_AXI_RVALID => '0', - M_AXI_RREADY => open, - axiClk => open, - axiRst => open, - axiReadMaster => AXI_READ_MASTER_INIT_C, - axiReadSlave => open, - axiWriteMaster => mAxiWriteMaster, - axiWriteSlave => mAxiWriteSlave); + M_AXI_ACLK => axiClk, + M_AXI_ARESETN => axiResetN, + M_AXI_AWID => M_AXI_AWID, + M_AXI_AWADDR => M_AXI_AWADDR, + M_AXI_AWLEN => M_AXI_AWLEN, + M_AXI_AWSIZE => M_AXI_AWSIZE, + M_AXI_AWBURST => M_AXI_AWBURST, + M_AXI_AWLOCK => mAxiAwLock, + M_AXI_AWCACHE => M_AXI_AWCACHE, + M_AXI_AWPROT => M_AXI_AWPROT, + M_AXI_AWREGION => M_AXI_AWREGION, + M_AXI_AWQOS => M_AXI_AWQOS, + M_AXI_AWVALID => M_AXI_AWVALID, + M_AXI_AWREADY => M_AXI_AWREADY, + M_AXI_WID => M_AXI_WID, + M_AXI_WDATA => M_AXI_WDATA, + M_AXI_WSTRB => M_AXI_WSTRB, + M_AXI_WLAST => M_AXI_WLAST, + M_AXI_WVALID => M_AXI_WVALID, + M_AXI_WREADY => M_AXI_WREADY, + M_AXI_BID => M_AXI_BID, + M_AXI_BRESP => M_AXI_BRESP, + M_AXI_BVALID => M_AXI_BVALID, + M_AXI_BREADY => M_AXI_BREADY, + M_AXI_ARID => open, + M_AXI_ARADDR => open, + M_AXI_ARLEN => open, + M_AXI_ARSIZE => open, + M_AXI_ARBURST => open, + M_AXI_ARLOCK => open, + M_AXI_ARCACHE => open, + M_AXI_ARPROT => open, + M_AXI_ARREGION => open, + M_AXI_ARQOS => open, + M_AXI_ARVALID => open, + M_AXI_ARREADY => '0', + M_AXI_RID => (others => '0'), + M_AXI_RDATA => (others => '0'), + M_AXI_RRESP => (others => '0'), + M_AXI_RLAST => '0', + M_AXI_RVALID => '0', + M_AXI_RREADY => open, + axiClk => open, + axiRst => open, + axiReadMaster => AXI_READ_MASTER_INIT_C, + axiReadSlave => open, + axiWriteMaster => mAxiWriteMaster, + axiWriteSlave => mAxiWriteSlave); U_DUT : entity surf.AxiWritePathMux generic map ( diff --git a/axi/axi4/rtl/AxiResize.vhd b/axi/axi4/rtl/AxiResize.vhd index 66195d06e4..54df7644e5 100644 --- a/axi/axi4/rtl/AxiResize.vhd +++ b/axi/axi4/rtl/AxiResize.vhd @@ -171,36 +171,36 @@ begin v.rdMaster.rready := '1'; if (ibRdM.rvalid = '1') then - v.rdHold := AXI_READ_SLAVE_INIT_C; + v.rdHold := AXI_READ_SLAVE_INIT_C; v.rdHold.rdata((MST_BYTES_C*8)-1 downto 0) := ibRdM.rdata((MST_BYTES_C*8)-1 downto 0); - v.rdHold.rid := ibRdM.rid; - v.rdHold.rresp := ibRdM.rresp; - v.rdHold.rlast := ibRdM.rlast; - v.rdHold.rvalid := '1'; + v.rdHold.rid := ibRdM.rid; + v.rdHold.rresp := ibRdM.rresp; + v.rdHold.rlast := ibRdM.rlast; + v.rdHold.rvalid := '1'; -- Queue slice 0 immediately while retaining the full -- beat so the remaining narrow slices can drain from -- rdHold without an extra bubble. v.rdSlave.rdata((SLV_BYTES_C*8)-1 downto 0) := ibRdM.rdata((SLV_BYTES_C*8)-1 downto 0); - v.rdSlave.rid := ibRdM.rid; - v.rdSlave.rresp := ibRdM.rresp; - v.rdSlave.rvalid := '1'; - v.rdSlave.rlast := '0'; - v.rdCount := toSlv(1, v.rdCount'length); + v.rdSlave.rid := ibRdM.rid; + v.rdSlave.rresp := ibRdM.rresp; + v.rdSlave.rvalid := '1'; + v.rdSlave.rlast := '0'; + v.rdCount := toSlv(1, v.rdCount'length); end if; else v.rdSlave.rdata((SLV_BYTES_C*8)-1 downto 0) := r.rdHold.rdata((SLV_BYTES_C*8*rdIdx)+((SLV_BYTES_C*8)-1) downto (SLV_BYTES_C*8*rdIdx)); - v.rdSlave.rid := r.rdHold.rid; - v.rdSlave.rresp := r.rdHold.rresp; - v.rdSlave.rvalid := '1'; + v.rdSlave.rid := r.rdHold.rid; + v.rdSlave.rresp := r.rdHold.rresp; + v.rdSlave.rvalid := '1'; if (r.rdCount = (COUNT_C-1)) then - v.rdCount := (others => '0'); - v.rdHold.rvalid := '0'; - v.rdSlave.rlast := r.rdHold.rlast; + v.rdCount := (others => '0'); + v.rdHold.rvalid := '0'; + v.rdSlave.rlast := r.rdHold.rlast; else - v.rdCount := r.rdCount + 1; - v.rdSlave.rlast := '0'; + v.rdCount := r.rdCount + 1; + v.rdSlave.rlast := '0'; end if; end if; diff --git a/axi/bridge/ip_integrator/AxiToAxiLiteIpIntegrator.vhd b/axi/bridge/ip_integrator/AxiToAxiLiteIpIntegrator.vhd index e8e725cff0..c2e8122eee 100644 --- a/axi/bridge/ip_integrator/AxiToAxiLiteIpIntegrator.vhd +++ b/axi/bridge/ip_integrator/AxiToAxiLiteIpIntegrator.vhd @@ -96,15 +96,15 @@ end entity AxiToAxiLiteIpIntegrator; architecture rtl of AxiToAxiLiteIpIntegrator is - signal axiResetN : sl := '1'; - signal axiReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; - signal axiReadSlave : AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; - signal axiWriteMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; - signal axiWriteSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C; - signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; - signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; - signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; - signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + signal axiResetN : sl := '1'; + signal axiReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; + signal axiReadSlave : AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; + signal axiWriteMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; + signal axiWriteSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C; + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; begin @@ -117,54 +117,54 @@ begin ADDR_WIDTH => AXI_ADDR_WIDTH_G, DATA_WIDTH => AXI_DATA_WIDTH_G) port map ( - S_AXI_ACLK => axiClk, - S_AXI_ARESETN => axiResetN, - S_AXI_AWID => S_AXI_AWID, - S_AXI_AWADDR => S_AXI_AWADDR, - S_AXI_AWLEN => S_AXI_AWLEN, - S_AXI_AWSIZE => S_AXI_AWSIZE, - S_AXI_AWBURST => S_AXI_AWBURST, - S_AXI_AWLOCK => '0' & S_AXI_AWLOCK, - S_AXI_AWCACHE => S_AXI_AWCACHE, - S_AXI_AWPROT => S_AXI_AWPROT, - S_AXI_AWREGION => S_AXI_AWREGION, - S_AXI_AWQOS => S_AXI_AWQOS, - S_AXI_AWVALID => S_AXI_AWVALID, - S_AXI_AWREADY => S_AXI_AWREADY, - S_AXI_WID => S_AXI_WID, - S_AXI_WDATA => S_AXI_WDATA, - S_AXI_WSTRB => S_AXI_WSTRB, - S_AXI_WLAST => S_AXI_WLAST, - S_AXI_WVALID => S_AXI_WVALID, - S_AXI_WREADY => S_AXI_WREADY, - S_AXI_BID => S_AXI_BID, - S_AXI_BRESP => S_AXI_BRESP, - S_AXI_BVALID => S_AXI_BVALID, - S_AXI_BREADY => S_AXI_BREADY, - S_AXI_ARID => S_AXI_ARID, - S_AXI_ARADDR => S_AXI_ARADDR, - S_AXI_ARLEN => S_AXI_ARLEN, - S_AXI_ARSIZE => S_AXI_ARSIZE, - S_AXI_ARBURST => S_AXI_ARBURST, - S_AXI_ARLOCK => '0' & S_AXI_ARLOCK, - S_AXI_ARCACHE => S_AXI_ARCACHE, - S_AXI_ARPROT => S_AXI_ARPROT, - S_AXI_ARREGION => S_AXI_ARREGION, - S_AXI_ARQOS => S_AXI_ARQOS, - S_AXI_ARVALID => S_AXI_ARVALID, - S_AXI_ARREADY => S_AXI_ARREADY, - S_AXI_RID => S_AXI_RID, - S_AXI_RDATA => S_AXI_RDATA, - S_AXI_RRESP => S_AXI_RRESP, - S_AXI_RLAST => S_AXI_RLAST, - S_AXI_RVALID => S_AXI_RVALID, - S_AXI_RREADY => S_AXI_RREADY, - axiClk => open, - axiRst => open, - axiReadMaster => axiReadMaster, - axiReadSlave => axiReadSlave, - axiWriteMaster => axiWriteMaster, - axiWriteSlave => axiWriteSlave); + S_AXI_ACLK => axiClk, + S_AXI_ARESETN => axiResetN, + S_AXI_AWID => S_AXI_AWID, + S_AXI_AWADDR => S_AXI_AWADDR, + S_AXI_AWLEN => S_AXI_AWLEN, + S_AXI_AWSIZE => S_AXI_AWSIZE, + S_AXI_AWBURST => S_AXI_AWBURST, + S_AXI_AWLOCK => '0' & S_AXI_AWLOCK, + S_AXI_AWCACHE => S_AXI_AWCACHE, + S_AXI_AWPROT => S_AXI_AWPROT, + S_AXI_AWREGION => S_AXI_AWREGION, + S_AXI_AWQOS => S_AXI_AWQOS, + S_AXI_AWVALID => S_AXI_AWVALID, + S_AXI_AWREADY => S_AXI_AWREADY, + S_AXI_WID => S_AXI_WID, + S_AXI_WDATA => S_AXI_WDATA, + S_AXI_WSTRB => S_AXI_WSTRB, + S_AXI_WLAST => S_AXI_WLAST, + S_AXI_WVALID => S_AXI_WVALID, + S_AXI_WREADY => S_AXI_WREADY, + S_AXI_BID => S_AXI_BID, + S_AXI_BRESP => S_AXI_BRESP, + S_AXI_BVALID => S_AXI_BVALID, + S_AXI_BREADY => S_AXI_BREADY, + S_AXI_ARID => S_AXI_ARID, + S_AXI_ARADDR => S_AXI_ARADDR, + S_AXI_ARLEN => S_AXI_ARLEN, + S_AXI_ARSIZE => S_AXI_ARSIZE, + S_AXI_ARBURST => S_AXI_ARBURST, + S_AXI_ARLOCK => '0' & S_AXI_ARLOCK, + S_AXI_ARCACHE => S_AXI_ARCACHE, + S_AXI_ARPROT => S_AXI_ARPROT, + S_AXI_ARREGION => S_AXI_ARREGION, + S_AXI_ARQOS => S_AXI_ARQOS, + S_AXI_ARVALID => S_AXI_ARVALID, + S_AXI_ARREADY => S_AXI_ARREADY, + S_AXI_RID => S_AXI_RID, + S_AXI_RDATA => S_AXI_RDATA, + S_AXI_RRESP => S_AXI_RRESP, + S_AXI_RLAST => S_AXI_RLAST, + S_AXI_RVALID => S_AXI_RVALID, + S_AXI_RREADY => S_AXI_RREADY, + axiClk => open, + axiRst => open, + axiReadMaster => axiReadMaster, + axiReadSlave => axiReadSlave, + axiWriteMaster => axiWriteMaster, + axiWriteSlave => axiWriteSlave); U_M : entity surf.MasterAxiLiteIpIntegrator generic map ( diff --git a/axi/bridge/ip_integrator/SlvArraytoAxiLiteIpIntegrator.vhd b/axi/bridge/ip_integrator/SlvArraytoAxiLiteIpIntegrator.vhd index 13dfbe7e83..3c52f736ad 100644 --- a/axi/bridge/ip_integrator/SlvArraytoAxiLiteIpIntegrator.vhd +++ b/axi/bridge/ip_integrator/SlvArraytoAxiLiteIpIntegrator.vhd @@ -50,7 +50,7 @@ end entity SlvArraytoAxiLiteIpIntegrator; architecture rtl of SlvArraytoAxiLiteIpIntegrator is - signal axilResetN : sl := '1'; + signal axilResetN : sl := '1'; signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; diff --git a/axi/dma/ip_integrator/AxiStreamDmaFifoIpIntegrator.vhd b/axi/dma/ip_integrator/AxiStreamDmaFifoIpIntegrator.vhd index e46eee5426..bb6fd419b6 100644 --- a/axi/dma/ip_integrator/AxiStreamDmaFifoIpIntegrator.vhd +++ b/axi/dma/ip_integrator/AxiStreamDmaFifoIpIntegrator.vhd @@ -23,27 +23,27 @@ use surf.AxiStreamPkg.all; entity AxiStreamDmaFifoIpIntegrator is port ( - axiClk : in sl; - axiRst : in sl; - S_AXI_AWADDR : in slv(7 downto 0); - S_AXI_AWPROT : in slv(2 downto 0); - S_AXI_AWVALID : in sl; - S_AXI_AWREADY : out sl; - S_AXI_WDATA : in slv(31 downto 0); - S_AXI_WSTRB : in slv(3 downto 0); - S_AXI_WVALID : in sl; - S_AXI_WREADY : out sl; - S_AXI_BRESP : out slv(1 downto 0); - S_AXI_BVALID : out sl; - S_AXI_BREADY : in sl; - S_AXI_ARADDR : in slv(7 downto 0); - S_AXI_ARPROT : in slv(2 downto 0); - S_AXI_ARVALID : in sl; - S_AXI_ARREADY : out sl; - S_AXI_RDATA : out slv(31 downto 0); - S_AXI_RRESP : out slv(1 downto 0); - S_AXI_RVALID : out sl; - S_AXI_RREADY : in sl); + axiClk : in sl; + axiRst : in sl; + S_AXI_AWADDR : in slv(7 downto 0); + S_AXI_AWPROT : in slv(2 downto 0); + S_AXI_AWVALID : in sl; + S_AXI_AWREADY : out sl; + S_AXI_WDATA : in slv(31 downto 0); + S_AXI_WSTRB : in slv(3 downto 0); + S_AXI_WVALID : in sl; + S_AXI_WREADY : out sl; + S_AXI_BRESP : out slv(1 downto 0); + S_AXI_BVALID : out sl; + S_AXI_BREADY : in sl; + S_AXI_ARADDR : in slv(7 downto 0); + S_AXI_ARPROT : in slv(2 downto 0); + S_AXI_ARVALID : in sl; + S_AXI_ARREADY : out sl; + S_AXI_RDATA : out slv(31 downto 0); + S_AXI_RRESP : out slv(1 downto 0); + S_AXI_RVALID : out sl; + S_AXI_RREADY : in sl); end entity AxiStreamDmaFifoIpIntegrator; architecture rtl of AxiStreamDmaFifoIpIntegrator is @@ -63,7 +63,7 @@ architecture rtl of AxiStreamDmaFifoIpIntegrator is ID_BITS_C => 1, LEN_BITS_C => 8); - signal axilResetN : sl := '1'; + signal axilResetN : sl := '1'; signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; diff --git a/axi/dma/ip_integrator/AxiStreamDmaIpIntegrator.vhd b/axi/dma/ip_integrator/AxiStreamDmaIpIntegrator.vhd index 89c1459c6a..5dd9b49280 100644 --- a/axi/dma/ip_integrator/AxiStreamDmaIpIntegrator.vhd +++ b/axi/dma/ip_integrator/AxiStreamDmaIpIntegrator.vhd @@ -23,30 +23,30 @@ use surf.AxiStreamPkg.all; entity AxiStreamDmaIpIntegrator is port ( - axiClk : in sl; - axiRst : in sl; - interrupt : out sl; - online : out sl; - acknowledge : out sl; - S_AXI_AWADDR : in slv(11 downto 0); - S_AXI_AWPROT : in slv(2 downto 0); - S_AXI_AWVALID : in sl; - S_AXI_AWREADY : out sl; - S_AXI_WDATA : in slv(31 downto 0); - S_AXI_WSTRB : in slv(3 downto 0); - S_AXI_WVALID : in sl; - S_AXI_WREADY : out sl; - S_AXI_BRESP : out slv(1 downto 0); - S_AXI_BVALID : out sl; - S_AXI_BREADY : in sl; - S_AXI_ARADDR : in slv(11 downto 0); - S_AXI_ARPROT : in slv(2 downto 0); - S_AXI_ARVALID : in sl; - S_AXI_ARREADY : out sl; - S_AXI_RDATA : out slv(31 downto 0); - S_AXI_RRESP : out slv(1 downto 0); - S_AXI_RVALID : out sl; - S_AXI_RREADY : in sl); + axiClk : in sl; + axiRst : in sl; + interrupt : out sl; + online : out sl; + acknowledge : out sl; + S_AXI_AWADDR : in slv(11 downto 0); + S_AXI_AWPROT : in slv(2 downto 0); + S_AXI_AWVALID : in sl; + S_AXI_AWREADY : out sl; + S_AXI_WDATA : in slv(31 downto 0); + S_AXI_WSTRB : in slv(3 downto 0); + S_AXI_WVALID : in sl; + S_AXI_WREADY : out sl; + S_AXI_BRESP : out slv(1 downto 0); + S_AXI_BVALID : out sl; + S_AXI_BREADY : in sl; + S_AXI_ARADDR : in slv(11 downto 0); + S_AXI_ARPROT : in slv(2 downto 0); + S_AXI_ARVALID : in sl; + S_AXI_ARREADY : out sl; + S_AXI_RDATA : out slv(31 downto 0); + S_AXI_RRESP : out slv(1 downto 0); + S_AXI_RVALID : out sl; + S_AXI_RREADY : in sl); end entity AxiStreamDmaIpIntegrator; architecture rtl of AxiStreamDmaIpIntegrator is @@ -66,7 +66,7 @@ architecture rtl of AxiStreamDmaIpIntegrator is ID_BITS_C => 1, LEN_BITS_C => 8); - signal axilResetN : sl := '1'; + signal axilResetN : sl := '1'; signal axilReadMasters : AxiLiteReadMasterArray(0 downto 0) := (others => AXI_LITE_READ_MASTER_INIT_C); signal axilReadSlaves : AxiLiteReadSlaveArray(0 downto 0) := (others => AXI_LITE_READ_SLAVE_INIT_C); signal axilWriteMasters : AxiLiteWriteMasterArray(0 downto 0) := (others => AXI_LITE_WRITE_MASTER_INIT_C); diff --git a/axi/dma/ip_integrator/AxiStreamDmaReadIpIntegrator.vhd b/axi/dma/ip_integrator/AxiStreamDmaReadIpIntegrator.vhd index 2c52acdf33..c0a6698d63 100644 --- a/axi/dma/ip_integrator/AxiStreamDmaReadIpIntegrator.vhd +++ b/axi/dma/ip_integrator/AxiStreamDmaReadIpIntegrator.vhd @@ -93,14 +93,14 @@ architecture rtl of AxiStreamDmaReadIpIntegrator is ID_BITS_C => 8, LEN_BITS_C => 8); - signal axisAResetN : sl := '1'; - signal dmaReq : AxiReadDmaReqType := AXI_READ_DMA_REQ_INIT_C; - signal dmaAck : AxiReadDmaAckType := AXI_READ_DMA_ACK_INIT_C; + signal axisAResetN : sl := '1'; + signal dmaReq : AxiReadDmaReqType := AXI_READ_DMA_REQ_INIT_C; + signal dmaAck : AxiReadDmaAckType := AXI_READ_DMA_ACK_INIT_C; signal axisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal axisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal axisCtrl : AxiStreamCtrlType := AXI_STREAM_CTRL_UNUSED_C; - signal axiReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; - signal axiReadSlave : AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; + signal axiReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; + signal axiReadSlave : AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; begin @@ -158,54 +158,54 @@ begin ADDR_WIDTH => 16, DATA_WIDTH => DATA_BYTES_G*8) port map ( - M_AXI_ACLK => axiClk, - M_AXI_ARESETN => axisAResetN, - M_AXI_AWID => open, - M_AXI_AWADDR => open, - M_AXI_AWLEN => open, - M_AXI_AWSIZE => open, - M_AXI_AWBURST => open, - M_AXI_AWLOCK => open, - M_AXI_AWCACHE => open, - M_AXI_AWPROT => open, - M_AXI_AWREGION => open, - M_AXI_AWQOS => open, - M_AXI_AWVALID => open, - M_AXI_AWREADY => '0', - M_AXI_WID => open, - M_AXI_WDATA => open, - M_AXI_WSTRB => open, - M_AXI_WLAST => open, - M_AXI_WVALID => open, - M_AXI_WREADY => '0', - M_AXI_BID => (others => '0'), - M_AXI_BRESP => (others => '0'), - M_AXI_BVALID => '0', - M_AXI_BREADY => open, - M_AXI_ARID => M_AXI_ARID, - M_AXI_ARADDR => M_AXI_ARADDR, - M_AXI_ARLEN => M_AXI_ARLEN, - M_AXI_ARSIZE => M_AXI_ARSIZE, - M_AXI_ARBURST => M_AXI_ARBURST, - M_AXI_ARLOCK => open, - M_AXI_ARCACHE => M_AXI_ARCACHE, - M_AXI_ARPROT => M_AXI_ARPROT, - M_AXI_ARREGION => M_AXI_ARREGION, - M_AXI_ARQOS => M_AXI_ARQOS, - M_AXI_ARVALID => M_AXI_ARVALID, - M_AXI_ARREADY => M_AXI_ARREADY, - M_AXI_RID => M_AXI_RID, - M_AXI_RDATA => M_AXI_RDATA, - M_AXI_RRESP => M_AXI_RRESP, - M_AXI_RLAST => M_AXI_RLAST, - M_AXI_RVALID => M_AXI_RVALID, - M_AXI_RREADY => M_AXI_RREADY, - axiClk => open, - axiRst => open, - axiReadMaster => axiReadMaster, - axiReadSlave => axiReadSlave, - axiWriteMaster => AXI_WRITE_MASTER_INIT_C, - axiWriteSlave => open); + M_AXI_ACLK => axiClk, + M_AXI_ARESETN => axisAResetN, + M_AXI_AWID => open, + M_AXI_AWADDR => open, + M_AXI_AWLEN => open, + M_AXI_AWSIZE => open, + M_AXI_AWBURST => open, + M_AXI_AWLOCK => open, + M_AXI_AWCACHE => open, + M_AXI_AWPROT => open, + M_AXI_AWREGION => open, + M_AXI_AWQOS => open, + M_AXI_AWVALID => open, + M_AXI_AWREADY => '0', + M_AXI_WID => open, + M_AXI_WDATA => open, + M_AXI_WSTRB => open, + M_AXI_WLAST => open, + M_AXI_WVALID => open, + M_AXI_WREADY => '0', + M_AXI_BID => (others => '0'), + M_AXI_BRESP => (others => '0'), + M_AXI_BVALID => '0', + M_AXI_BREADY => open, + M_AXI_ARID => M_AXI_ARID, + M_AXI_ARADDR => M_AXI_ARADDR, + M_AXI_ARLEN => M_AXI_ARLEN, + M_AXI_ARSIZE => M_AXI_ARSIZE, + M_AXI_ARBURST => M_AXI_ARBURST, + M_AXI_ARLOCK => open, + M_AXI_ARCACHE => M_AXI_ARCACHE, + M_AXI_ARPROT => M_AXI_ARPROT, + M_AXI_ARREGION => M_AXI_ARREGION, + M_AXI_ARQOS => M_AXI_ARQOS, + M_AXI_ARVALID => M_AXI_ARVALID, + M_AXI_ARREADY => M_AXI_ARREADY, + M_AXI_RID => M_AXI_RID, + M_AXI_RDATA => M_AXI_RDATA, + M_AXI_RRESP => M_AXI_RRESP, + M_AXI_RLAST => M_AXI_RLAST, + M_AXI_RVALID => M_AXI_RVALID, + M_AXI_RREADY => M_AXI_RREADY, + axiClk => open, + axiRst => open, + axiReadMaster => axiReadMaster, + axiReadSlave => axiReadSlave, + axiWriteMaster => AXI_WRITE_MASTER_INIT_C, + axiWriteSlave => open); M_AXI_ARLOCK <= '0'; diff --git a/axi/dma/ip_integrator/AxiStreamDmaRingReadIpIntegrator.vhd b/axi/dma/ip_integrator/AxiStreamDmaRingReadIpIntegrator.vhd index 93106b8a6e..17b7a16075 100644 --- a/axi/dma/ip_integrator/AxiStreamDmaRingReadIpIntegrator.vhd +++ b/axi/dma/ip_integrator/AxiStreamDmaRingReadIpIntegrator.vhd @@ -106,9 +106,9 @@ architecture rtl of AxiStreamDmaRingReadIpIntegrator is ID_BITS_C => 1, LEN_BITS_C => 8); - signal axilResetN : sl := '1'; - signal statusResetN : sl := '1'; - signal axiResetN : sl := '1'; + signal axilResetN : sl := '1'; + signal statusResetN : sl := '1'; + signal axiResetN : sl := '1'; signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; @@ -229,60 +229,60 @@ begin ADDR_WIDTH => 16, DATA_WIDTH => 32) port map ( - M_AXI_ACLK => axiClk, - M_AXI_ARESETN => axiResetN, - M_AXI_AWID => open, - M_AXI_AWADDR => open, - M_AXI_AWLEN => open, - M_AXI_AWSIZE => open, - M_AXI_AWBURST => open, - M_AXI_AWLOCK => open, - M_AXI_AWCACHE => open, - M_AXI_AWPROT => open, - M_AXI_AWREGION => open, - M_AXI_AWQOS => open, - M_AXI_AWVALID => open, - M_AXI_AWREADY => '0', - M_AXI_WID => open, - M_AXI_WDATA => open, - M_AXI_WSTRB => open, - M_AXI_WLAST => open, - M_AXI_WVALID => open, - M_AXI_WREADY => '0', - M_AXI_BID => (others => '0'), - M_AXI_BRESP => (others => '0'), - M_AXI_BVALID => '0', - M_AXI_BREADY => open, - M_AXI_ARID => M_AXI_ARID, - M_AXI_ARADDR => M_AXI_ARADDR, - M_AXI_ARLEN => M_AXI_ARLEN, - M_AXI_ARSIZE => M_AXI_ARSIZE, - M_AXI_ARBURST => M_AXI_ARBURST, - M_AXI_ARLOCK => open, - M_AXI_ARCACHE => open, - M_AXI_ARPROT => open, - M_AXI_ARREGION => open, - M_AXI_ARQOS => open, - M_AXI_ARVALID => M_AXI_ARVALID, - M_AXI_ARREADY => M_AXI_ARREADY, - M_AXI_RID => M_AXI_RID, - M_AXI_RDATA => M_AXI_RDATA, - M_AXI_RRESP => M_AXI_RRESP, - M_AXI_RLAST => M_AXI_RLAST, - M_AXI_RVALID => M_AXI_RVALID, - M_AXI_RREADY => M_AXI_RREADY, - axiClk => open, - axiRst => open, - axiReadMaster => axiReadMaster, - axiReadSlave => axiReadSlave, - axiWriteMaster => axiWriteMaster, - axiWriteSlave => axiWriteSlave); + M_AXI_ACLK => axiClk, + M_AXI_ARESETN => axiResetN, + M_AXI_AWID => open, + M_AXI_AWADDR => open, + M_AXI_AWLEN => open, + M_AXI_AWSIZE => open, + M_AXI_AWBURST => open, + M_AXI_AWLOCK => open, + M_AXI_AWCACHE => open, + M_AXI_AWPROT => open, + M_AXI_AWREGION => open, + M_AXI_AWQOS => open, + M_AXI_AWVALID => open, + M_AXI_AWREADY => '0', + M_AXI_WID => open, + M_AXI_WDATA => open, + M_AXI_WSTRB => open, + M_AXI_WLAST => open, + M_AXI_WVALID => open, + M_AXI_WREADY => '0', + M_AXI_BID => (others => '0'), + M_AXI_BRESP => (others => '0'), + M_AXI_BVALID => '0', + M_AXI_BREADY => open, + M_AXI_ARID => M_AXI_ARID, + M_AXI_ARADDR => M_AXI_ARADDR, + M_AXI_ARLEN => M_AXI_ARLEN, + M_AXI_ARSIZE => M_AXI_ARSIZE, + M_AXI_ARBURST => M_AXI_ARBURST, + M_AXI_ARLOCK => open, + M_AXI_ARCACHE => open, + M_AXI_ARPROT => open, + M_AXI_ARREGION => open, + M_AXI_ARQOS => open, + M_AXI_ARVALID => M_AXI_ARVALID, + M_AXI_ARREADY => M_AXI_ARREADY, + M_AXI_RID => M_AXI_RID, + M_AXI_RDATA => M_AXI_RDATA, + M_AXI_RRESP => M_AXI_RRESP, + M_AXI_RLAST => M_AXI_RLAST, + M_AXI_RVALID => M_AXI_RVALID, + M_AXI_RREADY => M_AXI_RREADY, + axiClk => open, + axiRst => open, + axiReadMaster => axiReadMaster, + axiReadSlave => axiReadSlave, + axiWriteMaster => axiWriteMaster, + axiWriteSlave => axiWriteSlave); - M_AXI_ARLOCK <= '0'; - M_AXI_ARCACHE <= (others => '0'); - M_AXI_ARPROT <= (others => '0'); + M_AXI_ARLOCK <= '0'; + M_AXI_ARCACHE <= (others => '0'); + M_AXI_ARPROT <= (others => '0'); M_AXI_ARREGION <= (others => '0'); - M_AXI_ARQOS <= (others => '0'); + M_AXI_ARQOS <= (others => '0'); --------------------------------------------------------------------------- -- DUT diff --git a/axi/dma/ip_integrator/AxiStreamDmaRingWriteIpIntegrator.vhd b/axi/dma/ip_integrator/AxiStreamDmaRingWriteIpIntegrator.vhd index 69fd81985a..7855a0b3d0 100644 --- a/axi/dma/ip_integrator/AxiStreamDmaRingWriteIpIntegrator.vhd +++ b/axi/dma/ip_integrator/AxiStreamDmaRingWriteIpIntegrator.vhd @@ -24,72 +24,72 @@ use surf.SsiPkg.all; entity AxiStreamDmaRingWriteIpIntegrator is port ( - axilClk : in sl; - axilRst : in sl; - S_AXI_AWADDR : in slv(11 downto 0); - S_AXI_AWPROT : in slv(2 downto 0); - S_AXI_AWVALID : in sl; - S_AXI_AWREADY : out sl; - S_AXI_WDATA : in slv(31 downto 0); - S_AXI_WSTRB : in slv(3 downto 0); - S_AXI_WVALID : in sl; - S_AXI_WREADY : out sl; - S_AXI_BRESP : out slv(1 downto 0); - S_AXI_BVALID : out sl; - S_AXI_BREADY : in sl; - S_AXI_ARADDR : in slv(11 downto 0); - S_AXI_ARPROT : in slv(2 downto 0); - S_AXI_ARVALID : in sl; - S_AXI_ARREADY : out sl; - S_AXI_RDATA : out slv(31 downto 0); - S_AXI_RRESP : out slv(1 downto 0); - S_AXI_RVALID : out sl; - S_AXI_RREADY : in sl; - axisStatusClk : in sl; - axisStatusRst : in sl; - M_STATUS_TVALID : out sl; - M_STATUS_TDATA : out slv(7 downto 0); - M_STATUS_TLAST : out sl; - M_STATUS_TUSER : out slv(1 downto 0); - M_STATUS_TDEST : out slv(3 downto 0); - M_STATUS_TREADY : in sl; - axiClk : in sl; - axiRst : in sl; - S_AXIS_TVALID : in sl; - S_AXIS_TDATA : in slv(31 downto 0); - S_AXIS_TKEEP : in slv(3 downto 0); - S_AXIS_TLAST : in sl; - S_AXIS_TDEST : in slv(0 downto 0); - S_AXIS_TUSER : in slv(1 downto 0); - S_AXIS_TREADY : out sl; - bufferEnabled : out slv(1 downto 0); - bufferEmpty : out slv(1 downto 0); - bufferFull : out slv(1 downto 0); - bufferDone : out slv(1 downto 0); - bufferTriggered : out slv(1 downto 0); - bufferError : out slv(1 downto 0); - M_AXI_AWID : out slv(0 downto 0); - M_AXI_AWADDR : out slv(15 downto 0); - M_AXI_AWLEN : out slv(7 downto 0); - M_AXI_AWSIZE : out slv(2 downto 0); - M_AXI_AWBURST : out slv(1 downto 0); - M_AXI_AWLOCK : out sl; - M_AXI_AWCACHE : out slv(3 downto 0); - M_AXI_AWPROT : out slv(2 downto 0); - M_AXI_AWREGION : out slv(3 downto 0); - M_AXI_AWQOS : out slv(3 downto 0); - M_AXI_AWVALID : out sl; - M_AXI_AWREADY : in sl; - M_AXI_WID : out slv(0 downto 0); - M_AXI_WDATA : out slv(31 downto 0); - M_AXI_WSTRB : out slv(3 downto 0); - M_AXI_WLAST : out sl; - M_AXI_WVALID : out sl; - M_AXI_WREADY : in sl; - M_AXI_BID : in slv(0 downto 0); - M_AXI_BRESP : in slv(1 downto 0); - M_AXI_BVALID : in sl; - M_AXI_BREADY : out sl); + axilClk : in sl; + axilRst : in sl; + S_AXI_AWADDR : in slv(11 downto 0); + S_AXI_AWPROT : in slv(2 downto 0); + S_AXI_AWVALID : in sl; + S_AXI_AWREADY : out sl; + S_AXI_WDATA : in slv(31 downto 0); + S_AXI_WSTRB : in slv(3 downto 0); + S_AXI_WVALID : in sl; + S_AXI_WREADY : out sl; + S_AXI_BRESP : out slv(1 downto 0); + S_AXI_BVALID : out sl; + S_AXI_BREADY : in sl; + S_AXI_ARADDR : in slv(11 downto 0); + S_AXI_ARPROT : in slv(2 downto 0); + S_AXI_ARVALID : in sl; + S_AXI_ARREADY : out sl; + S_AXI_RDATA : out slv(31 downto 0); + S_AXI_RRESP : out slv(1 downto 0); + S_AXI_RVALID : out sl; + S_AXI_RREADY : in sl; + axisStatusClk : in sl; + axisStatusRst : in sl; + M_STATUS_TVALID : out sl; + M_STATUS_TDATA : out slv(7 downto 0); + M_STATUS_TLAST : out sl; + M_STATUS_TUSER : out slv(1 downto 0); + M_STATUS_TDEST : out slv(3 downto 0); + M_STATUS_TREADY : in sl; + axiClk : in sl; + axiRst : in sl; + S_AXIS_TVALID : in sl; + S_AXIS_TDATA : in slv(31 downto 0); + S_AXIS_TKEEP : in slv(3 downto 0); + S_AXIS_TLAST : in sl; + S_AXIS_TDEST : in slv(0 downto 0); + S_AXIS_TUSER : in slv(1 downto 0); + S_AXIS_TREADY : out sl; + bufferEnabled : out slv(1 downto 0); + bufferEmpty : out slv(1 downto 0); + bufferFull : out slv(1 downto 0); + bufferDone : out slv(1 downto 0); + bufferTriggered : out slv(1 downto 0); + bufferError : out slv(1 downto 0); + M_AXI_AWID : out slv(0 downto 0); + M_AXI_AWADDR : out slv(15 downto 0); + M_AXI_AWLEN : out slv(7 downto 0); + M_AXI_AWSIZE : out slv(2 downto 0); + M_AXI_AWBURST : out slv(1 downto 0); + M_AXI_AWLOCK : out sl; + M_AXI_AWCACHE : out slv(3 downto 0); + M_AXI_AWPROT : out slv(2 downto 0); + M_AXI_AWREGION : out slv(3 downto 0); + M_AXI_AWQOS : out slv(3 downto 0); + M_AXI_AWVALID : out sl; + M_AXI_AWREADY : in sl; + M_AXI_WID : out slv(0 downto 0); + M_AXI_WDATA : out slv(31 downto 0); + M_AXI_WSTRB : out slv(3 downto 0); + M_AXI_WLAST : out sl; + M_AXI_WVALID : out sl; + M_AXI_WREADY : in sl; + M_AXI_BID : in slv(0 downto 0); + M_AXI_BRESP : in slv(1 downto 0); + M_AXI_BVALID : in sl; + M_AXI_BREADY : out sl); end entity AxiStreamDmaRingWriteIpIntegrator; architecture rtl of AxiStreamDmaRingWriteIpIntegrator is @@ -117,22 +117,22 @@ architecture rtl of AxiStreamDmaRingWriteIpIntegrator is ID_BITS_C => 1, LEN_BITS_C => 8); - signal axilResetN : sl := '1'; - signal axisResetN : sl := '1'; - signal statusResetN : sl := '1'; - signal axiResetN : sl := '1'; - signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; - signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; - signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; - signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; - signal axisDataMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal axisDataSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal axisStatusMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal axisStatusSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal axiReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; - signal axiReadSlave : AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; - signal axiWriteMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; - signal axiWriteSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C; + signal axilResetN : sl := '1'; + signal axisResetN : sl := '1'; + signal statusResetN : sl := '1'; + signal axiResetN : sl := '1'; + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + signal axisDataMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal axisDataSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal axisStatusMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal axisStatusSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal axiReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; + signal axiReadSlave : AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; + signal axiWriteMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; + signal axiWriteSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C; begin @@ -242,54 +242,54 @@ begin ADDR_WIDTH => 16, DATA_WIDTH => 32) port map ( - M_AXI_ACLK => axiClk, - M_AXI_ARESETN => axiResetN, - M_AXI_AWID => M_AXI_AWID, - M_AXI_AWADDR => M_AXI_AWADDR, - M_AXI_AWLEN => M_AXI_AWLEN, - M_AXI_AWSIZE => M_AXI_AWSIZE, - M_AXI_AWBURST => M_AXI_AWBURST, - M_AXI_AWLOCK => open, - M_AXI_AWCACHE => M_AXI_AWCACHE, - M_AXI_AWPROT => M_AXI_AWPROT, - M_AXI_AWREGION => M_AXI_AWREGION, - M_AXI_AWQOS => M_AXI_AWQOS, - M_AXI_AWVALID => M_AXI_AWVALID, - M_AXI_AWREADY => M_AXI_AWREADY, - M_AXI_WID => M_AXI_WID, - M_AXI_WDATA => M_AXI_WDATA, - M_AXI_WSTRB => M_AXI_WSTRB, - M_AXI_WLAST => M_AXI_WLAST, - M_AXI_WVALID => M_AXI_WVALID, - M_AXI_WREADY => M_AXI_WREADY, - M_AXI_BID => M_AXI_BID, - M_AXI_BRESP => M_AXI_BRESP, - M_AXI_BVALID => M_AXI_BVALID, - M_AXI_BREADY => M_AXI_BREADY, - M_AXI_ARID => open, - M_AXI_ARADDR => open, - M_AXI_ARLEN => open, - M_AXI_ARSIZE => open, - M_AXI_ARBURST => open, - M_AXI_ARLOCK => open, - M_AXI_ARCACHE => open, - M_AXI_ARPROT => open, - M_AXI_ARREGION => open, - M_AXI_ARQOS => open, - M_AXI_ARVALID => open, - M_AXI_ARREADY => '0', - M_AXI_RID => (others => '0'), - M_AXI_RDATA => (others => '0'), - M_AXI_RRESP => (others => '0'), - M_AXI_RLAST => '0', - M_AXI_RVALID => '0', - M_AXI_RREADY => open, - axiClk => open, - axiRst => open, - axiReadMaster => axiReadMaster, - axiReadSlave => axiReadSlave, - axiWriteMaster => axiWriteMaster, - axiWriteSlave => axiWriteSlave); + M_AXI_ACLK => axiClk, + M_AXI_ARESETN => axiResetN, + M_AXI_AWID => M_AXI_AWID, + M_AXI_AWADDR => M_AXI_AWADDR, + M_AXI_AWLEN => M_AXI_AWLEN, + M_AXI_AWSIZE => M_AXI_AWSIZE, + M_AXI_AWBURST => M_AXI_AWBURST, + M_AXI_AWLOCK => open, + M_AXI_AWCACHE => M_AXI_AWCACHE, + M_AXI_AWPROT => M_AXI_AWPROT, + M_AXI_AWREGION => M_AXI_AWREGION, + M_AXI_AWQOS => M_AXI_AWQOS, + M_AXI_AWVALID => M_AXI_AWVALID, + M_AXI_AWREADY => M_AXI_AWREADY, + M_AXI_WID => M_AXI_WID, + M_AXI_WDATA => M_AXI_WDATA, + M_AXI_WSTRB => M_AXI_WSTRB, + M_AXI_WLAST => M_AXI_WLAST, + M_AXI_WVALID => M_AXI_WVALID, + M_AXI_WREADY => M_AXI_WREADY, + M_AXI_BID => M_AXI_BID, + M_AXI_BRESP => M_AXI_BRESP, + M_AXI_BVALID => M_AXI_BVALID, + M_AXI_BREADY => M_AXI_BREADY, + M_AXI_ARID => open, + M_AXI_ARADDR => open, + M_AXI_ARLEN => open, + M_AXI_ARSIZE => open, + M_AXI_ARBURST => open, + M_AXI_ARLOCK => open, + M_AXI_ARCACHE => open, + M_AXI_ARPROT => open, + M_AXI_ARREGION => open, + M_AXI_ARQOS => open, + M_AXI_ARVALID => open, + M_AXI_ARREADY => '0', + M_AXI_RID => (others => '0'), + M_AXI_RDATA => (others => '0'), + M_AXI_RRESP => (others => '0'), + M_AXI_RLAST => '0', + M_AXI_RVALID => '0', + M_AXI_RREADY => open, + axiClk => open, + axiRst => open, + axiReadMaster => axiReadMaster, + axiReadSlave => axiReadSlave, + axiWriteMaster => axiWriteMaster, + axiWriteSlave => axiWriteSlave); M_AXI_AWLOCK <= '0'; diff --git a/axi/dma/ip_integrator/AxiStreamDmaV2DescIpIntegrator.vhd b/axi/dma/ip_integrator/AxiStreamDmaV2DescIpIntegrator.vhd index f8601e37e4..6655a428cf 100644 --- a/axi/dma/ip_integrator/AxiStreamDmaV2DescIpIntegrator.vhd +++ b/axi/dma/ip_integrator/AxiStreamDmaV2DescIpIntegrator.vhd @@ -120,31 +120,31 @@ architecture rtl of AxiStreamDmaV2DescIpIntegrator is ID_BITS_C => 8, LEN_BITS_C => 8); - signal axiResetN : sl := '1'; - signal mAxiAwLock : slv(1 downto 0) := (others => '0'); - signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; - signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; - signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; - signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; - signal onlineVec : slv(0 downto 0); - signal acknowledgeVec : slv(0 downto 0); - signal dmaWrDescReq : AxiWriteDmaDescReqArray(0 downto 0); - signal dmaWrDescAck : AxiWriteDmaDescAckArray(0 downto 0); - signal dmaWrDescRet : AxiWriteDmaDescRetArray(0 downto 0); + signal axiResetN : sl := '1'; + signal mAxiAwLock : slv(1 downto 0) := (others => '0'); + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + signal onlineVec : slv(0 downto 0); + signal acknowledgeVec : slv(0 downto 0); + signal dmaWrDescReq : AxiWriteDmaDescReqArray(0 downto 0); + signal dmaWrDescAck : AxiWriteDmaDescAckArray(0 downto 0); + signal dmaWrDescRet : AxiWriteDmaDescRetArray(0 downto 0); signal dmaWrDescRetAckVec : slv(0 downto 0); - signal dmaRdDescReq : AxiReadDmaDescReqArray(0 downto 0); - signal dmaRdDescAckVec : slv(0 downto 0); - signal dmaRdDescRet : AxiReadDmaDescRetArray(0 downto 0); + signal dmaRdDescReq : AxiReadDmaDescReqArray(0 downto 0); + signal dmaRdDescAckVec : slv(0 downto 0); + signal dmaRdDescRet : AxiReadDmaDescRetArray(0 downto 0); signal dmaRdDescRetAckVec : slv(0 downto 0); - signal axiWriteMasters : AxiWriteMasterArray(0 downto 0); - signal axiWriteSlaves : AxiWriteSlaveArray(0 downto 0); + signal axiWriteMasters : AxiWriteMasterArray(0 downto 0); + signal axiWriteSlaves : AxiWriteSlaveArray(0 downto 0); begin --------------------------------------------------------------------------- -- Flatten the single exposed descriptor-engine lane --------------------------------------------------------------------------- - axiResetN <= not axiRst; + axiResetN <= not axiRst; M_AXI_AWLOCK <= mAxiAwLock(0); dmaWrDescReq(0).valid <= dmaWrDescReqValid; @@ -232,63 +232,63 @@ begin ADDR_WIDTH => 16, DATA_WIDTH => 128) port map ( - M_AXI_ACLK => axiClk, - M_AXI_ARESETN => axiResetN, - M_AXI_AWID => M_AXI_AWID, - M_AXI_AWADDR => M_AXI_AWADDR, - M_AXI_AWLEN => M_AXI_AWLEN, - M_AXI_AWSIZE => M_AXI_AWSIZE, - M_AXI_AWBURST => M_AXI_AWBURST, - M_AXI_AWLOCK => mAxiAwLock, - M_AXI_AWCACHE => M_AXI_AWCACHE, - M_AXI_AWPROT => M_AXI_AWPROT, - M_AXI_AWREGION => M_AXI_AWREGION, - M_AXI_AWQOS => M_AXI_AWQOS, - M_AXI_AWVALID => M_AXI_AWVALID, - M_AXI_AWREADY => M_AXI_AWREADY, - M_AXI_WID => M_AXI_WID, - M_AXI_WDATA => M_AXI_WDATA, - M_AXI_WSTRB => M_AXI_WSTRB, - M_AXI_WLAST => M_AXI_WLAST, - M_AXI_WVALID => M_AXI_WVALID, - M_AXI_WREADY => M_AXI_WREADY, - M_AXI_BID => M_AXI_BID, - M_AXI_BRESP => M_AXI_BRESP, - M_AXI_BVALID => M_AXI_BVALID, - M_AXI_BREADY => M_AXI_BREADY, - M_AXI_ARID => open, - M_AXI_ARADDR => open, - M_AXI_ARLEN => open, - M_AXI_ARSIZE => open, - M_AXI_ARBURST => open, - M_AXI_ARLOCK => open, - M_AXI_ARCACHE => open, - M_AXI_ARPROT => open, - M_AXI_ARREGION => open, - M_AXI_ARQOS => open, - M_AXI_ARVALID => open, - M_AXI_ARREADY => '0', - M_AXI_RID => (others => '0'), - M_AXI_RDATA => (others => '0'), - M_AXI_RRESP => (others => '0'), - M_AXI_RLAST => '0', - M_AXI_RVALID => '0', - M_AXI_RREADY => open, - axiClk => open, - axiRst => open, - axiReadMaster => AXI_READ_MASTER_INIT_C, - axiReadSlave => open, - axiWriteMaster => axiWriteMasters(0), - axiWriteSlave => axiWriteSlaves(0)); + M_AXI_ACLK => axiClk, + M_AXI_ARESETN => axiResetN, + M_AXI_AWID => M_AXI_AWID, + M_AXI_AWADDR => M_AXI_AWADDR, + M_AXI_AWLEN => M_AXI_AWLEN, + M_AXI_AWSIZE => M_AXI_AWSIZE, + M_AXI_AWBURST => M_AXI_AWBURST, + M_AXI_AWLOCK => mAxiAwLock, + M_AXI_AWCACHE => M_AXI_AWCACHE, + M_AXI_AWPROT => M_AXI_AWPROT, + M_AXI_AWREGION => M_AXI_AWREGION, + M_AXI_AWQOS => M_AXI_AWQOS, + M_AXI_AWVALID => M_AXI_AWVALID, + M_AXI_AWREADY => M_AXI_AWREADY, + M_AXI_WID => M_AXI_WID, + M_AXI_WDATA => M_AXI_WDATA, + M_AXI_WSTRB => M_AXI_WSTRB, + M_AXI_WLAST => M_AXI_WLAST, + M_AXI_WVALID => M_AXI_WVALID, + M_AXI_WREADY => M_AXI_WREADY, + M_AXI_BID => M_AXI_BID, + M_AXI_BRESP => M_AXI_BRESP, + M_AXI_BVALID => M_AXI_BVALID, + M_AXI_BREADY => M_AXI_BREADY, + M_AXI_ARID => open, + M_AXI_ARADDR => open, + M_AXI_ARLEN => open, + M_AXI_ARSIZE => open, + M_AXI_ARBURST => open, + M_AXI_ARLOCK => open, + M_AXI_ARCACHE => open, + M_AXI_ARPROT => open, + M_AXI_ARREGION => open, + M_AXI_ARQOS => open, + M_AXI_ARVALID => open, + M_AXI_ARREADY => '0', + M_AXI_RID => (others => '0'), + M_AXI_RDATA => (others => '0'), + M_AXI_RRESP => (others => '0'), + M_AXI_RLAST => '0', + M_AXI_RVALID => '0', + M_AXI_RREADY => open, + axiClk => open, + axiRst => open, + axiReadMaster => AXI_READ_MASTER_INIT_C, + axiReadSlave => open, + axiWriteMaster => axiWriteMasters(0), + axiWriteSlave => axiWriteSlaves(0)); --------------------------------------------------------------------------- -- DUT --------------------------------------------------------------------------- U_DUT : entity surf.AxiStreamDmaV2Desc generic map ( - TPD_G => TPD_G, - CHAN_COUNT_G => 1, - AXI_CONFIG_G => AXI_CONFIG_C) + TPD_G => TPD_G, + CHAN_COUNT_G => 1, + AXI_CONFIG_G => AXI_CONFIG_C) port map ( axiClk => axiClk, axiRst => axiRst, diff --git a/axi/dma/ip_integrator/AxiStreamDmaV2FifoIpIntegrator.vhd b/axi/dma/ip_integrator/AxiStreamDmaV2FifoIpIntegrator.vhd index b073361ea9..409ad8a6e5 100644 --- a/axi/dma/ip_integrator/AxiStreamDmaV2FifoIpIntegrator.vhd +++ b/axi/dma/ip_integrator/AxiStreamDmaV2FifoIpIntegrator.vhd @@ -127,10 +127,10 @@ architecture rtl of AxiStreamDmaV2FifoIpIntegrator is ID_BITS_C => 8, LEN_BITS_C => 8); - signal axiResetN : sl := '1'; - signal axilResetN : sl := '1'; - signal mAxiAwLock : slv(1 downto 0) := (others => '0'); - signal mAxiArLock : slv(1 downto 0) := (others => '0'); + signal axiResetN : sl := '1'; + signal axilResetN : sl := '1'; + signal mAxiAwLock : slv(1 downto 0) := (others => '0'); + signal mAxiArLock : slv(1 downto 0) := (others => '0'); signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; @@ -254,54 +254,54 @@ begin ADDR_WIDTH => 16, DATA_WIDTH => 32) port map ( - M_AXI_ACLK => axiClk, - M_AXI_ARESETN => axiResetN, - M_AXI_AWID => M_AXI_AWID, - M_AXI_AWADDR => M_AXI_AWADDR, - M_AXI_AWLEN => M_AXI_AWLEN, - M_AXI_AWSIZE => M_AXI_AWSIZE, - M_AXI_AWBURST => M_AXI_AWBURST, - M_AXI_AWLOCK => mAxiAwLock, - M_AXI_AWCACHE => M_AXI_AWCACHE, - M_AXI_AWPROT => M_AXI_AWPROT, - M_AXI_AWREGION => M_AXI_AWREGION, - M_AXI_AWQOS => M_AXI_AWQOS, - M_AXI_AWVALID => M_AXI_AWVALID, - M_AXI_AWREADY => M_AXI_AWREADY, - M_AXI_WID => M_AXI_WID, - M_AXI_WDATA => M_AXI_WDATA, - M_AXI_WSTRB => M_AXI_WSTRB, - M_AXI_WLAST => M_AXI_WLAST, - M_AXI_WVALID => M_AXI_WVALID, - M_AXI_WREADY => M_AXI_WREADY, - M_AXI_BID => M_AXI_BID, - M_AXI_BRESP => M_AXI_BRESP, - M_AXI_BVALID => M_AXI_BVALID, - M_AXI_BREADY => M_AXI_BREADY, - M_AXI_ARID => M_AXI_ARID, - M_AXI_ARADDR => M_AXI_ARADDR, - M_AXI_ARLEN => M_AXI_ARLEN, - M_AXI_ARSIZE => M_AXI_ARSIZE, - M_AXI_ARBURST => M_AXI_ARBURST, - M_AXI_ARLOCK => mAxiArLock, - M_AXI_ARCACHE => M_AXI_ARCACHE, - M_AXI_ARPROT => M_AXI_ARPROT, - M_AXI_ARREGION => M_AXI_ARREGION, - M_AXI_ARQOS => M_AXI_ARQOS, - M_AXI_ARVALID => M_AXI_ARVALID, - M_AXI_ARREADY => M_AXI_ARREADY, - M_AXI_RID => M_AXI_RID, - M_AXI_RDATA => M_AXI_RDATA, - M_AXI_RRESP => M_AXI_RRESP, - M_AXI_RLAST => M_AXI_RLAST, - M_AXI_RVALID => M_AXI_RVALID, - M_AXI_RREADY => M_AXI_RREADY, - axiClk => open, - axiRst => open, - axiReadMaster => axiReadMaster, - axiReadSlave => axiReadSlave, - axiWriteMaster => axiWriteMaster, - axiWriteSlave => axiWriteSlave); + M_AXI_ACLK => axiClk, + M_AXI_ARESETN => axiResetN, + M_AXI_AWID => M_AXI_AWID, + M_AXI_AWADDR => M_AXI_AWADDR, + M_AXI_AWLEN => M_AXI_AWLEN, + M_AXI_AWSIZE => M_AXI_AWSIZE, + M_AXI_AWBURST => M_AXI_AWBURST, + M_AXI_AWLOCK => mAxiAwLock, + M_AXI_AWCACHE => M_AXI_AWCACHE, + M_AXI_AWPROT => M_AXI_AWPROT, + M_AXI_AWREGION => M_AXI_AWREGION, + M_AXI_AWQOS => M_AXI_AWQOS, + M_AXI_AWVALID => M_AXI_AWVALID, + M_AXI_AWREADY => M_AXI_AWREADY, + M_AXI_WID => M_AXI_WID, + M_AXI_WDATA => M_AXI_WDATA, + M_AXI_WSTRB => M_AXI_WSTRB, + M_AXI_WLAST => M_AXI_WLAST, + M_AXI_WVALID => M_AXI_WVALID, + M_AXI_WREADY => M_AXI_WREADY, + M_AXI_BID => M_AXI_BID, + M_AXI_BRESP => M_AXI_BRESP, + M_AXI_BVALID => M_AXI_BVALID, + M_AXI_BREADY => M_AXI_BREADY, + M_AXI_ARID => M_AXI_ARID, + M_AXI_ARADDR => M_AXI_ARADDR, + M_AXI_ARLEN => M_AXI_ARLEN, + M_AXI_ARSIZE => M_AXI_ARSIZE, + M_AXI_ARBURST => M_AXI_ARBURST, + M_AXI_ARLOCK => mAxiArLock, + M_AXI_ARCACHE => M_AXI_ARCACHE, + M_AXI_ARPROT => M_AXI_ARPROT, + M_AXI_ARREGION => M_AXI_ARREGION, + M_AXI_ARQOS => M_AXI_ARQOS, + M_AXI_ARVALID => M_AXI_ARVALID, + M_AXI_ARREADY => M_AXI_ARREADY, + M_AXI_RID => M_AXI_RID, + M_AXI_RDATA => M_AXI_RDATA, + M_AXI_RRESP => M_AXI_RRESP, + M_AXI_RLAST => M_AXI_RLAST, + M_AXI_RVALID => M_AXI_RVALID, + M_AXI_RREADY => M_AXI_RREADY, + axiClk => open, + axiRst => open, + axiReadMaster => axiReadMaster, + axiReadSlave => axiReadSlave, + axiWriteMaster => axiWriteMaster, + axiWriteSlave => axiWriteSlave); --------------------------------------------------------------------------- -- DUT diff --git a/axi/dma/ip_integrator/AxiStreamDmaV2IpIntegrator.vhd b/axi/dma/ip_integrator/AxiStreamDmaV2IpIntegrator.vhd index 6a73d664de..260774f60b 100644 --- a/axi/dma/ip_integrator/AxiStreamDmaV2IpIntegrator.vhd +++ b/axi/dma/ip_integrator/AxiStreamDmaV2IpIntegrator.vhd @@ -25,31 +25,31 @@ entity AxiStreamDmaV2IpIntegrator is generic ( TPD_G : time := 1 ns); port ( - axiClk : in sl; - axiRst : in sl; - interrupt : out sl; - online : out sl; - acknowledge : out sl; - buffGrpPause : out slv(7 downto 0); - S_AXI_AWADDR : in slv(11 downto 0); - S_AXI_AWPROT : in slv(2 downto 0); - S_AXI_AWVALID : in sl; - S_AXI_AWREADY : out sl; - S_AXI_WDATA : in slv(31 downto 0); - S_AXI_WSTRB : in slv(3 downto 0); - S_AXI_WVALID : in sl; - S_AXI_WREADY : out sl; - S_AXI_BRESP : out slv(1 downto 0); - S_AXI_BVALID : out sl; - S_AXI_BREADY : in sl; - S_AXI_ARADDR : in slv(11 downto 0); - S_AXI_ARPROT : in slv(2 downto 0); - S_AXI_ARVALID : in sl; - S_AXI_ARREADY : out sl; - S_AXI_RDATA : out slv(31 downto 0); - S_AXI_RRESP : out slv(1 downto 0); - S_AXI_RVALID : out sl; - S_AXI_RREADY : in sl); + axiClk : in sl; + axiRst : in sl; + interrupt : out sl; + online : out sl; + acknowledge : out sl; + buffGrpPause : out slv(7 downto 0); + S_AXI_AWADDR : in slv(11 downto 0); + S_AXI_AWPROT : in slv(2 downto 0); + S_AXI_AWVALID : in sl; + S_AXI_AWREADY : out sl; + S_AXI_WDATA : in slv(31 downto 0); + S_AXI_WSTRB : in slv(3 downto 0); + S_AXI_WVALID : in sl; + S_AXI_WREADY : out sl; + S_AXI_BRESP : out slv(1 downto 0); + S_AXI_BVALID : out sl; + S_AXI_BREADY : in sl; + S_AXI_ARADDR : in slv(11 downto 0); + S_AXI_ARPROT : in slv(2 downto 0); + S_AXI_ARVALID : in sl; + S_AXI_ARREADY : out sl; + S_AXI_RDATA : out slv(31 downto 0); + S_AXI_RRESP : out slv(1 downto 0); + S_AXI_RVALID : out sl; + S_AXI_RREADY : in sl); end entity AxiStreamDmaV2IpIntegrator; architecture rtl of AxiStreamDmaV2IpIntegrator is @@ -69,11 +69,11 @@ architecture rtl of AxiStreamDmaV2IpIntegrator is ID_BITS_C => 8, LEN_BITS_C => 8); - signal axiResetN : sl := '1'; - signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; - signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; - signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; - signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + signal axiResetN : sl := '1'; + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; signal sAxisMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); signal sAxisSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); signal mAxisMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); @@ -92,8 +92,8 @@ begin --------------------------------------------------------------------------- -- AXI-Lite shim --------------------------------------------------------------------------- - axiResetN <= not axiRst; - online <= onlineVec(0); + axiResetN <= not axiRst; + online <= onlineVec(0); acknowledge <= acknowledgeVec(0); U_AXIL : entity surf.SlaveAxiLiteIpIntegrator @@ -136,12 +136,12 @@ begin --------------------------------------------------------------------------- U_DUT : entity surf.AxiStreamDmaV2 generic map ( - TPD_G => TPD_G, - DESC_AWIDTH_G => 8, - AXIS_CONFIG_G => AXIS_CONFIG_C, + TPD_G => TPD_G, + DESC_AWIDTH_G => 8, + AXIS_CONFIG_G => AXIS_CONFIG_C, AXI_DMA_CONFIG_G => AXI_CONFIG_C, - CHAN_COUNT_G => 1, - BURST_BYTES_G => 16, + CHAN_COUNT_G => 1, + BURST_BYTES_G => 16, RD_PEND_THRESH_G => 4) port map ( axiClk => axiClk, diff --git a/axi/dma/ip_integrator/AxiStreamDmaV2ReadIpIntegrator.vhd b/axi/dma/ip_integrator/AxiStreamDmaV2ReadIpIntegrator.vhd index 2f2f86463e..f6218f6198 100644 --- a/axi/dma/ip_integrator/AxiStreamDmaV2ReadIpIntegrator.vhd +++ b/axi/dma/ip_integrator/AxiStreamDmaV2ReadIpIntegrator.vhd @@ -95,14 +95,14 @@ architecture rtl of AxiStreamDmaV2ReadIpIntegrator is ID_BITS_C => 8, LEN_BITS_C => 8); - signal axisAResetN : sl := '1'; - signal dmaRdDescReq : AxiReadDmaDescReqType := AXI_READ_DMA_DESC_REQ_INIT_C; - signal dmaRdDescRet : AxiReadDmaDescRetType := AXI_READ_DMA_DESC_RET_INIT_C; - signal axisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal axisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal axisCtrl : AxiStreamCtrlType := AXI_STREAM_CTRL_UNUSED_C; - signal axiReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; - signal axiReadSlave : AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; + signal axisAResetN : sl := '1'; + signal dmaRdDescReq : AxiReadDmaDescReqType := AXI_READ_DMA_DESC_REQ_INIT_C; + signal dmaRdDescRet : AxiReadDmaDescRetType := AXI_READ_DMA_DESC_RET_INIT_C; + signal axisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal axisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal axisCtrl : AxiStreamCtrlType := AXI_STREAM_CTRL_UNUSED_C; + signal axiReadMaster : AxiReadMasterType := AXI_READ_MASTER_INIT_C; + signal axiReadSlave : AxiReadSlaveType := AXI_READ_SLAVE_INIT_C; begin @@ -158,54 +158,54 @@ begin ADDR_WIDTH => 16, DATA_WIDTH => DATA_BYTES_G*8) port map ( - M_AXI_ACLK => axiClk, - M_AXI_ARESETN => axisAResetN, - M_AXI_AWID => open, - M_AXI_AWADDR => open, - M_AXI_AWLEN => open, - M_AXI_AWSIZE => open, - M_AXI_AWBURST => open, - M_AXI_AWLOCK => open, - M_AXI_AWCACHE => open, - M_AXI_AWPROT => open, - M_AXI_AWREGION => open, - M_AXI_AWQOS => open, - M_AXI_AWVALID => open, - M_AXI_AWREADY => '0', - M_AXI_WID => open, - M_AXI_WDATA => open, - M_AXI_WSTRB => open, - M_AXI_WLAST => open, - M_AXI_WVALID => open, - M_AXI_WREADY => '0', - M_AXI_BID => (others => '0'), - M_AXI_BRESP => (others => '0'), - M_AXI_BVALID => '0', - M_AXI_BREADY => open, - M_AXI_ARID => M_AXI_ARID, - M_AXI_ARADDR => M_AXI_ARADDR, - M_AXI_ARLEN => M_AXI_ARLEN, - M_AXI_ARSIZE => M_AXI_ARSIZE, - M_AXI_ARBURST => M_AXI_ARBURST, - M_AXI_ARLOCK => open, - M_AXI_ARCACHE => M_AXI_ARCACHE, - M_AXI_ARPROT => M_AXI_ARPROT, - M_AXI_ARREGION => M_AXI_ARREGION, - M_AXI_ARQOS => M_AXI_ARQOS, - M_AXI_ARVALID => M_AXI_ARVALID, - M_AXI_ARREADY => M_AXI_ARREADY, - M_AXI_RID => M_AXI_RID, - M_AXI_RDATA => M_AXI_RDATA, - M_AXI_RRESP => M_AXI_RRESP, - M_AXI_RLAST => M_AXI_RLAST, - M_AXI_RVALID => M_AXI_RVALID, - M_AXI_RREADY => M_AXI_RREADY, - axiClk => open, - axiRst => open, - axiReadMaster => axiReadMaster, - axiReadSlave => axiReadSlave, - axiWriteMaster => AXI_WRITE_MASTER_INIT_C, - axiWriteSlave => open); + M_AXI_ACLK => axiClk, + M_AXI_ARESETN => axisAResetN, + M_AXI_AWID => open, + M_AXI_AWADDR => open, + M_AXI_AWLEN => open, + M_AXI_AWSIZE => open, + M_AXI_AWBURST => open, + M_AXI_AWLOCK => open, + M_AXI_AWCACHE => open, + M_AXI_AWPROT => open, + M_AXI_AWREGION => open, + M_AXI_AWQOS => open, + M_AXI_AWVALID => open, + M_AXI_AWREADY => '0', + M_AXI_WID => open, + M_AXI_WDATA => open, + M_AXI_WSTRB => open, + M_AXI_WLAST => open, + M_AXI_WVALID => open, + M_AXI_WREADY => '0', + M_AXI_BID => (others => '0'), + M_AXI_BRESP => (others => '0'), + M_AXI_BVALID => '0', + M_AXI_BREADY => open, + M_AXI_ARID => M_AXI_ARID, + M_AXI_ARADDR => M_AXI_ARADDR, + M_AXI_ARLEN => M_AXI_ARLEN, + M_AXI_ARSIZE => M_AXI_ARSIZE, + M_AXI_ARBURST => M_AXI_ARBURST, + M_AXI_ARLOCK => open, + M_AXI_ARCACHE => M_AXI_ARCACHE, + M_AXI_ARPROT => M_AXI_ARPROT, + M_AXI_ARREGION => M_AXI_ARREGION, + M_AXI_ARQOS => M_AXI_ARQOS, + M_AXI_ARVALID => M_AXI_ARVALID, + M_AXI_ARREADY => M_AXI_ARREADY, + M_AXI_RID => M_AXI_RID, + M_AXI_RDATA => M_AXI_RDATA, + M_AXI_RRESP => M_AXI_RRESP, + M_AXI_RLAST => M_AXI_RLAST, + M_AXI_RVALID => M_AXI_RVALID, + M_AXI_RREADY => M_AXI_RREADY, + axiClk => open, + axiRst => open, + axiReadMaster => axiReadMaster, + axiReadSlave => axiReadSlave, + axiWriteMaster => AXI_WRITE_MASTER_INIT_C, + axiWriteSlave => open); M_AXI_ARLOCK <= '0'; diff --git a/axi/dma/ip_integrator/AxiStreamDmaV2WriteIpIntegrator.vhd b/axi/dma/ip_integrator/AxiStreamDmaV2WriteIpIntegrator.vhd index 316838d005..634137392c 100644 --- a/axi/dma/ip_integrator/AxiStreamDmaV2WriteIpIntegrator.vhd +++ b/axi/dma/ip_integrator/AxiStreamDmaV2WriteIpIntegrator.vhd @@ -107,43 +107,43 @@ architecture rtl of AxiStreamDmaV2WriteIpIntegrator is ID_BITS_C => 8, LEN_BITS_C => 8); - signal axisAResetN : sl := '1'; - signal dmaWrDescReq : AxiWriteDmaDescReqType := AXI_WRITE_DMA_DESC_REQ_INIT_C; - signal dmaWrDescAck : AxiWriteDmaDescAckType := AXI_WRITE_DMA_DESC_ACK_INIT_C; - signal dmaWrDescRet : AxiWriteDmaDescRetType := AXI_WRITE_DMA_DESC_RET_INIT_C; - signal axisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal axisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal axiWriteMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; - signal axiWriteSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C; - signal axiWriteCtrl : AxiCtrlType := AXI_CTRL_UNUSED_C; + signal axisAResetN : sl := '1'; + signal dmaWrDescReq : AxiWriteDmaDescReqType := AXI_WRITE_DMA_DESC_REQ_INIT_C; + signal dmaWrDescAck : AxiWriteDmaDescAckType := AXI_WRITE_DMA_DESC_ACK_INIT_C; + signal dmaWrDescRet : AxiWriteDmaDescRetType := AXI_WRITE_DMA_DESC_RET_INIT_C; + signal axisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal axisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal axiWriteMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; + signal axiWriteSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C; + signal axiWriteCtrl : AxiCtrlType := AXI_CTRL_UNUSED_C; begin axisAResetN <= not axiRst; - dmaWrDescReqValid <= dmaWrDescReq.valid; - dmaWrDescReqId <= dmaWrDescReq.id; - dmaWrDescReqDest <= dmaWrDescReq.dest; - dmaWrDescAck.valid <= dmaWrDescAckValid; - dmaWrDescAck.address <= dmaWrDescAckAddress; + dmaWrDescReqValid <= dmaWrDescReq.valid; + dmaWrDescReqId <= dmaWrDescReq.id; + dmaWrDescReqDest <= dmaWrDescReq.dest; + dmaWrDescAck.valid <= dmaWrDescAckValid; + dmaWrDescAck.address <= dmaWrDescAckAddress; dmaWrDescAck.metaEnable <= dmaWrDescAckMetaEnable; - dmaWrDescAck.metaAddr <= dmaWrDescAckMetaAddr; - dmaWrDescAck.dropEn <= dmaWrDescAckDropEn; - dmaWrDescAck.maxSize <= dmaWrDescAckMaxSize; - dmaWrDescAck.contEn <= dmaWrDescAckContEn; - dmaWrDescAck.buffId <= dmaWrDescAckBuffId; - dmaWrDescAck.timeout <= dmaWrDescAckTimeout; - dmaWrDescRetValid <= dmaWrDescRet.valid; - dmaWrDescRetBuffId <= dmaWrDescRet.buffId; - dmaWrDescRetFirstUser <= dmaWrDescRet.firstUser; - dmaWrDescRetLastUser <= dmaWrDescRet.lastUser; - dmaWrDescRetSize <= dmaWrDescRet.size; - dmaWrDescRetContinue <= dmaWrDescRet.continue; - dmaWrDescRetResult <= dmaWrDescRet.result; - dmaWrDescRetDest <= dmaWrDescRet.dest; - dmaWrDescRetId <= dmaWrDescRet.id; - axiWriteCtrl.pause <= axiWriteCtrlPause; - axiWriteCtrl.overflow <= axiWriteCtrlOver; + dmaWrDescAck.metaAddr <= dmaWrDescAckMetaAddr; + dmaWrDescAck.dropEn <= dmaWrDescAckDropEn; + dmaWrDescAck.maxSize <= dmaWrDescAckMaxSize; + dmaWrDescAck.contEn <= dmaWrDescAckContEn; + dmaWrDescAck.buffId <= dmaWrDescAckBuffId; + dmaWrDescAck.timeout <= dmaWrDescAckTimeout; + dmaWrDescRetValid <= dmaWrDescRet.valid; + dmaWrDescRetBuffId <= dmaWrDescRet.buffId; + dmaWrDescRetFirstUser <= dmaWrDescRet.firstUser; + dmaWrDescRetLastUser <= dmaWrDescRet.lastUser; + dmaWrDescRetSize <= dmaWrDescRet.size; + dmaWrDescRetContinue <= dmaWrDescRet.continue; + dmaWrDescRetResult <= dmaWrDescRet.result; + dmaWrDescRetDest <= dmaWrDescRet.dest; + dmaWrDescRetId <= dmaWrDescRet.id; + axiWriteCtrl.pause <= axiWriteCtrlPause; + axiWriteCtrl.overflow <= axiWriteCtrlOver; U_StreamSlave : entity surf.SlaveAxiStreamIpIntegrator generic map ( @@ -180,54 +180,54 @@ begin ADDR_WIDTH => 16, DATA_WIDTH => DATA_BYTES_G*8) port map ( - M_AXI_ACLK => axiClk, - M_AXI_ARESETN => axisAResetN, - M_AXI_AWID => M_AXI_AWID, - M_AXI_AWADDR => M_AXI_AWADDR, - M_AXI_AWLEN => M_AXI_AWLEN, - M_AXI_AWSIZE => M_AXI_AWSIZE, - M_AXI_AWBURST => M_AXI_AWBURST, - M_AXI_AWLOCK => open, - M_AXI_AWCACHE => M_AXI_AWCACHE, - M_AXI_AWPROT => M_AXI_AWPROT, - M_AXI_AWREGION => M_AXI_AWREGION, - M_AXI_AWQOS => M_AXI_AWQOS, - M_AXI_AWVALID => M_AXI_AWVALID, - M_AXI_AWREADY => M_AXI_AWREADY, - M_AXI_WID => M_AXI_WID, - M_AXI_WDATA => M_AXI_WDATA, - M_AXI_WSTRB => M_AXI_WSTRB, - M_AXI_WLAST => M_AXI_WLAST, - M_AXI_WVALID => M_AXI_WVALID, - M_AXI_WREADY => M_AXI_WREADY, - M_AXI_BID => M_AXI_BID, - M_AXI_BRESP => M_AXI_BRESP, - M_AXI_BVALID => M_AXI_BVALID, - M_AXI_BREADY => M_AXI_BREADY, - M_AXI_ARID => open, - M_AXI_ARADDR => open, - M_AXI_ARLEN => open, - M_AXI_ARSIZE => open, - M_AXI_ARBURST => open, - M_AXI_ARLOCK => open, - M_AXI_ARCACHE => open, - M_AXI_ARPROT => open, - M_AXI_ARREGION => open, - M_AXI_ARQOS => open, - M_AXI_ARVALID => open, - M_AXI_ARREADY => '0', - M_AXI_RID => (others => '0'), - M_AXI_RDATA => (others => '0'), - M_AXI_RRESP => (others => '0'), - M_AXI_RLAST => '0', - M_AXI_RVALID => '0', - M_AXI_RREADY => open, - axiClk => open, - axiRst => open, - axiReadMaster => AXI_READ_MASTER_INIT_C, - axiReadSlave => open, - axiWriteMaster => axiWriteMaster, - axiWriteSlave => axiWriteSlave); + M_AXI_ACLK => axiClk, + M_AXI_ARESETN => axisAResetN, + M_AXI_AWID => M_AXI_AWID, + M_AXI_AWADDR => M_AXI_AWADDR, + M_AXI_AWLEN => M_AXI_AWLEN, + M_AXI_AWSIZE => M_AXI_AWSIZE, + M_AXI_AWBURST => M_AXI_AWBURST, + M_AXI_AWLOCK => open, + M_AXI_AWCACHE => M_AXI_AWCACHE, + M_AXI_AWPROT => M_AXI_AWPROT, + M_AXI_AWREGION => M_AXI_AWREGION, + M_AXI_AWQOS => M_AXI_AWQOS, + M_AXI_AWVALID => M_AXI_AWVALID, + M_AXI_AWREADY => M_AXI_AWREADY, + M_AXI_WID => M_AXI_WID, + M_AXI_WDATA => M_AXI_WDATA, + M_AXI_WSTRB => M_AXI_WSTRB, + M_AXI_WLAST => M_AXI_WLAST, + M_AXI_WVALID => M_AXI_WVALID, + M_AXI_WREADY => M_AXI_WREADY, + M_AXI_BID => M_AXI_BID, + M_AXI_BRESP => M_AXI_BRESP, + M_AXI_BVALID => M_AXI_BVALID, + M_AXI_BREADY => M_AXI_BREADY, + M_AXI_ARID => open, + M_AXI_ARADDR => open, + M_AXI_ARLEN => open, + M_AXI_ARSIZE => open, + M_AXI_ARBURST => open, + M_AXI_ARLOCK => open, + M_AXI_ARCACHE => open, + M_AXI_ARPROT => open, + M_AXI_ARREGION => open, + M_AXI_ARQOS => open, + M_AXI_ARVALID => open, + M_AXI_ARREADY => '0', + M_AXI_RID => (others => '0'), + M_AXI_RDATA => (others => '0'), + M_AXI_RRESP => (others => '0'), + M_AXI_RLAST => '0', + M_AXI_RVALID => '0', + M_AXI_RREADY => open, + axiClk => open, + axiRst => open, + axiReadMaster => AXI_READ_MASTER_INIT_C, + axiReadSlave => open, + axiWriteMaster => axiWriteMaster, + axiWriteSlave => axiWriteSlave); M_AXI_AWLOCK <= '0'; diff --git a/axi/dma/ip_integrator/AxiStreamDmaV2WriteMuxIpIntegrator.vhd b/axi/dma/ip_integrator/AxiStreamDmaV2WriteMuxIpIntegrator.vhd index 94df343d7e..931b6f7468 100644 --- a/axi/dma/ip_integrator/AxiStreamDmaV2WriteMuxIpIntegrator.vhd +++ b/axi/dma/ip_integrator/AxiStreamDmaV2WriteMuxIpIntegrator.vhd @@ -119,28 +119,28 @@ architecture rtl of AxiStreamDmaV2WriteMuxIpIntegrator is begin - dataWriteCtrlPause <= dataWriteCtrl.pause; - dataWriteCtrlOver <= dataWriteCtrl.overflow; - mAxiWriteCtrl.pause <= mAxiWriteCtrlPause; + dataWriteCtrlPause <= dataWriteCtrl.pause; + dataWriteCtrlOver <= dataWriteCtrl.overflow; + mAxiWriteCtrl.pause <= mAxiWriteCtrlPause; mAxiWriteCtrl.overflow <= mAxiWriteCtrlOver; - dataWriteMaster.awid <= resize(DATA_AXI_AWID, dataWriteMaster.awid'length); - dataWriteMaster.awaddr <= resize(DATA_AXI_AWADDR, dataWriteMaster.awaddr'length); - dataWriteMaster.awlen <= DATA_AXI_AWLEN; - dataWriteMaster.awsize <= DATA_AXI_AWSIZE; - dataWriteMaster.awburst <= DATA_AXI_AWBURST; + dataWriteMaster.awid <= resize(DATA_AXI_AWID, dataWriteMaster.awid'length); + dataWriteMaster.awaddr <= resize(DATA_AXI_AWADDR, dataWriteMaster.awaddr'length); + dataWriteMaster.awlen <= DATA_AXI_AWLEN; + dataWriteMaster.awsize <= DATA_AXI_AWSIZE; + dataWriteMaster.awburst <= DATA_AXI_AWBURST; dataWriteMaster.awlock(0) <= DATA_AXI_AWLOCK; - dataWriteMaster.awcache <= DATA_AXI_AWCACHE; - dataWriteMaster.awprot <= DATA_AXI_AWPROT; - dataWriteMaster.awregion <= DATA_AXI_AWREGION; - dataWriteMaster.awqos <= DATA_AXI_AWQOS; - dataWriteMaster.awvalid <= DATA_AXI_AWVALID; - dataWriteMaster.wid <= resize(DATA_AXI_WID, dataWriteMaster.wid'length); - dataWriteMaster.wdata <= resize(DATA_AXI_WDATA, dataWriteMaster.wdata'length); - dataWriteMaster.wstrb <= resize(DATA_AXI_WSTRB, dataWriteMaster.wstrb'length); - dataWriteMaster.wlast <= DATA_AXI_WLAST; - dataWriteMaster.wvalid <= DATA_AXI_WVALID; - dataWriteMaster.bready <= DATA_AXI_BREADY; + dataWriteMaster.awcache <= DATA_AXI_AWCACHE; + dataWriteMaster.awprot <= DATA_AXI_AWPROT; + dataWriteMaster.awregion <= DATA_AXI_AWREGION; + dataWriteMaster.awqos <= DATA_AXI_AWQOS; + dataWriteMaster.awvalid <= DATA_AXI_AWVALID; + dataWriteMaster.wid <= resize(DATA_AXI_WID, dataWriteMaster.wid'length); + dataWriteMaster.wdata <= resize(DATA_AXI_WDATA, dataWriteMaster.wdata'length); + dataWriteMaster.wstrb <= resize(DATA_AXI_WSTRB, dataWriteMaster.wstrb'length); + dataWriteMaster.wlast <= DATA_AXI_WLAST; + dataWriteMaster.wvalid <= DATA_AXI_WVALID; + dataWriteMaster.bready <= DATA_AXI_BREADY; DATA_AXI_AWREADY <= dataWriteSlave.awready; DATA_AXI_WREADY <= dataWriteSlave.wready; @@ -148,23 +148,23 @@ begin DATA_AXI_BRESP <= dataWriteSlave.bresp; DATA_AXI_BVALID <= dataWriteSlave.bvalid; - descWriteMaster.awid <= resize(DESC_AXI_AWID, descWriteMaster.awid'length); - descWriteMaster.awaddr <= resize(DESC_AXI_AWADDR, descWriteMaster.awaddr'length); - descWriteMaster.awlen <= DESC_AXI_AWLEN; - descWriteMaster.awsize <= DESC_AXI_AWSIZE; - descWriteMaster.awburst <= DESC_AXI_AWBURST; + descWriteMaster.awid <= resize(DESC_AXI_AWID, descWriteMaster.awid'length); + descWriteMaster.awaddr <= resize(DESC_AXI_AWADDR, descWriteMaster.awaddr'length); + descWriteMaster.awlen <= DESC_AXI_AWLEN; + descWriteMaster.awsize <= DESC_AXI_AWSIZE; + descWriteMaster.awburst <= DESC_AXI_AWBURST; descWriteMaster.awlock(0) <= DESC_AXI_AWLOCK; - descWriteMaster.awcache <= DESC_AXI_AWCACHE; - descWriteMaster.awprot <= DESC_AXI_AWPROT; - descWriteMaster.awregion <= DESC_AXI_AWREGION; - descWriteMaster.awqos <= DESC_AXI_AWQOS; - descWriteMaster.awvalid <= DESC_AXI_AWVALID; - descWriteMaster.wid <= resize(DESC_AXI_WID, descWriteMaster.wid'length); - descWriteMaster.wdata <= resize(DESC_AXI_WDATA, descWriteMaster.wdata'length); - descWriteMaster.wstrb <= resize(DESC_AXI_WSTRB, descWriteMaster.wstrb'length); - descWriteMaster.wlast <= DESC_AXI_WLAST; - descWriteMaster.wvalid <= DESC_AXI_WVALID; - descWriteMaster.bready <= DESC_AXI_BREADY; + descWriteMaster.awcache <= DESC_AXI_AWCACHE; + descWriteMaster.awprot <= DESC_AXI_AWPROT; + descWriteMaster.awregion <= DESC_AXI_AWREGION; + descWriteMaster.awqos <= DESC_AXI_AWQOS; + descWriteMaster.awvalid <= DESC_AXI_AWVALID; + descWriteMaster.wid <= resize(DESC_AXI_WID, descWriteMaster.wid'length); + descWriteMaster.wdata <= resize(DESC_AXI_WDATA, descWriteMaster.wdata'length); + descWriteMaster.wstrb <= resize(DESC_AXI_WSTRB, descWriteMaster.wstrb'length); + descWriteMaster.wlast <= DESC_AXI_WLAST; + descWriteMaster.wvalid <= DESC_AXI_WVALID; + descWriteMaster.bready <= DESC_AXI_BREADY; DESC_AXI_AWREADY <= descWriteSlave.awready; DESC_AXI_WREADY <= descWriteSlave.wready; @@ -190,11 +190,11 @@ begin M_AXI_WVALID <= mAxiWriteMaster.wvalid; M_AXI_BREADY <= mAxiWriteMaster.bready; - mAxiWriteSlave.awready <= M_AXI_AWREADY; - mAxiWriteSlave.wready <= M_AXI_WREADY; + mAxiWriteSlave.awready <= M_AXI_AWREADY; + mAxiWriteSlave.wready <= M_AXI_WREADY; mAxiWriteSlave.bid(3 downto 0) <= M_AXI_BID; - mAxiWriteSlave.bresp <= M_AXI_BRESP; - mAxiWriteSlave.bvalid <= M_AXI_BVALID; + mAxiWriteSlave.bresp <= M_AXI_BRESP; + mAxiWriteSlave.bvalid <= M_AXI_BVALID; U_DUT : entity surf.AxiStreamDmaV2WriteMux generic map ( diff --git a/axi/dma/ip_integrator/AxiStreamDmaWriteIpIntegrator.vhd b/axi/dma/ip_integrator/AxiStreamDmaWriteIpIntegrator.vhd index 09a9b3cf69..a914fb94fb 100644 --- a/axi/dma/ip_integrator/AxiStreamDmaWriteIpIntegrator.vhd +++ b/axi/dma/ip_integrator/AxiStreamDmaWriteIpIntegrator.vhd @@ -23,54 +23,54 @@ use surf.AxiStreamPkg.all; entity AxiStreamDmaWriteIpIntegrator is port ( - axiClk : in sl; - axiRst : in sl; - dmaReqRequest : in sl; - dmaReqDrop : in sl; - dmaReqAddress : in slv(63 downto 0); - dmaReqMaxSize : in slv(31 downto 0); - dmaReqProt : in slv(2 downto 0); - dmaAckDone : out sl; - dmaAckIdle : out sl; - dmaAckSize : out slv(31 downto 0); - dmaAckOverflow : out sl; - dmaAckWriteError : out sl; - dmaAckErrorValue : out slv(1 downto 0); - dmaAckFirstUser : out slv(7 downto 0); - dmaAckLastUser : out slv(7 downto 0); - dmaAckDest : out slv(7 downto 0); - dmaAckId : out slv(7 downto 0); - axiCache : in slv(3 downto 0); - S_AXIS_TVALID : in sl; - S_AXIS_TDATA : in slv(63 downto 0); - S_AXIS_TKEEP : in slv(7 downto 0); - S_AXIS_TLAST : in sl; - S_AXIS_TDEST : in slv(7 downto 0); - S_AXIS_TID : in slv(7 downto 0); - S_AXIS_TUSER : in slv(1 downto 0); - S_AXIS_TREADY : out sl; - M_AXI_AWID : out slv(7 downto 0); - M_AXI_AWADDR : out slv(15 downto 0); - M_AXI_AWLEN : out slv(7 downto 0); - M_AXI_AWSIZE : out slv(2 downto 0); - M_AXI_AWBURST : out slv(1 downto 0); - M_AXI_AWLOCK : out sl; - M_AXI_AWCACHE : out slv(3 downto 0); - M_AXI_AWPROT : out slv(2 downto 0); - M_AXI_AWREGION : out slv(3 downto 0); - M_AXI_AWQOS : out slv(3 downto 0); - M_AXI_AWVALID : out sl; - M_AXI_AWREADY : in sl; - M_AXI_WID : out slv(7 downto 0); - M_AXI_WDATA : out slv(63 downto 0); - M_AXI_WSTRB : out slv(7 downto 0); - M_AXI_WLAST : out sl; - M_AXI_WVALID : out sl; - M_AXI_WREADY : in sl; - M_AXI_BID : in slv(7 downto 0); - M_AXI_BRESP : in slv(1 downto 0); - M_AXI_BVALID : in sl; - M_AXI_BREADY : out sl); + axiClk : in sl; + axiRst : in sl; + dmaReqRequest : in sl; + dmaReqDrop : in sl; + dmaReqAddress : in slv(63 downto 0); + dmaReqMaxSize : in slv(31 downto 0); + dmaReqProt : in slv(2 downto 0); + dmaAckDone : out sl; + dmaAckIdle : out sl; + dmaAckSize : out slv(31 downto 0); + dmaAckOverflow : out sl; + dmaAckWriteError : out sl; + dmaAckErrorValue : out slv(1 downto 0); + dmaAckFirstUser : out slv(7 downto 0); + dmaAckLastUser : out slv(7 downto 0); + dmaAckDest : out slv(7 downto 0); + dmaAckId : out slv(7 downto 0); + axiCache : in slv(3 downto 0); + S_AXIS_TVALID : in sl; + S_AXIS_TDATA : in slv(63 downto 0); + S_AXIS_TKEEP : in slv(7 downto 0); + S_AXIS_TLAST : in sl; + S_AXIS_TDEST : in slv(7 downto 0); + S_AXIS_TID : in slv(7 downto 0); + S_AXIS_TUSER : in slv(1 downto 0); + S_AXIS_TREADY : out sl; + M_AXI_AWID : out slv(7 downto 0); + M_AXI_AWADDR : out slv(15 downto 0); + M_AXI_AWLEN : out slv(7 downto 0); + M_AXI_AWSIZE : out slv(2 downto 0); + M_AXI_AWBURST : out slv(1 downto 0); + M_AXI_AWLOCK : out sl; + M_AXI_AWCACHE : out slv(3 downto 0); + M_AXI_AWPROT : out slv(2 downto 0); + M_AXI_AWREGION : out slv(3 downto 0); + M_AXI_AWQOS : out slv(3 downto 0); + M_AXI_AWVALID : out sl; + M_AXI_AWREADY : in sl; + M_AXI_WID : out slv(7 downto 0); + M_AXI_WDATA : out slv(63 downto 0); + M_AXI_WSTRB : out slv(7 downto 0); + M_AXI_WLAST : out sl; + M_AXI_WVALID : out sl; + M_AXI_WREADY : in sl; + M_AXI_BID : in slv(7 downto 0); + M_AXI_BRESP : in slv(1 downto 0); + M_AXI_BVALID : in sl; + M_AXI_BREADY : out sl); end entity AxiStreamDmaWriteIpIntegrator; architecture rtl of AxiStreamDmaWriteIpIntegrator is @@ -90,13 +90,13 @@ architecture rtl of AxiStreamDmaWriteIpIntegrator is ID_BITS_C => 8, LEN_BITS_C => 8); - signal axiResetN : sl := '1'; - signal dmaReq : AxiWriteDmaReqType := AXI_WRITE_DMA_REQ_INIT_C; - signal dmaAck : AxiWriteDmaAckType := AXI_WRITE_DMA_ACK_INIT_C; + signal axiResetN : sl := '1'; + signal dmaReq : AxiWriteDmaReqType := AXI_WRITE_DMA_REQ_INIT_C; + signal dmaAck : AxiWriteDmaAckType := AXI_WRITE_DMA_ACK_INIT_C; signal axisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal axisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal axiWriteMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; - signal axiWriteSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C; + signal axiWriteMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C; + signal axiWriteSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C; begin @@ -157,54 +157,54 @@ begin ADDR_WIDTH => 16, DATA_WIDTH => 64) port map ( - M_AXI_ACLK => axiClk, - M_AXI_ARESETN => axiResetN, - M_AXI_AWID => M_AXI_AWID, - M_AXI_AWADDR => M_AXI_AWADDR, - M_AXI_AWLEN => M_AXI_AWLEN, - M_AXI_AWSIZE => M_AXI_AWSIZE, - M_AXI_AWBURST => M_AXI_AWBURST, - M_AXI_AWLOCK => open, - M_AXI_AWCACHE => M_AXI_AWCACHE, - M_AXI_AWPROT => M_AXI_AWPROT, - M_AXI_AWREGION => M_AXI_AWREGION, - M_AXI_AWQOS => M_AXI_AWQOS, - M_AXI_AWVALID => M_AXI_AWVALID, - M_AXI_AWREADY => M_AXI_AWREADY, - M_AXI_WID => M_AXI_WID, - M_AXI_WDATA => M_AXI_WDATA, - M_AXI_WSTRB => M_AXI_WSTRB, - M_AXI_WLAST => M_AXI_WLAST, - M_AXI_WVALID => M_AXI_WVALID, - M_AXI_WREADY => M_AXI_WREADY, - M_AXI_BID => M_AXI_BID, - M_AXI_BRESP => M_AXI_BRESP, - M_AXI_BVALID => M_AXI_BVALID, - M_AXI_BREADY => M_AXI_BREADY, - M_AXI_ARID => open, - M_AXI_ARADDR => open, - M_AXI_ARLEN => open, - M_AXI_ARSIZE => open, - M_AXI_ARBURST => open, - M_AXI_ARLOCK => open, - M_AXI_ARCACHE => open, - M_AXI_ARPROT => open, - M_AXI_ARREGION => open, - M_AXI_ARQOS => open, - M_AXI_ARVALID => open, - M_AXI_ARREADY => '0', - M_AXI_RID => (others => '0'), - M_AXI_RDATA => (others => '0'), - M_AXI_RRESP => (others => '0'), - M_AXI_RLAST => '0', - M_AXI_RVALID => '0', - M_AXI_RREADY => open, - axiClk => open, - axiRst => open, - axiReadMaster => AXI_READ_MASTER_INIT_C, - axiReadSlave => open, - axiWriteMaster => axiWriteMaster, - axiWriteSlave => axiWriteSlave); + M_AXI_ACLK => axiClk, + M_AXI_ARESETN => axiResetN, + M_AXI_AWID => M_AXI_AWID, + M_AXI_AWADDR => M_AXI_AWADDR, + M_AXI_AWLEN => M_AXI_AWLEN, + M_AXI_AWSIZE => M_AXI_AWSIZE, + M_AXI_AWBURST => M_AXI_AWBURST, + M_AXI_AWLOCK => open, + M_AXI_AWCACHE => M_AXI_AWCACHE, + M_AXI_AWPROT => M_AXI_AWPROT, + M_AXI_AWREGION => M_AXI_AWREGION, + M_AXI_AWQOS => M_AXI_AWQOS, + M_AXI_AWVALID => M_AXI_AWVALID, + M_AXI_AWREADY => M_AXI_AWREADY, + M_AXI_WID => M_AXI_WID, + M_AXI_WDATA => M_AXI_WDATA, + M_AXI_WSTRB => M_AXI_WSTRB, + M_AXI_WLAST => M_AXI_WLAST, + M_AXI_WVALID => M_AXI_WVALID, + M_AXI_WREADY => M_AXI_WREADY, + M_AXI_BID => M_AXI_BID, + M_AXI_BRESP => M_AXI_BRESP, + M_AXI_BVALID => M_AXI_BVALID, + M_AXI_BREADY => M_AXI_BREADY, + M_AXI_ARID => open, + M_AXI_ARADDR => open, + M_AXI_ARLEN => open, + M_AXI_ARSIZE => open, + M_AXI_ARBURST => open, + M_AXI_ARLOCK => open, + M_AXI_ARCACHE => open, + M_AXI_ARPROT => open, + M_AXI_ARREGION => open, + M_AXI_ARQOS => open, + M_AXI_ARVALID => open, + M_AXI_ARREADY => '0', + M_AXI_RID => (others => '0'), + M_AXI_RDATA => (others => '0'), + M_AXI_RRESP => (others => '0'), + M_AXI_RLAST => '0', + M_AXI_RVALID => '0', + M_AXI_RREADY => open, + axiClk => open, + axiRst => open, + axiReadMaster => AXI_READ_MASTER_INIT_C, + axiReadSlave => open, + axiWriteMaster => axiWriteMaster, + axiWriteSlave => axiWriteSlave); M_AXI_AWLOCK <= '0'; diff --git a/base/general/wrappers/DebouncerWrapper.vhd b/base/general/wrappers/DebouncerWrapper.vhd index 279613c6a3..bf8719214a 100644 --- a/base/general/wrappers/DebouncerWrapper.vhd +++ b/base/general/wrappers/DebouncerWrapper.vhd @@ -21,14 +21,14 @@ use surf.StdRtlPkg.all; entity DebouncerWrapper is generic ( - TPD_G : time := 1 ns; - RST_POLARITY_G : sl := '1'; - RST_ASYNC_G : boolean := false; - INPUT_POLARITY_G : sl := '0'; - OUTPUT_POLARITY_G : sl := '1'; - SYNCHRONIZE_G : boolean := true; - SYNC_EDGE_TRIG_G : boolean := false; - DEBOUNCE_CYCLES_G : positive := 3); + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + INPUT_POLARITY_G : sl := '0'; + OUTPUT_POLARITY_G : sl := '1'; + SYNCHRONIZE_G : boolean := true; + SYNC_EDGE_TRIG_G : boolean := false; + DEBOUNCE_CYCLES_G : positive := 3); port ( clk : in sl; rst : in sl := not RST_POLARITY_G; diff --git a/base/general/wrappers/HeartbeatWrapper.vhd b/base/general/wrappers/HeartbeatWrapper.vhd index bf88bf4b8c..d9f3fc3e12 100644 --- a/base/general/wrappers/HeartbeatWrapper.vhd +++ b/base/general/wrappers/HeartbeatWrapper.vhd @@ -21,10 +21,10 @@ use surf.StdRtlPkg.all; entity HeartbeatWrapper is generic ( - TPD_G : time := 1 ns; - RST_POLARITY_G : sl := '1'; - RST_ASYNC_G : boolean := false; - TOGGLE_CYCLES_G : positive := 2); + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + TOGGLE_CYCLES_G : positive := 2); port ( clk : in sl; rst : in sl := not RST_POLARITY_G; diff --git a/base/sync/wrappers/SyncClockFreqWrapper.vhd b/base/sync/wrappers/SyncClockFreqWrapper.vhd index 0bc92c608f..d835625763 100644 --- a/base/sync/wrappers/SyncClockFreqWrapper.vhd +++ b/base/sync/wrappers/SyncClockFreqWrapper.vhd @@ -22,15 +22,15 @@ use surf.StdRtlPkg.all; entity SyncClockFreqWrapper is generic ( - TPD_G : time := 1 ns; - RST_ASYNC_G : boolean := false; - USE_DSP_G : string := "no"; - REF_CLK_FREQ_INT_G : positive := 8; - REFRESH_RATE_INT_G : positive := 1; - CLK_LOWER_LIMIT_G : natural := 0; - CLK_UPPER_LIMIT_G : natural := 16; - COMMON_CLK_G : boolean := false; - CNT_WIDTH_G : positive := 32); + TPD_G : time := 1 ns; + RST_ASYNC_G : boolean := false; + USE_DSP_G : string := "no"; + REF_CLK_FREQ_INT_G : positive := 8; + REFRESH_RATE_INT_G : positive := 1; + CLK_LOWER_LIMIT_G : natural := 0; + CLK_UPPER_LIMIT_G : natural := 16; + COMMON_CLK_G : boolean := false; + CNT_WIDTH_G : positive := 32); port ( freqOut : out slv(CNT_WIDTH_G-1 downto 0); freqUpdated : out sl; diff --git a/devices/AnalogDevices/ad9249/core/StreamPatternTester.vhd b/devices/AnalogDevices/ad9249/core/StreamPatternTester.vhd index 58c97fb363..7c01866580 100644 --- a/devices/AnalogDevices/ad9249/core/StreamPatternTester.vhd +++ b/devices/AnalogDevices/ad9249/core/StreamPatternTester.vhd @@ -86,7 +86,7 @@ begin ------------------------------------------------------------------------------------------------- -- AXIL Interface ------------------------------------------------------------------------------------------------- - comb : process (r, axilReadMaster, axilWriteMaster, rst, testFailed, + comb : process (axilReadMaster, axilWriteMaster, r, rst, testFailed, testPassed) is variable v : RegType; variable axilEp : AxiLiteEndpointType; @@ -168,7 +168,7 @@ begin end process; testDone <= '1' when (testCnt >= unsigned(r.testSamples) or timeoutCnt = 0) and r.testRequest = '0' else '0'; - testPassed <= '1' when testDone = '1' and passCnt = unsigned(r.testSamples) else '0'; - testFailed <= '1' when testDone = '1' and passCnt < unsigned(r.testSamples) else '0'; + testPassed <= '1' when testDone = '1' and passCnt = unsigned(r.testSamples) else '0'; + testFailed <= '1' when testDone = '1' and passCnt < unsigned(r.testSamples) else '0'; end rtl; diff --git a/dsp/generic/fixed/FirFilterSingleChannel.vhd b/dsp/generic/fixed/FirFilterSingleChannel.vhd index b318bf3f79..966665dff4 100755 --- a/dsp/generic/fixed/FirFilterSingleChannel.vhd +++ b/dsp/generic/fixed/FirFilterSingleChannel.vhd @@ -77,7 +77,7 @@ architecture mapping of FirFilterSingleChannel is constant NUM_ADDR_BITS_C : positive := bitSize(NUM_TAPS_G-1); - constant FILTER_DELAY_C : integer := (NUM_TAPS_G-1)/2; + constant FILTER_DELAY_C : integer := (NUM_TAPS_G-1)/2; constant OUTPUT_DELAY_C : positive := FILTER_DELAY_C+1; type SidebandPipelineArray is array (OUTPUT_DELAY_C downto 0) of slv(SIDEBAND_WIDTH_G-1 downto 0); diff --git a/dsp/generic/wrappers/FirFilterMultiChannelCacheTestWrapper.vhd b/dsp/generic/wrappers/FirFilterMultiChannelCacheTestWrapper.vhd index ed747ee0ca..40ef63c569 100644 --- a/dsp/generic/wrappers/FirFilterMultiChannelCacheTestWrapper.vhd +++ b/dsp/generic/wrappers/FirFilterMultiChannelCacheTestWrapper.vhd @@ -70,18 +70,18 @@ end entity FirFilterMultiChannelCacheTestWrapper; architecture rtl of FirFilterMultiChannelCacheTestWrapper is - signal axisClkSig : sl; - signal axisRstSig : sl; - signal sAxisMasterSig : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sAxisSlaveSig : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal mAxisMasterSig : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mAxisSlaveSig : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal axilClkSig : sl; - signal axilRstSig : sl; - signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; - signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; - signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; - signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + signal axisClkSig : sl; + signal axisRstSig : sl; + signal sAxisMasterSig : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlaveSig : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal mAxisMasterSig : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlaveSig : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal axilClkSig : sl; + signal axilRstSig : sl; + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; begin diff --git a/dsp/generic/wrappers/FirFilterMultiChannelTestWrapper.vhd b/dsp/generic/wrappers/FirFilterMultiChannelTestWrapper.vhd index 17de64a992..3679751136 100644 --- a/dsp/generic/wrappers/FirFilterMultiChannelTestWrapper.vhd +++ b/dsp/generic/wrappers/FirFilterMultiChannelTestWrapper.vhd @@ -70,18 +70,18 @@ end entity FirFilterMultiChannelTestWrapper; architecture rtl of FirFilterMultiChannelTestWrapper is - signal axisClkSig : sl; - signal axisRstSig : sl; - signal sAxisMasterSig : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sAxisSlaveSig : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal mAxisMasterSig : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mAxisSlaveSig : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal axilClkSig : sl; - signal axilRstSig : sl; - signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; - signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; - signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; - signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + signal axisClkSig : sl; + signal axisRstSig : sl; + signal sAxisMasterSig : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlaveSig : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal mAxisMasterSig : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlaveSig : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal axilClkSig : sl; + signal axilRstSig : sl; + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; begin diff --git a/dsp/generic/wrappers/FirFilterSingleChannelWrapper.vhd b/dsp/generic/wrappers/FirFilterSingleChannelWrapper.vhd index cca6033baf..55f3849c33 100644 --- a/dsp/generic/wrappers/FirFilterSingleChannelWrapper.vhd +++ b/dsp/generic/wrappers/FirFilterSingleChannelWrapper.vhd @@ -22,10 +22,10 @@ use surf.AxiLitePkg.all; entity FirFilterSingleChannelWrapper is generic ( - NUM_TAPS_G : positive := 3; - SIDEBAND_WIDTH_G : positive := 1; - DATA_WIDTH_G : positive := 8; - COEFF_WIDTH_G : positive range 1 to 32 := 4); + NUM_TAPS_G : positive := 3; + SIDEBAND_WIDTH_G : positive := 1; + DATA_WIDTH_G : positive := 8; + COEFF_WIDTH_G : positive range 1 to 32 := 4); port ( clk : in sl; rst : in sl; diff --git a/ethernet/EthMacCore/wrappers/EthMacFlowCtrlWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacFlowCtrlWrapper.vhd index 796f6e2986..69ad35e799 100644 --- a/ethernet/EthMacCore/wrappers/EthMacFlowCtrlWrapper.vhd +++ b/ethernet/EthMacCore/wrappers/EthMacFlowCtrlWrapper.vhd @@ -46,13 +46,13 @@ begin -- Flatten the small `AxiStreamCtrlType` record into individual pause and -- overflow bits so cocotb can drive the public control contract directly. - primCtrl.pause <= primPause; + primCtrl.pause <= primPause; primCtrl.overflow <= primOverflow; - primCtrl.idle <= '0'; + primCtrl.idle <= '0'; - bypCtrl.pause <= bypPause; + bypCtrl.pause <= bypPause; bypCtrl.overflow <= bypOverflow; - bypCtrl.idle <= '0'; + bypCtrl.idle <= '0'; -- Instantiate the real DUT. U_DUT : entity surf.EthMacFlowCtrl @@ -70,7 +70,7 @@ begin -- Re-expand the output record so the test can observe the merged flow -- control result without record-field access. - flowPause <= flowCtrl.pause; + flowPause <= flowCtrl.pause; flowOverflow <= flowCtrl.overflow; end architecture rtl; diff --git a/ethernet/EthMacCore/wrappers/EthMacImportExportLoopbackWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacImportExportLoopbackWrapper.vhd index 690153e751..d8943acfc5 100644 --- a/ethernet/EthMacCore/wrappers/EthMacImportExportLoopbackWrapper.vhd +++ b/ethernet/EthMacCore/wrappers/EthMacImportExportLoopbackWrapper.vhd @@ -62,27 +62,28 @@ architecture rtl of EthMacImportExportLoopbackWrapper is signal xlgmiiTxd : slv(127 downto 0) := (others => '0'); signal xlgmiiTxc : slv(15 downto 0) := (others => '0'); - signal xgmiiTxd : slv(63 downto 0) := (others => '0'); - signal xgmiiTxc : slv(7 downto 0) := (others => '0'); - signal gmiiTxEn : sl := '0'; - signal gmiiTxEr : sl := '0'; - signal gmiiTxd : slv(7 downto 0) := (others => '0'); + signal xgmiiTxd : slv(63 downto 0) := (others => '0'); + signal xgmiiTxc : slv(7 downto 0) := (others => '0'); + signal gmiiTxEn : sl := '0'; + signal gmiiTxEr : sl := '0'; + signal gmiiTxd : slv(7 downto 0) := (others => '0'); begin -- Flatten the source stream for the export-side stimulus path. - sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTDest, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTDest, + sAxisTKeep, sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(127 downto 0) := sAxisTData; - v.tKeep(15 downto 0) := sAxisTKeep; - v.tLast := sAxisTLast; - v.tDest(7 downto 0) := sAxisTDest; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + v.tDest(7 downto 0) := sAxisTDest; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; sAxisTReady <= sAxisSlave.tReady; @@ -91,12 +92,12 @@ begin mAxisView : process (mAxisMaster) is begin mAxisTValid <= mAxisMaster.tValid; - mAxisTData <= mAxisMaster.tData(127 downto 0); - mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); - mAxisTLast <= mAxisMaster.tLast; - mAxisTDest <= mAxisMaster.tDest(7 downto 0); - mAxisSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); - mAxisEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisTDest <= mAxisMaster.tDest(7 downto 0); + mAxisSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); end process mAxisView; -- Generate the PHY-coded stream from a clean AXIS packet source. diff --git a/ethernet/EthMacCore/wrappers/EthMacRxBypassWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacRxBypassWrapper.vhd index c5a52afdb1..cb25fa858b 100644 --- a/ethernet/EthMacCore/wrappers/EthMacRxBypassWrapper.vhd +++ b/ethernet/EthMacCore/wrappers/EthMacRxBypassWrapper.vhd @@ -28,30 +28,30 @@ entity EthMacRxBypassWrapper is BYP_EN_G : boolean := false; BYP_ETH_TYPE_G : slv(15 downto 0) := x"0090"); port ( - ethClk : in sl; - ethRst : in sl; - sAxisTValid : in sl; - sAxisTData : in slv(127 downto 0); - sAxisTKeep : in slv(15 downto 0); - sAxisTLast : in sl; - sAxisTDest : in slv(7 downto 0); - sAxisTReady : out sl; - sAxisSof : in sl; - sAxisEofe : in sl; - mPrimTValid : out sl; - mPrimTData : out slv(127 downto 0); - mPrimTKeep : out slv(15 downto 0); - mPrimTLast : out sl; - mPrimTDest : out slv(7 downto 0); - mPrimSof : out sl; - mPrimEofe : out sl; - mBypTValid : out sl; - mBypTData : out slv(127 downto 0); - mBypTKeep : out slv(15 downto 0); - mBypTLast : out sl; - mBypTDest : out slv(7 downto 0); - mBypSof : out sl; - mBypEofe : out sl); + ethClk : in sl; + ethRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTDest : in slv(7 downto 0); + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisEofe : in sl; + mPrimTValid : out sl; + mPrimTData : out slv(127 downto 0); + mPrimTKeep : out slv(15 downto 0); + mPrimTLast : out sl; + mPrimTDest : out slv(7 downto 0); + mPrimSof : out sl; + mPrimEofe : out sl; + mBypTValid : out sl; + mBypTData : out slv(127 downto 0); + mBypTKeep : out slv(15 downto 0); + mBypTLast : out sl; + mBypTDest : out slv(7 downto 0); + mBypSof : out sl; + mBypEofe : out sl); end entity EthMacRxBypassWrapper; architecture rtl of EthMacRxBypassWrapper is @@ -62,18 +62,19 @@ architecture rtl of EthMacRxBypassWrapper is begin - sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTDest, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTDest, + sAxisTKeep, sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(127 downto 0) := sAxisTData; - v.tKeep(15 downto 0) := sAxisTKeep; - v.tLast := sAxisTLast; - v.tDest(7 downto 0) := sAxisTDest; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + v.tDest(7 downto 0) := sAxisTDest; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; sAxisTReady <= '1'; @@ -81,23 +82,23 @@ begin mPrimView : process (mPrimMaster) is begin mPrimTValid <= mPrimMaster.tValid; - mPrimTData <= mPrimMaster.tData(127 downto 0); - mPrimTKeep <= mPrimMaster.tKeep(15 downto 0); - mPrimTLast <= mPrimMaster.tLast; - mPrimTDest <= mPrimMaster.tDest(7 downto 0); - mPrimSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_SOF_BIT_C, 0); - mPrimEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_EOFE_BIT_C); + mPrimTData <= mPrimMaster.tData(127 downto 0); + mPrimTKeep <= mPrimMaster.tKeep(15 downto 0); + mPrimTLast <= mPrimMaster.tLast; + mPrimTDest <= mPrimMaster.tDest(7 downto 0); + mPrimSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_SOF_BIT_C, 0); + mPrimEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_EOFE_BIT_C); end process mPrimView; mBypView : process (mBypMaster) is begin mBypTValid <= mBypMaster.tValid; - mBypTData <= mBypMaster.tData(127 downto 0); - mBypTKeep <= mBypMaster.tKeep(15 downto 0); - mBypTLast <= mBypMaster.tLast; - mBypTDest <= mBypMaster.tDest(7 downto 0); - mBypSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_SOF_BIT_C, 0); - mBypEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_EOFE_BIT_C); + mBypTData <= mBypMaster.tData(127 downto 0); + mBypTKeep <= mBypMaster.tKeep(15 downto 0); + mBypTLast <= mBypMaster.tLast; + mBypTDest <= mBypMaster.tDest(7 downto 0); + mBypSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_SOF_BIT_C, 0); + mBypEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_EOFE_BIT_C); end process mBypView; U_DUT : entity surf.EthMacRxBypass diff --git a/ethernet/EthMacCore/wrappers/EthMacRxCsumWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacRxCsumWrapper.vhd index 893e702cf9..36bd0b69be 100644 --- a/ethernet/EthMacCore/wrappers/EthMacRxCsumWrapper.vhd +++ b/ethernet/EthMacCore/wrappers/EthMacRxCsumWrapper.vhd @@ -61,18 +61,19 @@ architecture rtl of EthMacRxCsumWrapper is begin - sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, + sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(127 downto 0) := sAxisTData; - v.tKeep(15 downto 0) := sAxisTKeep; - v.tLast := sAxisTLast; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; sAxisTReady <= '1'; @@ -80,13 +81,13 @@ begin mAxisView : process (mAxisMaster) is begin mAxisTValid <= mAxisMaster.tValid; - mAxisTData <= mAxisMaster.tData(127 downto 0); - mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); - mAxisTLast <= mAxisMaster.tLast; - mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); - mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); - mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); - mAxisIpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_IPERR_BIT_C); + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + mAxisIpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_IPERR_BIT_C); mAxisTcpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_TCPERR_BIT_C); mAxisUdpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_UDPERR_BIT_C); end process mAxisView; diff --git a/ethernet/EthMacCore/wrappers/EthMacRxFifoWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacRxFifoWrapper.vhd index 457bc70f12..d7ec50052c 100644 --- a/ethernet/EthMacCore/wrappers/EthMacRxFifoWrapper.vhd +++ b/ethernet/EthMacCore/wrappers/EthMacRxFifoWrapper.vhd @@ -33,37 +33,37 @@ entity EthMacRxFifoWrapper is FIFO_ADDR_WIDTH_G : positive range 9 to 16 := 11; PRIM_COMMON_CLK_G : boolean := false); port ( - sClk : in sl; - sRst : in sl; - mPrimClk : in sl; - mPrimRst : in sl; - phyReady : in sl; - pauseThresh : in slv(15 downto 0); - rxFifoDrop : out sl; - sAxisTValid : in sl; - sAxisTData : in slv(127 downto 0); - sAxisTKeep : in slv(15 downto 0); - sAxisTLast : in sl; - sAxisTReady : out sl; - sAxisSof : in sl; - sAxisFrag : in sl; - sAxisEofe : in sl; - sAxisIpErr : in sl; - sAxisTcpErr : in sl; - sAxisUdpErr : in sl; - sAxisPause : out sl; - sAxisOverflow : out sl; - mAxisTValid : out sl; - mAxisTData : out slv(127 downto 0); - mAxisTKeep : out slv(15 downto 0); - mAxisTLast : out sl; - mAxisTReady : in sl := '1'; - mAxisSof : out sl; - mAxisFrag : out sl; - mAxisEofe : out sl; - mAxisIpErr : out sl; - mAxisTcpErr : out sl; - mAxisUdpErr : out sl); + sClk : in sl; + sRst : in sl; + mPrimClk : in sl; + mPrimRst : in sl; + phyReady : in sl; + pauseThresh : in slv(15 downto 0); + rxFifoDrop : out sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + sAxisIpErr : in sl; + sAxisTcpErr : in sl; + sAxisUdpErr : in sl; + sAxisPause : out sl; + sAxisOverflow : out sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTReady : in sl := '1'; + mAxisSof : out sl; + mAxisFrag : out sl; + mAxisEofe : out sl; + mAxisIpErr : out sl; + mAxisTcpErr : out sl; + mAxisUdpErr : out sl); end entity EthMacRxFifoWrapper; architecture rtl of EthMacRxFifoWrapper is @@ -78,39 +78,41 @@ begin -- The RX-side FIFO input is not backpressured by `TREADY`, so the wrapper -- ties the source ready high and exposes the real pause/overflow controls -- separately for observation in the sClk domain. - sAxisComb : process (sAxisEofe, sAxisFrag, sAxisIpErr, sAxisSof, sAxisTData, sAxisTcpErr, sAxisTKeep, sAxisTLast, sAxisTValid, sAxisUdpErr) is + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisIpErr, sAxisSof, sAxisTData, + sAxisTKeep, sAxisTLast, sAxisTValid, sAxisTcpErr, + sAxisUdpErr) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(127 downto 0) := sAxisTData; - v.tKeep(15 downto 0) := sAxisTKeep; - v.tLast := sAxisTLast; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_IPERR_BIT_C, sAxisIpErr); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_TCPERR_BIT_C, sAxisTcpErr); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_UDPERR_BIT_C, sAxisUdpErr); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; - sAxisTReady <= '1'; - sAxisPause <= sAxisCtrl.pause; - sAxisOverflow <= sAxisCtrl.overflow; + sAxisTReady <= '1'; + sAxisPause <= sAxisCtrl.pause; + sAxisOverflow <= sAxisCtrl.overflow; mAxisSlave.tReady <= mAxisTReady; -- Re-expand the primary output stream after the FIFO crossing. mAxisView : process (mAxisMaster) is begin mAxisTValid <= mAxisMaster.tValid; - mAxisTData <= mAxisMaster.tData(127 downto 0); - mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); - mAxisTLast <= mAxisMaster.tLast; - mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); - mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); - mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); - mAxisIpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_IPERR_BIT_C); + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + mAxisIpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_IPERR_BIT_C); mAxisTcpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_TCPERR_BIT_C); mAxisUdpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_UDPERR_BIT_C); end process mAxisView; diff --git a/ethernet/EthMacCore/wrappers/EthMacRxFilterWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacRxFilterWrapper.vhd index c08a60826e..e441575101 100644 --- a/ethernet/EthMacCore/wrappers/EthMacRxFilterWrapper.vhd +++ b/ethernet/EthMacCore/wrappers/EthMacRxFilterWrapper.vhd @@ -27,28 +27,28 @@ entity EthMacRxFilterWrapper is RST_ASYNC_G : boolean := false; FILT_EN_G : boolean := true); port ( - ethClk : in sl; - ethRst : in sl; - sAxisTValid : in sl; - sAxisTData : in slv(127 downto 0); - sAxisTKeep : in slv(15 downto 0); - sAxisTLast : in sl; - sAxisTReady : out sl; - sAxisSof : in sl; - sAxisFrag : in sl; - sAxisEofe : in sl; - mAxisTValid : out sl; - mAxisTData : out slv(127 downto 0); - mAxisTKeep : out slv(15 downto 0); - mAxisTLast : out sl; - mAxisTReady : in sl := '1'; - mAxisSof : out sl; - mAxisFrag : out sl; - mAxisEofe : out sl; - mAxisPause : in sl; - dropOnPause : in sl; - macAddress : in slv(47 downto 0); - filtEnable : in sl); + ethClk : in sl; + ethRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTReady : in sl := '1'; + mAxisSof : out sl; + mAxisFrag : out sl; + mAxisEofe : out sl; + mAxisPause : in sl; + dropOnPause : in sl; + macAddress : in slv(47 downto 0); + filtEnable : in sl); end entity EthMacRxFilterWrapper; architecture rtl of EthMacRxFilterWrapper is @@ -59,34 +59,35 @@ architecture rtl of EthMacRxFilterWrapper is begin - sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, + sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(127 downto 0) := sAxisTData; - v.tKeep(15 downto 0) := sAxisTKeep; - v.tLast := sAxisTLast; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; - sAxisTReady <= '1'; - mAxisCtrl.pause <= mAxisPause; + sAxisTReady <= '1'; + mAxisCtrl.pause <= mAxisPause; mAxisCtrl.overflow <= '0'; - mAxisCtrl.idle <= '0'; + mAxisCtrl.idle <= '0'; mAxisView : process (mAxisMaster) is begin mAxisTValid <= mAxisMaster.tValid; - mAxisTData <= mAxisMaster.tData(127 downto 0); - mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); - mAxisTLast <= mAxisMaster.tLast; - mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); - mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); - mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); end process mAxisView; U_DUT : entity surf.EthMacRxFilter diff --git a/ethernet/EthMacCore/wrappers/EthMacRxLoopbackWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacRxLoopbackWrapper.vhd index 37aa4ccaa4..d58500bf2d 100644 --- a/ethernet/EthMacCore/wrappers/EthMacRxLoopbackWrapper.vhd +++ b/ethernet/EthMacCore/wrappers/EthMacRxLoopbackWrapper.vhd @@ -32,80 +32,81 @@ entity EthMacRxLoopbackWrapper is BYP_ETH_TYPE_G : slv(15 downto 0) := x"B588"; SYNTH_MODE_G : string := "inferred"); port ( - ethClk : in sl; - ethRst : in sl; - ethClkEn : in sl := '1'; - phyReady : in sl; - sAxisTValid : in sl; - sAxisTData : in slv(127 downto 0); - sAxisTKeep : in slv(15 downto 0); - sAxisTLast : in sl; - sAxisTReady : out sl; - sAxisSof : in sl; - sAxisFrag : in sl; - sAxisEofe : in sl; - mPrimTValid : out sl; - mPrimTData : out slv(127 downto 0); - mPrimTKeep : out slv(15 downto 0); - mPrimTLast : out sl; - mPrimSof : out sl; - mPrimFrag : out sl; - mPrimEofe : out sl; - mPrimIpErr : out sl; - mPrimTcpErr : out sl; - mPrimUdpErr : out sl; - mBypTValid : out sl; - mBypTData : out slv(127 downto 0); - mBypTKeep : out slv(15 downto 0); - mBypTLast : out sl; - mBypSof : out sl; - mBypFrag : out sl; - mBypEofe : out sl; - mBypIpErr : out sl; - mBypTcpErr : out sl; - mBypUdpErr : out sl; - mPrimPause : in sl := '0'; - dropOnPause : in sl; - macAddress : in slv(47 downto 0); - filtEnable : in sl; - ipCsumEn : in sl; - tcpCsumEn : in sl; - udpCsumEn : in sl; - rxPauseReq : out sl; - rxPauseValue : out slv(15 downto 0); - rxCountEn : out sl; - rxCrcError : out sl); + ethClk : in sl; + ethRst : in sl; + ethClkEn : in sl := '1'; + phyReady : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + mPrimTValid : out sl; + mPrimTData : out slv(127 downto 0); + mPrimTKeep : out slv(15 downto 0); + mPrimTLast : out sl; + mPrimSof : out sl; + mPrimFrag : out sl; + mPrimEofe : out sl; + mPrimIpErr : out sl; + mPrimTcpErr : out sl; + mPrimUdpErr : out sl; + mBypTValid : out sl; + mBypTData : out slv(127 downto 0); + mBypTKeep : out slv(15 downto 0); + mBypTLast : out sl; + mBypSof : out sl; + mBypFrag : out sl; + mBypEofe : out sl; + mBypIpErr : out sl; + mBypTcpErr : out sl; + mBypUdpErr : out sl; + mPrimPause : in sl := '0'; + dropOnPause : in sl; + macAddress : in slv(47 downto 0); + filtEnable : in sl; + ipCsumEn : in sl; + tcpCsumEn : in sl; + udpCsumEn : in sl; + rxPauseReq : out sl; + rxPauseValue : out slv(15 downto 0); + rxCountEn : out sl; + rxCrcError : out sl); end entity EthMacRxLoopbackWrapper; architecture rtl of EthMacRxLoopbackWrapper is - signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal mPrimMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mBypMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mPrimCtrl : AxiStreamCtrlType := AXI_STREAM_CTRL_INIT_C; - signal xgmiiTxd : slv(63 downto 0) := (others => '0'); - signal xgmiiTxc : slv(7 downto 0) := (others => '1'); - signal gmiiTxEn : sl := '0'; - signal gmiiTxEr : sl := '0'; - signal gmiiTxd : slv(7 downto 0) := (others => '0'); - signal ethConfig : EthMacConfigType := ETH_MAC_CONFIG_INIT_C; + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mPrimMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mBypMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mPrimCtrl : AxiStreamCtrlType := AXI_STREAM_CTRL_INIT_C; + signal xgmiiTxd : slv(63 downto 0) := (others => '0'); + signal xgmiiTxc : slv(7 downto 0) := (others => '1'); + signal gmiiTxEn : sl := '0'; + signal gmiiTxEr : sl := '0'; + signal gmiiTxd : slv(7 downto 0) := (others => '0'); + signal ethConfig : EthMacConfigType := ETH_MAC_CONFIG_INIT_C; begin -- Flatten the packet source that is exported onto the chosen PHY loopback. - sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, + sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(127 downto 0) := sAxisTData; - v.tKeep(15 downto 0) := sAxisTKeep; - v.tLast := sAxisTLast; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; sAxisTReady <= sAxisSlave.tReady; @@ -114,13 +115,13 @@ begin mPrimView : process (mPrimMaster) is begin mPrimTValid <= mPrimMaster.tValid; - mPrimTData <= mPrimMaster.tData(127 downto 0); - mPrimTKeep <= mPrimMaster.tKeep(15 downto 0); - mPrimTLast <= mPrimMaster.tLast; - mPrimSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_SOF_BIT_C, 0); - mPrimFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_FRAG_BIT_C, 0); - mPrimEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_EOFE_BIT_C); - mPrimIpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_IPERR_BIT_C); + mPrimTData <= mPrimMaster.tData(127 downto 0); + mPrimTKeep <= mPrimMaster.tKeep(15 downto 0); + mPrimTLast <= mPrimMaster.tLast; + mPrimSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_SOF_BIT_C, 0); + mPrimFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_FRAG_BIT_C, 0); + mPrimEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_EOFE_BIT_C); + mPrimIpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_IPERR_BIT_C); mPrimTcpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_TCPERR_BIT_C); mPrimUdpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mPrimMaster, EMAC_UDPERR_BIT_C); end process mPrimView; @@ -129,31 +130,31 @@ begin mBypView : process (mBypMaster) is begin mBypTValid <= mBypMaster.tValid; - mBypTData <= mBypMaster.tData(127 downto 0); - mBypTKeep <= mBypMaster.tKeep(15 downto 0); - mBypTLast <= mBypMaster.tLast; - mBypSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_SOF_BIT_C, 0); - mBypFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_FRAG_BIT_C, 0); - mBypEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_EOFE_BIT_C); - mBypIpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_IPERR_BIT_C); + mBypTData <= mBypMaster.tData(127 downto 0); + mBypTKeep <= mBypMaster.tKeep(15 downto 0); + mBypTLast <= mBypMaster.tLast; + mBypSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_SOF_BIT_C, 0); + mBypFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_FRAG_BIT_C, 0); + mBypEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_EOFE_BIT_C); + mBypIpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_IPERR_BIT_C); mBypTcpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_TCPERR_BIT_C); mBypUdpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mBypMaster, EMAC_UDPERR_BIT_C); end process mBypView; -- Only the pause bit of the primary control record matters for these tests. - mPrimCtrl.pause <= mPrimPause; + mPrimCtrl.pause <= mPrimPause; mPrimCtrl.overflow <= '0'; - mPrimCtrl.idle <= '0'; + mPrimCtrl.idle <= '0'; -- Flatten the small EthMac config record into simple scalar inputs. - ethConfig.macAddress <= macAddress; - ethConfig.filtEnable <= filtEnable; + ethConfig.macAddress <= macAddress; + ethConfig.filtEnable <= filtEnable; ethConfig.pauseEnable <= '0'; - ethConfig.pauseTime <= (others => '0'); + ethConfig.pauseTime <= (others => '0'); ethConfig.pauseThresh <= (others => '0'); - ethConfig.ipCsumEn <= ipCsumEn; - ethConfig.tcpCsumEn <= tcpCsumEn; - ethConfig.udpCsumEn <= udpCsumEn; + ethConfig.ipCsumEn <= ipCsumEn; + ethConfig.tcpCsumEn <= tcpCsumEn; + ethConfig.udpCsumEn <= udpCsumEn; ethConfig.dropOnPause <= dropOnPause; -- Use the real export path to generate protocol-correct PHY symbols. diff --git a/ethernet/EthMacCore/wrappers/EthMacRxPauseWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacRxPauseWrapper.vhd index fde618c4b7..128c5173b9 100644 --- a/ethernet/EthMacCore/wrappers/EthMacRxPauseWrapper.vhd +++ b/ethernet/EthMacCore/wrappers/EthMacRxPauseWrapper.vhd @@ -56,18 +56,19 @@ architecture rtl of EthMacRxPauseWrapper is begin -- Build the EMAC stream record from cocotb-facing scalar ports. - sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, + sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(127 downto 0) := sAxisTData; - v.tKeep(15 downto 0) := sAxisTKeep; - v.tLast := sAxisTLast; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; sAxisTReady <= '1'; @@ -76,12 +77,12 @@ begin mAxisView : process (mAxisMaster) is begin mAxisTValid <= mAxisMaster.tValid; - mAxisTData <= mAxisMaster.tData(127 downto 0); - mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); - mAxisTLast <= mAxisMaster.tLast; - mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); - mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); - mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); end process mAxisView; -- Instantiate the real DUT. diff --git a/ethernet/EthMacCore/wrappers/EthMacRxShiftWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacRxShiftWrapper.vhd index 6264396807..6dcd2154c9 100644 --- a/ethernet/EthMacCore/wrappers/EthMacRxShiftWrapper.vhd +++ b/ethernet/EthMacCore/wrappers/EthMacRxShiftWrapper.vhd @@ -27,25 +27,25 @@ entity EthMacRxShiftWrapper is RST_ASYNC_G : boolean := false; SHIFT_EN_G : boolean := true); port ( - ethClk : in sl; - ethRst : in sl; - sAxisTValid : in sl; - sAxisTData : in slv(127 downto 0); - sAxisTKeep : in slv(15 downto 0); - sAxisTLast : in sl; - sAxisTReady : out sl; - sAxisSof : in sl; - sAxisFrag : in sl; - sAxisEofe : in sl; - mAxisTValid : out sl; - mAxisTData : out slv(127 downto 0); - mAxisTKeep : out slv(15 downto 0); - mAxisTLast : out sl; - mAxisTReady : in sl := '1'; - mAxisSof : out sl; - mAxisFrag : out sl; - mAxisEofe : out sl; - rxShift : in slv(3 downto 0)); + ethClk : in sl; + ethRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTReady : in sl := '1'; + mAxisSof : out sl; + mAxisFrag : out sl; + mAxisEofe : out sl; + rxShift : in slv(3 downto 0)); end entity EthMacRxShiftWrapper; architecture rtl of EthMacRxShiftWrapper is @@ -55,18 +55,19 @@ architecture rtl of EthMacRxShiftWrapper is begin - sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, + sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(127 downto 0) := sAxisTData; - v.tKeep(15 downto 0) := sAxisTKeep; - v.tLast := sAxisTLast; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; sAxisTReady <= '1'; @@ -74,12 +75,12 @@ begin mAxisView : process (mAxisMaster) is begin mAxisTValid <= mAxisMaster.tValid; - mAxisTData <= mAxisMaster.tData(127 downto 0); - mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); - mAxisTLast <= mAxisMaster.tLast; - mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); - mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); - mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); end process mAxisView; U_DUT : entity surf.EthMacRxShift diff --git a/ethernet/EthMacCore/wrappers/EthMacTopLoopbackWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacTopLoopbackWrapper.vhd index 434ba9ad55..9e7357f244 100644 --- a/ethernet/EthMacCore/wrappers/EthMacTopLoopbackWrapper.vhd +++ b/ethernet/EthMacCore/wrappers/EthMacTopLoopbackWrapper.vhd @@ -36,41 +36,41 @@ entity EthMacTopLoopbackWrapper is ROCEV2_EN_G : boolean := false; FILT_EN_G : boolean := false); port ( - ethClk : in sl; - ethRst : in sl; - phyReady : in sl; - sAxisTValid : in sl; - sAxisTData : in slv(127 downto 0); - sAxisTKeep : in slv(15 downto 0); - sAxisTLast : in sl; - sAxisTDest : in slv(7 downto 0); - sAxisTReady : out sl; - sAxisSof : in sl; - sAxisEofe : in sl; - mAxisTValid : out sl; - mAxisTData : out slv(127 downto 0); - mAxisTKeep : out slv(15 downto 0); - mAxisTLast : out sl; - mAxisTDest : out slv(7 downto 0); - mAxisTReady : in sl := '1'; - mAxisSof : out sl; - mAxisEofe : out sl; - localMac : in slv(47 downto 0); - filtEnable : in sl; - pauseEnable : in sl; - pauseTime : in slv(15 downto 0); - pauseThresh : in slv(15 downto 0); - ipCsumEn : in sl; - tcpCsumEn : in sl; - udpCsumEn : in sl; - dropOnPause : in sl; - rxPauseCnt : out sl; - rxOverFlow : out sl; - rxCountEn : out sl; - rxCrcErrorCnt : out sl; - txCountEn : out sl; - txUnderRunCnt : out sl; - txNotReadyCnt : out sl); + ethClk : in sl; + ethRst : in sl; + phyReady : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTDest : in slv(7 downto 0); + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTDest : out slv(7 downto 0); + mAxisTReady : in sl := '1'; + mAxisSof : out sl; + mAxisEofe : out sl; + localMac : in slv(47 downto 0); + filtEnable : in sl; + pauseEnable : in sl; + pauseTime : in slv(15 downto 0); + pauseThresh : in slv(15 downto 0); + ipCsumEn : in sl; + tcpCsumEn : in sl; + udpCsumEn : in sl; + dropOnPause : in sl; + rxPauseCnt : out sl; + rxOverFlow : out sl; + rxCountEn : out sl; + rxCrcErrorCnt : out sl; + txCountEn : out sl; + txUnderRunCnt : out sl; + txNotReadyCnt : out sl); end entity EthMacTopLoopbackWrapper; architecture rtl of EthMacTopLoopbackWrapper is @@ -87,52 +87,53 @@ architecture rtl of EthMacTopLoopbackWrapper is begin -- Flatten the primary AXIS source used by the test. - sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTDest, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTDest, + sAxisTKeep, sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(127 downto 0) := sAxisTData; - v.tKeep(15 downto 0) := sAxisTKeep; - v.tLast := sAxisTLast; - v.tDest(7 downto 0) := sAxisTDest; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; + v.tDest(7 downto 0) := sAxisTDest; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; - sAxisTReady <= sAxisSlave.tReady; + sAxisTReady <= sAxisSlave.tReady; mAxisSlave.tReady <= mAxisTReady; -- Re-expand the received primary AXIS stream for cocotb checks. mAxisView : process (mAxisMaster) is begin mAxisTValid <= mAxisMaster.tValid; - mAxisTData <= mAxisMaster.tData(127 downto 0); - mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); - mAxisTLast <= mAxisMaster.tLast; - mAxisTDest <= mAxisMaster.tDest(7 downto 0); - mAxisSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); - mAxisEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisTDest <= mAxisMaster.tDest(7 downto 0); + mAxisSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); end process mAxisView; -- Flatten the public EthMacTop config record. - ethConfig.macAddress <= localMac; - ethConfig.filtEnable <= filtEnable; + ethConfig.macAddress <= localMac; + ethConfig.filtEnable <= filtEnable; ethConfig.pauseEnable <= pauseEnable; - ethConfig.pauseTime <= pauseTime; + ethConfig.pauseTime <= pauseTime; ethConfig.pauseThresh <= pauseThresh; - ethConfig.ipCsumEn <= ipCsumEn; - ethConfig.tcpCsumEn <= tcpCsumEn; - ethConfig.udpCsumEn <= udpCsumEn; + ethConfig.ipCsumEn <= ipCsumEn; + ethConfig.tcpCsumEn <= tcpCsumEn; + ethConfig.udpCsumEn <= udpCsumEn; ethConfig.dropOnPause <= dropOnPause; -- Flatten the small status record for direct cocotb observation. - rxPauseCnt <= ethStatus.rxPauseCnt; - rxOverFlow <= ethStatus.rxOverFlow; - rxCountEn <= ethStatus.rxCountEn; + rxPauseCnt <= ethStatus.rxPauseCnt; + rxOverFlow <= ethStatus.rxOverFlow; + rxCountEn <= ethStatus.rxCountEn; rxCrcErrorCnt <= ethStatus.rxCrcErrorCnt; - txCountEn <= ethStatus.txCountEn; + txCountEn <= ethStatus.txCountEn; txUnderRunCnt <= ethStatus.txUnderRunCnt; txNotReadyCnt <= ethStatus.txNotReadyCnt; diff --git a/ethernet/EthMacCore/wrappers/EthMacTxBypassWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacTxBypassWrapper.vhd index 0221740083..09fec01471 100644 --- a/ethernet/EthMacCore/wrappers/EthMacTxBypassWrapper.vhd +++ b/ethernet/EthMacCore/wrappers/EthMacTxBypassWrapper.vhd @@ -26,32 +26,32 @@ entity EthMacTxBypassWrapper is RST_POLARITY_G : sl := '1'; BYP_EN_G : boolean := false); port ( - ethClk : in sl; - ethRst : in sl; - sPrimTValid : in sl; - sPrimTData : in slv(127 downto 0); - sPrimTKeep : in slv(15 downto 0); - sPrimTLast : in sl; - sPrimTDest : in slv(7 downto 0); - sPrimTReady : out sl; - sPrimSof : in sl; - sPrimEofe : in sl; - sBypTValid : in sl; - sBypTData : in slv(127 downto 0); - sBypTKeep : in slv(15 downto 0); - sBypTLast : in sl; - sBypTDest : in slv(7 downto 0); - sBypTReady : out sl; - sBypSof : in sl; - sBypEofe : in sl; - mAxisTValid : out sl; - mAxisTData : out slv(127 downto 0); - mAxisTKeep : out slv(15 downto 0); - mAxisTLast : out sl; - mAxisTDest : out slv(7 downto 0); - mAxisTReady : in sl := '1'; - mAxisSof : out sl; - mAxisEofe : out sl); + ethClk : in sl; + ethRst : in sl; + sPrimTValid : in sl; + sPrimTData : in slv(127 downto 0); + sPrimTKeep : in slv(15 downto 0); + sPrimTLast : in sl; + sPrimTDest : in slv(7 downto 0); + sPrimTReady : out sl; + sPrimSof : in sl; + sPrimEofe : in sl; + sBypTValid : in sl; + sBypTData : in slv(127 downto 0); + sBypTKeep : in slv(15 downto 0); + sBypTLast : in sl; + sBypTDest : in slv(7 downto 0); + sBypTReady : out sl; + sBypSof : in sl; + sBypEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTDest : out slv(7 downto 0); + mAxisTReady : in sl := '1'; + mAxisSof : out sl; + mAxisEofe : out sl); end entity EthMacTxBypassWrapper; architecture rtl of EthMacTxBypassWrapper is @@ -65,48 +65,50 @@ architecture rtl of EthMacTxBypassWrapper is begin - sPrimComb : process (sPrimEofe, sPrimSof, sPrimTData, sPrimTDest, sPrimTKeep, sPrimTLast, sPrimTValid) is + sPrimComb : process (sPrimEofe, sPrimSof, sPrimTData, sPrimTDest, + sPrimTKeep, sPrimTLast, sPrimTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sPrimTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sPrimTValid; v.tData(127 downto 0) := sPrimTData; - v.tKeep(15 downto 0) := sPrimTKeep; - v.tLast := sPrimTLast; - v.tDest(7 downto 0) := sPrimTDest; + v.tKeep(15 downto 0) := sPrimTKeep; + v.tLast := sPrimTLast; + v.tDest(7 downto 0) := sPrimTDest; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sPrimSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sPrimEofe); - sPrimMaster <= v; + sPrimMaster <= v; end process sPrimComb; - sBypComb : process (sBypEofe, sBypSof, sBypTData, sBypTDest, sBypTKeep, sBypTLast, sBypTValid) is + sBypComb : process (sBypEofe, sBypSof, sBypTData, sBypTDest, sBypTKeep, + sBypTLast, sBypTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sBypTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sBypTValid; v.tData(127 downto 0) := sBypTData; - v.tKeep(15 downto 0) := sBypTKeep; - v.tLast := sBypTLast; - v.tDest(7 downto 0) := sBypTDest; + v.tKeep(15 downto 0) := sBypTKeep; + v.tLast := sBypTLast; + v.tDest(7 downto 0) := sBypTDest; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sBypSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sBypEofe); - sBypMaster <= v; + sBypMaster <= v; end process sBypComb; mAxisSlave.tReady <= mAxisTReady; sPrimTReady <= sPrimSlave.tReady; - sBypTReady <= sBypSlave.tReady; + sBypTReady <= sBypSlave.tReady; mAxisView : process (mAxisMaster) is begin mAxisTValid <= mAxisMaster.tValid; - mAxisTData <= mAxisMaster.tData(127 downto 0); - mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); - mAxisTLast <= mAxisMaster.tLast; - mAxisTDest <= mAxisMaster.tDest(7 downto 0); - mAxisSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); - mAxisEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisTDest <= mAxisMaster.tDest(7 downto 0); + mAxisSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); end process mAxisView; U_DUT : entity surf.EthMacTxBypass diff --git a/ethernet/EthMacCore/wrappers/EthMacTxCsumLoopbackWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacTxCsumLoopbackWrapper.vhd index 7471ff5981..bf52a789b7 100644 --- a/ethernet/EthMacCore/wrappers/EthMacTxCsumLoopbackWrapper.vhd +++ b/ethernet/EthMacCore/wrappers/EthMacTxCsumLoopbackWrapper.vhd @@ -29,36 +29,36 @@ entity EthMacTxCsumLoopbackWrapper is ROCEV2_EN_G : boolean := false; SYNTH_MODE_G : string := "inferred"); port ( - ethClk : in sl; - ethRst : in sl; - sAxisTValid : in sl; - sAxisTData : in slv(127 downto 0); - sAxisTKeep : in slv(15 downto 0); - sAxisTLast : in sl; - sAxisTReady : out sl; - sAxisSof : in sl; - sAxisFrag : in sl; - sAxisEofe : in sl; - mAxisTValid : out sl; - mAxisTData : out slv(127 downto 0); - mAxisTKeep : out slv(15 downto 0); - mAxisTLast : out sl; - mAxisTReady : in sl := '1'; - mAxisSof : out sl; - mAxisFrag : out sl; - mAxisEofe : out sl; - mAxisIpErr : out sl; - mAxisTcpErr : out sl; - mAxisUdpErr : out sl; - ipCsumEn : in sl; - tcpCsumEn : in sl; - udpCsumEn : in sl); + ethClk : in sl; + ethRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTReady : in sl := '1'; + mAxisSof : out sl; + mAxisFrag : out sl; + mAxisEofe : out sl; + mAxisIpErr : out sl; + mAxisTcpErr : out sl; + mAxisUdpErr : out sl; + ipCsumEn : in sl; + tcpCsumEn : in sl; + udpCsumEn : in sl); end entity EthMacTxCsumLoopbackWrapper; architecture rtl of EthMacTxCsumLoopbackWrapper is - signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal txAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal txAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; @@ -66,21 +66,22 @@ architecture rtl of EthMacTxCsumLoopbackWrapper is begin -- Flatten the source packet stream that will be repaired by TxCsum. - sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, + sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(127 downto 0) := sAxisTData; - v.tKeep(15 downto 0) := sAxisTKeep; - v.tLast := sAxisTLast; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; - sAxisTReady <= sAxisSlave.tReady; + sAxisTReady <= sAxisSlave.tReady; txAxisSlave.tReady <= '1'; -- Present the post-checker stream to cocotb so the test can confirm the @@ -88,13 +89,13 @@ begin mAxisView : process (mAxisMaster) is begin mAxisTValid <= mAxisMaster.tValid; - mAxisTData <= mAxisMaster.tData(127 downto 0); - mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); - mAxisTLast <= mAxisMaster.tLast; - mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); - mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); - mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); - mAxisIpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_IPERR_BIT_C); + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + mAxisIpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_IPERR_BIT_C); mAxisTcpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_TCPERR_BIT_C); mAxisUdpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_UDPERR_BIT_C); end process mAxisView; diff --git a/ethernet/EthMacCore/wrappers/EthMacTxFifoWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacTxFifoWrapper.vhd index c58d10f3a2..22078c3cd7 100644 --- a/ethernet/EthMacCore/wrappers/EthMacTxFifoWrapper.vhd +++ b/ethernet/EthMacCore/wrappers/EthMacTxFifoWrapper.vhd @@ -27,32 +27,32 @@ entity EthMacTxFifoWrapper is PRIM_COMMON_CLK_G : boolean := false; SYNTH_MODE_G : string := "inferred"); port ( - mClk : in sl; - mRst : in sl; - sPrimClk : in sl; - sPrimRst : in sl; - sAxisTValid : in sl; - sAxisTData : in slv(127 downto 0); - sAxisTKeep : in slv(15 downto 0); - sAxisTLast : in sl; - sAxisTReady : out sl; - sAxisSof : in sl; - sAxisFrag : in sl; - sAxisEofe : in sl; - sAxisIpErr : in sl; - sAxisTcpErr : in sl; - sAxisUdpErr : in sl; - mAxisTValid : out sl; - mAxisTData : out slv(127 downto 0); - mAxisTKeep : out slv(15 downto 0); - mAxisTLast : out sl; - mAxisTReady : in sl := '1'; - mAxisSof : out sl; - mAxisFrag : out sl; - mAxisEofe : out sl; - mAxisIpErr : out sl; - mAxisTcpErr : out sl; - mAxisUdpErr : out sl); + mClk : in sl; + mRst : in sl; + sPrimClk : in sl; + sPrimRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + sAxisIpErr : in sl; + sAxisTcpErr : in sl; + sAxisUdpErr : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTReady : in sl := '1'; + mAxisSof : out sl; + mAxisFrag : out sl; + mAxisEofe : out sl; + mAxisIpErr : out sl; + mAxisTcpErr : out sl; + mAxisUdpErr : out sl); end entity EthMacTxFifoWrapper; architecture rtl of EthMacTxFifoWrapper is @@ -65,37 +65,39 @@ architecture rtl of EthMacTxFifoWrapper is begin -- Flatten the primary client stream entering the TX FIFO crossing. - sAxisComb : process (sAxisEofe, sAxisFrag, sAxisIpErr, sAxisSof, sAxisTData, sAxisTcpErr, sAxisTKeep, sAxisTLast, sAxisTValid, sAxisUdpErr) is + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisIpErr, sAxisSof, sAxisTData, + sAxisTKeep, sAxisTLast, sAxisTValid, sAxisTcpErr, + sAxisUdpErr) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(127 downto 0) := sAxisTData; - v.tKeep(15 downto 0) := sAxisTKeep; - v.tLast := sAxisTLast; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_IPERR_BIT_C, sAxisIpErr); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_TCPERR_BIT_C, sAxisTcpErr); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_UDPERR_BIT_C, sAxisUdpErr); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; - sAxisTReady <= sAxisSlave.tReady; + sAxisTReady <= sAxisSlave.tReady; mAxisSlave.tReady <= mAxisTReady; -- Re-expand the MAC-facing output stream for cocotb assertions. mAxisView : process (mAxisMaster) is begin mAxisTValid <= mAxisMaster.tValid; - mAxisTData <= mAxisMaster.tData(127 downto 0); - mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); - mAxisTLast <= mAxisMaster.tLast; - mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); - mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); - mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); - mAxisIpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_IPERR_BIT_C); + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + mAxisIpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_IPERR_BIT_C); mAxisTcpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_TCPERR_BIT_C); mAxisUdpErr <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_UDPERR_BIT_C); end process mAxisView; diff --git a/ethernet/EthMacCore/wrappers/EthMacTxLoopbackWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacTxLoopbackWrapper.vhd index f59380a358..7a4007538c 100644 --- a/ethernet/EthMacCore/wrappers/EthMacTxLoopbackWrapper.vhd +++ b/ethernet/EthMacCore/wrappers/EthMacTxLoopbackWrapper.vhd @@ -91,59 +91,61 @@ architecture rtl of EthMacTxLoopbackWrapper is begin -- Flatten the primary client stream that feeds the TX assembly. - sPrimComb : process (sPrimEofe, sPrimFrag, sPrimSof, sPrimTData, sPrimTKeep, sPrimTLast, sPrimTValid) is + sPrimComb : process (sPrimEofe, sPrimFrag, sPrimSof, sPrimTData, sPrimTKeep, + sPrimTLast, sPrimTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sPrimTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sPrimTValid; v.tData(127 downto 0) := sPrimTData; - v.tKeep(15 downto 0) := sPrimTKeep; - v.tLast := sPrimTLast; + v.tKeep(15 downto 0) := sPrimTKeep; + v.tLast := sPrimTLast; axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sPrimSof, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sPrimFrag, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sPrimEofe); - sPrimMaster <= v; + sPrimMaster <= v; end process sPrimComb; -- Flatten the bypass stream independently so the test can drive both ports. - sBypComb : process (sBypEofe, sBypFrag, sBypSof, sBypTData, sBypTKeep, sBypTLast, sBypTValid) is + sBypComb : process (sBypEofe, sBypFrag, sBypSof, sBypTData, sBypTKeep, + sBypTLast, sBypTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sBypTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sBypTValid; v.tData(127 downto 0) := sBypTData; - v.tKeep(15 downto 0) := sBypTKeep; - v.tLast := sBypTLast; + v.tKeep(15 downto 0) := sBypTKeep; + v.tLast := sBypTLast; axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sBypSof, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sBypFrag, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sBypEofe); - sBypMaster <= v; + sBypMaster <= v; end process sBypComb; sPrimTReady <= sPrimSlave.tReady; - sBypTReady <= sBypSlave.tReady; + sBypTReady <= sBypSlave.tReady; -- Present the recovered on-wire frame back to cocotb as a flat AXIS view. mAxisView : process (mAxisMaster) is begin mAxisTValid <= mAxisMaster.tValid; - mAxisTData <= mAxisMaster.tData(127 downto 0); - mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); - mAxisTLast <= mAxisMaster.tLast; - mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); - mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); - mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); end process mAxisView; -- Flatten the relevant TX config fields under software control. - ethConfig.macAddress <= macAddress; - ethConfig.filtEnable <= '0'; + ethConfig.macAddress <= macAddress; + ethConfig.filtEnable <= '0'; ethConfig.pauseEnable <= pauseEnable; - ethConfig.pauseTime <= pauseTime; + ethConfig.pauseTime <= pauseTime; ethConfig.pauseThresh <= (others => '0'); - ethConfig.ipCsumEn <= ipCsumEn; - ethConfig.tcpCsumEn <= tcpCsumEn; - ethConfig.udpCsumEn <= udpCsumEn; + ethConfig.ipCsumEn <= ipCsumEn; + ethConfig.tcpCsumEn <= tcpCsumEn; + ethConfig.udpCsumEn <= udpCsumEn; ethConfig.dropOnPause <= '0'; -- Drive the full TX assembly, including checksum, pause, and export logic. diff --git a/ethernet/EthMacCore/wrappers/EthMacTxPauseWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacTxPauseWrapper.vhd index 9abc259540..8d5f244e9c 100644 --- a/ethernet/EthMacCore/wrappers/EthMacTxPauseWrapper.vhd +++ b/ethernet/EthMacCore/wrappers/EthMacTxPauseWrapper.vhd @@ -66,21 +66,22 @@ architecture rtl of EthMacTxPauseWrapper is begin -- Flatten the source-side EMAC stream for cocotb. - sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, + sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(127 downto 0) := sAxisTData; - v.tKeep(15 downto 0) := sAxisTKeep; - v.tLast := sAxisTLast; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; - sAxisTReady <= sAxisSlave.tReady; + sAxisTReady <= sAxisSlave.tReady; mAxisSlave.tReady <= mAxisTReady; -- Flatten the DUT output so the pause-frame payload and pass-through data @@ -88,12 +89,12 @@ begin mAxisView : process (mAxisMaster) is begin mAxisTValid <= mAxisMaster.tValid; - mAxisTData <= mAxisMaster.tData(127 downto 0); - mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); - mAxisTLast <= mAxisMaster.tLast; - mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); - mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); - mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); end process mAxisView; U_DUT : entity surf.EthMacTxPause diff --git a/ethernet/EthMacCore/wrappers/EthMacTxShiftWrapper.vhd b/ethernet/EthMacCore/wrappers/EthMacTxShiftWrapper.vhd index 81f20d2ba6..bb17dff8a8 100644 --- a/ethernet/EthMacCore/wrappers/EthMacTxShiftWrapper.vhd +++ b/ethernet/EthMacCore/wrappers/EthMacTxShiftWrapper.vhd @@ -27,25 +27,25 @@ entity EthMacTxShiftWrapper is RST_ASYNC_G : boolean := false; SHIFT_EN_G : boolean := true); port ( - ethClk : in sl; - ethRst : in sl; - sAxisTValid : in sl; - sAxisTData : in slv(127 downto 0); - sAxisTKeep : in slv(15 downto 0); - sAxisTLast : in sl; - sAxisTReady : out sl; - sAxisSof : in sl; - sAxisFrag : in sl; - sAxisEofe : in sl; - mAxisTValid : out sl; - mAxisTData : out slv(127 downto 0); - mAxisTKeep : out slv(15 downto 0); - mAxisTLast : out sl; - mAxisTReady : in sl; - mAxisSof : out sl; - mAxisFrag : out sl; - mAxisEofe : out sl; - txShift : in slv(3 downto 0)); + ethClk : in sl; + ethRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(127 downto 0); + sAxisTKeep : in slv(15 downto 0); + sAxisTLast : in sl; + sAxisTReady : out sl; + sAxisSof : in sl; + sAxisFrag : in sl; + sAxisEofe : in sl; + mAxisTValid : out sl; + mAxisTData : out slv(127 downto 0); + mAxisTKeep : out slv(15 downto 0); + mAxisTLast : out sl; + mAxisTReady : in sl; + mAxisSof : out sl; + mAxisFrag : out sl; + mAxisEofe : out sl; + txShift : in slv(3 downto 0)); end entity EthMacTxShiftWrapper; architecture rtl of EthMacTxShiftWrapper is @@ -57,32 +57,33 @@ architecture rtl of EthMacTxShiftWrapper is begin - sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTKeep, + sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(127 downto 0) := sAxisTData; - v.tKeep(15 downto 0) := sAxisTKeep; - v.tLast := sAxisTLast; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; - sAxisTReady <= sAxisSlave.tReady; + sAxisTReady <= sAxisSlave.tReady; mAxisSlave.tReady <= mAxisTReady; mAxisView : process (mAxisMaster) is begin mAxisTValid <= mAxisMaster.tValid; - mAxisTData <= mAxisMaster.tData(127 downto 0); - mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); - mAxisTLast <= mAxisMaster.tLast; - mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); - mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); - mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisFrag <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_FRAG_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(INT_EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); end process mAxisView; U_DUT : entity surf.EthMacTxShift diff --git a/ethernet/IpV4Engine/wrappers/ArpEngineWrapper.vhd b/ethernet/IpV4Engine/wrappers/ArpEngineWrapper.vhd index 098243ab3f..b8e9124dfc 100644 --- a/ethernet/IpV4Engine/wrappers/ArpEngineWrapper.vhd +++ b/ethernet/IpV4Engine/wrappers/ArpEngineWrapper.vhd @@ -27,50 +27,50 @@ entity ArpEngineWrapper is RST_ASYNC_G : boolean := false; CLK_FREQ_G : real := 100.0E+06); port ( - clk : in sl; - rst : in sl; - localMac : in slv(47 downto 0); - localIp : in slv(31 downto 0); - reqTValid : in sl; - reqTData : in slv(127 downto 0); - reqTKeep : in slv(15 downto 0); - reqTLast : in sl; - reqTReady : out sl; - reqSof : in sl; - reqEofe : in sl; - ackTValid : out sl; - ackTData : out slv(127 downto 0); - ackTKeep : out slv(15 downto 0); - ackTLast : out sl; - ackTReady : in sl := '1'; - ackSof : out sl; - ackEofe : out sl; - sArpTValid : in sl; - sArpTData : in slv(127 downto 0); - sArpTKeep : in slv(15 downto 0); - sArpTLast : in sl; - sArpTReady : out sl; - sArpSof : in sl; - sArpEofe : in sl; - mArpTValid : out sl; - mArpTData : out slv(127 downto 0); - mArpTKeep : out slv(15 downto 0); - mArpTLast : out sl; - mArpTReady : in sl := '1'; - mArpSof : out sl; - mArpEofe : out sl); + clk : in sl; + rst : in sl; + localMac : in slv(47 downto 0); + localIp : in slv(31 downto 0); + reqTValid : in sl; + reqTData : in slv(127 downto 0); + reqTKeep : in slv(15 downto 0); + reqTLast : in sl; + reqTReady : out sl; + reqSof : in sl; + reqEofe : in sl; + ackTValid : out sl; + ackTData : out slv(127 downto 0); + ackTKeep : out slv(15 downto 0); + ackTLast : out sl; + ackTReady : in sl := '1'; + ackSof : out sl; + ackEofe : out sl; + sArpTValid : in sl; + sArpTData : in slv(127 downto 0); + sArpTKeep : in slv(15 downto 0); + sArpTLast : in sl; + sArpTReady : out sl; + sArpSof : in sl; + sArpEofe : in sl; + mArpTValid : out sl; + mArpTData : out slv(127 downto 0); + mArpTKeep : out slv(15 downto 0); + mArpTLast : out sl; + mArpTReady : in sl := '1'; + mArpSof : out sl; + mArpEofe : out sl); end entity ArpEngineWrapper; architecture rtl of ArpEngineWrapper is - signal reqMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal reqSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal ackMaster : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal ackSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal sArpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sArpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal mArpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mArpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal reqMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal reqSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal ackMaster : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal ackSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal sArpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sArpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mArpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mArpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; begin @@ -78,55 +78,56 @@ begin reqComb : process (reqEofe, reqSof, reqTData, reqTKeep, reqTLast, reqTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := reqTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := reqTValid; v.tData(127 downto 0) := reqTData; - v.tKeep(15 downto 0) := reqTKeep; - v.tLast := reqTLast; + v.tKeep(15 downto 0) := reqTKeep; + v.tLast := reqTLast; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, reqSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, reqEofe); - reqMaster <= v; + reqMaster <= v; end process reqComb; -- Flatten the inbound ARP frame stream from the MAC side. - sArpComb : process (sArpEofe, sArpSof, sArpTData, sArpTKeep, sArpTLast, sArpTValid) is + sArpComb : process (sArpEofe, sArpSof, sArpTData, sArpTKeep, sArpTLast, + sArpTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sArpTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sArpTValid; v.tData(127 downto 0) := sArpTData; - v.tKeep(15 downto 0) := sArpTKeep; - v.tLast := sArpTLast; + v.tKeep(15 downto 0) := sArpTKeep; + v.tLast := sArpTLast; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sArpSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sArpEofe); - sArpMaster <= v; + sArpMaster <= v; end process sArpComb; - reqTReady <= reqSlave(0).tReady; - sArpTReady <= sArpSlave.tReady; + reqTReady <= reqSlave(0).tReady; + sArpTReady <= sArpSlave.tReady; ackSlave(0).tReady <= ackTReady; - mArpSlave.tReady <= mArpTReady; + mArpSlave.tReady <= mArpTReady; -- Re-expand the client-facing ARP acknowledgement stream. - ackView : process (ackMaster(0)) is + ackView : process (ackMaster) is begin ackTValid <= ackMaster(0).tValid; - ackTData <= ackMaster(0).tData(127 downto 0); - ackTKeep <= ackMaster(0).tKeep(15 downto 0); - ackTLast <= ackMaster(0).tLast; - ackSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, ackMaster(0), EMAC_SOF_BIT_C, 0); - ackEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, ackMaster(0), EMAC_EOFE_BIT_C); + ackTData <= ackMaster(0).tData(127 downto 0); + ackTKeep <= ackMaster(0).tKeep(15 downto 0); + ackTLast <= ackMaster(0).tLast; + ackSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, ackMaster(0), EMAC_SOF_BIT_C, 0); + ackEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, ackMaster(0), EMAC_EOFE_BIT_C); end process ackView; -- Re-expand the outbound ARP frame stream for direct payload checks. mArpView : process (mArpMaster) is begin mArpTValid <= mArpMaster.tValid; - mArpTData <= mArpMaster.tData(127 downto 0); - mArpTKeep <= mArpMaster.tKeep(15 downto 0); - mArpTLast <= mArpMaster.tLast; - mArpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mArpMaster, EMAC_SOF_BIT_C, 0); - mArpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mArpMaster, EMAC_EOFE_BIT_C); + mArpTData <= mArpMaster.tData(127 downto 0); + mArpTKeep <= mArpMaster.tKeep(15 downto 0); + mArpTLast <= mArpMaster.tLast; + mArpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mArpMaster, EMAC_SOF_BIT_C, 0); + mArpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mArpMaster, EMAC_EOFE_BIT_C); end process mArpView; U_DUT : entity surf.ArpEngine @@ -137,17 +138,17 @@ begin CLIENT_SIZE_G => 1, CLK_FREQ_G => CLK_FREQ_G) port map ( - localMac => localMac, - localIp => localIp, + localMac => localMac, + localIp => localIp, arpReqMasters(0) => reqMaster, - arpReqSlaves => reqSlave, - arpAckMasters => ackMaster, - arpAckSlaves => ackSlave, - ibArpMaster => sArpMaster, - ibArpSlave => sArpSlave, - obArpMaster => mArpMaster, - obArpSlave => mArpSlave, - clk => clk, - rst => rst); + arpReqSlaves => reqSlave, + arpAckMasters => ackMaster, + arpAckSlaves => ackSlave, + ibArpMaster => sArpMaster, + ibArpSlave => sArpSlave, + obArpMaster => mArpMaster, + obArpSlave => mArpSlave, + clk => clk, + rst => rst); end architecture rtl; diff --git a/ethernet/IpV4Engine/wrappers/IcmpEngineWrapper.vhd b/ethernet/IpV4Engine/wrappers/IcmpEngineWrapper.vhd index ae7c7c880a..5b763a5fef 100644 --- a/ethernet/IpV4Engine/wrappers/IcmpEngineWrapper.vhd +++ b/ethernet/IpV4Engine/wrappers/IcmpEngineWrapper.vhd @@ -55,31 +55,32 @@ architecture rtl of IcmpEngineWrapper is begin -- Flatten the ICMP pseudo-header stream presented by cocotb. - sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTKeep, + sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(127 downto 0) := sAxisTData; - v.tKeep(15 downto 0) := sAxisTKeep; - v.tLast := sAxisTLast; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; - sAxisTReady <= sAxisSlave.tReady; + sAxisTReady <= sAxisSlave.tReady; mAxisSlave.tReady <= mAxisTReady; -- Re-expand the outbound ICMP reply pseudo-header stream for checks. mAxisView : process (mAxisMaster) is begin mAxisTValid <= mAxisMaster.tValid; - mAxisTData <= mAxisMaster.tData(127 downto 0); - mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); - mAxisTLast <= mAxisMaster.tLast; - mAxisSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); - mAxisEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); end process mAxisView; U_DUT : entity surf.IcmpEngine diff --git a/ethernet/IpV4Engine/wrappers/IgmpV2EngineWrapper.vhd b/ethernet/IpV4Engine/wrappers/IgmpV2EngineWrapper.vhd index ba200104b4..653652b37c 100644 --- a/ethernet/IpV4Engine/wrappers/IgmpV2EngineWrapper.vhd +++ b/ethernet/IpV4Engine/wrappers/IgmpV2EngineWrapper.vhd @@ -62,31 +62,32 @@ begin igmpIp(1) <= igmpIp1; -- Flatten the IGMP pseudo-header stream presented by cocotb. - sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTKeep, + sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(127 downto 0) := sAxisTData; - v.tKeep(15 downto 0) := sAxisTKeep; - v.tLast := sAxisTLast; + v.tKeep(15 downto 0) := sAxisTKeep; + v.tLast := sAxisTLast; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; - sAxisTReady <= sAxisSlave.tReady; + sAxisTReady <= sAxisSlave.tReady; mAxisSlave.tReady <= mAxisTReady; -- Re-expand the outbound IGMP report pseudo-header stream for checks. mAxisView : process (mAxisMaster) is begin mAxisTValid <= mAxisMaster.tValid; - mAxisTData <= mAxisMaster.tData(127 downto 0); - mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); - mAxisTLast <= mAxisMaster.tLast; - mAxisSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); - mAxisEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); + mAxisTData <= mAxisMaster.tData(127 downto 0); + mAxisTKeep <= mAxisMaster.tKeep(15 downto 0); + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_SOF_BIT_C, 0); + mAxisEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mAxisMaster, EMAC_EOFE_BIT_C); end process mAxisView; U_DUT : entity surf.IgmpV2Engine diff --git a/ethernet/IpV4Engine/wrappers/IpV4EngineDeMuxWrapper.vhd b/ethernet/IpV4Engine/wrappers/IpV4EngineDeMuxWrapper.vhd index 7792bfb592..e8f595605f 100644 --- a/ethernet/IpV4Engine/wrappers/IpV4EngineDeMuxWrapper.vhd +++ b/ethernet/IpV4Engine/wrappers/IpV4EngineDeMuxWrapper.vhd @@ -64,43 +64,44 @@ architecture rtl of IpV4EngineDeMuxWrapper is begin -- Flatten the inbound MAC frame source for direct cocotb stimulus. - sMacComb : process (sMacEofe, sMacSof, sMacTData, sMacTKeep, sMacTLast, sMacTValid) is + sMacComb : process (sMacEofe, sMacSof, sMacTData, sMacTKeep, sMacTLast, + sMacTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sMacTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sMacTValid; v.tData(127 downto 0) := sMacTData; - v.tKeep(15 downto 0) := sMacTKeep; - v.tLast := sMacTLast; + v.tKeep(15 downto 0) := sMacTKeep; + v.tLast := sMacTLast; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sMacSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sMacEofe); - sMacMaster <= v; + sMacMaster <= v; end process sMacComb; - sMacTReady <= sMacSlave.tReady; - mArpSlave.tReady <= mArpTReady; + sMacTReady <= sMacSlave.tReady; + mArpSlave.tReady <= mArpTReady; mIpv4Slave.tReady <= mIpv4TReady; -- Present the selected ARP output stream as a flat cocotb-facing bus. mArpView : process (mArpMaster) is begin mArpTValid <= mArpMaster.tValid; - mArpTData <= mArpMaster.tData(127 downto 0); - mArpTKeep <= mArpMaster.tKeep(15 downto 0); - mArpTLast <= mArpMaster.tLast; - mArpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mArpMaster, EMAC_SOF_BIT_C, 0); - mArpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mArpMaster, EMAC_EOFE_BIT_C); + mArpTData <= mArpMaster.tData(127 downto 0); + mArpTKeep <= mArpMaster.tKeep(15 downto 0); + mArpTLast <= mArpMaster.tLast; + mArpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mArpMaster, EMAC_SOF_BIT_C, 0); + mArpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mArpMaster, EMAC_EOFE_BIT_C); end process mArpView; -- Present the selected IPv4 output stream as a second flat bus. mIpv4View : process (mIpv4Master) is begin mIpv4TValid <= mIpv4Master.tValid; - mIpv4TData <= mIpv4Master.tData(127 downto 0); - mIpv4TKeep <= mIpv4Master.tKeep(15 downto 0); - mIpv4TLast <= mIpv4Master.tLast; - mIpv4Sof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mIpv4Master, EMAC_SOF_BIT_C, 0); - mIpv4Eofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mIpv4Master, EMAC_EOFE_BIT_C); + mIpv4TData <= mIpv4Master.tData(127 downto 0); + mIpv4TKeep <= mIpv4Master.tKeep(15 downto 0); + mIpv4TLast <= mIpv4Master.tLast; + mIpv4Sof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mIpv4Master, EMAC_SOF_BIT_C, 0); + mIpv4Eofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mIpv4Master, EMAC_EOFE_BIT_C); end process mIpv4View; U_DUT : entity surf.IpV4EngineDeMux diff --git a/ethernet/IpV4Engine/wrappers/IpV4EngineRxWrapper.vhd b/ethernet/IpV4Engine/wrappers/IpV4EngineRxWrapper.vhd index 702024bd94..d3159dbb15 100644 --- a/ethernet/IpV4Engine/wrappers/IpV4EngineRxWrapper.vhd +++ b/ethernet/IpV4Engine/wrappers/IpV4EngineRxWrapper.vhd @@ -55,52 +55,53 @@ architecture rtl of IpV4EngineRxWrapper is constant PROTOCOL_C : Slv8Array(1 downto 0) := (0 => UDP_C, 1 => ICMP_C); - signal sIpv4Master : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sIpv4Slave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal localhostSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal sIpv4Master : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sIpv4Slave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal localhostSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal ibProtocolMaster : AxiStreamMasterArray(1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); signal ibProtocolSlave : AxiStreamSlaveArray(1 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); begin -- Flatten the inbound IPv4 MAC frame stream. - sIpv4Comb : process (sIpv4Eofe, sIpv4Sof, sIpv4TData, sIpv4TKeep, sIpv4TLast, sIpv4TValid) is + sIpv4Comb : process (sIpv4Eofe, sIpv4Sof, sIpv4TData, sIpv4TKeep, + sIpv4TLast, sIpv4TValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sIpv4TValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sIpv4TValid; v.tData(127 downto 0) := sIpv4TData; - v.tKeep(15 downto 0) := sIpv4TKeep; - v.tLast := sIpv4TLast; + v.tKeep(15 downto 0) := sIpv4TKeep; + v.tLast := sIpv4TLast; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sIpv4Sof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sIpv4Eofe); - sIpv4Master <= v; + sIpv4Master <= v; end process sIpv4Comb; - sIpv4TReady <= sIpv4Slave.tReady; + sIpv4TReady <= sIpv4Slave.tReady; ibProtocolSlave(0).tReady <= mUdpTReady; ibProtocolSlave(1).tReady <= mIcmpTReady; -- Expose the UDP-routed output slot directly to cocotb. - mUdpView : process (ibProtocolMaster(0)) is + mUdpView : process (ibProtocolMaster) is begin mUdpTValid <= ibProtocolMaster(0).tValid; - mUdpTData <= ibProtocolMaster(0).tData(127 downto 0); - mUdpTKeep <= ibProtocolMaster(0).tKeep(15 downto 0); - mUdpTLast <= ibProtocolMaster(0).tLast; - mUdpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, ibProtocolMaster(0), EMAC_SOF_BIT_C, 0); - mUdpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, ibProtocolMaster(0), EMAC_EOFE_BIT_C); + mUdpTData <= ibProtocolMaster(0).tData(127 downto 0); + mUdpTKeep <= ibProtocolMaster(0).tKeep(15 downto 0); + mUdpTLast <= ibProtocolMaster(0).tLast; + mUdpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, ibProtocolMaster(0), EMAC_SOF_BIT_C, 0); + mUdpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, ibProtocolMaster(0), EMAC_EOFE_BIT_C); end process mUdpView; -- Expose the ICMP-routed output slot in the same flattened format. - mIcmpView : process (ibProtocolMaster(1)) is + mIcmpView : process (ibProtocolMaster) is begin mIcmpTValid <= ibProtocolMaster(1).tValid; - mIcmpTData <= ibProtocolMaster(1).tData(127 downto 0); - mIcmpTKeep <= ibProtocolMaster(1).tKeep(15 downto 0); - mIcmpTLast <= ibProtocolMaster(1).tLast; - mIcmpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, ibProtocolMaster(1), EMAC_SOF_BIT_C, 0); - mIcmpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, ibProtocolMaster(1), EMAC_EOFE_BIT_C); + mIcmpTData <= ibProtocolMaster(1).tData(127 downto 0); + mIcmpTKeep <= ibProtocolMaster(1).tKeep(15 downto 0); + mIcmpTLast <= ibProtocolMaster(1).tLast; + mIcmpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, ibProtocolMaster(1), EMAC_SOF_BIT_C, 0); + mIcmpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, ibProtocolMaster(1), EMAC_EOFE_BIT_C); end process mIcmpView; U_DUT : entity surf.IpV4EngineRx diff --git a/ethernet/IpV4Engine/wrappers/IpV4EngineTopWrapper.vhd b/ethernet/IpV4Engine/wrappers/IpV4EngineTopWrapper.vhd index 75cc47c08e..f3093840d9 100644 --- a/ethernet/IpV4Engine/wrappers/IpV4EngineTopWrapper.vhd +++ b/ethernet/IpV4Engine/wrappers/IpV4EngineTopWrapper.vhd @@ -28,154 +28,157 @@ entity IpV4EngineTopWrapper is CLK_FREQ_G : real := 100.0E+06; TTL_G : slv(7 downto 0) := x"20"); port ( - clk : in sl; - rst : in sl; - localMac : in slv(47 downto 0); - localIp : in slv(31 downto 0); - sMacTValid : in sl; - sMacTData : in slv(127 downto 0); - sMacTKeep : in slv(15 downto 0); - sMacTLast : in sl; - sMacTReady : out sl; - sMacSof : in sl; - sMacEofe : in sl; - mMacTValid : out sl; - mMacTData : out slv(127 downto 0); - mMacTKeep : out slv(15 downto 0); - mMacTLast : out sl; - mMacTReady : in sl := '1'; - mMacSof : out sl; - mMacEofe : out sl; - sProtTValid : in sl; - sProtTData : in slv(127 downto 0); - sProtTKeep : in slv(15 downto 0); - sProtTLast : in sl; - sProtTReady : out sl; - sProtSof : in sl; - sProtEofe : in sl; - mProtTValid : out sl; - mProtTData : out slv(127 downto 0); - mProtTKeep : out slv(15 downto 0); - mProtTLast : out sl; - mProtTReady : in sl := '1'; - mProtSof : out sl; - mProtEofe : out sl; - arpReqTValid : in sl; - arpReqTData : in slv(127 downto 0); - arpReqTKeep : in slv(15 downto 0); - arpReqTLast : in sl; - arpReqTReady : out sl; - arpReqSof : in sl; - arpReqEofe : in sl; - arpAckTValid : out sl; - arpAckTData : out slv(127 downto 0); - arpAckTKeep : out slv(15 downto 0); - arpAckTLast : out sl; - arpAckTReady : in sl := '1'; - arpAckSof : out sl; - arpAckEofe : out sl); + clk : in sl; + rst : in sl; + localMac : in slv(47 downto 0); + localIp : in slv(31 downto 0); + sMacTValid : in sl; + sMacTData : in slv(127 downto 0); + sMacTKeep : in slv(15 downto 0); + sMacTLast : in sl; + sMacTReady : out sl; + sMacSof : in sl; + sMacEofe : in sl; + mMacTValid : out sl; + mMacTData : out slv(127 downto 0); + mMacTKeep : out slv(15 downto 0); + mMacTLast : out sl; + mMacTReady : in sl := '1'; + mMacSof : out sl; + mMacEofe : out sl; + sProtTValid : in sl; + sProtTData : in slv(127 downto 0); + sProtTKeep : in slv(15 downto 0); + sProtTLast : in sl; + sProtTReady : out sl; + sProtSof : in sl; + sProtEofe : in sl; + mProtTValid : out sl; + mProtTData : out slv(127 downto 0); + mProtTKeep : out slv(15 downto 0); + mProtTLast : out sl; + mProtTReady : in sl := '1'; + mProtSof : out sl; + mProtEofe : out sl; + arpReqTValid : in sl; + arpReqTData : in slv(127 downto 0); + arpReqTKeep : in slv(15 downto 0); + arpReqTLast : in sl; + arpReqTReady : out sl; + arpReqSof : in sl; + arpReqEofe : in sl; + arpAckTValid : out sl; + arpAckTData : out slv(127 downto 0); + arpAckTKeep : out slv(15 downto 0); + arpAckTLast : out sl; + arpAckTReady : in sl := '1'; + arpAckSof : out sl; + arpAckEofe : out sl); end entity IpV4EngineTopWrapper; architecture rtl of IpV4EngineTopWrapper is constant PROTOCOL_C : Slv8Array(0 downto 0) := (0 => UDP_C); - signal sMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal mMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal sProtMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sProtSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal mProtMaster : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal mProtSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal arpReqMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal arpReqSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal arpAckMaster : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal arpAckSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal igmpIp : Slv32Array(0 downto 0) := (others => (others => '0')); + signal sMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal sProtMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sProtSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal mProtMaster : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal mProtSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal arpReqMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal arpReqSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal arpAckMaster : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal arpAckSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal igmpIp : Slv32Array(0 downto 0) := (others => (others => '0')); begin -- Flatten the inbound MAC stream for end-to-end top-level stimulus. - sMacComb : process (sMacEofe, sMacSof, sMacTData, sMacTKeep, sMacTLast, sMacTValid) is + sMacComb : process (sMacEofe, sMacSof, sMacTData, sMacTKeep, sMacTLast, + sMacTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sMacTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sMacTValid; v.tData(127 downto 0) := sMacTData; - v.tKeep(15 downto 0) := sMacTKeep; - v.tLast := sMacTLast; + v.tKeep(15 downto 0) := sMacTKeep; + v.tLast := sMacTLast; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sMacSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sMacEofe); - sMacMaster <= v; + sMacMaster <= v; end process sMacComb; -- Flatten the single external protocol-engine source slot. - sProtComb : process (sProtEofe, sProtSof, sProtTData, sProtTKeep, sProtTLast, sProtTValid) is + sProtComb : process (sProtEofe, sProtSof, sProtTData, sProtTKeep, + sProtTLast, sProtTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sProtTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sProtTValid; v.tData(127 downto 0) := sProtTData; - v.tKeep(15 downto 0) := sProtTKeep; - v.tLast := sProtTLast; + v.tKeep(15 downto 0) := sProtTKeep; + v.tLast := sProtTLast; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sProtSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sProtEofe); - sProtMaster <= v; + sProtMaster <= v; end process sProtComb; -- Flatten the single ARP client request slot. - arpReqComb : process (arpReqEofe, arpReqSof, arpReqTData, arpReqTKeep, arpReqTLast, arpReqTValid) is + arpReqComb : process (arpReqEofe, arpReqSof, arpReqTData, arpReqTKeep, + arpReqTLast, arpReqTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := arpReqTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := arpReqTValid; v.tData(127 downto 0) := arpReqTData; - v.tKeep(15 downto 0) := arpReqTKeep; - v.tLast := arpReqTLast; + v.tKeep(15 downto 0) := arpReqTKeep; + v.tLast := arpReqTLast; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, arpReqSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, arpReqEofe); - arpReqMaster <= v; + arpReqMaster <= v; end process arpReqComb; - sMacTReady <= sMacSlave.tReady; - sProtTReady <= sProtSlave(0).tReady; - arpReqTReady <= arpReqSlave(0).tReady; - mMacSlave.tReady <= mMacTReady; - mProtSlave(0).tReady <= mProtTReady; + sMacTReady <= sMacSlave.tReady; + sProtTReady <= sProtSlave(0).tReady; + arpReqTReady <= arpReqSlave(0).tReady; + mMacSlave.tReady <= mMacTReady; + mProtSlave(0).tReady <= mProtTReady; arpAckSlave(0).tReady <= arpAckTReady; -- Re-expand the top-level outbound MAC stream. mMacView : process (mMacMaster) is begin mMacTValid <= mMacMaster.tValid; - mMacTData <= mMacMaster.tData(127 downto 0); - mMacTKeep <= mMacMaster.tKeep(15 downto 0); - mMacTLast <= mMacMaster.tLast; - mMacSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mMacMaster, EMAC_SOF_BIT_C, 0); - mMacEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mMacMaster, EMAC_EOFE_BIT_C); + mMacTData <= mMacMaster.tData(127 downto 0); + mMacTKeep <= mMacMaster.tKeep(15 downto 0); + mMacTLast <= mMacMaster.tLast; + mMacSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mMacMaster, EMAC_SOF_BIT_C, 0); + mMacEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mMacMaster, EMAC_EOFE_BIT_C); end process mMacView; -- Re-expand the exposed protocol slot that receives inbound UDP traffic. - mProtView : process (mProtMaster(0)) is + mProtView : process (mProtMaster) is begin mProtTValid <= mProtMaster(0).tValid; - mProtTData <= mProtMaster(0).tData(127 downto 0); - mProtTKeep <= mProtMaster(0).tKeep(15 downto 0); - mProtTLast <= mProtMaster(0).tLast; - mProtSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mProtMaster(0), EMAC_SOF_BIT_C, 0); - mProtEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mProtMaster(0), EMAC_EOFE_BIT_C); + mProtTData <= mProtMaster(0).tData(127 downto 0); + mProtTKeep <= mProtMaster(0).tKeep(15 downto 0); + mProtTLast <= mProtMaster(0).tLast; + mProtSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mProtMaster(0), EMAC_SOF_BIT_C, 0); + mProtEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mProtMaster(0), EMAC_EOFE_BIT_C); end process mProtView; -- Re-expand the single client ARP acknowledgement slot. - arpAckView : process (arpAckMaster(0)) is + arpAckView : process (arpAckMaster) is begin arpAckTValid <= arpAckMaster(0).tValid; - arpAckTData <= arpAckMaster(0).tData(127 downto 0); - arpAckTKeep <= arpAckMaster(0).tKeep(15 downto 0); - arpAckTLast <= arpAckMaster(0).tLast; - arpAckSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, arpAckMaster(0), EMAC_SOF_BIT_C, 0); - arpAckEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, arpAckMaster(0), EMAC_EOFE_BIT_C); + arpAckTData <= arpAckMaster(0).tData(127 downto 0); + arpAckTKeep <= arpAckMaster(0).tKeep(15 downto 0); + arpAckTLast <= arpAckMaster(0).tLast; + arpAckSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, arpAckMaster(0), EMAC_SOF_BIT_C, 0); + arpAckEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, arpAckMaster(0), EMAC_EOFE_BIT_C); end process arpAckView; U_DUT : entity surf.IpV4Engine diff --git a/ethernet/IpV4Engine/wrappers/IpV4EngineTxWrapper.vhd b/ethernet/IpV4Engine/wrappers/IpV4EngineTxWrapper.vhd index 09031dc84f..8d744bbd03 100644 --- a/ethernet/IpV4Engine/wrappers/IpV4EngineTxWrapper.vhd +++ b/ethernet/IpV4Engine/wrappers/IpV4EngineTxWrapper.vhd @@ -27,85 +27,86 @@ entity IpV4EngineTxWrapper is RST_ASYNC_G : boolean := false; TTL_G : slv(7 downto 0) := x"20"); port ( - clk : in sl; - rst : in sl; - localMac : in slv(47 downto 0); - sProtTValid : in sl; - sProtTData : in slv(127 downto 0); - sProtTKeep : in slv(15 downto 0); - sProtTLast : in sl; - sProtTReady : out sl; - sProtSof : in sl; - sProtEofe : in sl; - mIpv4TValid : out sl; - mIpv4TData : out slv(127 downto 0); - mIpv4TKeep : out slv(15 downto 0); - mIpv4TLast : out sl; - mIpv4TReady : in sl := '1'; - mIpv4Sof : out sl; - mIpv4Eofe : out sl; - mLocalTValid : out sl; - mLocalTData : out slv(127 downto 0); - mLocalTKeep : out slv(15 downto 0); - mLocalTLast : out sl; - mLocalTReady : in sl := '1'; - mLocalSof : out sl; - mLocalEofe : out sl); + clk : in sl; + rst : in sl; + localMac : in slv(47 downto 0); + sProtTValid : in sl; + sProtTData : in slv(127 downto 0); + sProtTKeep : in slv(15 downto 0); + sProtTLast : in sl; + sProtTReady : out sl; + sProtSof : in sl; + sProtEofe : in sl; + mIpv4TValid : out sl; + mIpv4TData : out slv(127 downto 0); + mIpv4TKeep : out slv(15 downto 0); + mIpv4TLast : out sl; + mIpv4TReady : in sl := '1'; + mIpv4Sof : out sl; + mIpv4Eofe : out sl; + mLocalTValid : out sl; + mLocalTData : out slv(127 downto 0); + mLocalTKeep : out slv(15 downto 0); + mLocalTLast : out sl; + mLocalTReady : in sl := '1'; + mLocalSof : out sl; + mLocalEofe : out sl); end entity IpV4EngineTxWrapper; architecture rtl of IpV4EngineTxWrapper is constant PROTOCOL_C : Slv8Array(0 downto 0) := (0 => UDP_C); - signal sProtMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sProtSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal sProtMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sProtSlave : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); signal obProtocolMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal mIpv4Master : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mIpv4Slave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal mLocalMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mLocalSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mIpv4Master : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mIpv4Slave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mLocalMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mLocalSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; begin -- Flatten the single protocol-source stream that feeds the TX engine. - sProtComb : process (sProtEofe, sProtSof, sProtTData, sProtTKeep, sProtTLast, sProtTValid) is + sProtComb : process (sProtEofe, sProtSof, sProtTData, sProtTKeep, + sProtTLast, sProtTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sProtTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sProtTValid; v.tData(127 downto 0) := sProtTData; - v.tKeep(15 downto 0) := sProtTKeep; - v.tLast := sProtTLast; + v.tKeep(15 downto 0) := sProtTKeep; + v.tLast := sProtTLast; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sProtSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sProtEofe); - sProtMaster <= v; + sProtMaster <= v; end process sProtComb; obProtocolMasters(0) <= sProtMaster; - sProtTReady <= sProtSlave(0).tReady; - mIpv4Slave.tReady <= mIpv4TReady; - mLocalSlave.tReady <= mLocalTReady; + sProtTReady <= sProtSlave(0).tReady; + mIpv4Slave.tReady <= mIpv4TReady; + mLocalSlave.tReady <= mLocalTReady; -- Re-expand the external-IPv4 output path. mIpv4View : process (mIpv4Master) is begin mIpv4TValid <= mIpv4Master.tValid; - mIpv4TData <= mIpv4Master.tData(127 downto 0); - mIpv4TKeep <= mIpv4Master.tKeep(15 downto 0); - mIpv4TLast <= mIpv4Master.tLast; - mIpv4Sof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mIpv4Master, EMAC_SOF_BIT_C, 0); - mIpv4Eofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mIpv4Master, EMAC_EOFE_BIT_C); + mIpv4TData <= mIpv4Master.tData(127 downto 0); + mIpv4TKeep <= mIpv4Master.tKeep(15 downto 0); + mIpv4TLast <= mIpv4Master.tLast; + mIpv4Sof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mIpv4Master, EMAC_SOF_BIT_C, 0); + mIpv4Eofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mIpv4Master, EMAC_EOFE_BIT_C); end process mIpv4View; -- Re-expand the localhost shortcut output path separately. mLocalView : process (mLocalMaster) is begin mLocalTValid <= mLocalMaster.tValid; - mLocalTData <= mLocalMaster.tData(127 downto 0); - mLocalTKeep <= mLocalMaster.tKeep(15 downto 0); - mLocalTLast <= mLocalMaster.tLast; - mLocalSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mLocalMaster, EMAC_SOF_BIT_C, 0); - mLocalEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mLocalMaster, EMAC_EOFE_BIT_C); + mLocalTData <= mLocalMaster.tData(127 downto 0); + mLocalTKeep <= mLocalMaster.tKeep(15 downto 0); + mLocalTLast <= mLocalMaster.tLast; + mLocalSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mLocalMaster, EMAC_SOF_BIT_C, 0); + mLocalEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mLocalMaster, EMAC_EOFE_BIT_C); end process mLocalView; U_DUT : entity surf.IpV4EngineTx diff --git a/ethernet/RawEthFramer/wrappers/RawEthFramerFlatWrapper.vhd b/ethernet/RawEthFramer/wrappers/RawEthFramerFlatWrapper.vhd index 219a91eb44..4f47b5baf9 100644 --- a/ethernet/RawEthFramer/wrappers/RawEthFramerFlatWrapper.vhd +++ b/ethernet/RawEthFramer/wrappers/RawEthFramerFlatWrapper.vhd @@ -85,53 +85,55 @@ end entity RawEthFramerFlatWrapper; architecture rtl of RawEthFramerFlatWrapper is - signal sMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal mMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal sAppMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sAppSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal mAppMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mAppSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; - signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal sMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal sAppMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAppSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAppMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAppSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; begin -- Flatten the inbound MAC-side stream that feeds the RX path. - sMacComb : process (sMacEofe, sMacSof, sMacTData, sMacTKeep, sMacTLast, sMacTValid) is + sMacComb : process (sMacEofe, sMacSof, sMacTData, sMacTKeep, sMacTLast, + sMacTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sMacTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sMacTValid; v.tData(63 downto 0) := sMacTData; - v.tKeep(7 downto 0) := sMacTKeep; - v.tLast := sMacTLast; + v.tKeep(7 downto 0) := sMacTKeep; + v.tLast := sMacTLast; ssiSetUserSof(RAW_ETH_CONFIG_INIT_C, v, sMacSof); ssiSetUserEofe(RAW_ETH_CONFIG_INIT_C, v, sMacEofe); - sMacMaster <= v; + sMacMaster <= v; end process sMacComb; -- Flatten the application-side stream that feeds the TX path. - sAppComb : process (sAppBcf, sAppEofe, sAppSof, sAppTData, sAppTDest, sAppTKeep, sAppTLast, sAppTValid) is + sAppComb : process (sAppBcf, sAppEofe, sAppSof, sAppTData, sAppTDest, + sAppTKeep, sAppTLast, sAppTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAppTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAppTValid; v.tData(63 downto 0) := sAppTData; - v.tKeep(7 downto 0) := sAppTKeep; - v.tLast := sAppTLast; - v.tDest(7 downto 0) := sAppTDest; + v.tKeep(7 downto 0) := sAppTKeep; + v.tLast := sAppTLast; + v.tDest(7 downto 0) := sAppTDest; ssiSetUserSof(RAW_ETH_CONFIG_INIT_C, v, sAppSof); ssiSetUserBcf(RAW_ETH_CONFIG_INIT_C, v, sAppBcf); ssiSetUserEofe(RAW_ETH_CONFIG_INIT_C, v, sAppEofe); - sAppMaster <= v; + sAppMaster <= v; end process sAppComb; - sMacTReady <= sMacSlave.tReady; - sAppTReady <= sAppSlave.tReady; + sMacTReady <= sMacSlave.tReady; + sAppTReady <= sAppSlave.tReady; mMacSlave.tReady <= mMacTReady; mAppSlave.tReady <= mAppTReady; @@ -139,24 +141,24 @@ begin mMacView : process (mMacMaster) is begin mMacTValid <= mMacMaster.tValid; - mMacTData <= mMacMaster.tData(63 downto 0); - mMacTKeep <= mMacMaster.tKeep(7 downto 0); - mMacTLast <= mMacMaster.tLast; - mMacSof <= ssiGetUserSof(RAW_ETH_CONFIG_INIT_C, mMacMaster); - mMacEofe <= ssiGetUserEofe(RAW_ETH_CONFIG_INIT_C, mMacMaster); + mMacTData <= mMacMaster.tData(63 downto 0); + mMacTKeep <= mMacMaster.tKeep(7 downto 0); + mMacTLast <= mMacMaster.tLast; + mMacSof <= ssiGetUserSof(RAW_ETH_CONFIG_INIT_C, mMacMaster); + mMacEofe <= ssiGetUserEofe(RAW_ETH_CONFIG_INIT_C, mMacMaster); end process mMacView; -- Re-expand the application-side output stream and metadata. mAppView : process (mAppMaster) is begin mAppTValid <= mAppMaster.tValid; - mAppTData <= mAppMaster.tData(63 downto 0); - mAppTKeep <= mAppMaster.tKeep(7 downto 0); - mAppTLast <= mAppMaster.tLast; - mAppTDest <= mAppMaster.tDest(7 downto 0); - mAppSof <= ssiGetUserSof(RAW_ETH_CONFIG_INIT_C, mAppMaster); - mAppBcf <= ssiGetUserBcf(RAW_ETH_CONFIG_INIT_C, mAppMaster); - mAppEofe <= ssiGetUserEofe(RAW_ETH_CONFIG_INIT_C, mAppMaster); + mAppTData <= mAppMaster.tData(63 downto 0); + mAppTKeep <= mAppMaster.tKeep(7 downto 0); + mAppTLast <= mAppMaster.tLast; + mAppTDest <= mAppMaster.tDest(7 downto 0); + mAppSof <= ssiGetUserSof(RAW_ETH_CONFIG_INIT_C, mAppMaster); + mAppBcf <= ssiGetUserBcf(RAW_ETH_CONFIG_INIT_C, mAppMaster); + mAppEofe <= ssiGetUserEofe(RAW_ETH_CONFIG_INIT_C, mAppMaster); end process mAppView; U_AxilShim : entity surf.SlaveAxiLiteIpIntegrator diff --git a/ethernet/RawEthFramer/wrappers/RawEthFramerPairFlatWrapper.vhd b/ethernet/RawEthFramer/wrappers/RawEthFramerPairFlatWrapper.vhd index a2f367658d..778d3f535f 100644 --- a/ethernet/RawEthFramer/wrappers/RawEthFramerPairFlatWrapper.vhd +++ b/ethernet/RawEthFramer/wrappers/RawEthFramerPairFlatWrapper.vhd @@ -26,46 +26,46 @@ entity RawEthFramerPairFlatWrapper is TPD_G : time := 1 ns; ETH_TYPE_G : slv(15 downto 0) := x"0010"); port ( - clk : in sl; - rst : in sl; - serverLocalMac : in slv(47 downto 0); - clientLocalMac : in slv(47 downto 0); - sServerAppTValid : in sl; - sServerAppTData : in slv(63 downto 0); - sServerAppTKeep : in slv(7 downto 0); - sServerAppTLast : in sl; - sServerAppTReady : out sl; - sServerAppTDest : in slv(7 downto 0); - sServerAppSof : in sl; - sServerAppBcf : in sl; - sServerAppEofe : in sl; - mServerAppTValid : out sl; - mServerAppTData : out slv(63 downto 0); - mServerAppTKeep : out slv(7 downto 0); - mServerAppTLast : out sl; - mServerAppTReady : in sl := '1'; - mServerAppTDest : out slv(7 downto 0); - mServerAppSof : out sl; - mServerAppBcf : out sl; - mServerAppEofe : out sl; - sClientAppTValid : in sl; - sClientAppTData : in slv(63 downto 0); - sClientAppTKeep : in slv(7 downto 0); - sClientAppTLast : in sl; - sClientAppTReady : out sl; - sClientAppTDest : in slv(7 downto 0); - sClientAppSof : in sl; - sClientAppBcf : in sl; - sClientAppEofe : in sl; - mClientAppTValid : out sl; - mClientAppTData : out slv(63 downto 0); - mClientAppTKeep : out slv(7 downto 0); - mClientAppTLast : out sl; - mClientAppTReady : in sl := '1'; - mClientAppTDest : out slv(7 downto 0); - mClientAppSof : out sl; - mClientAppBcf : out sl; - mClientAppEofe : out sl); + clk : in sl; + rst : in sl; + serverLocalMac : in slv(47 downto 0); + clientLocalMac : in slv(47 downto 0); + sServerAppTValid : in sl; + sServerAppTData : in slv(63 downto 0); + sServerAppTKeep : in slv(7 downto 0); + sServerAppTLast : in sl; + sServerAppTReady : out sl; + sServerAppTDest : in slv(7 downto 0); + sServerAppSof : in sl; + sServerAppBcf : in sl; + sServerAppEofe : in sl; + mServerAppTValid : out sl; + mServerAppTData : out slv(63 downto 0); + mServerAppTKeep : out slv(7 downto 0); + mServerAppTLast : out sl; + mServerAppTReady : in sl := '1'; + mServerAppTDest : out slv(7 downto 0); + mServerAppSof : out sl; + mServerAppBcf : out sl; + mServerAppEofe : out sl; + sClientAppTValid : in sl; + sClientAppTData : in slv(63 downto 0); + sClientAppTKeep : in slv(7 downto 0); + sClientAppTLast : in sl; + sClientAppTReady : out sl; + sClientAppTDest : in slv(7 downto 0); + sClientAppSof : in sl; + sClientAppBcf : in sl; + sClientAppEofe : in sl; + mClientAppTValid : out sl; + mClientAppTData : out slv(63 downto 0); + mClientAppTKeep : out slv(7 downto 0); + mClientAppTLast : out sl; + mClientAppTReady : in sl := '1'; + mClientAppTDest : out slv(7 downto 0); + mClientAppSof : out sl; + mClientAppBcf : out sl; + mClientAppEofe : out sl); end entity RawEthFramerPairFlatWrapper; architecture rtl of RawEthFramerPairFlatWrapper is @@ -92,38 +92,42 @@ begin --------------------------------------------------------------------------- -- Application-side stream flattening --------------------------------------------------------------------------- - sServerAppComb : process (sServerAppBcf, sServerAppEofe, sServerAppSof, sServerAppTData, sServerAppTDest, sServerAppTKeep, sServerAppTLast, sServerAppTValid) is + sServerAppComb : process (sServerAppBcf, sServerAppEofe, sServerAppSof, + sServerAppTData, sServerAppTDest, sServerAppTKeep, + sServerAppTLast, sServerAppTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sServerAppTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sServerAppTValid; v.tData(63 downto 0) := sServerAppTData; - v.tKeep(7 downto 0) := sServerAppTKeep; - v.tLast := sServerAppTLast; - v.tDest(7 downto 0) := sServerAppTDest; + v.tKeep(7 downto 0) := sServerAppTKeep; + v.tLast := sServerAppTLast; + v.tDest(7 downto 0) := sServerAppTDest; ssiSetUserSof(RAW_ETH_CONFIG_INIT_C, v, sServerAppSof); ssiSetUserBcf(RAW_ETH_CONFIG_INIT_C, v, sServerAppBcf); ssiSetUserEofe(RAW_ETH_CONFIG_INIT_C, v, sServerAppEofe); - sServerAppMaster <= v; + sServerAppMaster <= v; end process sServerAppComb; - sClientAppComb : process (sClientAppBcf, sClientAppEofe, sClientAppSof, sClientAppTData, sClientAppTDest, sClientAppTKeep, sClientAppTLast, sClientAppTValid) is + sClientAppComb : process (sClientAppBcf, sClientAppEofe, sClientAppSof, + sClientAppTData, sClientAppTDest, sClientAppTKeep, + sClientAppTLast, sClientAppTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sClientAppTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sClientAppTValid; v.tData(63 downto 0) := sClientAppTData; - v.tKeep(7 downto 0) := sClientAppTKeep; - v.tLast := sClientAppTLast; - v.tDest(7 downto 0) := sClientAppTDest; + v.tKeep(7 downto 0) := sClientAppTKeep; + v.tLast := sClientAppTLast; + v.tDest(7 downto 0) := sClientAppTDest; ssiSetUserSof(RAW_ETH_CONFIG_INIT_C, v, sClientAppSof); ssiSetUserBcf(RAW_ETH_CONFIG_INIT_C, v, sClientAppBcf); ssiSetUserEofe(RAW_ETH_CONFIG_INIT_C, v, sClientAppEofe); - sClientAppMaster <= v; + sClientAppMaster <= v; end process sClientAppComb; - sServerAppTReady <= sServerAppSlave.tReady; - sClientAppTReady <= sClientAppSlave.tReady; + sServerAppTReady <= sServerAppSlave.tReady; + sClientAppTReady <= sClientAppSlave.tReady; mServerAppSlave.tReady <= mServerAppTReady; mClientAppSlave.tReady <= mClientAppTReady; @@ -133,34 +137,34 @@ begin mServerAppView : process (mServerAppMaster) is begin mServerAppTValid <= mServerAppMaster.tValid; - mServerAppTData <= mServerAppMaster.tData(63 downto 0); - mServerAppTKeep <= mServerAppMaster.tKeep(7 downto 0); - mServerAppTLast <= mServerAppMaster.tLast; - mServerAppTDest <= mServerAppMaster.tDest(7 downto 0); - mServerAppSof <= ssiGetUserSof(RAW_ETH_CONFIG_INIT_C, mServerAppMaster); - mServerAppBcf <= ssiGetUserBcf(RAW_ETH_CONFIG_INIT_C, mServerAppMaster); - mServerAppEofe <= ssiGetUserEofe(RAW_ETH_CONFIG_INIT_C, mServerAppMaster); + mServerAppTData <= mServerAppMaster.tData(63 downto 0); + mServerAppTKeep <= mServerAppMaster.tKeep(7 downto 0); + mServerAppTLast <= mServerAppMaster.tLast; + mServerAppTDest <= mServerAppMaster.tDest(7 downto 0); + mServerAppSof <= ssiGetUserSof(RAW_ETH_CONFIG_INIT_C, mServerAppMaster); + mServerAppBcf <= ssiGetUserBcf(RAW_ETH_CONFIG_INIT_C, mServerAppMaster); + mServerAppEofe <= ssiGetUserEofe(RAW_ETH_CONFIG_INIT_C, mServerAppMaster); end process mServerAppView; mClientAppView : process (mClientAppMaster) is begin mClientAppTValid <= mClientAppMaster.tValid; - mClientAppTData <= mClientAppMaster.tData(63 downto 0); - mClientAppTKeep <= mClientAppMaster.tKeep(7 downto 0); - mClientAppTLast <= mClientAppMaster.tLast; - mClientAppTDest <= mClientAppMaster.tDest(7 downto 0); - mClientAppSof <= ssiGetUserSof(RAW_ETH_CONFIG_INIT_C, mClientAppMaster); - mClientAppBcf <= ssiGetUserBcf(RAW_ETH_CONFIG_INIT_C, mClientAppMaster); - mClientAppEofe <= ssiGetUserEofe(RAW_ETH_CONFIG_INIT_C, mClientAppMaster); + mClientAppTData <= mClientAppMaster.tData(63 downto 0); + mClientAppTKeep <= mClientAppMaster.tKeep(7 downto 0); + mClientAppTLast <= mClientAppMaster.tLast; + mClientAppTDest <= mClientAppMaster.tDest(7 downto 0); + mClientAppSof <= ssiGetUserSof(RAW_ETH_CONFIG_INIT_C, mClientAppMaster); + mClientAppBcf <= ssiGetUserBcf(RAW_ETH_CONFIG_INIT_C, mClientAppMaster); + mClientAppEofe <= ssiGetUserEofe(RAW_ETH_CONFIG_INIT_C, mClientAppMaster); end process mClientAppView; --------------------------------------------------------------------------- -- Cross-connect the MAC-side ports as a direct link --------------------------------------------------------------------------- serverObMacMaster <= clientIbMacMaster; - clientIbMacSlave <= serverObMacSlave; + clientIbMacSlave <= serverObMacSlave; clientObMacMaster <= serverIbMacMaster; - serverIbMacSlave <= clientObMacSlave; + serverIbMacSlave <= clientObMacSlave; --------------------------------------------------------------------------- -- DUT instantiation diff --git a/ethernet/RawEthFramer/wrappers/RawEthFramerRxFlatWrapper.vhd b/ethernet/RawEthFramer/wrappers/RawEthFramerRxFlatWrapper.vhd index 57bc275596..13f5fbb5a4 100644 --- a/ethernet/RawEthFramer/wrappers/RawEthFramerRxFlatWrapper.vhd +++ b/ethernet/RawEthFramer/wrappers/RawEthFramerRxFlatWrapper.vhd @@ -26,29 +26,29 @@ entity RawEthFramerRxFlatWrapper is TPD_G : time := 1 ns; ETH_TYPE_G : slv(15 downto 0) := x"0010"); port ( - clk : in sl; - rst : in sl; - localMac : in slv(47 downto 0); - remoteMac : in slv(47 downto 0); - req : out sl; - ack : in sl; - tDest : out slv(7 downto 0); - sMacTValid : in sl; - sMacTData : in slv(63 downto 0); - sMacTKeep : in slv(7 downto 0); - sMacTLast : in sl; - sMacTReady : out sl; - sMacSof : in sl; - sMacEofe : in sl; - mAppTValid : out sl; - mAppTData : out slv(63 downto 0); - mAppTKeep : out slv(7 downto 0); - mAppTLast : out sl; - mAppTReady : in sl := '1'; - mAppTDest : out slv(7 downto 0); - mAppSof : out sl; - mAppBcf : out sl; - mAppEofe : out sl); + clk : in sl; + rst : in sl; + localMac : in slv(47 downto 0); + remoteMac : in slv(47 downto 0); + req : out sl; + ack : in sl; + tDest : out slv(7 downto 0); + sMacTValid : in sl; + sMacTData : in slv(63 downto 0); + sMacTKeep : in slv(7 downto 0); + sMacTLast : in sl; + sMacTReady : out sl; + sMacSof : in sl; + sMacEofe : in sl; + mAppTValid : out sl; + mAppTData : out slv(63 downto 0); + mAppTKeep : out slv(7 downto 0); + mAppTLast : out sl; + mAppTReady : in sl := '1'; + mAppTDest : out slv(7 downto 0); + mAppSof : out sl; + mAppBcf : out sl; + mAppEofe : out sl); end entity RawEthFramerRxFlatWrapper; architecture rtl of RawEthFramerRxFlatWrapper is @@ -63,20 +63,21 @@ begin --------------------------------------------------------------------------- -- Stream flattening --------------------------------------------------------------------------- - sMacComb : process (sMacEofe, sMacSof, sMacTData, sMacTKeep, sMacTLast, sMacTValid) is + sMacComb : process (sMacEofe, sMacSof, sMacTData, sMacTKeep, sMacTLast, + sMacTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sMacTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sMacTValid; v.tData(63 downto 0) := sMacTData; - v.tKeep(7 downto 0) := sMacTKeep; - v.tLast := sMacTLast; + v.tKeep(7 downto 0) := sMacTKeep; + v.tLast := sMacTLast; ssiSetUserSof(RAW_ETH_CONFIG_INIT_C, v, sMacSof); ssiSetUserEofe(RAW_ETH_CONFIG_INIT_C, v, sMacEofe); - sMacMaster <= v; + sMacMaster <= v; end process sMacComb; - sMacTReady <= sMacSlave.tReady; + sMacTReady <= sMacSlave.tReady; mAppSlave.tReady <= mAppTReady; --------------------------------------------------------------------------- @@ -85,13 +86,13 @@ begin mAppView : process (mAppMaster) is begin mAppTValid <= mAppMaster.tValid; - mAppTData <= mAppMaster.tData(63 downto 0); - mAppTKeep <= mAppMaster.tKeep(7 downto 0); - mAppTLast <= mAppMaster.tLast; - mAppTDest <= mAppMaster.tDest(7 downto 0); - mAppSof <= ssiGetUserSof(RAW_ETH_CONFIG_INIT_C, mAppMaster); - mAppBcf <= ssiGetUserBcf(RAW_ETH_CONFIG_INIT_C, mAppMaster); - mAppEofe <= ssiGetUserEofe(RAW_ETH_CONFIG_INIT_C, mAppMaster); + mAppTData <= mAppMaster.tData(63 downto 0); + mAppTKeep <= mAppMaster.tKeep(7 downto 0); + mAppTLast <= mAppMaster.tLast; + mAppTDest <= mAppMaster.tDest(7 downto 0); + mAppSof <= ssiGetUserSof(RAW_ETH_CONFIG_INIT_C, mAppMaster); + mAppBcf <= ssiGetUserBcf(RAW_ETH_CONFIG_INIT_C, mAppMaster); + mAppEofe <= ssiGetUserEofe(RAW_ETH_CONFIG_INIT_C, mAppMaster); end process mAppView; --------------------------------------------------------------------------- diff --git a/ethernet/RawEthFramer/wrappers/RawEthFramerTxFlatWrapper.vhd b/ethernet/RawEthFramer/wrappers/RawEthFramerTxFlatWrapper.vhd index b04611ca3f..3c36b4c4b5 100644 --- a/ethernet/RawEthFramer/wrappers/RawEthFramerTxFlatWrapper.vhd +++ b/ethernet/RawEthFramer/wrappers/RawEthFramerTxFlatWrapper.vhd @@ -26,29 +26,29 @@ entity RawEthFramerTxFlatWrapper is TPD_G : time := 1 ns; ETH_TYPE_G : slv(15 downto 0) := x"0010"); port ( - clk : in sl; - rst : in sl; - localMac : in slv(47 downto 0); - remoteMac : in slv(47 downto 0); - req : out sl; - ack : in sl; - tDest : out slv(7 downto 0); - sAppTValid : in sl; - sAppTData : in slv(63 downto 0); - sAppTKeep : in slv(7 downto 0); - sAppTLast : in sl; - sAppTReady : out sl; - sAppTDest : in slv(7 downto 0); - sAppSof : in sl; - sAppBcf : in sl; - sAppEofe : in sl; - mMacTValid : out sl; - mMacTData : out slv(63 downto 0); - mMacTKeep : out slv(7 downto 0); - mMacTLast : out sl; - mMacTReady : in sl := '1'; - mMacSof : out sl; - mMacEofe : out sl); + clk : in sl; + rst : in sl; + localMac : in slv(47 downto 0); + remoteMac : in slv(47 downto 0); + req : out sl; + ack : in sl; + tDest : out slv(7 downto 0); + sAppTValid : in sl; + sAppTData : in slv(63 downto 0); + sAppTKeep : in slv(7 downto 0); + sAppTLast : in sl; + sAppTReady : out sl; + sAppTDest : in slv(7 downto 0); + sAppSof : in sl; + sAppBcf : in sl; + sAppEofe : in sl; + mMacTValid : out sl; + mMacTData : out slv(63 downto 0); + mMacTKeep : out slv(7 downto 0); + mMacTLast : out sl; + mMacTReady : in sl := '1'; + mMacSof : out sl; + mMacEofe : out sl); end entity RawEthFramerTxFlatWrapper; architecture rtl of RawEthFramerTxFlatWrapper is @@ -63,22 +63,23 @@ begin --------------------------------------------------------------------------- -- Stream flattening --------------------------------------------------------------------------- - sAppComb : process (sAppBcf, sAppEofe, sAppSof, sAppTData, sAppTDest, sAppTKeep, sAppTLast, sAppTValid) is + sAppComb : process (sAppBcf, sAppEofe, sAppSof, sAppTData, sAppTDest, + sAppTKeep, sAppTLast, sAppTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAppTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAppTValid; v.tData(63 downto 0) := sAppTData; - v.tKeep(7 downto 0) := sAppTKeep; - v.tLast := sAppTLast; - v.tDest(7 downto 0) := sAppTDest; + v.tKeep(7 downto 0) := sAppTKeep; + v.tLast := sAppTLast; + v.tDest(7 downto 0) := sAppTDest; ssiSetUserSof(RAW_ETH_CONFIG_INIT_C, v, sAppSof); ssiSetUserBcf(RAW_ETH_CONFIG_INIT_C, v, sAppBcf); ssiSetUserEofe(RAW_ETH_CONFIG_INIT_C, v, sAppEofe); - sAppMaster <= v; + sAppMaster <= v; end process sAppComb; - sAppTReady <= sAppSlave.tReady; + sAppTReady <= sAppSlave.tReady; mMacSlave.tReady <= mMacTReady; --------------------------------------------------------------------------- @@ -87,11 +88,11 @@ begin mMacView : process (mMacMaster) is begin mMacTValid <= mMacMaster.tValid; - mMacTData <= mMacMaster.tData(63 downto 0); - mMacTKeep <= mMacMaster.tKeep(7 downto 0); - mMacTLast <= mMacMaster.tLast; - mMacSof <= ssiGetUserSof(RAW_ETH_CONFIG_INIT_C, mMacMaster); - mMacEofe <= ssiGetUserEofe(RAW_ETH_CONFIG_INIT_C, mMacMaster); + mMacTData <= mMacMaster.tData(63 downto 0); + mMacTKeep <= mMacMaster.tKeep(7 downto 0); + mMacTLast <= mMacMaster.tLast; + mMacSof <= ssiGetUserSof(RAW_ETH_CONFIG_INIT_C, mMacMaster); + mMacEofe <= ssiGetUserEofe(RAW_ETH_CONFIG_INIT_C, mMacMaster); end process mMacView; --------------------------------------------------------------------------- diff --git a/ethernet/RoCEv2/wrappers/EthMacPrepareForICrcWrapper.vhd b/ethernet/RoCEv2/wrappers/EthMacPrepareForICrcWrapper.vhd index afd1fc05ff..81fdd20ea4 100644 --- a/ethernet/RoCEv2/wrappers/EthMacPrepareForICrcWrapper.vhd +++ b/ethernet/RoCEv2/wrappers/EthMacPrepareForICrcWrapper.vhd @@ -61,10 +61,11 @@ begin ---------------------------------------------------------------------------- -- Flat cocotb input shim ---------------------------------------------------------------------------- - sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTDest, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTDest, + sAxisTKeep, sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; + v := AXI_STREAM_MASTER_INIT_C; v.tValid := sAxisTValid; v.tData(127 downto 0) := sAxisTData; v.tKeep(15 downto 0) := sAxisTKeep; @@ -73,7 +74,7 @@ begin axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; sAxisTReady <= sAxisSlave.tReady; @@ -81,8 +82,8 @@ begin mAxisReadyComb : process (mAxisTReady) is variable v : AxiStreamSlaveType; begin - v := AXI_STREAM_SLAVE_INIT_C; - v.tReady := mAxisTReady; + v := AXI_STREAM_SLAVE_INIT_C; + v.tReady := mAxisTReady; mAxisSlave <= v; end process mAxisReadyComb; diff --git a/ethernet/RoCEv2/wrappers/EthMacRxCheckICrcWrapper.vhd b/ethernet/RoCEv2/wrappers/EthMacRxCheckICrcWrapper.vhd index abae121bd9..9a1b2b20d2 100644 --- a/ethernet/RoCEv2/wrappers/EthMacRxCheckICrcWrapper.vhd +++ b/ethernet/RoCEv2/wrappers/EthMacRxCheckICrcWrapper.vhd @@ -54,22 +54,23 @@ end entity EthMacRxCheckICrcWrapper; architecture rtl of EthMacRxCheckICrcWrapper is - signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal sCrcMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sCrcSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal sCrcMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sCrcSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; begin ---------------------------------------------------------------------------- -- Flat cocotb input shims ---------------------------------------------------------------------------- - sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTDest, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTDest, + sAxisTKeep, sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; + v := AXI_STREAM_MASTER_INIT_C; v.tValid := sAxisTValid; v.tData(127 downto 0) := sAxisTData; v.tKeep(15 downto 0) := sAxisTKeep; @@ -78,7 +79,7 @@ begin axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; sAxisTReady <= sAxisSlave.tReady; @@ -86,12 +87,12 @@ begin sCrcComb : process (sCrcTData, sCrcTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; + v := AXI_STREAM_MASTER_INIT_C; v.tValid := sCrcTValid; v.tData(31 downto 0) := sCrcTData; v.tKeep(3 downto 0) := x"F"; v.tLast := '1'; - sCrcMaster <= v; + sCrcMaster <= v; end process sCrcComb; sCrcTReady <= sCrcSlave.tReady; @@ -99,8 +100,8 @@ begin mAxisReadyComb : process (mAxisTReady) is variable v : AxiStreamSlaveType; begin - v := AXI_STREAM_SLAVE_INIT_C; - v.tReady := mAxisTReady; + v := AXI_STREAM_SLAVE_INIT_C; + v.tReady := mAxisTReady; mAxisSlave <= v; end process mAxisReadyComb; diff --git a/ethernet/RoCEv2/wrappers/EthMacRxRoCEv2Wrapper.vhd b/ethernet/RoCEv2/wrappers/EthMacRxRoCEv2Wrapper.vhd index 45d42e3839..e509b0a6a3 100644 --- a/ethernet/RoCEv2/wrappers/EthMacRxRoCEv2Wrapper.vhd +++ b/ethernet/RoCEv2/wrappers/EthMacRxRoCEv2Wrapper.vhd @@ -56,10 +56,11 @@ begin ---------------------------------------------------------------------------- -- Flat cocotb input shim ---------------------------------------------------------------------------- - sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTDest, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTDest, + sAxisTKeep, sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; + v := AXI_STREAM_MASTER_INIT_C; v.tValid := sAxisTValid; v.tData(127 downto 0) := sAxisTData; v.tKeep(15 downto 0) := sAxisTKeep; @@ -68,7 +69,7 @@ begin axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; sAxisTReady <= '1'; diff --git a/ethernet/RoCEv2/wrappers/EthMacTxRoCEv2Wrapper.vhd b/ethernet/RoCEv2/wrappers/EthMacTxRoCEv2Wrapper.vhd index 3be75ea7b7..3d5a066609 100644 --- a/ethernet/RoCEv2/wrappers/EthMacTxRoCEv2Wrapper.vhd +++ b/ethernet/RoCEv2/wrappers/EthMacTxRoCEv2Wrapper.vhd @@ -58,10 +58,11 @@ begin ---------------------------------------------------------------------------- -- Flat cocotb input shim ---------------------------------------------------------------------------- - sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTDest, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisFrag, sAxisSof, sAxisTData, sAxisTDest, + sAxisTKeep, sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; + v := AXI_STREAM_MASTER_INIT_C; v.tValid := sAxisTValid; v.tData(127 downto 0) := sAxisTData; v.tKeep(15 downto 0) := sAxisTKeep; @@ -70,7 +71,7 @@ begin axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_FRAG_BIT_C, sAxisFrag, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAxisSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; sAxisTReady <= sAxisSlave.tReady; @@ -78,8 +79,8 @@ begin mAxisReadyComb : process (mAxisTReady) is variable v : AxiStreamSlaveType; begin - v := AXI_STREAM_SLAVE_INIT_C; - v.tReady := mAxisTReady; + v := AXI_STREAM_SLAVE_INIT_C; + v.tReady := mAxisTReady; mAxisSlave <= v; end process mAxisReadyComb; diff --git a/ethernet/RoCEv2/wrappers/RoceConfiguratorWrapper.vhd b/ethernet/RoCEv2/wrappers/RoceConfiguratorWrapper.vhd index 2f6675472d..b73df79eb2 100644 --- a/ethernet/RoCEv2/wrappers/RoceConfiguratorWrapper.vhd +++ b/ethernet/RoCEv2/wrappers/RoceConfiguratorWrapper.vhd @@ -26,33 +26,33 @@ entity RoceConfiguratorWrapper is RST_POLARITY_G : sl := '1'; RST_ASYNC_G : boolean := false); port ( - clk : in sl; - rst : in sl; - M_META_REQ_TVALID : out sl; - M_META_REQ_TDATA : out slv(302 downto 0); - M_META_REQ_TREADY : in sl; - S_META_RESP_TVALID : in sl; - S_META_RESP_TDATA : in slv(275 downto 0); - S_META_RESP_TREADY : out sl; - S_AXIL_AWADDR : in slv(31 downto 0); - S_AXIL_AWPROT : in slv(2 downto 0); - S_AXIL_AWVALID : in sl; - S_AXIL_AWREADY : out sl; - S_AXIL_WDATA : in slv(31 downto 0); - S_AXIL_WSTRB : in slv(3 downto 0); - S_AXIL_WVALID : in sl; - S_AXIL_WREADY : out sl; - S_AXIL_BRESP : out slv(1 downto 0); - S_AXIL_BVALID : out sl; - S_AXIL_BREADY : in sl; - S_AXIL_ARADDR : in slv(31 downto 0); - S_AXIL_ARPROT : in slv(2 downto 0); - S_AXIL_ARVALID : in sl; - S_AXIL_ARREADY : out sl; - S_AXIL_RDATA : out slv(31 downto 0); - S_AXIL_RRESP : out slv(1 downto 0); - S_AXIL_RVALID : out sl; - S_AXIL_RREADY : in sl); + clk : in sl; + rst : in sl; + M_META_REQ_TVALID : out sl; + M_META_REQ_TDATA : out slv(302 downto 0); + M_META_REQ_TREADY : in sl; + S_META_RESP_TVALID : in sl; + S_META_RESP_TDATA : in slv(275 downto 0); + S_META_RESP_TREADY : out sl; + S_AXIL_AWADDR : in slv(31 downto 0); + S_AXIL_AWPROT : in slv(2 downto 0); + S_AXIL_AWVALID : in sl; + S_AXIL_AWREADY : out sl; + S_AXIL_WDATA : in slv(31 downto 0); + S_AXIL_WSTRB : in slv(3 downto 0); + S_AXIL_WVALID : in sl; + S_AXIL_WREADY : out sl; + S_AXIL_BRESP : out slv(1 downto 0); + S_AXIL_BVALID : out sl; + S_AXIL_BREADY : in sl; + S_AXIL_ARADDR : in slv(31 downto 0); + S_AXIL_ARPROT : in slv(2 downto 0); + S_AXIL_ARVALID : in sl; + S_AXIL_ARREADY : out sl; + S_AXIL_RDATA : out slv(31 downto 0); + S_AXIL_RRESP : out slv(1 downto 0); + S_AXIL_RVALID : out sl; + S_AXIL_RREADY : in sl); end entity RoceConfiguratorWrapper; architecture rtl of RoceConfiguratorWrapper is @@ -121,7 +121,7 @@ begin sMetaRespComb : process (S_META_RESP_TDATA, S_META_RESP_TVALID) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; + v := AXI_STREAM_MASTER_INIT_C; v.tValid := S_META_RESP_TVALID; v.tData(275 downto 0) := S_META_RESP_TDATA; sMetaRespMaster <= v; diff --git a/ethernet/RoCEv2/wrappers/RoceResizeAndSwapIpIntegrator.vhd b/ethernet/RoCEv2/wrappers/RoceResizeAndSwapIpIntegrator.vhd index a6863b435f..eb31bfbd79 100644 --- a/ethernet/RoCEv2/wrappers/RoceResizeAndSwapIpIntegrator.vhd +++ b/ethernet/RoCEv2/wrappers/RoceResizeAndSwapIpIntegrator.vhd @@ -72,7 +72,7 @@ architecture rtl of RoceResizeAndSwapIpIntegrator is TUSER_BITS_C => 1, TUSER_MODE_C => TUSER_NORMAL_C); - signal axisAResetN : sl := '1'; + signal axisAResetN : sl := '1'; signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; diff --git a/ethernet/UdpEngine/wrappers/UdpEngineArpFlatWrapper.vhd b/ethernet/UdpEngine/wrappers/UdpEngineArpFlatWrapper.vhd index cd13e26093..9f5cf23dde 100644 --- a/ethernet/UdpEngine/wrappers/UdpEngineArpFlatWrapper.vhd +++ b/ethernet/UdpEngine/wrappers/UdpEngineArpFlatWrapper.vhd @@ -59,47 +59,48 @@ end entity UdpEngineArpFlatWrapper; architecture rtl of UdpEngineArpFlatWrapper is - signal arpReqMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal arpReqSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal arpAckMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal arpAckSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal arpTabMacAddrWArray : Slv48Array(0 downto 0); + signal arpReqMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal arpReqSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal arpAckMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal arpAckSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal arpTabMacAddrWArray : Slv48Array(0 downto 0); signal clientRemoteDetIpArray : Slv32Array(0 downto 0); - signal clientRemoteIpArray : Slv32Array(0 downto 0); - signal clientRemoteMacArray : Slv48Array(0 downto 0); + signal clientRemoteIpArray : Slv32Array(0 downto 0); + signal clientRemoteMacArray : Slv48Array(0 downto 0); begin - arpAckComb : process (arpAckEofe, arpAckSof, arpAckTData, arpAckTKeep, arpAckTLast, arpAckTValid) is + arpAckComb : process (arpAckEofe, arpAckSof, arpAckTData, arpAckTKeep, + arpAckTLast, arpAckTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := arpAckTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := arpAckTValid; v.tData(127 downto 0) := arpAckTData; - v.tKeep(15 downto 0) := arpAckTKeep; - v.tLast := arpAckTLast; + v.tKeep(15 downto 0) := arpAckTKeep; + v.tLast := arpAckTLast; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, arpAckSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, arpAckEofe); - arpAckMasters(0) <= v; + arpAckMasters(0) <= v; end process arpAckComb; - arpReqView : process (arpReqMasters(0)) is + arpReqView : process (arpReqMasters) is begin arpReqTValid <= arpReqMasters(0).tValid; - arpReqTData <= arpReqMasters(0).tData(127 downto 0); - arpReqTKeep <= arpReqMasters(0).tKeep(15 downto 0); - arpReqTLast <= arpReqMasters(0).tLast; - arpReqSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, arpReqMasters(0), EMAC_SOF_BIT_C, 0); - arpReqEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, arpReqMasters(0), EMAC_EOFE_BIT_C); + arpReqTData <= arpReqMasters(0).tData(127 downto 0); + arpReqTKeep <= arpReqMasters(0).tKeep(15 downto 0); + arpReqTLast <= arpReqMasters(0).tLast; + arpReqSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, arpReqMasters(0), EMAC_SOF_BIT_C, 0); + arpReqEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, arpReqMasters(0), EMAC_EOFE_BIT_C); end process arpReqView; arpReqSlaves(0).tReady <= arpReqTReady; - arpAckTReady <= arpAckSlaves(0).tReady; + arpAckTReady <= arpAckSlaves(0).tReady; clientRemoteDetIpArray(0) <= clientRemoteDetIp; - clientRemoteIpArray(0) <= clientRemoteIp; - clientRemoteMac <= clientRemoteMacArray(0); - arpTabMacAddrW <= arpTabMacAddrWArray(0); + clientRemoteIpArray(0) <= clientRemoteIp; + clientRemoteMac <= clientRemoteMacArray(0); + arpTabMacAddrW <= arpTabMacAddrWArray(0); U_DUT : entity surf.UdpEngineArp generic map ( @@ -111,21 +112,21 @@ begin COMM_TIMEOUT_G => COMM_TIMEOUT_G, RESP_TIMEOUT_G => RESP_TIMEOUT_G) port map ( - localIp => localIp, - arpReqMasters => arpReqMasters, - arpReqSlaves => arpReqSlaves, - arpAckMasters => arpAckMasters, - arpAckSlaves => arpAckSlaves, - arpTabFound(0) => arpTabFound, - arpTabMacAddr(0) => arpTabMacAddr, - arpTabIpWe(0) => arpTabIpWe, - arpTabMacWe(0) => arpTabMacWe, - arpTabMacAddrW => arpTabMacAddrWArray, + localIp => localIp, + arpReqMasters => arpReqMasters, + arpReqSlaves => arpReqSlaves, + arpAckMasters => arpAckMasters, + arpAckSlaves => arpAckSlaves, + arpTabFound(0) => arpTabFound, + arpTabMacAddr(0) => arpTabMacAddr, + arpTabIpWe(0) => arpTabIpWe, + arpTabMacWe(0) => arpTabMacWe, + arpTabMacAddrW => arpTabMacAddrWArray, clientRemoteDetValid(0) => clientRemoteDetValid, - clientRemoteDetIp => clientRemoteDetIpArray, - clientRemoteIp => clientRemoteIpArray, - clientRemoteMac => clientRemoteMacArray, - clk => clk, - rst => rst); + clientRemoteDetIp => clientRemoteDetIpArray, + clientRemoteIp => clientRemoteIpArray, + clientRemoteMac => clientRemoteMacArray, + clk => clk, + rst => rst); end architecture rtl; diff --git a/ethernet/UdpEngine/wrappers/UdpEngineDhcpFlatWrapper.vhd b/ethernet/UdpEngine/wrappers/UdpEngineDhcpFlatWrapper.vhd index de4ecb303e..57d84495be 100644 --- a/ethernet/UdpEngine/wrappers/UdpEngineDhcpFlatWrapper.vhd +++ b/ethernet/UdpEngine/wrappers/UdpEngineDhcpFlatWrapper.vhd @@ -59,30 +59,31 @@ architecture rtl of UdpEngineDhcpFlatWrapper is begin - sDhcpComb : process (sDhcpEofe, sDhcpSof, sDhcpTData, sDhcpTKeep, sDhcpTLast, sDhcpTValid) is + sDhcpComb : process (sDhcpEofe, sDhcpSof, sDhcpTData, sDhcpTKeep, + sDhcpTLast, sDhcpTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sDhcpTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sDhcpTValid; v.tData(127 downto 0) := sDhcpTData; - v.tKeep(15 downto 0) := sDhcpTKeep; - v.tLast := sDhcpTLast; + v.tKeep(15 downto 0) := sDhcpTKeep; + v.tLast := sDhcpTLast; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sDhcpSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sDhcpEofe); - sDhcpMaster <= v; + sDhcpMaster <= v; end process sDhcpComb; mDhcpView : process (mDhcpMaster) is begin mDhcpTValid <= mDhcpMaster.tValid; - mDhcpTData <= mDhcpMaster.tData(127 downto 0); - mDhcpTKeep <= mDhcpMaster.tKeep(15 downto 0); - mDhcpTLast <= mDhcpMaster.tLast; - mDhcpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mDhcpMaster, EMAC_SOF_BIT_C, 0); - mDhcpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mDhcpMaster, EMAC_EOFE_BIT_C); + mDhcpTData <= mDhcpMaster.tData(127 downto 0); + mDhcpTKeep <= mDhcpMaster.tKeep(15 downto 0); + mDhcpTLast <= mDhcpMaster.tLast; + mDhcpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mDhcpMaster, EMAC_SOF_BIT_C, 0); + mDhcpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mDhcpMaster, EMAC_EOFE_BIT_C); end process mDhcpView; - sDhcpTReady <= sDhcpSlave.tReady; + sDhcpTReady <= sDhcpSlave.tReady; mDhcpSlave.tReady <= mDhcpTReady; U_DUT : entity surf.UdpEngineDhcp diff --git a/ethernet/UdpEngine/wrappers/UdpEngineRxFlatWrapper.vhd b/ethernet/UdpEngine/wrappers/UdpEngineRxFlatWrapper.vhd index ac5369e5f1..0bda568786 100644 --- a/ethernet/UdpEngine/wrappers/UdpEngineRxFlatWrapper.vhd +++ b/ethernet/UdpEngine/wrappers/UdpEngineRxFlatWrapper.vhd @@ -71,8 +71,8 @@ end entity UdpEngineRxFlatWrapper; architecture rtl of UdpEngineRxFlatWrapper is signal igmpIpArray : Slv32Array(0 downto 0); - signal sUdpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sUdpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal sUdpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sUdpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; signal serverRemotePortA : Slv16Array(0 downto 0); signal serverRemoteIpA : Slv32Array(0 downto 0); signal serverRemoteMacA : Slv48Array(0 downto 0); @@ -82,67 +82,68 @@ architecture rtl of UdpEngineRxFlatWrapper is signal mServerSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); signal mClientMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); signal mClientSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal mDhcpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mDhcpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mDhcpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mDhcpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; begin - sUdpComb : process (sUdpEofe, sUdpSof, sUdpTData, sUdpTKeep, sUdpTLast, sUdpTValid) is + sUdpComb : process (sUdpEofe, sUdpSof, sUdpTData, sUdpTKeep, sUdpTLast, + sUdpTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sUdpTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sUdpTValid; v.tData(127 downto 0) := sUdpTData; - v.tKeep(15 downto 0) := sUdpTKeep; - v.tLast := sUdpTLast; + v.tKeep(15 downto 0) := sUdpTKeep; + v.tLast := sUdpTLast; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sUdpSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sUdpEofe); - sUdpMaster <= v; + sUdpMaster <= v; end process sUdpComb; - mServerView : process (mServerMasters(0)) is + mServerView : process (mServerMasters) is begin mServerTValid <= mServerMasters(0).tValid; - mServerTData <= mServerMasters(0).tData(127 downto 0); - mServerTKeep <= mServerMasters(0).tKeep(15 downto 0); - mServerTLast <= mServerMasters(0).tLast; - mServerTDest <= mServerMasters(0).tDest(7 downto 0); - mServerSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_SOF_BIT_C, 0); - mServerEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_EOFE_BIT_C); + mServerTData <= mServerMasters(0).tData(127 downto 0); + mServerTKeep <= mServerMasters(0).tKeep(15 downto 0); + mServerTLast <= mServerMasters(0).tLast; + mServerTDest <= mServerMasters(0).tDest(7 downto 0); + mServerSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_SOF_BIT_C, 0); + mServerEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_EOFE_BIT_C); end process mServerView; - mClientView : process (mClientMasters(0)) is + mClientView : process (mClientMasters) is begin mClientTValid <= mClientMasters(0).tValid; - mClientTData <= mClientMasters(0).tData(127 downto 0); - mClientTKeep <= mClientMasters(0).tKeep(15 downto 0); - mClientTLast <= mClientMasters(0).tLast; - mClientTDest <= mClientMasters(0).tDest(7 downto 0); - mClientSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mClientMasters(0), EMAC_SOF_BIT_C, 0); - mClientEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mClientMasters(0), EMAC_EOFE_BIT_C); + mClientTData <= mClientMasters(0).tData(127 downto 0); + mClientTKeep <= mClientMasters(0).tKeep(15 downto 0); + mClientTLast <= mClientMasters(0).tLast; + mClientTDest <= mClientMasters(0).tDest(7 downto 0); + mClientSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mClientMasters(0), EMAC_SOF_BIT_C, 0); + mClientEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mClientMasters(0), EMAC_EOFE_BIT_C); end process mClientView; mDhcpView : process (mDhcpMaster) is begin mDhcpTValid <= mDhcpMaster.tValid; - mDhcpTData <= mDhcpMaster.tData(127 downto 0); - mDhcpTKeep <= mDhcpMaster.tKeep(15 downto 0); - mDhcpTLast <= mDhcpMaster.tLast; - mDhcpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mDhcpMaster, EMAC_SOF_BIT_C, 0); - mDhcpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mDhcpMaster, EMAC_EOFE_BIT_C); + mDhcpTData <= mDhcpMaster.tData(127 downto 0); + mDhcpTKeep <= mDhcpMaster.tKeep(15 downto 0); + mDhcpTLast <= mDhcpMaster.tLast; + mDhcpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mDhcpMaster, EMAC_SOF_BIT_C, 0); + mDhcpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mDhcpMaster, EMAC_EOFE_BIT_C); end process mDhcpView; - sUdpTReady <= sUdpSlave.tReady; + sUdpTReady <= sUdpSlave.tReady; mServerSlaves(0).tReady <= mServerTReady; mClientSlaves(0).tReady <= mClientTReady; - mDhcpSlave.tReady <= mDhcpTReady; + mDhcpSlave.tReady <= mDhcpTReady; - igmpIpArray(0) <= igmpIp; - serverRemotePort <= serverRemotePortA(0); - serverRemoteIp <= serverRemoteIpA(0); - serverRemoteMac <= serverRemoteMacA(0); + igmpIpArray(0) <= igmpIp; + serverRemotePort <= serverRemotePortA(0); + serverRemoteIp <= serverRemoteIpA(0); + serverRemoteMac <= serverRemoteMacA(0); clientRemoteDetValid <= clientRemoteDetVA(0); - clientRemoteDetIp <= clientRemoteDetIA(0); + clientRemoteDetIp <= clientRemoteDetIA(0); U_DUT : entity surf.UdpEngineRx generic map ( diff --git a/ethernet/UdpEngine/wrappers/UdpEngineTopFlatWrapper.vhd b/ethernet/UdpEngine/wrappers/UdpEngineTopFlatWrapper.vhd index 7e153392c7..1e7aef0ede 100644 --- a/ethernet/UdpEngine/wrappers/UdpEngineTopFlatWrapper.vhd +++ b/ethernet/UdpEngine/wrappers/UdpEngineTopFlatWrapper.vhd @@ -100,134 +100,138 @@ end entity UdpEngineTopFlatWrapper; architecture rtl of UdpEngineTopFlatWrapper is - signal igmpIp : Slv32Array(0 downto 0) := (others => (others => '0')); + signal igmpIp : Slv32Array(0 downto 0) := (others => (others => '0')); signal clientRemotePortA : Slv16Array(0 downto 0); signal clientRemoteIpA : Slv32Array(0 downto 0); - signal sUdpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sUdpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal mUdpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mUdpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal arpReqMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal arpReqSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal arpAckMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal arpAckSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal sServerMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal sServerSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal mServerMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal mServerSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal sClientMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal sClientSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal mClientMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal mClientSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal sUdpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sUdpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mUdpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mUdpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal arpReqMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal arpReqSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal arpAckMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal arpAckSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal sServerMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal sServerSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal mServerMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal mServerSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal sClientMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal sClientSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal mClientMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal mClientSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); begin clientRemotePortA(0) <= clientRemotePort; - clientRemoteIpA(0) <= clientRemoteIp; + clientRemoteIpA(0) <= clientRemoteIp; - sUdpComb : process (sUdpEofe, sUdpSof, sUdpTData, sUdpTKeep, sUdpTLast, sUdpTValid) is + sUdpComb : process (sUdpEofe, sUdpSof, sUdpTData, sUdpTKeep, sUdpTLast, + sUdpTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sUdpTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sUdpTValid; v.tData(127 downto 0) := sUdpTData; - v.tKeep(15 downto 0) := sUdpTKeep; - v.tLast := sUdpTLast; + v.tKeep(15 downto 0) := sUdpTKeep; + v.tLast := sUdpTLast; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sUdpSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sUdpEofe); - sUdpMaster <= v; + sUdpMaster <= v; end process sUdpComb; - sServerComb : process (sServerEofe, sServerSof, sServerTData, sServerTDest, sServerTKeep, sServerTLast, sServerTValid) is + sServerComb : process (sServerEofe, sServerSof, sServerTData, sServerTDest, + sServerTKeep, sServerTLast, sServerTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sServerTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sServerTValid; v.tData(127 downto 0) := sServerTData; - v.tKeep(15 downto 0) := sServerTKeep; - v.tLast := sServerTLast; - v.tDest(7 downto 0) := sServerTDest; + v.tKeep(15 downto 0) := sServerTKeep; + v.tLast := sServerTLast; + v.tDest(7 downto 0) := sServerTDest; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sServerSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sServerEofe); - sServerMasters(0) <= v; + sServerMasters(0) <= v; end process sServerComb; - sClientComb : process (sClientEofe, sClientSof, sClientTData, sClientTDest, sClientTKeep, sClientTLast, sClientTValid) is + sClientComb : process (sClientEofe, sClientSof, sClientTData, sClientTDest, + sClientTKeep, sClientTLast, sClientTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sClientTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sClientTValid; v.tData(127 downto 0) := sClientTData; - v.tKeep(15 downto 0) := sClientTKeep; - v.tLast := sClientTLast; - v.tDest(7 downto 0) := sClientTDest; + v.tKeep(15 downto 0) := sClientTKeep; + v.tLast := sClientTLast; + v.tDest(7 downto 0) := sClientTDest; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sClientSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sClientEofe); - sClientMasters(0) <= v; + sClientMasters(0) <= v; end process sClientComb; - arpAckComb : process (arpAckEofe, arpAckSof, arpAckTData, arpAckTKeep, arpAckTLast, arpAckTValid) is + arpAckComb : process (arpAckEofe, arpAckSof, arpAckTData, arpAckTKeep, + arpAckTLast, arpAckTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := arpAckTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := arpAckTValid; v.tData(127 downto 0) := arpAckTData; - v.tKeep(15 downto 0) := arpAckTKeep; - v.tLast := arpAckTLast; + v.tKeep(15 downto 0) := arpAckTKeep; + v.tLast := arpAckTLast; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, arpAckSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, arpAckEofe); - arpAckMasters(0) <= v; + arpAckMasters(0) <= v; end process arpAckComb; mUdpView : process (mUdpMaster) is begin mUdpTValid <= mUdpMaster.tValid; - mUdpTData <= mUdpMaster.tData(127 downto 0); - mUdpTKeep <= mUdpMaster.tKeep(15 downto 0); - mUdpTLast <= mUdpMaster.tLast; - mUdpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mUdpMaster, EMAC_SOF_BIT_C, 0); - mUdpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mUdpMaster, EMAC_EOFE_BIT_C); + mUdpTData <= mUdpMaster.tData(127 downto 0); + mUdpTKeep <= mUdpMaster.tKeep(15 downto 0); + mUdpTLast <= mUdpMaster.tLast; + mUdpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mUdpMaster, EMAC_SOF_BIT_C, 0); + mUdpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mUdpMaster, EMAC_EOFE_BIT_C); end process mUdpView; - arpReqView : process (arpReqMasters(0)) is + arpReqView : process (arpReqMasters) is begin arpReqTValid <= arpReqMasters(0).tValid; - arpReqTData <= arpReqMasters(0).tData(127 downto 0); - arpReqTKeep <= arpReqMasters(0).tKeep(15 downto 0); - arpReqTLast <= arpReqMasters(0).tLast; - arpReqSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, arpReqMasters(0), EMAC_SOF_BIT_C, 0); - arpReqEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, arpReqMasters(0), EMAC_EOFE_BIT_C); + arpReqTData <= arpReqMasters(0).tData(127 downto 0); + arpReqTKeep <= arpReqMasters(0).tKeep(15 downto 0); + arpReqTLast <= arpReqMasters(0).tLast; + arpReqSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, arpReqMasters(0), EMAC_SOF_BIT_C, 0); + arpReqEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, arpReqMasters(0), EMAC_EOFE_BIT_C); end process arpReqView; - mServerView : process (mServerMasters(0)) is + mServerView : process (mServerMasters) is begin mServerTValid <= mServerMasters(0).tValid; - mServerTData <= mServerMasters(0).tData(127 downto 0); - mServerTKeep <= mServerMasters(0).tKeep(15 downto 0); - mServerTLast <= mServerMasters(0).tLast; - mServerTDest <= mServerMasters(0).tDest(7 downto 0); - mServerSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_SOF_BIT_C, 0); - mServerEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_EOFE_BIT_C); + mServerTData <= mServerMasters(0).tData(127 downto 0); + mServerTKeep <= mServerMasters(0).tKeep(15 downto 0); + mServerTLast <= mServerMasters(0).tLast; + mServerTDest <= mServerMasters(0).tDest(7 downto 0); + mServerSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_SOF_BIT_C, 0); + mServerEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_EOFE_BIT_C); end process mServerView; - mClientView : process (mClientMasters(0)) is + mClientView : process (mClientMasters) is begin mClientTValid <= mClientMasters(0).tValid; - mClientTData <= mClientMasters(0).tData(127 downto 0); - mClientTKeep <= mClientMasters(0).tKeep(15 downto 0); - mClientTLast <= mClientMasters(0).tLast; - mClientTDest <= mClientMasters(0).tDest(7 downto 0); - mClientSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mClientMasters(0), EMAC_SOF_BIT_C, 0); - mClientEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mClientMasters(0), EMAC_EOFE_BIT_C); + mClientTData <= mClientMasters(0).tData(127 downto 0); + mClientTKeep <= mClientMasters(0).tKeep(15 downto 0); + mClientTLast <= mClientMasters(0).tLast; + mClientTDest <= mClientMasters(0).tDest(7 downto 0); + mClientSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mClientMasters(0), EMAC_SOF_BIT_C, 0); + mClientEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mClientMasters(0), EMAC_EOFE_BIT_C); end process mClientView; - sUdpTReady <= sUdpSlave.tReady; - mUdpSlave.tReady <= mUdpTReady; - arpReqSlaves(0).tReady <= arpReqTReady; - arpAckTReady <= arpAckSlaves(0).tReady; - sServerTReady <= sServerSlaves(0).tReady; + sUdpTReady <= sUdpSlave.tReady; + mUdpSlave.tReady <= mUdpTReady; + arpReqSlaves(0).tReady <= arpReqTReady; + arpAckTReady <= arpAckSlaves(0).tReady; + sServerTReady <= sServerSlaves(0).tReady; mServerSlaves(0).tReady <= mServerTReady; - sClientTReady <= sClientSlaves(0).tReady; + sClientTReady <= sClientSlaves(0).tReady; mClientSlaves(0).tReady <= mClientTReady; U_DUT : entity surf.UdpEngine diff --git a/ethernet/UdpEngine/wrappers/UdpEngineTxFlatWrapper.vhd b/ethernet/UdpEngine/wrappers/UdpEngineTxFlatWrapper.vhd index 1af3526797..659c1aca00 100644 --- a/ethernet/UdpEngine/wrappers/UdpEngineTxFlatWrapper.vhd +++ b/ethernet/UdpEngine/wrappers/UdpEngineTxFlatWrapper.vhd @@ -75,61 +75,63 @@ architecture rtl of UdpEngineTxFlatWrapper is signal arpTabIpAddrA : Slv32Array(0 downto 0); signal arpTabMacA : Slv48Array(0 downto 0); signal linkUpA : slv(0 downto 0); - signal sDhcpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sDhcpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal mUdpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mUdpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal sDhcpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sDhcpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mUdpMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mUdpSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; begin - sAppComb : process (sAppEofe, sAppSof, sAppTData, sAppTDest, sAppTKeep, sAppTLast, sAppTValid) is + sAppComb : process (sAppEofe, sAppSof, sAppTData, sAppTDest, sAppTKeep, + sAppTLast, sAppTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAppTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAppTValid; v.tData(127 downto 0) := sAppTData; - v.tKeep(15 downto 0) := sAppTKeep; - v.tLast := sAppTLast; - v.tDest(7 downto 0) := sAppTDest; + v.tKeep(15 downto 0) := sAppTKeep; + v.tLast := sAppTLast; + v.tDest(7 downto 0) := sAppTDest; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sAppSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sAppEofe); - sAppMasters(0) <= v; + sAppMasters(0) <= v; end process sAppComb; - sDhcpComb : process (sDhcpEofe, sDhcpSof, sDhcpTData, sDhcpTKeep, sDhcpTLast, sDhcpTValid) is + sDhcpComb : process (sDhcpEofe, sDhcpSof, sDhcpTData, sDhcpTKeep, + sDhcpTLast, sDhcpTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sDhcpTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sDhcpTValid; v.tData(127 downto 0) := sDhcpTData; - v.tKeep(15 downto 0) := sDhcpTKeep; - v.tLast := sDhcpTLast; + v.tKeep(15 downto 0) := sDhcpTKeep; + v.tLast := sDhcpTLast; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sDhcpSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sDhcpEofe); - sDhcpMaster <= v; + sDhcpMaster <= v; end process sDhcpComb; mUdpView : process (mUdpMaster) is begin mUdpTValid <= mUdpMaster.tValid; - mUdpTData <= mUdpMaster.tData(127 downto 0); - mUdpTKeep <= mUdpMaster.tKeep(15 downto 0); - mUdpTLast <= mUdpMaster.tLast; - mUdpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mUdpMaster, EMAC_SOF_BIT_C, 0); - mUdpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mUdpMaster, EMAC_EOFE_BIT_C); + mUdpTData <= mUdpMaster.tData(127 downto 0); + mUdpTKeep <= mUdpMaster.tKeep(15 downto 0); + mUdpTLast <= mUdpMaster.tLast; + mUdpSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mUdpMaster, EMAC_SOF_BIT_C, 0); + mUdpEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mUdpMaster, EMAC_EOFE_BIT_C); end process mUdpView; - sAppTReady <= sAppSlaves(0).tReady; - sDhcpTReady <= sDhcpSlave.tReady; + sAppTReady <= sAppSlaves(0).tReady; + sDhcpTReady <= sDhcpSlave.tReady; mUdpSlave.tReady <= mUdpTReady; - linkUp <= linkUpA(0); - arpTabPos <= arpTabPosA(0); - remotePortA(0) <= remotePort; - remoteIpA(0) <= remoteIp; - remoteMacA(0) <= remoteMac; + linkUp <= linkUpA(0); + arpTabPos <= arpTabPosA(0); + remotePortA(0) <= remotePort; + remoteIpA(0) <= remoteIp; + remoteMacA(0) <= remoteMac; arpTabIpAddrA(0) <= arpTabIpAddr; - arpTabMacA(0) <= arpTabMacAddr; + arpTabMacA(0) <= arpTabMacAddr; U_DUT : entity surf.UdpEngineTx generic map ( @@ -141,23 +143,23 @@ begin IS_CLIENT_G => IS_CLIENT_G, PORT_G => (0 => PORT_G_VALUE)) port map ( - obUdpMaster => mUdpMaster, - obUdpSlave => mUdpSlave, - linkUp => linkUpA, - localMac => localMac, - localIp => localIp, - remotePort => remotePortA, - remoteIp => remoteIpA, - remoteMac => remoteMacA, - ibMasters => sAppMasters, - ibSlaves => sAppSlaves, - arpTabPos => arpTabPosA, - arpTabFound(0) => arpTabFound, - arpTabIpAddr => arpTabIpAddrA, - arpTabMacAddr => arpTabMacA, - obDhcpMaster => sDhcpMaster, - obDhcpSlave => sDhcpSlave, - clk => clk, - rst => rst); + obUdpMaster => mUdpMaster, + obUdpSlave => mUdpSlave, + linkUp => linkUpA, + localMac => localMac, + localIp => localIp, + remotePort => remotePortA, + remoteIp => remoteIpA, + remoteMac => remoteMacA, + ibMasters => sAppMasters, + ibSlaves => sAppSlaves, + arpTabPos => arpTabPosA, + arpTabFound(0) => arpTabFound, + arpTabIpAddr => arpTabIpAddrA, + arpTabMacAddr => arpTabMacA, + obDhcpMaster => sDhcpMaster, + obDhcpSlave => sDhcpSlave, + clk => clk, + rst => rst); end architecture rtl; diff --git a/ethernet/UdpEngine/wrappers/UdpEngineWrapperFlatWrapper.vhd b/ethernet/UdpEngine/wrappers/UdpEngineWrapperFlatWrapper.vhd index 2a3126d03b..d9ebae0ff2 100644 --- a/ethernet/UdpEngine/wrappers/UdpEngineWrapperFlatWrapper.vhd +++ b/ethernet/UdpEngine/wrappers/UdpEngineWrapperFlatWrapper.vhd @@ -29,171 +29,174 @@ entity UdpEngineWrapperFlatWrapper is CLK_FREQ_G : real := 4.0; COMM_TIMEOUT_G : positive := 6); port ( - clk : in sl; - rst : in sl; - localMac : in slv(47 downto 0); - localIp : in slv(31 downto 0); - softMac : out slv(47 downto 0); - softIp : out slv(31 downto 0); - sMacTValid : in sl; - sMacTData : in slv(127 downto 0); - sMacTKeep : in slv(15 downto 0); - sMacTLast : in sl; - sMacTReady : out sl; - sMacSof : in sl; - sMacEofe : in sl; - mMacTValid : out sl; - mMacTData : out slv(127 downto 0); - mMacTKeep : out slv(15 downto 0); - mMacTLast : out sl; - mMacTReady : in sl := '1'; - mMacSof : out sl; - mMacEofe : out sl; - sServerTValid : in sl; - sServerTData : in slv(127 downto 0); - sServerTKeep : in slv(15 downto 0); - sServerTLast : in sl; - sServerTReady : out sl; - sServerTDest : in slv(7 downto 0); - sServerSof : in sl; - sServerEofe : in sl; - mServerTValid : out sl; - mServerTData : out slv(127 downto 0); - mServerTKeep : out slv(15 downto 0); - mServerTLast : out sl; - mServerTReady : in sl := '1'; - mServerTDest : out slv(7 downto 0); - mServerSof : out sl; - mServerEofe : out sl; - sClientTValid : in sl; - sClientTData : in slv(127 downto 0); - sClientTKeep : in slv(15 downto 0); - sClientTLast : in sl; - sClientTReady : out sl; - sClientTDest : in slv(7 downto 0); - sClientSof : in sl; - sClientEofe : in sl; - mClientTValid : out sl; - mClientTData : out slv(127 downto 0); - mClientTKeep : out slv(15 downto 0); - mClientTLast : out sl; - mClientTReady : in sl := '1'; - mClientTDest : out slv(7 downto 0); - mClientSof : out sl; - mClientEofe : out sl; - S_AXI_AWADDR : in slv(31 downto 0); - S_AXI_AWPROT : in slv(2 downto 0); - S_AXI_AWVALID : in sl; - S_AXI_AWREADY : out sl; - S_AXI_WDATA : in slv(31 downto 0); - S_AXI_WSTRB : in slv(3 downto 0); - S_AXI_WVALID : in sl; - S_AXI_WREADY : out sl; - S_AXI_BRESP : out slv(1 downto 0); - S_AXI_BVALID : out sl; - S_AXI_BREADY : in sl; - S_AXI_ARADDR : in slv(31 downto 0); - S_AXI_ARPROT : in slv(2 downto 0); - S_AXI_ARVALID : in sl; - S_AXI_ARREADY : out sl; - S_AXI_RDATA : out slv(31 downto 0); - S_AXI_RRESP : out slv(1 downto 0); - S_AXI_RVALID : out sl; - S_AXI_RREADY : in sl); + clk : in sl; + rst : in sl; + localMac : in slv(47 downto 0); + localIp : in slv(31 downto 0); + softMac : out slv(47 downto 0); + softIp : out slv(31 downto 0); + sMacTValid : in sl; + sMacTData : in slv(127 downto 0); + sMacTKeep : in slv(15 downto 0); + sMacTLast : in sl; + sMacTReady : out sl; + sMacSof : in sl; + sMacEofe : in sl; + mMacTValid : out sl; + mMacTData : out slv(127 downto 0); + mMacTKeep : out slv(15 downto 0); + mMacTLast : out sl; + mMacTReady : in sl := '1'; + mMacSof : out sl; + mMacEofe : out sl; + sServerTValid : in sl; + sServerTData : in slv(127 downto 0); + sServerTKeep : in slv(15 downto 0); + sServerTLast : in sl; + sServerTReady : out sl; + sServerTDest : in slv(7 downto 0); + sServerSof : in sl; + sServerEofe : in sl; + mServerTValid : out sl; + mServerTData : out slv(127 downto 0); + mServerTKeep : out slv(15 downto 0); + mServerTLast : out sl; + mServerTReady : in sl := '1'; + mServerTDest : out slv(7 downto 0); + mServerSof : out sl; + mServerEofe : out sl; + sClientTValid : in sl; + sClientTData : in slv(127 downto 0); + sClientTKeep : in slv(15 downto 0); + sClientTLast : in sl; + sClientTReady : out sl; + sClientTDest : in slv(7 downto 0); + sClientSof : in sl; + sClientEofe : in sl; + mClientTValid : out sl; + mClientTData : out slv(127 downto 0); + mClientTKeep : out slv(15 downto 0); + mClientTLast : out sl; + mClientTReady : in sl := '1'; + mClientTDest : out slv(7 downto 0); + mClientSof : out sl; + mClientEofe : out sl; + S_AXI_AWADDR : in slv(31 downto 0); + S_AXI_AWPROT : in slv(2 downto 0); + S_AXI_AWVALID : in sl; + S_AXI_AWREADY : out sl; + S_AXI_WDATA : in slv(31 downto 0); + S_AXI_WSTRB : in slv(3 downto 0); + S_AXI_WVALID : in sl; + S_AXI_WREADY : out sl; + S_AXI_BRESP : out slv(1 downto 0); + S_AXI_BVALID : out sl; + S_AXI_BREADY : in sl; + S_AXI_ARADDR : in slv(31 downto 0); + S_AXI_ARPROT : in slv(2 downto 0); + S_AXI_ARVALID : in sl; + S_AXI_ARREADY : out sl; + S_AXI_RDATA : out slv(31 downto 0); + S_AXI_RRESP : out slv(1 downto 0); + S_AXI_RVALID : out sl; + S_AXI_RREADY : in sl); end entity UdpEngineWrapperFlatWrapper; architecture rtl of UdpEngineWrapperFlatWrapper is - signal sMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal mMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; - signal sServerMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal sServerSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal mServerMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal mServerSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal sClientMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal sClientSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal mClientMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal mClientSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); - signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; - signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; - signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; - signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + signal sMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mMacMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mMacSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal sServerMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal sServerSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal mServerMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal mServerSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal sClientMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal sClientSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal mClientMasters : AxiStreamMasterArray(0 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal mClientSlaves : AxiStreamSlaveArray(0 downto 0) := (others => AXI_STREAM_SLAVE_INIT_C); + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; begin - sMacComb : process (sMacEofe, sMacSof, sMacTData, sMacTKeep, sMacTLast, sMacTValid) is + sMacComb : process (sMacEofe, sMacSof, sMacTData, sMacTKeep, sMacTLast, + sMacTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sMacTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sMacTValid; v.tData(127 downto 0) := sMacTData; - v.tKeep(15 downto 0) := sMacTKeep; - v.tLast := sMacTLast; + v.tKeep(15 downto 0) := sMacTKeep; + v.tLast := sMacTLast; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sMacSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sMacEofe); - sMacMaster <= v; + sMacMaster <= v; end process sMacComb; - sServerComb : process (sServerEofe, sServerSof, sServerTData, sServerTDest, sServerTKeep, sServerTLast, sServerTValid) is + sServerComb : process (sServerEofe, sServerSof, sServerTData, sServerTDest, + sServerTKeep, sServerTLast, sServerTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sServerTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sServerTValid; v.tData(127 downto 0) := sServerTData; - v.tKeep(15 downto 0) := sServerTKeep; - v.tLast := sServerTLast; - v.tDest(7 downto 0) := sServerTDest; + v.tKeep(15 downto 0) := sServerTKeep; + v.tLast := sServerTLast; + v.tDest(7 downto 0) := sServerTDest; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sServerSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sServerEofe); - sServerMasters(0) <= v; + sServerMasters(0) <= v; end process sServerComb; - sClientComb : process (sClientEofe, sClientSof, sClientTData, sClientTDest, sClientTKeep, sClientTLast, sClientTValid) is + sClientComb : process (sClientEofe, sClientSof, sClientTData, sClientTDest, + sClientTKeep, sClientTLast, sClientTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sClientTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sClientTValid; v.tData(127 downto 0) := sClientTData; - v.tKeep(15 downto 0) := sClientTKeep; - v.tLast := sClientTLast; - v.tDest(7 downto 0) := sClientTDest; + v.tKeep(15 downto 0) := sClientTKeep; + v.tLast := sClientTLast; + v.tDest(7 downto 0) := sClientTDest; axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_SOF_BIT_C, sClientSof, 0); axiStreamSetUserBit(EMAC_AXIS_CONFIG_C, v, EMAC_EOFE_BIT_C, sClientEofe); - sClientMasters(0) <= v; + sClientMasters(0) <= v; end process sClientComb; mMacView : process (mMacMaster) is begin mMacTValid <= mMacMaster.tValid; - mMacTData <= mMacMaster.tData(127 downto 0); - mMacTKeep <= mMacMaster.tKeep(15 downto 0); - mMacTLast <= mMacMaster.tLast; - mMacSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mMacMaster, EMAC_SOF_BIT_C, 0); - mMacEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mMacMaster, EMAC_EOFE_BIT_C); + mMacTData <= mMacMaster.tData(127 downto 0); + mMacTKeep <= mMacMaster.tKeep(15 downto 0); + mMacTLast <= mMacMaster.tLast; + mMacSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mMacMaster, EMAC_SOF_BIT_C, 0); + mMacEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mMacMaster, EMAC_EOFE_BIT_C); end process mMacView; - mServerView : process (mServerMasters(0)) is + mServerView : process (mServerMasters) is begin mServerTValid <= mServerMasters(0).tValid; - mServerTData <= mServerMasters(0).tData(127 downto 0); - mServerTKeep <= mServerMasters(0).tKeep(15 downto 0); - mServerTLast <= mServerMasters(0).tLast; - mServerTDest <= mServerMasters(0).tDest(7 downto 0); - mServerSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_SOF_BIT_C, 0); - mServerEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_EOFE_BIT_C); + mServerTData <= mServerMasters(0).tData(127 downto 0); + mServerTKeep <= mServerMasters(0).tKeep(15 downto 0); + mServerTLast <= mServerMasters(0).tLast; + mServerTDest <= mServerMasters(0).tDest(7 downto 0); + mServerSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_SOF_BIT_C, 0); + mServerEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mServerMasters(0), EMAC_EOFE_BIT_C); end process mServerView; - mClientView : process (mClientMasters(0)) is + mClientView : process (mClientMasters) is begin mClientTValid <= mClientMasters(0).tValid; - mClientTData <= mClientMasters(0).tData(127 downto 0); - mClientTKeep <= mClientMasters(0).tKeep(15 downto 0); - mClientTLast <= mClientMasters(0).tLast; - mClientTDest <= mClientMasters(0).tDest(7 downto 0); - mClientSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mClientMasters(0), EMAC_SOF_BIT_C, 0); - mClientEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mClientMasters(0), EMAC_EOFE_BIT_C); + mClientTData <= mClientMasters(0).tData(127 downto 0); + mClientTKeep <= mClientMasters(0).tKeep(15 downto 0); + mClientTLast <= mClientMasters(0).tLast; + mClientTDest <= mClientMasters(0).tDest(7 downto 0); + mClientSof <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mClientMasters(0), EMAC_SOF_BIT_C, 0); + mClientEofe <= axiStreamGetUserBit(EMAC_AXIS_CONFIG_C, mClientMasters(0), EMAC_EOFE_BIT_C); end process mClientView; axilWriteMaster.awaddr <= S_AXI_AWADDR; @@ -209,19 +212,19 @@ begin axilReadMaster.rready <= S_AXI_RREADY; S_AXI_AWREADY <= axilWriteSlave.awready; - S_AXI_WREADY <= axilWriteSlave.wready; - S_AXI_BRESP <= axilWriteSlave.bresp; - S_AXI_BVALID <= axilWriteSlave.bvalid; + S_AXI_WREADY <= axilWriteSlave.wready; + S_AXI_BRESP <= axilWriteSlave.bresp; + S_AXI_BVALID <= axilWriteSlave.bvalid; S_AXI_ARREADY <= axilReadSlave.arready; - S_AXI_RDATA <= axilReadSlave.rdata; - S_AXI_RRESP <= axilReadSlave.rresp; - S_AXI_RVALID <= axilReadSlave.rvalid; + S_AXI_RDATA <= axilReadSlave.rdata; + S_AXI_RRESP <= axilReadSlave.rresp; + S_AXI_RVALID <= axilReadSlave.rvalid; - sMacTReady <= sMacSlave.tReady; - mMacSlave.tReady <= mMacTReady; - sServerTReady <= sServerSlaves(0).tReady; + sMacTReady <= sMacSlave.tReady; + mMacSlave.tReady <= mMacTReady; + sServerTReady <= sServerSlaves(0).tReady; mServerSlaves(0).tReady <= mServerTReady; - sClientTReady <= sClientSlaves(0).tReady; + sClientTReady <= sClientSlaves(0).tReady; mClientSlaves(0).tReady <= mClientTReady; U_DUT : entity surf.UdpEngineWrapper @@ -243,27 +246,27 @@ begin CLK_FREQ_G => CLK_FREQ_G, COMM_TIMEOUT_G => COMM_TIMEOUT_G) port map ( - localMac => localMac, - localIp => localIp, - softMac => softMac, - softIp => softIp, - obMacMaster => sMacMaster, - obMacSlave => sMacSlave, - ibMacMaster => mMacMaster, - ibMacSlave => mMacSlave, - obServerMasters => mServerMasters, - obServerSlaves => mServerSlaves, - ibServerMasters => sServerMasters, - ibServerSlaves => sServerSlaves, - obClientMasters => mClientMasters, - obClientSlaves => mClientSlaves, - ibClientMasters => sClientMasters, - ibClientSlaves => sClientSlaves, - axilReadMaster => axilReadMaster, - axilReadSlave => axilReadSlave, - axilWriteMaster => axilWriteMaster, - axilWriteSlave => axilWriteSlave, - clk => clk, - rst => rst); + localMac => localMac, + localIp => localIp, + softMac => softMac, + softIp => softIp, + obMacMaster => sMacMaster, + obMacSlave => sMacSlave, + ibMacMaster => mMacMaster, + ibMacSlave => mMacSlave, + obServerMasters => mServerMasters, + obServerSlaves => mServerSlaves, + ibServerMasters => sServerMasters, + ibServerSlaves => sServerSlaves, + obClientMasters => mClientMasters, + obClientSlaves => mClientSlaves, + ibClientMasters => sClientMasters, + ibClientSlaves => sClientSlaves, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave, + clk => clk, + rst => rst); end architecture rtl; diff --git a/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd b/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd index 090c14150a..dab02080f5 100644 --- a/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd +++ b/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd @@ -289,7 +289,7 @@ begin -- Starting point for next cycle IDLE state if (i /= NUM_LANES_G-1) then - v.wrd := i+1; + v.wrd := i+1; end if; end if; diff --git a/protocols/event-frame-sequencer/wrappers/EventFrameSequencerWrapper.vhd b/protocols/event-frame-sequencer/wrappers/EventFrameSequencerWrapper.vhd index 03d21943f6..65582faa6a 100644 --- a/protocols/event-frame-sequencer/wrappers/EventFrameSequencerWrapper.vhd +++ b/protocols/event-frame-sequencer/wrappers/EventFrameSequencerWrapper.vhd @@ -103,22 +103,22 @@ architecture rtl of EventFrameSequencerWrapper is constant AXIL_CONFIG_C : AxiLiteCrossbarMasterConfigArray(1 downto 0) := genAxiLiteConfig(2, x"0000_0000", 20, 16); - signal axilReadMaster : AxiLiteReadMasterType; - signal axilReadSlave : AxiLiteReadSlaveType; - signal axilWriteMaster : AxiLiteWriteMasterType; - signal axilWriteSlave : AxiLiteWriteSlaveType; + signal axilReadMaster : AxiLiteReadMasterType; + signal axilReadSlave : AxiLiteReadSlaveType; + signal axilWriteMaster : AxiLiteWriteMasterType; + signal axilWriteSlave : AxiLiteWriteSlaveType; signal axilReadMasters : AxiLiteReadMasterArray(1 downto 0); signal axilReadSlaves : AxiLiteReadSlaveArray(1 downto 0); signal axilWriteMasters : AxiLiteWriteMasterArray(1 downto 0); signal axilWriteSlaves : AxiLiteWriteSlaveArray(1 downto 0); - signal axisClk : sl := '0'; - signal axisRst : sl := '0'; - signal sAxisMasters : AxiStreamMasterArray(1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal sAxisSlaves : AxiStreamSlaveArray(1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); - signal axisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal axisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal mAxisMasters : AxiStreamMasterArray(1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); - signal mAxisSlaves : AxiStreamSlaveArray(1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); + signal axisClk : sl := '0'; + signal axisRst : sl := '0'; + signal sAxisMasters : AxiStreamMasterArray(1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal sAxisSlaves : AxiStreamSlaveArray(1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); + signal axisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal axisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal mAxisMasters : AxiStreamMasterArray(1 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + signal mAxisSlaves : AxiStreamSlaveArray(1 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); begin @@ -319,9 +319,9 @@ begin U_Demux : entity surf.EventFrameSequencerDemux generic map ( - TPD_G => TPD_C, - NUM_MASTERS_G => 2, - AXIS_CONFIG_G => AXIS_CONFIG_C) + TPD_G => TPD_C, + NUM_MASTERS_G => 2, + AXIS_CONFIG_G => AXIS_CONFIG_C) port map ( axisClk => axisClk, axisRst => axisRst, diff --git a/protocols/hamming-ecc/wrappers/HammingEccWrapper.vhd b/protocols/hamming-ecc/wrappers/HammingEccWrapper.vhd index 5ec1a8d9b1..d7d7129912 100644 --- a/protocols/hamming-ecc/wrappers/HammingEccWrapper.vhd +++ b/protocols/hamming-ecc/wrappers/HammingEccWrapper.vhd @@ -39,7 +39,7 @@ architecture rtl of HammingEccWrapper is constant ENC_WIDTH_C : positive := hammingEccDataWidth(DATA_WIDTH_G); - signal encValid : sl := '0'; + signal encValid : sl := '0'; signal encData : slv(ENC_WIDTH_C downto 0) := (others => '0'); signal encDataMask : slv(ENC_WIDTH_C downto 0) := (others => '0'); diff --git a/protocols/line-codes/rtl/Code12b14bPkg.vhd b/protocols/line-codes/rtl/Code12b14bPkg.vhd index fdec01c36b..05a3520191 100644 --- a/protocols/line-codes/rtl/Code12b14bPkg.vhd +++ b/protocols/line-codes/rtl/Code12b14bPkg.vhd @@ -448,7 +448,7 @@ package body Code12b14bPkg is variable data6 : slv(5 downto 0); variable blockDisp56 : BlockDisparityType; - variable debug : boolean := false; + variable debug : boolean := false; variable tmpDisp : integer range -8 to 8 := 0; variable compliment : sl; begin diff --git a/protocols/line-codes/wrappers/Code10b12bPkgWrapper.vhd b/protocols/line-codes/wrappers/Code10b12bPkgWrapper.vhd index dbb551da9b..444f6d87f3 100644 --- a/protocols/line-codes/wrappers/Code10b12bPkgWrapper.vhd +++ b/protocols/line-codes/wrappers/Code10b12bPkgWrapper.vhd @@ -43,7 +43,7 @@ begin -- Package-level encode/decode shim --------------------------------------------------------------------------- - comb : process (encDispIn, encDataIn, encDataKIn, decDispIn, decDataIn) is + comb : process (decDataIn, decDispIn, encDataIn, encDataKIn, encDispIn) is variable encodedDataVar : slv(11 downto 0); variable encodedDispVar : sl; variable decodedDataVar : slv(9 downto 0); diff --git a/protocols/line-codes/wrappers/Code12b14bPkgWrapper.vhd b/protocols/line-codes/wrappers/Code12b14bPkgWrapper.vhd index a865613d2a..10a3dad7fa 100644 --- a/protocols/line-codes/wrappers/Code12b14bPkgWrapper.vhd +++ b/protocols/line-codes/wrappers/Code12b14bPkgWrapper.vhd @@ -44,7 +44,7 @@ begin -- Package-level encode/decode shim --------------------------------------------------------------------------- - comb : process (encDispIn, encDataIn, encDataKIn, decDispIn, decDataIn) is + comb : process (decDataIn, decDispIn, encDataIn, encDataKIn, encDispIn) is variable encodedDataVar : slv(13 downto 0); variable encodedDispVar : slv(1 downto 0); variable invalidKVar : sl; diff --git a/protocols/line-codes/wrappers/Code8b10bPkgWrapper.vhd b/protocols/line-codes/wrappers/Code8b10bPkgWrapper.vhd index 0b71807273..94bc83bb72 100644 --- a/protocols/line-codes/wrappers/Code8b10bPkgWrapper.vhd +++ b/protocols/line-codes/wrappers/Code8b10bPkgWrapper.vhd @@ -42,7 +42,7 @@ begin --------------------------------------------------------------------------- -- Package-level encode/decode shim --------------------------------------------------------------------------- - comb : process (encDispIn, encDataIn, encDataKIn, decDispIn, decDataIn) is + comb : process (decDataIn, decDispIn, encDataIn, encDataKIn, encDispIn) is variable encodedDataVar : slv(9 downto 0); variable encodedDispVar : sl; variable decodedDataVar : slv(7 downto 0); diff --git a/protocols/pgp/pgp2b/core/wrappers/Pgp2bAxiWrapper.vhd b/protocols/pgp/pgp2b/core/wrappers/Pgp2bAxiWrapper.vhd index 0116c48557..a24bdde190 100644 --- a/protocols/pgp/pgp2b/core/wrappers/Pgp2bAxiWrapper.vhd +++ b/protocols/pgp/pgp2b/core/wrappers/Pgp2bAxiWrapper.vhd @@ -64,9 +64,9 @@ architecture rtl of Pgp2bAxiWrapper is signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; - signal pgpTxIn : Pgp2bTxInType := PGP2B_TX_IN_INIT_C; - signal pgpRxIn : Pgp2bRxInType := PGP2B_RX_IN_INIT_C; - signal locTxIn : Pgp2bTxInType := ( + signal pgpTxIn : Pgp2bTxInType := PGP2B_TX_IN_INIT_C; + signal pgpRxIn : Pgp2bRxInType := PGP2B_RX_IN_INIT_C; + signal locTxIn : Pgp2bTxInType := ( flush => '0', opCodeEn => '0', opCode => (others => '0'), diff --git a/protocols/pgp/pgp2b/core/wrappers/Pgp2bLaneWrapper.vhd b/protocols/pgp/pgp2b/core/wrappers/Pgp2bLaneWrapper.vhd index a62eb90c9f..8ec00b5de1 100644 --- a/protocols/pgp/pgp2b/core/wrappers/Pgp2bLaneWrapper.vhd +++ b/protocols/pgp/pgp2b/core/wrappers/Pgp2bLaneWrapper.vhd @@ -55,8 +55,8 @@ architecture rtl of Pgp2bLaneWrapper is signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal pgpTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal pgpTxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal pgpTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal pgpTxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; signal pgpTxMasters : AxiStreamMasterArray(3 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); signal pgpTxSlaves : AxiStreamSlaveArray(3 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); diff --git a/protocols/pgp/pgp2b/core/wrappers/Pgp2bRxCellWrapper.vhd b/protocols/pgp/pgp2b/core/wrappers/Pgp2bRxCellWrapper.vhd index 2ef571de3a..2ee654467b 100644 --- a/protocols/pgp/pgp2b/core/wrappers/Pgp2bRxCellWrapper.vhd +++ b/protocols/pgp/pgp2b/core/wrappers/Pgp2bRxCellWrapper.vhd @@ -44,22 +44,22 @@ begin generic map ( RX_LANE_CNT_G => 1) port map ( - pgpRxClk => clk, - pgpRxClkRst => rst, - pgpRxFlush => pgpRxFlush, - pgpRxLinkReady => pgpRxLinkReady, - cellRxPause => cellRxPause, - cellRxSOC => cellRxSOC, - cellRxSOF => cellRxSOF, - cellRxEOC => cellRxEOC, - cellRxEOF => cellRxEOF, - cellRxEOFE => cellRxEOFE, - cellRxData => cellRxData, - pgpRxCellError => pgpRxCellError, - vcFrameRxSOF => vcFrameRxSOF, - vcFrameRxEOF => vcFrameRxEOF, - vcFrameRxEOFE => vcFrameRxEOFE, - vcFrameRxData => vcFrameRxData, + pgpRxClk => clk, + pgpRxClkRst => rst, + pgpRxFlush => pgpRxFlush, + pgpRxLinkReady => pgpRxLinkReady, + cellRxPause => cellRxPause, + cellRxSOC => cellRxSOC, + cellRxSOF => cellRxSOF, + cellRxEOC => cellRxEOC, + cellRxEOF => cellRxEOF, + cellRxEOFE => cellRxEOFE, + cellRxData => cellRxData, + pgpRxCellError => pgpRxCellError, + vcFrameRxSOF => vcFrameRxSOF, + vcFrameRxEOF => vcFrameRxEOF, + vcFrameRxEOFE => vcFrameRxEOFE, + vcFrameRxData => vcFrameRxData, vc0FrameRxValid => vc0FrameRxValid, vc0RemAlmostFull => vc0RemAlmostFull, vc0RemOverflow => vc0RemOverflow, diff --git a/protocols/pgp/pgp2b/core/wrappers/Pgp2bRxPhyWrapper.vhd b/protocols/pgp/pgp2b/core/wrappers/Pgp2bRxPhyWrapper.vhd index e58711b351..ad932b721a 100644 --- a/protocols/pgp/pgp2b/core/wrappers/Pgp2bRxPhyWrapper.vhd +++ b/protocols/pgp/pgp2b/core/wrappers/Pgp2bRxPhyWrapper.vhd @@ -44,28 +44,28 @@ begin generic map ( RX_LANE_CNT_G => 1) port map ( - pgpRxClk => clk, - pgpRxClkRst => rst, - pgpRxLinkReady => pgpRxLinkReady, - pgpRxLinkDown => pgpRxLinkDown, - pgpRxLinkError => pgpRxLinkError, - pgpRxOpCodeEn => pgpRxOpCodeEn, - pgpRxOpCode => pgpRxOpCode, + pgpRxClk => clk, + pgpRxClkRst => rst, + pgpRxLinkReady => pgpRxLinkReady, + pgpRxLinkDown => pgpRxLinkDown, + pgpRxLinkError => pgpRxLinkError, + pgpRxOpCodeEn => pgpRxOpCodeEn, + pgpRxOpCode => pgpRxOpCode, pgpRemLinkReady => pgpRemLinkReady, - pgpRemData => pgpRemData, - cellRxPause => cellRxPause, - cellRxSOC => cellRxSOC, - cellRxSOF => cellRxSOF, - cellRxEOC => cellRxEOC, - cellRxEOF => cellRxEOF, - cellRxEOFE => cellRxEOFE, - cellRxData => cellRxData, - phyRxPolarity => phyRxPolarity, - phyRxData => phyRxData, - phyRxDataK => phyRxDataK, - phyRxDispErr => phyRxDispErr, - phyRxDecErr => phyRxDecErr, - phyRxReady => phyRxReady, - phyRxInit => phyRxInit); + pgpRemData => pgpRemData, + cellRxPause => cellRxPause, + cellRxSOC => cellRxSOC, + cellRxSOF => cellRxSOF, + cellRxEOC => cellRxEOC, + cellRxEOF => cellRxEOF, + cellRxEOFE => cellRxEOFE, + cellRxData => cellRxData, + phyRxPolarity => phyRxPolarity, + phyRxData => phyRxData, + phyRxDataK => phyRxDataK, + phyRxDispErr => phyRxDispErr, + phyRxDecErr => phyRxDecErr, + phyRxReady => phyRxReady, + phyRxInit => phyRxInit); end architecture rtl; diff --git a/protocols/pgp/pgp2b/core/wrappers/Pgp2bTxCellWrapper.vhd b/protocols/pgp/pgp2b/core/wrappers/Pgp2bTxCellWrapper.vhd index 22c509a235..95a2e895d4 100644 --- a/protocols/pgp/pgp2b/core/wrappers/Pgp2bTxCellWrapper.vhd +++ b/protocols/pgp/pgp2b/core/wrappers/Pgp2bTxCellWrapper.vhd @@ -46,25 +46,25 @@ begin generic map ( TX_LANE_CNT_G => 1) port map ( - pgpTxClk => clk, - pgpTxClkRst => rst, - pgpTxLinkReady => pgpTxLinkReady, - cellTxSOC => cellTxSOC, - cellTxSOF => cellTxSOF, - cellTxEOC => cellTxEOC, - cellTxEOF => cellTxEOF, - cellTxEOFE => cellTxEOFE, - cellTxData => cellTxData, - schTxIdle => schTxIdle, - schTxReq => schTxReq, - schTxAck => schTxAck, - schTxTimeout => schTxTimeout, - schTxDataVc => schTxDataVc, - vc0FrameTxValid => vc0FrameTxValid, - vc0FrameTxSOF => vc0FrameTxSOF, - vc0FrameTxEOF => vc0FrameTxEOF, - vc0FrameTxEOFE => vc0FrameTxEOFE, - vc0FrameTxData => vc0FrameTxData, + pgpTxClk => clk, + pgpTxClkRst => rst, + pgpTxLinkReady => pgpTxLinkReady, + cellTxSOC => cellTxSOC, + cellTxSOF => cellTxSOF, + cellTxEOC => cellTxEOC, + cellTxEOF => cellTxEOF, + cellTxEOFE => cellTxEOFE, + cellTxData => cellTxData, + schTxIdle => schTxIdle, + schTxReq => schTxReq, + schTxAck => schTxAck, + schTxTimeout => schTxTimeout, + schTxDataVc => schTxDataVc, + vc0FrameTxValid => vc0FrameTxValid, + vc0FrameTxSOF => vc0FrameTxSOF, + vc0FrameTxEOF => vc0FrameTxEOF, + vc0FrameTxEOFE => vc0FrameTxEOFE, + vc0FrameTxData => vc0FrameTxData, vc0LocAlmostFull => vc0LocAlmostFull, vc0LocOverflow => vc0LocOverflow, vc0RemAlmostFull => vc0RemAlmostFull, diff --git a/protocols/pgp/pgp2b/core/wrappers/Pgp2bTxPhyWrapper.vhd b/protocols/pgp/pgp2b/core/wrappers/Pgp2bTxPhyWrapper.vhd index 48887f1c9c..32c68057a9 100644 --- a/protocols/pgp/pgp2b/core/wrappers/Pgp2bTxPhyWrapper.vhd +++ b/protocols/pgp/pgp2b/core/wrappers/Pgp2bTxPhyWrapper.vhd @@ -37,21 +37,21 @@ begin generic map ( TX_LANE_CNT_G => 1) port map ( - pgpTxClk => clk, - pgpTxClkRst => rst, - pgpTxLinkReady => pgpTxLinkReady, - pgpTxOpCodeEn => pgpTxOpCodeEn, - pgpTxOpCode => pgpTxOpCode, + pgpTxClk => clk, + pgpTxClkRst => rst, + pgpTxLinkReady => pgpTxLinkReady, + pgpTxOpCodeEn => pgpTxOpCodeEn, + pgpTxOpCode => pgpTxOpCode, pgpLocLinkReady => pgpLocLinkReady, - pgpLocData => pgpLocData, - cellTxSOC => cellTxSOC, - cellTxSOF => cellTxSOF, - cellTxEOC => cellTxEOC, - cellTxEOF => cellTxEOF, - cellTxEOFE => cellTxEOFE, - cellTxData => cellTxData, - phyTxData => phyTxData, - phyTxDataK => phyTxDataK, - phyTxReady => phyTxReady); + pgpLocData => pgpLocData, + cellTxSOC => cellTxSOC, + cellTxSOF => cellTxSOF, + cellTxEOC => cellTxEOC, + cellTxEOF => cellTxEOF, + cellTxEOFE => cellTxEOFE, + cellTxData => cellTxData, + phyTxData => phyTxData, + phyTxDataK => phyTxDataK, + phyTxReady => phyTxReady); end architecture rtl; diff --git a/protocols/pgp/pgp2b/core/wrappers/Pgp2bTxSchedWrapper.vhd b/protocols/pgp/pgp2b/core/wrappers/Pgp2bTxSchedWrapper.vhd index 96ecedb25c..39d2b370db 100644 --- a/protocols/pgp/pgp2b/core/wrappers/Pgp2bTxSchedWrapper.vhd +++ b/protocols/pgp/pgp2b/core/wrappers/Pgp2bTxSchedWrapper.vhd @@ -34,21 +34,21 @@ begin generic map ( NUM_VC_EN_G => 1) port map ( - pgpTxClk => clk, - pgpTxClkRst => rst, - pgpTxFlush => pgpTxFlush, - pgpTxLinkReady => pgpTxLinkReady, - schTxSOF => schTxSOF, - schTxEOF => schTxEOF, - schTxIdle => schTxIdle, - schTxReq => schTxReq, - schTxAck => schTxAck, - schTxTimeout => schTxTimeout, - schTxDataVc => schTxDataVc, - vc0FrameTxValid => vc0FrameTxValid, - vc1FrameTxValid => '0', - vc2FrameTxValid => '0', - vc3FrameTxValid => '0', + pgpTxClk => clk, + pgpTxClkRst => rst, + pgpTxFlush => pgpTxFlush, + pgpTxLinkReady => pgpTxLinkReady, + schTxSOF => schTxSOF, + schTxEOF => schTxEOF, + schTxIdle => schTxIdle, + schTxReq => schTxReq, + schTxAck => schTxAck, + schTxTimeout => schTxTimeout, + schTxDataVc => schTxDataVc, + vc0FrameTxValid => vc0FrameTxValid, + vc1FrameTxValid => '0', + vc2FrameTxValid => '0', + vc3FrameTxValid => '0', vc0RemAlmostFull => vc0RemAlmostFull, vc1RemAlmostFull => '0', vc2RemAlmostFull => '0', diff --git a/protocols/pgp/pgp2b/core/wrappers/Pgp2bTxWrapper.vhd b/protocols/pgp/pgp2b/core/wrappers/Pgp2bTxWrapper.vhd index 7308cb34c3..8e5bcc4862 100644 --- a/protocols/pgp/pgp2b/core/wrappers/Pgp2bTxWrapper.vhd +++ b/protocols/pgp/pgp2b/core/wrappers/Pgp2bTxWrapper.vhd @@ -13,25 +13,25 @@ use surf.AxiStreamPkg.all; entity Pgp2bTxWrapper is port ( - clk : in sl; - rst : in sl; - txFlush : in sl := '0'; - txOpCodeEn : in sl := '0'; - txOpCode : in slv(7 downto 0) := (others => '0'); - txLocData : in slv(7 downto 0) := (others => '0'); - txFlowCntlDis : in sl := '0'; - txReset : in sl := '0'; - gtReset : in sl := '0'; - locLinkReady : in sl := '1'; - phyTxReady : in sl := '1'; - locOverflow : out slv(3 downto 0); - locPause : out slv(3 downto 0); - linkReady : out sl; - frameTx : out sl; - frameTxErr : out sl; - phyTxData : out slv(15 downto 0); - phyTxDataK : out slv(1 downto 0); - vc0FrameReady : out sl); + clk : in sl; + rst : in sl; + txFlush : in sl := '0'; + txOpCodeEn : in sl := '0'; + txOpCode : in slv(7 downto 0) := (others => '0'); + txLocData : in slv(7 downto 0) := (others => '0'); + txFlowCntlDis : in sl := '0'; + txReset : in sl := '0'; + gtReset : in sl := '0'; + locLinkReady : in sl := '1'; + phyTxReady : in sl := '1'; + locOverflow : out slv(3 downto 0); + locPause : out slv(3 downto 0); + linkReady : out sl; + frameTx : out sl; + frameTxErr : out sl; + phyTxData : out slv(15 downto 0); + phyTxDataK : out slv(1 downto 0); + vc0FrameReady : out sl); end entity Pgp2bTxWrapper; architecture rtl of Pgp2bTxWrapper is diff --git a/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcAlignmentControllerWrapper.vhd b/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcAlignmentControllerWrapper.vhd index da710f905f..0ce3162b9b 100644 --- a/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcAlignmentControllerWrapper.vhd +++ b/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcAlignmentControllerWrapper.vhd @@ -36,7 +36,7 @@ architecture rtl of Pgp2fcAlignmentControllerWrapper is signal mAxilReadMaster : AxiLiteReadMasterType; signal mAxilWriteMaster : AxiLiteWriteMasterType; - signal mAxilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal mAxilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; begin @@ -50,25 +50,25 @@ begin U_DUT : entity surf.Pgp2fcAlignmentController port map ( - stableClk => clk, - stableRst => rst, - linkAligned => linkAligned, - linkAlignOverride => linkAlignOverride, - linkAlignSlide => linkAlignSlide, - linkAlignSlideDone => linkAlignSlideDone, - linkAlignPhaseReq => linkAlignPhaseReq, - linkAlignPhase => linkAlignPhase, + stableClk => clk, + stableRst => rst, + linkAligned => linkAligned, + linkAlignOverride => linkAlignOverride, + linkAlignSlide => linkAlignSlide, + linkAlignSlideDone => linkAlignSlideDone, + linkAlignPhaseReq => linkAlignPhaseReq, + linkAlignPhase => linkAlignPhase, linkAlignPhaseValid => linkAlignPhaseValid, - protocolError => protocolError, - rxClk => clk, - rxReset => rxReset, - rxSlide => rxSlide, - rxReady => rxReady, - axilClk => clk, - axilRst => rst, - mAxilReadMaster => mAxilReadMaster, - mAxilReadSlave => mAxilReadSlave, - mAxilWriteMaster => mAxilWriteMaster, - mAxilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C); + protocolError => protocolError, + rxClk => clk, + rxReset => rxReset, + rxSlide => rxSlide, + rxReady => rxReady, + axilClk => clk, + axilRst => rst, + mAxilReadMaster => mAxilReadMaster, + mAxilReadSlave => mAxilReadSlave, + mAxilWriteMaster => mAxilWriteMaster, + mAxilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C); end architecture rtl; diff --git a/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcAxiWrapper.vhd b/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcAxiWrapper.vhd index cc446ed407..d43ee176c2 100644 --- a/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcAxiWrapper.vhd +++ b/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcAxiWrapper.vhd @@ -61,9 +61,9 @@ architecture rtl of Pgp2fcAxiWrapper is signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; - signal pgpTxIn : Pgp2fcTxInType := PGP2FC_TX_IN_INIT_C; - signal pgpRxIn : Pgp2fcRxInType := PGP2FC_RX_IN_INIT_C; - signal locTxIn : Pgp2fcTxInType := ( + signal pgpTxIn : Pgp2fcTxInType := PGP2FC_TX_IN_INIT_C; + signal pgpRxIn : Pgp2fcRxInType := PGP2FC_RX_IN_INIT_C; + signal locTxIn : Pgp2fcTxInType := ( flush => '0', fcValid => '0', fcWord => (others => '0'), diff --git a/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcLaneWrapper.vhd b/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcLaneWrapper.vhd index 07050ff0fc..9b1b2c8896 100644 --- a/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcLaneWrapper.vhd +++ b/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcLaneWrapper.vhd @@ -60,8 +60,8 @@ architecture rtl of Pgp2fcLaneWrapper is signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal pgpTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal pgpTxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal pgpTxMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal pgpTxSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; signal pgpTxMasters : AxiStreamMasterArray(3 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); signal pgpTxSlaves : AxiStreamSlaveArray(3 downto 0) := (others => AXI_STREAM_SLAVE_FORCE_C); @@ -84,14 +84,14 @@ architecture rtl of Pgp2fcLaneWrapper is begin - LINK_READY <= pgpRxOut.linkReady and pgpTxOut.linkReady; - TX_FC_SENT <= pgpTxOut.fcSent; + LINK_READY <= pgpRxOut.linkReady and pgpTxOut.linkReady; + TX_FC_SENT <= pgpTxOut.fcSent; RX_FC_VALID <= pgpRxOut.fcValid; - RX_FC_WORD <= pgpRxOut.fcWord(15 downto 0); + RX_FC_WORD <= pgpRxOut.fcWord(15 downto 0); - pgpTxMasters(0) <= pgpTxMaster; - pgpTxSlave <= pgpTxSlaves(0); - pgpTxIn.fcValid <= TX_FC_VALID; + pgpTxMasters(0) <= pgpTxMaster; + pgpTxSlave <= pgpTxSlaves(0); + pgpTxIn.fcValid <= TX_FC_VALID; pgpTxIn.fcWord(15 downto 0) <= TX_FC_WORD; phyRxLaneIn.data <= phyTxLaneOut.data; diff --git a/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcRxPhyWrapper.vhd b/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcRxPhyWrapper.vhd index 80983066d3..22752ad08d 100644 --- a/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcRxPhyWrapper.vhd +++ b/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcRxPhyWrapper.vhd @@ -43,14 +43,14 @@ begin U_DUT : entity surf.Pgp2fcRxPhy port map ( - pgpRxClk => clk, - pgpRxClkRst => rst, - pgpRxLinkReady => pgpRxLinkReady, - pgpRxLinkDown => pgpRxLinkDown, - pgpRxLinkError => pgpRxLinkError, - fcValid => fcValid, - fcWord => fcWord, - fcError => fcError, + pgpRxClk => clk, + pgpRxClkRst => rst, + pgpRxLinkReady => pgpRxLinkReady, + pgpRxLinkDown => pgpRxLinkDown, + pgpRxLinkError => pgpRxLinkError, + fcValid => fcValid, + fcWord => fcWord, + fcError => fcError, pgpRemLinkReady => pgpRemLinkReady, pgpRemData => pgpRemData, cellRxPause => cellRxPause, diff --git a/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcTxCellWrapper.vhd b/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcTxCellWrapper.vhd index 0a71742062..9bae6424cc 100644 --- a/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcTxCellWrapper.vhd +++ b/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcTxCellWrapper.vhd @@ -49,29 +49,29 @@ begin U_DUT : entity surf.Pgp2fcTxCell port map ( - pgpTxClk => clk, - pgpTxClkRst => rst, - pgpTxLinkReady => pgpTxLinkReady, - pgpTxBusy => pgpTxBusy, - cellTxSOC => cellTxSOC, - cellTxSOF => cellTxSOF, - cellTxEOC => cellTxEOC, - cellTxEOF => cellTxEOF, - cellTxEOFE => cellTxEOFE, - cellTxData => cellTxData, - schTxSOF => schTxSOF, - schTxEOF => schTxEOF, - schTxIdle => schTxIdle, - schTxReq => schTxReq, - schTxAck => schTxAck, - schTxTimeout => schTxTimeout, - schTxDataVc => schTxDataVc, - vc0FrameTxValid => vc0FrameTxValid, - vc0FrameTxReady => vc0FrameTxReady, - vc0FrameTxSOF => vc0FrameTxSOF, - vc0FrameTxEOF => vc0FrameTxEOF, - vc0FrameTxEOFE => vc0FrameTxEOFE, - vc0FrameTxData => vc0FrameTxData, + pgpTxClk => clk, + pgpTxClkRst => rst, + pgpTxLinkReady => pgpTxLinkReady, + pgpTxBusy => pgpTxBusy, + cellTxSOC => cellTxSOC, + cellTxSOF => cellTxSOF, + cellTxEOC => cellTxEOC, + cellTxEOF => cellTxEOF, + cellTxEOFE => cellTxEOFE, + cellTxData => cellTxData, + schTxSOF => schTxSOF, + schTxEOF => schTxEOF, + schTxIdle => schTxIdle, + schTxReq => schTxReq, + schTxAck => schTxAck, + schTxTimeout => schTxTimeout, + schTxDataVc => schTxDataVc, + vc0FrameTxValid => vc0FrameTxValid, + vc0FrameTxReady => vc0FrameTxReady, + vc0FrameTxSOF => vc0FrameTxSOF, + vc0FrameTxEOF => vc0FrameTxEOF, + vc0FrameTxEOFE => vc0FrameTxEOFE, + vc0FrameTxData => vc0FrameTxData, vc0LocAlmostFull => vc0LocAlmostFull, vc0LocOverflow => vc0LocOverflow, vc0RemAlmostFull => vc0RemAlmostFull, @@ -102,9 +102,9 @@ begin vc3LocAlmostFull => '0', vc3LocOverflow => '0', vc3RemAlmostFull => '0', - crcTxIn => crcTxIn, - crcTxInit => crcTxInit, - crcTxValid => crcTxValid, - crcTxOut => (others => '0')); + crcTxIn => crcTxIn, + crcTxInit => crcTxInit, + crcTxValid => crcTxValid, + crcTxOut => (others => '0')); end architecture rtl; diff --git a/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcTxPhyWrapper.vhd b/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcTxPhyWrapper.vhd index 5d91447bd7..7032570b31 100644 --- a/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcTxPhyWrapper.vhd +++ b/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcTxPhyWrapper.vhd @@ -14,17 +14,17 @@ entity Pgp2fcTxPhyWrapper is port ( clk : in sl; rst : in sl; - fcValid : in sl := '0'; - fcWord : in slv(15 downto 0) := (others => '0'); - pgpLocLinkReady : in sl := '1'; - pgpLocData : in slv(7 downto 0) := x"5A"; - cellTxSOC : in sl := '0'; - cellTxSOF : in sl := '0'; - cellTxEOC : in sl := '0'; - cellTxEOF : in sl := '0'; - cellTxEOFE : in sl := '0'; - cellTxData : in slv(15 downto 0) := (others => '0'); - phyTxReady : in sl := '1'; + fcValid : in sl := '0'; + fcWord : in slv(15 downto 0) := (others => '0'); + pgpLocLinkReady : in sl := '1'; + pgpLocData : in slv(7 downto 0) := x"5A"; + cellTxSOC : in sl := '0'; + cellTxSOF : in sl := '0'; + cellTxEOC : in sl := '0'; + cellTxEOF : in sl := '0'; + cellTxEOFE : in sl := '0'; + cellTxData : in slv(15 downto 0) := (others => '0'); + phyTxReady : in sl := '1'; pgpTxLinkReady : out sl; pgpBusy : out sl; fcSent : out sl; diff --git a/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcTxSchedWrapper.vhd b/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcTxSchedWrapper.vhd index 6813cdf9a5..7f8d5e05e9 100644 --- a/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcTxSchedWrapper.vhd +++ b/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcTxSchedWrapper.vhd @@ -36,22 +36,22 @@ begin generic map ( NUM_VC_EN_G => 1) port map ( - pgpTxClk => clk, - pgpTxClkRst => rst, - pgpTxFlush => pgpTxFlush, - pgpTxLinkReady => pgpTxLinkReady, - pgpTxBusy => pgpTxBusy, - schTxSOF => schTxSOF, - schTxEOF => schTxEOF, - schTxIdle => schTxIdle, - schTxReq => schTxReq, - schTxAck => schTxAck, - schTxTimeout => schTxTimeout, - schTxDataVc => schTxDataVc, - vc0FrameTxValid => vc0FrameTxValid, - vc1FrameTxValid => '0', - vc2FrameTxValid => '0', - vc3FrameTxValid => '0', + pgpTxClk => clk, + pgpTxClkRst => rst, + pgpTxFlush => pgpTxFlush, + pgpTxLinkReady => pgpTxLinkReady, + pgpTxBusy => pgpTxBusy, + schTxSOF => schTxSOF, + schTxEOF => schTxEOF, + schTxIdle => schTxIdle, + schTxReq => schTxReq, + schTxAck => schTxAck, + schTxTimeout => schTxTimeout, + schTxDataVc => schTxDataVc, + vc0FrameTxValid => vc0FrameTxValid, + vc1FrameTxValid => '0', + vc2FrameTxValid => '0', + vc3FrameTxValid => '0', vc0RemAlmostFull => vc0RemAlmostFull, vc1RemAlmostFull => '0', vc2RemAlmostFull => '0', diff --git a/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcTxWrapper.vhd b/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcTxWrapper.vhd index 4e890f8dce..3278b40976 100644 --- a/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcTxWrapper.vhd +++ b/protocols/pgp/pgp2fc/core/wrappers/Pgp2fcTxWrapper.vhd @@ -48,17 +48,17 @@ architecture rtl of Pgp2fcTxWrapper is signal pgpTxSlaves : AxiStreamSlaveArray(3 downto 0); signal phyTxLaneOut : Pgp2fcTxPhyLaneOutType; signal pgpTxOut : Pgp2fcTxOutType; - signal pgpTxIn : Pgp2fcTxInType := PGP2FC_TX_IN_INIT_C; + signal pgpTxIn : Pgp2fcTxInType := PGP2FC_TX_IN_INIT_C; begin - pgpTxIn.flush <= txFlush; - pgpTxIn.fcValid <= txFcValid; + pgpTxIn.flush <= txFlush; + pgpTxIn.fcValid <= txFcValid; pgpTxIn.fcWord(15 downto 0) <= txFcWord; - pgpTxIn.locData <= txLocData; - pgpTxIn.flowCntlDis <= txFlowCntlDis; - pgpTxIn.resetTx <= txReset; - pgpTxIn.resetGt <= gtReset; + pgpTxIn.locData <= txLocData; + pgpTxIn.flowCntlDis <= txFlowCntlDis; + pgpTxIn.resetTx <= txReset; + pgpTxIn.resetGt <= gtReset; locOverflow <= pgpTxOut.locOverflow; locPause <= pgpTxOut.locPause; @@ -70,16 +70,17 @@ begin phyTxDataK <= phyTxLaneOut.dataK; vc0FrameReady <= pgpTxSlaves(0).tReady; - process (vc0FrameData, vc0FrameEofe, vc0FrameLast, vc0FrameSof, vc0FrameValid) is + process (vc0FrameData, vc0FrameEofe, vc0FrameLast, vc0FrameSof, + vc0FrameValid) is variable master : AxiStreamMasterType; begin master := AXI_STREAM_MASTER_INIT_C; if vc0FrameValid = '1' then - master.tValid := '1'; + master.tValid := '1'; master.tData(15 downto 0) := vc0FrameData; - master.tKeep(1 downto 0) := "11"; - master.tStrb(1 downto 0) := "11"; - master.tLast := vc0FrameLast; + master.tKeep(1 downto 0) := "11"; + master.tStrb(1 downto 0) := "11"; + master.tLast := vc0FrameLast; axiStreamSetUserBit(PGP2FC_AXIS_CONFIG_C, master, SSI_EOFE_C, vc0FrameEofe); axiStreamSetUserBit(PGP2FC_AXIS_CONFIG_C, master, SSI_SOF_C, vc0FrameSof, 0); end if; diff --git a/protocols/pgp/shared/wrappers/PgpRxVcFifoWrapper.vhd b/protocols/pgp/shared/wrappers/PgpRxVcFifoWrapper.vhd index 5c114751a0..57272b44b3 100644 --- a/protocols/pgp/shared/wrappers/PgpRxVcFifoWrapper.vhd +++ b/protocols/pgp/shared/wrappers/PgpRxVcFifoWrapper.vhd @@ -22,30 +22,30 @@ use surf.Pgp4Pkg.all; entity PgpRxVcFifoWrapper is port ( - pgpClk : in sl; - pgpRst : in sl; - axisClk : in sl; - axisRst : in sl; - rxlinkReady : in sl; - pgpRxPause : out sl; - pgpRxOverflow : out sl; - pgpRxReady : out sl; - S_AXIS_TVALID : in sl; - S_AXIS_TDATA : in slv(63 downto 0); - S_AXIS_TKEEP : in slv(7 downto 0); - S_AXIS_TLAST : in sl; - S_AXIS_TDEST : in slv(0 downto 0); - S_AXIS_TID : in slv(0 downto 0); - S_AXIS_TUSER : in slv(0 downto 0); - S_AXIS_TREADY : out sl; - M_AXIS_TVALID : out sl; - M_AXIS_TDATA : out slv(63 downto 0); - M_AXIS_TKEEP : out slv(7 downto 0); - M_AXIS_TLAST : out sl; - M_AXIS_TDEST : out slv(0 downto 0); - M_AXIS_TID : out slv(0 downto 0); - M_AXIS_TUSER : out slv(0 downto 0); - M_AXIS_TREADY : in sl); + pgpClk : in sl; + pgpRst : in sl; + axisClk : in sl; + axisRst : in sl; + rxlinkReady : in sl; + pgpRxPause : out sl; + pgpRxOverflow : out sl; + pgpRxReady : out sl; + S_AXIS_TVALID : in sl; + S_AXIS_TDATA : in slv(63 downto 0); + S_AXIS_TKEEP : in slv(7 downto 0); + S_AXIS_TLAST : in sl; + S_AXIS_TDEST : in slv(0 downto 0); + S_AXIS_TID : in slv(0 downto 0); + S_AXIS_TUSER : in slv(0 downto 0); + S_AXIS_TREADY : out sl; + M_AXIS_TVALID : out sl; + M_AXIS_TDATA : out slv(63 downto 0); + M_AXIS_TKEEP : out slv(7 downto 0); + M_AXIS_TLAST : out sl; + M_AXIS_TDEST : out slv(0 downto 0); + M_AXIS_TID : out slv(0 downto 0); + M_AXIS_TUSER : out slv(0 downto 0); + M_AXIS_TREADY : in sl); end entity PgpRxVcFifoWrapper; architecture rtl of PgpRxVcFifoWrapper is @@ -58,12 +58,12 @@ architecture rtl of PgpRxVcFifoWrapper is signal pgpAResetN : sl := '1'; signal axisAResetN : sl := '1'; - signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal pgpRxCtrlInt : AxiStreamCtrlType := AXI_STREAM_CTRL_UNUSED_C; - signal pgpRxSlaveInt : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal pgpRxCtrlInt : AxiStreamCtrlType := AXI_STREAM_CTRL_UNUSED_C; + signal pgpRxSlaveInt : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; begin diff --git a/protocols/srp/wrappers/SrpV3AxiWrapper.vhd b/protocols/srp/wrappers/SrpV3AxiWrapper.vhd index bbbb6acac6..ad63659ddf 100644 --- a/protocols/srp/wrappers/SrpV3AxiWrapper.vhd +++ b/protocols/srp/wrappers/SrpV3AxiWrapper.vhd @@ -23,24 +23,24 @@ use surf.SsiPkg.all; entity SrpV3AxiWrapper is port ( - AXIS_ACLK : in std_logic; - AXIS_ARESETN : in std_logic; - S_AXIS_TVALID : in std_logic; - S_AXIS_TDATA : in std_logic_vector(31 downto 0); - S_AXIS_TKEEP : in std_logic_vector(3 downto 0); - S_AXIS_TLAST : in std_logic; - S_AXIS_TDEST : in std_logic_vector(3 downto 0); - S_AXIS_TID : in std_logic_vector(0 downto 0); - S_AXIS_TUSER : in std_logic_vector(1 downto 0); - S_AXIS_TREADY : out std_logic; - M_AXIS_TVALID : out std_logic; - M_AXIS_TDATA : out std_logic_vector(31 downto 0); - M_AXIS_TKEEP : out std_logic_vector(3 downto 0); - M_AXIS_TLAST : out std_logic; - M_AXIS_TDEST : out std_logic_vector(3 downto 0); - M_AXIS_TID : out std_logic_vector(0 downto 0); - M_AXIS_TUSER : out std_logic_vector(1 downto 0); - M_AXIS_TREADY : in std_logic); + AXIS_ACLK : in std_logic; + AXIS_ARESETN : in std_logic; + S_AXIS_TVALID : in std_logic; + S_AXIS_TDATA : in std_logic_vector(31 downto 0); + S_AXIS_TKEEP : in std_logic_vector(3 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TDEST : in std_logic_vector(3 downto 0); + S_AXIS_TID : in std_logic_vector(0 downto 0); + S_AXIS_TUSER : in std_logic_vector(1 downto 0); + S_AXIS_TREADY : out std_logic; + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector(31 downto 0); + M_AXIS_TKEEP : out std_logic_vector(3 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TDEST : out std_logic_vector(3 downto 0); + M_AXIS_TID : out std_logic_vector(0 downto 0); + M_AXIS_TUSER : out std_logic_vector(1 downto 0); + M_AXIS_TREADY : in std_logic); end entity SrpV3AxiWrapper; architecture rtl of SrpV3AxiWrapper is diff --git a/protocols/ssi/tb/SsiFifoTb.vhd b/protocols/ssi/tb/SsiFifoTb.vhd index a6ce6b0c3f..3c7064f44b 100644 --- a/protocols/ssi/tb/SsiFifoTb.vhd +++ b/protocols/ssi/tb/SsiFifoTb.vhd @@ -187,14 +187,14 @@ begin U_Rx : entity surf.SsiPrbsRx generic map ( -- General Configurations - TPD_G => TPD_C, + TPD_G => TPD_C, -- FIFO Configurations - GEN_SYNC_FIFO_G => true, + GEN_SYNC_FIFO_G => true, -- PRBS Configurations - PRBS_SEED_SIZE_G => PRBS_SEED_SIZE_C, - PRBS_TAPS_G => PRBS_TAPS_C, + PRBS_SEED_SIZE_G => PRBS_SEED_SIZE_C, + PRBS_TAPS_G => PRBS_TAPS_C, -- AXI Stream Configurations - SLAVE_AXI_STREAM_CONFIG_G => AXI_STREAM_CONFIG_C) + SLAVE_AXI_STREAM_CONFIG_G => AXI_STREAM_CONFIG_C) port map ( -- Streaming RX Data Interface (sAxisClk domain) sAxisClk => rxClk, diff --git a/protocols/ssi/wrappers/SsiAxiLiteMasterWrapper.vhd b/protocols/ssi/wrappers/SsiAxiLiteMasterWrapper.vhd index eb2a14bfa1..865073bc28 100644 --- a/protocols/ssi/wrappers/SsiAxiLiteMasterWrapper.vhd +++ b/protocols/ssi/wrappers/SsiAxiLiteMasterWrapper.vhd @@ -80,20 +80,21 @@ architecture rtl of SsiAxiLiteMasterWrapper is begin - sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTKeep, + sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(31 downto 0) := sAxisTData(31 downto 0); - v.tKeep(3 downto 0) := sAxisTKeep(3 downto 0); - v.tLast := sAxisTLast; + v.tKeep(3 downto 0) := sAxisTKeep(3 downto 0); + v.tLast := sAxisTLast; ssiSetUserSof(AXIS_CONFIG_C, v, sAxisSof); ssiSetUserEofe(AXIS_CONFIG_C, v, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; - sAxisTReady <= sAxisSlave.tReady; + sAxisTReady <= sAxisSlave.tReady; mAxisSlave.tReady <= mAxisTReady; mAxisView : process (mAxisMaster) is @@ -104,48 +105,48 @@ begin keepV := (others => '0'); dataV(31 downto 0) := mAxisMaster.tData(31 downto 0); - keepV(3 downto 0) := mAxisMaster.tKeep(3 downto 0); + keepV(3 downto 0) := mAxisMaster.tKeep(3 downto 0); mAxisTValid <= mAxisMaster.tValid; - mAxisTData <= dataV; - mAxisTKeep <= keepV; - mAxisTLast <= mAxisMaster.tLast; - mAxisSof <= ssiGetUserSof(AXIS_CONFIG_C, mAxisMaster); - mAxisEofe <= ssiGetUserEofe(AXIS_CONFIG_C, mAxisMaster); + mAxisTData <= dataV; + mAxisTKeep <= keepV; + mAxisTLast <= mAxisMaster.tLast; + mAxisSof <= ssiGetUserSof(AXIS_CONFIG_C, mAxisMaster); + mAxisEofe <= ssiGetUserEofe(AXIS_CONFIG_C, mAxisMaster); end process mAxisView; - M_AXIL_AWADDR <= mAxiLiteWriteMaster.awaddr; - M_AXIL_AWPROT <= mAxiLiteWriteMaster.awprot; + M_AXIL_AWADDR <= mAxiLiteWriteMaster.awaddr; + M_AXIL_AWPROT <= mAxiLiteWriteMaster.awprot; M_AXIL_AWVALID <= mAxiLiteWriteMaster.awvalid; - M_AXIL_WDATA <= mAxiLiteWriteMaster.wdata; - M_AXIL_WSTRB <= mAxiLiteWriteMaster.wstrb; - M_AXIL_WVALID <= mAxiLiteWriteMaster.wvalid; - M_AXIL_BREADY <= mAxiLiteWriteMaster.bready; - M_AXIL_ARADDR <= mAxiLiteReadMaster.araddr; - M_AXIL_ARPROT <= mAxiLiteReadMaster.arprot; + M_AXIL_WDATA <= mAxiLiteWriteMaster.wdata; + M_AXIL_WSTRB <= mAxiLiteWriteMaster.wstrb; + M_AXIL_WVALID <= mAxiLiteWriteMaster.wvalid; + M_AXIL_BREADY <= mAxiLiteWriteMaster.bready; + M_AXIL_ARADDR <= mAxiLiteReadMaster.araddr; + M_AXIL_ARPROT <= mAxiLiteReadMaster.arprot; M_AXIL_ARVALID <= mAxiLiteReadMaster.arvalid; - M_AXIL_RREADY <= mAxiLiteReadMaster.rready; + M_AXIL_RREADY <= mAxiLiteReadMaster.rready; mAxiLiteWriteSlave.awready <= M_AXIL_AWREADY; - mAxiLiteWriteSlave.wready <= M_AXIL_WREADY; - mAxiLiteWriteSlave.bresp <= M_AXIL_BRESP; - mAxiLiteWriteSlave.bvalid <= M_AXIL_BVALID; - mAxiLiteReadSlave.arready <= M_AXIL_ARREADY; - mAxiLiteReadSlave.rdata <= M_AXIL_RDATA; - mAxiLiteReadSlave.rresp <= M_AXIL_RRESP; - mAxiLiteReadSlave.rvalid <= M_AXIL_RVALID; + mAxiLiteWriteSlave.wready <= M_AXIL_WREADY; + mAxiLiteWriteSlave.bresp <= M_AXIL_BRESP; + mAxiLiteWriteSlave.bvalid <= M_AXIL_BVALID; + mAxiLiteReadSlave.arready <= M_AXIL_ARREADY; + mAxiLiteReadSlave.rdata <= M_AXIL_RDATA; + mAxiLiteReadSlave.rresp <= M_AXIL_RRESP; + mAxiLiteReadSlave.rvalid <= M_AXIL_RVALID; U_DUT : entity surf.SsiAxiLiteMaster generic map ( - TPD_G => 1 ns, - RESP_THOLD_G => 1, - SLAVE_READY_EN_G => true, - EN_32BIT_ADDR_G => false, - MEMORY_TYPE_G => "distributed", - GEN_SYNC_FIFO_G => true, - FIFO_ADDR_WIDTH_G => 4, - FIFO_PAUSE_THRESH_G => 1, - AXI_STREAM_CONFIG_G => AXIS_CONFIG_C) + TPD_G => 1 ns, + RESP_THOLD_G => 1, + SLAVE_READY_EN_G => true, + EN_32BIT_ADDR_G => false, + MEMORY_TYPE_G => "distributed", + GEN_SYNC_FIFO_G => true, + FIFO_ADDR_WIDTH_G => 4, + FIFO_PAUSE_THRESH_G => 1, + AXI_STREAM_CONFIG_G => AXIS_CONFIG_C) port map ( sAxisClk => axisClk, sAxisRst => axisRst, diff --git a/protocols/ssi/wrappers/SsiCmdMasterWrapper.vhd b/protocols/ssi/wrappers/SsiCmdMasterWrapper.vhd index 50fa06f502..ba8c5bbb3a 100644 --- a/protocols/ssi/wrappers/SsiCmdMasterWrapper.vhd +++ b/protocols/ssi/wrappers/SsiCmdMasterWrapper.vhd @@ -51,23 +51,24 @@ architecture rtl of SsiCmdMasterWrapper is begin - sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTKeep, + sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(31 downto 0) := sAxisTData(31 downto 0); - v.tKeep(3 downto 0) := sAxisTKeep(3 downto 0); - v.tLast := sAxisTLast; + v.tKeep(3 downto 0) := sAxisTKeep(3 downto 0); + v.tLast := sAxisTLast; ssiSetUserSof(AXIS_CONFIG_C, v, sAxisSof); ssiSetUserEofe(AXIS_CONFIG_C, v, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; sAxisTReady <= sAxisSlave.tReady; - cmdValid <= cmdMaster.valid; - cmdOpCode <= cmdMaster.opCode; - cmdCtx <= cmdMaster.ctx; + cmdValid <= cmdMaster.valid; + cmdOpCode <= cmdMaster.opCode; + cmdCtx <= cmdMaster.ctx; U_DUT : entity surf.SsiCmdMaster generic map ( diff --git a/protocols/ssi/wrappers/SsiDbgTapWrapper.vhd b/protocols/ssi/wrappers/SsiDbgTapWrapper.vhd index 2c37785899..c77cd8e249 100644 --- a/protocols/ssi/wrappers/SsiDbgTapWrapper.vhd +++ b/protocols/ssi/wrappers/SsiDbgTapWrapper.vhd @@ -24,16 +24,16 @@ entity SsiDbgTapWrapper is generic ( DATA_BYTES_G : positive := 2); port ( - axisClk : in sl; - axisRst : in sl; - axisTValid : in sl; - axisTData : in slv(63 downto 0); - axisTKeep : in slv(7 downto 0); - axisTLast : in sl; - axisTDest : in slv(3 downto 0); - axisSof : in sl; - axisEofe : in sl; - axisTReady : in sl); + axisClk : in sl; + axisRst : in sl; + axisTValid : in sl; + axisTData : in slv(63 downto 0); + axisTKeep : in slv(7 downto 0); + axisTLast : in sl; + axisTDest : in slv(3 downto 0); + axisSof : in sl; + axisEofe : in sl; + axisTReady : in sl); end entity SsiDbgTapWrapper; architecture rtl of SsiDbgTapWrapper is @@ -44,25 +44,26 @@ architecture rtl of SsiDbgTapWrapper is tUserMode => TUSER_FIRST_LAST_C, tDestBits => 4, tUserBits => 2); - constant DATA_WIDTH_C : positive := 8*DATA_BYTES_G; + constant DATA_WIDTH_C : positive := 8*DATA_BYTES_G; signal axisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal axisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; begin - axisComb : process (axisEofe, axisSof, axisTData, axisTDest, axisTKeep, axisTLast, axisTValid) is + axisComb : process (axisEofe, axisSof, axisTData, axisTDest, axisTKeep, + axisTLast, axisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := axisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := axisTValid; v.tData(DATA_WIDTH_C-1 downto 0) := axisTData(DATA_WIDTH_C-1 downto 0); v.tKeep(DATA_BYTES_G-1 downto 0) := axisTKeep(DATA_BYTES_G-1 downto 0); - v.tLast := axisTLast; - v.tDest(3 downto 0) := axisTDest; + v.tLast := axisTLast; + v.tDest(3 downto 0) := axisTDest; ssiSetUserSof(AXIS_CONFIG_C, v, axisSof); ssiSetUserEofe(AXIS_CONFIG_C, v, axisEofe); - axisMaster <= v; + axisMaster <= v; end process axisComb; axisSlave.tReady <= axisTReady; diff --git a/protocols/ssi/wrappers/SsiFifoWrapper.vhd b/protocols/ssi/wrappers/SsiFifoWrapper.vhd index a4e4f5a3e3..d4fe51b3ec 100644 --- a/protocols/ssi/wrappers/SsiFifoWrapper.vhd +++ b/protocols/ssi/wrappers/SsiFifoWrapper.vhd @@ -64,36 +64,37 @@ architecture rtl of SsiFifoWrapper is tUserMode => TUSER_FIRST_LAST_C, tDestBits => 4, tUserBits => 2); - constant DATA_WIDTH_C : positive := 8*DATA_BYTES_G; + constant DATA_WIDTH_C : positive := 8*DATA_BYTES_G; - signal sAxisMasterInt : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sAxisSlaveInt : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal sAxisCtrlInt : AxiStreamCtrlType := AXI_STREAM_CTRL_INIT_C; - signal mAxisMasterInt : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mAxisSlaveInt : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal sAxisMasterInt : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlaveInt : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal sAxisCtrlInt : AxiStreamCtrlType := AXI_STREAM_CTRL_INIT_C; + signal mAxisMasterInt : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlaveInt : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; signal fifoWrCntInt : slv(FIFO_ADDR_WIDTH_G-1 downto 0) := (others => '0'); signal pauseThreshInt : slv(FIFO_ADDR_WIDTH_G-1 downto 0) := (others => '1'); begin - sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTDest, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTDest, + sAxisTKeep, sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(DATA_WIDTH_C-1 downto 0) := sAxisTData(DATA_WIDTH_C-1 downto 0); v.tKeep(DATA_BYTES_G-1 downto 0) := sAxisTKeep(DATA_BYTES_G-1 downto 0); - v.tLast := sAxisTLast; - v.tDest(3 downto 0) := sAxisTDest; + v.tLast := sAxisTLast; + v.tDest(3 downto 0) := sAxisTDest; ssiSetUserSof(AXIS_CONFIG_C, v, sAxisSof); ssiSetUserEofe(AXIS_CONFIG_C, v, sAxisEofe); - sAxisMasterInt <= v; + sAxisMasterInt <= v; end process sAxisComb; - sAxisTReady <= sAxisSlaveInt.tReady; - sAxisPause <= sAxisCtrlInt.pause; - pauseThreshInt <= fifoPauseThresh(FIFO_ADDR_WIDTH_G-1 downto 0); - fifoWrCnt <= resize(fifoWrCntInt, fifoWrCnt'length); + sAxisTReady <= sAxisSlaveInt.tReady; + sAxisPause <= sAxisCtrlInt.pause; + pauseThreshInt <= fifoPauseThresh(FIFO_ADDR_WIDTH_G-1 downto 0); + fifoWrCnt <= resize(fifoWrCntInt, fifoWrCnt'length); mAxisSlaveInt.tReady <= mAxisTReady; mAxisView : process (mAxisMasterInt) is @@ -107,12 +108,12 @@ begin keepV(DATA_BYTES_G-1 downto 0) := mAxisMasterInt.tKeep(DATA_BYTES_G-1 downto 0); mAxisTValid <= mAxisMasterInt.tValid; - mAxisTData <= dataV; - mAxisTKeep <= keepV; - mAxisTLast <= mAxisMasterInt.tLast; - mAxisTDest <= mAxisMasterInt.tDest(3 downto 0); - mAxisSof <= ssiGetUserSof(AXIS_CONFIG_C, mAxisMasterInt); - mAxisEofe <= ssiGetUserEofe(AXIS_CONFIG_C, mAxisMasterInt); + mAxisTData <= dataV; + mAxisTKeep <= keepV; + mAxisTLast <= mAxisMasterInt.tLast; + mAxisTDest <= mAxisMasterInt.tDest(3 downto 0); + mAxisSof <= ssiGetUserSof(AXIS_CONFIG_C, mAxisMasterInt); + mAxisEofe <= ssiGetUserEofe(AXIS_CONFIG_C, mAxisMasterInt); end process mAxisView; U_DUT : entity surf.SsiFifo diff --git a/protocols/ssi/wrappers/SsiFrameLimiterWrapper.vhd b/protocols/ssi/wrappers/SsiFrameLimiterWrapper.vhd index b465d0d7de..264e79891a 100644 --- a/protocols/ssi/wrappers/SsiFrameLimiterWrapper.vhd +++ b/protocols/ssi/wrappers/SsiFrameLimiterWrapper.vhd @@ -53,7 +53,7 @@ architecture rtl of SsiFrameLimiterWrapper is tUserMode => TUSER_FIRST_LAST_C, tDestBits => 4, tUserBits => 2); - constant DATA_WIDTH_C : positive := 8*DATA_BYTES_G; + constant DATA_WIDTH_C : positive := 8*DATA_BYTES_G; signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; @@ -62,21 +62,22 @@ architecture rtl of SsiFrameLimiterWrapper is begin - sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTDest, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTDest, + sAxisTKeep, sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(DATA_WIDTH_C-1 downto 0) := sAxisTData(DATA_WIDTH_C-1 downto 0); v.tKeep(DATA_BYTES_G-1 downto 0) := sAxisTKeep(DATA_BYTES_G-1 downto 0); - v.tLast := sAxisTLast; - v.tDest(3 downto 0) := sAxisTDest; + v.tLast := sAxisTLast; + v.tDest(3 downto 0) := sAxisTDest; ssiSetUserSof(AXIS_CONFIG_C, v, sAxisSof); ssiSetUserEofe(AXIS_CONFIG_C, v, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; - sAxisTReady <= sAxisSlave.tReady; + sAxisTReady <= sAxisSlave.tReady; mAxisSlave.tReady <= mAxisTReady; mAxisView : process (mAxisMaster) is @@ -90,12 +91,12 @@ begin keepV(DATA_BYTES_G-1 downto 0) := mAxisMaster.tKeep(DATA_BYTES_G-1 downto 0); mAxisTValid <= mAxisMaster.tValid; - mAxisTData <= dataV; - mAxisTKeep <= keepV; - mAxisTLast <= mAxisMaster.tLast; - mAxisTDest <= mAxisMaster.tDest(3 downto 0); - mAxisSof <= ssiGetUserSof(AXIS_CONFIG_C, mAxisMaster); - mAxisEofe <= ssiGetUserEofe(AXIS_CONFIG_C, mAxisMaster); + mAxisTData <= dataV; + mAxisTKeep <= keepV; + mAxisTLast <= mAxisMaster.tLast; + mAxisTDest <= mAxisMaster.tDest(3 downto 0); + mAxisSof <= ssiGetUserSof(AXIS_CONFIG_C, mAxisMaster); + mAxisEofe <= ssiGetUserEofe(AXIS_CONFIG_C, mAxisMaster); end process mAxisView; U_DUT : entity surf.SsiFrameLimiter diff --git a/protocols/ssi/wrappers/SsiIbFrameFilterWrapper.vhd b/protocols/ssi/wrappers/SsiIbFrameFilterWrapper.vhd index 0d48df9667..15dc5c3179 100644 --- a/protocols/ssi/wrappers/SsiIbFrameFilterWrapper.vhd +++ b/protocols/ssi/wrappers/SsiIbFrameFilterWrapper.vhd @@ -25,26 +25,26 @@ entity SsiIbFrameFilterWrapper is DATA_BYTES_G : positive range 1 to 8 := 2; SLAVE_READY_EN_G : boolean := true); port ( - axisClk : in sl; - axisRst : in sl; - sAxisTValid : in sl; - sAxisTData : in slv(63 downto 0); - sAxisTKeep : in slv(7 downto 0); - sAxisTLast : in sl; - sAxisTDest : in slv(3 downto 0); - sAxisSof : in sl; - sAxisEofe : in sl; - sAxisTReady : out sl; - sAxisDropWord : out sl; - sAxisDropFrame : out sl; - mAxisTValid : out sl; - mAxisTData : out slv(63 downto 0); - mAxisTKeep : out slv(7 downto 0); - mAxisTLast : out sl; - mAxisTDest : out slv(3 downto 0); - mAxisSof : out sl; - mAxisEofe : out sl; - mAxisTReady : in sl); + axisClk : in sl; + axisRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(63 downto 0); + sAxisTKeep : in slv(7 downto 0); + sAxisTLast : in sl; + sAxisTDest : in slv(3 downto 0); + sAxisSof : in sl; + sAxisEofe : in sl; + sAxisTReady : out sl; + sAxisDropWord : out sl; + sAxisDropFrame : out sl; + mAxisTValid : out sl; + mAxisTData : out slv(63 downto 0); + mAxisTKeep : out slv(7 downto 0); + mAxisTLast : out sl; + mAxisTDest : out slv(3 downto 0); + mAxisSof : out sl; + mAxisEofe : out sl; + mAxisTReady : in sl); end entity SsiIbFrameFilterWrapper; architecture rtl of SsiIbFrameFilterWrapper is @@ -55,7 +55,7 @@ architecture rtl of SsiIbFrameFilterWrapper is tUserMode => TUSER_FIRST_LAST_C, tDestBits => 4, tUserBits => 2); - constant DATA_WIDTH_C : positive := 8*DATA_BYTES_G; + constant DATA_WIDTH_C : positive := 8*DATA_BYTES_G; signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; @@ -65,21 +65,22 @@ architecture rtl of SsiIbFrameFilterWrapper is begin - sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTDest, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTDest, + sAxisTKeep, sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(DATA_WIDTH_C-1 downto 0) := sAxisTData(DATA_WIDTH_C-1 downto 0); v.tKeep(DATA_BYTES_G-1 downto 0) := sAxisTKeep(DATA_BYTES_G-1 downto 0); - v.tLast := sAxisTLast; - v.tDest(3 downto 0) := sAxisTDest; + v.tLast := sAxisTLast; + v.tDest(3 downto 0) := sAxisTDest; ssiSetUserSof(AXIS_CONFIG_C, v, sAxisSof); ssiSetUserEofe(AXIS_CONFIG_C, v, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; - sAxisTReady <= sAxisSlave.tReady; + sAxisTReady <= sAxisSlave.tReady; mAxisSlave.tReady <= mAxisTReady; mAxisView : process (mAxisMaster) is @@ -93,12 +94,12 @@ begin keepV(DATA_BYTES_G-1 downto 0) := mAxisMaster.tKeep(DATA_BYTES_G-1 downto 0); mAxisTValid <= mAxisMaster.tValid; - mAxisTData <= dataV; - mAxisTKeep <= keepV; - mAxisTLast <= mAxisMaster.tLast; - mAxisTDest <= mAxisMaster.tDest(3 downto 0); - mAxisSof <= ssiGetUserSof(AXIS_CONFIG_C, mAxisMaster); - mAxisEofe <= ssiGetUserEofe(AXIS_CONFIG_C, mAxisMaster); + mAxisTData <= dataV; + mAxisTKeep <= keepV; + mAxisTLast <= mAxisMaster.tLast; + mAxisTDest <= mAxisMaster.tDest(3 downto 0); + mAxisSof <= ssiGetUserSof(AXIS_CONFIG_C, mAxisMaster); + mAxisEofe <= ssiGetUserEofe(AXIS_CONFIG_C, mAxisMaster); end process mAxisView; U_DUT : entity surf.SsiIbFrameFilter diff --git a/protocols/ssi/wrappers/SsiIncrementingTxWrapper.vhd b/protocols/ssi/wrappers/SsiIncrementingTxWrapper.vhd index 8e46ab3c24..8522ff3b32 100644 --- a/protocols/ssi/wrappers/SsiIncrementingTxWrapper.vhd +++ b/protocols/ssi/wrappers/SsiIncrementingTxWrapper.vhd @@ -65,16 +65,16 @@ begin keepV := (others => '0'); dataV(31 downto 0) := mAxisMaster.tData(31 downto 0); - keepV(3 downto 0) := mAxisMaster.tKeep(3 downto 0); + keepV(3 downto 0) := mAxisMaster.tKeep(3 downto 0); mAxisTValid <= mAxisMaster.tValid; - mAxisTData <= dataV; - mAxisTKeep <= keepV; - mAxisTLast <= mAxisMaster.tLast; - mAxisTDest <= mAxisMaster.tDest(7 downto 0); - mAxisTId <= mAxisMaster.tId(7 downto 0); - mAxisSof <= ssiGetUserSof(AXIS_CONFIG_C, mAxisMaster); - mAxisEofe <= ssiGetUserEofe(AXIS_CONFIG_C, mAxisMaster); + mAxisTData <= dataV; + mAxisTKeep <= keepV; + mAxisTLast <= mAxisMaster.tLast; + mAxisTDest <= mAxisMaster.tDest(7 downto 0); + mAxisTId <= mAxisMaster.tId(7 downto 0); + mAxisSof <= ssiGetUserSof(AXIS_CONFIG_C, mAxisMaster); + mAxisEofe <= ssiGetUserEofe(AXIS_CONFIG_C, mAxisMaster); end process mAxisView; U_DUT : entity surf.SsiIncrementingTx diff --git a/protocols/ssi/wrappers/SsiInsertSofWrapper.vhd b/protocols/ssi/wrappers/SsiInsertSofWrapper.vhd index c0a57bbc73..47bcf22732 100644 --- a/protocols/ssi/wrappers/SsiInsertSofWrapper.vhd +++ b/protocols/ssi/wrappers/SsiInsertSofWrapper.vhd @@ -23,33 +23,33 @@ use surf.SsiPkg.all; entity SsiInsertSofWrapper is generic ( - DATA_BYTES_G : positive range 1 to 8 := 2; - TUSER_BITS_G : positive range 2 to 8 := 4; - INSERT_USER_HDR_G : boolean := false; - COMMON_CLK_G : boolean := true; - SLAVE_FIFO_G : boolean := false; - MASTER_FIFO_G : boolean := false; - TUSER_MASK_G : natural range 0 to 255 := 0); + DATA_BYTES_G : positive range 1 to 8 := 2; + TUSER_BITS_G : positive range 2 to 8 := 4; + INSERT_USER_HDR_G : boolean := false; + COMMON_CLK_G : boolean := true; + SLAVE_FIFO_G : boolean := false; + MASTER_FIFO_G : boolean := false; + TUSER_MASK_G : natural range 0 to 255 := 0); port ( - axisClk : in sl; - axisRst : in sl; - sAxisTValid : in sl; - sAxisTData : in slv(63 downto 0); - sAxisTKeep : in slv(7 downto 0); - sAxisTLast : in sl; - sAxisTDest : in slv(3 downto 0); - sAxisSof : in sl; - sAxisEofe : in sl; - sAxisTReady : out sl; - mUserHdr : in slv(63 downto 0); - mAxisTValid : out sl; - mAxisTData : out slv(63 downto 0); - mAxisTKeep : out slv(7 downto 0); - mAxisTLast : out sl; - mAxisTDest : out slv(3 downto 0); - mAxisSof : out sl; - mAxisEofe : out sl; - mAxisTReady : in sl); + axisClk : in sl; + axisRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(63 downto 0); + sAxisTKeep : in slv(7 downto 0); + sAxisTLast : in sl; + sAxisTDest : in slv(3 downto 0); + sAxisSof : in sl; + sAxisEofe : in sl; + sAxisTReady : out sl; + mUserHdr : in slv(63 downto 0); + mAxisTValid : out sl; + mAxisTData : out slv(63 downto 0); + mAxisTKeep : out slv(7 downto 0); + mAxisTLast : out sl; + mAxisTDest : out slv(3 downto 0); + mAxisSof : out sl; + mAxisEofe : out sl; + mAxisTReady : in sl); end entity SsiInsertSofWrapper; architecture rtl of SsiInsertSofWrapper is @@ -67,31 +67,32 @@ architecture rtl of SsiInsertSofWrapper is tDestBits => 4, tUserBits => TUSER_BITS_G); - constant DATA_WIDTH_C : positive := 8*AXIS_CONFIG_C.TDATA_BYTES_C; - constant KEEP_WIDTH_C : positive := AXIS_CONFIG_C.TDATA_BYTES_C; + constant DATA_WIDTH_C : positive := 8*AXIS_CONFIG_C.TDATA_BYTES_C; + constant KEEP_WIDTH_C : positive := AXIS_CONFIG_C.TDATA_BYTES_C; constant TUSER_MASK_C : slv(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0) := buildUserMask; - signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; signal mUserHdrInt : slv(AXI_STREAM_MAX_TDATA_WIDTH_C-1 downto 0) := (others => '0'); begin -- Flatten the cocotb-driven scalar/vector ports into a normal SURF stream. - sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTDest, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTDest, + sAxisTKeep, sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(DATA_WIDTH_C-1 downto 0) := sAxisTData(DATA_WIDTH_C-1 downto 0); v.tKeep(KEEP_WIDTH_C-1 downto 0) := sAxisTKeep(KEEP_WIDTH_C-1 downto 0); - v.tLast := sAxisTLast; - v.tDest(3 downto 0) := sAxisTDest; + v.tLast := sAxisTLast; + v.tDest(3 downto 0) := sAxisTDest; ssiSetUserSof(AXIS_CONFIG_C, v, sAxisSof); ssiSetUserEofe(AXIS_CONFIG_C, v, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; sAxisTReady <= sAxisSlave.tReady; diff --git a/protocols/ssi/wrappers/SsiObFrameFilterWrapper.vhd b/protocols/ssi/wrappers/SsiObFrameFilterWrapper.vhd index 6a590fdf71..23b098731f 100644 --- a/protocols/ssi/wrappers/SsiObFrameFilterWrapper.vhd +++ b/protocols/ssi/wrappers/SsiObFrameFilterWrapper.vhd @@ -26,27 +26,27 @@ entity SsiObFrameFilterWrapper is VALID_THOLD_G : natural := 1; PIPE_STAGES_G : natural := 1); port ( - axisClk : in sl; - axisRst : in sl; - sAxisTValid : in sl; - sAxisTData : in slv(63 downto 0); - sAxisTKeep : in slv(7 downto 0); - sAxisTLast : in sl; - sAxisTDest : in slv(3 downto 0); - sAxisSof : in sl; - sAxisEofe : in sl; - sAxisTReady : out sl; - sTLastEofe : in sl; - mAxisDropWord : out sl; - mAxisDropFrame : out sl; - mAxisTValid : out sl; - mAxisTData : out slv(63 downto 0); - mAxisTKeep : out slv(7 downto 0); - mAxisTLast : out sl; - mAxisTDest : out slv(3 downto 0); - mAxisSof : out sl; - mAxisEofe : out sl; - mAxisTReady : in sl); + axisClk : in sl; + axisRst : in sl; + sAxisTValid : in sl; + sAxisTData : in slv(63 downto 0); + sAxisTKeep : in slv(7 downto 0); + sAxisTLast : in sl; + sAxisTDest : in slv(3 downto 0); + sAxisSof : in sl; + sAxisEofe : in sl; + sAxisTReady : out sl; + sTLastEofe : in sl; + mAxisDropWord : out sl; + mAxisDropFrame : out sl; + mAxisTValid : out sl; + mAxisTData : out slv(63 downto 0); + mAxisTKeep : out slv(7 downto 0); + mAxisTLast : out sl; + mAxisTDest : out slv(3 downto 0); + mAxisSof : out sl; + mAxisEofe : out sl; + mAxisTReady : in sl); end entity SsiObFrameFilterWrapper; architecture rtl of SsiObFrameFilterWrapper is @@ -57,7 +57,7 @@ architecture rtl of SsiObFrameFilterWrapper is tUserMode => TUSER_FIRST_LAST_C, tDestBits => 4, tUserBits => 2); - constant DATA_WIDTH_C : positive := 8*DATA_BYTES_G; + constant DATA_WIDTH_C : positive := 8*DATA_BYTES_G; signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; @@ -67,23 +67,24 @@ architecture rtl of SsiObFrameFilterWrapper is begin - sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTDest, sAxisTKeep, sAxisTLast, sAxisTValid) is + sAxisComb : process (sAxisEofe, sAxisSof, sAxisTData, sAxisTDest, + sAxisTKeep, sAxisTLast, sAxisTValid) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := sAxisTValid; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := sAxisTValid; v.tData(DATA_WIDTH_C-1 downto 0) := sAxisTData(DATA_WIDTH_C-1 downto 0); v.tKeep(DATA_BYTES_G-1 downto 0) := sAxisTKeep(DATA_BYTES_G-1 downto 0); - v.tLast := sAxisTLast; - v.tDest(3 downto 0) := sAxisTDest; + v.tLast := sAxisTLast; + v.tDest(3 downto 0) := sAxisTDest; ssiSetUserSof(AXIS_CONFIG_C, v, sAxisSof); ssiSetUserEofe(AXIS_CONFIG_C, v, sAxisEofe); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; - sAxisTReady <= sAxisSlave.tReady; + sAxisTReady <= sAxisSlave.tReady; sTLastTUser(SSI_EOFE_C) <= sTLastEofe; - mAxisSlave.tReady <= mAxisTReady; + mAxisSlave.tReady <= mAxisTReady; mAxisView : process (mAxisMaster) is variable dataV : slv(63 downto 0); @@ -96,12 +97,12 @@ begin keepV(DATA_BYTES_G-1 downto 0) := mAxisMaster.tKeep(DATA_BYTES_G-1 downto 0); mAxisTValid <= mAxisMaster.tValid; - mAxisTData <= dataV; - mAxisTKeep <= keepV; - mAxisTLast <= mAxisMaster.tLast; - mAxisTDest <= mAxisMaster.tDest(3 downto 0); - mAxisSof <= ssiGetUserSof(AXIS_CONFIG_C, mAxisMaster); - mAxisEofe <= ssiGetUserEofe(AXIS_CONFIG_C, mAxisMaster); + mAxisTData <= dataV; + mAxisTKeep <= keepV; + mAxisTLast <= mAxisMaster.tLast; + mAxisTDest <= mAxisMaster.tDest(3 downto 0); + mAxisSof <= ssiGetUserSof(AXIS_CONFIG_C, mAxisMaster); + mAxisEofe <= ssiGetUserEofe(AXIS_CONFIG_C, mAxisMaster); end process mAxisView; U_DUT : entity surf.SsiObFrameFilter diff --git a/protocols/ssi/wrappers/SsiPrbsWrapper.vhd b/protocols/ssi/wrappers/SsiPrbsWrapper.vhd index 7b67e689da..79db4d5ff2 100644 --- a/protocols/ssi/wrappers/SsiPrbsWrapper.vhd +++ b/protocols/ssi/wrappers/SsiPrbsWrapper.vhd @@ -61,17 +61,17 @@ architecture rtl of SsiPrbsWrapper is return ret; end function; - constant TPD_C : time := 10 ns/12; - constant STATUS_CNT_WIDTH_C : natural := 32; - constant TX_PACKET_LENGTH_C : slv(31 downto 0) := toSlv(64, 32); - constant MEMORY_TYPE_C : string := "block"; - constant GEN_SYNC_FIFO_C : boolean := false; - constant CASCADE_SIZE_C : natural := 1; - constant FIFO_ADDR_WIDTH_C : natural := 9; - constant FIFO_PAUSE_THRESH_C : natural := 2**8; - constant PRBS_SEED_SIZE_C : natural := PRBS_SEED_SIZE_G; - constant PRBS_TAPS_C : NaturalArray := (0 => 31, 1 => 6, 2 => 2, 3 => 1); - constant FORCE_EOFE_C : sl := '0'; + constant TPD_C : time := 10 ns/12; + constant STATUS_CNT_WIDTH_C : natural := 32; + constant TX_PACKET_LENGTH_C : slv(31 downto 0) := toSlv(64, 32); + constant MEMORY_TYPE_C : string := "block"; + constant GEN_SYNC_FIFO_C : boolean := false; + constant CASCADE_SIZE_C : natural := 1; + constant FIFO_ADDR_WIDTH_C : natural := 9; + constant FIFO_PAUSE_THRESH_C : natural := 2**8; + constant PRBS_SEED_SIZE_C : natural := PRBS_SEED_SIZE_G; + constant PRBS_TAPS_C : NaturalArray := (0 => 31, 1 => 6, 2 => 2, 3 => 1); + constant FORCE_EOFE_C : sl := '0'; constant AXI_STREAM_CONFIG_C : AxiStreamConfigType := PrbsAxiStreamConfig(DATA_BYTES_G, TKEEP_COMP_C); constant AXI_PIPE_STAGES_C : natural := 1; diff --git a/protocols/ssi/wrappers/SsiResizeFifoEofeWrapper.vhd b/protocols/ssi/wrappers/SsiResizeFifoEofeWrapper.vhd index 3a05ff4efe..4f21d0ee18 100644 --- a/protocols/ssi/wrappers/SsiResizeFifoEofeWrapper.vhd +++ b/protocols/ssi/wrappers/SsiResizeFifoEofeWrapper.vhd @@ -100,7 +100,7 @@ architecture rtl of SsiResizeFifoEofeWrapper is constant SLAVE_KEEP_WIDTH_C : positive := SLAVE_AXI_CONFIG_C.TDATA_BYTES_C; constant MASTER_KEEP_WIDTH_C : positive := MASTER_AXI_CONFIG_C.TDATA_BYTES_C; - signal axisRst : sl := '0'; + signal axisRst : sl := '0'; signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; @@ -136,14 +136,14 @@ begin S_AXIS_TLAST, S_AXIS_TVALID) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := S_AXIS_TVALID; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := S_AXIS_TVALID; v.tData(SLAVE_DATA_WIDTH_C-1 downto 0) := S_AXIS_TDATA(SLAVE_DATA_WIDTH_C-1 downto 0); v.tKeep(SLAVE_KEEP_WIDTH_C-1 downto 0) := S_AXIS_TKEEP(SLAVE_KEEP_WIDTH_C-1 downto 0); - v.tLast := S_AXIS_TLAST; - v.tDest(3 downto 0) := S_AXIS_TDEST; + v.tLast := S_AXIS_TLAST; + v.tDest(3 downto 0) := S_AXIS_TDEST; ssiSetUserEofe(SLAVE_AXI_CONFIG_C, v, S_AXIS_EOFE); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; U_AxiStreamFifoV2 : entity surf.AxiStreamFifoV2 From aa6bb589d8bb08a74dc12c5e6e8d2af1615e400b Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 1 May 2026 09:36:01 -0700 Subject: [PATCH 73/92] Add version of emacs beautify script that is compatible with zsh for mac. --- scripts/emacs_beautify_all_vhdl_mac.sh | 52 ++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 scripts/emacs_beautify_all_vhdl_mac.sh diff --git a/scripts/emacs_beautify_all_vhdl_mac.sh b/scripts/emacs_beautify_all_vhdl_mac.sh new file mode 100644 index 0000000000..e80bcf18e3 --- /dev/null +++ b/scripts/emacs_beautify_all_vhdl_mac.sh @@ -0,0 +1,52 @@ +#!/bin/zsh +#----------------------------------------------------------------------------- +# This file is part of 'SLAC Firmware Standard Library'. +# It is subject to the license terms in the LICENSE.txt file found in the +# top-level directory of this distribution and at: +# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +# No part of 'SLAC Firmware Standard Library', including this file, +# may be copied, modified, propagated, or distributed except according to +# the terms contained in the LICENSE.txt file. +#----------------------------------------------------------------------------- + +# zsh compatible version of emacs_beautify_all_vhdl.sh for macOS systems where +# zsh is the default user shell. + +setopt null_glob + +# Get the directory of the script +SCRIPT_DIR="${0:A:h}" + +# Define excluded files using an array +EXCLUDE_FILES=() +EXCLUDE_FILES+=("${(@f)$(find "$SCRIPT_DIR/../base/fifo/rtl/xilinx/FifoXpm.vhd" -type f -name "*.vhd")}") +EXCLUDE_FILES+=("${(@f)$(find "$SCRIPT_DIR/../protocols/i2c/rtl/stdlib.vhd" -type f -name "*.vhd")}") +EXCLUDE_FILES+=("${(@f)$(find "$SCRIPT_DIR/../protocols/i2c/rtl/orig" -type f -name "*.vhd")}") + +is_excluded() { + local candidate="$1" + local excluded_file + for excluded_file in "${EXCLUDE_FILES[@]}"; do + if [[ "$candidate" == "$excluded_file" ]]; then + return 0 + fi + done + return 1 +} + +# Find all .vhd files and filter +FILES=("${(@f)$(find "$SCRIPT_DIR/../" -type f -name "*.vhd")}") + +# Process files not in exclude list +for vhd_file in "${FILES[@]}"; do + if ! is_excluded "$vhd_file"; then + echo "Processing: $vhd_file" + emacs --batch "$vhd_file" \ + -l "$SCRIPT_DIR/../.emacs" \ + -f vhdl-beautify-buffer \ + -f vhdl-update-sensitivity-list-buffer \ + -f save-buffer + else + echo "Skipping: $vhd_file" + fi +done From d12f9372a8a42743ed57db1b8a4114326a1dbbde Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 1 May 2026 10:03:31 -0700 Subject: [PATCH 74/92] Bring in latest changes from main regression test branch. --- .../coaxpress/core/rtl/CoaXPressRxLane.vhd | 143 +++++++++++++++++- tests/protocols/coaxpress/README.md | 32 ++-- .../coaxpress/coaxpress_test_utils.py | 37 +++++ .../test_CoaXPressOverFiberBridgeRx.py | 52 +++++++ .../test_CoaXPressOverFiberBridgeTx.py | 80 ++++++++++ tests/protocols/coaxpress/test_CoaXPressRx.py | 32 ++-- .../coaxpress/test_CoaXPressRxLane.py | 97 ++++++++++-- .../coaxpress/test_CoaXPressRxLaneMux.py | 2 +- .../coaxpress/test_CoaXPressTxLsFsm.py | 67 ++++++++ 9 files changed, 506 insertions(+), 36 deletions(-) diff --git a/protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd b/protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd index 0f246e83ec..3e71fcb11d 100644 --- a/protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd +++ b/protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd @@ -25,6 +25,7 @@ use surf.AxiStreamPkg.all; use surf.SsiPkg.all; use surf.CoaXPressPkg.all; use surf.Code8b10bPkg.all; +use surf.CrcPkg.all; entity CoaXPressRxLane is generic ( @@ -61,6 +62,11 @@ architecture rtl of CoaXPressRxLane is CTRL_ACK_S, HEARTBEAT_S, EVENT_ACK_S, + EVENT_DSIZE_UPPER_S, + EVENT_DSIZE_LOWER_S, + EVENT_PAYLOAD_S, + EVENT_CRC_S, + EVENT_EOP_S, STREAM_ID_S, PACKET_TAG_S, DSIZE_UPPER_S, @@ -80,6 +86,7 @@ architecture rtl of CoaXPressRxLane is dsize : slv(15 downto 0); dcnt : slv(15 downto 0); dbgCnt : slv(31 downto 0); + crc : slv(31 downto 0); -- AXIS Interfaces cfgMaster : AxiStreamMasterType; dataMaster : AxiStreamMasterType; @@ -101,6 +108,7 @@ architecture rtl of CoaXPressRxLane is dsize => (others => '0'), dcnt => (others => '0'), dbgCnt => (others => '0'), + crc => (others => '1'), -- AXIS Interfaces cfgMaster => AXI_STREAM_MASTER_INIT_C, dataMaster => AXI_STREAM_MASTER_INIT_C, @@ -112,6 +120,34 @@ architecture rtl of CoaXPressRxLane is signal r : RegType := REG_INIT_C; signal rin : RegType; + function cxpCrcUpdate ( + crcIn : slv(31 downto 0); + data : slv(31 downto 0)) + return slv is + variable crc : slv(31 downto 0); + variable byteXor : slv(7 downto 0); + begin + crc := crcIn; + byteXor := (others => '0'); + for i in 0 to 3 loop + byteXor := crc(31 downto 24) xor bitReverse(data(8*i+7 downto 8*i)); + crc := (crc(23 downto 0) & x"00") xor crcByteLookup(byteXor, CXP_CRC_POLY_C); + end loop; + return crc; + end function cxpCrcUpdate; + + function cxpCrcFinal ( + crcIn : slv(31 downto 0)) + return slv is + variable retVar : slv(31 downto 0); + begin + retVar := (others => '0'); + for i in 0 to 3 loop + retVar(8*i+7 downto 8*i) := bitReverse(crcIn(8*i+7 downto 8*i)); + end loop; + return endianSwap(retVar); + end function cxpCrcFinal; + -- attribute dont_touch : string; -- attribute dont_touch of r : signal is "TRUE"; @@ -189,6 +225,11 @@ begin -- Check for "control acknowledge with tag" elsif (rxData = x"07_07_07_07") then + -- Reset event parser counters + v.ackCnt := 0; + v.dcnt := (others => '0'); + v.dsize := (others => '0'); + v.crc := x"FFFFFFFF"; -- Next State v.state := EVENT_ACK_S; @@ -265,20 +306,26 @@ begin ---------------------------------------------------------------------- when EVENT_ACK_S => -- Check for non-k word - if (rxDataK = x"0") then + if (rxDataK = x"0") + and ((r.ackCnt < 4) + or ((rxData(7 downto 0) = rxData(15 downto 8)) + and (rxData(7 downto 0) = rxData(23 downto 16)) + and (rxData(7 downto 0) = rxData(31 downto 24)))) then + + -- Include event ID and packet tag words in the CRC. + v.crc := cxpCrcUpdate(r.crc, rxData); -- Increment the counter v.ackCnt := r.ackCnt + 1; - -- "Acknowledgment code" index + -- Packet Tag index if (r.ackCnt = 4) then - -- Generate the ACK message w/ package tag - v.eventAck := '1'; + -- Save the packet tag v.eventTag := rxData(7 downto 0); -- Next State - v.state := IDLE_S; + v.state := EVENT_DSIZE_UPPER_S; end if; @@ -289,6 +336,92 @@ begin v.state := IDLE_S; end if; ---------------------------------------------------------------------- + when EVENT_DSIZE_UPPER_S => + -- Check for repeated-byte size upper word + if (rxDataK = x"0") + and (rxData(7 downto 0) = rxData(15 downto 8)) + and (rxData(7 downto 0) = rxData(23 downto 16)) + and (rxData(7 downto 0) = rxData(31 downto 24)) then + -- Save the upper byte of the event payload word count + v.dsize(15 downto 8) := rxData(7 downto 0); + v.crc := cxpCrcUpdate(r.crc, rxData); + -- Next State + v.state := EVENT_DSIZE_LOWER_S; + else + -- Set the flag + v.errDet := '1'; + -- Next State + v.state := IDLE_S; + end if; + ---------------------------------------------------------------------- + when EVENT_DSIZE_LOWER_S => + -- Check for repeated-byte size lower word + if (rxDataK = x"0") + and (rxData(7 downto 0) = rxData(15 downto 8)) + and (rxData(7 downto 0) = rxData(23 downto 16)) + and (rxData(7 downto 0) = rxData(31 downto 24)) then + -- Save the lower byte of the event payload word count + v.dsize(7 downto 0) := rxData(7 downto 0); + v.dcnt := (others => '0'); + v.crc := cxpCrcUpdate(r.crc, rxData); + -- Next State + if (r.dsize(15 downto 8) = 0) and (rxData(7 downto 0) = 0) then + v.state := EVENT_CRC_S; + else + v.state := EVENT_PAYLOAD_S; + end if; + else + -- Set the flag + v.errDet := '1'; + -- Next State + v.state := IDLE_S; + end if; + ---------------------------------------------------------------------- + when EVENT_PAYLOAD_S => + -- Check for event payload word + if (rxDataK = x"0") then + v.crc := cxpCrcUpdate(r.crc, rxData); + -- Check the counter + if (r.dcnt = (r.dsize-1)) then + -- Next State + v.state := EVENT_CRC_S; + else + -- Increment counter + v.dcnt := r.dcnt + 1; + end if; + else + -- Set the flag + v.errDet := '1'; + -- Next State + v.state := IDLE_S; + end if; + ---------------------------------------------------------------------- + when EVENT_CRC_S => + -- Check for CRC word + if (rxDataK = x"0") and (rxData = cxpCrcFinal(r.crc)) then + -- Next State + v.state := EVENT_EOP_S; + else + -- Set the flag + v.errDet := '1'; + -- Next State + v.state := IDLE_S; + end if; + ---------------------------------------------------------------------- + when EVENT_EOP_S => + -- Check for end of packet indication + if (rxDataK = x"F") and (rxData = CXP_EOP_C) then + -- Generate the ACK message w/ packet tag + v.eventAck := '1'; + -- Next State + v.state := IDLE_S; + else + -- Set the flag + v.errDet := '1'; + -- Next State + v.state := IDLE_S; + end if; + ---------------------------------------------------------------------- when HEARTBEAT_S => -- Check for non-k word if (rxDataK = x"0") then diff --git a/tests/protocols/coaxpress/README.md b/tests/protocols/coaxpress/README.md index a8f1a0d24d..0f660eb562 100644 --- a/tests/protocols/coaxpress/README.md +++ b/tests/protocols/coaxpress/README.md @@ -122,22 +122,29 @@ Important limitation: ### Heartbeat and event traffic -Heartbeat and event handling is only partially covered today: +Heartbeat and event handling is still intentionally narrow, but the receive +event parser now checks complete packet framing before acknowledging: - `test_CoaXPressRxLane.py` - checks the current 12-byte heartbeat payload collector - `test_CoaXPressEventAckMsg.py` - covers event acknowledgment generation on the transmit side - `test_CoaXPressRxLane.py` and `test_CoaXPressRx.py` - - drive a fuller event packet shape, but the current receive RTL only - consumes the event prefix through the `Packet Tag` field before returning to - `IDLE` + - drive full event packet framing through event ID, Packet Tag, payload size, + payload words, CRC, and `EOP` + - `CoaXPressRxLane` now acknowledges an event only after the CRC and `EOP` + pass, suppresses bad-CRC events, and recovers for a later clean event + - event payload is validated for framing/CRC but is not exported through a + receive-side payload interface -That means these benches do not yet prove full compliance with: +That means these benches now cover the parser/acknowledgment subset of: - section `9.8.1` event ordering rules - section `9.8.2` event payload parsing -- full event-payload CRC/trailer handling +- event-payload CRC/trailer handling + +They still do not prove an application-facing event-payload delivery contract, +because the current RTL exposes only `eventAck` and `eventTag`. ### Stream data and rectangular image traffic @@ -200,20 +207,23 @@ Current checked-in coverage: - start-word control bits - low-speed rate/update handling - partial-lane low-speed payload fill with CoaXPress idle insertion + - single-lane-enable sweeps with rotating idle fill in the disabled slots - payload packing - `/T/` plus `/I/` termination - `test_CoaXPressOverFiberBridgeRx.py` - RX start-word decode for normal packets and `IO_ACK` - HKP forwarding - negative lane-placement checks for `/S/` and `/Q/` + - lane-0 `/Q/` no-output guardrail, `/E/` packet abort behavior, and recovery + to a following valid low-speed packet - `test_CoaXPressOverFiberBridge.py` - top-level 32b/64b gearbox integration around the bridge leaves Still open on the bridge side: - normative `/Q/` sequence handling beyond the current negative guardrails -- explicit `/E/` error handling -- deeper HKP/data-mix coverage +- fuller `/E/` error semantics beyond the current abort-and-recover guardrail +- deeper HKP/data-mix coverage beyond the current HKP forwarding path - broader lane-0-only control-character sweeps ## Known Limitations @@ -233,9 +243,11 @@ The most important open limits are: - the checked-in known-issue core bench for overflow-vs-FSM-error behavior is skipped by default until the receive-side backpressure interaction is understood and fixed -- receive-side event handling still proves only the current RTL prefix contract +- receive-side event payload is validated for framing/CRC before ACK, but is not + exposed through an application-facing payload interface - trigger coverage still does not include the broader low-speed extra modes or - the full high-speed trigger matrix + the full high-speed trigger matrix, though the low-speed FSM now covers + active-pulse shortening through a runtime `txPulseWidth` update - CXPoF bridge coverage still does not exhaustively cover normative `/Q/`, `/E/`, and the full housekeeping/data mix diff --git a/tests/protocols/coaxpress/coaxpress_test_utils.py b/tests/protocols/coaxpress/coaxpress_test_utils.py index 5a5072f2af..94052d82e8 100644 --- a/tests/protocols/coaxpress/coaxpress_test_utils.py +++ b/tests/protocols/coaxpress/coaxpress_test_utils.py @@ -54,6 +54,8 @@ CXPOF_TERM = 0xFD CXPOF_ERROR = 0xFE +CXP_CRC32_POLY = 0x04C11DB7 + @dataclass class AxisBeat: @@ -89,6 +91,41 @@ def endian_swap32(word: int) -> int: return int.from_bytes((word & 0xFFFFFFFF).to_bytes(4, "little"), "big") +def reverse_bits(value: int, width: int) -> int: + result = 0 + for bit in range(width): + if value & (1 << bit): + result |= 1 << (width - 1 - bit) + return result + + +def _crc_byte_lookup(byte_value: int, *, poly: int = CXP_CRC32_POLY) -> int: + crc = (byte_value & 0xFF) << 24 + for _ in range(8): + if crc & 0x80000000: + crc = ((crc << 1) & 0xFFFFFFFF) ^ poly + else: + crc = (crc << 1) & 0xFFFFFFFF + return crc + + +def cxp_crc_word(words: Sequence[int]) -> int: + # Mirrors the CoaXPressConfig/CoaXPressRxLane CRC convention: initialize the + # CRC to all ones, bit-reverse each byte before lookup, bit-reverse each final + # CRC byte, then endian-swap the driven 32-bit word. + crc = 0xFFFFFFFF + for word in words: + for byte_index in range(4): + byte_value = (word >> (8 * byte_index)) & 0xFF + byte_xor = ((crc >> 24) & 0xFF) ^ reverse_bits(byte_value, 8) + crc = ((crc << 8) & 0xFFFFFFFF) ^ _crc_byte_lookup(byte_xor) + + ret = 0 + for byte_index in range(4): + ret |= reverse_bits((crc >> (8 * byte_index)) & 0xFF, 8) << (8 * byte_index) + return endian_swap32(ret) + + def pack_words(words: list[int], *, word_bits: int = 32) -> int: mask = (1 << word_bits) - 1 value = 0 diff --git a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py index bb8370a2f1..9176897361 100644 --- a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py +++ b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py @@ -32,6 +32,9 @@ CXP_IO_ACK, CXP_PKT_EVENT_ACK, CXP_SOP, + CXPOF_ERROR, + CXPOF_IDLE, + CXPOF_SEQ, CXPOF_START, cycle, repeat_byte, @@ -139,6 +142,55 @@ async def drive(rxd: int, rxc: int) -> None: ] +@cocotb.test() +async def coaxpress_over_fiber_bridge_rx_sequence_error_and_recovery_test(dut): + # The current bridge RX does not implement a normative /Q/ ordered-set path; + # lock it down as a no-output guardrail, then prove an explicit /E/ in a + # payload aborts the packet without emitting a synthetic CXP EOP and the next + # packet still decodes cleanly. + start_clock(dut.clk) + dut.rst.setimmediatevalue(1) + dut.xgmiiRxd.setimmediatevalue(0x07070707) + dut.xgmiiRxc.setimmediatevalue(0xF) + await reset_dut(dut, clk_name="clk", reset_names=("rst",)) + + observed: list[tuple[int, int]] = [] + + async def drive(rxd: int, rxc: int) -> None: + dut.xgmiiRxd.value = rxd + dut.xgmiiRxc.value = rxc + await cycle(dut.clk, 1) + sample = (int(dut.rxData.value), int(dut.rxDataK.value)) + if sample != (CXP_IDLE, CXP_IDLE_K): + observed.append(sample) + + await drive(CXPOF_SEQ | (0x00 << 8) | (0x12 << 16) | (0x34 << 24), 0x1) + await drive(0x07070707, 0xF) + await drive(0x07070707, 0xF) + + await drive(_cxp_start_word(CXP_PKT_EVENT_ACK), 0x1) + await drive(0x11223344, 0x0) + await drive(CXPOF_ERROR | (CXPOF_IDLE << 8) | (CXPOF_IDLE << 16) | (CXPOF_IDLE << 24), 0x1) + await drive(0x07070707, 0xF) + await drive(0x07070707, 0xF) + + await drive(_cxp_start_word(CXP_PKT_EVENT_ACK), 0x1) + await drive(0x55667788, 0x0) + await drive(0x07FD00FD, 0xC) + await drive(0x07070707, 0xF) + await drive(0x07070707, 0xF) + + assert observed == [ + (CXP_SOP, 0xF), + (repeat_byte(CXP_PKT_EVENT_ACK), 0x0), + (0x11223344, 0x0), + (CXP_SOP, 0xF), + (repeat_byte(CXP_PKT_EVENT_ACK), 0x0), + (0x55667788, 0x0), + (CXP_EOP, 0xF), + ] + + def test_CoaXPressOverFiberBridgeRx(): run_surf_vhdl_test( test_file=__file__, diff --git a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeTx.py b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeTx.py index 182b531387..3ae2b30e85 100644 --- a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeTx.py +++ b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeTx.py @@ -25,7 +25,9 @@ from tests.common.regression_utils import run_surf_vhdl_test from tests.protocols.coaxpress.coaxpress_test_utils import ( + CXP_D21_5, CXP_K28_1, + CXP_K28_5, CXPOF_IDLE, CXPOF_START, CXPOF_TERM, @@ -40,6 +42,24 @@ def _start_word(rate: int, update: int) -> int: return CXPOF_START | (sop_ctrl << 8) +IDLE_BYTES = [CXP_K28_5, CXP_K28_1, CXP_K28_1, CXP_D21_5] +IDLE_IS_K = [1, 1, 1, 0] + + +def _ls_slot(byte: int, is_k: int) -> int: + return (byte << 8) | (0x02 if is_k else 0x01) + + +def _bridge_payload_words(byte: int, is_k: int, lane_enable: int, idle_index: int) -> list[int]: + slots: list[int] = [] + for lane in range(4): + if (lane_enable >> lane) & 0x1: + slots.append(_ls_slot(byte, is_k)) + else: + slots.append(_ls_slot(IDLE_BYTES[idle_index], IDLE_IS_K[idle_index])) + return [slots[0] | (slots[1] << 16), slots[2] | (slots[3] << 16)] + + @cocotb.test() async def coaxpress_over_fiber_bridge_tx_packet_format_test(dut): # Reset into the idle state, then emit two packets with different rate and @@ -157,6 +177,66 @@ async def capture_words(count: int) -> None: ] +@cocotb.test() +async def coaxpress_over_fiber_bridge_tx_lane_enable_idle_rotation_test(dut): + # Sweep each single active low-speed lane over consecutive packets. Disabled + # lanes should be filled with the rotating CoaXPress idle sequence, and the + # update bit should only be set on the first same-rate packet after reset. + start_clock(dut.clk) + dut.rst.setimmediatevalue(1) + dut.txLsValid.setimmediatevalue(0) + dut.txLsData.setimmediatevalue(0) + dut.txLsDataK.setimmediatevalue(0) + dut.txLsRate.setimmediatevalue(1) + dut.txLsLaneEn.setimmediatevalue(0x1) + await reset_dut(dut, clk_name="clk", reset_names=("rst",)) + + observed: list[tuple[int, int]] = [] + + async def capture_words(count: int) -> None: + while len(observed) < count: + await RisingEdge(dut.clk) + await Timer(1, unit="ns") + observed.append((int(dut.xgmiiTxd.value), int(dut.xgmiiTxc.value))) + + async def send_byte(byte: int, lane_enable: int) -> None: + dut.txLsLaneEn.value = lane_enable + dut.txLsData.value = byte + dut.txLsDataK.value = 0 + dut.txLsValid.value = 1 + await RisingEdge(dut.clk) + await Timer(1, unit="ns") + dut.txLsValid.value = 0 + await cycle(dut.clk, 4) + + capture = cocotb.start_soon(capture_words(32)) + for index, lane_enable in enumerate((0x1, 0x2, 0x4, 0x8)): + await send_byte(0xA0 + index, lane_enable) + await capture + + starts: list[tuple[int, list[tuple[int, int]]]] = [] + for index in range(len(observed) - 3): + word, control = observed[index] + if control == 0x1 and (word & 0xFF) == CXPOF_START: + starts.append((word, observed[index : index + 4])) + + assert len(starts) >= 4, observed + for packet_index, (start_word, packet) in enumerate(starts[:4]): + expected_update = 1 if packet_index == 0 else 0 + expected_payload = _bridge_payload_words( + 0xA0 + packet_index, + 0, + 1 << packet_index, + packet_index, + ) + assert start_word == _start_word(rate=1, update=expected_update) + assert packet[1:] == [ + (expected_payload[0], 0x0), + (expected_payload[1], 0x0), + ((CXPOF_IDLE << 24) | (CXPOF_TERM << 16), 0xC), + ] + + def test_CoaXPressOverFiberBridgeTx(): run_surf_vhdl_test( test_file=__file__, diff --git a/tests/protocols/coaxpress/test_CoaXPressRx.py b/tests/protocols/coaxpress/test_CoaXPressRx.py index 5567e1e5a4..fcef05d0e0 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRx.py +++ b/tests/protocols/coaxpress/test_CoaXPressRx.py @@ -42,6 +42,7 @@ CXP_PKT_IMAGE_LINE, CXP_SOP, append_snapshot_if_valid, + cxp_crc_word, find_subsequence, pack_words, reset_signals, @@ -114,6 +115,20 @@ ] +def _event_crc_words(*, event_bytes: tuple[int, int, int, int], packet_tag: int, payload_words: list[int]) -> list[int]: + crc_inputs = [ + *[repeat_byte(byte) for byte in event_bytes], + repeat_byte(packet_tag), + repeat_byte((len(payload_words) >> 8) & 0xFF), + repeat_byte(len(payload_words) & 0xFF), + *payload_words, + ] + return [ + *crc_inputs, + cxp_crc_word(crc_inputs), + ] + + def _pack_lane_nibbles(values: list[int]) -> int: packed = 0 for index, value in enumerate(values): @@ -464,15 +479,14 @@ async def coaxpress_rx_one_lane_integration_test(dut): (CXP_EOP, 0xF), (CXP_SOP, 0xF), (repeat_byte(CXP_PKT_EVENT), 0x0), - (repeat_byte(0x10), 0x0), - (repeat_byte(0x11), 0x0), - (repeat_byte(0x12), 0x0), - (repeat_byte(0x13), 0x0), - (repeat_byte(0x5A), 0x0), - (0x00010000, 0x0), - (repeat_byte(0x00), 0x0), - (0x11223344, 0x0), - (0xA5A5A5A5, 0x0), + *[ + (word, 0x0) + for word in _event_crc_words( + event_bytes=(0x10, 0x11, 0x12, 0x13), + packet_tag=0x5A, + payload_words=[0x11223344], + ) + ], (CXP_EOP, 0xF), (CXP_IO_ACK, 0xF), (repeat_byte(0x01), 0x0), diff --git a/tests/protocols/coaxpress/test_CoaXPressRxLane.py b/tests/protocols/coaxpress/test_CoaXPressRxLane.py index 732b5c3d2c..7925977217 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRxLane.py +++ b/tests/protocols/coaxpress/test_CoaXPressRxLane.py @@ -22,7 +22,6 @@ # exposes only master-side pulse semantics with no backpressure input. import cocotb -import pytest from tests.common.regression_utils import run_surf_vhdl_test from tests.protocols.coaxpress.coaxpress_test_utils import ( @@ -37,6 +36,7 @@ CXP_PKT_STREAM_DATA, CXP_SOP, cycle, + cxp_crc_word, repeat_byte, reset_dut, send_rx_word, @@ -44,6 +44,20 @@ ) +def _event_crc_words(*, event_bytes: tuple[int, int, int, int], packet_tag: int, payload_words: list[int]) -> list[int]: + crc_inputs = [ + *[repeat_byte(byte) for byte in event_bytes], + repeat_byte(packet_tag), + repeat_byte((len(payload_words) >> 8) & 0xFF), + repeat_byte(len(payload_words) & 0xFF), + *payload_words, + ] + return [ + *crc_inputs, + cxp_crc_word(crc_inputs), + ] + + @cocotb.test() async def coaxpress_rx_lane_stream_and_io_ack_test(dut): start_clock(dut.rxClk) @@ -169,18 +183,12 @@ async def drive(data: int, data_k: int, *, link_up: int = 1) -> None: await drive(CXP_EOP, 0xF) # Drive a fuller event packet shape. The current RTL only consumes the - # prefix through the Packet Tag field, where it exports the tag and returns - # to IDLE; later size/data/trailer words are present to keep the on-wire - # stimulus aligned to the spec framing. + # prefix and payload internally, then exports the tag only after the CRC and + # EOP trailer have been validated. await drive(CXP_SOP, 0xF) await drive(repeat_byte(CXP_PKT_EVENT), 0x0) - for word in (0x10, 0x11, 0x12, 0x13): - await drive(repeat_byte(word), 0x0) - await drive(repeat_byte(0x5A), 0x0) - await drive(0x00010000, 0x0) - await drive(repeat_byte(0x00), 0x0) - await drive(0x11223344, 0x0) - await drive(0xA5A5A5A5, 0x0) + for word in _event_crc_words(event_bytes=(0x10, 0x11, 0x12, 0x13), packet_tag=0x5A, payload_words=[0x11223344]): + await drive(word, 0x0) await drive(CXP_EOP, 0xF) # A truncated event prefix must not raise a second event pulse. @@ -205,6 +213,73 @@ async def drive(data: int, data_k: int, *, link_up: int = 1) -> None: ] +@cocotb.test() +async def coaxpress_rx_lane_event_payload_crc_guardrail_test(dut): + start_clock(dut.rxClk) + dut.rxRst.setimmediatevalue(1) + dut.rxLinkUp.setimmediatevalue(1) + dut.rxData.setimmediatevalue(CXP_IDLE) + dut.rxDataK.setimmediatevalue(CXP_IDLE_K) + await reset_dut(dut) + + cfg_beats: list[dict[str, int]] = [] + data_beats: list[dict[str, int]] = [] + heartbeat_beats: list[dict[str, int]] = [] + event_tags: list[int] = [] + + async def drive(data: int, data_k: int) -> None: + await send_rx_word(dut, data=data, data_k=data_k, clk=dut.rxClk) + if int(dut.cfgTValid.value) == 1: + cfg_beats.append({"cfgTData": int(dut.cfgTData.value)}) + if int(dut.dataTValid.value) == 1: + data_beats.append( + { + "dataTData": int(dut.dataTData.value), + "dataTUser": int(dut.dataTUser.value), + "dataTLast": int(dut.dataTLast.value), + } + ) + if int(dut.heartbeatTValid.value) == 1: + heartbeat_beats.append({"heartbeatTData": int(dut.heartbeatTData.value)}) + if int(dut.eventAck.value) == 1: + event_tags.append(int(dut.eventTag.value)) + + # The receive-lane RTL validates the event payload count, CRC, and EOP before + # acknowledging the tag. The payload is intentionally not forwarded anywhere. + await drive(CXP_SOP, 0xF) + await drive(repeat_byte(CXP_PKT_EVENT), 0x0) + for word in _event_crc_words( + event_bytes=(0xA0, 0xA1, 0xA2, 0xA3), + packet_tag=0x6D, + payload_words=[0x11223344, 0x55667788], + ): + await drive(word, 0x0) + await drive(CXP_EOP, 0xF) + + # A bad CRC must suppress the acknowledgment and still leave the parser ready + # for a later clean event. + await drive(CXP_SOP, 0xF) + await drive(repeat_byte(CXP_PKT_EVENT), 0x0) + bad_crc_words = _event_crc_words(event_bytes=(0x90, 0x91, 0x92, 0x93), packet_tag=0x55, payload_words=[0x0BADCAFE]) + for word in [*bad_crc_words[:-1], bad_crc_words[-1] ^ 0x00000001]: + await drive(word, 0x0) + await drive(CXP_EOP, 0xF) + + # A later zero-payload event must still be accepted, proving the ignored + # bad-CRC packet did not leave stale parser state behind. + await drive(CXP_SOP, 0xF) + await drive(repeat_byte(CXP_PKT_EVENT), 0x0) + for word in _event_crc_words(event_bytes=(0xB0, 0xB1, 0xB2, 0xB3), packet_tag=0x7E, payload_words=[]): + await drive(word, 0x0) + await drive(CXP_EOP, 0xF) + await drive(CXP_IDLE, CXP_IDLE_K) + + assert event_tags == [0x6D, 0x7E] + assert cfg_beats == [] + assert data_beats == [] + assert heartbeat_beats == [] + + @cocotb.test() async def coaxpress_rx_lane_error_recovery_test(dut): start_clock(dut.rxClk) diff --git a/tests/protocols/coaxpress/test_CoaXPressRxLaneMux.py b/tests/protocols/coaxpress/test_CoaXPressRxLaneMux.py index 220aa18635..bba263f324 100644 --- a/tests/protocols/coaxpress/test_CoaXPressRxLaneMux.py +++ b/tests/protocols/coaxpress/test_CoaXPressRxLaneMux.py @@ -26,7 +26,7 @@ from cocotb.triggers import RisingEdge, Timer from tests.common.regression_utils import env_int, parameter_case, run_surf_vhdl_test -from tests.protocols.coaxpress.coaxpress_test_utils import cycle, pack_words, reset_dut, start_clock +from tests.protocols.coaxpress.coaxpress_test_utils import pack_words, reset_dut, start_clock def _set_lane_inputs(dut, lane_beats, *, num_lanes: int) -> None: diff --git a/tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py b/tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py index e6d9ec3d43..bdddc6ada7 100644 --- a/tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py +++ b/tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py @@ -83,6 +83,19 @@ async def _pulse_trigger(dut) -> None: dut.txTrig.value = 0 +def _trigger_window(payload: list[tuple[int, int]], *, asserted: bool, inverted: bool) -> bool: + if len(payload) != 6: + return False + link_trigger0 = [(CXP_K28_2, 1), (CXP_K28_4, 1), (CXP_K28_4, 1)] + link_trigger1 = [(CXP_K28_4, 1), (CXP_K28_2, 1), (CXP_K28_2, 1)] + expected_prefix = link_trigger1 if asserted == inverted else link_trigger0 + return ( + payload[:3] == expected_prefix + and payload[3][1] == payload[4][1] == payload[5][1] == 0 + and payload[3][0] == payload[4][0] == payload[5][0] + ) + + @cocotb.test() async def coaxpress_tx_ls_fsm_idle_and_config_cadence_test(dut): # Start from reset with config bytes already queued so the FSM proves it @@ -188,6 +201,60 @@ async def coaxpress_tx_ls_fsm_rate0_inverted_trigger_test(dut): assert any((data, is_k) == IDLE_SEQUENCE[0] for _, data, is_k in strobes[6:]) +@cocotb.test() +async def coaxpress_tx_ls_fsm_pulse_width_update_terminates_active_trigger_test(dut): + # Start with a long trigger pulse, then shorten txPulseWidth after the assert + # message has completed. The RTL should force the active pulse to terminate + # quickly instead of waiting for the original long timeout. + start_clock(dut.txClk) + dut.txRst.setimmediatevalue(1) + dut.cfgTValid.setimmediatevalue(0) + dut.cfgTData.setimmediatevalue(0) + dut.cfgTUser.setimmediatevalue(0) + dut.txTrig.setimmediatevalue(0) + dut.txTrigInv.setimmediatevalue(0) + dut.txPulseWidth.setimmediatevalue(1000) + dut.txRate.setimmediatevalue(1) + await reset_dut(dut, clk_name="txClk", reset_names=("txRst",)) + + await _pulse_trigger(dut) + + strobes: list[tuple[int, int, int]] = [] + pulse_width_update_cycle = None + asserted_start = None + deasserted_start = None + tx_trig_drop_seen = False + + for cycle_index in range(1800): + await RisingEdge(dut.txClk) + await Timer(1, unit="ns") + if int(dut.txTrigDrop.value) == 1: + tx_trig_drop_seen = True + if int(dut.txStrobe.value) == 1: + strobes.append((cycle_index, int(dut.txData.value), int(dut.txDataK.value))) + + for start in range(max(0, len(strobes) - 6), len(strobes) - 5): + payload = [(data, is_k) for _, data, is_k in strobes[start : start + 6]] + if asserted_start is None and _trigger_window(payload, asserted=True, inverted=False): + asserted_start = strobes[start][0] + elif pulse_width_update_cycle is not None and _trigger_window(payload, asserted=False, inverted=False): + deasserted_start = strobes[start][0] + break + + if asserted_start is not None and pulse_width_update_cycle is None and len(strobes) >= 6: + dut.txPulseWidth.value = 20 + pulse_width_update_cycle = cycle_index + + if deasserted_start is not None: + break + + assert asserted_start is not None, strobes + assert pulse_width_update_cycle is not None + assert deasserted_start is not None, strobes + assert deasserted_start - pulse_width_update_cycle < 200 + assert not tx_trig_drop_seen + + def test_CoaXPressTxLsFsm(): run_surf_vhdl_test( test_file=__file__, From 7973120f7961a1d854cc4c6a4f9d6fa3d9bbf537 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 1 May 2026 10:21:32 -0700 Subject: [PATCH 75/92] Fix indentation. --- axi/axi-stream/rtl/AxiStreamTimer.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/axi/axi-stream/rtl/AxiStreamTimer.vhd b/axi/axi-stream/rtl/AxiStreamTimer.vhd index c1f93ef215..757ffa775f 100644 --- a/axi/axi-stream/rtl/AxiStreamTimer.vhd +++ b/axi/axi-stream/rtl/AxiStreamTimer.vhd @@ -30,7 +30,7 @@ entity AxiStreamTimer is TPD_G : time := 1 ns; NUM_STREAMS_G : integer range 1 to 8 := 1; NUM_EVENT_G : integer range 1 to 16 := 1 - ); + ); port ( -- AXI-Stream interfaces axisClk : in sl; From 0e9ad04b57331a096466530fa75285c55d19a216 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 1 May 2026 11:07:46 -0700 Subject: [PATCH 76/92] Add more test coverage against spec. --- tests/protocols/coaxpress/README.md | 21 ++-- .../test_CoaXPressOverFiberBridgeRx.py | 103 ++++++++++++++++-- 2 files changed, 105 insertions(+), 19 deletions(-) diff --git a/tests/protocols/coaxpress/README.md b/tests/protocols/coaxpress/README.md index 0f660eb562..e3f31e4a85 100644 --- a/tests/protocols/coaxpress/README.md +++ b/tests/protocols/coaxpress/README.md @@ -212,8 +212,8 @@ Current checked-in coverage: - `/T/` plus `/I/` termination - `test_CoaXPressOverFiberBridgeRx.py` - RX start-word decode for normal packets and `IO_ACK` - - HKP forwarding - - negative lane-placement checks for `/S/` and `/Q/` + - HKP forwarding, including a housekeeping-to-payload transition + - negative lane-placement checks for `/S/`, `/Q/`, `/T/`, and `/E/` - lane-0 `/Q/` no-output guardrail, `/E/` packet abort behavior, and recovery to a following valid low-speed packet - `test_CoaXPressOverFiberBridge.py` @@ -221,10 +221,10 @@ Current checked-in coverage: Still open on the bridge side: -- normative `/Q/` sequence handling beyond the current negative guardrails -- fuller `/E/` error semantics beyond the current abort-and-recover guardrail -- deeper HKP/data-mix coverage beyond the current HKP forwarding path -- broader lane-0-only control-character sweeps +- normative `/Q/` sequence handling beyond the current no-output/recovery guardrails +- fuller `/E/` error semantics beyond malformed-placement and abort-and-recover guardrails +- full housekeeping protocol semantics beyond raw HKP forwarding and the current + HKP-to-payload transition check ## Known Limitations @@ -249,20 +249,23 @@ The most important open limits are: the full high-speed trigger matrix, though the low-speed FSM now covers active-pulse shortening through a runtime `txPulseWidth` update - CXPoF bridge coverage still does not exhaustively cover normative `/Q/`, - `/E/`, and the full housekeeping/data mix + `/E/`, and full housekeeping protocol semantics ## Running The Slice Typical local commands: ```bash -./.venv/bin/python -m pytest -n 0 -q tests/protocols/coaxpress +./.venv/bin/python -m pytest -n auto --dist=worksteal -q tests/protocols/coaxpress ``` Focused receive-path rerun: ```bash -./.venv/bin/python -m pytest -n 0 -q \ +./.venv/bin/python -m pytest -n auto --dist=worksteal -q \ tests/protocols/coaxpress/test_CoaXPressRxLane.py \ tests/protocols/coaxpress/test_CoaXPressRx.py ``` + +Use `-n 0` only when debugging a single cocotb simulation or preserving serial +log ordering is more important than runtime. diff --git a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py index 9176897361..4b69851630 100644 --- a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py +++ b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py @@ -9,16 +9,15 @@ ############################################################################## # Test methodology: -# - Sweep: Exercise the bridge RX on the two CoaXPress receive-side cases the -# current RTL decodes explicitly from the start word: normal low-speed -# packets and `IO_ACK`. -# - Stimulus: Drive one CXPoF start/payload/terminate sequence that encodes a -# serialized CoaXPress packet, then drive a separate start/terminate sequence -# that encodes an `IO_ACK`. -# - Checks: The bridge must reconstruct the repeated-byte `SOP`, packet-type, -# payload, and `EOP` words for the first packet, emit the standalone -# `IO_ACK` word for the second packet, and otherwise remain in the CoaXPress -# idle state. +# - Sweep: Exercise bridge RX low-speed packet decode, `IO_ACK`, HKP forwarding, +# HKP-to-payload transition, misplaced control-character guardrails, `/Q/` +# no-output behavior, `/E/` abort behavior, and recovery to a later packet. +# - Stimulus: Drive CXPoF start/payload/terminate sequences, housekeeping start +# words, lane-misplaced `/S/`, `/Q/`, `/T/`, and `/E/` controls, lane-0 `/Q/`, +# and an explicit `/E/` during an active low-speed packet. +# - Checks: The bridge must reconstruct repeated-byte `SOP`, packet-type, +# payload, and `EOP` words for valid packets, emit standalone `IO_ACK`, forward +# raw HKP words, suppress malformed control traffic, and recover cleanly. # - Timing: The bench samples the reconstructed CXP word stream every cycle so # it checks the bridge's real shift-register latency and output ordering. @@ -36,6 +35,7 @@ CXPOF_IDLE, CXPOF_SEQ, CXPOF_START, + CXPOF_TERM, cycle, repeat_byte, reset_dut, @@ -191,6 +191,89 @@ async def drive(rxd: int, rxc: int) -> None: ] +@cocotb.test() +async def coaxpress_over_fiber_bridge_rx_hkp_then_payload_mix_test(dut): + # A housekeeping start word may be followed by one raw K-coded HKP word and + # then normal data/EOP handling. This locks down the current RTL contract for + # the HKP-to-payload transition without claiming full housekeeping semantics. + start_clock(dut.clk) + dut.rst.setimmediatevalue(1) + dut.xgmiiRxd.setimmediatevalue(0x07070707) + dut.xgmiiRxc.setimmediatevalue(0xF) + await reset_dut(dut, clk_name="clk", reset_names=("rst",)) + + observed: list[tuple[int, int]] = [] + + async def drive(rxd: int, rxc: int) -> None: + dut.xgmiiRxd.value = rxd + dut.xgmiiRxc.value = rxc + await cycle(dut.clk, 1) + sample = (int(dut.rxData.value), int(dut.rxDataK.value)) + if sample != (CXP_IDLE, CXP_IDLE_K): + observed.append(sample) + + hkp_word = 0x9C5C3CBC + await drive(CXPOF_START | (0x81 << 8), 0x1) + await drive(hkp_word, 0xF) + await drive(0x10203040, 0x0) + await drive(0x07FD00FD, 0xC) + await drive(0x07070707, 0xF) + await drive(0x07070707, 0xF) + + assert observed == [ + (hkp_word, 0xF), + (0x10203040, 0x0), + (CXP_EOP, 0xF), + ] + + +@cocotb.test() +async def coaxpress_over_fiber_bridge_rx_control_lane_guardrail_sweep_test(dut): + # `/S/`, `/Q/`, `/T/`, and `/E/` are lane-sensitive XGMII control bytes. + # Misplaced control bytes should not leak any CoaXPress words, and a later + # valid low-speed packet must still decode. + start_clock(dut.clk) + dut.rst.setimmediatevalue(1) + dut.xgmiiRxd.setimmediatevalue(0x07070707) + dut.xgmiiRxc.setimmediatevalue(0xF) + await reset_dut(dut, clk_name="clk", reset_names=("rst",)) + + observed: list[tuple[int, int]] = [] + + async def drive(rxd: int, rxc: int) -> None: + dut.xgmiiRxd.value = rxd + dut.xgmiiRxc.value = rxc + await cycle(dut.clk, 1) + sample = (int(dut.rxData.value), int(dut.rxDataK.value)) + if sample != (CXP_IDLE, CXP_IDLE_K): + observed.append(sample) + + for control_byte in (CXPOF_START, CXPOF_SEQ, CXPOF_ERROR): + for lane in (1, 2, 3): + await drive(0x07070707 | (control_byte << (8 * lane)), 1 << lane) + await drive(0x07070707, 0xF) + + # `/T/` outside an active packet is also malformed for this bridge input. It + # is swept separately because lane 2 is valid only as part of a terminate + # word once a payload is already active. + for lane in (0, 1, 2, 3): + await drive(0x07070707 | (CXPOF_TERM << (8 * lane)), 1 << lane) + await drive(0x07070707, 0xF) + + await drive(_cxp_start_word(CXP_PKT_EVENT_ACK), 0x1) + await drive(0xA1B2C3D4, 0x0) + await drive(0x07FD00FD, 0xC) + await drive(0x07070707, 0xF) + await drive(0x07070707, 0xF) + + assert observed == [ + (CXP_SOP, 0xF), + (repeat_byte(CXP_PKT_EVENT_ACK), 0x0), + (0xA1B2C3D4, 0x0), + (CXP_EOP, 0xF), + ] + + def test_CoaXPressOverFiberBridgeRx(): run_surf_vhdl_test( test_file=__file__, From 71d6202cfdc70dba69f479ac3fd6f1b3d2ec0a4c Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 1 May 2026 11:31:05 -0700 Subject: [PATCH 77/92] /E/ abort and recovery through the 64b-to-32b gearbox HKP-to-payload mix through the top-level bridge lane-0 /Q/ no-output guardrail plus recovery to a valid packet --- tests/protocols/coaxpress/README.md | 2 + .../test_CoaXPressOverFiberBridge.py | 180 +++++++++++++++--- 2 files changed, 156 insertions(+), 26 deletions(-) diff --git a/tests/protocols/coaxpress/README.md b/tests/protocols/coaxpress/README.md index e3f31e4a85..c1633fb190 100644 --- a/tests/protocols/coaxpress/README.md +++ b/tests/protocols/coaxpress/README.md @@ -218,6 +218,8 @@ Current checked-in coverage: to a following valid low-speed packet - `test_CoaXPressOverFiberBridge.py` - top-level 32b/64b gearbox integration around the bridge leaves + - RX-side 64b gearbox coverage for `/E/` abort/recovery, HKP-to-payload + transition, and lane-0 `/Q/` no-output/recovery guardrails Still open on the bridge side: diff --git a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridge.py b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridge.py index 247790f36a..75e655f89b 100644 --- a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridge.py +++ b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridge.py @@ -10,15 +10,16 @@ # Test methodology: # - Sweep: Exercise the top-level CoaXPress-over-Fiber bridge across both its -# transmit and receive halves so the surrounding async gearboxes are covered, -# not only the inner 32-bit bridge leaves. +# transmit and receive halves, including RX packet decode, HKP/data mixing, +# lane-0 `/Q/` no-output behavior, and `/E/` abort/recovery, so the +# surrounding async gearboxes are covered, not only the inner 32-bit leaves. # - Stimulus: Inject one low-speed transmit byte on the 312 MHz CXP side and, -# separately, inject one packetized 64-bit XGMII receive sequence on the 156 -# MHz fiber side. +# separately, inject packetized, housekeeping, sequence, and error-bearing +# 64-bit XGMII receive sequences on the 156 MHz fiber side. # - Checks: The bridge must pack the inner 32-bit TX sequence into the # expected two 64-bit XGMII words and must unpack the RX 64-bit XGMII words -# back into the expected CoaXPress `SOP`, packet-type, payload, and `EOP` -# words. +# back into the expected CoaXPress `SOP`, packet-type, payload, HKP, and +# `EOP` words while suppressing unsupported `/Q/` and aborted `/E/` traffic. # - Timing: The bench samples both sides on their native clocks and searches # the resulting streams for the expected ordered windows, which keeps the # checks robust to gearbox latency while still validating real output order. @@ -33,7 +34,9 @@ CXP_IDLE_K, CXP_PKT_EVENT_ACK, CXP_SOP, + CXPOF_ERROR, CXPOF_IDLE, + CXPOF_SEQ, CXPOF_START, CXPOF_TERM, cycle, @@ -52,17 +55,23 @@ def _tx_start_word(rate: int, update: int) -> int: def _rx_start_word(packet_byte: int) -> int: return CXPOF_START | (0x80 << 8) | ((CXP_SOP & 0xFF) << 16) | (packet_byte << 24) -@cocotb.test() -async def coaxpress_over_fiber_bridge_top_level_integration_test(dut): - # Run the 312 MHz and 156 MHz domains at a 2:1 ratio so the async gearboxes - # see the intended width-conversion cadence while still operating on - # independent clocks. + +def _rx_hkp_start_word() -> int: + return CXPOF_START | (0x81 << 8) + + +def _idle64() -> int: + return int.from_bytes(bytes([CXPOF_IDLE] * 8), "little") + + +async def _setup_bridge(dut) -> None: + # Keep all four bridge clocks running so both async gearboxes are in a + # realistic environment even when a test only stimulates the RX side. start_clock(dut.txClk312, period_ns=4.0) start_clock(dut.txClk156, period_ns=8.0) start_clock(dut.rxClk312, period_ns=4.0) start_clock(dut.rxClk156, period_ns=8.0) - idle64 = int.from_bytes(bytes([CXPOF_IDLE] * 8), "little") set_initial_values( dut, { @@ -71,14 +80,46 @@ async def coaxpress_over_fiber_bridge_top_level_integration_test(dut): "txLsDataK": 0, "txLsLaneEn": 0xF, "txLsRate": 1, - "xgmiiRxd": idle64, + "xgmiiRxd": _idle64(), "xgmiiRxc": 0xFF, }, ) - await reset_signals(dut, clk=dut.txClk312, reset_names=("txRst312", "rxRst312"), assert_cycles=10, release_cycles=5) + await reset_signals( + dut, + clk=dut.txClk312, + reset_names=("txRst312", "rxRst312"), + assert_cycles=10, + release_cycles=5, + ) await cycle(dut.txClk312, 6) await cycle(dut.rxClk156, 2) + +async def _drive_rx64(dut, rxd: int, rxc: int) -> None: + dut.xgmiiRxd.value = rxd + dut.xgmiiRxc.value = rxc + await RisingEdge(dut.rxClk156) + await Timer(1, unit="ns") + + +async def _capture_rx_words(dut, *, cycles: int) -> list[tuple[int, int]]: + observed: list[tuple[int, int]] = [] + for _ in range(cycles): + await RisingEdge(dut.rxClk312) + await Timer(1, unit="ns") + sample = (int(dut.rxData.value), int(dut.rxDataK.value)) + if sample != (CXP_IDLE, CXP_IDLE_K): + observed.append(sample) + return observed + + +@cocotb.test() +async def coaxpress_over_fiber_bridge_top_level_integration_test(dut): + # Run the 312 MHz and 156 MHz domains at a 2:1 ratio so the async gearboxes + # see the intended width-conversion cadence while still operating on + # independent clocks. + await _setup_bridge(dut) + tx_observed: list[tuple[int, int]] = [] rx_observed: list[tuple[int, int]] = [] @@ -109,16 +150,9 @@ async def capture_rx_words(cycles: int) -> None: dut.txLsValid.value = 0 await cycle(dut.rxClk156, 3) - dut.xgmiiRxd.value = (_rx_start_word(CXP_PKT_EVENT_ACK) | (0x11223344 << 32)) - dut.xgmiiRxc.value = 0x01 - await RisingEdge(dut.rxClk156) - await Timer(1, unit="ns") - dut.xgmiiRxd.value = (0x07FD00FD | (repeat_byte(CXPOF_IDLE) << 32)) - dut.xgmiiRxc.value = 0xFC - await RisingEdge(dut.rxClk156) - await Timer(1, unit="ns") - dut.xgmiiRxd.value = idle64 - dut.xgmiiRxc.value = 0xFF + await _drive_rx64(dut, _rx_start_word(CXP_PKT_EVENT_ACK) | (0x11223344 << 32), 0x01) + await _drive_rx64(dut, 0x07FD00FD | (repeat_byte(CXPOF_IDLE) << 32), 0xFC) + await _drive_rx64(dut, _idle64(), 0xFF) await tx_capture await rx_capture @@ -134,8 +168,102 @@ async def capture_rx_words(cycles: int) -> None: (CXP_EOP, 0xF), ] - assert find_subsequence(tx_observed, tx_expected) is not None, f"missing TX gearbox sequence in observed stream: {tx_observed}" - assert find_subsequence(rx_observed, rx_expected) is not None, f"missing RX gearbox sequence in observed stream: {rx_observed}" + assert find_subsequence(tx_observed, tx_expected) is not None, ( + f"missing TX gearbox sequence in observed stream: {tx_observed}" + ) + assert find_subsequence(rx_observed, rx_expected) is not None, ( + f"missing RX gearbox sequence in observed stream: {rx_observed}" + ) + + +@cocotb.test() +async def coaxpress_over_fiber_bridge_top_rx_error_abort_and_recovery_test(dut): + await _setup_bridge(dut) + + rx_capture = cocotb.start_soon(_capture_rx_words(dut, cycles=64)) + + # Start a valid low-speed packet, then inject `/E/` as the next 32-bit word. + # The first packet must not receive a synthetic CXP EOP. + await _drive_rx64(dut, _rx_start_word(CXP_PKT_EVENT_ACK) | (0x11223344 << 32), 0x01) + await _drive_rx64( + dut, + CXPOF_ERROR + | (CXPOF_IDLE << 8) + | (CXPOF_IDLE << 16) + | (CXPOF_IDLE << 24) + | (_idle64() & 0xFFFFFFFF00000000), + 0xF1, + ) + await _drive_rx64(dut, _idle64(), 0xFF) + + # A later clean packet must still cross the 64b-to-32b gearbox and decode. + await _drive_rx64(dut, _rx_start_word(CXP_PKT_EVENT_ACK) | (0x55667788 << 32), 0x01) + await _drive_rx64(dut, 0x07FD00FD | (repeat_byte(CXPOF_IDLE) << 32), 0xFC) + await _drive_rx64(dut, _idle64(), 0xFF) + + rx_observed = await rx_capture + rx_expected = [ + (CXP_SOP, 0xF), + (repeat_byte(CXP_PKT_EVENT_ACK), 0x0), + (0x11223344, 0x0), + (CXP_SOP, 0xF), + (repeat_byte(CXP_PKT_EVENT_ACK), 0x0), + (0x55667788, 0x0), + (CXP_EOP, 0xF), + ] + assert find_subsequence(rx_observed, rx_expected) is not None, ( + f"missing RX /E/ recovery sequence: {rx_observed}" + ) + + +@cocotb.test() +async def coaxpress_over_fiber_bridge_top_rx_hkp_then_payload_mix_test(dut): + await _setup_bridge(dut) + + rx_capture = cocotb.start_soon(_capture_rx_words(dut, cycles=48)) + + hkp_word = 0x9C5C3CBC + await _drive_rx64(dut, _rx_hkp_start_word() | (hkp_word << 32), 0xF1) + await _drive_rx64(dut, 0x10203040 | (0x07FD00FD << 32), 0xC0) + await _drive_rx64(dut, _idle64(), 0xFF) + + rx_observed = await rx_capture + rx_expected = [ + (hkp_word, 0xF), + (0x10203040, 0x0), + (CXP_EOP, 0xF), + ] + assert find_subsequence(rx_observed, rx_expected) is not None, f"missing RX HKP/data sequence: {rx_observed}" + + +@cocotb.test() +async def coaxpress_over_fiber_bridge_top_rx_sequence_no_output_recovery_test(dut): + await _setup_bridge(dut) + + rx_capture = cocotb.start_soon(_capture_rx_words(dut, cycles=64)) + + # Lane-0 `/Q/` is not decoded into a CXP word by the current RX bridge. The + # top-level gearbox should preserve that no-output guardrail and allow a + # later valid low-speed packet to recover. + await _drive_rx64( + dut, + (CXPOF_SEQ | (0x12 << 16) | (0x34 << 24)) | (_idle64() & 0xFFFFFFFF00000000), + 0xF1, + ) + await _drive_rx64(dut, _idle64(), 0xFF) + + await _drive_rx64(dut, _rx_start_word(CXP_PKT_EVENT_ACK) | (0xA1B2C3D4 << 32), 0x01) + await _drive_rx64(dut, 0x07FD00FD | (repeat_byte(CXPOF_IDLE) << 32), 0xFC) + await _drive_rx64(dut, _idle64(), 0xFF) + + rx_observed = await rx_capture + rx_expected = [ + (CXP_SOP, 0xF), + (repeat_byte(CXP_PKT_EVENT_ACK), 0x0), + (0xA1B2C3D4, 0x0), + (CXP_EOP, 0xF), + ] + assert rx_observed == rx_expected def test_CoaXPressOverFiberBridge(): From 999eabae130e11e61bc2068be22c0854b65df78c Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 1 May 2026 12:53:20 -0700 Subject: [PATCH 78/92] Add _control_in_lane() and use it for the /S/, /Q/, /E/, and /T/ guardrail sweep. The test now replaces the target XGMII byte lane instead of ORing over idle bytes. --- .../coaxpress/test_CoaXPressOverFiberBridgeRx.py | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py index 4b69851630..2a770cc356 100644 --- a/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py +++ b/tests/protocols/coaxpress/test_CoaXPressOverFiberBridgeRx.py @@ -47,6 +47,11 @@ def _cxp_start_word(packet_byte: int) -> int: return CXPOF_START | (0x80 << 8) | ((CXP_SOP & 0xFF) << 16) | (packet_byte << 24) +def _control_in_lane(control_byte: int, lane: int) -> int: + shift = 8 * lane + return (0x07070707 & ~(0xFF << shift)) | ((control_byte & 0xFF) << shift) + + @cocotb.test() async def coaxpress_over_fiber_bridge_rx_decode_test(dut): # Hold the bridge in its XGMII idle state until reset completes, then feed @@ -250,14 +255,14 @@ async def drive(rxd: int, rxc: int) -> None: for control_byte in (CXPOF_START, CXPOF_SEQ, CXPOF_ERROR): for lane in (1, 2, 3): - await drive(0x07070707 | (control_byte << (8 * lane)), 1 << lane) + await drive(_control_in_lane(control_byte, lane), 1 << lane) await drive(0x07070707, 0xF) # `/T/` outside an active packet is also malformed for this bridge input. It # is swept separately because lane 2 is valid only as part of a terminate # word once a payload is already active. for lane in (0, 1, 2, 3): - await drive(0x07070707 | (CXPOF_TERM << (8 * lane)), 1 << lane) + await drive(_control_in_lane(CXPOF_TERM, lane), 1 << lane) await drive(0x07070707, 0xF) await drive(_cxp_start_word(CXP_PKT_EVENT_ACK), 0x1) From 7815ff8cc488b3d201082dc20e4e7a39ae8839c4 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 1 May 2026 14:05:04 -0700 Subject: [PATCH 79/92] Attempt to reduce logic path. --- .../coaxpress/core/rtl/CoaXPressRxHsFsm.vhd | 95 ++++++++++++------- 1 file changed, 63 insertions(+), 32 deletions(-) diff --git a/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd b/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd index 1c94693e66..d65e729954 100644 --- a/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd +++ b/protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd @@ -91,11 +91,14 @@ architecture rtl of CoaXPressRxHsFsm is wrd => 0, cnt => (others => '0')); + subtype LineRemType is natural range 0 to NUM_LANES_G+1; + type RegType is record endOfLine : sl; hdrValid : sl; yCnt : slv(RX_FSM_CNT_WIDTH_G-1 downto 0); dCnt : slv(RX_FSM_CNT_WIDTH_G-1 downto 0); + lineRem : LineRemType; hdrCnt : natural range 0 to 25; hdr : ImageHdrType; dbg : DebugType; @@ -110,6 +113,7 @@ architecture rtl of CoaXPressRxHsFsm is hdrValid => '0', yCnt => (others => '0'), dCnt => (others => '0'), + lineRem => 0, hdrCnt => 0, hdr => IMAGE_HDR_INIT_C, dbg => DEBUG_INIT_C, @@ -137,8 +141,9 @@ begin variable v : RegType; variable tData : slv(31 downto 0); variable eolBeat : sl; - variable eolCnt : slv(RX_FSM_CNT_WIDTH_G-1 downto 0); variable eolWrd : natural range 0 to NUM_LANES_G-1; + variable wordCnt : natural range 0 to NUM_LANES_G; + variable remCnt : slv(RX_FSM_CNT_WIDTH_G-1 downto 0); begin -- Latch the current value v := r; @@ -276,6 +281,20 @@ begin -- Increment the counter v.dCnt := r.dCnt + 1; + + -- Check for max count + if (r.lineRem = 1) then + + -- Move the data + v.dataMasters(0).tValid := '1'; + + -- Set the "end of line" flag + v.endOfLine := '1'; + + -- Next State + v.state := IDLE_S; + + end if; ---------------------------------------------------------------------- when LINE_S => -- Write the data @@ -285,58 +304,56 @@ begin -- reparsed as the next marker/type sequence. v.rxSlave.tReady := '1'; eolBeat := '0'; - eolCnt := r.dCnt; eolWrd := 0; + wordCnt := 0; - -- Infer the line-ending word from the registered count. Keeping - -- this independent of the TKEEP-building loop avoids placing the - -- post-increment data count in the TREADY path. + -- Loop the number of 32-bit words for i in 0 to NUM_LANES_G-1 loop - if (pipeMaster.tKeep(4*i) = '1') and (eolBeat = '0') then - eolCnt := eolCnt + 1; - if (eolCnt = r.hdr.dsizeL(RX_FSM_CNT_WIDTH_G-1 downto 0)) then - eolBeat := '1'; - eolWrd := i; - end if; - end if; - end loop; - if (eolBeat = '1') and (eolWrd /= NUM_LANES_G-1) then - if (pipeMaster.tKeep(4*(eolWrd+1)) = '1') then - v.rxSlave.tReady := '0'; - v.wrd := eolWrd+1; - end if; - end if; + -- Check for valid data + if (pipeMaster.tKeep(4*i) = '1') then + wordCnt := wordCnt + 1; - -- Loop the number of 32-bit words - for i in 0 to NUM_LANES_G-1 loop + -- Check for not "end of line" + if (wordCnt <= r.lineRem) then - -- Check for not "end of line" and valid data - if (v.endOfLine = '0') and (pipeMaster.tKeep(4*i) = '1') then + -- Update the TKEEP mask + v.dataMasters(0).tKeep(4*i+3 downto 4*i) := x"F"; - -- Update the TKEEP mask - v.dataMasters(0).tKeep(4*i+3 downto 4*i) := x"F"; + -- Increment the counter + v.dCnt := v.dCnt + 1; - -- Increment the counter - v.dCnt := v.dCnt + 1; + end if; -- Check for max count - if (v.dCnt = r.hdr.dsizeL(RX_FSM_CNT_WIDTH_G-1 downto 0)) then + if (wordCnt = r.lineRem) then + + -- Flag the end of line word in this beat + eolBeat := '1'; + eolWrd := i; -- Set the "end of line" flag v.endOfLine := '1'; -- Next State v.state := IDLE_S; - if (v.rxSlave.tReady = '1') then - v.wrd := 0; - end if; end if; end if; end loop; + + if (eolBeat = '1') and (eolWrd /= NUM_LANES_G-1) then + if (pipeMaster.tKeep(4*(eolWrd+1)) = '1') then + v.rxSlave.tReady := '0'; + v.wrd := eolWrd+1; + else + v.wrd := 0; + end if; + elsif (eolBeat = '1') then + v.wrd := 0; + end if; ---------------------------------------------------------------------- end case; @@ -375,7 +392,7 @@ begin end if; -- Check for STEP_S state - if (r.state = STEP_S) and (v.rxSlave.tReady = '1') then + if (r.state = STEP_S) and (v.state = STEP_S) and (v.rxSlave.tReady = '1') then -- Move the data v.dataMasters(0).tValid := '1'; @@ -463,6 +480,20 @@ begin null; end case; + -- Register a small saturated remaining-word count. This breaks the wide + -- dCnt-to-wrd path when a line ends mid-beat and the next marker is held + -- in the current input word. + if (v.dCnt >= v.hdr.dsizeL(RX_FSM_CNT_WIDTH_G-1 downto 0)) then + v.lineRem := 0; + else + remCnt := v.hdr.dsizeL(RX_FSM_CNT_WIDTH_G-1 downto 0) - v.dCnt; + if (conv_integer(remCnt) > NUM_LANES_G) then + v.lineRem := NUM_LANES_G+1; + else + v.lineRem := conv_integer(remCnt); + end if; + end if; + ----------------------------------------------------------------------------- -- Perform an endianness swap in header message and remove redundant bytes -- ----------------------------------------------------------------------------- From 32cd3e27024d68163f5ebd8aa5ef273fd47de9d1 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 1 May 2026 16:05:37 -0700 Subject: [PATCH 80/92] Fix comment. --- protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd b/protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd index 3e71fcb11d..3e873bf008 100644 --- a/protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd +++ b/protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd @@ -223,7 +223,7 @@ begin -- Next State v.state := CTRL_ACK_TAG_S; - -- Check for "control acknowledge with tag" + -- Check for "Event packet" elsif (rxData = x"07_07_07_07") then -- Reset event parser counters v.ackCnt := 0; From 04f98335e2fe871315e9de6025187df85a1318ba Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 1 May 2026 16:09:03 -0700 Subject: [PATCH 81/92] Update planning docs --- docs/_meta/rtl_regression_handoff.md | 8 ++++++-- docs/_meta/rtl_regression_plan.md | 3 +++ docs/_meta/rtl_regression_progress.md | 20 ++++++++++++-------- 3 files changed, 21 insertions(+), 10 deletions(-) diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index f4f9e83666..8179a2cf5e 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -19,12 +19,13 @@ - Treat stale simulator cleanup as part of task completion: after any `pytest`, cocotb, GHDL, or similar launched verification step, sweep for leftover child processes and kill them before moving on ## Quick Resume Snapshot -- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, the current Ethernet coverage spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the pure-VHDL RoCEv2 quartet (`EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator`), and a broader user-directed CoaXPress pure-VHDL wave is now checked in under `tests/protocols/coaxpress/`. The validated CoaXPress subset now includes the receive quartet `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, and `CoaXPressRxHsFsm`, the receive assembly `CoaXPressRx`, the transmit/bridge helpers `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressOverFiberBridgeRx`, and `CoaXPressOverFiberBridgeTx`, and the higher-level assemblies `CoaXPressTx`, `CoaXPressCore`, and `CoaXPressOverFiberBridge`. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. +- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, the current Ethernet coverage spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the pure-VHDL RoCEv2 quartet (`EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator`), and a broader user-directed CoaXPress pure-VHDL wave is now checked in under `tests/protocols/coaxpress/`. The validated CoaXPress subset now includes the receive quartet `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, and `CoaXPressRxHsFsm`, the receive assembly `CoaXPressRx`, the transmit/bridge helpers `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressOverFiberBridgeRx`, and `CoaXPressOverFiberBridgeTx`, and the higher-level assemblies `CoaXPressTx`, `CoaXPressCore`, and `CoaXPressOverFiberBridge`. The latest `coaxpress-tests` merge resolution into `verification-2` keeps `docs/_meta` from `verification-2` while taking the CoaXPress README/test updates from `coaxpress-tests`. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. - Current axi frontier: complete for the intended simulator-friendly pass in this branch snapshot; do not resume from the older stale `AxiResize` note. - Current validated-open issues: - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core` remain untouched in phase 1, while the remaining RoCEv2 gap is the mixed-language bench path for the five RTL entities that instantiate generated submodules: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`. - `EthMacRxImportXlgmii` and `EthMacTxExportXlgmii` are still placeholder no-op RTL; the checked-in tests now lock down that inert contract instead of claiming functional XLGMII support. - The remaining CoaXPress pure-VHDL gap is now `CoaXPressConfig`. The current CoaXPress receive benches now include a dual-lane `CoaXPressRxHsFsm` step/alignment case, a dual-lane `CoaXPressRx` lane-rotation case, and event packet validation through payload size, payload words, CRC, and `EOP` before `eventAck`. The receive side is still intentionally mixed-depth: event payload is validated for parser/CRC behavior but is not exported through an application-facing payload interface, and the multi-lane assembly checks still stop short of exhaustive per-lane stress coverage. + - The latest CXPoF bridge guardrail work is now reflected at both leaf and top level: `CoaXPressOverFiberBridgeRx` covers HKP-to-payload mixing and malformed lane-placement checks for `/S/`, `/Q/`, `/T/`, and `/E/`, while `CoaXPressOverFiberBridge` covers 64-bit RX gearbox traversal for `/E/` abort/recovery, HKP-to-payload transition, and lane-0 `/Q/` no-output/recovery. Treat these as current-RTL regression guardrails rather than complete normative `/Q/`, `/E/`, or housekeeping protocol coverage. - `tests/protocols/coaxpress/test_CoaXPressConfig.py` is intentionally checked in as a skipped investigation bench. When driven through the real SRP ingress, the current `CoaXPressConfig` / `SrpV3AxiLite` integration does not complete the request path within the bench timeout, so treat that as a likely RTL or integration defect to debug before re-enabling active assertions there. - `tests/protocols/coaxpress/test_CoaXPressCore.py` now also carries an opt-in skipped known-issue bench for RX backpressure vs. FSM-error behavior. Enable it with `RUN_KNOWN_ISSUE_TESTS=1` and optionally shrink the load with `CXP_RX_OVERFLOW_STORM_FRAME_COUNT=`. The current local reproduction under sustained `M_DATA_TREADY=0` and repeated one-line image frames observed `RxFsmErrorCnt=2` while `RxOverflowCnt=0` at `96` frames, and a narrowing sweep showed no repro at `48` frames but a repro by `72` frames with `RxFsmErrorCnt=1` while `RxOverflowCnt=0`. That is closer to the user report than the earlier directed single-error tests and should be treated as a likely RTL defect under investigation. - For future CoaXPress work, treat the named packet classes and control bytes in `tests/protocols/coaxpress/coaxpress_test_utils.py` as shared spec anchors, not as optional local style. Those constants were normalized against the same `CXP-001-2021` / `CXPR-008-2021` references cited in `CoaXPressPkg.vhd`. Keep the packet-layer names aligned to the spec even where current RTL ports still use legacy `eventAck` naming on the receive side: `0x07` is an event packet and `0x08` is an event acknowledgment. @@ -33,6 +34,7 @@ - Use manual user-directed area selection as the active source of truth for what to work on next. - Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the actual validated branch frontier. - Keep the graph and queue artifacts only as historical provenance or optional analysis context; do not use them as the next-module selector unless the user explicitly opts back into queue-driven planning. + - Prefer parallel pytest for routine local validation, especially cocotb subsystem slices: `-n auto --dist=worksteal` is the default shape unless a single simulation needs serial logs or interactive debugging. - Current wrapper discipline: - Prefer the existing subsystem `ip_integrator/` shim layers over bespoke record flattening. - Keep first-pass wrapper benches intentionally narrow and document any omitted branches explicitly. @@ -172,7 +174,9 @@ A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instan ## Immediate Next Task If the user keeps the focus on `protocols/coaxpress`, the next practical step is either: 1. debug and re-enable the skipped `CoaXPressConfig` investigation bench, starting with the SRP-driven request path that currently fails to complete through the real `CoaXPressConfig` / `SrpV3AxiLite` integration, or -2. deepen the remaining spec-level gaps around application-facing receive-side event payload delivery, normative CXPoF `/Q/` sequence handling, and fuller `/E/` / housekeeping-data interaction semantics. +2. deepen the remaining spec-level gaps around application-facing receive-side event payload delivery, normative CXPoF `/Q/` sequence handling, fuller `/E/` semantics, and complete housekeeping protocol behavior beyond the current HKP-to-payload guardrail. + +The current CoaXPress slice was last validated with `./.venv/bin/python -m pytest -n auto --dist=worksteal -q tests/protocols/coaxpress` and passed with `17 passed, 1 skipped`; the skipped bench is still `CoaXPressConfig`. If the user switches back to `ethernet/RoCEv2`, the next real step is still enabling a mixed-language cocotb path for the five remaining RTL entities listed above. Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the real validated subset, and do not reintroduce local stand-ins for `blue-*`. diff --git a/docs/_meta/rtl_regression_plan.md b/docs/_meta/rtl_regression_plan.md index edb96d6e54..3c71ca8600 100644 --- a/docs/_meta/rtl_regression_plan.md +++ b/docs/_meta/rtl_regression_plan.md @@ -72,6 +72,9 @@ - Tier-first split. - Separate `smoke` and `functional` regression tiers. - Shard by subsystem only if runtime requires it. +- Prefer parallel pytest for normal local validation and subsystem slices, using + `-n auto --dist=worksteal` unless a single cocotb simulation needs serial log + ordering or interactive debugging. - Keep room for PR-vs-nightly expansion later if runtime and coverage needs justify it. - Treat simulator process cleanup as part of every verification step, not as optional housekeeping. - After any command that launches `pytest`, cocotb, GHDL, or another simulation runner, check for stale child processes and kill any leftovers before moving on to the next step. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 0255161490..033ffec41a 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -4,7 +4,7 @@ - Current phase: Phase-1 implementation active - Current subsystem: manual user-directed rollout tracking - Current focus module: user-directed CoaXPress pure-VHDL rollout under `protocols/coaxpress/core/rtl`, with validated cocotb coverage now checked in for `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, `CoaXPressRxHsFsm`, `CoaXPressRx`, `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressTx`, `CoaXPressCore`, `CoaXPressOverFiberBridgeRx`, `CoaXPressOverFiberBridgeTx`, and `CoaXPressOverFiberBridge`. -- Last updated: 2026-04-20 +- Last updated: 2026-05-01 ## Current Frontier Snapshot - Active planning rule: take the next work item from the user's manual direction, not from `docs/_meta/rtl_phase1_queue.{md,json}`. @@ -28,6 +28,8 @@ - Known-issue bench note: `tests/protocols/coaxpress/test_CoaXPressCore.py` now also carries an opt-in skipped investigation bench for the user-reported RX backpressure path. When enabled with `RUN_KNOWN_ISSUE_TESTS=1`, the bench drives sustained `M_DATA_TREADY=0` pressure with repeated one-line image frames and encodes the expected software-facing behavior that `RxOverflowCnt` should rise before `RxFsmErrorCnt`. The current local reproduction showed `RxFsmErrorCnt=2` while `RxOverflowCnt=0` at `96` frames, and a narrowing sweep showed no repro at `48` frames but a repro by `72` frames (`RxFsmErrorCnt=1`, `RxOverflowCnt=0`), so treat that as a likely RTL defect until narrowed or disproved. - Spec discipline for this family: use the packet/control naming and byte values from `CXP-001-2021` and `CXPR-008-2021` via shared helpers, and keep future top-level/bridge benches explicit about whether they are proving normative spec behavior or only the currently validated RTL subset. At the packet layer, keep the published names even when current RTL signal names drift: `0x07` is an event packet and `0x08` is an event acknowledgment. - The checked-in RX benches now use more spec-shaped control-ack framing on the wire, include a dual-lane `CoaXPressRxHsFsm` step/alignment case and a dual-lane `CoaXPressRx` lane-rotation case, and validate receive-lane event payload size, payload words, CRC, and `EOP` before `eventAck`. Keep the remaining limitation documented: event payload is validated for parser/CRC behavior, but the current RTL still exposes only `eventAck/eventTag` rather than an application-facing payload stream. + - The CXPoF bridge benches now include the recent optional-depth guardrails from `coaxpress-tests`: leaf HKP-to-payload mixing, broader malformed control-lane sweeps for `/S/`, `/Q/`, `/T/`, and `/E/`, plus top-level 64-bit RX coverage for `/E/` abort/recovery, HKP-to-payload gearbox traversal, and lane-0 `/Q/` no-output/recovery behavior. These are regression guardrails for the current RTL contract, not complete normative `/Q/`, `/E/`, or housekeeping semantics. + - Latest focused validation for the CoaXPress slice used parallel pytest: `./.venv/bin/python -m pytest -n auto --dist=worksteal -q tests/protocols/coaxpress` (`17 passed, 1 skipped`). The skipped test remains `CoaXPressConfig`. - Most recent reusable bench pattern: - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. @@ -148,15 +150,15 @@ - The new package-surface coverage exposed a real `Code12b14bPkg` invalid-K disparity bug; `protocols/line-codes/rtl/Code12b14bPkg.vhd` now leaves `dispOut` unchanged on illegal K requests instead of tripping a GHDL bound-check failure. ## Current In-Progress Item -- Decide the next non-`pgp3` `protocols/pgp` target now that the shared VC FIFOs and the remaining non-vendor `pgp4/core/rtl` leaves are covered. -- Keep `pgp2b`, `pgp2fc`, `pgp3`, and `pgp4` organized as separate family subpackages with checked-in wrappers rather than falling back to generated shim HDL, but treat `pgp3` as deferred for now. -- Preserve the recent `pgp4` lesson: when the simulation wrapper only exposes stable lock/config surfaces, write the bench around those explicit contracts instead of claiming recovered payload coverage. -- Phase-2 follow-on for `protocols/pgp/pgp4`: broaden the current single payload-bitflip negative test into a small corruption-location matrix that separately covers SOF/header metadata corruption, EOF/tail corruption (including transmitted CRC-field corruption), and 66b header-side framing errors instead of treating all of those cases as equivalent to payload CRC failure. +- Finish the current `coaxpress-tests` to `verification-2` integration without replacing the `verification-2` `docs/_meta` artifacts. The merge conflicts have been resolved by keeping `docs/_meta` from `verification-2` and taking the CoaXPress test/README content from `coaxpress-tests`; this documentation update records the resulting frontier. +- Keep the CoaXPress suite as the current near-term merge target. The focused CoaXPress validation command is `./.venv/bin/python -m pytest -n auto --dist=worksteal -q tests/protocols/coaxpress`, and the latest run passed with `17 passed, 1 skipped`. +- Treat the skipped `CoaXPressConfig` bench and the opt-in `CoaXPressCore` overflow/FSM-error known-issue bench as the remaining blockers before claiming a fully clean CoaXPress protocol slice. +- Preserve the recent `pgp4` lesson for later PGP work: when the simulation wrapper only exposes stable lock/config surfaces, write the bench around those explicit contracts instead of claiming recovered payload coverage. ## Next 3 Concrete Tasks -- Decide whether the next family pass is deeper directed coverage for the existing `pgp2b`/`pgp2fc` RX and alignment benches or a move into another non-deferred protocol area. -- Keep the `protocols/pgp/pgp4` low-speed leaves on their dedicated lock/config guardrail benches unless a later wrapper explicitly proves the serialized payload path end to end. -- Reuse the new `tests/protocols/pgp/shared/` helper and wrappers if later shared PGP utilities need direct cocotb coverage. +- Conclude the pending `verification-2` merge once the user is ready to stage and commit, then push/update the branch as usual. +- If staying on CoaXPress immediately after the merge, debug the skipped `CoaXPressConfig` / `SrpV3AxiLite` request path before adding broader optional coverage. +- After `CoaXPressConfig`, the next real CoaXPress expansion targets are application-facing event payload delivery, normative CXPoF `/Q/` sequence handling, fuller `/E/` error semantics, and complete housekeeping protocol behavior beyond the current HKP-to-payload guardrail. ## Blockers And Risks - Runtime may grow quickly once configuration-heavy modules are added without careful tiering. @@ -234,6 +236,7 @@ - For checked-in VHDL changes, use the repo virtualenv's `vsg` with `vsg-linter.yml` so local lint matches CI, and prefer `--fix` before manual spacing/alignment cleanup. - The current `EthMacCore` wave has a few wrapper-visible behavior details worth preserving in the docs instead of rediscovering later: the XGMII import/export loopback retains a frame presented during `phyReady=0` and drains it after link recovery with Ethernet minimum-size padding applied, while the GMII path drops it; `EthMacRxCsum` reliably asserts `IPERR` on a bad IPv4 header checksum but the checked-in wrapper contract does not require `EOFE` on that case; and the RX/TX shift benches need a small idle-plus-settle gap before changing runtime shift controls because the underlying `AxiStreamShift` samples those controls from its IDLE state. - Verification hygiene now includes process cleanup: if a `pytest`/cocotb/GHDL step leaves stale run trees behind, kill those leftovers immediately before starting another compile or simulation command. +- For routine local validation, prefer parallel pytest (`-n auto --dist=worksteal`) so cocotb suites finish quickly. Drop to `-n 0` only when debugging one simulation or preserving serial log ordering. ## Log - 2026-03-20: Agreed on Python-only executable regression logic and wrapper-only VHDL retention. @@ -327,3 +330,4 @@ - 2026-04-20: Removed the temporary local CRC stand-ins and the stub-backed `EthMacTxRoCEv2` / `EthMacRxRoCEv2` benches after clarifying the intended boundary: there should be one cocotb test module per entity in `ethernet/RoCEv2/rtl`, but `blue-*` must remain real transitive dependencies rather than being replaced with local test doubles. The current open RoCEv2 bench set is therefore `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`, all of which now require a mixed-language simulation path. - 2026-04-20: Added the next CoaXPress assembly pass with `tests/protocols/coaxpress/test_CoaXPressRx.py`, `test_CoaXPressCore.py`, and the checked-in wrappers `protocols/coaxpress/core/wrappers/CoaXPressRxWrapper.vhd` and `CoaXPressCoreWrapper.vhd`. The validated subset now covers the one-lane `CoaXPressRx` receive assembly and the AXI-Lite-controlled `CoaXPressCore` TX/config assembly path. `tests/protocols/coaxpress/test_CoaXPressConfig.py` was kept in-tree as a skipped investigation bench because the real SRP-driven `CoaXPressConfig` request path does not complete under the current `CoaXPressConfig` / `SrpV3AxiLite` integration, which is now recorded as the remaining pure-VHDL CoaXPress blocker. - 2026-04-20: Deepened the CoaXPress receive/bridge coverage without changing RTL scope. `test_CoaXPressRxHsFsm.py` now includes a dual-lane step/alignment case, `test_CoaXPressRx.py` now includes a dual-lane lane-rotation integration case through a generalized `CoaXPressRxWrapper.vhd`, `test_CoaXPressRxLane.py` now covers alternate-success control acknowledgments plus truncated-event guardrails, `test_CoaXPressTxLsFsm.py` now covers the slower implemented low-speed-rate trigger cadence with inverted-trigger mapping, and the CXPoF bridge leaf benches now include HKP, negative lane-placement checks, and partial-lane low-speed fill behavior. The focused validation run across those six files passed locally with `8 passed`. +- 2026-05-01: Integrated the latest `coaxpress-tests` progress into the `verification-2` merge worktree while preserving the `verification-2` `docs/_meta` artifacts. The CoaXPress conflict resolution takes the updated bridge README/test coverage from `coaxpress-tests`: leaf HKP-to-payload mixing, malformed control-lane guardrails for `/S/`, `/Q/`, `/T/`, and `/E/`, and top-level 64-bit RX gearbox cases for `/E/` abort/recovery, HKP-to-payload transition, and lane-0 `/Q/` no-output/recovery. Focused validation used `./.venv/bin/python -m pytest -n auto --dist=worksteal -q tests/protocols/coaxpress` and passed with `17 passed, 1 skipped`; the skipped bench remains `CoaXPressConfig`. From fcd67f8392a3a17bf44b2100ff187ac1f1c6113c Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Sat, 2 May 2026 22:29:35 -0700 Subject: [PATCH 82/92] Clean up srpv3 tests. --- docs/_meta/rtl_regression_handoff.md | 4 +- docs/_meta/rtl_regression_progress.md | 12 +- .../srp/wrappers/SrpV3AxiLiteWideWrapper.vhd | 173 ------------- .../srp/wrappers/SrpV3AxiLiteWrapper.vhd | 31 +-- .../srp/wrappers/SrpV3CoreNarrowWrapper.vhd | 234 ------------------ protocols/srp/wrappers/SrpV3CoreWrapper.vhd | 117 +++++---- tests/protocols/srp/test_SrpV3AxiLite.py | 72 +++--- tests/protocols/srp/test_SrpV3Core.py | 156 ++++++++++-- tests/protocols/srp/test_SrpV3CoreNarrow.py | 154 ------------ 9 files changed, 264 insertions(+), 689 deletions(-) delete mode 100644 protocols/srp/wrappers/SrpV3AxiLiteWideWrapper.vhd delete mode 100644 protocols/srp/wrappers/SrpV3CoreNarrowWrapper.vhd delete mode 100644 tests/protocols/srp/test_SrpV3CoreNarrow.py diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index fa50d1b29b..345cd2dffe 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -27,7 +27,7 @@ - The remaining CoaXPress pure-VHDL gap is now `CoaXPressConfig`. The current CoaXPress receive benches now include a dual-lane `CoaXPressRxHsFsm` step/alignment case, a dual-lane `CoaXPressRx` lane-rotation case, and event packet validation through payload size, payload words, CRC, and `EOP` before `eventAck`. The receive side is still intentionally mixed-depth: event payload is validated for parser/CRC behavior but is not exported through an application-facing payload interface, and the multi-lane assembly checks still stop short of exhaustive per-lane stress coverage. - The latest CXPoF bridge guardrail work is now reflected at both leaf and top level: `CoaXPressOverFiberBridgeRx` covers HKP-to-payload mixing and malformed lane-placement checks for `/S/`, `/Q/`, `/T/`, and `/E/`, while `CoaXPressOverFiberBridge` covers 64-bit RX gearbox traversal for `/E/` abort/recovery, HKP-to-payload transition, and lane-0 `/Q/` no-output/recovery. Treat these as current-RTL regression guardrails rather than complete normative `/Q/`, `/E/`, or housekeeping protocol coverage. - `tests/protocols/coaxpress/test_CoaXPressConfig.py` is intentionally checked in as a skipped investigation bench. When driven through the real SRP ingress, the current `CoaXPressConfig` / `SrpV3AxiLite` integration does not complete the request path within the bench timeout, so treat that as a likely RTL or integration defect to debug before re-enabling active assertions there. - - `tests/protocols/srp/test_SrpV3Axi.py` is now the active SRPv3 AXI regression, not just the old legacy-style posted-write/readback smoke. It validates non-posted write echo/readback, posted-write no-response behavior, NULL responses, response backpressure, TDEST propagation, full-word `TKEEP`, and footer bits for version mismatch, malformed write framing, invalid alignment, invalid request size, downstream write address error, and downstream read address error. `tests/protocols/srp/test_SrpV3Core.py` adds direct reset/idle smoke for `SrpV3Core`, and the new `tests/protocols/srp/test_SrpV3CoreNarrow.py` bench adds direct 32-bit malformed-header and immediate-read-error fault injection. That narrow bench exposed and now covers two real `SrpV3Core` bugs: the response-header counter was not reset when emitting an error response from a truncated request header, and `READ_S` could miss an immediate downstream read error before any payload beat arrived. `tests/protocols/srp/test_SrpV0Loopback.py` covers `AxiLiteSrpV0` and `SrpV0AxiLite` together through the checked-in SRPv0 stream loopback wrapper. `tests/protocols/srp/test_SrpV3AxiLite.py` now carries active reset/idle smoke for direct, full, and legacy-wide wrappers, active narrow probes for the direct and full wrappers, active directed regressions for the direct and full wrappers, and the existing active legacy-wide directed regression. The direct narrow `SrpV3AxiLite` issue turned out to be a bench artifact, not an RTL defect: `tests/protocols/srp/srp_test_utils.py` now holds each source beat until a sampled clock edge confirms `TREADY`, which fixes the false failure on the original `SsiFrameLimiter` bypass configuration (`SLAVE_FIFO_G => false`). The focused `tests/protocols/ssi/test_SsiFrameLimiter.py` isolation regressions remain green in both limiter modes. The only remaining opt-in SRP coverage is now the duplicate wide-wrapper probe/direct slice under `RUN_KNOWN_ISSUE_TESTS=1`. + - `tests/protocols/srp/test_SrpV3Axi.py` is now the active SRPv3 AXI regression, not just the old legacy-style posted-write/readback smoke. It validates non-posted write echo/readback, posted-write no-response behavior, NULL responses, response backpressure, TDEST propagation, full-word `TKEEP`, and footer bits for version mismatch, malformed write framing, invalid alignment, invalid request size, downstream write address error, and downstream read address error. `tests/protocols/srp/test_SrpV3Core.py` now covers direct reset/idle smoke for the default `SrpV3CoreWrapper` mode plus direct 32-bit malformed-header and immediate-read-error fault injection through `CORE_DATA_BYTES_G => 4`. That narrow mode exposed and now covers two real `SrpV3Core` bugs: the response-header counter was not reset when emitting an error response from a truncated request header, and `READ_S` could miss an immediate downstream read error before any payload beat arrived. `tests/protocols/srp/test_SrpV0Loopback.py` covers `AxiLiteSrpV0` and `SrpV0AxiLite` together through the checked-in SRPv0 stream loopback wrapper. `tests/protocols/srp/test_SrpV3AxiLite.py` now carries active reset/idle smoke for direct, full, and legacy-wide `DATA_BYTES_G => 32` modes, active narrow probes for the direct and full wrappers, active directed regressions for the direct and full wrappers, and one active legacy-wide directed regression. The duplicate wide-wrapper probe/direct cases were removed instead of kept as skipped opt-in coverage, and the old wide/narrow-only SRP wrapper files were folded into generics, leaving the default `tests/protocols/srp` run skip-free. The direct narrow `SrpV3AxiLite` issue turned out to be a bench artifact, not an RTL defect: `tests/protocols/srp/srp_test_utils.py` now holds each source beat until a sampled clock edge confirms `TREADY`, which fixes the false failure on the original `SsiFrameLimiter` bypass configuration (`SLAVE_FIFO_G => false`). The focused `tests/protocols/ssi/test_SsiFrameLimiter.py` isolation regressions remain green in both limiter modes. - The broader flat-stream helper cleanup is now partially checked in beyond SRP. `tests/axi/utils.py` owns the shared `wait_sampled_ready()` primitive, and the flattened helper layers in `tests/protocols/ssi/ssi_test_utils.py`, `tests/protocols/srp/srp_test_utils.py`, `tests/protocols/pgp/pgp4/pgp4_test_utils.py`, `tests/protocols/coaxpress/coaxpress_test_utils.py`, `tests/ethernet/EthMacCore/ethmac_test_utils.py`, and `tests/ethernet/RawEthFramer/raw_eth_test_utils.py` now use it where appropriate instead of open-coded sampled-ready loops. Direct one-off benches that were good fits for the same cleanup now include `tests/protocols/srp/test_SrpV3Axi.py`, `tests/protocols/ssi/test_SsiResizeFifoEofe.py`, `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, `tests/protocols/coaxpress/test_CoaXPressTx.py`, `tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py`, and `tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py`. - One subtle point from that cleanup is important for future edits: `wait_sampled_ready()` returns after the accepting clock edge has already occurred. A source must therefore advance or deassert immediately after the helper returns; leaving an extra post-handshake clock in place can create duplicate transfers or malformed streams. The current checked-in cleanup already corrected the false regressions that came from that mistake. - The current validation subset for the flat-driver cleanup is `174 passed` across `tests/protocols/srp/test_SrpV3Axi.py`, `tests/protocols/ssi/test_SsiResizeFifoEofe.py`, the active PGP4 flat-wrapper subset, `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, `tests/protocols/coaxpress/test_CoaXPressTx.py`, `tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py`, and `tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py`. @@ -179,7 +179,7 @@ A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instan ## Immediate Next Task If the user keeps the focus on stream-helper cleanup rather than resuming a new subsystem, the next practical step is the remaining PGP interleaved source/capture helpers: decide whether `tests/protocols/pgp/pgp4/test_Pgp4Rx.py` and the protocol-word collector in `tests/protocols/pgp/pgp4/pgp4_test_utils.py` should stay intentionally manual or be folded into a richer shared helper that can hold a source beat through acceptance while concurrently capturing narrow output pulses. -If the user keeps the focus on `protocols/srp`, the next practical step inside that subsystem is now mostly cleanup rather than rescue work: decide whether the duplicate wide-wrapper opt-in cases in `tests/protocols/srp/test_SrpV3AxiLite.py` should be deleted, collapsed into the active legacy-wide directed test, or kept as explicit opt-in reproductions, and consider renaming `RUN_KNOWN_ISSUE_TESTS` now that it no longer refers to `SrpV3AxiLiteFull`. +If the user keeps the focus on `protocols/srp`, the next practical step inside that subsystem is deeper isolated coverage rather than rescue work: consider whether `tests/protocols/srp/test_SrpV3Core.py` should absorb more of the protocol-error matrix that is currently only covered transitively through `SrpV3Axi` and `SrpV3AxiLite`. If the user switches back to `protocols/coaxpress`, the next practical step is either: 1. debug and re-enable the skipped `CoaXPressConfig` investigation bench, starting with the SRP-driven request path that currently fails to complete through the real `CoaXPressConfig` / `SrpV3AxiLite` integration, or diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 2967d4799e..f87e3cb47d 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -3,7 +3,7 @@ ## Summary - Current phase: Phase-1 implementation active - Current subsystem: manual user-directed rollout tracking -- Current focus module: merging the user-directed `protocols/srp` regression work onto the current `verification-2` frontier while preserving the recently validated CoaXPress pure-VHDL rollout under `protocols/coaxpress/core/rtl`. +- Current focus module: user-directed `protocols/srp` regression cleanup after merging the SRP branch onto the current `verification-2` frontier, while preserving the recently validated CoaXPress pure-VHDL rollout under `protocols/coaxpress/core/rtl`. - Last updated: 2026-05-01 ## Current Frontier Snapshot @@ -33,9 +33,9 @@ - SRP RTL target matrix: - Covered now under the current GHDL-only flow: `SrpV3Axi` through the checked-in `protocols/srp/wrappers/SrpV3AxiWrapper.vhd` wrapper and `tests/protocols/srp/test_SrpV3Axi.py`. - The current SRPv3 AXI bench now validates non-posted write echo/readback, posted-write no-response behavior followed by readback, NULL header/footer behavior, response backpressure hold, TDEST propagation, full-word `TKEEP`, and footer bits for version mismatch, malformed write framing, invalid alignment, invalid request size, and downstream address error. - - `SrpV3Core` now has a direct checked-in wrapper and reset/idle smoke test plus a new narrow 32-bit fault-injection bench for malformed-header and immediate-read-error behavior. That bench exposed and now covers two core-side bugs: the response-header counter was not reset when emitting an error response from a truncated request header, and `READ_S` could miss an immediate downstream read error before any payload beat arrived. + - `SrpV3Core` now has a direct checked-in wrapper with reset/idle smoke coverage plus a narrow 32-bit fault-injection mode for malformed-header and immediate-read-error behavior. `tests/protocols/srp/test_SrpV3Core.py` now uses `SrpV3CoreWrapper` in both default mode and `CORE_DATA_BYTES_G => 4` mode instead of carrying a separate narrow test file. The narrow mode exposed and now covers two core-side bugs: the response-header counter was not reset when emitting an error response from a truncated request header, and `READ_S` could miss an immediate downstream read error before any payload beat arrived. - `AxiLiteSrpV0` and `SrpV0AxiLite` are now covered together by `protocols/srp/wrappers/SrpV0LoopbackWrapper.vhd` and `tests/protocols/srp/test_SrpV0Loopback.py`, which uses cocotb AXI-Lite master helpers to write/read through the old SRPv0 stream loopback and attached RAM. - - SRPv3 AXI-Lite status: `tests/protocols/srp/test_SrpV3AxiLite.py` now has active reset/idle coverage for the direct, full, and legacy-wide wrappers, active narrow probes (`short_frame`, `four_beat_header`, and `single_read`) for both the direct and full wrappers, active directed regressions for the direct and full wrappers, and the existing legacy-wide directed regression with duplicate wide probe/direct cases still opt-in. The earlier direct-wrapper failure was not an `SrpV3AxiLite` ingress RTL defect after all: the real issue was in `tests/protocols/srp/srp_test_utils.py`, where `FlatSrpAxis.send_packed_words()` treated combinational `TREADY` as immediate acceptance instead of holding each beat until a sampled clock edge confirmed the handshake. With that helper fixed and the two `SrpV3Core` fixes in place, the direct and full `SrpV3AxiLite` paths now pass on the original `SsiFrameLimiter` bypass configuration (`SLAVE_FIFO_G => false`), and the focused standalone `tests/protocols/ssi/test_SsiFrameLimiter.py` regressions remain green in both limiter modes. The current default SRP file run is `14 passed, 4 skipped`. + - SRPv3 AXI-Lite status: `tests/protocols/srp/test_SrpV3AxiLite.py` now has active reset/idle coverage for the direct, full, and legacy-wide `DATA_BYTES_G => 32` modes, active narrow probes (`short_frame`, `four_beat_header`, and `single_read`) for both the direct and full wrappers, active directed regressions for the direct and full wrappers, and one active legacy-wide directed regression. The earlier direct-wrapper failure was not an `SrpV3AxiLite` ingress RTL defect after all: the real issue was in `tests/protocols/srp/srp_test_utils.py`, where `FlatSrpAxis.send_packed_words()` treated combinational `TREADY` as immediate acceptance instead of holding each beat until a sampled clock edge confirmed the handshake. With that helper fixed and the two `SrpV3Core` fixes in place, the direct and full `SrpV3AxiLite` paths now pass on the original `SsiFrameLimiter` bypass configuration (`SLAVE_FIFO_G => false`), and the focused standalone `tests/protocols/ssi/test_SsiFrameLimiter.py` regressions remain green in both limiter modes. The duplicate wide-wrapper probe/direct cases were removed rather than kept as skipped opt-in coverage, and the old wide/narrow-only SRP wrapper files were folded into generics, so the default `tests/protocols/srp` run is now skip-free. - Flat AXI/SSI helper cleanup status: - `tests/axi/utils.py` now owns the shared `wait_sampled_ready()` primitive for flattened ready/valid sources that cannot use `cocotbext.axi.AxiStreamSource` directly. - The current flat-driver users are `tests/protocols/ssi/ssi_test_utils.py`, `tests/protocols/srp/srp_test_utils.py`, `tests/protocols/pgp/pgp4/pgp4_test_utils.py`, `tests/protocols/coaxpress/coaxpress_test_utils.py`, `tests/ethernet/EthMacCore/ethmac_test_utils.py`, and `tests/ethernet/RawEthFramer/raw_eth_test_utils.py`, plus direct one-off benches in `tests/protocols/srp/test_SrpV3Axi.py`, `tests/protocols/ssi/test_SsiResizeFifoEofe.py`, `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, `tests/protocols/coaxpress/test_CoaXPressTx.py`, `tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py`, and `tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py`. @@ -162,14 +162,14 @@ - The new package-surface coverage exposed a real `Code12b14bPkg` invalid-K disparity bug; `protocols/line-codes/rtl/Code12b14bPkg.vhd` now leaves `dispOut` unchanged on illegal K requests instead of tripping a GHDL bound-check failure. ## Current In-Progress Item -- Finish the `srp-tests` to `verification-2` merge. The docs keep the newer CoaXPress frontier from `verification-2` while adding the SRP regression matrix, `SrpV3Core` RTL fixes, SRPv0 loopback coverage, and shared sampled-ready helper cleanup from `srp-tests`. +- Finish reviewing the `srp-tests` to `verification-2` merge after removing the duplicate SRPv3 AXI-Lite wide-wrapper skip cases. The docs keep the newer CoaXPress frontier from `verification-2` while adding the SRP regression matrix, `SrpV3Core` RTL fixes, SRPv0 loopback coverage, and shared sampled-ready helper cleanup from `srp-tests`. - Keep the CoaXPress suite as an already validated current branch slice. The focused CoaXPress validation command is `./.venv/bin/python -m pytest -n auto --dist=worksteal -q tests/protocols/coaxpress`, and the latest pre-merge run passed with `17 passed, 1 skipped`. -- Treat the skipped `CoaXPressConfig` bench, the opt-in `CoaXPressCore` overflow/FSM-error known-issue bench, and the duplicate SRP wide-wrapper opt-in cases as the main open cleanup items before claiming a fully clean protocol slice. +- Treat the skipped `CoaXPressConfig` bench and the opt-in `CoaXPressCore` overflow/FSM-error known-issue bench as the main open protocol cleanup items after the SRP duplicate wide-wrapper skips were removed. - Preserve the recent `pgp4` lesson for later PGP work: when the simulation wrapper only exposes stable lock/config surfaces, write the bench around those explicit contracts instead of claiming recovered payload coverage. ## Next 3 Concrete Tasks - Review and commit the staged `srp-tests` merge once local validation and code review are satisfactory. -- Decide whether the duplicate wide-wrapper probe/direct cases should be deleted, collapsed into the legacy-wide active test, or kept only as explicit opt-in debug reproductions. +- Consider whether `tests/protocols/srp/test_SrpV3Core.py` should absorb more of the protocol-error matrix that is currently only covered transitively through `SrpV3Axi` and `SrpV3AxiLite`. - If staying on CoaXPress immediately after the merge, debug the skipped `CoaXPressConfig` / `SrpV3AxiLite` request path before adding broader optional coverage. ## Blockers And Risks diff --git a/protocols/srp/wrappers/SrpV3AxiLiteWideWrapper.vhd b/protocols/srp/wrappers/SrpV3AxiLiteWideWrapper.vhd deleted file mode 100644 index aec6320799..0000000000 --- a/protocols/srp/wrappers/SrpV3AxiLiteWideWrapper.vhd +++ /dev/null @@ -1,173 +0,0 @@ -------------------------------------------------------------------------------- --- Company : SLAC National Accelerator Laboratory -------------------------------------------------------------------------------- --- Description: 256-bit cocotb-facing wrapper for SrpV3AxiLite regression testing -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -library surf; -use surf.StdRtlPkg.all; -use surf.AxiLitePkg.all; -use surf.AxiStreamPkg.all; -use surf.SsiPkg.all; - -entity SrpV3AxiLiteWideWrapper is - port ( - AXIS_ACLK : in std_logic; - AXIS_ARESETN : in std_logic; - S_AXIS_TVALID : in std_logic; - S_AXIS_TDATA : in std_logic_vector(255 downto 0); - S_AXIS_TKEEP : in std_logic_vector(31 downto 0); - S_AXIS_TLAST : in std_logic; - S_AXIS_TDEST : in std_logic_vector(3 downto 0); - S_AXIS_TID : in std_logic_vector(0 downto 0); - S_AXIS_TUSER : in std_logic_vector(1 downto 0); - S_AXIS_TREADY : out std_logic; - M_AXIS_TVALID : out std_logic; - M_AXIS_TDATA : out std_logic_vector(255 downto 0); - M_AXIS_TKEEP : out std_logic_vector(31 downto 0); - M_AXIS_TLAST : out std_logic; - M_AXIS_TDEST : out std_logic_vector(3 downto 0); - M_AXIS_TID : out std_logic_vector(0 downto 0); - M_AXIS_TUSER : out std_logic_vector(1 downto 0); - M_AXIS_TREADY : in std_logic; - M_AXIL_AWADDR : out std_logic_vector(11 downto 0); - M_AXIL_AWPROT : out std_logic_vector(2 downto 0); - M_AXIL_AWVALID : out std_logic; - M_AXIL_AWREADY : in std_logic; - M_AXIL_WDATA : out std_logic_vector(31 downto 0); - M_AXIL_WSTRB : out std_logic_vector(3 downto 0); - M_AXIL_WVALID : out std_logic; - M_AXIL_WREADY : in std_logic; - M_AXIL_BRESP : in std_logic_vector(1 downto 0); - M_AXIL_BVALID : in std_logic; - M_AXIL_BREADY : out std_logic; - M_AXIL_ARADDR : out std_logic_vector(11 downto 0); - M_AXIL_ARPROT : out std_logic_vector(2 downto 0); - M_AXIL_ARVALID : out std_logic; - M_AXIL_ARREADY : in std_logic; - M_AXIL_RDATA : in std_logic_vector(31 downto 0); - M_AXIL_RRESP : in std_logic_vector(1 downto 0); - M_AXIL_RVALID : in std_logic; - M_AXIL_RREADY : out std_logic); -end entity SrpV3AxiLiteWideWrapper; - -architecture rtl of SrpV3AxiLiteWideWrapper is - - constant TPD_C : time := 10 ns / 4; - constant AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(32); - - signal axisRst : sl := '0'; - - signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; - signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; - signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; - signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; - - signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - -begin - - axisRst <= not AXIS_ARESETN; - - sAxisComb : process (S_AXIS_TDATA, S_AXIS_TDEST, S_AXIS_TKEEP, S_AXIS_TLAST, S_AXIS_TUSER, S_AXIS_TVALID) is - variable v : AxiStreamMasterType; - begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := S_AXIS_TVALID; - v.tData(255 downto 0) := S_AXIS_TDATA; - v.tKeep(31 downto 0) := S_AXIS_TKEEP; - v.tLast := S_AXIS_TLAST; - v.tDest(3 downto 0) := S_AXIS_TDEST; - ssiSetUserEofe(AXIS_CONFIG_C, v, S_AXIS_TUSER(SSI_EOFE_C)); - ssiSetUserSof(AXIS_CONFIG_C, v, S_AXIS_TUSER(SSI_SOF_C)); - sAxisMaster <= v; - end process sAxisComb; - - S_AXIS_TREADY <= sAxisSlave.tReady; - - mAxisSlave.tReady <= M_AXIS_TREADY; - - M_AXIS_TVALID <= mAxisMaster.tValid; - M_AXIS_TDATA <= mAxisMaster.tData(255 downto 0); - M_AXIS_TKEEP <= mAxisMaster.tKeep(31 downto 0); - M_AXIS_TLAST <= mAxisMaster.tLast; - M_AXIS_TDEST <= mAxisMaster.tDest(3 downto 0); - M_AXIS_TID <= (others => '0'); - M_AXIS_TUSER <= ssiGetUserSof(AXIS_CONFIG_C, mAxisMaster) & ssiGetUserEofe(AXIS_CONFIG_C, mAxisMaster); - - U_SRPv3 : entity surf.SrpV3AxiLite - generic map ( - TPD_G => TPD_C, - TX_VALID_THOLD_G => 1, - SLAVE_READY_EN_G => true, - GEN_SYNC_FIFO_G => true, - ENABLE_TIMER_G => false, - AXI_STREAM_CONFIG_G => AXIS_CONFIG_C) - port map ( - sAxisClk => AXIS_ACLK, - sAxisRst => axisRst, - sAxisMaster => sAxisMaster, - sAxisSlave => sAxisSlave, - sAxisCtrl => open, - mAxisClk => AXIS_ACLK, - mAxisRst => axisRst, - mAxisMaster => mAxisMaster, - mAxisSlave => mAxisSlave, - axilClk => AXIS_ACLK, - axilRst => axisRst, - mAxilWriteMaster => axilWriteMaster, - mAxilWriteSlave => axilWriteSlave, - mAxilReadMaster => axilReadMaster, - mAxilReadSlave => axilReadSlave); - - U_AxiLiteMaster : entity surf.MasterAxiLiteIpIntegrator - generic map ( - INTERFACENAME => "M_AXIL", - EN_ERROR_RESP => true, - HAS_PROT => 1, - HAS_WSTRB => 1, - ADDR_WIDTH => 12) - port map ( - M_AXI_ACLK => AXIS_ACLK, - M_AXI_ARESETN => AXIS_ARESETN, - M_AXI_AWADDR => M_AXIL_AWADDR, - M_AXI_AWPROT => M_AXIL_AWPROT, - M_AXI_AWVALID => M_AXIL_AWVALID, - M_AXI_AWREADY => M_AXIL_AWREADY, - M_AXI_WDATA => M_AXIL_WDATA, - M_AXI_WSTRB => M_AXIL_WSTRB, - M_AXI_WVALID => M_AXIL_WVALID, - M_AXI_WREADY => M_AXIL_WREADY, - M_AXI_BRESP => M_AXIL_BRESP, - M_AXI_BVALID => M_AXIL_BVALID, - M_AXI_BREADY => M_AXIL_BREADY, - M_AXI_ARADDR => M_AXIL_ARADDR, - M_AXI_ARPROT => M_AXIL_ARPROT, - M_AXI_ARVALID => M_AXIL_ARVALID, - M_AXI_ARREADY => M_AXIL_ARREADY, - M_AXI_RDATA => M_AXIL_RDATA, - M_AXI_RRESP => M_AXIL_RRESP, - M_AXI_RVALID => M_AXIL_RVALID, - M_AXI_RREADY => M_AXIL_RREADY, - axilClk => open, - axilRst => open, - axilReadMaster => axilReadMaster, - axilReadSlave => axilReadSlave, - axilWriteMaster => axilWriteMaster, - axilWriteSlave => axilWriteSlave); - -end architecture rtl; diff --git a/protocols/srp/wrappers/SrpV3AxiLiteWrapper.vhd b/protocols/srp/wrappers/SrpV3AxiLiteWrapper.vhd index 8ec2fd4dae..2ea2f1f30a 100644 --- a/protocols/srp/wrappers/SrpV3AxiLiteWrapper.vhd +++ b/protocols/srp/wrappers/SrpV3AxiLiteWrapper.vhd @@ -22,20 +22,22 @@ use surf.AxiStreamPkg.all; use surf.SsiPkg.all; entity SrpV3AxiLiteWrapper is + generic ( + DATA_BYTES_G : positive range 4 to 64 := 4); port ( AXIS_ACLK : in std_logic; AXIS_ARESETN : in std_logic; S_AXIS_TVALID : in std_logic; - S_AXIS_TDATA : in std_logic_vector(31 downto 0); - S_AXIS_TKEEP : in std_logic_vector(3 downto 0); + S_AXIS_TDATA : in std_logic_vector((8 * DATA_BYTES_G) - 1 downto 0); + S_AXIS_TKEEP : in std_logic_vector(DATA_BYTES_G - 1 downto 0); S_AXIS_TLAST : in std_logic; S_AXIS_TDEST : in std_logic_vector(3 downto 0); S_AXIS_TID : in std_logic_vector(0 downto 0); S_AXIS_TUSER : in std_logic_vector(1 downto 0); S_AXIS_TREADY : out std_logic; M_AXIS_TVALID : out std_logic; - M_AXIS_TDATA : out std_logic_vector(31 downto 0); - M_AXIS_TKEEP : out std_logic_vector(3 downto 0); + M_AXIS_TDATA : out std_logic_vector((8 * DATA_BYTES_G) - 1 downto 0); + M_AXIS_TKEEP : out std_logic_vector(DATA_BYTES_G - 1 downto 0); M_AXIS_TLAST : out std_logic; M_AXIS_TDEST : out std_logic_vector(3 downto 0); M_AXIS_TID : out std_logic_vector(0 downto 0); @@ -65,7 +67,8 @@ end entity SrpV3AxiLiteWrapper; architecture rtl of SrpV3AxiLiteWrapper is constant TPD_C : time := 10 ns / 4; - constant AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(4); + constant DATA_BITS_C : positive := 8 * DATA_BYTES_G; + constant AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(DATA_BYTES_G); signal axisRst : sl := '0'; @@ -86,15 +89,15 @@ begin sAxisComb : process (S_AXIS_TDATA, S_AXIS_TDEST, S_AXIS_TKEEP, S_AXIS_TLAST, S_AXIS_TUSER, S_AXIS_TVALID) is variable v : AxiStreamMasterType; begin - v := AXI_STREAM_MASTER_INIT_C; - v.tValid := S_AXIS_TVALID; - v.tData(31 downto 0) := S_AXIS_TDATA; - v.tKeep(3 downto 0) := S_AXIS_TKEEP; - v.tLast := S_AXIS_TLAST; - v.tDest(3 downto 0) := S_AXIS_TDEST; + v := AXI_STREAM_MASTER_INIT_C; + v.tValid := S_AXIS_TVALID; + v.tData(DATA_BITS_C - 1 downto 0) := S_AXIS_TDATA; + v.tKeep(DATA_BYTES_G - 1 downto 0) := S_AXIS_TKEEP; + v.tLast := S_AXIS_TLAST; + v.tDest(3 downto 0) := S_AXIS_TDEST; ssiSetUserEofe(AXIS_CONFIG_C, v, S_AXIS_TUSER(SSI_EOFE_C)); ssiSetUserSof(AXIS_CONFIG_C, v, S_AXIS_TUSER(SSI_SOF_C)); - sAxisMaster <= v; + sAxisMaster <= v; end process sAxisComb; S_AXIS_TREADY <= sAxisSlave.tReady; @@ -102,8 +105,8 @@ begin mAxisSlave.tReady <= M_AXIS_TREADY; M_AXIS_TVALID <= mAxisMaster.tValid; - M_AXIS_TDATA <= mAxisMaster.tData(31 downto 0); - M_AXIS_TKEEP <= mAxisMaster.tKeep(3 downto 0); + M_AXIS_TDATA <= mAxisMaster.tData(DATA_BITS_C - 1 downto 0); + M_AXIS_TKEEP <= mAxisMaster.tKeep(DATA_BYTES_G - 1 downto 0); M_AXIS_TLAST <= mAxisMaster.tLast; M_AXIS_TDEST <= mAxisMaster.tDest(3 downto 0); M_AXIS_TID <= (others => '0'); diff --git a/protocols/srp/wrappers/SrpV3CoreNarrowWrapper.vhd b/protocols/srp/wrappers/SrpV3CoreNarrowWrapper.vhd deleted file mode 100644 index 91f9c05f84..0000000000 --- a/protocols/srp/wrappers/SrpV3CoreNarrowWrapper.vhd +++ /dev/null @@ -1,234 +0,0 @@ -------------------------------------------------------------------------------- --- Company : SLAC National Accelerator Laboratory -------------------------------------------------------------------------------- --- Description: 32-bit cocotb-facing wrapper for direct SrpV3Core regressions -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -library surf; -use surf.StdRtlPkg.all; -use surf.AxiStreamPkg.all; -use surf.SsiPkg.all; -use surf.SrpV3Pkg.all; - -entity SrpV3CoreNarrowWrapper is - port ( - AXIS_ACLK : in std_logic; - AXIS_ARESETN : in std_logic; - S_AXIS_TVALID : in std_logic; - S_AXIS_TDATA : in std_logic_vector(31 downto 0); - S_AXIS_TKEEP : in std_logic_vector(3 downto 0); - S_AXIS_TLAST : in std_logic; - S_AXIS_TDEST : in std_logic_vector(3 downto 0); - S_AXIS_TID : in std_logic_vector(0 downto 0); - S_AXIS_TUSER : in std_logic_vector(1 downto 0); - S_AXIS_TREADY : out std_logic; - M_AXIS_TVALID : out std_logic; - M_AXIS_TDATA : out std_logic_vector(31 downto 0); - M_AXIS_TKEEP : out std_logic_vector(3 downto 0); - M_AXIS_TLAST : out std_logic; - M_AXIS_TDEST : out std_logic_vector(3 downto 0); - M_AXIS_TID : out std_logic_vector(0 downto 0); - M_AXIS_TUSER : out std_logic_vector(1 downto 0); - M_AXIS_TREADY : in std_logic; - RD_AXIS_TVALID : in std_logic; - RD_AXIS_TDATA : in std_logic_vector(31 downto 0); - RD_AXIS_TKEEP : in std_logic_vector(3 downto 0); - RD_AXIS_TLAST : in std_logic; - RD_AXIS_TUSER : in std_logic_vector(1 downto 0); - RD_AXIS_TREADY : out std_logic; - WR_AXIS_TVALID : out std_logic; - WR_AXIS_TDATA : out std_logic_vector(31 downto 0); - WR_AXIS_TKEEP : out std_logic_vector(3 downto 0); - WR_AXIS_TLAST : out std_logic; - WR_AXIS_TUSER : out std_logic_vector(1 downto 0); - WR_AXIS_TREADY : in std_logic; - SRP_REQ_REQUEST : out std_logic; - SRP_REQ_REM_VER : out std_logic_vector(7 downto 0); - SRP_REQ_OPCODE : out std_logic_vector(1 downto 0); - SRP_REQ_PROT : out std_logic_vector(2 downto 0); - SRP_REQ_TID : out std_logic_vector(31 downto 0); - SRP_REQ_ADDR : out std_logic_vector(63 downto 0); - SRP_REQ_REQ_SIZE : out std_logic_vector(31 downto 0); - SRP_ACK_DONE : in std_logic; - SRP_ACK_RESP : in std_logic_vector(7 downto 0)); -end entity SrpV3CoreNarrowWrapper; - -architecture rtl of SrpV3CoreNarrowWrapper is - - constant TPD_C : time := 10 ns / 4; - constant AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(4); - - signal axisRst : sl := '0'; - - signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal rdAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal rdAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - signal wrAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; - signal wrAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C; - - signal srpReq : SrpV3ReqType := SRPV3_REQ_INIT_C; - signal srpAck : SrpV3AckType := SRPV3_ACK_INIT_C; - -begin - - axisRst <= not AXIS_ARESETN; - - srpAck.done <= SRP_ACK_DONE; - srpAck.respCode <= SRP_ACK_RESP; - - SRP_REQ_REQUEST <= srpReq.request; - SRP_REQ_REM_VER <= srpReq.remVer; - SRP_REQ_OPCODE <= srpReq.opCode; - SRP_REQ_PROT <= srpReq.prot; - SRP_REQ_TID <= srpReq.tid; - SRP_REQ_ADDR <= srpReq.addr; - SRP_REQ_REQ_SIZE <= srpReq.reqSize; - - U_ShimLayerSlave : entity surf.SlaveAxiStreamIpIntegrator - generic map ( - INTERFACENAME => "S_AXIS", - HAS_TLAST => 1, - HAS_TKEEP => 1, - HAS_TSTRB => 0, - HAS_TREADY => 1, - TUSER_WIDTH => 2, - TID_WIDTH => 1, - TDEST_WIDTH => 4, - TDATA_NUM_BYTES => 4) - port map ( - S_AXIS_ACLK => AXIS_ACLK, - S_AXIS_ARESETN => AXIS_ARESETN, - S_AXIS_TVALID => S_AXIS_TVALID, - S_AXIS_TDATA => S_AXIS_TDATA, - S_AXIS_TKEEP => S_AXIS_TKEEP, - S_AXIS_TLAST => S_AXIS_TLAST, - S_AXIS_TDEST => S_AXIS_TDEST, - S_AXIS_TID => S_AXIS_TID, - S_AXIS_TUSER => S_AXIS_TUSER, - S_AXIS_TREADY => S_AXIS_TREADY, - axisClk => open, - axisRst => open, - axisMaster => sAxisMaster, - axisSlave => sAxisSlave); - - U_ShimLayerMaster : entity surf.MasterAxiStreamIpIntegrator - generic map ( - INTERFACENAME => "M_AXIS", - HAS_TLAST => 1, - HAS_TKEEP => 1, - HAS_TSTRB => 0, - HAS_TREADY => 1, - TUSER_WIDTH => 2, - TID_WIDTH => 1, - TDEST_WIDTH => 4, - TDATA_NUM_BYTES => 4) - port map ( - M_AXIS_ACLK => AXIS_ACLK, - M_AXIS_ARESETN => AXIS_ARESETN, - M_AXIS_TVALID => M_AXIS_TVALID, - M_AXIS_TDATA => M_AXIS_TDATA, - M_AXIS_TKEEP => M_AXIS_TKEEP, - M_AXIS_TLAST => M_AXIS_TLAST, - M_AXIS_TDEST => M_AXIS_TDEST, - M_AXIS_TID => M_AXIS_TID, - M_AXIS_TUSER => M_AXIS_TUSER, - M_AXIS_TREADY => M_AXIS_TREADY, - axisClk => open, - axisRst => open, - axisMaster => mAxisMaster, - axisSlave => mAxisSlave); - - U_ReadShim : entity surf.SlaveAxiStreamIpIntegrator - generic map ( - INTERFACENAME => "RD_AXIS", - HAS_TLAST => 1, - HAS_TKEEP => 1, - HAS_TSTRB => 0, - HAS_TREADY => 1, - TUSER_WIDTH => 2, - TID_WIDTH => 1, - TDEST_WIDTH => 1, - TDATA_NUM_BYTES => 4) - port map ( - S_AXIS_ACLK => AXIS_ACLK, - S_AXIS_ARESETN => AXIS_ARESETN, - S_AXIS_TVALID => RD_AXIS_TVALID, - S_AXIS_TDATA => RD_AXIS_TDATA, - S_AXIS_TKEEP => RD_AXIS_TKEEP, - S_AXIS_TLAST => RD_AXIS_TLAST, - S_AXIS_TDEST => "0", - S_AXIS_TID => "0", - S_AXIS_TUSER => RD_AXIS_TUSER, - S_AXIS_TREADY => RD_AXIS_TREADY, - axisClk => open, - axisRst => open, - axisMaster => rdAxisMaster, - axisSlave => rdAxisSlave); - - U_WriteShim : entity surf.MasterAxiStreamIpIntegrator - generic map ( - INTERFACENAME => "WR_AXIS", - HAS_TLAST => 1, - HAS_TKEEP => 1, - HAS_TSTRB => 0, - HAS_TREADY => 1, - TUSER_WIDTH => 2, - TID_WIDTH => 1, - TDEST_WIDTH => 1, - TDATA_NUM_BYTES => 4) - port map ( - M_AXIS_ACLK => AXIS_ACLK, - M_AXIS_ARESETN => AXIS_ARESETN, - M_AXIS_TVALID => WR_AXIS_TVALID, - M_AXIS_TDATA => WR_AXIS_TDATA, - M_AXIS_TKEEP => WR_AXIS_TKEEP, - M_AXIS_TLAST => WR_AXIS_TLAST, - M_AXIS_TDEST => open, - M_AXIS_TID => open, - M_AXIS_TUSER => WR_AXIS_TUSER, - M_AXIS_TREADY => WR_AXIS_TREADY, - axisClk => open, - axisRst => open, - axisMaster => wrAxisMaster, - axisSlave => wrAxisSlave); - - U_DUT : entity surf.SrpV3Core - generic map ( - TPD_G => TPD_C, - SLAVE_READY_EN_G => true, - GEN_SYNC_FIFO_G => true, - AXI_STREAM_CONFIG_G => AXIS_CONFIG_C) - port map ( - sAxisClk => AXIS_ACLK, - sAxisRst => axisRst, - sAxisMaster => sAxisMaster, - sAxisSlave => sAxisSlave, - sAxisCtrl => open, - mAxisClk => AXIS_ACLK, - mAxisRst => axisRst, - mAxisMaster => mAxisMaster, - mAxisSlave => mAxisSlave, - srpClk => AXIS_ACLK, - srpRst => axisRst, - srpReq => srpReq, - srpAck => srpAck, - srpWrMaster => wrAxisMaster, - srpWrSlave => wrAxisSlave, - srpRdMaster => rdAxisMaster, - srpRdSlave => rdAxisSlave); - -end architecture rtl; diff --git a/protocols/srp/wrappers/SrpV3CoreWrapper.vhd b/protocols/srp/wrappers/SrpV3CoreWrapper.vhd index f97f056105..d530f162e0 100644 --- a/protocols/srp/wrappers/SrpV3CoreWrapper.vhd +++ b/protocols/srp/wrappers/SrpV3CoreWrapper.vhd @@ -22,6 +22,8 @@ use surf.SsiPkg.all; use surf.SrpV3Pkg.all; entity SrpV3CoreWrapper is + generic ( + CORE_DATA_BYTES_G : positive range 4 to 64 := 8); port ( AXIS_ACLK : in std_logic; AXIS_ARESETN : in std_logic; @@ -68,7 +70,7 @@ architecture rtl of SrpV3CoreWrapper is constant TPD_C : time := 10 ns / 4; constant AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(4); - constant CORE_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(8); + constant CORE_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(CORE_DATA_BYTES_G); signal axisRst : sl := '0'; @@ -216,58 +218,73 @@ begin axisMaster => wrAxisMaster, axisSlave => wrAxisSlave); - -- Width adapters around the 64-bit SRPv3 core-facing stream configuration. - U_InputResize : entity surf.AxiStreamResize - generic map ( - TPD_G => TPD_C, - SLAVE_AXI_CONFIG_G => AXIS_CONFIG_C, - MASTER_AXI_CONFIG_G => CORE_CONFIG_C) - port map ( - axisClk => AXIS_ACLK, - axisRst => axisRst, - sAxisMaster => sAxisMaster, - sAxisSlave => sAxisSlave, - mAxisMaster => coreIbMaster, - mAxisSlave => coreIbSlave); + -- Optional width adapters around the SRPv3 core-facing stream + -- configuration. 32-bit direct-core fault injection bypasses these + -- adapters, while the default 64-bit path preserves the original wrapper. + GEN_DIRECT_CORE : if CORE_DATA_BYTES_G = 4 generate + coreIbMaster <= sAxisMaster; + sAxisSlave <= coreIbSlave; + mAxisMaster <= coreObMaster; + coreObSlave <= mAxisSlave; + coreRdMaster <= rdAxisMaster; + rdAxisSlave <= coreRdSlave; + wrAxisMaster <= coreWrMaster; + coreWrSlave <= wrAxisSlave; + end generate GEN_DIRECT_CORE; - U_OutputResize : entity surf.AxiStreamResize - generic map ( - TPD_G => TPD_C, - SLAVE_AXI_CONFIG_G => CORE_CONFIG_C, - MASTER_AXI_CONFIG_G => AXIS_CONFIG_C) - port map ( - axisClk => AXIS_ACLK, - axisRst => axisRst, - sAxisMaster => coreObMaster, - sAxisSlave => coreObSlave, - mAxisMaster => mAxisMaster, - mAxisSlave => mAxisSlave); + GEN_RESIZE_CORE : if CORE_DATA_BYTES_G /= 4 generate + U_InputResize : entity surf.AxiStreamResize + generic map ( + TPD_G => TPD_C, + SLAVE_AXI_CONFIG_G => AXIS_CONFIG_C, + MASTER_AXI_CONFIG_G => CORE_CONFIG_C) + port map ( + axisClk => AXIS_ACLK, + axisRst => axisRst, + sAxisMaster => sAxisMaster, + sAxisSlave => sAxisSlave, + mAxisMaster => coreIbMaster, + mAxisSlave => coreIbSlave); - U_ReadResize : entity surf.AxiStreamResize - generic map ( - TPD_G => TPD_C, - SLAVE_AXI_CONFIG_G => AXIS_CONFIG_C, - MASTER_AXI_CONFIG_G => CORE_CONFIG_C) - port map ( - axisClk => AXIS_ACLK, - axisRst => axisRst, - sAxisMaster => rdAxisMaster, - sAxisSlave => rdAxisSlave, - mAxisMaster => coreRdMaster, - mAxisSlave => coreRdSlave); + U_OutputResize : entity surf.AxiStreamResize + generic map ( + TPD_G => TPD_C, + SLAVE_AXI_CONFIG_G => CORE_CONFIG_C, + MASTER_AXI_CONFIG_G => AXIS_CONFIG_C) + port map ( + axisClk => AXIS_ACLK, + axisRst => axisRst, + sAxisMaster => coreObMaster, + sAxisSlave => coreObSlave, + mAxisMaster => mAxisMaster, + mAxisSlave => mAxisSlave); - U_WriteResize : entity surf.AxiStreamResize - generic map ( - TPD_G => TPD_C, - SLAVE_AXI_CONFIG_G => CORE_CONFIG_C, - MASTER_AXI_CONFIG_G => AXIS_CONFIG_C) - port map ( - axisClk => AXIS_ACLK, - axisRst => axisRst, - sAxisMaster => coreWrMaster, - sAxisSlave => coreWrSlave, - mAxisMaster => wrAxisMaster, - mAxisSlave => wrAxisSlave); + U_ReadResize : entity surf.AxiStreamResize + generic map ( + TPD_G => TPD_C, + SLAVE_AXI_CONFIG_G => AXIS_CONFIG_C, + MASTER_AXI_CONFIG_G => CORE_CONFIG_C) + port map ( + axisClk => AXIS_ACLK, + axisRst => axisRst, + sAxisMaster => rdAxisMaster, + sAxisSlave => rdAxisSlave, + mAxisMaster => coreRdMaster, + mAxisSlave => coreRdSlave); + + U_WriteResize : entity surf.AxiStreamResize + generic map ( + TPD_G => TPD_C, + SLAVE_AXI_CONFIG_G => CORE_CONFIG_C, + MASTER_AXI_CONFIG_G => AXIS_CONFIG_C) + port map ( + axisClk => AXIS_ACLK, + axisRst => axisRst, + sAxisMaster => coreWrMaster, + sAxisSlave => coreWrSlave, + mAxisMaster => wrAxisMaster, + mAxisSlave => wrAxisSlave); + end generate GEN_RESIZE_CORE; -- DUT. U_DUT : entity surf.SrpV3Core diff --git a/tests/protocols/srp/test_SrpV3AxiLite.py b/tests/protocols/srp/test_SrpV3AxiLite.py index 8897f1adc4..f4361d89ad 100644 --- a/tests/protocols/srp/test_SrpV3AxiLite.py +++ b/tests/protocols/srp/test_SrpV3AxiLite.py @@ -9,15 +9,15 @@ ############################################################################## # Test methodology: -# - Sweep: Keep reset coverage on the direct, full, and legacy-wide wrappers, -# and run active transactions through the direct 256-bit legacy framing that -# matches the existing VHDL testbench. +# - Sweep: Keep reset coverage on the direct, full, and legacy-wide modes, +# run probes and directed checks through the direct/full wrappers, and keep +# one 256-bit legacy-wide directed case matching the existing VHDL testbench. # - Stimulus: Drive SRPv3 write, read, posted-write, and malformed request # frames into each wrapper's SSI-side AXI Stream port. # - Checks: Non-posted writes echo data and update the RAM, posted writes remain # silent but are readable later, invalid requests set the expected footer bits -# without returning payload data, and known-issue probes preserve the narrowed -# 32-bit multi-beat failure mode. +# without returning payload data, and the legacy-wide case keeps the 256-bit +# wrapper framing path covered without duplicating every narrow probe. # - Timing: The bench uses ready/valid handshakes on every AXI Stream beat and # bounded response waits so a stalled SRP request fails deterministically. @@ -228,7 +228,7 @@ async def srpv3_axilite_read_write_and_error_paths_test(dut): ) -PARAMETER_SWEEP = [ +ACTIVE_PARAMETER_SWEEP = [ pytest.param( { "TOPLEVEL": "surf.srpv3axilitewrapper", @@ -243,78 +243,70 @@ async def srpv3_axilite_read_write_and_error_paths_test(dut): }, id="srpv3_axilite_full", ), +] + +RESET_PARAMETER_SWEEP = [ + *ACTIVE_PARAMETER_SWEEP, pytest.param( { - "TOPLEVEL": "surf.srpv3axilitewidewrapper", - "WRAPPER_SOURCE": "protocols/srp/wrappers/SrpV3AxiLiteWideWrapper.vhd", - "SRP_AXIS_BYTES": 32, + "TOPLEVEL": "surf.srpv3axilitewrapper", + "WRAPPER_SOURCE": "protocols/srp/wrappers/SrpV3AxiLiteWrapper.vhd", + "HDL_PARAMETERS": {"DATA_BYTES_G": 32}, + "EXTRA_ENV": {"SRP_AXIS_BYTES": 32}, }, id="srpv3_axilite_direct_wide", ), ] LEGACY_WIDE_DIRECT_PARAMETERS = { - "TOPLEVEL": "surf.srpv3axilitewidewrapper", - "WRAPPER_SOURCE": "protocols/srp/wrappers/SrpV3AxiLiteWideWrapper.vhd", - "SRP_AXIS_BYTES": 32, + "TOPLEVEL": "surf.srpv3axilitewrapper", + "WRAPPER_SOURCE": "protocols/srp/wrappers/SrpV3AxiLiteWrapper.vhd", + "HDL_PARAMETERS": {"DATA_BYTES_G": 32}, + "EXTRA_ENV": {"SRP_AXIS_BYTES": 32}, } def _run_srpv3_axilite_case(parameters, cocotb_test: str, build_label: str): - extra_env = dict(parameters) + hdl_parameters = parameters.get("HDL_PARAMETERS", {}) + extra_env = dict(parameters.get("EXTRA_ENV", {})) extra_env["SRP_AXI_LITE_COCOTB_TEST"] = cocotb_test + build_suffix = "" + if hdl_parameters: + build_suffix = "." + ".".join( + f"{key}_{value}" for key, value in hdl_parameters.items() + ) run_surf_vhdl_test( test_file=__file__, toplevel=parameters["TOPLEVEL"], - parameters={}, + parameters=hdl_parameters, extra_env=extra_env, extra_vhdl_sources={"surf": [parameters["WRAPPER_SOURCE"]]}, - sim_build_key=f"tests/sim_build/protocols/srp/test_SrpV3AxiLite.{build_label}.{parameters['TOPLEVEL'].split('.')[-1]}", + sim_build_key=f"tests/sim_build/protocols/srp/test_SrpV3AxiLite.{build_label}.{parameters['TOPLEVEL'].split('.')[-1]}{build_suffix}", ) -def _known_issue_opt_in_enabled() -> bool: - return os.environ.get("RUN_KNOWN_ISSUE_TESTS", "0") == "1" - - -def _skip_opt_in_probe(parameters): - if parameters["TOPLEVEL"] == "surf.srpv3axilitewidewrapper" and not _known_issue_opt_in_enabled(): - pytest.skip("Direct and Full SRPv3AxiLite probes are active; duplicate wide-wrapper probes stay opt-in.") - - -def _skip_opt_in_directed(parameters): - if parameters["TOPLEVEL"] == "surf.srpv3axilitewidewrapper" and not _known_issue_opt_in_enabled(): - pytest.skip( - "Direct and Full SRPv3AxiLite directed coverage are active; duplicate wide-wrapper cases stay opt-in." - ) - - -@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +@pytest.mark.parametrize("parameters", RESET_PARAMETER_SWEEP) def test_SrpV3AxiLite_reset_idle(parameters): _run_srpv3_axilite_case(parameters, "reset_idle", "reset_idle") -@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +@pytest.mark.parametrize("parameters", ACTIVE_PARAMETER_SWEEP) def test_SrpV3AxiLite_short_frame_probe(parameters): - _skip_opt_in_probe(parameters) _run_srpv3_axilite_case(parameters, "short_frame", "short_frame") -@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +@pytest.mark.parametrize("parameters", ACTIVE_PARAMETER_SWEEP) def test_SrpV3AxiLite_four_beat_header_probe(parameters): - _skip_opt_in_probe(parameters) _run_srpv3_axilite_case(parameters, "four_beat_header", "four_beat_header") -@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +@pytest.mark.parametrize("parameters", ACTIVE_PARAMETER_SWEEP) def test_SrpV3AxiLite_single_read_probe(parameters): - _skip_opt_in_probe(parameters) _run_srpv3_axilite_case(parameters, "single_read", "single_read") -@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +@pytest.mark.parametrize("parameters", ACTIVE_PARAMETER_SWEEP) def test_SrpV3AxiLite(parameters): - _skip_opt_in_directed(parameters) _run_srpv3_axilite_case(parameters, "directed", "directed") diff --git a/tests/protocols/srp/test_SrpV3Core.py b/tests/protocols/srp/test_SrpV3Core.py index caf551b7cb..277f28ee18 100644 --- a/tests/protocols/srp/test_SrpV3Core.py +++ b/tests/protocols/srp/test_SrpV3Core.py @@ -9,22 +9,33 @@ ############################################################################## # Test methodology: -# - Sweep: Keep one direct `SrpV3Core` wrapper smoke case while functional -# SRPv3Core behavior is exercised transitively through the `SrpV3Axi` matrix. +# - Sweep: Cover the default 64-bit core-facing wrapper path with reset/idle +# smoke, then use the same wrapper with `CORE_DATA_BYTES_G => 4` for direct +# core-local fault injection. # - Stimulus: Reset the wrapper with all exposed SRP, read-data, and stream -# inputs held idle. -# - Checks: The direct wrapper must elaborate, leave downstream request and -# write-output strobes idle after reset, and keep the response stream idle. -# - Timing: The bench samples after multiple post-reset clock edges so reset -# release and wrapper resize pipelines have time to settle. +# inputs held idle, or drive malformed/valid narrow SRPv3 request headers +# while directly controlling downstream ack/read-data return signals. +# - Checks: The default wrapper must elaborate and stay idle after reset. The +# narrow core mode must emit aligned error responses for truncated headers +# and immediate downstream read rejection without requiring a read-data beat. +# - Timing: Sources obey ready/valid sampling, and the downstream ack path is +# pulsed cycle-accurately to exercise the `READ_S` to `WAIT_ACK_S` corner. import cocotb +import os import pytest from cocotb.clock import Clock from cocotb.triggers import RisingEdge from tests.common.regression_utils import run_surf_vhdl_test -from tests.protocols.srp.srp_test_utils import FlatSrpAxis +from tests.protocols.srp.srp_test_utils import ( + FOOTER_ADDRESS_ERROR, + FOOTER_FRAME_ERROR, + FlatSrpAxis, + SRP_READ, + SrpV3Request, + assert_srpv3_response, +) class TB: @@ -34,9 +45,7 @@ def __init__(self, dut): self.axis = FlatSrpAxis(dut, clk=dut.AXIS_ACLK) self.read_axis = FlatSrpAxis(dut, clk=dut.AXIS_ACLK, source_prefix="RD_AXIS", sink_prefix="WR_AXIS") - async def reset(self): - # Hold every exposed stimulus side idle so this direct-core smoke is - # only checking reset/elaboration behavior, not a duplicated AXI matrix. + async def reset(self, *, settle_cycles: int = 8): self.dut.AXIS_ARESETN.setimmediatevalue(0) self.axis.init_source() self.axis.init_sink() @@ -47,26 +56,141 @@ async def reset(self): for _ in range(80): await RisingEdge(self.dut.AXIS_ACLK) self.dut.AXIS_ARESETN.value = 1 - for _ in range(32): + for _ in range(settle_cycles): await RisingEdge(self.dut.AXIS_ACLK) +def _selected_cocotb_test(name: str) -> bool: + return os.environ.get("SRP_CORE_COCOTB_TEST", "reset_idle") == name + + @cocotb.test() async def srpv3_core_reset_idle_smoke_test(dut): + if not _selected_cocotb_test("reset_idle"): + return + tb = TB(dut) - await tb.reset() + await tb.reset(settle_cycles=32) assert int(dut.SRP_REQ_REQUEST.value) == 0 assert int(dut.M_AXIS_TVALID.value) == 0 assert int(dut.WR_AXIS_TVALID.value) == 0 -@pytest.mark.parametrize("parameters", [pytest.param({}, id="direct_core_reset_idle")]) +@cocotb.test() +async def srpv3_core_narrow_header_error_probes_test(dut): + if not _selected_cocotb_test("narrow_fault_injection"): + return + + tb = TB(dut) + await tb.reset() + + await tb.axis.send_words([0x0000_0003]) + short_response = await tb.axis.recv_response() + assert_srpv3_response( + short_response, + SrpV3Request(SRP_READ, 0, 0, 1), + payload=[], + footer_mask=FOOTER_FRAME_ERROR, + footer_value=FOOTER_FRAME_ERROR, + ) + assert int(dut.SRP_REQ_REQUEST.value) == 0 + + await tb.axis.send_words( + [ + 0x0000_0003, + 0x5100_0200, + 0x0000_0020, + 0x0000_0000, + ], + tdest=0x3, + ) + four_beat_response = await tb.axis.recv_response() + assert_srpv3_response( + four_beat_response, + SrpV3Request(SRP_READ, 0x5100_0200, 0x20, 1), + payload=[], + footer_mask=FOOTER_FRAME_ERROR, + footer_value=FOOTER_FRAME_ERROR, + expected_tdest=0x3, + ) + assert int(dut.SRP_REQ_REQUEST.value) == 0 + + +@cocotb.test() +async def srpv3_core_narrow_immediate_read_error_test(dut): + if not _selected_cocotb_test("narrow_fault_injection"): + return + + tb = TB(dut) + await tb.reset() + dut.M_AXIS_TREADY.value = 0 + + request = SrpV3Request(SRP_READ, 0x6100_0001, 0x1_0000_0000, 4) + await tb.axis.send_words(request.response_header, tdest=0x5) + + for _ in range(64): + await RisingEdge(dut.AXIS_ACLK) + if int(dut.SRP_REQ_REQUEST.value) == 1: + break + else: + raise AssertionError("Timed out waiting for SRP_REQ_REQUEST") + + dut.SRP_ACK_RESP.value = FOOTER_ADDRESS_ERROR + dut.SRP_ACK_DONE.value = 1 + for _ in range(8): + await RisingEdge(dut.AXIS_ACLK) + if int(dut.SRP_REQ_REQUEST.value) == 0: + break + else: + raise AssertionError("Timed out waiting for SRP_REQ_REQUEST to release") + dut.SRP_ACK_DONE.value = 0 + dut.SRP_ACK_RESP.value = 0 + + for _ in range(64): + await RisingEdge(dut.AXIS_ACLK) + if int(dut.M_AXIS_TVALID.value) == 1: + break + else: + raise AssertionError("Timed out waiting for response header to become visible") + + response = await tb.axis.recv_response() + assert_srpv3_response( + response, + request, + payload=[], + footer_mask=FOOTER_ADDRESS_ERROR, + footer_value=FOOTER_ADDRESS_ERROR, + expected_tdest=0x5, + ) + assert int(dut.RD_AXIS_TREADY.value) == 0 + + +CORE_PARAMETER_SWEEP = [ + pytest.param( + { + "COCOTB_TEST": "reset_idle", + "HDL_PARAMETERS": {}, + }, + id="direct_core_reset_idle", + ), + pytest.param( + { + "COCOTB_TEST": "narrow_fault_injection", + "HDL_PARAMETERS": {"CORE_DATA_BYTES_G": 4}, + }, + id="direct_core_narrow_fault_injection", + ), +] + + +@pytest.mark.parametrize("parameters", CORE_PARAMETER_SWEEP) def test_SrpV3Core(parameters): + hdl_parameters = parameters["HDL_PARAMETERS"] run_surf_vhdl_test( test_file=__file__, toplevel="surf.srpv3corewrapper", - parameters=parameters, - extra_env=parameters, + parameters=hdl_parameters, + extra_env={"SRP_CORE_COCOTB_TEST": parameters["COCOTB_TEST"]}, extra_vhdl_sources={"surf": ["protocols/srp/wrappers/SrpV3CoreWrapper.vhd"]}, ) diff --git a/tests/protocols/srp/test_SrpV3CoreNarrow.py b/tests/protocols/srp/test_SrpV3CoreNarrow.py deleted file mode 100644 index d2047d3e3a..0000000000 --- a/tests/protocols/srp/test_SrpV3CoreNarrow.py +++ /dev/null @@ -1,154 +0,0 @@ -############################################################################## -## This file is part of 'SLAC Firmware Standard Library'. -## It is subject to the license terms in the LICENSE.txt file found in the -## top-level directory of this distribution and at: -## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -## No part of 'SLAC Firmware Standard Library', including this file, -## may be copied, modified, propagated, or distributed except according to -## the terms contained in the LICENSE.txt file. -############################################################################## - -# Test methodology: -# - Sweep: Keep one direct 32-bit `SrpV3Core` bench focused on core-local -# failure modes that are awkward to inject cleanly through the larger AXI and -# AXI-Lite wrappers. -# - Stimulus: Drive malformed or valid narrow SRPv3 request headers into the -# core-facing stream while directly controlling the downstream ack/read-data -# return signals. -# - Checks: A truncated request header must still produce a correctly aligned -# error response header, and an immediate downstream read rejection must -# complete with the expected footer bit even when no read-data beat arrives. -# - Timing: The source and sink obey ready/valid sampling, while the downstream -# ack path is pulsed cycle-accurately to exercise the `READ_S` to `WAIT_ACK_S` -# corner case directly. - -import cocotb -import pytest -from cocotb.clock import Clock -from cocotb.triggers import RisingEdge - -from tests.common.regression_utils import run_surf_vhdl_test -from tests.protocols.srp.srp_test_utils import ( - FOOTER_ADDRESS_ERROR, - FOOTER_FRAME_ERROR, - FlatSrpAxis, - SRP_READ, - SrpV3Request, - assert_srpv3_response, -) - - -class TB: - def __init__(self, dut): - self.dut = dut - cocotb.start_soon(Clock(dut.AXIS_ACLK, 10.0, unit="ns").start()) - self.axis = FlatSrpAxis(dut, clk=dut.AXIS_ACLK) - self.read_axis = FlatSrpAxis(dut, clk=dut.AXIS_ACLK, source_prefix="RD_AXIS", sink_prefix="WR_AXIS") - - async def reset(self): - self.dut.AXIS_ARESETN.setimmediatevalue(0) - self.axis.init_source() - self.axis.init_sink() - self.read_axis.init_source(prefix="RD_AXIS") - self.read_axis.init_sink(prefix="WR_AXIS") - self.dut.SRP_ACK_DONE.setimmediatevalue(0) - self.dut.SRP_ACK_RESP.setimmediatevalue(0) - for _ in range(80): - await RisingEdge(self.dut.AXIS_ACLK) - self.dut.AXIS_ARESETN.value = 1 - for _ in range(8): - await RisingEdge(self.dut.AXIS_ACLK) - - -@cocotb.test() -async def srpv3_core_narrow_header_error_probes_test(dut): - tb = TB(dut) - await tb.reset() - - await tb.axis.send_words([0x0000_0003]) - short_response = await tb.axis.recv_response() - assert_srpv3_response( - short_response, - SrpV3Request(SRP_READ, 0, 0, 1), - payload=[], - footer_mask=FOOTER_FRAME_ERROR, - footer_value=FOOTER_FRAME_ERROR, - ) - assert int(dut.SRP_REQ_REQUEST.value) == 0 - - await tb.axis.send_words( - [ - 0x0000_0003, - 0x5100_0200, - 0x0000_0020, - 0x0000_0000, - ], - tdest=0x3, - ) - four_beat_response = await tb.axis.recv_response() - assert_srpv3_response( - four_beat_response, - SrpV3Request(SRP_READ, 0x5100_0200, 0x20, 1), - payload=[], - footer_mask=FOOTER_FRAME_ERROR, - footer_value=FOOTER_FRAME_ERROR, - expected_tdest=0x3, - ) - assert int(dut.SRP_REQ_REQUEST.value) == 0 - - -@cocotb.test() -async def srpv3_core_narrow_immediate_read_error_test(dut): - tb = TB(dut) - await tb.reset() - dut.M_AXIS_TREADY.value = 0 - - request = SrpV3Request(SRP_READ, 0x6100_0001, 0x1_0000_0000, 4) - await tb.axis.send_words(request.response_header, tdest=0x5) - - for _ in range(64): - await RisingEdge(dut.AXIS_ACLK) - if int(dut.SRP_REQ_REQUEST.value) == 1: - break - else: - raise AssertionError("Timed out waiting for SRP_REQ_REQUEST") - - dut.SRP_ACK_RESP.value = FOOTER_ADDRESS_ERROR - dut.SRP_ACK_DONE.value = 1 - for _ in range(8): - await RisingEdge(dut.AXIS_ACLK) - if int(dut.SRP_REQ_REQUEST.value) == 0: - break - else: - raise AssertionError("Timed out waiting for SRP_REQ_REQUEST to release") - dut.SRP_ACK_DONE.value = 0 - dut.SRP_ACK_RESP.value = 0 - - for _ in range(64): - await RisingEdge(dut.AXIS_ACLK) - if int(dut.M_AXIS_TVALID.value) == 1: - break - else: - raise AssertionError("Timed out waiting for response header to become visible") - - response = await tb.axis.recv_response() - assert_srpv3_response( - response, - request, - payload=[], - footer_mask=FOOTER_ADDRESS_ERROR, - footer_value=FOOTER_ADDRESS_ERROR, - expected_tdest=0x5, - ) - assert int(dut.RD_AXIS_TREADY.value) == 0 - - -@pytest.mark.parametrize("parameters", [pytest.param({}, id="direct_core_narrow")]) -def test_SrpV3CoreNarrow(parameters): - run_surf_vhdl_test( - test_file=__file__, - toplevel="surf.srpv3corenarrowwrapper", - parameters=parameters, - extra_env=parameters, - extra_vhdl_sources={"surf": ["protocols/srp/wrappers/SrpV3CoreNarrowWrapper.vhd"]}, - ) From f59f1bae3be360c065807c5bcf12b53567f8382a Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Sat, 2 May 2026 22:42:02 -0700 Subject: [PATCH 83/92] Add more SRPv0 tests. --- docs/_meta/rtl_regression_handoff.md | 4 +- docs/_meta/rtl_regression_progress.md | 11 +- .../srp/wrappers/AxiLiteSrpV0Wrapper.vhd | 204 ++++++++++++++++ .../srp/wrappers/SrpV0AxiLiteWrapper.vhd | 207 ++++++++++++++++ tests/protocols/srp/test_AxiLiteSrpV0.py | 168 +++++++++++++ tests/protocols/srp/test_SrpV0AxiLite.py | 220 ++++++++++++++++++ 6 files changed, 807 insertions(+), 7 deletions(-) create mode 100644 protocols/srp/wrappers/AxiLiteSrpV0Wrapper.vhd create mode 100644 protocols/srp/wrappers/SrpV0AxiLiteWrapper.vhd create mode 100644 tests/protocols/srp/test_AxiLiteSrpV0.py create mode 100644 tests/protocols/srp/test_SrpV0AxiLite.py diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index 345cd2dffe..5d6cd48444 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -27,7 +27,7 @@ - The remaining CoaXPress pure-VHDL gap is now `CoaXPressConfig`. The current CoaXPress receive benches now include a dual-lane `CoaXPressRxHsFsm` step/alignment case, a dual-lane `CoaXPressRx` lane-rotation case, and event packet validation through payload size, payload words, CRC, and `EOP` before `eventAck`. The receive side is still intentionally mixed-depth: event payload is validated for parser/CRC behavior but is not exported through an application-facing payload interface, and the multi-lane assembly checks still stop short of exhaustive per-lane stress coverage. - The latest CXPoF bridge guardrail work is now reflected at both leaf and top level: `CoaXPressOverFiberBridgeRx` covers HKP-to-payload mixing and malformed lane-placement checks for `/S/`, `/Q/`, `/T/`, and `/E/`, while `CoaXPressOverFiberBridge` covers 64-bit RX gearbox traversal for `/E/` abort/recovery, HKP-to-payload transition, and lane-0 `/Q/` no-output/recovery. Treat these as current-RTL regression guardrails rather than complete normative `/Q/`, `/E/`, or housekeeping protocol coverage. - `tests/protocols/coaxpress/test_CoaXPressConfig.py` is intentionally checked in as a skipped investigation bench. When driven through the real SRP ingress, the current `CoaXPressConfig` / `SrpV3AxiLite` integration does not complete the request path within the bench timeout, so treat that as a likely RTL or integration defect to debug before re-enabling active assertions there. - - `tests/protocols/srp/test_SrpV3Axi.py` is now the active SRPv3 AXI regression, not just the old legacy-style posted-write/readback smoke. It validates non-posted write echo/readback, posted-write no-response behavior, NULL responses, response backpressure, TDEST propagation, full-word `TKEEP`, and footer bits for version mismatch, malformed write framing, invalid alignment, invalid request size, downstream write address error, and downstream read address error. `tests/protocols/srp/test_SrpV3Core.py` now covers direct reset/idle smoke for the default `SrpV3CoreWrapper` mode plus direct 32-bit malformed-header and immediate-read-error fault injection through `CORE_DATA_BYTES_G => 4`. That narrow mode exposed and now covers two real `SrpV3Core` bugs: the response-header counter was not reset when emitting an error response from a truncated request header, and `READ_S` could miss an immediate downstream read error before any payload beat arrived. `tests/protocols/srp/test_SrpV0Loopback.py` covers `AxiLiteSrpV0` and `SrpV0AxiLite` together through the checked-in SRPv0 stream loopback wrapper. `tests/protocols/srp/test_SrpV3AxiLite.py` now carries active reset/idle smoke for direct, full, and legacy-wide `DATA_BYTES_G => 32` modes, active narrow probes for the direct and full wrappers, active directed regressions for the direct and full wrappers, and one active legacy-wide directed regression. The duplicate wide-wrapper probe/direct cases were removed instead of kept as skipped opt-in coverage, and the old wide/narrow-only SRP wrapper files were folded into generics, leaving the default `tests/protocols/srp` run skip-free. The direct narrow `SrpV3AxiLite` issue turned out to be a bench artifact, not an RTL defect: `tests/protocols/srp/srp_test_utils.py` now holds each source beat until a sampled clock edge confirms `TREADY`, which fixes the false failure on the original `SsiFrameLimiter` bypass configuration (`SLAVE_FIFO_G => false`). The focused `tests/protocols/ssi/test_SsiFrameLimiter.py` isolation regressions remain green in both limiter modes. + - `tests/protocols/srp/test_SrpV3Axi.py` is now the active SRPv3 AXI regression, not just the old legacy-style posted-write/readback smoke. It validates non-posted write echo/readback, posted-write no-response behavior, NULL responses, response backpressure, TDEST propagation, full-word `TKEEP`, and footer bits for version mismatch, malformed write framing, invalid alignment, invalid request size, downstream write address error, and downstream read address error. `tests/protocols/srp/test_SrpV3Core.py` now covers direct reset/idle smoke for the default `SrpV3CoreWrapper` mode plus direct 32-bit malformed-header and immediate-read-error fault injection through `CORE_DATA_BYTES_G => 4`. That narrow mode exposed and now covers two real `SrpV3Core` bugs: the response-header counter was not reset when emitting an error response from a truncated request header, and `READ_S` could miss an immediate downstream read error before any payload beat arrived. SRPv0 now has direct bridge-half coverage plus loopback coverage: `tests/protocols/srp/test_AxiLiteSrpV0.py` checks request packing and bad-response handling through `AxiLiteSrpV0Wrapper`, `tests/protocols/srp/test_SrpV0AxiLite.py` checks legacy frame parsing/status/address expansion through `SrpV0AxiLiteWrapper`, and `tests/protocols/srp/test_SrpV0Loopback.py` still covers `AxiLiteSrpV0` and `SrpV0AxiLite` together through the checked-in stream loopback wrapper. `tests/protocols/srp/test_SrpV3AxiLite.py` now carries active reset/idle smoke for direct, full, and legacy-wide `DATA_BYTES_G => 32` modes, active narrow probes for the direct and full wrappers, active directed regressions for the direct and full wrappers, and one active legacy-wide directed regression. The duplicate wide-wrapper probe/direct cases were removed instead of kept as skipped opt-in coverage, and the old wide/narrow-only SRP wrapper files were folded into generics, leaving the default `tests/protocols/srp` run skip-free. The direct narrow `SrpV3AxiLite` issue turned out to be a bench artifact, not an RTL defect: `tests/protocols/srp/srp_test_utils.py` now holds each source beat until a sampled clock edge confirms `TREADY`, which fixes the false failure on the original `SsiFrameLimiter` bypass configuration (`SLAVE_FIFO_G => false`). The focused `tests/protocols/ssi/test_SsiFrameLimiter.py` isolation regressions remain green in both limiter modes. - The broader flat-stream helper cleanup is now partially checked in beyond SRP. `tests/axi/utils.py` owns the shared `wait_sampled_ready()` primitive, and the flattened helper layers in `tests/protocols/ssi/ssi_test_utils.py`, `tests/protocols/srp/srp_test_utils.py`, `tests/protocols/pgp/pgp4/pgp4_test_utils.py`, `tests/protocols/coaxpress/coaxpress_test_utils.py`, `tests/ethernet/EthMacCore/ethmac_test_utils.py`, and `tests/ethernet/RawEthFramer/raw_eth_test_utils.py` now use it where appropriate instead of open-coded sampled-ready loops. Direct one-off benches that were good fits for the same cleanup now include `tests/protocols/srp/test_SrpV3Axi.py`, `tests/protocols/ssi/test_SsiResizeFifoEofe.py`, `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, `tests/protocols/coaxpress/test_CoaXPressTx.py`, `tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py`, and `tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py`. - One subtle point from that cleanup is important for future edits: `wait_sampled_ready()` returns after the accepting clock edge has already occurred. A source must therefore advance or deassert immediately after the helper returns; leaving an extra post-handshake clock in place can create duplicate transfers or malformed streams. The current checked-in cleanup already corrected the false regressions that came from that mistake. - The current validation subset for the flat-driver cleanup is `174 passed` across `tests/protocols/srp/test_SrpV3Axi.py`, `tests/protocols/ssi/test_SsiResizeFifoEofe.py`, the active PGP4 flat-wrapper subset, `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, `tests/protocols/coaxpress/test_CoaXPressTx.py`, `tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py`, and `tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py`. @@ -179,7 +179,7 @@ A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instan ## Immediate Next Task If the user keeps the focus on stream-helper cleanup rather than resuming a new subsystem, the next practical step is the remaining PGP interleaved source/capture helpers: decide whether `tests/protocols/pgp/pgp4/test_Pgp4Rx.py` and the protocol-word collector in `tests/protocols/pgp/pgp4/pgp4_test_utils.py` should stay intentionally manual or be folded into a richer shared helper that can hold a source beat through acceptance while concurrently capturing narrow output pulses. -If the user keeps the focus on `protocols/srp`, the next practical step inside that subsystem is deeper isolated coverage rather than rescue work: consider whether `tests/protocols/srp/test_SrpV3Core.py` should absorb more of the protocol-error matrix that is currently only covered transitively through `SrpV3Axi` and `SrpV3AxiLite`. +If the user keeps the focus on `protocols/srp`, the next practical step inside that subsystem is deeper isolated SRPv3 coverage rather than SRPv0 rescue work: consider whether `tests/protocols/srp/test_SrpV3Core.py` should absorb more of the protocol-error matrix that is currently only covered transitively through `SrpV3Axi` and `SrpV3AxiLite`. The latest focused SRP validation command is `./.venv/bin/python -m pytest -n 0 -q tests/protocols/srp`, and it passed locally with `19 passed`. If the user switches back to `protocols/coaxpress`, the next practical step is either: 1. debug and re-enable the skipped `CoaXPressConfig` investigation bench, starting with the SRP-driven request path that currently fails to complete through the real `CoaXPressConfig` / `SrpV3AxiLite` integration, or diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index f87e3cb47d..23c76e094f 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -3,8 +3,8 @@ ## Summary - Current phase: Phase-1 implementation active - Current subsystem: manual user-directed rollout tracking -- Current focus module: user-directed `protocols/srp` regression cleanup after merging the SRP branch onto the current `verification-2` frontier, while preserving the recently validated CoaXPress pure-VHDL rollout under `protocols/coaxpress/core/rtl`. -- Last updated: 2026-05-01 +- Current focus module: user-directed `protocols/srp` regression cleanup after merging the SRP branch onto the current `verification-2` frontier, now including direct SRPv0 bridge-half coverage plus the existing loopback check. +- Last updated: 2026-05-03 ## Current Frontier Snapshot - Active planning rule: take the next work item from the user's manual direction, not from `docs/_meta/rtl_phase1_queue.{md,json}`. @@ -34,7 +34,7 @@ - Covered now under the current GHDL-only flow: `SrpV3Axi` through the checked-in `protocols/srp/wrappers/SrpV3AxiWrapper.vhd` wrapper and `tests/protocols/srp/test_SrpV3Axi.py`. - The current SRPv3 AXI bench now validates non-posted write echo/readback, posted-write no-response behavior followed by readback, NULL header/footer behavior, response backpressure hold, TDEST propagation, full-word `TKEEP`, and footer bits for version mismatch, malformed write framing, invalid alignment, invalid request size, and downstream address error. - `SrpV3Core` now has a direct checked-in wrapper with reset/idle smoke coverage plus a narrow 32-bit fault-injection mode for malformed-header and immediate-read-error behavior. `tests/protocols/srp/test_SrpV3Core.py` now uses `SrpV3CoreWrapper` in both default mode and `CORE_DATA_BYTES_G => 4` mode instead of carrying a separate narrow test file. The narrow mode exposed and now covers two core-side bugs: the response-header counter was not reset when emitting an error response from a truncated request header, and `READ_S` could miss an immediate downstream read error before any payload beat arrived. - - `AxiLiteSrpV0` and `SrpV0AxiLite` are now covered together by `protocols/srp/wrappers/SrpV0LoopbackWrapper.vhd` and `tests/protocols/srp/test_SrpV0Loopback.py`, which uses cocotb AXI-Lite master helpers to write/read through the old SRPv0 stream loopback and attached RAM. + - `AxiLiteSrpV0` and `SrpV0AxiLite` are now covered directly and together. `tests/protocols/srp/test_AxiLiteSrpV0.py` uses `protocols/srp/wrappers/AxiLiteSrpV0Wrapper.vhd` to validate AXI-Lite-to-SRPv0 request field packing, read data return, bad-response `SLVERR`, and bleed/recovery behavior. `tests/protocols/srp/test_SrpV0AxiLite.py` uses `protocols/srp/wrappers/SrpV0AxiLiteWrapper.vhd` to validate multi-word write/read frames, malformed/unsupported request status failures, and `EN_32BIT_ADDR_G` address expansion. `tests/protocols/srp/test_SrpV0Loopback.py` still covers both bridge halves together through the checked-in stream loopback wrapper and attached RAM. - SRPv3 AXI-Lite status: `tests/protocols/srp/test_SrpV3AxiLite.py` now has active reset/idle coverage for the direct, full, and legacy-wide `DATA_BYTES_G => 32` modes, active narrow probes (`short_frame`, `four_beat_header`, and `single_read`) for both the direct and full wrappers, active directed regressions for the direct and full wrappers, and one active legacy-wide directed regression. The earlier direct-wrapper failure was not an `SrpV3AxiLite` ingress RTL defect after all: the real issue was in `tests/protocols/srp/srp_test_utils.py`, where `FlatSrpAxis.send_packed_words()` treated combinational `TREADY` as immediate acceptance instead of holding each beat until a sampled clock edge confirmed the handshake. With that helper fixed and the two `SrpV3Core` fixes in place, the direct and full `SrpV3AxiLite` paths now pass on the original `SsiFrameLimiter` bypass configuration (`SLAVE_FIFO_G => false`), and the focused standalone `tests/protocols/ssi/test_SsiFrameLimiter.py` regressions remain green in both limiter modes. The duplicate wide-wrapper probe/direct cases were removed rather than kept as skipped opt-in coverage, and the old wide/narrow-only SRP wrapper files were folded into generics, so the default `tests/protocols/srp` run is now skip-free. - Flat AXI/SSI helper cleanup status: - `tests/axi/utils.py` now owns the shared `wait_sampled_ready()` primitive for flattened ready/valid sources that cannot use `cocotbext.axi.AxiStreamSource` directly. @@ -162,13 +162,14 @@ - The new package-surface coverage exposed a real `Code12b14bPkg` invalid-K disparity bug; `protocols/line-codes/rtl/Code12b14bPkg.vhd` now leaves `dispOut` unchanged on illegal K requests instead of tripping a GHDL bound-check failure. ## Current In-Progress Item -- Finish reviewing the `srp-tests` to `verification-2` merge after removing the duplicate SRPv3 AXI-Lite wide-wrapper skip cases. The docs keep the newer CoaXPress frontier from `verification-2` while adding the SRP regression matrix, `SrpV3Core` RTL fixes, SRPv0 loopback coverage, and shared sampled-ready helper cleanup from `srp-tests`. +- Finish reviewing the `protocols/srp` work after adding the direct SRPv0 bridge-half coverage. The docs keep the newer CoaXPress frontier from `verification-2` while adding the SRP regression matrix, `SrpV3Core` RTL fixes, SRPv0 direct/loopback coverage, and shared sampled-ready helper cleanup from `srp-tests`. - Keep the CoaXPress suite as an already validated current branch slice. The focused CoaXPress validation command is `./.venv/bin/python -m pytest -n auto --dist=worksteal -q tests/protocols/coaxpress`, and the latest pre-merge run passed with `17 passed, 1 skipped`. - Treat the skipped `CoaXPressConfig` bench and the opt-in `CoaXPressCore` overflow/FSM-error known-issue bench as the main open protocol cleanup items after the SRP duplicate wide-wrapper skips were removed. - Preserve the recent `pgp4` lesson for later PGP work: when the simulation wrapper only exposes stable lock/config surfaces, write the bench around those explicit contracts instead of claiming recovered payload coverage. +- Latest focused SRP validation: `./.venv/bin/python -m pytest -n 0 -q tests/protocols/srp` passed locally with `19 passed`. ## Next 3 Concrete Tasks -- Review and commit the staged `srp-tests` merge once local validation and code review are satisfactory. +- Finish the user-requested review of the uncommitted `protocols/srp` work; staging and committing remain user-controlled. - Consider whether `tests/protocols/srp/test_SrpV3Core.py` should absorb more of the protocol-error matrix that is currently only covered transitively through `SrpV3Axi` and `SrpV3AxiLite`. - If staying on CoaXPress immediately after the merge, debug the skipped `CoaXPressConfig` / `SrpV3AxiLite` request path before adding broader optional coverage. diff --git a/protocols/srp/wrappers/AxiLiteSrpV0Wrapper.vhd b/protocols/srp/wrappers/AxiLiteSrpV0Wrapper.vhd new file mode 100644 index 0000000000..d5541942ed --- /dev/null +++ b/protocols/srp/wrappers/AxiLiteSrpV0Wrapper.vhd @@ -0,0 +1,204 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for AxiLiteSrpV0 direct testing +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; +use surf.AxiStreamPkg.all; +use surf.SsiPkg.all; + +entity AxiLiteSrpV0Wrapper is + port ( + AXIS_ACLK : in std_logic; + AXIS_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(11 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(31 downto 0); + S_AXI_WSTRB : in std_logic_vector(3 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(11 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(31 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic; + S_AXIS_TVALID : in std_logic; + S_AXIS_TDATA : in std_logic_vector(127 downto 0); + S_AXIS_TKEEP : in std_logic_vector(15 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TUSER : in std_logic_vector(1 downto 0); + S_AXIS_TREADY : out std_logic; + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector(127 downto 0); + M_AXIS_TKEEP : out std_logic_vector(15 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TUSER : out std_logic_vector(1 downto 0); + M_AXIS_TREADY : in std_logic); +end entity AxiLiteSrpV0Wrapper; + +architecture rtl of AxiLiteSrpV0Wrapper is + + constant TPD_C : time := 10 ns / 4; + constant AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(16); + + signal axisRst : sl := '0'; + + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + axisRst <= not AXIS_ARESETN; + + -- AXI-Lite shim layer for cocotb-driven register requests. + U_ShimLayerAxil : entity surf.SlaveAxiLiteIpIntegrator + generic map ( + INTERFACENAME => "S_AXI", + EN_ERROR_RESP => true, + HAS_PROT => 1, + HAS_WSTRB => 1, + ADDR_WIDTH => 12) + port map ( + S_AXI_ACLK => AXIS_ACLK, + S_AXI_ARESETN => AXIS_ARESETN, + S_AXI_AWADDR => S_AXI_AWADDR, + S_AXI_AWPROT => S_AXI_AWPROT, + S_AXI_AWVALID => S_AXI_AWVALID, + S_AXI_AWREADY => S_AXI_AWREADY, + S_AXI_WDATA => S_AXI_WDATA, + S_AXI_WSTRB => S_AXI_WSTRB, + S_AXI_WVALID => S_AXI_WVALID, + S_AXI_WREADY => S_AXI_WREADY, + S_AXI_BRESP => S_AXI_BRESP, + S_AXI_BVALID => S_AXI_BVALID, + S_AXI_BREADY => S_AXI_BREADY, + S_AXI_ARADDR => S_AXI_ARADDR, + S_AXI_ARPROT => S_AXI_ARPROT, + S_AXI_ARVALID => S_AXI_ARVALID, + S_AXI_ARREADY => S_AXI_ARREADY, + S_AXI_RDATA => S_AXI_RDATA, + S_AXI_RRESP => S_AXI_RRESP, + S_AXI_RVALID => S_AXI_RVALID, + S_AXI_RREADY => S_AXI_RREADY, + axilClk => open, + axilRst => open, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + + -- AXI Stream response shim into the DUT. + U_ShimLayerSlave : entity surf.SlaveAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "S_AXIS", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 2, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 16) + port map ( + S_AXIS_ACLK => AXIS_ACLK, + S_AXIS_ARESETN => AXIS_ARESETN, + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TSTRB => (others => '0'), + S_AXIS_TKEEP => S_AXIS_TKEEP, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TDEST => "0", + S_AXIS_TID => "0", + S_AXIS_TUSER => S_AXIS_TUSER, + S_AXIS_TREADY => S_AXIS_TREADY, + axisClk => open, + axisRst => open, + axisMaster => sAxisMaster, + axisSlave => sAxisSlave); + + -- AXI Stream request shim out to cocotb. + U_ShimLayerMaster : entity surf.MasterAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "M_AXIS", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 2, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 16) + port map ( + M_AXIS_ACLK => AXIS_ACLK, + M_AXIS_ARESETN => AXIS_ARESETN, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TSTRB => open, + M_AXIS_TKEEP => M_AXIS_TKEEP, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TDEST => open, + M_AXIS_TID => open, + M_AXIS_TUSER => M_AXIS_TUSER, + M_AXIS_TREADY => M_AXIS_TREADY, + axisClk => open, + axisRst => open, + axisMaster => mAxisMaster, + axisSlave => mAxisSlave); + + -- DUT under test. + U_DUT : entity surf.AxiLiteSrpV0 + generic map ( + TPD_G => TPD_C, + RESP_THOLD_G => 1, + SLAVE_READY_EN_G => true, + GEN_SYNC_FIFO_G => true, + FIFO_ADDR_WIDTH_G => 9, + FIFO_PAUSE_THRESH_G => 256, + AXI_STREAM_CONFIG_G => AXIS_CONFIG_C) + port map ( + mAxisClk => AXIS_ACLK, + mAxisRst => axisRst, + mAxisMaster => mAxisMaster, + mAxisSlave => mAxisSlave, + sAxisClk => AXIS_ACLK, + sAxisRst => axisRst, + sAxisMaster => sAxisMaster, + sAxisSlave => sAxisSlave, + sAxisCtrl => open, + axilClk => AXIS_ACLK, + axilRst => axisRst, + sAxilWriteMaster => axilWriteMaster, + sAxilWriteSlave => axilWriteSlave, + sAxilReadMaster => axilReadMaster, + sAxilReadSlave => axilReadSlave); + +end architecture rtl; diff --git a/protocols/srp/wrappers/SrpV0AxiLiteWrapper.vhd b/protocols/srp/wrappers/SrpV0AxiLiteWrapper.vhd new file mode 100644 index 0000000000..b6056c9839 --- /dev/null +++ b/protocols/srp/wrappers/SrpV0AxiLiteWrapper.vhd @@ -0,0 +1,207 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Cocotb-facing wrapper for SrpV0AxiLite direct testing +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; +use surf.AxiStreamPkg.all; +use surf.SsiPkg.all; + +entity SrpV0AxiLiteWrapper is + generic ( + EN_32BIT_ADDR_G : boolean := false); + port ( + AXIS_ACLK : in std_logic; + AXIS_ARESETN : in std_logic; + S_AXIS_TVALID : in std_logic; + S_AXIS_TDATA : in std_logic_vector(31 downto 0); + S_AXIS_TKEEP : in std_logic_vector(3 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TUSER : in std_logic_vector(1 downto 0); + S_AXIS_TREADY : out std_logic; + M_AXIS_TVALID : out std_logic; + M_AXIS_TDATA : out std_logic_vector(31 downto 0); + M_AXIS_TKEEP : out std_logic_vector(3 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TUSER : out std_logic_vector(1 downto 0); + M_AXIS_TREADY : in std_logic; + M_AXIL_AWADDR : out std_logic_vector(31 downto 0); + M_AXIL_AWPROT : out std_logic_vector(2 downto 0); + M_AXIL_AWVALID : out std_logic; + M_AXIL_AWREADY : in std_logic; + M_AXIL_WDATA : out std_logic_vector(31 downto 0); + M_AXIL_WSTRB : out std_logic_vector(3 downto 0); + M_AXIL_WVALID : out std_logic; + M_AXIL_WREADY : in std_logic; + M_AXIL_BRESP : in std_logic_vector(1 downto 0); + M_AXIL_BVALID : in std_logic; + M_AXIL_BREADY : out std_logic; + M_AXIL_ARADDR : out std_logic_vector(31 downto 0); + M_AXIL_ARPROT : out std_logic_vector(2 downto 0); + M_AXIL_ARVALID : out std_logic; + M_AXIL_ARREADY : in std_logic; + M_AXIL_RDATA : in std_logic_vector(31 downto 0); + M_AXIL_RRESP : in std_logic_vector(1 downto 0); + M_AXIL_RVALID : in std_logic; + M_AXIL_RREADY : out std_logic); +end entity SrpV0AxiLiteWrapper; + +architecture rtl of SrpV0AxiLiteWrapper is + + constant TPD_C : time := 10 ns / 4; + constant AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(4); + + signal axisRst : sl := '0'; + + signal axilReadMaster : AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + signal axilReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C; + signal axilWriteMaster : AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + signal axilWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C; + + signal sAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal sAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + signal mAxisMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C; + signal mAxisSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C; + +begin + + axisRst <= not AXIS_ARESETN; + + -- AXI Stream request shim into the DUT. + U_ShimLayerSlave : entity surf.SlaveAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "S_AXIS", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 2, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 4) + port map ( + S_AXIS_ACLK => AXIS_ACLK, + S_AXIS_ARESETN => AXIS_ARESETN, + S_AXIS_TVALID => S_AXIS_TVALID, + S_AXIS_TDATA => S_AXIS_TDATA, + S_AXIS_TSTRB => (others => '0'), + S_AXIS_TKEEP => S_AXIS_TKEEP, + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TDEST => "0", + S_AXIS_TID => "0", + S_AXIS_TUSER => S_AXIS_TUSER, + S_AXIS_TREADY => S_AXIS_TREADY, + axisClk => open, + axisRst => open, + axisMaster => sAxisMaster, + axisSlave => sAxisSlave); + + -- AXI Stream response shim back to cocotb. + U_ShimLayerMaster : entity surf.MasterAxiStreamIpIntegrator + generic map ( + INTERFACENAME => "M_AXIS", + HAS_TLAST => 1, + HAS_TKEEP => 1, + HAS_TSTRB => 0, + HAS_TREADY => 1, + TUSER_WIDTH => 2, + TID_WIDTH => 1, + TDEST_WIDTH => 1, + TDATA_NUM_BYTES => 4) + port map ( + M_AXIS_ACLK => AXIS_ACLK, + M_AXIS_ARESETN => AXIS_ARESETN, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TSTRB => open, + M_AXIS_TKEEP => M_AXIS_TKEEP, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TDEST => open, + M_AXIS_TID => open, + M_AXIS_TUSER => M_AXIS_TUSER, + M_AXIS_TREADY => M_AXIS_TREADY, + axisClk => open, + axisRst => open, + axisMaster => mAxisMaster, + axisSlave => mAxisSlave); + + -- AXI-Lite shim exposes the DUT's generated bus to cocotb RAM/responders. + U_ShimLayerAxil : entity surf.MasterAxiLiteIpIntegrator + generic map ( + INTERFACENAME => "M_AXIL", + EN_ERROR_RESP => true, + HAS_PROT => 1, + HAS_WSTRB => 1, + ADDR_WIDTH => 32) + port map ( + M_AXI_ACLK => AXIS_ACLK, + M_AXI_ARESETN => AXIS_ARESETN, + M_AXI_AWADDR => M_AXIL_AWADDR, + M_AXI_AWPROT => M_AXIL_AWPROT, + M_AXI_AWVALID => M_AXIL_AWVALID, + M_AXI_AWREADY => M_AXIL_AWREADY, + M_AXI_WDATA => M_AXIL_WDATA, + M_AXI_WSTRB => M_AXIL_WSTRB, + M_AXI_WVALID => M_AXIL_WVALID, + M_AXI_WREADY => M_AXIL_WREADY, + M_AXI_BRESP => M_AXIL_BRESP, + M_AXI_BVALID => M_AXIL_BVALID, + M_AXI_BREADY => M_AXIL_BREADY, + M_AXI_ARADDR => M_AXIL_ARADDR, + M_AXI_ARPROT => M_AXIL_ARPROT, + M_AXI_ARVALID => M_AXIL_ARVALID, + M_AXI_ARREADY => M_AXIL_ARREADY, + M_AXI_RDATA => M_AXIL_RDATA, + M_AXI_RRESP => M_AXIL_RRESP, + M_AXI_RVALID => M_AXIL_RVALID, + M_AXI_RREADY => M_AXIL_RREADY, + axilClk => open, + axilRst => open, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + + -- DUT under test. + U_DUT : entity surf.SrpV0AxiLite + generic map ( + TPD_G => TPD_C, + RESP_THOLD_G => 1, + SLAVE_READY_EN_G => true, + EN_32BIT_ADDR_G => EN_32BIT_ADDR_G, + GEN_SYNC_FIFO_G => true, + FIFO_ADDR_WIDTH_G => 9, + FIFO_PAUSE_THRESH_G => 256, + AXI_STREAM_CONFIG_G => AXIS_CONFIG_C) + port map ( + sAxisClk => AXIS_ACLK, + sAxisRst => axisRst, + sAxisMaster => sAxisMaster, + sAxisSlave => sAxisSlave, + sAxisCtrl => open, + mAxisClk => AXIS_ACLK, + mAxisRst => axisRst, + mAxisMaster => mAxisMaster, + mAxisSlave => mAxisSlave, + axiLiteClk => AXIS_ACLK, + axiLiteRst => axisRst, + mAxiLiteWriteMaster => axilWriteMaster, + mAxiLiteWriteSlave => axilWriteSlave, + mAxiLiteReadMaster => axilReadMaster, + mAxiLiteReadSlave => axilReadSlave); + +end architecture rtl; diff --git a/tests/protocols/srp/test_AxiLiteSrpV0.py b/tests/protocols/srp/test_AxiLiteSrpV0.py new file mode 100644 index 0000000000..d473d7807a --- /dev/null +++ b/tests/protocols/srp/test_AxiLiteSrpV0.py @@ -0,0 +1,168 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Isolate `AxiLiteSrpV0` from the SRPv0 loopback wrapper and exercise +# write/read requests plus malformed response handling. +# - Stimulus: Drive AXI-Lite transactions from cocotb, capture the generated +# 128-bit SRPv0 stream word, and inject matching or intentionally bad stream +# responses. +# - Checks: The emitted SRPv0 fields must contain the transaction count, +# address/opcode, data, and terminal zero word expected by the legacy bridge, +# while bad responses must translate into AXI-Lite `SLVERR` responses. +# - Timing: AXI-Lite requests run concurrently with stream capture/response +# coroutines so the DUT is checked through real ready/valid handshakes. + +import cocotb +import pytest +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge +from cocotbext.axi import AxiLiteBus, AxiLiteMaster, AxiResp + +from tests.axi.utils import wait_sampled_ready +from tests.common.regression_utils import run_surf_vhdl_test +from tests.protocols.srp.srp_test_utils import FlatSrpAxis + + +SRPV0_READ = 0 +SRPV0_WRITE = 1 + + +def srpv0_addr_word(opcode: int, address: int) -> int: + return ((opcode & 0x3) << 30) | ((address >> 2) & 0x3FFF_FFFF) + + +class TB: + def __init__(self, dut): + self.dut = dut + cocotb.start_soon(Clock(dut.AXIS_ACLK, 8.0, unit="ns").start()) + self.axil = AxiLiteMaster( + AxiLiteBus.from_prefix(dut, "S_AXI"), + dut.AXIS_ACLK, + dut.AXIS_ARESETN, + reset_active_level=False, + ) + self.axis = FlatSrpAxis(dut, clk=dut.AXIS_ACLK, data_bytes=16) + + async def reset(self): + # Initialize both stream directions before releasing reset so the + # bridge cannot observe unknown ready/valid inputs. + self.dut.AXIS_ARESETN.setimmediatevalue(0) + self.axis.init_source() + self.axis.init_sink() + for _ in range(12): + await RisingEdge(self.dut.AXIS_ACLK) + self.dut.AXIS_ARESETN.value = 1 + for _ in range(12): + await RisingEdge(self.dut.AXIS_ACLK) + + async def send_response(self, words: list[int], *, last: int = 1, tkeep: int = 0xFFFF, sof: int = 0x2): + # The direct wrapper uses a 16-byte stream so one SRPv0 response beat + # carries the complete four-word legacy frame. + data = 0 + for index, word in enumerate(words): + data |= (word & 0xFFFF_FFFF) << (32 * index) + + self.dut.S_AXIS_TVALID.value = 1 + self.dut.S_AXIS_TDATA.value = data + self.dut.S_AXIS_TKEEP.value = tkeep + self.dut.S_AXIS_TLAST.value = last + self.dut.S_AXIS_TUSER.value = sof + await wait_sampled_ready(self.dut.S_AXIS_TREADY, clk=self.dut.AXIS_ACLK) + self.dut.S_AXIS_TVALID.value = 0 + self.dut.S_AXIS_TLAST.value = 0 + self.dut.S_AXIS_TUSER.value = 0 + + +async def recv_request(tb: TB) -> list[int]: + response = await tb.axis.recv_response() + assert response.tkeep == [0xF, 0xF, 0xF, 0xF] + assert response.tuser[0] & 0x2 == 0x2 + return response.words + + +@cocotb.test() +async def axilite_srpv0_write_read_translation_test(dut): + tb = TB(dut) + await tb.reset() + + # A write must become one SRPv0 request word bundle and complete only after + # the matching echoed response returns. + write_address = 0x014 + write_data = 0x1234_ABCD + write_task = cocotb.start_soon(tb.axil.write(write_address, write_data.to_bytes(4, "little"))) + write_request = await recv_request(tb) + assert write_request == [ + 0, + srpv0_addr_word(SRPV0_WRITE, write_address), + write_data, + 0, + ] + await tb.send_response(write_request) + write_txn = await write_task + assert write_txn.resp == AxiResp.OKAY + + # The next transaction count is visible in the stream frame, and read data + # is taken from the third response word. + read_address = 0x028 + read_data = 0xDEAD_BEEF + read_task = cocotb.start_soon(tb.axil.read(read_address, 4)) + read_request = await recv_request(tb) + assert read_request == [ + 1, + srpv0_addr_word(SRPV0_READ, read_address), + 0, + 0, + ] + await tb.send_response([read_request[0], read_request[1], read_data, 0]) + read_txn = await read_task + assert read_txn.resp == AxiResp.OKAY + assert read_txn.data == read_data.to_bytes(4, "little") + + +@cocotb.test() +async def axilite_srpv0_bad_response_recovery_test(dut): + tb = TB(dut) + await tb.reset() + + # A response whose echoed data does not match the outstanding write must be + # rejected as an AXI-Lite error. + bad_task = cocotb.start_soon(tb.axil.write(0x030, (0xA5A5_5A5A).to_bytes(4, "little"))) + bad_request = await recv_request(tb) + await tb.send_response([bad_request[0], bad_request[1], 0xFFFF_0000, 0]) + bad_txn = await bad_task + assert bad_txn.resp == AxiResp.SLVERR + + # A non-terminal response beat forces the DUT through its bleed state. The + # trailing beat drains that bad frame, then a normal read proves recovery. + bleed_task = cocotb.start_soon(tb.axil.read(0x034, 4)) + bleed_request = await recv_request(tb) + await tb.send_response([bleed_request[0], bleed_request[1], 0x1111_2222, 0], last=0) + await tb.send_response([0, 0, 0, 0]) + bleed_txn = await bleed_task + assert bleed_txn.resp == AxiResp.SLVERR + + recovery_task = cocotb.start_soon(tb.axil.read(0x038, 4)) + recovery_request = await recv_request(tb) + await tb.send_response([recovery_request[0], recovery_request[1], 0xCAFE_BABE, 0]) + recovery_txn = await recovery_task + assert recovery_txn.resp == AxiResp.OKAY + assert recovery_txn.data == (0xCAFE_BABE).to_bytes(4, "little") + + +@pytest.mark.parametrize("parameters", [pytest.param({}, id="direct")]) +def test_AxiLiteSrpV0(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.axilitesrpv0wrapper", + parameters=parameters, + extra_env=parameters, + extra_vhdl_sources={"surf": ["protocols/srp/wrappers/AxiLiteSrpV0Wrapper.vhd"]}, + ) diff --git a/tests/protocols/srp/test_SrpV0AxiLite.py b/tests/protocols/srp/test_SrpV0AxiLite.py new file mode 100644 index 0000000000..1c12a5e450 --- /dev/null +++ b/tests/protocols/srp/test_SrpV0AxiLite.py @@ -0,0 +1,220 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +# Test methodology: +# - Sweep: Isolate `SrpV0AxiLite` from the loopback wrapper, covering +# multi-word write/read frames, malformed request frames, and 32-bit address +# expansion. +# - Stimulus: Drive legacy four-word SRPv0 request frames directly on AXI +# Stream and attach a cocotb AXI-Lite RAM to the generated master bus. +# - Checks: Response frames must echo the request header/data, return readback +# payload words, set bit 16 on malformed frames, and issue AXI-Lite accesses +# at the expected decoded addresses. +# - Timing: The flat stream helper holds every beat until sampled `TREADY`, and +# response collection is bounded so lost terminal status words fail quickly. + +import os + +import cocotb +import pytest +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge +from cocotbext.axi import AxiLiteBus, AxiLiteRam + +from tests.common.regression_utils import hdl_parameters_from, run_surf_vhdl_test +from tests.protocols.srp.srp_test_utils import FlatSrpAxis + + +SRPV0_READ = 0 +SRPV0_WRITE = 1 +SRPV0_UNSUPPORTED = 2 +SRPV0_STATUS_FAIL = 1 << 16 + + +def srpv0_addr_word(opcode: int, address: int) -> int: + high = (address >> 26) & 0x3F + low = (address >> 2) & 0x00FF_FFFF + return ((opcode & 0x3) << 30) | (high << 24) | low + + +class TB: + def __init__(self, dut, *, use_ram: bool = True): + self.dut = dut + cocotb.start_soon(Clock(dut.AXIS_ACLK, 8.0, unit="ns").start()) + self.axis = FlatSrpAxis(dut, clk=dut.AXIS_ACLK, data_bytes=4) + self.ram = None + if use_ram: + self.ram = AxiLiteRam( + AxiLiteBus.from_prefix(dut, "M_AXIL"), + dut.AXIS_ACLK, + dut.AXIS_ARESETN, + reset_active_level=False, + size=2**20, + ) + + async def reset(self): + # Initialize stream ports while reset is asserted. The AXI-Lite RAM + # model follows the same active-low reset as the wrapper. + self.dut.AXIS_ARESETN.setimmediatevalue(0) + self.axis.init_source() + self.axis.init_sink() + if self.ram is None: + self.dut.M_AXIL_AWREADY.setimmediatevalue(0) + self.dut.M_AXIL_WREADY.setimmediatevalue(0) + self.dut.M_AXIL_BRESP.setimmediatevalue(0) + self.dut.M_AXIL_BVALID.setimmediatevalue(0) + self.dut.M_AXIL_ARREADY.setimmediatevalue(0) + self.dut.M_AXIL_RDATA.setimmediatevalue(0) + self.dut.M_AXIL_RRESP.setimmediatevalue(0) + self.dut.M_AXIL_RVALID.setimmediatevalue(0) + for _ in range(12): + await RisingEdge(self.dut.AXIS_ACLK) + self.dut.AXIS_ARESETN.value = 1 + for _ in range(12): + await RisingEdge(self.dut.AXIS_ACLK) + + async def accept_one_write(self) -> dict[str, int]: + # This minimal responder is used only for the high-address decode case, + # where a dense cocotb RAM would waste memory just to cover one address. + record = {} + self.dut.M_AXIL_AWREADY.value = 1 + self.dut.M_AXIL_WREADY.value = 1 + + while "address" not in record or "data" not in record: + await RisingEdge(self.dut.AXIS_ACLK) + if int(self.dut.M_AXIL_AWVALID.value) and int(self.dut.M_AXIL_AWREADY.value): + record["address"] = int(self.dut.M_AXIL_AWADDR.value) + if int(self.dut.M_AXIL_WVALID.value) and int(self.dut.M_AXIL_WREADY.value): + record["data"] = int(self.dut.M_AXIL_WDATA.value) + record["strobe"] = int(self.dut.M_AXIL_WSTRB.value) + + self.dut.M_AXIL_AWREADY.value = 0 + self.dut.M_AXIL_WREADY.value = 0 + self.dut.M_AXIL_BRESP.value = 0 + self.dut.M_AXIL_BVALID.value = 1 + while True: + await RisingEdge(self.dut.AXIS_ACLK) + if int(self.dut.M_AXIL_BREADY.value): + break + self.dut.M_AXIL_BVALID.value = 0 + return record + + +async def send_request(tb: TB, words: list[int]) -> list[int]: + await tb.axis.send_words(words) + return (await tb.axis.recv_response()).words + + +@cocotb.test() +async def srpv0_axilite_write_read_frames_test(dut): + tb = TB(dut) + await tb.reset() + + # A write frame carries an echo word, an address/opcode word, one or more + # data words, and a terminal padding word. The response echoes the useful + # words and appends a zero status. + address = 0x100 + payload = [0x1122_3344, 0x5566_7788] + write_words = [0x0102_0304, srpv0_addr_word(SRPV0_WRITE, address), *payload, 0] + assert await send_request(tb, write_words) == [ + write_words[0], + write_words[1], + payload[0], + payload[1], + 0, + ] + + # The generated AXI-Lite writes must land in consecutive 32-bit locations. + assert tb.ram is not None + assert tb.ram.read(address, 8) == b"\x44\x33\x22\x11\x88\x77\x66\x55" + + # A read frame returns the requested number of zero-based data words before + # the final status word. + read_words = [0xA0B0_C0D0, srpv0_addr_word(SRPV0_READ, address), 1, 0] + assert await send_request(tb, read_words) == [ + read_words[0], + read_words[1], + payload[0], + payload[1], + 0, + ] + + +@cocotb.test() +async def srpv0_axilite_error_frames_test(dut): + tb = TB(dut) + await tb.reset() + + # Ending the frame on the address word is a malformed request and must set + # the legacy fail bit in the returned status word. + short_frame = [0x1111_2222, srpv0_addr_word(SRPV0_READ, 0x120)] + short_response = await send_request(tb, short_frame) + assert short_response == [short_frame[0], short_frame[1], SRPV0_STATUS_FAIL] + + # Unsupported opcodes dump the rest of the request and then report the same + # status failure without issuing a read or write. + unsupported_frame = [ + 0x3333_4444, + srpv0_addr_word(SRPV0_UNSUPPORTED, 0x124), + 0xAAAA_5555, + 0, + ] + unsupported_response = await send_request(tb, unsupported_frame) + assert unsupported_response == [ + unsupported_frame[0], + unsupported_frame[1], + SRPV0_STATUS_FAIL, + ] + + +@cocotb.test() +async def srpv0_axilite_32bit_address_decode_test(dut): + if os.environ.get("EN_32BIT_ADDR_G", "false").lower() != "true": + return + + tb = TB(dut, use_ram=False) + await tb.reset() + + # With EN_32BIT_ADDR_G enabled, bits 29:24 of the address/opcode word feed + # address bits 31:26. A custom responder avoids allocating a sparse RAM for + # this high address while still returning an OK AXI-Lite write response. + address = 0x0800_0120 + payload = [0xFEED_FACE] + write_words = [0x5555_AAAA, srpv0_addr_word(SRPV0_WRITE, address), payload[0], 0] + write_task = cocotb.start_soon(tb.accept_one_write()) + assert await send_request(tb, write_words) == [ + write_words[0], + write_words[1], + payload[0], + 0, + ] + write_record = await write_task + assert write_record == { + "address": address, + "data": payload[0], + "strobe": 0xF, + } + + +PARAMETER_SWEEP = [ + pytest.param({}, id="legacy_26bit_addr"), + pytest.param({"EN_32BIT_ADDR_G": True}, id="extended_32bit_addr"), +] + + +@pytest.mark.parametrize("parameters", PARAMETER_SWEEP) +def test_SrpV0AxiLite(parameters): + run_surf_vhdl_test( + test_file=__file__, + toplevel="surf.srpv0axilitewrapper", + parameters=hdl_parameters_from(parameters), + extra_env=parameters, + extra_vhdl_sources={"surf": ["protocols/srp/wrappers/SrpV0AxiLiteWrapper.vhd"]}, + ) From be07f88c22a888235ba1a15d00240072c4d6b605 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Sat, 2 May 2026 23:03:38 -0700 Subject: [PATCH 84/92] Add more srp tests. --- docs/_meta/rtl_regression_handoff.md | 4 +- docs/_meta/rtl_regression_progress.md | 16 +- protocols/srp/wrappers/SrpV3CoreWrapper.vhd | 8 +- tests/protocols/srp/srp_test_utils.py | 1 + tests/protocols/srp/test_SrpV0AxiLite.py | 72 +++++- tests/protocols/srp/test_SrpV3Axi.py | 242 ++++--------------- tests/protocols/srp/test_SrpV3AxiLite.py | 98 ++++++-- tests/protocols/srp/test_SrpV3Core.py | 243 +++++++++++++++++--- 8 files changed, 419 insertions(+), 265 deletions(-) diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md index 5d6cd48444..de54863df3 100644 --- a/docs/_meta/rtl_regression_handoff.md +++ b/docs/_meta/rtl_regression_handoff.md @@ -27,7 +27,7 @@ - The remaining CoaXPress pure-VHDL gap is now `CoaXPressConfig`. The current CoaXPress receive benches now include a dual-lane `CoaXPressRxHsFsm` step/alignment case, a dual-lane `CoaXPressRx` lane-rotation case, and event packet validation through payload size, payload words, CRC, and `EOP` before `eventAck`. The receive side is still intentionally mixed-depth: event payload is validated for parser/CRC behavior but is not exported through an application-facing payload interface, and the multi-lane assembly checks still stop short of exhaustive per-lane stress coverage. - The latest CXPoF bridge guardrail work is now reflected at both leaf and top level: `CoaXPressOverFiberBridgeRx` covers HKP-to-payload mixing and malformed lane-placement checks for `/S/`, `/Q/`, `/T/`, and `/E/`, while `CoaXPressOverFiberBridge` covers 64-bit RX gearbox traversal for `/E/` abort/recovery, HKP-to-payload transition, and lane-0 `/Q/` no-output/recovery. Treat these as current-RTL regression guardrails rather than complete normative `/Q/`, `/E/`, or housekeeping protocol coverage. - `tests/protocols/coaxpress/test_CoaXPressConfig.py` is intentionally checked in as a skipped investigation bench. When driven through the real SRP ingress, the current `CoaXPressConfig` / `SrpV3AxiLite` integration does not complete the request path within the bench timeout, so treat that as a likely RTL or integration defect to debug before re-enabling active assertions there. - - `tests/protocols/srp/test_SrpV3Axi.py` is now the active SRPv3 AXI regression, not just the old legacy-style posted-write/readback smoke. It validates non-posted write echo/readback, posted-write no-response behavior, NULL responses, response backpressure, TDEST propagation, full-word `TKEEP`, and footer bits for version mismatch, malformed write framing, invalid alignment, invalid request size, downstream write address error, and downstream read address error. `tests/protocols/srp/test_SrpV3Core.py` now covers direct reset/idle smoke for the default `SrpV3CoreWrapper` mode plus direct 32-bit malformed-header and immediate-read-error fault injection through `CORE_DATA_BYTES_G => 4`. That narrow mode exposed and now covers two real `SrpV3Core` bugs: the response-header counter was not reset when emitting an error response from a truncated request header, and `READ_S` could miss an immediate downstream read error before any payload beat arrived. SRPv0 now has direct bridge-half coverage plus loopback coverage: `tests/protocols/srp/test_AxiLiteSrpV0.py` checks request packing and bad-response handling through `AxiLiteSrpV0Wrapper`, `tests/protocols/srp/test_SrpV0AxiLite.py` checks legacy frame parsing/status/address expansion through `SrpV0AxiLiteWrapper`, and `tests/protocols/srp/test_SrpV0Loopback.py` still covers `AxiLiteSrpV0` and `SrpV0AxiLite` together through the checked-in stream loopback wrapper. `tests/protocols/srp/test_SrpV3AxiLite.py` now carries active reset/idle smoke for direct, full, and legacy-wide `DATA_BYTES_G => 32` modes, active narrow probes for the direct and full wrappers, active directed regressions for the direct and full wrappers, and one active legacy-wide directed regression. The duplicate wide-wrapper probe/direct cases were removed instead of kept as skipped opt-in coverage, and the old wide/narrow-only SRP wrapper files were folded into generics, leaving the default `tests/protocols/srp` run skip-free. The direct narrow `SrpV3AxiLite` issue turned out to be a bench artifact, not an RTL defect: `tests/protocols/srp/srp_test_utils.py` now holds each source beat until a sampled clock edge confirms `TREADY`, which fixes the false failure on the original `SsiFrameLimiter` bypass configuration (`SLAVE_FIFO_G => false`). The focused `tests/protocols/ssi/test_SsiFrameLimiter.py` isolation regressions remain green in both limiter modes. + - `tests/protocols/srp/test_SrpV3Axi.py` is now the active SRPv3 AXI regression, not just the old legacy-style posted-write/readback smoke, and it reuses the shared SRPv3 helper/model layer from `tests/protocols/srp/srp_test_utils.py`. It validates non-posted write echo/readback, posted-write no-response behavior, NULL responses, response backpressure, TDEST propagation, full-word `TKEEP`, and footer bits for version mismatch, malformed write framing, invalid alignment, invalid request size, downstream write address error, and downstream read address error. `tests/protocols/srp/test_SrpV3Core.py` now covers direct reset/idle smoke for the default `SrpV3CoreWrapper` mode plus direct 32-bit malformed-header, immediate-read-error, disabled-read/write, missing-SOF blowoff, short-write framing, and early/late read-data TLAST EOFE behavior through `CORE_DATA_BYTES_G => 4`. That narrow mode exposed and now covers two real `SrpV3Core` bugs: the response-header counter was not reset when emitting an error response from a truncated request header, and `READ_S` could miss an immediate downstream read error before any payload beat arrived. SRPv0 now has direct bridge-half coverage plus loopback coverage: `tests/protocols/srp/test_AxiLiteSrpV0.py` checks request packing and bad-response handling through `AxiLiteSrpV0Wrapper`, `tests/protocols/srp/test_SrpV0AxiLite.py` checks legacy frame parsing/status/address expansion plus downstream AXI-Lite read/write error propagation through `SrpV0AxiLiteWrapper`, and `tests/protocols/srp/test_SrpV0Loopback.py` still covers `AxiLiteSrpV0` and `SrpV0AxiLite` together through the checked-in stream loopback wrapper. `tests/protocols/srp/test_SrpV3AxiLite.py` now carries active reset/idle smoke for direct, full, and legacy-wide `DATA_BYTES_G => 32` modes, active narrow probes for the direct and full wrappers, active directed regressions for the direct and full wrappers, one active legacy-wide directed regression, and direct-wrapper `ignoreMemResp` coverage for an AXI-Lite `SLVERR` read. The duplicate wide-wrapper probe/direct cases were removed instead of kept as skipped opt-in coverage, and the old wide/narrow-only SRP wrapper files were folded into generics, leaving the default `tests/protocols/srp` run skip-free. The direct narrow `SrpV3AxiLite` issue turned out to be a bench artifact, not an RTL defect: `tests/protocols/srp/srp_test_utils.py` now holds each source beat until a sampled clock edge confirms `TREADY`, which fixes the false failure on the original `SsiFrameLimiter` bypass configuration (`SLAVE_FIFO_G => false`). The focused `tests/protocols/ssi/test_SsiFrameLimiter.py` isolation regressions remain green in both limiter modes. - The broader flat-stream helper cleanup is now partially checked in beyond SRP. `tests/axi/utils.py` owns the shared `wait_sampled_ready()` primitive, and the flattened helper layers in `tests/protocols/ssi/ssi_test_utils.py`, `tests/protocols/srp/srp_test_utils.py`, `tests/protocols/pgp/pgp4/pgp4_test_utils.py`, `tests/protocols/coaxpress/coaxpress_test_utils.py`, `tests/ethernet/EthMacCore/ethmac_test_utils.py`, and `tests/ethernet/RawEthFramer/raw_eth_test_utils.py` now use it where appropriate instead of open-coded sampled-ready loops. Direct one-off benches that were good fits for the same cleanup now include `tests/protocols/srp/test_SrpV3Axi.py`, `tests/protocols/ssi/test_SsiResizeFifoEofe.py`, `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, `tests/protocols/coaxpress/test_CoaXPressTx.py`, `tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py`, and `tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py`. - One subtle point from that cleanup is important for future edits: `wait_sampled_ready()` returns after the accepting clock edge has already occurred. A source must therefore advance or deassert immediately after the helper returns; leaving an extra post-handshake clock in place can create duplicate transfers or malformed streams. The current checked-in cleanup already corrected the false regressions that came from that mistake. - The current validation subset for the flat-driver cleanup is `174 passed` across `tests/protocols/srp/test_SrpV3Axi.py`, `tests/protocols/ssi/test_SsiResizeFifoEofe.py`, the active PGP4 flat-wrapper subset, `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, `tests/protocols/coaxpress/test_CoaXPressTx.py`, `tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py`, and `tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py`. @@ -179,7 +179,7 @@ A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instan ## Immediate Next Task If the user keeps the focus on stream-helper cleanup rather than resuming a new subsystem, the next practical step is the remaining PGP interleaved source/capture helpers: decide whether `tests/protocols/pgp/pgp4/test_Pgp4Rx.py` and the protocol-word collector in `tests/protocols/pgp/pgp4/pgp4_test_utils.py` should stay intentionally manual or be folded into a richer shared helper that can hold a source beat through acceptance while concurrently capturing narrow output pulses. -If the user keeps the focus on `protocols/srp`, the next practical step inside that subsystem is deeper isolated SRPv3 coverage rather than SRPv0 rescue work: consider whether `tests/protocols/srp/test_SrpV3Core.py` should absorb more of the protocol-error matrix that is currently only covered transitively through `SrpV3Axi` and `SrpV3AxiLite`. The latest focused SRP validation command is `./.venv/bin/python -m pytest -n 0 -q tests/protocols/srp`, and it passed locally with `19 passed`. +If the user keeps the focus on `protocols/srp`, the main review findings and high-value coverage additions are complete. The optional remaining SRP follow-up is deeper timeout or posted-write disabled-op permutations if a future change touches those RTL branches. The latest focused SRP validation command is `./.venv/bin/python -m pytest -n 0 -q tests/protocols/srp`, and it passed locally with `23 passed`. If the user switches back to `protocols/coaxpress`, the next practical step is either: 1. debug and re-enable the skipped `CoaXPressConfig` investigation bench, starting with the SRP-driven request path that currently fails to complete through the real `CoaXPressConfig` / `SrpV3AxiLite` integration, or diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md index 23c76e094f..44f3f043b8 100644 --- a/docs/_meta/rtl_regression_progress.md +++ b/docs/_meta/rtl_regression_progress.md @@ -3,7 +3,7 @@ ## Summary - Current phase: Phase-1 implementation active - Current subsystem: manual user-directed rollout tracking -- Current focus module: user-directed `protocols/srp` regression cleanup after merging the SRP branch onto the current `verification-2` frontier, now including direct SRPv0 bridge-half coverage plus the existing loopback check. +- Current focus module: user-directed `protocols/srp` regression cleanup after merging the SRP branch onto the current `verification-2` frontier, now including direct SRPv0 bridge-half coverage, direct SRPv3 core edge coverage, and the existing loopback check. - Last updated: 2026-05-03 ## Current Frontier Snapshot @@ -33,9 +33,9 @@ - SRP RTL target matrix: - Covered now under the current GHDL-only flow: `SrpV3Axi` through the checked-in `protocols/srp/wrappers/SrpV3AxiWrapper.vhd` wrapper and `tests/protocols/srp/test_SrpV3Axi.py`. - The current SRPv3 AXI bench now validates non-posted write echo/readback, posted-write no-response behavior followed by readback, NULL header/footer behavior, response backpressure hold, TDEST propagation, full-word `TKEEP`, and footer bits for version mismatch, malformed write framing, invalid alignment, invalid request size, and downstream address error. - - `SrpV3Core` now has a direct checked-in wrapper with reset/idle smoke coverage plus a narrow 32-bit fault-injection mode for malformed-header and immediate-read-error behavior. `tests/protocols/srp/test_SrpV3Core.py` now uses `SrpV3CoreWrapper` in both default mode and `CORE_DATA_BYTES_G => 4` mode instead of carrying a separate narrow test file. The narrow mode exposed and now covers two core-side bugs: the response-header counter was not reset when emitting an error response from a truncated request header, and `READ_S` could miss an immediate downstream read error before any payload beat arrived. - - `AxiLiteSrpV0` and `SrpV0AxiLite` are now covered directly and together. `tests/protocols/srp/test_AxiLiteSrpV0.py` uses `protocols/srp/wrappers/AxiLiteSrpV0Wrapper.vhd` to validate AXI-Lite-to-SRPv0 request field packing, read data return, bad-response `SLVERR`, and bleed/recovery behavior. `tests/protocols/srp/test_SrpV0AxiLite.py` uses `protocols/srp/wrappers/SrpV0AxiLiteWrapper.vhd` to validate multi-word write/read frames, malformed/unsupported request status failures, and `EN_32BIT_ADDR_G` address expansion. `tests/protocols/srp/test_SrpV0Loopback.py` still covers both bridge halves together through the checked-in stream loopback wrapper and attached RAM. - - SRPv3 AXI-Lite status: `tests/protocols/srp/test_SrpV3AxiLite.py` now has active reset/idle coverage for the direct, full, and legacy-wide `DATA_BYTES_G => 32` modes, active narrow probes (`short_frame`, `four_beat_header`, and `single_read`) for both the direct and full wrappers, active directed regressions for the direct and full wrappers, and one active legacy-wide directed regression. The earlier direct-wrapper failure was not an `SrpV3AxiLite` ingress RTL defect after all: the real issue was in `tests/protocols/srp/srp_test_utils.py`, where `FlatSrpAxis.send_packed_words()` treated combinational `TREADY` as immediate acceptance instead of holding each beat until a sampled clock edge confirmed the handshake. With that helper fixed and the two `SrpV3Core` fixes in place, the direct and full `SrpV3AxiLite` paths now pass on the original `SsiFrameLimiter` bypass configuration (`SLAVE_FIFO_G => false`), and the focused standalone `tests/protocols/ssi/test_SsiFrameLimiter.py` regressions remain green in both limiter modes. The duplicate wide-wrapper probe/direct cases were removed rather than kept as skipped opt-in coverage, and the old wide/narrow-only SRP wrapper files were folded into generics, so the default `tests/protocols/srp` run is now skip-free. + - `SrpV3Core` now has a direct checked-in wrapper with reset/idle smoke coverage plus a narrow 32-bit fault-injection mode for malformed-header, immediate-read-error, disabled-read/write, missing-SOF blowoff, short-write framing, and early/late read-data TLAST EOFE behavior. `tests/protocols/srp/test_SrpV3Core.py` now uses `SrpV3CoreWrapper` in both default mode and `CORE_DATA_BYTES_G => 4` mode instead of carrying a separate narrow test file. The narrow mode exposed and now covers two core-side bugs: the response-header counter was not reset when emitting an error response from a truncated request header, and `READ_S` could miss an immediate downstream read error before any payload beat arrived. + - `AxiLiteSrpV0` and `SrpV0AxiLite` are now covered directly and together. `tests/protocols/srp/test_AxiLiteSrpV0.py` uses `protocols/srp/wrappers/AxiLiteSrpV0Wrapper.vhd` to validate AXI-Lite-to-SRPv0 request field packing, read data return, bad-response `SLVERR`, and bleed/recovery behavior. `tests/protocols/srp/test_SrpV0AxiLite.py` uses `protocols/srp/wrappers/SrpV0AxiLiteWrapper.vhd` to validate multi-word write/read frames, malformed/unsupported request status failures, `EN_32BIT_ADDR_G` address expansion, and downstream AXI-Lite read/write error propagation into the legacy fail status. `tests/protocols/srp/test_SrpV0Loopback.py` still covers both bridge halves together through the checked-in stream loopback wrapper and attached RAM. + - SRPv3 AXI-Lite status: `tests/protocols/srp/test_SrpV3AxiLite.py` now has active reset/idle coverage for the direct, full, and legacy-wide `DATA_BYTES_G => 32` modes, active narrow probes (`short_frame`, `four_beat_header`, and `single_read`) for both the direct and full wrappers, active directed regressions for the direct and full wrappers, one active legacy-wide directed regression, and direct-wrapper `ignoreMemResp` coverage for an AXI-Lite `SLVERR` read. The earlier direct-wrapper failure was not an `SrpV3AxiLite` ingress RTL defect after all: the real issue was in `tests/protocols/srp/srp_test_utils.py`, where `FlatSrpAxis.send_packed_words()` treated combinational `TREADY` as immediate acceptance instead of holding each beat until a sampled clock edge confirmed the handshake. With that helper fixed and the two `SrpV3Core` fixes in place, the direct and full `SrpV3AxiLite` paths now pass on the original `SsiFrameLimiter` bypass configuration (`SLAVE_FIFO_G => false`), and the focused standalone `tests/protocols/ssi/test_SsiFrameLimiter.py` regressions remain green in both limiter modes. The duplicate wide-wrapper probe/direct cases were removed rather than kept as skipped opt-in coverage, and the old wide/narrow-only SRP wrapper files were folded into generics, so the default `tests/protocols/srp` run is now skip-free. - Flat AXI/SSI helper cleanup status: - `tests/axi/utils.py` now owns the shared `wait_sampled_ready()` primitive for flattened ready/valid sources that cannot use `cocotbext.axi.AxiStreamSource` directly. - The current flat-driver users are `tests/protocols/ssi/ssi_test_utils.py`, `tests/protocols/srp/srp_test_utils.py`, `tests/protocols/pgp/pgp4/pgp4_test_utils.py`, `tests/protocols/coaxpress/coaxpress_test_utils.py`, `tests/ethernet/EthMacCore/ethmac_test_utils.py`, and `tests/ethernet/RawEthFramer/raw_eth_test_utils.py`, plus direct one-off benches in `tests/protocols/srp/test_SrpV3Axi.py`, `tests/protocols/ssi/test_SsiResizeFifoEofe.py`, `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, `tests/protocols/coaxpress/test_CoaXPressTx.py`, `tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py`, and `tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py`. @@ -162,15 +162,15 @@ - The new package-surface coverage exposed a real `Code12b14bPkg` invalid-K disparity bug; `protocols/line-codes/rtl/Code12b14bPkg.vhd` now leaves `dispOut` unchanged on illegal K requests instead of tripping a GHDL bound-check failure. ## Current In-Progress Item -- Finish reviewing the `protocols/srp` work after adding the direct SRPv0 bridge-half coverage. The docs keep the newer CoaXPress frontier from `verification-2` while adding the SRP regression matrix, `SrpV3Core` RTL fixes, SRPv0 direct/loopback coverage, and shared sampled-ready helper cleanup from `srp-tests`. +- The user-requested `protocols/srp` review fixes are complete: `test_SrpV3Axi.py` now reuses the shared SRPv3 helper/model layer, `test_SrpV3Core.py` uses decorator-based cocotb test selection, the stray SRPv3 AXI-Lite debug logging is removed, and the high-value SRP coverage additions are checked in locally. - Keep the CoaXPress suite as an already validated current branch slice. The focused CoaXPress validation command is `./.venv/bin/python -m pytest -n auto --dist=worksteal -q tests/protocols/coaxpress`, and the latest pre-merge run passed with `17 passed, 1 skipped`. - Treat the skipped `CoaXPressConfig` bench and the opt-in `CoaXPressCore` overflow/FSM-error known-issue bench as the main open protocol cleanup items after the SRP duplicate wide-wrapper skips were removed. - Preserve the recent `pgp4` lesson for later PGP work: when the simulation wrapper only exposes stable lock/config surfaces, write the bench around those explicit contracts instead of claiming recovered payload coverage. -- Latest focused SRP validation: `./.venv/bin/python -m pytest -n 0 -q tests/protocols/srp` passed locally with `19 passed`. +- Latest focused SRP validation: `./.venv/bin/python -m pytest -n 0 -q tests/protocols/srp` passed locally with `23 passed`. ## Next 3 Concrete Tasks -- Finish the user-requested review of the uncommitted `protocols/srp` work; staging and committing remain user-controlled. -- Consider whether `tests/protocols/srp/test_SrpV3Core.py` should absorb more of the protocol-error matrix that is currently only covered transitively through `SrpV3Axi` and `SrpV3AxiLite`. +- Review any newly requested SRP changes from the user; staging and committing remain user-controlled. +- Optional SRP follow-up is now lower priority: add deeper timeout/posted-write disabled-op permutations only if a future change touches those RTL branches. - If staying on CoaXPress immediately after the merge, debug the skipped `CoaXPressConfig` / `SrpV3AxiLite` request path before adding broader optional coverage. ## Blockers And Risks diff --git a/protocols/srp/wrappers/SrpV3CoreWrapper.vhd b/protocols/srp/wrappers/SrpV3CoreWrapper.vhd index d530f162e0..fa70fc65aa 100644 --- a/protocols/srp/wrappers/SrpV3CoreWrapper.vhd +++ b/protocols/srp/wrappers/SrpV3CoreWrapper.vhd @@ -23,7 +23,9 @@ use surf.SrpV3Pkg.all; entity SrpV3CoreWrapper is generic ( - CORE_DATA_BYTES_G : positive range 4 to 64 := 8); + CORE_DATA_BYTES_G : positive range 4 to 64 := 8; + WRITE_EN_G : boolean := true; + READ_EN_G : boolean := true); port ( AXIS_ACLK : in std_logic; AXIS_ARESETN : in std_logic; @@ -292,7 +294,9 @@ begin TPD_G => TPD_C, SLAVE_READY_EN_G => true, GEN_SYNC_FIFO_G => true, - AXI_STREAM_CONFIG_G => CORE_CONFIG_C) + AXI_STREAM_CONFIG_G => CORE_CONFIG_C, + WRITE_EN_G => WRITE_EN_G, + READ_EN_G => READ_EN_G) port map ( sAxisClk => AXIS_ACLK, sAxisRst => axisRst, diff --git a/tests/protocols/srp/srp_test_utils.py b/tests/protocols/srp/srp_test_utils.py index c4da932a7d..5fd3384054 100644 --- a/tests/protocols/srp/srp_test_utils.py +++ b/tests/protocols/srp/srp_test_utils.py @@ -24,6 +24,7 @@ SRP_NULL = 0x3 FOOTER_FRAME_ERROR = 1 << 10 +FOOTER_EOFE = 1 << 9 FOOTER_VERSION_MISMATCH = 1 << 11 FOOTER_REQUEST_ERROR = 1 << 12 FOOTER_ADDRESS_ERROR = 1 << 7 diff --git a/tests/protocols/srp/test_SrpV0AxiLite.py b/tests/protocols/srp/test_SrpV0AxiLite.py index 1c12a5e450..7bfab9b071 100644 --- a/tests/protocols/srp/test_SrpV0AxiLite.py +++ b/tests/protocols/srp/test_SrpV0AxiLite.py @@ -26,7 +26,7 @@ import pytest from cocotb.clock import Clock from cocotb.triggers import RisingEdge -from cocotbext.axi import AxiLiteBus, AxiLiteRam +from cocotbext.axi import AxiLiteBus, AxiLiteRam, AxiResp from tests.common.regression_utils import hdl_parameters_from, run_surf_vhdl_test from tests.protocols.srp.srp_test_utils import FlatSrpAxis @@ -80,7 +80,7 @@ async def reset(self): for _ in range(12): await RisingEdge(self.dut.AXIS_ACLK) - async def accept_one_write(self) -> dict[str, int]: + async def accept_one_write(self, *, resp: AxiResp = AxiResp.OKAY) -> dict[str, int]: # This minimal responder is used only for the high-address decode case, # where a dense cocotb RAM would waste memory just to cover one address. record = {} @@ -97,13 +97,34 @@ async def accept_one_write(self) -> dict[str, int]: self.dut.M_AXIL_AWREADY.value = 0 self.dut.M_AXIL_WREADY.value = 0 - self.dut.M_AXIL_BRESP.value = 0 + self.dut.M_AXIL_BRESP.value = int(resp) self.dut.M_AXIL_BVALID.value = 1 while True: await RisingEdge(self.dut.AXIS_ACLK) if int(self.dut.M_AXIL_BREADY.value): break self.dut.M_AXIL_BVALID.value = 0 + self.dut.M_AXIL_BRESP.value = 0 + return record + + async def accept_one_read(self, *, data: int, resp: AxiResp = AxiResp.OKAY) -> dict[str, int]: + record = {} + self.dut.M_AXIL_ARREADY.value = 1 + while "address" not in record: + await RisingEdge(self.dut.AXIS_ACLK) + if int(self.dut.M_AXIL_ARVALID.value) and int(self.dut.M_AXIL_ARREADY.value): + record["address"] = int(self.dut.M_AXIL_ARADDR.value) + + self.dut.M_AXIL_ARREADY.value = 0 + self.dut.M_AXIL_RDATA.value = data + self.dut.M_AXIL_RRESP.value = int(resp) + self.dut.M_AXIL_RVALID.value = 1 + while True: + await RisingEdge(self.dut.AXIS_ACLK) + if int(self.dut.M_AXIL_RREADY.value): + break + self.dut.M_AXIL_RVALID.value = 0 + self.dut.M_AXIL_RRESP.value = 0 return record @@ -174,6 +195,51 @@ async def srpv0_axilite_error_frames_test(dut): ] +@cocotb.test() +async def srpv0_axilite_downstream_error_status_test(dut): + tb = TB(dut, use_ram=False) + await tb.reset() + + # Downstream AXI-Lite write errors must preserve the echoed write payload + # and set the legacy fail bit in the final status word. + write_address = 0x180 + write_payload = 0x0BAD_F00D + write_frame = [ + 0x1111_AAAA, + srpv0_addr_word(SRPV0_WRITE, write_address), + write_payload, + 0, + ] + write_task = cocotb.start_soon(tb.accept_one_write(resp=AxiResp.SLVERR)) + assert await send_request(tb, write_frame) == [ + write_frame[0], + write_frame[1], + write_payload, + SRPV0_STATUS_FAIL, + ] + assert await write_task == { + "address": write_address, + "data": write_payload, + "strobe": 0xF, + } + + # Read errors still return the sampled read-data word followed by the fail + # status so software can distinguish bus failure from an absent response. + read_address = 0x184 + read_data = 0xFFFF_0001 + read_frame = [0x2222_BBBB, srpv0_addr_word(SRPV0_READ, read_address), 0, 0] + read_task = cocotb.start_soon( + tb.accept_one_read(data=read_data, resp=AxiResp.SLVERR), + ) + assert await send_request(tb, read_frame) == [ + read_frame[0], + read_frame[1], + read_data, + SRPV0_STATUS_FAIL, + ] + assert await read_task == {"address": read_address} + + @cocotb.test() async def srpv0_axilite_32bit_address_decode_test(dut): if os.environ.get("EN_32BIT_ADDR_G", "false").lower() != "true": diff --git a/tests/protocols/srp/test_SrpV3Axi.py b/tests/protocols/srp/test_SrpV3Axi.py index 1ec661d446..812e498c91 100644 --- a/tests/protocols/srp/test_SrpV3Axi.py +++ b/tests/protocols/srp/test_SrpV3Axi.py @@ -22,89 +22,40 @@ # under output backpressure before release, and every expected or forbidden # response is bounded by an explicit timeout. -from dataclasses import dataclass - import cocotb import pytest from cocotb.clock import Clock from cocotb.triggers import RisingEdge, with_timeout -from tests.axi.utils import wait_sampled_ready from tests.common.regression_utils import run_surf_vhdl_test - - -SRP_VERSION = 0x03 -SRP_READ = 0x0 -SRP_WRITE = 0x1 -SRP_POSTED_WRITE = 0x2 -SRP_NULL = 0x3 - -FOOTER_FRAME_ERROR = 1 << 10 -FOOTER_VERSION_MISMATCH = 1 << 11 -FOOTER_REQUEST_ERROR = 1 << 12 -FOOTER_ADDRESS_ERROR = 1 << 7 - - -@dataclass(frozen=True) -class SrpRequest: - opcode: int - tid: int - address: int - byte_count: int - version: int = SRP_VERSION - timeout: int = 0 - prot: int = 0 - spare: int = 0 - - @property - def req_size(self) -> int: - return self.byte_count - 1 - - @property - def response_header(self) -> list[int]: - # The response reports the local SRPv3 version while echoing the rest - # of the request metadata that software uses to match transactions. - return request_header( - opcode=self.opcode, - tid=self.tid, - address=self.address, - req_size=self.req_size, - version=SRP_VERSION, - timeout=self.timeout, - prot=self.prot, - spare=self.spare, - ) - - -@dataclass(frozen=True) -class SrpResponse: - words: list[int] - tdest: list[int] - tuser: list[int] - tkeep: list[int] - - @property - def footer(self) -> int: - return self.words[-1] +from tests.protocols.srp.srp_test_utils import ( + FOOTER_ADDRESS_ERROR, + FOOTER_FRAME_ERROR, + FOOTER_REQUEST_ERROR, + FOOTER_VERSION_MISMATCH, + FlatSrpAxis, + SRP_NULL, + SRP_POSTED_WRITE, + SRP_READ, + SRP_WRITE, + SrpV3Request, + assert_srpv3_response, + srpv3_frame, +) class TB: def __init__(self, dut): self.dut = dut cocotb.start_soon(Clock(dut.AXIS_ACLK, 10.0, unit="ns").start()) + self.axis = FlatSrpAxis(dut, clk=dut.AXIS_ACLK) async def reset(self): # Initialize every driven bus field before the first clock edge so the # DUT never sees unknown stimulus during reset release. self.dut.AXIS_ARESETN.setimmediatevalue(0) - self.dut.S_AXIS_TVALID.setimmediatevalue(0) - self.dut.S_AXIS_TDATA.setimmediatevalue(0) - self.dut.S_AXIS_TKEEP.setimmediatevalue(0xF) - self.dut.S_AXIS_TLAST.setimmediatevalue(0) - self.dut.S_AXIS_TDEST.setimmediatevalue(0) - self.dut.S_AXIS_TID.setimmediatevalue(0) - self.dut.S_AXIS_TUSER.setimmediatevalue(0) - self.dut.M_AXIS_TREADY.setimmediatevalue(1) + self.axis.init_source() + self.axis.init_sink() # Match the legacy benches by holding reset long enough for the SRP # FIFOs and attached RAM model to settle before the first frame. @@ -114,132 +65,23 @@ async def reset(self): for _ in range(8): await RisingEdge(self.dut.AXIS_ACLK) - async def send_words(self, words: list[int], *, tdest: int = 0): - # Present one 32-bit SSI beat at a time and only advance after the DUT - # accepts it. The first beat carries SOF in the flattened SSI TUSER bit. - for index, word in enumerate(words): - self.dut.S_AXIS_TVALID.value = 1 - self.dut.S_AXIS_TDATA.value = word & 0xFFFF_FFFF - self.dut.S_AXIS_TKEEP.value = 0xF - self.dut.S_AXIS_TLAST.value = int(index == len(words) - 1) - self.dut.S_AXIS_TDEST.value = tdest - self.dut.S_AXIS_TID.value = 0 - self.dut.S_AXIS_TUSER.value = 0x2 if index == 0 else 0x0 - - await wait_sampled_ready(self.dut.S_AXIS_TREADY, clk=self.dut.AXIS_ACLK) - - self.dut.S_AXIS_TVALID.value = 0 - self.dut.S_AXIS_TLAST.value = 0 - self.dut.S_AXIS_TUSER.value = 0 - async def wait_for_output_valid(self): # Used by the backpressure check: wait until the DUT has a response # pending while the sink is deliberately not ready. while int(self.dut.M_AXIS_TVALID.value) != 1: await with_timeout(RisingEdge(self.dut.AXIS_ACLK), 2, "ms") - async def recv_response(self) -> SrpResponse: - words = [] - tdest = [] - tuser = [] - tkeep = [] - self.dut.M_AXIS_TREADY.value = 1 - - # Capture exactly the beats that complete a ready/valid handshake. - while True: - await with_timeout(RisingEdge(self.dut.AXIS_ACLK), 2, "ms") - if int(self.dut.M_AXIS_TVALID.value) != 1: - continue - - words.append(int(self.dut.M_AXIS_TDATA.value)) - tdest.append(int(self.dut.M_AXIS_TDEST.value)) - tuser.append(int(self.dut.M_AXIS_TUSER.value)) - tkeep.append(int(self.dut.M_AXIS_TKEEP.value)) - if int(self.dut.M_AXIS_TLAST.value) == 1: - return SrpResponse(words=words, tdest=tdest, tuser=tuser, tkeep=tkeep) - - async def expect_no_response(self, *, cycles: int = 80): - # Posted writes are expected to update memory without producing any - # outbound SRP frame. Keep the sink ready so a surprise response cannot - # hide behind backpressure. - self.dut.M_AXIS_TREADY.value = 1 - for _ in range(cycles): - await RisingEdge(self.dut.AXIS_ACLK) - assert int(self.dut.M_AXIS_TVALID.value) == 0 - - -def request_header( - *, - opcode: int, - tid: int, - address: int, - req_size: int, - version: int = SRP_VERSION, - timeout: int = 0, - prot: int = 0, - spare: int = 0, -) -> list[int]: - word0 = ( - (version & 0xFF) - | ((opcode & 0x3) << 8) - | ((spare & 0x7FF) << 10) - | ((prot & 0x7) << 21) - | ((timeout & 0xFF) << 24) - ) - return [ - word0, - tid & 0xFFFF_FFFF, - address & 0xFFFF_FFFF, - (address >> 32) & 0xFFFF_FFFF, - req_size & 0xFFFF_FFFF, - ] - - -def request_frame(request: SrpRequest, payload: list[int] | None = None) -> list[int]: - payload = [] if payload is None else payload - return request_header( - opcode=request.opcode, - tid=request.tid, - address=request.address, - req_size=request.req_size, - version=request.version, - timeout=request.timeout, - prot=request.prot, - spare=request.spare, - ) + payload - - -def assert_response( - response: SrpResponse, - request: SrpRequest, - payload: list[int], - *, - footer_mask: int = 0, - footer_value: int = 0, - expected_tdest: int | None = None, -): - assert response.words[:5] == request.response_header - assert response.words[5:-1] == [word & 0xFFFF_FFFF for word in payload] - assert response.footer & footer_mask == footer_value - - if expected_tdest is not None: - assert response.tdest == [expected_tdest] * len(response.words) - - # All curated responses are full 32-bit words, including the footer. - assert response.tkeep == [0xF] * len(response.words) - assert response.tuser[0] & 0x2 == 0x2 - async def issue_and_check_error( tb: TB, - request: SrpRequest, + request: SrpV3Request, payload: list[int], *, expected_footer_bits: int, ): - await tb.send_words(request_frame(request, payload)) - response = await tb.recv_response() - assert_response( + await tb.axis.send_words(srpv3_frame(request, payload)) + response = await tb.axis.recv_response() + assert_srpv3_response( response, request, payload=payload, @@ -256,15 +98,15 @@ async def srpv3_axi_directed_protocol_matrix_test(dut): # A non-posted write must echo the accepted data, complete with a clean # footer, and the same bytes must be readable from the attached AXI RAM. write_payload = [0x11223344, 0x55667788, 0xA5A55A5A] - write_req = SrpRequest(SRP_WRITE, 0x1000_0001, 0x40, 4 * len(write_payload)) - await tb.send_words(request_frame(write_req, write_payload), tdest=0x3) - assert_response(await tb.recv_response(), write_req, write_payload, expected_tdest=0x3) + write_req = SrpV3Request(SRP_WRITE, 0x1000_0001, 0x40, 4 * len(write_payload)) + await tb.axis.send_words(srpv3_frame(write_req, write_payload), tdest=0x3) + assert_srpv3_response(await tb.axis.recv_response(), write_req, write_payload, expected_tdest=0x3) # Hold the response sink not-ready until the first read beat is pending. # The first header beat must remain stable until the sink accepts it. - read_req = SrpRequest(SRP_READ, 0x1000_0002, 0x40, 4 * len(write_payload), prot=0x5) + read_req = SrpV3Request(SRP_READ, 0x1000_0002, 0x40, 4 * len(write_payload), prot=0x5) tb.dut.M_AXIS_TREADY.value = 0 - await tb.send_words(request_frame(read_req), tdest=0x5) + await tb.axis.send_words(srpv3_frame(read_req), tdest=0x5) await tb.wait_for_output_valid() held_word = int(tb.dut.M_AXIS_TDATA.value) for _ in range(5): @@ -272,29 +114,29 @@ async def srpv3_axi_directed_protocol_matrix_test(dut): assert int(tb.dut.M_AXIS_TVALID.value) == 1 assert int(tb.dut.M_AXIS_TDATA.value) == held_word tb.dut.M_AXIS_TREADY.value = 1 - assert_response(await tb.recv_response(), read_req, write_payload, expected_tdest=0x5) + assert_srpv3_response(await tb.axis.recv_response(), read_req, write_payload, expected_tdest=0x5) # Posted writes are common in applications: they must not return a frame, # but a later read still has to observe the memory update. posted_payload = [0x01020304, 0xAABBCCDD, 0x0BADF00D, 0xCAFEBABE] - posted_req = SrpRequest(SRP_POSTED_WRITE, 0x2000_0001, 0x80, 4 * len(posted_payload)) - await tb.send_words(request_frame(posted_req, posted_payload), tdest=0x7) - await tb.expect_no_response() + posted_req = SrpV3Request(SRP_POSTED_WRITE, 0x2000_0001, 0x80, 4 * len(posted_payload)) + await tb.axis.send_words(srpv3_frame(posted_req, posted_payload), tdest=0x7) + await tb.axis.expect_no_response() - posted_read_req = SrpRequest(SRP_READ, 0x2000_0002, 0x80, 4 * len(posted_payload)) - await tb.send_words(request_frame(posted_read_req), tdest=0x7) - assert_response(await tb.recv_response(), posted_read_req, posted_payload, expected_tdest=0x7) + posted_read_req = SrpV3Request(SRP_READ, 0x2000_0002, 0x80, 4 * len(posted_payload)) + await tb.axis.send_words(srpv3_frame(posted_read_req), tdest=0x7) + assert_srpv3_response(await tb.axis.recv_response(), posted_read_req, posted_payload, expected_tdest=0x7) # NULL requests exercise the header/footer-only path without touching the # AXI RAM. The request size is still echoed so software can correlate it. - null_req = SrpRequest(SRP_NULL, 0x3000_0001, 0x0000, 1) - await tb.send_words(request_frame(null_req), tdest=0x1) - assert_response(await tb.recv_response(), null_req, [], expected_tdest=0x1) + null_req = SrpV3Request(SRP_NULL, 0x3000_0001, 0x0000, 1) + await tb.axis.send_words(srpv3_frame(null_req), tdest=0x1) + assert_srpv3_response(await tb.axis.recv_response(), null_req, [], expected_tdest=0x1) # The footer matrix locks down common software-visible failure reporting: # bad version, malformed write framing, invalid alignment/size, and an AXI # address-range error returned from the bridge layer. - bad_version_req = SrpRequest(SRP_READ, 0x4000_0001, 0x40, 4, version=0x02) + bad_version_req = SrpV3Request(SRP_READ, 0x4000_0001, 0x40, 4, version=0x02) await issue_and_check_error( tb, bad_version_req, @@ -302,7 +144,7 @@ async def srpv3_axi_directed_protocol_matrix_test(dut): expected_footer_bits=FOOTER_VERSION_MISMATCH, ) - truncated_write_req = SrpRequest(SRP_WRITE, 0x4000_0002, 0x40, 4) + truncated_write_req = SrpV3Request(SRP_WRITE, 0x4000_0002, 0x40, 4) await issue_and_check_error( tb, truncated_write_req, @@ -310,7 +152,7 @@ async def srpv3_axi_directed_protocol_matrix_test(dut): expected_footer_bits=FOOTER_FRAME_ERROR, ) - unaligned_read_req = SrpRequest(SRP_READ, 0x4000_0003, 0x42, 4) + unaligned_read_req = SrpV3Request(SRP_READ, 0x4000_0003, 0x42, 4) await issue_and_check_error( tb, unaligned_read_req, @@ -318,7 +160,7 @@ async def srpv3_axi_directed_protocol_matrix_test(dut): expected_footer_bits=FOOTER_REQUEST_ERROR, ) - short_read_req = SrpRequest(SRP_READ, 0x4000_0004, 0x40, 2) + short_read_req = SrpV3Request(SRP_READ, 0x4000_0004, 0x40, 2) await issue_and_check_error( tb, short_read_req, @@ -326,7 +168,7 @@ async def srpv3_axi_directed_protocol_matrix_test(dut): expected_footer_bits=FOOTER_REQUEST_ERROR, ) - out_of_range_write_req = SrpRequest(SRP_WRITE, 0x4000_0005, 0x1000, 4) + out_of_range_write_req = SrpV3Request(SRP_WRITE, 0x4000_0005, 0x1000, 4) await issue_and_check_error( tb, out_of_range_write_req, @@ -334,7 +176,7 @@ async def srpv3_axi_directed_protocol_matrix_test(dut): expected_footer_bits=FOOTER_ADDRESS_ERROR, ) - out_of_range_read_req = SrpRequest(SRP_READ, 0x4000_0006, 0x1_0000_0000, 4) + out_of_range_read_req = SrpV3Request(SRP_READ, 0x4000_0006, 0x1_0000_0000, 4) await issue_and_check_error( tb, out_of_range_read_req, diff --git a/tests/protocols/srp/test_SrpV3AxiLite.py b/tests/protocols/srp/test_SrpV3AxiLite.py index f4361d89ad..838ec3c676 100644 --- a/tests/protocols/srp/test_SrpV3AxiLite.py +++ b/tests/protocols/srp/test_SrpV3AxiLite.py @@ -26,7 +26,7 @@ import pytest from cocotb.clock import Clock from cocotb.triggers import RisingEdge -from cocotbext.axi import AxiLiteBus, AxiLiteRam +from cocotbext.axi import AxiLiteBus, AxiLiteRam, AxiResp from tests.common.regression_utils import run_surf_vhdl_test from tests.protocols.srp.srp_test_utils import ( @@ -45,7 +45,7 @@ class TB: - def __init__(self, dut): + def __init__(self, dut, *, use_ram: bool = True): self.dut = dut cocotb.start_soon(Clock(dut.AXIS_ACLK, 10.0, unit="ns").start()) self.axis = FlatSrpAxis( @@ -53,13 +53,15 @@ def __init__(self, dut): clk=dut.AXIS_ACLK, data_bytes=int(os.environ.get("SRP_AXIS_BYTES", "4")), ) - self.axil_ram = AxiLiteRam( - AxiLiteBus.from_prefix(dut, "M_AXIL"), - dut.AXIS_ACLK, - dut.AXIS_ARESETN, - reset_active_level=False, - size=2**12, - ) + self.axil_ram = None + if use_ram: + self.axil_ram = AxiLiteRam( + AxiLiteBus.from_prefix(dut, "M_AXIL"), + dut.AXIS_ACLK, + dut.AXIS_ARESETN, + reset_active_level=False, + size=2**12, + ) async def reset(self): # Reset the wrapper and initialize both stream directions before any @@ -67,12 +69,38 @@ async def reset(self): self.dut.AXIS_ARESETN.setimmediatevalue(0) self.axis.init_source() self.axis.init_sink() + if self.axil_ram is None: + self.dut.M_AXIL_AWREADY.setimmediatevalue(0) + self.dut.M_AXIL_WREADY.setimmediatevalue(0) + self.dut.M_AXIL_BRESP.setimmediatevalue(0) + self.dut.M_AXIL_BVALID.setimmediatevalue(0) + self.dut.M_AXIL_ARREADY.setimmediatevalue(0) + self.dut.M_AXIL_RDATA.setimmediatevalue(0) + self.dut.M_AXIL_RRESP.setimmediatevalue(0) + self.dut.M_AXIL_RVALID.setimmediatevalue(0) for _ in range(80): await RisingEdge(self.dut.AXIS_ACLK) self.dut.AXIS_ARESETN.value = 1 for _ in range(8): await RisingEdge(self.dut.AXIS_ACLK) + async def respond_one_read(self, *, data: int, resp: AxiResp = AxiResp.OKAY): + self.dut.M_AXIL_ARREADY.value = 1 + while True: + await RisingEdge(self.dut.AXIS_ACLK) + if int(self.dut.M_AXIL_ARVALID.value) and int(self.dut.M_AXIL_ARREADY.value): + break + self.dut.M_AXIL_ARREADY.value = 0 + self.dut.M_AXIL_RDATA.value = data + self.dut.M_AXIL_RRESP.value = int(resp) + self.dut.M_AXIL_RVALID.value = 1 + while True: + await RisingEdge(self.dut.AXIS_ACLK) + if int(self.dut.M_AXIL_RREADY.value): + break + self.dut.M_AXIL_RVALID.value = 0 + self.dut.M_AXIL_RRESP.value = 0 + def _selected_cocotb_test(name: str) -> bool: return os.environ.get("SRP_AXI_LITE_COCOTB_TEST", "directed") == name @@ -152,18 +180,7 @@ async def srpv3_axilite_single_read_probe_test(dut): # First valid AXI-Lite-backed read. If this stalls, the failure is after # header parsing and in the AXI-Lite transaction or response path. read_req = SrpV3Request(SRP_READ, 0x5100_0100, 0x20, 4) - dut._log.info("single read probe: sending request") await tb.axis.send_words(srpv3_frame(read_req), tdest=0x1) - dut._log.info("single read probe: request accepted") - dut._log.info( - "single read probe: post-request pins " - "M_AXIS_TVALID=%s M_AXIS_TREADY=%s M_AXIL_ARVALID=%s M_AXIL_ARREADY=%s M_AXIL_RREADY=%s", - dut.M_AXIS_TVALID.value, - dut.M_AXIS_TREADY.value, - dut.M_AXIL_ARVALID.value, - dut.M_AXIL_ARREADY.value, - dut.M_AXIL_RREADY.value, - ) assert_srpv3_response( await tb.axis.recv_response(), read_req, @@ -228,6 +245,36 @@ async def srpv3_axilite_read_write_and_error_paths_test(dut): ) +@cocotb.test(skip=not _selected_cocotb_test("ignore_mem_resp")) +async def srpv3_axilite_ignore_memory_response_test(dut): + tb = TB(dut, use_ram=False) + await tb.reset() + + # The direct SRPv3 AXI-Lite bridge supports the legacy ignoreMemResp bit. + # A failing AXI-Lite read should still return payload and a clean footer + # when that bit is set. + read_req = SrpV3Request( + SRP_READ, + 0x5100_0007, + 0x40, + 4, + ignore_mem_resp=1, + ) + read_task = cocotb.start_soon( + tb.respond_one_read(data=0x1234_5678, resp=AxiResp.SLVERR), + ) + await tb.axis.send_words(srpv3_frame(read_req), tdest=0x1) + response = await tb.axis.recv_response() + await read_task + assert_srpv3_response( + response, + read_req, + [0xFFFF_FFFF], + expected_tdest=0x1, + ) + assert response.footer == 0 + + ACTIVE_PARAMETER_SWEEP = [ pytest.param( { @@ -310,6 +357,17 @@ def test_SrpV3AxiLite(parameters): _run_srpv3_axilite_case(parameters, "directed", "directed") +def test_SrpV3AxiLite_ignore_mem_resp(): + _run_srpv3_axilite_case( + { + "TOPLEVEL": "surf.srpv3axilitewrapper", + "WRAPPER_SOURCE": "protocols/srp/wrappers/SrpV3AxiLiteWrapper.vhd", + }, + "ignore_mem_resp", + "ignore_mem_resp", + ) + + def test_SrpV3AxiLite_legacy_wide_directed(): _run_srpv3_axilite_case( LEGACY_WIDE_DIRECT_PARAMETERS, diff --git a/tests/protocols/srp/test_SrpV3Core.py b/tests/protocols/srp/test_SrpV3Core.py index 277f28ee18..f6aca6b06b 100644 --- a/tests/protocols/srp/test_SrpV3Core.py +++ b/tests/protocols/srp/test_SrpV3Core.py @@ -27,14 +27,19 @@ from cocotb.clock import Clock from cocotb.triggers import RisingEdge +from tests.axi.utils import wait_sampled_ready from tests.common.regression_utils import run_surf_vhdl_test from tests.protocols.srp.srp_test_utils import ( FOOTER_ADDRESS_ERROR, + FOOTER_EOFE, FOOTER_FRAME_ERROR, + FOOTER_REQUEST_ERROR, FlatSrpAxis, SRP_READ, + SRP_WRITE, SrpV3Request, assert_srpv3_response, + srpv3_frame, ) @@ -59,16 +64,87 @@ async def reset(self, *, settle_cycles: int = 8): for _ in range(settle_cycles): await RisingEdge(self.dut.AXIS_ACLK) + async def pulse_ack(self, *, resp: int = 0): + self.dut.SRP_ACK_RESP.value = resp + self.dut.SRP_ACK_DONE.value = 1 + for _ in range(8): + await RisingEdge(self.dut.AXIS_ACLK) + if int(self.dut.SRP_REQ_REQUEST.value) == 0: + break + else: + raise AssertionError("Timed out waiting for SRP_REQ_REQUEST to release") + self.dut.SRP_ACK_DONE.value = 0 + self.dut.SRP_ACK_RESP.value = 0 + + async def wait_for_request(self): + for _ in range(64): + await RisingEdge(self.dut.AXIS_ACLK) + if int(self.dut.SRP_REQ_REQUEST.value) == 1: + return + raise AssertionError("Timed out waiting for SRP_REQ_REQUEST") + + async def send_words_with_tuser( + self, + words: list[int], + users: list[int], + *, + lasts: list[int] | None = None, + tdest: int = 0, + prefix: str = "S_AXIS", + ): + assert len(words) == len(users) + if lasts is None: + lasts = [int(index == len(words) - 1) for index in range(len(words))] + assert len(words) == len(lasts) + for index, (word, user) in enumerate(zip(words, users)): + getattr(self.dut, f"{prefix}_TVALID").value = 1 + getattr(self.dut, f"{prefix}_TDATA").value = word & 0xFFFF_FFFF + getattr(self.dut, f"{prefix}_TKEEP").value = 0xF + getattr(self.dut, f"{prefix}_TLAST").value = lasts[index] + if hasattr(self.dut, f"{prefix}_TDEST"): + getattr(self.dut, f"{prefix}_TDEST").value = tdest + if hasattr(self.dut, f"{prefix}_TID"): + getattr(self.dut, f"{prefix}_TID").value = 0 + getattr(self.dut, f"{prefix}_TUSER").value = user + await wait_sampled_ready( + getattr(self.dut, f"{prefix}_TREADY"), + clk=self.dut.AXIS_ACLK, + ) + getattr(self.dut, f"{prefix}_TVALID").value = 0 + getattr(self.dut, f"{prefix}_TLAST").value = 0 + getattr(self.dut, f"{prefix}_TUSER").value = 0 + def _selected_cocotb_test(name: str) -> bool: return os.environ.get("SRP_CORE_COCOTB_TEST", "reset_idle") == name -@cocotb.test() -async def srpv3_core_reset_idle_smoke_test(dut): - if not _selected_cocotb_test("reset_idle"): - return +async def issue_and_check_error( + tb: TB, + request: SrpV3Request, + payload: list[int] | None = None, + *, + expected_footer_bits: int, + expected_tdest: int | None = None, +): + payload = [] if payload is None else payload + response_task = cocotb.start_soon(tb.axis.recv_response()) + await tb.axis.send_words( + srpv3_frame(request, payload), + tdest=0 if expected_tdest is None else expected_tdest, + ) + assert_srpv3_response( + await response_task, + request, + payload=payload if expected_footer_bits in (FOOTER_FRAME_ERROR, FOOTER_EOFE) else [], + footer_mask=expected_footer_bits, + footer_value=expected_footer_bits, + expected_tdest=expected_tdest, + ) + +@cocotb.test(skip=not _selected_cocotb_test("reset_idle")) +async def srpv3_core_reset_idle_smoke_test(dut): tb = TB(dut) await tb.reset(settle_cycles=32) @@ -77,11 +153,8 @@ async def srpv3_core_reset_idle_smoke_test(dut): assert int(dut.WR_AXIS_TVALID.value) == 0 -@cocotb.test() +@cocotb.test(skip=not _selected_cocotb_test("narrow_fault_injection")) async def srpv3_core_narrow_header_error_probes_test(dut): - if not _selected_cocotb_test("narrow_fault_injection"): - return - tb = TB(dut) await tb.reset() @@ -117,11 +190,8 @@ async def srpv3_core_narrow_header_error_probes_test(dut): assert int(dut.SRP_REQ_REQUEST.value) == 0 -@cocotb.test() +@cocotb.test(skip=not _selected_cocotb_test("narrow_fault_injection")) async def srpv3_core_narrow_immediate_read_error_test(dut): - if not _selected_cocotb_test("narrow_fault_injection"): - return - tb = TB(dut) await tb.reset() dut.M_AXIS_TREADY.value = 0 @@ -129,23 +199,8 @@ async def srpv3_core_narrow_immediate_read_error_test(dut): request = SrpV3Request(SRP_READ, 0x6100_0001, 0x1_0000_0000, 4) await tb.axis.send_words(request.response_header, tdest=0x5) - for _ in range(64): - await RisingEdge(dut.AXIS_ACLK) - if int(dut.SRP_REQ_REQUEST.value) == 1: - break - else: - raise AssertionError("Timed out waiting for SRP_REQ_REQUEST") - - dut.SRP_ACK_RESP.value = FOOTER_ADDRESS_ERROR - dut.SRP_ACK_DONE.value = 1 - for _ in range(8): - await RisingEdge(dut.AXIS_ACLK) - if int(dut.SRP_REQ_REQUEST.value) == 0: - break - else: - raise AssertionError("Timed out waiting for SRP_REQ_REQUEST to release") - dut.SRP_ACK_DONE.value = 0 - dut.SRP_ACK_RESP.value = 0 + await tb.wait_for_request() + await tb.pulse_ack(resp=FOOTER_ADDRESS_ERROR) for _ in range(64): await RisingEdge(dut.AXIS_ACLK) @@ -166,6 +221,108 @@ async def srpv3_core_narrow_immediate_read_error_test(dut): assert int(dut.RD_AXIS_TREADY.value) == 0 +@cocotb.test(skip=not _selected_cocotb_test("disabled_op")) +async def srpv3_core_disabled_operation_test(dut): + tb = TB(dut) + await tb.reset() + + mode = os.environ["SRP_CORE_DISABLED_OP"] + if mode == "read": + request = SrpV3Request(SRP_READ, 0x7100_0001, 0x20, 4) + await issue_and_check_error( + tb, + request, + expected_footer_bits=FOOTER_REQUEST_ERROR, + expected_tdest=0x2, + ) + else: + request = SrpV3Request(SRP_WRITE, 0x7100_0002, 0x20, 4) + await issue_and_check_error( + tb, + request, + [0x1357_9BDF], + expected_footer_bits=FOOTER_REQUEST_ERROR, + expected_tdest=0x3, + ) + assert int(dut.SRP_REQ_REQUEST.value) == 0 + + +@cocotb.test(skip=not _selected_cocotb_test("narrow_protocol_edges")) +async def srpv3_core_narrow_protocol_edge_cases_test(dut): + tb = TB(dut) + await tb.reset() + + # Frames without SOF should be discarded rather than interpreted as a + # request. + no_sof_request = SrpV3Request(SRP_READ, 0x7200_0001, 0x20, 4) + await tb.send_words_with_tuser(srpv3_frame(no_sof_request), [0, 0, 0, 0, 0]) + await tb.axis.expect_no_response(cycles=96) + assert int(dut.SRP_REQ_REQUEST.value) == 0 + + # A write that terminates before the requested byte count reports a framing + # error while still echoing the data word that was accepted. + short_write_request = SrpV3Request(SRP_WRITE, 0x7200_0003, 0x28, 8) + short_write_payload = [0xDEAD_BEEF] + response_task = cocotb.start_soon(tb.axis.recv_response()) + await tb.axis.send_words( + srpv3_frame(short_write_request, short_write_payload), + tdest=0x5, + ) + await tb.wait_for_request() + await tb.pulse_ack() + assert_srpv3_response( + await response_task, + short_write_request, + payload=short_write_payload, + footer_mask=FOOTER_FRAME_ERROR, + footer_value=FOOTER_FRAME_ERROR, + expected_tdest=0x5, + ) + + # A read-data stream that asserts TLAST before the requested byte count is + # surfaced as EOFE in the response footer after the downstream ack. + early_read_request = SrpV3Request(SRP_READ, 0x7200_0004, 0x2C, 8) + early_read_payload = [0xCAFE_BABE] + response_task = cocotb.start_soon(tb.axis.recv_response()) + await tb.axis.send_words(srpv3_frame(early_read_request), tdest=0x6) + await tb.wait_for_request() + await tb.read_axis.send_words(early_read_payload, prefix="RD_AXIS") + await tb.pulse_ack() + assert_srpv3_response( + await response_task, + early_read_request, + payload=early_read_payload, + footer_mask=FOOTER_EOFE, + footer_value=FOOTER_EOFE, + expected_tdest=0x6, + ) + + # A read-data stream that omits TLAST when the requested byte count is + # reached also reports EOFE, then blows off the trailing data beat. + late_read_request = SrpV3Request(SRP_READ, 0x7200_0005, 0x30, 4) + late_read_payload = [0x0BAD_C0DE] + response_task = cocotb.start_soon(tb.axis.recv_response()) + await tb.axis.send_words(srpv3_frame(late_read_request), tdest=0x7) + await tb.wait_for_request() + read_data_task = cocotb.start_soon( + tb.send_words_with_tuser( + late_read_payload + [0xFEED_FACE], + [0x2, 0], + lasts=[0, 1], + prefix="RD_AXIS", + ), + ) + assert_srpv3_response( + await response_task, + late_read_request, + payload=late_read_payload, + footer_mask=FOOTER_EOFE, + footer_value=FOOTER_EOFE, + expected_tdest=0x7, + ) + await read_data_task + + CORE_PARAMETER_SWEEP = [ pytest.param( { @@ -181,6 +338,29 @@ async def srpv3_core_narrow_immediate_read_error_test(dut): }, id="direct_core_narrow_fault_injection", ), + pytest.param( + { + "COCOTB_TEST": "narrow_protocol_edges", + "HDL_PARAMETERS": {"CORE_DATA_BYTES_G": 4}, + }, + id="direct_core_narrow_protocol_edges", + ), + pytest.param( + { + "COCOTB_TEST": "disabled_op", + "DISABLED_OP": "read", + "HDL_PARAMETERS": {"CORE_DATA_BYTES_G": 4, "READ_EN_G": False}, + }, + id="direct_core_read_disabled", + ), + pytest.param( + { + "COCOTB_TEST": "disabled_op", + "DISABLED_OP": "write", + "HDL_PARAMETERS": {"CORE_DATA_BYTES_G": 4, "WRITE_EN_G": False}, + }, + id="direct_core_write_disabled", + ), ] @@ -191,6 +371,9 @@ def test_SrpV3Core(parameters): test_file=__file__, toplevel="surf.srpv3corewrapper", parameters=hdl_parameters, - extra_env={"SRP_CORE_COCOTB_TEST": parameters["COCOTB_TEST"]}, + extra_env={ + "SRP_CORE_COCOTB_TEST": parameters["COCOTB_TEST"], + "SRP_CORE_DISABLED_OP": parameters.get("DISABLED_OP", ""), + }, extra_vhdl_sources={"surf": ["protocols/srp/wrappers/SrpV3CoreWrapper.vhd"]}, ) From 2e5f324e079952530e2be30509782f520f3c5f91 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Sun, 3 May 2026 16:00:04 -0700 Subject: [PATCH 85/92] Add SIMULATION_G to SugoiManagerRx hierarchy to bypass IDELAYE3 The Xilinx Unisim IDELAYE3 simulation model emits "Invalid Scenario LOAD = X CE = 0 INC = 0" warnings every clock cycle when LOAD has X during initialization (e.g. before reset propagates), spamming the simulation log. Add SIMULATION_G to SugoiManagerRxUltrascale and SugoiManagerRx so the existing SugoiManagerCore.SIMULATION_G can propagate down and bypass the IDELAYE3 instance during simulation (rxDly <= rxIn). For real hardware builds (SIMULATION_G=false, the default) the IDELAYE3 is instantiated as before. --- protocols/sugoi/rtl/SugoiManagerCore.vhd | 1 + protocols/sugoi/rtl/SugoiManagerRx.vhd | 2 + .../UltraScale/SugoiManagerRxUltrascale.vhd | 54 +++++++++++-------- .../dummy/SugoiManagerRxUltrascaleDummy.vhd | 1 + 4 files changed, 35 insertions(+), 23 deletions(-) diff --git a/protocols/sugoi/rtl/SugoiManagerCore.vhd b/protocols/sugoi/rtl/SugoiManagerCore.vhd index 28c867dd14..e3c4bc6ebe 100644 --- a/protocols/sugoi/rtl/SugoiManagerCore.vhd +++ b/protocols/sugoi/rtl/SugoiManagerCore.vhd @@ -141,6 +141,7 @@ begin U_Rx : entity surf.SugoiManagerRx generic map ( TPD_G => TPD_G, + SIMULATION_G => SIMULATION_G, DIFF_PAIR_G => DIFF_PAIR_G, DEVICE_FAMILY_G => DEVICE_FAMILY_G, IODELAY_GROUP_G => IODELAY_GROUP_G, diff --git a/protocols/sugoi/rtl/SugoiManagerRx.vhd b/protocols/sugoi/rtl/SugoiManagerRx.vhd index 90f4f216ec..7328954508 100644 --- a/protocols/sugoi/rtl/SugoiManagerRx.vhd +++ b/protocols/sugoi/rtl/SugoiManagerRx.vhd @@ -25,6 +25,7 @@ use surf.StdRtlPkg.all; entity SugoiManagerRx is generic ( TPD_G : time := 1 ns; + SIMULATION_G : boolean := false; DIFF_PAIR_G : boolean := true; DEVICE_FAMILY_G : string := "ULTRASCALE"; IODELAY_GROUP_G : string := "DESER_GROUP"; -- IDELAYCTRL not used in COUNT mode @@ -72,6 +73,7 @@ begin U_SugoiManagerRx_1 : entity surf.SugoiManagerRxUltrascale generic map ( TPD_G => TPD_G, + SIMULATION_G => SIMULATION_G, DIFF_PAIR_G => DIFF_PAIR_G, DEVICE_FAMILY_G => DEVICE_FAMILY_G, IODELAY_GROUP_G => IODELAY_GROUP_G, diff --git a/protocols/sugoi/rtl/UltraScale/SugoiManagerRxUltrascale.vhd b/protocols/sugoi/rtl/UltraScale/SugoiManagerRxUltrascale.vhd index 71d76d55a1..b6fdefacde 100644 --- a/protocols/sugoi/rtl/UltraScale/SugoiManagerRxUltrascale.vhd +++ b/protocols/sugoi/rtl/UltraScale/SugoiManagerRxUltrascale.vhd @@ -28,6 +28,7 @@ use unisim.vcomponents.all; entity SugoiManagerRxUltrascale is generic ( TPD_G : time := 1 ns; + SIMULATION_G : boolean := false; DIFF_PAIR_G : boolean := true; DEVICE_FAMILY_G : string := "ULTRASCALE"; IODELAY_GROUP_G : string := "DESER_GROUP"; -- IDELAYCTRL not used in COUNT mode @@ -71,29 +72,36 @@ begin O => rxIn); end generate; - U_DELAY : entity surf.Idelaye3Wrapper - generic map ( - DELAY_FORMAT => "COUNT", - SIM_DEVICE => DEVICE_FAMILY_G, - DELAY_VALUE => 0, - REFCLK_FREQUENCY => REF_FREQ_G, -- IDELAYCTRL not used in COUNT mode - UPDATE_MODE => "ASYNC", - CASCADE => "NONE", - DELAY_SRC => "IDATAIN", - DELAY_TYPE => "VAR_LOAD") - port map( - DATAIN => '0', - IDATAIN => rxIn, - DATAOUT => rxDly, - CLK => clk, - RST => rst, - CE => '0', - INC => '0', - LOAD => dlyLoad, - EN_VTC => '0', - CASC_IN => '0', - CASC_RETURN => '0', - CNTVALUEIN => dlyCfg); + GEN_REAL : if (SIMULATION_G = false) generate + U_DELAY : entity surf.Idelaye3Wrapper + generic map ( + DELAY_FORMAT => "COUNT", + SIM_DEVICE => DEVICE_FAMILY_G, + DELAY_VALUE => 0, + REFCLK_FREQUENCY => REF_FREQ_G, -- IDELAYCTRL not used in COUNT mode + UPDATE_MODE => "ASYNC", + CASCADE => "NONE", + DELAY_SRC => "IDATAIN", + DELAY_TYPE => "VAR_LOAD") + port map( + DATAIN => '0', + IDATAIN => rxIn, + DATAOUT => rxDly, + CLK => clk, + RST => rst, + CE => '0', + INC => '0', + LOAD => dlyLoad, + EN_VTC => '0', + CASC_IN => '0', + CASC_RETURN => '0', + CNTVALUEIN => dlyCfg); + end generate GEN_REAL; + + GEN_SIM : if (SIMULATION_G = true) generate + -- Bypass IDELAYE3 in simulation to avoid Unisim model assertion warnings + rxDly <= rxIn; + end generate GEN_SIM; U_IDDR : IDDRE1 generic map ( diff --git a/protocols/sugoi/rtl/dummy/SugoiManagerRxUltrascaleDummy.vhd b/protocols/sugoi/rtl/dummy/SugoiManagerRxUltrascaleDummy.vhd index 488cf555b1..20bc387a2d 100644 --- a/protocols/sugoi/rtl/dummy/SugoiManagerRxUltrascaleDummy.vhd +++ b/protocols/sugoi/rtl/dummy/SugoiManagerRxUltrascaleDummy.vhd @@ -25,6 +25,7 @@ use surf.StdRtlPkg.all; entity SugoiManagerRxUltrascale is generic ( TPD_G : time := 1 ns; + SIMULATION_G : boolean := false; DIFF_PAIR_G : boolean := true; DEVICE_FAMILY_G : string := "ULTRASCALE"; IODELAY_GROUP_G : string := "DESER_GROUP"; -- IDELAYCTRL not used in COUNT mode From 045de704912f5d86970b6b44f657b332144022ce Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Sun, 3 May 2026 22:07:19 -0700 Subject: [PATCH 86/92] Remove planning files. --- docs/_meta/rtl_instantiation_graph.json | 14578 ------------------- docs/_meta/rtl_instantiation_graph.md | 270 - docs/_meta/rtl_phase1_queue.json | 5874 -------- docs/_meta/rtl_phase1_queue.md | 272 - docs/_meta/rtl_phase1_queue_overrides.json | 85 - 5 files changed, 21079 deletions(-) delete mode 100644 docs/_meta/rtl_instantiation_graph.json delete mode 100644 docs/_meta/rtl_instantiation_graph.md delete mode 100644 docs/_meta/rtl_phase1_queue.json delete mode 100644 docs/_meta/rtl_phase1_queue.md delete mode 100644 docs/_meta/rtl_phase1_queue_overrides.json diff --git a/docs/_meta/rtl_instantiation_graph.json b/docs/_meta/rtl_instantiation_graph.json deleted file mode 100644 index cac3414382..0000000000 --- a/docs/_meta/rtl_instantiation_graph.json +++ /dev/null @@ -1,14578 +0,0 @@ -{ - "generated_from": { - "scan_dirs": [ - "base", - "axi", - "dsp", - "protocols", - "ethernet", - "devices", - "xilinx" - ], - "parser_scope": "VHDL entities outside tb/build/.venv paths", - "parser_limitations": [ - "Package calls are not graph nodes.", - "Direct entity instantiations are handled explicitly.", - "Component-style instantiations are inferred only when the instantiated name matches a known entity name inside an architecture body." - ] - }, - "summary": { - "entity_count": 795, - "edge_count": 1584, - "duplicate_entity_names": { - "Ad9249Deserializer": [ - "devices/AnalogDevices/ad9249/7Series/rtl/Ad9249Deserializer.vhd", - "devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd" - ], - "Ad9249ReadoutGroup": [ - "devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd", - "devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd" - ], - "ClinkDataClk": [ - "protocols/clink/7Series/ClinkDataClk.vhd", - "protocols/clink/UltraScale/ClinkDataClk.vhd" - ], - "ClinkDataShift": [ - "protocols/clink/7Series/ClinkDataShift.vhd", - "protocols/clink/UltraScale/ClinkDataShift.vhd" - ], - "ClkOutBufDiff": [ - "xilinx/dummy/ClkOutBufDiffDummy.vhd", - "xilinx/general/rtl/ClkOutBufDiff.vhd" - ], - "ClkOutBufSingle": [ - "xilinx/dummy/ClkOutBufSingleDummy.vhd", - "xilinx/general/rtl/ClkOutBufSingle.vhd" - ], - "ClockManagerUltraScale": [ - "xilinx/UltraScale/clocking/rtl/ClockManagerUltraScale.vhd", - "xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd" - ], - "CoaXPressOverFiberGthUsIpWrapper": [ - "protocols/coaxpress/gthUs/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd", - "protocols/coaxpress/gthUs+/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd" - ], - "CoaxpressOverFiberGthUs": [ - "protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUs.vhd", - "protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUs.vhd" - ], - "CoaxpressOverFiberGthUsQpll": [ - "protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUsQpll.vhd", - "protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUsQpll.vhd" - ], - "DS2411Core": [ - "devices/Maxim/dummy/DS2411CoreDummy.vhd", - "devices/Maxim/rtl/DS2411Core.vhd" - ], - "DeviceDna": [ - "xilinx/dummy/DeviceDnaDummy.vhd", - "xilinx/general/rtl/DeviceDna.vhd" - ], - "FifoAlteraMf": [ - "base/fifo/rtl/altera/FifoAlteraMf.vhd", - "base/fifo/rtl/dummy/FifoAlteraMfDummy.vhd" - ], - "FifoXpm": [ - "base/fifo/rtl/dummy/FifoXpmDummy.vhd", - "base/fifo/rtl/xilinx/FifoXpm.vhd" - ], - "GigEthGthUltraScale": [ - "ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd", - "ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd" - ], - "GigEthGthUltraScaleWrapper": [ - "ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd", - "ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd" - ], - "GthUltraScaleQuadPll": [ - "xilinx/UltraScale/gthUs/rtl/GthUltraScaleQuadPll.vhd", - "xilinx/UltraScale+/gthUs+/rtl/GthUltraScaleQuadPll.vhd" - ], - "Idelaye3Wrapper": [ - "xilinx/7Series/dummy/Idelaye3WrapperDummy.vhd", - "xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd" - ], - "InputBufferReg": [ - "xilinx/7Series/general/rtl/InputBufferReg.vhd", - "xilinx/UltraScale/general/rtl/InputBufferReg.vhd" - ], - "IoBufWrapper": [ - "xilinx/dummy/IoBufWrapperDummy.vhd", - "xilinx/general/rtl/IoBufWrapper.vhd" - ], - "Iprog": [ - "xilinx/dummy/IprogDummy.vhd", - "xilinx/general/rtl/Iprog.vhd" - ], - "MicroblazeBasicCoreWrapper": [ - "xilinx/general/microblaze/bypass/MicroblazeBasicCoreWrapper.vhd", - "xilinx/general/microblaze/generate/MicroblazeBasicCoreWrapper.vhd" - ], - "Odelaye3Wrapper": [ - "xilinx/7Series/dummy/Odelaye3WrapperDummy.vhd", - "xilinx/UltraScale/general/rtl/Odelaye3Wrapper.vhd" - ], - "OutputBufferReg": [ - "xilinx/7Series/general/rtl/OutputBufferReg.vhd", - "xilinx/UltraScale/general/rtl/OutputBufferReg.vhd", - "xilinx/dummy/OutputBufferRegDummy.vhd" - ], - "Pgp2bGthUltra": [ - "protocols/pgp/pgp2b/gthUltraScale/rtl/Pgp2bGthUltra.vhd", - "protocols/pgp/pgp2b/gthUltraScale+/rtl/Pgp2bGthUltra.vhd" - ], - "Pgp3GthUs": [ - "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUs.vhd", - "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUs.vhd" - ], - "Pgp3GthUsIpWrapper": [ - "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd", - "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsIpWrapper.vhd" - ], - "Pgp3GthUsQpll": [ - "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd", - "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsQpll.vhd" - ], - "Pgp3GthUsWrapper": [ - "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsWrapper.vhd", - "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsWrapper.vhd" - ], - "Pgp4GthUs": [ - "protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUs.vhd", - "protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUs.vhd" - ], - "Pgp4GthUsWrapper": [ - "protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUsWrapper.vhd", - "protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUsWrapper.vhd" - ], - "PgpGthCoreWrapper": [ - "protocols/pgp/pgp2b/gthUltraScale/rtl/PgpGthCoreWrapper.vhd", - "protocols/pgp/pgp2b/gthUltraScale+/rtl/PgpGthCoreWrapper.vhd" - ], - "RogueSideBand": [ - "axi/simlink/ghdl/RogueSideBand.vhd", - "axi/simlink/sim/RogueSideBand.vhd" - ], - "RogueTcpMemory": [ - "axi/simlink/ghdl/RogueTcpMemory.vhd", - "axi/simlink/sim/RogueTcpMemory.vhd" - ], - "RogueTcpStream": [ - "axi/simlink/ghdl/RogueTcpStream.vhd", - "axi/simlink/sim/RogueTcpStream.vhd" - ], - "SaltRxDeser": [ - "protocols/salt/rtl/7Series/SaltRxDeser.vhd", - "protocols/salt/rtl/UltraScale/SaltRxDeser.vhd" - ], - "SaltTxSer": [ - "protocols/salt/rtl/7Series/SaltTxSer.vhd", - "protocols/salt/rtl/UltraScale/SaltTxSer.vhd" - ], - "SimpleDualPortRamXpm": [ - "base/ram/dummy/SimpleDualPortRamXpmDummy.vhd", - "base/ram/xilinx/SimpleDualPortRamXpm.vhd" - ], - "SinglePortRamPrimitive": [ - "base/ram/dummy/SinglePortRamPrimitiveDummy.vhd", - "base/ram/xilinx/SinglePortRamPrimitive.vhd" - ], - "Srl16Delay": [ - "xilinx/dummy/Srl16DelayDummy.vhd", - "xilinx/general/rtl/Srl16Delay.vhd" - ], - "SugoiManagerRx7Series": [ - "protocols/sugoi/rtl/7Series/SugoiManagerRx7Series.vhd", - "protocols/sugoi/rtl/dummy/SugoiManagerRx7SeriesDummy.vhd" - ], - "SugoiManagerRxUltrascale": [ - "protocols/sugoi/rtl/UltraScale/SugoiManagerRxUltrascale.vhd", - "protocols/sugoi/rtl/dummy/SugoiManagerRxUltrascaleDummy.vhd" - ], - "TenGigEthGthUltraScale": [ - "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd", - "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd" - ], - "TenGigEthGthUltraScaleClk": [ - "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleClk.vhd", - "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleClk.vhd" - ], - "TenGigEthGthUltraScaleRst": [ - "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleRst.vhd", - "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleRst.vhd" - ], - "TenGigEthGthUltraScaleWrapper": [ - "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd", - "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd" - ], - "TrueDualPortRamXpm": [ - "base/ram/dummy/TrueDualPortRamXpmDummy.vhd", - "base/ram/xilinx/TrueDualPortRamXpm.vhd" - ], - "UdpDebugBridge": [ - "xilinx/xvc-udp/dcp/7Series/Impl/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/7Series/Stub/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/UltraScale/Impl/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/UltraScale/Stub/images/UdpDebugBridge_stub.vhd", - "xilinx/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd", - "xilinx/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd" - ], - "UdpDebugBridgeWrapper": [ - "xilinx/xvc-udp/dcp/core/UdpDebugBridgeWrapper.vhd", - "xilinx/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd" - ], - "XauiGthUltraScale": [ - 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"i2cmst", - "paths": [ - "protocols/i2c/rtl/orig/i2cmst.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "i2c_master_byte_ctrl" - ], - "instantiated_by": [ - "i2cmst_gen" - ], - "instantiates_count": 1, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "i2cmst_gen", - "paths": [ - "protocols/i2c/rtl/orig/i2cmst_gen.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "i2cmst" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "i2cslv", - "paths": [ - "protocols/i2c/rtl/orig/i2cslv.vhd" - ], - "subsystem": "protocols", - "instantiates": [], - "instantiated_by": [], - "instantiates_count": 0, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "iq16bTo32b", - "paths": [ - "protocols/jesd204b/rtl/iq16bTo32b.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "Fifo" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "iq32bTo16b", - "paths": [ - "protocols/jesd204b/rtl/iq32bTo16b.vhd" - ], - "subsystem": "protocols", - "instantiates": [ - "Fifo" - ], - "instantiated_by": [], - "instantiates_count": 1, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "sfixedDelay", - "paths": [ - "dsp/xilinx/fixed/SfixedDelay.vhd" - ], - "subsystem": "dsp", - "instantiates": [ - "SlvFixedDelay" - ], - "instantiated_by": [ - "FirAverage", - "IirSimple" - ], - "instantiates_count": 1, - "instantiated_by_count": 2, - "topological_layer": 1 - }, - { - "entity": "sfixedMult", - "paths": [ - "dsp/xilinx/fixed/SfixedMult.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [ - "SinCosTaylor" - ], - "instantiates_count": 0, - "instantiated_by_count": 1, - "topological_layer": 1 - }, - { - "entity": "sfixedMultAdd", - "paths": [ - "dsp/xilinx/fixed/SfixedMultAdd.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [], - "instantiates_count": 0, - "instantiated_by_count": 0, - "topological_layer": 0 - }, - { - "entity": "sfixedPreAddMultAdd", - "paths": [ - "dsp/xilinx/fixed/SfixedPreAddMultAdd.vhd" - ], - "subsystem": "dsp", - "instantiates": [], - "instantiated_by": [], - "instantiates_count": 0, - "instantiated_by_count": 0, - "topological_layer": 0 - } - ] -} diff --git a/docs/_meta/rtl_instantiation_graph.md b/docs/_meta/rtl_instantiation_graph.md deleted file mode 100644 index 33b4e08d81..0000000000 --- a/docs/_meta/rtl_instantiation_graph.md +++ /dev/null @@ -1,270 +0,0 @@ -# SURF RTL Instantiation Graph - -## Scope -- Scan dirs: `base, axi, dsp, protocols, ethernet, devices, xilinx` -- Included files: VHDL files outside `tb/`, `build/`, and `.venv/` paths. -- Direct entity instantiations are parsed explicitly. -- Component-style instantiations are included only when the instantiated token matches a known entity name inside an architecture body. -- Packages are not graph nodes. - -## Summary -- Entities: `795` -- Edges: `1584` -- Topological layers: `12` -- Duplicate entity names: `51` - -## Top Instantiated Entities -| entity | instantiated_by_count | instantiates_count | path | -| --- | --- | --- | --- | -| RstSync | 75 | 1 | base/sync/rtl/RstSync.vhd | -| Synchronizer | 73 | 0 | base/sync/rtl/Synchronizer.vhd | -| AxiStreamFifoV2 | 41 | 5 | axi/axi-stream/rtl/AxiStreamFifoV2.vhd | -| SynchronizerVector | 41 | 0 | base/sync/rtl/SynchronizerVector.vhd | -| AxiStreamPipeline | 38 | 0 | axi/axi-stream/rtl/AxiStreamPipeline.vhd | -| MasterAxiStreamIpIntegrator | 37 | 1 | axi/axi-stream/ip_integrator/MasterAxiStreamIpIntegrator.vhd | -| SlaveAxiLiteIpIntegrator | 37 | 1 | axi/axi-lite/ip_integrator/SlaveAxiLiteIpIntegrator.vhd | -| SlaveAxiStreamIpIntegrator | 37 | 1 | axi/axi-stream/ip_integrator/SlaveAxiStreamIpIntegrator.vhd | -| SynchronizerFifo | 37 | 1 | base/sync/rtl/SynchronizerFifo.vhd | -| PwrUpRst | 36 | 1 | base/general/rtl/PwrUpRst.vhd | -| AxiLiteCrossbar | 32 | 0 | axi/axi-lite/rtl/AxiLiteCrossbar.vhd | -| AxiLiteToDrp | 28 | 1 | axi/bridge/rtl/AxiLiteToDrp.vhd | -| SynchronizerOneShot | 28 | 2 | base/sync/rtl/SynchronizerOneShot.vhd | -| AxiLiteAsync | 23 | 1 | axi/axi-lite/rtl/AxiLiteAsync.vhd | -| Fifo | 18 | 4 | base/fifo/rtl/Fifo.vhd | -| MasterAxiIpIntegrator | 16 | 1 | axi/axi4/ip_integrator/MasterAxiIpIntegrator.vhd | -| SyncStatusVector | 16 | 2 | base/sync/rtl/SyncStatusVector.vhd | -| SynchronizerEdge | 16 | 1 | base/sync/rtl/SynchronizerEdge.vhd | -| RstPipeline | 15 | 0 | base/general/rtl/RstPipeline.vhd | -| AxiLiteMaster | 14 | 0 | axi/axi-lite/rtl/AxiLiteMaster.vhd | - -## Top Assemblers -| entity | instantiates_count | instantiated_by_count | path | -| --- | --- | --- | --- | -| RssiCore | 13 | 1 | protocols/rssi/v1/rtl/RssiCore.vhd | -| EthMacRxRoCEv2 | 10 | 1 | ethernet/RoCEv2/rtl/EthMacRxRoCEv2.vhd | -| SugoiManagerCore | 10 | 0 | protocols/sugoi/rtl/SugoiManagerCore.vhd | -| Ad9681Readout | 8 | 0 | devices/AnalogDevices/ad9681/7Series/rtl/Ad9681Readout.vhd | -| CoaXPressAxiL | 8 | 1 | protocols/coaxpress/core/rtl/CoaXPressAxiL.vhd | -| EthMacTxRoCEv2 | 8 | 1 | ethernet/RoCEv2/rtl/EthMacTxRoCEv2.vhd | -| Gth7Core | 8 | 2 | xilinx/7Series/gth7/rtl/Gth7Core.vhd | -| RssiCoreWrapper | 8 | 0 | protocols/rssi/v1/rtl/RssiCoreWrapper.vhd | -| Ad9249ReadoutGroup | 7 | 0 | devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd | -| Ad9249ReadoutGroup2 | 7 | 0 | devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd | -| AxiRingBuffer | 7 | 1 | axi/axi4/rtl/AxiRingBuffer.vhd | -| AxiStreamRingBuffer | 7 | 1 | axi/axi-stream/rtl/AxiStreamRingBuffer.vhd | -| ClinkTop | 7 | 0 | protocols/clink/rtl/ClinkTop.vhd | -| CoaXPressRx | 7 | 1 | protocols/coaxpress/core/rtl/CoaXPressRx.vhd | -| FifoAsync | 7 | 8 | base/fifo/rtl/inferred/FifoAsync.vhd | -| GLinkGtx7Core | 7 | 1 | protocols/glink/gtx7/rtl/GLinkGtx7Core.vhd | -| Gtp7Core | 7 | 4 | xilinx/7Series/gtp7/rtl/Gtp7Core.vhd | -| IpV4Engine | 7 | 1 | ethernet/IpV4Engine/rtl/IpV4Engine.vhd | -| Jesd204bRx | 7 | 1 | protocols/jesd204b/rtl/Jesd204bRx.vhd | -| Jesd204bTx | 7 | 1 | protocols/jesd204b/rtl/Jesd204bTx.vhd | - -## Top Leaf Entities -| entity | instantiated_by_count | path | -| --- | --- | --- | -| Synchronizer | 73 | base/sync/rtl/Synchronizer.vhd | -| SynchronizerVector | 41 | base/sync/rtl/SynchronizerVector.vhd | -| AxiStreamPipeline | 38 | axi/axi-stream/rtl/AxiStreamPipeline.vhd | -| AxiLiteCrossbar | 32 | axi/axi-lite/rtl/AxiLiteCrossbar.vhd | -| RstPipeline | 15 | base/general/rtl/RstPipeline.vhd | -| AxiLiteMaster | 14 | axi/axi-lite/rtl/AxiLiteMaster.vhd | -| IoBufWrapper | 14 | xilinx/dummy/IoBufWrapperDummy.vhd | -| Decoder8b10b | 10 | protocols/line-codes/rtl/Decoder8b10b.vhd | -| SimpleDualPortRam | 10 | base/ram/inferred/SimpleDualPortRam.vhd | -| FifoOutputPipeline | 9 | base/fifo/rtl/FifoOutputPipeline.vhd | -| Crc32Parallel | 7 | base/crc/rtl/Crc32Parallel.vhd | -| SimpleDualPortRamXpm | 7 | base/ram/dummy/SimpleDualPortRamXpmDummy.vhd | -| SpiMaster | 7 | protocols/spi/rtl/SpiMaster.vhd | -| Gearbox | 6 | base/general/rtl/Gearbox.vhd | -| SelectIoRxGearboxAligner | 6 | xilinx/general/rtl/SelectIoRxGearboxAligner.vhd | -| ClkOutBufDiff | 5 | xilinx/dummy/ClkOutBufDiffDummy.vhd | -| Pgp3RxGearboxAligner | 5 | protocols/pgp/pgp3/core/rtl/Pgp3RxGearboxAligner.vhd | -| Scrambler | 5 | base/general/rtl/Scrambler.vhd | -| AxiStreamFlush | 4 | axi/axi-stream/rtl/AxiStreamFlush.vhd | -| CRC32Rtl | 4 | base/crc/rtl/CRC32Rtl.vhd | - -## Base Bottom-Up Candidates -| entity | instantiated_by_count | instantiates_count | path | -| --- | --- | --- | --- | -| Synchronizer | 73 | 0 | base/sync/rtl/Synchronizer.vhd | -| SynchronizerVector | 41 | 0 | base/sync/rtl/SynchronizerVector.vhd | -| RstPipeline | 15 | 0 | base/general/rtl/RstPipeline.vhd | -| SimpleDualPortRam | 10 | 0 | base/ram/inferred/SimpleDualPortRam.vhd | -| FifoOutputPipeline | 9 | 0 | base/fifo/rtl/FifoOutputPipeline.vhd | -| Crc32Parallel | 7 | 0 | base/crc/rtl/Crc32Parallel.vhd | -| SimpleDualPortRamXpm | 7 | 0 | base/ram/dummy/SimpleDualPortRamXpmDummy.vhd | -| Gearbox | 6 | 0 | base/general/rtl/Gearbox.vhd | -| Scrambler | 5 | 0 | base/general/rtl/Scrambler.vhd | -| CRC32Rtl | 4 | 0 | base/crc/rtl/CRC32Rtl.vhd | -| Crc32 | 3 | 0 | base/crc/rtl/Crc32.vhd | -| SimpleDualPortRamAlteraMf | 3 | 0 | base/ram/dummy/SimpleDualPortRamAlteraMfDummy.vhd | -| SlvDelay | 3 | 0 | base/delay/rtl/SlvDelay.vhd | -| TrueDualPortRam | 3 | 0 | base/ram/inferred/TrueDualPortRam.vhd | -| FifoRdFsm | 2 | 0 | base/fifo/rtl/inferred/FifoRdFsm.vhd | -| FifoWrFsm | 2 | 0 | base/fifo/rtl/inferred/FifoWrFsm.vhd | -| LutRam | 2 | 0 | base/ram/inferred/LutRam.vhd | -| TrueDualPortRamAlteraMf | 2 | 0 | base/ram/dummy/TrueDualPortRamXpmAlteraMfDummy.vhd | -| TrueDualPortRamXpm | 2 | 0 | base/ram/dummy/TrueDualPortRamXpmDummy.vhd | -| Arbiter | 1 | 0 | base/general/rtl/Arbiter.vhd | - -## Duplicate Entity Names -- `Ad9249Deserializer` - - `devices/AnalogDevices/ad9249/7Series/rtl/Ad9249Deserializer.vhd` - - `devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd` -- `Ad9249ReadoutGroup` - - `devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd` - - `devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd` -- `ClinkDataClk` - - `protocols/clink/7Series/ClinkDataClk.vhd` - - `protocols/clink/UltraScale/ClinkDataClk.vhd` -- `ClinkDataShift` - - `protocols/clink/7Series/ClinkDataShift.vhd` - - `protocols/clink/UltraScale/ClinkDataShift.vhd` -- `ClkOutBufDiff` - - `xilinx/dummy/ClkOutBufDiffDummy.vhd` - - `xilinx/general/rtl/ClkOutBufDiff.vhd` -- `ClkOutBufSingle` - - `xilinx/dummy/ClkOutBufSingleDummy.vhd` - - `xilinx/general/rtl/ClkOutBufSingle.vhd` -- `ClockManagerUltraScale` - - `xilinx/UltraScale/clocking/rtl/ClockManagerUltraScale.vhd` - - `xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd` -- `CoaXPressOverFiberGthUsIpWrapper` - - `protocols/coaxpress/gthUs/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd` - - `protocols/coaxpress/gthUs+/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd` -- `CoaxpressOverFiberGthUs` - - `protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUs.vhd` - - `protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUs.vhd` -- `CoaxpressOverFiberGthUsQpll` - - `protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUsQpll.vhd` - - `protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUsQpll.vhd` -- `DS2411Core` - - `devices/Maxim/dummy/DS2411CoreDummy.vhd` - - `devices/Maxim/rtl/DS2411Core.vhd` -- `DeviceDna` - - `xilinx/dummy/DeviceDnaDummy.vhd` - - `xilinx/general/rtl/DeviceDna.vhd` -- `FifoAlteraMf` - - `base/fifo/rtl/altera/FifoAlteraMf.vhd` - - `base/fifo/rtl/dummy/FifoAlteraMfDummy.vhd` -- `FifoXpm` - - `base/fifo/rtl/dummy/FifoXpmDummy.vhd` - - `base/fifo/rtl/xilinx/FifoXpm.vhd` -- `GigEthGthUltraScale` - - `ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd` - - `ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd` -- `GigEthGthUltraScaleWrapper` - - `ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd` - - `ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd` -- `GthUltraScaleQuadPll` - - `xilinx/UltraScale/gthUs/rtl/GthUltraScaleQuadPll.vhd` - - `xilinx/UltraScale+/gthUs+/rtl/GthUltraScaleQuadPll.vhd` -- `Idelaye3Wrapper` - - `xilinx/7Series/dummy/Idelaye3WrapperDummy.vhd` - - `xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd` -- `InputBufferReg` - - `xilinx/7Series/general/rtl/InputBufferReg.vhd` - - `xilinx/UltraScale/general/rtl/InputBufferReg.vhd` -- `IoBufWrapper` - - `xilinx/dummy/IoBufWrapperDummy.vhd` - - `xilinx/general/rtl/IoBufWrapper.vhd` -- `Iprog` - - `xilinx/dummy/IprogDummy.vhd` - - `xilinx/general/rtl/Iprog.vhd` -- `MicroblazeBasicCoreWrapper` - - `xilinx/general/microblaze/bypass/MicroblazeBasicCoreWrapper.vhd` - - `xilinx/general/microblaze/generate/MicroblazeBasicCoreWrapper.vhd` -- `Odelaye3Wrapper` - - `xilinx/7Series/dummy/Odelaye3WrapperDummy.vhd` - - `xilinx/UltraScale/general/rtl/Odelaye3Wrapper.vhd` -- `OutputBufferReg` - - `xilinx/7Series/general/rtl/OutputBufferReg.vhd` - - `xilinx/UltraScale/general/rtl/OutputBufferReg.vhd` - - `xilinx/dummy/OutputBufferRegDummy.vhd` -- `Pgp2bGthUltra` - - `protocols/pgp/pgp2b/gthUltraScale/rtl/Pgp2bGthUltra.vhd` - - `protocols/pgp/pgp2b/gthUltraScale+/rtl/Pgp2bGthUltra.vhd` -- `Pgp3GthUs` - - `protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUs.vhd` - - `protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUs.vhd` -- `Pgp3GthUsIpWrapper` - - `protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd` - - `protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsIpWrapper.vhd` -- `Pgp3GthUsQpll` - - `protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd` - - `protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsQpll.vhd` -- `Pgp3GthUsWrapper` - - `protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsWrapper.vhd` - - `protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsWrapper.vhd` -- `Pgp4GthUs` - - `protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUs.vhd` - - `protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUs.vhd` -- `Pgp4GthUsWrapper` - - `protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUsWrapper.vhd` - - `protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUsWrapper.vhd` -- `PgpGthCoreWrapper` - - `protocols/pgp/pgp2b/gthUltraScale/rtl/PgpGthCoreWrapper.vhd` - - `protocols/pgp/pgp2b/gthUltraScale+/rtl/PgpGthCoreWrapper.vhd` -- `RogueSideBand` - - `axi/simlink/ghdl/RogueSideBand.vhd` - - `axi/simlink/sim/RogueSideBand.vhd` -- `RogueTcpMemory` - - `axi/simlink/ghdl/RogueTcpMemory.vhd` - - `axi/simlink/sim/RogueTcpMemory.vhd` -- `RogueTcpStream` - - `axi/simlink/ghdl/RogueTcpStream.vhd` - - `axi/simlink/sim/RogueTcpStream.vhd` -- `SaltRxDeser` - - `protocols/salt/rtl/7Series/SaltRxDeser.vhd` - - `protocols/salt/rtl/UltraScale/SaltRxDeser.vhd` -- `SaltTxSer` - - `protocols/salt/rtl/7Series/SaltTxSer.vhd` - - `protocols/salt/rtl/UltraScale/SaltTxSer.vhd` -- `SimpleDualPortRamXpm` - - `base/ram/dummy/SimpleDualPortRamXpmDummy.vhd` - - `base/ram/xilinx/SimpleDualPortRamXpm.vhd` -- `SinglePortRamPrimitive` - - `base/ram/dummy/SinglePortRamPrimitiveDummy.vhd` - - `base/ram/xilinx/SinglePortRamPrimitive.vhd` -- `Srl16Delay` - - `xilinx/dummy/Srl16DelayDummy.vhd` - - `xilinx/general/rtl/Srl16Delay.vhd` -- `SugoiManagerRx7Series` - - `protocols/sugoi/rtl/7Series/SugoiManagerRx7Series.vhd` - - `protocols/sugoi/rtl/dummy/SugoiManagerRx7SeriesDummy.vhd` -- `SugoiManagerRxUltrascale` - - `protocols/sugoi/rtl/UltraScale/SugoiManagerRxUltrascale.vhd` - - `protocols/sugoi/rtl/dummy/SugoiManagerRxUltrascaleDummy.vhd` -- `TenGigEthGthUltraScale` - - `ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd` - - `ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd` -- `TenGigEthGthUltraScaleClk` - - `ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleClk.vhd` - - `ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleClk.vhd` -- `TenGigEthGthUltraScaleRst` - - `ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleRst.vhd` - - `ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleRst.vhd` -- `TenGigEthGthUltraScaleWrapper` - - `ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd` - - `ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd` -- `TrueDualPortRamXpm` - - `base/ram/dummy/TrueDualPortRamXpmDummy.vhd` - - `base/ram/xilinx/TrueDualPortRamXpm.vhd` -- `UdpDebugBridge` - - `xilinx/xvc-udp/dcp/7Series/Impl/images/UdpDebugBridge_stub.vhd` - - `xilinx/xvc-udp/dcp/7Series/Stub/images/UdpDebugBridge_stub.vhd` - - `xilinx/xvc-udp/dcp/UltraScale/Impl/images/UdpDebugBridge_stub.vhd` - - `xilinx/xvc-udp/dcp/UltraScale/Stub/images/UdpDebugBridge_stub.vhd` - - `xilinx/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd` - - `xilinx/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd` -- `UdpDebugBridgeWrapper` - - `xilinx/xvc-udp/dcp/core/UdpDebugBridgeWrapper.vhd` - - `xilinx/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd` -- `XauiGthUltraScale` - - `ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd` - - `ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd` -- `XauiGthUltraScaleWrapper` - - `ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd` - - `ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd` diff --git a/docs/_meta/rtl_phase1_queue.json b/docs/_meta/rtl_phase1_queue.json deleted file mode 100644 index a77d778b6b..0000000000 --- a/docs/_meta/rtl_phase1_queue.json +++ /dev/null @@ -1,5874 +0,0 @@ -{ - "generated_from": { - "scan_dirs": [ - "base", - "axi", - "dsp", - "protocols", - "ethernet", - "devices", - "xilinx" - ], - "source_graph_script": "scripts/build_rtl_instantiation_graph.py", - "override_file": "docs/_meta/rtl_phase1_queue_overrides.json", - "queue_policy": "Path-qualified, phase-1 filtered, bottom-up instantiation order" - }, - "summary": { - "phase1_module_count": 219, - "phase1_edge_count": 392, - "phase1_bottom_up_layers": 10, - "deferred_module_count": 632, - "unresolved_phase1_edges": 0, - "applied_order_overrides": 0 - }, - "phase1_rules": { - "force_include_entities": [], - "force_include_paths": [], - "deferred_subsystems": [ - { - "name": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "name": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "name": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "name": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - } - ], - "deferred_entities": [ - { - "entity": "LutFixedDelay", - "reason": "Depends on SinglePortRamPrimitive under the current open-source flow." - } - ], - "deferred_paths": [], - "deferred_path_substrings": [ - { - "pattern": "axi/simlink/", - "reason": "Simulation support models are not part of the synthesizable phase-1 queue." - }, - { - "pattern": "/sim/", - "reason": "Simulation-only support modules are not part of the synthesizable phase-1 queue." - }, - { - "pattern": "/dummy/", - "reason": "Dummy-backed variants are deferred from the phase-1 executable queue." - }, - { - "pattern": "/altera/", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "/xilinx/", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "7Series", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "UltraScale", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "UltraScale+", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "/gth", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gtp", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gty", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gtx", - "reason": "GT-family implementation branches are deferred in phase 1." - } - ], - "preferred_paths_by_entity": {}, - "order_overrides": [] - }, - "applied_order_overrides": [], - "queue": [ - { - "order": 1, - "bottom_up_layer": 0, - "entity": "AxiLiteCrossbar", - "path": "axi/axi-lite/rtl/AxiLiteCrossbar.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 3 - }, - { - "order": 2, - "bottom_up_layer": 0, - "entity": "AxiLiteMaster", - "path": "axi/axi-lite/rtl/AxiLiteMaster.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 6 - }, - { - "order": 3, - "bottom_up_layer": 0, - "entity": "AxiLiteRegs", - "path": "axi/axi-lite/rtl/AxiLiteRegs.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 4, - "bottom_up_layer": 0, - "entity": "AxiLiteRespTimer", - "path": "axi/axi-lite/rtl/AxiLiteRespTimer.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 5, - "bottom_up_layer": 0, - "entity": "AxiLiteSlave", - "path": "axi/axi-lite/rtl/AxiLiteSlave.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 6, - "bottom_up_layer": 0, - "entity": "AxiLiteWriteFilter", - "path": "axi/axi-lite/rtl/AxiLiteWriteFilter.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 7, - "bottom_up_layer": 0, - "entity": "AxiVersion", - "path": "axi/axi-lite/rtl/AxiVersion.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 8, - "bottom_up_layer": 0, - "entity": "AxiStreamCombiner", - "path": "axi/axi-stream/rtl/AxiStreamCombiner.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 9, - "bottom_up_layer": 0, - "entity": "AxiStreamFlush", - "path": "axi/axi-stream/rtl/AxiStreamFlush.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 10, - "bottom_up_layer": 0, - "entity": "AxiStreamGearboxPack", - "path": "axi/axi-stream/rtl/AxiStreamGearboxPack.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 11, - "bottom_up_layer": 0, - "entity": "AxiStreamGearboxUnpack", - "path": "axi/axi-stream/rtl/AxiStreamGearboxUnpack.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 12, - "bottom_up_layer": 0, - "entity": "AxiStreamPipeline", - "path": "axi/axi-stream/rtl/AxiStreamPipeline.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 18 - }, - { - "order": 13, - "bottom_up_layer": 0, - "entity": "AxiStreamSplitter", - "path": "axi/axi-stream/rtl/AxiStreamSplitter.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 14, - "bottom_up_layer": 0, - "entity": "AxiStreamPkgWrapper", - "path": "axi/axi-stream/wrappers/AxiStreamPkgWrapper.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 15, - "bottom_up_layer": 0, - "entity": "AxiReadPathMux", - "path": "axi/axi4/rtl/AxiReadPathMux.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 16, - "bottom_up_layer": 0, - "entity": "AxiResize", - "path": "axi/axi4/rtl/AxiResize.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 17, - "bottom_up_layer": 0, - "entity": "AxiWritePathMux", - "path": "axi/axi4/rtl/AxiWritePathMux.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 18, - "bottom_up_layer": 0, - "entity": "AxiToAxiLite", - "path": "axi/bridge/rtl/AxiToAxiLite.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 19, - "bottom_up_layer": 0, - "entity": "AxiStreamDmaV2WriteMux", - "path": "axi/dma/rtl/v2/AxiStreamDmaV2WriteMux.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 20, - "bottom_up_layer": 0, - "entity": "CRC32Rtl", - "path": "base/crc/rtl/CRC32Rtl.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 21, - "bottom_up_layer": 0, - "entity": "Crc32", - "path": "base/crc/rtl/Crc32.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 22, - "bottom_up_layer": 0, - "entity": "Crc32Parallel", - "path": "base/crc/rtl/Crc32Parallel.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 23, - "bottom_up_layer": 0, - "entity": "SlvDelay", - "path": "base/delay/rtl/SlvDelay.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 24, - "bottom_up_layer": 0, - "entity": "SlvDelayRam", - "path": "base/delay/rtl/SlvDelayRam.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 25, - "bottom_up_layer": 0, - "entity": "SlvFixedDelay", - "path": "base/delay/rtl/SlvFixedDelay.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 26, - "bottom_up_layer": 0, - "entity": "FifoOutputPipeline", - "path": "base/fifo/rtl/FifoOutputPipeline.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 7 - }, - { - "order": 27, - "bottom_up_layer": 0, - "entity": "FifoRdFsm", - "path": "base/fifo/rtl/inferred/FifoRdFsm.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 28, - "bottom_up_layer": 0, - "entity": "FifoWrFsm", - "path": "base/fifo/rtl/inferred/FifoWrFsm.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 29, - "bottom_up_layer": 0, - "entity": "MasterRamIpIntegrator", - "path": "base/general/ip_integrator/MasterRamIpIntegrator.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 30, - "bottom_up_layer": 0, - "entity": "SlaveRamIpIntegrator", - "path": "base/general/ip_integrator/SlaveRamIpIntegrator.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 31, - "bottom_up_layer": 0, - "entity": "Arbiter", - "path": "base/general/rtl/Arbiter.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 32, - "bottom_up_layer": 0, - "entity": "ClockDivider", - "path": "base/general/rtl/ClockDivider.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 33, - "bottom_up_layer": 0, - "entity": "Gearbox", - "path": "base/general/rtl/Gearbox.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 34, - "bottom_up_layer": 0, - "entity": "Heartbeat", - "path": "base/general/rtl/Heartbeat.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 35, - "bottom_up_layer": 0, - "entity": "Mux", - "path": "base/general/rtl/Mux.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 36, - "bottom_up_layer": 0, - "entity": "OneShot", - "path": "base/general/rtl/OneShot.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 37, - "bottom_up_layer": 0, - "entity": "RegisterVector", - "path": "base/general/rtl/RegisterVector.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 38, - "bottom_up_layer": 0, - "entity": "RstPipeline", - "path": "base/general/rtl/RstPipeline.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 3 - }, - { - "order": 39, - "bottom_up_layer": 0, - "entity": "Scrambler", - "path": "base/general/rtl/Scrambler.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 40, - "bottom_up_layer": 0, - "entity": "LutRam", - "path": "base/ram/inferred/LutRam.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 41, - "bottom_up_layer": 0, - "entity": "SimpleDualPortRam", - "path": "base/ram/inferred/SimpleDualPortRam.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 6 - }, - { - "order": 42, - "bottom_up_layer": 0, - "entity": "TrueDualPortRam", - "path": "base/ram/inferred/TrueDualPortRam.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 3 - }, - { - "order": 43, - "bottom_up_layer": 0, - "entity": "Synchronizer", - "path": "base/sync/rtl/Synchronizer.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 13 - }, - { - "order": 44, - "bottom_up_layer": 0, - "entity": "SynchronizerVector", - "path": "base/sync/rtl/SynchronizerVector.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 7 - }, - { - "order": 45, - "bottom_up_layer": 0, - "entity": "FirFilterTap", - "path": "dsp/generic/fixed/FirFilterTap.vhd", - "subsystem": "dsp", - "instantiates_in_phase1_count": 0, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 46, - "bottom_up_layer": 1, - "entity": "AxiLiteMasterProxy", - "path": "axi/axi-lite/rtl/AxiLiteMasterProxy.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 47, - "bottom_up_layer": 1, - "entity": "AxiLiteSequencerRam", - "path": "axi/axi-lite/rtl/AxiLiteSequencerRam.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 48, - "bottom_up_layer": 1, - "entity": "AxiStreamCompact", - "path": "axi/axi-stream/rtl/AxiStreamCompact.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 49, - "bottom_up_layer": 1, - "entity": "AxiStreamConcat", - "path": "axi/axi-stream/rtl/AxiStreamConcat.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 50, - "bottom_up_layer": 1, - "entity": "AxiStreamDeMux", - "path": "axi/axi-stream/rtl/AxiStreamDeMux.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 51, - "bottom_up_layer": 1, - "entity": "AxiStreamFrameRateLimiter", - "path": "axi/axi-stream/rtl/AxiStreamFrameRateLimiter.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 4, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 52, - "bottom_up_layer": 1, - "entity": "AxiStreamMux", - "path": "axi/axi-stream/rtl/AxiStreamMux.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 53, - "bottom_up_layer": 1, - "entity": "AxiStreamRepeater", - "path": "axi/axi-stream/rtl/AxiStreamRepeater.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 54, - "bottom_up_layer": 1, - "entity": "AxiStreamResize", - "path": "axi/axi-stream/rtl/AxiStreamResize.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 55, - "bottom_up_layer": 1, - "entity": "AxiStreamShift", - "path": "axi/axi-stream/rtl/AxiStreamShift.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 3 - }, - { - "order": 56, - "bottom_up_layer": 1, - "entity": "AxiStreamTrailerAppend", - "path": "axi/axi-stream/rtl/AxiStreamTrailerAppend.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 57, - "bottom_up_layer": 1, - "entity": "AxiStreamTrailerRemove", - "path": "axi/axi-stream/rtl/AxiStreamTrailerRemove.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 58, - "bottom_up_layer": 1, - "entity": "AxiRam", - "path": "axi/axi4/rtl/AxiRam.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 59, - "bottom_up_layer": 1, - "entity": "AxiLiteToIpBus", - "path": "axi/bridge/rtl/AxiLiteToIpBus.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 60, - "bottom_up_layer": 1, - "entity": "IpBusToAxiLite", - "path": "axi/bridge/rtl/IpBusToAxiLite.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 61, - "bottom_up_layer": 1, - "entity": "AxiStreamDmaV2WriteMuxIpIntegrator", - "path": "axi/dma/ip_integrator/AxiStreamDmaV2WriteMuxIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 62, - "bottom_up_layer": 1, - "entity": "Crc32PolyWrapper", - "path": "base/crc/wrappers/Crc32PolyWrapper.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 63, - "bottom_up_layer": 1, - "entity": "FifoSync", - "path": "base/fifo/rtl/inferred/FifoSync.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 4, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 64, - "bottom_up_layer": 1, - "entity": "RstPipelineVector", - "path": "base/general/rtl/RstPipelineVector.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 65, - "bottom_up_layer": 1, - "entity": "WatchDogRst", - "path": "base/general/rtl/WatchDogRst.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 66, - "bottom_up_layer": 1, - "entity": "HeartbeatWrapper", - "path": "base/general/wrappers/HeartbeatWrapper.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 67, - "bottom_up_layer": 1, - "entity": "DualPortRam", - "path": "base/ram/inferred/DualPortRam.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 4 - }, - { - "order": 68, - "bottom_up_layer": 1, - "entity": "RstSync", - "path": "base/sync/rtl/RstSync.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 15 - }, - { - "order": 69, - "bottom_up_layer": 1, - "entity": "SynchronizerEdge", - "path": "base/sync/rtl/SynchronizerEdge.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 70, - "bottom_up_layer": 1, - "entity": "BoxcarIntegrator", - "path": "dsp/generic/fixed/BoxcarIntegrator.vhd", - "subsystem": "dsp", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 71, - "bottom_up_layer": 1, - "entity": "DspAddSub", - "path": "dsp/generic/fixed/DspAddSub.vhd", - "subsystem": "dsp", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 72, - "bottom_up_layer": 1, - "entity": "DspComparator", - "path": "dsp/generic/fixed/DspComparator.vhd", - "subsystem": "dsp", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 4 - }, - { - "order": 73, - "bottom_up_layer": 1, - "entity": "DspPreSubMult", - "path": "dsp/generic/fixed/DspPreSubMult.vhd", - "subsystem": "dsp", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 74, - "bottom_up_layer": 1, - "entity": "DspSquareDiffMult", - "path": "dsp/generic/fixed/DspSquareDiffMult.vhd", - "subsystem": "dsp", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 75, - "bottom_up_layer": 2, - "entity": "MasterAxiLiteIpIntegrator", - "path": "axi/axi-lite/ip_integrator/MasterAxiLiteIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 9 - }, - { - "order": 76, - "bottom_up_layer": 2, - "entity": "SlaveAxiLiteIpIntegrator", - "path": "axi/axi-lite/ip_integrator/SlaveAxiLiteIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 32 - }, - { - "order": 77, - "bottom_up_layer": 2, - "entity": "AxiLiteAsync", - "path": "axi/axi-lite/rtl/AxiLiteAsync.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 7 - }, - { - "order": 78, - "bottom_up_layer": 2, - "entity": "MasterAxiStreamIpIntegrator", - "path": "axi/axi-stream/ip_integrator/MasterAxiStreamIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 30 - }, - { - "order": 79, - "bottom_up_layer": 2, - "entity": "SlaveAxiStreamIpIntegrator", - "path": "axi/axi-stream/ip_integrator/SlaveAxiStreamIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 30 - }, - { - "order": 80, - "bottom_up_layer": 2, - "entity": "AxiStreamGearbox", - "path": "axi/axi-stream/rtl/AxiStreamGearbox.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 81, - "bottom_up_layer": 2, - "entity": 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"axi", - "instantiates_in_phase1_count": 4, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 153, - "bottom_up_layer": 4, - "entity": "SlvDelayFifo", - "path": "base/delay/rtl/SlvDelayFifo.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 154, - "bottom_up_layer": 4, - "entity": "FifoCascade", - "path": "base/fifo/rtl/FifoCascade.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 8 - }, - { - "order": 155, - "bottom_up_layer": 4, - "entity": "FwftCntWrapper", - "path": "base/fifo/wrappers/FwftCntWrapper.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 156, - "bottom_up_layer": 4, - "entity": "SyncClockFreq", - "path": "base/sync/rtl/SyncClockFreq.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 157, - "bottom_up_layer": 4, - "entity": "SyncMinMax", - "path": "base/sync/rtl/SyncMinMax.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 158, - "bottom_up_layer": 4, - "entity": "SynchronizerOneShotCnt", - "path": "base/sync/rtl/SynchronizerOneShotCnt.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 159, - "bottom_up_layer": 5, - "entity": "AxiDualPortRamIpIntegrator", - "path": "axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 160, - "bottom_up_layer": 5, - "entity": "AxiLiteCrossbarIpIntegrator", - "path": "axi/axi-lite/ip_integrator/AxiLiteCrossbarIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 161, - "bottom_up_layer": 5, - "entity": "AxiLiteRingBufferIpIntegrator", - "path": "axi/axi-lite/ip_integrator/AxiLiteRingBufferIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 162, - "bottom_up_layer": 5, - "entity": "AxiLiteFifoPop", - "path": "axi/axi-lite/rtl/AxiLiteFifoPop.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 163, - "bottom_up_layer": 5, - "entity": "AxiLiteFifoPush", - "path": "axi/axi-lite/rtl/AxiLiteFifoPush.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 164, - "bottom_up_layer": 5, - "entity": "AxiLiteFifoPushPop", - "path": "axi/axi-lite/rtl/AxiLiteFifoPushPop.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 165, - "bottom_up_layer": 5, - "entity": "AxiStreamScatterGatherIpIntegrator", - "path": "axi/axi-stream/ip_integrator/AxiStreamScatterGatherIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 4, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 166, - "bottom_up_layer": 5, - "entity": "AxiStreamFifoV2", - "path": "axi/axi-stream/rtl/AxiStreamFifoV2.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 5, - "instantiated_by_in_phase1_count": 7 - }, - { - "order": 167, - "bottom_up_layer": 5, - "entity": "AxiMemTesterIpIntegrator", - "path": "axi/axi4/ip_integrator/AxiMemTesterIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 168, - "bottom_up_layer": 5, - "entity": "AxiReadPathFifo", - "path": "axi/axi4/rtl/AxiReadPathFifo.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 3 - }, - { - "order": 169, - "bottom_up_layer": 5, - "entity": "AxiWritePathFifo", - "path": "axi/axi4/rtl/AxiWritePathFifo.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 3 - }, - { - "order": 170, - "bottom_up_layer": 5, - "entity": "SlvArraytoAxiLiteIpIntegrator", - "path": "axi/bridge/ip_integrator/SlvArraytoAxiLiteIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 171, - "bottom_up_layer": 5, - "entity": "AxiStreamDmaV2DescIpIntegrator", - "path": "axi/dma/ip_integrator/AxiStreamDmaV2DescIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 172, - "bottom_up_layer": 5, - "entity": "AxiStreamDmaV2FifoIpIntegrator", - "path": "axi/dma/ip_integrator/AxiStreamDmaV2FifoIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 5, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 173, - "bottom_up_layer": 5, - "entity": "AxiStreamDmaV2", - "path": "axi/dma/rtl/v2/AxiStreamDmaV2.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 5, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 174, - "bottom_up_layer": 5, - "entity": "FifoMux", - "path": "base/fifo/rtl/FifoMux.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 175, - "bottom_up_layer": 5, - "entity": "SyncTrigRate", - "path": "base/sync/rtl/SyncTrigRate.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 3 - }, - { - "order": 176, - "bottom_up_layer": 5, - "entity": "SynchronizerOneShotCntVector", - "path": "base/sync/rtl/SynchronizerOneShotCntVector.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 4, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 177, - "bottom_up_layer": 5, - "entity": "SyncClockFreqWrapper", - "path": "base/sync/wrappers/SyncClockFreqWrapper.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 178, - "bottom_up_layer": 5, - "entity": "FirFilterMultiChannel", - "path": "dsp/generic/fixed/FirFilterMultiChannel.vhd", - "subsystem": "dsp", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 179, - "bottom_up_layer": 6, - "entity": "AxiLiteFifoPopIpIntegrator", - "path": "axi/axi-lite/ip_integrator/AxiLiteFifoPopIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 180, - "bottom_up_layer": 6, - "entity": "AxiLiteFifoPushIpIntegrator", - "path": "axi/axi-lite/ip_integrator/AxiLiteFifoPushIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 181, - "bottom_up_layer": 6, - "entity": "AxiLiteFifoPushPopIpIntegrator", - "path": "axi/axi-lite/ip_integrator/AxiLiteFifoPushPopIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 182, - "bottom_up_layer": 6, - "entity": "AxiStreamFifoV2IpIntegrator", - "path": "axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 183, - "bottom_up_layer": 6, - "entity": "AxiStreamBatchingFifo", - "path": "axi/axi-stream/rtl/AxiStreamBatchingFifo.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 184, - "bottom_up_layer": 6, - "entity": "AxiStreamMon", - "path": "axi/axi-stream/rtl/AxiStreamMon.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 4, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 185, - "bottom_up_layer": 6, - "entity": "AxiStreamRingBuffer", - "path": "axi/axi-stream/rtl/AxiStreamRingBuffer.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 5, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 186, - "bottom_up_layer": 6, - "entity": "AxiReadPathFifoIpIntegrator", - "path": "axi/axi4/ip_integrator/AxiReadPathFifoIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 187, - "bottom_up_layer": 6, - "entity": "AxiWritePathFifoIpIntegrator", - "path": "axi/axi4/ip_integrator/AxiWritePathFifoIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 188, - "bottom_up_layer": 6, - "entity": "AxiReadEmulate", - "path": "axi/axi4/rtl/AxiReadEmulate.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 189, - "bottom_up_layer": 6, - "entity": "AxiRingBuffer", - "path": "axi/axi4/rtl/AxiRingBuffer.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 6, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 190, - "bottom_up_layer": 6, - "entity": "AxiWriteEmulate", - "path": "axi/axi4/rtl/AxiWriteEmulate.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 191, - "bottom_up_layer": 6, - "entity": "AxiStreamDmaV2IpIntegrator", - "path": "axi/dma/ip_integrator/AxiStreamDmaV2IpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 192, - "bottom_up_layer": 6, - "entity": "AxiStreamDmaRingRead", - "path": "axi/dma/rtl/v1/AxiStreamDmaRingRead.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 5, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 193, - "bottom_up_layer": 6, - "entity": "AxiStreamDmaWrite", - "path": "axi/dma/rtl/v1/AxiStreamDmaWrite.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 4 - }, - { - "order": 194, - "bottom_up_layer": 6, - "entity": "SyncStatusVector", - "path": "base/sync/rtl/SyncStatusVector.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 195, - "bottom_up_layer": 6, - "entity": "SyncTrigRateVector", - "path": "base/sync/rtl/SyncTrigRateVector.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 196, - "bottom_up_layer": 6, - "entity": "SyncTrigRateWrapper", - "path": "base/sync/wrappers/SyncTrigRateWrapper.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 197, - "bottom_up_layer": 6, - "entity": "SynchronizerOneShotCntVectorFlatWrapper", - "path": "base/sync/wrappers/SynchronizerOneShotCntVectorFlatWrapper.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 198, - "bottom_up_layer": 7, - "entity": "AxiLiteRamSyncStatusVector", - "path": "axi/axi-lite/rtl/AxiLiteRamSyncStatusVector.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 199, - "bottom_up_layer": 7, - "entity": "AxiStreamBatchingFifoIpIntegrator", - "path": "axi/axi-stream/ip_integrator/AxiStreamBatchingFifoIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 4, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 200, - "bottom_up_layer": 7, - "entity": "AxiStreamMonIpIntegrator", - "path": "axi/axi-stream/ip_integrator/AxiStreamMonIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 201, - "bottom_up_layer": 7, - "entity": "AxiStreamRingBufferIpIntegrator", - "path": "axi/axi-stream/ip_integrator/AxiStreamRingBufferIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 202, - "bottom_up_layer": 7, - "entity": "AxiStreamMonAxiL", - "path": "axi/axi-stream/rtl/AxiStreamMonAxiL.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 2 - }, - { - "order": 203, - "bottom_up_layer": 7, - "entity": "AxiReadEmulateIpIntegrator", - "path": "axi/axi4/ip_integrator/AxiReadEmulateIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 204, - "bottom_up_layer": 7, - "entity": "AxiRingBufferIpIntegrator", - "path": "axi/axi4/ip_integrator/AxiRingBufferIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 205, - "bottom_up_layer": 7, - "entity": "AxiWriteEmulateIpIntegrator", - "path": "axi/axi4/ip_integrator/AxiWriteEmulateIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 206, - "bottom_up_layer": 7, - "entity": "AxiStreamDmaRingReadIpIntegrator", - "path": "axi/dma/ip_integrator/AxiStreamDmaRingReadIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 5, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 207, - "bottom_up_layer": 7, - "entity": "AxiStreamDmaWriteIpIntegrator", - "path": "axi/dma/ip_integrator/AxiStreamDmaWriteIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 208, - "bottom_up_layer": 7, - "entity": "AxiStreamDma", - "path": "axi/dma/rtl/v1/AxiStreamDma.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 4, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 209, - "bottom_up_layer": 7, - "entity": "AxiStreamDmaFifo", - "path": "axi/dma/rtl/v1/AxiStreamDmaFifo.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 4, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 210, - "bottom_up_layer": 7, - "entity": "AxiStreamDmaRingWrite", - "path": "axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 4, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 211, - "bottom_up_layer": 7, - "entity": "SyncStatusVectorFlatWrapper", - "path": "base/sync/wrappers/SyncStatusVectorFlatWrapper.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 212, - "bottom_up_layer": 7, - "entity": "SyncTrigRateVectorFlatWrapper", - "path": "base/sync/wrappers/SyncTrigRateVectorFlatWrapper.vhd", - "subsystem": "base", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 213, - "bottom_up_layer": 8, - "entity": "AxiLiteRamSyncStatusVectorIpIntegrator", - "path": "axi/axi-lite/ip_integrator/AxiLiteRamSyncStatusVectorIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 214, - "bottom_up_layer": 8, - "entity": "AxiStreamMonAxiLIpIntegrator", - "path": "axi/axi-stream/ip_integrator/AxiStreamMonAxiLIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 3, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 215, - "bottom_up_layer": 8, - "entity": "AxiMonAxiL", - "path": "axi/axi4/rtl/AxiMonAxiL.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 1, - "instantiated_by_in_phase1_count": 1 - }, - { - "order": 216, - "bottom_up_layer": 8, - "entity": "AxiStreamDmaFifoIpIntegrator", - "path": "axi/dma/ip_integrator/AxiStreamDmaFifoIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 217, - "bottom_up_layer": 8, - "entity": "AxiStreamDmaIpIntegrator", - "path": "axi/dma/ip_integrator/AxiStreamDmaIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 218, - "bottom_up_layer": 8, - "entity": "AxiStreamDmaRingWriteIpIntegrator", - "path": "axi/dma/ip_integrator/AxiStreamDmaRingWriteIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 5, - "instantiated_by_in_phase1_count": 0 - }, - { - "order": 219, - "bottom_up_layer": 9, - "entity": "AxiMonAxiLIpIntegrator", - "path": "axi/axi4/ip_integrator/AxiMonAxiLIpIntegrator.vhd", - "subsystem": "axi", - "instantiates_in_phase1_count": 2, - "instantiated_by_in_phase1_count": 0 - } - ], - "deferred": [ - { - "entity": "RogueSideBand", - "path": "axi/simlink/ghdl/RogueSideBand.vhd", - "subsystem": "axi", - "reason": "Simulation support models are not part of the synthesizable phase-1 queue." - }, - { - "entity": "RogueTcpMemory", - "path": "axi/simlink/ghdl/RogueTcpMemory.vhd", - "subsystem": "axi", - "reason": "Simulation support models are not part of the synthesizable phase-1 queue." - }, - { - "entity": "RogueTcpStream", - "path": "axi/simlink/ghdl/RogueTcpStream.vhd", - "subsystem": "axi", - "reason": "Simulation support models are not part of the synthesizable phase-1 queue." - }, - { - "entity": "RogueSideBand", - "path": "axi/simlink/sim/RogueSideBand.vhd", - "subsystem": "axi", - "reason": "Simulation support models are not part of the synthesizable phase-1 queue." - }, - { - "entity": "RogueTcpMemory", - "path": "axi/simlink/sim/RogueTcpMemory.vhd", - "subsystem": "axi", - "reason": "Simulation support models are not part of the synthesizable phase-1 queue." - }, - { - "entity": "RogueTcpStream", - "path": "axi/simlink/sim/RogueTcpStream.vhd", - "subsystem": "axi", - "reason": "Simulation support models are not part of the synthesizable phase-1 queue." - }, - { - "entity": "LutFixedDelay", - "path": "base/delay/rtl/LutFixedDelay.vhd", - "subsystem": "base", - "reason": "Depends on SinglePortRamPrimitive under the current open-source flow." - }, - { - "entity": "FifoAlteraMf", - "path": "base/fifo/rtl/altera/FifoAlteraMf.vhd", - "subsystem": "base", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "FifoAlteraMf", - "path": "base/fifo/rtl/dummy/FifoAlteraMfDummy.vhd", - "subsystem": "base", - "reason": "Dummy-backed variants are deferred from the phase-1 executable queue." - }, - { - "entity": "FifoXpm", - "path": "base/fifo/rtl/dummy/FifoXpmDummy.vhd", - "subsystem": "base", - "reason": "Dummy-backed variants are deferred from the phase-1 executable queue." - }, - { - "entity": "FifoXpm", - "path": "base/fifo/rtl/xilinx/FifoXpm.vhd", - "subsystem": "base", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "SimpleDualPortRamAlteraMf", - "path": "base/ram/dummy/SimpleDualPortRamAlteraMfDummy.vhd", - "subsystem": "base", - "reason": "Dummy-backed variants are deferred from the phase-1 executable queue." - }, - { - "entity": "SimpleDualPortRamXpm", - "path": "base/ram/dummy/SimpleDualPortRamXpmDummy.vhd", - "subsystem": "base", - "reason": "Dummy-backed variants are deferred from the phase-1 executable queue." - }, - { - "entity": "SinglePortRamPrimitive", - "path": "base/ram/dummy/SinglePortRamPrimitiveDummy.vhd", - "subsystem": "base", - "reason": "Dummy-backed variants are deferred from the phase-1 executable queue." - }, - { - "entity": "TrueDualPortRamAlteraMf", - "path": "base/ram/dummy/TrueDualPortRamXpmAlteraMfDummy.vhd", - "subsystem": "base", - "reason": "Dummy-backed variants are deferred from the phase-1 executable queue." - }, - { - "entity": "TrueDualPortRamXpm", - "path": "base/ram/dummy/TrueDualPortRamXpmDummy.vhd", - "subsystem": "base", - "reason": "Dummy-backed variants are deferred from the phase-1 executable queue." - }, - { - "entity": "SimpleDualPortRamXpm", - "path": "base/ram/xilinx/SimpleDualPortRamXpm.vhd", - "subsystem": "base", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "SinglePortRamPrimitive", - "path": "base/ram/xilinx/SinglePortRamPrimitive.vhd", - "subsystem": "base", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "TrueDualPortRamXpm", - "path": "base/ram/xilinx/TrueDualPortRamXpm.vhd", - "subsystem": "base", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "LeapXcvr", - "path": "devices/Amphenol/LeapXcvr/rtl/LeapXcvr.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "LeapXcvrCdrDisable", - "path": "devices/Amphenol/LeapXcvr/rtl/LeapXcvrCdrDisable.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "LeapXcvrCore", - "path": "devices/Amphenol/LeapXcvr/rtl/LeapXcvrCore.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd5541Core", - "path": "devices/AnalogDevices/ad5541/rtl/AxiAd5541Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd5780Core", - "path": "devices/AnalogDevices/ad5780/rtl/AxiAd5780Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd5780Reg", - "path": "devices/AnalogDevices/ad5780/rtl/AxiAd5780Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd5780Ser", - "path": "devices/AnalogDevices/ad5780/rtl/AxiAd5780Ser.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249ConfigNoPullup", - "path": "devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ConfigNoPullup.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249Deserializer", - "path": "devices/AnalogDevices/ad9249/7Series/rtl/Ad9249Deserializer.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249ReadoutGroup", - "path": "devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249Deserializer", - "path": "devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249ReadoutGroup", - "path": "devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249ReadoutGroup2", - "path": "devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9249Config", - "path": "devices/AnalogDevices/ad9249/core/Ad9249Config.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "StreamPatternTester", - "path": "devices/AnalogDevices/ad9249/core/StreamPatternTester.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467Core", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467Deser", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467Deser.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467DeserBit", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467DeserBit.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467Mon", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467Mon.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467Pll", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467Pll.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467Reg", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAd9467Spi", - "path": "devices/AnalogDevices/ad9467/rtl/AxiAd9467Spi.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681Deserializer", - "path": "devices/AnalogDevices/ad9681/7Series/rtl/Ad9681Deserializer.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681Readout", - "path": "devices/AnalogDevices/ad9681/7Series/rtl/Ad9681Readout.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681ReadoutManual", - "path": "devices/AnalogDevices/ad9681/7Series/rtl/Ad9681ReadoutManual.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681Config", - "path": "devices/AnalogDevices/ad9681/core/Ad9681Config.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681", - "path": "devices/AnalogDevices/ad9681/sim/Ad9681.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Ad9681Serializer", - "path": "devices/AnalogDevices/ad9681/sim/Ad9681Serializer.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AdiConfigSlave", - "path": "devices/AnalogDevices/general/rtl/AdiConfigSlave.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiLtc2270Core", - "path": "devices/Linear/lct2270/rtl/AxiLtc2270Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiLtc2270Deser", - "path": "devices/Linear/lct2270/rtl/AxiLtc2270Deser.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiLtc2270DeserBit", - "path": "devices/Linear/lct2270/rtl/AxiLtc2270DeserBit.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiLtc2270Reg", - "path": "devices/Linear/lct2270/rtl/AxiLtc2270Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sgmii88E1111Mdio", - "path": "devices/Marvell/Sgmii88E1111/core/Sgmii88E1111Mdio.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sgmii88E1111LvdsUltraScale", - "path": "devices/Marvell/Sgmii88E1111/lvdsUltraScale/Sgmii88E1111LvdsUltraScale.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DS2411Core", - "path": "devices/Maxim/dummy/DS2411CoreDummy.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DS2411Core", - "path": "devices/Maxim/rtl/DS2411Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Max5443", - "path": "devices/Maxim/rtl/Max5443.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Max5443DacCntrl", - "path": "devices/Maxim/rtl/Max5443DacCntrl.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiSy56040Core", - "path": "devices/Microchip/sy56040/rtl/AxiSy56040Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiSy56040Reg", - "path": "devices/Microchip/sy56040/rtl/AxiSy56040Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sy89297", - "path": "devices/Microchip/sy89297/rtl/Sy89297.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronMt28ewCore", - "path": "devices/Micron/mt28ew/rtl/AxiMicronMt28ewCore.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronMt28ewReg", - "path": "devices/Micron/mt28ew/rtl/AxiMicronMt28ewReg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronN25QCore", - "path": "devices/Micron/n25q/rtl/AxiMicronN25QCore.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronN25QReg", - "path": "devices/Micron/n25q/rtl/AxiMicronN25QReg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronP30Core", - "path": "devices/Micron/p30/rtl/AxiMicronP30Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiMicronP30Reg", - "path": "devices/Micron/p30/rtl/AxiMicronP30Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sc18Is602", - "path": "devices/Nxp/Sc18Is602/rtl/Sc18Is602.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sc18Is602Core", - "path": "devices/Nxp/Sc18Is602/rtl/Sc18Is602Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Si5324", - "path": "devices/Silabs/si5324/rtl/Si5324.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Si5345", - "path": "devices/Silabs/si5345/rtl/Si5345.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Si5394I2c", - "path": "devices/Silabs/si5394/rtl/Si5394I2c.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Si5394I2cCore", - "path": "devices/Silabs/si5394/rtl/Si5394I2cCore.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Lmk048Base", - "path": "devices/Ti/Lmk048Base/rtl/Lmk048Base.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "adc32rf45", - "path": "devices/Ti/adc32rf45/rtl/adc32rf45.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAds42lb69Core", - "path": "devices/Ti/ads42lb69/rtl/AxiAds42lb69Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAds42lb69Deser", - "path": "devices/Ti/ads42lb69/rtl/AxiAds42lb69Deser.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAds42lb69DeserBit", - "path": "devices/Ti/ads42lb69/rtl/AxiAds42lb69DeserBit.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAds42lb69Pll", - "path": "devices/Ti/ads42lb69/rtl/AxiAds42lb69Pll.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiAds42lb69Reg", - "path": "devices/Ti/ads42lb69/rtl/AxiAds42lb69Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ads54j60", - "path": "devices/Ti/ads54j60/rtl/ads54j60.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiDac7654Core", - "path": "devices/Ti/dac7654/rtl/AxiDac7654Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiDac7654Reg", - "path": "devices/Ti/dac7654/rtl/AxiDac7654Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiDac7654Spi", - "path": "devices/Ti/dac7654/rtl/AxiDac7654Spi.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SgmiiDp83867Mdio", - "path": "devices/Ti/dp83867/core/SgmiiDp83867Mdio.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SgmiiDp83867LvdsUltraScale", - "path": "devices/Ti/dp83867/lvdsUltraScale/SgmiiDp83867LvdsUltraScale.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiXcf128Core", - "path": "devices/Xilinx/xcf128/rtl/AxiXcf128Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiXcf128Reg", - "path": "devices/Xilinx/xcf128/rtl/AxiXcf128Reg.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "QsfpCdrDisable", - "path": "devices/transceivers/rtl/QsfpCdrDisable.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sff8472", - "path": "devices/transceivers/rtl/Sff8472.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Sff8472Core", - "path": "devices/transceivers/rtl/Sff8472Core.vhd", - "subsystem": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "add3", - "path": "dsp/xilinx/fixed/Add3.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "CfixedAccumulator", - "path": "dsp/xilinx/fixed/CfixedAccumulator.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "cfixedDelay", - "path": "dsp/xilinx/fixed/CfixedDelay.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "cfixedMult", - "path": "dsp/xilinx/fixed/CfixedMult.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "cfixedMultAdd", - "path": "dsp/xilinx/fixed/CfixedMultAdd.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "CfixedPreAddMult", - "path": "dsp/xilinx/fixed/CfixedPreAddMult.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "csa3", - "path": "dsp/xilinx/fixed/Csa3.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "FirAverage", - "path": "dsp/xilinx/fixed/FirAverage.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "IirSimple", - "path": "dsp/xilinx/fixed/IirSimple.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "SfixedAccumulator", - "path": "dsp/xilinx/fixed/SfixedAccumulator.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "sfixedDelay", - "path": "dsp/xilinx/fixed/SfixedDelay.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "sfixedMult", - "path": "dsp/xilinx/fixed/SfixedMult.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "sfixedMultAdd", - "path": "dsp/xilinx/fixed/SfixedMultAdd.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "sfixedPreAddMultAdd", - "path": "dsp/xilinx/fixed/SfixedPreAddMultAdd.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "SinCosLut", - "path": "dsp/xilinx/fixed/SinCosLut.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "SinCosTaylor", - "path": "dsp/xilinx/fixed/SinCosTaylor.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "DspXor", - "path": "dsp/xilinx/logic/DspXor.vhd", - "subsystem": "dsp", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "entity": "Caui4GtyIpWrapper", - "path": "ethernet/Caui4Core/gtyUltraScale+/rtl/Caui4GtyIpWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthCrc32Parallel", - "path": "ethernet/EthMacCore/rtl/EthCrc32Parallel.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacFlowCtrl", - "path": "ethernet/EthMacCore/rtl/EthMacFlowCtrl.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRx", - "path": "ethernet/EthMacCore/rtl/EthMacRx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxBypass", - "path": "ethernet/EthMacCore/rtl/EthMacRxBypass.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxCsum", - "path": "ethernet/EthMacCore/rtl/EthMacRxCsum.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxFifo", - "path": "ethernet/EthMacCore/rtl/EthMacRxFifo.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxFilter", - "path": "ethernet/EthMacCore/rtl/EthMacRxFilter.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxImport", - "path": "ethernet/EthMacCore/rtl/EthMacRxImport.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxImportGmii", - "path": "ethernet/EthMacCore/rtl/EthMacRxImportGmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxImportXgmii", - "path": "ethernet/EthMacCore/rtl/EthMacRxImportXgmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxImportXlgmii", - "path": "ethernet/EthMacCore/rtl/EthMacRxImportXlgmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxPause", - "path": "ethernet/EthMacCore/rtl/EthMacRxPause.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxShift", - "path": "ethernet/EthMacCore/rtl/EthMacRxShift.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTop", - "path": "ethernet/EthMacCore/rtl/EthMacTop.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTx", - "path": "ethernet/EthMacCore/rtl/EthMacTx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxBypass", - "path": "ethernet/EthMacCore/rtl/EthMacTxBypass.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxCsum", - "path": "ethernet/EthMacCore/rtl/EthMacTxCsum.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxExport", - "path": "ethernet/EthMacCore/rtl/EthMacTxExport.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxExportGmii", - "path": "ethernet/EthMacCore/rtl/EthMacTxExportGmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxExportXgmii", - "path": "ethernet/EthMacCore/rtl/EthMacTxExportXgmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxExportXlgmii", - "path": "ethernet/EthMacCore/rtl/EthMacTxExportXlgmii.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxFifo", - "path": "ethernet/EthMacCore/rtl/EthMacTxFifo.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxPause", - "path": "ethernet/EthMacCore/rtl/EthMacTxPause.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxShift", - "path": "ethernet/EthMacCore/rtl/EthMacTxShift.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthReg", - "path": "ethernet/GigEthCore/core/rtl/GigEthReg.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGth7", - "path": "ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGth7Wrapper", - "path": "ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGthUltraScale", - "path": "ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGthUltraScaleWrapper", - "path": "ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGthUltraScale", - "path": "ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGthUltraScaleWrapper", - "path": "ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtp7", - "path": "ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtp7Wrapper", - "path": "ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtx7", - "path": "ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtx7Wrapper", - "path": "ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtyUltraScale", - "path": "ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthGtyUltraScaleWrapper", - "path": "ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GigEthLvdsUltraScale", - "path": "ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ArpEngine", - "path": "ethernet/IpV4Engine/rtl/ArpEngine.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IcmpEngine", - "path": "ethernet/IpV4Engine/rtl/IcmpEngine.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IgmpV2Engine", - "path": "ethernet/IpV4Engine/rtl/IgmpV2Engine.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IpV4Engine", - "path": "ethernet/IpV4Engine/rtl/IpV4Engine.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IpV4EngineDeMux", - "path": "ethernet/IpV4Engine/rtl/IpV4EngineDeMux.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IpV4EngineRx", - "path": "ethernet/IpV4Engine/rtl/IpV4EngineRx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "IpV4EngineTx", - "path": "ethernet/IpV4Engine/rtl/IpV4EngineTx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RawEthFramer", - "path": "ethernet/RawEthFramer/rtl/RawEthFramer.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RawEthFramerRx", - "path": "ethernet/RawEthFramer/rtl/RawEthFramerRx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RawEthFramerTx", - "path": "ethernet/RawEthFramer/rtl/RawEthFramerTx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RawEthFramerWrapper", - "path": "ethernet/RawEthFramer/rtl/RawEthFramerWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacCrcAxiStreamWrapperRecv", - "path": "ethernet/RoCEv2/rtl/EthMacCrcAxiStreamWrapperRecv.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacCrcAxiStreamWrapperSend", - "path": "ethernet/RoCEv2/rtl/EthMacCrcAxiStreamWrapperSend.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacPrepareForICrc", - "path": "ethernet/RoCEv2/rtl/EthMacPrepareForICrc.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxCheckICrc", - "path": "ethernet/RoCEv2/rtl/EthMacRxCheckICrc.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacRxRoCEv2", - "path": "ethernet/RoCEv2/rtl/EthMacRxRoCEv2.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EthMacTxRoCEv2", - "path": "ethernet/RoCEv2/rtl/EthMacTxRoCEv2.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RoceConfigurator", - "path": "ethernet/RoCEv2/rtl/RoceConfigurator.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RoceEngineWrapper", - "path": "ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RoceResizeAndSwap", - "path": "ethernet/RoCEv2/rtl/RoceResizeAndSwap.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthReg", - "path": "ethernet/TenGigEthCore/core/rtl/TenGigEthReg.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthRst", - "path": "ethernet/TenGigEthCore/core/rtl/TenGigEthRst.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGth7", - "path": "ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGth7Clk", - "path": "ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Clk.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGth7Wrapper", - "path": "ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScale", - "path": "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleClk", - "path": "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleClk.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleRst", - "path": "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleRst.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleWrapper", - "path": "ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScale", - "path": "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleClk", - "path": "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleClk.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleRst", - "path": "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleRst.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGthUltraScaleWrapper", - "path": "ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtx7", - "path": "ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtx7Clk", - "path": "ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Clk.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtx7Wrapper", - "path": "ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtyUltraScale", - "path": "ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtyUltraScaleClk", - "path": "ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleClk.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtyUltraScaleRst", - "path": "ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleRst.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "TenGigEthGtyUltraScaleWrapper", - "path": "ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ArpIpTable", - "path": "ethernet/UdpEngine/rtl/ArpIpTable.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngine", - "path": "ethernet/UdpEngine/rtl/UdpEngine.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngineArp", - "path": "ethernet/UdpEngine/rtl/UdpEngineArp.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngineDhcp", - "path": "ethernet/UdpEngine/rtl/UdpEngineDhcp.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngineRx", - "path": "ethernet/UdpEngine/rtl/UdpEngineRx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngineTx", - "path": "ethernet/UdpEngine/rtl/UdpEngineTx.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UdpEngineWrapper", - "path": "ethernet/UdpEngine/rtl/UdpEngineWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiReg", - "path": "ethernet/XauiCore/core/rtl/XauiReg.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGth7", - "path": "ethernet/XauiCore/gth7/rtl/XauiGth7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGth7Core", - "path": "ethernet/XauiCore/gth7/rtl/XauiGth7Core.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGth7Wrapper", - "path": "ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGthUltraScale", - "path": "ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGthUltraScaleWrapper", - "path": "ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGthUltraScale", - "path": "ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGthUltraScaleWrapper", - "path": "ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGtx7", - "path": "ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGtx7Core", - "path": "ethernet/XauiCore/gtx7/rtl/XauiGtx7Core.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGtx7Wrapper", - "path": "ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGtyUltraScale", - "path": "ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "XauiGtyUltraScaleWrapper", - "path": "ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd", - "subsystem": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamBatcher", - "path": "protocols/batcher/rtl/AxiStreamBatcher.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamBatcherAxil", - "path": "protocols/batcher/rtl/AxiStreamBatcherAxil.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamBatcherEventBuilder", - "path": "protocols/batcher/rtl/AxiStreamBatcherEventBuilder.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkDataClk", - "path": "protocols/clink/7Series/ClinkDataClk.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkDataShift", - "path": "protocols/clink/7Series/ClinkDataShift.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkDataClk", - "path": "protocols/clink/UltraScale/ClinkDataClk.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkDataShift", - "path": "protocols/clink/UltraScale/ClinkDataShift.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkCtrl", - "path": "protocols/clink/rtl/ClinkCtrl.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkData", - "path": "protocols/clink/rtl/ClinkData.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkFraming", - "path": "protocols/clink/rtl/ClinkFraming.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkReg", - "path": "protocols/clink/rtl/ClinkReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkTop", - "path": "protocols/clink/rtl/ClinkTop.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkUart", - "path": "protocols/clink/rtl/ClinkUart.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ClinkUartThrottle", - "path": "protocols/clink/rtl/ClinkUartThrottle.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressAxiL", - "path": "protocols/coaxpress/core/rtl/CoaXPressAxiL.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressConfig", - "path": "protocols/coaxpress/core/rtl/CoaXPressConfig.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressCore", - "path": "protocols/coaxpress/core/rtl/CoaXPressCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressEventAckMsg", - "path": "protocols/coaxpress/core/rtl/CoaXPressEventAckMsg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberBridge", - "path": "protocols/coaxpress/core/rtl/CoaXPressOverFiberBridge.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberBridgeRx", - "path": "protocols/coaxpress/core/rtl/CoaXPressOverFiberBridgeRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberBridgeTx", - "path": "protocols/coaxpress/core/rtl/CoaXPressOverFiberBridgeTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressRx", - "path": "protocols/coaxpress/core/rtl/CoaXPressRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressRxHsFsm", - "path": "protocols/coaxpress/core/rtl/CoaXPressRxHsFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressRxLane", - "path": "protocols/coaxpress/core/rtl/CoaXPressRxLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressRxLaneMux", - "path": "protocols/coaxpress/core/rtl/CoaXPressRxLaneMux.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressRxWordPacker", - "path": "protocols/coaxpress/core/rtl/CoaXPressRxWordPacker.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressTx", - "path": "protocols/coaxpress/core/rtl/CoaXPressTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressTxLsFsm", - "path": "protocols/coaxpress/core/rtl/CoaXPressTxLsFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberGthUsIpWrapper", - "path": "protocols/coaxpress/gthUs+/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGthUs", - "path": "protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGthUsQpll", - "path": "protocols/coaxpress/gthUs+/rtl/CoaxpressOverFiberGthUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberGthUsIpWrapper", - "path": "protocols/coaxpress/gthUs/rtl/CoaXPressOverFiberGthUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGthUs", - "path": "protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGthUsQpll", - "path": "protocols/coaxpress/gthUs/rtl/CoaxpressOverFiberGthUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaXPressOverFiberGtyUsIpWrapper", - "path": "protocols/coaxpress/gtyUs+/rtl/CoaXPressOverFiberGtyUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGtyUs", - "path": "protocols/coaxpress/gtyUs+/rtl/CoaxpressOverFiberGtyUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CoaxpressOverFiberGtyUsQpll", - "path": "protocols/coaxpress/gtyUs+/rtl/CoaxpressOverFiberGtyUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EventFrameSequencerDemux", - "path": "protocols/event-frame-sequencer/rtl/EventFrameSequencerDemux.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EventFrameSequencerMux", - "path": "protocols/event-frame-sequencer/rtl/EventFrameSequencerMux.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "EventFrameSequencerWrapper", - "path": "protocols/event-frame-sequencer/wrappers/EventFrameSequencerWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkDecoder", - "path": "protocols/glink/core/rtl/GLinkDecoder.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkEncoder", - "path": "protocols/glink/core/rtl/GLinkEncoder.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkTxToRx", - "path": "protocols/glink/core/rtl/GLinkTxToRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkGtp7FixedLat", - "path": "protocols/glink/gtp7/rtl/GLinkGtp7FixedLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkGtx7Core", - "path": "protocols/glink/gtx7/rtl/GLinkGtx7Core.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkGtx7FixedLat", - "path": "protocols/glink/gtx7/rtl/GLinkGtx7FixedLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "GLinkGtx7RxRst", - "path": "protocols/glink/gtx7/rtl/GLinkGtx7RxRst.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HammingEccDecoder", - "path": "protocols/hamming-ecc/rtl/HammingEccDecoder.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HammingEccEncoder", - "path": "protocols/hamming-ecc/rtl/HammingEccEncoder.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HammingEccWrapper", - "path": "protocols/hamming-ecc/wrappers/HammingEccWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspAxiL", - "path": "protocols/htsp/core/rtl/HtspAxiL.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspCore", - "path": "protocols/htsp/core/rtl/HtspCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspRx", - "path": "protocols/htsp/core/rtl/HtspRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspRxFifo", - "path": "protocols/htsp/core/rtl/HtspRxFifo.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspTx", - "path": "protocols/htsp/core/rtl/HtspTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspTxFifo", - "path": "protocols/htsp/core/rtl/HtspTxFifo.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "HtspCaui4Gty", - "path": "protocols/htsp/gtyUs+/rtl/HtspCaui4Gty.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiI2cEeprom", - "path": "protocols/i2c/axi/AxiI2cEeprom.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiI2cEepromCore", - "path": "protocols/i2c/axi/AxiI2cEepromCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiI2cRegMaster", - "path": "protocols/i2c/axi/AxiI2cRegMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiI2cRegMasterCore", - "path": "protocols/i2c/axi/AxiI2cRegMasterCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLiteCrossbarI2cMux", - "path": "protocols/i2c/axi/AxiLiteCrossbarI2cMux.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cMaster", - "path": "protocols/i2c/rtl/I2cMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRegMaster", - "path": "protocols/i2c/rtl/I2cRegMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRegMasterAxiBridge", - "path": "protocols/i2c/rtl/I2cRegMasterAxiBridge.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRegMasterMux", - "path": "protocols/i2c/rtl/I2cRegMasterMux.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRegSlave", - "path": "protocols/i2c/rtl/I2cRegSlave.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cSlave", - "path": "protocols/i2c/rtl/I2cSlave.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2c_master_bit_ctrl", - "path": "protocols/i2c/rtl/i2c_master_bit_ctrl.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2c_master_byte_ctrl", - "path": "protocols/i2c/rtl/i2c_master_byte_ctrl.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2c2ahb", - "path": "protocols/i2c/rtl/orig/i2c2ahb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2c2ahb_apb", - "path": "protocols/i2c/rtl/orig/i2c2ahb_apb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2c2ahbx", - "path": "protocols/i2c/rtl/orig/i2c2ahbx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2cmst", - "path": "protocols/i2c/rtl/orig/i2cmst.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2cmst_gen", - "path": "protocols/i2c/rtl/orig/i2cmst_gen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "i2cslv", - "path": "protocols/i2c/rtl/orig/i2cslv.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRamSlave", - "path": "protocols/i2c/sim/I2cRamSlave.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "I2cRegTb", - "path": "protocols/i2c/sim/I2cRegTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd16bTo32b", - "path": "protocols/jesd204b/rtl/Jesd16bTo32b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd204bRx", - "path": "protocols/jesd204b/rtl/Jesd204bRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd204bTx", - "path": "protocols/jesd204b/rtl/Jesd204bTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd32bTo16b", - "path": "protocols/jesd204b/rtl/Jesd32bTo16b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd32bTo64b", - "path": "protocols/jesd204b/rtl/Jesd32bTo64b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd64bTo32b", - "path": "protocols/jesd204b/rtl/Jesd64bTo32b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdAlignChGen", - "path": "protocols/jesd204b/rtl/JesdAlignChGen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdAlignFrRepCh", - "path": "protocols/jesd204b/rtl/JesdAlignFrRepCh.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdIlasGen", - "path": "protocols/jesd204b/rtl/JesdIlasGen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdLmfcGen", - "path": "protocols/jesd204b/rtl/JesdLmfcGen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdRxLane", - "path": "protocols/jesd204b/rtl/JesdRxLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdRxReg", - "path": "protocols/jesd204b/rtl/JesdRxReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdSyncFsmRx", - "path": "protocols/jesd204b/rtl/JesdSyncFsmRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdSyncFsmTx", - "path": "protocols/jesd204b/rtl/JesdSyncFsmTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdSyncFsmTxTest", - "path": "protocols/jesd204b/rtl/JesdSyncFsmTxTest.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdSysrefMon", - "path": "protocols/jesd204b/rtl/JesdSysrefMon.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdTestSigGen", - "path": "protocols/jesd204b/rtl/JesdTestSigGen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdTestStreamTx", - "path": "protocols/jesd204b/rtl/JesdTestStreamTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdTxLane", - "path": "protocols/jesd204b/rtl/JesdTxLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdTxReg", - "path": "protocols/jesd204b/rtl/JesdTxReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "JesdTxTest", - "path": "protocols/jesd204b/rtl/JesdTxTest.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "iq16bTo32b", - "path": "protocols/jesd204b/rtl/iq16bTo32b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "iq32bTo16b", - "path": "protocols/jesd204b/rtl/iq32bTo16b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "DescrambleTb", - "path": "protocols/jesd204b/sim/DescrambleTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Jesd204bTb", - "path": "protocols/jesd204b/sim/Jesd204bTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "ScramblerTb", - "path": "protocols/jesd204b/sim/ScramblerTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Decoder10b12b", - "path": "protocols/line-codes/rtl/Decoder10b12b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Decoder12b14b", - "path": "protocols/line-codes/rtl/Decoder12b14b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Decoder8b10b", - "path": "protocols/line-codes/rtl/Decoder8b10b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Encoder10b12b", - "path": "protocols/line-codes/rtl/Encoder10b12b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Encoder12b14b", - "path": "protocols/line-codes/rtl/Encoder12b14b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Encoder8b10b", - "path": "protocols/line-codes/rtl/Encoder8b10b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Code10b12bPkgWrapper", - "path": "protocols/line-codes/wrappers/Code10b12bPkgWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Code12b14bPkgWrapper", - "path": "protocols/line-codes/wrappers/Code12b14bPkgWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Code8b10bPkgWrapper", - "path": "protocols/line-codes/wrappers/Code8b10bPkgWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "MdioCore", - "path": "protocols/mdio/rtl/MdioCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "MdioLinkIrqHandler", - "path": "protocols/mdio/rtl/MdioLinkIrqHandler.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "MdioSeqCore", - "path": "protocols/mdio/rtl/MdioSeqCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamBytePacker", - "path": "protocols/packetizer/rtl/AxiStreamBytePacker.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamDepacketizer", - "path": "protocols/packetizer/rtl/AxiStreamDepacketizer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamDepacketizer2", - "path": "protocols/packetizer/rtl/AxiStreamDepacketizer2.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamPacketizer", - "path": "protocols/packetizer/rtl/AxiStreamPacketizer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiStreamPacketizer2", - "path": "protocols/packetizer/rtl/AxiStreamPacketizer2.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bAxi", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bLane", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bRx", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bRxCell", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bRxCell.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bRxPhy", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bRxPhy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bTx", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bTxCell", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bTxCell.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bTxPhy", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bTxPhy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bTxSched", - "path": "protocols/pgp/pgp2b/core/rtl/Pgp2bTxSched.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGth7Fixedlat", - "path": "protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7FixedLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGth7FixedLatWrapper", - "path": "protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7FixedLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGth7MultiLane", - "path": "protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7MultiLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGth7VarLat", - "path": "protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7VarLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGth7VarLatWrapper", - "path": "protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7VarLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGthUltra", - "path": "protocols/pgp/pgp2b/gthUltraScale+/rtl/Pgp2bGthUltra.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpGthCoreWrapper", - "path": "protocols/pgp/pgp2b/gthUltraScale+/rtl/PgpGthCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGthUltra", - "path": "protocols/pgp/pgp2b/gthUltraScale/rtl/Pgp2bGthUltra.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpGthCoreWrapper", - "path": "protocols/pgp/pgp2b/gthUltraScale/rtl/PgpGthCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtp7FixedLat", - "path": "protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7FixedLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtp7FixedLatWrapper", - "path": "protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7FixedLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtp7MultiLane", - "path": "protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7MultiLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtp7VarLat", - "path": "protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7VarLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtp7VarLatWrapper", - "path": "protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7VarLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtx7Fixedlat", - "path": "protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtx7FixedLatWrapper", - "path": "protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtx7MultiLane", - "path": "protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7MultiLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtx7VarLat", - "path": "protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7VarLat.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtx7VarLatWrapper", - "path": "protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7VarLatWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2bGtyUltra", - "path": "protocols/pgp/pgp2b/gtyUltraScale+/rtl/Pgp2bGtyUltra.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpGtyCoreWrapper", - "path": "protocols/pgp/pgp2b/gtyUltraScale+/rtl/PgpGtyCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "CRC7Rtl", - "path": "protocols/pgp/pgp2fc/core/rtl/CRC7Rtl.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcAlignmentChecker", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcAlignmentChecker.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcAlignmentController", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcAlignmentController.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcAxi", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcLane", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcRx", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcRxCell", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxCell.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcRxPhy", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxPhy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcTx", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcTxCell", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxCell.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcTxPhy", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcTxSched", - "path": "protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxSched.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGthCoreWrapper", - "path": "protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGthUltra", - "path": "protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGtp7", - "path": "protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGtp7Wrapper", - "path": "protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7Wrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGtyCoreWrapper", - "path": "protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp2fcGtyUltra", - "path": "protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3AxiL", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3AxiL.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Core", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3Core.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Rx", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3Rx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3RxEb", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3RxEb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3RxGearboxAligner", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3RxGearboxAligner.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3RxProtocol", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3RxProtocol.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Tx", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3Tx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3TxProtocol", - "path": "protocols/pgp/pgp3/core/rtl/Pgp3TxProtocol.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUs", - "path": "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsIpWrapper", - "path": "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsQpll", - "path": "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsWrapper", - "path": "protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUs", - "path": "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsIpWrapper", - "path": "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsQpll", - "path": "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GthUsWrapper", - "path": "protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7IpWrapper", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7IpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7Qpll", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7Qpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7RxGearbox", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7RxGearbox.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7TxGearbox", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7TxGearbox.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtp7Wrapper", - "path": "protocols/pgp/pgp3/gtp7/rtl/Pgp3Gtp7Wrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtx7", - "path": "protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtx7IpWrapper", - "path": "protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7IpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtx7Qpll", - "path": "protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Qpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3Gtx7Wrapper", - "path": "protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Wrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GtyUs", - "path": "protocols/pgp/pgp3/gtyUs+/rtl/Pgp3GtyUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GtyUsIpWrapper", - "path": "protocols/pgp/pgp3/gtyUs+/rtl/Pgp3GtyUsIpWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GtyUsQpll", - "path": "protocols/pgp/pgp3/gtyUs+/rtl/Pgp3GtyUsQpll.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp3GtyUsWrapper", - "path": "protocols/pgp/pgp3/gtyUs+/rtl/Pgp3GtyUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4AxiL", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4AxiL.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Core", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4Core.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4CoreLite", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4CoreLite.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Rx", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4Rx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4RxEb", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4LiteRxLowSpeed", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4RxLiteLowSpeed.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4RxLiteLowSpeedLane", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4RxLiteLowSpeedLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4RxLiteLowSpeedReg", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4RxLiteLowSpeedReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4RxProtocol", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4RxProtocol.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Tx", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4Tx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4TxLite", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4TxLite.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4TxLiteProtocol", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4TxLiteProtocol.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4TxLiteWrapper", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4TxProtocol", - "path": "protocols/pgp/pgp4/core/rtl/Pgp4TxProtocol.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4CoreLiteWrapper", - "path": "protocols/pgp/pgp4/core/wrappers/Pgp4CoreLiteWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4CoreWrapper", - "path": "protocols/pgp/pgp4/core/wrappers/Pgp4CoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GthUs", - "path": "protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GthUsWrapper", - "path": "protocols/pgp/pgp4/gthUs+/rtl/Pgp4GthUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GthUs", - "path": "protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GthUsWrapper", - "path": "protocols/pgp/pgp4/gthUs/rtl/Pgp4GthUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Gtp7", - "path": "protocols/pgp/pgp4/gtp7/rtl/Pgp4Gtp7.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Gtp7Wrapper", - "path": "protocols/pgp/pgp4/gtp7/rtl/Pgp4Gtp7Wrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Gtx7", - "path": "protocols/pgp/pgp4/gtx7/rtl/Pgp4Gtx7.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4Gtx7Wrapper", - "path": "protocols/pgp/pgp4/gtx7/rtl/Pgp4Gtx7Wrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GtyUs", - "path": "protocols/pgp/pgp4/gtyUs+/rtl/Pgp4GtyUs.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GtyUsIpFecWrapper", - "path": "protocols/pgp/pgp4/gtyUs+/rtl/Pgp4GtyUsIpFecWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Pgp4GtyUsWrapper", - "path": "protocols/pgp/pgp4/gtyUs+/rtl/Pgp4GtyUsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpRxVcFifo", - "path": "protocols/pgp/shared/PgpRxVcFifo.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpTxVcFifo", - "path": "protocols/pgp/shared/PgpTxVcFifo.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "PgpXvcWrapper", - "path": "protocols/pgp/shared/xilinx/PgpXvcWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLitePMbusMaster", - "path": "protocols/pmbus/rtl/AxiLitePMbusMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLitePMbusMasterCore", - "path": "protocols/pmbus/rtl/AxiLitePMbusMasterCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiAxiLiteRegItf", - "path": "protocols/rssi/v1/rtl/RssiAxiLiteRegItf.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiChksum", - "path": "protocols/rssi/v1/rtl/RssiChksum.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiConnFsm", - "path": "protocols/rssi/v1/rtl/RssiConnFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiCore", - "path": "protocols/rssi/v1/rtl/RssiCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiCoreWrapper", - "path": "protocols/rssi/v1/rtl/RssiCoreWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiHeaderReg", - "path": "protocols/rssi/v1/rtl/RssiHeaderReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiMonitor", - "path": "protocols/rssi/v1/rtl/RssiMonitor.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiParamSync", - "path": "protocols/rssi/v1/rtl/RssiParamSync.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiRxFsm", - "path": "protocols/rssi/v1/rtl/RssiRxFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "RssiTxFsm", - "path": "protocols/rssi/v1/rtl/RssiTxFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLiteSaciMaster", - "path": "protocols/saci/saci1/rtl/AxiLiteSaciMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciAxiLiteMaster", - "path": "protocols/saci/saci1/rtl/SaciAxiLiteMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciMaster", - "path": "protocols/saci/saci1/rtl/SaciMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciMaster2", - "path": "protocols/saci/saci1/rtl/SaciMaster2.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciMasterSync", - "path": "protocols/saci/saci1/rtl/SaciMasterSync.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciMultiPixel", - "path": "protocols/saci/saci1/rtl/SaciMultiPixel.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciPrepRdout", - "path": "protocols/saci/saci1/rtl/SaciPrepRdout.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciSlave", - "path": "protocols/saci/saci1/rtl/SaciSlave.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciSlaveOld", - "path": "protocols/saci/saci1/rtl/SaciSlaveOld.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLiteSaciMasterTb", - "path": "protocols/saci/saci1/sim/AxiLiteSaciMasterTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciAxiLiteMasterTb", - "path": "protocols/saci/saci1/sim/SaciAxiLiteMasterTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciAxiLiteMasterTbWrapper", - "path": "protocols/saci/saci1/sim/SaciAxiLiteMasterTbWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciSlaveRam", - "path": "protocols/saci/saci1/sim/SaciSlaveRam.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciSlaveWrapper", - "path": "protocols/saci/saci1/sim/SaciSlaveWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaciAxiLiteMasterWrapper", - "path": "protocols/saci/saci1/wrappers/SaciAxiLiteMasterWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLiteToSaci2", - "path": "protocols/saci/saci2/rtl/AxiLiteToSaci2.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Saci2Coordinator", - "path": "protocols/saci/saci2/rtl/Saci2Coordinator.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Saci2Subordinate", - "path": "protocols/saci/saci2/rtl/Saci2Subordinate.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Saci2ToAxiLite", - "path": "protocols/saci/saci2/rtl/Saci2ToAxiLite.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Saci2ToAxiLiteTb", - "path": "protocols/saci/saci2/sim/Saci2ToAxiLiteTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Saci2ToAxiLiteWrapper", - "path": "protocols/saci/saci2/wrappers/Saci2ToAxiLiteWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltRxDeser", - "path": "protocols/salt/rtl/7Series/SaltRxDeser.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltTxSer", - "path": "protocols/salt/rtl/7Series/SaltTxSer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltCore", - "path": "protocols/salt/rtl/SaltCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltDelayCtrl", - "path": "protocols/salt/rtl/SaltDelayCtrl.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltRx", - "path": "protocols/salt/rtl/SaltRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltRxLvds", - "path": "protocols/salt/rtl/SaltRxLvds.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltTx", - "path": "protocols/salt/rtl/SaltTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltTxLvds", - "path": "protocols/salt/rtl/SaltTxLvds.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltTxResize", - "path": "protocols/salt/rtl/SaltTxResize.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltRxDeser", - "path": "protocols/salt/rtl/UltraScale/SaltRxDeser.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SaltTxSer", - "path": "protocols/salt/rtl/UltraScale/SaltTxSer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiSpiMaster", - "path": "protocols/spi/rtl/AxiSpiMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SpiMaster", - "path": "protocols/spi/rtl/SpiMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SpiSlave", - "path": "protocols/spi/rtl/SpiSlave.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "AxiLiteSrpV0", - "path": "protocols/srp/rtl/AxiLiteSrpV0.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV0AxiLite", - "path": "protocols/srp/rtl/SrpV0AxiLite.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV3Axi", - "path": "protocols/srp/rtl/SrpV3Axi.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV3AxiLite", - "path": "protocols/srp/rtl/SrpV3AxiLite.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV3AxiLiteFull", - "path": "protocols/srp/rtl/SrpV3AxiLiteFull.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV3Core", - "path": "protocols/srp/rtl/SrpV3Core.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SrpV3AxiWrapper", - "path": "protocols/srp/wrappers/SrpV3AxiWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiAxiLiteMaster", - "path": "protocols/ssi/rtl/SsiAxiLiteMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiCmdMaster", - "path": "protocols/ssi/rtl/SsiCmdMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiCmdMasterPulser", - "path": "protocols/ssi/rtl/SsiCmdMasterPulser.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiDbgTap", - "path": "protocols/ssi/rtl/SsiDbgTap.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiFifo", - "path": "protocols/ssi/rtl/SsiFifo.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiFrameLimiter", - "path": "protocols/ssi/rtl/SsiFrameLimiter.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiIbFrameFilter", - "path": "protocols/ssi/rtl/SsiIbFrameFilter.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiIncrementingTx", - "path": "protocols/ssi/rtl/SsiIncrementingTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiInsertSof", - "path": "protocols/ssi/rtl/SsiInsertSof.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiObFrameFilter", - "path": "protocols/ssi/rtl/SsiObFrameFilter.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiPrbsRateGen", - "path": "protocols/ssi/rtl/SsiPrbsRateGen.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiPrbsRx", - "path": "protocols/ssi/rtl/SsiPrbsRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiPrbsTx", - "path": "protocols/ssi/rtl/SsiPrbsTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiPrbsWrapper", - "path": "protocols/ssi/wrappers/SsiPrbsWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SsiResizeFifoEofeWrapper", - "path": "protocols/ssi/wrappers/SsiResizeFifoEofeWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspDecoder10b12b", - "path": "protocols/ssp/rtl/SspDecoder10b12b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspDecoder12b14b", - "path": "protocols/ssp/rtl/SspDecoder12b14b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspDecoder8b10b", - "path": "protocols/ssp/rtl/SspDecoder8b10b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspDeframer", - "path": "protocols/ssp/rtl/SspDeframer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspEncoder10b12b", - "path": "protocols/ssp/rtl/SspEncoder10b12b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspEncoder12b14b", - "path": "protocols/ssp/rtl/SspEncoder12b14b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspEncoder8b10b", - "path": "protocols/ssp/rtl/SspEncoder8b10b.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspFramer", - "path": "protocols/ssp/rtl/SspFramer.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspLowSpeedDecoder10b12bWrapper", - "path": "protocols/ssp/rtl/SspLowSpeedDecoder10b12bWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspLowSpeedDecoder12b14bWrapper", - "path": "protocols/ssp/rtl/SspLowSpeedDecoder12b14bWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspLowSpeedDecoder8b10bWrapper", - "path": "protocols/ssp/rtl/SspLowSpeedDecoder8b10bWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspLowSpeedDecoderLane", - "path": "protocols/ssp/rtl/SspLowSpeedDecoderLane.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SspLowSpeedDecoderReg", - "path": "protocols/ssp/rtl/SspLowSpeedDecoderReg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerRx7Series", - "path": "protocols/sugoi/rtl/7Series/SugoiManagerRx7Series.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiAxiLitePixelMatrixConfig", - "path": "protocols/sugoi/rtl/SugoiAxiLitePixelMatrixConfig.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerCore", - "path": "protocols/sugoi/rtl/SugoiManagerCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerFsm", - "path": "protocols/sugoi/rtl/SugoiManagerFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerRx", - "path": "protocols/sugoi/rtl/SugoiManagerRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiSubordinateCore", - "path": "protocols/sugoi/rtl/SugoiSubordinateCore.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiSubordinateFsm", - "path": "protocols/sugoi/rtl/SugoiSubordinateFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerRxUltrascale", - "path": "protocols/sugoi/rtl/UltraScale/SugoiManagerRxUltrascale.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerRx7Series", - "path": "protocols/sugoi/rtl/dummy/SugoiManagerRx7SeriesDummy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "SugoiManagerRxUltrascale", - "path": "protocols/sugoi/rtl/dummy/SugoiManagerRxUltrascaleDummy.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartAxiLiteMaster", - "path": "protocols/uart/rtl/UartAxiLiteMaster.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartAxiLiteMasterFsm", - "path": "protocols/uart/rtl/UartAxiLiteMasterFsm.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartBrg", - "path": "protocols/uart/rtl/UartBrg.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartRx", - "path": "protocols/uart/rtl/UartRx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartTx", - "path": "protocols/uart/rtl/UartTx.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartWrapper", - "path": "protocols/uart/rtl/UartWrapper.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "UartAxiLiteMasterTb", - "path": "protocols/uart/sim/UartAxiLiteMasterTb.vhd", - "subsystem": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "entity": "Idelaye3Wrapper", - "path": "xilinx/7Series/dummy/Idelaye3WrapperDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Odelaye3Wrapper", - "path": "xilinx/7Series/dummy/Odelaye3WrapperDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClockManager7", - "path": "xilinx/7Series/general/rtl/ClockManager7.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DeviceDna7Series", - "path": "xilinx/7Series/general/rtl/DeviceDna7Series.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Dsp48Comparator4x12b", - "path": "xilinx/7Series/general/rtl/Dsp48Comparator4x12b.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "InputBufferReg", - "path": "xilinx/7Series/general/rtl/InputBufferReg.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Iprog7Series", - "path": "xilinx/7Series/general/rtl/Iprog7Series.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Iprog7SeriesCore", - "path": "xilinx/7Series/general/rtl/Iprog7SeriesCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "OutputBufferReg", - "path": "xilinx/7Series/general/rtl/OutputBufferReg.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SelectioDeser7Series", - "path": "xilinx/7Series/general/rtl/SelectioDeser7Series.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SelectioDeserLane7Series", - "path": "xilinx/7Series/general/rtl/SelectioDeserLane7Series.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7AutoPhaseAligner", - "path": "xilinx/7Series/gth7/rtl/Gth7AutoPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7Core", - "path": "xilinx/7Series/gth7/rtl/Gth7Core.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7QuadPll", - "path": "xilinx/7Series/gth7/rtl/Gth7QuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7RecClkMonitor", - "path": "xilinx/7Series/gth7/rtl/Gth7RecClkMonitor.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7RxFixedLatPhaseAligner", - "path": "xilinx/7Series/gth7/rtl/Gth7RxFixedLatPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7RxRst", - "path": "xilinx/7Series/gth7/rtl/Gth7RxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7RxRstSeq", - "path": "xilinx/7Series/gth7/rtl/Gth7RxRstSeq.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7TxManualPhaseAligner", - "path": "xilinx/7Series/gth7/rtl/Gth7TxManualPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gth7TxRst", - "path": "xilinx/7Series/gth7/rtl/Gth7TxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7AutoPhaseAligner", - "path": "xilinx/7Series/gtp7/rtl/Gtp7AutoPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7Core", - "path": "xilinx/7Series/gtp7/rtl/Gtp7Core.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7QuadPll", - "path": "xilinx/7Series/gtp7/rtl/Gtp7QuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7RecClkMonitor", - "path": "xilinx/7Series/gtp7/rtl/Gtp7RecClkMonitor.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7RxFixedLatPhaseAligner", - "path": "xilinx/7Series/gtp7/rtl/Gtp7RxFixedLatPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7RxRst", - "path": "xilinx/7Series/gtp7/rtl/Gtp7RxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7RxRstSeq", - "path": "xilinx/7Series/gtp7/rtl/Gtp7RxRstSeq.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7TxManualPhaseAligner", - "path": "xilinx/7Series/gtp7/rtl/Gtp7TxManualPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp7TxRst", - "path": "xilinx/7Series/gtp7/rtl/Gtp7TxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtpe2ChannelDummy", - "path": "xilinx/7Series/gtp7/rtl/Gtpe2ChannelDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7AutoPhaseAligner", - "path": "xilinx/7Series/gtx7/rtl/Gtx7AutoPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7Core", - "path": "xilinx/7Series/gtx7/rtl/Gtx7Core.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7QuadPll", - "path": "xilinx/7Series/gtx7/rtl/Gtx7QuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7RecClkMonitor", - "path": "xilinx/7Series/gtx7/rtl/Gtx7RecClkMonitor.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7RxFixedLatPhaseAligner", - "path": "xilinx/7Series/gtx7/rtl/Gtx7RxFixedLatPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7RxRst", - "path": "xilinx/7Series/gtx7/rtl/Gtx7RxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7TxManualPhaseAligner", - "path": "xilinx/7Series/gtx7/rtl/Gtx7TxManualPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtx7TxRst", - "path": "xilinx/7Series/gtx7/rtl/Gtx7TxRst.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtxe2ChannelDummy", - "path": "xilinx/7Series/gtx7/rtl/Gtxe2ChannelDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SemWrapper", - "path": "xilinx/7Series/sem/rtl/SemWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SsiSem", - "path": "xilinx/7Series/sem/rtl/SsiSem.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UartSem", - "path": "xilinx/7Series/sem/rtl/UartSem.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiXadcMinimumCore", - "path": "xilinx/7Series/xadc/rtl/AxiXadcMinimumCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "XadcSimpleCore", - "path": "xilinx/7Series/xadc/rtl/XadcSimpleCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClockManagerUltraScale", - "path": "xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GthUltraScaleQuadPll", - "path": "xilinx/UltraScale+/gthUs+/rtl/GthUltraScaleQuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gthe4ChannelDummy", - "path": "xilinx/UltraScale+/gthUs+/rtl/Gthe4ChannelDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GtyUltraScaleQuadPll", - "path": "xilinx/UltraScale+/gtyUs+/rtl/GtyUltraScaleQuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtye4ChannelDummy", - "path": "xilinx/UltraScale+/gtyUs+/rtl/Gtye4ChannelDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClockManagerUltraScale", - "path": "xilinx/UltraScale/clocking/rtl/ClockManagerUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Delaye3PatchFsm", - "path": "xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DeviceDnaUltraScale", - "path": "xilinx/UltraScale/general/rtl/DeviceDnaUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Idelaye3Wrapper", - "path": "xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "InputBufferReg", - "path": "xilinx/UltraScale/general/rtl/InputBufferReg.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "IprogUltraScale", - "path": "xilinx/UltraScale/general/rtl/IprogUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Odelaye3Wrapper", - "path": "xilinx/UltraScale/general/rtl/Odelaye3Wrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "OutputBufferReg", - "path": "xilinx/UltraScale/general/rtl/OutputBufferReg.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SelectioDeserLaneUltraScale", - "path": "xilinx/UltraScale/general/rtl/SelectioDeserLaneUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SelectioDeserUltraScale", - "path": "xilinx/UltraScale/general/rtl/SelectioDeserUltraScale.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GthUltraScaleQuadPll", - "path": "xilinx/UltraScale/gthUs/rtl/GthUltraScaleQuadPll.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gthe3ChannelDummy", - "path": "xilinx/UltraScale/gthUs/rtl/Gthe3ChannelDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClockManagerVersal", - "path": "xilinx/Versal/clocking/rtl/ClockManagerVersal.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Gtp16FixedLatCore", - "path": "xilinx/Virtex5/gtp/rtl/Gtp16FixedLatCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GtpDualFixedLatCore", - "path": "xilinx/Virtex5/gtp/rtl/GtpDualFixedLatCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GtpRxCommaAligner", - "path": "xilinx/Virtex5/gtp/rtl/GtpRxCommaAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GtpTxPhaseAligner", - "path": "xilinx/Virtex5/gtp/rtl/GtpTxPhaseAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClkOutBufDiff", - "path": "xilinx/dummy/ClkOutBufDiffDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClkOutBufSingle", - "path": "xilinx/dummy/ClkOutBufSingleDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DeviceDna", - "path": "xilinx/dummy/DeviceDnaDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "IoBufWrapper", - "path": "xilinx/dummy/IoBufWrapperDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Iprog", - "path": "xilinx/dummy/IprogDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "OutputBufferReg", - "path": "xilinx/dummy/OutputBufferRegDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Srl16Delay", - "path": "xilinx/dummy/Srl16DelayDummy.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "MicroblazeBasicCoreWrapper", - "path": "xilinx/general/microblaze/bypass/MicroblazeBasicCoreWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "MicroblazeBasicCoreWrapper", - "path": "xilinx/general/microblaze/generate/MicroblazeBasicCoreWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClkOutBufDiff", - "path": "xilinx/general/rtl/ClkOutBufDiff.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "ClkOutBufSingle", - "path": "xilinx/general/rtl/ClkOutBufSingle.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DeviceDna", - "path": "xilinx/general/rtl/DeviceDna.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "GtRxAlignCheck", - "path": "xilinx/general/rtl/GtRxAlignCheck.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "IoBufWrapper", - "path": "xilinx/general/rtl/IoBufWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Iprog", - "path": "xilinx/general/rtl/Iprog.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "SelectIoRxGearboxAligner", - "path": "xilinx/general/rtl/SelectIoRxGearboxAligner.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "Srl16Delay", - "path": "xilinx/general/rtl/Srl16Delay.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/7Series/Impl/images/UdpDebugBridge_stub.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/7Series/Stub/images/UdpDebugBridge_stub.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/UltraScale/Impl/images/UdpDebugBridge_stub.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/UltraScale/Stub/images/UdpDebugBridge_stub.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridge", - "path": "xilinx/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridgeWrapper", - "path": "xilinx/xvc-udp/dcp/core/UdpDebugBridgeWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxiStreamSelector", - "path": "xilinx/xvc-udp/jtag/rtl/AxiStreamSelector.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxisJtagDebugBridge", - "path": "xilinx/xvc-udp/jtag/rtl/AxisJtagDebugBridge.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxisToJtag", - "path": "xilinx/xvc-udp/jtag/rtl/AxisToJtag.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "AxisToJtagCore", - "path": "xilinx/xvc-udp/jtag/rtl/AxisToJtagCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "JtagSerDesCore", - "path": "xilinx/xvc-udp/jtag/rtl/JtagSerDesCore.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "DmaXvcWrapper", - "path": "xilinx/xvc-udp/rtl/DmaXvcWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "entity": "UdpDebugBridgeWrapper", - "path": "xilinx/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd", - "subsystem": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - } - ], - "unresolved_phase1_edges": [] -} diff --git a/docs/_meta/rtl_phase1_queue.md b/docs/_meta/rtl_phase1_queue.md deleted file mode 100644 index 6b39ac00f6..0000000000 --- a/docs/_meta/rtl_phase1_queue.md +++ /dev/null @@ -1,272 +0,0 @@ -# SURF RTL Phase-1 Queue - -## Scope -- Scan dirs: `base, axi, dsp, protocols, ethernet, devices, xilinx` -- Queue nodes are path-qualified RTL entity definitions, not bare entity names. -- Queue order is bottom-up: leaves first, higher-level assemblies later. -- Manual phase-1 deferrals and order overrides live in `docs/_meta/rtl_phase1_queue_overrides.json`. - -## Summary -- Phase-1 modules: `219` -- Phase-1 dependency edges: `392` -- Bottom-up layers: `10` -- Deferred modules: `632` -- Unresolved duplicate-name phase-1 edges: `0` -- Applied order overrides: `0` - -## Phase-1 Filters -- Force-included entities: - - None -- Force-included paths: - - None -- Deferred subsystems: - - `ethernet`: Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first. - - `protocols`: Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first. - - `devices`: Subsystem is currently dominated by vendor-heavy modules in phase 1. - - `xilinx`: Subsystem is currently dominated by vendor-heavy modules in phase 1. -- Deferred entities: - - `LutFixedDelay`: Depends on SinglePortRamPrimitive under the current open-source flow. -- Deferred exact paths: - - None -- Deferred path substrings: - - `axi/simlink/`: Simulation support models are not part of the synthesizable phase-1 queue. - - `/sim/`: Simulation-only support modules are not part of the synthesizable phase-1 queue. - - `/dummy/`: Dummy-backed variants are deferred from the phase-1 executable queue. - - `/altera/`: Vendor-specific implementation branches are deferred in phase 1. - - `/xilinx/`: Vendor-specific implementation branches are deferred in phase 1. - - `7Series`: Family-specific implementation branches are deferred in phase 1. - - `UltraScale`: Family-specific implementation branches are deferred in phase 1. - - `UltraScale+`: Family-specific implementation branches are deferred in phase 1. - - `/gth`: GT-family implementation branches are deferred in phase 1. - - `/gtp`: GT-family implementation branches are deferred in phase 1. - - `/gty`: GT-family implementation branches are deferred in phase 1. - - `/gtx`: GT-family implementation branches are deferred in phase 1. - -## Manual Order Overrides -- None - -## Unresolved Duplicate-Name Phase-1 Edges -- None - -## Flat Bottom-Up Order -| order | layer | entity | subsystem | path | instantiated_by_count | -| --- | --- | --- | --- | --- | --- | -| 1 | 0 | AxiLiteCrossbar | axi | axi/axi-lite/rtl/AxiLiteCrossbar.vhd | 3 | -| 2 | 0 | AxiLiteMaster | axi | axi/axi-lite/rtl/AxiLiteMaster.vhd | 6 | -| 3 | 0 | AxiLiteRegs | axi | axi/axi-lite/rtl/AxiLiteRegs.vhd | 2 | -| 4 | 0 | AxiLiteRespTimer | axi | axi/axi-lite/rtl/AxiLiteRespTimer.vhd | 1 | -| 5 | 0 | AxiLiteSlave | axi | axi/axi-lite/rtl/AxiLiteSlave.vhd | 2 | -| 6 | 0 | AxiLiteWriteFilter | axi | axi/axi-lite/rtl/AxiLiteWriteFilter.vhd | 1 | -| 7 | 0 | AxiVersion | axi | axi/axi-lite/rtl/AxiVersion.vhd | 1 | -| 8 | 0 | AxiStreamCombiner | axi | axi/axi-stream/rtl/AxiStreamCombiner.vhd | 1 | -| 9 | 0 | AxiStreamFlush | axi | axi/axi-stream/rtl/AxiStreamFlush.vhd | 1 | -| 10 | 0 | AxiStreamGearboxPack | axi | axi/axi-stream/rtl/AxiStreamGearboxPack.vhd | 1 | -| 11 | 0 | AxiStreamGearboxUnpack | axi | axi/axi-stream/rtl/AxiStreamGearboxUnpack.vhd | 1 | -| 12 | 0 | AxiStreamPipeline | axi | axi/axi-stream/rtl/AxiStreamPipeline.vhd | 18 | -| 13 | 0 | AxiStreamSplitter | axi | axi/axi-stream/rtl/AxiStreamSplitter.vhd | 1 | -| 14 | 0 | AxiStreamPkgWrapper | axi | axi/axi-stream/wrappers/AxiStreamPkgWrapper.vhd | 0 | -| 15 | 0 | AxiReadPathMux | axi | axi/axi4/rtl/AxiReadPathMux.vhd | 1 | -| 16 | 0 | AxiResize | axi | axi/axi4/rtl/AxiResize.vhd | 1 | -| 17 | 0 | AxiWritePathMux | axi | axi/axi4/rtl/AxiWritePathMux.vhd | 1 | -| 18 | 0 | AxiToAxiLite | axi | axi/bridge/rtl/AxiToAxiLite.vhd | 1 | -| 19 | 0 | AxiStreamDmaV2WriteMux | axi | axi/dma/rtl/v2/AxiStreamDmaV2WriteMux.vhd | 2 | -| 20 | 0 | CRC32Rtl | base | base/crc/rtl/CRC32Rtl.vhd | 0 | -| 21 | 0 | Crc32 | base | base/crc/rtl/Crc32.vhd | 1 | -| 22 | 0 | Crc32Parallel | base | base/crc/rtl/Crc32Parallel.vhd | 0 | -| 23 | 0 | SlvDelay | base | base/delay/rtl/SlvDelay.vhd | 0 | -| 24 | 0 | SlvDelayRam | base | base/delay/rtl/SlvDelayRam.vhd | 0 | -| 25 | 0 | SlvFixedDelay | base | base/delay/rtl/SlvFixedDelay.vhd | 0 | -| 26 | 0 | FifoOutputPipeline | base | base/fifo/rtl/FifoOutputPipeline.vhd | 7 | -| 27 | 0 | FifoRdFsm | base | base/fifo/rtl/inferred/FifoRdFsm.vhd | 2 | -| 28 | 0 | FifoWrFsm | base | base/fifo/rtl/inferred/FifoWrFsm.vhd | 2 | -| 29 | 0 | MasterRamIpIntegrator | base | base/general/ip_integrator/MasterRamIpIntegrator.vhd | 0 | -| 30 | 0 | SlaveRamIpIntegrator | base | base/general/ip_integrator/SlaveRamIpIntegrator.vhd | 0 | -| 31 | 0 | Arbiter | base | base/general/rtl/Arbiter.vhd | 0 | -| 32 | 0 | ClockDivider | base | base/general/rtl/ClockDivider.vhd | 0 | -| 33 | 0 | Gearbox | base | base/general/rtl/Gearbox.vhd | 1 | -| 34 | 0 | Heartbeat | base | base/general/rtl/Heartbeat.vhd | 1 | -| 35 | 0 | Mux | base | base/general/rtl/Mux.vhd | 0 | -| 36 | 0 | OneShot | base | base/general/rtl/OneShot.vhd | 0 | -| 37 | 0 | RegisterVector | base | base/general/rtl/RegisterVector.vhd | 0 | -| 38 | 0 | RstPipeline | base | base/general/rtl/RstPipeline.vhd | 3 | -| 39 | 0 | Scrambler | base | base/general/rtl/Scrambler.vhd | 0 | -| 40 | 0 | LutRam | base | base/ram/inferred/LutRam.vhd | 1 | -| 41 | 0 | SimpleDualPortRam | base | base/ram/inferred/SimpleDualPortRam.vhd | 6 | -| 42 | 0 | TrueDualPortRam | base | base/ram/inferred/TrueDualPortRam.vhd | 3 | -| 43 | 0 | Synchronizer | base | base/sync/rtl/Synchronizer.vhd | 13 | -| 44 | 0 | SynchronizerVector | base | base/sync/rtl/SynchronizerVector.vhd | 7 | -| 45 | 0 | FirFilterTap | dsp | dsp/generic/fixed/FirFilterTap.vhd | 2 | -| 46 | 1 | AxiLiteMasterProxy | axi | axi/axi-lite/rtl/AxiLiteMasterProxy.vhd | 1 | -| 47 | 1 | AxiLiteSequencerRam | axi | axi/axi-lite/rtl/AxiLiteSequencerRam.vhd | 1 | -| 48 | 1 | AxiStreamCompact | axi | axi/axi-stream/rtl/AxiStreamCompact.vhd | 1 | -| 49 | 1 | AxiStreamConcat | axi | axi/axi-stream/rtl/AxiStreamConcat.vhd | 1 | -| 50 | 1 | AxiStreamDeMux | axi | axi/axi-stream/rtl/AxiStreamDeMux.vhd | 2 | -| 51 | 1 | AxiStreamFrameRateLimiter | axi | axi/axi-stream/rtl/AxiStreamFrameRateLimiter.vhd | 1 | -| 52 | 1 | AxiStreamMux | axi | axi/axi-stream/rtl/AxiStreamMux.vhd | 2 | -| 53 | 1 | AxiStreamRepeater | axi | axi/axi-stream/rtl/AxiStreamRepeater.vhd | 1 | -| 54 | 1 | AxiStreamResize | axi | axi/axi-stream/rtl/AxiStreamResize.vhd | 2 | -| 55 | 1 | AxiStreamShift | axi | axi/axi-stream/rtl/AxiStreamShift.vhd | 3 | -| 56 | 1 | AxiStreamTrailerAppend | axi | axi/axi-stream/rtl/AxiStreamTrailerAppend.vhd | 1 | -| 57 | 1 | AxiStreamTrailerRemove | axi | axi/axi-stream/rtl/AxiStreamTrailerRemove.vhd | 1 | -| 58 | 1 | AxiRam | axi | axi/axi4/rtl/AxiRam.vhd | 1 | -| 59 | 1 | AxiLiteToIpBus | axi | axi/bridge/rtl/AxiLiteToIpBus.vhd | 1 | -| 60 | 1 | IpBusToAxiLite | axi | axi/bridge/rtl/IpBusToAxiLite.vhd | 1 | -| 61 | 1 | AxiStreamDmaV2WriteMuxIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2WriteMuxIpIntegrator.vhd | 0 | -| 62 | 1 | Crc32PolyWrapper | base | base/crc/wrappers/Crc32PolyWrapper.vhd | 0 | -| 63 | 1 | FifoSync | base | base/fifo/rtl/inferred/FifoSync.vhd | 2 | -| 64 | 1 | RstPipelineVector | base | base/general/rtl/RstPipelineVector.vhd | 0 | -| 65 | 1 | WatchDogRst | base | base/general/rtl/WatchDogRst.vhd | 0 | -| 66 | 1 | HeartbeatWrapper | base | base/general/wrappers/HeartbeatWrapper.vhd | 0 | -| 67 | 1 | DualPortRam | base | base/ram/inferred/DualPortRam.vhd | 4 | -| 68 | 1 | RstSync | base | base/sync/rtl/RstSync.vhd | 15 | -| 69 | 1 | SynchronizerEdge | base | base/sync/rtl/SynchronizerEdge.vhd | 1 | -| 70 | 1 | BoxcarIntegrator | dsp | dsp/generic/fixed/BoxcarIntegrator.vhd | 1 | -| 71 | 1 | DspAddSub | dsp | dsp/generic/fixed/DspAddSub.vhd | 1 | -| 72 | 1 | DspComparator | dsp | dsp/generic/fixed/DspComparator.vhd | 4 | -| 73 | 1 | DspPreSubMult | dsp | dsp/generic/fixed/DspPreSubMult.vhd | 0 | -| 74 | 1 | DspSquareDiffMult | dsp | dsp/generic/fixed/DspSquareDiffMult.vhd | 0 | -| 75 | 2 | MasterAxiLiteIpIntegrator | axi | axi/axi-lite/ip_integrator/MasterAxiLiteIpIntegrator.vhd | 9 | -| 76 | 2 | SlaveAxiLiteIpIntegrator | axi | axi/axi-lite/ip_integrator/SlaveAxiLiteIpIntegrator.vhd | 32 | -| 77 | 2 | AxiLiteAsync | axi | axi/axi-lite/rtl/AxiLiteAsync.vhd | 7 | -| 78 | 2 | MasterAxiStreamIpIntegrator | axi | axi/axi-stream/ip_integrator/MasterAxiStreamIpIntegrator.vhd | 30 | -| 79 | 2 | SlaveAxiStreamIpIntegrator | axi | axi/axi-stream/ip_integrator/SlaveAxiStreamIpIntegrator.vhd | 30 | -| 80 | 2 | AxiStreamGearbox | axi | axi/axi-stream/rtl/AxiStreamGearbox.vhd | 2 | -| 81 | 2 | AxiStreamPrbsFlowCtrl | axi | axi/axi-stream/rtl/AxiStreamPrbsFlowCtrl.vhd | 1 | -| 82 | 2 | AxiStreamTap | axi | axi/axi-stream/rtl/AxiStreamTap.vhd | 1 | -| 83 | 2 | MasterAxiIpIntegrator | axi | axi/axi4/ip_integrator/MasterAxiIpIntegrator.vhd | 16 | -| 84 | 2 | SlaveAxiIpIntegrator | axi | axi/axi4/ip_integrator/SlaveAxiIpIntegrator.vhd | 9 | -| 85 | 2 | AxiStreamDmaRead | axi | axi/dma/rtl/v1/AxiStreamDmaRead.vhd | 4 | -| 86 | 2 | AxiStreamDmaV2Read | axi | axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd | 3 | -| 87 | 2 | AxiStreamDmaV2Write | axi | axi/dma/rtl/v2/AxiStreamDmaV2Write.vhd | 3 | -| 88 | 2 | FifoAsync | base | base/fifo/rtl/inferred/FifoAsync.vhd | 4 | -| 89 | 2 | Debouncer | base | base/general/rtl/Debouncer.vhd | 1 | -| 90 | 2 | PwrUpRst | base | base/general/rtl/PwrUpRst.vhd | 0 | -| 91 | 2 | SynchronizerOneShot | base | base/sync/rtl/SynchronizerOneShot.vhd | 8 | -| 92 | 2 | BoxcarFilter | dsp | dsp/generic/fixed/BoxcarFilter.vhd | 0 | -| 93 | 3 | AxiLiteAsyncIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteAsyncIpIntegrator.vhd | 0 | -| 94 | 3 | AxiLiteMasterIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteMasterIpIntegrator.vhd | 0 | -| 95 | 3 | AxiLiteMasterProxyIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteMasterProxyIpIntegrator.vhd | 0 | -| 96 | 3 | AxiLiteRegsIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteRegsIpIntegrator.vhd | 0 | -| 97 | 3 | AxiLiteRespTimerIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteRespTimerIpIntegrator.vhd | 0 | -| 98 | 3 | AxiLiteSequencerRamIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteSequencerRamIpIntegrator.vhd | 0 | -| 99 | 3 | AxiLiteSlaveIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteSlaveIpIntegrator.vhd | 0 | -| 100 | 3 | AxiLiteWriteFilterIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteWriteFilterIpIntegrator.vhd | 0 | -| 101 | 3 | AxiVersionIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiVersionIpIntegrator.vhd | 0 | -| 102 | 3 | AxiStreamCombinerIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamCombinerIpIntegrator.vhd | 0 | -| 103 | 3 | AxiStreamCompactIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamCompactIpIntegrator.vhd | 0 | -| 104 | 3 | AxiStreamConcatIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamConcatIpIntegrator.vhd | 0 | -| 105 | 3 | AxiStreamDeMuxIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd | 0 | -| 106 | 3 | AxiStreamFlushIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamFlushIpIntegrator.vhd | 0 | -| 107 | 3 | AxiStreamFrameRateLimiterIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamFrameRateLimiterIpIntegrator.vhd | 0 | -| 108 | 3 | AxiStreamGearboxIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamGearboxIpIntegrator.vhd | 0 | -| 109 | 3 | AxiStreamGearboxPackIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamGearboxPackIpIntegrator.vhd | 0 | -| 110 | 3 | AxiStreamGearboxUnpackIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamGearboxUnpackIpIntegrator.vhd | 0 | -| 111 | 3 | AxiStreamMuxIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd | 0 | -| 112 | 3 | AxiStreamPipelineIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd | 0 | -| 113 | 3 | AxiStreamPrbsFlowCtrlIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamPrbsFlowCtrlIpIntegrator.vhd | 0 | -| 114 | 3 | AxiStreamRepeaterIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamRepeaterIpIntegrator.vhd | 0 | -| 115 | 3 | AxiStreamResizeIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamResizeIpIntegrator.vhd | 0 | -| 116 | 3 | AxiStreamShiftIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamShiftIpIntegrator.vhd | 0 | -| 117 | 3 | AxiStreamSplitterIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamSplitterIpIntegrator.vhd | 0 | -| 118 | 3 | AxiStreamTapIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamTapIpIntegrator.vhd | 0 | -| 119 | 3 | AxiStreamTrailerAppendIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamTrailerAppendIpIntegrator.vhd | 0 | -| 120 | 3 | AxiStreamTrailerRemoveIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamTrailerRemoveIpIntegrator.vhd | 0 | -| 121 | 3 | MasterAxiStreamTerminateIpIntegrator | axi | axi/axi-stream/ip_integrator/MasterAxiStreamTerminateIpIntegrator.vhd | 0 | -| 122 | 3 | SlaveAxiStreamTerminateIpIntegrator | axi | axi/axi-stream/ip_integrator/SlaveAxiStreamTerminateIpIntegrator.vhd | 0 | -| 123 | 3 | AxiStreamTimer | axi | axi/axi-stream/rtl/AxiStreamTimer.vhd | 1 | -| 124 | 3 | AxiRamIpIntegrator | axi | axi/axi4/ip_integrator/AxiRamIpIntegrator.vhd | 0 | -| 125 | 3 | AxiReadPathMuxIpIntegrator | axi | axi/axi4/ip_integrator/AxiReadPathMuxIpIntegrator.vhd | 0 | -| 126 | 3 | AxiResizeIpIntegrator | axi | axi/axi4/ip_integrator/AxiResizeIpIntegrator.vhd | 0 | -| 127 | 3 | AxiWritePathMuxIpIntegrator | axi | axi/axi4/ip_integrator/AxiWritePathMuxIpIntegrator.vhd | 0 | -| 128 | 3 | AxiRateGen | axi | axi/axi4/rtl/AxiRateGen.vhd | 1 | -| 129 | 3 | AxiLiteToIpBusIpIntegrator | axi | axi/bridge/ip_integrator/AxiLiteToIpBusIpIntegrator.vhd | 0 | -| 130 | 3 | AxiToAxiLiteIpIntegrator | axi | axi/bridge/ip_integrator/AxiToAxiLiteIpIntegrator.vhd | 0 | -| 131 | 3 | IpBusToAxiLiteIpIntegrator | axi | axi/bridge/ip_integrator/IpBusToAxiLiteIpIntegrator.vhd | 0 | -| 132 | 3 | AxiLiteToDrp | axi | axi/bridge/rtl/AxiLiteToDrp.vhd | 1 | -| 133 | 3 | AxiStreamDmaReadIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaReadIpIntegrator.vhd | 0 | -| 134 | 3 | AxiStreamDmaV2ReadIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2ReadIpIntegrator.vhd | 0 | -| 135 | 3 | AxiStreamDmaV2WriteIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2WriteIpIntegrator.vhd | 0 | -| 136 | 3 | Fifo | base | base/fifo/rtl/Fifo.vhd | 6 | -| 137 | 3 | AsyncGearbox | base | base/general/rtl/AsyncGearbox.vhd | 0 | -| 138 | 3 | DebouncerWrapper | base | base/general/wrappers/DebouncerWrapper.vhd | 0 | -| 139 | 3 | SyncTrigPeriod | base | base/sync/rtl/SyncTrigPeriod.vhd | 0 | -| 140 | 3 | SynchronizerFifo | base | base/sync/rtl/SynchronizerFifo.vhd | 11 | -| 141 | 3 | SynchronizerOneShotVector | base | base/sync/rtl/SynchronizerOneShotVector.vhd | 0 | -| 142 | 3 | FirFilterSingleChannel | dsp | dsp/generic/fixed/FirFilterSingleChannel.vhd | 0 | -| 143 | 4 | AxiDualPortRam | axi | axi/axi-lite/rtl/AxiDualPortRam.vhd | 6 | -| 144 | 4 | AxiLiteRingBuffer | axi | axi/axi-lite/rtl/AxiLiteRingBuffer.vhd | 1 | -| 145 | 4 | AxiStreamTimerIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamTimerIpIntegrator.vhd | 0 | -| 146 | 4 | AxiStreamScatterGather | axi | axi/axi-stream/rtl/AxiStreamScatterGather.vhd | 1 | -| 147 | 4 | AxiRateGenIpIntegrator | axi | axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd | 0 | -| 148 | 4 | AxiMemTester | axi | axi/axi4/rtl/AxiMemTester.vhd | 1 | -| 149 | 4 | AxiLiteToDrpIpIntegrator | axi | axi/bridge/ip_integrator/AxiLiteToDrpIpIntegrator.vhd | 0 | -| 150 | 4 | SlvArraytoAxiLite | axi | axi/bridge/rtl/SlvArraytoAxiLite.vhd | 1 | -| 151 | 4 | AxiStreamDmaV2Desc | axi | axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd | 2 | -| 152 | 4 | AxiStreamDmaV2Fifo | axi | axi/dma/rtl/v2/AxiStreamDmaV2Fifo.vhd | 1 | -| 153 | 4 | SlvDelayFifo | base | base/delay/rtl/SlvDelayFifo.vhd | 0 | -| 154 | 4 | FifoCascade | base | base/fifo/rtl/FifoCascade.vhd | 8 | -| 155 | 4 | FwftCntWrapper | base | base/fifo/wrappers/FwftCntWrapper.vhd | 0 | -| 156 | 4 | SyncClockFreq | base | base/sync/rtl/SyncClockFreq.vhd | 1 | -| 157 | 4 | SyncMinMax | base | base/sync/rtl/SyncMinMax.vhd | 2 | -| 158 | 4 | SynchronizerOneShotCnt | base | base/sync/rtl/SynchronizerOneShotCnt.vhd | 1 | -| 159 | 5 | AxiDualPortRamIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd | 0 | -| 160 | 5 | AxiLiteCrossbarIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteCrossbarIpIntegrator.vhd | 0 | -| 161 | 5 | AxiLiteRingBufferIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteRingBufferIpIntegrator.vhd | 0 | -| 162 | 5 | AxiLiteFifoPop | axi | axi/axi-lite/rtl/AxiLiteFifoPop.vhd | 1 | -| 163 | 5 | AxiLiteFifoPush | axi | axi/axi-lite/rtl/AxiLiteFifoPush.vhd | 1 | -| 164 | 5 | AxiLiteFifoPushPop | axi | axi/axi-lite/rtl/AxiLiteFifoPushPop.vhd | 2 | -| 165 | 5 | AxiStreamScatterGatherIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamScatterGatherIpIntegrator.vhd | 0 | -| 166 | 5 | AxiStreamFifoV2 | axi | axi/axi-stream/rtl/AxiStreamFifoV2.vhd | 7 | -| 167 | 5 | AxiMemTesterIpIntegrator | axi | axi/axi4/ip_integrator/AxiMemTesterIpIntegrator.vhd | 0 | -| 168 | 5 | AxiReadPathFifo | axi | axi/axi4/rtl/AxiReadPathFifo.vhd | 3 | -| 169 | 5 | AxiWritePathFifo | axi | axi/axi4/rtl/AxiWritePathFifo.vhd | 3 | -| 170 | 5 | SlvArraytoAxiLiteIpIntegrator | axi | axi/bridge/ip_integrator/SlvArraytoAxiLiteIpIntegrator.vhd | 0 | -| 171 | 5 | AxiStreamDmaV2DescIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2DescIpIntegrator.vhd | 0 | -| 172 | 5 | AxiStreamDmaV2FifoIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2FifoIpIntegrator.vhd | 0 | -| 173 | 5 | AxiStreamDmaV2 | axi | axi/dma/rtl/v2/AxiStreamDmaV2.vhd | 1 | -| 174 | 5 | FifoMux | base | base/fifo/rtl/FifoMux.vhd | 0 | -| 175 | 5 | SyncTrigRate | base | base/sync/rtl/SyncTrigRate.vhd | 3 | -| 176 | 5 | SynchronizerOneShotCntVector | base | base/sync/rtl/SynchronizerOneShotCntVector.vhd | 2 | -| 177 | 5 | SyncClockFreqWrapper | base | base/sync/wrappers/SyncClockFreqWrapper.vhd | 0 | -| 178 | 5 | FirFilterMultiChannel | dsp | dsp/generic/fixed/FirFilterMultiChannel.vhd | 0 | -| 179 | 6 | AxiLiteFifoPopIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteFifoPopIpIntegrator.vhd | 0 | -| 180 | 6 | AxiLiteFifoPushIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteFifoPushIpIntegrator.vhd | 0 | -| 181 | 6 | AxiLiteFifoPushPopIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteFifoPushPopIpIntegrator.vhd | 0 | -| 182 | 6 | AxiStreamFifoV2IpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd | 0 | -| 183 | 6 | AxiStreamBatchingFifo | axi | axi/axi-stream/rtl/AxiStreamBatchingFifo.vhd | 1 | -| 184 | 6 | AxiStreamMon | axi | axi/axi-stream/rtl/AxiStreamMon.vhd | 2 | -| 185 | 6 | AxiStreamRingBuffer | axi | axi/axi-stream/rtl/AxiStreamRingBuffer.vhd | 1 | -| 186 | 6 | AxiReadPathFifoIpIntegrator | axi | axi/axi4/ip_integrator/AxiReadPathFifoIpIntegrator.vhd | 0 | -| 187 | 6 | AxiWritePathFifoIpIntegrator | axi | axi/axi4/ip_integrator/AxiWritePathFifoIpIntegrator.vhd | 0 | -| 188 | 6 | AxiReadEmulate | axi | axi/axi4/rtl/AxiReadEmulate.vhd | 1 | -| 189 | 6 | AxiRingBuffer | axi | axi/axi4/rtl/AxiRingBuffer.vhd | 1 | -| 190 | 6 | AxiWriteEmulate | axi | axi/axi4/rtl/AxiWriteEmulate.vhd | 1 | -| 191 | 6 | AxiStreamDmaV2IpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaV2IpIntegrator.vhd | 0 | -| 192 | 6 | AxiStreamDmaRingRead | axi | axi/dma/rtl/v1/AxiStreamDmaRingRead.vhd | 1 | -| 193 | 6 | AxiStreamDmaWrite | axi | axi/dma/rtl/v1/AxiStreamDmaWrite.vhd | 4 | -| 194 | 6 | SyncStatusVector | base | base/sync/rtl/SyncStatusVector.vhd | 2 | -| 195 | 6 | SyncTrigRateVector | base | base/sync/rtl/SyncTrigRateVector.vhd | 1 | -| 196 | 6 | SyncTrigRateWrapper | base | base/sync/wrappers/SyncTrigRateWrapper.vhd | 0 | -| 197 | 6 | SynchronizerOneShotCntVectorFlatWrapper | base | base/sync/wrappers/SynchronizerOneShotCntVectorFlatWrapper.vhd | 0 | -| 198 | 7 | AxiLiteRamSyncStatusVector | axi | axi/axi-lite/rtl/AxiLiteRamSyncStatusVector.vhd | 1 | -| 199 | 7 | AxiStreamBatchingFifoIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamBatchingFifoIpIntegrator.vhd | 0 | -| 200 | 7 | AxiStreamMonIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamMonIpIntegrator.vhd | 0 | -| 201 | 7 | AxiStreamRingBufferIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamRingBufferIpIntegrator.vhd | 0 | -| 202 | 7 | AxiStreamMonAxiL | axi | axi/axi-stream/rtl/AxiStreamMonAxiL.vhd | 2 | -| 203 | 7 | AxiReadEmulateIpIntegrator | axi | axi/axi4/ip_integrator/AxiReadEmulateIpIntegrator.vhd | 0 | -| 204 | 7 | AxiRingBufferIpIntegrator | axi | axi/axi4/ip_integrator/AxiRingBufferIpIntegrator.vhd | 0 | -| 205 | 7 | AxiWriteEmulateIpIntegrator | axi | axi/axi4/ip_integrator/AxiWriteEmulateIpIntegrator.vhd | 0 | -| 206 | 7 | AxiStreamDmaRingReadIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaRingReadIpIntegrator.vhd | 0 | -| 207 | 7 | AxiStreamDmaWriteIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaWriteIpIntegrator.vhd | 0 | -| 208 | 7 | AxiStreamDma | axi | axi/dma/rtl/v1/AxiStreamDma.vhd | 1 | -| 209 | 7 | AxiStreamDmaFifo | axi | axi/dma/rtl/v1/AxiStreamDmaFifo.vhd | 1 | -| 210 | 7 | AxiStreamDmaRingWrite | axi | axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd | 1 | -| 211 | 7 | SyncStatusVectorFlatWrapper | base | base/sync/wrappers/SyncStatusVectorFlatWrapper.vhd | 0 | -| 212 | 7 | SyncTrigRateVectorFlatWrapper | base | base/sync/wrappers/SyncTrigRateVectorFlatWrapper.vhd | 0 | -| 213 | 8 | AxiLiteRamSyncStatusVectorIpIntegrator | axi | axi/axi-lite/ip_integrator/AxiLiteRamSyncStatusVectorIpIntegrator.vhd | 0 | -| 214 | 8 | AxiStreamMonAxiLIpIntegrator | axi | axi/axi-stream/ip_integrator/AxiStreamMonAxiLIpIntegrator.vhd | 0 | -| 215 | 8 | AxiMonAxiL | axi | axi/axi4/rtl/AxiMonAxiL.vhd | 1 | -| 216 | 8 | AxiStreamDmaFifoIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaFifoIpIntegrator.vhd | 0 | -| 217 | 8 | AxiStreamDmaIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaIpIntegrator.vhd | 0 | -| 218 | 8 | AxiStreamDmaRingWriteIpIntegrator | axi | axi/dma/ip_integrator/AxiStreamDmaRingWriteIpIntegrator.vhd | 0 | -| 219 | 9 | AxiMonAxiLIpIntegrator | axi | axi/axi4/ip_integrator/AxiMonAxiLIpIntegrator.vhd | 0 | diff --git a/docs/_meta/rtl_phase1_queue_overrides.json b/docs/_meta/rtl_phase1_queue_overrides.json deleted file mode 100644 index 474d21dbc1..0000000000 --- a/docs/_meta/rtl_phase1_queue_overrides.json +++ /dev/null @@ -1,85 +0,0 @@ -{ - "force_include_entities": [], - "force_include_paths": [], - "deferred_subsystems": [ - { - "name": "ethernet", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "name": "protocols", - "reason": "Temporarily deferred during the current rollout so the remaining axi/ queue can be completed first." - }, - { - "name": "devices", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - }, - { - "name": "xilinx", - "reason": "Subsystem is currently dominated by vendor-heavy modules in phase 1." - } - ], - "deferred_entities": [ - { - "entity": "LutFixedDelay", - "reason": "Depends on SinglePortRamPrimitive under the current open-source flow." - } - ], - "deferred_paths": [], - "deferred_path_substrings": [ - { - "pattern": "protocols/pgp/pgp3/", - "reason": "PGP3 is intentionally deferred for now so current protocol work stays on pgp2b/pgp2fc/pgp4 and shared PGP blocks." - }, - { - "pattern": "axi/simlink/", - "reason": "Simulation support models are not part of the synthesizable phase-1 queue." - }, - { - "pattern": "/sim/", - "reason": "Simulation-only support modules are not part of the synthesizable phase-1 queue." - }, - { - "pattern": "/dummy/", - "reason": "Dummy-backed variants are deferred from the phase-1 executable queue." - }, - { - "pattern": "/altera/", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "/xilinx/", - "reason": "Vendor-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "7Series", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "UltraScale", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "UltraScale+", - "reason": "Family-specific implementation branches are deferred in phase 1." - }, - { - "pattern": "/gth", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gtp", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gty", - "reason": "GT-family implementation branches are deferred in phase 1." - }, - { - "pattern": "/gtx", - "reason": "GT-family implementation branches are deferred in phase 1." - } - ], - "preferred_paths_by_entity": {}, - "order_overrides": [] -} From 0ddb615ae47b596f72b0e8b7fb552c5538e05df5 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Sun, 3 May 2026 22:08:02 -0700 Subject: [PATCH 87/92] Linting. --- tests/protocols/srp/test_SrpV3AxiLite.py | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/protocols/srp/test_SrpV3AxiLite.py b/tests/protocols/srp/test_SrpV3AxiLite.py index 838ec3c676..b939c4d1bd 100644 --- a/tests/protocols/srp/test_SrpV3AxiLite.py +++ b/tests/protocols/srp/test_SrpV3AxiLite.py @@ -34,7 +34,6 @@ FOOTER_VERSION_MISMATCH, FOOTER_FRAME_ERROR, SRP_POSTED_WRITE, - SRP_NULL, SRP_READ, SRP_WRITE, FlatSrpAxis, From 344c16e70bbf7107a3270accfe0c6d15aebd7c8e Mon Sep 17 00:00:00 2001 From: Luca Scomparin Date: Mon, 4 May 2026 09:43:04 -0700 Subject: [PATCH 88/92] Fixed printing of floating point values --- python/surf/protocols/coaxpress/_PhantomS641.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/python/surf/protocols/coaxpress/_PhantomS641.py b/python/surf/protocols/coaxpress/_PhantomS641.py index b49fe46e3a..ec61dc70b8 100755 --- a/python/surf/protocols/coaxpress/_PhantomS641.py +++ b/python/surf/protocols/coaxpress/_PhantomS641.py @@ -300,7 +300,7 @@ def __init__(self, isPhantomS711=False, **kwargs): mode = 'RW', minimum = 1, units = '\u03BCs', - disp = '{:d}' if not isPhantomS711 else '', + disp = '{:d}' if not isPhantomS711 else None, )) self.add(pr.RemoteVariable( @@ -310,18 +310,18 @@ def __init__(self, isPhantomS711=False, **kwargs): base = pr.UIntBE if not isPhantomS711 else pr.FloatBE, mode = 'RO', units = '\u03BCs', - disp = '{:d}' if not isPhantomS711 else '', + disp = '{:d}' if not isPhantomS711 else None, )) self.add(pr.RemoteVariable( name = 'EDRTimeReg', description = 'Sets the EDR time (in microseconds). This controls the EDR reset of the sensor', offset = 0x80D0, - base = pr.UIntBE, + base = pr.UIntBE if not isPhantomS711 else pr.FloatBE, mode = 'RW', minimum = 0, units = '\u03BCs', - disp = '{:d}' if not isPhantomS711 else '', + disp = '{:d}' if not isPhantomS711 else None, )) self.add(pr.RemoteVariable( From 04d3398331f6adadc974fd9aaa2f82a4480cec4a Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 6 May 2026 15:23:21 -0700 Subject: [PATCH 89/92] Remove planning docs. --- docs/_meta/rtl_regression_handoff.md | 238 -------- docs/_meta/rtl_regression_inventory.yaml | 700 ----------------------- docs/_meta/rtl_regression_plan.md | 160 ------ docs/_meta/rtl_regression_progress.md | 346 ----------- 4 files changed, 1444 deletions(-) delete mode 100644 docs/_meta/rtl_regression_handoff.md delete mode 100644 docs/_meta/rtl_regression_inventory.yaml delete mode 100644 docs/_meta/rtl_regression_plan.md delete mode 100644 docs/_meta/rtl_regression_progress.md diff --git a/docs/_meta/rtl_regression_handoff.md b/docs/_meta/rtl_regression_handoff.md deleted file mode 100644 index de54863df3..0000000000 --- a/docs/_meta/rtl_regression_handoff.md +++ /dev/null @@ -1,238 +0,0 @@ -# SURF RTL Regression Handoff - -## Objective -- Build a repo-wide regression system for synthesizable SURF RTL. -- Keep all executable test logic in Python. -- Use `pytest + cocotb + GHDL + ruckus`. -- Keep VHDL only for wrappers, shims, and required simulation models. - -## Chosen Constraints -- Python-only test logic -- VHDL wrappers allowed -- Whole-repo target -- Vendor-heavy modules deferred in phase 1 -- Comment new Python regression code at a tutorial level, assuming the reader may be new to cocotb -- Give each Python regression the normal SURF/SLAC file header and two distinct comment layers: a module-specific `Test methodology` block under that header and tutorial-style comments in the executable code body -- Give each checked-in cocotb-facing `*IpIntegrator.vhd` wrapper the normal SURF file banner plus section comments for shim setup, DUT instantiation, and any flattening/status wiring -- For any VHDL file created or edited during this work, run `./.venv/bin/vsg` with `vsg-linter.yml`, the same config CI uses, and use `--fix`/autofix on fixable issues before moving on -- Treat VHDL packages as transitively covered unless a behavioral function/procedure needs a dedicated wrapper -- Treat stale simulator cleanup as part of task completion: after any `pytest`, cocotb, GHDL, or similar launched verification step, sweep for leftover child processes and kill them before moving on - -## Quick Resume Snapshot -- Current frontier: the axi-first pass is complete, the merged branch line includes the landed `protocols/ssi` and `protocols/pgp` waves from `pre-release`, the current Ethernet coverage spans `EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the pure-VHDL RoCEv2 quartet (`EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator`), and a broader user-directed CoaXPress pure-VHDL wave is checked in under `tests/protocols/coaxpress/`. The validated CoaXPress subset now includes the receive quartet `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, and `CoaXPressRxHsFsm`, the receive assembly `CoaXPressRx`, the transmit/bridge helpers `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressOverFiberBridgeRx`, and `CoaXPressOverFiberBridgeTx`, and the higher-level assemblies `CoaXPressTx`, `CoaXPressCore`, and `CoaXPressOverFiberBridge`. The `srp-tests` merge adds a widened SRPv3 AXI protocol matrix in `tests/protocols/srp/test_SrpV3Axi.py` covering read/write/post/null flows, response backpressure, TDEST propagation, and representative protocol-error footers through the checked-in `SrpV3AxiWrapper`. Task selection is now user-directed rather than queue-driven, so the planning docs must track the real done/open frontier directly. -- Current axi frontier: complete for the intended simulator-friendly pass in this branch snapshot; do not resume from the older stale `AxiResize` note. -- Current validated-open issues: - - The larger Ethernet families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core` remain untouched in phase 1, while the remaining RoCEv2 gap is the mixed-language bench path for the five RTL entities that instantiate generated submodules: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`. - - `EthMacRxImportXlgmii` and `EthMacTxExportXlgmii` are still placeholder no-op RTL; the checked-in tests now lock down that inert contract instead of claiming functional XLGMII support. - - The remaining CoaXPress pure-VHDL gap is now `CoaXPressConfig`. The current CoaXPress receive benches now include a dual-lane `CoaXPressRxHsFsm` step/alignment case, a dual-lane `CoaXPressRx` lane-rotation case, and event packet validation through payload size, payload words, CRC, and `EOP` before `eventAck`. The receive side is still intentionally mixed-depth: event payload is validated for parser/CRC behavior but is not exported through an application-facing payload interface, and the multi-lane assembly checks still stop short of exhaustive per-lane stress coverage. - - The latest CXPoF bridge guardrail work is now reflected at both leaf and top level: `CoaXPressOverFiberBridgeRx` covers HKP-to-payload mixing and malformed lane-placement checks for `/S/`, `/Q/`, `/T/`, and `/E/`, while `CoaXPressOverFiberBridge` covers 64-bit RX gearbox traversal for `/E/` abort/recovery, HKP-to-payload transition, and lane-0 `/Q/` no-output/recovery. Treat these as current-RTL regression guardrails rather than complete normative `/Q/`, `/E/`, or housekeeping protocol coverage. - - `tests/protocols/coaxpress/test_CoaXPressConfig.py` is intentionally checked in as a skipped investigation bench. When driven through the real SRP ingress, the current `CoaXPressConfig` / `SrpV3AxiLite` integration does not complete the request path within the bench timeout, so treat that as a likely RTL or integration defect to debug before re-enabling active assertions there. - - `tests/protocols/srp/test_SrpV3Axi.py` is now the active SRPv3 AXI regression, not just the old legacy-style posted-write/readback smoke, and it reuses the shared SRPv3 helper/model layer from `tests/protocols/srp/srp_test_utils.py`. It validates non-posted write echo/readback, posted-write no-response behavior, NULL responses, response backpressure, TDEST propagation, full-word `TKEEP`, and footer bits for version mismatch, malformed write framing, invalid alignment, invalid request size, downstream write address error, and downstream read address error. `tests/protocols/srp/test_SrpV3Core.py` now covers direct reset/idle smoke for the default `SrpV3CoreWrapper` mode plus direct 32-bit malformed-header, immediate-read-error, disabled-read/write, missing-SOF blowoff, short-write framing, and early/late read-data TLAST EOFE behavior through `CORE_DATA_BYTES_G => 4`. That narrow mode exposed and now covers two real `SrpV3Core` bugs: the response-header counter was not reset when emitting an error response from a truncated request header, and `READ_S` could miss an immediate downstream read error before any payload beat arrived. SRPv0 now has direct bridge-half coverage plus loopback coverage: `tests/protocols/srp/test_AxiLiteSrpV0.py` checks request packing and bad-response handling through `AxiLiteSrpV0Wrapper`, `tests/protocols/srp/test_SrpV0AxiLite.py` checks legacy frame parsing/status/address expansion plus downstream AXI-Lite read/write error propagation through `SrpV0AxiLiteWrapper`, and `tests/protocols/srp/test_SrpV0Loopback.py` still covers `AxiLiteSrpV0` and `SrpV0AxiLite` together through the checked-in stream loopback wrapper. `tests/protocols/srp/test_SrpV3AxiLite.py` now carries active reset/idle smoke for direct, full, and legacy-wide `DATA_BYTES_G => 32` modes, active narrow probes for the direct and full wrappers, active directed regressions for the direct and full wrappers, one active legacy-wide directed regression, and direct-wrapper `ignoreMemResp` coverage for an AXI-Lite `SLVERR` read. The duplicate wide-wrapper probe/direct cases were removed instead of kept as skipped opt-in coverage, and the old wide/narrow-only SRP wrapper files were folded into generics, leaving the default `tests/protocols/srp` run skip-free. The direct narrow `SrpV3AxiLite` issue turned out to be a bench artifact, not an RTL defect: `tests/protocols/srp/srp_test_utils.py` now holds each source beat until a sampled clock edge confirms `TREADY`, which fixes the false failure on the original `SsiFrameLimiter` bypass configuration (`SLAVE_FIFO_G => false`). The focused `tests/protocols/ssi/test_SsiFrameLimiter.py` isolation regressions remain green in both limiter modes. - - The broader flat-stream helper cleanup is now partially checked in beyond SRP. `tests/axi/utils.py` owns the shared `wait_sampled_ready()` primitive, and the flattened helper layers in `tests/protocols/ssi/ssi_test_utils.py`, `tests/protocols/srp/srp_test_utils.py`, `tests/protocols/pgp/pgp4/pgp4_test_utils.py`, `tests/protocols/coaxpress/coaxpress_test_utils.py`, `tests/ethernet/EthMacCore/ethmac_test_utils.py`, and `tests/ethernet/RawEthFramer/raw_eth_test_utils.py` now use it where appropriate instead of open-coded sampled-ready loops. Direct one-off benches that were good fits for the same cleanup now include `tests/protocols/srp/test_SrpV3Axi.py`, `tests/protocols/ssi/test_SsiResizeFifoEofe.py`, `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, `tests/protocols/coaxpress/test_CoaXPressTx.py`, `tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py`, and `tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py`. - - One subtle point from that cleanup is important for future edits: `wait_sampled_ready()` returns after the accepting clock edge has already occurred. A source must therefore advance or deassert immediately after the helper returns; leaving an extra post-handshake clock in place can create duplicate transfers or malformed streams. The current checked-in cleanup already corrected the false regressions that came from that mistake. - - The current validation subset for the flat-driver cleanup is `174 passed` across `tests/protocols/srp/test_SrpV3Axi.py`, `tests/protocols/ssi/test_SsiResizeFifoEofe.py`, the active PGP4 flat-wrapper subset, `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, `tests/protocols/coaxpress/test_CoaXPressTx.py`, `tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py`, and `tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py`. - - Remaining intentionally manual AXI-style cases after the static sweep are `tests/protocols/pgp/pgp4/test_Pgp4Rx.py`, the interleaved protocol-word capture helper in `tests/protocols/pgp/pgp4/pgp4_test_utils.py`, and the manual stress path in `tests/axi/axi_stream/test_AxiStreamScatterGather.py`. Those should only be refactored if a richer shared helper is added that can observe outputs while a source beat is still in flight. - - `tests/protocols/coaxpress/test_CoaXPressCore.py` now also carries an opt-in skipped known-issue bench for RX backpressure vs. FSM-error behavior. Enable it with `RUN_KNOWN_ISSUE_TESTS=1` and optionally shrink the load with `CXP_RX_OVERFLOW_STORM_FRAME_COUNT=`. The current local reproduction under sustained `M_DATA_TREADY=0` and repeated one-line image frames observed `RxFsmErrorCnt=2` while `RxOverflowCnt=0` at `96` frames, and a narrowing sweep showed no repro at `48` frames but a repro by `72` frames with `RxFsmErrorCnt=1` while `RxOverflowCnt=0`. That is closer to the user report than the earlier directed single-error tests and should be treated as a likely RTL defect under investigation. - - For future CoaXPress work, treat the named packet classes and control bytes in `tests/protocols/coaxpress/coaxpress_test_utils.py` as shared spec anchors, not as optional local style. Those constants were normalized against the same `CXP-001-2021` / `CXPR-008-2021` references cited in `CoaXPressPkg.vhd`. Keep the packet-layer names aligned to the spec even where current RTL ports still use legacy `eventAck` naming on the receive side: `0x07` is an event packet and `0x08` is an event acknowledgment. - - The current receive benches are intentionally mixed-depth: control-ack traffic is now driven with fuller spec-shaped framing, and `CoaXPressRxLane` now validates event payload size, payload words, CRC, and `EOP` before pulsing `eventAck`. Do not describe that as full application-facing event-payload coverage unless a payload output contract is added and covered. -- Current planning discipline: - - Use manual user-directed area selection as the active source of truth for what to work on next. - - Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the actual validated branch frontier. - - Keep the graph and queue artifacts only as historical provenance or optional analysis context; do not use them as the next-module selector unless the user explicitly opts back into queue-driven planning. - - Prefer parallel pytest for routine local validation, especially cocotb subsystem slices: `-n auto --dist=worksteal` is the default shape unless a single simulation needs serial logs or interactive debugging. -- Current wrapper discipline: - - Prefer the existing subsystem `ip_integrator/` shim layers over bespoke record flattening. - - Keep first-pass wrapper benches intentionally narrow and document any omitted branches explicitly. - - Use `start_lockstep_clocks()` when a DUT depends on truly shared clock edges. - - Prefer explicit short sim-build keys for generated-wrapper benches when case metadata would otherwise create fragile build paths. - - When a wrapper is checked in, write it like the surrounding repo HDL: include the SLAC/SURF banner and enough section comments that a new session can identify the shim, DUT, and flattening regions quickly. - - For the current Ethernet slice, the checked-in wrappers under `ethernet/EthMacCore/wrappers/`, `ethernet/RawEthFramer/wrappers/`, `ethernet/UdpEngine/wrappers/`, `ethernet/IpV4Engine/wrappers/`, and the new `ethernet/RoCEv2/wrappers/` leaf adapters are the expected cocotb surfaces. Keep using those subsystem-local wrappers rather than rebuilding record-packing logic in Python. -- Current cocotb-file discipline: - - New test files should start with the standard SURF/SLAC header block. - - The `Test methodology` block belongs directly under that header. - - In-body tutorial comments are still required; the methodology block does not replace them. - -## Session Learnings To Preserve -- Start with the smallest stable wrapper that exposes the DUT cleanly to cocotb. Reuse the existing subsystem `ip_integrator/` shims before inventing bespoke flattening or a new subsystem-local wrapper. -- Prefer checked-in subsystem-local wrappers for durable integration patterns, including simulator-hostile generic adapters. -- If a Python cocotb file is permanent enough to check in, do not leave it with a custom or abbreviated header. Use the standard repo header immediately, then add the methodology block and tutorial comments in the same first pass. -- If a wrapper is permanent enough to check in, do not leave it as a bare anonymous adapter. Add the standard SURF banner and short section comments immediately, not as a cleanup pass later. -- For AXI and AXI-Lite benches, the practical first-pass shape is usually: - - cocotb protocol master on the control/request side, - - cocotb RAM or simple protocol model on the generated/response side, - - lightweight monitors on accepted handshakes when timing or burst shape matters. -- Do not rely on final memory contents alone when the contract includes timing-visible behavior. Record accepted handshakes if the bench is supposed to prove spacing, burst length, sideband propagation, partial-last-beat strobes, or arbitration order. -- For `COMMON_CLK_G` style wrappers, use one shared clock coroutine via `start_lockstep_clocks()` when the RTL expects true shared edges rather than merely equal nominal periods. -- For first-pass wrapper benches, prove the externally visible stable path first and defer shakier simulator-sensitive branches explicitly in the docs instead of stretching one bench to cover everything. -- `AxiStreamDmaV2Read` needed a real RTL/runtime fix rather than a bench workaround: keep the bounded byte-count conversion fix in `axi/axi4/rtl/AxiPkg.vhd` and the direct terminal-mask generation in `axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd`. The current wrapper only exposes an 8-bit `TUSER`, so the observable contract in the checked-in bench is first-user propagation plus payload/keep/id/dest and descriptor return fields. -- `tests/dsp/generic/dsp_test_utils.py` is now the shared home for DSP-specific signed helpers, rolling reference models, cocotb clock-settle timing, and generated FIR wrappers. Reuse it instead of cloning DSP arithmetic or wrapper boilerplate. -- Before writing new AXI-Lite, AXI Stream, SSI, or ethernet transaction code, search the nearest subsystem `tests/` package for an existing helper module first. Future sessions should assume that a reusable helper probably already exists and should only write new transaction plumbing after confirming the local helper layer is insufficient. -- `tests/ethernet/EthMacCore/ethmac_test_utils.py` is now the shared home for the current Ethernet MAC slice: flat EMAC beat helpers, Ethernet/IPv4/UDP packet builders, checksum reference code, MAC-config byte-order helpers, and minimum-frame padding helpers. Reuse it instead of cloning packet or sideband plumbing across `EthMacCore` benches. -- Do not replace `ethernet/RoCEv2/blue-*` with local test doubles when the target boundary is `ethernet/RoCEv2/rtl`. The intended shape is one cocotb bench per RTL entity in `ethernet/RoCEv2/rtl`, with `blue-crc`, `blue-rdma`, and `blue-lib` used as real transitive dependencies where instantiated. Under the current local toolchain only `ghdl` is available, so the pure-VHDL quartet is covered now and the remaining five mixed-language entities stay open until the runner supports real VHDL+Verilog simulation. -- RoCEv2 RTL entity matrix for the next session: - - Covered now with the current GHDL-only flow: `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, `RoceConfigurator` - - Still required, but must use real generated dependencies: `EthMacCrcAxiStreamWrapperSend` -> `blue-crc/mkCrcRawAxiStreamCustomSend.v`, `EthMacCrcAxiStreamWrapperRecv` -> `blue-crc/mkCrcRawAxiStreamCustomRecv.v`, `EthMacTxRoCEv2` -> send CRC wrapper, `EthMacRxRoCEv2` -> recv CRC wrapper, `RoceEngineWrapper` -> `blue-rdma/mkAxisTransportLayer.v` plus `blue-lib/` -- `tests/ethernet/RawEthFramer/raw_eth_test_utils.py` now holds the shared raw-Ethernet helper pieces: flat app-side beat helpers, raw-Ethernet header/frame builders, and lookup-handshake utilities reused by the `RawEthFramer`, `RawEthFramerRx`, and `RawEthFramerTx` benches. -- `tests/ethernet/UdpEngine/udp_test_utils.py` is now the shared home for the UDP slice: legacy-address constants, pseudo-frame builders, DHCP option helpers, and the common cocotb bench setup for the `ArpIpTable`, `UdpEngine*`, and `UdpEngineWrapper*` wrappers. Reuse it instead of rebuilding IPv4/UDP helper glue in each test module. -- `tests/ethernet/IpV4Engine/ipv4_test_utils.py` is now the shared home for the IPv4 slice: packet/header builders and common cocotb bench setup for the `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, and `IpV4Engine*` wrappers. Reuse it instead of cloning IPv4 framing helpers across that directory. -- `tests/protocols/ssi/ssi_test_utils.py` is the shared home for SSI transaction work: flat SSI endpoints, beat/frame helpers, contiguous-frame send, receive/no-output utilities, and `SOF`/`EOFE`-aware assertions. Use it instead of open-coding SSI handshake loops or terminal-flag checks. -- `tests/protocols/coaxpress/coaxpress_test_utils.py` is now the shared home for the CoaXPress leaf/assembly slice: protocol constants, repeated-byte word builders, byte-splitting helpers, wide-word packing helpers, basic clock/reset helpers, and simple pulse-capture utilities for the raw-word wrappers. Reuse it instead of cloning CoaXPress symbol constants or one-cycle output capture loops across future CoaXPress benches. -- Keep future CoaXPress benches explicit about the boundary between normative spec behavior and current RTL-contract-only coverage. For top-level and over-fiber work in particular, the governing references are the CoaXPress protocol spec (`CXP-001-2021`) and the CoaXPress-over-Fiber bridge spec (`CXPR-008-2021`); use the shared helper names for packet classes and control symbols instead of sprinkling raw byte literals through new tests. -- Across the AXI slices, prefer the subsystem helper paths that already exist for register transactions, frame movement, and setup. In practice that means reusing helpers such as `tests/common/regression_utils.py`, the AXI/ethernet subsystem utility modules, and any nearby module-family helpers before inventing a one-off local transaction wrapper. -- The current `EthMacCore` slice is intentionally a checked-in-wrapper-first rollout, not a cocotb-generated-wrapper experiment. Keep new Ethernet work on that same pattern unless the simulator forces a very local generic adapter. -- The XGMII import/export loopback behavior differs from the GMII path when `phyReady` drops mid-traffic: the blocked frame is retained and drains after link recovery, padded to Ethernet's minimum frame size if it was short. The GMII path drops that blocked frame. Future import/export coverage should preserve that distinction instead of forcing one common expectation. -- The current `EthMacRxImportXlgmii.vhd` and `EthMacTxExportXlgmii.vhd` leaves are placeholders: they drive no data-path activity and never pulse the count/status outputs. Future work should treat functional XLGMII support as an RTL gap, not as a missing bench. -- `EthMacRxCsum` reliably raises `IPERR` on a bad IPv4 header checksum, but the checked-in wrapper contract does not currently require `EOFE` for that case. Keep the negative test aligned to the real observable contract rather than to a stronger assumption. -- The RX/TX shift benches need a small idle-plus-settle gap before changing runtime shift controls because the underlying `AxiStreamShift` samples those controls while idle. Preserve that guardrail if those benches are refactored or expanded. -- `EthMacRxBypass` compares the EtherType field in the flattened EMAC byte-lane order, not normal wire-order host integer order. In practice that means a wire EtherType like `0x9000` must be compared as `x"0090"` at the wrapper/DUT generic boundary, just as `0x88B5` appears as `x"B588"` in the existing wrappers. -- Do not leave stale simulation trees behind between tasks. If a verification command launched `pytest`, cocotb, GHDL, or wrapper executables, treat post-run process cleanup as mandatory before the next edit or test cycle. - -## Current Status -Planning is complete and implementation is well underway. The agreed direction is a Python-only executable regression framework with tiered `smoke` and `functional` coverage. Existing VHDL TBs are reference material only and should be rewritten in Python when migrated, unless a thin wrapper is still useful for cocotb access. - -The repo now has the initial handoff artifacts, a checked-in inventory scaffold at `docs/_meta/rtl_regression_inventory.yaml`, and local bootstrap helpers in `scripts/setup_regression_env.sh` plus `.vscode/tasks.json`. The first pilot modules were `FifoAsync`, `AxiStreamFifoV2`, and `AxiLiteAsync`, and the work has since moved into a graph-guided bottom-up rollout across `base/`. - -The local machine now has `ghdl`, a working `.venv`, the Python regression packages, a repo-local `ruckus` link to `~/ruckus`, and a successful `make MODULES="$PWD" import` run. Local environment bootstrap is no longer the blocker. The first shared-helper-based pilot regression now exists in `tests/base/fifo/test_FifoAsync.py` and passes locally. - -New regressions are now being organized by subsystem under `tests/`, with shared helpers in `tests/common/`. The `FifoAsync` pilot lives in `tests/base/fifo/test_FifoAsync.py`, and `AxiStreamFifoV2` now lives in `tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py`. New work should follow that package layout instead of adding more flat files under `tests/`. - -`FifoAsync` now has a validated expanded 12-case matrix, `FifoSync` has a validated expanded 11-case matrix, `Synchronizer` and `SynchronizerVector` now each have validated 6-case matrices under `tests/base/sync/`, `RstPipeline` has a validated 4-case matrix under `tests/base/general/`, `SimpleDualPortRam` has a validated 5-case matrix under `tests/base/ram/`, `FifoOutputPipeline` has a validated 5-case matrix under `tests/base/fifo/`, and `FifoWrFsm` has a validated 4-case matrix under `tests/base/fifo/`. - -The next graph-guided 10-module follow-on is also now in place: `Crc32Parallel`, `Crc32`, `CRC32Rtl`, `RstSync`, `PwrUpRst`, `SynchronizerEdge`, `SynchronizerOneShot`, `TrueDualPortRam`, `LutRam`, and `FifoRdFsm`. The combined validation command for that batch is `./.venv/bin/python -m pytest -v tests/base/crc/test_Crc32Parallel.py tests/base/crc/test_Crc32.py tests/base/crc/test_CRC32Rtl.py tests/base/sync/test_RstSync.py tests/base/general/test_PwrUpRst.py tests/base/sync/test_SynchronizerEdge.py tests/base/sync/test_SynchronizerOneShot.py tests/base/ram/test_TrueDualPortRam.py tests/base/ram/test_LutRam.py tests/base/fifo/test_FifoRdFsm.py`, and it currently passes with `38 passed`. - -The next 15-module `base/` general/delay/sync batch is now also implemented and validated: `Arbiter`, `ClockDivider`, `Debouncer`, `Gearbox`, `Heartbeat`, `Mux`, `OneShot`, `RegisterVector`, `RstPipelineVector`, `Scrambler`, `WatchDogRst`, `SlvDelay`, `SlvFixedDelay`, `SynchronizerFifo`, and `SynchronizerOneShotCnt`. The combined validation command for that batch is `./.venv/bin/python -m pytest -n 0 -q tests/base/general/test_Arbiter.py tests/base/general/test_ClockDivider.py tests/base/general/test_Debouncer.py tests/base/general/test_Gearbox.py tests/base/general/test_Heartbeat.py tests/base/general/test_Mux.py tests/base/general/test_OneShot.py tests/base/general/test_RegisterVector.py tests/base/general/test_RstPipelineVector.py tests/base/general/test_Scrambler.py tests/base/general/test_WatchDogRst.py tests/base/delay/test_SlvDelay.py tests/base/delay/test_SlvFixedDelay.py tests/base/sync/test_SynchronizerFifo.py tests/base/sync/test_SynchronizerOneShotCnt.py`, and it currently passes with `41 passed`. - -The next 10-module wrapper/integration batch is now also implemented and validated: `DspComparator`, `Fifo`, `FifoCascade`, `FifoMux`, `AsyncGearbox`, `SynchronizerOneShotVector`, `SynchronizerOneShotCntVector`, `SyncStatusVector`, `SyncTrigPeriod`, and `SyncMinMax`. The combined validation command for that batch is `./.venv/bin/python -m pytest -n 0 -q tests/dsp/generic/test_DspComparator.py tests/base/fifo/test_Fifo.py tests/base/fifo/test_FifoCascade.py tests/base/fifo/test_FifoMux.py tests/base/general/test_AsyncGearbox.py tests/base/sync/test_SynchronizerOneShotVector.py tests/base/sync/test_SynchronizerOneShotCntVector.py tests/base/sync/test_SyncStatusVector.py tests/base/sync/test_SyncTrigPeriod.py tests/base/sync/test_SyncMinMax.py`, and it currently passes with `18 passed`. - -The remaining practical non-vendor, non-dummy `base/` modules are now also implemented and validated: `MasterRamIpIntegrator`, `SlaveRamIpIntegrator`, `DualPortRam`, `SlvDelayRam`, `SlvDelayFifo`, `SyncClockFreq`, `SyncTrigRate`, and `SyncTrigRateVector`. The combined validation command for that batch is `./.venv/bin/python -m pytest -n 0 -q tests/base/general/test_MasterRamIpIntegrator.py tests/base/general/test_SlaveRamIpIntegrator.py tests/base/ram/test_DualPortRam.py tests/base/delay/test_SlvDelayRam.py tests/base/delay/test_SlvDelayFifo.py tests/base/sync/test_SyncClockFreq.py tests/base/sync/test_SyncTrigRate.py tests/base/sync/test_SyncTrigRateVector.py`, and it currently passes with `15 passed`. - -`Crc32` now covers multiple common 32-bit polynomials instead of only the default IEEE CRC-32 polynomial. That test uses a thin wrapper at `base/crc/wrappers/Crc32PolyWrapper.vhd` because the local GHDL flow rejects direct command-line overrides of the `CRC_POLY_G : slv(31 downto 0)` generic. Pytest still defaults to `-n auto --dist=worksteal` through `pytest.ini` so parameterized regressions fan out across worker processes by default. - -The project now also has a shared helper path in `tests/common/regression_utils.py` for test scaffolding, but the wrapper policy is to keep durable cocotb-facing HDL shims checked in under subsystem-local `wrappers/` or `ip_integrator/` folders. `Heartbeat` and `Debouncer` remain useful examples of very small wrappers, but new permanent generic-adapter shims should follow the checked-in subsystem-local pattern. - -`tests/common/regression_utils.py` now also includes `start_lockstep_clocks()` for DUTs whose generics assume truly common clocks in both ports. Use that helper instead of launching two same-period clocks independently when the RTL assumes shared edge identity. - -`ethernet/EthMacCore/` now has checked-in regression coverage under `tests/ethernet/EthMacCore/` for both the original leaf slice and the deeper assembly layer. The current benches cover `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, `EthMacTop`, `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, `EthMacTxFifo`, `EthMacRxBypass`, and `EthMacTxBypass`. The import/export benches now also explicitly encode the current placeholder `XLGMII` contract so future functional XLGMII RTL work will show up as a deliberate expectation change instead of an accidental gap. The current Ethernet wrappers live under `ethernet/EthMacCore/wrappers/` and should be treated as the stable cocotb-facing surfaces for further `EthMacCore` work. - -`ethernet/UdpEngine/` and `ethernet/IpV4Engine/` also received a thin-area cleanup pass on this branch. The `UdpEngine` top/wrapper benches now cover additional client/server routing paths beyond the earlier single happy-path smoke, while `IpV4Engine` now has a top-level protocol-TX path and deeper `IcmpEngine` negative/recovery coverage. The combined local validation command for that focused follow-up is `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/EthMacCore/test_EthMacRxImport.py tests/ethernet/EthMacCore/test_EthMacTxExport.py tests/ethernet/EthMacCore/test_EthMacRxBypass.py tests/ethernet/EthMacCore/test_EthMacTxBypass.py tests/ethernet/UdpEngine/test_UdpEngine.py tests/ethernet/UdpEngine/test_UdpEngineWrapper.py tests/ethernet/IpV4Engine/test_IpV4Engine.py tests/ethernet/IpV4Engine/test_IcmpEngine.py`, and it passes locally with `14 passed`. - -`ethernet/RawEthFramer/` now also has checked-in regression coverage under `tests/ethernet/RawEthFramer/`. The earlier top-level `RawEthFramer` wrapper bench is joined by direct leaf benches for `RawEthFramerRx` and `RawEthFramerTx`, plus a `RawEthFramerPair` integration bench whose wrapper cross-connects two `RawEthFramer` instances to mirror the legacy `ethernet/RawEthFramer/tb/RawEthFramerTb.vhd` topology. The validated RX leaf bench covers lookup-gated unicast decode, short-frame trim behavior, broadcast bypass, and representative reject cases. The validated TX leaf bench now covers lookup-request exposure before forwarding, successful multi-beat unicast forwarding after lookup resolution, broadcast bypass with the observed padded wire image, and zero-MAC lookup-miss drop. The successful unicast leaf case intentionally models the nonzero lookup latency that the integrated `RawEthFramer` wrapper inserts before `ack`, so keep that timing assumption if the TX bench is expanded further. - -`ethernet/UdpEngine/` now has checked-in regression coverage under `tests/ethernet/UdpEngine/` as well. The current validated set covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, all backed by checked-in wrappers under `ethernet/UdpEngine/wrappers/` and the shared helper layer in `tests/ethernet/UdpEngine/udp_test_utils.py`. - -`ethernet/IpV4Engine/` now also has checked-in regression coverage under `tests/ethernet/IpV4Engine/`. The current validated set covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, all backed by checked-in wrappers under `ethernet/IpV4Engine/wrappers/` and the shared helper layer in `tests/ethernet/IpV4Engine/ipv4_test_utils.py`. The `IgmpV2Engine` leaf bench covers power-up reports, general-query re-arming, and report suppression on matching inbound membership reports; it also documents the leaf-level stale pseudo-header bytes that are ignored by downstream `IpV4EngineTx` assembly. - -The wrapper coverage policy is now more explicit in practice: test the wrapper-specific behavior, not the full leaf matrix again. `Fifo` validated both inferred sync/async selection branches, `FifoCascade` validated public stage-vector mapping plus a curated output smoke, and `FifoMux` is currently validated only on the stable split-to-narrow path. The pack-to-wide `FifoMux` path should be treated as still open rather than silently assumed covered. - -That same wrapper-policy lesson now applies to the late `base/sync` wrappers as well. `SyncClockFreq` is stable with a checked-in subsystem wrapper, but its common-clock measurement quantizes one count above the abstract target under the current GHDL flow, so the regression checks a bounded expected range rather than an exact integer. `SyncTrigRate` is intentionally covered as a wrapper/integration bench only: it proves aligned update publication, denser-window rate growth, reset-path liveness, and strobe pulse behavior, while exact min/max pipeline semantics remain the responsibility of the dedicated `SyncMinMax` leaf test. - -At this point the practical phase-1 `base/` rollout is effectively complete. The only uncovered non-dummy `base/` module is `LutFixedDelay`, and it remains deferred because it still depends on the vendor-backed `SinglePortRamPrimitive` path. The other remaining `base/` gaps are vendor-heavy or dummy-backed variants. - -The first post-`base/` `axi/` follow-on is now in place as well. `AxiStreamPipeline` is validated under `tests/axi/axi_stream/test_AxiStreamPipeline.py` using a thin flat-port adapter at `axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd`, and `AxiLiteCrossbar` is validated under `tests/axi/axi_lite/test_AxiLiteCrossbar.py` using the existing `axi/axi-lite/tb/AxiLiteCrossbarTb.vhd` harness as a cocotb-facing shell. The combined validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamPipeline.py tests/axi/axi_lite/test_AxiLiteCrossbar.py`, and it currently passes with `4 passed`. - -For `AxiStreamPipeline`, treat the zero-stage case as a true combinational pass-through and the staged cases as wrapper-visible buffered paths. The stable expectation under the current wrapper is sink-handshake latency of `PIPE_STAGES_G + 2` clocks plus bounded reset flush behavior, not a naive one-to-one mapping from the user generic name. For `AxiLiteCrossbar`, the useful regression surface is region routing, decode-miss `DECERR` handling, and concurrent traffic through the existing cascaded harness topology rather than a broad generic sweep. - -`AxiStreamMux` is now validated under `tests/axi/axi_stream/test_AxiStreamMux.py` using a thin two-input adapter at `axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd`. The module-local validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamMux.py`, and it currently passes with `3 passed`. A small follow-on sanity run across `tests/axi/axi_stream/test_AxiStreamPipeline.py`, `tests/axi/axi_stream/test_AxiStreamMux.py`, and `tests/axi/axi_lite/test_AxiLiteCrossbar.py` also passes with `7 passed`. Keep the validated subset intentionally narrow: indexed arbitration with explicit priority plus `disableSel`, routed `TDEST`/`TID` remap under backpressure, and staged asynchronous active-low reset recovery in passthrough mode. Interleave and explicit rearbitrate branches remain open for later work. Also note the mux-specific nuance from this bench: `disableSel` is applied before the separate priority-mask generation, so a disabled higher-priority source can still suppress lower-priority requesters. - -`AxiStreamDeMux` is now validated under `tests/axi/axi_stream/test_AxiStreamDeMux.py` using a thin one-input/two-output adapter at `axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd`. The module-local validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamDeMux.py`, and it currently passes with `3 passed`. A small follow-on sanity run across `tests/axi/axi_stream/test_AxiStreamPipeline.py`, `tests/axi/axi_stream/test_AxiStreamMux.py`, `tests/axi/axi_stream/test_AxiStreamDeMux.py`, and `tests/axi/axi_lite/test_AxiLiteCrossbar.py` passes with `10 passed`. Keep the validated subset intentionally narrow: indexed decode to both outputs, exact-match routed decode under output backpressure, and dynamic-route table behavior including unmatched-destination drop plus staged asynchronous active-low reset flush. Wildcard-route patterns and larger fanout counts remain open for later work. - -The next five flat-queue modules are now also in place and validated. `AxiStreamResize` uses `axi/axi-stream/ip_integrator/AxiStreamResizeIpIntegrator.vhd` plus `tests/axi/axi_stream/test_AxiStreamResize.py`; `AxiLiteAsync` uses `axi/axi-lite/ip_integrator/AxiLiteAsyncIpIntegrator.vhd` plus `tests/axi/axi_lite/test_AxiLiteAsync.py`; `AxiLiteMaster` uses `axi/axi-lite/ip_integrator/AxiLiteMasterIpIntegrator.vhd` plus `tests/axi/axi_lite/test_AxiLiteMaster.py`; `AxiLiteToDrp` uses `axi/bridge/ip_integrator/AxiLiteToDrpIpIntegrator.vhd` plus `tests/axi/bridge/test_AxiLiteToDrp.py`; and `AxiDualPortRam` is validated through the existing `axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd` wrapper plus `tests/axi/axi_lite/test_AxiDualPortRam.py`. The five-module validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamResize.py tests/axi/axi_lite/test_AxiLiteAsync.py tests/axi/axi_lite/test_AxiLiteMaster.py tests/axi/bridge/test_AxiLiteToDrp.py tests/axi/axi_lite/test_AxiDualPortRam.py`, and it currently passes with `10 passed`. A broader AXI follow-on sanity run across pipeline, mux, demux, resize, crossbar, async, master, DRP bridge, and dual-port RAM also passes with `20 passed`. - -The next 10 generated-queue AXI modules are now also in place and validated. `AxiLiteRegs`, `AxiLiteRespTimer`, `AxiLiteSlave`, `AxiLiteWriteFilter`, and `AxiVersion` are covered under `tests/axi/axi_lite/` with thin subsystem-local wrappers in `axi/axi-lite/ip_integrator/`. `AxiStreamCombiner`, `AxiStreamFlush`, `AxiStreamGearboxPack`, `AxiStreamGearboxUnpack`, and `AxiStreamSplitter` are covered under `tests/axi/axi_stream/` with thin subsystem-local wrappers in `axi/axi-stream/ip_integrator/`. The combined validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_lite/test_AxiLiteRegs.py tests/axi/axi_lite/test_AxiLiteRespTimer.py tests/axi/axi_lite/test_AxiLiteSlave.py tests/axi/axi_lite/test_AxiLiteWriteFilter.py tests/axi/axi_lite/test_AxiVersion.py tests/axi/axi_stream/test_AxiStreamCombiner.py tests/axi/axi_stream/test_AxiStreamFlush.py tests/axi/axi_stream/test_AxiStreamGearboxPack.py tests/axi/axi_stream/test_AxiStreamGearboxUnpack.py tests/axi/axi_stream/test_AxiStreamSplitter.py`, and it currently passes with `14 passed`. - -Keep the validated subset intentionally narrow for the two most timing-sensitive wrappers. `AxiStreamResize` covers equal-width pass-through plus curated upsize/downsize cases with sideband alignment and staged reset flush. `AxiLiteMaster` covers request/ack sequencing, staggered AXI ready/valid handshakes, propagated `SLVERR` responses, and reset return to idle. `AxiDualPortRam` covers AXI round-trips, system-port visibility, byte-masked system writes, and AXI write-disable error responses through the existing wrapper. `AxiLiteAsync` is currently validated only on the stable `COMMON_CLK_G=true` wrapper path; the asynchronous reset-crossing branches remain open for later work. `AxiLiteToDrp` is currently validated only on the stable common-clock non-arbitrated path with timeout recovery; the async arbitration branch remains open for later work. - -`AxiRateGen` is now also validated under `tests/axi/axi4/test_AxiRateGen.py` using `axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd`. The module-local validation command is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiRateGen.py`, and it currently passes with `1 passed`. Keep the validated subset intentionally narrow here too: the stable `COMMON_CLK_G=true` path covers AXI-Lite register programming, timer-spaced generated AXI writes, and generated-read completion through a cocotb AXI RAM model, while the asynchronous AXI-Lite crossing branches remain open for later work. - -The remaining final 11 `axi/` modules from the axi-first pass are now also implemented and validated. The new checked-in benches are: -- `tests/axi/axi4/test_AxiReadEmulate.py` -- `tests/axi/axi4/test_AxiWriteEmulate.py` -- `tests/axi/axi4/test_AxiRingBuffer.py` -- `tests/axi/axi4/test_AxiMonAxiL.py` -- `tests/axi/axi_lite/test_AxiLiteRamSyncStatusVector.py` -- `tests/axi/axi_stream/test_AxiStreamMonAxiL.py` -- `tests/axi/dma/test_AxiStreamDmaWrite.py` -- `tests/axi/dma/test_AxiStreamDma.py` -- `tests/axi/dma/test_AxiStreamDmaFifo.py` -- `tests/axi/dma/test_AxiStreamDmaRingRead.py` -- `tests/axi/dma/test_AxiStreamDmaRingWrite.py` - -The supporting wrappers added for that batch are: -- `axi/axi4/ip_integrator/AxiReadEmulateIpIntegrator.vhd` -- `axi/axi4/ip_integrator/AxiWriteEmulateIpIntegrator.vhd` -- `axi/axi4/ip_integrator/AxiRingBufferIpIntegrator.vhd` -- `axi/axi4/ip_integrator/AxiMonAxiLIpIntegrator.vhd` -- `axi/axi-lite/ip_integrator/AxiLiteRamSyncStatusVectorIpIntegrator.vhd` -- `axi/axi-stream/ip_integrator/AxiStreamMonAxiLIpIntegrator.vhd` -- `axi/dma/ip_integrator/AxiStreamDmaWriteIpIntegrator.vhd` -- `axi/dma/ip_integrator/AxiStreamDmaFifoIpIntegrator.vhd` -- `axi/dma/ip_integrator/AxiStreamDmaIpIntegrator.vhd` -- `axi/dma/ip_integrator/AxiStreamDmaRingReadIpIntegrator.vhd` -- `axi/dma/ip_integrator/AxiStreamDmaRingWriteIpIntegrator.vhd` - -The combined validation command for that batch is `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiReadEmulate.py tests/axi/axi4/test_AxiWriteEmulate.py tests/axi/axi4/test_AxiRingBuffer.py tests/axi/axi4/test_AxiMonAxiL.py tests/axi/axi_lite/test_AxiLiteRamSyncStatusVector.py tests/axi/axi_stream/test_AxiStreamMonAxiL.py tests/axi/dma/test_AxiStreamDmaWrite.py tests/axi/dma/test_AxiStreamDma.py tests/axi/dma/test_AxiStreamDmaFifo.py tests/axi/dma/test_AxiStreamDmaRingRead.py tests/axi/dma/test_AxiStreamDmaRingWrite.py`, and it passes locally with `11 passed`. - -One small RTL fix landed during that validation pass because the new `AxiStreamDmaRingWrite` test exposed a real simulation-width hazard: `axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd` now slices `dmaAck.size` back to `RAM_DATA_WIDTH_C` before incrementing `nextAddr`. Keep that change; it is what allows the checked-in narrow wrapper to simulate cleanly under GHDL. - -A first-pass RTL instantiation graph is now checked in at `docs/_meta/rtl_instantiation_graph.md` and `docs/_meta/rtl_instantiation_graph.json`, and the same generator now also emits a path-qualified bottom-up phase-1 queue at `docs/_meta/rtl_phase1_queue.md` and `docs/_meta/rtl_phase1_queue.json`. Keep the graph and queue for provenance, but treat them as historical context rather than as the default source of truth for what to implement next. - -## Immediate Next Task -If the user keeps the focus on stream-helper cleanup rather than resuming a new subsystem, the next practical step is the remaining PGP interleaved source/capture helpers: decide whether `tests/protocols/pgp/pgp4/test_Pgp4Rx.py` and the protocol-word collector in `tests/protocols/pgp/pgp4/pgp4_test_utils.py` should stay intentionally manual or be folded into a richer shared helper that can hold a source beat through acceptance while concurrently capturing narrow output pulses. - -If the user keeps the focus on `protocols/srp`, the main review findings and high-value coverage additions are complete. The optional remaining SRP follow-up is deeper timeout or posted-write disabled-op permutations if a future change touches those RTL branches. The latest focused SRP validation command is `./.venv/bin/python -m pytest -n 0 -q tests/protocols/srp`, and it passed locally with `23 passed`. - -If the user switches back to `protocols/coaxpress`, the next practical step is either: -1. debug and re-enable the skipped `CoaXPressConfig` investigation bench, starting with the SRP-driven request path that currently fails to complete through the real `CoaXPressConfig` / `SrpV3AxiLite` integration, or -2. deepen the remaining spec-level gaps around application-facing receive-side event payload delivery, normative CXPoF `/Q/` sequence handling, fuller `/E/` semantics, and complete housekeeping protocol behavior beyond the current HKP-to-payload guardrail. - -The current CoaXPress slice was last validated with `./.venv/bin/python -m pytest -n auto --dist=worksteal -q tests/protocols/coaxpress` and passed with `17 passed, 1 skipped`; the skipped bench is still `CoaXPressConfig`. - -If the user switches back to `ethernet/RoCEv2`, the next real step is still enabling a mixed-language cocotb path for the five remaining RTL entities listed above. Keep `docs/_meta/rtl_regression_progress.md` and this handoff file aligned with the real validated subset, and do not reintroduce local stand-ins for `blue-*`. - -## Read Order -1. `docs/_meta/rtl_regression_handoff.md` -2. `docs/_meta/rtl_regression_progress.md` -3. `docs/_meta/rtl_regression_plan.md` -4. `docs/_meta/rtl_phase1_queue.md` only if historical graph output is useful for context; it is no longer the active planning driver. - -Before writing code in a fresh session: -1. Re-read the Python comment rules and the checked-in wrapper comment/header rules above. -2. If adding a permanent `*IpIntegrator.vhd`, include the standard SURF banner and section comments in the first edit, not as an afterthought. -3. If adding a Python regression, include the standard SURF/SLAC header, the `Test methodology` header block, and in-body tutorial comments in the first draft. -4. If creating or editing any VHDL file, run `./.venv/bin/vsg -c vsg-linter.yml ...` on that file set, use `--fix` when possible, and rerun the same lint command until it is clean. -5. After any step that launches `pytest`, cocotb, GHDL, or another simulator process, sweep for stale child processes and kill any leftovers before starting the next step. - -## Important Repo Facts -- New Python regressions should be organized under subsystem packages in `tests/` -- Shared Python regression helper lives in `tests/common/regression_utils.py` -- `tests/common/regression_utils.py` now supports both test-local extra VHDL source lists and generated test-local wrapper emission for wrapper-based cases -- `tests/common/regression_utils.py` also now provides `start_lockstep_clocks()` for `COMMON_CLK_G` style benches that require truly shared edges -- When starting a new test, check for nearby shared helper modules before writing any new transaction boilerplate. The expected search order is: `tests/common/`, then the current subsystem package, then closely related subsystem packages that already cover the same protocol family. -- For AXI-Lite benches, prefer existing helpers for repeated register reads/writes, environment decoding, and common bench setup rather than spelling out raw transactions in every file. -- For AXI Stream benches, prefer existing helpers for beat/frame packing, contiguous-frame driving, whole-frame receive, no-output checks, and handshake observation rather than writing custom ready/valid loops unless the DUT exposes a genuinely new contract. -- For SSI benches, prefer `tests/protocols/ssi/ssi_test_utils.py` for beat models, frame helpers, `EOFE`/`SOF` handling, and sink/source setup instead of duplicating SSI transaction utilities in a local test file. -- Default comment style for new cocotb tests has two parts: a wrapped four-bullet `Test methodology` header (`Sweep`, `Stimulus`, `Checks`, `Timing`) plus tutorial-style in-body comments that explain what each coroutine step is doing and why -- New cocotb tests should also use the standard SURF/SLAC file header, not a shortened local variant -- The methodology header should be module-specific and describe the real curated sweep, driven sequence, expected outputs/state changes, and timing checks; avoid generic boilerplate -- Keep methodology comment lines to a normal readable width in the source file -- Checked-in cocotb-facing `*IpIntegrator.vhd` files should also follow repo style: standard SLAC/SURF banner at the top and short section comments marking shim setup, DUT hookup, and flattening/status export logic -- For AXI Stream and AXI-Lite record ports, prefer the existing IP-integrator shim entities to flatten record interfaces for cocotb instead of hand-writing record packing in each wrapper -- If an AXI wrapper needs DUT-specific extra signals, keep the standard shim pair for the bus itself and only wire the extra signals manually -- More generally, if any module needs a VHDL shim layer to fit cleanly into the cocotb flow, that shim belongs in the nearest real subsystem `ip_integrator/` tree rather than under `tests/` -- Do not use generic `hdl/` buckets for cocotb-facing adapter layers; reserve those locations for genuinely different kinds of HDL support -- Many VHDL wrappers live under `*/tb/` -- The initial regression inventory lives in `docs/_meta/rtl_regression_inventory.yaml` -- The RTL instantiation graph lives in `docs/_meta/rtl_instantiation_graph.{md,json}` -- The generated path-qualified phase-1 queue lives in `docs/_meta/rtl_phase1_queue.{md,json}`, but it is now historical context only rather than the next-module source of truth -- Manual phase-1 queue deferrals and order overrides still live in `docs/_meta/rtl_phase1_queue_overrides.json`, but that file is not the active task-selection mechanism anymore -- Use `./.venv/bin/python ...` for repo-local Python commands unless the virtualenv has already been activated in the current shell; do not assume a `python` shim exists on `PATH` -- If GHDL rejects a direct command-line override for a non-scalar or real generic, prefer a generated thin test-only wrapper over simulator-specific literal workarounds or another checked-in one-off HDL shim -- If a wrapper branch is unstable under the current open-source flow, keep the validated subset narrow and record the omitted branch explicitly in the docs instead of over-claiming wrapper coverage -- Use `ps -Ao pid,ppid,stat,time,command` when needed to find stale simulation children, then terminate only the leftover run trees instead of broad process classes -- `LutFixedDelay` remains intentionally deferred because it depends on `SinglePortRamPrimitive`; do not accidentally treat the now-small remaining `base/` set as phase-1 work that still needs to be forced through -- Regenerate the graph and the phase-1 queue with `./.venv/bin/python scripts/build_rtl_instantiation_graph.py` only when historical analysis is useful or the user explicitly asks for it -- Local bootstrap entrypoint: `scripts/setup_regression_env.sh` -- Local `ruckus` is linked from `~/ruckus` - -## Resume Rule -If resuming implementation, update `docs/_meta/rtl_regression_progress.md` first. diff --git a/docs/_meta/rtl_regression_inventory.yaml b/docs/_meta/rtl_regression_inventory.yaml deleted file mode 100644 index 7b84471fd9..0000000000 --- a/docs/_meta/rtl_regression_inventory.yaml +++ /dev/null @@ -1,700 +0,0 @@ -version: 1 -last_updated: 2026-03-21 - -field_guide: - entity: "Synthesizable RTL entity name" - path: "Path to the synthesizable RTL source file" - subsystem: "High-level repo grouping used for rollout and sharding" - tier: "One of functional_python, smoke_python, wrapper_required, deferred_vendor_heavy" - status: "Implementation state for this inventory row" - priority: "Rollout priority; pilot marks the initial implementation set" - wrapper_path: "Optional VHDL wrapper/shim used for cocotb access" - python_test: "Planned or implemented Python regression entrypoint" - reference_assets: "Legacy assets worth mining for intent, not preserving as execution requirements" - notes: "Short implementation notes" - deferred_reason: "Required when tier is deferred_vendor_heavy" - -inventory_rules: - - "Every synthesizable RTL entity should eventually appear exactly once in this inventory." - - "Executable regression logic must live in Python." - - "VHDL may remain only as thin wrappers, shims, or required simulation models." - - "Legacy VHDL testbenches are reference material, not a preservation target." - - "Generic-heavy modules should prefer functional_python over smoke_python when actively implemented." - -modules: - - entity: Crc32Parallel - path: base/crc/rtl/Crc32Parallel.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/crc/test_Crc32Parallel.py - reference_assets: [] - notes: "Graph-guided CRC leaf with validated coverage for byte-width variation, registered vs direct input handling, and reset polarity/style variants against a shared Python CRC model." - deferred_reason: "" - - - entity: Crc32 - path: base/crc/rtl/Crc32.vhd - subsystem: base - tier: functional_python - status: implemented_validated_expanded - priority: phase1_low_level - wrapper_path: base/crc/wrappers/Crc32PolyWrapper.vhd - python_test: tests/base/crc/test_Crc32.py - reference_assets: [] - notes: "Graph-guided generic CRC leaf with validated coverage for IEEE CRC-32, Castagnoli, and Koopman-style 32-bit polynomial cases plus byte-width, input-register, and reset polarity/style variation. Uses a thin test-only wrapper because the local GHDL flow rejects direct command-line overrides of the 32-bit `CRC_POLY_G` `slv` generic." - deferred_reason: "" - - - entity: CRC32Rtl - path: base/crc/rtl/CRC32Rtl.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/crc/test_CRC32Rtl.py - reference_assets: [] - notes: "Legacy-compatible fixed-polynomial CRC leaf with validated baseline behavioral coverage for synchronous and asynchronous reset handling and reset polarity variation." - deferred_reason: "" - - - entity: RstSync - path: base/sync/rtl/RstSync.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_RstSync.py - reference_assets: [] - notes: "High-fanout reset synchronizer from the graph-guided leaf set. Validated coverage includes release-delay behavior, active-high vs active-low reset polarity, asynchronous vs synchronous power-on reset handling, and bypass/no-output configurations." - deferred_reason: "" - - - entity: PwrUpRst - path: base/general/rtl/PwrUpRst.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/general/test_PwrUpRst.py - reference_assets: [] - notes: "Reusable reset-generator primitive with validated coverage for counter-based startup stretch behavior, synchronous vs asynchronous reset handling, and reset polarity variation." - deferred_reason: "" - - - entity: SynchronizerEdge - path: base/sync/rtl/SynchronizerEdge.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SynchronizerEdge.py - reference_assets: [] - notes: "Graph-guided edge-detect synchronizer with validated coverage for rising/falling pulse detection through different sync depths, reset polarity/style variation, and bypass handling." - deferred_reason: "" - - - entity: SynchronizerOneShot - path: base/sync/rtl/SynchronizerOneShot.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SynchronizerOneShot.py - reference_assets: [] - notes: "Graph-guided one-shot synchronizer with validated coverage for single-pulse capture, stretched output behavior, reset polarity/style variation, active-low output mode, and bypass operation." - deferred_reason: "" - - - entity: TrueDualPortRam - path: base/ram/inferred/TrueDualPortRam.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/ram/test_TrueDualPortRam.py - reference_assets: [] - notes: "Reusable dual-port RAM primitive with validated direct cocotb coverage for read-first, write-first, and no-change modes, registered output behavior, byte-write masking, and reset polarity/style variants." - deferred_reason: "" - - - entity: LutRam - path: base/ram/inferred/LutRam.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/ram/test_LutRam.py - reference_assets: [] - notes: "Reusable LUTRAM primitive with validated coverage for combinational and registered variants, read-first/write-first/no-change behavior, multiport access, byte-write masking, and reset polarity/style variants." - deferred_reason: "" - - - entity: FifoRdFsm - path: base/fifo/rtl/inferred/FifoRdFsm.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/fifo/test_FifoRdFsm.py - reference_assets: [] - notes: "Graph-guided FIFO read-side primitive with validated coverage for standard vs FWFT behavior, block vs distributed memory modes, count progression, visible prefetch behavior, underflow-safe idle behavior, and reset polarity/style variants." - deferred_reason: "" - - - entity: SynchronizerVector - path: base/sync/rtl/SynchronizerVector.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SynchronizerVector.py - reference_assets: [] - notes: "High-reuse `base/sync` vector leaf selected from the instantiation graph. Validated curated matrix covers width variation, stage-depth latency, synchronous vs asynchronous reset handling, active-high vs active-low reset polarity, output inversion, and bypass behavior." - deferred_reason: "" - - - entity: RstPipeline - path: base/general/rtl/RstPipeline.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/general/test_RstPipeline.py - reference_assets: [] - notes: "High-reuse `base/general` reset-distribution leaf selected from the instantiation graph. Validated matrix covers stage-depth latency and `INV_RST_G` behavior; timing-only and synthesis-only generics remain intentionally out of scope." - deferred_reason: "" - - - entity: SimpleDualPortRam - path: base/ram/inferred/SimpleDualPortRam.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/ram/test_SimpleDualPortRam.py - reference_assets: [] - notes: "Graph-guided shared RAM primitive with validated direct cocotb coverage for baseline port-A write/port-B read operation, optional output register behavior, byte-write masking, and synchronous/asynchronous reset polarity variants on the read side." - deferred_reason: "" - - - entity: FifoOutputPipeline - path: base/fifo/rtl/FifoOutputPipeline.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/fifo/test_FifoOutputPipeline.py - reference_assets: [] - notes: "Graph-guided FIFO leaf with validated coverage for zero-latency passthrough, pipelined ordering, backpressure holding behavior, and synchronous/asynchronous reset polarity variants using a small FWFT-style source model." - deferred_reason: "" - - - entity: FifoWrFsm - path: base/fifo/rtl/inferred/FifoWrFsm.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/fifo/test_FifoWrFsm.py - reference_assets: [] - notes: "Graph-guided FIFO write-side primitive with validated coverage for startup readiness, count/index progression, full and overflow behavior, programmable-full threshold behavior, gray-coded async mode, and reset polarity/style variants." - deferred_reason: "" - - - entity: Synchronizer - path: base/sync/rtl/Synchronizer.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_Synchronizer.py - reference_assets: [] - notes: "High-reuse `base/sync` leaf selected from the instantiation graph. Validated curated matrix covers synchronous vs asynchronous reset handling, active-high vs active-low reset polarity, stage-depth latency, output inversion, and bypass behavior without introducing a wrapper." - deferred_reason: "" - - - entity: FifoSync - path: base/fifo/rtl/inferred/FifoSync.vhd - subsystem: base - tier: functional_python - status: implemented_validated_expanded - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/fifo/test_FifoSync.py - reference_assets: - - base/fifo/tb/FifoFwftTb.vhd - - base/fifo/tb/FwftCntTb.vhd - notes: "Bottom-up follow-on to FifoAsync. Expanded validated matrix covers FWFT vs standard mode, block vs distributed RAM, reset polarity/style variants, wider/deeper sizing, FWFT pipeline behavior, and threshold-focused cases for the synchronous implementation path." - deferred_reason: "" - - - entity: FifoAsync - path: base/fifo/rtl/inferred/FifoAsync.vhd - subsystem: base - tier: functional_python - status: implemented_validated_expanded - priority: pilot - wrapper_path: "" - python_test: tests/base/fifo/test_FifoAsync.py - reference_assets: - - base/sync/tb/SynchronizerFifoTb.vhd - notes: "Low-level async FIFO pilot. Expanded validated matrix covers FWFT vs standard mode, block vs distributed RAM, reset polarity/style variants, wider/deeper sizing, non-default sync depth, pipeline behavior, and threshold-focused cases. The matrix intentionally excludes TPD_G and INIT_G as non-behavioral here, and BYP_RAM_G because the current implementation does not exercise a separate bypass-RAM path." - deferred_reason: "" - - - entity: DspComparator - path: dsp/generic/fixed/DspComparator.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/dsp/generic/test_DspComparator.py - reference_assets: [] - notes: "First validated `dsp/` leaf in the new cocotb flow. Coverage focuses on comparator truth behavior and pipeline/reset variation rather than a large DSP-generic sweep." - deferred_reason: "" - - - entity: DspAddSub - path: dsp/generic/fixed/DspAddSub.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/dsp/generic/test_DspAddSub.py - reference_assets: - - dsp/generic/tb/DspAddSubTb.vhd - notes: "Validated signed add and subtract behavior with direct and pipelined output paths, including backpressure hold and reset clearing. The legacy VHDL bench only provided free-running stimulus, so the cocotb bench replaces it with explicit arithmetic and interface assertions." - deferred_reason: "" - - - entity: FirFilterTap - path: dsp/generic/fixed/FirFilterTap.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: generated_test_local - python_test: tests/dsp/generic/test_FirFilterTap.py - reference_assets: [] - notes: "Validated signed multiply-accumulate behavior for both generic coefficient initialization and runtime coefficient updates through a generated wrapper. The bench also checks that disabled cycles hold the previous cascade output." - deferred_reason: "" - - - entity: DspPreSubMult - path: dsp/generic/fixed/DspPreSubMult.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/dsp/generic/test_DspPreSubMult.py - reference_assets: [] - notes: "Validated signed pre-subtract multiply behavior, output hold under backpressure, and reset recovery with a direct arithmetic reference model." - deferred_reason: "" - - - entity: DspSquareDiffMult - path: dsp/generic/fixed/DspSquareDiffMult.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/dsp/generic/test_DspSquareDiffMult.py - reference_assets: [] - notes: "Validated signed square-difference multiplication, output hold under backpressure, and reset recovery with explicit Python arithmetic checks." - deferred_reason: "" - - - entity: BoxcarIntegrator - path: dsp/generic/fixed/BoxcarIntegrator.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/dsp/generic/test_BoxcarIntegrator.py - reference_assets: - - dsp/generic/tb/BoxcarIntegratorTb.vhd - notes: "Validated unsigned and signed modes, direct and registered output paths, `obAck` hold behavior, and `intCount` reconfiguration. The cocotb bench keeps the useful rolling-sum intent from the legacy bench but adds explicit interface assertions." - deferred_reason: "" - - - entity: BoxcarFilter - path: dsp/generic/fixed/BoxcarFilter.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/dsp/generic/test_BoxcarFilter.py - reference_assets: - - dsp/generic/tb/BoxcarFilterTb.vhd - notes: "Validated the integrated boxcar filter output scaling and hold behavior with a Python rolling-average model, replacing the legacy demo-style ramp-only bench with explicit output checks." - deferred_reason: "" - - - entity: FirFilterSingleChannel - path: dsp/generic/fixed/FirFilterSingleChannel.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/dsp/generic/test_FirFilterSingleChannel.py - reference_assets: - - dsp/generic/tb/FirFilterSingleChannelTb.vhd - notes: "Validated common-clock FIR data flow, sideband alignment, and AXI-Lite coefficient programming through a generated wrapper. The new bench keeps the useful coefficient-programming intent from the legacy environment but replaces its unasserted waveform stimulus with explicit filtered-output checks." - deferred_reason: "" - - - entity: FirFilterMultiChannel - path: dsp/generic/fixed/FirFilterMultiChannel.vhd - subsystem: dsp - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/dsp/generic/test_FirFilterMultiChannel.py - reference_assets: [] - notes: "Validated common-clock parallel multichannel FIR frame flow and AXI-Lite coefficient updates through a generated wrapper, using a per-channel Python FIR reference model and cocotbext-axi stream endpoints." - deferred_reason: "" - - - entity: Fifo - path: base/fifo/rtl/Fifo.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/fifo/test_Fifo.py - reference_assets: [] - notes: "Validated wrapper-focused coverage for the inferred backend only. The regression checks sync-vs-async branch selection, wrapper-level data flow, `INIT_G` forwarding, and the sync-mode `wr_data_count`/`rd_data_count` aliasing rule instead of replaying the full FIFO primitive matrix." - deferred_reason: "" - - - entity: FifoCascade - path: base/fifo/rtl/FifoCascade.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/fifo/test_FifoCascade.py - reference_assets: [] - notes: "Validated wrapper-specific coverage for inferred FWFT paths. The regression checks public `progFullVec`/`progEmptyVec` stage mapping plus a curated output smoke; it intentionally does not claim full multi-stage drain ordering under the current GHDL flow." - deferred_reason: "" - - - entity: FifoMux - path: base/fifo/rtl/FifoMux.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/fifo/test_FifoMux.py - reference_assets: [] - notes: "Validated wrapper-specific coverage currently targets the stable split-to-narrow path, including endian-aware slicing and reset-safe drain behavior. The pack-to-wide branch remains intentionally unclaimed in phase 1 because it did not surface a stable visible output in the current open-source flow." - deferred_reason: "" - - - entity: AsyncGearbox - path: base/general/rtl/AsyncGearbox.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/general/test_AsyncGearbox.py - reference_assets: [] - notes: "Validated asynchronous gearbox wrapper with a Python bit-level reference model, covering representative width conversion and reset behavior without trying to exhaust the full ratio space." - deferred_reason: "" - - - entity: SynchronizerOneShotVector - path: base/sync/rtl/SynchronizerOneShotVector.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SynchronizerOneShotVector.py - reference_assets: [] - notes: "Validated vectorized one-shot synchronizer coverage for lane independence and bypass behavior using a small curated lane matrix." - deferred_reason: "" - - - entity: SynchronizerOneShotCntVector - path: base/sync/rtl/SynchronizerOneShotCntVector.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: generated_test_local - python_test: tests/base/sync/test_SynchronizerOneShotCntVector.py - reference_assets: [] - notes: "Validated counted vector one-shot coverage using a generated test-local wrapper to flatten the array-typed output into a cocotb-friendly interface." - deferred_reason: "" - - - entity: SyncStatusVector - path: base/sync/rtl/SyncStatusVector.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/base/sync/test_SyncStatusVector.py - reference_assets: [] - notes: "Validated status-vector coverage for count/IRQ snapshot behavior. Uses a generated test-local wrapper for the vectorized count output and a lockstep shared-clock helper when `COMMON_CLK_G=true`." - deferred_reason: "" - - - entity: SyncTrigPeriod - path: base/sync/rtl/SyncTrigPeriod.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SyncTrigPeriod.py - reference_assets: [] - notes: "Validated trigger-period monitor with curated common-clock coverage for period accumulation and reset behavior." - deferred_reason: "" - - - entity: SyncMinMax - path: base/sync/rtl/SyncMinMax.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/sync/test_SyncMinMax.py - reference_assets: [] - notes: "Validated common-clock min/max snapshot behavior, including `rstStat` reseeding. Current phase-1 coverage is intentionally limited to the stable common-clock path." - deferred_reason: "" - - - entity: MasterRamIpIntegrator - path: base/general/ip_integrator/MasterRamIpIntegrator.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/general/test_MasterRamIpIntegrator.py - reference_assets: [] - notes: "Validated IP-integrator wrapper coverage for master-side write and read request forwarding, including handshake-safe addressing and shared comment-rich cocotb sequencing." - deferred_reason: "" - - - entity: SlaveRamIpIntegrator - path: base/general/ip_integrator/SlaveRamIpIntegrator.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: "" - python_test: tests/base/general/test_SlaveRamIpIntegrator.py - reference_assets: [] - notes: "Validated IP-integrator wrapper coverage for slave-side data return and write acceptance behavior using direct cocotb handshakes against the exported RAM-style ports." - deferred_reason: "" - - - entity: DualPortRam - path: base/ram/inferred/DualPortRam.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/ram/test_DualPortRam.py - reference_assets: [] - notes: "Validated inferred dual-port RAM wrapper with curated coverage for independent port readback, write-mode semantics, registered-output behavior, byte-write masking, and reset polarity variation." - deferred_reason: "" - - - entity: SlvDelayRam - path: base/delay/rtl/SlvDelayRam.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/delay/test_SlvDelayRam.py - reference_assets: [] - notes: "Validated RAM-backed delay line for configured latency, enable-hold behavior, and reset handling. The bench documents the observed GHDL-visible latency offset instead of pretending the comment-level ideal is cycle-exact." - deferred_reason: "" - - - entity: SlvDelayFifo - path: base/delay/rtl/SlvDelayFifo.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_low_level - wrapper_path: "" - python_test: tests/base/delay/test_SlvDelayFifo.py - reference_assets: [] - notes: "Validated FIFO-backed delay line with curated coverage for timestamp-ordered delayed delivery and a short-delay smoke that stays inside the stable visible behavior under the current GHDL flow." - deferred_reason: "" - - - entity: SyncClockFreq - path: base/sync/rtl/SyncClockFreq.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/base/sync/test_SyncClockFreq.py - reference_assets: [] - notes: "Validated frequency-monitor wrapper using a generated real-generic shim and lockstep shared-clock helper. The common-clock case is checked against a bounded expected range because the current GHDL-visible quantization lands one count above the abstract target." - deferred_reason: "" - - - entity: SyncTrigRate - path: base/sync/rtl/SyncTrigRate.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/base/sync/test_SyncTrigRate.py - reference_assets: [] - notes: "Validated wrapper/integration coverage for aligned update publication, denser-window rate growth, reset-path liveness, and update-strobe pulse behavior. Exact min/max pipeline semantics remain intentionally covered by the dedicated `SyncMinMax` leaf regression." - deferred_reason: "" - - - entity: SyncTrigRateVector - path: base/sync/rtl/SyncTrigRateVector.vhd - subsystem: base - tier: functional_python - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: generated_test_local - python_test: tests/base/sync/test_SyncTrigRateVector.py - reference_assets: [] - notes: "Validated vectorized trigger-rate wrapper with a generated flattening shim, per-lane rate independence checks, and shared update-strobe pulse behavior on the stable common-clock path." - deferred_reason: "" - - - entity: LutFixedDelay - path: base/delay/rtl/LutFixedDelay.vhd - subsystem: base - tier: deferred_vendor_heavy - status: deferred_phase1 - priority: phase1_deferred - wrapper_path: "" - python_test: "" - reference_assets: [] - notes: "Single remaining non-dummy `base/` gap after the phase-1 practical rollout." - deferred_reason: "Depends on `SinglePortRamPrimitive`, so the current implementation path still drags vendor-specific infrastructure back into the open-source simulation flow." - - - entity: AxiStreamFifoV2 - path: axi/axi-stream/rtl/AxiStreamFifoV2.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: pilot - wrapper_path: axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd - python_test: tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py - reference_assets: - - tests/test_AxiStreamFifoV2IpIntegrator.py - notes: "Generic-heavy AXI-Stream pilot. Reused the IP integrator wrapper and migrated the Python regression into the shared package layout. Current validated sweep covers width-conversion cases plus one VALID_THOLD=0 configuration." - deferred_reason: "" - - - entity: AxiStreamPipeline - path: axi/axi-stream/rtl/AxiStreamPipeline.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd - python_test: tests/axi/axi_stream/test_AxiStreamPipeline.py - reference_assets: - - tests/test_AxiStreamPipelineTb.py - notes: "Validated AXI-Stream helper with a thin flat-port wrapper. The curated sweep covers zero-stage pass-through, staged pipeline ordering and sideband forwarding, backpressure stability, and synchronous/asynchronous reset handling. Staged cases are checked against the wrapper-visible latency of `PIPE_STAGES_G + 2` clocks plus bounded reset flush behavior." - deferred_reason: "" - - - entity: AxiStreamMux - path: axi/axi-stream/rtl/AxiStreamMux.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd - python_test: tests/axi/axi_stream/test_AxiStreamMux.py - reference_assets: - - axi/axi-stream/tb/AxiStreamMuxTb.vhd - - axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd - notes: "Validated AXI-Stream mux coverage with a thin two-input wrapper. The curated sweep covers indexed arbitration with explicit priority plus `disableSel`, routed `TDEST`/`TID` remap under backpressure, and staged asynchronous active-low reset recovery in passthrough mode. Interleave and explicit rearbitrate branches remain intentionally open for later work." - deferred_reason: "" - - - entity: AxiStreamDeMux - path: axi/axi-stream/rtl/AxiStreamDeMux.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd - python_test: tests/axi/axi_stream/test_AxiStreamDeMux.py - reference_assets: - - axi/axi-stream/tb/AxiStreamDemuxMuxTb.vhd - - tests/test_AxiStreamDemuxMuxTb.py - notes: "Validated AXI-Stream demux coverage with a thin one-input/two-output wrapper. The curated sweep covers indexed routing, exact-match routed decode under output backpressure, and dynamic-route table behavior including unmatched-destination drop and staged asynchronous active-low reset flush. Wildcard-route patterns and larger fanout counts remain intentionally open for later work." - deferred_reason: "" - - - entity: AxiLiteCrossbar - path: axi/axi-lite/rtl/AxiLiteCrossbar.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-lite/tb/AxiLiteCrossbarTb.vhd - python_test: tests/axi/axi_lite/test_AxiLiteCrossbar.py - reference_assets: - - axi/axi-lite/tb/AxiLiteCrossbarTb.vhd - notes: "Validated AXI-Lite crossbar coverage through the existing cocotb-facing harness topology. The regression checks routed read/write correctness across the local and cascaded regions, decode-miss `DECERR` responses, and concurrent traffic without region cross-coupling." - deferred_reason: "" - - - entity: AxiLiteAsync - path: axi/axi-lite/rtl/AxiLiteAsync.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-lite/ip_integrator/AxiLiteAsyncIpIntegrator.vhd - python_test: tests/axi/axi_lite/test_AxiLiteAsync.py - reference_assets: - - axi/axi-lite/tb/AxiLiteAsyncTb.vhd - notes: "Validated AXI-Lite async-wrapper coverage with a purpose-built IP-integrator adapter. The current passing subset is intentionally narrow: common-clock pass-through plus restart/recovery on the stable wrapper path. The asynchronous reset-crossing branches remain open for later work because they were not simulator-stable enough for this initial batch." - deferred_reason: "" - - - entity: AxiStreamResize - path: axi/axi-stream/rtl/AxiStreamResize.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-stream/ip_integrator/AxiStreamResizeIpIntegrator.vhd - python_test: tests/axi/axi_stream/test_AxiStreamResize.py - reference_assets: - - axi/axi-stream/tb/AxiStreamResizeTb.vhd - notes: "Validated AXI-Stream resize coverage with a thin flat-port adapter. The curated sweep covers equal-width pass-through, 2-byte to 4-byte upsize, and 4-byte to 2-byte downsize with sideband alignment checks plus staged reset flush in the resized cases." - deferred_reason: "" - - - entity: AxiLiteMaster - path: axi/axi-lite/rtl/AxiLiteMaster.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-lite/ip_integrator/AxiLiteMasterIpIntegrator.vhd - python_test: tests/axi/axi_lite/test_AxiLiteMaster.py - reference_assets: [] - notes: "Validated AXI-Lite master coverage with a thin request/ack-to-flat-port adapter and a cocotb slave model. The first bench covers write/read request sequencing, staggered AXI ready/valid handshakes, propagated `SLVERR` responses, and reset return to idle." - deferred_reason: "" - - - entity: AxiLiteToDrp - path: axi/bridge/rtl/AxiLiteToDrp.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/bridge/ip_integrator/AxiLiteToDrpIpIntegrator.vhd - python_test: tests/axi/bridge/test_AxiLiteToDrp.py - reference_assets: [] - notes: "Validated AXI-Lite-to-DRP bridge coverage with a thin flat-port wrapper. The current passing subset is intentionally narrow: common-clock non-arbitrated write/read mapping plus timeout-driven `SLVERR` and `drpUsrRst` recovery. The async arbitration branch remains open for later work." - deferred_reason: "" - - - entity: AxiDualPortRam - path: axi/axi-lite/rtl/AxiDualPortRam.vhd - subsystem: axi - tier: wrapper_required - status: implemented_validated_initial - priority: phase1_wrapper - wrapper_path: axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd - python_test: tests/axi/axi_lite/test_AxiDualPortRam.py - reference_assets: - - axi/axi-lite/ip_integrator/AxiDualPortRamIpIntegrator.vhd - notes: "Validated AXI dual-port RAM coverage through the existing wrapper. The curated sweep covers AXI round-trips, system-port visibility of AXI writes, byte-masked system writes, and AXI write-disable `SLVERR` behavior when wrapper error responses are enabled." - deferred_reason: "" diff --git a/docs/_meta/rtl_regression_plan.md b/docs/_meta/rtl_regression_plan.md deleted file mode 100644 index 3c71ca8600..0000000000 --- a/docs/_meta/rtl_regression_plan.md +++ /dev/null @@ -1,160 +0,0 @@ -# SURF RTL Regression Plan - -## Objective -- Build a repo-wide regression system for synthesizable SURF RTL. -- Standardize on a single executable test framework so new work stays consistent. -- Make progress resumable across many context windows without re-discovery. - -## Chosen Methodology -- Python-only executable test logic. -- Primary stack: `pytest + cocotb + GHDL + ruckus`. -- Local Python commands should use the repo virtualenv interpreter (`./.venv/bin/python`) unless the virtualenv has already been explicitly activated in that shell. -- VHDL is allowed only for thin wrappers, shims, or required simulation models. -- Existing VHDL testbenches are reference material, not execution constraints. -- New Python regression code should use tutorial-style comments by default. -- New Python cocotb test files should start with the standard SURF/SLAC header block, not an ad hoc local header. -- Every Python regression should also carry a short module-specific `Test methodology` block immediately under the SLAC header comment. -- The header methodology block should use four wrapped bullets: `Sweep`, `Stimulus`, `Checks`, and `Timing`. -- The methodology bullets must describe the actual curated parameter sweep, the actual driven input sequence, the expected outputs or state changes, and the timing/latency/pulse/backpressure behavior being checked for that specific module. -- Do not use generic placeholder methodology prose; the header should tell a reader what this specific bench is proving. -- Keep methodology comment lines at a normal source width so the block is readable in the editor instead of turning into single-line paragraphs. -- Assume the reader is not already comfortable with cocotb. -- Comment the purpose of each major step in the test flow, including clock startup, reset sequencing, trigger waits, stimulus phases, and result checks. -- Treat the header methodology block and the in-body tutorial comments as separate requirements; one does not replace the other. -- Shared helpers may stay somewhat denser, but module-level tests should still explain how the Python coroutine behavior maps onto DUT behavior. -- When a DUT generic assumes truly common clocks, drive those clocks from one shared cocotb coroutine rather than starting two same-period clocks independently. -- For Python cocotb files, the minimum first-draft structure is: - - standard SURF/SLAC file header, - - module-specific `Test methodology` block, - - tutorial-style comments in the executable body. -- Checked-in cocotb-facing VHDL wrappers should follow the in-tree SURF style too: add the standard SLAC/SURF banner at the top and include brief section comments for the major adapter regions. -- For `*IpIntegrator.vhd` wrappers, the minimum expected sectioning is usually: - - bus shim section, - - DUT instantiation section, - - output/status flattening section when present. -- Do not leave permanent checked-in wrappers as uncommented bare port maps even if the logic is thin; future sessions should be able to scan the file and identify the adapter shape immediately. -- For any VHDL file you create or edit, run the `vsg` linter with the same configuration CI uses (`./.venv/bin/vsg -c vsg-linter.yml ...`) before considering the work done. -- When `vsg` reports fixable issues, use `--fix`/autofix first, then rerun the same CI-configured lint command to confirm the file is clean. - -## Scope -- Whole repo target. -- Phase 1 focuses on simulator-friendly modules. -- Vendor-heavy modules are deferred in phase 1 unless they become practical under the open-source flow. - -## Coverage Model -- `functional_python` - - Module has a Python-authored cocotb regression. -- `smoke_python` - - Module has compile/elaborate coverage only. -- `wrapper_required` - - Module needs a retained or added VHDL wrapper to expose a cocotb-friendly interface. -- `deferred_vendor_heavy` - - Module is intentionally excluded from phase 1 executable regression. - -## Package Coverage Policy -- VHDL packages are not treated as standalone executable regression targets. -- Type/constant packages are covered transitively through the modules that compile and use them. -- Behavioral package functions and procedures should be covered through DUTs that exercise them whenever practical. -- If an important package function or procedure is not well reached transitively, add a minimal VHDL wrapper and test that wrapper from Python. -- Package-helper wrappers should be tracked separately from the main synthesizable-module inventory when they are introduced. - -## Generic And Configuration Policy -- Generic-heavy modules are Python-first by default. -- Build curated configuration matrices in Python. -- Do not use naive full Cartesian products for broad generic spaces. -- Compute expected behavior dynamically in Python from the active generics. -- If simulator limitations make direct generic overrides awkward, prefer checked-in subsystem-local VHDL wrappers over ad hoc test-local copies. -- Keep checked-in wrappers thin and declarative: expose cycle-friendly or cocotb-friendly generics, map them onto the real DUT generics, and keep them beside the subsystem RTL they adapt. -- For integration wrappers, test the wrapper-specific behavior rather than replaying the full underlying leaf matrix through the wrapper. -- If only a simulator-stable subset of a wrapper is practical in phase 1, keep that subset intentionally narrow and document the unvalidated branches explicitly in the handoff/progress docs. - -## CI And Runtime Policy -- Tier-first split. -- Separate `smoke` and `functional` regression tiers. -- Shard by subsystem only if runtime requires it. -- Prefer parallel pytest for normal local validation and subsystem slices, using - `-n auto --dist=worksteal` unless a single cocotb simulation needs serial log - ordering or interactive debugging. -- Keep room for PR-vs-nightly expansion later if runtime and coverage needs justify it. -- Treat simulator process cleanup as part of every verification step, not as optional housekeeping. -- After any command that launches `pytest`, cocotb, GHDL, or another simulation runner, check for stale child processes and kill any leftovers before moving on to the next step. -- When cleanup is needed, prefer an explicit process sweep first (for example with `ps -Ao pid,ppid,stat,time,command`) so only the stale run trees are terminated. - -## Reuse Policy -- Legacy VHDL testbenches are reference material only. -- Rewrite executable test logic in Python when migrating a module into the new regression system. -- Keep VHDL wrappers only when they make Python stimulus materially cleaner. -- Do not preserve old benches purely for historical reasons. -- Before writing new cocotb transaction code, search the nearest subsystem `tests/` package for an existing `*_test_utils.py` or equivalent shared helper module and reuse it when possible. -- Prefer extending an existing helper with one more narrowly useful utility over cloning handshake loops, packet builders, frame receivers, or register-access boilerplate into each new test file. -- For AXI-Lite work, look for existing read/write helpers, setup helpers, and protocol-master wrappers first; do not hand-code repeated register transactions if the subsystem already has a stable helper path. -- For AXI Stream work, look for existing frame/beat helpers, contiguous-send helpers, receive helpers, keep-mask helpers, and handshake monitors before writing custom ready/valid loops. -- For SSI work, prefer the existing SSI helper layer for flat endpoint setup, beat modeling, frame send/receive, no-output checks, and `EOFE`/`SOF`-aware assertions instead of rebuilding SSI transaction plumbing in each bench. -- When a wrapper is needed only to adapt simulator-hostile generics, check it into the nearest subsystem-local `wrappers/` or `ip_integrator/` folder instead of hiding it under `tests/` or a generic `hdl/` bucket. -- For SURF AXI/AxiLite record ports, prefer the existing IP-integrator shim layers (`SlaveAxiStreamIpIntegrator`, `MasterAxiStreamIpIntegrator`, `SlaveAxiLiteIpIntegrator`, `MasterAxiLiteIpIntegrator`) instead of hand-writing record-to-flat unpacking in each test wrapper. -- If a DUT has extra nonstandard side signals, compose those on top of the standard AXI shim pair rather than replacing the standard flattening pattern. -- For wrapper-style protocol benches, prefer thin subsystem wrappers plus cocotb protocol masters/RAM models, and add accepted-handshake monitoring whenever timing-visible protocol behavior is part of the contract being proven. -- More generally, if a VHDL shim layer is needed to make a module practical to drive from cocotb, place that file in the nearest real subsystem `wrappers/` or `ip_integrator/` folder beside related adapter layers. -- Do not place cocotb-facing shim/adaptor VHDL under `tests/` or generic `hdl/` buckets when it is serving the same integration role as the existing `*IpIntegrator.vhd` files. -- When a wrapper is checked in under `wrappers/` or `ip_integrator/`, treat it like production repo HDL for readability purposes: keep the standard file banner and add concise section comments instead of relying on file naming alone. -- Treat checked-in Python cocotb tests the same way: use the normal repo header/comment style in the first draft instead of leaving cleanup for later. - -## Rollout Planning Policy -- Use a checked-in RTL instantiation graph to guide bottom-up rollout decisions. -- Prefer testing high-reuse leaf primitives directly before spending effort on higher-level assemblies that mostly repackage them. -- Use the graph to reduce repeated behavioral testing across adjacent hierarchy levels, not as a substitute for engineering judgment about externally visible behavior. -- Keep the graph and queue artifacts for provenance and optional analysis, but do not use them as the active day-to-day source of truth for task selection. -- The active planning driver is now manual user-directed area selection, with `docs/_meta/rtl_regression_progress.md` and `docs/_meta/rtl_regression_handoff.md` tracking what is done, what is intentionally narrow, and what remains open. -- Do not hand-maintain queue order in this plan. If the graph or queue is regenerated for analysis, treat it as secondary context unless the user explicitly switches back to queue-driven planning. - -## CoaXPress Spec Discipline -- Treat the published CoaXPress specifications as normative for future `protocols/coaxpress/` work, especially for top-level receive/transmit and over-fiber bridge benches. -- The two governing references are the CoaXPress protocol spec (`CXP-001-2021`) and the CoaXPress-over-Fiber bridge spec (`CXPR-008-2021`), matching the links already called out in `protocols/coaxpress/core/rtl/CoaXPressPkg.vhd`. -- When a CoaXPress bench encodes packet classes, control symbols, or bridge control characters, derive those values from the spec-defined names first and mirror them through shared helpers such as `tests/protocols/coaxpress/coaxpress_test_utils.py` instead of scattering raw literals. -- At the packet layer, prefer the published names even when the current RTL signal naming drifts; for example, `0x07` is an event packet and `0x08` is an event acknowledgment even though some existing RTL ports still use `eventAck` for the receive-side event indication. -- For CoaXPress image/header benches, keep the repeated-byte field encoding, header field order, endianness conversion, line-size semantics, and end-of-frame rules explicitly tied to the spec-defined rectangular image packet layout. -- For CoaXPress-over-Fiber benches, keep `/I/`, `/Q/`, `/S/`, `/T/`, and `/E/` handling, lane-0-only start/sequence semantics, and payload-vs-housekeeping start words aligned to `CXPR-008-2021`. -- If a checked-in bench intentionally validates only the current RTL contract instead of the full normative spec behavior, document that narrowed scope explicitly in the progress and handoff docs rather than implying full spec coverage. -- If a CoaXPress top-level bench has to be checked in as skipped because it exposes a likely RTL defect, keep the spec-shaped stimulus and the skip reason in-tree, and record the blocking symptom explicitly in the progress and handoff docs so the next pass resumes from the defect rather than from scratch. - -## Historical Queue Artifacts -The phase-1 simulator-friendly queue remains available as a generated bottom-up artifact, but it is now historical context rather than the active workflow. - -Retained artifacts: -- `docs/_meta/rtl_phase1_queue.md` -- `docs/_meta/rtl_phase1_queue.json` -- `docs/_meta/rtl_phase1_queue_overrides.json` - -If they are regenerated: -1. Use `./.venv/bin/python scripts/build_rtl_instantiation_graph.py`. -2. Treat the resulting graph and queue as reference material only. -3. Keep the real done/open frontier in `docs/_meta/rtl_regression_progress.md` and `docs/_meta/rtl_regression_handoff.md`. - -## Phase Breakdown -### Phase 1 -- Create the regression inventory and artifact scaffolding. -- Generate and maintain a repo-wide RTL instantiation graph to guide bottom-up prioritization. -- Establish shared Python regression helpers. -- Add smoke coverage for simulator-friendly modules. -- Add functional Python tests for the highest-value pilot modules and reusable blocks. -- Define the migration pattern for wrappers and generic-heavy modules. -- Standardize the subsystem-local checked-in wrapper pattern for real- or vector-generic leaves that need cycle-native test knobs under GHDL. - -### Phase 2 -- Deepen randomized and adversarial coverage. -- Expand curated configuration sweeps for generic-heavy modules. -- Add stronger reusable scoreboards and protocol-specific helpers. -- Revisit deferred vendor-heavy modules after phase 1 baseline stability. - -## Acceptance Criteria For Phase 1 -- The repo has a checked-in inventory and handoff system. -- New windows can recover project state by reading the handoff artifacts only. -- The Python-only regression direction is documented and stable. -- The progress and handoff artifacts stay aligned with the actual validated branch frontier instead of lagging behind completed subsystem waves. -- The smoke/functional tier split is established in the plan and progress tracking. - -## Open Questions And Deferred Decisions -- Whether PR-vs-nightly split is needed immediately or only after runtime data. -- Exact criteria for moving a vendor-heavy module out of `deferred_vendor_heavy`. -- Which user-directed subsystem slice should be taken next after the current documented frontier. -- Whether a separate tracked list of high-risk behavioral package helpers is needed once the module inventory stabilizes. diff --git a/docs/_meta/rtl_regression_progress.md b/docs/_meta/rtl_regression_progress.md deleted file mode 100644 index 44f3f043b8..0000000000 --- a/docs/_meta/rtl_regression_progress.md +++ /dev/null @@ -1,346 +0,0 @@ -# SURF RTL Regression Progress - -## Summary -- Current phase: Phase-1 implementation active -- Current subsystem: manual user-directed rollout tracking -- Current focus module: user-directed `protocols/srp` regression cleanup after merging the SRP branch onto the current `verification-2` frontier, now including direct SRPv0 bridge-half coverage, direct SRPv3 core edge coverage, and the existing loopback check. -- Last updated: 2026-05-03 - -## Current Frontier Snapshot -- Active planning rule: take the next work item from the user's manual direction, not from `docs/_meta/rtl_phase1_queue.{md,json}`. -- Manual planning note: - - The axi-first pass is complete through the previously remaining final 11 `axi/` modules. - - The current `verification-2` branch already includes the merged `pre-release` state through PR #1392, so the validated `protocols/ssi`, `protocols/pgp`, and current Ethernet waves (`EthMacCore`, `RawEthFramer`, `UdpEngine`, `IpV4Engine`, and the current pure-VHDL RoCEv2 quartet) are all part of the present branch snapshot. - - The checked-in queue and override artifacts are now retained only as historical provenance and optional graph output; they are no longer the source of truth for choosing the next area. - - Keep the done/open frontier in this progress file and in `docs/_meta/rtl_regression_handoff.md` aligned to the actual tree even if the queue artifacts are stale. - - Treat stale simulator cleanup as mandatory after every launched verification command: after any `pytest`, cocotb, GHDL, or similar simulation step, sweep for leftover child processes and kill them before starting the next task. -- Known expected-open tests on this branch: - - No simulator-friendly expected-open leaf tests remain in the currently covered `ethernet/IpV4Engine` slice, and the recent `EthMacCore` / `UdpEngine` thin-area follow-up is also checked in on this branch. - - The current `EthMac*Xlgmii` import/export leaves are still placeholder no-op RTL, so the checked-in benches document that inert contract rather than claiming functional XLGMII datapath coverage. - - The remaining Ethernet work is in the larger untouched families `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core`, plus the five still-open RoCEv2 RTL entities that depend on generated submodules: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`. -- RoCEv2 RTL target matrix: - - Covered now under the current GHDL-only flow: `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, `RoceConfigurator` - - Still required, but need real `blue-*` dependencies under a mixed-language simulator: `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, `RoceEngineWrapper` -- CoaXPress RTL target matrix: - - Covered now under the current GHDL-only flow: `CoaXPressRxWordPacker`, `CoaXPressRxLaneMux`, `CoaXPressRxLane`, `CoaXPressRxHsFsm`, `CoaXPressRx`, `CoaXPressEventAckMsg`, `CoaXPressTxLsFsm`, `CoaXPressTx`, `CoaXPressCore`, `CoaXPressOverFiberBridgeRx`, `CoaXPressOverFiberBridgeTx`, and `CoaXPressOverFiberBridge` - - Still open in the same pure-VHDL family: `CoaXPressConfig` - - Blocked bench note: `tests/protocols/coaxpress/test_CoaXPressConfig.py` is checked in as a skipped investigation bench because the real SRP-driven request path does not complete under the current `CoaXPressConfig`/`SrpV3AxiLite` integration. Treat that as a likely RTL or integration defect to debug before re-enabling active assertions on the config return path. - - Known-issue bench note: `tests/protocols/coaxpress/test_CoaXPressCore.py` now also carries an opt-in skipped investigation bench for the user-reported RX backpressure path. When enabled with `RUN_KNOWN_ISSUE_TESTS=1`, the bench drives sustained `M_DATA_TREADY=0` pressure with repeated one-line image frames and encodes the expected software-facing behavior that `RxOverflowCnt` should rise before `RxFsmErrorCnt`. The current local reproduction showed `RxFsmErrorCnt=2` while `RxOverflowCnt=0` at `96` frames, and a narrowing sweep showed no repro at `48` frames but a repro by `72` frames (`RxFsmErrorCnt=1`, `RxOverflowCnt=0`), so treat that as a likely RTL defect until narrowed or disproved. - - Spec discipline for this family: use the packet/control naming and byte values from `CXP-001-2021` and `CXPR-008-2021` via shared helpers, and keep future top-level/bridge benches explicit about whether they are proving normative spec behavior or only the currently validated RTL subset. At the packet layer, keep the published names even when current RTL signal names drift: `0x07` is an event packet and `0x08` is an event acknowledgment. - - The checked-in RX benches now use more spec-shaped control-ack framing on the wire, include a dual-lane `CoaXPressRxHsFsm` step/alignment case and a dual-lane `CoaXPressRx` lane-rotation case, and validate receive-lane event payload size, payload words, CRC, and `EOP` before `eventAck`. Keep the remaining limitation documented: event payload is validated for parser/CRC behavior, but the current RTL still exposes only `eventAck/eventTag` rather than an application-facing payload stream. - - The CXPoF bridge benches now include the recent optional-depth guardrails from `coaxpress-tests`: leaf HKP-to-payload mixing, broader malformed control-lane sweeps for `/S/`, `/Q/`, `/T/`, and `/E/`, plus top-level 64-bit RX coverage for `/E/` abort/recovery, HKP-to-payload gearbox traversal, and lane-0 `/Q/` no-output/recovery behavior. These are regression guardrails for the current RTL contract, not complete normative `/Q/`, `/E/`, or housekeeping semantics. - - Latest focused validation for the CoaXPress slice used parallel pytest: `./.venv/bin/python -m pytest -n auto --dist=worksteal -q tests/protocols/coaxpress` (`17 passed, 1 skipped`). The skipped test remains `CoaXPressConfig`. -- SRP RTL target matrix: - - Covered now under the current GHDL-only flow: `SrpV3Axi` through the checked-in `protocols/srp/wrappers/SrpV3AxiWrapper.vhd` wrapper and `tests/protocols/srp/test_SrpV3Axi.py`. - - The current SRPv3 AXI bench now validates non-posted write echo/readback, posted-write no-response behavior followed by readback, NULL header/footer behavior, response backpressure hold, TDEST propagation, full-word `TKEEP`, and footer bits for version mismatch, malformed write framing, invalid alignment, invalid request size, and downstream address error. - - `SrpV3Core` now has a direct checked-in wrapper with reset/idle smoke coverage plus a narrow 32-bit fault-injection mode for malformed-header, immediate-read-error, disabled-read/write, missing-SOF blowoff, short-write framing, and early/late read-data TLAST EOFE behavior. `tests/protocols/srp/test_SrpV3Core.py` now uses `SrpV3CoreWrapper` in both default mode and `CORE_DATA_BYTES_G => 4` mode instead of carrying a separate narrow test file. The narrow mode exposed and now covers two core-side bugs: the response-header counter was not reset when emitting an error response from a truncated request header, and `READ_S` could miss an immediate downstream read error before any payload beat arrived. - - `AxiLiteSrpV0` and `SrpV0AxiLite` are now covered directly and together. `tests/protocols/srp/test_AxiLiteSrpV0.py` uses `protocols/srp/wrappers/AxiLiteSrpV0Wrapper.vhd` to validate AXI-Lite-to-SRPv0 request field packing, read data return, bad-response `SLVERR`, and bleed/recovery behavior. `tests/protocols/srp/test_SrpV0AxiLite.py` uses `protocols/srp/wrappers/SrpV0AxiLiteWrapper.vhd` to validate multi-word write/read frames, malformed/unsupported request status failures, `EN_32BIT_ADDR_G` address expansion, and downstream AXI-Lite read/write error propagation into the legacy fail status. `tests/protocols/srp/test_SrpV0Loopback.py` still covers both bridge halves together through the checked-in stream loopback wrapper and attached RAM. - - SRPv3 AXI-Lite status: `tests/protocols/srp/test_SrpV3AxiLite.py` now has active reset/idle coverage for the direct, full, and legacy-wide `DATA_BYTES_G => 32` modes, active narrow probes (`short_frame`, `four_beat_header`, and `single_read`) for both the direct and full wrappers, active directed regressions for the direct and full wrappers, one active legacy-wide directed regression, and direct-wrapper `ignoreMemResp` coverage for an AXI-Lite `SLVERR` read. The earlier direct-wrapper failure was not an `SrpV3AxiLite` ingress RTL defect after all: the real issue was in `tests/protocols/srp/srp_test_utils.py`, where `FlatSrpAxis.send_packed_words()` treated combinational `TREADY` as immediate acceptance instead of holding each beat until a sampled clock edge confirmed the handshake. With that helper fixed and the two `SrpV3Core` fixes in place, the direct and full `SrpV3AxiLite` paths now pass on the original `SsiFrameLimiter` bypass configuration (`SLAVE_FIFO_G => false`), and the focused standalone `tests/protocols/ssi/test_SsiFrameLimiter.py` regressions remain green in both limiter modes. The duplicate wide-wrapper probe/direct cases were removed rather than kept as skipped opt-in coverage, and the old wide/narrow-only SRP wrapper files were folded into generics, so the default `tests/protocols/srp` run is now skip-free. -- Flat AXI/SSI helper cleanup status: - - `tests/axi/utils.py` now owns the shared `wait_sampled_ready()` primitive for flattened ready/valid sources that cannot use `cocotbext.axi.AxiStreamSource` directly. - - The current flat-driver users are `tests/protocols/ssi/ssi_test_utils.py`, `tests/protocols/srp/srp_test_utils.py`, `tests/protocols/pgp/pgp4/pgp4_test_utils.py`, `tests/protocols/coaxpress/coaxpress_test_utils.py`, `tests/ethernet/EthMacCore/ethmac_test_utils.py`, and `tests/ethernet/RawEthFramer/raw_eth_test_utils.py`, plus direct one-off benches in `tests/protocols/srp/test_SrpV3Axi.py`, `tests/protocols/ssi/test_SsiResizeFifoEofe.py`, `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, `tests/protocols/coaxpress/test_CoaXPressTx.py`, `tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py`, and `tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py`. - - One important cleanup correction landed during that pass: when a source now waits with `wait_sampled_ready()`, the handshake already completed on the sampled edge, so the source must advance or deassert immediately after the helper returns. The first draft left extra post-handshake clock edges in a few benches and caused false regressions; those benches were corrected before the current validation run. - - Current validation for that cleanup pass is green on `tests/protocols/srp/test_SrpV3Axi.py`, `tests/protocols/ssi/test_SsiResizeFifoEofe.py`, the PGP4 subset (`test_Pgp4Tx.py`, `test_Pgp4LiteRxLowSpeed.py`, `test_Pgp4RxCrcError.py`, `test_Pgp4RxLiteLowSpeedLane.py`, `test_Pgp4TxProtocol.py`, `test_Pgp4TxLiteProtocol.py`, `test_Pgp4TxLite.py`), `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, `tests/protocols/coaxpress/test_CoaXPressTx.py`, `tests/protocols/coaxpress/test_CoaXPressTxLsFsm.py`, and `tests/protocols/coaxpress/test_CoaXPressRxHsFsm.py` with `174 passed`. - - Remaining intentionally manual cases after the static sweep are `tests/protocols/pgp/pgp4/test_Pgp4Rx.py`, the interleaved capture helper in `tests/protocols/pgp/pgp4/pgp4_test_utils.py`, and the manual stress path in `tests/axi/axi_stream/test_AxiStreamScatterGather.py`. Those were left alone because they interleave input acceptance with concurrent output observation or deliberately spell out handshake timing inside the test body. -- Most recent reusable bench pattern: - - Prefer the existing subsystem shims, cocotb protocol masters/RAM models, and explicit handshake monitoring when the behavior under test includes timing-visible protocol details. - - For `protocols/pgp`, keep the first pass family-oriented: shared Python helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family subpackages under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, and `tests/protocols/pgp/pgp4/`, thin wrapper-level loopback benches for the core lane/core surfaces, direct register benches for the AXI management blocks, and checked-in low-speed wrappers whose benches assert wrapper-visible lock/config behavior unless the serialized payload-recovery path is explicitly proven. `pgp3` stays documented and organized, but it is intentionally out of the near-term rollout plan on this branch. The reusable helper now also tolerates the trailing zero padding that appears on short odd-byte frames when the older 16-bit SSI/PGP2 wrappers return compressed-keep traffic through `cocotbext.axi`. - - For `ethernet`, keep using the checked-in wrappers under `ethernet/*/wrappers/` plus the shared helper layers in `tests/ethernet/EthMacCore/ethmac_test_utils.py`, `tests/ethernet/RawEthFramer/raw_eth_test_utils.py`, `tests/ethernet/UdpEngine/udp_test_utils.py`, and `tests/ethernet/IpV4Engine/ipv4_test_utils.py`. The practical first-pass shape is flat EMAC/app beat wrappers with explicit sideband bits, curated functional slices instead of exhaustive generic sweeps, and dedicated pair/integration wrappers only where an old VHDL bench contributes a topology worth preserving. - - For `protocols/coaxpress`, the practical first-pass shape is subsystem-local wrappers under `protocols/coaxpress/core/wrappers/` plus a small helper layer in `tests/protocols/coaxpress/coaxpress_test_utils.py`. Keep the input side raw and cycle-native where the DUT already consumes protocol words directly, and only flatten the observable AXI-stream outputs or handshaked lane arrays that cocotb actually needs to inspect. - - The checked-in CoaXPress helper now carries named spec constants for packet classes and bridge control characters. Reuse those names instead of introducing more raw `0x01`/`0x02`/`0x07`-style literals in future benches. - -## Status -| Subsystem | Inventory | Smoke | Functional | Notes | -| --- | --- | --- | --- | --- | -| Cross-cutting infrastructure | started | not started | started | Shared helper structure now lives in `tests/common/regression_utils.py`; pytest now defaults to `xdist` parallel execution via `pytest.ini`; the checked-in graph/queue artifacts under `docs/_meta/` are retained for provenance, while `rtl_regression_progress.md` and `rtl_regression_handoff.md` are the active planning inputs | -| `base` | started | not started | started | Validated low-level regressions now exist for `FifoAsync`, `FifoSync`, `FifoOutputPipeline`, `FifoWrFsm`, `FifoRdFsm`, `Fifo`, `FifoCascade`, `FifoMux`, `Synchronizer`, `SynchronizerVector`, `SynchronizerEdge`, `SynchronizerOneShot`, `SynchronizerFifo`, `SynchronizerOneShotCnt`, `SynchronizerOneShotVector`, `SynchronizerOneShotCntVector`, `SyncStatusVector`, `SyncTrigPeriod`, `SyncMinMax`, `SyncClockFreq`, `SyncTrigRate`, `SyncTrigRateVector`, `RstSync`, `RstPipeline`, `RstPipelineVector`, `PwrUpRst`, `Arbiter`, `ClockDivider`, `Debouncer`, `Gearbox`, `AsyncGearbox`, `Heartbeat`, `Mux`, `OneShot`, `RegisterVector`, `WatchDogRst`, `Scrambler`, `MasterRamIpIntegrator`, `SlaveRamIpIntegrator`, `SimpleDualPortRam`, `DualPortRam`, `TrueDualPortRam`, `LutRam`, `SlvDelay`, `SlvFixedDelay`, `SlvDelayRam`, `SlvDelayFifo`, `Crc32Parallel`, `Crc32`, and `CRC32Rtl` under subsystem-organized `tests/base/` packages. Remaining uncovered `base/` entities are vendor-heavy, dummy-backed, or `LutFixedDelay`, which is deferred because it depends on `SinglePortRamPrimitive`. | -| `dsp` | started | not started | started | The planned `dsp/generic/fixed` leaf batch is now validated under `tests/dsp/generic/`: `FirFilterTap`, `DspAddSub`, `DspComparator`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`. Shared DSP helpers now live in `tests/dsp/generic/dsp_test_utils.py`, and the legacy VHDL benches under `dsp/generic/tb/` were treated as behavioral reference material rather than as execution constraints. | -| `axi` | started | not started | started | The axi-first pass is now complete for the simulator-friendly queue. The final locally validated batch adds `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`, with a combined `11 passed` validation run on 2026-03-27. Added checked-in subsystem wrappers under `axi/axi4/ip_integrator/`, `axi/axi-lite/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/` for those benches. `AxiStreamFifoV2` now has an expanded `10 passed` wrapper regression under `tests/axi/axi_stream/` covering async and sync width conversion, metadata truncation, `VALID_THOLD` frame-ready and burst-release modes, dynamic pause-threshold behavior, `CASCADE_SIZE=2`, and the `S_HAS_TREADY=0` pause-only source-side path. `AxiResize` now passes its equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` wrapper regression on this branch after the read-hold RTL fix. `AxiLiteAsync`, `AxiLiteToDrp`, and `AxiRateGen` still keep intentionally narrow common-clock subsets while the more timing-sensitive async AXI-Lite crossing branches remain open. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` still keep intentionally narrow first-pass subsets. `AxiStreamDmaV2Read` is now validated with a two-case wrapper regression covering both aligned and short terminal-beat reads after fixing bounded byte-count conversion in `AxiPkg` and terminal-mask generation in `AxiStreamDmaV2Read`. | -| `protocols` | started | not started | started | `protocols/line-codes` is now validated under `tests/protocols/line_codes/` with shared Python helper coverage for `LineCode8b10b`, `LineCode10b12b`, and `LineCode12b14b`, plus package-level `Code8b10b`, `Code10b12b`, and `Code12b14b` cocotb coverage. The package benches preserve explicit disparity-seed sweeps, and the 12b14b package bench also preserves its historical training/transition sequences. `protocols/ssi/` now has checked-in cocotb coverage for `SsiInsertSof`, `SsiIbFrameFilter`, `SsiObFrameFilter`, and `SsiFifo`, plus first-pass coverage for `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiFrameLimiter`, `SsiIncrementingTx`, `SsiAxiLiteMaster`, and a traffic-smoke `SsiDbgTap`, all backed by the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` and checked-in wrappers under `protocols/ssi/wrappers/`. The SSI helper layer now uses handshake-based frame receive/capture so contiguous multi-beat traffic is observed correctly, the checked-in benches now carry the tutorial-style comment pass and shared setup cleanup, `SsiObFrameFilter` now covers the cached-last-user `VALID_THOLD_G=0` malformed/drop path plus a pipelined `PIPE_STAGES_G=2` pass-through case, and the remaining SSI gaps are optional deeper branch work rather than blockers. `protocols/pgp/` now has shared helper coverage in `tests/protocols/pgp/pgp_test_utils.py`, family-organized benches under `tests/protocols/pgp/pgp2b/`, `tests/protocols/pgp/pgp2fc/`, `tests/protocols/pgp/pgp3/`, `tests/protocols/pgp/pgp4/`, and `tests/protocols/pgp/shared/`, checked-in wrappers for the direct-wrapper cases, validated loopback benches for `Pgp2bLane`, `Pgp2fcLane`, `Pgp4Core`, `Pgp4CoreLite`, and `Pgp3Core`, direct wrapper benches for `Pgp2bAxi`, `Pgp2fcAxi`, `Pgp4AxiL`, `Pgp4TxLite`, `Pgp4Tx`, `Pgp4RxLiteLowSpeedReg`, the remaining non-vendor `pgp4/core/rtl` leaves (`Pgp4Rx`, `Pgp4RxEb`, `Pgp4RxProtocol`, `Pgp4TxLiteProtocol`, `Pgp4TxProtocol`, `Pgp4RxLiteLowSpeedLane`, and `Pgp4LiteRxLowSpeed`), and the shared VC FIFOs (`PgpRxVcFifo` and `PgpTxVcFifo`). The two shared FIFO benches now cover async link-up pass-through plus the family-specific control behavior: `PgpRxVcFifo` covers link-down blowoff and exported pause assertion under output backpressure, while `PgpTxVcFifo` covers link-down drop and mid-frame flush/truncation. The two `pgp4` low-speed receive leaves now have dedicated guardrail benches around lock/config behavior through checked-in wrappers rather than the earlier smoke-only placeholders, while `pgp2b/core/rtl` and `pgp2fc/core/rtl` both have leaf-wrapper cocotb coverage across every non-vendor entity. `pgp2fc` now also has fixed-latency fast-control coverage at three levels: `Pgp2fcTxPhy` checks deterministic FC entry timing from the quiescent training path plus active cell and empty-path contexts, `Pgp2fcTx` checks scheduler-context invariance, and `Pgp2fcLane` loopback calibrates `TX_FC_VALID -> RX_FC_VALID` latency once and proves that the same cycle delta holds while user frame traffic is active. The current `pgp2b` and `pgp2fc` leaf suite is intentionally mixed-depth: `Pgp2bTxSched`, `Pgp2bTxPhy`, `Pgp2bTx`, `CRC7Rtl`, `Pgp2fcAlignmentChecker`, `Pgp2fcTxSched`, `Pgp2fcTxPhy`, and `Pgp2fcTx` keep directed behavioral checks, while the remaining RX, cell, and alignment-control benches currently hold first-pass quiescent or guardrail assertions until later wrapper expansion exposes enough state for deeper deterministic traffic. `protocols/coaxpress/` now has a broader pure-VHDL staged rollout under `tests/protocols/coaxpress/` backed by checked-in wrappers in `protocols/coaxpress/core/wrappers/`: the receive leaves now cover offset-start packing, lane rotation, stream/config/event/heartbeat decode, rectangular-header framing, and a dual-lane `CoaXPressRxHsFsm` step/alignment case; the receive assembly now covers both the original one-lane integration path and a dual-lane `CoaXPressRx` lane-rotation case; the transmit/bridge leaf benches cover `CoaXPressEventAckMsg` serialization under backpressure, `CoaXPressTxLsFsm` idle/config/trigger cadence across both implemented low-speed rates, `CoaXPressOverFiberBridgeTx` CXPoF start/payload/terminate formatting plus partial-lane fill behavior, and `CoaXPressOverFiberBridgeRx` CXPoF start-word decode plus HKP and negative lane-placement guardrails; and the higher-level assembly benches cover `CoaXPressTx` config/event-ack arbitration plus software-trigger injection across the cfg-to-tx clock crossing and `CoaXPressOverFiberBridge` top-level 32b/64b gearbox integration on both the TX and RX sides. The current CoaXPress subset remains intentionally staged: it normalizes packet/control literals onto named spec constants in `tests/protocols/coaxpress/coaxpress_test_utils.py`, leaves `CoaXPressConfig` as the remaining pure-VHDL blocker, and still documents receive-side event parsing and normative CXPoF `/Q/`/`/E/` handling as open spec-depth gaps rather than claiming full protocol compliance. | -| `ethernet` | started | not started | started | `tests/ethernet/EthMacCore/` now covers both the original leaf slice and the deeper assembly benches for `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo`, plus direct `EthMacRxBypass` / `EthMacTxBypass` leaf benches and import/export sweeps that now explicitly include the current placeholder `XLGMII` contract. `tests/ethernet/RawEthFramer/` covers the `RawEthFramer` leaves/top/pair slice, including the successful multi-beat `RawEthFramerTx` unicast-forwarding path after lookup resolution. `tests/ethernet/UdpEngine/` covers `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`, with the top/wrapper benches now widened across client/server routing paths. `tests/ethernet/IpV4Engine/` covers `ArpEngine`, `IcmpEngine`, `IgmpV2Engine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`, and the top/leaf benches now also include protocol-TX and deeper ICMP reject/recovery coverage. `tests/ethernet/RoCEv2/` currently covers the pure-VHDL RTL entities `EthMacPrepareForICrc`, `EthMacRxCheckICrc`, `RoceResizeAndSwap`, and `RoceConfigurator` through checked-in wrappers under `ethernet/RoCEv2/wrappers/`. The remaining RoCEv2 RTL entities that still need cocotb benches are `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`, and those should use the real generated `blue-*` dependencies rather than local stand-ins. The explicit Ethernet caveats are now the larger untouched families such as `GigEthCore`, `TenGigEthCore`, `XauiCore`, `XlauiCore`, and `Caui4Core`, the mixed-language RoCEv2 bench gap listed above, plus the still-placeholder `EthMac*Xlgmii` RTL. | -| `devices` | not started | not started | not started | Many vendor-heavy cases | -| `xilinx` | not started | not started | not started | Many vendor-heavy cases | - -## Completed Decisions -- Use Python-only executable test logic. -- Use `pytest + cocotb + GHDL + ruckus` as the primary stack. -- Keep VHDL only for wrappers, shims, and required simulation models. -- Comment new Python regression code at a tutorial level so readers who are new to cocotb can follow the flow in-place. -- Whole repo is the long-term target. -- Phase 1 focuses on simulator-friendly modules. -- Vendor-heavy modules are deferred in phase 1. -- Generic-heavy modules are Python-first. -- Use curated configuration matrices instead of full Cartesian products. -- Keep a tier-first CI model: `smoke` and `functional`. -- Rewrite legacy VHDL TB logic in Python rather than preserving it by default. -- Keep wrappers only when they make Python interaction cleaner. -- Run the `vsg` linter with CI's `vsg-linter.yml` settings on any created or edited VHDL files, and use autofix before doing manual cleanup when possible. -- Treat VHDL packages as transitively covered unless a behavioral function/procedure needs a dedicated wrapper. -- Treat `docs/_meta/rtl_regression_progress.md` and `docs/_meta/rtl_regression_handoff.md` as the living planning inputs, and treat the checked-in queue artifacts as archival unless the user explicitly asks to resume queue-driven planning. - -## Completed Work Items -- Surveyed repo structure and existing verification flow. -- Reviewed existing Python regressions and representative VHDL testbenches. -- Merged the current `pre-release` branch into `verification-2`, bringing the already-landed `protocols/ssi` and `protocols/pgp` regression waves into the same branch line as the earlier `ethernet/EthMacCore` slice. -- Re-added `dsp/` to the generated phase-1 queue scope so DSP work is tracked by the same bottom-up planner as the other simulator-friendly subsystems. -- Implemented `tests/dsp/generic/test_DspAddSub.py`. -- Validated `tests/dsp/generic/test_DspAddSub.py` locally with `./.venv/bin/python -m pytest -n 0 -q tests/dsp/generic/test_DspAddSub.py`. -- Added shared DSP helpers in `tests/dsp/generic/dsp_test_utils.py` for signed packing/truncation, rolling reference models, cocotb clock-settle timing, and generated FIR wrappers. -- Extended `tests/common/regression_utils.py` so generated-wrapper benches can use short explicit sim-build keys instead of overloading generic/extra-env strings into fragile build paths. -- Implemented `tests/dsp/generic/test_FirFilterTap.py`, `tests/dsp/generic/test_DspPreSubMult.py`, `tests/dsp/generic/test_DspSquareDiffMult.py`, `tests/dsp/generic/test_BoxcarIntegrator.py`, `tests/dsp/generic/test_BoxcarFilter.py`, `tests/dsp/generic/test_FirFilterSingleChannel.py`, and `tests/dsp/generic/test_FirFilterMultiChannel.py`. -- Fixed DSP RTL issues exposed by the new benches in `dsp/generic/fixed/FirFilterTap.vhd`, `dsp/generic/fixed/BoxcarIntegrator.vhd`, and `dsp/generic/fixed/FirFilterSingleChannel.vhd`. -- Validated the full planned DSP leaf batch locally with `./.venv/bin/python -m pytest -n 0 -q tests/dsp/generic` (`15 passed`). -- Compared `cocotb + pytest`, `VUnit`, and `OSVVM` for SURF. -- Chose Python-only executable regression logic. -- Defined the context-handoff artifact set. -- Created the checked-in handoff artifacts under `docs/_meta/`. -- Created the initial regression inventory scaffold in `docs/_meta/rtl_regression_inventory.yaml`. -- Selected and documented the first pilot modules: `FifoAsync`, `AxiStreamFifoV2`, and `AxiLiteAsync`. -- Added `scripts/setup_regression_env.sh` to bootstrap the local regression environment. -- Added `.vscode/tasks.json` with setup, import, and regression tasks. -- Installed local `ghdl` via Homebrew. -- Created `.venv`, installed Python regression dependencies, linked `~/ruckus`, and completed `make MODULES="$PWD" import`. -- Added shared regression helpers in `tests/regression_utils.py`. -- Implemented the first Python pilot regression in `tests/base/fifo/test_FifoAsync.py`. -- Validated `tests/base/fifo/test_FifoAsync.py` locally with `./.venv/bin/python -m pytest -v tests/base/fifo/test_FifoAsync.py`. -- Reorganized new regressions into subsystem packages under `tests/` and moved shared helpers to `tests/common/`. -- Added `tests/README.md` to document the regression layout policy. -- Added the shared Ethernet MAC helper layer in `tests/ethernet/EthMacCore/ethmac_test_utils.py`, including packet builders, checksum helpers, MAC-config byte-order handling, flat EMAC beat helpers, and Ethernet minimum-frame padding support for the import/export loopback benches. -- Added checked-in cocotb-facing wrappers under `ethernet/EthMacCore/wrappers/` for the first `EthMacCore` wave, including loopback wrappers for import/export and top-level tests plus flat wrappers for the checksum, pause, filter, and shift leaves. -- Implemented and validated the first `ethernet/EthMacCore` functional wave under `tests/ethernet/EthMacCore/`: `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`. -- Expanded the first `EthMacCore` wave beyond the initial happy paths: `EthMacTop` now covers filter/backpressure/checksum/pause interactions, `EthMacRxImport` and `EthMacTxExport` now cover both GMII and XGMII plus link-not-ready recovery behavior, the RX/TX checksum benches now include negative and partial-repair cases, `EthMacRxFilter` now covers multicast/broadcast/filter-disable/multi-beat-drop behavior, the RX/TX shift benches now cover runtime shift changes and control-bit propagation, and `EthCrc32Parallel` now sweeps all byte widths `1..16`. -- Ran a quick HDL coverage spike against the local Homebrew `ghdl` build and confirmed it does not expose `--coverage` or a `coverage` subcommand. -- Migrated `AxiStreamFifoV2` into `tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py` and validated the current 10-case sweep locally. -- Expanded `tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py` into a broader 10-case `AxiStreamFifoV2` regression covering thresholded release modes, metadata truncation, multi-stage cascade buffering, and the `S_HAS_TREADY=0` pause-only path, and validated it locally with `10 passed`. -- Revalidated `tests/axi/axi4/test_AxiResize.py` after merging `verification` into `fix-axi-resize`; the equal-width, `32-bit -> 64-bit`, and `64-bit -> 32-bit` cases now all pass locally on this branch, so the stale upsize `xfail` was removed. -- Expanded `FifoAsync` into a curated 12-case matrix and validated it locally under parallel pytest execution. -- Added `pytest.ini` to default to `-n auto --dist=worksteal`, and aligned CI to rely on that default xdist configuration. -- Implemented `tests/base/fifo/test_FifoSync.py` and validated its 11-case matrix locally under parallel pytest execution. -- Added `scripts/build_rtl_instantiation_graph.py` and generated checked-in graph artifacts in `docs/_meta/rtl_instantiation_graph.{md,json}`. -- Implemented `tests/base/sync/test_Synchronizer.py` and validated its 6-case matrix locally under parallel pytest execution. -- Implemented `tests/base/sync/test_SynchronizerVector.py` and validated its 6-case matrix locally under parallel pytest execution. -- Implemented `tests/base/general/test_RstPipeline.py` and validated its 4-case matrix locally under parallel pytest execution. -- Implemented `tests/base/ram/test_SimpleDualPortRam.py` and validated its 5-case matrix locally under parallel pytest execution. -- Implemented `tests/base/fifo/test_FifoOutputPipeline.py` and validated its 5-case matrix locally under parallel pytest execution. -- Implemented `tests/base/fifo/test_FifoWrFsm.py` and validated its 4-case matrix locally under parallel pytest execution. -- Extended `tests/common/regression_utils.py` so regressions can add test-local VHDL wrapper sources when simulator limitations make a thin shim cleaner than direct generic overrides. -- Implemented `tests/base/crc/test_Crc32Parallel.py`, `tests/base/crc/test_Crc32.py`, and `tests/base/crc/test_CRC32Rtl.py` and validated their combined 9-case CRC batch locally under parallel pytest execution. -- Implemented `tests/base/sync/test_RstSync.py`, `tests/base/sync/test_SynchronizerEdge.py`, and `tests/base/sync/test_SynchronizerOneShot.py` and validated their combined 11-case sync/reset batch locally under parallel pytest execution. -- Implemented `tests/base/general/test_PwrUpRst.py` and validated its 3-case matrix locally under parallel pytest execution. -- Implemented `tests/base/ram/test_TrueDualPortRam.py` and `tests/base/ram/test_LutRam.py` and validated their combined 9-case RAM batch locally under parallel pytest execution. -- Implemented `tests/base/fifo/test_FifoRdFsm.py` and validated its 4-case matrix locally under parallel pytest execution. -- Validated the full 10-module follow-on subset in one run with `./.venv/bin/python -m pytest -v tests/base/crc/test_Crc32Parallel.py tests/base/crc/test_Crc32.py tests/base/crc/test_CRC32Rtl.py tests/base/sync/test_RstSync.py tests/base/general/test_PwrUpRst.py tests/base/sync/test_SynchronizerEdge.py tests/base/sync/test_SynchronizerOneShot.py tests/base/ram/test_TrueDualPortRam.py tests/base/ram/test_LutRam.py tests/base/fifo/test_FifoRdFsm.py` (`38 passed`). -- Implemented `tests/base/general/test_Arbiter.py`, `tests/base/general/test_ClockDivider.py`, `tests/base/general/test_Debouncer.py`, `tests/base/general/test_Gearbox.py`, `tests/base/general/test_Heartbeat.py`, `tests/base/general/test_Mux.py`, `tests/base/general/test_OneShot.py`, `tests/base/general/test_RegisterVector.py`, `tests/base/general/test_RstPipelineVector.py`, `tests/base/general/test_Scrambler.py`, `tests/base/general/test_WatchDogRst.py`, `tests/base/delay/test_SlvDelay.py`, `tests/base/delay/test_SlvFixedDelay.py`, `tests/base/sync/test_SynchronizerFifo.py`, and `tests/base/sync/test_SynchronizerOneShotCnt.py`. -- Implemented `tests/axi/axi_stream/test_AxiStreamScatterGather.py`, `tests/axi/axi4/test_AxiMemTester.py`, `tests/axi/dma/test_AxiStreamDmaV2Desc.py`, `tests/axi/dma/test_AxiStreamDmaV2Fifo.py`, `tests/axi/axi4/test_AxiReadPathFifo.py`, `tests/axi/axi4/test_AxiWritePathFifo.py`, `tests/axi/dma/test_AxiStreamDmaV2.py`, `tests/axi/axi_stream/test_AxiStreamBatchingFifo.py`, `tests/axi/axi_stream/test_AxiStreamMon.py`, and `tests/axi/axi_stream/test_AxiStreamRingBuffer.py`, plus the supporting `*IpIntegrator.vhd` wrappers needed for the new AXI4/AXIS/DMA benches. -- Validated the full 15-module follow-on subset in one run with `./.venv/bin/python -m pytest -n 0 -q tests/base/general/test_Arbiter.py tests/base/general/test_ClockDivider.py tests/base/general/test_Debouncer.py tests/base/general/test_Gearbox.py tests/base/general/test_Heartbeat.py tests/base/general/test_Mux.py tests/base/general/test_OneShot.py tests/base/general/test_RegisterVector.py tests/base/general/test_RstPipelineVector.py tests/base/general/test_Scrambler.py tests/base/general/test_WatchDogRst.py tests/base/delay/test_SlvDelay.py tests/base/delay/test_SlvFixedDelay.py tests/base/sync/test_SynchronizerFifo.py tests/base/sync/test_SynchronizerOneShotCnt.py` (`41 passed`). -- Added a shared generated-wrapper path in `tests/common/regression_utils.py` and migrated the `Heartbeat` and `Debouncer` regressions away from checked-in one-off VHDL wrappers. -- Revalidated the generated-wrapper migration locally with `./.venv/bin/python -m pytest -n 0 -q tests/base/general/test_Heartbeat.py tests/base/general/test_Debouncer.py` (`6 passed`) and then revalidated the full 15-module batch (`41 passed`). -- Implemented `tests/dsp/generic/test_DspComparator.py`, `tests/base/fifo/test_Fifo.py`, `tests/base/fifo/test_FifoCascade.py`, `tests/base/fifo/test_FifoMux.py`, `tests/base/general/test_AsyncGearbox.py`, `tests/base/sync/test_SynchronizerOneShotVector.py`, `tests/base/sync/test_SynchronizerOneShotCntVector.py`, `tests/base/sync/test_SyncStatusVector.py`, `tests/base/sync/test_SyncTrigPeriod.py`, and `tests/base/sync/test_SyncMinMax.py`. -- Validated the combined 10-module wrapper/integration batch with `./.venv/bin/python -m pytest -n 0 -q tests/dsp/generic/test_DspComparator.py tests/base/fifo/test_Fifo.py tests/base/fifo/test_FifoCascade.py tests/base/fifo/test_FifoMux.py tests/base/general/test_AsyncGearbox.py tests/base/sync/test_SynchronizerOneShotVector.py tests/base/sync/test_SynchronizerOneShotCntVector.py tests/base/sync/test_SyncStatusVector.py tests/base/sync/test_SyncTrigPeriod.py tests/base/sync/test_SyncMinMax.py` (`18 passed`). -- Implemented `tests/base/general/test_MasterRamIpIntegrator.py`, `tests/base/general/test_SlaveRamIpIntegrator.py`, `tests/base/ram/test_DualPortRam.py`, `tests/base/delay/test_SlvDelayRam.py`, `tests/base/delay/test_SlvDelayFifo.py`, `tests/base/sync/test_SyncClockFreq.py`, `tests/base/sync/test_SyncTrigRate.py`, and `tests/base/sync/test_SyncTrigRateVector.py`. -- Validated the combined remaining non-vendor, non-dummy `base/` batch with `./.venv/bin/python -m pytest -n 0 -q tests/base/general/test_MasterRamIpIntegrator.py tests/base/general/test_SlaveRamIpIntegrator.py tests/base/ram/test_DualPortRam.py tests/base/delay/test_SlvDelayRam.py tests/base/delay/test_SlvDelayFifo.py tests/base/sync/test_SyncClockFreq.py tests/base/sync/test_SyncTrigRate.py tests/base/sync/test_SyncTrigRateVector.py` (`15 passed`). -- Implemented `tests/axi/axi_stream/test_AxiStreamPipeline.py` with a thin flat-port adapter at `axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd`, and validated its curated 3-case sweep locally. -- Implemented `tests/axi/axi_lite/test_AxiLiteCrossbar.py` with a cocotb-facing crossbar wrapper and validated its routed-region, decode-error, and concurrent-traffic coverage locally. -- Validated the first post-`base/` `axi/` pair with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamPipeline.py tests/axi/axi_lite/test_AxiLiteCrossbar.py` (`4 passed`). -- Implemented `tests/axi/axi_stream/test_AxiStreamMux.py` with a thin two-input adapter at `axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd`, and validated its curated indexed-priority, routed-remap, and asynchronous reset/recovery sweep locally (`3 passed`). -- Revalidated the small post-`base/` `axi/` follow-on set with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamPipeline.py tests/axi/axi_stream/test_AxiStreamMux.py tests/axi/axi_lite/test_AxiLiteCrossbar.py` (`7 passed`). -- Implemented `tests/axi/axi_stream/test_AxiStreamDeMux.py` with a thin two-output adapter at `axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd`, and validated its curated indexed-routing, routed-backpressure, and dynamic-route/drop/reset sweep locally (`3 passed`). -- Revalidated the current small `axi/` follow-on subset with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamPipeline.py tests/axi/axi_stream/test_AxiStreamMux.py tests/axi/axi_stream/test_AxiStreamDeMux.py tests/axi/axi_lite/test_AxiLiteCrossbar.py` (`10 passed`). -- Replaced the hand-curated flat phase-1 list with a generated path-qualified queue emitted by `scripts/build_rtl_instantiation_graph.py` into `docs/_meta/rtl_phase1_queue.{md,json}`, backed by explicit filters and manual-order inputs in `docs/_meta/rtl_phase1_queue_overrides.json`. -- Implemented `tests/axi/axi_lite/test_AxiLiteRegs.py`, `tests/axi/axi_lite/test_AxiLiteRespTimer.py`, `tests/axi/axi_lite/test_AxiLiteSlave.py`, `tests/axi/axi_lite/test_AxiLiteWriteFilter.py`, `tests/axi/axi_lite/test_AxiVersion.py`, `tests/axi/axi_stream/test_AxiStreamCombiner.py`, `tests/axi/axi_stream/test_AxiStreamFlush.py`, `tests/axi/axi_stream/test_AxiStreamGearboxPack.py`, `tests/axi/axi_stream/test_AxiStreamGearboxUnpack.py`, and `tests/axi/axi_stream/test_AxiStreamSplitter.py` with thin subsystem-local adapters under `axi/axi-lite/ip_integrator/` and `axi/axi-stream/ip_integrator/`. -- Validated the generated-queue 10-module AXI batch with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_lite/test_AxiLiteRegs.py tests/axi/axi_lite/test_AxiLiteRespTimer.py tests/axi/axi_lite/test_AxiLiteSlave.py tests/axi/axi_lite/test_AxiLiteWriteFilter.py tests/axi/axi_lite/test_AxiVersion.py tests/axi/axi_stream/test_AxiStreamCombiner.py tests/axi/axi_stream/test_AxiStreamFlush.py tests/axi/axi_stream/test_AxiStreamGearboxPack.py tests/axi/axi_stream/test_AxiStreamGearboxUnpack.py tests/axi/axi_stream/test_AxiStreamSplitter.py` (`14 passed`). -- Implemented `tests/axi/axi4/test_AxiReadPathMux.py`, `tests/axi/axi4/test_AxiWritePathMux.py`, `tests/axi/axi4/test_AxiResize.py`, and `tests/axi/bridge/test_AxiToAxiLite.py` with thin subsystem-local adapters at `axi/axi4/ip_integrator/AxiReadPathMuxIpIntegrator.vhd`, `axi/axi4/ip_integrator/AxiWritePathMuxIpIntegrator.vhd`, `axi/axi4/ip_integrator/AxiResizeIpIntegrator.vhd`, and `axi/bridge/ip_integrator/AxiToAxiLiteIpIntegrator.vhd`. -- Validated the stable AXI4/bridge follow-on subset with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiReadPathMux.py tests/axi/axi4/test_AxiWritePathMux.py tests/axi/bridge/test_AxiToAxiLite.py` (`3 passed`). `tests/axi/axi4/test_AxiResize.py` is present on this branch with the restored upsize case, but that case is expected to fail until the separate `AxiResize` RTL-fix branch is merged. -- Implemented `tests/axi/axi_stream/test_AxiStreamTrailerRemove.py`, `tests/axi/axi4/test_AxiRam.py`, `tests/axi/bridge/test_AxiLiteToIpBus.py`, `tests/axi/bridge/test_IpBusToAxiLite.py`, `tests/axi/dma/test_AxiStreamDmaV2Read.py`, `tests/axi/axi_stream/test_AxiStreamGearbox.py`, `tests/axi/axi_stream/test_AxiStreamTap.py`, `tests/axi/dma/test_AxiStreamDmaRead.py`, `tests/axi/dma/test_AxiStreamDmaV2Write.py`, and `tests/axi/axi_stream/test_AxiStreamTimer.py` with subsystem-local adapters under `axi/axi-stream/ip_integrator/`, `axi/bridge/ip_integrator/`, and `axi/dma/ip_integrator/`. -- Validated the stable 9-module subset of that generated-queue window with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiRam.py tests/axi/bridge/test_AxiLiteToIpBus.py tests/axi/bridge/test_IpBusToAxiLite.py tests/axi/dma/test_AxiStreamDmaRead.py tests/axi/dma/test_AxiStreamDmaV2Write.py tests/axi/axi_stream/test_AxiStreamGearbox.py tests/axi/axi_stream/test_AxiStreamTap.py tests/axi/axi_stream/test_AxiStreamTimer.py tests/axi/axi_stream/test_AxiStreamTrailerRemove.py` (`9 passed`). `tests/axi/dma/test_AxiStreamDmaV2Read.py` is present on this branch as a minimal one-beat aligned reproducer, but it still fails immediately inside `AxiStreamDmaV2Read` at `31 ns` with `std_logic_arith.vhdl:2014:9: ARG is too large in CONV_INTEGER`, so `AxiStreamDmaV2Read` remains open rather than counted as validated. -- Implemented `tests/axi/axi4/test_AxiRateGen.py` with a thin subsystem-local adapter at `axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd`. -- Validated `AxiRateGen` locally with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiRateGen.py` (`1 passed`) and revalidated the nearby AXI4 subset with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi4/test_AxiReadPathMux.py tests/axi/axi4/test_AxiWritePathMux.py tests/axi/axi4/test_AxiRam.py tests/axi/axi4/test_AxiRateGen.py` (`4 passed`). -- Refactored `protocols/line-codes` into a clean three-layer cocotb layout backed by a shared helper in `tests/protocols/line_codes/line_code_test_utils.py`: direct package benches via checked-in `Code*PkgWrapper.vhd` adapters, direct `Encoder*`/`Decoder*` entity benches, and small end-to-end integration smokes that reuse the legacy `protocols/line-codes/tb/LineCode*Tb.vhd` shells instead of duplicated wrapper HDL. -- Added permanent checked-in package adapters at `protocols/line-codes/wrappers/Code8b10bPkgWrapper.vhd`, `protocols/line-codes/wrappers/Code10b12bPkgWrapper.vhd`, and `protocols/line-codes/wrappers/Code12b14bPkgWrapper.vhd`, then removed the duplicated `protocols/line-codes/wrappers/LineCode*Wrapper.vhd` files and their matching `test_LineCode*Wrapper.py` benches. -- The direct-entity benches now cover clock-enable gating, flow-control hold behavior, malformed decoder inputs, dual-byte 8b10b lane coverage, and 12b14b debug-disparity handoff through `test_Encoder*.py` and `test_Decoder*.py`. -- The current line-code validation command is `./.venv/bin/python -m pytest -n 0 -q tests/protocols/line_codes`, and it passes locally with `23 passed`. -- The new package-surface coverage exposed a real `Code12b14bPkg` invalid-K disparity bug; `protocols/line-codes/rtl/Code12b14bPkg.vhd` now leaves `dispOut` unchanged on illegal K requests instead of tripping a GHDL bound-check failure. - -## Current In-Progress Item -- The user-requested `protocols/srp` review fixes are complete: `test_SrpV3Axi.py` now reuses the shared SRPv3 helper/model layer, `test_SrpV3Core.py` uses decorator-based cocotb test selection, the stray SRPv3 AXI-Lite debug logging is removed, and the high-value SRP coverage additions are checked in locally. -- Keep the CoaXPress suite as an already validated current branch slice. The focused CoaXPress validation command is `./.venv/bin/python -m pytest -n auto --dist=worksteal -q tests/protocols/coaxpress`, and the latest pre-merge run passed with `17 passed, 1 skipped`. -- Treat the skipped `CoaXPressConfig` bench and the opt-in `CoaXPressCore` overflow/FSM-error known-issue bench as the main open protocol cleanup items after the SRP duplicate wide-wrapper skips were removed. -- Preserve the recent `pgp4` lesson for later PGP work: when the simulation wrapper only exposes stable lock/config surfaces, write the bench around those explicit contracts instead of claiming recovered payload coverage. -- Latest focused SRP validation: `./.venv/bin/python -m pytest -n 0 -q tests/protocols/srp` passed locally with `23 passed`. - -## Next 3 Concrete Tasks -- Review any newly requested SRP changes from the user; staging and committing remain user-controlled. -- Optional SRP follow-up is now lower priority: add deeper timeout/posted-write disabled-op permutations only if a future change touches those RTL branches. -- If staying on CoaXPress immediately after the merge, debug the skipped `CoaXPressConfig` / `SrpV3AxiLite` request path before adding broader optional coverage. - -## Blockers And Risks -- Runtime may grow quickly once configuration-heavy modules are added without careful tiering. -- Wrapper policy must stay narrow or VHDL cruft will accumulate again. -- HDL source coverage is not immediately available with the current local `ghdl` LLVM build; it needs a separate tooling decision if we want it later. - -## Findings Worth Preserving -- For a quick resume, read this file’s `Current Frontier Snapshot`, `Current In-Progress Item`, `Next 3 Concrete Tasks`, and `Findings Worth Preserving` sections before digging through the full log. -- Existing Python regressions are generally the best reusable verification assets. -- Existing VHDL TBs contain useful behavioral intent but are inconsistent as a scalable execution framework. -- Generic-heavy modules strongly favor Python-authored tests. -- Broad repo coverage will require tiering and likely later sharding. -- The initial inventory file should remain small and explicit rather than auto-generated until the schema stabilizes. -- `AxiStreamFifoV2` already has a useful wrapper-plus-Python pattern, and the same shim-first approach works well for later AXI wrappers when the DUT-specific extra signals are kept thin. -- AXI Stream leaves with partially driven sideband fields can upset `cocotbext.axi` sinks under GHDL when those fields stay `U`; for first-pass benches, prefer either wrappers that drive those sidebands deterministically or hand-monitored payload checks when the sidebands are not part of the behavior under test. -- Real-generic overrides are still awkward under the local open-source stack; if a module only needs a small non-default real-generic operating point, prefer baking the stable value into the thin subsystem wrapper over fighting simulator-specific override syntax. -- Some wrapper benches need to stay intentionally narrow on this branch to avoid conflating simulator limitations with RTL failures. In this batch that applies to `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux`. -- The local machine needs a reproducible one-command bootstrap path before test implementation work can move efficiently. -- The bootstrap path is now working locally with `~/ruckus` linked into the repo. -- Bare `python` should not be assumed to exist on `PATH` in this repo's shell environment; use `./.venv/bin/python` for local pytest and helper-script invocations unless the virtualenv is already activated. -- The first shared-helper-based pilot is working; start simple and grow coverage incrementally rather than front-loading every edge case. -- New regressions need to live in subsystem packages from the start; do not add more flat `tests/test_*.py` files. -- The current Homebrew `ghdl` install is sufficient for cocotb regressions but not for a simple built-in HDL coverage flow. -- The existing `AxiLiteAsyncTb.vhd` is useful as intent/reference, but it is not an appropriate long-term wrapper because it embeds clocks, memories, and transaction logic; `AxiLiteAsyncIpIntegrator.vhd` is now the cleaner cocotb-facing adapter. -- Future Python regression code should follow the user's preferred two-layer comment style: keep a module-specific `Test methodology` header block under the SLAC banner and also explain major coroutine steps, waits, stimulus phases, and checks in-place for readers who are not already comfortable with cocotb. -- Future Python regression code should also keep the standard SURF/SLAC file header itself; do not treat the methodology block as a substitute for the normal repo banner. -- The methodology block should use wrapped `Sweep`, `Stimulus`, `Checks`, and `Timing` bullets and describe the real bench behavior, not generic filler text. -- The same “write it readable on the first pass” rule applies to permanent cocotb-facing VHDL wrappers: checked-in `*IpIntegrator.vhd` files should carry the standard SURF banner and short section comments for shim setup, DUT hookup, and flattening/status wiring. -- `FifoAsync` needed a curated matrix rather than a naive Cartesian sweep: standard FIFO mode, FWFT mode, and pipelined FWFT do not share identical read/full semantics. -- VHDL packages should not become top-level test targets by default; only high-value behavioral helpers warrant dedicated wrapper tests. -- `FifoSync` benefits from the same curated-matrix approach as `FifoAsync`, but its threshold checks needed event-driven flag handling because `prog_full`/`prog_empty` timing did not line up with fixed write-count assumptions. -- The instantiation graph is useful for rollout planning because it exposes both high-reuse leaves and likely duplicated coverage paths; it should guide prioritization, not dictate exact test depth. -- The generated path-qualified queue in `rtl_phase1_queue.{md,json}` is now the operational phase-1 order. Use the graph for provenance and regeneration, and use `rtl_phase1_queue_overrides.json` for justified defer/reorder exceptions instead of hand-maintaining queue text in the plan doc. -- The first graph pass surfaced `Synchronizer`, `SynchronizerVector`, `SimpleDualPortRam`, `FifoOutputPipeline`, `FifoRdFsm`, and `FifoWrFsm` as concrete `base/` bottom-up candidates after the FIFO pilots. -- Duplicate entity names are common in SURF due to dummy/vendor variants, so graph consumers need to read path context rather than rely on entity names alone. -- A generated path-qualified queue is practical under the current graph parser: the first pass yields `411` phase-1 modules with `0` unresolved duplicate-name phase-1 edges under the checked-in filter set. -- Keep `docs/_meta/rtl_phase1_queue_overrides.json` small and explicit. It should record only real phase-1 scope decisions or blocker-driven order exceptions, not day-to-day queue churn. -- Direct cocotb tests for simple SURF leaf modules still need to account for `TPD_G` when sampling outputs after clock or reset events; sampling exactly at the nominal edge can create false negatives. -- Simple RAM tests benefit from a small startup warm-up and conservative read sampling so direct and registered output configurations share one stable helper. -- For leaf modules with combinational outputs derived from current request inputs, pulse-based tests should drop the request before sampling post-edge state or they may observe the next pending transaction instead of the one just accepted. -- The local GHDL flow rejects direct command-line overrides of a 32-bit `slv` generic in `Crc32`; when a parameterized leaf still needs expanded coverage, prefer a thin test-only wrapper over simulator-specific literal hacks. -- For repeated real-generic shim cases, generated test-local wrappers are a better default than checking in one VHDL file per module; they keep the workaround explicit without growing permanent HDL debris. -- `COMMON_CLK_G` style benches need truly shared edges, not just same-period clocks. A single cocotb coroutine that drives both clocks in lockstep is the safer default for those wrappers. -- Integration-wrapper tests should stay narrow and wrapper-specific. `Fifo` validated both inferred sync/async wrapper branches, `FifoCascade` validated public stage-vector plumbing plus a curated output smoke, and `FifoMux` is currently validated only on the stable split-to-narrow path while the packed-write branch remains deferred. -- `SyncClockFreq` is stable under the generated-wrapper approach, but the common-clock path quantizes one count above the abstract frequency target under GHDL, so the regression checks a bounded expected range instead of an over-precise exact integer. -- `SyncTrigRate` is now covered as a wrapper/integration bench: it validates aligned update publication, denser-window rate growth, reset-path liveness, and update-strobe pulse behavior. Exact min/max pipeline arithmetic remains covered by the dedicated `SyncMinMax` leaf regression rather than being re-proven through the wrapper. -- `LutFixedDelay` is the lone non-dummy `base/` entity still deferred in phase 1 because it depends on `SinglePortRamPrimitive`, which is currently only available through the vendor/dummy-backed path. -- `AxiStreamPipeline` is stable with a thin flat-port wrapper. The zero-stage case should be checked as true pass-through, while staged cases should be checked against the wrapper-visible latency of `PIPE_STAGES_G + 2` clocks and a bounded reset flush rather than an over-precise internal-stage assumption. -- `AxiStreamMux` is stable with a thin two-input adapter, but its `disableSel` handling composes with the separate priority-masking step in a non-obvious order: a disabled higher-priority source can still suppress lower-priority requesters. Disable-focused benches should either use equal priorities or mask the lower-priority source instead. -- `AxiStreamMux` interleave and explicit rearbitrate branches remain intentionally out of scope for the first wrapper bench; the validated subset is indexed arbitration plus `disableSel`, routed `TDEST`/`TID` remap under backpressure, and staged reset/recovery in passthrough mode. -- `AxiStreamDeMux` is stable with a thin one-input/two-output adapter. The first bench covers indexed decode, exact-match routed decode under output backpressure, and dynamic-route table behavior including unmatched-destination drop and staged reset flush. Broader wildcard-route patterns and larger fanout counts remain intentionally unproven in this first wrapper bench. -- `AxiLiteCrossbar` is practical under the current open-source flow with a thin cocotb-facing wrapper around the cascaded topology. The useful regression surface is routed-region correctness, decode-miss `DECERR` handling, and concurrent traffic through the cascaded topology, not a giant generic sweep. -- SURF already has reusable AXI record-flattening shims. New AXI Stream and AXI-Lite wrappers should prefer the existing IP-integrator shim layers over hand-written record packing, and only custom-wire the DUT-specific extra side signals on top. -- More generally, any VHDL shim layer added only to make a module fit cleanly into cocotb should live in the nearest real subsystem `ip_integrator/` tree, not under `tests/` and not under generic `hdl/` directories. -- If that shim layer is checked in instead of generated locally, treat it like normal repo HDL rather than disposable glue: add the standard header and enough section comments that the adapter structure is obvious during a later resume. -- Apply the same “first-draft readability” rule to checked-in cocotb tests: standard header first, methodology block second, tutorial comments in the body. -- `AxiReadPathMux` and `AxiWritePathMux` are more stable with tiny source-side pin drivers than with `cocotbext.axi` masters because the muxes rewrite IDs internally; the downstream shared-port checks can still use the library RAM models. -- `protocols/line-codes` is cleaner when split into three layers: direct package benches for exhaustive legal-space and explicit disparity-seed checks, direct `Encoder*`/`Decoder*` entity benches for clock/reset/flow-control behavior, and one small family-level integration smoke that proves the encoder-to-decoder chain still matches the legacy shell. -- For the line-code families, keep the shared Python harness generic and keep legality decisions local to each module bench. `8b10b` varies by byte-lane width, `10b12b` uses the curated `x & 28` K-symbol subset from the legacy bench, and `12b14b` also preserves its historical mixed training pattern plus explicit malformed-decode and illegal-K checks. -- For line-code package coverage, prefer checked-in subsystem wrappers only where the package surface truly needs explicit disparity seeding or direct encode/decode visibility. `Code8b10bPkg`, `Code10b12bPkg`, and `Code12b14bPkg` all follow that pattern now; the family integration layer should reuse existing `tb/LineCode*Tb.vhd` shells rather than cloning them into new wrapper HDL. -- The new package-surface tests are strong enough to expose latent package bugs. In this batch they caught an illegal-K path defect in `Code12b14bPkg` where the package could drive an out-of-range disparity sum; that path is now fixed and should stay covered. -- The current `Code12b14b` cocotb coverage preserves the legacy explicit disparity seeds plus the training/transition sequences, but it still does not carry forward the old VHDL bench's stateful run-length monitor as a passing assertion. Treat that run-length monitor as a known follow-up gap rather than silently assuming it is covered. -- `AxiToAxiLite` is practical with a thin bridge-local adapter, but mixed-width checks need to stay single-beat on the AXI side when the downstream response path is fundamentally AXI-Lite-like. -- `AxiResize` still has an expected verification-branch gap: the restored `32-bit -> 64-bit` upsize case in `tests/axi/axi4/test_AxiResize.py` should keep failing here until the separate RTL-fix branch is merged. -- `AxiRateGen` is practical with the existing AXI4 and AXI-Lite IP-integrator shim pair plus a cocotb AXI RAM model, and the stable first-pass subset is the `COMMON_CLK_G=true` path with timer spacing, zero-fill writes, and generated-read completion rather than the asynchronous AXI-Lite crossing branches. -- For protocol-generator or wrapper-style benches, pair end-state checks with explicit accepted-handshake monitoring whenever the externally visible contract includes timing, burst shape, sideband propagation, or arbitration order. -- The SSI helper layer is now broad enough to justify reuse across the whole subsystem: `FlatSsiEndpoint`, `SsiBeat`, `recv_frame`, contiguous frame driving, optional `TID` handling, and no-output checks cover the current flattened SSI wrappers without each bench re-implementing handshake plumbing. -- `SsiInsertSof` is practical with a small SSI-local wrapper that exposes semantic SOF/EOFE controls instead of treating raw `TUSER` layout as the cocotb API. The currently validated subset keeps `COMMON_CLK_G=true` and FIFO-backed paths enabled; raw `TUSER_MASK_G` bit-level expectations are still a follow-up item if we want to pin down SSI user-bit indexing more aggressively. -- `SsiIbFrameFilter` is practical with the same semantic-wrapper approach, but the wrapper should use native SSI `TUSER_FIRST_LAST_C` encoding rather than a generic normal-user layout so cocotb can drive `SOF`/`EOFE` directly and the DUT sees the expected first/last byte markers. -- `SsiObFrameFilter` is practical with the same native-SSI wrapper contract. The checked-in bench now covers good-frame pass-through, missing-SOF drop, repeated-`SOF` termination, mid-frame `TDEST` termination, the cached-last-user `VALID_THOLD_G=0` `EOFE` drop path with exported drop-flag pulses, and one pipelined `PIPE_STAGES_G=2` pass-through case without relying on fixed latency assumptions. -- `SsiFifo` is practical with the same flat SSI wrapper pattern, but contiguous multi-beat checks need handshake-based observation rather than late frame collection. The earlier apparent middle-beat loss on a 3-beat `SsiFifoWrapper` probe turned out to be a receive-helper artifact; once the helper was corrected to capture accepted handshakes, both `SsiIbFrameFilter` and `SsiFifo` preserved the full frame and the checked-in `SsiFifo` regression could safely add real 3-beat pass-through assertions on the default, frame-ready, and thresholded paths plus a repeated-`SOF` termination check on the composite FIFO wrapper. -- The first reusable SSI Python helper can now absorb whole-frame receive and metadata-extension commonality, but it should still stop short of becoming a golden protocol model. Module-specific policy such as header injection, command decode rules, or filter-drop counters should remain in each bench. -- `AxiStreamDmaV2Read` is stable with a thin IP-integrator wrapper once the read-path byte-count conversions stay bounded to the burst-size window. The checked-in bench proves both aligned and short terminal-beat reads; because the wrapper exports only an 8-bit `TUSER`, the observable contract is first-user propagation rather than separate first/last byte tagging. -- The `axi/dma/rtl/v2/` benches are now intentionally split by behavior instead of repeatedly re-proving the same path through the top-level DMA stack: `AxiStreamDmaV2` and `AxiStreamDmaV2Desc` stay focused on descriptor-manager register/control surfaces, `AxiStreamDmaV2Read` owns aligned and short terminal-beat readout, `AxiStreamDmaV2Write` owns descriptor-return integrity plus burst splitting, `AxiStreamDmaV2WriteMux` owns arbitration ordering, and `AxiStreamDmaV2Fifo` owns the integrated FIFO register/count/pause-threshold surface. -- For checked-in VHDL changes, use the repo virtualenv's `vsg` with `vsg-linter.yml` so local lint matches CI, and prefer `--fix` before manual spacing/alignment cleanup. -- The current `EthMacCore` wave has a few wrapper-visible behavior details worth preserving in the docs instead of rediscovering later: the XGMII import/export loopback retains a frame presented during `phyReady=0` and drains it after link recovery with Ethernet minimum-size padding applied, while the GMII path drops it; `EthMacRxCsum` reliably asserts `IPERR` on a bad IPv4 header checksum but the checked-in wrapper contract does not require `EOFE` on that case; and the RX/TX shift benches need a small idle-plus-settle gap before changing runtime shift controls because the underlying `AxiStreamShift` samples those controls from its IDLE state. -- Verification hygiene now includes process cleanup: if a `pytest`/cocotb/GHDL step leaves stale run trees behind, kill those leftovers immediately before starting another compile or simulation command. -- For routine local validation, prefer parallel pytest (`-n auto --dist=worksteal`) so cocotb suites finish quickly. Drop to `-n 0` only when debugging one simulation or preserving serial log ordering. - -## Log -- 2026-03-20: Agreed on Python-only executable regression logic and wrapper-only VHDL retention. -- 2026-03-20: Agreed on whole-repo scope with simulator-friendly phase 1 and vendor-heavy deferral. -- 2026-03-20: Agreed to add stable handoff artifacts under `docs/_meta/` before deeper implementation work. -- 2026-03-20: Added `docs/_meta/rtl_regression_inventory.yaml` and seeded it with the first three pilot modules. -- 2026-03-20: Added local bootstrap helpers in `scripts/setup_regression_env.sh` and `.vscode/tasks.json`. -- 2026-03-20: Installed local toolchain and completed the first successful `make MODULES="$PWD" import`. -- 2026-03-20: Added `tests/regression_utils.py` and landed the first passing pilot regression for `FifoAsync`. -- 2026-03-20: Moved new regression infrastructure to `tests/common/`, relocated `FifoAsync` to `tests/base/fifo/`, and documented the subsystem-organized test layout. -- 2026-03-20: Checked local HDL coverage viability; the installed LLVM-backed `ghdl` rejects `--coverage`, so HDL coverage is deferred pending a different simulator/backend decision. -- 2026-03-20: Migrated `AxiStreamFifoV2` into `tests/axi/axi_stream/` and validated the full current 10-case sweep in 146s. -- 2026-04-02: Expanded `tests/axi/axi_stream/test_AxiStreamFifoV2IpIntegrator.py` to cover `VALID_THOLD` release behavior, burst gating, dynamic pause control, `CASCADE_SIZE=2`, and `S_HAS_TREADY=0`, and revalidated it locally with `10 passed`. -- 2026-04-02: Merged `verification` into `fix-axi-resize`, reran `tests/axi/axi4/test_AxiResize.py`, and confirmed the previous `32-bit -> 64-bit` upsize `xfail` now passes on this branch; removed the stale `xfail`. -- 2026-04-02: Expanded the `axi/dma/rtl/v2/` regression split without broad overlap. `tests/axi/dma/test_AxiStreamDmaV2Write.py` now covers both single-frame and multi-burst writes, `tests/axi/dma/test_AxiStreamDmaV2WriteMux.py` now covers descriptor-first, simultaneous-launch, and data-first arbitration cases, and `tests/axi/dma/test_AxiStreamDmaV2Fifo.py` now covers the integrated FIFO register map plus dynamic pause-threshold behavior against the live write-buffer count. The combined validation run across `tests/axi/dma/test_AxiStreamDmaV2.py`, `tests/axi/dma/test_AxiStreamDmaV2Desc.py`, `tests/axi/dma/test_AxiStreamDmaV2Read.py`, `tests/axi/dma/test_AxiStreamDmaV2Write.py`, `tests/axi/dma/test_AxiStreamDmaV2WriteMux.py`, and `tests/axi/dma/test_AxiStreamDmaV2Fifo.py` passes locally with `9 passed`. -- 2026-04-02: Started the `protocols/line-codes` refactor by moving the family benches onto a shared helper in `tests/protocols/line_codes/line_code_test_utils.py` and by adding checked-in package-surface wrappers for `Code8b10bPkg`, `Code10b12bPkg`, and `Code12b14bPkg`. -- 2026-04-02: Compared the cocotb line-code coverage against the legacy VHDL benches under `protocols/line-codes/tb/`, preserved the legacy disparity-seed and training-pattern intent in the `Code*Pkg` Python benches, and noted the old `Code12b14bTb.vhd` run-length monitor as the only still-unported legacy assertion. -- 2026-04-02: Completed the clean-slate line-code redesign: deleted the duplicated `LineCode*Wrapper.vhd` and `test_LineCode*Wrapper.py` layer, added direct `test_Encoder*.py` and `test_Decoder*.py` benches against the real RTL entities, reused `protocols/line-codes/tb/LineCode*Tb.vhd` as the thin integration shells, fixed an illegal-K disparity bug in `protocols/line-codes/rtl/Code12b14bPkg.vhd`, and validated the full `tests/protocols/line_codes` directory locally with `23 passed`. -- 2026-04-03: Added `dsp/` back into `scripts/build_rtl_instantiation_graph.py` so the regenerated `docs/_meta/rtl_instantiation_graph.{md,json}` and `docs/_meta/rtl_phase1_queue.{md,json}` artifacts now track `dsp/generic/fixed` alongside the other phase-1 subsystems. -- 2026-04-03: Implemented `tests/dsp/generic/test_DspAddSub.py` as the first post-resume DSP leaf bench, replacing the old free-running `dsp/generic/tb/DspAddSubTb.vhd` stimulus with explicit signed add/sub arithmetic checks plus backpressure-hold and reset-clearing assertions. The module-local validation run passes locally with `2 passed`. -- 2026-04-03: Completed the planned `dsp/generic/fixed` cocotb leaf batch. Added new benches for `FirFilterTap`, `DspPreSubMult`, `DspSquareDiffMult`, `BoxcarIntegrator`, `BoxcarFilter`, `FirFilterSingleChannel`, and `FirFilterMultiChannel`; centralized shared DSP timing/model/wrapper helpers in `tests/dsp/generic/dsp_test_utils.py`; added explicit sim-build-key support for generated wrappers in `tests/common/regression_utils.py`; fixed RTL issues in `FirFilterTap`, `BoxcarIntegrator`, and `FirFilterSingleChannel`; and validated the full directory with `15 passed`. -- 2026-04-06: Started the manual `protocols/ssi` rollout with `SsiInsertSof`. Added the checked-in wrapper `protocols/ssi/wrappers/SsiInsertSofWrapper.vhd`, implemented `tests/protocols/ssi/test_SsiInsertSof.py`, validated the three-case FIFO-backed sweep locally with `3 passed`, and linted the wrapper cleanly with `vsg -c vsg-linter.yml -f`. -- 2026-04-06: Validated the narrow next SSI step with `SsiIbFrameFilter`. Added the checked-in native-SSI wrapper `protocols/ssi/wrappers/SsiIbFrameFilterWrapper.vhd`, implemented `tests/protocols/ssi/test_SsiIbFrameFilter.py`, validated the first-pass same-clock sweep locally with `1 passed`, linted the wrapper cleanly with `vsg --fix -c vsg-linter.yml -f`, and then consolidated shared flat SSI driver/sink timing into `tests/protocols/ssi/ssi_test_utils.py` so `test_SsiInsertSof.py` and `test_SsiIbFrameFilter.py` use the same basic endpoint helper layer. -- 2026-04-06: Added the next outbound SSI step with `SsiObFrameFilter`. Added the checked-in native-SSI wrapper `protocols/ssi/wrappers/SsiObFrameFilterWrapper.vhd`, implemented `tests/protocols/ssi/test_SsiObFrameFilter.py`, validated the narrowed default-mode regression locally with `1 passed`, revalidated the current SSI trio with `5 passed`, and linted the wrapper cleanly with `vsg --fix -c vsg-linter.yml -f`. The stable checked-in subset covers good-frame pass-through plus repeated-`SOF` termination with `PIPE_STAGES_G=0`; the cached-last-user `EOFE` branch for `VALID_THOLD_G=0` remains a follow-up item. -- 2026-04-06: Added the next composite SSI step with `SsiFifo`. Added the checked-in wrapper `protocols/ssi/wrappers/SsiFifoWrapper.vhd`, implemented `tests/protocols/ssi/test_SsiFifo.py`, validated the narrowed smoke regression locally with `1 passed`, and linted the wrapper cleanly with `vsg --fix -c vsg-linter.yml -f`. The stable checked-in subset keeps one physical clock and currently proves valid single-beat pass-through plus missing-SOF drop; multi-beat good-frame integrity, buffered occupancy behavior, and the sync-output gearbox branch remain follow-up items. -- 2026-04-06: Completed the remaining manual `protocols/ssi` leaf batch. Added checked-in wrappers `protocols/ssi/wrappers/SsiCmdMasterPulserWrapper.vhd`, `protocols/ssi/wrappers/SsiCmdMasterWrapper.vhd`, `protocols/ssi/wrappers/SsiFrameLimiterWrapper.vhd`, `protocols/ssi/wrappers/SsiIncrementingTxWrapper.vhd`, `protocols/ssi/wrappers/SsiAxiLiteMasterWrapper.vhd`, and `protocols/ssi/wrappers/SsiDbgTapWrapper.vhd`; added `tests/protocols/ssi/test_SsiCmdMasterPulser.py`, `tests/protocols/ssi/test_SsiCmdMaster.py`, `tests/protocols/ssi/test_SsiFrameLimiter.py`, `tests/protocols/ssi/test_SsiIncrementingTx.py`, `tests/protocols/ssi/test_SsiAxiLiteMaster.py`, and `tests/protocols/ssi/test_SsiDbgTap.py`; extended `tests/protocols/ssi/ssi_test_utils.py` with optional `TID` handling plus shared frame-receive helpers; validated the new six-test batch locally with `6 passed`; and kept wrapper lint clean under `vsg --fix -c vsg-linter.yml -f` plus a clean follow-up lint pass. The current scope is intentionally uneven: `SsiCmdMasterPulser`, `SsiCmdMaster`, `SsiIncrementingTx`, and `SsiAxiLiteMaster` have functional first-pass checks, `SsiFrameLimiter` is currently a narrowed single-beat/missing-SOF subset, and `SsiDbgTap` is traffic smoke only because the RTL exposes no externally visible state. -- 2026-04-07: Tightened the shared SSI helper layer in `tests/protocols/ssi/ssi_test_utils.py` so flat SSI sources wait for a real handshake edge and shared frame receivers capture accepted handshakes instead of inferring contiguous traffic from post-send snapshots. Revalidated the existing SSI slice locally with `19 passed`. A focused follow-up on `SsiIbFrameFilter` and `SsiFifo` showed the earlier apparent 3-beat middle-word loss was a bench observation bug rather than an RTL bug, after which the checked-in `SsiFifo` regression added a real contiguous 3-beat pass-through assertion and the `SsiAxiLiteMaster` / `SsiIncrementingTx` benches were updated to assert the full emitted frame shapes. -- 2026-04-07: Expanded `tests/protocols/ssi/test_SsiFifo.py` beyond the earlier single-beat subset. The checked-in FIFO bench now proves contiguous 3-beat frame preservation on the default, `VALID_THOLD_G=0`, and `VALID_THOLD_G=2` wrapper paths; exercises repeated-`SOF` malformed-frame handling across the buffered modes; and keeps the existing missing-`SOF` drop plus `SLAVE_READY_EN_G=false` overflow checks. The buffered malformed-frame result is mode-specific at the wrapper boundary: `VALID_THOLD_G=0` drops the malformed repeated-`SOF` frame outright, while `VALID_THOLD_G=2` emits the expected two-beat terminated `EOFE` frame. A follow-up backpressure pass also added explicit drain-side ready toggling on a good 5-beat frame, malformed termination under toggled ready, and thresholded release under intermittent drain stalls so SSI frame policy is now checked under nontrivial sink backpressure without duplicating the full `AxiStreamFifoV2` transport matrix. Revalidated the full touched SSI slice locally with `19 passed`. -- 2026-04-10: Landed the first manual `ethernet/EthMacCore` bench wave under `tests/ethernet/EthMacCore/`, added the required checked-in wrappers under `ethernet/EthMacCore/wrappers/`, and validated the baseline 12-module slice covering `EthCrc32Parallel`, `EthMacFlowCtrl`, `EthMacRxPause`, `EthMacTxPause`, `EthMacRxFilter`, `EthMacRxShift`, `EthMacTxShift`, `EthMacRxImport`, `EthMacTxExport`, `EthMacRxCsum`, `EthMacTxCsum`, and `EthMacTop`. -- 2026-04-10: Expanded that same `EthMacCore` slice beyond the initial happy paths. The checked-in Ethernet MAC suite now covers `EthMacTop` filter/backpressure/checksum/pause interactions, GMII and XGMII import/export plus link-not-ready recovery behavior, checksum negative cases, filter multicast/broadcast/filter-disable/multi-beat-drop behavior, shift runtime-control and control-bit propagation edges, and full byte-width `1..16` logic-path coverage for `EthCrc32Parallel`. The full `tests/ethernet/EthMacCore` directory currently passes locally with `32 passed`. -- 2026-04-17: Expanded the `ethernet/EthMacCore` slice into the deeper assembly layer. The checked-in Ethernet MAC benches now also cover `EthMacRx`, `EthMacTx`, `EthMacRxFifo`, and `EthMacTxFifo` through the existing subsystem-local wrappers under `ethernet/EthMacCore/wrappers/`. -- 2026-04-17: Added the manual `ethernet/UdpEngine` wave under `tests/ethernet/UdpEngine/`. The checked-in helper layer now lives in `tests/ethernet/UdpEngine/udp_test_utils.py`, the new checked-in wrappers live under `ethernet/UdpEngine/wrappers/`, and the locally validated benches cover `ArpIpTable`, `UdpEngineArp`, `UdpEngineDhcp`, `UdpEngineRx`, `UdpEngineTx`, `UdpEngine`, and `UdpEngineWrapper`. The current local validation command `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/UdpEngine/test_ArpIpTable.py tests/ethernet/UdpEngine/test_UdpEngineArp.py tests/ethernet/UdpEngine/test_UdpEngineDhcp.py tests/ethernet/UdpEngine/test_UdpEngineRx.py tests/ethernet/UdpEngine/test_UdpEngineTx.py tests/ethernet/UdpEngine/test_UdpEngine.py tests/ethernet/UdpEngine/test_UdpEngineWrapper.py` passes with `7 passed`. -- 2026-04-17: Added the manual `ethernet/IpV4Engine` wave under `tests/ethernet/IpV4Engine/`. The checked-in helper layer now lives in `tests/ethernet/IpV4Engine/ipv4_test_utils.py`, the checked-in wrappers live under `ethernet/IpV4Engine/wrappers/`, and the validated benches cover `ArpEngine`, `IcmpEngine`, `IpV4Engine`, `IpV4EngineDeMux`, `IpV4EngineRx`, and `IpV4EngineTx`. -- 2026-04-17: Added `ethernet/IpV4Engine/wrappers/IgmpV2EngineWrapper.vhd` plus `tests/ethernet/IpV4Engine/test_IgmpV2Engine.py`, extending the IPv4 helper layer with IGMP packet builders in `tests/ethernet/IpV4Engine/ipv4_test_utils.py`. The new leaf bench covers power-up membership reports, general-query re-arming, and suppression of a pending local report when a matching inbound membership report is observed, while documenting the two leaf-boundary stale-field quirks that `IpV4EngineTx` ignores. -- 2026-04-16: Merged the current `pre-release` branch into `verification-2`, so this branch line now contains the already-landed SSI and PGP waves from PR #1391 and PR #1392 in addition to the manual Ethernet slice. -- 2026-04-16: Refreshed the planning docs to move the active frontier from “continue Ethernet next” to “refresh the stale queue/override inputs, then resume from the real merged-branch frontier.” -- 2026-04-17: Switched the planning docs from queue-driven task selection to user-directed frontier tracking. The graph and queue artifacts remain checked in for provenance, but `rtl_regression_progress.md` and `rtl_regression_handoff.md` are now the active done/open source of truth. -- 2026-04-17: Expanded `tests/ethernet/RawEthFramer/test_RawEthFramerTx.py` to cover the successful multi-beat unicast forwarding path after lookup resolution. The new leaf test holds the source frame through the exported request phase, models the same nonzero lookup latency the integrated `RawEthFramer` wrapper inserts before `ack`, and validates the full MAC-side wire image alongside the existing request, broadcast-bypass, and zero-MAC drop checks. -- 2026-04-17: Completed the Ethernet thin-area follow-up across `EthMacCore`, `UdpEngine`, and `IpV4Engine`. Added checked-in wrappers `ethernet/EthMacCore/wrappers/EthMacRxBypassWrapper.vhd` and `ethernet/EthMacCore/wrappers/EthMacTxBypassWrapper.vhd`, added `tests/ethernet/EthMacCore/test_EthMacRxBypass.py` and `tests/ethernet/EthMacCore/test_EthMacTxBypass.py`, widened `test_EthMacRxImport.py` / `test_EthMacTxExport.py` to cover the current placeholder `XLGMII` contract, widened `tests/ethernet/UdpEngine/test_UdpEngine.py` and `tests/ethernet/UdpEngine/test_UdpEngineWrapper.py` across additional client/server routing paths, widened `tests/ethernet/IpV4Engine/test_IpV4Engine.py` with a top-level protocol-TX path, and deepened `tests/ethernet/IpV4Engine/test_IcmpEngine.py` with truncated-request rejection, EOFE preservation, and post-reject recovery checks. The combined local validation command `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/EthMacCore/test_EthMacRxImport.py tests/ethernet/EthMacCore/test_EthMacTxExport.py tests/ethernet/EthMacCore/test_EthMacRxBypass.py tests/ethernet/EthMacCore/test_EthMacTxBypass.py tests/ethernet/UdpEngine/test_UdpEngine.py tests/ethernet/UdpEngine/test_UdpEngineWrapper.py tests/ethernet/IpV4Engine/test_IpV4Engine.py tests/ethernet/IpV4Engine/test_IcmpEngine.py` passes locally with `14 passed`. -- 2026-03-20: Added an explicit project rule to comment new Python regression code where intent or runner behavior is not self-evident. -- 2026-03-20: Expanded `FifoAsync` to a validated 12-case parameter matrix and enabled default pytest xdist parallelization with `pytest.ini`. -- 2026-03-20: Added package-coverage policy: packages are covered transitively unless a behavioral helper warrants a dedicated wrapper test. -- 2026-03-20: Switched from pilot-only work to the bottom-up rollout and selected `FifoSync` as the next low-level target. -- 2026-03-20: Implemented and validated an 11-case `FifoSync` matrix under `tests/base/fifo/test_FifoSync.py`. -- 2026-03-20: Added and generated the first-pass RTL instantiation graph to guide bottom-up rollout decisions and reduce repeated test effort across the hierarchy. -- 2026-03-20: Implemented and validated a 6-case `Synchronizer` matrix under `tests/base/sync/test_Synchronizer.py` as the next graph-guided `base` leaf. -- 2026-03-20: Documented that local Python commands should use `./.venv/bin/python` unless the virtualenv is already activated, after a bare `python` invocation failed due to a missing shell shim. -- 2026-03-20: Implemented and validated the next five graph-guided `base` regressions: `SynchronizerVector`, `RstPipeline`, `SimpleDualPortRam`, `FifoOutputPipeline`, and `FifoWrFsm`. -- 2026-03-20: Updated the planning and handoff docs to preserve the user's tutorial-style cocotb comment preference for future regressions. -- 2026-03-20: Implemented and validated the next 10 graph-guided `base` regressions: `Crc32Parallel`, `Crc32`, `CRC32Rtl`, `RstSync`, `PwrUpRst`, `SynchronizerEdge`, `SynchronizerOneShot`, `TrueDualPortRam`, `LutRam`, and `FifoRdFsm`. -- 2026-03-20: Expanded `Crc32` coverage beyond the default IEEE polynomial to include Castagnoli and Koopman-style cases, using a thin test-only VHDL wrapper because local GHDL rejected direct runtime overrides of the 32-bit `CRC_POLY_G` vector generic. -- 2026-03-20: Implemented and validated the next 15 graph-guided `base` regressions: `Arbiter`, `ClockDivider`, `Debouncer`, `Gearbox`, `Heartbeat`, `Mux`, `OneShot`, `RegisterVector`, `RstPipelineVector`, `Scrambler`, `WatchDogRst`, `SlvDelay`, `SlvFixedDelay`, `SynchronizerFifo`, and `SynchronizerOneShotCnt` (`41 passed`). -- 2026-03-21: Replaced the checked-in `Heartbeat`/`Debouncer` wrapper files with a shared generated-wrapper helper in `tests/common/regression_utils.py` and revalidated both the targeted tests (`6 passed`) and the full 15-module batch (`41 passed`). -- 2026-03-21: Implemented and validated the next 10-module wrapper/integration batch: `DspComparator`, `Fifo`, `FifoCascade`, `FifoMux`, `AsyncGearbox`, `SynchronizerOneShotVector`, `SynchronizerOneShotCntVector`, `SyncStatusVector`, `SyncTrigPeriod`, and `SyncMinMax` (`18 passed`). -- 2026-03-21: Added `start_lockstep_clocks()` in `tests/common/regression_utils.py` for `COMMON_CLK_G` style benches and recorded that `FifoCascade`/`FifoMux` should keep intentionally narrow wrapper coverage under the current GHDL flow instead of forcing unstable branches. -- 2026-03-21: Implemented and validated the remaining non-vendor, non-dummy `base/` batch: `MasterRamIpIntegrator`, `SlaveRamIpIntegrator`, `DualPortRam`, `SlvDelayRam`, `SlvDelayFifo`, `SyncClockFreq`, `SyncTrigRate`, and `SyncTrigRateVector` (`15 passed`). `LutFixedDelay` remains deferred because it still depends on `SinglePortRamPrimitive`. -- 2026-03-21: Tightened the comment policy for Python regressions: header-level methodology comments and in-body tutorial comments are both required, the methodology block should use wrapped `Sweep`/`Stimulus`/`Checks`/`Timing` bullets, and the text should stay module-specific and editor-readable. -- 2026-03-21: Started the first post-`base/` simulator-friendly `axi/` follow-on with `AxiStreamPipeline` and `AxiLiteCrossbar` as the next migration targets, using the legacy flat Python benches only as intent/reference while keeping the new work under subsystem-packaged tests. -- 2026-03-21: Implemented and validated `AxiStreamPipeline` and `AxiLiteCrossbar` as the first post-`base/` `axi/` follow-on. `AxiStreamPipeline` uses a thin flat-port wrapper plus a curated pass-through/staged/reset sweep, and `AxiLiteCrossbar` uses a cocotb-facing wrapper for routed-region, decode-error, and concurrent-traffic checks (`4 passed` combined). -- 2026-03-21: Refactored the `AxiStreamPipeline` test adapter to reuse the existing `SlaveAxiStreamIpIntegrator`/`MasterAxiStreamIpIntegrator` shim pair for standard AXIS flattening, preserving only the pipeline-specific sideband wiring in the adapter (`3 passed` on the pipeline regression after the refactor). -- 2026-03-21: Moved and renamed the `AxiStreamPipeline` adapter to `axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd` so its path and name match the existing AXI IP-integrator adapter conventions and live with the rest of the AXI adapter layer. -- 2026-03-21: Tightened the planning rule for cocotb-facing shim placement: if a VHDL adapter is needed to fit a module into cocotb, place it in the nearest real subsystem `ip_integrator/` tree alongside the existing integration shims rather than under `tests/`. -- 2026-03-21: Collapsed the large instantiation-graph output into a reviewed flat phase-1 module build order in `rtl_regression_plan.md` so future windows can take the next queued module directly instead of re-analyzing the JSON graph before every step. -- 2026-03-21: Resumed the flat `axi/` queue at `AxiStreamMux` and chose a dedicated IP-integrator adapter over the existing combined DeMux/Mux harness so the new cocotb bench can stay mux-specific and exercise arbitration plus `TDEST`/`TID` remap behavior directly. -- 2026-03-21: Implemented and validated `AxiStreamMux` with `axi/axi-stream/ip_integrator/AxiStreamMuxIpIntegrator.vhd` plus `tests/axi/axi_stream/test_AxiStreamMux.py`. The validated 3-case sweep covers indexed arbitration with explicit priority and `disableSel`, routed `TDEST`/`TID` remap under backpressure, and staged asynchronous active-low reset recovery (`3 passed`). -- 2026-03-21: Revalidated the current small `axi/` follow-on subset with `tests/axi/axi_stream/test_AxiStreamPipeline.py`, `tests/axi/axi_stream/test_AxiStreamMux.py`, and `tests/axi/axi_lite/test_AxiLiteCrossbar.py` in one run (`7 passed`). -- 2026-03-21: Started the next flat-queue `axi/` item, `AxiStreamDeMux`, and began evaluating whether a dedicated cocotb-facing adapter is cleaner than reusing the older combined DeMux/Mux harness for the first narrow wrapper bench. -- 2026-03-21: Implemented and validated `AxiStreamDeMux` with `axi/axi-stream/ip_integrator/AxiStreamDeMuxIpIntegrator.vhd` plus `tests/axi/axi_stream/test_AxiStreamDeMux.py`. The validated 3-case sweep covers indexed routing, exact-match routed decode under output backpressure, and dynamic-route/drop/reset behavior (`3 passed`). -- 2026-03-21: Revalidated the current small `axi/` follow-on subset with `tests/axi/axi_stream/test_AxiStreamPipeline.py`, `tests/axi/axi_stream/test_AxiStreamMux.py`, `tests/axi/axi_stream/test_AxiStreamDeMux.py`, and `tests/axi/axi_lite/test_AxiLiteCrossbar.py` in one run (`10 passed`). -- 2026-03-21: Started scoping the next five flat-queue modules after `AxiStreamDeMux`: `AxiStreamResize`, `AxiLiteAsync`, `AxiLiteMaster`, `AxiLiteToDrp`, and `AxiDualPortRam`, beginning with a wrapper/reference-asset pass to separate straightforward benches from blocks that still need adapter cleanup. -- 2026-03-21: Implemented and validated the next five flat-queue modules: `AxiStreamResize`, `AxiLiteAsync`, `AxiLiteMaster`, `AxiLiteToDrp`, and `AxiDualPortRam`. The five-module batch passes with `10 passed`, and a broader AXI follow-on sanity run across pipeline, mux, demux, resize, crossbar, async, master, DRP bridge, and dual-port RAM passes with `20 passed`. `AxiLiteAsync` and `AxiLiteToDrp` intentionally keep only the stable common-clock subsets in this first batch; the async CDC/arbitration branches remain open. -- 2026-03-21: Replaced the hand-maintained flat phase-1 list in the plan with a generated path-qualified bottom-up queue emitted by `scripts/build_rtl_instantiation_graph.py` into `docs/_meta/rtl_phase1_queue.{md,json}`. Checked in `docs/_meta/rtl_phase1_queue_overrides.json` as the only supported input for manual phase-1 deferrals and ordering exceptions; the initial generated queue contains `411` phase-1 modules with `0` unresolved duplicate-name phase-1 edges under the current filter set. -- 2026-03-21: Implemented and validated the next 10 generated-queue AXI modules: `AxiLiteRegs`, `AxiLiteRespTimer`, `AxiLiteSlave`, `AxiLiteWriteFilter`, `AxiVersion`, `AxiStreamCombiner`, `AxiStreamFlush`, `AxiStreamGearboxPack`, `AxiStreamGearboxUnpack`, and `AxiStreamSplitter`. The combined validation command across those 10 module files passes with `14 passed`. -- 2026-03-26: Implemented and validated `AxiReadPathMux`, `AxiWritePathMux`, and `AxiToAxiLite` with subsystem-local IP-integrator adapters plus new `tests/axi/axi4/` and `tests/axi/bridge/` cocotb benches. `tests/axi/axi4/test_AxiResize.py` is also present on this branch, including the restored `32-bit -> 64-bit` upsize case, but that case is expected to fail here until the separate `AxiResize` RTL-fix branch is merged. -- 2026-03-26: Implemented and validated the next 10 generated-queue AXI modules: `AxiStreamDmaV2WriteMux`, `AxiLiteMasterProxy`, `AxiLiteSequencerRam`, `AxiStreamCompact`, `AxiStreamConcat`, `AxiStreamFrameRateLimiter`, `AxiStreamPrbsFlowCtrl`, `AxiStreamRepeater`, `AxiStreamShift`, and `AxiStreamTrailerAppend`. Added subsystem-local wrappers under `axi/dma/ip_integrator/`, `axi/axi-lite/ip_integrator/`, and `axi/axi-stream/ip_integrator/`, plus new cocotb benches under `tests/axi/`. The combined validation run across those 10 module files passes with `10 passed`. `AxiStreamCompact`, `AxiStreamFrameRateLimiter`, and `AxiStreamDmaV2WriteMux` currently keep intentionally narrow first-pass checks on this branch instead of forcing the less stable simulator corners. -- 2026-03-26: Implemented the next 10 generated-queue AXI module benches: `AxiStreamTrailerRemove`, `AxiRam`, `AxiLiteToIpBus`, `IpBusToAxiLite`, `AxiStreamDmaV2Read`, `AxiStreamGearbox`, `AxiStreamTap`, `AxiStreamDmaRead`, `AxiStreamDmaV2Write`, and `AxiStreamTimer`. The stable 9-module subset passes with `9 passed`, while `AxiStreamDmaV2Read` remains an expected open failure on this branch because the new minimal aligned one-beat reproducer still aborts at `31 ns` inside the DUT with `std_logic_arith.vhdl:2014:9: ARG is too large in CONV_INTEGER`. -- 2026-04-02: Fixed the remaining `AxiStreamDmaV2Read` open issue by bounding the byte-count `conv_integer()` paths in `axi/axi4/rtl/AxiPkg.vhd`, replacing terminal-beat `tKeep`/`tStrb` generation in `axi/dma/rtl/v2/AxiStreamDmaV2Read.vhd` with direct `slv` mask construction, and expanding `tests/axi/dma/test_AxiStreamDmaV2Read.py` into aligned and short-terminal-beat cases. Local validation now passes with `./.venv/bin/python -m pytest -n 0 -q tests/axi/dma/test_AxiStreamDmaV2Read.py` (`2 passed`). -- 2026-03-26: Replaced the temporary legacy-harness `AxiStreamDmaRead` smoke with a cocotb-owned bench plus `AxiStreamDmaReadIpIntegrator.vhd`. The new test drives the DMA request directly, uses a cocotb AXI RAM model, applies output backpressure, and checks payload plus sideband fields without delegating pass/fail to the old VHDL testbench shell (`1 passed`). -- 2026-03-26: Retargeted the remaining legacy-entity holdouts in the current validated set. `AxiRam` now uses `AxiRamIpIntegrator.vhd` plus a cocotb AXI master round-trip bench, `AxiStreamGearbox` now targets `AxiStreamGearboxIpIntegrator.vhd` instead of the old `tb/` shell, and `AxiLiteCrossbar` now targets `AxiLiteCrossbarIpIntegrator.vhd` instead of `AxiLiteCrossbarTb.vhd` (`3 passed` across the retargeted tests). -- 2026-03-26: Resumed the generated queue at `AxiRateGen` and started scoping the cocotb-facing AXI4/IP-integrator pattern for the next `axi/axi4/` regression. -- 2026-03-26: Implemented and validated `AxiRateGen` with `axi/axi4/ip_integrator/AxiRateGenIpIntegrator.vhd` plus `tests/axi/axi4/test_AxiRateGen.py`. The stable common-clock subset passes with `1 passed`, and a nearby AXI4 sanity run across `AxiReadPathMux`, `AxiWritePathMux`, `AxiRam`, and `AxiRateGen` passes with `4 passed`. -- 2026-03-26: Tightened the planning docs so wrapper readability is explicit instead of implicit: permanent cocotb-facing `*IpIntegrator.vhd` files should include the standard SURF banner and brief section comments in the first edit, just like the Python benches are required to carry their methodology and tutorial comments. -- 2026-03-26: Tightened the planning docs again so the Python-side header rule is explicit too: checked-in cocotb tests should keep the standard SURF/SLAC banner in addition to the required methodology block and tutorial comments; this is now documented as a first-draft requirement rather than an implied cleanup step. -- 2026-03-26: Corrected the queue frontier after noticing the prior resume notes had jumped ahead to `IpV4Engine`. The real next unfinished non-deferred queue entry is `EthMacRxShift`, followed by `EthMacTxExportGmii`, `EthMacTxShift`, `IpV4EngineRx`, `IpV4EngineTx`, `RawEthFramer`, `UdpEngineRx`, `GLinkTxToRx`, `HtspRx`, and `HtspTx`. -- 2026-03-26: Changed the rollout policy to finish `axi/` first before returning to other subsystems. Recorded temporary `ethernet` and `protocols` subsystem deferrals in `docs/_meta/rtl_phase1_queue_overrides.json`, regenerated the queue, and set the active axi frontier to `AxiResize`. -- 2026-03-27: Implemented and validated the final 11 pending `axi/` benches: `AxiReadEmulate`, `AxiRingBuffer`, `AxiWriteEmulate`, `AxiStreamDmaRingRead`, `AxiStreamDmaWrite`, `AxiLiteRamSyncStatusVector`, `AxiStreamMonAxiL`, `AxiStreamDma`, `AxiStreamDmaFifo`, `AxiStreamDmaRingWrite`, and `AxiMonAxiL`. Added the required subsystem-local `*IpIntegrator.vhd` wrappers, kept the new Python tests fully commented with the standard SURF header plus methodology/tutorial notes, and validated the final batch with `./.venv/bin/python -m pytest -n 0 -q ...` across the 11 files (`11 passed`). -- 2026-03-27: The new `AxiStreamDmaRingWrite` regression exposed a width-safety issue in the DUT pointer update under GHDL. Fixed `axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd` so `dmaAck.size` is sliced back to the local pointer width before incrementing `nextAddr`, which keeps the logic behavior unchanged for narrower address maps while making the testbench-safe wrapper configuration simulate cleanly. -- 2026-03-26: Implemented and validated the next 10 generated-queue AXI modules after the two known expected-open skips (`AxiResize` and `AxiStreamDmaV2Read`): `AxiStreamScatterGather`, `AxiMemTester`, `AxiStreamDmaV2Desc`, `AxiStreamDmaV2Fifo`, `AxiReadPathFifo`, `AxiWritePathFifo`, `AxiStreamDmaV2`, `AxiStreamBatchingFifo`, `AxiStreamMon`, and `AxiStreamRingBuffer`. Added the required new wrapper files under `axi/axi4/ip_integrator/`, `axi/axi-stream/ip_integrator/`, and `axi/dma/ip_integrator/`, fixed `tests/common/regression_utils.py` to stringify simulator env values before dispatch, and validated the combined batch with `./.venv/bin/python -m pytest -n 0 -q tests/axi/axi_stream/test_AxiStreamScatterGather.py tests/axi/axi4/test_AxiMemTester.py tests/axi/dma/test_AxiStreamDmaV2Desc.py tests/axi/dma/test_AxiStreamDmaV2Fifo.py tests/axi/axi4/test_AxiReadPathFifo.py tests/axi/axi4/test_AxiWritePathFifo.py tests/axi/dma/test_AxiStreamDmaV2.py tests/axi/axi_stream/test_AxiStreamBatchingFifo.py tests/axi/axi_stream/test_AxiStreamMon.py tests/axi/axi_stream/test_AxiStreamRingBuffer.py` (`10 passed`). -- 2026-04-20: Started the first `ethernet/RoCEv2` phase-1 slice with the stable VHDL-only helper leaves instead of the mixed-language top wrappers. Added `ethernet/RoCEv2/wrappers/EthMacPrepareForICrcWrapper.vhd` and `ethernet/RoCEv2/wrappers/EthMacRxCheckICrcWrapper.vhd`, implemented `tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py` and `tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py`, linted both wrappers cleanly with `./.venv/bin/vsg -c vsg-linter.yml -f ...`, validated the pair with `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py` (`2 passed`), and recorded the remaining open RoCEv2 work as the mixed-language wrapper/assembly path rather than claiming full-family coverage. -- 2026-04-20: Added the pure-VHDL RoCEv2 follow-on benches `tests/ethernet/RoCEv2/test_RoceResizeAndSwap.py` and `test_RoceConfigurator.py` plus their checked-in wrappers `ethernet/RoCEv2/wrappers/RoceResizeAndSwapIpIntegrator.vhd` and `RoceConfiguratorWrapper.vhd`, and validated the pure-VHDL RoCEv2 bench set with `./.venv/bin/python -m pytest -n 0 -q tests/ethernet/RoCEv2/test_EthMacPrepareForICrc.py tests/ethernet/RoCEv2/test_EthMacRxCheckICrc.py tests/ethernet/RoCEv2/test_RoceResizeAndSwap.py tests/ethernet/RoCEv2/test_RoceConfigurator.py` (`4 passed`). -- 2026-04-20: Removed the temporary local CRC stand-ins and the stub-backed `EthMacTxRoCEv2` / `EthMacRxRoCEv2` benches after clarifying the intended boundary: there should be one cocotb test module per entity in `ethernet/RoCEv2/rtl`, but `blue-*` must remain real transitive dependencies rather than being replaced with local test doubles. The current open RoCEv2 bench set is therefore `EthMacCrcAxiStreamWrapperSend`, `EthMacCrcAxiStreamWrapperRecv`, `EthMacTxRoCEv2`, `EthMacRxRoCEv2`, and `RoceEngineWrapper`, all of which now require a mixed-language simulation path. -- 2026-04-20: Added the next CoaXPress assembly pass with `tests/protocols/coaxpress/test_CoaXPressRx.py`, `test_CoaXPressCore.py`, and the checked-in wrappers `protocols/coaxpress/core/wrappers/CoaXPressRxWrapper.vhd` and `CoaXPressCoreWrapper.vhd`. The validated subset now covers the one-lane `CoaXPressRx` receive assembly and the AXI-Lite-controlled `CoaXPressCore` TX/config assembly path. `tests/protocols/coaxpress/test_CoaXPressConfig.py` was kept in-tree as a skipped investigation bench because the real SRP-driven `CoaXPressConfig` request path does not complete under the current `CoaXPressConfig` / `SrpV3AxiLite` integration, which is now recorded as the remaining pure-VHDL CoaXPress blocker. -- 2026-04-20: Deepened the CoaXPress receive/bridge coverage without changing RTL scope. `test_CoaXPressRxHsFsm.py` now includes a dual-lane step/alignment case, `test_CoaXPressRx.py` now includes a dual-lane lane-rotation integration case through a generalized `CoaXPressRxWrapper.vhd`, `test_CoaXPressRxLane.py` now covers alternate-success control acknowledgments plus truncated-event guardrails, `test_CoaXPressTxLsFsm.py` now covers the slower implemented low-speed-rate trigger cadence with inverted-trigger mapping, and the CXPoF bridge leaf benches now include HKP, negative lane-placement checks, and partial-lane low-speed fill behavior. The focused validation run across those six files passed locally with `8 passed`. -- 2026-05-01: Integrated the latest `coaxpress-tests` progress into the `verification-2` merge worktree while preserving the `verification-2` `docs/_meta` artifacts. The CoaXPress conflict resolution takes the updated bridge README/test coverage from `coaxpress-tests`: leaf HKP-to-payload mixing, malformed control-lane guardrails for `/S/`, `/Q/`, `/T/`, and `/E/`, and top-level 64-bit RX gearbox cases for `/E/` abort/recovery, HKP-to-payload transition, and lane-0 `/Q/` no-output/recovery. Focused validation used `./.venv/bin/python -m pytest -n auto --dist=worksteal -q tests/protocols/coaxpress` and passed with `17 passed, 1 skipped`; the skipped bench remains `CoaXPressConfig`. From 0a91cebaf36496c56dac80882d88d9f5b6af32fb Mon Sep 17 00:00:00 2001 From: Luca Scomparin Date: Fri, 8 May 2026 13:17:38 -0700 Subject: [PATCH 90/92] Added write guard to Phantom cameras --- python/surf/protocols/coaxpress/_Bootstrap.py | 19 ++++++++++++ .../surf/protocols/coaxpress/_PhantomS641.py | 31 +++++++++++++++++-- .../surf/protocols/coaxpress/_PhantomS991.py | 31 +++++++++++++++++-- 3 files changed, 77 insertions(+), 4 deletions(-) diff --git a/python/surf/protocols/coaxpress/_Bootstrap.py b/python/surf/protocols/coaxpress/_Bootstrap.py index 11957aafad..6488fc5f72 100644 --- a/python/surf/protocols/coaxpress/_Bootstrap.py +++ b/python/surf/protocols/coaxpress/_Bootstrap.py @@ -16,6 +16,16 @@ def __init__(self, GenDc=False, CoaXPressAxiL=None, **kwargs): super().__init__(**kwargs) self.CoaXPressAxiL = CoaXPressAxiL + # Default write guard: no-op until setAcquisitionMonitor() provides a camera. + # Uses the pre-write listener API from rogue PR #1229. + self._acq_var = None + + def _write_guard(path, value, state): + if self._acq_var is not None and self._acq_var.value(): + raise pr.WriteBlockedError(path, 'cannot write registers during acquisition') + + self.addPreWriteListener(_write_guard) + self.add(pr.RemoteVariable( name = 'Standard', description = 'This register shall provide a magic number indicating the Device implements the CoaXPress standard. The magic number shall be 0xC0A79AE5.', @@ -633,6 +643,15 @@ def __init__(self, GenDc=False, CoaXPressAxiL=None, **kwargs): dependencies = [self.MajorVersionUsed,self.MinorVersionUsed], )) + def setAcquisitionMonitor(self, camera): + """Block Bootstrap register writes while the given camera is acquiring. + + Call this after the camera device is ready. The guard checks + ``camera.IsAcquiring`` before every write and raises + ``pr.WriteBlockedError`` if acquisition is in progress. + """ + self._acq_var = camera.IsAcquiring + def DeviceDiscovery(self, arg=None): # Updates all the local device register values self.CoaXPressAxiL.readBlocks(recurse=True) diff --git a/python/surf/protocols/coaxpress/_PhantomS641.py b/python/surf/protocols/coaxpress/_PhantomS641.py index ec61dc70b8..bcaa1e8b20 100755 --- a/python/surf/protocols/coaxpress/_PhantomS641.py +++ b/python/surf/protocols/coaxpress/_PhantomS641.py @@ -249,6 +249,22 @@ def __init__(self, isPhantomS711=False, **kwargs): }, )) + self.add(pr.LocalVariable( + name = 'IsAcquiring', + description = 'True while the camera is acquiring frames.', + mode = 'RO', + value = False, + hidden = True, + )) + + def _acq_start(cmd): + cmd.post(1) + self.IsAcquiring.set(True) + + def _acq_stop(cmd): + cmd.post(0) + self.IsAcquiring.set(False) + self.add(pr.RemoteCommand( name = 'AcquisitionStart', description = 'This feature starts the Acquisition of the device.', @@ -256,7 +272,7 @@ def __init__(self, isPhantomS711=False, **kwargs): base = pr.UIntBE, bitSize = 8, bitOffset = 24, - function = lambda cmd: cmd.post(1), + function = _acq_start, )) self.add(pr.RemoteCommand( @@ -266,7 +282,7 @@ def __init__(self, isPhantomS711=False, **kwargs): base = pr.UIntBE, bitSize = 8, bitOffset = 24, - function = lambda cmd: cmd.post(0), + function = _acq_stop, )) self.add(pr.RemoteVariable( @@ -783,3 +799,14 @@ def __init__(self, isPhantomS711=False, **kwargs): mode = 'RW', hidden = True, )) + + # Block all register writes while the camera is acquiring. + # AcquisitionStart and AcquisitionStop must remain writable to allow stopping. + # Uses the pre-write listener API from rogue PR #1229. + def _write_guard(path, value, state): + if state.get(self.IsAcquiring.path): + name = path.rsplit('.', 1)[-1] + if name not in ('AcquisitionStart', 'AcquisitionStop', 'IsAcquiring'): + raise pr.WriteBlockedError(path, 'cannot write registers during acquisition') + + self.addPreWriteListener(_write_guard, stateVars=[self.IsAcquiring]) diff --git a/python/surf/protocols/coaxpress/_PhantomS991.py b/python/surf/protocols/coaxpress/_PhantomS991.py index e41e8895c9..f3322cef86 100644 --- a/python/surf/protocols/coaxpress/_PhantomS991.py +++ b/python/surf/protocols/coaxpress/_PhantomS991.py @@ -166,6 +166,22 @@ def __init__(self, **kwargs): }, )) + self.add(pr.LocalVariable( + name = 'IsAcquiring', + description = 'True while the camera is acquiring frames.', + mode = 'RO', + value = False, + hidden = True, + )) + + def _acq_start(cmd): + cmd.post(1) + self.IsAcquiring.set(True) + + def _acq_stop(cmd): + cmd.post(0) + self.IsAcquiring.set(False) + self.add(pr.RemoteCommand( name = 'AcquisitionStart', description = 'This feature starts the Acquisition of the device.', @@ -173,7 +189,7 @@ def __init__(self, **kwargs): base = pr.UIntBE, bitSize = 8, bitOffset = 24, - function = lambda cmd: cmd.post(1), + function = _acq_start, )) self.add(pr.RemoteCommand( @@ -183,7 +199,7 @@ def __init__(self, **kwargs): base = pr.UIntBE, bitSize = 8, bitOffset = 24, - function = lambda cmd: cmd.post(0), + function = _acq_stop, )) self.add(pr.RemoteVariable( @@ -636,3 +652,14 @@ def __init__(self, **kwargs): mode = 'RW', hidden = True, )) + + # Block all register writes while the camera is acquiring. + # AcquisitionStart and AcquisitionStop must remain writable to allow stopping. + # Uses the pre-write listener API from rogue PR #1229. + def _write_guard(path, value, state): + if state.get(self.IsAcquiring.path): + name = path.rsplit('.', 1)[-1] + if name not in ('AcquisitionStart', 'AcquisitionStop', 'IsAcquiring'): + raise pr.WriteBlockedError(path, 'cannot write registers during acquisition') + + self.addPreWriteListener(_write_guard, stateVars=[self.IsAcquiring]) From bb09f3072572bbcde5a18de62151bebf59a2016d Mon Sep 17 00:00:00 2001 From: Luca Scomparin Date: Fri, 8 May 2026 13:20:10 -0700 Subject: [PATCH 91/92] Added rogue version guard for write guard functionality --- python/surf/protocols/coaxpress/_Bootstrap.py | 4 ++++ python/surf/protocols/coaxpress/_PhantomS641.py | 3 +++ python/surf/protocols/coaxpress/_PhantomS991.py | 4 ++++ 3 files changed, 11 insertions(+) diff --git a/python/surf/protocols/coaxpress/_Bootstrap.py b/python/surf/protocols/coaxpress/_Bootstrap.py index 6488fc5f72..b34f72b65d 100644 --- a/python/surf/protocols/coaxpress/_Bootstrap.py +++ b/python/surf/protocols/coaxpress/_Bootstrap.py @@ -9,11 +9,15 @@ #----------------------------------------------------------------------------- import pyrogue as pr +import rogue import time class Bootstrap(pr.Device): def __init__(self, GenDc=False, CoaXPressAxiL=None, **kwargs): super().__init__(**kwargs) + + rogue.Version.minVersion('6.13.0') + self.CoaXPressAxiL = CoaXPressAxiL # Default write guard: no-op until setAcquisitionMonitor() provides a camera. diff --git a/python/surf/protocols/coaxpress/_PhantomS641.py b/python/surf/protocols/coaxpress/_PhantomS641.py index bcaa1e8b20..7849bff2ef 100755 --- a/python/surf/protocols/coaxpress/_PhantomS641.py +++ b/python/surf/protocols/coaxpress/_PhantomS641.py @@ -9,10 +9,13 @@ #----------------------------------------------------------------------------- import pyrogue as pr +import rogue class PhantomS641(pr.Device): def __init__(self, isPhantomS711=False, **kwargs): super().__init__(**kwargs) + + rogue.Version.minVersion('6.13.0') ############################################################# # Start of manufacturer-specific register space at 0x00006000 ############################################################# diff --git a/python/surf/protocols/coaxpress/_PhantomS991.py b/python/surf/protocols/coaxpress/_PhantomS991.py index f3322cef86..d90846a506 100644 --- a/python/surf/protocols/coaxpress/_PhantomS991.py +++ b/python/surf/protocols/coaxpress/_PhantomS991.py @@ -9,10 +9,14 @@ #----------------------------------------------------------------------------- import pyrogue as pr +import rogue class PhantomS991(pr.Device): def __init__(self, **kwargs): super().__init__(**kwargs) + + rogue.Version.minVersion('6.13.0') + ############################################################# # Start of manufacturer-specific register space at 0x00006000 ############################################################# From 6e85c6d545744a794f6dfc03d94fd242a616243c Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 14 May 2026 07:59:04 -0700 Subject: [PATCH 92/92] BittWare QSFP/SFP I2C stabilization: retry+sentinel + CMIS QsfpDd class --- python/surf/devices/transceivers/_Qsfp.py | 174 +++++++---- python/surf/devices/transceivers/_QsfpDd.py | 285 +++++++++++++++++++ python/surf/devices/transceivers/_Sfp.py | 8 + python/surf/devices/transceivers/__init__.py | 107 ++++++- 4 files changed, 502 insertions(+), 72 deletions(-) create mode 100644 python/surf/devices/transceivers/_QsfpDd.py diff --git a/python/surf/devices/transceivers/_Qsfp.py b/python/surf/devices/transceivers/_Qsfp.py index 89c1dfcfd0..ca973a8477 100644 --- a/python/surf/devices/transceivers/_Qsfp.py +++ b/python/surf/devices/transceivers/_Qsfp.py @@ -14,7 +14,9 @@ # contained in the LICENSE.txt file. #----------------------------------------------------------------------------- +import logging import pyrogue as pr +import rogue import rogue.interfaces.memory as rim import threading @@ -22,10 +24,25 @@ from surf.devices import transceivers +# Exception types to catch and mask in _pollWorker. Mirrors _RETRY_EXC_TYPES +# from __init__.py but defined here to avoid a circular import (this module is +# loaded by __init__.py before _RETRY_EXC_TYPES is defined there). +_POLL_EXC = (rogue.GeneralError, pr.MemoryError) if hasattr(pr, 'MemoryError') else (rogue.GeneralError,) + +_log = logging.getLogger(__name__) + class Qsfp(pr.Device): def __init__(self, advDebug=False, **kwargs): super().__init__(**kwargs) + self.add(pr.LocalVariable( + name = 'ErrorCount', + description = 'I2C read failures after retry exhaustion (cumulative since Rogue start)', + mode = 'RO', + value = 0, + typeStr = 'UInt32', + )) + ################ # Lower Page 00h ################ @@ -39,6 +56,24 @@ def __init__(self, advDebug=False, **kwargs): enum = transceivers.IdentifierDict, )) + self.add(pr.RemoteVariable( + name = 'Flat_mem', + description = 'Upper memory flat or paged', + offset = (2 << 2), + bitSize = 1, + bitOffset = 2, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'Data_Not_Ready', + description = 'Indicates free-side does not yet have valid monitor data. The bit remains high until valid data can be read at which time the bit goes low.', + offset = (2 << 2), + bitSize = 1, + bitOffset = 0, + mode = 'RO', + )) + if advDebug: self.add(pr.RemoteVariable( @@ -61,15 +96,6 @@ def __init__(self, advDebug=False, **kwargs): }, )) - self.add(pr.RemoteVariable( - name = 'Flat_mem', - description = 'Upper memory flat or paged', - offset = (2 << 2), - bitSize = 1, - bitOffset = 2, - mode = 'RO', - )) - self.add(pr.RemoteVariable( name = 'IntL', description = 'Digital state of the IntL Interrupt output pin', @@ -79,15 +105,6 @@ def __init__(self, advDebug=False, **kwargs): mode = 'RO', )) - self.add(pr.RemoteVariable( - name = 'Data_Not_Ready', - description = 'Indicates free-side does not yet have valid monitor data. The bit remains high until valid data can be read at which time the bit goes low.', - offset = (2 << 2), - bitSize = 1, - bitOffset = 0, - mode = 'RO', - )) - self.add(pr.RemoteVariable( name = 'LatchedTxLos', description = 'Interrupt flags for TX LOS', @@ -855,6 +872,12 @@ def __init__(self, **kwargs): def proxyTransaction(self, transaction): self._queue.put(transaction) + def _writePageSelect(self, pageSelect): + """Write the page-select byte if it differs from the cached value, or if the proxy was just armed. _CmisUpperPageProxy overrides this to write the bank-select byte first.""" + if (self.PageSelectByte.value() != pageSelect) or not self._armed: + self._armed = True + self.PageSelectByte.set(value=pageSelect, write=True) + def _pollWorker(self): while True: #print('Main thread loop start') @@ -862,46 +885,81 @@ def _pollWorker(self): if transaction is None: return with self._memLock, transaction.lock(): - - # Determine the page select and register index - pageSelect = ((transaction.address()>>10)&0xFF)-1 - regIndex = ((transaction.address()>>2)&0xFF)-128 - - # Check if the page select has changed - if (self.PageSelectByte.value() != pageSelect) or not self._armed: - - # Set the flag - self._armed = True - - # Perform the hardware write - self.PageSelectByte.set(value=pageSelect, write=True) - - # Check for a write or post TXN - if (transaction.type() == rim.Write) or (transaction.type() == rim.Post): - - # Convert from TXN.data to the write byte array - dataBa = bytearray(4) - transaction.getData(dataBa, 0) - data = int.from_bytes(dataBa, 'little', signed=False) - - # Perform the hardware write - self.UpperPage.set(index=regIndex, value=data, write=True) - - # Close out the transaction - transaction.done() - - # Else this is a read or verify TXN - else: - - # Perform the hardware read - data = self.UpperPage.get(index=regIndex, read=True) - - # Convert from write byte array to TXN.data to the - dataBa = bytearray(data.to_bytes(4, 'little', signed=False)) - transaction.setData(dataBa, 0) - - # Close out the transaction - transaction.done() + try: + # Determine the page select and register index + pageSelect = ((transaction.address()>>10)&0xFF)-1 + regIndex = ((transaction.address()>>2)&0xFF)-128 + + # Gate: suppress upper pages 1-3 if Flat_mem=1 (SFF-8636 flat memory) + # Page 0 (upper page 00h) is always present per spec. + if pageSelect >= 1: + try: + flat = self.parent.Flat_mem.value() + except Exception: + flat = 0 + if flat: + tt = transaction.type() + if (tt == rim.Write) or (tt == rim.Post): + transaction.done() + else: + dataBa = bytearray(4) + transaction.setData(dataBa, 0) + transaction.done() + continue + + self._writePageSelect(pageSelect) + + # Check for a write or post TXN + if (transaction.type() == rim.Write) or (transaction.type() == rim.Post): + + # Convert from TXN.data to the write byte array + dataBa = bytearray(4) + transaction.getData(dataBa, 0) + data = int.from_bytes(dataBa, 'little', signed=False) + + # Perform the hardware write + self.UpperPage.set(index=regIndex, value=data, write=True) + + # Close out the transaction + transaction.done() + + # Else this is a read or verify TXN + else: + + # Perform the hardware read + data = self.UpperPage.get(index=regIndex, read=True) + + # Convert from write byte array to TXN.data to the + dataBa = bytearray(data.to_bytes(4, 'little', signed=False)) + transaction.setData(dataBa, 0) + + # Close out the transaction + transaction.done() + + except _POLL_EXC as _exc: + try: + tt = transaction.type() + if (tt == rim.Write) or (tt == rim.Post): + transaction.done() + else: + dataBa = bytearray(4) + transaction.setData(dataBa, 0) + transaction.done() + except Exception: + pass + try: + self.parent.ErrorCount.set( + self.parent.ErrorCount.value() + 1, write=False) + except Exception: + pass + try: + _log.warning( + f"_UpperPageProxy._pollWorker masked I2C failure " + f"at addr=0x{transaction.address():08x} type={transaction.type()}: " + f"{type(_exc).__name__}: {_exc}" + ) + except Exception: + pass def _stop(self): self._queue.put(None) diff --git a/python/surf/devices/transceivers/_QsfpDd.py b/python/surf/devices/transceivers/_QsfpDd.py new file mode 100644 index 0000000000..f1f0b0bc1b --- /dev/null +++ b/python/surf/devices/transceivers/_QsfpDd.py @@ -0,0 +1,285 @@ +#----------------------------------------------------------------------------- +# Description: +# +# Based on CMIS (Common Management Interface Specification) Rev 5.0 (May 2021) +# http://www.qsfp-dd.com/wp-content/uploads/2021/05/CMIS5p0.pdf +# +#----------------------------------------------------------------------------- +# This file is part of the 'SLAC Firmware Standard Library'. It is subject to +# the license terms in the LICENSE.txt file found in the top-level directory +# of this distribution and at: +# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +# No part of the 'SLAC Firmware Standard Library', including this file, may be +# copied, modified, propagated, or distributed except according to the terms +# contained in the LICENSE.txt file. +#----------------------------------------------------------------------------- + +import pyrogue as pr + +from surf.devices import transceivers +from surf.devices.transceivers._Qsfp import _UpperPageProxy, _ProxySlave, _POLL_EXC, _log # noqa: F401 + +############################################################################## +# CMIS-specific enum dictionaries +############################################################################## + +# CMIS spec revision compliance (lower page byte 1). Upper nibble = major, +# lower nibble = minor. Only published revisions are mapped explicitly; every +# other byte value resolves to 'Undefined' so the GUI cannot misreport an +# unrecognized revision as a known one (D4). +CmisRevisionDict = { + 0x30: 'CMIS 3.0', + 0x40: 'CMIS 4.0', + 0x50: 'CMIS 5.0', + 0x51: 'CMIS 5.1', + 0x52: 'CMIS 5.2', +} + +for _code in range(0x100): + CmisRevisionDict.setdefault(_code, 'Undefined') + +# CMIS Module State Machine (lower page byte 3 bits 3:1) per CMIS §6.3. +ModuleStateDict = { + 0b001: 'ModuleLowPwr', + 0b010: 'ModulePwrUp', + 0b011: 'ModuleReady', + 0b100: 'ModulePwrDn', + 0b101: 'ModuleFault', +} + + +class QsfpDd(pr.Device): + def __init__(self, advDebug=False, **kwargs): + super().__init__(**kwargs) + + self.add(pr.LocalVariable( + name = 'ErrorCount', + description = 'I2C read failures after retry exhaustion (cumulative since Rogue start)', + mode = 'RO', + value = 0, + typeStr = 'UInt32', + )) + + ################ + # Lower Page 00h + ################ + + self.add(pr.RemoteVariable( + name = 'Identifier', + description = 'Type of serial transceiver (SFF-8024 form-factor code)', + offset = (0 << 2), + bitSize = 8, + mode = 'RO', + enum = transceivers.IdentifierDict, + )) + + self.add(pr.RemoteVariable( + name = 'CmisRevision', + description = 'CMIS spec revision compliance (upper nibble = major, lower nibble = minor)', + offset = (1 << 2), + bitSize = 8, + mode = 'RO', + enum = CmisRevisionDict, + )) + + if advDebug: + self.add(pr.RemoteVariable( + name = 'ModuleState', + description = 'CMIS Module State Machine state (lower page byte 3 bits 3:1)', + offset = (3 << 2), + bitSize = 3, + bitOffset = 1, + mode = 'RO', + enum = ModuleStateDict, + )) + + self.addRemoteVariables( + name = 'TemperatureRaw', + description = 'Module temperature (signed 16-bit, 1/256 degC)', + offset = (14 << 2), + bitSize = 8, + mode = 'RO', + number = 2, # BYTE14:BYTE15 + stride = 4, + hidden = True, + ) + + self.add(pr.LinkVariable( + name = 'Temperature', + description = 'Internally measured module temperature', + mode = 'RO', + linkedGet = transceivers.getTemp, + dependencies = [self.TemperatureRaw[0], self.TemperatureRaw[1]], + units = 'degC', + disp = '{:1.3f}', + )) + + self.addRemoteVariables( + name = 'VccRaw', + description = 'Module supply voltage (unsigned 16-bit, 100 uV)', + offset = (16 << 2), + bitSize = 8, + mode = 'RO', + number = 2, # BYTE16:BYTE17 + stride = 4, + hidden = True, + ) + + self.add(pr.LinkVariable( + name = 'Vcc', + description = 'Internally measured supply voltage in transceiver', + mode = 'RO', + linkedGet = transceivers.getVolt, + dependencies = [self.VccRaw[0], self.VccRaw[1]], + units = 'V', + disp = '{:1.3f}', + )) + + ############################## + # Upper Page Proxy + children + ############################## + + self.add(_CmisUpperPageProxy( + name = 'UpperPageProxy', + memBase = self, + offset = 0x0000, + hidden = True, + )) + self.proxy = _ProxySlave(self.UpperPageProxy) + + # Note: the analog SFF-8636 class _QsfpUpperPage00h.py accepts an advDebug kwarg to + # expose the byte-128 'UppperIdentifier' echo (a duplicate of lower-page byte 0 + # kept around for legacy diagnostics). CMIS does not have an analogous echo and + # v1 has no other upper-page debug-only field, so we drop the kwarg. If a future + # CMIS upper-page debug field needs gating, re-introduce advDebug then. + self.add(QsfpDdUpperPage00h( + name = 'UpperPage00h', + memBase = self.proxy, + offset = (0+1) << 10, + )) + + def add(self, node): + pr.Node.add(self, node) + + if isinstance(node, pr.Device): + if node._memBase is None: + node._setSlave(self.proxy) + + +class _CmisUpperPageProxy(_UpperPageProxy): + """CMIS variant that writes bank-select byte 126 before page-select byte 127. + + v1 always writes bank=0 (no banked pages are wired in this version; D1 keeps + the write unconditional per CMIS §8.2.2 + RES-08 mask). + """ + + def __init__(self, **kwargs): + super().__init__(**kwargs) + + self.add(pr.RemoteVariable( + name = 'BankSelectByte', + description = 'CMIS byte 126: bank select (always 0 in v1)', + offset = (126 << 2), + bitSize = 8, + mode = 'WO', + hidden = True, + groups = ['NoStream', 'NoState', 'NoConfig'], + )) + + self._bankArmed = False + + def _writePageSelect(self, pageSelect): + """CMIS §8.2.2: BankSelect MUST be applied before PageSelect. + + v1 always writes bank=0 once at first transaction; the parent's RES-08 + mask absorbs any module NACK (D1). + """ + if not self._bankArmed: + self._bankArmed = True + self.BankSelectByte.set(value=0, write=True) + super()._writePageSelect(pageSelect) + + +class QsfpDdUpperPage00h(pr.Device): + def __init__(self, **kwargs): + super().__init__(**kwargs) + + self.addRemoteVariables( + name = 'VendorNameRaw', + description = 'CMIS vendor name (ASCII)', + offset = (129 << 2), + bitSize = 8, + mode = 'RO', + base = pr.String, + number = 16, # BYTE129:BYTE144 + stride = 4, + hidden = True, + ) + + self.add(pr.LinkVariable( + name = 'VendorName', + description = 'CMIS vendor name (ASCII)', + mode = 'RO', + linkedGet = transceivers.parseStrArrayByte, + dependencies = [self.VendorNameRaw[x] for x in range(16)], + )) + + self.addRemoteVariables( + name = 'VendorPnRaw', + description = 'CMIS vendor part number (ASCII)', + offset = (148 << 2), + bitSize = 8, + mode = 'RO', + base = pr.String, + number = 16, # BYTE148:BYTE163 + stride = 4, + hidden = True, + ) + + self.add(pr.LinkVariable( + name = 'VendorPn', + description = 'CMIS vendor part number (ASCII)', + mode = 'RO', + linkedGet = transceivers.parseStrArrayByte, + dependencies = [self.VendorPnRaw[x] for x in range(16)], + )) + + self.addRemoteVariables( + name = 'VendorSnRaw', + description = 'CMIS vendor serial number (ASCII)', + offset = (166 << 2), + bitSize = 8, + mode = 'RO', + base = pr.String, + number = 16, # BYTE166:BYTE181 + stride = 4, + hidden = True, + ) + + self.add(pr.LinkVariable( + name = 'VendorSn', + description = 'CMIS vendor serial number (ASCII)', + mode = 'RO', + linkedGet = transceivers.parseStrArrayByte, + dependencies = [self.VendorSnRaw[x] for x in range(16)], + )) + + self.addRemoteVariables( + name = 'DateCode', + description = "Vendor's manufacturing date code (ASCII YYMMDD; CMIS lot code bytes 188-189 dropped in v1)", + offset = (182 << 2), + bitSize = 8, + mode = 'RO', + base = pr.String, + number = 6, # BYTE182:BYTE187 (YYMMDD only; CMIS LL lot code bytes 188-189 dropped) + stride = 4, + hidden = True, + ) + + self.add(pr.LinkVariable( + name = 'ManufactureDate', + description = "Vendor's manufacturing date code (ASCII)", + mode = 'RO', + linkedGet = transceivers.getDate, + dependencies = [self.DateCode[x] for x in [0, 1, 4, 5, 2, 3]], + )) diff --git a/python/surf/devices/transceivers/_Sfp.py b/python/surf/devices/transceivers/_Sfp.py index f850088008..ce272b1e53 100644 --- a/python/surf/devices/transceivers/_Sfp.py +++ b/python/surf/devices/transceivers/_Sfp.py @@ -22,6 +22,14 @@ class Sfp(pr.Device): def __init__(self,**kwargs): super().__init__(**kwargs) + self.add(pr.LocalVariable( + name = 'ErrorCount', + description = 'I2C read failures after retry exhaustion (cumulative since Rogue start)', + mode = 'RO', + value = 0, + typeStr = 'UInt32', + )) + ##################################################### # Serial ID: Data Fields – Address A0h # ##################################################### diff --git a/python/surf/devices/transceivers/__init__.py b/python/surf/devices/transceivers/__init__.py index af564bf7ea..b24928b68b 100644 --- a/python/surf/devices/transceivers/__init__.py +++ b/python/surf/devices/transceivers/__init__.py @@ -11,8 +11,47 @@ from surf.devices.transceivers._QsfpUpperPage00h import * from surf.devices.transceivers._QsfpUpperPage03h import * from surf.devices.transceivers._Qsfp import * +from surf.devices.transceivers._QsfpDd import * import math +import rogue +import pyrogue as pr + +# Retry constants for I2C read failures. +_RETRY_MAX = 3 +_RETRY_SENTINEL = object() # unique sentinel; compare with 'is', never '==' + +# Build exception tuple at import time so the except clause stays cheap. +# pr.MemoryError is present in Rogue >= 6.x builds (confirmed v6.12.0). +_RETRY_EXC_TYPES = (rogue.GeneralError, pr.MemoryError) if hasattr(pr, 'MemoryError') else (rogue.GeneralError,) + + +def _retryGet(var, dep, read): + """Attempt dep.get(read=read) up to _RETRY_MAX times. + + On success (any attempt), return the value immediately. + On _RETRY_EXC_TYPES exhaustion, log a single WARN, increment + ErrorCount on the parent device (best-effort, wrapped in try/except), + and return _RETRY_SENTINEL so the caller can substitute a safe default. + Any other exception type propagates out unchanged. + """ + last_exc = None + for attempt in range(_RETRY_MAX): + try: + return dep.get(read=read) + except _RETRY_EXC_TYPES as exc: + last_exc = exc + # All retries exhausted. + var._log.warning('I2C read failed after %d retries for %s: %s', _RETRY_MAX, dep.path, last_exc) + try: + dev = var.parent + if not hasattr(dev, 'ErrorCount'): + dev = dev.parent + dev.ErrorCount.set(dev.ErrorCount.value() + 1, write=False) + except Exception: + pass + return _RETRY_SENTINEL + # Can't use SparseString + bulk memory read if there is a AXI-Lite Proxy # So recoded using 4 byte transactions + this get function @@ -20,47 +59,80 @@ def parseStrArrayByte(dev, var, read): with dev.root.updateGroup(): retVar = '' for x in range(len(var.dependencies)): - retVar += var.dependencies[x].get(read=read) + val = _retryGet(var, var.dependencies[x], read) + if val is not _RETRY_SENTINEL: + retVar += val return retVar # Used to decode the "dateCode" variable def getDate(dev, var, read): with dev.root.updateGroup(): - year = '20' + var.dependencies[0].get(read=read) + var.dependencies[1].get(read=read) - month = var.dependencies[2].get(read=read) + var.dependencies[3].get(read=read) - day = var.dependencies[4].get(read=read) + var.dependencies[5].get(read=read) + vals = [_retryGet(var, var.dependencies[i], read) for i in range(6)] + if any(v is _RETRY_SENTINEL for v in vals): + return None + year = '20' + vals[0] + vals[1] + month = vals[2] + vals[3] + day = vals[4] + vals[5] # Check if not empty or blank string if month.strip() and day.strip(): return f'{month}/{day}/{year}' def getTemp(dev, var, read): with dev.root.updateGroup(): - msb = var.dependencies[0].get(read=read) - lsb = var.dependencies[1].get(read=read) + try: + if var.parent.Data_Not_Ready.value(): + return float('nan') + except Exception: + pass + msb = _retryGet(var, var.dependencies[0], read) + lsb = _retryGet(var, var.dependencies[1], read) + if msb is _RETRY_SENTINEL or lsb is _RETRY_SENTINEL: + return float('nan') raw = (msb << 8) | lsb # Return value in units of degC return float(raw)/256.0 def getVolt(dev, var, read): with dev.root.updateGroup(): - msb = var.dependencies[0].get(read=read) - lsb = var.dependencies[1].get(read=read) + try: + if var.parent.Data_Not_Ready.value(): + return float('nan') + except Exception: + pass + msb = _retryGet(var, var.dependencies[0], read) + lsb = _retryGet(var, var.dependencies[1], read) + if msb is _RETRY_SENTINEL or lsb is _RETRY_SENTINEL: + return float('nan') raw = (msb << 8) | lsb # Return value in units of Volts return float(raw)*100.0E-6 def getTxBias(dev, var, read): with dev.root.updateGroup(): - msb = var.dependencies[0].get(read=read) - lsb = var.dependencies[1].get(read=read) + try: + if var.parent.Data_Not_Ready.value(): + return float('nan') + except Exception: + pass + msb = _retryGet(var, var.dependencies[0], read) + lsb = _retryGet(var, var.dependencies[1], read) + if msb is _RETRY_SENTINEL or lsb is _RETRY_SENTINEL: + return float('nan') raw = (msb << 8) | lsb # Return value in units of mA return float(raw)*0.002 def getOpticalPwr(dev, var, read): with dev.root.updateGroup(): - msb = var.dependencies[0].get(read=read) - lsb = var.dependencies[1].get(read=read) + try: + if var.parent.Data_Not_Ready.value(): + return float('nan') + except Exception: + pass + msb = _retryGet(var, var.dependencies[0], read) + lsb = _retryGet(var, var.dependencies[1], read) + if msb is _RETRY_SENTINEL or lsb is _RETRY_SENTINEL: + return float('nan') raw = (msb << 8) | lsb if raw == 0: pwrWatts = 0.1e-6 # Prevent log10(zero) case by forcing 0.1 µW if raw=0 @@ -71,8 +143,15 @@ def getOpticalPwr(dev, var, read): def getTec(dev, var, read): with dev.root.updateGroup(): - msb = var.dependencies[0].get(read=read) - lsb = var.dependencies[1].get(read=read) + try: + if var.parent.Data_Not_Ready.value(): + return float('nan') + except Exception: + pass + msb = _retryGet(var, var.dependencies[0], read) + lsb = _retryGet(var, var.dependencies[1], read) + if msb is _RETRY_SENTINEL or lsb is _RETRY_SENTINEL: + return float('nan') raw = (msb << 8) | lsb # Return value in units of mA return float(raw)*0.1