Verilator 5.046 cannot elaborate INIT/OBI transport modules: member access on `parameter type` request/response ports (REFDTYPE)

[DanielKellerM]

Summary

Verilator 5.046 cannot elaborate the iDMA INIT and OBI transport-layer
modules. Every member access on a port whose type is a parameter type
request/response struct (read_req_t, read_rsp_t, write_req_t,
write_rsp_t) is rejected as %Error-UNSUPPORTED: Member call on object ... which is a 'REFDTYPE ...'. This blocks Verilator-based simulation of any design
that instantiates a backend containing these modules (e.g. the
r_obi_rw_init_w_axi / r_axi_rw_init_rw_obi Occamy variants).

QuestaSim 2023.4 elaborates the identical RTL without complaint, so this is a
Verilator limitation interacting with iDMA's genericized transport layer rather
than an outright RTL bug.

Environment

Verilator	5.046 2026-02-28 rev v5.046
iDMA	devel (210982a, #136) — identical lines present
Reference sim	QuestaSim 2023.4 — elaborates fine
Backend variant	rw_axi_rw_init_rw_obi (INIT + OBI), via the inst64 frontend

The construct

The protocol transport modules declare their request/response channels as type
parameters and then perform (sub-)member access on the corresponding ports, e.g.
src/backend/idma_obi_write.sv:

module idma_obi_write #(
    parameter type write_req_t = logic,
    parameter type write_rsp_t = logic,
    ...
)(
    output write_req_t write_req_o,
    input  write_rsp_t write_rsp_i,
    ...
);
    assign write_happening    = ready_to_write & write_rsp_i.gnt;        // line 107
    assign write_req_o.req    = ready_to_write;                          // line 113
    assign write_req_o.a.addr = aw_req_i.obi.a_chan.addr;                // line 142
    assign write_req_o.a.aid  = aw_req_i.obi.a_chan.aid;                 // line 143

Verilator leaves write_req_t / write_rsp_t as a REFDTYPE at the point of
member access and errors:

%Error-UNSUPPORTED: idma_obi_write.sv:107:59: Unsupported: Member call on object
  'VARREF 'write_rsp_i'' which is a 'REFDTYPE 'write_rsp_t''
%Error-UNSUPPORTED: idma_obi_write.sv:113:24: Unsupported: Member call on object
  'VARREF 'write_req_o'' which is a 'REFDTYPE 'write_req_t''
%Error:             idma_obi_write.sv:142:30: Member selection of non-struct/union
  object 'METHODCALL 'a'' which is a 'VOIDDTYPE'

Scope

51 errors total (hits --error-limit=50), confined to the four INIT/OBI
transport modules. The plain AXI module (idma_axi_write.sv) is not affected:

Module	REFDTYPE error lines
src/backend/idma_init_read.sv	84, 85, 86
src/backend/idma_init_write.sv	107, 113, 121–124, 133, 135, 161, 165
src/backend/idma_obi_read.sv	84–86, 110, 120, 124, 128–130, 133, 138
src/backend/idma_obi_write.sv	107, 113, 142–144, 148, 149, 164, 168

Reproduction

Verilator-lint any backend variant that instantiates the INIT or OBI protocol
modules (e.g. r_obi_rw_init_w_axi or r_axi_rw_init_rw_obi from idma.mk)
with Verilator ≥ 5.046:

verilator --lint-only --timing <flist-for-an-init/obi-backend> --top-module <tb>

(Originally surfaced while building a snitch_cluster whose inst64 DMA core
selects the rw_axi_rw_init_rw_obi backend.)

Notes

• The same RTL elaborates cleanly in QuestaSim 2023.4 — the type parameters do
  resolve to concrete OBI/INIT structs there.
• A reduced standalone reproducer (a leaf module doing o.a.addr on a
  parameter type port, even forwarded through several generic module levels
  and generate blocks) does not trip Verilator — it only fails through
  iDMA's full transport-layer type construction.
• The plain AXI write/read modules are unaffected, so a fix likely only needs to
  touch how the INIT/OBI channel types are forwarded/accessed (or wait on
  Verilator REFDTYPE support).

Happy to file the corresponding upstream Verilator report if you'd prefer this
tracked there instead.