diff --git a/target/xilinx/constraints/vcu128.xdc b/target/xilinx/constraints/vcu128.xdc
index c0857740e..4e70be37d 100644
--- a/target/xilinx/constraints/vcu128.xdc
+++ b/target/xilinx/constraints/vcu128.xdc
@@ -83,4 +83,354 @@ set_property PACKAGE_PIN BJ51 [get_ports sys_clk_n]
 set_property PACKAGE_PIN BM29 [get_ports sys_reset]
 set_property IOSTANDARD LVCMOS12 [get_ports sys_reset]
 
+# MIG interface
+set_property PACKAGE_PIN BF50       [get_ports "c0_ddr4_adr[0]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_adr[0]"]
+
+set_property PACKAGE_PIN BD51       [get_ports "c0_ddr4_adr[1]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_adr[1]"]
+
+set_property PACKAGE_PIN BG48       [get_ports "c0_ddr4_adr[2]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_adr[2]"]
+
+set_property PACKAGE_PIN BE50       [get_ports "c0_ddr4_adr[3]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_adr[3]"]
+
+set_property PACKAGE_PIN BE49       [get_ports "c0_ddr4_adr[4]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_adr[4]"]
+
+set_property PACKAGE_PIN BE51       [get_ports "c0_ddr4_adr[5]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_adr[5]"]
+
+set_property PACKAGE_PIN BF53       [get_ports "c0_ddr4_adr[6]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_adr[6]"]
+
+set_property PACKAGE_PIN BG50       [get_ports "c0_ddr4_adr[7]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_adr[7]"]
+
+set_property PACKAGE_PIN BF51       [get_ports "c0_ddr4_adr[8]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_adr[8]"]
+
+set_property PACKAGE_PIN BG47       [get_ports "c0_ddr4_adr[9]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_adr[9]"]
+
+set_property PACKAGE_PIN BF47       [get_ports "c0_ddr4_adr[10]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_adr[10]"]
+
+set_property PACKAGE_PIN BG49       [get_ports "c0_ddr4_adr[11]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_adr[11]"]
+
+set_property PACKAGE_PIN BF48       [get_ports "c0_ddr4_adr[12]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_adr[12]"]
+
+set_property PACKAGE_PIN BF52       [get_ports "c0_ddr4_adr[13]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_adr[13]"]
+
+set_property PACKAGE_PIN BG53       [get_ports "c0_ddr4_adr[14]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_adr[14]"]
+
+set_property PACKAGE_PIN BH54       [get_ports "c0_ddr4_adr[15]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_adr[15]"]
+
+set_property PACKAGE_PIN BJ54       [get_ports "c0_ddr4_adr[16]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_adr[16]"]
+
+set_property PACKAGE_PIN BE54       [get_ports "c0_ddr4_ba[0]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_ba[0]"]
+
+set_property PACKAGE_PIN BE53       [get_ports "c0_ddr4_ba[1]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_ba[1]"]
+
+set_property PACKAGE_PIN BG54       [get_ports "c0_ddr4_bg[0]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_bg[0]"]
+
+set_property PACKAGE_PIN BK54            [get_ports "c0_ddr4_ck_c[0]"]
+set_property IOSTANDARD  DIFF_SSTL12_DCI [get_ports "c0_ddr4_ck_c[0]"]
+
+set_property PACKAGE_PIN BK53            [get_ports "c0_ddr4_ck_t[0]"]
+set_property IOSTANDARD  DIFF_SSTL12_DCI [get_ports "c0_ddr4_ck_t[0]"]
+
+set_property PACKAGE_PIN BH52       [get_ports "c0_ddr4_cke[0]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_cke[0]"]
+
+set_property PACKAGE_PIN BG52       [get_ports "c0_ddr4_act_n"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_act_n"]
+
+set_property PACKAGE_PIN BH50       [get_ports "c0_ddr4_reset_n"]
+set_property IOSTANDARD  LVCMOS12   [get_ports "c0_ddr4_reset_n"]
+
+set_property PACKAGE_PIN BH49       [get_ports "c0_ddr4_odt[0]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_odt[0]"]
+
+set_property PACKAGE_PIN BK48       [get_ports "c0_ddr4_cs_n[1]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_cs_n[1]"]
+
+set_property PACKAGE_PIN BP49       [get_ports "c0_ddr4_cs_n[0]"]
+set_property IOSTANDARD  SSTL12_DCI [get_ports "c0_ddr4_cs_n[0]"]
+
+set_property PACKAGE_PIN BM45      [get_ports "c0_ddr4_dq[0]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[0]"]
+
+set_property PACKAGE_PIN BP44      [get_ports "c0_ddr4_dq[1]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[1]"]
+
+set_property PACKAGE_PIN BP47      [get_ports "c0_ddr4_dq[2]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[2]"]
+
+set_property PACKAGE_PIN BN45      [get_ports "c0_ddr4_dq[3]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[3]"]
+
+set_property PACKAGE_PIN BM44      [get_ports "c0_ddr4_dq[4]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[4]"]
+
+set_property PACKAGE_PIN BN44      [get_ports "c0_ddr4_dq[5]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[5]"]
+
+set_property PACKAGE_PIN BN47      [get_ports "c0_ddr4_dq[6]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[6]"]
+
+set_property PACKAGE_PIN BP43      [get_ports "c0_ddr4_dq[7]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[7]"]
+
+set_property PACKAGE_PIN BL45      [get_ports "c0_ddr4_dq[8]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[8]"]
+
+set_property PACKAGE_PIN BK44      [get_ports "c0_ddr4_dq[9]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[9]"]
+
+set_property PACKAGE_PIN BL46      [get_ports "c0_ddr4_dq[10]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[10]"]
+
+set_property PACKAGE_PIN BK43      [get_ports "c0_ddr4_dq[11]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[11]"]
+
+set_property PACKAGE_PIN BL43      [get_ports "c0_ddr4_dq[12]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[12]"]
+
+set_property PACKAGE_PIN BJ44      [get_ports "c0_ddr4_dq[13]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[13]"]
+
+set_property PACKAGE_PIN BL42      [get_ports "c0_ddr4_dq[14]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[14]"]
+
+set_property PACKAGE_PIN BJ43      [get_ports "c0_ddr4_dq[15]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[15]"]
+
+set_property PACKAGE_PIN BK41      [get_ports "c0_ddr4_dq[16]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[16]"]
+
+set_property PACKAGE_PIN BG44      [get_ports "c0_ddr4_dq[17]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[17]"]
+
+set_property PACKAGE_PIN BG42      [get_ports "c0_ddr4_dq[18]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[18]"]
+
+set_property PACKAGE_PIN BH44      [get_ports "c0_ddr4_dq[19]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[19]"]
+
+set_property PACKAGE_PIN BH45      [get_ports "c0_ddr4_dq[20]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[20]"]
+
+set_property PACKAGE_PIN BG45      [get_ports "c0_ddr4_dq[21]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[21]"]
+
+set_property PACKAGE_PIN BG43      [get_ports "c0_ddr4_dq[22]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[22]"]
+
+set_property PACKAGE_PIN BJ41      [get_ports "c0_ddr4_dq[23]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[23]"]
+
+set_property PACKAGE_PIN BE43      [get_ports "c0_ddr4_dq[24]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[24]"]
+
+set_property PACKAGE_PIN BF42      [get_ports "c0_ddr4_dq[25]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[25]"]
+
+set_property PACKAGE_PIN BC42      [get_ports "c0_ddr4_dq[26]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[26]"]
+
+set_property PACKAGE_PIN BF43      [get_ports "c0_ddr4_dq[27]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[27]"]
+
+set_property PACKAGE_PIN BD42      [get_ports "c0_ddr4_dq[28]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[28]"]
+
+set_property PACKAGE_PIN BF45      [get_ports "c0_ddr4_dq[29]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[29]"]
+
+set_property PACKAGE_PIN BE44      [get_ports "c0_ddr4_dq[30]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[30]"]
+
+set_property PACKAGE_PIN BF46      [get_ports "c0_ddr4_dq[31]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[31]"]
+
+set_property PACKAGE_PIN BP32      [get_ports "c0_ddr4_dq[32]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[32]"]
+
+set_property PACKAGE_PIN BP29      [get_ports "c0_ddr4_dq[33]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[33]"]
+
+set_property PACKAGE_PIN BP31      [get_ports "c0_ddr4_dq[34]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[34]"]
+
+set_property PACKAGE_PIN BP28      [get_ports "c0_ddr4_dq[35]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[35]"]
+
+set_property PACKAGE_PIN BN32      [get_ports "c0_ddr4_dq[36]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[36]"]
+
+set_property PACKAGE_PIN BM30      [get_ports "c0_ddr4_dq[37]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[37]"]
+
+set_property PACKAGE_PIN BN31      [get_ports "c0_ddr4_dq[38]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[38]"]
+
+set_property PACKAGE_PIN BL30      [get_ports "c0_ddr4_dq[39]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[39]"]
+
+set_property PACKAGE_PIN BL32      [get_ports "c0_ddr4_dq[40]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[40]"]
+
+set_property PACKAGE_PIN BP34      [get_ports "c0_ddr4_dq[41]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[41]"]
+
+set_property PACKAGE_PIN BN34      [get_ports "c0_ddr4_dq[42]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[42]"]
+
+set_property PACKAGE_PIN BK33      [get_ports "c0_ddr4_dq[43]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[43]"]
+
+set_property PACKAGE_PIN BL31      [get_ports "c0_ddr4_dq[44]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[44]"]
+
+set_property PACKAGE_PIN BL33      [get_ports "c0_ddr4_dq[45]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[45]"]
+
+set_property PACKAGE_PIN BM33      [get_ports "c0_ddr4_dq[46]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[46]"]
+
+set_property PACKAGE_PIN BK31      [get_ports "c0_ddr4_dq[47]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[47]"]
+
+set_property PACKAGE_PIN BJ34      [get_ports "c0_ddr4_dq[48]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[48]"]
+
+set_property PACKAGE_PIN BG35      [get_ports "c0_ddr4_dq[49]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[49]"]
+
+set_property PACKAGE_PIN BH34      [get_ports "c0_ddr4_dq[50]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[50]"]
+
+set_property PACKAGE_PIN BH35      [get_ports "c0_ddr4_dq[51]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[51]"]
+
+set_property PACKAGE_PIN BJ33      [get_ports "c0_ddr4_dq[52]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[52]"]
+
+set_property PACKAGE_PIN BF35      [get_ports "c0_ddr4_dq[53]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[53]"]
+
+set_property PACKAGE_PIN BG34      [get_ports "c0_ddr4_dq[54]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[54]"]
+
+set_property PACKAGE_PIN BF36      [get_ports "c0_ddr4_dq[55]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[55]"]
+
+set_property PACKAGE_PIN BF31      [get_ports "c0_ddr4_dq[56]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[56]"]
+
+set_property PACKAGE_PIN BH30      [get_ports "c0_ddr4_dq[57]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[57]"]
+
+set_property PACKAGE_PIN BJ31      [get_ports "c0_ddr4_dq[58]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[58]"]
+
+set_property PACKAGE_PIN BG32      [get_ports "c0_ddr4_dq[59]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[59]"]
+
+set_property PACKAGE_PIN BH31      [get_ports "c0_ddr4_dq[60]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[60]"]
+
+set_property PACKAGE_PIN BF32      [get_ports "c0_ddr4_dq[61]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[61]"]
+
+set_property PACKAGE_PIN BH29      [get_ports "c0_ddr4_dq[62]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[62]"]
+
+set_property PACKAGE_PIN BF33      [get_ports "c0_ddr4_dq[63]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dq[63]"]
+
+set_property PACKAGE_PIN BK30           [get_ports "c0_ddr4_dqs_c[7]"]
+set_property IOSTANDARD  DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[7]"]
+
+set_property PACKAGE_PIN BK35           [get_ports "c0_ddr4_dqs_c[6]"]
+set_property IOSTANDARD  DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[6]"]
+
+set_property PACKAGE_PIN BM35           [get_ports "c0_ddr4_dqs_c[5]"]
+set_property IOSTANDARD  DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[5]"]
+
+set_property PACKAGE_PIN BN30           [get_ports "c0_ddr4_dqs_c[4]"]
+set_property IOSTANDARD  DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[4]"]
+
+set_property PACKAGE_PIN BE46           [get_ports "c0_ddr4_dqs_c[3]"]
+set_property IOSTANDARD  DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[3]"]
+
+set_property PACKAGE_PIN BJ46           [get_ports "c0_ddr4_dqs_c[2]"]
+set_property IOSTANDARD  DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[2]"]
+
+set_property PACKAGE_PIN BK46           [get_ports "c0_ddr4_dqs_c[1]"]
+set_property IOSTANDARD  DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[1]"]
+
+set_property PACKAGE_PIN BP46           [get_ports "c0_ddr4_dqs_c[0]"]
+set_property IOSTANDARD  DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[0]"]
+
+set_property PACKAGE_PIN BJ29           [get_ports "c0_ddr4_dqs_t[7]"]
+set_property IOSTANDARD  DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[7]"]
+
+set_property PACKAGE_PIN BK34           [get_ports "c0_ddr4_dqs_t[6]"]
+set_property IOSTANDARD  DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[6]"]
+
+set_property PACKAGE_PIN BL35           [get_ports "c0_ddr4_dqs_t[5]"]
+set_property IOSTANDARD  DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[5]"]
+
+set_property PACKAGE_PIN BN29           [get_ports "c0_ddr4_dqs_t[4]"]
+set_property IOSTANDARD  DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[4]"]
+
+set_property PACKAGE_PIN BE45           [get_ports "c0_ddr4_dqs_t[3]"]
+set_property IOSTANDARD  DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[3]"]
+
+set_property PACKAGE_PIN BH46           [get_ports "c0_ddr4_dqs_t[2]"]
+set_property IOSTANDARD  DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[2]"]
+
+set_property PACKAGE_PIN BK45           [get_ports "c0_ddr4_dqs_t[1]"]
+set_property IOSTANDARD  DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[1]"]
+
+set_property PACKAGE_PIN BN46           [get_ports "c0_ddr4_dqs_t[0]"]
+set_property IOSTANDARD  DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[0]"]
+
+set_property PACKAGE_PIN BG29      [get_ports "c0_ddr4_dm_dbi_n[7]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[7]"]
+
+set_property PACKAGE_PIN BH32      [get_ports "c0_ddr4_dm_dbi_n[6]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[6]"]
+
+set_property PACKAGE_PIN BM34      [get_ports "c0_ddr4_dm_dbi_n[5]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[5]"]
+
+set_property PACKAGE_PIN BM28      [get_ports "c0_ddr4_dm_dbi_n[4]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[4]"]
+
+set_property PACKAGE_PIN BD41      [get_ports "c0_ddr4_dm_dbi_n[3]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[3]"]
+
+set_property PACKAGE_PIN BH42      [get_ports "c0_ddr4_dm_dbi_n[2]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[2]"]
+
+set_property PACKAGE_PIN BL47      [get_ports "c0_ddr4_dm_dbi_n[1]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[1]"]
+
+set_property PACKAGE_PIN BN42      [get_ports "c0_ddr4_dm_dbi_n[0]"]
+set_property IOSTANDARD  POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[0]"]
+
+
 # tclint-enable line-length, spacing
diff --git a/target/xilinx/scripts/impl_ip.tcl b/target/xilinx/scripts/impl_ip.tcl
index 43343e636..b5ab1492a 100644
--- a/target/xilinx/scripts/impl_ip.tcl
+++ b/target/xilinx/scripts/impl_ip.tcl
@@ -183,15 +183,15 @@ switch $proj {
             vcu128 {
                 set_property -dict [list \
                     CONFIG.C0.DDR4_Clamshell {true} \
-                    CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram} \
+                    CONFIG.C0_DDR4_BOARD_INTERFACE {Custom} \
                     CONFIG.System_Clock {No_Buffer} \
                     CONFIG.Reference_Clock {No_Buffer} \
                     CONFIG.C0.DDR4_InputClockPeriod {10000} \
                     CONFIG.C0.DDR4_CLKOUT0_DIVIDE {3} \
                     CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} \
-                    CONFIG.C0.DDR4_DataWidth {72} \
-                    CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \
-                    CONFIG.C0.DDR4_Ecc {true} \
+                    CONFIG.C0.DDR4_DataWidth {64} \
+                    CONFIG.C0.DDR4_DataMask {DM_NO_DBI} \
+                    CONFIG.C0.DDR4_Ecc {false} \
                     CONFIG.C0.DDR4_AxiDataWidth {512} \
                     CONFIG.C0.DDR4_AxiAddressWidth {32} \
                     CONFIG.C0.DDR4_AxiIDWidth {8} \
diff --git a/target/xilinx/scripts/impl_sys.tcl b/target/xilinx/scripts/impl_sys.tcl
index 5dc521dad..ca1c04b11 100644
--- a/target/xilinx/scripts/impl_sys.tcl
+++ b/target/xilinx/scripts/impl_sys.tcl
@@ -22,6 +22,9 @@ import_files -fileset constrs_1 -norecurse ${xilinx_root}/constraints/${board}.x
 # Load RTL sources
 source ${xilinx_root}/scripts/add_sources.${board}.tcl
 
+# Avoid changing top level randomly in case of error
+set_property source_mgmt_mode None [current_project]
+
 # Set top module
 set_property top ${proj}_top_xilinx [current_fileset]
 update_compile_order -fileset sources_1
diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv
index 5215b960e..19b47edaf 100644
--- a/target/xilinx/src/cheshire_top_xilinx.sv
+++ b/target/xilinx/src/cheshire_top_xilinx.sv
@@ -17,9 +17,9 @@
 module cheshire_top_xilinx import cheshire_pkg::*; #(
 `ifdef TARGET_VCU128
   localparam int unsigned Ddr4CsNWidth = 2,
-  localparam int unsigned Ddr4DmDbiNWidth = 9,
-  localparam int unsigned Ddr4DqWidth = 72,
-  localparam int unsigned Ddr4DqsWidth = 9
+  localparam int unsigned Ddr4DmDbiNWidth = 8,
+  localparam int unsigned Ddr4DqWidth = 64,
+  localparam int unsigned Ddr4DqsWidth = 8
 `else // Default to VCU118
   localparam int unsigned Ddr4CsNWidth = 1,
   localparam int unsigned Ddr4DmDbiNWidth = 8,
diff --git a/target/xilinx/src/dram_wrapper_xilinx.sv b/target/xilinx/src/dram_wrapper_xilinx.sv
index 5fe0f28a1..1329c2f36 100644
--- a/target/xilinx/src/dram_wrapper_xilinx.sv
+++ b/target/xilinx/src/dram_wrapper_xilinx.sv
@@ -287,27 +287,6 @@ module dram_wrapper_xilinx #(
     .c0_ddr4_s_axi_rresp        ( cdc_dram_rsp.r.resp   ),
     .c0_ddr4_s_axi_rlast        ( cdc_dram_rsp.r.last   ),
     .c0_ddr4_s_axi_rvalid       ( cdc_dram_rsp.r_valid  ),
-    `ifdef TARGET_VCU128
-      // TODO: Shouldn't we map this to an external reg port?
-      // AXI control
-      .c0_ddr4_s_axi_ctrl_awvalid ( '0 ),
-      .c0_ddr4_s_axi_ctrl_awready ( ),
-      .c0_ddr4_s_axi_ctrl_awaddr  ( '0 ),
-      .c0_ddr4_s_axi_ctrl_wvalid  ( '0 ),
-      .c0_ddr4_s_axi_ctrl_wready  ( ),
-      .c0_ddr4_s_axi_ctrl_wdata   ( '0 ),
-      .c0_ddr4_s_axi_ctrl_bvalid  ( ),
-      .c0_ddr4_s_axi_ctrl_bready  ( '0 ),
-      .c0_ddr4_s_axi_ctrl_bresp   ( ),
-      .c0_ddr4_s_axi_ctrl_arvalid ( '0 ),
-      .c0_ddr4_s_axi_ctrl_arready ( ),
-      .c0_ddr4_s_axi_ctrl_araddr  ( '0 ),
-      .c0_ddr4_s_axi_ctrl_rvalid  ( ),
-      .c0_ddr4_s_axi_ctrl_rready  ( '0 ),
-      .c0_ddr4_s_axi_ctrl_rdata   ( ),
-      .c0_ddr4_s_axi_ctrl_rresp   ( ),
-      .c0_ddr4_interrupt          ( ),
-    `endif
     // Others
     .c0_init_calib_complete     ( ),
     .addn_ui_clkout1            ( dram_clk_o ),