Skip to content

Commit ff0bbbb

Browse files
V-FEXrtV-FEXrt
authored
[SM6.10] LinAlg: Remove bias interp per spec (#8702)
Fixes #8697 Removes the bias interp parameter from VecMulAdd per microsoft/hlsl-specs#901
1 parent 31576b8 commit ff0bbbb

22 files changed

Lines changed: 90 additions & 107 deletions

File tree

‎include/dxc/DXIL/DxilInstructions.h‎

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10781,7 +10781,7 @@ struct DxilInst_LinAlgMatVecMulAdd {
1078110781
// Validation support
1078210782
bool isAllowed() const { return true; }
1078310783
bool isArgumentListValid() const {
10784-
if (7 != llvm::dyn_cast<llvm::CallInst>(Instr)->getNumArgOperands())
10784+
if (6 != llvm::dyn_cast<llvm::CallInst>(Instr)->getNumArgOperands())
1078510785
return false;
1078610786
return true;
1078710787
}
@@ -10794,7 +10794,6 @@ struct DxilInst_LinAlgMatVecMulAdd {
1079410794
arg_inputVector = 3,
1079510795
arg_inputInterpretation = 4,
1079610796
arg_biasVector = 5,
10797-
arg_biasInterpretation = 6,
1079810797
};
1079910798
// Accessors
1080010799
llvm::Value *get_matrix() const { return Instr->getOperand(1); }
@@ -10807,8 +10806,6 @@ struct DxilInst_LinAlgMatVecMulAdd {
1080710806
void set_inputInterpretation(llvm::Value *val) { Instr->setOperand(4, val); }
1080810807
llvm::Value *get_biasVector() const { return Instr->getOperand(5); }
1080910808
void set_biasVector(llvm::Value *val) { Instr->setOperand(5, val); }
10810-
llvm::Value *get_biasInterpretation() const { return Instr->getOperand(6); }
10811-
void set_biasInterpretation(llvm::Value *val) { Instr->setOperand(6, val); }
1081210809
};
1081310810

1081410811
/// This instruction accumulates a matrix to a RWByteAddressBuffer

‎lib/DXIL/DxilOperations.cpp‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6649,7 +6649,6 @@ Function *OP::GetOpFunc(OpCode opCode, Type *pOverloadType) {
66496649
A(EXT(2));
66506650
A(pI32);
66516651
A(EXT(3));
6652-
A(pI32);
66536652
break;
66546653
case OpCode::LinAlgMatrixAccumulateToDescriptor:
66556654
A(pV);

‎lib/HLSL/HLOperationLower.cpp‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -6852,16 +6852,15 @@ Value *TranslateLinAlgMatVecMulAdd(CallInst *CI, IntrinsicOp IOP,
68526852
Value *InputVector = CI->getArgOperand(4);
68536853
Value *InputVectorInterp = CI->getArgOperand(5);
68546854
Value *BiasVector = CI->getArgOperand(6);
6855-
Value *BiasVectorInterp = CI->getArgOperand(7);
68566855

68576856
Constant *OpArg = HlslOp->GetU32Const((unsigned)OpCode);
68586857
Function *DxilFunc = HlslOp->GetOpFunc(
68596858
OpCode, {ReturnVecType, Matrix->getType(), InputVector->getType(),
68606859
BiasVector->getType()});
68616860

6862-
Value *ReturnVec = Builder.CreateCall(
6863-
DxilFunc, {OpArg, Matrix, IsOutputSigned, InputVector, InputVectorInterp,
6864-
BiasVector, BiasVectorInterp});
6861+
Value *ReturnVec =
6862+
Builder.CreateCall(DxilFunc, {OpArg, Matrix, IsOutputSigned, InputVector,
6863+
InputVectorInterp, BiasVector});
68656864
Builder.CreateStore(ReturnVec, ReturnVecPtr);
68666865

68676866
return nullptr;

‎tools/clang/lib/Headers/hlsl/dx/linalg.h‎

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -505,8 +505,7 @@ MultiplyAdd(Matrix<MatrixDT, M, K, MatrixUse::A, MatrixScope::Thread> MatrixA,
505505
vector<OutputElTy, M> Result;
506506
__builtin_LinAlg_MatrixVectorMultiplyAdd(
507507
Result, MatrixA.__handle, hlsl::is_signed<OutputElTy>::value, Vec,
508-
__detail::TypeTraits<InputElTy>::CompType, BiasConvInterp.Data,
509-
BiasConvInterp.Interpretation);
508+
__detail::TypeTraits<InputElTy>::CompType, BiasConvInterp.Data);
510509
return Result;
511510
}
512511

@@ -527,8 +526,7 @@ MultiplyAdd(Matrix<MatrixDT, M, K, MatrixUse::A, MatrixScope::Thread> MatrixA,
527526
vector<OutputElTy, M> Result;
528527
__builtin_LinAlg_MatrixVectorMultiplyAdd(
529528
Result, MatrixA.__handle, hlsl::is_signed<OutputElTy>::value,
530-
InterpVec.Data, InterpVec.Interpretation, BiasConvInterp.Data,
531-
BiasConvInterp.Interpretation);
529+
InterpVec.Data, InterpVec.Interpretation, BiasConvInterp.Data);
532530
return Result;
533531
}
534532

@@ -570,8 +568,7 @@ MultiplyAdd(Matrix<MatrixDT, M, K, MatrixUse::A, MatrixScope::Thread> MatrixA,
570568
vector<OutputElTy, M> Result;
571569
__builtin_LinAlg_MatrixVectorMultiplyAdd(
572570
Result, MatrixA.__handle, hlsl::is_signed<OutputElTy>::value, Vec,
573-
__detail::TypeTraits<InputElTy>::CompType, BiasConv,
574-
__detail::TypeTraits<OutputElTy>::CompType);
571+
__detail::TypeTraits<InputElTy>::CompType, BiasConv);
575572
return Result;
576573
}
577574

@@ -615,8 +612,7 @@ MultiplyAdd(Matrix<MatrixDT, M, K, MatrixUse::A, MatrixScope::Thread> MatrixA,
615612
vector<OutputElTy, M> Result;
616613
__builtin_LinAlg_MatrixVectorMultiplyAdd(
617614
Result, MatrixA.__handle, hlsl::is_signed<OutputElTy>::value,
618-
InterpVec.Data, InterpVec.Interpretation, BiasConv,
619-
__detail::TypeTraits<OutputElTy>::CompType);
615+
InterpVec.Data, InterpVec.Interpretation, BiasConv);
620616
return Result;
621617
}
622618

‎tools/clang/test/CodeGenDXIL/hlsl/linalg/api/vectors.hlsl‎

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -39,13 +39,13 @@ void main(uint ID : SV_GroupID) {
3939

4040
// CHECK: %[[VEC3:.*]] = call <8 x half> @dx.op.linAlgMatVecMulAdd.v8f16.mC8M8N4U0S0.v4f16.v8f16(i32 -2147483622,
4141
// CHECK-SAME: %dx.types.LinAlgMatrixC8M8N4U0S0 %[[MAT1]], i1 true, <4 x half> <half 0xH4926, half 0xH4926, half 0xH4926,
42-
// CHECK-SAME: half 0xH4926>, i32 8, <8 x half> %[[VEC29]], i32 8)
43-
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector,biasInterpretation)
42+
// CHECK-SAME: half 0xH4926>, i32 8, <8 x half> %[[VEC29]])
43+
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector)
4444
vector<half, 8> vec3 = MultiplyAdd<half>(Mat1, vec1, vec29);
4545

4646
// CHECK: %[[VEC4:.*]] = call <8 x half> @dx.op.linAlgMatVecMulAdd.v8f16.mC8M8N4U0S0.v4f16.v8f16(i32 -2147483622,
47-
// CHECK-SAME: %dx.types.LinAlgMatrixC8M8N4U0S0 %[[MAT1]], i1 true, <4 x half> %[[VEC20]], i32 8, <8 x half> %[[VEC3]], i32 8)
48-
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector,biasInterpretation)
47+
// CHECK-SAME: %dx.types.LinAlgMatrixC8M8N4U0S0 %[[MAT1]], i1 true, <4 x half> %[[VEC20]], i32 8, <8 x half> %[[VEC3]])
48+
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector)
4949
InterpretedVector<half, 4, ComponentType::F16> interpVec2 = MakeInterpretedVector<ComponentType::F16>(vec20);
5050
vector<half, 8> vec4 = MultiplyAdd<half>(Mat1, interpVec2, vec3);
5151

@@ -57,8 +57,8 @@ void main(uint ID : SV_GroupID) {
5757
// CHECK: %[[BIAS_CONV:.*]] = call <8 x half> @dx.op.linAlgConvert.v8f16.v8i16(i32 -2147483618, <8 x i16> %[[VEC_BIAS]], i32 2, i32 8)
5858
// CHECK-SAME: ; LinAlgConvert(inputVector,inputInterpretation,outputInterpretation)
5959
// CHECK: %[[VEC5:.*]] = call <8 x half> @dx.op.linAlgMatVecMulAdd.v8f16.mC8M8N4U0S0.v4f16.v8f16(i32 -2147483622,
60-
// CHECK-SAME: %dx.types.LinAlgMatrixC8M8N4U0S0 %[[MAT1]], i1 true, <4 x half> %[[VEC20]], i32 8, <8 x half> %[[BIAS_CONV]], i32 8)
61-
// CHECK-SAME:; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector,biasInterpretation)
60+
// CHECK-SAME: %dx.types.LinAlgMatrixC8M8N4U0S0 %[[MAT1]], i1 true, <4 x half> %[[VEC20]], i32 8, <8 x half> %[[BIAS_CONV]])
61+
// CHECK-SAME:; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector)
6262
VectorRef<ComponentType::I16, 8> memBias = {BAB, 4096};
6363
vector<half, 8> vec5 = MultiplyAdd<half>(Mat1, interpVec2, memBias);
6464

@@ -71,8 +71,8 @@ void main(uint ID : SV_GroupID) {
7171
// CHECK: %[[BIAS_CONV:.*]] = call <8 x half> @dx.op.linAlgConvert.v8f16.v8i16(i32 -2147483618, <8 x i16> %[[VEC_BIAS]], i32 2, i32 8)
7272
// CHECK-SAME: ; LinAlgConvert(inputVector,inputInterpretation,outputInterpretation)
7373
// CHECK: %[[VEC6:.*]] = call <8 x half> @dx.op.linAlgMatVecMulAdd.v8f16.mC8M8N4U0S0.v4f16.v8f16(i32 -2147483622,
74-
// CHECK-SAME: %dx.types.LinAlgMatrixC8M8N4U0S0 %[[MAT1]], i1 true, <4 x half> %[[VEC20]], i32 8, <8 x half> %[[BIAS_CONV]], i32 8)
75-
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector,biasInterpretation)
74+
// CHECK-SAME: %dx.types.LinAlgMatrixC8M8N4U0S0 %[[MAT1]], i1 true, <4 x half> %[[VEC20]], i32 8, <8 x half> %[[BIAS_CONV]])
75+
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector)
7676
vector<half, 8> vec6 = MultiplyAdd<half>(Mat1, interpVec2, memBias);
7777

7878
// CHECK: %[[ACCUM1:.*]] = call %dx.types.LinAlgMatrixC8M8N8U2S0
@@ -112,29 +112,29 @@ void main(uint ID : SV_GroupID) {
112112
Matrix_7_15_ATy Mat_7_15 = Matrix_7_15_ATy::Load<MatrixLayoutEnum::ColMajor>(BAB, 0, 16);
113113

114114
// CHECK: call <7 x half> @dx.op.linAlgMatVecMulAdd.v7f16.mC8M7N15U0S0.v15f16.v7f16(i32 -2147483622,
115-
// CHECK-SAME: %dx.types.LinAlgMatrixC8M7N15U0S0 %[[MAT_7_15]], i1 true, <15 x half> %{{[0-9]+}}, i32 8, <7 x half> %{{[0-9]+}}, i32 8)
116-
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector,biasInterpretation)
115+
// CHECK-SAME: %dx.types.LinAlgMatrixC8M7N15U0S0 %[[MAT_7_15]], i1 true, <15 x half> %{{[0-9]+}}, i32 8, <7 x half> %{{[0-9]+}})
116+
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector)
117117
vector<half, 7> vec7 = MultiplyAdd<half>(Mat_7_15, vecH15, vecH7);
118118

119119
// CHECK: call <7 x half> @dx.op.linAlgMatVecMulAdd.v7f16.mC8M7N15U0S0.v15f16.v7f16(i32 -2147483622, %dx.types.LinAlgMatrixC8M7N15U0S0 %[[MAT_7_15]],
120-
// CHECK-SAME; i1 true, <15 x half> %{{[0-9]+}}, i32 8, <7 x half> %{{[0-9]+}}, i32 8)
121-
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector,biasInterpretation)
120+
// CHECK-SAME; i1 true, <15 x half> %{{[0-9]+}}, i32 8, <7 x half> %{{[0-9]+}})
121+
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector)
122122
vector<half, 7> vec8 = MultiplyAdd<half>(Mat_7_15, interpVecH15, vecH7);
123123

124124
// CHECK: %[[LOAD1:.*]] = call %dx.types.ResRet.v7f16 @dx.op.rawBufferVectorLoad.v7f16(i32 303, %dx.types.Handle %{{[0-9]+}}, i32 512, i32 undef, i32 2)
125125
// CHECK-SAME: ; RawBufferVectorLoad(buf,index,elementOffset,alignment)
126126
// CHECK-NEXT: %[[MEM_BIAS1:.*]] = extractvalue %dx.types.ResRet.v7f16 %[[LOAD1]], 0
127127
// CHECK-NEXT: call <7 x half> @dx.op.linAlgMatVecMulAdd.v7f16.mC8M7N15U0S0.v15f16.v7f16(i32 -2147483622,
128-
// CHECK-SAME: %dx.types.LinAlgMatrixC8M7N15U0S0 %[[MAT_7_15]], i1 true, <15 x half> %{{[0-9]+}}, i32 8, <7 x half> %{{[0-9]+}}, i32 8)
129-
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector,biasInterpretation)
128+
// CHECK-SAME: %dx.types.LinAlgMatrixC8M7N15U0S0 %[[MAT_7_15]], i1 true, <15 x half> %{{[0-9]+}}, i32 8, <7 x half> %{{[0-9]+}})
129+
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector)
130130
VectorRef<ComponentType::F16, 7> memBias7 = {BAB, 512};
131131
vector<half, 7> vec9 = MultiplyAdd<half>(Mat_7_15, vecH15, memBias7);
132132

133133
// CHECK: %[[LOAD2:.*]] = call %dx.types.ResRet.v7f16 @dx.op.rawBufferVectorLoad.v7f16(i32 303, %dx.types.Handle %{{[0-9]+}}, i32 512, i32 undef, i32 2)
134134
// CHECK-SAME: ; RawBufferVectorLoad(buf,index,elementOffset,alignment)
135135
// CHECK-NEXT: %[[MEM_BIAS2:.*]] = extractvalue %dx.types.ResRet.v7f16 %[[LOAD2]], 0
136-
// CHECK-NEXT: %dx.types.LinAlgMatrixC8M7N15U0S0 %[[MAT_7_15]], i1 true, <15 x half> %{{[0-9]+}}, i32 8, <7 x half> %[[MEM_BIAS2]], i32 8)
137-
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector,biasInterpretation)
136+
// CHECK-NEXT: %dx.types.LinAlgMatrixC8M7N15U0S0 %[[MAT_7_15]], i1 true, <15 x half> %{{[0-9]+}}, i32 8, <7 x half> %[[MEM_BIAS2]])
137+
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector)
138138
vector<half, 7> vec10 = MultiplyAdd<half>(Mat_7_15, interpVecH15, memBias7);
139139

140140
// Test MultiplyAdd with packed input vector
@@ -144,16 +144,16 @@ void main(uint ID : SV_GroupID) {
144144
InterpretedVector<uint, 4, ComponentEnum::F8_E4M3FN> interpVecH15Packed = Convert<ComponentEnum::F8_E4M3FN, ComponentEnum::F16>(vecH15);
145145

146146
// CHECK: call <7 x half> @dx.op.linAlgMatVecMulAdd.v7f16.mC8M7N15U0S0.v4i32.v7f16(i32 -2147483622,
147-
// CHECK-SAME: %dx.types.LinAlgMatrixC8M7N15U0S0 %[[MAT_7_15]], i1 true, <4 x i32> %{{[0-9]+}}, i32 21, <7 x half> %{{[0-9]+}}, i32 8)
148-
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector,biasInterpretation)
147+
// CHECK-SAME: %dx.types.LinAlgMatrixC8M7N15U0S0 %[[MAT_7_15]], i1 true, <4 x i32> %{{[0-9]+}}, i32 21, <7 x half> %{{[0-9]+}})
148+
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector)
149149
vector<half, 7> vec11 = MultiplyAdd<half>(Mat_7_15, interpVecH15Packed, vecH7);
150150

151151
// CHECK: %[[LOAD3:.+]] = call %dx.types.ResRet.v7f16 @dx.op.rawBufferVectorLoad.v7f16(i32 303, %dx.types.Handle %{{[0-9]+}}, i32 512, i32 undef, i32 2)
152152
// CHECK-SAME: ; RawBufferVectorLoad(buf,index,elementOffset,alignment)
153153
// CHECK-NEXT: %[[MEM_BIAS3:.*]] = extractvalue %dx.types.ResRet.v7f16 %{{[0-9]+}}, 0
154154
// CHECK-NEXT: call <7 x half> @dx.op.linAlgMatVecMulAdd.v7f16.mC8M7N15U0S0.v4i32.v7f16(i32 -2147483622,
155-
// CHECK-SAME: %dx.types.LinAlgMatrixC8M7N15U0S0 %[[MAT_7_15]], i1 true, <4 x i32> %[[INTERP_VEC_H15_PACKED]], i32 21, <7 x half> %[[MEM_BIAS3]], i32 8)
156-
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector,biasInterpretation)
155+
// CHECK-SAME: %dx.types.LinAlgMatrixC8M7N15U0S0 %[[MAT_7_15]], i1 true, <4 x i32> %[[INTERP_VEC_H15_PACKED]], i32 21, <7 x half> %[[MEM_BIAS3]])
156+
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector)
157157

158158
vector<half, 7> vec12 = MultiplyAdd<half>(Mat_7_15, interpVecH15Packed, memBias7);
159159

@@ -164,13 +164,13 @@ void main(uint ID : SV_GroupID) {
164164
MatrixPacked_7_15_ATy Mat_7_15_Packed = MatrixPacked_7_15_ATy::Load<MatrixLayoutEnum::ColMajor>(BAB, 0, 16);
165165

166166
// CHECK: call <7 x half> @dx.op.linAlgMatVecMulAdd.v7f16.mC21M7N15U0S0.v15f16.v7f16(i32 -2147483622,
167-
// CHECK-SAME: %dx.types.LinAlgMatrixC21M7N15U0S0 %[[MAT_7_15_PACKED]], i1 true, <15 x half> %{{[0-9]+}}, i32 8, <7 x half> %{{[0-9]+}}, i32 8)
168-
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector,biasInterpretation)
167+
// CHECK-SAME: %dx.types.LinAlgMatrixC21M7N15U0S0 %[[MAT_7_15_PACKED]], i1 true, <15 x half> %{{[0-9]+}}, i32 8, <7 x half> %{{[0-9]+}})
168+
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector)
169169
vector<half, 7> vec21 = MultiplyAdd<half>(Mat_7_15_Packed, vecH15, vecH7);
170170

171171
// CHECK: call <7 x half> @dx.op.linAlgMatVecMulAdd.v7f16.mC21M7N15U0S0.v4i32.v7f16(i32 -2147483622, %dx.types.LinAlgMatrixC21M7N15U0S0 %[[MAT_7_15_PACKED]],
172-
// CHECK-SAME: i1 true, <4 x i32> %[[INTERP_VEC_H15_PACKED]], i32 21, <7 x half> %{{[0-9]+}}, i32 8)
173-
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector,biasInterpretation)
172+
// CHECK-SAME: i1 true, <4 x i32> %[[INTERP_VEC_H15_PACKED]], i32 21, <7 x half> %{{[0-9]+}})
173+
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector)
174174
vector<half, 7> vec22 = MultiplyAdd<half>(Mat_7_15_Packed, interpVecH15Packed, vecH7);
175175

176176
// CHECK: %[[LOAD4:.*]] = call %dx.types.ResRet.v2i32 @dx.op.rawBufferVectorLoad.v2i32(i32 303, %dx.types.Handle %{{[0-9]+}}, i32 512, i32 undef, i32 4)
@@ -180,8 +180,8 @@ void main(uint ID : SV_GroupID) {
180180
// CHECK-SAME: <2 x i32> %[[MEM_BIAS_PACKED1]], i32 21, i32 8) ; LinAlgConvert(inputVector,inputInterpretation,outputInterpretation)
181181
// CHECK-NEXT: %[[MEM_BIAS_CONV1:.*]] = shufflevector <8 x half> %[[MEM_BIAS_CONV_PADDED]], <8 x half> undef, <7 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
182182
// CHECK-NEXT: call <7 x half> @dx.op.linAlgMatVecMulAdd.v7f16.mC21M7N15U0S0.v15f16.v7f16(i32 -2147483622,
183-
// CHECK-SAME: %dx.types.LinAlgMatrixC21M7N15U0S0 %[[MAT_7_15_PACKED]], i1 true, <15 x half> %{{[0-9]+}}, i32 8, <7 x half> %[[MEM_BIAS_CONV1]], i32 8)
184-
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector,biasInterpretation)
183+
// CHECK-SAME: %dx.types.LinAlgMatrixC21M7N15U0S0 %[[MAT_7_15_PACKED]], i1 true, <15 x half> %{{[0-9]+}}, i32 8, <7 x half> %[[MEM_BIAS_CONV1]])
184+
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector)
185185
VectorRef<ComponentType::F8_E4M3FN, 7> memBias7Packed = {BAB, 512};
186186
vector<half, 7> vec23 = MultiplyAdd<half>(Mat_7_15_Packed, vecH15, memBias7Packed);
187187

@@ -192,8 +192,8 @@ void main(uint ID : SV_GroupID) {
192192
// CHECK-SAME: <2 x i32> %[[MEM_BIAS_PACKED2]], i32 21, i32 8) ; LinAlgConvert(inputVector,inputInterpretation,outputInterpretation)
193193
// CHECK-NEXT: %[[MEM_BIAS_CONV2:.*]] = shufflevector <8 x half> %[[MEM_BIAS_CONV_PADDED2]], <8 x half> undef, <7 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
194194
// CHECK-NEXT: call <7 x half> @dx.op.linAlgMatVecMulAdd.v7f16.mC21M7N15U0S0.v4i32.v7f16(i32 -2147483622,
195-
// CHECK-SAME: %dx.types.LinAlgMatrixC21M7N15U0S0 %[[MAT_7_15_PACKED]], i1 true, <4 x i32> %[[INTERP_VEC_H15_PACKED]], i32 21, <7 x half> %[[MEM_BIAS_CONV2]], i32 8)
196-
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector,biasInterpretation)
195+
// CHECK-SAME: %dx.types.LinAlgMatrixC21M7N15U0S0 %[[MAT_7_15_PACKED]], i1 true, <4 x i32> %[[INTERP_VEC_H15_PACKED]], i32 21, <7 x half> %[[MEM_BIAS_CONV2]])
196+
// CHECK-SAME: ; LinAlgMatVecMulAdd(matrix,isOutputSigned,inputVector,inputInterpretation,biasVector)
197197
vector<half, 7> vec24 = MultiplyAdd<half>(Mat_7_15_Packed, interpVecH15Packed, memBias7Packed);
198198

199199
// CHECK: call void @dx.op.linAlgVectorAccumulateToDescriptor.v4f16(i32 -2147483617, %dx.types.Handle %{{[0-9]+}},

0 commit comments

Comments
 (0)