diff --git a/package.yaml b/package.yaml
index 71d1416..3aada36 100644
--- a/package.yaml
+++ b/package.yaml
@@ -27,7 +27,7 @@ dependencies:
   - bytestring
   - mtl
   - transformers
-  - barbies ^>= 2.0.1
+  - barbies >= 2.0.1
   - barbies-th
   - containers
   - array
@@ -71,6 +71,7 @@ ghc-options:
   -fplugin GHC.TypeLits.KnownNat.Solver
   -fplugin GHC.TypeLits.Normalise
   -fplugin GHC.TypeLits.Extra.Solver
+  -freduction-depth=1024
 
 source-dirs:
   - src
diff --git a/src/Hardware/Intel8080.hs b/src/Hardware/Intel8080.hs
index 4a41b94..80800ef 100644
--- a/src/Hardware/Intel8080.hs
+++ b/src/Hardware/Intel8080.hs
@@ -1,7 +1,7 @@
 {-# LANGUAGE PatternSynonyms #-}
 module Hardware.Intel8080 where
 
-import Clash.Prelude
+import Clash.Prelude hiding (And)
 import Clash.Annotations.BitRepresentation hiding (Value)
 
 type Reg = Index 8
diff --git a/src/Hardware/Intel8080/ALU.hs b/src/Hardware/Intel8080/ALU.hs
index 3a8a31f..277212f 100644
--- a/src/Hardware/Intel8080/ALU.hs
+++ b/src/Hardware/Intel8080/ALU.hs
@@ -2,7 +2,7 @@ module Hardware.Intel8080.ALU (binALU, shiftRotateALU) where
 
 import Prelude ()
 import Data.Word
-import Clash.Prelude
+import Clash.Prelude hiding (And)
 import Hardware.Intel8080
 
 nybbles :: Value -> (Unsigned 4, Unsigned 4)
diff --git a/src/Hardware/Intel8080/CPU.hs b/src/Hardware/Intel8080/CPU.hs
index a4c0c65..bcc2c75 100644
--- a/src/Hardware/Intel8080/CPU.hs
+++ b/src/Hardware/Intel8080/CPU.hs
@@ -19,6 +19,7 @@ import Control.Monad.State
 import Control.Monad.Trans.Maybe
 import Control.Monad.Except
 import Control.Lens hiding (Index)
+import Control.Monad (void, guard, when, unless)
 import Data.Maybe (fromMaybe, isJust)
 import Data.Wedge
 
diff --git a/src/Hardware/Intel8080/MicroCPU.hs b/src/Hardware/Intel8080/MicroCPU.hs
index 2e80e7c..7accbae 100644
--- a/src/Hardware/Intel8080/MicroCPU.hs
+++ b/src/Hardware/Intel8080/MicroCPU.hs
@@ -17,6 +17,7 @@ import Control.Monad.State
 import Control.Arrow ((&&&))
 import Control.Monad.Trans.Maybe
 import Control.Monad.Except
+import Control.Monad (unless, when)
 import Text.Printf
 
 data FlowControl
diff --git a/src/Hardware/Intel8080/Microcode.hs b/src/Hardware/Intel8080/Microcode.hs
index 2a3ccb9..7e671dd 100644
--- a/src/Hardware/Intel8080/Microcode.hs
+++ b/src/Hardware/Intel8080/Microcode.hs
@@ -106,6 +106,8 @@ pop2 =
 popPC :: MicroSteps True False
 popPC = pop2 >++> step INothing Jump INothing
 
+instance NFDataX (Wedge OutAddr InAddr)
+
 type MicroOp = (MicroInstr, Wedge OutAddr InAddr)
 type Setup = Maybe InAddr
 type MicroOps = [MicroOp]
diff --git a/src/Hardware/Intel8080/Model.hs b/src/Hardware/Intel8080/Model.hs
index e8ae643..ffc9e97 100644
--- a/src/Hardware/Intel8080/Model.hs
+++ b/src/Hardware/Intel8080/Model.hs
@@ -16,6 +16,7 @@ import Control.Monad.Trans.Maybe
 import Data.Foldable (traverse_)
 import Data.Bifoldable (bitraverse_)
 import Control.Monad.Extra (whenM, whileM)
+import Control.Monad (unless, when, void, (<=<))
 import Control.Lens hiding (index)
 import Data.Wedge
 
diff --git a/test/test-model.hs b/test/test-model.hs
index d51d3e1..6d43899 100644
--- a/test/test-model.hs
+++ b/test/test-model.hs
@@ -18,7 +18,7 @@ import Data.Char (chr)
 import Test.Tasty (defaultMain, TestTree, testGroup)
 import Test.Tasty.Golden (goldenVsString, findByExtension)
 import System.FilePath ((<.>))
-import Data.ByteString.Lazy.Builder
+import Data.ByteString.Builder
 import Data.ByteString.Lazy (ByteString)
 
 run :: Bool -> IOArray Addr Value -> IO ByteString
diff --git a/test/test-sim.hs b/test/test-sim.hs
index 78fcaab..fee90b1 100644
--- a/test/test-sim.hs
+++ b/test/test-sim.hs
@@ -23,7 +23,7 @@ import Test.Tasty (defaultMain, TestTree, testGroup)
 import Test.Tasty.Golden (goldenVsString, findByExtension)
 import Test.QuickCheck
 import System.FilePath ((<.>))
-import Data.ByteString.Lazy.Builder
+import Data.ByteString.Builder
 import Data.ByteString.Lazy (ByteString)
 
 run :: Bool -> IOArray Addr Value -> IO ByteString