From 52d4cfe5c9afbffbe1f1b0dfb2cabf363f7155b7 Mon Sep 17 00:00:00 2001 From: Benjamin Ramhorst Date: Wed, 12 Mar 2025 14:47:10 +0100 Subject: [PATCH 01/52] Delete unnecessary files for the tutorial/test --- driver-guest/Makefile | 10 - driver-guest/guest_dev.h | 202 -- driver-guest/guest_drv.c | 103 - driver-guest/guest_drv.h | 13 - driver-guest/guest_fops.c | 329 --- driver-guest/guest_fops.h | 12 - driver-guest/guest_irq.c | 96 - driver-guest/guest_irq.h | 36 - driver-guest/guest_mm.c | 277 --- driver-guest/guest_mm.h | 10 - driver-guest/guest_pci.c | 226 --- driver-guest/guest_pci.h | 10 - driver-guest/setup.sh | 5 - driver-guest/test/Makefile | 18 - driver-guest/test/bench_huge.c | 165 -- driver-guest/test/test | Bin 16344 -> 0 bytes driver-guest/test/test.c | 178 -- driver-guest/test/test.h | 54 - driver-guest/test/test2.c | 72 - driver-guest/test/test_inter.c | 58 - driver/hypervisor/hypervisor.h | 171 -- driver/hypervisor/hypervisor_drv.c | 110 - driver/hypervisor/hypervisor_drv.h | 37 - driver/hypervisor/hypervisor_interrupts.c | 331 --- driver/hypervisor/hypervisor_interrupts.h | 43 - driver/hypervisor/hypervisor_mmu.c | 546 ----- driver/hypervisor/hypervisor_mmu.h | 39 - driver/hypervisor/hypervisor_ops.c | 1772 ----------------- driver/hypervisor/hypervisor_ops.h | 38 - examples_hw/CMakeLists.txt | 257 --- examples_hw/apps/gbm_dtrees/hdl/DTPackage.sv | 91 - .../apps/gbm_dtrees/hdl/DTProcessor.sv | 557 ------ .../apps/gbm_dtrees/hdl/Data_Memory.sv | 73 - .../gbm_dtrees/hdl/FPAdder_2cycles_latency.sv | 389 ---- .../gbm_dtrees/hdl/FPAdder_3cycles_latency.v | 458 ----- .../gbm_dtrees/hdl/FPAdder_4cycles_latency.v | 420 ---- .../apps/gbm_dtrees/hdl/FPAddersReduceTree.sv | 156 -- .../gbm_dtrees/hdl/FPAddersReduceTree_sync.sv | 286 --- .../apps/gbm_dtrees/hdl/FPAggregator.sv | 174 -- .../apps/gbm_dtrees/hdl/LineRateConvertor.sv | 134 -- .../apps/gbm_dtrees/hdl/RegBasedFIFO.sv | 122 -- .../apps/gbm_dtrees/hdl/Tree_Memory.sv | 192 -- examples_hw/apps/gbm_dtrees/hdl/bram.sv | 55 - .../apps/gbm_dtrees/hdl/bram_1_in_2_out.sv | 136 -- .../apps/gbm_dtrees/hdl/bus_aligner.sv | 183 -- .../apps/gbm_dtrees/hdl/compute_unit.sv | 241 --- examples_hw/apps/gbm_dtrees/hdl/delay.sv | 75 - .../apps/gbm_dtrees/hdl/dual_port_mem.sv | 128 -- examples_hw/apps/gbm_dtrees/hdl/gbm_slave.sv | 293 --- .../apps/gbm_dtrees/hdl/pe_datapath.sv | 369 ---- .../apps/gbm_dtrees/hdl/processing_element.sv | 442 ---- .../hdl/processing_element_async.sv | 453 ----- examples_hw/apps/gbm_dtrees/hdl/quick_fifo.sv | 149 -- .../apps/gbm_dtrees/hdl/smart_shifter.sv | 83 - examples_hw/apps/gbm_dtrees/init_ip.tcl | 2 - examples_hw/apps/gbm_dtrees/vfpga_top.svh | 240 --- .../hls/hllsketch_16x32/Collector.hpp | 144 -- .../hls/hllsketch_16x32/HllSketch.hpp | 183 -- .../hls/hllsketch_16x32/bit_utils.hpp | 165 -- .../hls/hllsketch_16x32/hashes.hpp | 108 - .../hls/hllsketch_16x32/hllsketch_16x32.cpp | 108 - .../hls/hllsketch_16x32/hllsketch_16x32.hpp | 101 - .../hls/hllsketch_16x32/stream.hpp | 310 --- examples_hw/apps/hyperloglog/init_ip.tcl | 2 - examples_hw/apps/hyperloglog/vfpga_top.svh | 70 - .../apps/rdma_aes/hdl/aes_pipe_stage.vhd | 75 - .../apps/rdma_aes/hdl/aes_pipeline.vhd | 129 -- examples_hw/apps/rdma_aes/hdl/aes_round.vhd | 81 - .../apps/rdma_aes/hdl/aes_round_last.vhd | 64 - examples_hw/apps/rdma_aes/hdl/aes_top.vhd | 256 --- .../apps/rdma_aes/hdl/data_pipeline.vhd | 86 - examples_hw/apps/rdma_aes/hdl/gf_mult.vhd | 127 -- .../apps/rdma_aes/hdl/inv_mix_columns.vhd | 81 - .../apps/rdma_aes/hdl/inv_s_box_lut.vhd | 41 - .../apps/rdma_aes/hdl/inv_shift_rows.vhd | 54 - .../apps/rdma_aes/hdl/key_expansion.vhd | 100 - .../apps/rdma_aes/hdl/key_pipe_reg.vhd | 50 - .../apps/rdma_aes/hdl/key_pipe_stage.vhd | 52 - .../apps/rdma_aes/hdl/key_pipeline.vhd | 106 - examples_hw/apps/rdma_aes/hdl/key_top.vhd | 66 - examples_hw/apps/rdma_aes/hdl/mix_columns.vhd | 51 - .../rdma_aes/hdl/mux_host_card_rd_rdma.sv | 178 -- .../rdma_aes/hdl/mux_host_card_wr_rdma.sv | 187 -- examples_hw/apps/rdma_aes/hdl/pipe_reg.vhd | 66 - examples_hw/apps/rdma_aes/hdl/rdma_aes_slv.sv | 245 --- examples_hw/apps/rdma_aes/hdl/s_box_lut.vhd | 40 - examples_hw/apps/rdma_aes/hdl/shift_rows.vhd | 54 - examples_hw/apps/rdma_aes/hdl/utils.vhd | 58 - examples_hw/apps/rdma_aes/vfpga_top.svh | 158 -- .../rdma_base/hdl/mux_host_card_rd_rdma.sv | 178 -- .../rdma_base/hdl/mux_host_card_wr_rdma.sv | 187 -- .../apps/rdma_base/hdl/rdma_base_slv.sv | 214 -- examples_hw/apps/rdma_base/vfpga_top.svh | 51 - examples_hw/apps/tcp_iperf/hls/CMakeLists.txt | 80 - examples_hw/apps/tcp_iperf/hls/axi_utils.cpp | 311 --- examples_hw/apps/tcp_iperf/hls/axi_utils.hpp | 1393 ------------- examples_hw/apps/tcp_iperf/hls/make.tcl.in | 34 - examples_hw/apps/tcp_iperf/hls/packet.hpp | 166 -- examples_hw/apps/tcp_iperf/hls/send_recv.cpp | 470 ----- examples_hw/apps/tcp_iperf/hls/send_recv.hpp | 99 - .../tcp_iperf/hls/send_recv_config.hpp.in | 3 - .../apps/tcp_iperf/hls/test_send_recv.cpp | 122 -- examples_hw/apps/tcp_iperf/hls/toe.hpp | 195 -- examples_hw/apps/tcp_iperf/perf_tcp_c0_0.svh | 56 - examples_hw/apps/tcp_iperf/send_recv.sv | 116 -- examples_hw/apps/tcp_iperf/send_recv_role.sv | 630 ------ examples_hw/apps/tcp_iperf/send_recv_slave.sv | 372 ---- examples_hw/apps/tcp_iperf/set_ila.tcl | 33 - .../floorplans/streaming_fplan_u55c.xdc | 9 - examples_sw/CMakeLists.txt | 116 -- .../apps/streaming_service/client/main.cpp | 142 -- .../apps/streaming_service/include/types.hpp | 23 - .../server/include/gbm_dtrees.hpp | 179 -- .../apps/streaming_service/server/main.cpp | 257 --- examples_sw/apps/tcp_iperf/main.cpp | 179 -- 115 files changed, 20330 deletions(-) delete mode 100644 driver-guest/Makefile delete mode 100644 driver-guest/guest_dev.h delete mode 100644 driver-guest/guest_drv.c delete mode 100644 driver-guest/guest_drv.h delete mode 100644 driver-guest/guest_fops.c delete mode 100644 driver-guest/guest_fops.h delete mode 100644 driver-guest/guest_irq.c delete mode 100644 driver-guest/guest_irq.h delete mode 100644 driver-guest/guest_mm.c delete mode 100644 driver-guest/guest_mm.h delete mode 100644 driver-guest/guest_pci.c delete mode 100644 driver-guest/guest_pci.h delete mode 100755 driver-guest/setup.sh delete mode 100644 driver-guest/test/Makefile delete mode 100644 driver-guest/test/bench_huge.c delete mode 100644 driver-guest/test/test delete mode 100644 driver-guest/test/test.c delete mode 100644 driver-guest/test/test.h delete mode 100644 driver-guest/test/test2.c delete mode 100644 driver-guest/test/test_inter.c delete mode 100644 driver/hypervisor/hypervisor.h delete mode 100644 driver/hypervisor/hypervisor_drv.c delete mode 100644 driver/hypervisor/hypervisor_drv.h delete mode 100644 driver/hypervisor/hypervisor_interrupts.c delete mode 100644 driver/hypervisor/hypervisor_interrupts.h delete mode 100644 driver/hypervisor/hypervisor_mmu.c delete mode 100644 driver/hypervisor/hypervisor_mmu.h delete mode 100644 driver/hypervisor/hypervisor_ops.c delete mode 100644 driver/hypervisor/hypervisor_ops.h delete mode 100644 examples_hw/CMakeLists.txt delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/DTPackage.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/DTProcessor.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/Data_Memory.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/FPAdder_2cycles_latency.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/FPAdder_3cycles_latency.v delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/FPAdder_4cycles_latency.v delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/FPAddersReduceTree.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/FPAddersReduceTree_sync.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/FPAggregator.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/LineRateConvertor.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/RegBasedFIFO.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/Tree_Memory.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/bram.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/bram_1_in_2_out.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/bus_aligner.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/compute_unit.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/delay.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/dual_port_mem.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/gbm_slave.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/pe_datapath.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/processing_element.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/processing_element_async.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/quick_fifo.sv delete mode 100644 examples_hw/apps/gbm_dtrees/hdl/smart_shifter.sv delete mode 100644 examples_hw/apps/gbm_dtrees/init_ip.tcl delete mode 100644 examples_hw/apps/gbm_dtrees/vfpga_top.svh delete mode 100644 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examples_sw/apps/tcp_iperf/main.cpp diff --git a/driver-guest/Makefile b/driver-guest/Makefile deleted file mode 100644 index 448f886b0..000000000 --- a/driver-guest/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -KERNELDIR ?= /lib/modules/$(shell uname -r)/build - -obj-m := coyote-guest.o -coyote-guest-objs := guest_drv.o guest_fops.o guest_pci.o guest_mm.o guest_irq.o - -all: - $(MAKE) -C $(KERNELDIR) M=$(PWD) modules - -clean: - $(MAKE) -C $(KERNELDIR) M=$(PWD) clean \ No newline at end of file diff --git a/driver-guest/guest_dev.h b/driver-guest/guest_dev.h deleted file mode 100644 index 7b366d01a..000000000 --- a/driver-guest/guest_dev.h +++ /dev/null @@ -1,202 +0,0 @@ -#ifndef __GUEST_DEV_H__ -#define __GUEST_DEV_H__ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define GUEST_MODULE_AUTHOR "Paul Dahlke " -#define GUEST_MODULE_LICENSE "GPL" -#define GUEST_MODULE_DESCRIPTION "Coyote hypervisor guest driver" -#define DRV_NAME "coyote-guest" - -#define COYOTE_DEBUG 0 -#define MAX_USER_ARGS 32 -#define INVALID_CPID 0xffffffffffffffff -#define N_CPID_MAX 64 - -/* Hash */ -#define USER_HASH_TABLE_ORDER 8 - -/* MMAP Regions */ -#define MMAP_CTRL 0x0 -#define MMAP_CNFG 0x1 -#define MMAP_CNFG_AVX 0x2 -#define MMAP_WB 0x3 -#define MMAP_BUFF 0x200 -#define MMAP_PR 0x400 -#define FPGA_CTRL_SIZE 256 * 1024 -#define FPGA_CTRL_OFFS 0x100000 -#define FPGA_CTRL_LTLB_SIZE FPGA_CTRL_SIZE / 4 -#define FPGA_CTRL_LTLB_OFFS 0x0 -#define FPGA_CTRL_STLB_SIZE FPGA_CTRL_SIZE / 4 -#define FPGA_CTRL_STLB_OFFS 0x10000 -#define FPGA_CTRL_USER_SIZE FPGA_CTRL_SIZE / 4 -#define FPGA_CTRL_USER_OFFS 0x20000 -#define FPGA_CTRL_CNFG_SIZE FPGA_CTRL_SIZE / 4 -#define FPGA_CTRL_CNFG_OFFS 0x30000 -#define FPGA_CTRL_CNFG_AVX_SIZE 256 * 1024 -#define FPGA_CTRL_CNFG_AVX_OFFS 0x1000000 - -/* FPGA dynamic control config */ -#define FPGA_CNFG_CTRL_IRQ_RESTART 0x100 - -/* IOCTL */ -#define IOCTL_ALLOC_HOST_USER_MEM _IOW('D', 1, unsigned long) // large pages (no hugepage support) -#define IOCTL_FREE_HOST_USER_MEM _IOW('D', 2, unsigned long) -#define IOCTL_ALLOC_HOST_RECONFIG_MEM _IOW('D', 3, unsigned long) // pr pages -#define IOCTL_FREE_HOST_RECONFIG_MEM _IOW('D', 4, unsigned long) -#define IOCTL_MAP_USER _IOW('D', 5, unsigned long) // map -#define IOCTL_UNMAP_USER _IOW('D', 6, unsigned long) -#define IOCTL_REGISTER_PID _IOW('D', 7, unsigned long) // register pid -#define IOCTL_UNREGISTER_PID _IOW('D', 8, unsigned long) -#define IOCTL_RECONFIG_LOAD _IOW('D', 9, unsigned long) // reconfiguration - -#define IOCTL_ARP_LOOKUP _IOW('D', 10, unsigned long) // arp lookup -#define IOCTL_SET_IP_ADDRESS _IOW('D', 11, unsigned long) -#define IOCTL_SET_MAC_ADDRESS _IOW('D', 12, unsigned long) -#define IOCTL_WRITE_CTX _IOW('D', 13, unsigned long) // qp context -#define IOCTL_WRITE_CONN _IOW('D', 14, unsigned long) // qp connection -#define IOCTL_SET_TCP_OFFS _IOW('D', 15, unsigned long) // tcp mem offsets - -#define IOCTL_READ_CNFG _IOR('D', 32, unsigned long) // status cnfg -#define IOCTL_XDMA_STATS _IOR('D', 33, unsigned long) // status xdma -#define IOCTL_NET_STATS _IOR('D', 34, unsigned long) // status network -#define IOCTL_READ_ENG_STATUS _IOR('D', 35, unsigned long) // status engines - -#define IOCTL_NET_DROP _IOW('D', 36, unsigned long) // net dropper -#define IOCTL_TEST_INTERRUPT _IO('D', 37) - -/* BAR2 offsets */ -#define REGISTER_PID_OFFSET 0x00 -#define UNREGISTER_PID_OFFSET 0x08 -#define MAP_USER_OFFSET 0x10 -#define UNMAP_USER_OFFSET 0x18 -#define READ_CNFG_OFFSET 0x20 -#define PUT_ALL_USER_PAGES 0x28 -#define TEST_INTERRUPT_OFFSET 0x30 - -/* Interrupts */ -#define NUM_USER_INTERRUPTS 1 - -/* LTLB values */ -// TODO: read the config from the device to popoulate those -#define LTLB_PAGE_SHIFT 21 -#define LTLB_PAGE_SIZE (1 << LTLB_PAGE_SHIFT) - -/* Obtain the 32 most significant (high) bits of a 32-bit or 64-bit address */ -#define HIGH_32(addr) ((addr >> 16) >> 16) -/* Obtain the 32 least significant (low) bits of a 32-bit or 64-bit address */ -#define LOW_32(addr) (addr & 0xffffffffUL) - -#if (COYOTE_DEBUG == 0) -#define dbg_info(...) -#else -#define dbg_info(fmt, ...) pr_info("%s():" fmt, \ - __func__, ##__VA_ARGS__) -#endif - -/* FPGA dynamic config reg map */ -struct fpga_cnfg_regs -{ - uint64_t ctrl; - uint64_t vaddr_rd; - uint64_t len_rd; - uint64_t vaddr_wr; - uint64_t len_wr; - uint64_t vaddr_miss; - uint64_t len_miss; - uint64_t datapath_set; - uint64_t datapath_clr; - uint64_t stat_cmd_used_rd; - uint64_t stat_cmd_used_wr; - uint64_t stat_sent[6]; - uint64_t stat_pfaults; - uint64_t wback[4]; - // Rest of regs not used in the driver -} __packed; - -/* FPGA dynamic config reg map */ -struct fpga_cnfg_regs_avx -{ - uint64_t ctrl[4]; - uint64_t vaddr_miss; - uint64_t len_miss; - uint64_t pf[2]; - uint64_t datapath_set[4]; - uint64_t datapath_clr[4]; - uint64_t stat[4]; - uint64_t wback[4]; - // Rest not used in the driver -} __packed; - -/* vfpga device */ -struct vfpga -{ - struct pci_dev *pdev; - struct cdev cdev; - struct device *dev; - pid_t *pid_array; - - spinlock_t cpid_lock; - spinlock_t lock; - - uint64_t curr_offset; - uint64_t n_pages; - - struct - { - volatile void __iomem *bar0; - volatile void __iomem *bar2; - volatile void __iomem *bar4; - - resource_size_t bar0_start, bar0_end; - resource_size_t bar2_start, bar2_end; - resource_size_t bar4_start, bar4_end; - } pci_resources; - - struct msix_entry irq_entry[32]; - - // Control region - uint64_t fpga_phys_addr_ctrl; - uint64_t fpga_phys_addr_ctrl_avx; - - struct fpga_cnfg_regs *fpga_cnfg; // config - struct fpga_cnfg_regs_avx *fpga_cnfg_avx; // config AVX - - int en_avx; -}; - -struct user_pages -{ - struct hlist_node entry; - uint64_t vaddr; - uint64_t n_pages; - int32_t cpid; - struct page **hpages; -}; - -struct hypervisor_map_notifier -{ - uint64_t npages; - uint64_t len; - uint64_t gva; - uint64_t cpid; - uint64_t dirtied; - uint64_t is_huge; - uint64_t gpas[0]; -}; - -extern struct hlist_head user_sbuff_map[1 << (USER_HASH_TABLE_ORDER)]; - -extern struct class *guest_class; -extern struct vfpga vfpga; -extern dev_t devt; -extern struct file_operations fops; - -#endif \ No newline at end of file diff --git a/driver-guest/guest_drv.c b/driver-guest/guest_drv.c deleted file mode 100644 index b1b943904..000000000 --- a/driver-guest/guest_drv.c +++ /dev/null @@ -1,103 +0,0 @@ - -#include "guest_drv.h" - -struct class *guest_class; - -// -// Device driver struct -// - -static struct pci_device_id ids[] = { - { PCI_DEVICE(0x0102, 0x0304) }, - { 0 } -}; -MODULE_DEVICE_TABLE(pci, ids); - -static struct pci_driver driver = { - .name = DRV_NAME, - .probe = guest_probe, - .remove = guest_remove, - .id_table = ids -}; - -/** - * @brief Sets the permissions for the device file. Harcoded - * to rw for all users - * - * @param dev - * @param env - * @return int - */ -static int guest_uevent(struct device *dev, struct kobj_uevent_env *env) -{ - add_uevent_var(env, "DEVMODE=%#o", 0666); - - return 0; -} - -// -// Module enty points -// - -/** - * @brief Called on load of the module and sets up a driver that - * can handle the emulated pci device - * - * @return int - */ -static int __init guest_init() -{ - int ret_val; - - ret_val = 0; - - // Create class - guest_class = class_create(THIS_MODULE, "coyote-guest"); - guest_class->dev_uevent = guest_uevent; - - if (IS_ERR_OR_NULL(guest_class)) - { - pr_err("Failed to create pci class\n"); - return -1; - } - - // Register driver - ret_val = pci_register_driver(&driver); - if (ret_val) - { - pr_err("Failed to register driver\n"); - } - - dbg_info("init coyote guest driver"); - - return ret_val; - -} - -/** - * @brief clean up of management structures - * and removes all sysfs entries. Deregisters the driver - * with the kernel. - * - */ -static void __exit guest_exit() -{ - int ret_val; - - ret_val = 0; - - pci_unregister_driver(&driver); - class_destroy(guest_class); - - dbg_info("exit coyote guest driver"); -} - -// -// Registering module -// - -module_init(guest_init); -module_exit(guest_exit); -MODULE_AUTHOR(GUEST_MODULE_AUTHOR); -MODULE_LICENSE(GUEST_MODULE_LICENSE); -MODULE_DESCRIPTION(GUEST_MODULE_DESCRIPTION); \ No newline at end of file diff --git a/driver-guest/guest_drv.h b/driver-guest/guest_drv.h deleted file mode 100644 index d067b8cb7..000000000 --- a/driver-guest/guest_drv.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __GUEST_DRV_H__ -#define __GUEST_DRV_H__ - -#include "guest_dev.h" -#include "guest_pci.h" - -/* -* Main functions -*/ -static int __init guest_init(void); -static void __exit guest_exit(void); - -#endif \ No newline at end of file diff --git a/driver-guest/guest_fops.c b/driver-guest/guest_fops.c deleted file mode 100644 index 7e45802c8..000000000 --- a/driver-guest/guest_fops.c +++ /dev/null @@ -1,329 +0,0 @@ -#include "guest_fops.h" - -/** - * @brief file operations that handle this device - * - */ -struct file_operations fops = { - .open = guest_open, - .release = guest_release, - .unlocked_ioctl = guest_ioctl, - .mmap = guest_mmap}; - -/** - * @brief called on opening a file. - * Sets the file descriptor private data to later on access the - * device struct easier. - * - * @param inode - * @param f - * @return int - */ -int guest_open(struct inode *inode, struct file *f) -{ - struct vfpga *d; - - d = container_of(inode->i_cdev, struct vfpga, cdev); - BUG_ON(!d); - - dbg_info("fpga device acquired\n"); - - f->private_data = (void *)d; - - return 0; -} - -/** - * @brief Called when the device file is closed. - * Releases all memory associated with this device by performing a - * call to the hypervisor and cleaning up all local mappings. - * - * @param inode - * @param f - * @return int - */ -int guest_release(struct inode *inode, struct file *f) -{ - struct vfpga *d; - - d = (struct vfpga *)f->private_data; - BUG_ON(!d); - - // release all user pages - guest_put_all_user_pages(d, 1); - - dbg_info("fpga device released"); - return 0; -} - -/** - * @brief guest version of register pid. - * Writes to the REGISTER_PID register to - * notify hypervisor of pid and then reads the same register - * to get a cpid - * - * @param d vfpga struct - * @param pid pid of the process - * @return int32_t returns the cpid - */ -static int32_t register_pid(struct vfpga *d, pid_t pid) -{ - uint64_t cpid; - unsigned long addr; - - BUG_ON(!d); - addr = (unsigned long)d->pci_resources.bar2 + REGISTER_PID_OFFSET; - cpid = INVALID_CPID; - - // Write pid to device - writeq((uint64_t)pid, (void __iomem *)addr); - - // pull cpid - while (cpid == INVALID_CPID) - { - cpid = readq((void __iomem *)addr); - } - - // store for bookkeeping - d->pid_array[cpid] = pid; - - return cpid; -} - -/** - * @brief Notifies the hypervisor of the unregistration of a process. Management - * is handled in the hypervisor. - * - * @param d - * @param cpid - */ -static void unregister_pid(struct vfpga *d, pid_t cpid) -{ - unsigned long addr; - - BUG_ON(!d); - addr = (unsigned long)d->pci_resources.bar2 + UNREGISTER_PID_OFFSET; - - // write cpid to unregister offset - writeq((uint64_t)cpid, (void __iomem *)addr); - d->pid_array[cpid] = 0; -} - -/** - * @brief Handles ioctls to the device. Exposes - * a similar interface as the normal driver to make it - * easy to use the library and existing code. The following - * ioctl calls are implemented: - * - * - IOCTL_REGISTER_PID - * Called to register a process. Passes its pid as argument and returns - * a cpid - * - * - IOCTL_UNREGISTER_PID - * Called with the cpid and deregisters this cpid again. - * - * - IOCTL_MAP_USER - * Called with vaddr, length, and cpid. Maps a region allocated by the user - * to the fpga. - * - * - IOCTL_UNMAP_USER - * Called with vaddr and cpid. Unmaps a previously mapped region. - * - * - IOCTL_READ_CNFG - * Called without any arguments and returns a number that encodes - * the platform configuration. - * - * @param f - * @param cmd - * @param arg - * @return long - */ -long guest_ioctl(struct file *f, unsigned int cmd, unsigned long arg) -{ - struct vfpga *d; - int ret_val; - uint64_t tmp[MAX_USER_ARGS]; - uint64_t cpid; - - d = (struct vfpga *)f->private_data; - BUG_ON(!d); - - dbg_info("ioctl called with cmd %d and arg %lx\n", cmd, arg); - - switch (cmd) - { - case IOCTL_REGISTER_PID: - { - ret_val = copy_from_user(&tmp, (unsigned long *)arg, sizeof(unsigned long)); - if (ret_val) - { - pr_info("Failed to copy from user"); - return ret_val; - } - - spin_lock(&d->cpid_lock); - cpid = register_pid(d, tmp[0]); - if (cpid == -1) - { - dbg_info("registraion failed for pid %lld\n", tmp[0]); - spin_unlock(&d->cpid_lock); - return -EIO; - } - - dbg_info("registration succeeded pid %lld, cpid %lld\n", tmp[0], cpid); - ret_val = copy_to_user((unsigned long *)arg + 1, &cpid, sizeof(unsigned long)); - if (ret_val) - { - pr_info("Failed to wirte data"); - spin_unlock(&d->cpid_lock); - return ret_val; - } - spin_unlock(&d->cpid_lock); - return 0; - } - case IOCTL_UNREGISTER_PID: - { - ret_val = copy_from_user(&tmp, (unsigned long *)arg, sizeof(unsigned long)); - if (ret_val) - { - pr_info("Failed to copy from user"); - return ret_val; - } - - spin_lock(&d->cpid_lock); - - unregister_pid(d, tmp[0]); - - spin_unlock(&d->cpid_lock); - dbg_info("unregistration succeeded cpid %lld\n", tmp[0]); - - return 0; - } - case IOCTL_MAP_USER: - { - // read vaddr + len + cpid - ret_val = copy_from_user(&tmp, (unsigned long *)arg, sizeof(unsigned long) * 3); - if (ret_val) - { - pr_info("Failed to copy addr info from user\n"); - return ret_val; - } - - cpid = tmp[2]; - - dbg_info("Mapping user vaddr %llx of size %llu for cpid %llu\n", tmp[0], tmp[1], tmp[2]); - ret_val = guest_get_user_pages(d, tmp[0], tmp[1], (int32_t)tmp[2], d->pid_array[cpid]); - return ret_val; - } - case IOCTL_UNMAP_USER: - { - // read vaddr + cpid - ret_val = copy_from_user(&tmp, (unsigned long *)arg, sizeof(unsigned long) * 2); - if (ret_val) - { - pr_info("could not get addr info from user\n"); - return ret_val; - } - - dbg_info("Putting user pages\n"); - ret_val = guest_put_user_pages(d, tmp[0], (int32_t)tmp[1], 1); - return ret_val; - } - case IOCTL_READ_CNFG: - { - tmp[0] = readq((void __iomem *)d->pci_resources.bar2 + READ_CNFG_OFFSET); - ret_val = copy_to_user((unsigned long *)arg, &tmp, sizeof(unsigned long)); - if (ret_val) - { - pr_info("Cannot read configuration\n"); - return ret_val; - } - return 0; - } - case IOCTL_TEST_INTERRUPT: - { - writeq(0, d->pci_resources.bar2 + TEST_INTERRUPT_OFFSET); - return 0; - } - } - - // Not supported IOCTL - return -EINVAL; -} - -/** - * @brief mmap of regions of the fpga. The actual fpga is here not available - * we map into bar0 of the virtual device that acts as a passthrough to the - * real hardware. Transparent to the user. - * - * @param f - * @param vma - * @return int - */ -int guest_mmap(struct file *f, struct vm_area_struct *vma) -{ - struct vfpga *d; - unsigned long vaddr; - unsigned long target_addr; - int ret_val; - - d = (struct vfpga *)f->private_data; - BUG_ON(!d); - - vaddr = vma->vm_start; - - dbg_info("called mmap with offset %lu\n", vma->vm_pgoff); - - // Do not cache this pages - vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); - - // user ctrl region - if (vma->vm_pgoff == MMAP_CTRL) - { - dbg_info("mapping user ctrl region at %llx of size %x\n", - d->fpga_phys_addr_ctrl + FPGA_CTRL_USER_OFFS, FPGA_CTRL_USER_SIZE); - target_addr = (unsigned long)d->fpga_phys_addr_ctrl + FPGA_CTRL_USER_OFFS; - - ret_val = remap_pfn_range(vma, vma->vm_start, target_addr >> PAGE_SHIFT, - FPGA_CTRL_USER_SIZE, vma->vm_page_prot); - if (ret_val) - { - return -EIO; - } - return 0; - } - - // cnfg region - if (vma->vm_pgoff == MMAP_CNFG) - { - dbg_info("mapping config region at %llx of size %x\n", - d->fpga_phys_addr_ctrl + FPGA_CTRL_CNFG_OFFS, FPGA_CTRL_USER_SIZE); - target_addr = (unsigned long)d->fpga_phys_addr_ctrl + FPGA_CTRL_CNFG_OFFS; - - ret_val = remap_pfn_range(vma, vma->vm_start, target_addr >> PAGE_SHIFT, - FPGA_CTRL_CNFG_SIZE, vma->vm_page_prot); - if (ret_val) - { - return -EIO; - } - return 0; - } - - // cnfg AVX region - if (vma->vm_pgoff == MMAP_CNFG_AVX) - { - dbg_info("mapping config AVX region at %llx of size %x\n", - d->fpga_phys_addr_ctrl_avx, FPGA_CTRL_CNFG_AVX_SIZE); - target_addr = (unsigned long)d->fpga_phys_addr_ctrl_avx; - - ret_val = remap_pfn_range(vma, vma->vm_start, target_addr >> PAGE_SHIFT, - FPGA_CTRL_CNFG_AVX_SIZE, vma->vm_page_prot); - if (ret_val) - { - return -EIO; - } - return 0; - } - - return -EINVAL; -} \ No newline at end of file diff --git a/driver-guest/guest_fops.h b/driver-guest/guest_fops.h deleted file mode 100644 index 37eb9b473..000000000 --- a/driver-guest/guest_fops.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef __GUEST_FOPS_H__ -#define __GUEST_FOPS_H__ - -#include "guest_dev.h" -#include "guest_mm.h" - -int guest_open(struct inode* inode, struct file *f); -int guest_release(struct inode *inode, struct file *f); -long guest_ioctl(struct file *f, unsigned int cmd, unsigned long arg); -int guest_mmap(struct file *f, struct vm_area_struct *vma); - -#endif \ No newline at end of file diff --git a/driver-guest/guest_irq.c b/driver-guest/guest_irq.c deleted file mode 100644 index 6dcb3e7e9..000000000 --- a/driver-guest/guest_irq.c +++ /dev/null @@ -1,96 +0,0 @@ -/** - * Copyright (c) 2021, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "guest_irq.h" - -/** - * @brief Guest callback for a page fault on the fpga. - * This handles an interrupt that is fired by the hypervisor - * as a response to a real interrupt happening in hardware. - * The function reads the faulting address from special hardware - * registers and uses the get user pages function - * to install mappings on the hardware. - * - * @param irq - * @param dev_id - * @return irqreturn_t - */ -irqreturn_t guest_fpga_tlb_miss_isr(int irq, void *dev_id) -{ - unsigned long flags; - uint64_t vaddr; - uint32_t len; - int32_t cpid; - struct vfpga *d; - int ret_val = 0; - pid_t pid; - uint64_t tmp; - - dbg_info("(irq=%d) page fault ISR\n", irq); - BUG_ON(!dev_id); - - d = (struct vfpga *)dev_id; - BUG_ON(!d); - - // lock - spin_lock_irqsave(&(d->lock), flags); - - // read page fault from hardware register - if (d->en_avx) { - vaddr = d->fpga_cnfg_avx->vaddr_miss; - tmp = d->fpga_cnfg_avx->len_miss; - len = LOW_32(tmp); - cpid = (int32_t)HIGH_32(tmp); - } - else { - vaddr = d->fpga_cnfg->vaddr_miss; - tmp = d->fpga_cnfg->len_miss; - len = LOW_32(tmp); - cpid = (int32_t)HIGH_32(tmp); - } - dbg_info("page fault, vaddr %llx, length %x, cpid %d\n", vaddr, len, cpid); - - // get user pages - pid = d->pid_array[cpid]; - ret_val = guest_get_user_pages(d, vaddr, len, cpid, pid); - - if (!ret_val) { - // restart the engine - if (d->en_avx) - d->fpga_cnfg_avx->ctrl[0] = FPGA_CNFG_CTRL_IRQ_RESTART; - else - d->fpga_cnfg->ctrl = FPGA_CNFG_CTRL_IRQ_RESTART; - } - else { - dbg_info("pages could not be obtained\n"); - } - - // unlock - spin_unlock_irqrestore(&(d->lock), flags); - - return IRQ_HANDLED; -} \ No newline at end of file diff --git a/driver-guest/guest_irq.h b/driver-guest/guest_irq.h deleted file mode 100644 index a0c3f90e3..000000000 --- a/driver-guest/guest_irq.h +++ /dev/null @@ -1,36 +0,0 @@ -/** - * Copyright (c) 2021, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __GUEST_IRQ_H__ -#define __GUEST_IRQ_H__ - -#include "guest_dev.h" -#include "guest_mm.h" - -irqreturn_t guest_fpga_tlb_miss_isr(int irq, void *dev_id); - -#endif \ No newline at end of file diff --git a/driver-guest/guest_mm.c b/driver-guest/guest_mm.c deleted file mode 100644 index da72379a6..000000000 --- a/driver-guest/guest_mm.c +++ /dev/null @@ -1,277 +0,0 @@ -#include "guest_mm.h" - -struct hlist_head user_sbuff_map[1 << (USER_HASH_TABLE_ORDER)]; - -/** - * @brief Release all pages that are hold by the device - * d. The param dirtied specifies if the pages should be marked - * dirty before they can be evicted. - * - * @param d vfpga struct - * @param dirtied - * @return int - */ -int guest_put_all_user_pages(struct vfpga *d, int dirtied) -{ - int i, bkt; - struct user_pages *tmp_buff; - - BUG_ON(!d); - - hash_for_each(user_sbuff_map, bkt, tmp_buff, entry) - { - if (dirtied) - { - for (i = 0; i < tmp_buff->n_pages; i++) - SetPageDirty(tmp_buff->hpages[i]); - } - - for (i = 0; i < tmp_buff->n_pages; i++) - { - put_page(tmp_buff->hpages[i]); - } - - kfree(tmp_buff->hpages); - hash_del(&tmp_buff->entry); - } - - // tell hypervisor to flush everything - writeq((uint64_t) dirtied, (void __iomem *)d->pci_resources.bar2 + PUT_ALL_USER_PAGES); - - return 0; -} - -/** - * @brief explictly unmap an existing mapping. - * Takes the vaddr and cpid and unmaps an existing mapping - * from the fpga. It also removes this mapping from the hashtable. - * - * @param d vfpga device - * @param vaddr start address that is to be unmapped - * @param cpid cpid that mapped this address - * @param dirtied mark pages as dirty prior to putting them - * @return int - */ -int guest_put_user_pages(struct vfpga *d, uint64_t vaddr, int32_t cpid, int dirtied) -{ - int i; - struct user_pages *tmp_buff; - struct hypervisor_map_notifier *notifier; - uint64_t notifier_addr; - - BUG_ON(!d); - - /* - Iterate through all possible buckets there the vaddr could be mapped - to. Check if the found the correct entry and if so, remove it. - - The unmapping involves a call to the hypervisor. - */ - hash_for_each_possible(user_sbuff_map, tmp_buff, entry, vaddr) - { - if (tmp_buff->vaddr == vaddr && tmp_buff->cpid == cpid) - { - if (dirtied) - { - for (i = 0; i < tmp_buff->n_pages; i++) - SetPageDirty(tmp_buff->hpages[i]); - } - - for (i = 0; i < tmp_buff->n_pages; i++) - { - put_page(tmp_buff->hpages[i]); - } - - // Notifiy hypervisor of unmap - notifier = kzalloc(sizeof(struct hypervisor_map_notifier), GFP_KERNEL); - if (!notifier) - { - pr_info("failed to allocate memory for the hypervisor notifier"); - return -ENOMEM; - } - - // populate notifier - notifier->gva = vaddr; - notifier->cpid = cpid; - notifier->dirtied = dirtied; - - // notify - notifier_addr = virt_to_phys(notifier); - writeq(notifier_addr, d->pci_resources.bar2 + UNMAP_USER_OFFSET); - - // free - kfree(notifier); - - // Clean up - hash_del(&tmp_buff->entry); - kfree(tmp_buff->hpages); - // kfree(tmp_buff); - } - } - - return 0; -} - -/** - * @brief Pins a user buffer so that it will not be evicted from cache and makes - * it readable to the vfpga by a call to the hypervisor. - * - * @param d vfpga device - * @param start start address - * @param count number of bytes that should be mapped - * @param cpid cpid of the calling process - * @param pid pid of the calling process - * @return int - */ -int guest_get_user_pages(struct vfpga *d, uint64_t start, size_t count, int32_t cpid, pid_t pid) -{ - uint64_t first, last; - uint64_t notifier_addr; - int n_pages; - int ret_val; - int i; - - struct task_struct *curr_task; - struct mm_struct *curr_mm; - struct vm_area_struct *vma_area_init; - int hugepages; - - struct user_pages *user_pg; - struct hypervisor_map_notifier *notifier; - - dbg_info("Getting user pages\n"); - - ret_val = 0; - BUG_ON(!d); - - // get mmu context - curr_task = pid_task(find_vpid(pid), PIDTYPE_PID); - if (!curr_task) - { - dbg_info("failed to get pid\n"); - return -1; - } - dbg_info("pid found %d", pid); - curr_mm = curr_task->mm; - - // Determine if hugepages - vma_area_init = find_vma(curr_mm, start); - hugepages = is_vm_hugetlb_page(vma_area_init); - - // number of pages - first = (start & PAGE_MASK) >> PAGE_SHIFT; - last = ((start + count - 1) & PAGE_MASK) >> PAGE_SHIFT; - n_pages = last - first + 1; - - if (start + count < start) - return -EINVAL; - if (count == 0) - return 0; - - // alloc user_pages - user_pg = kzalloc(sizeof(struct user_pages), GFP_KERNEL); - if (!user_pg) - { - pr_info("Failed to allocate memory\n"); - ret_val = -ENOMEM; - goto err_user_pg; - } - - // alloc hardware pages - user_pg->hpages = kcalloc(n_pages, sizeof(*user_pg->hpages), GFP_KERNEL); - if (!user_pg->hpages) - { - pr_info("Failed to allocate memory\n"); - ret_val = -ENOMEM; - goto err_hpages; - } - - dbg_info("allocated buffer for %d pages, passed size %ld.\n", n_pages, count); - dbg_info("pages=0x%p\n", user_pg->hpages); - dbg_info("first = %llx, last = %llx\n", first, last); - dbg_info("hugepages: %d\n", hugepages); - - // Pin the pages -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 9, 0) - ret_val = get_user_pages_remote(curr_mm, (unsigned long)start, n_pages, 1, user_pg->hpages, NULL, NULL); -#else - ret_val = get_user_pages_remote(curr_task, curr_mm, (unsigned long)start, n_pages, 1, user_pg->hpages, NULL); -#endif - - // It was not possible to pin all pages - if (ret_val < n_pages) - { - pr_info("could not get all user pages, %d\n", ret_val); - goto fail_host_unmap; - } - - // flush data cache for those pages - for (i = 0; i < n_pages; i++) - flush_dcache_page(user_pg->hpages[i]); - - // populte user pages struct - user_pg->vaddr = start; - user_pg->n_pages = n_pages; - user_pg->cpid = cpid; - - // Prepare map notifier - notifier = kzalloc(sizeof(struct hypervisor_map_notifier) + sizeof(uint64_t) * n_pages, GFP_KERNEL); - if (!notifier) - { - pr_info("Could not allocate notifier\n"); - goto err_notifier; - } - - // populate notifier - notifier->gva = start; - notifier->len = count; - notifier->cpid = cpid; - notifier->npages = n_pages; - notifier->is_huge = hugepages; - - /* - Do the first step of the page table walk inside the vm - and pass the guest physical addresses to the hypervisor. - */ - for (i = 0; i < n_pages; i++) - { - notifier->gpas[i] = page_to_phys(user_pg->hpages[i]); - // dbg_info("Notifier gpa %d is set to %llx\n", i, notifier->gpas[i]); - } - - dbg_info("populated notifier with %lld pages\n", notifier->npages); - - /* - Pass physical address to the hypervisor - */ - notifier_addr = virt_to_phys(notifier); - writeq(notifier_addr, d->pci_resources.bar2 + MAP_USER_OFFSET); - - dbg_info("Notified hypervisor with notifier at addr 0x%llx\n", notifier_addr); - - kfree(notifier); - - // Add to the hash table - hash_add(user_sbuff_map, &user_pg->entry, start); - - return 0; - -err_notifier: - for (i = 0; i < n_pages; i++) - { - put_page(user_pg->hpages[i]); - } - kfree(user_pg->hpages); -err_hpages: - kfree(user_pg); -err_user_pg: - return ret_val; -fail_host_unmap: - for (i = 0; i < ret_val; i++) - { - put_page(user_pg->hpages[i]); - } - kfree(user_pg->hpages); - kfree(user_pg); - return -ENOMEM; -} \ No newline at end of file diff --git a/driver-guest/guest_mm.h b/driver-guest/guest_mm.h deleted file mode 100644 index e31f85f7e..000000000 --- a/driver-guest/guest_mm.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef __GUEST_MM_H__ -#define __GUEST_MM_H__ - -#include "guest_dev.h" - -int guest_put_all_user_pages(struct vfpga *d, int dirtied); -int guest_get_user_pages(struct vfpga *d, uint64_t start, size_t count, int32_t cpid, pid_t pid); -int guest_put_user_pages(struct vfpga *d, uint64_t vaddr, int32_t cpid, int dirtied); - -#endif \ No newline at end of file diff --git a/driver-guest/guest_pci.c b/driver-guest/guest_pci.c deleted file mode 100644 index 919ddd9f5..000000000 --- a/driver-guest/guest_pci.c +++ /dev/null @@ -1,226 +0,0 @@ -#include "guest_pci.h" - -dev_t devt; -struct vfpga vfpga; - -/** - * @brief Sets-up the msix interrupts such that the hypervisor can interrupt - * in a case of a page fault on the system. - * - * @param pdev - * @return int - */ -static int register_msix(struct pci_dev *pdev) -{ - int nvecs; - int i; - int ret_val; - - nvecs = NUM_USER_INTERRUPTS; - ret_val = 0; - - for (i = 0; i < nvecs; i++) - { - vfpga.irq_entry[i].entry = i; - } - - /* Enable as many interrupts as possible */ - ret_val = pci_enable_msix_range(pdev, vfpga.irq_entry, 0, nvecs); - if (ret_val < 0) - { - dbg_info("Failed to allocate all msix vectors"); - return ret_val; - } - - /* For now, the guest only needs one interrupt, for the page fault - this will be extended eventaully to support user interrupts*/ - - ret_val = request_irq(vfpga.irq_entry[0].vector, - guest_fpga_tlb_miss_isr, 0, DRV_NAME, &vfpga); - - if (ret_val) - { - dbg_info("could not register irq!\n"); - return ret_val; - } - - return 0; -} - -/** - * @brief Load configuration for the fpga from the hypervisor - * This is done by reading from the READ_CNFG offset. - * - * @param d vfpga struct - */ -static void load_fpga_config(struct vfpga *d) -{ - uint64_t config; - // load from bar2 offset - - config = readq((volatile __iomem void *)d->pci_resources.bar2 + READ_CNFG_OFFSET); - - // set avx enabled - d->en_avx = config & 0x01; -} - -/** - * @brief Called upon the bus picks up the emulated - * pci device. Creates chardevs, claims resources - * and maps the BARs. - * - * @param pdev - * @param id - * @return int - */ -int guest_probe(struct pci_dev *pdev, const struct pci_device_id *id) -{ - int ret_val; - - ret_val = 0; - vfpga.pdev = pdev; - dbg_info("probed driver\n"); - - // Alloc char region - ret_val = alloc_chrdev_region(&devt, 0, 1, "coyote-guest"); - if (ret_val) - { - dbg_info("failed to allocate chrdev region\n"); - goto err; - } - - /* Init the chardev */ - cdev_init(&vfpga.cdev, &fops); - ret_val = cdev_add(&vfpga.cdev, devt, 1); - if (ret_val) - { - dbg_info("Failed to add chrdev\n"); - goto err_cdev_add; - } - - /* Enable the pci device */ - ret_val = pci_enable_device(pdev); - if (ret_val) - { - dbg_info("Failed to enable pci dev\n"); - goto err_pci_enable; - } - - /* Allocate all regions of the pci device */ - ret_val = pci_request_regions(pdev, "coyote-guest-drv"); - if (ret_val) - { - dbg_info("failed to request regions"); - goto err_pci_request_regions; - } - - // This device is allowed to master the bus - pci_set_master(pdev); - - dbg_info("Successfully requested resources\n"); - - /* Requesting all bars and store information about the bars*/ - vfpga.pci_resources.bar0 = pci_iomap(pdev, 0, pci_resource_len(pdev, 0)); - vfpga.pci_resources.bar2 = pci_iomap(pdev, 2, pci_resource_len(pdev, 2)); - vfpga.pci_resources.bar4 = pci_iomap(pdev, 4, pci_resource_len(pdev, 4)); - - vfpga.pci_resources.bar0_start = pci_resource_start(pdev, 0); - vfpga.pci_resources.bar0_end = pci_resource_end(pdev, 0); - - vfpga.pci_resources.bar2_start = pci_resource_start(pdev, 2); - vfpga.pci_resources.bar2_end = pci_resource_end(pdev, 2); - - vfpga.pci_resources.bar4_start = pci_resource_start(pdev, 4); - vfpga.pci_resources.bar4_end = pci_resource_end(pdev, 4); - - dbg_info("Loaded BAR 0, 2 and 4 into the driver with sizes\nBAR0: %llx\nBAR2: %llx\nBAR4: %llx\n", - pci_resource_len(pdev, 0), - pci_resource_len(pdev, 2), - pci_resource_len(pdev, 4)); - - /* CTRL is BAR0 and AVX-CTRL is BAR4 */ - vfpga.fpga_phys_addr_ctrl = vfpga.pci_resources.bar0_start; - vfpga.fpga_phys_addr_ctrl_avx = vfpga.pci_resources.bar4_start; - - /* Map the CTRL registers to allow the access from the kernel */ - vfpga.fpga_cnfg = ioremap(vfpga.fpga_phys_addr_ctrl + FPGA_CTRL_CNFG_OFFS, FPGA_CTRL_CNFG_SIZE); - vfpga.fpga_cnfg_avx = ioremap(vfpga.fpga_phys_addr_ctrl_avx, FPGA_CTRL_CNFG_AVX_SIZE); - - /* Enable MSIX interrupts */ - ret_val = register_msix(pdev); - if (ret_val) - { - dbg_info("Failed to register interrupts\n"); - goto err_interrupt; - } - - /* Load config from hypervisor */ - load_fpga_config(&vfpga); - - // Init pid array - vfpga.pid_array = vcalloc(N_CPID_MAX, sizeof(pid_t)); - - // Init locks - spin_lock_init(&vfpga.cpid_lock); - spin_lock_init(&vfpga.lock); - - /* Create kernel device */ - vfpga.dev = device_create(guest_class, NULL, devt, NULL, "fpga0"); - if (IS_ERR_OR_NULL(vfpga.dev)) - { - dbg_info("Failed to create device\n"); - ret_val = -1; - goto err_device_create; - } - - dbg_info("created coyote device\n"); - - return 0; - -err_device_create: - pci_free_irq_vectors(pdev); - pci_disable_msix(pdev); -err_interrupt: - pci_iounmap(pdev, (void __iomem *)vfpga.pci_resources.bar0); - pci_iounmap(pdev, (void __iomem *)vfpga.pci_resources.bar2); - pci_iounmap(pdev, (void __iomem *)vfpga.pci_resources.bar4); - vfpga.pci_resources.bar0 = NULL; - vfpga.pci_resources.bar2 = NULL; - vfpga.pci_resources.bar4 = NULL; - pci_release_regions(pdev); -err_pci_request_regions: - pci_disable_device(pdev); -err_pci_enable: - cdev_del(&vfpga.cdev); -err_cdev_add: - unregister_chrdev_region(devt, 1); -err: - return ret_val; -} - -/** - * @brief Called on deletion of the device. - * Frees resources and unmaps the bar regions. - * - * @param pdev - */ -void guest_remove(struct pci_dev *pdev) -{ - // Destory device - device_destroy(guest_class, devt); - - // Unmap pci regions - pci_iounmap(pdev, (void __iomem *)vfpga.pci_resources.bar0); - pci_iounmap(pdev, (void __iomem *)vfpga.pci_resources.bar2); - pci_iounmap(pdev, (void __iomem *)vfpga.pci_resources.bar4); - - /* Release regions */ - pci_release_regions(pdev); - - // Disable device - free_irq(vfpga.irq_entry[0].vector, &vfpga); - pci_disable_msix(pdev); - pci_disable_device(pdev); - cdev_del(&vfpga.cdev); - unregister_chrdev_region(devt, 1); -} \ No newline at end of file diff --git a/driver-guest/guest_pci.h b/driver-guest/guest_pci.h deleted file mode 100644 index 35636dd82..000000000 --- a/driver-guest/guest_pci.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef __GUEST_PCI_H__ -#define __GUEST_PCI_H__ - -#include "guest_dev.h" -#include "guest_irq.h" - -int guest_probe(struct pci_dev *pdev, const struct pci_device_id *id); -void guest_remove(struct pci_dev *pdev); - -#endif \ No newline at end of file diff --git a/driver-guest/setup.sh b/driver-guest/setup.sh deleted file mode 100755 index 1a511587a..000000000 --- a/driver-guest/setup.sh +++ /dev/null @@ -1,5 +0,0 @@ -cd guest/guest-driver -make -sudo insmod coyote-guest.ko -echo 100 | sudo tee /sys/devices/system/node/node0/hugepages/hugepages-2048kB/nr_hugepages -cd diff --git a/driver-guest/test/Makefile b/driver-guest/test/Makefile deleted file mode 100644 index a357e9ed5..000000000 --- a/driver-guest/test/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -.PHONY = run clean - -SRCS := $(wildcard *.c) -OBJS := $(SRCS:%.c=%.o) - -LINKERFLAGS = -lm - -%.o: %.c - $(CC) -c $< - -%: %.o - $(CC) $< -o $@ - -run: test - ./test - -clean: - rm -rvf *.o test test2 diff --git a/driver-guest/test/bench_huge.c b/driver-guest/test/bench_huge.c deleted file mode 100644 index 362ee37ba..000000000 --- a/driver-guest/test/bench_huge.c +++ /dev/null @@ -1,165 +0,0 @@ -#include "test.h" -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -static const char *filename = "/dev/coyote-dev-0"; -static const int remote_pages = 16; -static const size_t native_size = remote_pages*(1 << 21); -static const uint64_t iterations = 10; - -void test_native_lat(int fd, int cpid, uint64_t iterations) -{ - if (iterations * 8 >= native_size) - { - printf("Aborted %s, too many iterations for chosen pages\n", __func__); - return; - } - - int ret_val = 0; - uint64_t tmp[64]; - size_t len = native_size; - volatile uint64_t *buffer = malloc(len); - uint64_t *data = calloc(1, len); - - tmp[0] = (uint64_t)buffer; - tmp[1] = len; - tmp[2] = cpid; - - ret_val = ioctl(fd, IOCTL_MAP_USER, tmp); - if (ret_val) - { - printf("Failed to map user buffer: %d\n", ret_val); - return; - } - - printf("--- NATIVE BENCHMARKS ---\n"); - uint64_t start = _rdtsc(); - for (uint64_t i = 0; i < iterations; i++) - { - memcpy((void *) buffer, data, len); - } - uint64_t end = _rdtsc(); - printf("Average write latency of %lu runs: %lu\n", iterations, (end - start) * 8 / (iterations * len)); - - start = _rdtsc(); - for (uint64_t i = 0; i < iterations; i++) - { - memcpy(data, (void *) buffer, len); - } - end = _rdtsc(); - printf("Average read latency of %lu runs: %lu\n", iterations, (end - start) * 8 / (iterations * len)); - - tmp[0] = (uint64_t)buffer; - tmp[1] = cpid; - ret_val = ioctl(fd, IOCTL_UNMAP_USER, tmp); - if (ret_val) - { - printf("Failed to unmap buffer!\n"); - } - - free((void *) buffer); - free((void *) data); -} - -void test_legacy_lat(int fd, int cpid, uint64_t iterations) -{ - uint64_t tmp[64]; - int ret_val; - - if (iterations * 8 >= remote_pages * LTLB_PAGE_SIZE) - { - printf("Aborted %s, too many iterations for chosen pages\n", __func__); - } - - tmp[0] = remote_pages; - tmp[1] = cpid; - - ret_val = ioctl(fd, IOCTL_ALLOC_HOST_USER_MEM, tmp); - if (ret_val) - { - printf("failed to allocate memory\n"); - return; - } - - uint64_t *buff = mmap(NULL, (remote_pages + 1) * LTLB_PAGE_SIZE, PROT_READ | PROT_WRITE, - MAP_SHARED, fd, MMAP_BUFF << 12); - if (buff == (void *)(-1)) - { - printf("failed to map memory\n"); - return; - } - void *buff_old = buff; - buff = (uint64_t *)((((uint64_t)buff + LTLB_PAGE_SIZE - 1) >> LTLB_PAGE_SHIFT) << LTLB_PAGE_SHIFT); - - printf("--- LEGACY BENCHMARKS ---\n"); - - uint64_t start = _rdtsc(); - for (uint64_t i = 0; i < iterations; i++) - { - *(buff + i) = i; - } - uint64_t end = _rdtsc(); - printf("Average write latency of %lu runs: %lu\n", iterations, (end - start) / iterations); - - start = _rdtsc(); - for (uint64_t i = 0; i < iterations; i++) - { - uint64_t val = *(buff + i); - } - end = _rdtsc(); - printf("Average read latency of %lu runs: %lu\n", iterations, (end - start) / iterations); - - munmap(buff_old, (remote_pages + 1) * LTLB_PAGE_SIZE); - - tmp[0] = (uint64_t) buff; - tmp[1] = cpid; - ret_val = ioctl(fd, IOCTL_FREE_HOST_USER_MEM, tmp); - if (ret_val) - { - printf("Failed to free buffer\n"); - } - - return; -} - -int main() -{ - int fd = open(filename, O_RDWR); - uint64_t tmp[64]; - int ret_val = 0; - - if (fd < 0) - { - printf("Failed to open device file\n"); - return -1; - } - - pid_t pid = getpid(); - tmp[0] = pid; - ret_val = ioctl(fd, IOCTL_REGISTER_PID, tmp); - if (ret_val) - { - printf("Failed to register pid\n"); - goto err; - } - - int32_t cpid = (int32_t)tmp[1]; - printf("registered with cpid %d, running benchmarks...\n", cpid); - - test_native_lat(fd, cpid, iterations); - test_legacy_lat(fd, cpid, iterations); - - tmp[0] = cpid; - ret_val = ioctl(fd, IOCTL_UNREGISTER_PID, tmp); -err: - close(fd); - return ret_val; -} \ No newline at end of file diff --git a/driver-guest/test/test b/driver-guest/test/test deleted file mode 100644 index c538a522dba3660ca94501211df75f10ec71ed41..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 16344 zcmeHOYiwM_6&^crV)Ar?Q=Eh*mp~8?d1EI|6hMJ>Y$t1!7m1^&K)GD+!@FW1X7_Gl zM?f99MzM^mq$&j}S_O#~N=utoMI?x%PDvA>f+j+0Q?+UnN-A5tj7y74L$=?UnR9*j zvMVaoA8oZ`dC#2hJm$=qnccaM`AW-%b>(Gcg3Bavvmoy7ISTP>LCtDi0r88~VkSNp zi$!7z_{kDea=#*ws&b}0pH^yo5-8c#P^AF9T)~1VM@W?Hij`}0158Dg(j>bIs%qX# zEp5k?K@g>TSmo_L^Fy;1cgB|7N z-z_}MTXlQI#$m6{KU1Avu`C{IU)8WI9;%JUlG(1>uGOn*S2g%DDc^D#0>x$EpXSv1 zP1^j&;CeOt>vVD;)9#Vqq}bZ-gfhnO;^l){`+sf_N#kIhvFt1(xF2B zbcm9t`YimDj>^X#i4#WUboljzsuliR1bA)%(bs?(1#p@#h4d-TLioBO_+3Tt9Yt_| z5qxD4{2AZ|{=MZg0EObbsR(`;xPgCfDFd*?3leXd!7j^;#FAD#wmU33!ggmYBof(V z!s>(&(2`iQqomo30g7H))EK;4}q===0b{u+83EpD{qxYB*D;5`>=~&W^ zhy*zy7c}u!iS-*=*EX5UeGN`+xo@RYU(q1U*0zmiD4Y&=#4>g`-L|nQo=S$>toC>q zZFD43Nga!+R0}GiQ{|XnlkhiLeo{^G^r;Hff~fL3tB%EH(l-!IKEkpKVwceD-KF`T z?f)jGYq{tJPldk^`FqH(2dPJY-!aaESLv5#f^p`nyttwC&fKCXtq~eKE@xf1dtD8? z@M)|JI_kpFL8pwna9(>P+^6xWsB^9ef7FH3I_Gl0h0EV3EqL06t97mf2VFR|!R3$( z=Nyr2$c1A-obs{@pYEVSoO0naTzIKk%0MXtr3{oZP|83l1OGo6`0MON9|wBhsSFHM z{BD^LfxaQTJa;P4d%W@`*~#3>+X0W|mfis}d$Az>C`raf&gF8seUhgQ*4W5tho_Cz z*vK)5r;X6q$WI)eHb7$|PdGene8xuhJ3MW8#zyuyJZ*HwM(%ZZ+Te_hSj;23S{Yrl zknw?k&PUNs@Xvbq?|S%ed-#Vv{Gf;L^YHh3_^g|+f48;&^j(4eHv_$Ijc#dcsUNC; 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- -int main() -{ - int ret_val = 0; - printf("Opening device %s\n", filename); - uint64_t tmp[64]; - - int fd = open(filename, O_RDWR); - if (fd < 0) - { - printf("Failed to open device file\n"); - return -1; - } - - pid_t pid = getpid(); - tmp[0] = pid; - ret_val = ioctl(fd, IOCTL_REGISTER_PID, tmp); - if (ret_val) - { - printf("Failed to register pid\n"); - goto err; - } - - int32_t cpid = (int32_t) tmp[1]; - - printf("Got cpid %d\n", cpid); - - printf("Trying to map regions\n"); - - // Map ctrl - void * user_ctrl = mmap(NULL, FPGA_CTRL_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, MMAP_CTRL << 12); - if (!user_ctrl) - { - printf("Failed to map ctrl region\n"); - } - else - { - printf("Mapped ctrl region\n"); - *((uint64_t *) user_ctrl) = 0; - printf("Wrote test to user ctrl\n"); - ret_val = munmap(user_ctrl, FPGA_CTRL_SIZE); - if (ret_val) - { - printf("Failed to unmap with code %d\n", ret_val); - } - else - { - printf("Unmapped ctrl region\n"); - } - } - - // map cnfg - void * user_cnfg = mmap(NULL, FPGA_CTRL_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, MMAP_CNFG << 12); - if (!user_cnfg) - { - printf("Failed to map ctrl region\n"); - } - else - { - printf("Mapped user cnfg\n"); - *((uint64_t *) user_cnfg) = 0; - printf("Wrote test to user cnfg\n"); - ret_val = munmap(user_cnfg, FPGA_CTRL_SIZE); - if (ret_val) - { - printf("Failed to unmap with code %d\n", ret_val); - } - else - { - printf("Unmapped user confg\n"); - } - } - - // map avx cnfg - void * user_cnfg_avx = mmap(NULL, FPGA_CTRL_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, MMAP_CNFG_AVX << 12); - if (!user_cnfg_avx) - { - printf("Failed to map ctrl region\n"); - } - else - { - printf("Mapped cnfg avx\n"); - *((__m256i *) user_cnfg_avx) = _mm256_set_epi64x(0,0,0,0); - printf("Wrote test to cnfg avx\n"); - ret_val = munmap(user_cnfg_avx, FPGA_CTRL_SIZE); - if (ret_val) - { - printf("Failed to unmap with code %d\n", ret_val); - } - else - { - printf("Unmapped user cnfg\n"); - } - } - - // Test get config - ret_val = ioctl(fd, IOCTL_READ_CNFG, tmp); - if (ret_val) - { - printf("Failed to read config!\n"); - } - else - { - printf("Config is 0x%lx\n", tmp[0]); - if (tmp[0] != 0xdeadbeef) - { - printf("WARNING: Config value differs from test value. Ignore this if running on actual hardware\n"); - } - } - - // TODO: extend this to more test cases - // map 4 pages - size_t len = 1*(1 << 12); - // void *buffer = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS | MAP_HUGETLB, -1, 0); - void *buffer = malloc(len); - if (!buffer) - { - printf("Failed to allocate buffer\n"); - goto err_cpid; - } - tmp[0] = (uint64_t) buffer; - tmp[1] = len; - tmp[2] = cpid; - - ret_val = ioctl(fd, IOCTL_MAP_USER, tmp); - if (ret_val) - { - printf("Failed to allocate with code %d\n", ret_val); - goto err_map; - } - - printf("Mapped user buffer for fpga use\n"); - - tmp[0] = (uint64_t) buffer; - tmp[1] = cpid; - ret_val = ioctl(fd, IOCTL_UNMAP_USER, tmp); - if (ret_val) - { - printf("Failed to unmap with code %d\n", ret_val); - } - else - { - printf("Unmapped user buffer successfully\n"); - } - - - -err_map: - munmap(buffer, len); -err_cpid: - tmp[0] = cpid; - ret_val = ioctl(fd, IOCTL_UNREGISTER_PID, tmp); - if (ret_val) - { - printf("Failed to unreguster cpid\n"); - goto err; - } - - printf("Unregistered cpid %d\n", cpid); - -err: - printf("Closing device file %d\n", fd); - close(fd); - return ret_val; -} \ No newline at end of file diff --git a/driver-guest/test/test.h b/driver-guest/test/test.h deleted file mode 100644 index 278665e27..000000000 --- a/driver-guest/test/test.h +++ /dev/null @@ -1,54 +0,0 @@ -#ifndef __TEST_H__ - -/* MMAP */ -/* MMAP Regions */ -#define MMAP_CTRL 0x0 -#define MMAP_CNFG 0x1 -#define MMAP_CNFG_AVX 0x2 -#define MMAP_WB 0x3 -#define MMAP_BUFF 0x200 -#define MMAP_PR 0x400 -#define FPGA_CTRL_SIZE 256 * 1024 -#define FPGA_CTRL_OFFS 0x100000 -#define FPGA_CTRL_LTLB_SIZE FPGA_CTRL_SIZE / 4 -#define FPGA_CTRL_LTLB_OFFS 0x0 -#define FPGA_CTRL_STLB_SIZE FPGA_CTRL_SIZE / 4 -#define FPGA_CTRL_STLB_OFFS 0x10000 -#define FPGA_CTRL_USER_SIZE FPGA_CTRL_SIZE / 4 -#define FPGA_CTRL_USER_OFFS 0x20000 -#define FPGA_CTRL_CNFG_SIZE FPGA_CTRL_SIZE / 4 -#define FPGA_CTRL_CNFG_OFFS 0x30000 -#define FPGA_CTRL_CNFG_AVX_SIZE 256 * 1024 -#define FPGA_CTRL_CNFG_AVX_OFFS 0x1000000 - -/* IOCTL */ -#define IOCTL_ALLOC_HOST_USER_MEM _IOW('D', 1, unsigned long) // large pages (no hugepage support) -#define IOCTL_FREE_HOST_USER_MEM _IOW('D', 2, unsigned long) -#define IOCTL_ALLOC_HOST_RECONFIG_MEM _IOW('D', 3, unsigned long) // pr pages -#define IOCTL_FREE_HOST_RECONFIG_MEM _IOW('D', 4, unsigned long) -#define IOCTL_MAP_USER _IOW('D', 5, unsigned long) // map -#define IOCTL_UNMAP_USER _IOW('D', 6, unsigned long) -#define IOCTL_REGISTER_PID _IOW('D', 7, unsigned long) // register pid -#define IOCTL_UNREGISTER_PID _IOW('D', 8, unsigned long) -#define IOCTL_RECONFIG_LOAD _IOW('D', 9, unsigned long) // reconfiguration - -#define IOCTL_ARP_LOOKUP _IOW('D', 10, unsigned long) // arp lookup -#define IOCTL_SET_IP_ADDRESS _IOW('D', 11, unsigned long) -#define IOCTL_SET_MAC_ADDRESS _IOW('D', 12, unsigned long) -#define IOCTL_WRITE_CTX _IOW('D', 13, unsigned long) // qp context -#define IOCTL_WRITE_CONN _IOW('D', 14, unsigned long) // qp connection -#define IOCTL_SET_TCP_OFFS _IOW('D', 15, unsigned long) // tcp mem offsets - -#define IOCTL_READ_CNFG _IOR('D', 32, unsigned long) // status cnfg -#define IOCTL_XDMA_STATS _IOR('D', 33, unsigned long) // status xdma -#define IOCTL_NET_STATS _IOR('D', 34, unsigned long) // status network -#define IOCTL_READ_ENG_STATUS _IOR('D', 35, unsigned long) // status engines - -#define IOCTL_NET_DROP _IOW('D', 36, unsigned long) // net dropper - -#define IOCTL_TEST_INTERRUPT _IO('D', 37) - -#define LTLB_PAGE_SHIFT 21 -#define LTLB_PAGE_SIZE (1 << 21) - -#endif \ No newline at end of file diff --git a/driver-guest/test/test2.c b/driver-guest/test/test2.c deleted file mode 100644 index 9d612576d..000000000 --- a/driver-guest/test/test2.c +++ /dev/null @@ -1,72 +0,0 @@ -#include "test.h" - -#include -#include -#include -#include -#include - -#include -#include - -static const char *filename = "/dev/fpga0"; - -int main() -{ - uint64_t tmp[64]; - int ret_val = 0; - int fd = open(filename, O_RDWR); - if (fd < 0) - { - printf("Failed to open file\n"); - return -1; - } - - pid_t pid = getpid(); - tmp[0] = pid; - ret_val = ioctl(fd, IOCTL_REGISTER_PID, tmp); - if (ret_val) - { - printf("Failed to register pid with code %d\n", ret_val); - goto err; - } - - int cpid = tmp[1]; - tmp[0] = 1; - tmp[1] = cpid; - ret_val = ioctl(fd, IOCTL_ALLOC_HOST_USER_MEM, tmp); - if (ret_val) - { - printf("failed to allocate memory with code %d\n", ret_val); - goto err; - } - uint64_t *m = mmap(NULL, (tmp[0] + 1) * (1 << 21), PROT_READ | PROT_WRITE, MAP_SHARED, fd, MMAP_BUFF << 12); - if (m == (void *)(-1)) - { - printf("Failed ot mmap\n"); - goto err; - } - void *m_old = m; - m = (uint64_t *)((((uint64_t)m + LTLB_PAGE_SIZE - 1) >> LTLB_PAGE_SHIFT) << LTLB_PAGE_SHIFT); - - printf("Mapped region @%p of size %lu\n", m, (uint64_t)2 * (1 << 21)); - - // test if read and writes work as expected - for (int i = 0; i < 1000; i++) - { - // printf("Iteration %d\n", i); - *(m + i) = i; - if (*(m + i) != i) - { - printf("ERROR: read does not return written data!\n"); - } - } - - printf("Done with test\n"); - - munmap(m_old, (tmp[0] + 1) * (1 << 21)); - -err: - close(fd); - return ret_val; -} \ No newline at end of file diff --git a/driver-guest/test/test_inter.c b/driver-guest/test/test_inter.c deleted file mode 100644 index 2c4288ede..000000000 --- a/driver-guest/test/test_inter.c +++ /dev/null @@ -1,58 +0,0 @@ -#include -#include -#include -#include -#include - -#include -#include - -#include "test.h" - -static const char *filename = "/dev/fpga0"; - -int main() -{ - int ret_val = 0; - printf("Opening device %s\n", filename); - uint64_t tmp[64]; - - int fd = open(filename, O_RDWR); - if (fd < 0) - { - printf("Failed to open device file\n"); - return -1; - } - - pid_t pid = getpid(); - tmp[0] = pid; - ret_val = ioctl(fd, IOCTL_REGISTER_PID, tmp); - if (ret_val) - { - printf("Failed to register pid\n"); - goto err; - } - - int32_t cpid = (int32_t)tmp[1]; - - printf("Got cpid %d\n", cpid); - - ret_val = ioctl(fd, IOCTL_TEST_INTERRUPT); - if (ret_val) - { - printf("Failed to trigger interrupt\n"); - } - - tmp[0] = cpid; - ret_val = ioctl(fd, IOCTL_UNREGISTER_PID, tmp); - if (ret_val) - { - printf("Failed to unreguster cpid\n"); - goto err; - } - - printf("Unregistered cpid %d\n", cpid); - -err: - return ret_val; -} \ No newline at end of file diff --git a/driver/hypervisor/hypervisor.h b/driver/hypervisor/hypervisor.h deleted file mode 100644 index 777a8d5b1..000000000 --- a/driver/hypervisor/hypervisor.h +++ /dev/null @@ -1,171 +0,0 @@ -/** - * Copyright (c) 2023, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HYPERVISOR_H__ -#define __HYPERVISOR_H__ - -#include "../coyote_dev.h" -#include - -// #define HYPERVISOR_TEST - -#define NUM_INTERRUPTS 1 -#define MAX_VMS 16 - -#define COYOTE_HYPERVISOR_CONFIG_SIZE 0x100 -#define COYOTE_HYPERVISOR_BAR0_SIZE ((uint64_t)FPGA_CTRL_SIZE) -#define COYOTE_HYPERVISOR_BAR2_SIZE ((uint64_t)0x4000) -#define COYOTE_HYPERVISOR_BAR4_SIZE ((uint64_t)FPGA_CTRL_CNFG_AVX_SIZE) -#define COYOTE_HYPERVISOR_BAR0_MASK ~(COYOTE_HYPERVISOR_BAR0_SIZE - 1) -#define COYOTE_HYPERVISOR_BAR2_MASK ~(COYOTE_HYPERVISOR_BAR2_SIZE - 1) -#define COYOTE_HYPERVISOR_BAR4_MASK ~(COYOTE_HYPERVISOR_BAR4_SIZE - 1) -#define COYOTE_HYPERVISOR_PCI_MASK(__size) (~(__size - 1)) - -#define BAR0_INDEX_SHIFT 16 - -#define COYOTE_REGION_OFFSET 32 -#define COYOTE_GET_INDEX(__addr) (__addr >> COYOTE_REGION_OFFSET) -#define COYOTE_INDEX_TO_ADDR(__index) (__index << COYOTE_REGION_OFFSET); -#define HYPERVISOR_OFFSET_MASK (((uint64_t)1 << COYOTE_REGION_OFFSET) - 1) - -/* Offsets into BAR2 */ -#define REGISTER_PID_OFFSET 0x00 -#define UNREGISTER_PID_OFFSET 0x08 -#define MAP_USER_OFFSET 0x10 -#define UNMAP_USER_OFFSET 0x18 -#define READ_CNFG_OFFSET 0x20 -#define PUT_ALL_USER_PAGES 0x28 -#define TEST_INTERRUPT_OFFSET 0x30 - -#define INVALID_CPID 0xffffffffffffffff - -#define HYPERVISOR_HASH_TABLE_ORDER 8 -#define HASH_TABLE_BUCKETS (1 << HYPERVISOR_HASH_TABLE_ORDER) - -#define MAX_USER_BUF_SHIFT 27 -#define MAX_USER_BUF_SIZE (1 << MAX_USER_BUF_SHIFT) - -#define LARGE_TABLE_SHIFT 21 -#define LARGE_TABLE_SIZE (1 << 21) - -#define MSIX_OFFSET 0x40 -#define MSIX_SIZE sizeof(struct msix_cap_header) - -/* PCI-Capability header */ -struct cap_header -{ - uint8_t cap_id; - uint8_t next_pointer; -} __packed; - -/* MSI-X header*/ -struct msix_cap_header -{ - uint8_t cap_id; - uint8_t next_pointer; - uint16_t message_control; - uint32_t table_offset; - uint32_t pba_offset; - uint32_t mua; -} __packed; - -// struct to manage information about a single entry of an interrupt vector -struct msix_interrupt -{ - int eventfd; - struct eventfd_ctx * ctx; - int masked; -}; - -/* PCI config header */ -struct pci_config_space -{ - uint16_t vendor_id; // 0x00 RO - uint16_t device_id; // 0x02 RO - uint16_t command; // 0x04 - uint16_t status; // 0x06 - uint8_t revison_id; // 0x08 RO - uint8_t programming_interface; // 0x09 - uint8_t subclass; // 0x0a - uint8_t class_code; // 0x0b RO - uint8_t cache_line_size; // 0x0c - uint8_t lat_time; // 0x0d - uint8_t header_typer; // 0x0e RO - uint8_t bist; // 0x0f - uint32_t bar0; // 0x10 - uint32_t bar1; // 0x14 - uint32_t bar2; // 0x18 - uint32_t bar3; // 0x1c - uint32_t bar4; // 0x20 - uint32_t bar5; // 0x24 - uint32_t cardbus_pointer; // 0x28 - uint16_t subsys_vendor_id; // 0x2c - uint16_t subsys_id; // 0x2e - uint32_t expansion_rom_base; // 0x30 - uint8_t cap_pointer; // 0x34 - uint8_t reserved[7]; // 0x35 - uint8_t interrupt_line; // 0x3c - uint8_t interrupt_pin; // 0x3d - uint8_t min_gnt; // 0x3e - uint8_t max_lat; // 0x3f - uint8_t cap_section[0xbf]; // 0x40 -} __packed; - -struct hypervisor_map_notifier -{ - uint64_t npages; - uint64_t len; - uint64_t gva; - uint64_t cpid; - uint64_t dirtied; - uint64_t is_huge; - uint64_t gpas[0]; -}; - -/* Mediated vFPGA management data */ -struct m_fpga_dev -{ - struct fpga_dev *fpga; // Parent fpga struct - uint32_t id; - - struct list_head next; // next virtual fpga - struct pci_config_space pci_config; - spinlock_t current_cpid_lock; - uint64_t current_cpid; - struct kvm *kvm; - uint32_t in_use; - struct notifier_block notifier; - - void *msix_table; - struct msix_interrupt *msix_vector; - - struct hlist_head sbuff_map[HASH_TABLE_BUCKETS]; - - spinlock_t lock; -}; - -#endif diff --git a/driver/hypervisor/hypervisor_drv.c b/driver/hypervisor/hypervisor_drv.c deleted file mode 100644 index 6e2ec2875..000000000 --- a/driver/hypervisor/hypervisor_drv.c +++ /dev/null @@ -1,110 +0,0 @@ -/** - * Copyright (c) 2023, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "hypervisor_drv.h" - -/** - * @brief Initalizes the hypervisor and creates - * the mdev types inside the device tree. - * - * @param bd bus_drvdata, initiliazed prior to this call - * @return int 0 if succeeded - */ -int hypervisor_init(struct bus_drvdata *bd) { - struct mdev_parent_ops *ops; - int ret_val; - int i, j; - - BUG_ON(!bd); - - for (i = 0; i < bd->n_fpga_reg; i++) { - - // Get ops for the device - ops = hypervisor_get_ops(&bd->fpga_dev[i]); - if (!ops) { - pr_err ("Failed to get mdev-vfio ops\n"); - goto rollback; - } - - // Allocate vcid chunks - bd->fpga_dev[i].vcid_chunks = vzalloc(sizeof(struct chunk) * MAX_VMS); - BUG_ON(!bd->fpga_dev->vcid_chunks); - - for (j = 1; j < MAX_VMS; j++) - { - bd->fpga_dev[i].vcid_chunks[j].id = j; - bd->fpga_dev[i].vcid_chunks[j-1].next = &bd->fpga_dev->vcid_chunks[j]; - } - - bd->fpga_dev[i].vcid_alloc = bd->fpga_dev->vcid_chunks; - bd->fpga_dev[i].num_free_vcid_chunks = MAX_VMS; - - spin_lock_init(&bd->fpga_dev[i].vcid_lock); - - // Register with mdev - ret_val = mdev_register_device(bd->fpga_dev[i].dev, ops); - if (ret_val) { - pr_err ("Error while registering mdev\n"); - goto rollback; - } - - dbg_info("Registered mdev device %d\n", i); - } - - dbg_info("Hypervisor initialized\n"); - - return 0; - -rollback: - for (i = i - 1; i >= 0; i--) { - mdev_unregister_device(bd->fpga_dev[i].dev); - } - return ret_val; -} - -/** - * @brief tear down code for the hypervisor. Unregisters the mdev - * class and therefore removes the types for the fpgas. - * Might block if there are still mediated devices - * opened and used by vms. - * - * @param bd bus_drvdata, initiliazed prior to this call - * @return int 0 if succeeded - */ -void hypervisor_exit(struct bus_drvdata *bd) { - int i; - - for (i = 0; i < bd->n_fpga_reg; i++) - { - mdev_unregister_device(bd->fpga_dev[i].dev); - } - - dbg_info("Unregistered all mdev devices"); - return; -} - -MODULE_LICENSE("GPL"); \ No newline at end of file diff --git a/driver/hypervisor/hypervisor_drv.h b/driver/hypervisor/hypervisor_drv.h deleted file mode 100644 index f38a25f85..000000000 --- a/driver/hypervisor/hypervisor_drv.h +++ /dev/null @@ -1,37 +0,0 @@ -/** - * Copyright (c) 2023, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HYPERVISOR_INIT_H__ -#define __HYPERVISOR_INIT_H__ - -#include "../coyote_dev.h" -#include "hypervisor_ops.h" - -int hypervisor_init(struct bus_drvdata *bd); -void hypervisor_exit(struct bus_drvdata *bd); - -#endif // hypervisor_init.h \ No newline at end of file diff --git a/driver/hypervisor/hypervisor_interrupts.c b/driver/hypervisor/hypervisor_interrupts.c deleted file mode 100644 index a92ff9223..000000000 --- a/driver/hypervisor/hypervisor_interrupts.c +++ /dev/null @@ -1,331 +0,0 @@ -/** - * Copyright (c) 2023, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "hypervisor_interrupts.h" - -/** - * @brief Set the up msix header. - * This function will place the MSIX capapbility in the pci config space - * to communicate to the guest vm that we this emulated device supports - * MSIX interrupts. The next pointer of the capapbility is set to zero - * and has to be set by the caller if there are more capabilities this - * one should point to. - * - * @param cfg Pointer to the pci config space - * @param offset offset from the the start of the config region where the cap should - * be placed. - * @param regs Number of interrupts that should be supported - */ -void set_up_msix_header(struct pci_config_space *cfg, uint8_t offset, uint16_t regs) -{ - struct msix_cap_header *header; - - BUG_ON(regs > 2048); - - header = (struct msix_cap_header *)((uint8_t *)cfg + offset); - - header->cap_id = 0x11; - // explictly set to null, if this is not the last element, this will be handled by the caller - header->next_pointer = 0x00; - - // message control - header->message_control = (regs - 1) & GENMASK(10, 0); - header->message_control |= (0x0 & GENMASK(14, 11)); - header->message_control |= 0 & BIT(15); - - // message upper address - header->mua = 0x0; - - // table offset - // lower 3 bits are for identfying the bar (BAR2) - header->table_offset = 2 & GENMASK(2, 0); - // The table located at an 0x2000 offset of the BAR2 region - header->table_offset |= 0x2000 & GENMASK(31, 3); - - // pba table - header->pba_offset = 2 & GENMASK(2, 0); - header->pba_offset |= 0x3000 & GENMASK(31, 3); -} - -/** - * @brief Emulating writes to the msix header of the - * pci device. This happens according to the - * pci documentation. - * - * @param cfg pointer to the start of the capability - * @param offset into the capability - * @param val val that is to be written - * @param count number of bytes to write - * @return size_t number of bytes actually written (or error code) - */ -size_t write_to_msix_header(void *cfg, uint8_t offset, uint32_t val, uint8_t count) -{ - struct msix_cap_header *header; - - header = (struct msix_cap_header *)cfg; - switch (offset) - { - case 0x2: // message control - { - if (count != 2) - { - return -EFAULT; - } - - header->message_control = val & BIT(15); - return count; - } - case 0x04: - { - if (count != 4) - { - return -EFAULT; - } - - header->mua = val; - return count; - } - default: - { - return -EFAULT; - } - } -} - -/** - * @brief Unsets all handlers for all interrupts. - * Should only be used in an emulated manner since - * this function is only unsetting internal management structs - * and could lead to problems if it does not match the state of - * the vm. - * - * @param d mediated fpga device - */ - -void msix_unset_all_interrupts(struct m_fpga_dev *d) -{ - int i; - for (i = 0; i < NUM_INTERRUPTS; i++) - { - // Check if interrupt was ever registered - if (d->msix_vector[i].eventfd != -1) - { - // Only put the eventfd context if we got it before - if (!IS_ERR_OR_NULL(d->msix_vector[i].ctx)) - { - eventfd_ctx_put(d->msix_vector[i].ctx); - } - - // Invalidate - d->msix_vector[i].eventfd = -1; - } - } -} - -/** - * @brief Handles the VFIO ioctl call. Have a look at the documentation - * of VFIO for more information about the vfio_irq_set struct, it contains - * framework specific fields. - * - * The following cases are supported: - * -+-------------------------------------------------------------------+----------------------------------+ -| flags | action | -+-------------------------------------------------------------------+----------------------------------+ -| VFIO_IRQ_SET_ACTION_TRIGGER & VFIO_IRQ_SET_DATA_NONE & count == 0 | unset all interrupts | -| VFIO_IRQ_SET_ACTION_TRIGGER & VFIO_IRQ_SET_DATA_EVENTFD | set interrupt with given eventfd | -| VFIO_IRQ_SET_ACTION_MASK || VFIO_IRQ_SET_ACTION_UNMASK | Mask interrupt | -+-------------------------------------------------------------------+----------------------------------+ - * this function should only called from the SET_INTERRUPT vfio ioctl. For more information consult the - * VFIO documentation. - * - * @param d mediated fpga device - * @param irq_set irq_set struct passed from userspace from the vfio ioctl - * @return int error code - */ -int handle_set_irq_msix(struct m_fpga_dev *d, struct vfio_irq_set *irq_set) -{ - int i; - int ret_val; - int start, end; - int mask_val; - - ret_val = 0; - - // Disable all interrupts - if ((irq_set->flags & VFIO_IRQ_SET_ACTION_TRIGGER) && (irq_set->flags & VFIO_IRQ_SET_DATA_NONE) && (irq_set->count == 0)) - { - msix_unset_all_interrupts(d); - } - - // Set eventfd - else if ((irq_set->flags & VFIO_IRQ_SET_ACTION_TRIGGER) && (irq_set->flags & VFIO_IRQ_SET_DATA_EVENTFD)) - { - // start and end allows to only specify a range of interrupts to set - start = irq_set->start; - end = start + irq_set->count; - - for (i = start; i < end; i++) - { - // There is already an interrupt, deregister - if (d->msix_vector[i].eventfd != -1 && !IS_ERR_OR_NULL(d->msix_vector[i].ctx)) - { - eventfd_ctx_put(d->msix_vector[i].ctx); - } - - // Register the interrupt and get the eventfd context - d->msix_vector[i].eventfd = irq_set->data[i - start]; - d->msix_vector[i].ctx = eventfd_ctx_fdget(irq_set->data[i - start]); - if (IS_ERR_OR_NULL(d->msix_vector[i].ctx)) - { - dbg_info("Failed to get eventfd ctx, fd: %d, ctx: %p", d->msix_vector[i].eventfd, d->msix_vector[i].ctx); - } - dbg_info("Set interrupt %d to %d, ctx: %p\n", i, irq_set->data[i - start], d->msix_vector[i].ctx); - } - } - - // Mask interrupts - else if ((irq_set->flags & VFIO_IRQ_SET_ACTION_MASK) || (irq_set->flags & VFIO_IRQ_SET_ACTION_UNMASK)) - { - mask_val = (irq_set->flags & VFIO_IRQ_SET_ACTION_MASK) ? 1 : 0; - // start and end allow to mask a range of interrupts - start = irq_set->start; - end = start + irq_set->count; - - // If data none is set, then all interrupts should be set accordingly to the - // mask or unmask flask - if (irq_set->flags & VFIO_IRQ_SET_DATA_NONE) - { - for (i = start; i < end; i++) - { - d->msix_vector[i].masked = mask_val; - dbg_info("Set %d to %s\n", i, (mask_val ? "masked" : "unmasked")); - } - } - // Else, we have a bool array and the interrupts should be masked based on the - // values in this array. - else - { - for (i = start; i < end; i++) - { - if (irq_set->data[i - start]) - { - d->msix_vector[i].masked = mask_val; - dbg_info("Set %d to %s\n", i, (mask_val ? "masked" : "unmasked")); - } - } - } - } - - else - { - dbg_info("Invalid args\n"); - return -EINVAL; - } - - return ret_val; -} - -/** - * @brief forwards an interrupt to the vm. Uses the eventfd context - * stored in the passed argument. This function should only - * be called when currently handling an interrupt! - * - * @param inter msix interrupt storage. - * @return uint64_t eventfd_signal value. Can be discarded for our use. - */ -inline uint64_t fire_interrupt(struct msix_interrupt *inter) -{ - if (IS_ERR_OR_NULL(inter->ctx)) - { - pr_info("Failed ot get context for eventfd %d", inter->eventfd); - return -1; - } - - // dbg_info("Firing interrupt!\n"); - return eventfd_signal(inter->ctx, 0); -} - -/** - * @brief Hypervisor version of the tlb miss interrupt - * service routine. This function uses the same registers from the - * fpga to read the faulting address. Instead of handling the page fault - * it is forwarded to the vm to be handled there. This is because - * the fault address will be a guest virtual address and cannot be - * resolved from the hypervisor. - * - * @param irq interrupt request number - * @param dev_id pointer to device, given then registered the interrupt - * @return irqreturn_t - */ -irqreturn_t hypervisor_tlb_miss_isr(int irq, void *dev_id) -{ - struct m_fpga_dev *md; - unsigned long flags; - int32_t cpid; - struct fpga_dev *d; - struct bus_drvdata *pd; - uint64_t tmp; - - dbg_info("(irq=%d) page fault ISR\n", irq); - BUG_ON(!dev_id); - - d = (struct fpga_dev *)dev_id; - BUG_ON(!d); - - pd = d->pd; - BUG_ON(!pd); - - // lock - spin_lock_irqsave(&(d->lock), flags); - - // read page fault - // tmp cointains the cpid. - if (pd->en_avx) - { - tmp = d->fpga_cnfg_avx->len_miss; - cpid = (int32_t)HIGH_32(tmp); - } - else - { - tmp = d->fpga_cnfg->len_miss; - cpid = (int32_t)HIGH_32(tmp); - } - - // Get the medaited device by looking up the cpid - md = d->vdevs[cpid]; - BUG_ON(!md); - - // Fire interrupt in vm - fire_interrupt(&md->msix_vector[0]); - // dbg_info("Interrupt forwarded to vm!\n"); - - // unlock - spin_unlock_irqrestore(&(d->lock), flags); - - return IRQ_HANDLED; -} \ No newline at end of file diff --git a/driver/hypervisor/hypervisor_interrupts.h b/driver/hypervisor/hypervisor_interrupts.h deleted file mode 100644 index b96f5d28d..000000000 --- a/driver/hypervisor/hypervisor_interrupts.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * Copyright (c) 2023, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HYPERVISOR_INTERRUPTS_H__ -#define __HYPERVISOR_INTERRUPTS_H__ - -#include "../coyote_dev.h" - -/* MSIX header set up */ -void set_up_msix_header(struct pci_config_space *cfg, uint8_t offset, uint16_t regs); -size_t write_to_msix_header(void *cfg, uint8_t offset, uint32_t val, uint8_t count); - -/* MSIX management */ -void msix_unset_all_interrupts(struct m_fpga_dev *d); -int handle_set_irq_msix(struct m_fpga_dev *d, struct vfio_irq_set *irq_set); -uint64_t fire_interrupt(struct msix_interrupt *inter); -irqreturn_t hypervisor_tlb_miss_isr(int irq, void *dev_id); - -#endif \ No newline at end of file diff --git a/driver/hypervisor/hypervisor_mmu.c b/driver/hypervisor/hypervisor_mmu.c deleted file mode 100644 index 9e2824c90..000000000 --- a/driver/hypervisor/hypervisor_mmu.c +++ /dev/null @@ -1,546 +0,0 @@ -/** - * Copyright (c) 2023, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "hypervisor_mmu.h" - -/** - * @brief Pin user pages allocated in a vm. - * This is a modified version to work on the notifier that is passed - * down from the vm. - * - * The function reads the notifier and pins the pages from the vm. - * The notifier contains gpa addresses. So first the function performs - * a page table walk from guest physical address (gpa) to host virtual address (hva). - * We use the hva to pin the corresponding physical pages. - * - * After this step, this function will install mappings on the fpga TLB that correspond - * to the virtual address given in the notifier. If the function uses the - * huge table TLB or the small table TLB depends on the notifier. This information - * is passed down from the hypervisor. This is because if the vm runs with - * huge pages all pages inside the vm are seen as huge pages by the hypervisor - * so we have to pass through the intent on the user with the hypervisor. - * - * In a last step, we actual fire the mapping to the fpga. - * - * @param d mediated dev - * @param notifier notifier from the vm, already copied into the kernel - * @return int 0 if successfull - */ -int hypervisor_tlb_get_user_pages(struct m_fpga_dev *d, struct hypervisor_map_notifier *notifier) -{ - int ret_val, i, j; - struct fpga_dev *fd; - struct bus_drvdata *pd; - struct mm_struct *curr_mm; - struct task_struct *curr_task; - struct kvm *kvm; - pid_t pid; - uint64_t first, last; - uint64_t curr_vaddr, last_vaddr, vaddr_tmp, gva; - int n_pages, n_pages_huge; - int hugepages; - struct user_pages *user_pg; - uint64_t *hpages_phys, *map_array; - uint64_t count; - uint64_t *kvm_hvas; - - ret_val = 0; - - BUG_ON(!d); - fd = d->fpga; - BUG_ON(!fd); - pd = fd->pd; - BUG_ON(!pd); - kvm = d->kvm; - BUG_ON(!kvm); - BUG_ON(!notifier); - BUG_ON(notifier->npages == 0); - - // number of pages - n_pages = notifier->npages; - gva = notifier->gva; - dbg_info("Going to pin %d pages for gva %llx\n", n_pages, gva); - - // Get mmu context from kvm process - curr_mm = kvm->mm; - pid = kvm->userspace_pid; - curr_task = pid_task(find_vpid(pid), PIDTYPE_PID); - - // get first host virtual address in kvm space - kvm_hvas = kcalloc(notifier->npages, sizeof(uint64_t), GFP_KERNEL); - if (!kvm_hvas) - { - goto err_hvas; - } - - for (i = 0; i < n_pages; i++) - { - kvm_hvas[i] = gfn_to_hva(kvm, gpa_to_gfn(notifier->gpas[i])); - } - count = notifier->len; - - // hugepages support passed from vm - hugepages = (int) notifier->is_huge; - - if (hugepages) - { - if (n_pages > MAX_N_MAP_HUGE_PAGES) - n_pages = MAX_N_MAP_HUGE_PAGES; - } - else - { - if (n_pages > MAX_N_MAP_PAGES) - n_pages = MAX_N_MAP_PAGES; - } - - // overflow check - if (gva + count < gva) - return -EINVAL; - if (count == 0) - return 0; - - // allocate management structs - user_pg = kzalloc(sizeof(struct user_pages), GFP_KERNEL); - if (!user_pg) - { - ret_val = -ENOMEM; - goto err_user_pg; - } - - user_pg->hpages = kcalloc(n_pages, sizeof(struct page *), GFP_KERNEL); - if (!user_pg->hpages) - { - ret_val = -ENOMEM; - goto err_hpages; - } - - // Pin all pages obtained from the vm - for (i = 0; i < n_pages; i++) - { - // pin pages of the kvm -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 9, 0) - ret_val = get_user_pages_remote(curr_mm, (unsigned long)kvm_hvas[i], 1, 1, user_pg->hpages + i, NULL, NULL); -#else - ret_val = get_user_pages_remote(curr_task, curr_mm, (unsigned long)kvm_hvas[i], n_pages, 1, user_pg->hpages + i, NULL); -#endif - if (ret_val != 1 || !user_pg->hpages[i]) - { - pr_info("%s.%d: Failed to pin all pages, failed to map %d with ret_val %d", __func__, __LINE__, i, ret_val); - goto err_pin_pages; - } - // dbg_info("pinned page hpa: %llx\n", page_to_phys(user_pg->hpages[i])); - } - - dbg_info("Pinned pages\n"); - - // Reset ret_val - ret_val = 0; - - // flush cache - for (i = 0; i < n_pages; i++) - { - flush_dcache_page(user_pg->hpages[i]); - } - - // populate map entry - user_pg->vaddr = gva; - user_pg->n_hpages = n_pages; - user_pg->huge = hugepages; - - dbg_info("mapping vaddr %llx, cpid %llu, hugepages %llu\n", gva, notifier->cpid, notifier->is_huge); - - vaddr_tmp = gva; - - if (hugepages) // For hugepages - { - // Shift page numbers to work on huge pages - first = (gva & pd->ltlb_order->page_mask) >> pd->ltlb_order->page_shift; - last = ((gva + count - 1) & pd->ltlb_order->page_mask) >> pd->ltlb_order->page_shift; - n_pages_huge = last - first + 1; - user_pg->n_pages = n_pages_huge; - - // allocate pages array - hpages_phys = kzalloc(n_pages_huge * sizeof(uint64_t), GFP_KERNEL); - if (!hpages_phys) - { - ret_val = -ENOMEM; - goto err_phys_pages; - } - - j = 0; - curr_vaddr = gva; - last_vaddr = -1; - - // Get the hpa for the huge pages - for (i = 0; i < n_pages; i++) - { - // Only store an entry if we encounter a new huge page - if (((curr_vaddr & pd->ltlb_order->page_mask) >> pd->ltlb_order->page_shift) != - ((last_vaddr & pd->ltlb_order->page_mask) >> pd->ltlb_order->page_shift)) - { - hpages_phys[j] = page_to_phys(user_pg->hpages[i]) & pd->ltlb_order->page_mask; - last_vaddr = curr_vaddr; - j++; - } - curr_vaddr += PAGE_SIZE; - } - - // If we have memory attached on the card we want to allocate - // the same amount of memory on the card - if (pd->en_mem) - { - // Allocate memory - user_pg->cpages = kzalloc(n_pages_huge * sizeof(uint64_t), GFP_KERNEL); - if (!user_pg->cpages) - { - pr_info("Failed to allocate card buffer"); - ret_val = -ENOMEM; - goto err_cpages; - } - - // Alloc 2MB chunks from the card - ret_val = card_alloc(fd, user_pg->cpages, n_pages_huge, LARGE_CHUNK_ALLOC); - if (ret_val) - { - pr_info("Failed to allocate card memory"); - ret_val = -ENOMEM; - goto err_card_mem; - } - dbg_info("card allocated %d hugepages in hypervisor\n", n_pages_huge); - } - - // alloc map array - map_array = kzalloc(n_pages_huge * 2 * sizeof(uint64_t), GFP_KERNEL); - if (!map_array) - { - pr_info("Failed to allocate map buffers\n"); - goto err_map_buffer; - } - - vaddr_tmp = gva; - - // populate map with mappings from guest virtual address - // to host physical addresses - for (i = 0; i < n_pages_huge; i++) - { - tlb_create_map(pd->ltlb_order, - vaddr_tmp, - hpages_phys[i], - (pd->en_mem ? user_pg->cpages[i] : 0), - notifier->cpid, - &map_array[2 * i]); - vaddr_tmp += pd->ltlb_order->page_size; - } - -#ifndef HYPERVISOR_TEST - // Fire the fpga to the fpga - tlb_service_dev(fd, pd->ltlb_order, map_array, n_pages_huge); -#endif - - kfree(map_array); - kfree(hpages_phys); - } - else // For small pages - { - user_pg->n_pages = n_pages; - - // if memory is attached to the card we want to allocate - // the same amount on the card - if (pd->en_mem) - { - // Allocate pages management array - user_pg->cpages = kzalloc(n_pages * sizeof(uint64_t), GFP_KERNEL); - if (!user_pg->cpages) - { - dbg_info("could not allocate card buffer\n"); - ret_val = -ENOMEM; - goto err_cpages; - } - - // Allocate 4KB chunks of card memory - ret_val = card_alloc(fd, user_pg->cpages, n_pages, SMALL_CHUNK_ALLOC); - if (ret_val) - { - dbg_info("could not get all card pages, %d\n", ret_val); - goto err_card_mem; - } - } - - // allocate map array - map_array = (uint64_t *)kzalloc(n_pages * 2 * sizeof(uint64_t), GFP_KERNEL); - if (!map_array) - { - dbg_info("map buffers could not be allocated\n"); - return -ENOMEM; - } - - // populate mappings array with guest virtual address - // to host physical mapping. - for (i = 0; i < n_pages; i++) - { - tlb_create_map(pd->stlb_order, - vaddr_tmp, - page_to_phys(user_pg->hpages[i]), - (pd->en_mem ? user_pg->cpages[i] : 0), - notifier->cpid, &map_array[2 * i]); - vaddr_tmp += pd->stlb_order->page_size; - } - -#ifndef HYPERVISOR_TEST - // fire interrupt to install the mappings on the fpga - tlb_service_dev(fd, pd->stlb_order, map_array, n_pages); -#endif - - // free buffers - kfree(map_array); - kfree(hpages_phys); - } - - // Add entry into the sbuff hash map. This is for - // managment of allocated memory and allows deallocation - // later on. - hash_add(d->sbuff_map, &user_pg->entry, notifier->gva); - - return ret_val; - -err_pin_pages: - for (j = 0; j < i; j++) - { - put_page(user_pg->hpages[j]); - } - - kfree(user_pg->hpages); - kfree(user_pg); - kfree(kvm_hvas); - return -ENOMEM; - -err_map_buffer: - card_free(fd, user_pg->cpages, n_pages_huge, LARGE_CHUNK_ALLOC); -err_card_mem: - kfree(user_pg->cpages); -err_cpages: - kfree(hpages_phys); -err_phys_pages: - for (i = 0; i < user_pg->n_hpages; i++) - { - put_page(user_pg->hpages[i]); - } -err_hpages: - kfree(user_pg); -err_user_pg: - kfree(kvm_hvas); -err_hvas: - return ret_val; -} - -/** - * @brief Unmap an entry described by a - * tmp_buffer. This is the hypervisor version - * of the put user pages. This code is a small refactor of the original - * version since this function contains the code to actually unmap - * a buffer and in turn is used by the put and put all functions. - * - * @param md mediated device - * @param tmp_buffer user pages struct that describes the mapped region - * @param dirtied Indicates if all pages should be marked dirty before putting - * @return int 0 if successfull - */ -static int unmap_entry(struct m_fpga_dev *md, struct user_pages *tmp_buffer, int dirtied) -{ - int i; - struct fpga_dev *d; - struct bus_drvdata *pd; - uint64_t vaddr_tmp, vaddr; - uint64_t *map_array; - int32_t cpid; - struct tlb_order *tlb_order; - - BUG_ON(!md); - d = md->fpga; - BUG_ON(!d); - pd = d->pd; - BUG_ON(!pd); - BUG_ON(!tmp_buffer); - BUG_ON(!(tmp_buffer->hpages)); - - dbg_info("Putting user_pages entry\n"); - - vaddr = tmp_buffer->vaddr; - cpid = tmp_buffer->cpid; - - // If the pages should be dirtied, - // go through all pages and mark them as dirty. - if (dirtied) - { - for (i = 0; i < tmp_buffer->n_hpages; i++) - { - if (tmp_buffer->hpages[i]) - SetPageDirty(tmp_buffer->hpages[i]); - else - dbg_info("entry for page %d is NULL!\n", i); - } - dbg_info("Marked pages as dirty\n"); - } - - // Put all pages that belong to this buffer - // and allow the machine to evict them from memory - // if it desires to do so. - for (i = 0; i < tmp_buffer->n_hpages; i++) - { - // dbg_info("Putting page %d...\n", i); - if (tmp_buffer->hpages[i]) - put_page(tmp_buffer->hpages[i]); - else - dbg_info("entry for page %d is NULL!\n", i); - } - - // release card pages - if (pd->en_mem) - { - card_free(d, tmp_buffer->cpages, tmp_buffer->n_pages, - tmp_buffer->huge ? LARGE_CHUNK_ALLOC : SMALL_CHUNK_ALLOC); - } - - // - // Unmap from the TLB - // - vaddr_tmp = vaddr; - - // alloc map array - map_array = (uint64_t *)kzalloc(tmp_buffer->n_pages * 2 * sizeof(uint64_t), GFP_KERNEL); - if (!map_array) - { - dbg_info("map buffers could not be allocated\n"); - return -ENOMEM; - } - - tlb_order = tmp_buffer->huge ? pd->ltlb_order : pd->stlb_order; - - for (i = 0; i < tmp_buffer->n_pages; i++) - { - // This code works for huge and small pages and therefore - // there is no need here to seperate the code for the two cases. - // Create unmap entries in the map array. - tlb_create_unmap(tlb_order, vaddr_tmp, cpid, &map_array[2 * i]); - vaddr_tmp += tlb_order->page_size; - } -#ifndef HYPERVISOR_TEST - // Fire to actually remove the mappings from the tlb. - tlb_service_dev(d, tlb_order, map_array, tmp_buffer->n_pages); -#endif - kfree(map_array); - - dbg_info("Successfully put user pages at gva %llx consisting of %llu pages for cpid %d\n", - tmp_buffer->vaddr, tmp_buffer->n_hpages, tmp_buffer->cpid); - return 0; -} - -/** - * @brief Put all card and kernel pages and therefore allow evicitions, - * as described by the notifier. The notifier contains the vaddr of the - * region that should be put. This function searches the hash table - * for a corresponding mapping and uses the unmap_entry function - * to unmap the corresponding buffer. Afterwards it removes - * the mapping from the hashtable. - * - * @param md mediated device - * @param notifier notifier passed from the vm, copied into kernelspace - * @return int 0 if successfull - */ -int hypervisor_tlb_put_user_pages(struct m_fpga_dev *md, struct hypervisor_map_notifier *notifier) -{ - struct user_pages *tmp_buff; - struct fpga_dev *d; - struct bus_drvdata *pd; - - uint64_t vaddr; - uint64_t dirtied; - int32_t cpid; - - BUG_ON(!md); - d = md->fpga; - BUG_ON(!d); - pd = d->pd; - - BUG_ON(!notifier); - vaddr = notifier->gva; - dirtied = notifier->dirtied; - cpid = notifier->cpid; - - // Find all user mappings that map to the same bucket as - // vaddr. - hash_for_each_possible(md->sbuff_map, tmp_buff, entry, vaddr) - { - // Check if it is the correct entry - if (tmp_buff->vaddr == vaddr && tmp_buff->cpid == cpid) - { - // unmap from TLB - unmap_entry(md, tmp_buff, dirtied); - // delete from hashtable - hash_del(&tmp_buff->entry); - // free memory - kfree(tmp_buff->hpages); - kfree(tmp_buff); - } - } - return 0; -} - -/** - * @brief Similar to hypervisor_tlb_put_user_pages but put all pages - * hold by the device md. - * - * @param md mediated device - * @param dirtied indicates if all pages should be marked dirty before putting - * @return int 0 if successfull - */ -int hypervisor_tlb_put_user_pages_all(struct m_fpga_dev *md, int dirtied) -{ - struct fpga_dev *d; - struct bus_drvdata *pd; - int bkt; - struct user_pages *tmp_buff; - - BUG_ON(!md); - d = md->fpga; - BUG_ON(!d); - pd = d->pd; - BUG_ON(!pd); - - // Iterate through all mappings and unmap all - hash_for_each(md->sbuff_map, bkt, tmp_buff, entry) - { - // unmap from TLB - unmap_entry(md, tmp_buff, dirtied); - // delete from hash table - hash_del(&tmp_buff->entry); - // free memory - kfree(tmp_buff->hpages); - kfree(tmp_buff); - } - return 0; -} \ No newline at end of file diff --git a/driver/hypervisor/hypervisor_mmu.h b/driver/hypervisor/hypervisor_mmu.h deleted file mode 100644 index bc1dc8d3c..000000000 --- a/driver/hypervisor/hypervisor_mmu.h +++ /dev/null @@ -1,39 +0,0 @@ -/** - * Copyright (c) 2023, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HYPERVISOR_MMU_H__ -#define __HYPERVISOR_MMU_H__ - -#include "../coyote_dev.h" -#include "../fpga_mmu.h" -#include "hypervisor.h" - -int hypervisor_tlb_get_user_pages(struct m_fpga_dev *d, struct hypervisor_map_notifier *notifier); -int hypervisor_tlb_put_user_pages(struct m_fpga_dev *md, struct hypervisor_map_notifier *notifier); -int hypervisor_tlb_put_user_pages_all(struct m_fpga_dev *md, int dirtied); - -#endif \ No newline at end of file diff --git a/driver/hypervisor/hypervisor_ops.c b/driver/hypervisor/hypervisor_ops.c deleted file mode 100644 index e60976484..000000000 --- a/driver/hypervisor/hypervisor_ops.c +++ /dev/null @@ -1,1772 +0,0 @@ -/** - * Copyright (c) 2023, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "hypervisor_ops.h" - -/** - * @brief Set the up capability section of the pci config space. - * At the moment this includes the MSIX capability and the PCI express - * endpoint capability which is copied from the actual hardware. - * This of course only happens if we are on PCI platform. - * - * @param cfg - * @param pd - */ -static void set_up_cap_section(struct pci_config_space *cfg, struct bus_drvdata *pd) -{ - struct cap_header *header; - uint8_t offset; - int i; - - // Init at the first position for the cap list - cfg->cap_pointer = MSIX_OFFSET; - // Let the OS know that this device has caps - cfg->status |= BIT(4); - - set_up_msix_header(cfg, MSIX_OFFSET, NUM_INTERRUPTS); - - // Get header - header = (struct cap_header *)((uint8_t *)cfg + MSIX_OFFSET); - - // If we are on a PCI platform, copy the endpoint header - if (cyt_arch == CYT_ARCH_PCI) - { - // Point to the next cap - header->next_pointer = MSIX_OFFSET + MSIX_SIZE; - - // Copy cap struct from pci device - offset = pci_find_capability(pd->pci_dev, PCI_CAP_ID_EXP); - for (i = 0; i < PCI_CAP_PCIX_SIZEOF_V2; i++) - { - pci_read_config_byte(pd->pci_dev, - offset + i, (uint8_t *)cfg + MSIX_OFFSET + MSIX_SIZE + i); - } - - header = (struct cap_header *)((uint8_t *)cfg + MSIX_OFFSET + MSIX_SIZE); - } - header->next_pointer = 0; -} - -/** - * @brief Sets the pci configuration of the mdev - * on creation of the virtual device. The configuration space - * communicates to the guest os that we use 3 64bit bars - * and communicates the size of these bars. Furthermore - * we emulate the the vendor_id 0x0102 and device_id 0x0304. - * TODO: Discuss a change to the illeagal address 0xffff - * for the vendor id. QEMU replaces this illeageal id - * with an free vendor id. However, this might not be the - * case for other emulation solutions. - * - * @param cfg pointer to pci_config_space - */ -static void set_pci_config(struct pci_config_space *cfg, - struct bus_drvdata *pd) -{ - - uint64_t bar0_addr, bar2_addr, bar4_addr; - - // Clear memory - memset(cfg, 0, sizeof(struct pci_config_space)); - - // Device id - cfg->vendor_id = 0x0102; - cfg->device_id = 0x0304; - - // Can control the (virtual) bus - cfg->command = PCI_COMMAND_IO | PCI_COMMAND_MEMORY; - - // No status - cfg->status = 0x0200; - - cfg->revison_id = 0x10; - cfg->programming_interface = 0x00; - cfg->subclass = 0x00; - cfg->class_code = 0xff; - - // Bar0: 64 bit in memory mode - bar0_addr = COYOTE_HYPERVISOR_BAR0_MASK | - PCI_BASE_ADDRESS_MEM_TYPE_64 | - PCI_BASE_ADDRESS_SPACE_MEMORY; - - if (COYOTE_HYPERVISOR_BAR0_SIZE) - { - cfg->bar0 = bar0_addr; - cfg->bar1 = (uint32_t)(bar0_addr >> 32); - } - - // Bar2: 64 bit in memory mode - bar2_addr = COYOTE_HYPERVISOR_BAR2_MASK | - PCI_BASE_ADDRESS_MEM_TYPE_64 | - PCI_BASE_ADDRESS_SPACE_MEMORY; - - if (COYOTE_HYPERVISOR_BAR2_SIZE) - { - cfg->bar2 = (uint32_t)bar2_addr; - cfg->bar3 = (uint32_t)(bar2_addr >> 32); - } - - // Bar4: 64 bit in memory mode - bar4_addr = COYOTE_HYPERVISOR_BAR4_MASK | - PCI_BASE_ADDRESS_MEM_TYPE_64 | - PCI_BASE_ADDRESS_SPACE_MEMORY; - - if (COYOTE_HYPERVISOR_BAR4_SIZE) - { - cfg->bar4 = (uint32_t)bar4_addr; - cfg->bar5 = (uint32_t)(bar4_addr >> 32); - } - - // Init cap list - set_up_cap_section(cfg, pd); - - // Interrupt pin - cfg->interrupt_pin = 0x01; -} - -/** - * @brief handles create operation for the mediated device - * allocates data structures and does basic initizalization. - * This function should only called from the mdev framework! - * - * @param mdev passed from the vfio_mdev framework - * @return int zero on success - */ -static int hypervisor_vfpga_create(struct mdev_device *mdev) -{ - struct device *dev; - struct bus_drvdata *d; - struct fpga_dev *fpga; - struct m_fpga_dev *m_vfpga; - int i; - int ret_val; - - ret_val = 0; - dbg_info("Create start.\n"); - - // Load parent data to find out - // the fpga region we belong to - BUG_ON(!mdev); - dev = mdev_parent_dev(mdev); - if (!dev) - { - pr_err("Failed to get mdev parent device\n"); - return -EIO; - } - d = dev_get_drvdata(dev); - if (!d) - { - pr_err("Failed to get bus drv data\n"); - return -EIO; - } - - dbg_info("Got info\n"); - - // Get id of parent device by parsing the name - sscanf(dev->kobj.name, "fpga%d", &i); - dbg_info("Create for parent device %d\n", i); - // use the id to get the fpga_dev - fpga = &d->fpga_dev[i]; - - BUG_ON(!fpga); - dbg_info("Got fpga\n"); - - // allocate mangement struct for the new mediated device - m_vfpga = kzalloc(sizeof(struct m_fpga_dev), GFP_KERNEL); - if (!m_vfpga) - { - pr_err("failed to allocate m_vfpga memory\n"); - return -ENOMEM; - } - - m_vfpga->fpga = fpga; - m_vfpga->current_cpid = INVALID_CPID; - - // Get vcid. Unique per fpga region and - // used to make the pid unique - spin_lock(&fpga->vcid_lock); - m_vfpga->id = fpga->vcid_alloc->id; - fpga->vcid_alloc = fpga->vcid_alloc->next; - fpga->num_free_vcid_chunks -= 1; - spin_unlock(&fpga->vcid_lock); - - // Set up pci config - set_pci_config(&m_vfpga->pci_config, d); - - // Init locks - spin_lock_init(&m_vfpga->lock); - spin_lock_init(&m_vfpga->current_cpid_lock); - - // add into the list of virtual fpgas - spin_lock(&fpga->list_lock); - list_add(&m_vfpga->next, &fpga->mdev_list); - spin_unlock(&fpga->list_lock); - - mdev_set_drvdata(mdev, m_vfpga); - - dbg_info("successfully created medaited vfpga device\n"); - - return ret_val; -} - -/** - * @brief Called on deletion of the mediated device. - * Furthermore it frees up the vcid and removes it from - * the list of fpgas. This function should only be called from the - * mdev framework! - * - * @param mdev passed from the mdev framework - * @return int zero on success - */ -static int hypervisor_vfpga_remove(struct mdev_device *mdev) -{ - struct fpga_dev *fpga; - struct m_fpga_dev *m_vfpga; - - m_vfpga = mdev_get_drvdata(mdev); - fpga = m_vfpga->fpga; - - // release vcid - spin_lock(&fpga->vcid_lock); - fpga->vcid_chunks[m_vfpga->id].next = fpga->vcid_alloc; - fpga->vcid_alloc = &fpga->vcid_chunks[m_vfpga->id]; - fpga->num_free_pid_chunks += 1; - spin_unlock(&fpga->vcid_lock); - - // Remove from the list of virtual vFPGAs - spin_lock(&fpga->list_lock); - list_del(&m_vfpga->next); - spin_unlock(&fpga->list_lock); - - // Free memory - kfree(m_vfpga); - - dbg_info("successfully removed mdeiated vfpga device\n"); - - return 0; -} - -/** - * @brief handler function for the vfio kvm notify event. - * Only called by the vfio framework. For example, if we use qemu - * this function is called by qemu to let out module know which - * kvm it is using. This is later needed to do page table walks inside - * this module. - * - * @param nb notifier block from vfio - * @param action what event happend - * @param data payload - * @return int zero on success - */ -int hypervisor_vfio_notifier(struct notifier_block *nb, unsigned long action, void *data) -{ - struct m_fpga_dev *vfpga; - - vfpga = container_of(nb, struct m_fpga_dev, notifier); - - spin_lock(&vfpga->lock); - - // only do something if this is a set kvm event - if (action == VFIO_GROUP_NOTIFY_SET_KVM) - { - vfpga->kvm = data; - dbg_info("kvm set successfully"); - } - - spin_unlock(&vfpga->lock); - - return 0; -} - -/** - * @brief handles the opening of the mediated device file (after creation) - * this happens if the vm boots and therefore the file - * is opened from the hypervisor to emulate the pci device. This function - * does most of the allocation to allow the emulation. - * This includes the MSIX region setup and the registration - * of the kvm notifier. - * - * @param mdev passed from the mdev framework - * @return int zero on success - */ -static int hypervisor_vfpga_open(struct mdev_device *mdev) -{ - struct m_fpga_dev *vfpga; - long unsigned int events; - int ret_val; - int i; - - ret_val = 0; - - // Get virtual vFGPA struct - vfpga = mdev_get_drvdata(mdev); - - spin_lock(&vfpga->lock); - // mediated vfpgas are only inteded for the use by one vm at the time - if (vfpga->in_use) - { - dbg_info("Failed to open vfio device: busy\n"); - spin_unlock(&vfpga->lock); - return -EBUSY; - } - - // Set busy - vfpga->in_use = 1; - spin_unlock(&vfpga->lock); - - // allocate msix table - // TODO: remove this, seems to be handled by QEMU - vfpga->msix_table = kzalloc(2000, GFP_KERNEL); - if (!vfpga->msix_table) - { - dbg_info("Failed to allocate msix tabel\n"); - ret_val = -ENOMEM; - goto err_msix_table; - } - - // allocate array for eventfd fds - vfpga->msix_vector = kzalloc(NUM_INTERRUPTS * sizeof(struct msix_interrupt), GFP_KERNEL); - if (!vfpga->msix_vector) - { - dbg_info("Failed to allocate msix interrupts\n"); - ret_val = -ENOMEM; - goto err_msix_interrupts; - } - - // expliclty invalidate all file descriptors entries - for (i = 0; i < NUM_INTERRUPTS; i++) - { - vfpga->msix_vector[i].eventfd = -1; - } - - // Init memory maps - hash_init(vfpga->sbuff_map); - - /* We know that this is the only thread accessing this device */ - - // Register KVM notifier - events = VFIO_GROUP_NOTIFY_SET_KVM; - vfpga->notifier.notifier_call = hypervisor_vfio_notifier; - ret_val = vfio_register_notifier(mdev_dev(mdev), VFIO_GROUP_NOTIFY, &events, &vfpga->notifier); - if (ret_val) - { - pr_err("notifier registration failed\n"); - } - - dbg_info("successfully opened mediated vfpga\n"); - - return ret_val; - -err_msix_interrupts: - kfree(vfpga->msix_table); -err_msix_table: - return ret_val; -} - -/** - * @brief called when the device file is closed. This happens if the vm shuts down - * removes every state that was associated with the current vm. This includes - * to disable all current interrupts and free all msix data. - * - * @param mdev mdev device in question - */ -static void hypervisor_vfpga_close(struct mdev_device *mdev) -{ - struct m_fpga_dev *vfpga; - int ret_val; - - ret_val = 0; - - // Get virtual vFGPA struct - vfpga = mdev_get_drvdata(mdev); - - spin_lock(&vfpga->lock); - - BUG_ON(!vfpga->in_use); - - // unset all interrupts - msix_unset_all_interrupts(vfpga); - - // Set free - vfpga->in_use = 0; - spin_unlock(&vfpga->lock); - - // free allocated memory - kfree(vfpga->msix_table); - kfree(vfpga->msix_vector); - - // Unregister vfio notifier - ret_val = vfio_unregister_notifier(mdev_dev(mdev), VFIO_GROUP_NOTIFY, &vfpga->notifier); - if (ret_val) - { - dbg_info("Failed to unregister VFIO notifier\n"); - } - - dbg_info("Closed mediated vfpga file\n"); -} - -/** - * @brief General function to access data inside of the vm, - * allows to read and write from the vm that is associated with the vfpga. - * Only works after the device file was opened! - * - * @param vfpga mediated vfpga device - * @param gpa guest physical address - * @param count bytes to read/write - * @param buf source/target buffer - * @param write - * @return ssize_t - */ -static ssize_t hypervisor_access_kvm(struct m_fpga_dev *vfpga, - gpa_t gpa, - size_t count, - void *buf, - int write) -{ - struct kvm *kvm; - int ret_val; - int idx; - - kvm = vfpga->kvm; - BUG_ON(!kvm); - - ret_val = 0; - - dbg_info("Accessing kvm at gpa %llx to %s %lu bytes", gpa, (write ? "write" : "read"), count); - - /* - The function uses the page tables of the vm and - therefore they are not allowed to change during the translation. - Therefore we have to hold the srce lock. - */ - idx = srcu_read_lock(&kvm->srcu); - if (write) - { - ret_val = kvm_write_guest(kvm, gpa, buf, count); - } - else - { - ret_val = kvm_read_guest(kvm, gpa, buf, count); - } - - if (ret_val) - { - pr_info("Failed to %s kvm\n", (write ? "write" : "read")); - } - srcu_read_unlock(&kvm->srcu, idx); - - return ret_val; -} - -/** - * @brief Bar0 access are relayed to the actual hardware for - * calls that would be mmap in a not vm scenario. BAR0 acts as a passthrough - * for this cases and are mmaped in the vm. Therefore this function is - * not used and should not be used since the trap comes at a very high cost - * and should be avoided whenever possible! - * - * @param vfpga mediated vfpga - * @param buf read/write buffer - * @param count bytes to read/write - * @param pos offset into the bar register - * @param write 1 for write - * @return ssize_t bytes read/write - */ -static ssize_t handle_bar0_access(struct m_fpga_dev *vfpga, char __user *buf, - size_t count, loff_t pos, int write) -{ - uint64_t offset; - uint64_t index; - struct fpga_dev *d; - uint64_t tmp[64]; - void __iomem *ioaddr; - int ret_val; - ret_val = 0; - - BUG_ON(!vfpga); - d = vfpga->fpga; - BUG_ON(!d); - - /* - 20 is the shift that is used for the subregions between the not avx and avx - regions. Therefore to differentiate between accesses of this two regions - the fastes way is to compute the value of the upper bits. - */ - index = pos >> 20; - offset = pos & ((1 << 20) - 1); - if (write) - { - dbg_info("Accessing bar0 at addr %#llx and offset %#llx with count %lu at index %llx\n", pos, offset, count, index); - } - - switch (index) - { - case 0x1: - /* - Depending on the offset into the region we want to access at different - mappings. This is happening here. This is one of the reasons why a trap - is not very efficent. - */ - if (offset >= FPGA_CTRL_LTLB_OFFS && offset < FPGA_CTRL_LTLB_SIZE + FPGA_CTRL_LTLB_OFFS) - { - ioaddr = (void __iomem *)vfpga->fpga->fpga_lTlb + (offset - FPGA_CTRL_LTLB_OFFS); - } - else if (offset >= FPGA_CTRL_STLB_OFFS && offset < FPGA_CTRL_STLB_SIZE + FPGA_CTRL_STLB_OFFS) - { - ioaddr = (void __iomem *)vfpga->fpga->fpga_sTlb + (offset - FPGA_CTRL_STLB_OFFS); - } - else if (offset >= FPGA_CTRL_USER_OFFS && offset < FPGA_CTRL_USER_OFFS + FPGA_CTRL_USER_SIZE) - { - ioaddr = (void __iomem *)vfpga->fpga->fpga_user + (offset - FPGA_CTRL_USER_OFFS); - } - else if (offset >= FPGA_CTRL_CNFG_OFFS && offset < FPGA_CTRL_CNFG_OFFS + FPGA_CTRL_CNFG_SIZE) - { - ioaddr = (void __iomem *)vfpga->fpga->fpga_cnfg + (offset - FPGA_CTRL_CNFG_OFFS); - } - else - { - return -EFAULT; - } - break; - case 0x10: - /* - For avx accesses we do not have this problem. However, during testing we found out - that this part is not working. The corresponding avx instrunction cannot - be trapped and therefore if the corresponding region is not mmaped we cannot - use avx. - */ - ioaddr = (void __iomem *)vfpga->fpga->fpga_cnfg_avx + offset; - break; - default: - dbg_info("Access to unspported offset!\n"); - return -EFAULT; - } - - if (write) - dbg_info("%s at ioaddr %p\n", write ? "write" : "read", ioaddr); - - if (write) - dbg_info("tmp addr %p and buf addr %p\n", tmp, buf); - -#ifndef HYPERVISOR_TEST - if (write) - { - // copy from user - ret_val = copy_from_user(tmp, buf, count); - BUG_ON(ret_val); - memcpy_toio(ioaddr, tmp, count); - // write through to hardware - dbg_info("performed write to ioaddr %p of %lu bytes, first 8 bytes %#016llx", ioaddr, count, tmp[0]); - } - else - { - // copy from io to user - memcpy_fromio(tmp, ioaddr, count); - ret_val = copy_to_user(buf, tmp, count); - BUG_ON(ret_val); - } - -#endif - - return count; -} - -/** - * @brief BAR2 is for communication between the hypervisor - * and the guest driver. These are virtualized versions of the IOCTL - * calls in fpga_fops. This function only handles reads from the register. - * Here are control functions trapped and handled according to the - * desired behaviour but in a mediated manner. All these - * calls are made by the guest driver to communicate with the hypervisor. - * The instructions are: - * - * REGISTER_PID: - * Register PID. This is used in combination with a write to REGISTER_PID. - * The read returns a new CPID that can be used by the guest. - * - * READ_CNFG: - * Read through of the the corresponding ioctl call. Returns key - * configuration parameters of the fpga platform. - * - * @param vfpga mediated vfpga - * @param buf read buffer - * @param count bytes to read - * @param pos offset into the register - * @return ssize_t bytes read - */ -static ssize_t handle_bar2_read(struct m_fpga_dev *vfpga, char __user *buf, - size_t count, loff_t pos) -{ - loff_t offset; - int ret_val; - uint64_t tmp[MAX_USER_ARGS]; - struct fpga_dev *d; - struct bus_drvdata *pd; - - BUG_ON(!vfpga); - d = vfpga->fpga; - BUG_ON(!d); - pd = d->pd; - BUG_ON(!pd); - - // The lower 32 bit represent a command that should be executed - offset = pos & HYPERVISOR_OFFSET_MASK; - switch (offset) - { - case REGISTER_PID_OFFSET: - { - spin_lock(&vfpga->current_cpid_lock); - ret_val = copy_to_user(buf, &vfpga->current_cpid, sizeof(&vfpga->current_cpid)); - if (ret_val) - { - pr_err("%s.%u: Failed to read\n", __func__, __LINE__); - spin_unlock(&vfpga->current_cpid_lock); - return -EFAULT; - } - - // Reset cpid - vfpga->current_cpid = INVALID_CPID; - spin_unlock(&vfpga->current_cpid_lock); - - return count; - } - case READ_CNFG_OFFSET: - { - if (!IS_ALIGNED(pos, 8)) - { - dbg_info("READ_CNFG not correctly alligned\n"); - return -EFAULT; - } - - if (count != 8) - { - dbg_info("READ_CNFG not 8 byte read\n"); - return -EFAULT; - } - -#ifdef HYPERVISOR_TEST - tmp[0] = 0xdeadbeef; -#else - tmp[0] = ((uint64_t)pd->n_fpga_chan << 32) | ((uint64_t)pd->n_fpga_reg << 48) | - ((uint64_t)pd->en_avx) | ((uint64_t)pd->en_bypass << 1) | ((uint64_t)pd->en_tlbf << 2) | ((uint64_t)pd->en_wb << 3) | - ((uint64_t)pd->en_strm << 4) | ((uint64_t)pd->en_mem << 5) | ((uint64_t)pd->en_pr << 6) | - ((uint64_t)pd->en_rdma_0 << 16) | ((uint64_t)pd->en_rdma_1 << 17) | ((uint64_t)pd->en_tcp_0 << 18) | ((uint64_t)pd->en_tcp_1 << 19); -#endif - dbg_info("reading config 0x%llx\n", tmp[0]); - - ret_val = copy_to_user(buf, tmp, count); - - if (ret_val) - { - dbg_info("Failed to copy to user\n"); - return -EFAULT; - } - - return count; - } - default: - { - // Not mapped, return no meaningful data - return count; - } - } -} - -/** - * @brief AVX passthrough. this is not implemented for the simple reason, - * that trapping AVX instrunctions does not work at the moment. Therefore if - * this function would be needed it would not work and therefore the user should - * fallback to a bitstream that does not use avx. - * - * @param vfpga - * @param buf - * @param count - * @param pos - * @param is_write - * @return ssize_t - */ -static ssize_t handle_bar4_access(struct m_fpga_dev *vfpga, char __user *buf, - size_t count, loff_t pos, int is_write) -{ - return count; -} - -/** - * @brief Called by the vfpga framework for any access to the virtual pci - * device in the vm. Based on the region accessed the access is handled - * by a special function. Therefore this function acts as a simple - * demultiplexer. - * - * @param mdev mediated vfpga device - * @param buf read buffer - * @param count bytes to read - * @param ppos position, this is determined by VFIO by IOCTL calls to the driver, handled below - * @return ssize_t bytes read - */ -static ssize_t hypervisor_vfpga_read(struct mdev_device *mdev, char __user *buf, - size_t count, loff_t *ppos) -{ - loff_t pos, offset, index; - int ret_val; - struct m_fpga_dev *vfpga; - - pos = *ppos; - offset = pos & HYPERVISOR_OFFSET_MASK; - index = COYOTE_GET_INDEX(pos); - ret_val = 0; - vfpga = mdev_get_drvdata(mdev); - - switch (index) - { - case VFIO_PCI_CONFIG_REGION_INDEX: - { - // dbg_info("Reading pci config at offset %llu, reading %lu bytes\n", offset, count); - if (offset + count > COYOTE_HYPERVISOR_CONFIG_SIZE) - { - pr_err("%s.%u: Out of bound read\n", __func__, __LINE__); - return -EFAULT; - } - - // Read from in memory config - ret_val = copy_to_user(buf, ((char *)&vfpga->pci_config) + offset, count); - if (ret_val) - { - pr_err("%s.%u: Failed to read\n", __func__, __LINE__); - return -EFAULT; - } - - return count; - } - case VFIO_PCI_BAR0_REGION_INDEX: - { - // Check bounds - if (offset + count > COYOTE_HYPERVISOR_BAR0_SIZE) - { - pr_err("%s.%u: Out of bound read\n", __func__, __LINE__); - return -EFAULT; - } - - return handle_bar0_access(vfpga, buf, count, pos, 0); - } - case VFIO_PCI_BAR2_REGION_INDEX: - { - // Check bounds - if (offset + count > COYOTE_HYPERVISOR_BAR2_SIZE) - { - pr_err("%s.%u: Out of bound read\n", __func__, __LINE__); - return -EFAULT; - } - - return handle_bar2_read(vfpga, buf, count, pos); - } - case VFIO_PCI_BAR4_REGION_INDEX: - { - // Check bounds - if (offset + count > COYOTE_HYPERVISOR_BAR4_SIZE) - { - pr_err("%s.%u: Out of bound read\n", __func__, __LINE__); - return -EFAULT; - } - - return handle_bar4_access(vfpga, buf, count, pos, 0); - } - default: - { - // Not a valid region to read - pr_debug("%s.%u: Read to invalid region %lld\n", __func__, __LINE__, index); - return 0; - } - } -} - -/** - * @brief write to a base address register (BAR). Keeps the lowest 4 bits - * at all time, since they contain non writeable bits. - * - * @param bar pointer to BAR - * @param val value to be written - * @param low write to low(1) or high(0) register - */ -static void cfg_bar_write(uint32_t *bar, uint32_t val, int low) -{ - if (low) - { - *bar = (val & GENMASK(31, 4)) | - (*bar & GENMASK(3, 0)); - } - else - { - *bar = val; - } -} - -/** - * @brief Function to handle writes to the PCI config. Not all writes should be permitted - * so this function emulates that should happen if we would wirte to an actual pci device - * TODO: Here is some functionaly missing, but at the moment the relevant subset is implemented - * - * @param fpga mediated vfpga that the wrote is to - * @param buf write buffer - * @param count bytes to write - * @param pos offset into the configuration space - * @return int zero on success - */ -static int handle_pci_cfg_write(struct m_fpga_dev *fpga, char __user *buf, size_t count, loff_t pos) -{ - uint32_t new_val; - int ret_val; - - ret_val = copy_from_user(&new_val, buf, count); - if (ret_val) - { - dbg_info("could not copy new pci cfg value from userspace\n"); - return -EFAULT; - } - - pos = pos & HYPERVISOR_OFFSET_MASK; - - switch (pos) - { - case 0x10: // BAR 0 - if (new_val == GENMASK(31, 0)) - { - cfg_bar_write(&fpga->pci_config.bar0, (uint32_t)(COYOTE_HYPERVISOR_BAR0_MASK | PCI_BASE_ADDRESS_MEM_TYPE_64 | PCI_BASE_ADDRESS_SPACE_MEMORY), 1); - } - else - { - cfg_bar_write(&fpga->pci_config.bar0, new_val, 1); - } - break; - case 0x14: // BAR 1 - if (new_val == GENMASK(31, 0)) - { - cfg_bar_write(&fpga->pci_config.bar1, (uint32_t)(~(COYOTE_HYPERVISOR_BAR0_SIZE - 1) >> 32), 0); - } - else - { - cfg_bar_write(&fpga->pci_config.bar1, new_val, 0); - } - break; - case 0x18: // BAR 2 - if (new_val == GENMASK(31, 0)) - { - cfg_bar_write(&fpga->pci_config.bar2, (uint32_t)(COYOTE_HYPERVISOR_BAR2_MASK | PCI_BASE_ADDRESS_MEM_TYPE_64 | PCI_BASE_ADDRESS_SPACE_MEMORY), 1); - } - else - { - cfg_bar_write(&fpga->pci_config.bar2, new_val, 1); - } - break; - case 0x1C: // BAR 3 - if (new_val == GENMASK(31, 0)) - { - cfg_bar_write(&fpga->pci_config.bar3, (uint32_t)(~(COYOTE_HYPERVISOR_BAR2_SIZE - 1) >> 32), 0); - } - else - { - cfg_bar_write(&fpga->pci_config.bar3, new_val, 0); - } - break; - case 0x20: // BAR 4 - if (new_val == GENMASK(31, 0)) - { - cfg_bar_write(&fpga->pci_config.bar4, (uint32_t)(COYOTE_HYPERVISOR_BAR4_MASK | PCI_BASE_ADDRESS_MEM_TYPE_64 | PCI_BASE_ADDRESS_SPACE_MEMORY), 1); - } - else - { - cfg_bar_write(&fpga->pci_config.bar4, new_val, 1); - } - break; - case 0x24: // BAR 5 - if (new_val == GENMASK(31, 0)) - { - cfg_bar_write(&fpga->pci_config.bar5, (uint32_t)(~(COYOTE_HYPERVISOR_BAR4_SIZE - 1) >> 32), 0); - } - else - { - cfg_bar_write(&fpga->pci_config.bar5, new_val, 0); - } - break; - case 0x3C: // Interrupt line - fpga->pci_config.interrupt_line = (uint8_t)new_val; - break; - default: - if (pos >= MSIX_OFFSET && pos < MSIX_OFFSET + MSIX_SIZE) - { - // Emulate write to msix header - ret_val = write_to_msix_header((void *)(fpga->pci_config.cap_section + MSIX_OFFSET), pos - MSIX_OFFSET, new_val, count); - if (ret_val < 0) - { - return ret_val; - } - } - else - { - // dbg_info("write to fpga config with %lu not handled writes at offset 0x%llx", - // count, pos); - } - } - - return 0; -} - -/** - * @brief This function handles most of the communication. - * The offset is interpreted as command to the hypervisor and - * the value of the write can be used as argument either to pass a simple - * number or in case of more complicated data it passes a pointer to data - * inside the vm. - * The following functionalities are handled: - * - * REGISTER_PID: - * A write to this command allocates a new CPID (if any are free) - * and registers the pid passed as argument. The CPID can be retrieved by the - * guest by a read at the same offset. - * - * UNREGISTER_PID: - * Complement to REGISTER_PID. The guest writes the CPID to this offset - * to deregister a guest process. - * - * MAP_USER: - * The guest writes the address to the notifier to this offset. The hypervisor - * copies the notifier from the vm. The notifier contains information about - * the address range that should be mapped on the fpga. - * - * UNMAP_USER: - * Counterpart to MAP_USER. Works in a similar matter. The guest writes - * the address of a notifier to this offset. The hypervisor reads the struct from the - * vm and unmaps the range. The range has to be mapped previsously with a call to - * MAP_USER. - * - * PUT_ALL_USER_PAGES: - * The guest writes 0 or non zero to this offset to indicate if the pages - * should not be dirtied/should be dirtied before releasing them. - * The call then puts all pages that were mapped by the mediated device. - * The guest usally calls this if the device is closed in the vm. - * - * TEST_INTERRUPT: - * TODO: delete - * - * @param vfpga mediated vfpga - * @param buf write buffer - * @param count bytes to write - * @param pos offset into BAR2 region - * @return ssize_t bytes written - */ -static ssize_t handle_bar2_write(struct m_fpga_dev *vfpga, const char __user *buf, - size_t count, loff_t pos) -{ - loff_t offset; - int ret_val; - uint64_t pid, epid; - uint64_t cpid; - struct bus_drvdata *pd; - uint64_t tmp[MAX_USER_ARGS + 2]; - struct hypervisor_map_notifier map_notifier, *full_map_notifier; - uint64_t map_full_size; - - ret_val = 0; - offset = pos & HYPERVISOR_OFFSET_MASK; - pd = vfpga->fpga->pd; - - switch (offset) - { - case REGISTER_PID_OFFSET: - { - ret_val = copy_from_user(tmp, buf, count); - if (ret_val) - { - pr_err("%s.%u: Failed to copy data from user\n", __func__, __LINE__); - return -EFAULT; - } - - pid = tmp[0]; - dbg_info("Registering pid %llu\n", pid); - - spin_lock(&pd->stat_lock); - spin_lock(&vfpga->current_cpid_lock); - - // Calculate an effective pid to avoid clashes with other vms - // lower 16 bits are the pid inside the vm and the upper 16 - // bits are to identify the vm - epid = pid | (vfpga->id << 16); - - // register epid - cpid = register_pid(vfpga->fpga, epid); - if (cpid == -1) - { - pr_err("registration failed in hypervisor pid: %lld id: %d", pid, vfpga->id); - spin_unlock(&pd->stat_lock); - return -EIO; - } - - // bookeeping which virtual devices belongs to which region - vfpga->fpga->vdevs[cpid] = vfpga; - - vfpga->current_cpid = cpid; - - spin_unlock(&pd->stat_lock); - spin_unlock(&vfpga->current_cpid_lock); - - dbg_info("Successfully registered pid %llu\n", pid); - - return count; - } - case UNREGISTER_PID_OFFSET: - { - // read cpid - ret_val = copy_from_user(&tmp, buf, count); - if (ret_val) - { - pr_err("%s.%u: Failed to copy data from user\n", __func__, __LINE__); - return -EFAULT; - } - - cpid = tmp[0]; - dbg_info("Unregistering cpid %llu\n", cpid); - - // Unregister cpid - spin_lock(&pd->stat_lock); - - ret_val = unregister_pid(vfpga->fpga, cpid); - if (ret_val) - { - pr_err("unregestration failed in hypervisor pid: %lld id: %d\n", pid, vfpga->id); - spin_unlock(&pd->stat_lock); - return -EIO; - } - - // Remove reverse mapping, cpid is not in use anymore - vfpga->fpga->vdevs[cpid] = NULL; - dbg_info("unregestration succesfull in hypervisor pid: %lld id: %d\n", pid, vfpga->id); - spin_unlock(&pd->stat_lock); - return count; - } - case MAP_USER_OFFSET: - { - // read gpa of the arguments - ret_val = copy_from_user(&tmp, buf, count); - if (ret_val) - { - pr_info("%s.%d: Failed to copy gpa", __func__, __LINE__); - return -EFAULT; - } - - // read notifier header from guest - ret_val = hypervisor_access_kvm(vfpga, tmp[0], sizeof(struct hypervisor_map_notifier), &map_notifier, 0); - if (ret_val) - { - pr_info("%s.%d: Failed to read from guest", __func__, __LINE__); - return -EIO; - } - - // read complete notifier from guest - map_full_size = sizeof(struct hypervisor_map_notifier) + map_notifier.npages * sizeof(uint64_t); - full_map_notifier = kzalloc(map_full_size, GFP_KERNEL); - - ret_val = hypervisor_access_kvm(vfpga, tmp[0], map_full_size, full_map_notifier, 0); - if (ret_val) - { - pr_info("%s.%d: Failed to read from guest", __func__, __LINE__); - kfree(full_map_notifier); - return -EIO; - } - - dbg_info("Mapping user pages from hypervisor: gva: %llx, len: %llu, cpid: %llu", full_map_notifier->gva, - full_map_notifier->len, full_map_notifier->cpid); - - // Pin pages and install user mappings onto fpga. - ret_val = hypervisor_tlb_get_user_pages(vfpga, full_map_notifier); - if (ret_val) - { - pr_info("%s.%d: Failed to get all user pages", __func__, __LINE__); - } - else - { - ret_val = count; - dbg_info("Successfully mapped user buffer\n"); - } - - kfree(full_map_notifier); - return ret_val; - } - case UNMAP_USER_OFFSET: - { - // Copy gpa - ret_val = copy_from_user(&tmp, buf, count); - if (ret_val) - { - pr_info("%s.%d: Failed to copy gpa", __func__, __LINE__); - return -EFAULT; - } - - // read gva + cpid from kvm - ret_val = hypervisor_access_kvm(vfpga, tmp[0], sizeof(struct hypervisor_map_notifier), &map_notifier, - 0); - if (ret_val) - { - pr_info("%s.%d: Failed to read from kvm", __func__, __LINE__); - return -EFAULT; - } - - ret_val = hypervisor_tlb_put_user_pages(vfpga, &map_notifier); - if (ret_val) - { - pr_info("%s.%d: Failed to put all user pages", __func__, __LINE__); - } - else - { - ret_val = count; - dbg_info("Successfully unmapped user buffer\n"); - } - - return ret_val; - } - case PUT_ALL_USER_PAGES: - { - // read dirtied flag - ret_val = copy_from_user(&tmp, buf, count); - if (ret_val) - { - pr_info("could not copy dirtied flag\n"); - return -EFAULT; - } - - // put all user pages - ret_val = hypervisor_tlb_put_user_pages_all(vfpga, tmp[0]); - if (ret_val) - { - pr_info("could not put all user pages\n"); - return -EIO; - } - - return count; - } - case TEST_INTERRUPT_OFFSET: - { - dbg_info("Fired interrupt with ret_val %llu!\n", fire_interrupt(&vfpga->msix_vector[0])); - return count; - } - default: - { - // Not used, should not cause any state change - return count; - } - } - - return count; -} - -/** - * @brief Similar to vfpga_read. Demultiplexes the writes - * to the emulated pci device. - * - * @param mdev mediated virtual device - * @param buf write buffer - * @param count bytes to write - * @param ppos address - * @return ssize_t bytes written - */ -static ssize_t hypervisor_vfpga_write(struct mdev_device *mdev, const char __user *buf, - size_t count, loff_t *ppos) -{ - loff_t pos, offset, index; - int ret_val; - struct m_fpga_dev *vfpga; - - pos = *ppos; - offset = pos & HYPERVISOR_OFFSET_MASK; - index = COYOTE_GET_INDEX(pos); - ret_val = 0; - - vfpga = mdev_get_drvdata(mdev); - BUG_ON(!vfpga); - - switch (index) - { - case VFIO_PCI_CONFIG_REGION_INDEX: - { - if (offset + count > COYOTE_HYPERVISOR_CONFIG_SIZE) - { - pr_err("%s.%u: Out of bound write\n", __func__, __LINE__); - return -EFAULT; - } - - ret_val = handle_pci_cfg_write(vfpga, (char __user *)buf, count, pos); - if (ret_val) - { - dbg_info("could not write pci cfg\n"); - return -EIO; - } - - return count; - } - case VFIO_PCI_BAR0_REGION_INDEX: - { - // Check bounds - if (offset + count > COYOTE_HYPERVISOR_BAR0_SIZE) - { - pr_err("%s.%u: Out of bound read\n", __func__, __LINE__); - return -EFAULT; - } - - return handle_bar0_access(vfpga, (char __user *)buf, count, pos, 1); - } - case VFIO_PCI_BAR2_REGION_INDEX: - { - // Check bounds - if (offset + count > COYOTE_HYPERVISOR_BAR2_SIZE) - { - pr_err("%s.%u: Out of bound read\n", __func__, __LINE__); - return -EFAULT; - } - - return handle_bar2_write(vfpga, buf, count, pos); - } - case VFIO_PCI_BAR4_REGION_INDEX: - { - // Check bounds - if (offset + count > COYOTE_HYPERVISOR_BAR4_SIZE) - { - pr_err("%s.%u: Out of bound read\n", __func__, __LINE__); - return -EFAULT; - } - - return handle_bar4_access(vfpga, (char *)buf, count, pos, 1); - } - default: - { - // Not a valid region to read - pr_debug("%s.%d: Write to invalid region %lld\n", __func__, __LINE__, index); - return 0; - } - } -} - -/** - * @brief IOCTL calls to the device. The vm cannot perform any ioctl calls - * but the VFIO framework has a set of IOCTL functions that it will use to gather - * information over the pci device that is emulated by this driver. - * - * These are: - * - VFIO_DEVICE_GET_INFO - * Passes a pointer to a struct. This is filled by this function with the - * amount of regions and interrupts. Furthermore it communicates the - * capabilties of the device. - * - * - VFIO_DEVICE_GET_REGION_INFO - * Passes a pointer to a struct. The user set the index of the region - * it wants more information about and this function will set the remaining fields - * with relevant information such as offset and size. - * - * - VFIO_DEVICE_GET_IRQ_INFO - * Similar to GET_REGION_INFO, but for interrupts. The user passes - * a struct and specifies about which kind of interrupt the information should - * be provided and the this function will set the other fields. - * - * - VFIO_DEVICE_SET_IRQS - * Managment for the interrupts. The user calls with a combination of flags that - * set interrupts. For more information consult the VFIO documentation. - * - * - VFIO_DEVICE_RESET - * TODO: Implement - * - * @param mdev mediated vfpga - * @param cmd - * @param arg - * @return long - */ -static long hypervisor_vfpga_ioctl(struct mdev_device *mdev, unsigned int cmd, unsigned long arg) -{ - struct m_fpga_dev *vfpga; - struct vfio_device_info dev_info; - struct vfio_region_info region_info; - struct vfio_irq_info irq_info; - struct vfio_irq_set *irq_set; - int ret_val; - unsigned int bytes; - void __user *argp; - uint64_t index; - - BUG_ON(!mdev); - vfpga = mdev_get_drvdata(mdev); - if (!vfpga) - { - pr_err("Failed to get drv data\n"); - return -EIO; - } - - ret_val = 0; - argp = (void __user *)arg; - - switch (cmd) - { - case VFIO_DEVICE_GET_INFO: - { - // Copy the argsz paramter from user space - ret_val = copy_from_user(&bytes, argp, sizeof(bytes)); - if (ret_val) - { - pr_err("%s.%u: Failed to copy from user space", __func__, __LINE__); - return -EFAULT; - } - - // Copy the dev_info struct - ret_val = copy_from_user(&dev_info, argp, bytes); - if (ret_val) - { - pr_err("%s.%u: Failed to copy from user space", __func__, __LINE__); - return -EFAULT; - } - - // Resetable PCI device - dev_info.flags = VFIO_DEVICE_FLAGS_PCI | VFIO_DEVICE_FLAGS_RESET; - - // Propagate default values from the framework - dev_info.num_regions = VFIO_PCI_NUM_REGIONS; - dev_info.num_irqs = VFIO_PCI_NUM_IRQS; - - // Copy the updated info struct back to the user - ret_val = copy_to_user(argp, &dev_info, bytes); - if (ret_val) - { - pr_err("%s.%u: Failed to copy from user space", __func__, __LINE__); - return -EFAULT; - } - - return 0; - } - case VFIO_DEVICE_GET_REGION_INFO: - { - // Copy the argsz paramter from user space - ret_val = copy_from_user(&bytes, argp, sizeof(bytes)); - if (ret_val) - { - pr_err("%s.%u: Failed to copy from user space", __func__, __LINE__); - return -EFAULT; - } - - // Copy the dev_info struct - ret_val = copy_from_user(®ion_info, argp, bytes); - if (ret_val) - { - pr_err("%s.%u: Failed to copy from user space", __func__, __LINE__); - return -EFAULT; - } - - // For the config region and the - // 3 64 bit registers return the size. Everything else does not - // exist and is therefore 0. - index = region_info.index; - switch (index) - { - case VFIO_PCI_CONFIG_REGION_INDEX: - { - region_info.size = COYOTE_HYPERVISOR_CONFIG_SIZE; - break; - } - case VFIO_PCI_BAR0_REGION_INDEX: - { - region_info.size = COYOTE_HYPERVISOR_BAR0_SIZE; - // direct pass through, for high performance, do not trap this instructions - region_info.flags |= VFIO_REGION_INFO_FLAG_MMAP; - break; - } - case VFIO_PCI_BAR2_REGION_INDEX: - { - region_info.size = COYOTE_HYPERVISOR_BAR2_SIZE; - break; - } - case VFIO_PCI_BAR4_REGION_INDEX: - { - region_info.size = COYOTE_HYPERVISOR_BAR4_SIZE; - // direct pass through, for high performance, do not trap this instructions - region_info.flags |= VFIO_REGION_INFO_FLAG_MMAP; - break; - } - default: - { - region_info.size = 0; - } - } - - // Upper 32 bits are used to indicate the index - region_info.offset = COYOTE_INDEX_TO_ADDR(index); - - // Allow read and write - region_info.flags |= VFIO_REGION_INFO_FLAG_READ | VFIO_REGION_INFO_FLAG_WRITE; - - // Copy the updated info struct back to the user - ret_val = copy_to_user(argp, ®ion_info, bytes); - if (ret_val) - { - pr_err("%s.%u: Failed to copy from user space", __func__, __LINE__); - return -EFAULT; - } - - return 0; - } - case VFIO_DEVICE_GET_IRQ_INFO: - { - // Copy the argsz paramter from user space - ret_val = copy_from_user(&bytes, argp, sizeof(bytes)); - if (ret_val) - { - pr_err("%s.%u: Failed to copy from user space", __func__, __LINE__); - return -EFAULT; - } - - // Copy the dev_info struct - ret_val = copy_from_user(&irq_info, argp, bytes); - if (ret_val) - { - pr_err("%s.%u: Failed to copy from user space", __func__, __LINE__); - return -EFAULT; - } - - // This device supports MSIX interrupts - if (irq_info.index == VFIO_PCI_MSIX_IRQ_INDEX) - { - irq_info.flags = VFIO_IRQ_INFO_NORESIZE | VFIO_IRQ_INFO_EVENTFD; - - // Defined by a define in the header - irq_info.count = NUM_INTERRUPTS; - } - // All other types are not supported - else - { - irq_info.flags = 0; - irq_info.flags = 0; - } - - // Copy the updated info struct back to the user - ret_val = copy_to_user(argp, &irq_info, bytes); - if (ret_val) - { - pr_err("%s.%u: Failed to copy from user space", __func__, __LINE__); - return -EFAULT; - } - - return 0; - } - case VFIO_DEVICE_SET_IRQS: - { - // copy argz field - ret_val = copy_from_user(&bytes, argp, sizeof(bytes)); - if (ret_val) - { - dbg_info("Failed to copy from user space\n"); - return -EFAULT; - } - - // Allocate memory for addtional data - irq_set = kzalloc(bytes, GFP_KERNEL); - BUG_ON(!irq_set); - - // copy struct from user - ret_val = copy_from_user(irq_set, argp, bytes); - if (ret_val) - { - dbg_info("Failed to copy from user space\n"); - kfree(irq_set); - return -EFAULT; - } - - // Only MSIX interrupts are supported and needed by the - // guest driver. - switch (irq_set->index) - { - case VFIO_PCI_MSIX_IRQ_INDEX: - ret_val = handle_set_irq_msix(vfpga, irq_set); - break; - default: - // dbg_info("Tried to set IRQ! Flags: %x, Index: %u, Start: %u, Count: %u\n", - // irq_set->flags, irq_set->index, irq_set->start, irq_set->count); - break; - } - - kfree(irq_set); - return ret_val; - } - case VFIO_DEVICE_RESET: - { - return 0; - } - default: - { - return -EINVAL; - } - } -} - -/** - * @brief Allows mmap of BAR 0 and 4, and therefore enables - * direct pass through of the control registers. The vma struct contains an offset - * into the pci region and from this we can determine which BAR is mapped. - * BAR 0 and BAR 4 are seperated from each other. This allows to adjust sizes of - * these control registers later on without to much effort to change the hypervisor. - * - * @param mdev - * @param vma - * @return int - */ -int hypervisor_vfpga_mmap(struct mdev_device *mdev, struct vm_area_struct *vma) -{ - int region; - unsigned long vaddr; - unsigned long offset; - - struct m_fpga_dev *md; - struct fpga_dev *d; - struct bus_drvdata *pd; - - int ret_val; - - md = mdev_get_drvdata(mdev); - BUG_ON(!md); - d = md->fpga; - BUG_ON(!d); - pd = d->pd; - BUG_ON(!pd); - - // offset into the pci region - vaddr = vma->vm_pgoff << PAGE_SHIFT; - // get the region that should be mapped - region = COYOTE_GET_INDEX(vaddr); - // offset into this region - offset = vaddr & HYPERVISOR_OFFSET_MASK; - ret_val = 0; - - dbg_info("MMAP with vaddr %lu, VFIO region index %d, offset %lu\n", vaddr, region, offset); - - // Do not cache - vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); - - // Allow passthrough to hardware - if (region == VFIO_PCI_BAR0_REGION_INDEX) - { - // BAR0 is for the address ctrl registers - ret_val = remap_pfn_range(vma, vma->vm_start, d->fpga_phys_addr_ctrl >> PAGE_SHIFT, - FPGA_CTRL_SIZE, vma->vm_page_prot); - if (ret_val) - { - dbg_info("Failed to mmap BAR0.\n"); - } - else - { - dbg_info("Mapped addr %llx with size %u\n", d->fpga_phys_addr_ctrl, - FPGA_CTRL_SIZE); - } - } - else if (region == VFIO_PCI_BAR4_REGION_INDEX) - { - // BAR4 is for the avx address ctrl registers - ret_val = remap_pfn_range(vma, vma->vm_start, d->fpga_phys_addr_ctrl_avx >> PAGE_SHIFT, - FPGA_CTRL_CNFG_AVX_SIZE, vma->vm_page_prot); - if (ret_val) - { - dbg_info("Failed to mmap BAR4.\n"); - } - else - { - dbg_info("Mapped addr %llx with size %u\n", d->fpga_phys_addr_ctrl_avx, - FPGA_CTRL_CNFG_AVX_SIZE); - } - } - else - { - // Not allowed region - ret_val = -EINVAL; - } - - return ret_val; -} - -// -// -// START: This section contains static functions and arrays that display information 0x2000for the mediated devices in sysfs -// -// - -static ssize_t -info_show(struct device *dev, struct device_attribute *attr, char *buf) -{ - - return sprintf(buf, "fpga region\n"); -} -static DEVICE_ATTR_RO(info); - -static struct attribute *dummy_attrs[] = { - &dev_attr_info.attr, - NULL, -}; - -static const struct attribute_group fpga_dev_group = { - .name = "vfpga", - .attrs = dummy_attrs, -}; - -const struct attribute_group *fpga_dev_groups[] = { - &fpga_dev_group, - NULL, -}; - -static ssize_t -vfpga_info_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct mdev_device *mdev = mdev_from_dev(dev); - struct m_fpga_dev *vfpga = mdev_get_drvdata(mdev); - - return sprintf(buf, "virtual vfpga device with id %d\n", vfpga->id); -} -DEVICE_ATTR_RO(vfpga_info); - -static struct attribute *vpga_attrs[] = { - &dev_attr_vfpga_info.attr, - NULL, -}; - -static const struct attribute_group vfpga_dev_group = { - .name = "vpga info", - .attrs = vpga_attrs, -}; - -const struct attribute_group *vfpga_dev_groups[] = { - &vfpga_dev_group, - NULL, -}; - -static ssize_t -name_show(struct device *dev, struct device_attribute *attrs, char *buf) -{ - return sprintf(buf, "%s-type\n", dev->kobj.name); -} -DEVICE_ATTR_RO(name); - -static ssize_t -device_api_show(struct device *dev, struct device_attribute *attrs, char *buf) -{ - return sprintf(buf, VFIO_DEVICE_API_PCI_STRING); -} -DEVICE_ATTR_RO(device_api); - -static struct attribute *vfpga_type_attrs[] = { - &dev_attr_name.attr, - &dev_attr_device_api.attr, - NULL, -}; - -// -// END -// - -/** - * @brief This function populates a mdev_parent_ops - * struct that is used to create a mediated type - * that is shown in the sysfs and provides all the callbacks - * used to manage all the devices - * - * @param vfpga virtual fpga region - * @return struct mdev_parent_ops* - */ -struct mdev_parent_ops *hypervisor_get_ops(struct fpga_dev *vfpga) -{ - struct mdev_parent_ops *ops; - struct attribute_group *type_group, **type_groups; - char *name; - - BUG_ON(!vfpga); - - // alloc type group - type_group = kzalloc(sizeof(struct attribute_group), GFP_KERNEL); - - if (!type_group) - { - dbg_info("Failed to allocate type group\n"); - goto err; - } - - // alloc name - name = kzalloc(64, GFP_KERNEL); - if (!name) - { - dbg_info("could not allocate name\n"); - goto err_name; - } - - // Create first and only type group - sprintf(name, "fpga_mdev.%d", vfpga->id); - type_group->name = name; - type_group->attrs = vfpga_type_attrs; - - // Create type groups array - type_groups = kzalloc(sizeof(struct attribute_group *) * 2, GFP_KERNEL); - if (!type_groups) - { - dbg_info("Could not allocate type group array\n"); - goto err_type_groups; - } - type_groups[0] = type_group; - type_groups[1] = NULL; - - ops = kzalloc(sizeof(struct mdev_parent_ops), GFP_KERNEL); - if (!ops) - { - dbg_info("could not allocate mdev parent ops\n"); - goto err_ops; - } - - // Set attributes - ops->owner = THIS_MODULE; - ops->dev_attr_groups = fpga_dev_groups; - ops->mdev_attr_groups = vfpga_dev_groups; - ops->supported_type_groups = type_groups; - - // Set handler functions - ops->open_device = hypervisor_vfpga_open; - ops->close_device = hypervisor_vfpga_close; - ops->create = hypervisor_vfpga_create; - ops->remove = hypervisor_vfpga_remove; - ops->write = hypervisor_vfpga_write; - ops->read = hypervisor_vfpga_read; - ops->ioctl = hypervisor_vfpga_ioctl; - ops->mmap = hypervisor_vfpga_mmap; - - dbg_info("created vfio-mdev operations\n"); - - return ops; - -err_ops: - kfree(type_groups); -err_type_groups: - kfree(name); -err_name: - kfree(type_group); -err: - return NULL; -} \ No newline at end of file diff --git a/driver/hypervisor/hypervisor_ops.h b/driver/hypervisor/hypervisor_ops.h deleted file mode 100644 index 042b4edc1..000000000 --- a/driver/hypervisor/hypervisor_ops.h +++ /dev/null @@ -1,38 +0,0 @@ -/** - * Copyright (c) 2023, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HYPERVISOR_OPS_H__ -#define __HYPERVISOR_OPS_H__ - -#include "../coyote_dev.h" -#include "../fpga_fops.h" -#include "hypervisor_mmu.h" -#include "hypervisor_interrupts.h" - -struct mdev_parent_ops *hypervisor_get_ops(struct fpga_dev *vfpga); - -#endif \ No newline at end of file diff --git a/examples_hw/CMakeLists.txt b/examples_hw/CMakeLists.txt deleted file mode 100644 index baba026e5..000000000 --- a/examples_hw/CMakeLists.txt +++ /dev/null @@ -1,257 +0,0 @@ -cmake_minimum_required(VERSION 3.0) -project(test) - -set(CYT_DIR ${CMAKE_SOURCE_DIR}/../) -set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CYT_DIR}/cmake) - -find_package(CoyoteHW REQUIRED) - -# -# TEST -# - -# -# Static -# @brief: Default shell, contains interconnect and memory link testing circuits (perf_local) -# -# @note: Add a target device (FDEV_NAME) -# -# This is what every other shell is built against -# - -if(EXAMPLE STREQUAL "static") - set(BUILD_STATIC 1) - set(BUILD_SHELL 0) - set(BUILD_OPT 1) - set(N_REGIONS 4) - set(EN_STRM 1) - set(EN_MEM 1) - set(HBM_SPLIT 1) - - validation_checks_hw() - - load_apps ( - VFPGA_C0_0 "apps/perf_local" - VFPGA_C0_1 "apps/perf_local" - VFPGA_C0_2 "apps/perf_local" - VFPGA_C0_3 "apps/perf_local" - ) - - create_hw() -endif() - - -if(EXAMPLE STREQUAL "interrupts") - message("** User interrupts example") - set(N_REGIONS 1) - set(EN_STRM 1) - set(EN_MEM 0) - set(EN_PR 0) - - validation_checks_hw() - - load_apps ( - VFPGA_C0_0 "apps/user_interrupts" - ) - - create_hw() -endif() - -if(EXAMPLE STREQUAL "hls_vadd") - message("** HLS vector addition example") - set(N_REGIONS 1) - set(EN_STRM 1) - set(EN_MEM 0) - set(N_STRM_AXI 2) - - validation_checks_hw() - - load_apps ( - VFPGA_C0_0 "apps/hls_vadd" - ) - - create_hw() -endif() - -# -# Shells with examples -# - -# Application examples, streaming examples -# @brief: Streaming interface example -# The first application is gradient boosting decision trees inference - RTL integration example -# The second one is HyperLogLog cardinality estimation - HLS integration example -# -# @note: Floorplan provided for u55c only -> add manual app floorplans for other devices -# -if(EXAMPLE STREQUAL "streaming") - message("** Streaming examples: HyperLogLog (cardinality estimation), GBM decision trees (inference) and AES CBC mode") - set(SHELL_PROBE 1) - set(FDEV_NAME "u55c") - set(N_REGIONS 1) - set(EN_STRM 1) - set(EN_MEM 0) - set(EN_PR 1) - set(N_CONFIG 2) - set(FPLAN_PATH "${CMAKE_SOURCE_DIR}/floorplans/streaming_fplan_u55c.xdc") - - validation_checks_hw() - - load_apps ( - VFPGA_C0_0 "apps/hyperloglog" - VFPGA_C1_0 "apps/gbm_dtrees" - ) - - create_hw() -endif() - -# @brief Shell add app -# This is an example how a previous shell can be extended with additional application on the fly -# This means you don't have to recompile the whole shell, just this new apps will additionally compiled -# -# @note: Need to provide a path to the existing shell build dir ($SHELL_PATH) -# -if(EXAMPLE STREQUAL "streaming_add_aes") - message("** Streaming examples: Add AES to the previous two apps (app build flow)") - set(BUILD_APP 1) - set(BUILD_SHELL 0) - set(N_CONFIG 1) - - validation_checks_hw() - - load_apps ( - VFPGA_C0_0 "apps/aes_ecb" - ) - - create_hw() -endif() - -# @brief: AES encryption multithreading -# Running multiple threads within one vFPGA -# -# -if(EXAMPLE STREQUAL "multithreading") - message("** Streaming examples: Multithreading AES CBC") - set(SHELL_PROBE 2) - set(FDEV_NAME "u55c") - set(N_REGIONS 1) - set(EN_STRM 1) - set(N_STRM_AXI 8) - set(EN_MEM 0) - set(EN_PR 0) - - validation_checks_hw() - - load_apps ( - VFPGA_C0_0 "apps/aes_cbc" - ) - - create_hw() -endif() - - -# GPU example -# @brief: GPU perf test -# -# @note: Add a target device (FDEV_NAME) -# -if(EXAMPLE STREQUAL "perf_gpu") - message("** GPU perf example") - set(SHELL_PROBE 4) - set(N_REGIONS 1) - set(EN_MEM 1) - set(N_CARD_AXI 2) - - validation_checks_hw() - - load_apps ( - VFPGA_C0_0 "apps/kmeans" - VFPGA_C0_1 "apps/kmeans" - ) - - create_hw() -endif() - -# Network example, RDMA -# @brief: RDMA with AES encryption example -# -# @note: Add a target device (FDEV_NAME) -# -if(EXAMPLE STREQUAL "rdma_aes") - message("** RDMA AES-en(de)cryption test") - set(SHELL_PROBE 5) - set(N_REGIONS 2) - set(EN_STRM 1) - set(EN_MEM 1) - set(EN_RDMA 1) - - validation_checks_hw() - - load_apps ( - VFPGA_C0_0 "apps/rdma_base" - VFPGA_C0_1 "apps/rdma_aes" - ) - - create_hw() -endif() - -if(EXAMPLE STREQUAL "rdma_perf") - message("** RDMA perf test") - set(SHELL_PROBE 6) - set(N_REGIONS 1) - set(EN_STRM 1) - set(EN_RDMA 1) - set(N_STRM_AXI 2) - - validation_checks_hw() - - load_apps ( - VFPGA_C0_0 "apps/rdma_perf" - ) - - create_hw() -endif() - -# Network example, TCP iperf -# @brief: TCP iperf -# -# @note: Add a target device (FDEV_NAME) -# -if(EXAMPLE STREQUAL "tcp_iperf") - message("** TCP iperf") - set(SHELL_PROBE 7) - set(N_REGIONS 1) - set(EN_STRM 1) - set(EN_TCP 1) - - validation_checks_hw() - - load_apps ( - VFPGA_C0_0 "apps/tcp_iperf" - ) - - create_hw() -endif() - -# -# Perf FPGA -# @brief: Link benchmarks, FPGA initiated -# -# @note: Add a target device (FDEV_NAME) -# - -if(EXAMPLE STREQUAL "perf_fpga") - set(N_REGIONS 1) - set(EN_STRM 1) - set(N_STRM_AXI 2) - set(EN_MEM 0) # Should work with MEM as well - set(N_CARD_AXI 2) - - validation_checks_hw() - - load_apps ( - VFPGA_C0_0 "apps/perf_fpga" - ) - - create_hw() -endif() diff --git a/examples_hw/apps/gbm_dtrees/hdl/DTPackage.sv b/examples_hw/apps/gbm_dtrees/hdl/DTPackage.sv deleted file mode 100644 index 1e97d417c..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/DTPackage.sv +++ /dev/null @@ -1,91 +0,0 @@ - -/* - * Copyright 2019 - 2020 Systems Group, ETH Zurich - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - - - -package DTPackage; - -parameter TREE_OFFSET_BITS = 10; -parameter TUPLE_OFFSET_BITS = 9; -parameter TREE_MEM_WIDTH_BITS = 1; -parameter MAX_TREE_DEPTH_BITS = 4; - -parameter NUM_PUS_PER_CLUSTER_BITS = 5; -parameter NUM_PUS_PER_CLUSTER = 28; -parameter NUM_DTPU_CLUSTERS = 4; -parameter NUM_DTPU_CLUSTERS_BITS = 2; -parameter NUM_TREES_PER_PU = 32; -parameter FEATURES_DISTR_DELAY = 8; -parameter DATA_PRECISION = 32; -parameter DATA_LINE_WIDTH = 64; - - -parameter TREE_MEM_READ_LATENCY = 2; -parameter DATA_MEM_READ_LATENCY = 2; - -parameter EMPTY_PIPELINE_WAIT_CYCLES = 128; - -parameter FP_ADDER_LATENCY = 2; - - - -typedef struct packed { - bit [TREE_OFFSET_BITS-1:0] tree_offset; - bit [TUPLE_OFFSET_BITS-1:0] tuple_offset; - bit last_tree; - bit empty_tree; -} TreeInstruction_t; - -typedef struct packed { - bit [TREE_OFFSET_BITS+TREE_MEM_WIDTH_BITS-1:0] node_address; - bit [TUPLE_OFFSET_BITS-1:0] tuple_offset; - bit [MAX_TREE_DEPTH_BITS-1:0] node_level; - bit empty_tree; - bit node_nop; - bit last_tree; - bit leaf_node; - - bit [31:0] node_res_val; -} NodeInstruction_t; - - - -typedef struct packed { - bit [3:0] split_dir; - bit [7:0] findex; - bit right_child; - bit left_child; - bit [1:0] op_type; -} NodeType_t; - -typedef struct packed { - bit [15:0] word_1_h; - bit [15:0] word_1_l; - bit [15:0] right_child_offset; - NodeType_t node_type; -} TreeNode_t; - - - -endpackage - diff --git a/examples_hw/apps/gbm_dtrees/hdl/DTProcessor.sv b/examples_hw/apps/gbm_dtrees/hdl/DTProcessor.sv deleted file mode 100644 index c4b148d26..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/DTProcessor.sv +++ /dev/null @@ -1,557 +0,0 @@ - -/* - * Copyright 2019 - 2020 Systems Group, ETH Zurich - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -/* - - The Core module is where computations happen - - core_data_in carry a stream of Trees/Data for processing in the core - - tuple_out_data carries the result of inference on one tuple, this can be - a partial result if not the complete model is stored in the core or the - full result if the complete model fits in the core. -*/ - -import DTPackage::*; - -module DTProcessor ( - input wire clk, - input wire rst_n, - // parameters - input wire start_core, - - input wire [5:0] tuple_length, - input wire [4:0] num_trees_per_pu_minus_one, - input wire [3:0] tree_depth, - input wire [8:0] num_lines_per_tuple, - // input trees - input wire [511:0] core_data_in, - input wire core_data_in_type, // 0: trees, 1: data - input wire core_data_in_valid, - input wire core_data_in_last, - output wire core_data_in_ready, - // output - input wire last_result_line, - input wire [15:0] last_result_line_mask, - output wire [511:0] core_result_out, - output wire core_result_valid, - input wire core_result_ready -); - - - -localparam IDLE = 1'b0, - RUN_MODE = 1'b1; - - -wire [511:0] ctrl_line; - -wire in_fifo_re; -wire in_fifo_full; -wire in_fifo_valid; -wire in_fifo_data_last; -wire in_fifo_data_type; -wire [511:0] in_fifo_data; - -reg tree_length_set; -reg [9:0] tree_received_words; -reg [9:0] curr_tree_length; - -wire [9:0] tree_possible_words; -wire [9:0] tree_remaining_words; -wire [9:0] curr_tree_line_words; -wire tree_data_in_last; -wire in_fifo_trees_re; - - -reg aligned_fifo_data_type_d1; -reg tuple_start_set; -reg [5:0] tuple_received_words; -reg [5:0] curr_tuple_off; - -wire [5:0] tuple_possible_words; -wire [5:0] tuple_remaining_words; -wire [5:0] curr_tuple_line_words; -wire tuple_data_in_last; -wire in_fifo_tuples_re; - -wire in_fifo_item_last; -wire [3:0] in_fifo_data_off; -wire [4:0] in_fifo_data_word_count; -wire [2:0] in_fifo_data_size; -wire [4:0] in_fifo_data_size_t; - -wire aligned_fifo_almfull; -wire aligned_fifo_valid; -wire aligned_fifo_re; -wire aligned_fifo_data_last; -wire aligned_fifo_data_type; - -wire [2:0] aligned_fifo_data_size; -wire [511:0] aligned_fifo_data; - -wire aligner_data_out_valid; -wire aligner_data_out_last; -wire aligner_data_out_type; -wire [2:0] aligner_data_out_size; -wire [511:0] aligner_data_out; - -reg core_fsm_state; -reg [NUM_DTPU_CLUSTERS_BITS-1:0] data_line_cu; -reg [4:0] data_line_pu; -reg [NUM_DTPU_CLUSTERS_BITS-1:0] data_line_cu_d1; -reg [4:0] data_line_pu_d1; -reg [511:0] data_line; -reg data_line_last; -reg [2:0] data_line_last_valid_pos; -reg data_line_valid; - -logic [511:0] data_line_array[NUM_DTPU_CLUSTERS:0]; -logic data_line_valid_array[NUM_DTPU_CLUSTERS:0]; -logic data_line_prog_array[NUM_DTPU_CLUSTERS:0]; -logic data_line_ctrl_array[NUM_DTPU_CLUSTERS:0]; -logic data_line_last_array[NUM_DTPU_CLUSTERS:0]; - -logic [2:0] data_line_last_valid_pos_array[NUM_DTPU_CLUSTERS:0]; -logic [4:0] data_line_pu_array[NUM_DTPU_CLUSTERS:0]; -logic [NUM_DTPU_CLUSTERS_BITS-1:0] data_line_cu_array[NUM_DTPU_CLUSTERS:0]; - -wire [NUM_DTPU_CLUSTERS-1:0] data_line_ready_array; - -wire [31:0] cu_tuple_result_out[NUM_DTPU_CLUSTERS-1:0]; -wire [NUM_DTPU_CLUSTERS-1:0] cu_tuple_result_out_valid; - -reg [3-NUM_DTPU_CLUSTERS_BITS:0] curr_dest_result_fifo[NUM_DTPU_CLUSTERS-1:0]; - -wire [15:0] res_fifo_we; -wire [511:0] res_fifo_dout; -wire [15:0] res_fifo_valid; -wire [15:0] res_fifo_full; -wire res_fifo_re; - - - -reg start_core_d1; - -reg [7:0] data_present_age; -reg last_tree_line_sent; -reg pipeline_emptied; -wire aligned_fifo_empty; - - -// Reset (handled badly within this core ...) -localparam integer N_RST_STG = 2; -logic [N_RST_STG:0] rst_n_int_s; -logic rst_n_int; -assign rst_n_int_s[0] = rst_n; -assign rst_n_int = rst_n_int_s[N_RST_STG]; - -always_ff @(posedge clk) begin - for(int i = 1; i <= N_RST_STG; i++) - rst_n_int_s[i] <= rst_n_int_s[i-1]; -end - -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Core Input FIFO ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -assign ctrl_line = {480'b0, 7'b0, num_lines_per_tuple, 4'h0, tree_depth, 3'b0, num_trees_per_pu_minus_one}; - - -quick_fifo #(.FIFO_WIDTH(514), // data + data valid flag + last flag + prog flags - .FIFO_DEPTH_BITS(9), - .FIFO_ALMOSTFULL_THRESHOLD(508) - ) InDataFIFO - ( - .clk (clk), - .reset_n (rst_n_int), - .din ({core_data_in_last, core_data_in_type, core_data_in}), - .we (core_data_in_valid), - - .re (in_fifo_re), - .dout ({in_fifo_data_last, in_fifo_data_type, in_fifo_data}), - .empty (), - .valid (in_fifo_valid), - .full (in_fifo_full), - .count (), - .almostfull () - ); - - -assign core_data_in_ready = ~in_fifo_full; -assign in_fifo_re = ~aligned_fifo_almfull && ((in_fifo_data_type)? in_fifo_tuples_re && pipeline_emptied : in_fifo_trees_re ); -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Tracking Trees/Tuples ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -// Trees input stream decoding -always@(posedge clk) begin - // buffer start signal - start_core_d1 <= start_core; - - // Reset the rest - if(~rst_n_int || start_core) begin - tree_length_set <= 1'b0; - tree_received_words <= 10'd0; - curr_tree_length <= 10'd0; - last_tree_line_sent <= 1'b0; - data_present_age <= 0; - end - else begin - if(in_fifo_valid && ~aligned_fifo_almfull && !in_fifo_data_type) begin - if(!tree_length_set) begin - curr_tree_length <= in_fifo_data[9:0]; - if(in_fifo_data[9:0] > 15) begin - tree_length_set <= 1'b1; - tree_received_words <= 10'd15; - end - end - else if( tree_data_in_last ) begin - tree_length_set <= 1'b0; - tree_received_words <= 10'd0; - end - else begin - tree_received_words <= tree_received_words + 10'd16; - end - if(in_fifo_data_last) begin - last_tree_line_sent <= 1'b1; - end - end - // - if(last_tree_line_sent) begin - data_present_age <= data_present_age + 1'b1; - end - end -end -// -assign tree_possible_words = (tree_length_set)? 16 : 15; -assign tree_remaining_words = (tree_length_set)? (curr_tree_length - tree_received_words) : in_fifo_data[9:0]; -assign curr_tree_line_words = (tree_remaining_words > tree_possible_words)? tree_possible_words : tree_remaining_words; -assign tree_data_in_last = (tree_remaining_words > tree_possible_words)? 1'b0 : 1'b1; -assign in_fifo_trees_re = 1'b1; - -// Tuples input stream decoding -always@(posedge clk) begin - if(~rst_n_int || start_core) begin - tuple_received_words <= 6'd0; - tuple_start_set <= 1'b0; - curr_tuple_off <= 6'd0; - - pipeline_emptied <= 1'b0; - end - else begin - if(in_fifo_valid && ~aligned_fifo_almfull && in_fifo_data_type && pipeline_emptied) begin - if(!tuple_start_set) begin - if( (6'd16 - curr_tuple_off[3:0]) < tuple_length ) begin - tuple_start_set <= 1'b1; - tuple_received_words <= 6'd16 - curr_tuple_off[3:0]; - end - end - else if( tuple_data_in_last ) begin - tuple_start_set <= 1'b0; - tuple_received_words <= 6'd0; - end - else begin - tuple_received_words <= tuple_received_words + 6'd16; - end - // Tuple offset - if( tuple_data_in_last ) begin - curr_tuple_off <= curr_tuple_off + tuple_length; - end - end - // - if((data_present_age > EMPTY_PIPELINE_WAIT_CYCLES) && aligned_fifo_empty) begin - pipeline_emptied <= 1'b1; - end - end -end - - -assign tuple_possible_words = (tuple_start_set)? 6'd16 : (6'd16 - curr_tuple_off[3:0]); -assign tuple_remaining_words = tuple_length - tuple_received_words; -assign curr_tuple_line_words = (tuple_remaining_words > tuple_possible_words)? tuple_possible_words : tuple_remaining_words; -assign tuple_data_in_last = (tuple_remaining_words > tuple_possible_words)? 1'b0 : 1'b1; -assign in_fifo_tuples_re = (tuple_data_in_last)? (tuple_remaining_words == 6'd16) : 1'b1; - -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Bus Aligner ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -assign in_fifo_item_last = (in_fifo_data_type)? tuple_data_in_last : tree_data_in_last; -assign in_fifo_data_off = (in_fifo_data_type)? curr_tuple_off[3:0] : 4'd1; -assign in_fifo_data_size_t = ((in_fifo_data_type)? tuple_length[4:0] : ((tree_length_set)? curr_tree_length[4:0] : in_fifo_data[4:0])) - 5'd1; -assign in_fifo_data_size = in_fifo_data_size_t[3:1]; -assign in_fifo_data_word_count = (in_fifo_data_type)? curr_tuple_line_words : curr_tree_line_words; - -bus_aligner bus_aligner - ( - .clk (clk), - .rst_n (rst_n_int), - - .data_in (in_fifo_data), - .data_in_last (in_fifo_item_last), - .data_in_type (in_fifo_data_type), - .data_in_valid (in_fifo_valid && ~aligned_fifo_almfull && (~in_fifo_data_type || pipeline_emptied)), - .data_in_off (in_fifo_data_off), - .data_in_size (in_fifo_data_size), - .data_in_word_count (in_fifo_data_word_count), - .stream_last (in_fifo_data_last), - - .data_out (aligner_data_out), - .data_out_last (aligner_data_out_last), - .data_out_type (aligner_data_out_type), - .data_out_size (aligner_data_out_size), - .data_out_valid (aligner_data_out_valid) - ); - -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Aligned Data FIFO ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -quick_fifo #(.FIFO_WIDTH(517), // data + data valid flag + last flag + prog flags - .FIFO_DEPTH_BITS(9), - .FIFO_ALMOSTFULL_THRESHOLD(490) - ) AlignedDataFIFO - ( - .clk (clk), - .reset_n (rst_n_int), - .din ({aligner_data_out_last, aligner_data_out_type, aligner_data_out_size, aligner_data_out}), - .we (aligner_data_out_valid), - - .re (aligned_fifo_re), - .dout ({aligned_fifo_data_last, aligned_fifo_data_type, aligned_fifo_data_size, aligned_fifo_data}), - .empty (aligned_fifo_empty), - .valid (aligned_fifo_valid), - .full (), - .count (), - .almostfull (aligned_fifo_almfull) - ); - -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Distribute Trees/Tuples ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// -// -always@(posedge clk) begin - if(~rst_n_int || start_core) begin - core_fsm_state <= IDLE; - data_line_cu <= 0; - data_line_pu <= 5'd0; - data_line_cu_d1 <= 0; - data_line_pu_d1 <= 0; - data_line_last_valid_pos <= 4'd0; - data_line_valid <= 1'b0; - data_line_last <= 1'b0; - aligned_fifo_data_type_d1<= 1'b0; - end - else begin - // - data_line_last_valid_pos <= aligned_fifo_data_size; - data_line_valid <= aligned_fifo_valid; - data_line_last <= aligned_fifo_data_last; - aligned_fifo_data_type_d1<= aligned_fifo_data_type; - data_line_cu_d1 <= data_line_cu; - data_line_pu_d1 <= data_line_pu; - // - case (core_fsm_state) - IDLE: begin - data_line_cu <= 0; - data_line_pu <= 5'd0; - - if(start_core_d1) begin - core_fsm_state <= RUN_MODE; - end - end - RUN_MODE: begin - if(aligned_fifo_valid && aligned_fifo_re) begin - if(aligned_fifo_data_type == 1'b0) begin // trees stream - // PU - if(aligned_fifo_data_last) begin - if(data_line_pu == NUM_PUS_PER_CLUSTER-1) begin - data_line_pu <= 5'd0; - end - else begin - data_line_pu <= data_line_pu + 5'd1; - end - end - // CU - data_line_cu <= 0; - end - else begin // tuples stream - // PU - data_line_pu <= 5'd0; - // CU - if(aligned_fifo_data_last) begin - if(data_line_cu == NUM_DTPU_CLUSTERS-1) begin - data_line_cu <= 0; - end - else begin - data_line_cu <= data_line_cu + 1; - end - end - end - end - end - default : begin - core_fsm_state <= IDLE; - data_line_cu <= 0; - data_line_pu <= 5'd0; - end - endcase - end - // - data_line <= aligned_fifo_data; - // -end -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Engine Clusters ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// -/*assign data_line_array[0] = (core_fsm_state == IDLE)? ctrl_line : data_line; -assign data_line_valid_array[0] = (core_fsm_state == IDLE)? 1'b0 : data_line_valid && aligned_fifo_data_type_d1 && aligned_fifo_re; -assign data_line_last_valid_pos_array[0] = (core_fsm_state == IDLE)? 3'b0 : data_line_last_valid_pos; -assign data_line_prog_array[0] = (core_fsm_state == IDLE)? 1'b0 : data_line_valid && ~aligned_fifo_data_type_d1 && aligned_fifo_re; -assign data_line_last_array[0] = (core_fsm_state == IDLE)? start_core : data_line_last; -assign data_line_ctrl_array[0] = (core_fsm_state == IDLE)? start_core : 1'b0; -assign data_line_pu_array[0] = data_line_pu_d1; -assign data_line_cu_array[0] = data_line_cu_d1; -*/ - -always@(posedge clk) begin - if(~rst_n_int) begin - data_line_ctrl_array[0] <= 0; - data_line_prog_array[0] <= 0; - data_line_valid_array[0] <= 0; - end - else begin - data_line_ctrl_array[0] <= start_core; - data_line_prog_array[0] <= (start_core || (core_fsm_state == IDLE))? 1'b0 : aligned_fifo_valid && ~aligned_fifo_data_type && aligned_fifo_re; - data_line_valid_array[0] <= (start_core || (core_fsm_state == IDLE))? 1'b0 : aligned_fifo_valid && aligned_fifo_data_type && aligned_fifo_re; - end - // - data_line_array[0] <= (start_core)? ctrl_line : aligned_fifo_data; - data_line_last_valid_pos_array[0] <= (start_core)? 3'b0 : aligned_fifo_data_size; - data_line_last_array[0] <= start_core | aligned_fifo_data_last; - - data_line_pu_array[0] <= data_line_pu; - data_line_cu_array[0] <= data_line_cu; -end - -assign aligned_fifo_re = (aligned_fifo_data_type)? data_line_ready_array[ data_line_cu ] : data_line_ready_array[0]; - - -genvar i; -generate - for (i = 0; i < NUM_DTPU_CLUSTERS; i = i + 1) begin: cus - compute_unit #(.CU_ID (i) ) - cu_x( - .clk (clk), - .rst_n (rst_n_int && ~start_core), - - .data_line_in (data_line_array[i]), - .data_line_in_valid (data_line_valid_array[i]), - .data_line_in_last_valid_pos (data_line_last_valid_pos_array[i]), - .data_line_in_last (data_line_last_array[i]), - .data_line_in_ctrl (data_line_ctrl_array[i]), - .data_line_in_prog (data_line_prog_array[i]), - .data_line_in_pu (data_line_pu_array[i]), - .data_line_in_cu (data_line_cu_array[i]), - .data_line_in_ready (data_line_ready_array[i]), - - .data_line_out (data_line_array[i+1]), - .data_line_out_valid (data_line_valid_array[i+1]), - .data_line_out_last_valid_pos (data_line_last_valid_pos_array[i+1]), - .data_line_out_last (data_line_last_array[i+1]), - .data_line_out_ctrl (data_line_ctrl_array[i+1]), - .data_line_out_prog (data_line_prog_array[i+1]), - .data_line_out_pu (data_line_pu_array[i+1]), - .data_line_out_cu (data_line_cu_array[i+1]), - - .tuple_result_out (cu_tuple_result_out[i]), - .tuple_result_out_valid (cu_tuple_result_out_valid[i]), - .tuple_result_out_ready ( ~res_fifo_full[i] ) - ); - - - // - always@(posedge clk) begin - if(~rst_n_int) begin - curr_dest_result_fifo[i] <= 0; - end - else begin - if(cu_tuple_result_out_valid[i]) begin - if(~res_fifo_full[ ({curr_dest_result_fifo[i], {NUM_DTPU_CLUSTERS_BITS{1'b0}}} + i) ]) begin - curr_dest_result_fifo[i] <= curr_dest_result_fifo[i] + 1'b1; - end - end - end -end - end -endgenerate -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Push Results Out ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// -// -generate - for (i = 0; i < 16; i = i + 1) begin: out_fifos - quick_fifo #(.FIFO_WIDTH(32), // data - .FIFO_DEPTH_BITS(9), - .FIFO_ALMOSTFULL_THRESHOLD(490) ) - ResultsFIFO_x( - .clk (clk), - .reset_n (rst_n_int), - .din ( cu_tuple_result_out[i%NUM_DTPU_CLUSTERS] ), - .we ( res_fifo_we[i] ), - - .re (res_fifo_re), - .dout (res_fifo_dout[32*i+31:i*32]), - .empty (), - .valid (res_fifo_valid[i]), - .full (res_fifo_full[i]), - .count (), - .almostfull () - ); - - assign res_fifo_we[i] = cu_tuple_result_out_valid[i%NUM_DTPU_CLUSTERS] && (curr_dest_result_fifo[i%NUM_DTPU_CLUSTERS] == (i/NUM_DTPU_CLUSTERS)); - - end -endgenerate - -assign res_fifo_re = core_result_ready && core_result_valid; -assign core_result_out = res_fifo_dout; -assign core_result_valid = &res_fifo_valid || ((&(res_fifo_valid | last_result_line_mask)) && last_result_line) ; - - -endmodule diff --git a/examples_hw/apps/gbm_dtrees/hdl/Data_Memory.sv b/examples_hw/apps/gbm_dtrees/hdl/Data_Memory.sv deleted file mode 100644 index ee541e4bf..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/Data_Memory.sv +++ /dev/null @@ -1,73 +0,0 @@ - -/* - * Copyright 2019 - 2020 Systems Group, ETH Zurich - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -module Data_Memory #( - parameter DATA_WIDTH = 32, - parameter ADDR_WIDTH = 8 -) ( - input wire clk, - input wire rst_n, - input wire we, - input wire re, - input wire [ADDR_WIDTH-1:0] raddr, - input wire [ADDR_WIDTH-2:0] waddr, - input wire [DATA_WIDTH-1:0] din, - output reg [31:0] dout, - output reg valid_out -); - -wire [DATA_WIDTH-1:0] dline; -reg raddr_d1; -reg re_d1; - - - -dual_port_mem Dualport_mem_inst ( - .clk ( clk ), - .da ( din ), - .wea ( we), - .ena ( we), - .addra ( waddr ), - - .web (1'b0), - .addrb ( raddr[ADDR_WIDTH-1:1] ), - .enb ( re ), - .qb ( dline ) - ); - - -always @(posedge clk) begin - raddr_d1 <= raddr[0]; - re_d1 <= re; - dout <= (raddr_d1)? dline[63:32] : dline[31:0]; - - if(~rst_n) begin - valid_out <= 1'b0; - end - else begin - valid_out <= re_d1; - end -end - -endmodule - diff --git a/examples_hw/apps/gbm_dtrees/hdl/FPAdder_2cycles_latency.sv b/examples_hw/apps/gbm_dtrees/hdl/FPAdder_2cycles_latency.sv deleted file mode 100644 index 178202d4e..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/FPAdder_2cycles_latency.sv +++ /dev/null @@ -1,389 +0,0 @@ -// File 2cycles_latency.vhdl translated with vhd2vl v2.4 VHDL to Verilog RTL translator -// vhd2vl settings: -// * Verilog Module Declaration Style: 1995 - -// vhd2vl is Free (libre) Software: -// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd -// http://www.ocean-logic.com -// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc -// Modifications (C) 2010 Shankar Giri -// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL -// http://doolittle.icarus.com/~larry/vhd2vl/ -// -// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting -// Verilog for correctness, ideally with a formal verification tool. -// -// You are welcome to redistribute vhd2vl under certain conditions. -// See the license (GPLv2) file included with the source for details. - -// The result of translation follows. Its copyright status should be -// considered unchanged from the original VHDL. - -//------------------------------------------------------------------------------ -// FPAdder_8_23_uid2_RightShifter -// (RightShifter_24_by_max_26_uid4) -// This operator is part of the Infinite Virtual Library FloPoCoLib -// and is distributed under the terms of the GNU Lesser General Public Licence -// with a Tobin Tax restriction (see README file for details). -// Authors: Florent de Dinechin, Bogdan Pasca (2007,2008,2009,2010) -//------------------------------------------------------------------------------ -// no timescale needed - -module FPAdder_8_23_uid2_RightShifter_l2( -X, -S, -R -); - -input [23:0] X; -input [4:0] S; -output [49:0] R; - -wire clk; -wire rst; -wire [23:0] X; -wire [4:0] S; -wire [49:0] R; - - -wire [23:0] level0; -wire [4:0] ps; -wire [24:0] level1; -wire [26:0] level2; -wire [30:0] level3; -wire [38:0] level4; -wire [54:0] level5; - - - assign level0 = X; - assign ps = S; - assign level1 = ps[0] == 1'b1 ? {1'b0,level0} : {level0,1'b0}; - assign level2 = ps[1] == 1'b1 ? {2'b00,level1} : {level1,2'b00}; - assign level3 = ps[2] == 1'b1 ? {4'b0000,level2} : {level2,4'b0000}; - assign level4 = ps[3] == 1'b1 ? {8'b00000000,level3} : {level3,8'b00000000}; - assign level5 = ps[4] == 1'b1 ? {16'b0000000000000000,level4} : {level4,16'b0000000000000000}; - assign R = level5[54:5]; - -endmodule - -//------------------------------------------------------------------------------ -// IntAdder_27_f110_uid6 -// This operator is part of the Infinite Virtual Library FloPoCoLib -// and is distributed under the terms of the GNU Lesser General Public Licence -// with a Tobin Tax restriction (see README file for details). -// Authors: Bogdan Pasca, Florent de Dinechin (2008-2010) -//------------------------------------------------------------------------------ -// Pipeline depth: 0 cycles -// no timescale needed - -module IntAdder_27_f110_uid6_l2( -X, -Y, -Cin, -R -); - -input [26:0] X; -input [26:0] Y; -input Cin; -output [26:0] R; - -wire clk; -wire rst; -wire [26:0] X; -wire [26:0] Y; -wire Cin; -wire [26:0] R; - - //Alternative - assign R = X + Y + Cin; -//------------------------------------------------------------------------------ -// LZCShifter_28_to_28_counting_32_uid16 -// This operator is part of the Infinite Virtual Library FloPoCoLib -// and is distributed under the terms of the GNU Lesser General Public Licence -// with a Tobin Tax restriction (see README file for details). -// Authors: Florent de Dinechin, Bogdan Pasca (2007) -//------------------------------------------------------------------------------ -// Pipeline depth: 1 cycles - -endmodule - -module LZCShifter_28_to_28_counting_32_uid16_l2( -clk, -stall, -I, -Count, -O -); - -input clk, stall; -input [27:0] I; -output [4:0] Count; -output [27:0] O; - -wire clk; -wire rst; -wire [27:0] I; -wire [4:0] Count; -wire [27:0] O; - - -wire [27:0] level5; -wire count4; reg count4_d1; -wire [27:0] level4; -wire count3; reg count3_d1; -wire [27:0] level3; -wire count2; reg count2_d1; -wire [27:0] level2; reg [27:0] level2_d1; -wire count1; -wire [27:0] level1; -wire count0; -wire [27:0] level0; -wire [4:0] sCount; - - always @(posedge clk) begin - if( ~stall ) begin - count4_d1 <= count4; - count3_d1 <= count3; - count2_d1 <= count2; - level2_d1 <= level2; - end - end - - assign level5 = I; - assign count4 = level5[27:12] == 16'b0000000000000000 ? 1'b1 : 1'b0; - assign level4 = count4 == 1'b0 ? level5[27:0] : {level5[11:0],16'b0000000000000000}; - assign count3 = level4[27:20] == 8'b00000000 ? 1'b1 : 1'b0; - assign level3 = count3 == 1'b0 ? level4[27:0] : {level4[19:0],8'b00000000}; - assign count2 = level3[27:24] == 4'b0000 ? 1'b 1 : 1'b0; - assign level2 = count2 == 1'b0 ? level3[27:0] : {level3[23:0],4'b0000}; - //--------------Synchro barrier, entering cycle 1---------------- - assign count1 = level2_d1[27:26] == 2'b00 ? 1'b1 : 1'b0; - assign level1 = count1 == 1'b0 ? level2_d1[27:0] : {level2_d1[25:0],2'b00}; - assign count0 = level1[27:27] == 1'b0 ? 1'b1 : 1'b0; - assign level0 = count0 == 1'b0 ? level1[27:0] : {level1[26:0],1'b0}; - assign O = level0; - assign sCount = {count4_d1,count3_d1,count2_d1,count1,count0}; - assign Count = sCount; -//------------------------------------------------------------------------------ -// IntAdder_34_f110_uid18 -// This operator is part of the Infinite Virtual Library FloPoCoLib -// and is distributed under the terms of the GNU Lesser General Public Licence -// with a Tobin Tax restriction (see README file for details). -// Authors: Bogdan Pasca, Florent de Dinechin (2008-2010) -//------------------------------------------------------------------------------ -// Pipeline depth: 0 cycles - -endmodule - -module IntAdder_34_f110_uid18_l2( -X, -Y, -Cin, -R -); - - -input [33:0] X; -input [33:0] Y; -input Cin; -output [33:0] R; - -wire [33:0] X; -wire [33:0] Y; -wire Cin; -wire [33:0] R; - - //Alternative - assign R = X + Y + Cin; -//------------------------------------------------------------------------------ -// FPAdder_8_23_uid2 -// This operator is part of the Infinite Virtual Library FloPoCoLib -// and is distributed under the terms of the GNU Lesser General Public Licence -// with a Tobin Tax restriction (see README file for details). -// Authors: Bogdan Pasca, Florent de Dinechin (2010) -//------------------------------------------------------------------------------ -// Pipeline depth: 2 cycles - -endmodule - -module FPAdder_8_23_uid2_l2( -clk, -rst, -seq_stall, -X, -Y, -R -); - -input clk, rst; -input seq_stall; -input [8 + 23 + 2:0] X; -input [8 + 23 + 2:0] Y; -output [8 + 23 + 2:0] R; - -wire clk; -wire rst; -wire [8 + 23 + 2:0] X; -wire [8 + 23 + 2:0] Y; -wire [8 + 23 + 2:0] R; - - -wire [32:0] excExpFracX; -wire [32:0] excExpFracY; -wire [8:0] eXmeY; -wire [8:0] eYmeX; -wire swap; -wire [33:0] newX; reg [33:0] newX_d1; -wire [33:0] newY; -wire [7:0] expX; reg [7:0] expX_d1; -wire [1:0] excX; -wire [1:0] excY; -wire signX; -wire signY; -wire EffSub; reg EffSub_d1; reg EffSub_d2; -wire [5:0] sdsXsYExnXY; -wire [3:0] sdExnXY; -wire [23:0] fracY; -reg [1:0] excRt; reg [1:0] excRt_d1; reg [1:0] excRt_d2; -wire signR; reg signR_d1; reg signR_d2; -wire [8:0] expDiff; -wire shiftedOut; -wire [4:0] shiftVal; -wire [49:0] shiftedFracY; reg [49:0] shiftedFracY_d1; -wire sticky; -wire [26:0] fracYfar; -wire [26:0] fracYfarXorOp; -wire [26:0] fracXfar; -wire cInAddFar; -wire [26:0] fracAddResult; -wire [27:0] fracGRS; -wire [9:0] extendedExpInc; reg [9:0] extendedExpInc_d1; -wire [4:0] nZerosNew; -wire [27:0] shiftedFrac; -wire [9:0] updatedExp; -wire eqdiffsign; -wire [33:0] expFrac; -wire stk; -wire rnd; -wire grd; -wire lsb; -wire addToRoundBit; -wire [33:0] RoundedExpFrac; -wire [1:0] upExc; -wire [22:0] fracR; -wire [7:0] expR; -wire [3:0] exExpExc; -reg [1:0] excRt2; -wire [1:0] excR; -wire [33:0] computedR; - - always @(posedge clk) begin - if( ~seq_stall)begin - newX_d1 <= newX; - expX_d1 <= expX; - EffSub_d1 <= EffSub; - EffSub_d2 <= EffSub_d1; - excRt_d1 <= excRt; - excRt_d2 <= excRt_d1; - signR_d1 <= signR; - signR_d2 <= signR_d1; - shiftedFracY_d1 <= shiftedFracY; - extendedExpInc_d1 <= extendedExpInc; - end - end - - // Exponent difference and swap -- - assign excExpFracX = {X[33:32],X[30:0]}; - assign excExpFracY = {Y[33:32],Y[30:0]}; - assign eXmeY = ({1'b 0,X[30:23]}) - ({1'b 0,Y[30:23]}); - assign eYmeX = ({1'b 0,Y[30:23]}) - ({1'b 0,X[30:23]}); - assign swap = excExpFracX >= excExpFracY ? 1'b 0 : 1'b 1; - assign newX = swap == 1'b0 ? X : Y; - assign newY = swap == 1'b0 ? Y : X; - assign expX = newX[30:23]; - assign excX = newX[33:32]; - assign excY = newY[33:32]; - assign signX = newX[31]; - assign signY = newY[31]; - assign EffSub = signX ^ signY; - assign sdsXsYExnXY = {signX,signY,excX,excY}; - assign sdExnXY = {excX,excY}; - assign fracY = excY == 2'b00 ? 24'b000000000000000000000000 : {1'b1,newY[22:0]}; - always @(*) begin - case(sdsXsYExnXY) - 6'b000000,6'b010000,6'b100000,6'b110000 : excRt <= 2'b00; - 6'b000101,6'b010101,6'b100101,6'b110101,6'b000100,6'b010100,6'b100100,6'b110100,6'b000001,6'b010001,6'b100001,6'b110001 : excRt <= 2'b01; - 6'b111010,6'b001010,6'b001000,6'b011000,6'b101000,6'b111000,6'b000010,6'b010010,6'b100010,6'b110010,6'b001001,6'b011001,6'b101001,6'b111001,6'b000110,6'b010110,6'b100110,6'b110110 : excRt <= 2'b10; - default : excRt <= 2'b 11; - endcase - end - - assign signR = (sdsXsYExnXY == 6'b100000 || sdsXsYExnXY == 6'b010000) ? 1'b0 : signX; - //-------------- cycle 0---------------- - assign expDiff = swap == 1'b0 ? eXmeY : eYmeX; - assign shiftedOut = (expDiff >= 25) ? 1'b1 : 1'b0; - assign shiftVal = shiftedOut == 1'b0 ? expDiff[4:0] : 5'b11010; - FPAdder_8_23_uid2_RightShifter_l2 RightShifterComponent( - .R(shiftedFracY), - .S(shiftVal), - .X(fracY)); - - //--------------Synchro barrier, entering cycle 1---------------- - assign sticky = (shiftedFracY_d1[23:0] == 23'b00000000000000000000000) ? 1'b0 : 1'b1; - //-------------- cycle 0---------------- - //--------------Synchro barrier, entering cycle 1---------------- - assign fracYfar = {1'b 0,shiftedFracY_d1[49:24]}; - assign fracYfarXorOp = fracYfar ^ ({EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1}); - assign fracXfar = {2'b01,(newX_d1[22:0]),2'b00}; - assign cInAddFar = EffSub_d1 & ~sticky; - IntAdder_27_f110_uid6_l2 fracAdder( - .Cin(cInAddFar), - .R(fracAddResult), - .X(fracXfar), - .Y(fracYfarXorOp)); - - assign fracGRS = {fracAddResult,sticky}; - assign extendedExpInc = ({2'b00,expX_d1}) + 1'b1; - LZCShifter_28_to_28_counting_32_uid16_l2 LZC_component( - .clk(clk), - .stall(seq_stall), - .Count(nZerosNew), - .I(fracGRS), - .O(shiftedFrac)); - - //--------------Synchro barrier, entering cycle 2---------------- - assign updatedExp = extendedExpInc_d1 - ({5'b00000,nZerosNew}); - assign eqdiffsign = nZerosNew == 5'b11111 ? 1'b1 : 1'b0; - assign expFrac = {updatedExp,shiftedFrac[26:3]}; - //-------------- cycle 2---------------- - assign stk = shiftedFrac[1] | shiftedFrac[0]; - assign rnd = shiftedFrac[2]; - assign grd = shiftedFrac[3]; - assign lsb = shiftedFrac[4]; - assign addToRoundBit = (lsb == 1'b0 && grd == 1'b1 && rnd == 1'b0 && stk == 1'b0) ? 1'b0 : 1'b1; - IntAdder_34_f110_uid18_l2 roundingAdder( - .Cin(addToRoundBit), - .R(RoundedExpFrac), - .X(expFrac), - .Y(34'b0000000000000000000000000000000000)); - - //-------------- cycle 2---------------- - assign upExc = RoundedExpFrac[33:32]; - assign fracR = RoundedExpFrac[23:1]; - assign expR = RoundedExpFrac[31:24]; - assign exExpExc = {upExc,excRt_d2}; - always @(*) begin - case((exExpExc)) - 4'b0000,4'b0100,4'b1000,4'b1100,4'b1001,4'b1101 : excRt2 <= 2'b00; - 4'b0001 : excRt2 <= 2'b01; - 4'b0010,4'b0110,4'b0101 : excRt2 <= 2'b10; - default : excRt2 <= 2'b11; - endcase - end - - assign excR = (eqdiffsign == 1'b1 && EffSub_d2 == 1'b1) ? 2'b00 : excRt2; - assign computedR = {excR,signR_d2,expR,fracR}; - assign R = computedR; - -endmodule diff --git a/examples_hw/apps/gbm_dtrees/hdl/FPAdder_3cycles_latency.v b/examples_hw/apps/gbm_dtrees/hdl/FPAdder_3cycles_latency.v deleted file mode 100644 index ab8c0e7a6..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/FPAdder_3cycles_latency.v +++ /dev/null @@ -1,458 +0,0 @@ -//------------------------------------------------------------------------------ -// FPAdder_8_23_uid2_RightShifter -// (RightShifter_24_by_max_26_uid4) -// This operator is part of the Infinite Virtual Library FloPoCoLib -// and is distributed under the terms of the GNU Lesser General Public Licence -// with a Tobin Tax restriction (see README file for details). -// Authors: Florent de Dinechin, Bogdan Pasca (2007,2008,2009,2010) -//------------------------------------------------------------------------------ -// no timescale needed - -module FPAdder_8_23_uid2_RightShifter_l3( -clk, -rst, -X, -S, -R -); - -input clk, rst; -input [23:0] X; -input [4:0] S; -output [49:0] R; - -wire clk; -wire rst; -wire [23:0] X; -wire [4:0] S; -wire [49:0] R; - - -wire [23:0] level0; -wire [4:0] ps; -wire [24:0] level1; -wire [26:0] level2; -wire [30:0] level3; -wire [38:0] level4; -wire [54:0] level5; - - - assign level0 = X; - assign ps = S; - assign level1 = ps[0] == 1'b1 ? {1'b0,level0} : {level0,1'b0}; - assign level2 = ps[1] == 1'b1 ? {2'b00,level1} : {level1,2'b00}; - assign level3 = ps[2] == 1'b1 ? {4'b0000,level2} : {level2,4'b0000}; - assign level4 = ps[3] == 1'b1 ? {8'b00000000,level3} : {level3,8'b00000000}; - assign level5 = ps[4] == 1'b1 ? {16'b0000000000000000,level4} : {level4,16'b0000000000000000}; - assign R = level5[54:5]; - -endmodule - -//------------------------------------------------------------------------------ -// IntAdder_27_f150_uid6 -// This operator is part of the Infinite Virtual Library FloPoCoLib -// and is distributed under the terms of the GNU Lesser General Public Licence -// with a Tobin Tax restriction (see README file for details). -// Authors: Bogdan Pasca, Florent de Dinechin (2008-2010) -//------------------------------------------------------------------------------ -// Pipeline depth: 0 cycles -// no timescale needed - -module IntAdder_27_f150_uid6_l3( -clk, -rst, -X, -Y, -Cin, -R -); - -input clk, rst; -input [26:0] X; -input [26:0] Y; -input Cin; -output [26:0] R; - -wire clk; -wire rst; -wire [26:0] X; -wire [26:0] Y; -wire Cin; -wire [26:0] R; - - - //Alternative - assign R = X + Y + Cin; - -endmodule - -//------------------------------------------------------------------------------ -// LZCShifter_28_to_28_counting_32_uid16 -// This operator is part of the Infinite Virtual Library FloPoCoLib -// and is distributed under the terms of the GNU Lesser General Public Licence -// with a Tobin Tax restriction (see README file for details). -// Authors: Florent de Dinechin, Bogdan Pasca (2007) -//------------------------------------------------------------------------------ -// Pipeline depth: 1 cycles -// no timescale needed - -module LZCShifter_28_to_28_counting_32_uid16_l3( -clk, -rst, -I, -Count, -O -); - -input clk, rst; -input [27:0] I; -output [4:0] Count; -output [27:0] O; - -wire clk; -wire rst; -wire [27:0] I; -wire [4:0] Count; -wire [27:0] O; -wire [27:0] level5; - -wire count4; -//reg count4_d1; -wire count4_d1; - -wire [27:0] level4; -//reg [27:0] level4_d1; -wire [27:0] level4_d1; - -wire count3; -//reg count3_d1; -wire count3_d1; - -wire [27:0] level3; -wire count2; -wire [27:0] level2; -wire count1; -wire [27:0] level1; -wire count0; -wire [27:0] level0; -wire [4:0] sCount; - - assign level5 = I; - assign count4 = level5[27:12] == 16'b0000000000000000 ? 1'b1 : 1'b0; - assign level4 = count4 == 1'b0 ? level5[27:0] : {level5[11:0],16'b0000000000000000}; - assign count3 = level4[27:20] == 8'b00000000 ? 1'b1 : 1'b0; - //--------------Synchro barrier, entering cycle 1---------------- - - /* Added by Babis */ - assign count4_d1 = count4; - assign level4_d1 = level4; - assign count3_d1 = count3; - - assign level3 = count3_d1 == 1'b0 ? level4_d1[27:0] : {level4_d1[19:0],8'b00000000}; - assign count2 = level3[27:24] == 4'b0000 ? 1'b1 : 1'b0; - assign level2 = count2 == 1'b0 ? level3[27:0] : {level3[23:0],4'b0000}; - assign count1 = level2[27:26] == 2'b00 ? 1'b1 : 1'b0; - assign level1 = count1 == 1'b0 ? level2[27:0] : {level2[25:0],2'b00}; - assign count0 = level1[27:27] == 1'b0 ? 1'b1 : 1'b0; - assign level0 = count0 == 1'b0 ? level1[27:0] : {level1[26:0],1'b0}; - assign O = level0; - assign sCount = {count4_d1,count3_d1,count2,count1,count0}; - assign Count = sCount; - -endmodule - -//------------------------------------------------------------------------------ -// IntAdder_34_f150_uid18 -// This operator is part of the Infinite Virtual Library FloPoCoLib -// and is distributed under the terms of the GNU Lesser General Public Licence -// with a Tobin Tax restriction (see README file for details). -// Authors: Bogdan Pasca, Florent de Dinechin (2008-2010) -//------------------------------------------------------------------------------ -// Pipeline depth: 0 cycles -// no timescale needed - -module IntAdder_34_f150_uid18_l3( -clk, -rst, -X, -Y, -Cin, -R -); - -input clk, rst; -input [33:0] X; -input [33:0] Y; -input Cin; -output [33:0] R; - -wire clk; -wire rst; -wire [33:0] X; -wire [33:0] Y; -wire Cin; -wire [33:0] R; - - always @(posedge clk) begin - end - - //Alternative - assign R = X + Y + Cin; - -endmodule - -//------------------------------------------------------------------------------ -// FPAdder_8_23_uid2 -// This operator is part of the Infinite Virtual Library FloPoCoLib -// and is distributed under the terms of the GNU Lesser General Public Licence -// with a Tobin Tax restriction (see README file for details). -// Authors: Bogdan Pasca, Florent de Dinechin (2010) -//------------------------------------------------------------------------------ -// Pipeline depth: 3 cycles -// no timescale needed - -module FPAdder_8_23_uid2_l3( -clk, -rst, -seq_stall, -X, -Y, -R -); - -input clk, rst, seq_stall; -input [8 + 23 + 2:0] X; -input [8 + 23 + 2:0] Y; -output [8 + 23 + 2:0] R; - -wire clk; -wire rst; -wire seq_stall; -wire [8 + 23 + 2:0] X; -wire [8 + 23 + 2:0] Y; -wire [8 + 23 + 2:0] R; - - -wire [32:0] excExpFracX; -wire [32:0] excExpFracY; -wire [8:0] eXmeY; -wire [8:0] eYmeX; -wire swap; -wire [33:0] newX; reg [33:0] newX_d1; -wire [33:0] newY; -wire [7:0] expX; reg [7:0] expX_d1; -wire [1:0] excX; -wire [1:0] excY; -wire signX; -wire signY; -wire EffSub; reg EffSub_d1; reg EffSub_d2; reg EffSub_d3; -wire [5:0] sdsXsYExnXY; -wire [3:0] sdExnXY; -wire [23:0] fracY; -reg [1:0] excRt; reg [1:0] excRt_d1; reg [1:0] excRt_d2; reg [1:0] excRt_d3; -wire signR; reg signR_d1; reg signR_d2; reg signR_d3; -wire [8:0] expDiff; -wire shiftedOut; -wire [4:0] shiftVal; -wire [49:0] shiftedFracY; - -wire sticky; -wire [26:0] fracYfar; -wire [26:0] fracYfarXorOp; -wire [26:0] fracXfar; -wire cInAddFar; -wire [26:0] fracAddResult; -wire [27:0] fracGRS; - -//added by Babis -reg [27:0] fracGRS_d1; - -wire [9:0] extendedExpInc; reg [9:0] extendedExpInc_d1; reg [9:0] extendedExpInc_d2; -wire [4:0] nZerosNew; reg [4:0] nZerosNew_d1; -wire [27:0] shiftedFrac; -reg [27:0] shiftedFrac_d1; - -//reg [49:0] shiftedFracY_d1; - -/* Added by Babis */ -reg [4:0] shiftVal_d1; -reg [23:0] fracY_d1; - -wire [9:0] updatedExp; -wire eqdiffsign; -wire [33:0] expFrac; -wire stk; reg stk_d1; -wire rnd; reg rnd_d1; -wire grd; reg grd_d1; -wire lsb; reg lsb_d1; -wire addToRoundBit; -wire [33:0] RoundedExpFrac; -wire [1:0] upExc; -wire [22:0] fracR; -wire [7:0] expR; -wire [3:0] exExpExc; -reg [1:0] excRt2; -wire [1:0] excR; -wire [33:0] computedR; - - always @(posedge clk) begin - if(rst == 1'b1) begin - newX_d1 <= {34{1'b0}}; - expX_d1 <= {8{1'b0}}; - EffSub_d1 <= 1'b 0; - EffSub_d2 <= 1'b 0; - EffSub_d3 <= 1'b 0; - excRt_d1 <= {2{1'b0}}; - excRt_d2 <= {2{1'b0}}; - excRt_d3 <= {2{1'b0}}; - signR_d1 <= 1'b0; - signR_d2 <= 1'b0; - signR_d3 <= 1'b0; - //shiftedFracY_d1 <= {50{1'b0}}; - /* Added by Babis */ - shiftVal_d1 <= {4{1'b0}}; - fracY_d1 <= {24{1'b0}}; - fracGRS_d1 <= {28{1'b0}}; - - extendedExpInc_d1 <= {10{1'b0}}; - extendedExpInc_d2 <= {10{1'b0}}; - nZerosNew_d1 <= {5{1'b0}}; - shiftedFrac_d1 <= {28{1'b0}}; - stk_d1 <= 1'b 0; - rnd_d1 <= 1'b 0; - grd_d1 <= 1'b 0; - lsb_d1 <= 1'b 0; - end - else begin - if(~seq_stall) begin - newX_d1 <= newX; - expX_d1 <= expX; - EffSub_d1 <= EffSub; - EffSub_d2 <= EffSub_d1; - EffSub_d3 <= EffSub_d2; - excRt_d1 <= excRt; - excRt_d2 <= excRt_d1; - excRt_d3 <= excRt_d2; - signR_d1 <= signR; - signR_d2 <= signR_d1; - signR_d3 <= signR_d2; - //shiftedFracY_d1 <= shiftedFracY; - /* Added by Babis */ - shiftVal_d1 <= shiftVal; - fracY_d1 <= fracY; - fracGRS_d1 <= fracGRS; - - extendedExpInc_d1 <= extendedExpInc; - extendedExpInc_d2 <= extendedExpInc_d1; - nZerosNew_d1 <= nZerosNew; - shiftedFrac_d1 <= shiftedFrac; - stk_d1 <= stk; - rnd_d1 <= rnd; - grd_d1 <= grd; - lsb_d1 <= lsb; - end - end - end - - // Exponent difference and swap -- - assign excExpFracX = {X[33:32],X[30:0]}; - assign excExpFracY = {Y[33:32],Y[30:0]}; - assign eXmeY = ({1'b0,X[30:23]}) - ({1'b0,Y[30:23]}); - assign eYmeX = ({1'b0,Y[30:23]}) - ({1'b0,X[30:23]}); - assign swap = excExpFracX >= excExpFracY ? 1'b0 : 1'b1; - assign newX = swap == 1'b0 ? X : Y; - assign newY = swap == 1'b0 ? Y : X; - assign expX = newX[30:23]; - assign excX = newX[33:32]; - assign excY = newY[33:32]; - assign signX = newX[31]; - assign signY = newY[31]; - assign EffSub = signX ^ signY; - assign sdsXsYExnXY = {signX,signY,excX,excY}; - assign sdExnXY = {excX,excY}; - assign fracY = excY == 2'b00 ? 24'b000000000000000000000000 : {1'b1, newY[22:0]}; - always @(*) begin - case(sdsXsYExnXY) - 6'b000000,6'b010000,6'b100000,6'b110000 : excRt <= 2'b00; - 6'b000101,6'b010101,6'b100101,6'b110101,6'b000100,6'b010100,6'b100100,6'b110100,6'b000001,6'b010001,6'b100001,6'b110001 : excRt <= 2'b01; - 6'b111010,6'b001010,6'b001000,6'b011000,6'b101000,6'b111000,6'b000010,6'b010010,6'b100010,6'b110010,6'b001001,6'b011001,6'b101001,6'b111001,6'b000110,6'b010110,6'b100110,6'b110110 : excRt <= 2'b10; - default : excRt <= 2'b11; - endcase - end - - assign signR = (sdsXsYExnXY == 6'b100000 || sdsXsYExnXY == 6'b010000) ? 1'b0 : signX; - //-------------- cycle 0---------------- - assign expDiff = swap == 1'b0 ? eXmeY : eYmeX; - assign shiftedOut = (expDiff >= 25) ? 1'b1 : 1'b0; - assign shiftVal = shiftedOut == 1'b0 ? expDiff[4:0] : 5'b11010; - FPAdder_8_23_uid2_RightShifter_l3 RightShifterComponent( - .clk(clk), - .rst(rst), - .R(shiftedFracY), - .S(shiftVal_d1), - .X(fracY_d1)); - - //--------------Synchro barrier, entering cycle 1---------------- - assign sticky = (shiftedFracY[23:0] == 23'b00000000000000000000000) ? 1'b0 : 1'b1; - //-------------- cycle 0---------------- - //--------------Synchro barrier, entering cycle 1---------------- - assign fracYfar = {1'b0,shiftedFracY[49:24]}; - assign fracYfarXorOp = fracYfar ^ ({EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1}); - assign fracXfar = {2'b01,(newX_d1[22:0]),2'b00}; - assign cInAddFar = EffSub_d1 & ~sticky; - IntAdder_27_f150_uid6_l3 fracAdder( - .clk(clk), - .rst(rst), - .Cin(cInAddFar), - .R(fracAddResult), - .X(fracXfar), - .Y(fracYfarXorOp)); - - assign fracGRS = {fracAddResult,sticky}; - assign extendedExpInc = ({2'b 00,expX_d1}) + 1'b 1; - LZCShifter_28_to_28_counting_32_uid16_l3 LZC_component( - .clk(clk), - .rst(rst), - .Count(nZerosNew), - .I(fracGRS_d1), /* Added by Babis */ - .O(shiftedFrac)); - - //--------------Synchro barrier, entering cycle 2---------------- - //--------------Synchro barrier, entering cycle 3---------------- - assign updatedExp = extendedExpInc_d2 - ({5'b00000,nZerosNew_d1}); - assign eqdiffsign = nZerosNew_d1 == 5'b11111 ? 1'b1 : 1'b0; - assign expFrac = {updatedExp,shiftedFrac_d1[26:3]}; - //-------------- cycle 2---------------- - assign stk = shiftedFrac[1] | shiftedFrac[0]; - assign rnd = shiftedFrac[2]; - assign grd = shiftedFrac[3]; - assign lsb = shiftedFrac[4]; - //--------------Synchro barrier, entering cycle 3---------------- - assign addToRoundBit = (lsb_d1 == 1'b 0 && grd_d1 == 1'b 1 && rnd_d1 == 1'b 0 && stk_d1 == 1'b 0) ? 1'b 0 : 1'b 1; - IntAdder_34_f150_uid18_l3 roundingAdder( - .clk(clk), - .rst(rst), - .Cin(addToRoundBit), - .R(RoundedExpFrac), - .X(expFrac), - .Y(34'b0000000000000000000000000000000000)); - - //-------------- cycle 3---------------- - assign upExc = RoundedExpFrac[33:32]; - assign fracR = RoundedExpFrac[23:1]; - assign expR = RoundedExpFrac[31:24]; - assign exExpExc = {upExc,excRt_d3}; - always @(*) begin - case((exExpExc)) - 4'b 0000,4'b 0100,4'b 1000,4'b 1100,4'b 1001,4'b 1101 : excRt2 <= 2'b 00; - 4'b 0001 : excRt2 <= 2'b 01; - 4'b 0010,4'b 0110,4'b 0101 : excRt2 <= 2'b 10; - default : excRt2 <= 2'b 11; - endcase - end - - assign excR = (eqdiffsign == 1'b 1 && EffSub_d3 == 1'b 1) ? 2'b 00 : excRt2; - assign computedR = {excR,signR_d3,expR,fracR}; - assign R = computedR; - -endmodule diff --git a/examples_hw/apps/gbm_dtrees/hdl/FPAdder_4cycles_latency.v b/examples_hw/apps/gbm_dtrees/hdl/FPAdder_4cycles_latency.v deleted file mode 100644 index f6b677ceb..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/FPAdder_4cycles_latency.v +++ /dev/null @@ -1,420 +0,0 @@ -//------------------------------------------------------------------------------ -// FPAdder_8_23_uid2_RightShifter -// (RightShifter_24_by_max_26_uid4) -// This operator is part of the Infinite Virtual Library FloPoCoLib -// and is distributed under the terms of the GNU Lesser General Public Licence -// with a Tobin Tax restriction (see README file for details). -// Authors: Florent de Dinechin, Bogdan Pasca (2007,2008,2009,2010) -//------------------------------------------------------------------------------ -// no timescale needed - -module FPAdder_8_23_uid2_RightShifter_l4( X, S, R ); - -// input/output definition - -input [23:0] X; -input [4:0] S; -output [49:0] R; - -//signals - -wire [23:0] X; -wire [4:0] S; -wire [49:0] R; - -wire [23:0] level0; -wire [4:0] ps; -wire [24:0] level1; -wire [26:0] level2; -wire [30:0] level3; -wire [38:0] level4; -wire [54:0] level5; - - assign level0 = X; - assign ps = S; - assign level1 = ps[0] == 1'b 1 ? { 1'b0,level0 } : { level0,1'b0 }; - assign level2 = ps[1] == 1'b 1 ? { 2'b00,level1 } : { level1,2'b00 }; - assign level3 = ps[2] == 1'b 1 ? { 4'b0000,level2 } : { level2,4'b0000 }; - assign level4 = ps[3] == 1'b 1 ? { 8'b00000000,level3 } : { level3,8'b00000000 }; - assign level5 = ps[4] == 1'b 1 ? { 16'b0000000000000000,level4 } : { level4,16'b0000000000000000 }; - assign R = level5[54:5]; - -endmodule - -//------------------------------------------------------------------------------ -// IntAdder_27_f200_uid6 -// This operator is part of the Infinite Virtual Library FloPoCoLib -// and is distributed under the terms of the GNU Lesser General Public Licence -// with a Tobin Tax restriction (see README file for details). -// Authors: Bogdan Pasca, Florent de Dinechin (2008-2010) -//------------------------------------------------------------------------------ -// Pipeline depth: 0 cycles -// no timescale needed - -module IntAdder_27_f200_uid6_l4( X, Y, Cin, R); - -input [26:0] X; -input [26:0] Y; -input Cin; -output [26:0] R; - -wire [26:0] X; -wire [26:0] Y; -wire Cin; -wire [26:0] R; - - //Classical - assign R = X + Y + Cin; - -endmodule - -//------------------------------------------------------------------------------ -// LZCShifter_28_to_28_counting_32_uid16 -// This operator is part of the Infinite Virtual Library FloPoCoLib -// and is distributed under the terms of the GNU Lesser General Public Licence -// with a Tobin Tax restriction (see README file for details). -// Authors: Florent de Dinechin, Bogdan Pasca (2007) -//------------------------------------------------------------------------------ -// Pipeline depth: 2 cycles -// no timescale needed - -module LZCShifter_28_to_28_counting_32_uid16_l4( clk, rst, seq_stall, I, Count, O ); - -input clk, rst; -input seq_stall; -input [27:0] I; -output [4:0] Count; -output [27:0] O; - -wire clk; -wire rst; -wire seq_stall; -wire [27:0] I; -wire [4:0] Count; -wire [27:0] O; - -wire [27:0] level5; -wire count4; reg count4_d1; reg count4_d2; -wire [27:0] level4; reg [27:0] level4_d1; -wire count3; reg count3_d1; -wire [27:0] level3; -wire count2; reg count2_d1; -wire [27:0] level2; -wire count1; reg count1_d1; -wire [27:0] level1; reg [27:0] level1_d1; -wire count0; -wire [27:0] level0; -wire [4:0] sCount; - - always @( posedge clk, posedge rst ) begin - - if( rst==1'b1 ) - begin - count4_d1 <= 0; - count4_d2 <= 0; - level4_d1 <= 0; - count3_d1 <= 0; - count2_d1 <= 0; - count1_d1 <= 0; - level1_d1 <= 0; - end - - else if(~seq_stall) - begin - count4_d1 <= count4; - count4_d2 <= count4_d1; - level4_d1 <= level4; - count3_d1 <= count3; - count2_d1 <= count2; - count1_d1 <= count1; - level1_d1 <= level1; - end - end - - assign level5 = I; - assign count4 = level5[27:12] == 16'b0000000000000000 ? 1'b1 : 1'b0; - assign level4 = count4 == 1'b 0 ? level5[27:0] : { level5[11:0],16'b0000000000000000 }; - - //--------------Synchro barrier, entering cycle 1---------------- - assign count3 = level4_d1[27:20] == 8'b00000000 ? 1'b1 : 1'b0; - assign level3 = count3 == 1'b 0 ? level4_d1[27:0] : { level4_d1[19:0],8'b00000000 }; - assign count2 = level3[27:24] == 4'b0000 ? 1'b1 : 1'b0; - assign level2 = count2 == 1'b 0 ? level3[27:0] : { level3[23:0],4'b0000 }; - assign count1 = level2[27:26] == 2'b00 ? 1'b1 : 1'b0; - assign level1 = count1 == 1'b 0 ? level2[27:0] : { level2[25:0],2'b00 }; - - //--------------Synchro barrier, entering cycle 2---------------- - assign count0 = level1_d1[27:27] == 1'b0 ? 1'b 1 : 1'b0; - assign level0 = count0 == 1'b0 ? level1_d1[27:0] : { level1_d1[26:0],1'b0 }; - assign O = level0; - assign sCount = { count4_d2,count3_d1,count2_d1,count1_d1,count0 }; - assign Count = sCount; - -endmodule - -//------------------------------------------------------------------------------ -// IntAdder_34_f200_uid18 -// This operator is part of the Infinite Virtual Library FloPoCoLib -// and is distributed under the terms of the GNU Lesser General Public Licence -// with a Tobin Tax restriction (see README file for details). -// Authors: Bogdan Pasca, Florent de Dinechin (2008-2010) -//------------------------------------------------------------------------------ -// Pipeline depth: 1 cycles -// no timescale needed - -module IntAdder_34_f200_uid18_l4( clk, rst, seq_stall, X, Y, Cin, R ); - -input clk, rst; -input seq_stall; -input [33:0] X; -input [33:0] Y; -input Cin; -output [33:0] R; - -wire clk; -wire rst; -wire seq_stall; -wire [33:0] X; -wire [33:0] Y; -wire Cin; -wire [33:0] R; - -reg [33:0] X_d1; -reg [33:0] Y_d1; -reg Cin_d1; - - always @(posedge clk, posedge rst) begin - - if ( rst == 1'b1 ) - begin - X_d1 <= 0; - Y_d1 <= 0; - Cin_d1 <= 0; - end - - else if(~seq_stall) - begin - X_d1 <= X; - Y_d1 <= Y; - Cin_d1 <= Cin; - end - end - - //Classical - //--------------Synchro barrier, entering cycle 1---------------- - - assign R = X_d1 + Y_d1 + Cin_d1; - -endmodule - -//------------------------------------------------------------------------------ -// FPAdder_8_23_uid2 -// This operator is part of the Infinite Virtual Library FloPoCoLib -// and is distributed under the terms of the GNU Lesser General Public Licence -// with a Tobin Tax restriction (see README file for details). -// Authors: Bogdan Pasca, Florent de Dinechin (2010) -//------------------------------------------------------------------------------ -// Pipeline depth: 4 cycles -// no timescale needed - -module FPAdder_8_23_uid2_l4( clk, rst, seq_stall, X, Y, R); - -input clk, rst; -input seq_stall; -input [8 + 23 + 2:0] X; -input [8 + 23 + 2:0] Y; -output [8 + 23 + 2:0] R; - -wire clk; -wire rst; -wire seq_stall; -wire [8 + 23 + 2:0] X; -wire [8 + 23 + 2:0] Y; -wire [8 + 23 + 2:0] R; - -wire [32:0] excExpFracX; -wire [32:0] excExpFracY; -wire [8:0] eXmeY; -wire [8:0] eYmeX; -wire swap; -wire [33:0] newX; reg [33:0] newX_d1; -wire [33:0] newY; -wire [7:0] expX; reg [7:0] expX_d1; -wire [1:0] excX; -wire [1:0] excY; -wire signX; -wire signY; -wire EffSub; reg EffSub_d1; reg EffSub_d2; reg EffSub_d3; reg EffSub_d4; -wire [5:0] sdsXsYExnXY; -wire [3:0] sdExnXY; -wire [23:0] fracY; -reg [1:0] excRt; reg [1:0] excRt_d1; reg [1:0] excRt_d2; reg [1:0] excRt_d3; reg [1:0] excRt_d4; -wire signR; reg signR_d1; reg signR_d2; reg signR_d3; reg signR_d4; -wire [8:0] expDiff; -wire shiftedOut; -wire [4:0] shiftVal; -wire [49:0] shiftedFracY; reg [49:0] shiftedFracY_d1; -wire sticky; -wire [26:0] fracYfar; -wire [26:0] fracYfarXorOp; -wire [26:0] fracXfar; -wire cInAddFar; -wire [26:0] fracAddResult; -wire [27:0] fracGRS; -wire [9:0] extendedExpInc; reg [9:0] extendedExpInc_d1; reg [9:0] extendedExpInc_d2; -wire [4:0] nZerosNew; -wire [27:0] shiftedFrac; -wire [9:0] updatedExp; -wire eqdiffsign; reg eqdiffsign_d1; -wire [33:0] expFrac; -wire stk; -wire rnd; -wire grd; -wire lsb; -wire addToRoundBit; -wire [33:0] RoundedExpFrac; -wire [1:0] upExc; -wire [22:0] fracR; -wire [7:0] expR; -wire [3:0] exExpExc; -reg [1:0] excRt2; -wire [1:0] excR; -wire [33:0] computedR; - - always @(posedge clk) begin - - if(~seq_stall) - begin - newX_d1 <= newX; - expX_d1 <= expX; - EffSub_d1 <= EffSub; - EffSub_d2 <= EffSub_d1; - EffSub_d3 <= EffSub_d2; - EffSub_d4 <= EffSub_d3; - excRt_d1 <= excRt; - excRt_d2 <= excRt_d1; - excRt_d3 <= excRt_d2; - excRt_d4 <= excRt_d3; - signR_d1 <= signR; - signR_d2 <= signR_d1; - signR_d3 <= signR_d2; - signR_d4 <= signR_d3; - shiftedFracY_d1 <= shiftedFracY; - extendedExpInc_d1 <= extendedExpInc; - extendedExpInc_d2 <= extendedExpInc_d1; - eqdiffsign_d1 <= eqdiffsign; - end - end - - // Exponent difference and swap -- - - assign excExpFracX = {X[33:32],X[30:0]}; - assign excExpFracY = {Y[33:32],Y[30:0]}; - assign eXmeY = ({1'b0,X[30:23]}) - ({1'b0,Y[30:23]}); - assign eYmeX = ({1'b0,Y[30:23]}) - ({1'b0,X[30:23]}); - assign swap = excExpFracX >= excExpFracY ? 1'b0 : 1'b1; - assign newX = swap == 1'b0 ? X : Y; - assign newY = swap == 1'b0 ? Y : X; - assign expX = newX[30:23]; - assign excX = newX[33:32]; - assign excY = newY[33:32]; - assign signX = newX[31]; - assign signY = newY[31]; - assign EffSub = signX ^ signY; - assign sdsXsYExnXY = {signX,signY,excX,excY}; - assign sdExnXY = {excX,excY}; - assign fracY = excY == 2'b00 ? 24'b000000000000000000000000 : {1'b 1,newY[22:0]}; - - always @(*) begin - case(sdsXsYExnXY) - 6'b000000,6'b010000,6'b100000,6'b110000 : excRt <= 2'b00; - 6'b000101,6'b010101,6'b100101,6'b110101,6'b000100,6'b010100,6'b100100,6'b110100,6'b000001,6'b010001,6'b100001,6'b110001 : excRt <= 2'b01; - 6'b111010,6'b001010,6'b001000,6'b011000,6'b101000,6'b111000,6'b000010,6'b010010,6'b100010,6'b110010,6'b001001,6'b011001,6'b101001,6'b111001,6'b000110,6'b010110,6'b100110,6'b110110 : excRt <= 2'b10; - default : excRt <= 2'b11; - endcase - end - - assign signR = (sdsXsYExnXY == 6'b100000 || sdsXsYExnXY == 6'b010000) ? 1'b0 : signX; - - //-------------- cycle 0---------------- - assign expDiff = swap == 1'b0 ? eXmeY : eYmeX; - assign shiftedOut = (expDiff >= 25) ? 1'b1 : 1'b0; - assign shiftVal = shiftedOut == 1'b0 ? expDiff[4:0] : 5'b11010; - - FPAdder_8_23_uid2_RightShifter_l4 RightShifterComponent( - .R(shiftedFracY), - .S(shiftVal), - .X(fracY)); - - //--------------Synchro barrier, entering cycle 1---------------- - assign sticky = (shiftedFracY_d1[23:0] == 23'b00000000000000000000000) ? 1'b0 : 1'b1; - - //-------------- cycle 0---------------- - - //--------------Synchro barrier, entering cycle 1---------------- - - assign fracYfar = {1'b 0,shiftedFracY_d1[49:24]}; - assign fracYfarXorOp = fracYfar ^({EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1,EffSub_d1}); - assign fracXfar = {2'b 01,(newX_d1[22:0]),2'b 00}; - assign cInAddFar = EffSub_d1 & ~sticky; - - IntAdder_27_f200_uid6_l4 fracAdder( - .Cin(cInAddFar), - .R(fracAddResult), - .X(fracXfar), - .Y(fracYfarXorOp)); - - assign fracGRS = {fracAddResult,sticky}; - assign extendedExpInc = ( {2'b00,expX_d1} ) + 1'b1; - - LZCShifter_28_to_28_counting_32_uid16_l4 LZC_component( - .clk(clk), - .rst(rst), - .seq_stall(seq_stall), - .Count(nZerosNew), - .I(fracGRS), - .O(shiftedFrac)); - - //--------------Synchro barrier, entering cycle 3---------------- - assign updatedExp = extendedExpInc_d2 - ({5'b00000,nZerosNew}); - assign eqdiffsign = nZerosNew == 5'b11111 ? 1'b1 : 1'b0; - assign expFrac = {updatedExp,shiftedFrac[26:3]}; - //-------------- cycle 3---------------- - - assign stk = shiftedFrac[1] | shiftedFrac[0]; - assign rnd = shiftedFrac[2]; - assign grd = shiftedFrac[3]; - assign lsb = shiftedFrac[4]; - assign addToRoundBit = (lsb == 1'b0 && grd == 1'b1 && rnd == 1'b0 && stk == 1'b0) ? 1'b0 : 1'b1; - - IntAdder_34_f200_uid18_l4 roundingAdder( - .clk(clk), - .rst(rst), - .seq_stall(seq_stall), - .Cin(addToRoundBit), - .R(RoundedExpFrac), - .X(expFrac), - .Y(34'b0000000000000000000000000000000000)); - - //-------------- cycle 4---------------- - - assign upExc = RoundedExpFrac[33:32]; - assign fracR = RoundedExpFrac[23:1]; - assign expR = RoundedExpFrac[31:24]; - assign exExpExc = {upExc,excRt_d4}; - - always @(*) begin - case((exExpExc)) - 4'b0000,4'b0100,4'b1000,4'b1100,4'b1001,4'b1101 : excRt2 <= 2'b00; - 4'b0001 : excRt2 <= 2'b01; - 4'b0010,4'b0110,4'b0101 : excRt2 <= 2'b10; - default : excRt2 <= 2'b 11; - endcase - end - - assign excR = (eqdiffsign_d1 == 1'b1 && EffSub_d4 == 1'b1) ? 2'b00 : excRt2; - assign computedR = {excR,signR_d4,expR,fracR}; - assign R = computedR; - -endmodule - diff --git a/examples_hw/apps/gbm_dtrees/hdl/FPAddersReduceTree.sv b/examples_hw/apps/gbm_dtrees/hdl/FPAddersReduceTree.sv deleted file mode 100644 index f4d88c2d3..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/FPAddersReduceTree.sv +++ /dev/null @@ -1,156 +0,0 @@ - -/* - * Copyright 2019 - 2020 Systems Group, ETH Zurich - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - - -module FPAddersReduceTree #(parameter NUM_FP_POINTS = 8, - parameter FP_ADDER_LATENCY = 3) - ( - input wire clk, - input wire rst_n, - - input wire [31:0] fp_in_vector[NUM_FP_POINTS-1:0], - input wire fp_in_vector_valid[NUM_FP_POINTS-1:0], - input wire fp_in_vector_last[NUM_FP_POINTS-1:0], - - output wire [31:0] reduce_out, - output wire reduce_out_valid, - input wire reduce_out_ready - ); - - -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Local Parameters ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -localparam NUM_TREE_LEVELS = (NUM_FP_POINTS <= 2 )? 1 : - (NUM_FP_POINTS <= 4 )? 2 : - (NUM_FP_POINTS <= 8 )? 3 : - (NUM_FP_POINTS <= 16)? 4 : - (NUM_FP_POINTS <= 32)? 5 : 6; - - -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Signals Declarations ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -wire [33:0] tree_data[NUM_TREE_LEVELS:0][(NUM_FP_POINTS>>1)-1:0][1:0]; -wire [31:0] tree_out; - -wire fp_in_valid_delayed; -wire fp_in_last_delayed; - - -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// FP Adders Tree ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// -// first level of tree adders -generate - genvar i; - for (i = 0; i < (NUM_FP_POINTS>>1); i = i + 1) - begin:treeLevel1 - - assign tree_data[0][i][0] = {1'b0, {|(fp_in_vector[i<<1])}, fp_in_vector[i<<1] }; - assign tree_data[0][i][1] = {1'b0, {|(fp_in_vector[(i<<1)+1])}, fp_in_vector[(i<<1)+1] }; - - FPAdder_8_23_uid2_l3 fpadder_1_x( - .clk (clk), - .rst (~rst_n), - .seq_stall (1'b0), - .X (tree_data[0][i][0]), - .Y (tree_data[0][i][1]), - .R (tree_data[1][i>>1][i%2]) - ); - end -endgenerate - -// the rest of levels -generate - genvar j; - for (i = 1; i < NUM_TREE_LEVELS; i = i + 1) - begin:treeLevels - for (j = 0; j < (NUM_FP_POINTS >> (i+1)); j = j + 1) - begin:levelAdders - FPAdder_8_23_uid2_l3 fpadder_i_x( - .clk (clk), - .rst (~rst_n), - .seq_stall (1'b0), - .X (tree_data[i][j][0]), - .Y (tree_data[i][j][1]), - .R (tree_data[i+1][j>>1][j%2]) - ); - end - end -endgenerate - -// delay valid and last -delay #(.DATA_WIDTH(1), - .DELAY_CYCLES(FP_ADDER_LATENCY*NUM_TREE_LEVELS) - ) fpadder_delay( - - .clk (clk), - .rst_n (rst_n), - .data_in (fp_in_vector_last[0]), // - .data_in_valid (fp_in_vector_valid[0]), - .data_out (fp_in_last_delayed), - .data_out_valid (fp_in_valid_delayed) - ); - -// assign tree output -assign tree_out = (tree_data[NUM_TREE_LEVELS][0][0][33:32] == 2'b00)? 0 : tree_data[NUM_TREE_LEVELS][0][0][31:0]; - -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// FP Aggregator ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -FPAggregator #(.FP_ADDER_LATENCY(2)) - - tree_aggregator( - - .clk (clk), - .rst_n (rst_n), - - .fp_in (tree_out), - .fp_in_valid (fp_in_valid_delayed), - .fp_in_last (fp_in_last_delayed), - .fp_in_ready (), - - .aggreg_out (reduce_out), - .aggreg_out_valid (reduce_out_valid), - .aggreg_out_ready (reduce_out_ready) - ); - - - - - - -endmodule - diff --git a/examples_hw/apps/gbm_dtrees/hdl/FPAddersReduceTree_sync.sv b/examples_hw/apps/gbm_dtrees/hdl/FPAddersReduceTree_sync.sv deleted file mode 100644 index 6d7972174..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/FPAddersReduceTree_sync.sv +++ /dev/null @@ -1,286 +0,0 @@ - -/* - * Copyright 2019 - 2020 Systems Group, ETH Zurich - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - - -module FPAddersReduceTree_sync #(parameter NUM_FP_POINTS = 8, - parameter FP_ADDER_LATENCY = 3) - ( - input wire clk, - input wire rst_n, - - input wire [31:0] fp_in_vector[NUM_FP_POINTS-1:0], - input wire fp_in_vector_valid[NUM_FP_POINTS-1:0], - input wire fp_in_vector_last[NUM_FP_POINTS-1:0], - - output wire [31:0] reduce_out, - output wire reduce_out_valid, - input wire reduce_out_ready - ); - - - -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Signals Declarations ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -wire [33:0] tree_data_il1[27:0]; -wire [33:0] tree_data_ol1[13:0]; - -wire [33:0] tree_data_il2[13:0]; -wire [33:0] tree_data_ol2[6:0]; - -wire [33:0] tree_data_il3[6:0]; -wire [33:0] tree_data_ol3[3:0]; - -wire [33:0] tree_data_il4[3:0]; -wire [33:0] tree_data_ol4[1:0]; - -wire [33:0] tree_data_il5[1:0]; -wire [33:0] tree_data_ol5; - -reg [31:0] tree_out; - -wire fp_in_valid_delayed; -wire fp_in_last_delayed; - -genvar i; -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// FP Adders Tree ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// -// Level 0: introduce delay on even words - -generate for (i = 0; i < 28; i=i+1) begin : Level0 - if(i%2 == 0) begin - delay #(.DATA_WIDTH(34), - .DELAY_CYCLES(1) - ) level0_regs - ( - .clk (clk), - .rst_n (rst_n), - .data_in ({1'b0, {|(fp_in_vector[i])}, fp_in_vector[i]}), // - .data_in_valid (1'b0), - .data_out (tree_data_il1[i]), - .data_out_valid () - ); - end - else begin - assign tree_data_il1[i] = {1'b0, {|(fp_in_vector[i])}, fp_in_vector[i] }; - end -end -endgenerate - -// Level 1: Adders -generate for (i = 0; i < 28; i = i + 2) begin:treeLevel1 - - FPAdder_8_23_uid2_l3 fpadder_l1 - ( - .clk (clk), - .rst (~rst_n), - .seq_stall (1'b0), - .X (tree_data_il1[i]), - .Y (tree_data_il1[i+1]), - .R (tree_data_ol1[i/2]) - ); - - if(i%4 == 0) begin - delay #(.DATA_WIDTH(34), - .DELAY_CYCLES(2) - ) level1_regs - ( - .clk (clk), - .rst_n (rst_n), - .data_in (tree_data_ol1[i/2]), // - .data_in_valid (1'b0), - .data_out (tree_data_il2[i/2]), - .data_out_valid () - ); - end - else begin - assign tree_data_il2[i/2] = tree_data_ol1[i/2]; - end -end -endgenerate - -// Level 2: Adders -generate for (i = 0; i < 14; i = i + 2) begin:treeLevel2 - - FPAdder_8_23_uid2_l3 fpadder_l2 - ( - .clk (clk), - .rst (~rst_n), - .seq_stall (1'b0), - .X (tree_data_il2[i]), - .Y (tree_data_il2[i+1]), - .R (tree_data_ol2[i/2]) - ); - - if((i%4 == 0) && (i < 12)) begin - delay #(.DATA_WIDTH(34), - .DELAY_CYCLES(4) - ) level2_regs - ( - .clk (clk), - .rst_n (rst_n), - .data_in (tree_data_ol2[i/2]), // - .data_in_valid (1'b0), - .data_out (tree_data_il3[i/2]), - .data_out_valid () - ); - end - else begin - assign tree_data_il3[i/2] = tree_data_ol2[i/2]; - end -end -endgenerate -// Level 3: Adders -generate for (i = 0; i < 7; i = i + 2) begin:treeLevel3 -if(i < 6) begin - FPAdder_8_23_uid2_l3 fpadder_l3 - ( - .clk (clk), - .rst (~rst_n), - .seq_stall (1'b0), - .X (tree_data_il3[i]), - .Y (tree_data_il3[i+1]), - .R (tree_data_ol3[i/2]) - ); - - if(i%4 == 0) begin - delay #(.DATA_WIDTH(34), - .DELAY_CYCLES( (i == 0)?8:1) - ) level3_regs - ( - .clk (clk), - .rst_n (rst_n), - .data_in (tree_data_ol3[i/2]), // - .data_in_valid (1'b0), - .data_out (tree_data_il4[i/2]), - .data_out_valid () - ); - end - else begin - assign tree_data_il4[i/2] = tree_data_ol3[i/2]; - end -end -else begin - assign tree_data_il4[i/2] = tree_data_il3[i]; -end -end -endgenerate - -// Level 4: Adders -generate for (i = 0; i < 4; i = i + 2) begin:treeLevel4 - - FPAdder_8_23_uid2_l3 fpadder_l4 - ( - .clk (clk), - .rst (~rst_n), - .seq_stall (1'b0), - .X (tree_data_il4[i]), - .Y (tree_data_il4[i+1]), - .R (tree_data_ol4[i/2]) - ); - - if(i%4 == 0) begin - delay #(.DATA_WIDTH(34), - .DELAY_CYCLES(9) - ) level4_regs - ( - .clk (clk), - .rst_n (rst_n), - .data_in (tree_data_ol4[i/2]), // - .data_in_valid (1'b0), - .data_out (tree_data_il5[i/2]), - .data_out_valid () - ); - end - else begin - assign tree_data_il5[i/2] = tree_data_ol4[i/2]; - end -end -endgenerate - -// Level 5: Adders - - FPAdder_8_23_uid2_l3 fpadder_l5 - ( - .clk (clk), - .rst (~rst_n), - .seq_stall (1'b0), - .X (tree_data_il5[0]), - .Y (tree_data_il5[1]), - .R (tree_data_ol5) - ); - -// delay valid and last -delay #(.DATA_WIDTH(1), - .DELAY_CYCLES(FP_ADDER_LATENCY*5 + 1 + 24) - ) fpadder_delay( - - .clk (clk), - .rst_n (rst_n), - .data_in (fp_in_vector_last[0]), // - .data_in_valid (fp_in_vector_valid[0]), - .data_out (fp_in_last_delayed), - .data_out_valid (fp_in_valid_delayed) - ); - -// assign tree output -always@(posedge clk) begin - tree_out <= (tree_data_ol5[33:32] == 2'b00)? 0 : tree_data_ol5[31:0]; -end - -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// FP Aggregator ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -FPAggregator #(.FP_ADDER_LATENCY(3)) - - tree_aggregator( - - .clk (clk), - .rst_n (rst_n), - - .fp_in (tree_out), - .fp_in_valid (fp_in_valid_delayed), - .fp_in_last (fp_in_last_delayed), - .fp_in_ready (), - - .aggreg_out (reduce_out), - .aggreg_out_valid (reduce_out_valid), - .aggreg_out_ready (reduce_out_ready) - ); - - - - - - -endmodule - diff --git a/examples_hw/apps/gbm_dtrees/hdl/FPAggregator.sv b/examples_hw/apps/gbm_dtrees/hdl/FPAggregator.sv deleted file mode 100644 index 4124cd2f2..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/FPAggregator.sv +++ /dev/null @@ -1,174 +0,0 @@ - -/* - * Copyright 2019 - 2020 Systems Group, ETH Zurich - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -module FPAggregator #(parameter FP_ADDER_LATENCY = 2) ( - - input wire clk, - input wire rst_n, - - input wire [31:0] fp_in, - input wire fp_in_valid, - input wire fp_in_last, - output wire fp_in_ready, - - output wire [31:0] aggreg_out, - output wire aggreg_out_valid, - input wire aggreg_out_ready - ); - - - - -wire aggreg_in_fifo_full; -wire aggreg_in_fifo_valid; -wire aggreg_in_fifo_re; -wire [32:0] aggreg_in_fifo_dout; - -wire [33:0] input_A; -reg [33:0] prev_aggreg_value; -wire [33:0] aggreg_value; -reg [3:0] fpadder_latency_count; - - -wire fp_in_valid_delayed; -wire fp_in_last_delayed; -wire aggregator_ready; - -reg [31:0] aggreg_out_d1; -reg aggreg_out_valid_d1; - -wire aggreg_out_fifo_almfull; -//////////////////////////////////////////////////////////////////////////////// -assign fp_in_ready = ~aggreg_in_fifo_full; - -quick_fifo #(.FIFO_WIDTH(32+1), - .FIFO_DEPTH_BITS(9), - .FIFO_ALMOSTFULL_THRESHOLD(508) - ) aggreg_in_fifo ( - .clk (clk), - .reset_n (rst_n), - .din ({fp_in_last, fp_in}), - .we (fp_in_valid), - - .re (aggreg_in_fifo_re), - .dout (aggreg_in_fifo_dout), - .empty (), - .valid (aggreg_in_fifo_valid), - .full (aggreg_in_fifo_full), - .count (), - .almostfull () - ); - -assign aggreg_in_fifo_re = aggregator_ready; -//////////////////////////////////////////////////////////////////////////////// - -always @(posedge clk) begin - if (~rst_n) begin - // reset - prev_aggreg_value <= 0; - fpadder_latency_count <= 0; - aggreg_out_valid_d1 <= 1'b0; - aggreg_out_d1 <= 0; - end - else begin - if(aggregator_ready & aggreg_in_fifo_valid) begin - fpadder_latency_count <= FP_ADDER_LATENCY; - end - else if(!(fpadder_latency_count == 0)) begin - fpadder_latency_count <= fpadder_latency_count - 1'b1; - end - //--------------------- Do aggregation --------------------------// - if(fp_in_valid_delayed) begin - if(~fp_in_last_delayed) begin - prev_aggreg_value <= aggreg_value; - end - else begin - prev_aggreg_value <= 0; - end - end - - //--------------------- Tuple Output ----------------------------// - aggreg_out_valid_d1 <= 1'b0; - - if(fp_in_valid_delayed & fp_in_last_delayed) begin - if(aggreg_value[33:32] == 2'b00) begin - aggreg_out_d1 <= 0; - end - else begin - aggreg_out_d1 <= aggreg_value[31:0]; - end - - aggreg_out_valid_d1 <= 1'b1; - end - end -end - -assign aggregator_ready = (fpadder_latency_count == 0) & ~aggreg_out_fifo_almfull; - -assign input_A = {1'b0, {|(aggreg_in_fifo_dout[31:0])}, aggreg_in_fifo_dout[31:0]}; - -FPAdder_8_23_uid2_l3 fpadder( - .clk (clk), - .rst (~rst_n), - .seq_stall (1'b0), - .X (input_A), - .Y (prev_aggreg_value), - .R (aggreg_value) - ); - -// delay valid, last with FPAdder Latency -delay #(.DATA_WIDTH(1), - .DELAY_CYCLES(FP_ADDER_LATENCY) - ) fpadder_delay( - - .clk (clk), - .rst_n (rst_n), - .data_in (aggreg_in_fifo_dout[32]), // - .data_in_valid (aggreg_in_fifo_valid & aggregator_ready), - .data_out (fp_in_last_delayed), - .data_out_valid (fp_in_valid_delayed) - ); - - -quick_fifo #(.FIFO_WIDTH(32), - .FIFO_DEPTH_BITS(9), - .FIFO_ALMOSTFULL_THRESHOLD(490) - ) aggreg_out_fifo ( - .clk (clk), - .reset_n (rst_n), - .din (aggreg_out_d1), - .we (aggreg_out_valid_d1), - - .re (aggreg_out_ready), - .dout (aggreg_out), - .empty (), - .valid (aggreg_out_valid), - .full (), - .count (), - .almostfull (aggreg_out_fifo_almfull) - ); - - - - -endmodule diff --git a/examples_hw/apps/gbm_dtrees/hdl/LineRateConvertor.sv b/examples_hw/apps/gbm_dtrees/hdl/LineRateConvertor.sv deleted file mode 100644 index dfbb6f8a1..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/LineRateConvertor.sv +++ /dev/null @@ -1,134 +0,0 @@ - -/* - * Copyright 2019 - 2020 Systems Group, ETH Zurich - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -import DTPackage::*; - - -module LineRateConvertor #(parameter CU_ID = 0 ) - ( - input wire clk, - input wire rst_n, - - input wire [511:0] data_line_in, - input wire data_line_in_valid, - input wire [2:0] data_line_in_last_valid_pos, - input wire data_line_in_last, - input wire data_line_in_ctrl, - input wire data_line_in_prog, - input wire [NUM_PUS_PER_CLUSTER_BITS-1:0] data_line_in_pu, - input wire [NUM_DTPU_CLUSTERS_BITS-1:0] data_line_in_cu, - output wire data_line_in_ready, - - output reg [DATA_LINE_WIDTH-1:0] data_line_out, - output reg data_line_out_valid, - output reg data_line_out_ctrl, - output reg data_line_out_last, - output reg data_line_out_prog, - output reg [NUM_PUS_PER_CLUSTER_BITS-1:0] data_line_out_pu, - input wire data_line_out_ready -); - - -wire data_line_fifo_we; -wire data_line_fifo_almfull; -wire data_line_fifo_valid; -wire data_line_fifo_re; - -wire [63:0] data_line_array[7:0]; - -wire [511:0] data_line_in_fifo_data; -wire data_line_in_fifo_valid; -wire [2:0] data_line_in_fifo_last_valid_pos; -wire data_line_in_fifo_last; -wire data_line_in_fifo_ctrl; -wire data_line_in_fifo_prog; -wire [NUM_PUS_PER_CLUSTER_BITS-1:0] data_line_in_fifo_pu; - -reg [2:0] curr_word; - -///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -assign data_line_fifo_we = (data_line_in_valid && (data_line_in_cu == CU_ID)) || data_line_in_ctrl || data_line_in_prog; -assign data_line_in_ready = ~data_line_fifo_almfull; - -// Input Line FIFO -quick_fifo #(.FIFO_WIDTH(512+3+1+1+1+1+5), - .FIFO_DEPTH_BITS(9), - .FIFO_ALMOSTFULL_THRESHOLD(500) - ) data_line_fifo ( - .clk (clk), - .reset_n (rst_n), - .din ({data_line_in_pu, data_line_in_prog, data_line_in_ctrl, data_line_in_last, data_line_in_valid, data_line_in_last_valid_pos, data_line_in}), - .we (data_line_fifo_we), - - .re (data_line_fifo_re), - .dout ({data_line_in_fifo_pu, data_line_in_fifo_prog, data_line_in_fifo_ctrl, data_line_in_fifo_last, data_line_in_fifo_valid, data_line_in_fifo_last_valid_pos, data_line_in_fifo_data}), - .empty (), - .valid (data_line_fifo_valid), - .full (), - .count (), - .almostfull (data_line_fifo_almfull) - ); - - -// Put the input data line in an array -genvar i; -generate for (i = 0; i < 8; i=i+1) begin - assign data_line_array[i] = data_line_in_fifo_data[64*i+63:64*i]; -end -endgenerate - -// Select output 64-bit word -always@(posedge clk) begin - data_line_out <= data_line_array[ curr_word ]; - data_line_out_valid <= data_line_fifo_valid && data_line_in_fifo_valid && data_line_out_ready; - data_line_out_last <= data_line_in_fifo_last && (curr_word == data_line_in_fifo_last_valid_pos); - data_line_out_ctrl <= data_line_fifo_valid && data_line_in_fifo_ctrl; - data_line_out_prog <= data_line_fifo_valid && data_line_in_fifo_prog; - data_line_out_pu <= data_line_in_fifo_pu; -end - -// data_line_fifo_re -assign data_line_fifo_re = data_line_out_ready && ( (data_line_in_fifo_last && (curr_word == data_line_in_fifo_last_valid_pos)) || (curr_word == 3'b111) ); - -// curr_word calculation -always@(posedge clk) begin - if(~rst_n) begin - curr_word <= 3'b000; - end - else begin - if(data_line_out_ready && data_line_fifo_valid) begin - if(data_line_in_fifo_last && (curr_word == data_line_in_fifo_last_valid_pos) ) begin - curr_word <= 3'b000; - end - else if(curr_word == 3'b111) begin - curr_word <= 3'b000; - end - else begin - curr_word <= curr_word + 1'b1; - end - end - end -end - - -endmodule \ No newline at end of file diff --git a/examples_hw/apps/gbm_dtrees/hdl/RegBasedFIFO.sv b/examples_hw/apps/gbm_dtrees/hdl/RegBasedFIFO.sv deleted file mode 100644 index 19b8a46ea..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/RegBasedFIFO.sv +++ /dev/null @@ -1,122 +0,0 @@ - -/* - * Copyright 2019 - 2020 Systems Group, ETH Zurich - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -module RegBasedFIFO #(parameter FIFO_WIDTH = 32, - parameter FIFO_DEPTH_BITS = 2 - )( - input wire clk, - input wire rst_n, - - input wire [FIFO_WIDTH-1:0] data_in, - input wire data_in_valid, - output wire data_in_ready, - - output wire [FIFO_WIDTH-1:0] data_out, - output wire data_out_valid, - input wire data_out_ready - ); - - - -localparam FIFO_NUM_REGS = 2**FIFO_DEPTH_BITS; - - -reg [FIFO_WIDTH-1:0] fifo_reg_data[FIFO_NUM_REGS-1:0]; -reg fifo_reg_valid[FIFO_NUM_REGS-1:0]; - -// Last Reg in the FIFO -// valid -always@(posedge clk) begin - // data - if(data_out_ready || ~fifo_reg_valid[FIFO_NUM_REGS-1]) begin - fifo_reg_data[FIFO_NUM_REGS-1] <= data_in; - end - // valid - if(~rst_n) begin - fifo_reg_valid[FIFO_NUM_REGS-1] <= 1'b0; - end - else begin - if(data_out_ready) begin - fifo_reg_valid[FIFO_NUM_REGS-1] <= 1'b0; - end - else if(!fifo_reg_valid[FIFO_NUM_REGS-1] && fifo_reg_valid[FIFO_NUM_REGS-2]) begin - fifo_reg_valid[FIFO_NUM_REGS-1] <= data_in_valid; - end - end -end - -// Rest of Regs -genvar i; - -generate for (i = 0; i < FIFO_NUM_REGS-1; i=i+1) begin: fifo_regs - // valid - always@(posedge clk) begin - // Data - if(~fifo_reg_valid[i]) begin - fifo_reg_data[i] <= data_in; - end - else if(data_out_ready) begin - if(fifo_reg_valid[i+1]) begin - fifo_reg_data[i] <= fifo_reg_data[i+1]; - end - else begin - fifo_reg_data[i] <= data_in; - end - end - // valid - if(~rst_n) begin - fifo_reg_valid[i] <= 1'b0; - end - else if(~fifo_reg_valid[i]) begin - if(i == 0) begin - fifo_reg_valid[i] <= data_in_valid; - end - else begin - if(!data_out_ready && fifo_reg_valid[i-1]) begin - fifo_reg_valid[i] <= data_in_valid; - end - end - end - else if(data_out_ready) begin - if(fifo_reg_valid[i+1]) begin - fifo_reg_valid[i] <= 1'b1; - end - else begin - fifo_reg_valid[i] <= data_in_valid; - end - end - end -end -endgenerate - - -// -assign data_in_ready = ~fifo_reg_valid[FIFO_NUM_REGS-2]; -assign data_out = fifo_reg_data[0]; -assign data_out_valid = fifo_reg_valid[0]; - - - - - -endmodule \ No newline at end of file diff --git a/examples_hw/apps/gbm_dtrees/hdl/Tree_Memory.sv b/examples_hw/apps/gbm_dtrees/hdl/Tree_Memory.sv deleted file mode 100644 index a01e31345..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/Tree_Memory.sv +++ /dev/null @@ -1,192 +0,0 @@ - -/* - * Copyright 2019 - 2020 Systems Group, ETH Zurich - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - - - - -module Tree_Memory #( - parameter DATA_WIDTH = 32, - parameter ADDR_WIDTH = 10 -) ( - input wire clk, - input wire rst_n, - input wire we, - input wire rea, - input wire reb, - input wire [ADDR_WIDTH-1:0] addr_port_b, - input wire [ADDR_WIDTH-1:0] addr_port_a, - input wire [DATA_WIDTH-1:0] din, - output reg [DATA_WIDTH-1:0] dout1, - output reg valid_out1, - output reg [31:0] dout2, - output reg valid_out2 -); - - -// Port A -reg rea_d1; -reg addr_port_a_d1; - -wire [31:0] dout_a_1; -wire [31:0] dout_a_2; - -wire [9:0] addr_a_1; -wire [9:0] addr_a_2; - -// Port B -reg reb_d1; -reg addr_port_b_d1; - -wire [31:0] dout_b_1; -wire [31:0] dout_b_2; - - - -bram_1_in_2_out bram1in2out_inst_1 ( - .clk ( clk ), - .da ( din[31:0] ), - .ena (rea || we), - .addra ( addr_a_1 ), - .wea ( we ), - .qa ( dout_a_1 ), - - .enb (reb), - .db ( 0 ), - .addrb ( addr_port_b[10:1] ), - .web ( 1'b0 ), - .qb ( dout_b_1 ) - ); - - bram_1_in_2_out bram1in2out_inst_2 ( - .clk ( clk ), - .da ( din[63:32] ), - .ena (rea || we), - .addra ( addr_a_2 ), - .wea ( we ), - .qa ( dout_a_2 ), - - .enb (reb), - .db ( 0 ), - .addrb ( addr_port_b[10:1] ), - .web ( 1'b0 ), - .qb ( dout_b_2 ) - ); - - - -/*bram_1_in_2_out bram1in2out_inst_1 ( - .address_a ( addr_a_1 ), - .address_b ( addr_port_b[10:2] ), - .clock ( clk ), - .data_a ( din[31:0] ), - .data_b ( 0 ), - .wren_a ( we ), - .wren_b ( 1'b0 ), - .q_a ( dout_a_1 ), - .q_b ( dout_b_1 ) - ); - -bram_1_in_2_out bram1in2out_inst_2 ( - .address_a ( addr_a_2 ), - .address_b ( addr_port_b[10:2] ), - .clock ( clk ), - .data_a ( din[63:32] ), - .data_b ( 0 ), - .wren_a ( we ), - .wren_b ( 1'b0 ), - .q_a ( dout_a_2 ), - .q_b ( dout_b_2 ) - ); - -bram_1_in_2_out bram1in2out_inst_3 ( - .address_a ( addr_a_3 ), - .address_b ( addr_port_b[10:2] ), - .clock ( clk ), - .data_a ( din[95:64] ), - .data_b ( 0 ), - .wren_a ( we ), - .wren_b ( 1'b0 ), - .q_a ( dout_a_3 ), - .q_b ( dout_b_3 ) - ); - -bram_1_in_2_out bram1in2out_inst_4 ( - .address_a ( addr_a_4 ), - .address_b ( addr_port_b[10:2] ), - .clock ( clk ), - .data_a ( din[127:96] ), - .data_b ( 0 ), - .wren_a ( we ), - .wren_b ( 1'b0 ), - .q_a ( dout_a_4 ), - .q_b ( dout_b_4 ) - ); -*/ -//------------------------ Port A ---------------------------// -// rd_addr_a -assign addr_a_1 = (we || (addr_port_a[0] == 1'b0))? addr_port_a[10:1] : addr_port_a[10:1] + 1'b1; -assign addr_a_2 = addr_port_a[10:1]; -// -always @(posedge clk) begin - addr_port_a_d1 <= addr_port_a[0]; - - if(~rst_n) begin - valid_out1 <= 1'b0; - rea_d1 <= 1'b0; - end - else begin - rea_d1 <= rea; - valid_out1 <= rea_d1; - end - // - case (addr_port_a_d1) - 1'b0: dout1 <= {dout_a_2, dout_a_1}; - 1'b1: dout1 <= {dout_a_1, dout_a_2}; - default: dout1 <= 64'b0; - endcase -end -//----------------------- Port B ----------------------------// -always @(posedge clk) begin - - addr_port_b_d1 <= addr_port_b[0]; - - if(~rst_n) begin - reb_d1 <= 1'b0; - valid_out2 <= 1'b0; - end - else begin - reb_d1 <= reb; - valid_out2 <= reb_d1; - end - // - if (addr_port_b_d1) begin - dout2 <= dout_b_2; - end - else begin - dout2 <= dout_b_1; - end -end - - - -endmodule // Mem1in2out diff --git a/examples_hw/apps/gbm_dtrees/hdl/bram.sv b/examples_hw/apps/gbm_dtrees/hdl/bram.sv deleted file mode 100644 index a7d650ff1..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/bram.sv +++ /dev/null @@ -1,55 +0,0 @@ - - -/* - * Copyright 2019 - 2020 Systems Group, ETH Zurich - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -module bram #( - parameter DATA_WIDTH = 32, - parameter ADDR_WIDTH = 8 -) ( - input wire clk, - input wire we, - input wire re, - input wire [ADDR_WIDTH-1:0] raddr, - input wire [ADDR_WIDTH-1:0] waddr, - input wire [DATA_WIDTH-1:0] din, - output reg [DATA_WIDTH-1:0] dout -); - - -`ifdef VENDOR_XILINX - (* ram_extract = "yes", ram_style = "block" *) - reg [DATA_WIDTH-1:0] mem[0:2**ADDR_WIDTH-1]; -`else -(* ramstyle = "no_rw_check" *) reg [DATA_WIDTH-1:0] mem[0:2**ADDR_WIDTH-1]; -`endif - - - always @(posedge clk) begin - if (we) - mem[waddr] <= din; - - if (re) - dout <= mem[raddr]; - end - -endmodule \ No newline at end of file diff --git a/examples_hw/apps/gbm_dtrees/hdl/bram_1_in_2_out.sv b/examples_hw/apps/gbm_dtrees/hdl/bram_1_in_2_out.sv deleted file mode 100644 index 7cabab16b..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/bram_1_in_2_out.sv +++ /dev/null @@ -1,136 +0,0 @@ -//--------------------------------------------------------------------------------------- -// Amazon FPGA Hardware Development Kit -// -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. -// -// Licensed under the Amazon Software License (the "License"). You may not use -// this file except in compliance with the License. A copy of the License is -// located at -// -// http://aws.amazon.com/asl/ -// -// or in the "license" file accompanying this file. This file is distributed on -// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or -// implied. See the License for the specific language governing permissions and -// limitations under the License. -//--------------------------------------------------------------------------------------- -//---------------------------------------------------- -// This is a dual ported BRAM -//---------------------------------------------------- -module bram_1_in_2_out #(parameter WIDTH=32, parameter ADDR_WIDTH=10, parameter DEPTH=1024, parameter PIPELINE=0, parameter MEMORY_TYPE = "auto") -( - input clk, - input wea, - input ena, - input[ADDR_WIDTH-1:0] addra, - input[WIDTH-1:0] da, - output logic[WIDTH-1:0] qa, - - input web, - input enb, - input[ADDR_WIDTH-1:0] addrb, - input[WIDTH-1:0] db, - output logic[WIDTH-1:0] qb - - - ); - -`ifndef NO_XILINX_XPM_RAM - - xpm_memory_tdpram # ( - // Common module parameters - .MEMORY_SIZE (WIDTH*DEPTH), //positive integer - .MEMORY_PRIMITIVE (MEMORY_TYPE), //string; "auto", "distributed", "block" or "ultra"; - .CLOCKING_MODE ("common_clock"), //string; "common_clock", "independent_clock" - .MEMORY_INIT_FILE ("none"), //string; "none" or ".mem" - .MEMORY_INIT_PARAM ("" ), //string; - .USE_MEM_INIT (1), //integer; 0,1 - .WAKEUP_TIME ("disable_sleep"), //string; "disable_sleep" or "use_sleep_pin" - .MESSAGE_CONTROL (0), //integer; 0,1 - // Port A module parameters - .WRITE_DATA_WIDTH_A (WIDTH), //positive integer - .READ_DATA_WIDTH_A (WIDTH), //positive integer - .BYTE_WRITE_WIDTH_A (WIDTH), //integer; 8, 9, or WRITE_DATA_WIDTH_A value - .ADDR_WIDTH_A (ADDR_WIDTH), //positive integer - .READ_RESET_VALUE_A ("0"), //string - .READ_LATENCY_A (PIPELINE+1), //non-negative integer - .WRITE_MODE_A ("read_first"), //string; "write_first", "read_first", "no_change" - // Port B module parameters - .WRITE_DATA_WIDTH_B (WIDTH), //positive integer - .READ_DATA_WIDTH_B (WIDTH), //positive integer - .BYTE_WRITE_WIDTH_B (WIDTH), //integer; 8, 9, or WRITE_DATA_WIDTH_B value - .ADDR_WIDTH_B (ADDR_WIDTH), //positive integer - .READ_RESET_VALUE_B ("0"), //vector of READ_DATA_WIDTH_B bits - .READ_LATENCY_B (PIPELINE+1), //non-negative integer - .WRITE_MODE_B ("read_first") //string; "write_first", "read_first", "no_change" - ) xpm_memory_tdpram_inst ( - // Common module ports - .sleep (1'b0), - // Port A module ports - .clka (clk), - .rsta (1'b0), - .ena (ena), - .regcea (1'b1), - .wea (wea), - .addra (addra), - .dina (da), - .injectsbiterra (1'b0), //do not change - .injectdbiterra (1'b0), //do not change - .douta (qa), - .sbiterra (), //do not change - .dbiterra (), //do not change - // Port B module ports - .clkb (clk), - .rstb (1'b0), - .enb (enb), - .regceb (1'b1), - .web (web), - .addrb (addrb), - .dinb (db), - .injectsbiterrb (1'b0), //do not change - .injectdbiterrb (1'b0), //do not change - .doutb (qb), - .sbiterrb (), //do not change - .dbiterrb () //do not change - ); - // End of xpm_memory_tdpram instance declaration - -`else - - logic[WIDTH-1:0] ram[DEPTH-1:0]; - - logic[WIDTH-1:0] rddata_a, rddata_a_q; - logic[WIDTH-1:0] rddata_b, rddata_b_q; - - always @(posedge clk) - if (ena) - begin - if (wea) - ram[addra] <= da; - else - rddata_a <= ram[addra]; - end - - always @(posedge clk) - rddata_a_q <= rddata_a; - - always @(posedge clk) - if (enb) - begin - if (web) - ram[addrb] <= db; - else - rddata_b <= ram[addrb]; - end - - always @(posedge clk) - rddata_b_q <= rddata_b; - - assign qa = (PIPELINE)? rddata_a_q: rddata_a; - assign qb = (PIPELINE)? rddata_b_q: rddata_b; - -`endif - - - -endmodule diff --git a/examples_hw/apps/gbm_dtrees/hdl/bus_aligner.sv b/examples_hw/apps/gbm_dtrees/hdl/bus_aligner.sv deleted file mode 100644 index b023dce91..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/bus_aligner.sv +++ /dev/null @@ -1,183 +0,0 @@ - -/* - * Copyright 2019 - 2020 Systems Group, ETH Zurich - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -import DTPackage::*; - -module bus_aligner - ( - input wire clk, - input wire rst_n, - - input wire [511:0] data_in, - input wire data_in_last, - input wire data_in_type, - input wire data_in_valid, - input wire [3:0] data_in_off, - input wire [2:0] data_in_size, - input wire [4:0] data_in_word_count, - input wire stream_last, - - output wire [511:0] data_out, - output wire data_out_last, - output wire data_out_type, - output wire [2:0] data_out_size, - output wire data_out_valid - ); - - -reg [511:0] data_in_d1; -reg [511:0] data_in_d2; - -reg data_in_valid_d1; -reg data_in_valid_d2; - -reg data_in_last_d1; -reg data_in_last_d2; - -reg [3:0] data_in_off_d1; -reg [3:0] data_in_off_d2; - -reg [2:0] data_in_size_d1; -reg [2:0] data_in_size_d2; - -reg [4:0] data_in_word_count_d1; -reg [4:0] data_in_word_count_d2; - -reg stream_last_d1; -reg stream_last_d2; - -reg data_in_type_d1; -reg data_in_type_d2; - -wire shifter_in_last; -/////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Prepare lines for Shifter ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// -always@(posedge clk)begin - ////////////// Signals with reset ////////////////// - // Line 1 - if(~rst_n) begin - data_in_valid_d1 <= 1'b0; - data_in_valid_d2 <= 1'b0; - end - else begin - // Line 1 - data_in_valid_d1 <= data_in_valid; - - // Line 2 - if(data_in_valid_d2) begin - if(data_in_valid_d1) begin - if(data_in_last_d2) begin - data_in_valid_d2 <= 1'b1; - end - else if(data_in_last_d1) begin - data_in_valid_d2 <= data_in_word_count_d1 > data_in_off_d2; - end - else begin - data_in_valid_d2 <= 1'b1; - end - end - else if(stream_last_d2) begin - data_in_valid_d2 <= 1'b0; - end - end - else begin - data_in_valid_d2 <= data_in_valid_d1; - end - end - ////////////// Signals with no reset ////////////////// - // Line 1 - data_in_last_d1 <= data_in_last; - data_in_d1 <= data_in; - data_in_off_d1 <= data_in_off; - data_in_word_count_d1 <= data_in_word_count; - data_in_size_d1 <= data_in_size; - data_in_type_d1 <= data_in_type; - stream_last_d1 <= stream_last; - - // Line 2 - if(data_in_valid_d2) begin - if(data_in_valid_d1) begin - data_in_last_d2 <= data_in_last_d1; - data_in_d2 <= data_in_d1; - data_in_off_d2 <= data_in_off_d1; - data_in_word_count_d2 <= data_in_word_count_d1; - data_in_size_d2 <= data_in_size_d1; - data_in_type_d2 <= data_in_type_d1; - stream_last_d2 <= stream_last_d1; - end - end - else begin - data_in_last_d2 <= data_in_last_d1; - data_in_d2 <= data_in_d1; - data_in_off_d2 <= data_in_off_d1; - data_in_word_count_d2 <= data_in_word_count_d1; - data_in_type_d2 <= data_in_type_d1; - data_in_size_d2 <= data_in_size_d1; - stream_last_d2 <= stream_last_d1; - end -end - - -delay #(.DATA_WIDTH( 4 ), - .DELAY_CYCLES(16) - ) smart_shifter_delay( - .clk (clk), - .rst_n (rst_n), - .data_in ( {data_in_type_d2, data_in_size_d2} ), // - .data_in_valid ( (data_in_valid_d1 || stream_last_d2) && data_in_valid_d2 ), - .data_out ( {data_out_type, data_out_size} ), - .data_out_valid ( ) - ); - -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Smart Shifter ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -assign shifter_in_last = data_in_last_d2 || (data_in_last_d1 && (data_in_word_count_d1 <= data_in_off_d1)); - -smart_shifter #(.ELEMENTS_PER_CL(16), - .ELEMENTS_PER_CL_BITS(4)) - smart_shifter_x( - .clk (clk), - .rst_n (rst_n), - - .inValid ((data_in_valid_d1 || stream_last_d2) && data_in_valid_d2), - .inOffs (data_in_off_d2), - .inLast (shifter_in_last), - .inData ({data_in_d1, data_in_d2}), - - .outValid (data_out_valid), - .outLast (data_out_last), - .outData (data_out) - ); - - -endmodule - - - diff --git a/examples_hw/apps/gbm_dtrees/hdl/compute_unit.sv b/examples_hw/apps/gbm_dtrees/hdl/compute_unit.sv deleted file mode 100644 index 08aba4737..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/compute_unit.sv +++ /dev/null @@ -1,241 +0,0 @@ - - -/* - * Copyright 2019 - 2020 Systems Group, ETH Zurich - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - - -import DTPackage::*; - - -module compute_unit #(parameter CU_ID = 0 ) - ( - input wire clk, - input wire rst_n, - - input wire [511:0] data_line_in, - input wire data_line_in_valid, - input wire [2:0] data_line_in_last_valid_pos, - input wire data_line_in_last, - input wire data_line_in_ctrl, - input wire data_line_in_prog, - input wire [NUM_PUS_PER_CLUSTER_BITS-1:0] data_line_in_pu, - input wire [NUM_DTPU_CLUSTERS_BITS-1:0] data_line_in_cu, - output wire data_line_in_ready, - - output reg [511:0] data_line_out, - output reg data_line_out_valid, - output reg [2:0] data_line_out_last_valid_pos, - output reg data_line_out_ctrl, - output reg data_line_out_last, - output reg data_line_out_prog, - output reg [NUM_PUS_PER_CLUSTER_BITS-1:0] data_line_out_pu, - output reg [NUM_DTPU_CLUSTERS_BITS-1:0] data_line_out_cu, - - output wire [DATA_PRECISION-1:0] tuple_result_out, - output wire tuple_result_out_valid, - input wire tuple_result_out_ready - - ); - - -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Signals Declarations ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// -wire [DATA_LINE_WIDTH-1:0] line_rate_convertor_data_out; -wire line_rate_convertor_out_valid; -wire line_rate_convertor_out_last; -wire line_rate_convertor_out_ctrl; -wire line_rate_convertor_out_prog; -wire line_rate_convertor_out_ready; -wire [NUM_PUS_PER_CLUSTER_BITS-1:0] line_rate_convertor_out_pu; - - -wire [DATA_LINE_WIDTH-1:0] data_line_array[NUM_PUS_PER_CLUSTER:0]; -wire data_line_valid_array[NUM_PUS_PER_CLUSTER:0]; -wire data_line_last_array[NUM_PUS_PER_CLUSTER:0]; -wire data_line_ready_array[NUM_PUS_PER_CLUSTER:0]; -wire data_line_ctrl_array[NUM_PUS_PER_CLUSTER:0]; -wire data_line_prog_array[NUM_PUS_PER_CLUSTER:0]; -wire [NUM_PUS_PER_CLUSTER_BITS-1:0] data_line_pu_array[NUM_PUS_PER_CLUSTER:0]; - -wire [DATA_PRECISION-1:0] pu_tree_leaf_out[NUM_PUS_PER_CLUSTER-1:0]; -wire pu_tree_leaf_out_valid[NUM_PUS_PER_CLUSTER-1:0]; -wire pu_tree_leaf_out_last[NUM_PUS_PER_CLUSTER-1:0]; - -wire [31:0] fp_in_vector[31:0]; -wire fp_in_vector_valid[31:0]; -wire fp_in_vector_last[31:0]; -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Pipeline to next CU ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -always @(posedge clk) begin - // info - data_line_out <= data_line_in; - data_line_out_pu <= data_line_in_pu; - data_line_out_last_valid_pos <= data_line_in_last_valid_pos; - data_line_out_cu <= data_line_in_cu; - data_line_out_last <= data_line_in_last; - - // valids - if(~rst_n) begin - data_line_out_valid <= 1'b0; - data_line_out_ctrl <= 1'b0; - data_line_out_prog <= 1'b0; - end - else begin - data_line_out_valid <= data_line_in_valid; - data_line_out_ctrl <= data_line_in_ctrl; - data_line_out_prog <= data_line_in_prog; - end -end -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Line Rate Convertor ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -LineRateConvertor #(.CU_ID (CU_ID) ) - bus_convertor( - .clk (clk), - .rst_n (rst_n), - - .data_line_in (data_line_in), - .data_line_in_valid (data_line_in_valid), - .data_line_in_last_valid_pos (data_line_in_last_valid_pos), - .data_line_in_last (data_line_in_last), - .data_line_in_ctrl (data_line_in_ctrl), - .data_line_in_prog (data_line_in_prog), - .data_line_in_pu (data_line_in_pu), - .data_line_in_cu (data_line_in_cu), - .data_line_in_ready (data_line_in_ready), - - - .data_line_out (line_rate_convertor_data_out), - .data_line_out_valid (line_rate_convertor_out_valid), - .data_line_out_ctrl (line_rate_convertor_out_ctrl), - .data_line_out_last (line_rate_convertor_out_last), - .data_line_out_prog (line_rate_convertor_out_prog), - .data_line_out_pu (line_rate_convertor_out_pu), - .data_line_out_ready (line_rate_convertor_out_ready) - ); - - -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Generate DTPU Instances ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -// initialize input to first PU -assign data_line_array[0] = line_rate_convertor_data_out; -assign data_line_valid_array[0] = line_rate_convertor_out_valid; -assign data_line_last_array[0] = line_rate_convertor_out_last; -assign data_line_ctrl_array[0] = line_rate_convertor_out_ctrl; -assign data_line_prog_array[0] = line_rate_convertor_out_prog; -assign data_line_pu_array[0] = line_rate_convertor_out_pu; - -assign line_rate_convertor_out_ready = data_line_ready_array[0]; - - -// generate a cascade of PUs -genvar i; -generate - for (i = 0; i < NUM_PUS_PER_CLUSTER; i = i + 1) begin: pus - processing_element_async #(.PE_ID (i) ) - pe_x( - .clk (clk), - .rst_n (rst_n), - - .data_line_in (data_line_array[i]), - .data_line_in_valid (data_line_valid_array[i]), - .data_line_in_last (data_line_last_array[i]), - .data_line_in_ctrl (data_line_ctrl_array[i]), - .data_line_in_prog (data_line_prog_array[i]), - .data_line_in_pu (data_line_pu_array[i]), - .data_line_in_ready (data_line_ready_array[i]), - - .data_line_out (data_line_array[i+1]), - .data_line_out_valid (data_line_valid_array[i+1]), - .data_line_out_ctrl (data_line_ctrl_array[i+1]), - .data_line_out_last (data_line_last_array[i+1]), - .data_line_out_prog (data_line_prog_array[i+1]), - .data_line_out_pu (data_line_pu_array[i+1]), - - .pu_tree_leaf_out (pu_tree_leaf_out[i]), - .pu_tree_leaf_out_valid (pu_tree_leaf_out_valid[i]), - .pu_tree_leaf_out_last (pu_tree_leaf_out_last[i]) - ); - end -endgenerate -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Instance of FPAdders Tree ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -generate for (i = 0; i < 32; i=i+1) begin - if( i < NUM_PUS_PER_CLUSTER ) begin - assign fp_in_vector[i] = pu_tree_leaf_out[i]; - assign fp_in_vector_valid[i] = pu_tree_leaf_out_valid[i]; - assign fp_in_vector_last[i] = pu_tree_leaf_out_last[i]; - end - else begin - assign fp_in_vector[i] = 32'b0; - assign fp_in_vector_valid[i] = 1'b0; - assign fp_in_vector_last[i] = 1'b0; - end -end -endgenerate - -FPAddersReduceTree_sync #(.NUM_FP_POINTS(32) - ) reduce_leaves( - .clk (clk), - .rst_n (rst_n), - - .fp_in_vector (fp_in_vector), - .fp_in_vector_valid (fp_in_vector_valid), - .fp_in_vector_last (fp_in_vector_last), - - .reduce_out (tuple_result_out), - .reduce_out_valid (tuple_result_out_valid), - .reduce_out_ready (tuple_result_out_ready) - ); - - -endmodule - - - - - - - - - - - - diff --git a/examples_hw/apps/gbm_dtrees/hdl/delay.sv b/examples_hw/apps/gbm_dtrees/hdl/delay.sv deleted file mode 100644 index fe4b7a76b..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/delay.sv +++ /dev/null @@ -1,75 +0,0 @@ - - -/* - * Copyright 2019 - 2020 Systems Group, ETH Zurich - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - - -module delay #(parameter DATA_WIDTH = 32, - parameter DELAY_CYCLES = 4 - ) ( - - input wire clk, - input wire rst_n, - input wire [DATA_WIDTH-1:0] data_in, - input wire data_in_valid, - output wire [DATA_WIDTH-1:0] data_out, - output wire data_out_valid - ); - - -reg [DATA_WIDTH-1:0] data_array[DELAY_CYCLES]; -reg data_array_valid[DELAY_CYCLES]; - - -always @(posedge clk) begin - // Valid Bit - if(~rst_n) begin - data_array_valid[0] <= 0; - end - else begin - data_array_valid[0] <= data_in_valid; - end - // Data word - data_array[0] <= data_in; -end - - -genvar i; -generate for (i = 1; i < DELAY_CYCLES; i = i +1) begin: delayPipe - always @(posedge clk) begin - // Valid Bit - if(~rst_n) begin - data_array_valid[i] <= 0; - end - else begin - data_array_valid[i] <= data_array_valid[i-1]; - end - // Data word - data_array[i] <= data_array[i-1]; - end -end -endgenerate - -assign data_out = data_array[DELAY_CYCLES-1]; -assign data_out_valid = data_array_valid[DELAY_CYCLES-1]; - -endmodule // delay diff --git a/examples_hw/apps/gbm_dtrees/hdl/dual_port_mem.sv b/examples_hw/apps/gbm_dtrees/hdl/dual_port_mem.sv deleted file mode 100644 index c6640267d..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/dual_port_mem.sv +++ /dev/null @@ -1,128 +0,0 @@ -//--------------------------------------------------------------------------------------- -// Amazon FPGA Hardware Development Kit -// -// Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. -// -// Licensed under the Amazon Software License (the "License"). You may not use -// this file except in compliance with the License. A copy of the License is -// located at -// -// http://aws.amazon.com/asl/ -// -// or in the "license" file accompanying this file. This file is distributed on -// an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or -// implied. See the License for the specific language governing permissions and -// limitations under the License. -//--------------------------------------------------------------------------------------- -//---------------------------------------------------- -// This is a dual ported BRAM -//---------------------------------------------------- -module dual_port_mem #(parameter WIDTH=64, parameter ADDR_WIDTH=9, parameter DEPTH=512, parameter PIPELINE=0, parameter MEMORY_TYPE = "auto") -( - input clk, - input wea, - input ena, - input[ADDR_WIDTH-1:0] addra, - input[WIDTH-1:0] da, - output logic[WIDTH-1:0] qa, - - input web, - input enb, - input[ADDR_WIDTH-1:0] addrb, - input[WIDTH-1:0] db, - output logic[WIDTH-1:0] qb - - - ); - -`ifndef NO_XILINX_XPM_RAM - - xpm_memory_tdpram # ( - // Common module parameters - .MEMORY_SIZE (WIDTH*DEPTH), //positive integer - .MEMORY_PRIMITIVE (MEMORY_TYPE), //string; "auto", "distributed", "block" or "ultra"; - .CLOCKING_MODE ("common_clock"), //string; "common_clock", "independent_clock" - .MEMORY_INIT_FILE ("none"), //string; "none" or ".mem" - .MEMORY_INIT_PARAM ("" ), //string; - .USE_MEM_INIT (1), //integer; 0,1 - .WAKEUP_TIME ("disable_sleep"), //string; "disable_sleep" or "use_sleep_pin" - .MESSAGE_CONTROL (0), //integer; 0,1 - // Port A module parameters - .WRITE_DATA_WIDTH_A (WIDTH), //positive integer - .READ_DATA_WIDTH_A (WIDTH), //positive integer - .BYTE_WRITE_WIDTH_A (WIDTH), //integer; 8, 9, or WRITE_DATA_WIDTH_A value - .ADDR_WIDTH_A (ADDR_WIDTH), //positive integer - .READ_RESET_VALUE_A ("0"), //string - .READ_LATENCY_A (PIPELINE+1), //non-negative integer - .WRITE_MODE_A ("read_first"), //string; "write_first", "read_first", "no_change" - // Port B module parameters - .WRITE_DATA_WIDTH_B (WIDTH), //positive integer - .READ_DATA_WIDTH_B (WIDTH), //positive integer - .BYTE_WRITE_WIDTH_B (WIDTH), //integer; 8, 9, or WRITE_DATA_WIDTH_B value - .ADDR_WIDTH_B (ADDR_WIDTH), //positive integer - .READ_RESET_VALUE_B ("0"), //vector of READ_DATA_WIDTH_B bits - .READ_LATENCY_B (PIPELINE+1), //non-negative integer - .WRITE_MODE_B ("read_first") //string; "write_first", "read_first", "no_change" - ) xpm_memory_tdpram_inst ( - // Common module ports - .sleep (1'b0), - // Port A module ports - .clka (clk), - .rsta (1'b0), - .ena (ena), - .regcea (1'b1), - .wea (wea), - .addra (addra), - .dina (da), - .injectsbiterra (1'b0), //do not change - .injectdbiterra (1'b0), //do not change - .douta (qa), - .sbiterra (), //do not change - .dbiterra (), //do not change - // Port B module ports - .clkb (clk), - .rstb (1'b0), - .enb (enb), - .regceb (1'b1), - .web (web), - .addrb (addrb), - .dinb (db), - .injectsbiterrb (1'b0), //do not change - .injectdbiterrb (1'b0), //do not change - .doutb (qb), - .sbiterrb (), //do not change - .dbiterrb () //do not change - ); - // End of xpm_memory_tdpram instance declaration - -`else - - logic[WIDTH-1:0] ram[DEPTH-1:0]; - - logic[WIDTH-1:0] rddata_a, rddata_a_q; - logic[WIDTH-1:0] rddata_b, rddata_b_q; - - always @(posedge clk) - if (enb) begin - rddata_b <= ram[addrb]; - end - - always @(posedge clk) - rddata_b_q <= rddata_b; - - always @(posedge clk) - if (wea) begin - ram[addra] <= da; - end - - always @(posedge clk) - rddata_a_q <= 0; - - assign qa = (PIPELINE)? rddata_a_q: rddata_a; - assign qb = (PIPELINE)? rddata_b_q: rddata_b; - -`endif - - - -endmodule diff --git a/examples_hw/apps/gbm_dtrees/hdl/gbm_slave.sv b/examples_hw/apps/gbm_dtrees/hdl/gbm_slave.sv deleted file mode 100644 index 5de9d2b53..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/gbm_slave.sv +++ /dev/null @@ -1,293 +0,0 @@ -/** - * GBM slave - */ -import lynxTypes::*; - -module gbm_slave #( - parameter integer NFEAUTRES_BITS = 16, - parameter integer TREEDEPTH_BITS = 8, - parameter integer PUTREES_BITS = 8, - parameter integer OUTNUMCLS_BITS = 32, - parameter integer LSTOUTMASK_BITS = 16 -) ( - input logic aclk, - input logic aresetn, - - AXI4L.s axi_ctrl, - - // User defined arguments - output logic ap_start, - output logic [NFEAUTRES_BITS-1:0] numFeatures, - output logic [TREEDEPTH_BITS-1:0] treeDepth, - output logic [PUTREES_BITS-1:0] puTrees, - output logic [OUTNUMCLS_BITS-1:0] outputNumCLs, - output logic [LSTOUTMASK_BITS-1:0] lastOutLineMask -); - -// -- Decl ---------------------------------------------------------- -// ------------------------------------------------------------------ -// Constants -localparam integer N_REGS = 6; -localparam integer ADDR_LSB = $clog2(AXIL_DATA_BITS/8); -localparam integer ADDR_MSB = $clog2(N_REGS); -localparam integer AXIL_ADDR_BITS = ADDR_LSB + ADDR_MSB; - -// Internal registers -logic [AXIL_ADDR_BITS-1:0] axi_awaddr; -logic axi_awready; -logic [AXIL_ADDR_BITS-1:0] axi_araddr; -logic axi_arready; -logic [1:0] axi_bresp; -logic axi_bvalid; -logic axi_wready; -logic [AXIL_DATA_BITS-1:0] axi_rdata; -logic [1:0] axi_rresp; -logic axi_rvalid; - -// Registers -logic [N_REGS-1:0][AXIL_DATA_BITS-1:0] slv_reg; -logic slv_reg_rden; -logic slv_reg_wren; -logic aw_en; - -// -- Def ----------------------------------------------------------- -// ------------------------------------------------------------------ - -// -- Register map ----------------------------------------------------------------------- -// 0 (W1S) : AP start ( -localparam integer AP_CTRL_REG = 0; -// 0 - start -// 1 (WR) : Number of features -localparam integer NFEAUTERS_REG = 1; -// 2 (WR) : Treedepth -localparam integer TREEDEPTH_REG = 2; -// 3 (WR) : Putrees -localparam integer PUTREES_REG = 3; -// 4 (WR) : OutputNumCLs -localparam integer OUTNUMCLS_REG = 4; -// 5 (WR) : LastOutLineMask -localparam integer LSTOUTMASK_REG = 5; - -// Write process -assign slv_reg_wren = axi_wready && axi_ctrl.wvalid && axi_awready && axi_ctrl.awvalid; - -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) begin - slv_reg <= 0; - end - else begin - // Control - slv_reg[AP_CTRL_REG] <= 0; - - if(slv_reg_wren) begin - case (axi_awaddr[ADDR_LSB+:ADDR_MSB]) - AP_CTRL_REG: // Control - for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin - if(axi_ctrl.wstrb[i]) begin - slv_reg[AP_CTRL_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8]; - end - end - NFEAUTERS_REG: // Number of features - for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin - if(axi_ctrl.wstrb[i]) begin - slv_reg[NFEAUTERS_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8]; - end - end - TREEDEPTH_REG: // Treedepth - for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin - if(axi_ctrl.wstrb[i]) begin - slv_reg[TREEDEPTH_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8]; - end - end - PUTREES_REG: // Putrees - for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin - if(axi_ctrl.wstrb[i]) begin - slv_reg[PUTREES_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8]; - end - end - OUTNUMCLS_REG: // Output number of CLs - for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin - if(axi_ctrl.wstrb[i]) begin - slv_reg[OUTNUMCLS_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8]; - end - end - LSTOUTMASK_REG: // Last out line mask - for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin - if(axi_ctrl.wstrb[i]) begin - slv_reg[LSTOUTMASK_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8]; - end - end - default : ; - endcase - end - end -end - -// Read process -assign slv_reg_rden = axi_arready & axi_ctrl.arvalid & ~axi_rvalid; - -always_ff @(posedge aclk) begin - if( aresetn == 1'b0 ) begin - axi_rdata <= 0; - end - else begin - if(slv_reg_rden) begin - axi_rdata <= 0; - - case (axi_araddr[ADDR_LSB+:ADDR_MSB]) - NFEAUTERS_REG: // Key low - axi_rdata[NFEAUTRES_BITS-1:0] <= slv_reg[NFEAUTERS_REG][NFEAUTRES_BITS-1:0]; - TREEDEPTH_REG: // Key high - axi_rdata[TREEDEPTH_BITS-1:0] <= slv_reg[TREEDEPTH_REG][TREEDEPTH_BITS-1:0]; - PUTREES_REG: // Key high - axi_rdata[PUTREES_BITS-1:0] <= slv_reg[PUTREES_REG][PUTREES_BITS-1:0]; - OUTNUMCLS_REG: // Key high - axi_rdata[OUTNUMCLS_BITS-1:0] <= slv_reg[OUTNUMCLS_REG][OUTNUMCLS_BITS-1:0]; - LSTOUTMASK_REG: // Key high - axi_rdata[LSTOUTMASK_BITS-1:0] <= slv_reg[LSTOUTMASK_REG][LSTOUTMASK_BITS-1:0]; - default: ; - endcase - end - end -end - -// Output -always_comb begin - ap_start = slv_reg[AP_CTRL_REG][0]; - numFeatures = slv_reg[NFEAUTERS_REG][15:0]; - treeDepth = slv_reg[TREEDEPTH_REG][7:0]; - puTrees = slv_reg[PUTREES_REG][7:0]; - outputNumCLs = slv_reg[OUTNUMCLS_REG][31:0]; - lastOutLineMask = slv_reg[LSTOUTMASK_REG][15:0]; -end - - -// -------------------------------------------------------------------------------------- -// AXI CTRL -// -------------------------------------------------------------------------------------- -// Don't edit - -// I/O -assign axi_ctrl.awready = axi_awready; -assign axi_ctrl.arready = axi_arready; -assign axi_ctrl.bresp = axi_bresp; -assign axi_ctrl.bvalid = axi_bvalid; -assign axi_ctrl.wready = axi_wready; -assign axi_ctrl.rdata = axi_rdata; -assign axi_ctrl.rresp = axi_rresp; -assign axi_ctrl.rvalid = axi_rvalid; - -// awready and awaddr -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) - begin - axi_awready <= 1'b0; - axi_awaddr <= 0; - aw_en <= 1'b1; - end - else - begin - if (~axi_awready && axi_ctrl.awvalid && axi_ctrl.wvalid && aw_en) - begin - axi_awready <= 1'b1; - aw_en <= 1'b0; - axi_awaddr <= axi_ctrl.awaddr; - end - else if (axi_ctrl.bready && axi_bvalid) - begin - aw_en <= 1'b1; - axi_awready <= 1'b0; - end - else - begin - axi_awready <= 1'b0; - end - end -end - -// arready and araddr -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) - begin - axi_arready <= 1'b0; - axi_araddr <= 0; - end - else - begin - if (~axi_arready && axi_ctrl.arvalid) - begin - axi_arready <= 1'b1; - axi_araddr <= axi_ctrl.araddr; - end - else - begin - axi_arready <= 1'b0; - end - end -end - -// bvalid and bresp -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) - begin - axi_bvalid <= 0; - axi_bresp <= 2'b0; - end - else - begin - if (axi_awready && axi_ctrl.awvalid && ~axi_bvalid && axi_wready && axi_ctrl.wvalid) - begin - axi_bvalid <= 1'b1; - axi_bresp <= 2'b0; - end - else - begin - if (axi_ctrl.bready && axi_bvalid) - begin - axi_bvalid <= 1'b0; - end - end - end -end - -// wready -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) - begin - axi_wready <= 1'b0; - end - else - begin - if (~axi_wready && axi_ctrl.wvalid && axi_ctrl.awvalid && aw_en ) - begin - axi_wready <= 1'b1; - end - else - begin - axi_wready <= 1'b0; - end - end -end - -// rvalid and rresp (1Del?) -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) - begin - axi_rvalid <= 0; - axi_rresp <= 0; - end - else - begin - if (axi_arready && axi_ctrl.arvalid && ~axi_rvalid) - begin - axi_rvalid <= 1'b1; - axi_rresp <= 2'b0; - end - else if (axi_rvalid && axi_ctrl.rready) - begin - axi_rvalid <= 1'b0; - end - end -end - -endmodule // gbm slave \ No newline at end of file diff --git a/examples_hw/apps/gbm_dtrees/hdl/pe_datapath.sv b/examples_hw/apps/gbm_dtrees/hdl/pe_datapath.sv deleted file mode 100644 index d0fe17479..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/pe_datapath.sv +++ /dev/null @@ -1,369 +0,0 @@ - -/* - * Copyright 2019 - 2020 Systems Group, ETH Zurich - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -/* - PE Datapath flow: - - - Read Tree Node: This stage consumes either the input tree instruction or the next node instruction. - This stage issues a read address to tree memory and delays all the necessary information - for the tree memory delay. By the end of the stage, the tree node basic and extra part are - available in addition to the delayed information. - - - Read feature: Use the feature index in the tree node to compute the feature address and read it from - the data memory. Then, we delay the current node instruction and obtained tree node info. - - - Read Split Set: In this stage, we compute the address for large bitset word to read from - tree memory, If there is no large split bitset then the tree memory output is ignored. - In addition, the early tree evaluation occurs. In parallel, we use the feature value to select - from the small bitset, we use it also to compare to the split value, and we use the feature value - to check if it is outside the boundaries of the large bitset. In addition, If node_nop flag is zero, - then the node_res_val is not used, hence we store W2 of the tree node in its place to save resources. - In addition, we check if the feature value is NaN or not. - - Evaluate Node: At this stage we have all the necessary information to process a node. - Then based on the operation type the evaluation happens. - Pick A branch: In this stage, based on the node evaluation result then we compute next node - to evaluate, or pick result if no children on the next branch and set NOP if we - are not at the last level. In this branch, also if we at the last level, then we - output the result if the tree is not empty. -*/ - -import DTPackage::*; - -module pe_datapath ( - - input wire clk, - input wire rst_n, - - input wire [MAX_TREE_DEPTH_BITS-1:0] tree_depth, - - // tree instruction - input TreeInstruction_t tree_instruction, - input wire tree_instruction_valid, - output wire tree_instruction_ready, - - // data memory read port - output wire [TUPLE_OFFSET_BITS:0] data_mem_rd_addr, - output wire data_mem_ren, - input wire [31:0] data_mem_feature, - - // tree memory read port A - output wire [TREE_OFFSET_BITS:0] tree_mem_rd_addr_a, - output wire tree_mem_ren_a, - input TreeNode_t tree_node_basic, - - // tree memory read port B - output wire [TREE_OFFSET_BITS:0] tree_mem_rd_addr_b, - output wire tree_mem_ren_b, - input wire [31:0] node_large_bitset, - - // result output - output wire [31:0] tree_eval_result, - output wire tree_eval_last, - output wire tree_eval_result_valid -); - - - - -NodeInstruction_t next_node_instr; -wire next_node_instr_valid; - -NodeInstruction_t curr_node_instr_s1; -wire curr_node_instr_valid_s1; -NodeInstruction_t curr_node_instr_s2; -wire curr_node_instr_valid_s2; -NodeInstruction_t curr_node_instr_s3; -NodeInstruction_t curr_node_instr_s3_1; -wire curr_node_instr_valid_s3; -NodeInstruction_t curr_node_instr_s4; -NodeInstruction_t curr_node_instr_s4_1; -wire curr_node_instr_valid_s4; -NodeInstruction_t curr_node_instr_s5; -NodeInstruction_t curr_node_instr_s5_1; -wire curr_node_instr_valid_s5; - -wire [31:0] small_bitset; -wire is_Feature_NaN; -wire small_bitset_eval; -wire split_value_eval; -wire feature_data_outside_bitset; - -wire is_Feature_NaN_s4; -wire small_bitset_eval_s4; -wire split_value_eval_s4; -wire feature_data_outside_bitset_s4; -wire [4:0] feature_data_s4; - -wire is_Feature_NaN_s5; - -TreeNode_t tree_node_basic_s3; -TreeNode_t tree_node_basic_s4; -TreeNode_t tree_node_basic_s5; - -reg go_right; -reg node_eval; - -wire [10:0] left_child_offset_1; -wire [10:0] left_child_offset_2; - -wire [10:0] right_child_offset; - -wire [10:0] next_node_address; -wire [MAX_TREE_DEPTH_BITS-1:0] next_node_level; - -wire next_node_nop; -wire [10:0] next_child_offset; -wire [10:0] result_offset; -wire next_node_leaf; - -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Read Node Stage ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// -/* -*/ -always @(*) begin - if(next_node_instr_valid) begin - curr_node_instr_s1 = next_node_instr; - end - else begin - curr_node_instr_s1 = '{node_address: {tree_instruction.tree_offset, 1'b0}, - tuple_offset: tree_instruction.tuple_offset, - node_level : 3'b000, - empty_tree : tree_instruction.empty_tree, - node_nop : 1'b0, - last_tree : tree_instruction.last_tree, - leaf_node : 1'b0, - node_res_val: 32'b0 - }; - end -end - -assign curr_node_instr_valid_s1 = next_node_instr_valid | tree_instruction_valid; - -assign tree_instruction_ready = !next_node_instr_valid; - -// Send read requests to tree memory -assign tree_mem_rd_addr_a = curr_node_instr_s1.node_address; -assign tree_mem_ren_a = curr_node_instr_valid_s1; - -// Pipeline to next stage -delay #(.DATA_WIDTH( $bits(NodeInstruction_t)), - .DELAY_CYCLES(TREE_MEM_READ_LATENCY) - ) ReadNodeStageDelay( - .clk ( clk ), - .rst_n ( rst_n ), - .data_in ( curr_node_instr_s1 ), // - .data_in_valid ( curr_node_instr_valid_s1 ), - .data_out ( curr_node_instr_s2 ), - .data_out_valid ( curr_node_instr_valid_s2 ) - ); - -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Read Feature Stage ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// -/* - This stage reads the feature data corresponding to current tree node. -*/ -assign data_mem_ren = curr_node_instr_valid_s2 && (tree_node_basic.node_type.findex != 8'hFF); -assign data_mem_rd_addr = {curr_node_instr_s2.tuple_offset, 1'b0} + tree_node_basic.node_type.findex; // 10-bit address - -// Pipeline to next stage -delay #(.DATA_WIDTH($bits(NodeInstruction_t) + $bits(TreeNode_t)), - .DELAY_CYCLES(DATA_MEM_READ_LATENCY) - ) ReadFeatureStageDelay( - .clk (clk), - .rst_n (rst_n), - .data_in ( {curr_node_instr_s2, tree_node_basic} ), // - .data_in_valid ( curr_node_instr_valid_s2 ), - .data_out ( {curr_node_instr_s3, tree_node_basic_s3} ), - .data_out_valid ( curr_node_instr_valid_s3 ) - ); -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Read Split Set/Value Stage ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// -assign tree_mem_rd_addr_b = curr_node_instr_s3.node_address + - ((curr_node_instr_s3.leaf_node)? 0 : - (((!tree_node_basic_s3.node_type.left_child)? 1'b1 : 0) + - ((!tree_node_basic_s3.node_type.right_child)? 1'b1 : 0) + - data_mem_feature[15:5] + 11'b00000010)); -assign tree_mem_ren_b = curr_node_instr_valid_s3; - -// Early Node evaluation -assign curr_node_instr_s3_1 = '{ node_address: curr_node_instr_s3.node_address, - tuple_offset: curr_node_instr_s3.tuple_offset, - node_level : curr_node_instr_s3.node_level, - empty_tree : curr_node_instr_s3.empty_tree, - node_nop : ((curr_node_instr_s3.node_nop)? 1'b1 : !curr_node_instr_s3.leaf_node && (tree_node_basic_s3.node_type.findex == 8'hFF) ), - last_tree : curr_node_instr_s3.last_tree, - leaf_node : curr_node_instr_s3.leaf_node, - node_res_val: ( (curr_node_instr_s3.node_nop)? curr_node_instr_s3.node_res_val : {tree_node_basic_s3.word_1_h, tree_node_basic_s3.word_1_l}) - }; - -assign small_bitset = {tree_node_basic_s3.word_1_h, tree_node_basic_s3.word_1_l}; - -assign is_Feature_NaN = (data_mem_feature[30:23] == 7'b1111111) && (|data_mem_feature[22:0]); -assign small_bitset_eval = (data_mem_feature[31:5] == 0)? small_bitset[ data_mem_feature[4:0] ] : 1'b0; -assign split_value_eval = data_mem_feature < {tree_node_basic_s3.word_1_h, tree_node_basic_s3.word_1_l}; - -assign feature_data_outside_bitset = (data_mem_feature < tree_node_basic_s3.word_1_h) || - (data_mem_feature > (tree_node_basic_s3.word_1_h + (tree_node_basic_s3.word_1_l << 5) ) ); - -// Pipeline to next stage -delay #(.DATA_WIDTH($bits(NodeInstruction_t) + $bits(TreeNode_t) + 5 + 1 + 1 + 1 + 1), - .DELAY_CYCLES(TREE_MEM_READ_LATENCY) - ) ReadSplitSetStageDelay( - .clk (clk), - .rst_n (rst_n), - .data_in ( {curr_node_instr_s3_1, tree_node_basic_s3, data_mem_feature[4:0], small_bitset_eval, split_value_eval, feature_data_outside_bitset, is_Feature_NaN} ), // - .data_in_valid ( curr_node_instr_valid_s3 ), - .data_out ( {curr_node_instr_s4, tree_node_basic_s4, feature_data_s4, small_bitset_eval_s4, split_value_eval_s4, feature_data_outside_bitset_s4, is_Feature_NaN_s4} ), - .data_out_valid ( curr_node_instr_valid_s4 ) - ); - -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Node Evaluation Stage ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// -/* -*/ - -always@(posedge clk)begin - if(~rst_n) begin - node_eval <= 1'b0; - end - else begin - case (tree_node_basic_s4.node_type.op_type) - 2'b00: node_eval <= split_value_eval_s4; - 2'b10: node_eval <= small_bitset_eval_s4; - 2'b11: node_eval <= (feature_data_outside_bitset_s4)? 1'b0 : node_large_bitset[ feature_data_s4 ]; - default : node_eval <= 1'b0; - endcase - end -end - -// Early Node evaluation -assign curr_node_instr_s4_1 = '{ node_address: curr_node_instr_s4.node_address, - tuple_offset: curr_node_instr_s4.tuple_offset, - node_level : curr_node_instr_s4.node_level, - empty_tree : curr_node_instr_s4.empty_tree, - node_nop : curr_node_instr_s4.node_nop, - last_tree : curr_node_instr_s4.last_tree, - leaf_node : curr_node_instr_s4.leaf_node, - node_res_val: ( (curr_node_instr_s4.node_nop || !curr_node_instr_s4.leaf_node)? curr_node_instr_s4.node_res_val : node_large_bitset ) - }; - -// Pipeline to next stage -delay #(.DATA_WIDTH($bits(NodeInstruction_t) + $bits(TreeNode_t) + 1), - .DELAY_CYCLES(1) - ) EvalNodeStageDelay( - .clk (clk), - .rst_n (rst_n), - .data_in ( {curr_node_instr_s4_1, tree_node_basic_s4, is_Feature_NaN_s4} ), // - .data_in_valid ( curr_node_instr_valid_s4 ), - .data_out ( {curr_node_instr_s5, tree_node_basic_s5, is_Feature_NaN_s5} ), - .data_out_valid ( curr_node_instr_valid_s5 ) - ); - -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Pick Branch Stage ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// -/* -*/ - -always@(*)begin - if(tree_node_basic_s5.node_type.split_dir == 4'b0001) begin - go_right = is_Feature_NaN_s5; - end - else if(tree_node_basic_s5.node_type.split_dir[0] == 1'b0) begin - if(is_Feature_NaN_s5) begin - go_right = 1'b0; - end - else begin - go_right = node_eval; - end - end - else begin - if(is_Feature_NaN_s5) begin - go_right = 1'b1; - end - else begin - go_right = node_eval; - end - end -end - -// compute left child offset, -assign left_child_offset_1 = 11'b00000000010 + ((tree_node_basic_s5.node_type.left_child)? 0 : 1'b1) + ((tree_node_basic_s5.node_type.right_child)? 0 : 1'b1); -assign left_child_offset_2 = left_child_offset_1 + ( (tree_node_basic_s5.node_type.op_type != 3)? 11'd0 : tree_node_basic_s5.word_1_l[10:0]); -// compute right child offset -assign right_child_offset = left_child_offset_2 + tree_node_basic_s5.right_child_offset[10:0]; -assign next_child_offset = (go_right && tree_node_basic_s5.node_type.left_child)? right_child_offset : left_child_offset_2; - -// compute leaf node result offset -assign result_offset = (go_right)? 11'b00000000010 + ((tree_node_basic_s5.node_type.left_child)? 0 : 1'b1) : 11'b00000000010; -assign next_node_leaf = (go_right)? !tree_node_basic_s5.node_type.right_child : !tree_node_basic_s5.node_type.left_child; - -// Next level node address -assign next_node_address = curr_node_instr_s5.node_address + ( (next_node_leaf)? result_offset : next_child_offset); - -assign next_node_level = (curr_node_instr_s5.node_level == (tree_depth))? (tree_depth) : curr_node_instr_s5.node_level + 1'b1; -assign next_node_nop = curr_node_instr_s5.node_nop || ((curr_node_instr_s5.node_level < (tree_depth) && curr_node_instr_s5.leaf_node)? 1'b1 : 1'b0); - -assign curr_node_instr_s5_1 = '{ node_address: next_node_address, - tuple_offset: curr_node_instr_s5.tuple_offset, - node_level : next_node_level, - empty_tree : curr_node_instr_s5.empty_tree, - node_nop : next_node_nop, - last_tree : curr_node_instr_s5.last_tree, - leaf_node : ( curr_node_instr_s5.leaf_node || next_node_leaf), - node_res_val: curr_node_instr_s5.node_res_val - }; -// Pipeline to next stage -delay #(.DATA_WIDTH( $bits(NodeInstruction_t) ), - .DELAY_CYCLES(1) - ) PickBranchStageDelay( - .clk (clk), - .rst_n (rst_n), - .data_in ( curr_node_instr_s5_1 ), // - .data_in_valid ( curr_node_instr_valid_s5 && (curr_node_instr_s5.node_level < (tree_depth)) ), - .data_out ( next_node_instr ), - .data_out_valid ( next_node_instr_valid ) - ); - - -assign tree_eval_result = (curr_node_instr_s5.empty_tree)? 32'b0 : curr_node_instr_s5.node_res_val; -assign tree_eval_result_valid = curr_node_instr_valid_s5 && (curr_node_instr_s5.node_level == (tree_depth) ); -assign tree_eval_last = curr_node_instr_s5.last_tree; - - - -endmodule \ No newline at end of file diff --git a/examples_hw/apps/gbm_dtrees/hdl/processing_element.sv b/examples_hw/apps/gbm_dtrees/hdl/processing_element.sv deleted file mode 100644 index 19194934e..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/processing_element.sv +++ /dev/null @@ -1,442 +0,0 @@ - -/* - * Copyright 2019 - 2020 Systems Group, ETH Zurich - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - - -import DTPackage::*; - -/* - -*/ -module processing_element #(parameter PE_ID = 0 ) - ( - input wire clk, - input wire rst_n, - - input wire [DATA_LINE_WIDTH-1:0] data_line_in, - input wire data_line_in_valid, - input wire data_line_in_last, - input wire data_line_in_ctrl, - input wire data_line_in_prog, - input wire [NUM_PUS_PER_CLUSTER_BITS-1:0] data_line_in_pu, - output reg data_line_in_ready, - - output reg [DATA_LINE_WIDTH-1:0] data_line_out, - output reg data_line_out_valid, - output reg data_line_out_ctrl, - output reg data_line_out_last, - output reg data_line_out_prog, - output reg [NUM_PUS_PER_CLUSTER_BITS-1:0] data_line_out_pu, - - output reg [DATA_PRECISION-1:0] pu_tree_leaf_out, - output reg pu_tree_leaf_out_valid, - output reg pu_tree_leaf_out_last - ); - -localparam INSTRUCTION_DELAY = NUM_PUS_PER_CLUSTER - PE_ID - 1; // PU pipeline depth-1 - PU_ID -localparam TREE_MODE = 1'b0; -localparam DATA_MODE = 1'b1; -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Signals Declarations ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - - -TreeInstruction_t dp_tree_instruction; -wire dp_tree_instruction_valid; -wire dp_tree_instruction_ready; - -wire dp_data_mem_ren; -wire [31:0] dp_data_mem_feature; -wire [TUPLE_OFFSET_BITS:0] dp_data_mem_rd_addr; - -// tree memory read port A -wire [TREE_OFFSET_BITS:0] dp_tree_mem_rd_addr_a; -wire dp_tree_mem_ren_a; -TreeNode_t dp_tree_node_basic; -wire [63:0] dp_tree_node_basic_vec; - -// tree memory read port B -wire [TREE_OFFSET_BITS:0] dp_tree_mem_rd_addr_b; -wire dp_tree_mem_ren_b; -wire [31:0] dp_node_large_bitset; - -// result output -wire [31:0] dp_tree_eval_result; -wire dp_tree_eval_last; -wire dp_tree_eval_result_valid; - - -reg [1:0] curr_tree_id; -reg [8:0] curr_tuple_offset; -reg [9:0] time_stamp; -reg tuple_old_enough_set; - -wire tuple_instr_fifo_ready; -wire tuple_instr_fifo_valid; -wire [9:0] tuple_instr_fifo_dout; -wire tuple_instr_re; -wire tuple_old_enough; - - -wire curr_feature_done; -reg [9:0] features_mem_count; -reg [8:0] features_wr_addr; - -reg [2:0] local_num_trees; -reg [2:0] local_num_trees_minus_one; -reg [TREE_OFFSET_BITS-1:0] received_tree_lines; -reg [TREE_OFFSET_BITS-1:0] tree_prog_addr; -reg [TREE_OFFSET_BITS-1:0] tree_offsets[3:0]; -wire [TREE_OFFSET_BITS :0] tree_mem_addr_a; - -reg [4:0] num_trees_per_pu_minus_one; -reg [3:0] tree_depth; -reg [8:0] num_lines_per_tuple; - -reg [7:0] tree_addra[5:0]; -reg [7:0] tree_addrb[5:0]; - -reg [2:0] rd_a_count; -reg [2:0] rd_b_count; - -reg first_word_correct; -reg [63:0] first_word; -reg pe_state; - -reg [63:0] tree_mem_out_a; -reg [31:0] data_mem_out_a; -reg tree_out_a_set; -reg data_out_a_set; -wire dp_tree_valid_out1; -wire dp_data_mem_feature_valid; -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// PU Programming Logic ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -always @(posedge clk) begin - if(~rst_n) begin - data_line_out_valid <= 0; - data_line_out_last <= 0; - data_line_out_ctrl <= 0; - data_line_out_prog <= 0; - - pe_state <= TREE_MODE; - end - else begin - data_line_out_valid <= data_line_in_valid; - data_line_out_last <= data_line_in_last; - data_line_out_ctrl <= data_line_in_ctrl; - data_line_out_prog <= data_line_in_prog; - - if(data_line_in_valid | (pe_state == DATA_MODE) ) begin - pe_state <= DATA_MODE; - end - end - // - data_line_out <= data_line_in; - data_line_out_pu <= data_line_in_pu; -end - -always @(posedge clk) begin - if(~rst_n) begin - num_trees_per_pu_minus_one <= 5'b0; - tree_depth <= 4'b0; - num_lines_per_tuple <= 9'b0; - end - else if(data_line_in_ctrl) begin - num_trees_per_pu_minus_one <= data_line_in[4:0]; - tree_depth <= data_line_in[8+4-1:8]; - num_lines_per_tuple <= data_line_in[16+9-1:16]; - end -end - -//assign pu_debug_counters = {local_num_trees, received_tree_lines[8:0], tree_offsets[3][8:0], tree_offsets[2][8:0], tree_offsets[1][8:0], tree_offsets[0][8:0]}; -assign pu_debug_counters = {tree_addrb[5], tree_addrb[4], tree_addrb[3], tree_addrb[2], tree_addrb[1], tree_addrb[0], tree_addra[5], tree_addra[4], tree_addra[3], tree_addra[2], tree_addra[1], tree_addra[0]}; -assign pu_debug_counters2 = {tree_mem_out_a[31:0], first_word}; -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Memory Banks ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -genvar j; -generate for ( j = 0; j < 6; j=j+1) begin - always@(posedge clk) begin - if(~rst_n) begin - tree_addra[j] <= 0; - tree_addrb[j] <= 0; - end - else begin - if(dp_tree_mem_ren_a && (rd_a_count == j)) begin - tree_addra[j] <= tree_mem_addr_a[7:0]; - end - - if(dp_tree_mem_ren_b && (rd_b_count == j)) begin - tree_addrb[j] <= dp_tree_mem_rd_addr_b[7:0]; - end - end - end -end -endgenerate - -integer i; -always@(posedge clk) begin - if(~rst_n) begin - rd_a_count <= 0; - rd_b_count <= 0; - - tree_mem_out_a <= 0; - data_mem_out_a <= 0; - tree_out_a_set <= 1'b0; - data_out_a_set <= 1'b0; - first_word_correct <= 0; - first_word <= 0; - end - else begin - if(dp_tree_mem_ren_a && rd_a_count < 6) begin - rd_a_count <= rd_a_count + 1'b1; - end - - if(dp_tree_mem_ren_b && rd_b_count < 6) begin - rd_b_count <= rd_b_count + 1'b1; - end - // - if(dp_tree_valid_out1 && ~tree_out_a_set) begin - tree_mem_out_a <= dp_tree_node_basic_vec; - tree_out_a_set <= 1'b1; - end - - if(dp_data_mem_feature_valid && ~data_out_a_set) begin - data_mem_out_a <= dp_data_mem_feature; - data_out_a_set <= 1'b1; - end - - // - if((tree_prog_addr == 0) && (data_line_in_prog && (data_line_in_pu == PE_ID) )) begin - first_word_correct <= data_line_in[15:0] == 16'h200c; - first_word <= data_line_in; - end - end -end - - -//----------------------------- Tree Nodes Weight memory ------------------------------// -Tree_Memory #( .DATA_WIDTH(64), - .ADDR_WIDTH(11) ) -TreeNodes( - - .clk ( clk ), - .rst_n ( rst_n ), - .we ( data_line_in_prog && (data_line_in_pu == PE_ID) ), - .rea ( dp_tree_mem_ren_a ), - .reb ( dp_tree_mem_ren_b ), - .addr_port_a ( tree_mem_addr_a ), - .addr_port_b ( dp_tree_mem_rd_addr_b ), - .din ( data_line_in ), - .dout1 ( dp_tree_node_basic_vec ), - .valid_out1 ( dp_tree_valid_out1), - .dout2 ( dp_node_large_bitset ), - .valid_out2 () -); -assign dp_tree_node_basic.word_1_h = dp_tree_node_basic_vec[63:48]; -assign dp_tree_node_basic.word_1_l = dp_tree_node_basic_vec[47:32]; -assign dp_tree_node_basic.right_child_offset = dp_tree_node_basic_vec[31:16]; -assign dp_tree_node_basic.node_type.op_type = dp_tree_node_basic_vec[1:0]; -assign dp_tree_node_basic.node_type.left_child = dp_tree_node_basic_vec[2]; -assign dp_tree_node_basic.node_type.right_child = dp_tree_node_basic_vec[3]; -assign dp_tree_node_basic.node_type.findex = dp_tree_node_basic_vec[11:4]; -assign dp_tree_node_basic.node_type.split_dir = dp_tree_node_basic_vec[15:12]; - - -assign tree_mem_addr_a = ( pe_state == TREE_MODE )? {tree_prog_addr, 1'b0} : dp_tree_mem_rd_addr_a; - -always @(posedge clk) begin - // - if(~rst_n) begin - tree_prog_addr <= 0; - local_num_trees <= 0; - received_tree_lines <= 0; - - local_num_trees_minus_one <= 0; - - for (i = 0; i < 4; i++) begin - tree_offsets[ i ] <= 0; - end - end - else begin - local_num_trees_minus_one <= local_num_trees; - // - if(data_line_in_prog && (data_line_in_pu == PE_ID)) begin - tree_prog_addr <= tree_prog_addr + 1'b1; - received_tree_lines <= received_tree_lines + 1'b1; - - if(data_line_in_last && (local_num_trees[1:0] < num_trees_per_pu_minus_one[1:0])) begin - tree_offsets[ local_num_trees[1:0] + 1'b1 ] <= received_tree_lines + 1'b1; - local_num_trees <= local_num_trees + 1'b1; - end - end - end -end -//--------------------------- Input tuple features memory -----------------------------// -/* We write to the features memory when flags indicate incoming data is tuples and not programming data -*/ -Data_Memory #( .DATA_WIDTH(64), - .ADDR_WIDTH(10) ) -SamplesFeatures_Mem( - .clk (clk), - .rst_n (rst_n), - .we (data_line_in_valid), - .re (dp_data_mem_ren), - .raddr (dp_data_mem_rd_addr), - .waddr (features_wr_addr), - .din (data_line_in), - .dout (dp_data_mem_feature), - .valid_out (dp_data_mem_feature_valid) -); - -always @(posedge clk) begin - if(~rst_n) begin - features_wr_addr <= 9'b0; - features_mem_count <= 0; - end - else begin - features_wr_addr <= features_wr_addr + ((data_line_in_valid)? 9'd1 : 9'd0); - features_mem_count <= features_mem_count + ((data_line_in_valid)? 9'd1 : 9'd0) - ((curr_feature_done)? num_lines_per_tuple : 9'b0); - end -end - -assign curr_feature_done = dp_tree_eval_result_valid & dp_tree_eval_last; - -assign data_line_in_ready = tuple_instr_fifo_ready & (features_mem_count < (512- PE_ID - 1)); -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Tuple Instruction FIFO ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// -/* Once all features of a tuple are in features memory, we enqueue an instruction to execute all the - trees in the PU on the current tuple features, the instruction simply include the tuple offset. -*/ -RegBasedFIFO #(.FIFO_WIDTH(10), - .FIFO_DEPTH_BITS(2) - ) tuple_instr_fifo ( - .clk (clk), - .rst_n (rst_n), - .data_in ( time_stamp ), - .data_in_valid ( data_line_in_valid && data_line_in_last ), - .data_out_ready (tuple_instr_re), - .data_out (tuple_instr_fifo_dout), - .data_out_valid (tuple_instr_fifo_valid), - .data_in_ready (tuple_instr_fifo_ready) - ); - -assign tuple_instr_re = dp_tree_instruction_ready && (tuple_old_enough || tuple_old_enough_set) && (curr_tree_id == num_trees_per_pu_minus_one); - -assign tuple_old_enough = tuple_instr_fifo_valid && ((time_stamp <= tuple_instr_fifo_dout) || ((time_stamp - tuple_instr_fifo_dout) > INSTRUCTION_DELAY)); - -assign dp_tree_instruction_valid = tuple_instr_fifo_valid && (tuple_old_enough || tuple_old_enough_set); - -assign dp_tree_instruction = '{tree_offset: tree_offsets[curr_tree_id], - tuple_offset: curr_tuple_offset, - last_tree: (curr_tree_id == num_trees_per_pu_minus_one), - empty_tree: (curr_tree_id > local_num_trees)}; - -// Flags, counters used in issuing tree instructions to the datapath and synchronizing logic with other PEs. -always @(posedge clk) begin - if(~rst_n) begin - time_stamp <= 0; - tuple_old_enough_set <= 0; - curr_tuple_offset <= 0; - curr_tree_id <= 0; - end - else begin - // tuple_old_enough_set - tuple_old_enough_set <= (tuple_instr_re && tuple_instr_fifo_valid)? 1'b0 : (tuple_old_enough_set || tuple_old_enough); - - // time_stamp - time_stamp <= time_stamp + 1'b1; - - // curr_tuple_offset - if(tuple_instr_fifo_valid && tuple_instr_re) begin - curr_tuple_offset <= curr_tuple_offset + num_lines_per_tuple; - end - - // curr_tree_id - if(tuple_instr_fifo_valid && dp_tree_instruction_ready && (tuple_old_enough || tuple_old_enough_set)) begin - if(curr_tree_id == num_trees_per_pu_minus_one) begin - curr_tree_id <= 0; - end - else begin - curr_tree_id <= curr_tree_id + 1'b1; - end - end - end -end -//////////////////////////////////////////////////////////////////////////////////////////////////// -// PE Datapath -pe_datapath pe_datapath( - .clk (clk), - .rst_n (rst_n), - .tree_depth (tree_depth), - // tree instruction - .tree_instruction (dp_tree_instruction), - .tree_instruction_valid (dp_tree_instruction_valid), - .tree_instruction_ready (dp_tree_instruction_ready), - // data memory read port - .data_mem_rd_addr (dp_data_mem_rd_addr), - .data_mem_ren (dp_data_mem_ren), - .data_mem_feature (dp_data_mem_feature), - // tree memory read port A - .tree_mem_rd_addr_a (dp_tree_mem_rd_addr_a), - .tree_mem_ren_a (dp_tree_mem_ren_a), - .tree_node_basic (dp_tree_node_basic), - // tree memory read port B - .tree_mem_rd_addr_b (dp_tree_mem_rd_addr_b), - .tree_mem_ren_b (dp_tree_mem_ren_b), - .node_large_bitset (dp_node_large_bitset), - // result output - .tree_eval_result (dp_tree_eval_result), - .tree_eval_last (dp_tree_eval_last), - .tree_eval_result_valid (dp_tree_eval_result_valid) -); - -always @(posedge clk) begin - if(~rst_n) begin - pu_tree_leaf_out <= 0; - pu_tree_leaf_out_last <= 0; - pu_tree_leaf_out_valid <= 0; - end - else begin - pu_tree_leaf_out <= dp_tree_eval_result; - pu_tree_leaf_out_last <= dp_tree_eval_last; - pu_tree_leaf_out_valid <= dp_tree_eval_result_valid; - end -end - - - -endmodule // DTPU - - diff --git a/examples_hw/apps/gbm_dtrees/hdl/processing_element_async.sv b/examples_hw/apps/gbm_dtrees/hdl/processing_element_async.sv deleted file mode 100644 index 87929fcde..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/processing_element_async.sv +++ /dev/null @@ -1,453 +0,0 @@ - -/* - * Copyright 2019 - 2020 Systems Group, ETH Zurich - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - - -import DTPackage::*; - -/* - -*/ -module processing_element_async #(parameter PE_ID = 0 ) - ( - input wire clk, - input wire rst_n, - - input wire [DATA_LINE_WIDTH-1:0] data_line_in, - input wire data_line_in_valid, - input wire data_line_in_last, - input wire data_line_in_ctrl, - input wire data_line_in_prog, - input wire [NUM_PUS_PER_CLUSTER_BITS-1:0] data_line_in_pu, - output reg data_line_in_ready, - - output reg [DATA_LINE_WIDTH-1:0] data_line_out, - output reg data_line_out_valid, - output reg data_line_out_ctrl, - output reg data_line_out_last, - output reg data_line_out_prog, - output reg [NUM_PUS_PER_CLUSTER_BITS-1:0] data_line_out_pu, - - output reg [DATA_PRECISION-1:0] pu_tree_leaf_out, - output reg pu_tree_leaf_out_valid, - output reg pu_tree_leaf_out_last, - - // debug counters - output wire [95:0] pu_debug_counters, - output wire [95:0] pu_debug_counters2 - - ); - -localparam INSTRUCTION_DELAY = NUM_PUS_PER_CLUSTER - PE_ID - 1; // PU pipeline depth-1 - PU_ID -localparam TREE_MODE = 1'b0; -localparam DATA_MODE = 1'b1; -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Signals Declarations ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - - -TreeInstruction_t dp_tree_instruction; -wire dp_tree_instruction_valid; -wire dp_tree_instruction_ready; - -wire dp_data_mem_ren; -wire [31:0] dp_data_mem_feature; -wire [TUPLE_OFFSET_BITS:0] dp_data_mem_rd_addr; - -// tree memory read port A -wire [TREE_OFFSET_BITS:0] dp_tree_mem_rd_addr_a; -wire dp_tree_mem_ren_a; -TreeNode_t dp_tree_node_basic; -wire [63:0] dp_tree_node_basic_vec; - -// tree memory read port B -wire [TREE_OFFSET_BITS:0] dp_tree_mem_rd_addr_b; -wire dp_tree_mem_ren_b; -wire [31:0] dp_node_large_bitset; - -// result output -wire [31:0] dp_tree_eval_result; -wire dp_tree_eval_last; -wire dp_tree_eval_result_valid; - - -reg [2:0] curr_tree_id; -reg [8:0] curr_tuple_offset; -reg [9:0] time_stamp; -reg tuple_old_enough_set; - -wire tuple_instr_fifo_ready; -wire tuple_instr_fifo_valid; -wire [9:0] tuple_instr_fifo_dout; -wire tuple_instr_re; -wire tuple_old_enough; - - -wire curr_feature_done; -reg [9:0] features_mem_count; -reg [8:0] features_wr_addr; - -reg [2:0] local_num_trees; -reg [2:0] local_num_trees_minus_one; -reg [TREE_OFFSET_BITS-1:0] received_tree_lines; -reg [TREE_OFFSET_BITS-1:0] tree_prog_addr; -reg [TREE_OFFSET_BITS-1:0] tree_offsets[7:0]; -wire [TREE_OFFSET_BITS :0] tree_mem_addr_a; - -reg [4:0] num_trees_per_pu_minus_one; -reg [3:0] tree_depth; -reg [8:0] num_lines_per_tuple; - -reg [7:0] tree_addra[5:0]; -reg [7:0] tree_addrb[5:0]; - -reg [2:0] rd_a_count; -reg [2:0] rd_b_count; - -reg first_word_correct; -reg [63:0] first_word; -reg pe_state; - -reg [63:0] tree_mem_out_a; -reg [31:0] data_mem_out_a; -reg tree_out_a_set; -reg data_out_a_set; -wire dp_tree_valid_out1; -wire dp_data_mem_feature_valid; - -reg [31:0] num_tuples_received; -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// PU Programming Logic ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -always @(posedge clk) begin - if(~rst_n) begin - data_line_out_valid <= 0; - data_line_out_last <= 0; - data_line_out_ctrl <= 0; - data_line_out_prog <= 0; - - pe_state <= TREE_MODE; - - num_tuples_received <= 0; - end - else begin - data_line_out_valid <= data_line_in_valid; - data_line_out_last <= data_line_in_last; - data_line_out_ctrl <= data_line_in_ctrl; - data_line_out_prog <= data_line_in_prog; - - if(data_line_in_valid | (pe_state == DATA_MODE) ) begin - pe_state <= DATA_MODE; - end - - if(data_line_in_valid && data_line_in_last) begin - num_tuples_received <= num_tuples_received + 1'b1; - end - end - // - data_line_out <= data_line_in; - data_line_out_pu <= data_line_in_pu; -end - -always @(posedge clk) begin - if(~rst_n) begin - num_trees_per_pu_minus_one <= 5'b0; - tree_depth <= 4'b0; - num_lines_per_tuple <= 9'b0; - end - else if(data_line_in_ctrl) begin - num_trees_per_pu_minus_one <= data_line_in[4:0]; - tree_depth <= data_line_in[8+4-1:8]; - num_lines_per_tuple <= data_line_in[16+9-1:16]; - end -end - -//assign pu_debug_counters = {local_num_trees, received_tree_lines[8:0], tree_offsets[3][8:0], tree_offsets[2][8:0], tree_offsets[1][8:0], tree_offsets[0][8:0]}; -assign pu_debug_counters = {tree_addrb[5], tree_addrb[4], tree_addrb[3], tree_addrb[2], tree_addrb[1], tree_addrb[0], tree_addra[5], tree_addra[4], tree_addra[3], tree_addra[2], tree_addra[1], tree_addra[0]}; -assign pu_debug_counters2 = {tree_mem_out_a[31:0], first_word}; -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Memory Banks ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -genvar j; -generate for ( j = 0; j < 6; j=j+1) begin - always@(posedge clk) begin - if(~rst_n) begin - tree_addra[j] <= 0; - tree_addrb[j] <= 0; - end - else begin - if(dp_tree_mem_ren_a && (rd_a_count == j)) begin - tree_addra[j] <= tree_mem_addr_a[7:0]; - end - - if(dp_tree_mem_ren_b && (rd_b_count == j)) begin - tree_addrb[j] <= dp_tree_mem_rd_addr_b[7:0]; - end - end - end -end -endgenerate - -integer i; -always@(posedge clk) begin - if(~rst_n) begin - rd_a_count <= 0; - rd_b_count <= 0; - - tree_mem_out_a <= 0; - data_mem_out_a <= 0; - tree_out_a_set <= 1'b0; - data_out_a_set <= 1'b0; - first_word_correct <= 0; - first_word <= 0; - end - else begin - if(dp_tree_mem_ren_a && rd_a_count < 6) begin - rd_a_count <= rd_a_count + 1'b1; - end - - if(dp_tree_mem_ren_b && rd_b_count < 6) begin - rd_b_count <= rd_b_count + 1'b1; - end - // - if(dp_tree_valid_out1 && ~tree_out_a_set) begin - tree_mem_out_a <= dp_tree_node_basic_vec; - tree_out_a_set <= 1'b1; - end - - if(dp_data_mem_feature_valid && ~data_out_a_set) begin - data_mem_out_a <= dp_data_mem_feature; - data_out_a_set <= 1'b1; - end - - // - if((tree_prog_addr == 0) && (data_line_in_prog && (data_line_in_pu == PE_ID) )) begin - first_word_correct <= data_line_in[15:0] == 4'h200c; - first_word <= data_line_in; - end - end -end - - -//----------------------------- Tree Nodes Weight memory ------------------------------// -Tree_Memory #( .DATA_WIDTH(64), - .ADDR_WIDTH(11) ) -TreeNodes( - - .clk ( clk ), - .rst_n ( rst_n ), - .we ( data_line_in_prog && (data_line_in_pu == PE_ID) ), - .rea ( dp_tree_mem_ren_a ), - .reb ( dp_tree_mem_ren_b ), - .addr_port_a ( tree_mem_addr_a ), - .addr_port_b ( dp_tree_mem_rd_addr_b ), - .din ( data_line_in ), - .dout1 ( dp_tree_node_basic_vec ), - .valid_out1 ( dp_tree_valid_out1), - .dout2 ( dp_node_large_bitset ), - .valid_out2 () -); -assign dp_tree_node_basic.word_1_h = dp_tree_node_basic_vec[63:48]; -assign dp_tree_node_basic.word_1_l = dp_tree_node_basic_vec[47:32]; -assign dp_tree_node_basic.right_child_offset = dp_tree_node_basic_vec[31:16]; -assign dp_tree_node_basic.node_type.op_type = dp_tree_node_basic_vec[1:0]; -assign dp_tree_node_basic.node_type.left_child = dp_tree_node_basic_vec[2]; -assign dp_tree_node_basic.node_type.right_child = dp_tree_node_basic_vec[3]; -assign dp_tree_node_basic.node_type.findex = dp_tree_node_basic_vec[11:4]; -assign dp_tree_node_basic.node_type.split_dir = dp_tree_node_basic_vec[15:12]; - - -assign tree_mem_addr_a = ( pe_state == TREE_MODE )? {tree_prog_addr, 1'b0} : dp_tree_mem_rd_addr_a; - -always @(posedge clk) begin - // - if(~rst_n) begin - tree_prog_addr <= 0; - local_num_trees <= 0; - received_tree_lines <= 0; - - local_num_trees_minus_one <= 0; - - for (i = 0; i < 8; i++) begin - tree_offsets[ i ] <= 0; - end - end - else begin - local_num_trees_minus_one <= local_num_trees; - // - if(data_line_in_prog && (data_line_in_pu == PE_ID)) begin - tree_prog_addr <= tree_prog_addr + 1'b1; - received_tree_lines <= received_tree_lines + 1'b1; - - if(data_line_in_last && (local_num_trees[2:0] < num_trees_per_pu_minus_one[2:0])) begin - tree_offsets[ local_num_trees[2:0] + 1'b1 ] <= received_tree_lines + 1'b1; - local_num_trees <= local_num_trees + 1'b1; - end - end - end -end -//--------------------------- Input tuple features memory -----------------------------// -/* We write to the features memory when flags indicate incoming data is tuples and not programming data -*/ -Data_Memory #( .DATA_WIDTH(64), - .ADDR_WIDTH(10) ) -SamplesFeatures_Mem( - .clk (clk), - .rst_n (rst_n), - .we (data_line_in_valid), - .re (dp_data_mem_ren), - .raddr (dp_data_mem_rd_addr), - .waddr (features_wr_addr), - .din (data_line_in), - .dout (dp_data_mem_feature), - .valid_out (dp_data_mem_feature_valid) -); - -always @(posedge clk) begin - if(~rst_n) begin - features_wr_addr <= 9'b0; - features_mem_count <= 0; - end - else begin - features_wr_addr <= features_wr_addr + ((data_line_in_valid)? 9'd1 : 9'd0); - features_mem_count <= features_mem_count + ((data_line_in_valid)? 9'd1 : 9'd0) - ((curr_feature_done)? num_lines_per_tuple : 9'b0); - end -end - -assign curr_feature_done = dp_tree_eval_result_valid & dp_tree_eval_last; - - -always @(posedge clk) begin - if(~rst_n) begin - data_line_in_ready <= 0; - end - else begin - data_line_in_ready <= tuple_instr_fifo_ready & (features_mem_count < (512- PE_ID - 4)); - end -end -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Tuple Instruction FIFO ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// -/* Once all features of a tuple are in features memory, we enqueue an instruction to execute all the - trees in the PU on the current tuple features, the instruction simply include the tuple offset. -*/ -RegBasedFIFO #(.FIFO_WIDTH(1), - .FIFO_DEPTH_BITS(2) - ) tuple_instr_fifo ( - .clk (clk), - .rst_n (rst_n), - .data_in ( 1'b1 ), - .data_in_valid ( data_line_in_valid && data_line_in_last ), - .data_out_ready (tuple_instr_re), - .data_out (tuple_instr_fifo_dout), - .data_out_valid (tuple_instr_fifo_valid), - .data_in_ready (tuple_instr_fifo_ready) - ); - -assign tuple_instr_re = dp_tree_instruction_ready && (curr_tree_id == num_trees_per_pu_minus_one); - -assign dp_tree_instruction_valid = tuple_instr_fifo_valid; - -assign dp_tree_instruction = '{tree_offset: tree_offsets[curr_tree_id], - tuple_offset: curr_tuple_offset, - last_tree: (curr_tree_id == num_trees_per_pu_minus_one), - empty_tree: (curr_tree_id > local_num_trees)}; - -// Flags, counters used in issuing tree instructions to the datapath and synchronizing logic with other PEs. -always @(posedge clk) begin - if(~rst_n) begin - curr_tuple_offset <= 0; - curr_tree_id <= 0; - end - else begin - // curr_tuple_offset - if(tuple_instr_fifo_valid && tuple_instr_re) begin - curr_tuple_offset <= curr_tuple_offset + num_lines_per_tuple; - end - - // curr_tree_id - if(tuple_instr_fifo_valid && dp_tree_instruction_ready) begin - if(curr_tree_id == num_trees_per_pu_minus_one) begin - curr_tree_id <= 0; - end - else begin - curr_tree_id <= curr_tree_id + 1'b1; - end - end - end -end -//////////////////////////////////////////////////////////////////////////////////////////////////// -// PE Datapath -pe_datapath pe_datapath( - .clk (clk), - .rst_n (rst_n), - .tree_depth (tree_depth), - // tree instruction - .tree_instruction (dp_tree_instruction), - .tree_instruction_valid (dp_tree_instruction_valid), - .tree_instruction_ready (dp_tree_instruction_ready), - // data memory read port - .data_mem_rd_addr (dp_data_mem_rd_addr), - .data_mem_ren (dp_data_mem_ren), - .data_mem_feature (dp_data_mem_feature), - // tree memory read port A - .tree_mem_rd_addr_a (dp_tree_mem_rd_addr_a), - .tree_mem_ren_a (dp_tree_mem_ren_a), - .tree_node_basic (dp_tree_node_basic), - // tree memory read port B - .tree_mem_rd_addr_b (dp_tree_mem_rd_addr_b), - .tree_mem_ren_b (dp_tree_mem_ren_b), - .node_large_bitset (dp_node_large_bitset), - // result output - .tree_eval_result (dp_tree_eval_result), - .tree_eval_last (dp_tree_eval_last), - .tree_eval_result_valid (dp_tree_eval_result_valid) -); - - -always @(posedge clk) begin - if(~rst_n) begin - pu_tree_leaf_out <= 0; - pu_tree_leaf_out_last <= 0; - pu_tree_leaf_out_valid <= 0; - end - else begin - pu_tree_leaf_out <= dp_tree_eval_result; - pu_tree_leaf_out_last <= dp_tree_eval_last; - pu_tree_leaf_out_valid <= dp_tree_eval_result_valid; - end -end - - -endmodule // DTPU - - diff --git a/examples_hw/apps/gbm_dtrees/hdl/quick_fifo.sv b/examples_hw/apps/gbm_dtrees/hdl/quick_fifo.sv deleted file mode 100644 index 79360b2e9..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/quick_fifo.sv +++ /dev/null @@ -1,149 +0,0 @@ - -/* - * Copyright 2019 - 2020 Systems Group, ETH Zurich - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - - -module quick_fifo #( - parameter FIFO_WIDTH = 32, - parameter FIFO_DEPTH_BITS = 8, - parameter FIFO_ALMOSTFULL_THRESHOLD = 2**FIFO_DEPTH_BITS - 4 -) ( - input wire clk, - input wire reset_n, - - input wire we, // input write enable - input wire [FIFO_WIDTH - 1:0] din, // input write data with configurable width - - input wire re, // input read enable - output reg valid, // dout valid - output reg [FIFO_WIDTH - 1:0] dout, // output read data with configurable width - - output reg [FIFO_DEPTH_BITS - 1:0] count, // output FIFOcount - output reg empty, // output FIFO empty - output reg full, // output FIFO full - output reg almostfull // output configurable programmable full/ almost full -); - - reg [FIFO_DEPTH_BITS - 1:0] rp = 0; - reg [FIFO_DEPTH_BITS - 1:0] wp = 0; - - reg [FIFO_DEPTH_BITS - 1:0] mem_count = 0; // output FIFOcount - reg mem_empty = 1'b1; - - reg valid_t1 = 0, valid_t2 = 0; - reg valid0 = 0; - - wire remem; - wire wemem; - wire remem_valid; - - wire [FIFO_WIDTH-1:0] dout_mem; - - assign remem = (re & valid_t1 & valid_t2) | ~(valid_t1 & valid_t2); - assign wemem = we & ~full; - - assign remem_valid = remem & ~mem_empty; - - - bram #(.DATA_WIDTH(FIFO_WIDTH), - .ADDR_WIDTH(FIFO_DEPTH_BITS)) fifo_mem( - .clk (clk), - .we (wemem), - .re (remem), - .raddr (rp), - .waddr (wp), - .din (din), - .dout (dout_mem) - ); - - // data - always @(posedge clk) begin - dout <= (valid_t2)? ((re)? dout_mem : dout) : dout_mem; - end - - // valids, flags - always @(posedge clk) begin - if (~reset_n) begin - empty <= 1'b1; - full <= 1'b0; - almostfull <= 1'b0; - count <= 0; //32'b0; - rp <= 0; - wp <= 0; - valid_t2 <= 1'b0; - valid_t1 <= 1'b0; - mem_empty <= 1'b1; - mem_count <= 'b0; - - //dout <= 0; - valid <= 0; - valid0 <= 0; - end - - else begin - - valid <= (valid)? ((re)? valid0 : 1'b1) : valid0; - valid0 <= (remem)? ~mem_empty : valid0; - - valid_t2 <= (valid_t2)? ((re)? valid_t1 : 1'b1) : valid_t1; - - valid_t1 <= (remem)? ~mem_empty : valid_t1; - rp <= (remem & ~mem_empty)? (rp + 1'b1) : rp; - wp <= (wemem)? (wp + 1'b1) : wp; - - // mem_empty - if (we) mem_empty <= 1'b0; - else if(remem & (mem_count == 1'b1)) mem_empty <= 1'b1; - - // mem_count - if( wemem & ~remem_valid) mem_count <= mem_count + 1'b1; - else if (~wemem & remem_valid) mem_count <= mem_count - 1'b1; - - - // empty - if (we) empty <= 1'b0; - else if((re & valid_t2 & ~valid_t1) & (count == 1'b1)) empty <= 1'b1; - - // count - if( wemem & (~(re & valid_t2) | ~re) ) count <= count + 1'b1; - else if (~wemem & (re & valid_t2)) count <= count - 1'b1; - - // - if (we & ~re) begin - - if (count == (2**FIFO_DEPTH_BITS-1)) - full <= 1'b1; - - if (count == (FIFO_ALMOSTFULL_THRESHOLD-1)) - almostfull <= 1'b1; - end - // - if ((~we | full) & re) begin // - full <= 1'b0; - - if (count == FIFO_ALMOSTFULL_THRESHOLD) - almostfull <= 1'b0; - end - end - end - -endmodule diff --git a/examples_hw/apps/gbm_dtrees/hdl/smart_shifter.sv b/examples_hw/apps/gbm_dtrees/hdl/smart_shifter.sv deleted file mode 100644 index 65331caed..000000000 --- a/examples_hw/apps/gbm_dtrees/hdl/smart_shifter.sv +++ /dev/null @@ -1,83 +0,0 @@ - -/* - * Copyright 2019 - 2020 Systems Group, ETH Zurich - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - - -module smart_shifter #(parameter ELEMENTS_PER_CL = 16, - parameter ELEMENTS_PER_CL_BITS = 4) - ( - input wire clk, - input wire rst_n, - - input wire inValid, - input wire inLast, - input wire [3:0] inOffs, - input wire [1023:0] inData, - - output wire outValid, - output wire outLast, - output reg [511:0] outData - ); - - reg [1023:0] shData [14:0]; - reg [3:0] shOffs [14:0]; - - integer i; - - always @(posedge clk) begin - // Level 0 - if ( |inOffs ) begin - shData[0] <= {32'b0, inData[1023:32]}; - shOffs[0] <= inOffs - 4'd1; - end - else begin - shData[0] <= inData; - shOffs[0] <= inOffs; - end - // Rest of levels: Data, shOffs - for ( i = 0; i <14; i = i+1) begin - if ( |shOffs[i] ) begin - shData[i+1] <= {32'b0, shData[i][1023:32]}; - shOffs[i+1] <= shOffs[i] - 4'd1; - end - else begin - shData[i+1] <= shData[i]; - shOffs[i+1] <= shOffs[i]; - end - end - - outData <= shData[14][511:0]; - end - // - - delay #(.DATA_WIDTH(1), - .DELAY_CYCLES(16) - ) validDelay( - .clk (clk), - .rst_n (rst_n), - .data_in ( inLast ), // - .data_in_valid ( inValid ), - .data_out ( outLast ), - .data_out_valid ( outValid ) - ); - -endmodule diff --git a/examples_hw/apps/gbm_dtrees/init_ip.tcl b/examples_hw/apps/gbm_dtrees/init_ip.tcl deleted file mode 100644 index 44e4ad4a6..000000000 --- a/examples_hw/apps/gbm_dtrees/init_ip.tcl +++ /dev/null @@ -1,2 +0,0 @@ -create_ip -name vio -vendor xilinx.com -library ip -version 3.0 -module_name vio_gbm -set_property -dict [list CONFIG.C_PROBE_IN2_WIDTH {32} CONFIG.C_PROBE_IN1_WIDTH {32} CONFIG.C_PROBE_IN0_WIDTH {32} CONFIG.C_NUM_PROBE_OUT {0} CONFIG.C_NUM_PROBE_IN {3} CONFIG.Component_Name {vio_gbm}] [get_ips vio_gbm] \ No newline at end of file diff --git a/examples_hw/apps/gbm_dtrees/vfpga_top.svh b/examples_hw/apps/gbm_dtrees/vfpga_top.svh deleted file mode 100644 index 86aa97f99..000000000 --- a/examples_hw/apps/gbm_dtrees/vfpga_top.svh +++ /dev/null @@ -1,240 +0,0 @@ -/** - * VFPGA TOP - * - * Tie up all signals to the user kernels - * Still to this day, interfaces are not supported by Vivado packager ... - * This means verilog style port connections are needed. - * - */ - -// -// Instantiate top level -// - -// UL -AXI4SR axis_sink (); -AXI4SR axis_src (); - -axisr_reg inst_reg_sink (.aclk(aclk), .aresetn(aresetn), .s_axis(axis_host_recv[0]), .m_axis(axis_sink)); -axisr_reg inst_reg_src (.aclk(aclk), .aresetn(aresetn), .s_axis(axis_src), .m_axis(axis_host_send[0])); - -// GBM dtrees -localparam [1:0] IDLE = 2'b00, - READ_TREES = 2'b01, - WAIT_ALL_TREES = 2'b10, - READ_DATA = 2'b11; - -reg [1:0] reader_state; -reg [1:0] nxt_reader_state; -wire trees_read_done; -wire data_read_done; - -wire wr_tvalid; -wire wr_tready; -wire [511:0] wr_tdata; - -wire rd_tvalid; -wire rd_ttype; -wire rd_tlast; -wire rd_tready; -wire [511:0] rd_tdata; - -reg [31:0] sentOutCLs; -wire [31:0] next_sentOutCLs; - -logic ap_start_r = 1'b0; -logic ap_start_pulse_d1 = 1'b0; -wire ap_start ; -wire [16-1:0] numFeatures ; -wire [8-1:0] treeDepth ; -wire [8-1:0] puTrees ; -wire [16-1:0] lastOutLineMask ; -wire [31:0] outputNumCLs; - -logic [16-1:0] num_64bit_words_per_tuple; -logic [8-1:0] num_trees_per_pu_minus_one; - -logic [31:0] num_data_cls; -logic [31:0] num_trees_cls; -logic [31:0] num_result_cls; - -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Parameters on AxiLite ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -// AXI4-Lite slave interface -gbm_slave inst_control_s_axi ( - .aclk ( aclk ), - .aresetn ( aresetn ), - .axi_ctrl ( axi_ctrl ), - .ap_start ( ap_start ), - .numFeatures ( numFeatures ), - .treeDepth ( treeDepth ), - .puTrees ( puTrees ), - .outputNumCLs ( outputNumCLs ), - .lastOutLineMask ( lastOutLineMask ) -); - -always @(posedge aclk) begin - if (~aresetn) begin - num_trees_per_pu_minus_one <= 0; - num_64bit_words_per_tuple <= 0; - - ap_start_r <= 0; - ap_start_pulse_d1 <= 0; - end - else begin - num_trees_per_pu_minus_one <= puTrees - 1'b1; - num_64bit_words_per_tuple <= numFeatures[7:1] + numFeatures[0]; - - ap_start_r <= ap_start; - ap_start_pulse_d1 <= ap_start_pulse; - end -end - -assign ap_start_pulse = ap_start & ~ap_start_r; -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Decode Input Streams ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -// Reader State -always@(posedge aclk) begin - if(~aresetn) begin - reader_state <= IDLE; - end - else begin - reader_state <= nxt_reader_state; - end -end - -always@(*) begin - case (reader_state) - IDLE : nxt_reader_state = (ap_start_pulse_d1)? READ_TREES : IDLE; - READ_TREES : nxt_reader_state = (trees_read_done)? WAIT_ALL_TREES: READ_TREES; - WAIT_ALL_TREES: nxt_reader_state = READ_DATA; - READ_DATA : nxt_reader_state = (data_read_done)? IDLE : READ_DATA; - default : nxt_reader_state = IDLE; - endcase -end - -assign trees_read_done = axis_sink.tlast && axis_sink.tvalid && axis_sink.tready; -assign data_read_done = axis_sink.tlast && axis_sink.tvalid && axis_sink.tready; - - -//////////////////////////////////////////////////////////////////////////////////////////////////// -////////////////////////////////////// ////////////////////////////////// -////////////////////////////// Engine Core ///////////////////////// -////////////////////////////////////// ////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////// - -// Input Streams -assign rd_tdata = axis_sink.tdata; -assign rd_tvalid = axis_sink.tvalid; -assign rd_tlast = axis_sink.tlast; -assign rd_ttype = reader_state == READ_DATA; - -assign axis_sink.tready = rd_tready && (reader_state == READ_TREES || reader_state == READ_DATA); - -// Output Stream -assign axis_src.tdata = wr_tdata; -assign axis_src.tkeep = 64'hffffffffffffffff; -assign axis_src.tid = 0; -assign axis_src.tvalid = wr_tvalid; -assign axis_src.tlast = next_sentOutCLs == outputNumCLs; - -assign wr_tready = axis_src.tready; - -// Count output numCLs - -assign next_sentOutCLs = sentOutCLs + 1'b1; - -always@(posedge aclk) begin - if(~aresetn) begin - sentOutCLs <= 0; - end - else begin - if(sentOutCLs == outputNumCLs) begin - sentOutCLs <= 0; - end - else if(wr_tvalid && wr_tready) begin - sentOutCLs <= next_sentOutCLs; - end - end -end - - -DTProcessor DTProcessor( - .clk (aclk), - .rst_n (aresetn), - .start_core (ap_start_pulse_d1), - // parameters - - .tuple_length (numFeatures[5:0]), - .num_trees_per_pu_minus_one (num_trees_per_pu_minus_one[4:0]), - .tree_depth (treeDepth[3:0]), - .num_lines_per_tuple ({2'b00, num_64bit_words_per_tuple[6:0]}), - // input trees - .core_data_in (rd_tdata), - .core_data_in_type (rd_ttype), - .core_data_in_valid (rd_tvalid), - .core_data_in_last (rd_tlast), - .core_data_in_ready (rd_tready), - // output - .last_result_line ( (next_sentOutCLs == outputNumCLs) ), - .last_result_line_mask (lastOutLineMask[15:0]), - .core_result_out (wr_tdata), - .core_result_valid (wr_tvalid), - .core_result_ready (wr_tready) -); - -//////////////////////////////////////////////////////////////////////////////////////////////////// -// debug counters -always@(posedge aclk) begin - if(~aresetn) begin - num_data_cls <= 0; - num_trees_cls <= 0; - num_result_cls <= 0; - end - else begin - // - if(ap_start_pulse) begin - num_data_cls <= 0; - num_trees_cls <= 0; - num_result_cls <= 0; - end - else begin - // - if(rd_tvalid && rd_tready && rd_ttype) begin - num_data_cls <= num_data_cls + 1'b1; - end - // - if(rd_tvalid && rd_tready && !rd_ttype) begin - num_trees_cls <= num_trees_cls + 1'b1; - end - // - if(wr_tvalid && wr_tready) begin - num_result_cls <= num_result_cls + 1'b1; - end - end - end -end - - -// Tie-off the rest of the interfaces -always_comb notify.tie_off_m(); -always_comb sq_rd.tie_off_m(); -always_comb sq_wr.tie_off_m(); -always_comb cq_rd.tie_off_s(); -always_comb cq_wr.tie_off_s(); - -// ILA -vio_gbm inst_vio_gbm ( - .clk(aclk), - .probe_in0(num_data_cls), // 32 - .probe_in1(num_trees_cls), // 32 - .probe_in2(num_result_cls) // 32 -); diff --git a/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/Collector.hpp b/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/Collector.hpp deleted file mode 100644 index 335f94b4d..000000000 --- a/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/Collector.hpp +++ /dev/null @@ -1,144 +0,0 @@ -#ifndef COLLECTOR_HPP -#define COLLECTOR_HPP - -#include -#include - -#include "stream.hpp" - -/** - * Statistics collector over an input stream using a key space of 2**K and - * the value type TV. - */ -template< - unsigned K, - typename TV -> -class Collector { - - static unsigned const FEED = 0; - static unsigned const SETTLE1 = 1; - static unsigned const SETTLE2 = 2; - static unsigned const DUMP = 3; - using TK = ap_uint; - - unsigned state = FEED; - TK dump_ptr = 0; - TV mem[1< - void collect( - F &&f, // Update Value Folding Function: (TV, TV) -> TV - hls::stream &src, // Input: tixl(x) -> last, tixk(x) -> key, tixv(x) -> val - hls::stream &dst, // Output: toxl(y) <- last, toxv(y) <- val - TIXL &&tixl = TIXL(), // default: TI.last - TIXK &&tixk = TIXK(), // default: TI.key - TIXV &&tixv = TIXV(), // default: TI.val - TOXL &&toxl = TOXL(), // default: TO.last - TOXV &&toxv = TOXV() // default: TO.val - ) { -#pragma HLS inline off -#pragma HLS pipeline II=1 - -#if defined( __VITIS_HLS__) - #pragma HLS bind_storage variable=mem type=RAM_T2P impl=BRAM -#else - #pragma HLS RESOURCE variable=mem core=RAM_T2P_BRAM -#endif - -#pragma HLS DEPENDENCE variable=mem inter distance=2 - - // Execute pending Memory Update and Output - bool const z_stb0 = z_stb; - TK const z_key0 = z_key; - TV const z_val0 = z_val; - if(z_stb) mem[z_key] = z_val; - - if(y_stb) { - TO y; - toxl(y) = y_last; - toxv(y) = y_val; - if(dst.write_nb(y)) y_stb = false; - } - - // Controlling FSM - switch(state) { - - // Read and process Data - case FEED: { - TI x; - bool const x_stb = src.read_nb(x); - TK const x_key = tixk(x); - bool const z_match = z_stb && (z_key == x_key); - bool const zz_match = zz_stb && (zz_key == x_key); - bool const zzz_match = zzz_stb && (zzz_key == x_key); - TV const x_val = f(tixv(x), z_match? z_val : zz_match? zz_val : zzz_match? zzz_val : mem[x_key]); - - z_stb = x_stb; - z_key = x_key; - z_val = x_val; - if(x_stb && tixl(x)) state = SETTLE1; - } - break; - - // Cover Memory Update Latency - case SETTLE1: state = SETTLE2; break; - case SETTLE2: state = DUMP; break; - - // Stream out Contents - case DUMP: { - if(!y_stb) { - bool const last = ~dump_ptr == 0; - - y_stb = true; - y_last = last; - y_val = mem[dump_ptr]; - - z_stb = true; - z_key = dump_ptr; - z_val = 0; - - if(last) state = FEED; - dump_ptr++; - } - } - break; - } - zzz_stb = zz_stb; - zzz_key = zz_key; - zzz_val = zz_val; - zz_stb = z_stb0; - zz_key = z_key0; - zz_val = z_val0; - - } // collect() - -}; // class Collector - -#endif diff --git a/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/HllSketch.hpp b/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/HllSketch.hpp deleted file mode 100644 index 426bc6deb..000000000 --- a/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/HllSketch.hpp +++ /dev/null @@ -1,183 +0,0 @@ -#ifndef HLLSKETCH_HPP -#define HLLSKETCH_HPP - -#include "Collector.hpp" -#include "stream.hpp" -#include "bit_utils.hpp" -#include "hls_math.h" - -#include - -template< - unsigned H, // Total Number of Hash Bits - unsigned P // Precision: Bits used to differentiate Buckets -> -class HllEstimator { - static unsigned constexpr M = 1u<= 128 - - /** - * Exact accumulation until float conversion for output for M=2^P buckets: - * - * | <- P -> . <- H-P+1 -> | - * - * Numeric Range: - * 0.0 .. (2^P)*1.0 - * - * All values are represented exact except for the maximum final result - * in the case that *all* buckets report a rank of zero, i.e. empty. The - * accumulator will then be ignored in favor of linear counting. - */ - using accu_t = ap_ufixed; - ap_uint zeros = 0; - accu_t accu = 0; - -public: - template - void collect(TR rank) { -#pragma HLS inline - if(rank == 0) zeros++; - accu_t d = 0; // d = 2^(-rank) - d[H-P+1 - rank] = 1; - accu += d; - - } // collect() - -public: - float estimate() { -#pragma HLS inline - // Raw Cardinality - float card = ALPHAM2 / accu.to_float(); - - // Estimate Refinement - if(card <= 2.5*M){ - // Linear Counting if there are empty Buckets - if(zeros != 0) card = M*logf((float)M / (float)zeros); - } - - // State Reset - zeros = 0; - accu = 0; - - return card; - - } // estimate() - -}; // HllEstimator - -template< - unsigned N, - unsigned H, // Total Number of Hash Bits - unsigned P // Precision: Bits used to differentiate Buckets -> -class HllSketch { - using buck_t = ap_uint

; // Key - using rank_t = ap_uint::value>; // Rank: 0, 1, .., (H-P+1) - using ranked_t = flit_kv_t; - using res_t = flit_v_t; - - //- Structure ----------------------------------------------------------- - hls::stream ranked[N]; - Collector collector[N]; - hls::stream dsti[N]; - HllEstimator estimator; - -public: - template< - typename TIXL = MemberLast, - typename TIXV = MemberVal, - typename TOXL = MemberLast, - typename TOXV = MemberVal, - typename TI, - typename TO - > - void sketch( - hls::stream (&src)[N], - hls::stream &dst, - TIXL &&tixl = TIXL(), // TI.last - TIXV &&tixv = TIXV(), // TI.val - TOXL &&toxl = TOXL(), // TO.last - TOXV &&toxv = TOXV() // TO.val - ) { -#pragma HLS inline off -#pragma HLS dataflow -#pragma HLS array_partition variable=collector dim=1 - -#if defined( __VITIS_HLS__) - #pragma HLS aggregate variable=ranked compact=bit - #pragma HLS aggregate variable=dsti compact=bit -#else - #pragma HLS data_pack variable=ranked - #pragma HLS data_pack variable=dsti -#endif - - rank(src, tixl, tixv); - collect(); - fold(dst, toxl, toxv); - - } // sketch() - -private: - template - void rank(hls::stream (&src)[N], TIXL &&tixl, TIXV &&tixv) { -#pragma HLS inline off -#pragma HLS pipeline II=1 - auto const f_rank = [&tixl,&tixv](TI const& x)->ranked_t{ -#pragma HLS inline - auto const& hash = tixv(x); - return ranked_t{tixl(x), hash(H-1, H-P), 1+btl::clz(ap_uint(hash))}; - }; - for(unsigned i = 0; i < N; i++) { -#pragma HLS unroll - stage_guarded(src[i], ranked[i], f_rank); - } - } // rank() - - void collect() { -#pragma HLS inline - for(unsigned i = 0; i < N; i++) { -#pragma HLS unroll - collector[i].collect( - [](rank_t const &a, rank_t const &b)->rank_t{ return std::max(a, b); }, - ranked[i], dsti[i]); - } - } // collect() - - template - void fold(hls::stream &dst, TOXL &&toxl, TOXV &&toxv) { -#pragma HLS pipeline II=1 - ap_uint empty; - for(unsigned i = 0; i < N; i++) { -#pragma HLS unroll - empty[i] = dsti[i].empty(); - } - if(empty == 0) { - - // Maximum Fold across parallel Channels - bool last = false; - rank_t rank = 0; - for(unsigned i = 0; i < N; i++) { -#pragma HLS unroll - res_t x; - dsti[i].read_nb(x); - last |= x.last; - rank = std::max(rank, x.val); - } - - // HLL Metrics Update - estimator.collect(rank); - - // Result Output - if(last) { - TO y{}; - toxl(y) = true; - toxv(y) = estimator.estimate(); - dst.write(y); - } - } - - } // fold() - -}; // class HllSketch - -#endif diff --git a/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/bit_utils.hpp b/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/bit_utils.hpp deleted file mode 100644 index 5194eb980..000000000 --- a/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/bit_utils.hpp +++ /dev/null @@ -1,165 +0,0 @@ -/**************************************************************************** - * Copyright (c) 2020, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - **************************************************************************** - * @brief - * Utilities for de- and transcoding low-level data representations. - * - * This implementation is fiercely templated and supports both signed and - * unsigned representations as ap_(u)int as much as semantically sensible. - * - * @author - * Thomas B. Preußer - ****************************************************************************/ -#ifndef BIT_UTILS_HPP -#define BIT_UTILS_HPP - -#include - -namespace btl { // Part of the Bit-level Template Library -//--------------------------------------------------------------------------- -// Compile-Time Arithmetic: LOG2 / POW2 - -// As soon as the HLS compiler supports modern C++ features, -// the template computations below may be simplified to: -// constexpr unsigned flog2(unsigned n) { return n < 2? 0 : 1+flog2(n/2); } -// constexpr unsigned clog2(unsigned n) { return n < 2? 0 : 1+flog2(n-1); } -// constexpr unsigned pow2 (unsigned n) { return n == 0? 1 : 2*pow2(n-1); } - -/** floor(log2(N)) */ -template struct flog2 { - static unsigned const value = 1+flog2::value; -}; -template<> struct flog2<0> {}; -template<> struct flog2<1> { - static unsigned const value = 0; -}; - -/** ceil(log2(N)) */ -template struct clog2 { - static unsigned const value = 1+flog2::value; -}; -template<> struct clog2<0> {}; -template<> struct clog2<1> { - static unsigned const value = 0; -}; - -/** 2**N */ -template struct pow2 { - static unsigned const value = 2*pow2::value; -}; -template<> struct pow2<0> { - static unsigned const value = 1; -}; - -//--------------------------------------------------------------------------- -// Transcoding - -/** Least-Significant Asserted Bit as 1-Hot (or zero if it does not exist). */ -template -inline ap_int_base lsab_hot(ap_int_base x) { -#pragma HLS inline - return x & ap_int_base(~x+1); -} - -/** Most-Significant Asserted Bit as 1-Hot (or zero if it does not exist). */ -template -inline ap_int_base msab_hot(ap_int_base x) { -#pragma HLS inline - return lsab_hot(x.reverse()).reverse(); -} - -/** One-Hot to binary. - * The returned result is undefined if the input is not one-hot encoded. - */ -template::value> -inline ap_int_base hot2bin(ap_int_base x) { -#pragma HLS inline - // Selective ORing to obtain binary index - ap_int_base res = 0; - - // This is what would be done in VHDL/Verilog: - // for(unsigned i = 0; i < W+1; i++) if(h[i]) res |= i; - - // This is what HLS needs for a decent synthesis: - for(unsigned i = 0; i < M; i++) { -#pragma HLS unroll - for(ap_uint::value> j = 0; j < W; j++) { -#pragma HLS unroll -#pragma TODO ap_fix - if(j[i]) res[i] = res[i] | x[j]; - } - } - return res; -} - -/** Binary to One-Hot. */ -template::value> -inline ap_int_base bin2hot(ap_int_base x) { -#pragma HLS inline - ap_int_base res(0); - res[x] = 1; - return res; -} - -/** Binary to reflected GRAY code. */ -template -inline ap_int_base bin2gray(ap_int_base x) { -#pragma HLS inline - return x ^ x(W-1, 1); -} - -/** Reflected GRAY code to binary. */ -template -inline ap_int_base gray2bin(ap_int_base x) { -#pragma HLS inline - ap_int_base y = x; - for(unsigned i = W-1; i > 0; i--) { -#pragma HLS unroll -#pragma TODO ap_fix - y[i-1] = y[i] ^ y[i-1]; - } - return y; -} - -//--------------------------------------------------------------------------- -// Prefix and suffix counting - -/** Count leading zeros. */ -template::value> -inline ap_int_base clz(ap_int_base x) { -#pragma HLS inline - return ap_int_base(x.countLeadingZeros()); -} - -/** Count trailing zeros. */ -template::value> -inline ap_int_base ctz(ap_int_base x) { -#pragma HLS inline - return clz(x.reverse()); -} - -} // namespace btl -#endif diff --git a/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/hashes.hpp b/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/hashes.hpp deleted file mode 100644 index 536f7ce1f..000000000 --- a/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/hashes.hpp +++ /dev/null @@ -1,108 +0,0 @@ -#ifndef HASHES_HPP -#define HASHES_HPP - -#include -#include - -//--------------------------------------------------------------------------- -// ConcatHash -// Allows to assemble a wider hash function by concatenating sub hashes. -template -class ConcatHash; - -template -class ConcatHash : public Hash { - Hash hash; -public: - ConcatHash() {} - ~ConcatHash() {} -public: - template - auto operator()(T val) const -> ap_uint { - return hash(val); - } -}; - -template -class ConcatHash { - Hash hash; - ConcatHash tail; -public: - ConcatHash() {} - ~ConcatHash() {} -public: - template - auto operator()(T val) const -> ap_uint { - return (hash(val), tail(val)); - } -}; - -//--------------------------------------------------------------------------- -// Murmur3_128 -template -class Murmur3_128 { - static uint64_t const c1 = 0x87c37b91114253d5; - static uint64_t const c2 = 0x4cf5ad432745937f; - static uint64_t const c3 = 0xff51afd7ed558ccd; - static uint64_t const c4 = 0xc4ceb9fe1a85ec53; - -public: - Murmur3_128() {} - ~Murmur3_128() {} - -public: - ap_uint<128> operator()(ap_uint<32> data) const { - ap_uint<64> const len = 4; - ap_uint<64> k1 = data; - - ap_uint<64> h1 = SEED; - ap_uint<64> h2 = SEED; - - k1 *= c1; - k1 = (k1 << 31) | (k1 >> (64 - 31)); - k1 *= c2; - h1 ^= k1; - - h1 ^= len; - h2 ^= len; - - h1 += h2; - h2 += h1; - - h1 ^= h1 >> 33; - h1 *= c3; - h1 ^= h1 >> 33; - h1 *= c4; - h1 ^= h1 >> 33; - - h2 ^= h2 >> 33; - h2 *= c3; - h2 ^= h2 >> 33; - h2 *= c4; - h2 ^= h2 >> 33; - - h1 += h2; - h2 += h1; - - return (h2, h1); - } - -}; // Murmur3_128 - -// A truncated implementation of the 128-bit Murmur3 hash. -template -class Murmur3_64 { - Murmur3_128 hash; - -public: - Murmur3_64() {} - ~Murmur3_64() {} - -public: - ap_uint<64> operator()(ap_uint<32> data) const { - return hash(data); - } - -}; // Murmur3_64 - -#endif diff --git a/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/hllsketch_16x32.cpp b/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/hllsketch_16x32.cpp deleted file mode 100644 index 605e66290..000000000 --- a/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/hllsketch_16x32.cpp +++ /dev/null @@ -1,108 +0,0 @@ -//#include "user_hls_c0_0.hpp" - -#include "hllsketch_16x32.hpp" - -#include -#include "ap_int.h" -#include -#include -#include -#include -#include "ap_axi_sdata.h" - -#define AXI_DATA_BITS 512 - -#define VADDR_BITS 48 -#define LEN_BITS 28 -#define DEST_BITS 4 -#define PID_BITS 6 -#define RID_BITS 4 - -/** - * User logic - * - */ - -// Interface adjustments -// Sink - -void input_cnvrt ( - hls::stream >& axis_host_sink, - hls::stream& hll_sink -) { -#pragma HLS inline off -#pragma HLS pipeline II=1 - - ap_axiu in_data; - input_t out_data; - - if (!axis_host_sink.empty()) { - axis_host_sink.read(in_data); - - out_data.data = in_data.data; - out_data.keep = in_data.keep; - out_data.id = in_data.id; - out_data.last = in_data.last; - - hll_sink.write(out_data); - } -} - -void output_cnvrt ( - hls::stream& hll_src, - hls::stream >& axis_host_src -) { -#pragma HLS inline off -#pragma HLS pipeline II=1 - - output_t in_data; - ap_axiu out_data; - - if(!hll_src.empty()) { - hll_src.read(in_data); - - out_data.data = in_data.data; - out_data.keep = in_data.keep; - out_data.id = in_data.id; - out_data.last = in_data.last; - - axis_host_src.write(out_data); - } -} - -/** - * Main - */ -void hllsketch_16x32 ( - // Host streams - hls::stream >& axis_host_sink, - hls::stream >& axis_host_src, - - ap_uint<64> axi_ctrl -) { - #pragma HLS DATAFLOW disable_start_propagation - #pragma HLS INTERFACE ap_ctrl_none port=return - - #pragma HLS INTERFACE axis register port=axis_host_sink name=s_axis_host_sink - #pragma HLS INTERFACE axis register port=axis_host_src name=m_axis_host_src - - - #pragma HLS INTERFACE s_axilite port=return bundle=control - //#pragma HLS INTERFACE s_axilite port=axi_ctrl_a bundle=control - //#pragma HLS INTERFACE s_axilite port=axi_ctrl_b bundle=control - //#pragma HLS INTERFACE s_axilite port=axi_ctrl_c bundle=control - #pragma HLS INTERFACE s_axilite port=axi_ctrl bundle=control - - // - // User logic - // - static hls::stream hll_sink; - static hls::stream hll_src; - #pragma HLS STREAM depth=2 variable=hll_sink - #pragma HLS STREAM depth=2 variable=hll_src - - input_cnvrt(axis_host_sink, hll_sink); - top(hll_sink, hll_src); - output_cnvrt(hll_src, axis_host_src); - -} diff --git a/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/hllsketch_16x32.hpp b/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/hllsketch_16x32.hpp deleted file mode 100644 index 3c4037849..000000000 --- a/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/hllsketch_16x32.hpp +++ /dev/null @@ -1,101 +0,0 @@ -#include -#include -#include - -#include "HllSketch.hpp" -#include "stream.hpp" -#include "hashes.hpp" - -//=========================================================================== -// Design Dimensioning -unsigned const N = 16; // Parallel Data Lanes -unsigned const P = 14; // Precision -using Hash = Murmur3_64<0xDEADF00D>; -unsigned const H = 64; - -template -struct net_axis { - ap_uint data; - ap_uint keep; - ap_uint<6> id; - ap_uint<1> last; -}; - -unsigned const DATA_WIDTH = 32; -unsigned const LINE_WIDTH = N*DATA_WIDTH; -using input_t = net_axis; // Input Tuple -using item_t = flit_v_t>; // Decomposed Input Item -using output_t = net_axis<32>; // Output: Wrapped float - - -//=========================================================================== -// Input Split -static void divide_data(hls::stream &src, hls::stream (&dst)[N]) { -#pragma HLS PIPELINE II=1 -#pragma HLS INLINE off - static item_t buf[N] = {}; - static bool flush = false; - - if(flush) { - for(unsigned i = 0; i < N; i++) { -#pragma HLS unroll - if(buf[i].last) dst[i].write(buf[i]); - } - flush = false; - } - else { - input_t x; - if(src.read_nb(x)) { - bool const last = x.last; - for(unsigned i = 0; i < N; i++) { -#pragma HLS unroll - bool const keep = (x.keep(4*i+3, 4*i) == 0xF); - dst[i].write(item_t{last&&!keep, buf[i].val}); - buf[i] = item_t{keep, x.data((i+1)*DATA_WIDTH-1, i*DATA_WIDTH)}; - } - flush = last; - } - } -} // divide_data() - -//=========================================================================== -void top( - hls::stream &s_axis_data, - hls::stream &m_axis_card -) { -//#pragma HLS INTERFACE axis port=s_axis_data -//#pragma HLS INTERFACE axis port=m_axis_card - -#pragma HLS dataflow - - // Split the Data Lanes - static hls::stream src_hll[N]; - -#if defined( __VITIS_HLS__) - #pragma HLS aggregate variable=src_hll compact=bit -#else - #pragma HLS data_pack variable=src_hll -#endif - - divide_data(s_axis_data, src_hll); - - // HLL Sketch - class YAssign { - output_t& m_y; - public: - YAssign(output_t &y) : m_y(y) {} - void operator=(float v) { - union { float f; uint32_t i; } const conv = { .f = v }; - m_y.data = conv.i; - m_y.keep = 0xF; - } - }; - - static HllSketch hll_sketch; - hll_sketch.sketch( - src_hll, m_axis_card, - MemberLast(), [](item_t const& x){ return Hash()(x.val); }, - MemberLast(), [](output_t &y){ return YAssign(y); } - ); - -} // top diff --git a/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/stream.hpp b/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/stream.hpp deleted file mode 100644 index 928393470..000000000 --- a/examples_hw/apps/hyperloglog/hls/hllsketch_16x32/stream.hpp +++ /dev/null @@ -1,310 +0,0 @@ -#ifndef STREAM_HPP -#define STREAM_HPP - -#include -#include -#include "bit_utils.hpp" - -#include -#include - -//=========================================================================== -// Flit structs carrying user data and batch boundary info (`last`) - -// Flit Base -struct flit_t { - bool last; - flit_t(bool l = false) : last(l) {} -}; - -// Flit with User Data -template -struct flit_v_t : public flit_t { - TV val; - flit_v_t() : flit_t(), val() {} - flit_v_t(bool l, TV const &v) : flit_t(l), val(v) {} -}; - -// Flit with User Key-Value Pair -template -struct flit_kv_t : public flit_v_t { - TK key; - flit_kv_t() : flit_v_t(), key() {} - flit_kv_t(bool l, TK const &k, TV const &v) : flit_v_t(l, v), key(k) {} -}; - -//=========================================================================== -// Lightweight plug-in member accessor functors. - -/** - * DevNull f; - * f(...) is assignable from any expression. - */ -struct DevNull { - struct Sink { - template - void operator=(T&& rhs) const {} - }; - template - constexpr Sink operator()(Args&&... args) const { return Sink(); } -}; - -/** - * Const f(1); - * f(arg0, arg1, ...) returns 1 - */ -template -class Const { - T const m_val; -public: - Const(T const& val) : m_val(val) {} -public: - template - constexpr T const& operator()(Args&&...) const noexcept { return m_val; } -}; - -/** - * Arg f; - * f(arg0, arg1, ...) returns arg_i - * Maintains references except for rvalue refs, which are reduced to prvalues. - */ -template -struct Arg { - template - constexpr auto operator()(A&& a, Args&&... args) const noexcept - -> decltype(Arg()(std::forward(args)...)) { - return Arg()(std::forward(args)...); - } -}; -template<> -struct Arg<0> { - template struct remove_rvref { using type = T; }; - template struct remove_rvref { using type = T; }; - template - constexpr auto operator()(A&& a, Args&&... args) const noexcept - -> typename remove_rvref::type { - return a; - } -}; - -// Flit Inspection Functors -#define BUILD_MEMBER_ACCESSOR(NAME, MEMBER) \ -struct NAME { \ - template \ - auto operator()(T& x) const noexcept \ - -> typename std::add_lvalue_reference::type { \ - return x.MEMBER; \ - } \ - template \ - auto operator()(T const& x) const noexcept \ - -> typename std::add_lvalue_reference::type>::type { \ - return x.MEMBER; \ - } \ - template \ - auto operator()(T&& x) const noexcept \ - -> decltype(x.MEMBER) { \ - return x.MEMBER; \ - } \ -}; -BUILD_MEMBER_ACCESSOR(MemberLast, last) -BUILD_MEMBER_ACCESSOR(MemberKey, key) -BUILD_MEMBER_ACCESSOR(MemberVal, val) -#undef BUILD_MEMBER_ACCESSOR - -//=========================================================================== -// Stateless Stream Manipulation Stages -template< - typename F = Arg<0>, - typename TI, - typename TO -> -void stage_guarded( - hls::stream &src, - hls::stream &dst, - F &&f = F() -) { -#pragma HLS inline off -#pragma HLS pipeline II=1 - TI x; - if(src.read_nb(x)) dst.write(f(x)); -} - -template< - typename F = Arg<0>, // f(TI, 0:N-1) -> TO - typename TI, - typename TO, - unsigned N -> -void stream_split( - hls::stream &src, - hls::stream (&dst)[N], - F &&f = F() -) { -#pragma HLS inline off -#pragma HLS pipeline II=1 - TI x; - if(src.read_nb(x)) { - for(unsigned i = 0; i < N; i++) { -#pragma HLS unroll - dst[i].write(f(x, i)); - } - } -} // stream_split() - -/** - * Folds N source streams into one destination stream output by output - * yielding f(...f(f(null_val, src[0].read()), src[1].read()), ... ). - */ -template< - typename F, // f(TO, TI) -> TO - typename TI, - typename TO, - unsigned N -> -void stream_fold( - hls::stream (&src)[N], - hls::stream &dst, - F&& f -) { -#pragma HLS inline off -#pragma HLS pipeline II=1 - ap_uint empty; - for(unsigned i = 0; i < N; i++) { -#pragma HLS unroll - empty[i] = src[i].empty(); - } - - if(empty == 0) { - TO y = 0; - for(unsigned i = 0; i < N; i++) { -#pragma HLS unroll - y = f(y, src[i].read()); - } - dst.write(y); - } - -} // stream_fold() - -//=========================================================================== -/** - * Stream concatenation of N streams 0, .., N-1 switching to the next - * when seeing T.last. - */ -template -class StreamConcatenator { - ap_uint::value> idx = 0; - -public: - template< - typename TXL = MemberLast, - typename F = Arg<0>, - typename TI, - typename TO - > - void concat( - hls::stream (&src)[N], - hls::stream &dst, - TXL &&txl = TXL(), - F &&f = F() - ) { -#pragma HLS inline off -#pragma HLS pipeline II=1 - TI x; - if(src[idx].read_nb(x)) { - if(txl(x)) { - if(idx == N-1) idx = 0; else idx++; - } - dst.write(f(x)); - } - } - -}; // class StreamConcatenator - -//--------------------------------------------------------------------------- -// Trivial Specialization for N=1 -template<> -class StreamConcatenator<1> { -public: - template< - typename TXL = MemberLast, - typename F = Arg<0>, - typename TI, - typename TO - > - void concat( - hls::stream (&src)[1], - hls::stream &dst, - TXL &&txl = TXL(), - F &&f = F() - ) { -#pragma HLS inline off -#pragma HLS pipeline II=1 - TI x; - if(src[0].read_nb(x)) dst.write(f(x)); - } -}; // class StreamConcatenator - -template<> -class StreamConcatenator<0> {}; - -//=========================================================================== -template -class StreamInterleaver { - ap_uint::value> idx = 0; - -public: - /** - * Round-robin through source streams 0,..N-1 forwarding each - * value x to the destination stream after manipulation by f(x, idx). - * The default manipulation passes the value unchanged. - */ - template< - typename F = Arg<0>, - typename TI, - typename TO - > - void interleave( - hls::stream (&src)[N], - hls::stream &dst, - F &&f = F() - ) { -#pragma HLS inline off -#pragma HLS pipeline II=1 - TI x; - if(src[idx].read_nb(x)) { - dst.write(f(x, idx)); - if(idx == N-1) idx = 0; else idx++; - } - } - -}; // class StreamInterleaver - -//--------------------------------------------------------------------------- -// Trivial Specialization for N=1 -template<> -class StreamInterleaver<1> { -public: - template< - typename F = Arg<0>, - typename TI, - typename TO - > - void interleave( - hls::stream (&src)[1], - hls::stream &dst, - F &&f = F() - ) { -#pragma HLS inline off -#pragma HLS pipeline II=1 - TI x; - if(src[0].read_nb(x)) { - dst.write(f(x, 0)); - } - } - -}; // class StreamInterleaver - -template<> -class StreamInterleaver<0> {}; - -#endif diff --git a/examples_hw/apps/hyperloglog/init_ip.tcl b/examples_hw/apps/hyperloglog/init_ip.tcl deleted file mode 100644 index 0280e42a5..000000000 --- a/examples_hw/apps/hyperloglog/init_ip.tcl +++ /dev/null @@ -1,2 +0,0 @@ -create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_hll -set_property -dict [list CONFIG.C_PROBE6_WIDTH {32} CONFIG.C_NUM_OF_PROBES {7} CONFIG.Component_Name {ila_hll} CONFIG.C_EN_STRG_QUAL {1} CONFIG.C_PROBE6_MU_CNT {2} CONFIG.C_PROBE5_MU_CNT {2} CONFIG.C_PROBE4_MU_CNT {2} CONFIG.C_PROBE3_MU_CNT {2} CONFIG.C_PROBE2_MU_CNT {2} CONFIG.C_PROBE1_MU_CNT {2} CONFIG.C_PROBE0_MU_CNT {2} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_hll] \ No newline at end of file diff --git a/examples_hw/apps/hyperloglog/vfpga_top.svh b/examples_hw/apps/hyperloglog/vfpga_top.svh deleted file mode 100644 index 7a11c0327..000000000 --- a/examples_hw/apps/hyperloglog/vfpga_top.svh +++ /dev/null @@ -1,70 +0,0 @@ -/** - * VFPGA TOP - * - * Tie up all signals to the user kernels - * Still to this day, interfaces are not supported by Vivado packager ... - * This means verilog style port connections are needed. - * - */ - -// -// Instantiate top level -// - -hllsketch_16x32 ( - .s_axis_host_sink_TDATA (axis_host_recv[0].tdata), - .s_axis_host_sink_TKEEP (axis_host_recv[0].tkeep), - .s_axis_host_sink_TLAST (axis_host_recv[0].tlast), - .s_axis_host_sink_TID (axis_host_recv[0].tid), - .s_axis_host_sink_TSTRB (0), - .s_axis_host_sink_TVALID (axis_host_recv[0].tvalid), - .s_axis_host_sink_TREADY (axis_host_recv[0].tready), - - .m_axis_host_src_TDATA (axis_host_send[0].tdata), - .m_axis_host_src_TKEEP (axis_host_send[0].tkeep), - .m_axis_host_src_TLAST (axis_host_send[0].tlast), - .m_axis_host_src_TID (axis_host_send[0].tid), - .m_axis_host_src_TSTRB (), - .m_axis_host_src_TVALID (axis_host_send[0].tvalid), - .m_axis_host_src_TREADY (axis_host_send[0].tready), - - .s_axi_control_ARADDR (axi_ctrl.araddr), - .s_axi_control_ARVALID (axi_ctrl.arvalid), - .s_axi_control_ARREADY (axi_ctrl.arready), - .s_axi_control_AWADDR (axi_ctrl.awaddr), - .s_axi_control_AWVALID (axi_ctrl.awvalid), - .s_axi_control_AWREADY (axi_ctrl.awready), - .s_axi_control_RDATA (axi_ctrl.rdata), - .s_axi_control_RRESP (axi_ctrl.rresp), - .s_axi_control_RVALID (axi_ctrl.rvalid), - .s_axi_control_RREADY (axi_ctrl.rready), - .s_axi_control_WDATA (axi_ctrl.wdata), - .s_axi_control_WSTRB (axi_ctrl.wstrb), - .s_axi_control_WVALID (axi_ctrl.wvalid), - .s_axi_control_WREADY (axi_ctrl.wready), - .s_axi_control_BRESP (axi_ctrl.bresp), - .s_axi_control_BVALID (axi_ctrl.bvalid), - .s_axi_control_BREADY (axi_ctrl.bready), - - .ap_clk (aclk), - .ap_rst_n (aresetn) -); - -// Tie-off the rest of the interfaces -always_comb notify.tie_off_m(); -always_comb sq_rd.tie_off_m(); -always_comb sq_wr.tie_off_m(); -always_comb cq_rd.tie_off_s(); -always_comb cq_wr.tie_off_s(); - -// ILA -ila_hll inst_ila_hll ( - .clk(aclk), - .probe0(axis_host_recv[0].tvalid), - .probe1(axis_host_recv[0].tready), - .probe2(axis_host_recv[0].tlast), - .probe3(axis_host_send[0].tvalid), - .probe4(axis_host_send[0].tready), - .probe5(axis_host_send[0].tlast), - .probe6(axis_host_send[0].tdata[31:0]) -); diff --git a/examples_hw/apps/rdma_aes/hdl/aes_pipe_stage.vhd b/examples_hw/apps/rdma_aes/hdl/aes_pipe_stage.vhd deleted file mode 100644 index 6c152fa92..000000000 --- a/examples_hw/apps/rdma_aes/hdl/aes_pipe_stage.vhd +++ /dev/null @@ -1,75 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity aes_pipe_stage is - generic( - OPERATION : integer := 0; -- [0-encryption, 1-decryption] - LAST : boolean := false - ); - port( - clk : in std_logic; - reset_n : in std_logic; - stall : in std_logic; - key_in : in std_logic_vector(127 downto 0); - last_in : in std_logic; - last_out : out std_logic; - keep_in : in std_logic_vector(15 downto 0); - keep_out : out std_logic_vector(15 downto 0); - dVal_in : in std_logic; - dVal_out : out std_logic; - data_in : in std_logic_vector(127 downto 0); - data_out : out std_logic_vector(127 downto 0) - ); -end entity aes_pipe_stage; - -architecture RTL of aes_pipe_stage is - - -- Internal signals - signal data_aes_out : std_logic_vector(127 downto 0); - -begin - - -- Instantiate AES round - GEN_RND: if LAST = false generate - GEN_AES_RND: entity work.aes_round - generic map( - OPERATION => OPERATION - ) - port map( - key_in => key_in, - data_in => data_in, - data_out => data_aes_out - ); - end generate GEN_RND; - - GEN_LAST: if LAST = true generate - GEN_AES_RND: entity work.aes_round_last - generic map( - OPERATION => OPERATION - ) - port map( - key_in => key_in, - key_last => (others => '0'), - data_in => data_in, - data_out => data_aes_out - ); - end generate GEN_LAST; - - -- Instantiate Pipe register - GEN_AES_REG: entity work.pipe_reg - port map( - clk => clk, - reset_n => reset_n, - stall => stall, - last_in => last_in, - last_out => last_out, - keep_in => keep_in, - keep_out => keep_out, - dVal_in => dVal_in, - dVal_out => dVal_out, - data_in => data_aes_out, - data_out => data_out - ); - -end architecture RTL; \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/aes_pipeline.vhd b/examples_hw/apps/rdma_aes/hdl/aes_pipeline.vhd deleted file mode 100644 index a8f12ae23..000000000 --- a/examples_hw/apps/rdma_aes/hdl/aes_pipeline.vhd +++ /dev/null @@ -1,129 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity aes_pipeline is - generic( - KEY_WIDTH : integer := 128; - KEY_ROUNDS: integer := 11; - ENC_ROUNDS: integer := 10; - OPERATION : integer := 0; --[0-encryption, 1-decryption] - MODE : integer := 0 --[0-ECB, 1-CTR, 2-CBC] - ); - port( - clk : in std_logic; - reset_n : in std_logic; - stall : in std_logic; - -- Key - key_in : in std_logic_vector(KEY_ROUNDS*KEY_WIDTH-1 downto 0); - last_in : in std_logic; - last_out : out std_logic; - keep_in : in std_logic_vector(15 downto 0); - keep_out : out std_logic_vector(15 downto 0); - -- Data valid - dVal_in : in std_logic; -- Data valid - dVal_out : out std_logic; - -- Data - data_in : in std_logic_vector(127 downto 0); - data_out : out std_logic_vector(127 downto 0); - -- CTR - cntr_in : in std_logic_vector(127 downto 0) - ); -end entity aes_pipeline; - -architecture RTL of aes_pipeline is - - -- Internal signals - type dVal_array is array ((ENC_ROUNDS) downto 0) of std_logic; - type data_array is array ((ENC_ROUNDS) downto 0) of std_logic_vector(127 downto 0); - type last_array is array ((ENC_ROUNDS) downto 0) of std_logic; - type keep_array is array ((ENC_ROUNDS) downto 0) of std_logic_vector(15 downto 0); - - signal s_data_to_block : std_logic_vector(127 downto 0); - signal s_data_from_block : std_logic_vector(127 downto 0); - - signal dVal_pipe : dVal_array; -- Data valid signal pipeline - signal data_pipe : data_array; -- Data pipeline - signal last_pipe : last_array; - signal keep_pipe : keep_array; - -begin - - GEN_EBC: if (MODE = 0) generate - s_data_to_block <= data_in; - s_data_from_block <= data_pipe(ENC_ROUNDS); - end generate GEN_EBC; - - GEN_CTR: if (MODE = 1) generate - s_data_to_block <= data_in; - s_data_from_block <= cntr_in xor data_pipe(ENC_ROUNDS); - end generate GEN_CTR; - - GEN_CBC: if (MODE = 2) generate - -- encryption - GEN_CBC_EN: if (OPERATION = 0) generate - s_data_to_block <= data_in xor cntr_in; - s_data_from_block <= data_pipe(ENC_ROUNDS); - end generate GEN_CBC_EN; - - -- decryption - GEN_CBC_DE: if (OPERATION = 1) generate - s_data_to_block <= data_in; - s_data_from_block <= cntr_in xor data_pipe(ENC_ROUNDS); - end generate GEN_CBC_DE; - end generate GEN_CBC; - - -- Instantiate regular AES stages - GEN_AES: for i in 0 to ENC_ROUNDS generate - - GEN_S0: if i = 0 generate - S0: entity work.aes_pipe_stage - generic map( - OPERATION => OPERATION - ) - port map( - clk => clk, - reset_n => reset_n, - stall => stall, - key_in => key_in(255 downto 128), - last_in => last_in, - last_out => last_pipe(0), - keep_in => keep_in, - keep_out => keep_pipe(0), - dVal_in => dVal_in, - dVal_out => dVal_pipe(0), - data_in => (s_data_to_block xor key_in(127 downto 0)), - data_out => data_pipe(0) - ); - end generate GEN_S0; - - GEN_SX: if i > 0 generate - SX: entity work.aes_pipe_stage - generic map( - OPERATION => OPERATION, - LAST => (i=ENC_ROUNDS) - ) - port map( - clk => clk, - reset_n => reset_n, - stall => stall, - key_in => key_in(128*(i+1)+127 downto 128*(i+1)), - last_in => last_pipe(i-1), - last_out => last_pipe(i), - keep_in => keep_pipe(i-1), - keep_out => keep_pipe(i), - dVal_in => dVal_pipe(i-1), - dVal_out => dVal_pipe(i), - data_in => data_pipe(i-1), - data_out => data_pipe(i) - ); - end generate GEN_SX; - - end generate GEN_AES; - - last_out <= last_pipe(ENC_ROUNDS); - keep_out <= keep_pipe(ENC_ROUNDS); - dVal_out <= dVal_pipe(ENC_ROUNDS); - data_out <= s_data_from_block; - -end architecture RTL; \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/aes_round.vhd b/examples_hw/apps/rdma_aes/hdl/aes_round.vhd deleted file mode 100644 index a0f145e58..000000000 --- a/examples_hw/apps/rdma_aes/hdl/aes_round.vhd +++ /dev/null @@ -1,81 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity aes_round is - generic( - OPERATION : integer := 0 -- [0-encryption, 1-decryption] - ); - port( - key_in : in std_logic_vector(127 downto 0); - data_in : in std_logic_vector(127 downto 0); - data_out : out std_logic_vector(127 downto 0) - ); -end entity aes_round; - -architecture RTL of aes_round is - - -- Internal signals - signal data_step_one : std_logic_vector(127 downto 0); - signal data_step_two : std_logic_vector(127 downto 0); - signal data_step_three : std_logic_vector(127 downto 0); - signal data_step_four : std_logic_vector(127 downto 0); - -begin - - -- Encryption - GEN_ENC: if OPERATION = 0 generate - -- S-box stage - GEN_SBOX: for i in 0 to 15 generate - SBOX: entity work.s_box_lut port map( - data_in => data_in(8*i+7 downto 8*i), - data_out => data_step_one(8*i+7 downto 8*i) - ); - end generate GEN_SBOX; - - -- Shift row - GEN_SROW: entity work.shift_rows port map( - data_in => data_step_one, - data_out => data_step_two - ); - - -- Mix columns - GEN_MCOL: entity work.mix_columns port map( - data_in => data_step_two, - data_out => data_step_three - ); - - -- Add round key - data_step_four <= data_step_three xor key_in; - end generate GEN_ENC; - - -- Decryption - GEN_DEC: if OPERATION = 1 generate - -- Inverse Shift row - GEN_INV_SROW: entity work.inv_shift_rows port map( - data_in => data_in, - data_out => data_step_one - ); - - -- Inverse S-box stage - GEN_INV_SBOX: for i in 0 to 15 generate - INV_SBOX: entity work.inv_s_box_lut port map( - data_in => data_step_one(8*i+7 downto 8*i), - data_out => data_step_two(8*i+7 downto 8*i) - ); - end generate GEN_INV_SBOX; - - -- Add round key - data_step_three <= data_step_two xor key_in; - - -- Inverse Mix columns - GEN_INV_MCOL: entity work.inv_mix_columns port map( - data_in => data_step_three, - data_out => data_step_four - ); - end generate GEN_DEC; - - -- Output - data_out <= data_step_four; - -end architecture RTL; \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/aes_round_last.vhd b/examples_hw/apps/rdma_aes/hdl/aes_round_last.vhd deleted file mode 100644 index c2397d03e..000000000 --- a/examples_hw/apps/rdma_aes/hdl/aes_round_last.vhd +++ /dev/null @@ -1,64 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity aes_round_last is - generic( - OPERATION : integer := 0 -- [0-encryption, 1-decryption] - ); - port( - key_in : in std_logic_vector(127 downto 0); - key_last : in std_logic_vector(127 downto 0); - data_in : in std_logic_vector(127 downto 0); - data_out : out std_logic_vector(127 downto 0) - ); -end entity aes_round_last; - -architecture RTL of aes_round_last is - - -- Internal signals - signal data_step_one : std_logic_vector(127 downto 0); - signal data_step_two : std_logic_vector(127 downto 0); - -begin - - -- Encryption - GEN_ENC: if OPERATION = 0 generate - -- S-box stage - GEN_SBOX: for i in 0 to 15 generate - SBOX: entity work.s_box_lut port map( - data_in => data_in(8*i+7 downto 8*i), - data_out => data_step_one(8*i+7 downto 8*i) - ); - end generate GEN_SBOX; - - -- Shift row - GEN_SROW: entity work.shift_rows port map( - data_in => data_step_one, - data_out => data_step_two - ); - - end generate GEN_ENC; - - -- Decryption - GEN_DEC: if OPERATION = 1 generate - -- Inverse Shift row - GEN_INV_SROW: entity work.inv_shift_rows port map( - data_in => data_in, - data_out => data_step_one - ); - - -- Inverse S-box stage - GEN_INV_SBOX: for i in 0 to 15 generate - INV_SBOX: entity work.inv_s_box_lut port map( - data_in => data_step_one(8*i+7 downto 8*i), - data_out => data_step_two(8*i+7 downto 8*i) - ); - end generate GEN_INV_SBOX; - - end generate GEN_DEC; - - -- Last add round key - data_out <= data_step_two xor key_in; - -end architecture RTL; \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/aes_top.vhd b/examples_hw/apps/rdma_aes/hdl/aes_top.vhd deleted file mode 100644 index bd7d9d36a..000000000 --- a/examples_hw/apps/rdma_aes/hdl/aes_top.vhd +++ /dev/null @@ -1,256 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.rounds.all; - -entity aes_top is - generic( - NPAR : integer := 2; - KEY_WIDTH : integer := 128; - KEY_ROUNDS: integer := 11; - OPERATION : integer := 0; -- [0-encryption, 1-decryption] - MODE : integer := 0 -- [0-ECB, 1-CTR, 2-CBC] - ); - port( - clk : in std_logic; - reset_n : in std_logic; - stall : in std_logic; - -- key/Last/ keep - key_in : in std_logic_vector(KEY_ROUNDS*KEY_WIDTH-1 downto 0); - last_in : in std_logic; - last_out : out std_logic; - keep_in : in std_logic_vector(NPAR*16-1 downto 0); - keep_out : out std_logic_vector(NPAR*16-1 downto 0); - -- Data valid - dVal_in : in std_logic; -- Data valid - dVal_out : out std_logic; - -- Data - data_in : in std_logic_vector(NPAR*128-1 downto 0); - data_out : out std_logic_vector(NPAR*128-1 downto 0); - -- CTR - nonce+value - cntr_in : in std_logic_vector(NPAR*128-1 downto 0) - ); -end entity aes_top; - -architecture RTL of aes_top is - - type keep_array is array (NPAR-1 downto 0) of std_logic_vector(15 downto 0); - - type dataf_array is array (NPAR-1 downto 0) of std_logic_vector(NPAR*128-1 downto 0); - type data_array is array (NPAR-1 downto 0) of std_logic_vector(128-1 downto 0); - - type keepf_array is array (NPAR-1 downto 0) of std_logic_vector(NPAR*16-1 downto 0); - - --variable key_rounds : integer := key_rounds_number(KEY_WIDTH); - -- Internal signals - signal dVal : std_logic_vector(NPAR-1 downto 0); - signal last : std_logic_vector(NPAR-1 downto 0); - - signal s_cntr : std_logic_vector(NPAR*128-1 downto 0); - - signal keep : keep_array; - signal s_data : data_array; - - signal s_data_full : dataf_array; - signal s_data_piped: dataf_array; - signal s_keep_piped: keepf_array; - -begin - -GEN_4: if (MODE=0 OR MODE=1 OR (MODE=2 AND OPERATION=1)) generate - -- Instantiate AES pipelines - GEN_AES_PAR: for i in 0 to NPAR-1 generate - GEN_AES_PIPE: entity work.aes_pipeline - generic map( - KEY_WIDTH => KEY_WIDTH, - KEY_ROUNDS => key_rounds_number(KEY_WIDTH), - ENC_ROUNDS => encrypt_rounds_number(KEY_WIDTH), - MODE => MODE, - OPERATION => OPERATION - ) - port map( - clk => clk, - reset_n => reset_n, - stall => stall, - -- Key - key_in => key_in, - -- Data valid - dVal_in => dVal_in, - dVal_out => dVal(i), - last_in => last_in, - last_out => last(i), - keep_in => keep_in(i*16+15 downto i*16), - keep_out => keep(i), - -- Data - data_in => data_in(i*128+127 downto i*128), - data_out => data_out(i*128+127 downto i*128), - -- CTR - cntr_in => s_cntr(i*128+127 downto i*128) - ); - end generate GEN_AES_PAR; - - GEN_DAT: if (MODE=2 OR MODE=1) generate - DATA_PIPE_0: entity work.data_pipeline - generic map( - NPAR => NPAR, - ENC_ROUNDS => encrypt_rounds_number(KEY_WIDTH) - ) - port map( - clk => clk, - reset_n => reset_n, - stall => stall, - -- Control - keep_in => keep_in, - keep_out => s_keep_piped(0), - -- Data - data_in => cntr_in, - data_out => s_data_piped(0) - ); - end generate GEN_DAT; - - GEN_CNTR2: if (MODE=2 OR MODE=1) generate - s_cntr <= s_data_piped(0); - end generate; - - GEN_CNTR1: if (MODE=0) generate - s_cntr <= cntr_in; - end generate GEN_CNTR1; - - GEN_VALID: process (dVal) is - variable tmp : std_logic; - begin - tmp := '0'; - for i in 0 to NPAR-1 loop - tmp := tmp or dVal(i); - end loop; - dVal_out <= tmp; - end process GEN_VALID; - - GEN_LAST: process (last) is - variable tmp : std_logic; - begin - tmp := '0'; - for i in 0 to NPAR-1 loop - tmp := tmp or last(i); - end loop; - last_out <= tmp; - end process GEN_LAST; - - GEN_KEEP: for i in 0 to NPAR-1 generate - keep_out(i*16+15 downto i*16) <= keep(i); - end generate GEN_KEEP; - -end generate GEN_4; - -GEN_1: if (MODE=2 AND OPERATION=0) generate - -- Instantiate AES pipelines - AES_PIPE_0: entity work.aes_pipeline - generic map( - KEY_WIDTH => KEY_WIDTH, - KEY_ROUNDS => key_rounds_number(KEY_WIDTH), - ENC_ROUNDS => encrypt_rounds_number(KEY_WIDTH), - MODE => MODE, - OPERATION => OPERATION - ) - port map( - clk => clk, - reset_n => reset_n, - stall => stall, - -- Key - key_in => key_in, - -- Data valid - dVal_in => dVal_in, - dVal_out => dVal(0), - last_in => last_in, - last_out => last(0), - keep_in => keep_in(0*16+15 downto 0*16), - keep_out => open, - -- Data - data_in => data_in(0*128+127 downto 0*128), - data_out => s_data(0), - -- CTR - cntr_in => cntr_in(0*128+127 downto 0*128) - ); - - DATA_PIPE_0: entity work.data_pipeline - generic map( - NPAR => NPAR, - ENC_ROUNDS => encrypt_rounds_number(KEY_WIDTH) - ) - port map( - clk => clk, - reset_n => reset_n, - stall => stall, - -- Control - keep_in => keep_in, - keep_out => s_keep_piped(0), - -- Data - data_in => data_in, - data_out => s_data_piped(0) - ); - - s_data_full(0)(0*128+127 downto 0*128) <= s_data(0); - s_data_full(0)((NPAR-1)*128+127 downto 0*128+128) <= s_data_piped(0)((NPAR-1)*128+127 downto 0*128+128); - - AES_PAR: for i in 1 to NPAR-1 generate - AES_PIPE_X: entity work.aes_pipeline - generic map( - KEY_WIDTH => KEY_WIDTH, - KEY_ROUNDS => key_rounds_number(KEY_WIDTH), - ENC_ROUNDS => encrypt_rounds_number(KEY_WIDTH), - MODE => MODE, --[0-encryption, 1-decryption] - OPERATION => OPERATION --[0-ECB, 1-CTR, 2-CBC] - ) - port map( - clk => clk, - reset_n => reset_n, - stall => stall, - -- Key - key_in => key_in, - -- Data valid - dVal_in => dVal(i-1), - dVal_out => dVal(i), - last_in => last(i-1), - last_out => last(i), - keep_in => s_keep_piped(i-1)(i*16+15 downto i*16), - keep_out => keep(i), - -- Data - data_in => s_data_full(i-1)(i*128+127 downto i*128), - data_out => s_data(i), - -- CTR - cntr_in => s_data_full(i-1)((i-1)*128+127 downto (i-1)*128) - ); - - DATA_PIPE_X: entity work.data_pipeline - generic map( - NPAR => NPAR, - ENC_ROUNDS => encrypt_rounds_number(KEY_WIDTH) - ) - port map( - clk => clk, - reset_n => reset_n, - stall => stall, - -- Control - keep_in => s_keep_piped(i-1), - keep_out => s_keep_piped(i), - -- Data - data_in => s_data_full(i-1), - data_out => s_data_piped(i) - ); - - s_data_full(i)(i*128+127 downto i*128) <= s_data(i); - s_data_full(i)((NPAR-1)*128+127 downto i*128+128) <= s_data_piped(i)((NPAR-1)*128+127 downto i*128+128); - s_data_full(i)((i-1)*128+127 downto 0) <= s_data_piped(i)((i-1)*128+127 downto 0); - - end generate AES_PAR; - - data_out <= s_data_full(NPAR-1); - dVal_out <= dVal(NPAR-1); - last_out <= last(NPAR-1); - keep_out <= s_keep_piped(NPAR-1); - -end generate GEN_1; - -end architecture RTL; \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/data_pipeline.vhd b/examples_hw/apps/rdma_aes/hdl/data_pipeline.vhd deleted file mode 100644 index 0d6a9faed..000000000 --- a/examples_hw/apps/rdma_aes/hdl/data_pipeline.vhd +++ /dev/null @@ -1,86 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity data_pipeline is - generic( - NPAR : integer := 2; - ENC_ROUNDS: integer := 10 - ); - port( - clk : in std_logic; - reset_n : in std_logic; - stall : in std_logic; - -- Control - keep_in : in std_logic_vector(NPAR*16-1 downto 0); - keep_out : out std_logic_vector(NPAR*16-1 downto 0); - -- Data - data_in : in std_logic_vector(NPAR*128-1 downto 0); - data_out : out std_logic_vector(NPAR*128-1 downto 0) - ); -end entity data_pipeline; - -architecture RTL of data_pipeline is - - -- Internal signals - type dVal_array is array ((ENC_ROUNDS) downto 0) of std_logic; - type data_array is array ((ENC_ROUNDS) downto 0) of std_logic_vector(NPAR*128-1 downto 0); - type last_array is array ((ENC_ROUNDS) downto 0) of std_logic; - type keep_array is array ((ENC_ROUNDS) downto 0) of std_logic_vector(NPAR*16-1 downto 0); - - signal dVal_pipe : dVal_array; -- Data valid signal pipeline - signal data_pipe : data_array; -- Data pipeline - signal last_pipe : last_array; - signal keep_pipe : keep_array; - -begin - - -- Instantiate data stages - GEN_DAT: for i in 0 to ENC_ROUNDS generate - - GEN_D0: if i = 0 generate - D0: entity work.pipe_reg - generic map( - DATA_WIDTH => NPAR*128 - ) - port map( - clk => clk, - reset_n => reset_n, - stall => stall, - last_in => '0', - last_out => last_pipe(0), - keep_in => keep_in, - keep_out => keep_pipe(0), - dVal_in => '1', - dVal_out => dVal_pipe(0), - data_in => data_in, - data_out => data_pipe(0) - ); - end generate GEN_D0; - - GEN_DX: if i > 0 generate - DX: entity work.pipe_reg - generic map( - DATA_WIDTH => NPAR*128 - ) - port map( - clk => clk, - reset_n => reset_n, - stall => stall, - last_in => last_pipe(i-1), - last_out => last_pipe(i), - keep_in => keep_pipe(i-1), - keep_out => keep_pipe(i), - dVal_in => dVal_pipe(i-1), - dVal_out => dVal_pipe(i), - data_in => data_pipe(i-1), - data_out => data_pipe(i) - ); - end generate GEN_DX; - - end generate GEN_DAT; - - keep_out <= keep_pipe(ENC_ROUNDS); - data_out <= data_pipe(ENC_ROUNDS); - -end architecture RTL; \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/gf_mult.vhd b/examples_hw/apps/rdma_aes/hdl/gf_mult.vhd deleted file mode 100644 index 06b16a6cc..000000000 --- a/examples_hw/apps/rdma_aes/hdl/gf_mult.vhd +++ /dev/null @@ -1,127 +0,0 @@ -------------------------------------------------------------------------- --- Copyright (C) 2018 Kaan Kara - Systems Group, ETH Zurich - --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU Affero General Public License as published --- by the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. - --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU Affero General Public License for more details. - --- You should have received a copy of the GNU Affero General Public License --- along with this program. If not, see . ----------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity gf_mult is - generic ( - SELECTION : integer := 9 - ); - port ( - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0) - ); -end entity gf_mult; - -architecture behavioral of gf_mult is - -signal x : integer range 0 to 15; -signal y : integer range 0 to 15; - -type lookup_type is array(15 downto 0) of std_logic_vector(127 downto 0); -signal lookup : lookup_type; - -begin - - SELECTION_9: if SELECTION = 9 generate - lookup <= ( - 0 => X"00_09_12_1b_24_2d_36_3f_48_41_5a_53_6c_65_7e_77", - 1 => X"90_99_82_8b_b4_bd_a6_af_d8_d1_ca_c3_fc_f5_ee_e7", - 2 => X"3b_32_29_20_1f_16_0d_04_73_7a_61_68_57_5e_45_4c", - 3 => X"ab_a2_b9_b0_8f_86_9d_94_e3_ea_f1_f8_c7_ce_d5_dc", - 4 => X"76_7f_64_6d_52_5b_40_49_3e_37_2c_25_1a_13_08_01", - 5 => X"e6_ef_f4_fd_c2_cb_d0_d9_ae_a7_bc_b5_8a_83_98_91", - 6 => X"4d_44_5f_56_69_60_7b_72_05_0c_17_1e_21_28_33_3a", - 7 => X"dd_d4_cf_c6_f9_f0_eb_e2_95_9c_87_8e_b1_b8_a3_aa", - 8 => X"ec_e5_fe_f7_c8_c1_da_d3_a4_ad_b6_bf_80_89_92_9b", - 9 => X"7c_75_6e_67_58_51_4a_43_34_3d_26_2f_10_19_02_0b", - 10 => X"d7_de_c5_cc_f3_fa_e1_e8_9f_96_8d_84_bb_b2_a9_a0", - 11 => X"47_4e_55_5c_63_6a_71_78_0f_06_1d_14_2b_22_39_30", - 12 => X"9a_93_88_81_be_b7_ac_a5_d2_db_c0_c9_f6_ff_e4_ed", - 13 => X"0a_03_18_11_2e_27_3c_35_42_4b_50_59_66_6f_74_7d", - 14 => X"a1_a8_b3_ba_85_8c_97_9e_e9_e0_fb_f2_cd_c4_df_d6", - 15 => X"31_38_23_2a_15_1c_07_0e_79_70_6b_62_5d_54_4f_46"); - end generate; - - SELECTION_11: if SELECTION = 11 generate - lookup <= ( - 0 => X"00_0b_16_1d_2c_27_3a_31_58_53_4e_45_74_7f_62_69", - 1 => X"b0_bb_a6_ad_9c_97_8a_81_e8_e3_fe_f5_c4_cf_d2_d9", - 2 => X"7b_70_6d_66_57_5c_41_4a_23_28_35_3e_0f_04_19_12", - 3 => X"cb_c0_dd_d6_e7_ec_f1_fa_93_98_85_8e_bf_b4_a9_a2", - 4 => X"f6_fd_e0_eb_da_d1_cc_c7_ae_a5_b8_b3_82_89_94_9f", - 5 => X"46_4d_50_5b_6a_61_7c_77_1e_15_08_03_32_39_24_2f", - 6 => X"8d_86_9b_90_a1_aa_b7_bc_d5_de_c3_c8_f9_f2_ef_e4", - 7 => X"3d_36_2b_20_11_1a_07_0c_65_6e_73_78_49_42_5f_54", - 8 => X"f7_fc_e1_ea_db_d0_cd_c6_af_a4_b9_b2_83_88_95_9e", - 9 => X"47_4c_51_5a_6b_60_7d_76_1f_14_09_02_33_38_25_2e", - 10 => X"8c_87_9a_91_a0_ab_b6_bd_d4_df_c2_c9_f8_f3_ee_e5", - 11 => X"3c_37_2a_21_10_1b_06_0d_64_6f_72_79_48_43_5e_55", - 12 => X"01_0a_17_1c_2d_26_3b_30_59_52_4f_44_75_7e_63_68", - 13 => X"b1_ba_a7_ac_9d_96_8b_80_e9_e2_ff_f4_c5_ce_d3_d8", - 14 => X"7a_71_6c_67_56_5d_40_4b_22_29_34_3f_0e_05_18_13", - 15 => X"ca_c1_dc_d7_e6_ed_f0_fb_92_99_84_8f_be_b5_a8_a3"); - end generate; - - SELECTION_13: if SELECTION = 13 generate - lookup <= ( - 0 => X"00_0d_1a_17_34_39_2e_23_68_65_72_7f_5c_51_46_4b", - 1 => X"d0_dd_ca_c7_e4_e9_fe_f3_b8_b5_a2_af_8c_81_96_9b", - 2 => X"bb_b6_a1_ac_8f_82_95_98_d3_de_c9_c4_e7_ea_fd_f0", - 3 => X"6b_66_71_7c_5f_52_45_48_03_0e_19_14_37_3a_2d_20", - 4 => X"6d_60_77_7a_59_54_43_4e_05_08_1f_12_31_3c_2b_26", - 5 => X"bd_b0_a7_aa_89_84_93_9e_d5_d8_cf_c2_e1_ec_fb_f6", - 6 => X"d6_db_cc_c1_e2_ef_f8_f5_be_b3_a4_a9_8a_87_90_9d", - 7 => X"06_0b_1c_11_32_3f_28_25_6e_63_74_79_5a_57_40_4d", - 8 => X"da_d7_c0_cd_ee_e3_f4_f9_b2_bf_a8_a5_86_8b_9c_91", - 9 => X"0a_07_10_1d_3e_33_24_29_62_6f_78_75_56_5b_4c_41", - 10 => X"61_6c_7b_76_55_58_4f_42_09_04_13_1e_3d_30_27_2a", - 11 => X"b1_bc_ab_a6_85_88_9f_92_d9_d4_c3_ce_ed_e0_f7_fa", - 12 => X"b7_ba_ad_a0_83_8e_99_94_df_d2_c5_c8_eb_e6_f1_fc", - 13 => X"67_6a_7d_70_53_5e_49_44_0f_02_15_18_3b_36_21_2c", - 14 => X"0c_01_16_1b_38_35_22_2f_64_69_7e_73_50_5d_4a_47", - 15 => X"dc_d1_c6_cb_e8_e5_f2_ff_b4_b9_ae_a3_80_8d_9a_97"); - end generate; - - SELECTION_14: if SELECTION = 14 generate - lookup <= ( - 0 => X"00_0e_1c_12_38_36_24_2a_70_7e_6c_62_48_46_54_5a", - 1 => X"e0_ee_fc_f2_d8_d6_c4_ca_90_9e_8c_82_a8_a6_b4_ba", - 2 => X"db_d5_c7_c9_e3_ed_ff_f1_ab_a5_b7_b9_93_9d_8f_81", - 3 => X"3b_35_27_29_03_0d_1f_11_4b_45_57_59_73_7d_6f_61", - 4 => X"ad_a3_b1_bf_95_9b_89_87_dd_d3_c1_cf_e5_eb_f9_f7", - 5 => X"4d_43_51_5f_75_7b_69_67_3d_33_21_2f_05_0b_19_17", - 6 => X"76_78_6a_64_4e_40_52_5c_06_08_1a_14_3e_30_22_2c", - 7 => X"96_98_8a_84_ae_a0_b2_bc_e6_e8_fa_f4_de_d0_c2_cc", - 8 => X"41_4f_5d_53_79_77_65_6b_31_3f_2d_23_09_07_15_1b", - 9 => X"a1_af_bd_b3_99_97_85_8b_d1_df_cd_c3_e9_e7_f5_fb", - 10 => X"9a_94_86_88_a2_ac_be_b0_ea_e4_f6_f8_d2_dc_ce_c0", - 11 => X"7a_74_66_68_42_4c_5e_50_0a_04_16_18_32_3c_2e_20", - 12 => X"ec_e2_f0_fe_d4_da_c8_c6_9c_92_80_8e_a4_aa_b8_b6", - 13 => X"0c_02_10_1e_34_3a_28_26_7c_72_60_6e_44_4a_58_56", - 14 => X"37_39_2b_25_0f_01_13_1d_47_49_5b_55_7f_71_63_6d", - 15 => X"d7_d9_cb_c5_ef_e1_f3_fd_a7_a9_bb_b5_9f_91_83_8d"); - end generate; - - x <= to_integer(unsigned(data_in(7 downto 4))); - y <= 15 - to_integer(unsigned(data_in(3 downto 0))); - - data_out <= lookup(x)(y*8+7 downto y*8 ); - -end architecture; \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/inv_mix_columns.vhd b/examples_hw/apps/rdma_aes/hdl/inv_mix_columns.vhd deleted file mode 100644 index 520b69060..000000000 --- a/examples_hw/apps/rdma_aes/hdl/inv_mix_columns.vhd +++ /dev/null @@ -1,81 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity inv_mix_columns is - port( - data_in : in std_logic_vector(127 downto 0); - data_out : out std_logic_vector(127 downto 0) - ); -end entity inv_mix_columns; - -architecture RTL of inv_mix_columns is - - -- Internal signals - type data_array is array (15 downto 0) of std_logic_vector(7 downto 0); - - -- x9, xb, xd, xe multiplication - signal in_array, out_array, in_array_x9, in_array_xb, in_array_xd, in_array_xe: data_array; - -begin - - -- Input generation - GEN_IN: for i in 15 downto 0 generate - in_array(15-i) <= data_in(i*8+7 downto i*8); - end generate GEN_IN; - - -- Multiplication - GEN_M: for i in 15 downto 0 generate - -- x9 - gf_inst0: entity work.gf_mult - generic map( - SELECTION => 9 - ) - port map( - data_in => in_array(i), - data_out => in_array_x9(i) - ); - - -- x11 - gf_inst1: entity work.gf_mult - generic map( - SELECTION => 11 - ) - port map( - data_in => in_array(i), - data_out => in_array_xb(i) - ); - -- x13 - gf_inst2: entity work.gf_mult - generic map( - SELECTION => 13 - ) - port map( - data_in => in_array(i), - data_out => in_array_xd(i) - ); - -- x14 - gf_inst3: entity work.gf_mult - generic map( - SELECTION => 14 - ) - port map( - data_in => in_array(i), - data_out => in_array_xe(i) - ); - end generate GEN_M; - - -- Mixed columns generation - GEN_MC: for i in 0 to 3 generate - out_array(4*i) <= in_array_xe(4*i) xor in_array_xb(4*i+1) xor in_array_xd(4*i+2) xor in_array_x9(4*i+3); - out_array(4*i+1) <= in_array_x9(4*i) xor in_array_xe(4*i+1) xor in_array_xb(4*i+2) xor in_array_xd(4*i+3); - out_array(4*i+2) <= in_array_xd(4*i) xor in_array_x9(4*i+1) xor in_array_xe(4*i+2) xor in_array_xb(4*i+3); - out_array(4*i+3) <= in_array_xb(4*i) xor in_array_xd(4*i+1) xor in_array_x9(4*i+2) xor in_array_xe(4*i+3); - end generate; - - -- Output generation - GEN_O: for i in 15 downto 0 generate - data_out(i*8+7 downto i*8) <= out_array(15-i); - end generate GEN_O; - -end architecture RTL; \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/inv_s_box_lut.vhd b/examples_hw/apps/rdma_aes/hdl/inv_s_box_lut.vhd deleted file mode 100644 index 23fa43f1d..000000000 --- a/examples_hw/apps/rdma_aes/hdl/inv_s_box_lut.vhd +++ /dev/null @@ -1,41 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity inv_s_box_lut is - port( - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0) - ); -end entity inv_s_box_lut; - -architecture RTL of inv_s_box_lut is - - -- Internal RAM - type ram_type is array(natural range<>) of std_logic_vector(7 downto 0); - - constant inv_sbox_ram : ram_type(255 downto 0) := ( - X"7d", X"0c", X"21", X"55", X"63", X"14", X"69", X"e1", X"26", X"d6", X"77", X"ba", X"7e", X"04", X"2b", X"17", - X"61", X"99", X"53", X"83", X"3c", X"bb", X"eb", X"c8", X"b0", X"f5", X"2a", X"ae", X"4d", X"3b", X"e0", X"a0", - X"ef", X"9c", X"c9", X"93", X"9f", X"7a", X"e5", X"2d", X"0d", X"4a", X"b5", X"19", X"a9", X"7f", X"51", X"60", - X"5f", X"ec", X"80", X"27", X"59", X"10", X"12", X"b1", X"31", X"c7", X"07", X"88", X"33", X"a8", X"dd", X"1f", - X"f4", X"5a", X"cd", X"78", X"fe", X"c0", X"db", X"9a", X"20", X"79", X"d2", X"c6", X"4b", X"3e", X"56", X"fc", - X"1b", X"be", X"18", X"aa", X"0e", X"62", X"b7", X"6f", X"89", X"c5", X"29", X"1d", X"71", X"1a", X"f1", X"47", - X"6e", X"df", X"75", X"1c", X"e8", X"37", X"f9", X"e2", X"85", X"35", X"ad", X"e7", X"22", X"74", X"ac", X"96", - X"73", X"e6", X"b4", X"f0", X"ce", X"cf", X"f2", X"97", X"ea", X"dc", X"67", X"4f", X"41", X"11", X"91", X"3a", - X"6b", X"8a", X"13", X"01", X"03", X"bd", X"af", X"c1", X"02", X"0f", X"3f", X"ca", X"8f", X"1e", X"2c", X"d0", - X"06", X"45", X"b3", X"b8", X"05", X"58", X"e4", X"f7", X"0a", X"d3", X"bc", X"8c", X"00", X"ab", X"d8", X"90", - X"84", X"9d", X"8d", X"a7", X"57", X"46", X"15", X"5e", X"da", X"b9", X"ed", X"fd", X"50", X"48", X"70", X"6c", - X"92", X"b6", X"65", X"5d", X"cc", X"5c", X"a4", X"d4", X"16", X"98", X"68", X"86", X"64", X"f6", X"f8", X"72", - X"25", X"d1", X"8b", X"6d", X"49", X"a2", X"5b", X"76", X"b2", X"24", X"d9", X"28", X"66", X"a1", X"2e", X"08", - X"4e", X"c3", X"fa", X"42", X"0b", X"95", X"4c", X"ee", X"3d", X"23", X"c2", X"a6", X"32", X"94", X"7b", X"54", - X"cb", X"e9", X"de", X"c4", X"44", X"43", X"8e", X"34", X"87", X"ff", X"2f", X"9b", X"82", X"39", X"e3", X"7c", - X"fb", X"d7", X"f3", X"81", X"9e", X"a3", X"40", X"bf", X"38", X"a5", X"36", X"30", X"d5", X"6a", X"09", X"52" - ); - -begin - - -- Output - data_out <= inv_sbox_ram(to_integer(unsigned(data_in))); - -end architecture RTL; \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/inv_shift_rows.vhd b/examples_hw/apps/rdma_aes/hdl/inv_shift_rows.vhd deleted file mode 100644 index da73d5d95..000000000 --- a/examples_hw/apps/rdma_aes/hdl/inv_shift_rows.vhd +++ /dev/null @@ -1,54 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity inv_shift_rows is - port( - data_in : in std_logic_vector(127 downto 0); - data_out : out std_logic_vector(127 downto 0) - ); -end entity inv_shift_rows; - -architecture RTL of inv_shift_rows is - - -- Internal signals - type data_array is array (15 downto 0) of std_logic_vector(7 downto 0); - signal in_array, out_array : data_array; - -begin - - -- Input generation - GEN_IN: for i in 15 downto 0 generate - in_array(15-i) <= data_in(i*8+7 downto i*8); - end generate GEN_IN; - - --First mixed column input - out_array(0) <= in_array(0); - out_array(5) <= in_array(1); - out_array(10) <= in_array(2); - out_array(15) <= in_array(3); - - -- Second mixed column input - out_array(4) <= in_array(4); - out_array(9) <= in_array(5); - out_array(14) <= in_array(6); - out_array(3) <= in_array(7); - - -- Third mixed column input - out_array(8) <= in_array(8); - out_array(13) <= in_array(9); - out_array(2) <= in_array(10); - out_array(7) <= in_array(11); - - -- Fourth mixed column input - out_array(12) <= in_array(12); - out_array(1) <= in_array(13); - out_array(6) <= in_array(14); - out_array(11) <= in_array(15); - - -- Output generation - GEN_OUT: for i in 15 downto 0 generate - data_out(i*8+7 downto i*8) <= out_array(15-i); - end generate GEN_OUT; - -end architecture RTL; \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/key_expansion.vhd b/examples_hw/apps/rdma_aes/hdl/key_expansion.vhd deleted file mode 100644 index 6fabb5d1e..000000000 --- a/examples_hw/apps/rdma_aes/hdl/key_expansion.vhd +++ /dev/null @@ -1,100 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity key_expansion is - generic( - KEY_WIDTH : integer := 128 - ); - port( - key_in : in std_logic_vector(KEY_WIDTH-1 downto 0); - key_out : out std_logic_vector(KEY_WIDTH-1 downto 0); - rnd_const : in std_logic_vector(7 downto 0) - ); -end entity key_expansion; - -architecture RTL of key_expansion is - - -- Internal signals - type word_array is array ((KEY_WIDTH/32-1) downto 0) of std_logic_vector(31 downto 0); - signal key_word : word_array; - signal key_next : word_array; - - signal key_shift : std_logic_vector(31 downto 0); - signal key_s_box_0 : std_logic_vector(31 downto 0); - signal key_s_box_4 : std_logic_vector(31 downto 0); - signal temp_0 : std_logic_vector(31 downto 0); - signal temp_4 : std_logic_vector(31 downto 0); - signal key_temp : std_logic_vector(KEY_WIDTH-1 downto 0); - - -begin - - -- Key words - GEN_KW: for i in 0 to (KEY_WIDTH/32-1) generate - key_word(((KEY_WIDTH/32-1))-i) <= key_in(32*i+31 downto 32*i); --moc: key_word(((KEY_WIDTH/32-1))-i) - end generate GEN_KW; - - -- Rotate 8 bits - key_shift <= key_word((KEY_WIDTH/32-1))(23 downto 0) & key_word((KEY_WIDTH/32-1))(31 downto 24); - - -- S-box-0: applied at state level for temporal value %(KEY_WIDTH/32) == 0 - GEN_SBOX_0: for i in 0 to 3 generate - SBOX_0: entity work.s_box_lut port map( - data_in => key_shift(i*8+7 downto i*8), - data_out => key_s_box_0(i*8+7 downto i*8) - ); - end generate GEN_SBOX_0; - - -- Add round constant - temp_0(31 downto 24) <= key_s_box_0(31 downto 24) xor rnd_const; - temp_0(23 downto 0) <= key_s_box_0(23 downto 0); - - -- Next key - -- 0%(KEY_WIDTH/32) == 0 - key_next(0) <= key_word(0) xor temp_0; - - GEN_TEMP_MIDDLE: if (KEY_WIDTH/32)>6 generate - -- S-box-4: applied at state level for temporal value %(KEY_WIDTH/32) == 4 && (KEY_WIDTH>6) - GEN_SBOX_4: for i in 0 to 3 generate - SBOX_4: entity work.s_box_lut port map( - data_in => key_next(3)(i*8+7 downto i*8), - data_out => key_s_box_4(i*8+7 downto i*8) - ); - end generate GEN_SBOX_4; - - temp_4 <= key_s_box_4 xor key_word(4); - key_next(4) <= temp_4; - - -- (1-(KEY_WIDTH/32-1))%(KEY_WIDTH/32) != 0 - GEN_NEXT_KEY_4: for i in 0 to (KEY_WIDTH/32-1-1) generate - GEN_4: if i /= 3 generate - key_next(i+1) <= key_word(i+1) xor key_next(i); - end generate GEN_4; - end generate GEN_NEXT_KEY_4; - - end generate GEN_TEMP_MIDDLE; - - GEN_NEXT_KEY: if (KEY_WIDTH/32)<=6 generate - GEN_KEY: for i in 0 to (KEY_WIDTH/32-1-1) generate - key_next(i+1) <= key_word(i+1) xor key_next(i); - end generate GEN_KEY; - end generate GEN_NEXT_KEY; - - -- Output - - GEN_KEY_TEMP_4: if (KEY_WIDTH/32)=4 generate - key_temp <= key_next(0) & key_next(1) & key_next(2) & key_next(3); - end generate GEN_KEY_TEMP_4; - - GEN_KEY_TEMP_6: if (KEY_WIDTH/32)=6 generate - key_temp <= key_next(0) & key_next(1) & key_next(2) & key_next(3) & key_next(4) & key_next(5); - end generate GEN_KEY_TEMP_6; - - GEN_KEY_TEMP_8: if (KEY_WIDTH/32)=8 generate - key_temp <= key_next(0) & key_next(1) & key_next(2) & key_next(3) & key_next(4) & key_next(5) & key_next(6) & key_next(7); - end generate GEN_KEY_TEMP_8; - - key_out <= key_temp; - -end architecture RTL; \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/key_pipe_reg.vhd b/examples_hw/apps/rdma_aes/hdl/key_pipe_reg.vhd deleted file mode 100644 index 747ba417a..000000000 --- a/examples_hw/apps/rdma_aes/hdl/key_pipe_reg.vhd +++ /dev/null @@ -1,50 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity key_pipe_reg is - generic( - KEY_WIDTH : integer := 128 - ); - port( - clk : in std_logic; - reset_n : in std_logic; - dVal_in : in std_logic; -- Data valid signal - dVal_out : out std_logic; - data_in : in std_logic_vector(KEY_WIDTH-1 downto 0); - data_out : out std_logic_vector(KEY_WIDTH-1 downto 0) - ); -end entity key_pipe_reg; - -architecture RTL of key_pipe_reg is - - -- Internal registers - signal dVal_reg : std_logic; - signal data_reg : std_logic_vector(KEY_WIDTH-1 downto 0); - -begin - - -- Register process - -- - CR_REG: process (clk, reset_n) is - begin - if rising_edge(clk) then - if reset_n = '0' then - dVal_reg <= '0'; - data_reg <= (others => '0'); - else - dVal_reg <= '0'; - if dVal_in = '1' then - dVal_reg <= '1'; - data_reg <= data_in; - end if; - end if; - end if; - - end process CR_REG; - - -- Output - dVal_out <= dVal_reg; - data_out <= data_reg; - -end architecture RTL; \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/key_pipe_stage.vhd b/examples_hw/apps/rdma_aes/hdl/key_pipe_stage.vhd deleted file mode 100644 index b71b3c2bb..000000000 --- a/examples_hw/apps/rdma_aes/hdl/key_pipe_stage.vhd +++ /dev/null @@ -1,52 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity key_pipe_stage is - generic( - KEY_WIDTH : integer := 128 - ); - port( - clk : in std_logic; - reset_n : in std_logic; - keyVal_in : in std_logic; -- Key valid signal - keyVal_out : out std_logic; - key_in : in std_logic_vector(KEY_WIDTH-1 downto 0); - key_out : out std_logic_vector(KEY_WIDTH-1 downto 0); - rnd_const : in std_logic_vector(7 downto 0) - ); -end entity key_pipe_stage; - -architecture RTL of key_pipe_stage is - - -- Internal signals - signal key_exp : std_logic_vector(KEY_WIDTH-1 downto 0); - -begin - - -- Instantiate Key expansion - GEN_KEY_EXP: entity work.key_expansion - generic map( - KEY_WIDTH => KEY_WIDTH - ) - port map( - key_in => key_in, - key_out => key_exp, - rnd_const => rnd_const - ); - - -- Instantiate Pipe register - GEN_AES_REG: entity work.key_pipe_reg - generic map( - KEY_WIDTH => KEY_WIDTH - ) - port map( - clk => clk, - reset_n => reset_n, - dVal_in => keyVal_in, - dVal_out => keyVal_out, - data_in => key_exp, - data_out => key_out - ); - -end architecture RTL; \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/key_pipeline.vhd b/examples_hw/apps/rdma_aes/hdl/key_pipeline.vhd deleted file mode 100644 index 03a811ee3..000000000 --- a/examples_hw/apps/rdma_aes/hdl/key_pipeline.vhd +++ /dev/null @@ -1,106 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - -entity key_pipeline is - generic( - KEY_WIDTH : integer := 128; - KEY_ROUNDS: integer := 11 - ); - port( - clk : in std_logic; - reset_n : in std_logic; - keyVal_in : in std_logic; -- Key valid - keyVal_out : out std_logic; - key_in : in std_logic_vector(KEY_WIDTH-1 downto 0); - key_out : out std_logic_vector(KEY_ROUNDS*KEY_WIDTH-1 downto 0) - ); -end entity key_pipeline; - -architecture RTL of key_pipeline is - - -- Internal signals - type keyVal_array is array (KEY_ROUNDS-1 downto 0) of std_logic; - type key_array is array (KEY_ROUNDS-1 downto 0) of std_logic_vector((KEY_WIDTH-1) downto 0); - - signal keyVal_pipe : keyVal_array; -- Key valid signal pipeline - signal key_pipe : key_array; -- Key pipeline - - -- Internal RAM for round constants - type ram_type is array(natural range<>) of std_logic_vector(7 downto 0); - constant rcon: ram_type(0 to 9) := (X"01", X"02", X"04", X"08", X"10", X"20", X"40", X"80", X"1b", X"36"); - -begin - - -- Instantiate base key register - GEN_KEY_BASE: entity work.key_pipe_reg - generic map ( - KEY_WIDTH => KEY_WIDTH - ) - port map( - clk => clk, - reset_n => reset_n, - dVal_in => keyVal_in, - dVal_out => keyVal_pipe(0), - data_in => key_in, - data_out => key_pipe(0) - ); - - -- Instantiate key expansion pipeline - GEN_KEY_EXP: for i in 0 to KEY_ROUNDS-1-1 generate - KEY_X: entity work.key_pipe_stage - generic map( - KEY_WIDTH => KEY_WIDTH - ) - port map( - clk => clk, - reset_n => reset_n, - keyVal_in => keyVal_pipe(i), - keyVal_out => keyVal_pipe(i+1), - key_in => key_pipe(i), - key_out => key_pipe(i+1), - rnd_const => rcon(i) - ); - end generate GEN_KEY_EXP; - - -- Key valid out - keyVal_out <= keyVal_pipe(KEY_ROUNDS-1); - - -- Keys out - - - GEN_KEYS_OUT_4: if (KEY_WIDTH/32)=4 generate - GEN_4: for i in 0 to KEY_ROUNDS-1 generate - key_out(i*KEY_WIDTH+(KEY_WIDTH-1) downto i*KEY_WIDTH) <= key_pipe(i); - end generate GEN_4; - end generate GEN_KEYS_OUT_4; - - GEN_KEYS_OUT_6: if (KEY_WIDTH/32)=6 generate - key_out(127 downto 0) <= key_pipe(0)(191 downto 64); - key_out(255 downto 128) <= key_pipe(0)(63 downto 0) & key_pipe(1)(191 downto 128); - key_out(383 downto 256) <= key_pipe(1)(127 downto 0); - - key_out(511 downto 384) <= key_pipe(2)(191 downto 64); - key_out(639 downto 512) <= key_pipe(2)(63 downto 0) & key_pipe(3)(191 downto 128); - key_out(767 downto 640) <= key_pipe(3)(127 downto 0); - - key_out(895 downto 768) <= key_pipe(4)(191 downto 64); - key_out(1023 downto 896) <= key_pipe(4)(63 downto 0) & key_pipe(5)(191 downto 128); - key_out(1151 downto 1024) <= key_pipe(5)(127 downto 0); - - key_out(1279 downto 1152) <= key_pipe(6)(191 downto 64); - key_out(1407 downto 1280) <= key_pipe(6)(63 downto 0) & key_pipe(7)(191 downto 128); - key_out(1535 downto 1408) <= key_pipe(7)(127 downto 0); - - key_out(1663 downto 1536) <= key_pipe(8)(191 downto 64); - - end generate GEN_KEYS_OUT_6; - - GEN_KEYS_OUT_8: if (KEY_WIDTH/32)=8 generate - GEN_8: for i in 0 to KEY_ROUNDS-1 generate - key_out(i*KEY_WIDTH+(KEY_WIDTH-1) downto i*KEY_WIDTH) <= key_pipe(i)(127 downto 0) & key_pipe(i)(255 downto 128); - end generate GEN_8; - end generate GEN_KEYS_OUT_8; - -end architecture RTL; \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/key_top.vhd b/examples_hw/apps/rdma_aes/hdl/key_top.vhd deleted file mode 100644 index 4796ed496..000000000 --- a/examples_hw/apps/rdma_aes/hdl/key_top.vhd +++ /dev/null @@ -1,66 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.rounds.all; - -entity key_top is - generic( - NPAR : integer := 2; - KEY_WIDTH : integer := 128; - KEY_ROUNDS: integer := 11; - OPERATION : integer := 0 -- [0-encryption, 1-decryption] - ); - port( - clk : in std_logic; - reset_n : in std_logic; - stall : in std_logic; - -- Key - key_in : in std_logic_vector(KEY_WIDTH-1 downto 0); - keyVal_in : in std_logic; - keyVal_out: out std_logic; - key_out : out std_logic_vector(KEY_ROUNDS*KEY_WIDTH-1 downto 0) - ); -end entity key_top; - -architecture RTL of key_top is - - type keep_array is array (NPAR-1 downto 0) of std_logic_vector(15 downto 0); - - --variable key_rounds : integer := key_rounds_number(KEY_WIDTH); - -- Internal signals - signal key_exp : std_logic_vector(key_rounds_number(KEY_WIDTH)*KEY_WIDTH-1 downto 0); - signal key_op: std_logic_vector(key_rounds_number(KEY_WIDTH)*KEY_WIDTH-1 downto 0); - -begin - - -- Instantiate key pipeline - GEN_KEY_PIPE: entity work.key_pipeline - generic map( - KEY_WIDTH => KEY_WIDTH, - KEY_ROUNDS => key_rounds_number(KEY_WIDTH) - ) - port map( - clk => clk, - reset_n => reset_n, - keyVal_in => keyVal_in, - keyVal_out => keyVal_out, - key_in => key_in, - key_out => key_exp - ); - - -- Gen key depending on the OPERATION - GEN_KEY_ENC: if OPERATION=0 generate - key_op <= key_exp; - end generate GEN_KEY_ENC; - - GEN_KEY_DEC: if OPERATION=1 generate - GEN_KEY: for i in 0 to encrypt_rounds_number(KEY_WIDTH)+1 generate --ENC_ROUNDS - key_op(128*i+127 downto 128*i) <= key_exp((encrypt_rounds_number(KEY_WIDTH)+1-i)*128+127 downto (encrypt_rounds_number(KEY_WIDTH)+1-i)*128); - end generate GEN_KEY; - end generate GEN_KEY_DEC; - - key_out <= key_op; - -end architecture RTL; \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/mix_columns.vhd b/examples_hw/apps/rdma_aes/hdl/mix_columns.vhd deleted file mode 100644 index f73f96c5a..000000000 --- a/examples_hw/apps/rdma_aes/hdl/mix_columns.vhd +++ /dev/null @@ -1,51 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity mix_columns is - port( - data_in : in std_logic_vector(127 downto 0); - data_out : out std_logic_vector(127 downto 0) - ); -end entity mix_columns; - -architecture RTL of mix_columns is - - -- Internal signals - type data_array is array (15 downto 0) of std_logic_vector(7 downto 0); - -- x1, x2, x3 multiplication - signal in_array, out_array, in_array_x2, in_array_x3 : data_array; - -begin - - -- Input generation - GEN_IN: for i in 15 downto 0 generate - in_array(15-i) <= data_in(i*8+7 downto i*8); - end generate GEN_IN; - - -- Multiplication - GEN_M: for i in 15 downto 0 generate - -- x2 - in_array_x2(15-i) <= - (in_array(15-i)(6 downto 0) & '0') xor "00011011" when in_array(15-i)(7) = '1' else - (in_array(15-i)(6 downto 0) & '0'); - -- x3 - in_array_x3(15-i) <= - (in_array(15-i)(6 downto 0) & '0') xor in_array(15-i) xor "00011011" when in_array(15-i)(7) = '1' else - (in_array(15-i)(6 downto 0) & '0') xor in_array(15-i); - end generate GEN_M; - - -- Mixed columns generation - GEN_MC: for i in 0 to 3 generate - out_array(4*i) <= in_array_x2(4*i) xor in_array_x3(4*i+1) xor in_array(4*i+2) xor in_array(4*i+3); - out_array(4*i+1) <= in_array(4*i) xor in_array_x2(4*i+1) xor in_array_x3(4*i+2) xor in_array(4*i+3); - out_array(4*i+2) <= in_array(4*i) xor in_array(4*i+1) xor in_array_x2(4*i+2) xor in_array_x3(4*i+3); - out_array(4*i+3) <= in_array_x3(4*i) xor in_array(4*i+1) xor in_array(4*i+2) xor in_array_x2(4*i+3); - end generate; - - -- Output generation - GEN_O: for i in 15 downto 0 generate - data_out(i*8+7 downto i*8) <= out_array(15-i); - end generate GEN_O; - -end architecture RTL; \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/mux_host_card_rd_rdma.sv b/examples_hw/apps/rdma_aes/hdl/mux_host_card_rd_rdma.sv deleted file mode 100644 index cf5904be8..000000000 --- a/examples_hw/apps/rdma_aes/hdl/mux_host_card_rd_rdma.sv +++ /dev/null @@ -1,178 +0,0 @@ -/** - * Copyright (c) 2021, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -`timescale 1ns / 1ps - -import lynxTypes::*; - - -module mux_host_card_rd_rdma ( - input logic aclk, - input logic aresetn, - - input logic [PID_BITS-1:0] mux_ctid, - metaIntf.s s_rq, - metaIntf.m m_sq, - - AXI4SR.s s_axis_host, - AXI4SR.s s_axis_card, - AXI4SR.m m_axis -); - -// -- FSM -typedef enum logic[0:0] {ST_IDLE, ST_MUX} state_t; -logic [0:0] state_C, state_N; - -// -- Meta -metaIntf #(.STYPE(req_t)) sq (); -queue_meta inst_queue_sq (.aclk(aclk), .aresetn(aresetn), .s_meta(sq), .m_meta(m_sq)); - -// -- Internal regs -logic host_C, host_N; -logic [BLEN_BITS-1:0] cnt_C, cnt_N; - -// -- Internal signals -logic tr_done; - -// -- AXIS -AXI4SR axis_int (); - -// ----------------------------------------------------------------------------------------------------------------------- -// Mux -// ----------------------------------------------------------------------------------------------------------------------- -always_comb begin - if(state_C == ST_MUX) begin - axis_int.tvalid = host_C ? s_axis_host.tvalid : s_axis_card.tvalid; - axis_int.tlast = host_C ? s_axis_host.tlast : s_axis_card.tlast; - axis_int.tkeep = host_C ? s_axis_host.tkeep : s_axis_card.tkeep; - axis_int.tdata = host_C ? s_axis_host.tdata : s_axis_card.tdata; - axis_int.tid = host_C ? s_axis_host.tid : s_axis_card.tid; - - s_axis_card.tready = host_C ? 1'b0 : axis_int.tready; - s_axis_host.tready = host_C ? axis_int.tready : 1'b0; - end - else begin - axis_int.tvalid = 1'b0; - axis_int.tlast = 1'b0; - axis_int.tkeep = 0; - axis_int.tdata = 0; - axis_int.tid = 0; - - s_axis_card.tready = 1'b0; - s_axis_host.tready = 1'b0; - end -end - -// ----------------------------------------------------------------------------------------------------------------------- -// State -// ----------------------------------------------------------------------------------------------------------------------- -always_ff @(posedge aclk) begin: PROC_REG -if (aresetn == 1'b0) begin - state_C <= ST_IDLE; - - cnt_C <= 'X; - host_C <= 'X; -end -else - state_C <= state_N; - - cnt_C <= cnt_N; - host_C <= host_N; -end - -// -- NSL -always_comb begin: NSL - state_N = state_C; - - case(state_C) - ST_IDLE: - state_N = s_rq.valid && sq.ready ? ST_MUX : ST_IDLE; - - ST_MUX: - state_N = tr_done ? (s_rq.valid && sq.ready ? ST_MUX : ST_IDLE) : ST_MUX; - - endcase // state_C -end - -// -- DP -always_comb begin : DP - cnt_N = cnt_C; - host_N = host_C; - - // Transfer done - tr_done = (cnt_C == 0) && (axis_int.tvalid & axis_int.tready); - - // Mux - s_rq.ready = 1'b0; - sq.valid = 1'b0; - sq.data = s_rq.data; - - case(state_C) - ST_IDLE: begin - if(s_rq.valid && sq.ready) begin - s_rq.ready = 1'b1; - sq.valid = 1'b1; - cnt_N = s_rq.data.len; - host_N = (mux_ctid == s_rq.data.pid); - end - end - - ST_MUX: begin - if(tr_done) begin - if(s_rq.valid && sq.ready) begin - s_rq.ready = 1'b1; - sq.valid = 1'b1; - cnt_N = s_rq.data.len; - host_N = (mux_ctid == s_rq.data.pid); - end - end - else begin - cnt_N = (axis_int.tvalid & axis_int.tready) ? cnt_C - 1 : cnt_C; - end - end - - endcase -end - -axisr_data_fifo_512 inst_data_fifo ( - .s_axis_aresetn(aresetn), - .s_axis_aclk(aclk), - .s_axis_tvalid(axis_int.tvalid), - .s_axis_tready(axis_int.tready), - .s_axis_tdata (axis_int.tdata), - .s_axis_tkeep (axis_int.tkeep), - .s_axis_tlast (axis_int.tlast), - .s_axis_tid (axis_int.tid), - .m_axis_tvalid(m_axis.tvalid), - .m_axis_tready(m_axis.tready), - .m_axis_tdata (m_axis.tdata), - .m_axis_tkeep (m_axis.tkeep), - .m_axis_tlast (m_axis.tlast), - .m_axis_tid (m_axis.tid) -); - -endmodule \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/mux_host_card_wr_rdma.sv b/examples_hw/apps/rdma_aes/hdl/mux_host_card_wr_rdma.sv deleted file mode 100644 index 563a94385..000000000 --- a/examples_hw/apps/rdma_aes/hdl/mux_host_card_wr_rdma.sv +++ /dev/null @@ -1,187 +0,0 @@ -/** - * Copyright (c) 2021, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -`timescale 1ns / 1ps - -import lynxTypes::*; - -module mux_host_card_wr_rdma ( - input logic aclk, - input logic aresetn, - - input logic [PID_BITS-1:0] mux_ctid, - metaIntf.s s_rq, - metaIntf.m m_sq, - - AXI4SR.s s_axis, - AXI4SR.m m_axis_host, - AXI4SR.m m_axis_card -); - -// -- FSM -typedef enum logic[0:0] {ST_IDLE, ST_MUX} state_t; -logic [0:0] state_C, state_N; - -// -- Meta -metaIntf #(.STYPE(req_t)) sq (); -queue_meta inst_queue_sq (.aclk(aclk), .aresetn(aresetn), .s_meta(sq), .m_meta(m_sq)); - -// -- Internal regs -logic host_C, host_N; -logic [BLEN_BITS-1:0] cnt_C, cnt_N; - -// -- Internal signals -logic tr_done; - -// -- AXIS -AXI4SR axis_int (); - -// ----------------------------------------------------------------------------------------------------------------------- -// Mux -// ----------------------------------------------------------------------------------------------------------------------- -always_comb begin - if(state_C == ST_MUX) begin - m_axis_host.tvalid = host_C ? axis_int.tvalid : 1'b0; - m_axis_host.tlast = host_C ? axis_int.tlast : 1'b0; - m_axis_host.tdata = host_C ? axis_int.tdata : 0; - m_axis_host.tkeep = host_C ? axis_int.tkeep : 0; - m_axis_host.tid = host_C ? axis_int.tid : 0; - - m_axis_card.tvalid = ~host_C ? axis_int.tvalid : 1'b0; - m_axis_card.tlast = ~host_C ? axis_int.tlast : 1'b0; - m_axis_card.tdata = ~host_C ? axis_int.tdata : 0; - m_axis_card.tkeep = ~host_C ? axis_int.tkeep : 0; - m_axis_card.tid = ~host_C ? axis_int.tid : 0; - - axis_int.tready = host_C ? m_axis_host.tready : m_axis_card.tready; - end - else begin - m_axis_host.tvalid = 1'b0; - m_axis_host.tlast = 1'b0; - m_axis_host.tdata = 0; - m_axis_host.tkeep = 0; - m_axis_host.tid = 0; - - m_axis_card.tvalid = 1'b0; - m_axis_card.tlast = 1'b0; - m_axis_card.tdata = 0; - m_axis_card.tkeep = 0; - m_axis_card.tid = 0; - - axis_int.tready = 1'b0; - end -end - -// ----------------------------------------------------------------------------------------------------------------------- -// State -// ----------------------------------------------------------------------------------------------------------------------- -always_ff @(posedge aclk) begin: PROC_REG -if (aresetn == 1'b0) begin - state_C <= ST_IDLE; - - cnt_C <= 'X; - host_C <= 'X; -end -else - state_C <= state_N; - - cnt_C <= cnt_N; - host_C <= host_N; -end - -// -- NSL -always_comb begin: NSL - state_N = state_C; - - case(state_C) - ST_IDLE: - state_N = s_rq.valid && sq.ready ? ST_MUX : ST_IDLE; - - ST_MUX: - state_N = tr_done ? (s_rq.valid && sq.ready ? ST_MUX : ST_IDLE) : ST_MUX; - - endcase // state_C -end - -// -- DP -always_comb begin : DP - cnt_N = cnt_C; - host_N = host_C; - - // Transfer done - tr_done = (cnt_C == 0) && (axis_int.tvalid & axis_int.tready); - - // Mux - s_rq.ready = 1'b0; - sq.valid = 1'b0; - sq.data = s_rq.data; - - case(state_C) - ST_IDLE: begin - if(s_rq.valid && sq.ready) begin - s_rq.ready = 1'b1; - sq.valid = 1'b1; - cnt_N = s_rq.data.len; - host_N = (mux_ctid == s_rq.data.pid); - end - end - - ST_MUX: begin - if(tr_done) begin - if(s_rq.valid && sq.ready) begin - s_rq.ready = 1'b1; - sq.valid = 1'b1; - cnt_N = s_rq.data.len; - host_N = (mux_ctid == s_rq.data.pid); - end - end - else begin - cnt_N = (axis_int.tvalid & axis_int.tready) ? cnt_C - 1 : cnt_C; - end - end - - endcase -end - -axisr_data_fifo_512 inst_data_fifo ( - .s_axis_aresetn(aresetn), - .s_axis_aclk(aclk), - .s_axis_tvalid(s_axis.tvalid), - .s_axis_tready(s_axis.tready), - .s_axis_tdata (s_axis.tdata), - .s_axis_tkeep (s_axis.tkeep), - .s_axis_tlast (s_axis.tlast), - .s_axis_tid (s_axis.tid), - .m_axis_tvalid(axis_int.tvalid), - .m_axis_tready(axis_int.tready), - .m_axis_tdata (axis_int.tdata), - .m_axis_tkeep (axis_int.tkeep), - .m_axis_tlast (axis_int.tlast), - .m_axis_tid (axis_int.tid) -); - -endmodule \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/pipe_reg.vhd b/examples_hw/apps/rdma_aes/hdl/pipe_reg.vhd deleted file mode 100644 index bd1badd02..000000000 --- a/examples_hw/apps/rdma_aes/hdl/pipe_reg.vhd +++ /dev/null @@ -1,66 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity pipe_reg is - generic( - DATA_WIDTH : integer := 128 - ); - port( - clk : in std_logic; - reset_n : in std_logic; - stall : in std_logic; - last_in : in std_logic; - last_out : out std_logic; - keep_in : in std_logic_vector(DATA_WIDTH/8-1 downto 0); - keep_out : out std_logic_vector(DATA_WIDTH/8-1 downto 0); - dVal_in : in std_logic; -- Data valid signal - dVal_out : out std_logic; - data_in : in std_logic_vector(DATA_WIDTH-1 downto 0); - data_out : out std_logic_vector(DATA_WIDTH-1 downto 0) - ); -end entity pipe_reg; - -architecture RTL of pipe_reg is - - -- Internal registers - signal dVal_reg : std_logic; - signal last_reg : std_logic; - signal keep_reg : std_logic_vector(DATA_WIDTH/8-1 downto 0); - signal data_reg : std_logic_vector(DATA_WIDTH-1 downto 0); - -begin - - -- Register process - -- - CR_REG: process (clk, reset_n) is - begin - if rising_edge(clk) then - if reset_n = '0' then - dVal_reg <= '0'; - last_reg <= '0'; - keep_reg <= (others => '0'); - data_reg <= (others => '0'); - else --if rising_edge(clk) then - if stall = '0' then - dVal_reg <= '0'; - if dVal_in = '1' then - dVal_reg <= '1'; - last_reg <= last_in; - keep_reg <= keep_in; - data_reg <= data_in; - end if; - end if; - - end if; - end if; - - end process CR_REG; - - -- Output - dVal_out <= dVal_reg; - last_out <= last_reg; - keep_out <= keep_reg; - data_out <= data_reg; - -end architecture RTL; \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/rdma_aes_slv.sv b/examples_hw/apps/rdma_aes/hdl/rdma_aes_slv.sv deleted file mode 100644 index f7fbb2412..000000000 --- a/examples_hw/apps/rdma_aes/hdl/rdma_aes_slv.sv +++ /dev/null @@ -1,245 +0,0 @@ -import lynxTypes::*; - -module rdma_aes_slv ( - input logic aclk, - input logic aresetn, - - AXI4L.s axi_ctrl, - - output logic [PID_BITS-1:0] mux_ctid, - - output logic [127:0] key_out, - output logic keyStart -); - -//`define DEBUG_CNFG_SLAVE - -// -- Decl ---------------------------------------------------------- -// ------------------------------------------------------------------ - -// Constants -localparam integer N_REGS = 3; - -localparam integer ADDR_LSB = $clog2(AXIL_DATA_BITS/8); -localparam integer ADDR_MSB = $clog2(N_REGS); -localparam integer AXI_ADDR_BITS = ADDR_LSB + ADDR_MSB; - -// Internal registers -logic [AXI_ADDR_BITS-1:0] axi_awaddr; -logic axi_awready; -logic [AXI_ADDR_BITS-1:0] axi_araddr; -logic axi_arready; -logic [1:0] axi_bresp; -logic axi_bvalid; -logic axi_wready; -logic [AXIL_DATA_BITS-1:0] axi_rdata; -logic [1:0] axi_rresp; -logic axi_rvalid; - -// Registers -logic [N_REGS-1:0][AXIL_DATA_BITS-1:0] slv_reg; -logic slv_reg_rden; -logic slv_reg_wren; -logic aw_en; - -// -- Def ----------------------------------------------------------- -// ------------------------------------------------------------------ - -// -- Register map ----------------------------------------------------------------------- -localparam integer CTID_REG = 0; -// 0 (WR) : Ctid -localparam integer KEY_LOW_REG = 1; -// 1 (WR) : Key low -localparam integer KEY_HIGH_REG = 2; -// 2 (WR) : Key high - -// Write process -assign slv_reg_wren = axi_wready && axi_ctrl.wvalid && axi_awready && axi_ctrl.awvalid; - -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) begin - slv_reg <= 0; - - keyStart <= 1'b0; - end - else begin - keyStart <= 1'b0; - - if(slv_reg_wren) begin - case (axi_awaddr[ADDR_LSB+:ADDR_MSB]) - CTID_REG: // Ctid select - for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin - if(axi_ctrl.wstrb[i]) begin - slv_reg[CTID_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8]; - end - end - KEY_LOW_REG: // Key low - for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin - if(axi_ctrl.wstrb[i]) begin - slv_reg[KEY_LOW_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8]; - end - end - KEY_HIGH_REG: // Key high - for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin - if(axi_ctrl.wstrb[i]) begin - slv_reg[KEY_HIGH_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8]; - keyStart <= 1'b1; - end - end - default : ; - endcase - end - end -end - -assign mux_ctid = slv_reg[CTID_REG][PID_BITS-1:0]; -assign key_out[63:0] = slv_reg[KEY_LOW_REG]; -assign key_out[127:64] = slv_reg[KEY_HIGH_REG]; - -// Read process -assign slv_reg_rden = axi_arready & axi_ctrl.arvalid & ~axi_rvalid; - -always_ff @(posedge aclk) begin - if( aresetn == 1'b0 ) begin - axi_rdata <= 0; - end - else begin - if(slv_reg_rden) begin - axi_rdata <= 0; - case (axi_araddr[ADDR_LSB+:ADDR_MSB]) - CTID_REG: // Ctid - axi_rdata <= slv_reg[CTID_REG]; - KEY_LOW_REG: // Key low - axi_rdata <= slv_reg[KEY_LOW_REG]; - KEY_HIGH_REG: // Key high - axi_rdata <= slv_reg[KEY_HIGH_REG]; - default: ; - endcase - end - end -end - -// I/O -assign axi_ctrl.awready = axi_awready; -assign axi_ctrl.arready = axi_arready; -assign axi_ctrl.bresp = axi_bresp; -assign axi_ctrl.bvalid = axi_bvalid; -assign axi_ctrl.wready = axi_wready; -assign axi_ctrl.rdata = axi_rdata; -assign axi_ctrl.rresp = axi_rresp; -assign axi_ctrl.rvalid = axi_rvalid; - -// awready and awaddr -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) - begin - axi_awready <= 1'b0; - axi_awaddr <= 0; - aw_en <= 1'b1; - end - else - begin - if (~axi_awready && axi_ctrl.awvalid && axi_ctrl.wvalid && aw_en) - begin - axi_awready <= 1'b1; - aw_en <= 1'b0; - axi_awaddr <= axi_ctrl.awaddr; - end - else if (axi_ctrl.bready && axi_bvalid) - begin - aw_en <= 1'b1; - axi_awready <= 1'b0; - end - else - begin - axi_awready <= 1'b0; - end - end -end - -// arready and araddr -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) - begin - axi_arready <= 1'b0; - axi_araddr <= 0; - end - else - begin - if (~axi_arready && axi_ctrl.arvalid) - begin - axi_arready <= 1'b1; - axi_araddr <= axi_ctrl.araddr; - end - else - begin - axi_arready <= 1'b0; - end - end -end - -// bvalid and bresp -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) - begin - axi_bvalid <= 0; - axi_bresp <= 2'b0; - end - else - begin - if (axi_awready && axi_ctrl.awvalid && ~axi_bvalid && axi_wready && axi_ctrl.wvalid) - begin - axi_bvalid <= 1'b1; - axi_bresp <= 2'b0; - end - else - begin - if (axi_ctrl.bready && axi_bvalid) - begin - axi_bvalid <= 1'b0; - end - end - end -end - -// wready -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) - begin - axi_wready <= 1'b0; - end - else - begin - if (~axi_wready && axi_ctrl.wvalid && axi_ctrl.awvalid && aw_en ) - begin - axi_wready <= 1'b1; - end - else - begin - axi_wready <= 1'b0; - end - end -end - -// rvalid and rresp (1Del?) -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) - begin - axi_rvalid <= 0; - axi_rresp <= 0; - end - else - begin - if (axi_arready && axi_ctrl.arvalid && ~axi_rvalid) - begin - axi_rvalid <= 1'b1; - axi_rresp <= 2'b0; - end - else if (axi_rvalid && axi_ctrl.rready) - begin - axi_rvalid <= 1'b0; - end - end -end - -endmodule // cnfg_slave \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/s_box_lut.vhd b/examples_hw/apps/rdma_aes/hdl/s_box_lut.vhd deleted file mode 100644 index b556e9064..000000000 --- a/examples_hw/apps/rdma_aes/hdl/s_box_lut.vhd +++ /dev/null @@ -1,40 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity s_box_lut is - port( - data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0) - ); -end entity s_box_lut; - -architecture RTL of s_box_lut is - - -- Internal RAM - type ram_type is array(natural range<>) of std_logic_vector(7 downto 0); - constant sbox_ram : ram_type(255 downto 0) := ( - X"16", X"bb", X"54", X"b0", X"0f", X"2d", X"99", X"41", X"68", X"42", X"e6", X"bf", X"0d", X"89", X"a1", X"8c", - X"df", X"28", X"55", X"ce", X"e9", X"87", X"1e", X"9b", X"94", X"8e", X"d9", X"69", X"11", X"98", X"f8", X"e1", - X"9e", X"1d", X"c1", X"86", X"b9", X"57", X"35", X"61", X"0e", X"f6", X"03", X"48", X"66", X"b5", X"3e", X"70", - X"8a", X"8b", X"bd", X"4b", X"1f", X"74", X"dd", X"e8", X"c6", X"b4", X"a6", X"1c", X"2e", X"25", X"78", X"ba", - X"08", X"ae", X"7a", X"65", X"ea", X"f4", X"56", X"6c", X"a9", X"4e", X"d5", X"8d", X"6d", X"37", X"c8", X"e7", - X"79", X"e4", X"95", X"91", X"62", X"ac", X"d3", X"c2", X"5c", X"24", X"06", X"49", X"0a", X"3a", X"32", X"e0", - X"db", X"0b", X"5e", X"de", X"14", X"b8", X"ee", X"46", X"88", X"90", X"2a", X"22", X"dc", X"4f", X"81", X"60", - X"73", X"19", X"5d", X"64", X"3d", X"7e", X"a7", X"c4", X"17", X"44", X"97", X"5f", X"ec", X"13", X"0c", X"cd", - X"d2", X"f3", X"ff", X"10", X"21", X"da", X"b6", X"bc", X"f5", X"38", X"9d", X"92", X"8f", X"40", X"a3", X"51", - X"a8", X"9f", X"3c", X"50", X"7f", X"02", X"f9", X"45", X"85", X"33", X"4d", X"43", X"fb", X"aa", X"ef", X"d0", - X"cf", X"58", X"4c", X"4a", X"39", X"be", X"cb", X"6a", X"5b", X"b1", X"fc", X"20", X"ed", X"00", X"d1", X"53", - X"84", X"2f", X"e3", X"29", X"b3", X"d6", X"3b", X"52", X"a0", X"5a", X"6e", X"1b", X"1a", X"2c", X"83", X"09", - X"75", X"b2", X"27", X"eb", X"e2", X"80", X"12", X"07", X"9a", X"05", X"96", X"18", X"c3", X"23", X"c7", X"04", - X"15", X"31", X"d8", X"71", X"f1", X"e5", X"a5", X"34", X"cc", X"f7", X"3f", X"36", X"26", X"93", X"fd", X"b7", - X"c0", X"72", X"a4", X"9c", X"af", X"a2", X"d4", X"ad", X"f0", X"47", X"59", X"fa", X"7d", X"c9", X"82", X"ca", - X"76", X"ab", X"d7", X"fe", X"2b", X"67", X"01", X"30", X"c5", X"6f", X"6b", X"f2", X"7b", X"77", X"7c", X"63" - ); - -begin - - -- Output - data_out <= sbox_ram(to_integer(unsigned(data_in))); - -end architecture RTL; \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/shift_rows.vhd b/examples_hw/apps/rdma_aes/hdl/shift_rows.vhd deleted file mode 100644 index 4f3d227bc..000000000 --- a/examples_hw/apps/rdma_aes/hdl/shift_rows.vhd +++ /dev/null @@ -1,54 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity shift_rows is - port( - data_in : in std_logic_vector(127 downto 0); - data_out : out std_logic_vector(127 downto 0) - ); -end entity shift_rows; - -architecture RTL of shift_rows is - - -- Internal signals - type data_array is array (15 downto 0) of std_logic_vector(7 downto 0); - signal in_array, out_array : data_array; - -begin - - -- Input generation - GEN_IN: for i in 15 downto 0 generate - in_array(15-i) <= data_in(i*8+7 downto i*8); - end generate GEN_IN; - - --First mixed column input - out_array(0) <= in_array(0); - out_array(1) <= in_array(5); - out_array(2) <= in_array(10); - out_array(3) <= in_array(15); - - -- Second mixed column input - out_array(4) <= in_array(4); - out_array(5) <= in_array(9); - out_array(6) <= in_array(14); - out_array(7) <= in_array(3); - - -- Third mixed column input - out_array(8) <= in_array(8); - out_array(9) <= in_array(13); - out_array(10) <= in_array(2); - out_array(11) <= in_array(7); - - -- Fourth mixed column input - out_array(12) <= in_array(12); - out_array(13) <= in_array(1); - out_array(14) <= in_array(6); - out_array(15) <= in_array(11); - - -- Output generation - GEN_OUT: for i in 15 downto 0 generate - data_out(i*8+7 downto i*8) <= out_array(15-i); - end generate GEN_OUT; - -end architecture RTL; \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/hdl/utils.vhd b/examples_hw/apps/rdma_aes/hdl/utils.vhd deleted file mode 100644 index 8ed12ab55..000000000 --- a/examples_hw/apps/rdma_aes/hdl/utils.vhd +++ /dev/null @@ -1,58 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - ---package utils is --- function bitlength(number : integer) return positive; --- ---end package utils; - ---package body utils is --- --- -- purpose: returns the minimum # of bits needed to represent the input number --- function bitlength(number : integer) return positive is --- variable acc : positive := 1; --- variable i : natural := 0; --- begin --- if number = 0 or number = -1 then --- return 1; --- else --- while True loop --- if acc > number then --- return i; --- end if; --- --- acc := acc * 2; --- i := i + 1; --- end loop; --- end if; --- end function bitlength; --- ---end package body utils; - -package rounds is - function key_rounds_number (key_width:integer) return integer; - function encrypt_rounds_number (key_width:integer) return integer; -end package rounds; - -package body rounds is - function key_rounds_number (key_width:integer) return integer is - begin - case key_width is - when 128 => return 11; -- 128*11/128 = 11 - when 192 => return 9; -- 128*13/192 = 9 - when 256 => return 8; -- 128*15/256 = 8 - when others => return 11; - end case; - end function; - - function encrypt_rounds_number (key_width:integer) return integer is - begin - case key_width is - when 128 => return 9; -- 10(total rounds)-1(final round) = 9 - when 192 => return 11; -- 12(total rounds)-1(final round) = 11 - when 256 => return 13; -- 14(total rounds)-1(final round) = 13 - when others => return 9; - end case; - end function; -end package body rounds; \ No newline at end of file diff --git a/examples_hw/apps/rdma_aes/vfpga_top.svh b/examples_hw/apps/rdma_aes/vfpga_top.svh deleted file mode 100644 index 1a6d574ed..000000000 --- a/examples_hw/apps/rdma_aes/vfpga_top.svh +++ /dev/null @@ -1,158 +0,0 @@ -/** - * VFPGA TOP - * - * Tie up all signals to the user kernels - * Still to this day, interfaces are not supported by Vivado packager ... - * This means verilog style port connections are needed. - * - */ - -// Consts -localparam integer N_AES_PIPELINES = 4; -localparam integer KEY_ROUNDS = 11; - -// CSR -logic [PID_BITS-1:0] mux_ctid; // go to card with this ctid -logic [128*KEY_ROUNDS-1:0] key_dec; -logic [128*KEY_ROUNDS-1:0] key_enc; -logic [128-1:0] key_slv; -logic key_start; - -rdma_aes_slv inst_rdma_aes_slv ( - .aclk(aclk), - .aresetn(aresetn), - - .axi_ctrl(axi_ctrl), - - .key_out(key_slv), - .keyStart(key_start), - - .mux_ctid(mux_ctid) -); - -AXI4SR axis_s0_send (); -AXI4SR axis_s0_recv (); - -mux_host_card_rd_rdma inst_mux_send ( - .aclk(aclk), - .aresetn(aresetn), - - .mux_ctid(mux_ctid), - .s_rq(rq_rd), - .m_sq(sq_rd), - - .s_axis_host(axis_host_recv[0]), - .s_axis_card(axis_card_recv[0]), - .m_axis(axis_s0_send) -); - -mux_host_card_wr_rdma inst_mux_recv ( - .aclk(aclk), - .aresetn(aresetn), - - .mux_ctid(mux_ctid), - .s_rq(rq_wr), - .m_sq(sq_wr), - - .s_axis(axis_s0_recv), - .m_axis_host(axis_host_send[0]), - .m_axis_card(axis_card_send[0]) -); - -// -// AES encryption and decryption -// - -// Key decryption -key_top #( - .OPERATION(1) -) inst_key_top_dec ( - .clk(aclk), - .reset_n(aresetn), - - .stall(1'b0), - - .key_in(key_slv), - .keyVal_in(keyStart), - .keyVal_out(), - .key_out(key_dec) -); - -// AES pipeline - receive (decrypt) -aes_top #( - .NPAR(N_AES_PIPELINES), - .OPERATION(1), // 0 - enc, 1 - dec - .MODE(0) // 0 - ECB, 1 - CTR, 2 - CBC -) inst_aes_top_dec ( - .clk(aclk), - .reset_n(aresetn), - .stall(~axis_s0_recv.tready), - // Key - .key_in(key_dec), - // - .last_in(axis_rdma_recv[0].tlast), - .last_out(axis_s0_recv.tlast), - .keep_in(axis_rdma_recv[0].tkeep), - .keep_out(axis_s0_recv.tkeep), - // Data - .dVal_in(axis_rdma_recv[0].tvalid), - .dVal_out(axis_s0_recv.tvalid), - .data_in(axis_rdma_recv[0].tdata), - .data_out(axis_s0_recv.tdata), - // Counter mode - .cntr_in(0) -); - -assign axis_rdma_recv[0].tready = axis_s0_recv.tready; -assign axis_s0_recv.tid = 0; - -// Key encryption -key_top #( - .OPERATION(1) -) inst_key_top_enc ( - .clk(aclk), - .reset_n(aresetn), - - .stall(1'b0), - - .key_in(key_slv), - .keyVal_in(keyStart), - .keyVal_out(), - .key_out(key_enc) -); - -// AES pipeline - send (encrypt) -aes_top #( - .NPAR(N_AES_PIPELINES), - .OPERATION(0), // 0 - enc, 1 - dec - .MODE(0) // 0 - ECB, 1 - CTR, 2 - CBC -) inst_aes_top_enc ( - .clk(aclk), - .reset_n(aresetn), - .stall(~axis_rdma_send[0].tready), - // Key - .key_in(key), - // - .last_in(axis_s0_send.tlast), - .last_out(axis_rdma_send[0].tlast), - .keep_in(axis_s0_send.tkeep), - .keep_out(axis_rdma_send[0].tkeep), - // Data - .dVal_in(axis_s0_send.tvalid), - .dVal_out(axis_rdma_send[0].tvalid), - .data_in(axis_s0_send.tdata), - .data_out(axis_rdma_send[0].tdata), - // Counter mode - .cntr_in(0) -); - -assign axis_s0_send.tready = axis_rdma_send[0].tready; -assign axis_rdma_send[0].tid = 0; - -// -// Tie-off unused -// - -always_comb notify.tie_off_m(); -always_comb cq_wr.tie_off_s(); -always_comb cq_rd.tie_off_s(); \ No newline at end of file diff --git a/examples_hw/apps/rdma_base/hdl/mux_host_card_rd_rdma.sv b/examples_hw/apps/rdma_base/hdl/mux_host_card_rd_rdma.sv deleted file mode 100644 index cf5904be8..000000000 --- a/examples_hw/apps/rdma_base/hdl/mux_host_card_rd_rdma.sv +++ /dev/null @@ -1,178 +0,0 @@ -/** - * Copyright (c) 2021, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -`timescale 1ns / 1ps - -import lynxTypes::*; - - -module mux_host_card_rd_rdma ( - input logic aclk, - input logic aresetn, - - input logic [PID_BITS-1:0] mux_ctid, - metaIntf.s s_rq, - metaIntf.m m_sq, - - AXI4SR.s s_axis_host, - AXI4SR.s s_axis_card, - AXI4SR.m m_axis -); - -// -- FSM -typedef enum logic[0:0] {ST_IDLE, ST_MUX} state_t; -logic [0:0] state_C, state_N; - -// -- Meta -metaIntf #(.STYPE(req_t)) sq (); -queue_meta inst_queue_sq (.aclk(aclk), .aresetn(aresetn), .s_meta(sq), .m_meta(m_sq)); - -// -- Internal regs -logic host_C, host_N; -logic [BLEN_BITS-1:0] cnt_C, cnt_N; - -// -- Internal signals -logic tr_done; - -// -- AXIS -AXI4SR axis_int (); - -// ----------------------------------------------------------------------------------------------------------------------- -// Mux -// ----------------------------------------------------------------------------------------------------------------------- -always_comb begin - if(state_C == ST_MUX) begin - axis_int.tvalid = host_C ? s_axis_host.tvalid : s_axis_card.tvalid; - axis_int.tlast = host_C ? s_axis_host.tlast : s_axis_card.tlast; - axis_int.tkeep = host_C ? s_axis_host.tkeep : s_axis_card.tkeep; - axis_int.tdata = host_C ? s_axis_host.tdata : s_axis_card.tdata; - axis_int.tid = host_C ? s_axis_host.tid : s_axis_card.tid; - - s_axis_card.tready = host_C ? 1'b0 : axis_int.tready; - s_axis_host.tready = host_C ? axis_int.tready : 1'b0; - end - else begin - axis_int.tvalid = 1'b0; - axis_int.tlast = 1'b0; - axis_int.tkeep = 0; - axis_int.tdata = 0; - axis_int.tid = 0; - - s_axis_card.tready = 1'b0; - s_axis_host.tready = 1'b0; - end -end - -// ----------------------------------------------------------------------------------------------------------------------- -// State -// ----------------------------------------------------------------------------------------------------------------------- -always_ff @(posedge aclk) begin: PROC_REG -if (aresetn == 1'b0) begin - state_C <= ST_IDLE; - - cnt_C <= 'X; - host_C <= 'X; -end -else - state_C <= state_N; - - cnt_C <= cnt_N; - host_C <= host_N; -end - -// -- NSL -always_comb begin: NSL - state_N = state_C; - - case(state_C) - ST_IDLE: - state_N = s_rq.valid && sq.ready ? ST_MUX : ST_IDLE; - - ST_MUX: - state_N = tr_done ? (s_rq.valid && sq.ready ? ST_MUX : ST_IDLE) : ST_MUX; - - endcase // state_C -end - -// -- DP -always_comb begin : DP - cnt_N = cnt_C; - host_N = host_C; - - // Transfer done - tr_done = (cnt_C == 0) && (axis_int.tvalid & axis_int.tready); - - // Mux - s_rq.ready = 1'b0; - sq.valid = 1'b0; - sq.data = s_rq.data; - - case(state_C) - ST_IDLE: begin - if(s_rq.valid && sq.ready) begin - s_rq.ready = 1'b1; - sq.valid = 1'b1; - cnt_N = s_rq.data.len; - host_N = (mux_ctid == s_rq.data.pid); - end - end - - ST_MUX: begin - if(tr_done) begin - if(s_rq.valid && sq.ready) begin - s_rq.ready = 1'b1; - sq.valid = 1'b1; - cnt_N = s_rq.data.len; - host_N = (mux_ctid == s_rq.data.pid); - end - end - else begin - cnt_N = (axis_int.tvalid & axis_int.tready) ? cnt_C - 1 : cnt_C; - end - end - - endcase -end - -axisr_data_fifo_512 inst_data_fifo ( - .s_axis_aresetn(aresetn), - .s_axis_aclk(aclk), - .s_axis_tvalid(axis_int.tvalid), - .s_axis_tready(axis_int.tready), - .s_axis_tdata (axis_int.tdata), - .s_axis_tkeep (axis_int.tkeep), - .s_axis_tlast (axis_int.tlast), - .s_axis_tid (axis_int.tid), - .m_axis_tvalid(m_axis.tvalid), - .m_axis_tready(m_axis.tready), - .m_axis_tdata (m_axis.tdata), - .m_axis_tkeep (m_axis.tkeep), - .m_axis_tlast (m_axis.tlast), - .m_axis_tid (m_axis.tid) -); - -endmodule \ No newline at end of file diff --git a/examples_hw/apps/rdma_base/hdl/mux_host_card_wr_rdma.sv b/examples_hw/apps/rdma_base/hdl/mux_host_card_wr_rdma.sv deleted file mode 100644 index 563a94385..000000000 --- a/examples_hw/apps/rdma_base/hdl/mux_host_card_wr_rdma.sv +++ /dev/null @@ -1,187 +0,0 @@ -/** - * Copyright (c) 2021, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -`timescale 1ns / 1ps - -import lynxTypes::*; - -module mux_host_card_wr_rdma ( - input logic aclk, - input logic aresetn, - - input logic [PID_BITS-1:0] mux_ctid, - metaIntf.s s_rq, - metaIntf.m m_sq, - - AXI4SR.s s_axis, - AXI4SR.m m_axis_host, - AXI4SR.m m_axis_card -); - -// -- FSM -typedef enum logic[0:0] {ST_IDLE, ST_MUX} state_t; -logic [0:0] state_C, state_N; - -// -- Meta -metaIntf #(.STYPE(req_t)) sq (); -queue_meta inst_queue_sq (.aclk(aclk), .aresetn(aresetn), .s_meta(sq), .m_meta(m_sq)); - -// -- Internal regs -logic host_C, host_N; -logic [BLEN_BITS-1:0] cnt_C, cnt_N; - -// -- Internal signals -logic tr_done; - -// -- AXIS -AXI4SR axis_int (); - -// ----------------------------------------------------------------------------------------------------------------------- -// Mux -// ----------------------------------------------------------------------------------------------------------------------- -always_comb begin - if(state_C == ST_MUX) begin - m_axis_host.tvalid = host_C ? axis_int.tvalid : 1'b0; - m_axis_host.tlast = host_C ? axis_int.tlast : 1'b0; - m_axis_host.tdata = host_C ? axis_int.tdata : 0; - m_axis_host.tkeep = host_C ? axis_int.tkeep : 0; - m_axis_host.tid = host_C ? axis_int.tid : 0; - - m_axis_card.tvalid = ~host_C ? axis_int.tvalid : 1'b0; - m_axis_card.tlast = ~host_C ? axis_int.tlast : 1'b0; - m_axis_card.tdata = ~host_C ? axis_int.tdata : 0; - m_axis_card.tkeep = ~host_C ? axis_int.tkeep : 0; - m_axis_card.tid = ~host_C ? axis_int.tid : 0; - - axis_int.tready = host_C ? m_axis_host.tready : m_axis_card.tready; - end - else begin - m_axis_host.tvalid = 1'b0; - m_axis_host.tlast = 1'b0; - m_axis_host.tdata = 0; - m_axis_host.tkeep = 0; - m_axis_host.tid = 0; - - m_axis_card.tvalid = 1'b0; - m_axis_card.tlast = 1'b0; - m_axis_card.tdata = 0; - m_axis_card.tkeep = 0; - m_axis_card.tid = 0; - - axis_int.tready = 1'b0; - end -end - -// ----------------------------------------------------------------------------------------------------------------------- -// State -// ----------------------------------------------------------------------------------------------------------------------- -always_ff @(posedge aclk) begin: PROC_REG -if (aresetn == 1'b0) begin - state_C <= ST_IDLE; - - cnt_C <= 'X; - host_C <= 'X; -end -else - state_C <= state_N; - - cnt_C <= cnt_N; - host_C <= host_N; -end - -// -- NSL -always_comb begin: NSL - state_N = state_C; - - case(state_C) - ST_IDLE: - state_N = s_rq.valid && sq.ready ? ST_MUX : ST_IDLE; - - ST_MUX: - state_N = tr_done ? (s_rq.valid && sq.ready ? ST_MUX : ST_IDLE) : ST_MUX; - - endcase // state_C -end - -// -- DP -always_comb begin : DP - cnt_N = cnt_C; - host_N = host_C; - - // Transfer done - tr_done = (cnt_C == 0) && (axis_int.tvalid & axis_int.tready); - - // Mux - s_rq.ready = 1'b0; - sq.valid = 1'b0; - sq.data = s_rq.data; - - case(state_C) - ST_IDLE: begin - if(s_rq.valid && sq.ready) begin - s_rq.ready = 1'b1; - sq.valid = 1'b1; - cnt_N = s_rq.data.len; - host_N = (mux_ctid == s_rq.data.pid); - end - end - - ST_MUX: begin - if(tr_done) begin - if(s_rq.valid && sq.ready) begin - s_rq.ready = 1'b1; - sq.valid = 1'b1; - cnt_N = s_rq.data.len; - host_N = (mux_ctid == s_rq.data.pid); - end - end - else begin - cnt_N = (axis_int.tvalid & axis_int.tready) ? cnt_C - 1 : cnt_C; - end - end - - endcase -end - -axisr_data_fifo_512 inst_data_fifo ( - .s_axis_aresetn(aresetn), - .s_axis_aclk(aclk), - .s_axis_tvalid(s_axis.tvalid), - .s_axis_tready(s_axis.tready), - .s_axis_tdata (s_axis.tdata), - .s_axis_tkeep (s_axis.tkeep), - .s_axis_tlast (s_axis.tlast), - .s_axis_tid (s_axis.tid), - .m_axis_tvalid(axis_int.tvalid), - .m_axis_tready(axis_int.tready), - .m_axis_tdata (axis_int.tdata), - .m_axis_tkeep (axis_int.tkeep), - .m_axis_tlast (axis_int.tlast), - .m_axis_tid (axis_int.tid) -); - -endmodule \ No newline at end of file diff --git a/examples_hw/apps/rdma_base/hdl/rdma_base_slv.sv b/examples_hw/apps/rdma_base/hdl/rdma_base_slv.sv deleted file mode 100644 index a1de99995..000000000 --- a/examples_hw/apps/rdma_base/hdl/rdma_base_slv.sv +++ /dev/null @@ -1,214 +0,0 @@ -import lynxTypes::*; - -module rdma_base_slv ( - input logic aclk, - input logic aresetn, - - AXI4L.s axi_ctrl, - - output logic [PID_BITS-1:0] mux_ctid -); - -//`define DEBUG_CNFG_SLAVE - -// -- Decl ---------------------------------------------------------- -// ------------------------------------------------------------------ - -// Constants -localparam integer N_REGS = 2; - -localparam integer ADDR_LSB = $clog2(AXIL_DATA_BITS/8); -localparam integer ADDR_MSB = $clog2(N_REGS); -localparam integer AXI_ADDR_BITS = ADDR_LSB + ADDR_MSB; - -// Internal registers -logic [AXI_ADDR_BITS-1:0] axi_awaddr; -logic axi_awready; -logic [AXI_ADDR_BITS-1:0] axi_araddr; -logic axi_arready; -logic [1:0] axi_bresp; -logic axi_bvalid; -logic axi_wready; -logic [AXIL_DATA_BITS-1:0] axi_rdata; -logic [1:0] axi_rresp; -logic axi_rvalid; - -// Registers -logic [N_REGS-1:0][AXIL_DATA_BITS-1:0] slv_reg; -logic slv_reg_rden; -logic slv_reg_wren; -logic aw_en; - -// -- Def ----------------------------------------------------------- -// ------------------------------------------------------------------ - -// -- Register map ----------------------------------------------------------------------- -localparam integer CTID_REG = 0; - -// Write process -assign slv_reg_wren = axi_wready && axi_ctrl.wvalid && axi_awready && axi_ctrl.awvalid; - -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) begin - slv_reg <= 0; - end - else begin - if(slv_reg_wren) begin - case (axi_awaddr[ADDR_LSB+:ADDR_MSB]) - CTID_REG: // Ctid select - for (int i = 0; i < (AXIL_DATA_BITS/8); i++) begin - if(axi_ctrl.wstrb[i]) begin - slv_reg[CTID_REG][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8]; - end - end - default : ; - endcase - end - end -end - -assign mux_ctid = slv_reg[CTID_REG][PID_BITS-1:0]; - -// Read process -assign slv_reg_rden = axi_arready & axi_ctrl.arvalid & ~axi_rvalid; - -always_ff @(posedge aclk) begin - if( aresetn == 1'b0 ) begin - axi_rdata <= 0; - end - else begin - if(slv_reg_rden) begin - axi_rdata <= 0; - case (axi_araddr[ADDR_LSB+:ADDR_MSB]) - CTID_REG: // Ctid - axi_rdata <= slv_reg[CTID_REG]; - default: ; - endcase - end - end -end - -// I/O -assign axi_ctrl.awready = axi_awready; -assign axi_ctrl.arready = axi_arready; -assign axi_ctrl.bresp = axi_bresp; -assign axi_ctrl.bvalid = axi_bvalid; -assign axi_ctrl.wready = axi_wready; -assign axi_ctrl.rdata = axi_rdata; -assign axi_ctrl.rresp = axi_rresp; -assign axi_ctrl.rvalid = axi_rvalid; - -// awready and awaddr -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) - begin - axi_awready <= 1'b0; - axi_awaddr <= 0; - aw_en <= 1'b1; - end - else - begin - if (~axi_awready && axi_ctrl.awvalid && axi_ctrl.wvalid && aw_en) - begin - axi_awready <= 1'b1; - aw_en <= 1'b0; - axi_awaddr <= axi_ctrl.awaddr; - end - else if (axi_ctrl.bready && axi_bvalid) - begin - aw_en <= 1'b1; - axi_awready <= 1'b0; - end - else - begin - axi_awready <= 1'b0; - end - end -end - -// arready and araddr -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) - begin - axi_arready <= 1'b0; - axi_araddr <= 0; - end - else - begin - if (~axi_arready && axi_ctrl.arvalid) - begin - axi_arready <= 1'b1; - axi_araddr <= axi_ctrl.araddr; - end - else - begin - axi_arready <= 1'b0; - end - end -end - -// bvalid and bresp -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) - begin - axi_bvalid <= 0; - axi_bresp <= 2'b0; - end - else - begin - if (axi_awready && axi_ctrl.awvalid && ~axi_bvalid && axi_wready && axi_ctrl.wvalid) - begin - axi_bvalid <= 1'b1; - axi_bresp <= 2'b0; - end - else - begin - if (axi_ctrl.bready && axi_bvalid) - begin - axi_bvalid <= 1'b0; - end - end - end -end - -// wready -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) - begin - axi_wready <= 1'b0; - end - else - begin - if (~axi_wready && axi_ctrl.wvalid && axi_ctrl.awvalid && aw_en ) - begin - axi_wready <= 1'b1; - end - else - begin - axi_wready <= 1'b0; - end - end -end - -// rvalid and rresp (1Del?) -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) - begin - axi_rvalid <= 0; - axi_rresp <= 0; - end - else - begin - if (axi_arready && axi_ctrl.arvalid && ~axi_rvalid) - begin - axi_rvalid <= 1'b1; - axi_rresp <= 2'b0; - end - else if (axi_rvalid && axi_ctrl.rready) - begin - axi_rvalid <= 1'b0; - end - end -end - -endmodule // cnfg_slave \ No newline at end of file diff --git a/examples_hw/apps/rdma_base/vfpga_top.svh b/examples_hw/apps/rdma_base/vfpga_top.svh deleted file mode 100644 index 899aa76bf..000000000 --- a/examples_hw/apps/rdma_base/vfpga_top.svh +++ /dev/null @@ -1,51 +0,0 @@ -/** - * VFPGA TOP - * - * Tie up all signals to the user kernels - * Still to this day, interfaces are not supported by Vivado packager ... - * This means verilog style port connections are needed. - * - */ - -// CSR -logic [PID_BITS-1:0] mux_ctid; // go to card with this ctid - -rdma_base_slv inst_rdma_base_slv ( - .aclk(aclk), - .aresetn(aresetn), - - .axi_ctrl(axi_ctrl), - - .mux_ctid(mux_ctid) -); - -mux_host_card_rd_rdma inst_mux_send ( - .aclk(aclk), - .aresetn(aresetn), - - .mux_ctid(mux_ctid), - .s_rq(rq_rd), - .m_sq(sq_rd), - - .s_axis_host(axis_host_recv[0]), - .s_axis_card(axis_card_recv[0]), - .m_axis(axis_rdma_send[0]) -); - -mux_host_card_wr_rdma inst_mux_recv ( - .aclk(aclk), - .aresetn(aresetn), - - .mux_ctid(mux_ctid), - .s_rq(rq_wr), - .m_sq(sq_wr), - - .s_axis(axis_rdma_recv[0]), - .m_axis_host(axis_host_send[0]), - .m_axis_card(axis_card_send[0]) -); - -// Tie-off unused -always_comb notify.tie_off_m(); -always_comb cq_rd.tie_off_s(); -always_comb cq_wr.tie_off_s(); \ No newline at end of file diff --git a/examples_hw/apps/tcp_iperf/hls/CMakeLists.txt b/examples_hw/apps/tcp_iperf/hls/CMakeLists.txt deleted file mode 100644 index 8e58388b7..000000000 --- a/examples_hw/apps/tcp_iperf/hls/CMakeLists.txt +++ /dev/null @@ -1,80 +0,0 @@ -# Author: David Sidler (david.sidler@inf.ethz.ch) - -cmake_minimum_required(VERSION 3.0) - -set (PROJECT_NAME send_recv) -project(${PROJECT_NAME}) - -# Include custom Find.cmake scripts to enable searching for Vivado & Vitis HLS -set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/../../cmake) - -# Without this variable set, CMake will build tests when running install -#set(CMAKE_SKIP_INSTALL_ALL_DEPENDENCY ON) - -# Generate Doxygen if available -#find_package(Doxygen) -#if(Doxygen_FOUND) -# configure_file(${CMAKE_SOURCE_DIR}/Doxyfile.in Doxyfile) -# add_custom_target(doxygen ALL -# COMMAND ${DOXYGEN_EXECUTABLE} Doxyfile -# WORKING_DIRECTORY ${CMAKE_BINARY_DIR}) -#endif() - -if (NOT hasParent) - if (DEVICE_NAME STREQUAL "u280") - set(FPGA_PART xcu280-fsvh2892-2L-e) - set(FPGA_FAMILY ultraplus) - set(NETWORK_BANDWIDTH 100 CACHE STRING "Network bandwidth") - endif() -endif() -set(DATA_WIDTH 64 CACHE STRING "Width of data path in bytes") -set(CLOCK_PERIOD 3.2 CACHE STRING "Target clock period in nanoseconds") - - -# Find Xilinx Vitis HLS -find_package(VitisHLS REQUIRED) -if (NOT VITIS_HLS_FOUND) - message(FATAL_ERROR "Vitis HLS not found.") -endif() - - -include_directories(${CMAKE_CURRENT_BINARY_DIR}) - -configure_file(${CMAKE_CURRENT_SOURCE_DIR}/send_recv_config.hpp.in send_recv_config.hpp) -configure_file(${CMAKE_CURRENT_SOURCE_DIR}/make.tcl.in make.tcl) - - -set(EXAMPLE_HLS_DEPENDS - ${CMAKE_CURRENT_SOURCE_DIR}/send_recv.cpp - ${CMAKE_CURRENT_SOURCE_DIR}/send_recv.hpp - ${CMAKE_CURRENT_SOURCE_DIR}/send_recv_config.hpp.in - ${CMAKE_CURRENT_SOURCE_DIR}/test_send_recv.cpp) - - -#Setup HLS custom targets -set(HLS_TARGETS synthesis csim ip services) - -foreach (target ${HLS_TARGETS}) - if (NOT TARGET ${target}) - add_custom_target(${target}) - endif() - - add_custom_target(${target}.${PROJECT_NAME} - COMMAND ${VITIS_HLS_BINARY} -f make.tcl -tclargs ${target} - DEPENDS ${EXAMPLE_HLS_DEPENDS}) - add_dependencies(${target} ${target}.${PROJECT_NAME}) -endforeach() - -#target dependencies -add_dependencies(ip.${PROJECT_NAME} synthesis.${PROJECT_NAME}) -add_dependencies(services.${PROJECT_NAME} ip.${PROJECT_NAME}) - -# Installation -if (DEFINED ENV{IPREPO_DIR}) - set(IPREPO_DIR $ENV{IPREPO_DIR}) -elseif(NOT IPREPO_DIR) - set(IPREPO_DIR ${CMAKE_CURRENT_SOURCE_DIR}/iprepo/) -endif() -#install(DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}_prj/solution1/impl/ip/ -# DESTINATION ${IPREPO_DIR}/${PROJECT_NAME}/) - diff --git a/examples_hw/apps/tcp_iperf/hls/axi_utils.cpp b/examples_hw/apps/tcp_iperf/hls/axi_utils.cpp deleted file mode 100644 index c0699fdf0..000000000 --- a/examples_hw/apps/tcp_iperf/hls/axi_utils.cpp +++ /dev/null @@ -1,311 +0,0 @@ -/* - * Copyright (c) 2019, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "axi_utils.hpp" - -ap_uint<64> lenToKeep(ap_uint<6> length) -{ - switch (length) - { - case 1: - return 0x01; - case 2: - return 0x03; - case 3: - return 0x07; - case 4: - return 0x0F; - case 5: - return 0x1F; - case 6: - return 0x3F; - case 7: - return 0x7F; - case 8: - return 0xFF; - case 9: - return 0x01FF; - case 10: - return 0x03FF; - case 11: - return 0x07FF; - case 12: - return 0x0FFF; - case 13: - return 0x1FFF; - case 14: - return 0x3FFF; - case 15: - return 0x7FFF; - case 16: - return 0xFFFF; - case 17: - return 0x01FFFF; - case 18: - return 0x03FFFF; - case 19: - return 0x07FFFF; - case 20: - return 0x0FFFFF; - case 21: - return 0x1FFFFF; - case 22: - return 0x3FFFFF; - case 23: - return 0x7FFFFF; - case 24: - return 0xFFFFFF; - case 25: - return 0x01FFFFFF; - case 26: - return 0x03FFFFFF; - case 27: - return 0x07FFFFFF; - case 28: - return 0x0FFFFFFF; - case 29: - return 0x1FFFFFFF; - case 30: - return 0x3FFFFFFF; - case 31: - return 0x7FFFFFFF; - case 32: - return 0xFFFFFFFF; - case 33: - return 0x01FFFFFFFF; - case 34: - return 0x03FFFFFFFF; - case 35: - return 0x07FFFFFFFF; - case 36: - return 0x0FFFFFFFFF; - case 37: - return 0x1FFFFFFFFF; - case 38: - return 0x3FFFFFFFFF; - case 39: - return 0x7FFFFFFFFF; - case 40: - return 0xFFFFFFFFFF; - case 41: - return 0x01FFFFFFFFFF; - case 42: - return 0x03FFFFFFFFFF; - case 43: - return 0x07FFFFFFFFFF; - case 44: - return 0x0FFFFFFFFFFF; - case 45: - return 0x1FFFFFFFFFFF; - case 46: - return 0x3FFFFFFFFFFF; - case 47: - return 0x7FFFFFFFFFFF; - case 48: - return 0xFFFFFFFFFFFF; - case 49: - return 0x01FFFFFFFFFFFF; - case 50: - return 0x03FFFFFFFFFFFF; - case 51: - return 0x07FFFFFFFFFFFF; - case 52: - return 0x0FFFFFFFFFFFFF; - case 53: - return 0x1FFFFFFFFFFFFF; - case 54: - return 0x3FFFFFFFFFFFFF; - case 55: - return 0x7FFFFFFFFFFFFF; - case 56: - return 0xFFFFFFFFFFFFFF; - case 57: - return 0x01FFFFFFFFFFFFFF; - case 58: - return 0x03FFFFFFFFFFFFFF; - case 59: - return 0x07FFFFFFFFFFFFFF; - case 60: - return 0x0FFFFFFFFFFFFFFF; - case 61: - return 0x1FFFFFFFFFFFFFFF; - case 62: - return 0x3FFFFFFFFFFFFFFF; - case 63: - return 0x7FFFFFFFFFFFFFFF; - default: - return 0xFFFFFFFFFFFFFFFF; - }//switch -} - -//Input argument cannot be templatized, otherwise the case statement leads to duplicate definitions -ap_uint<8> keepToLen(ap_uint<64> keepValue) -{ -#pragma HLS INLINE - - switch (keepValue) - { - case 0x01: - return 0x1; - case 0x3: - return 0x2; - case 0x07: - return 0x3; - case 0x0F: - return 0x4; - case 0x1F: - return 0x5; - case 0x3F: - return 0x6; - case 0x7F: - return 0x7; - case 0xFF: - return 0x8; -//#if W > 64 - case 0x01FF: - return 0x9; - case 0x3FF: - return 0xA; - case 0x07FF: - return 0xB; - case 0x0FFF: - return 0xC; - case 0x1FFF: - return 0xD; - case 0x3FFF: - return 0xE; - case 0x7FFF: - return 0xF; - case 0xFFFF: - return 0x10; -//#if W > 128 - case 0x01FFFF: - return 0x11; - case 0x3FFFF: - return 0x12; - case 0x07FFFF: - return 0x13; - case 0x0FFFFF: - return 0x14; - case 0x1FFFFF: - return 0x15; - case 0x3FFFFF: - return 0x16; - case 0x7FFFFF: - return 0x17; - case 0xFFFFFF: - return 0x18; - case 0x01FFFFFF: - return 0x19; - case 0x3FFFFFF: - return 0x1A; - case 0x07FFFFFF: - return 0x1B; - case 0x0FFFFFFF: - return 0x1C; - case 0x1FFFFFFF: - return 0x1D; - case 0x3FFFFFFF: - return 0x1E; - case 0x7FFFFFFF: - return 0x1F; - case 0xFFFFFFFF: - return 0x20; -//#if W > 256 - case 0x01FFFFFFFF: - return 0x21; - case 0x3FFFFFFFF: - return 0x22; - case 0x07FFFFFFFF: - return 0x23; - case 0x0FFFFFFFFF: - return 0x24; - case 0x1FFFFFFFFF: - return 0x25; - case 0x3FFFFFFFFF: - return 0x26; - case 0x7FFFFFFFFF: - return 0x27; - case 0xFFFFFFFFFF: - return 0x28; - case 0x01FFFFFFFFFF: - return 0x29; - case 0x3FFFFFFFFFF: - return 0x2A; - case 0x07FFFFFFFFFF: - return 0x2B; - case 0x0FFFFFFFFFFF: - return 0x2C; - case 0x1FFFFFFFFFFF: - return 0x2D; - case 0x3FFFFFFFFFFF: - return 0x2E; - case 0x7FFFFFFFFFFF: - return 0x2F; - case 0xFFFFFFFFFFFF: - return 0x30; - - case 0x01FFFFFFFFFFFF: - return 0x31; - case 0x3FFFFFFFFFFFF: - return 0x32; - case 0x07FFFFFFFFFFFF: - return 0x33; - case 0x0FFFFFFFFFFFFF: - return 0x34; - case 0x1FFFFFFFFFFFFF: - return 0x35; - case 0x3FFFFFFFFFFFFF: - return 0x36; - case 0x7FFFFFFFFFFFFF: - return 0x37; - case 0xFFFFFFFFFFFFFF: - return 0x38; - case 0x01FFFFFFFFFFFFFF: - return 0x39; - case 0x3FFFFFFFFFFFFFF: - return 0x3A; - case 0x07FFFFFFFFFFFFFF: - return 0x3B; - case 0x0FFFFFFFFFFFFFFF: - return 0x3C; - case 0x1FFFFFFFFFFFFFFF: - return 0x3D; - case 0x3FFFFFFFFFFFFFFF: - return 0x3E; - case 0x7FFFFFFFFFFFFFFF: - return 0x3F; - case 0xFFFFFFFFFFFFFFFF: - return 0x40; - default: - return 0xFF; -//#endif -//#endif -//#endif - } -} - - diff --git a/examples_hw/apps/tcp_iperf/hls/axi_utils.hpp b/examples_hw/apps/tcp_iperf/hls/axi_utils.hpp deleted file mode 100644 index c09965bc9..000000000 --- a/examples_hw/apps/tcp_iperf/hls/axi_utils.hpp +++ /dev/null @@ -1,1393 +0,0 @@ -/* - * Copyright (c) 2019, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#pragma once - -#include -#include "ap_int.h" -#include -#include -#include -#include -#if defined( __VITIS_HLS__) -#include "ap_axi_sdata.h" -#endif - -//Adaptation of ap_axiu<> - -/*template -struct axis -{ - ap_uint data; - ap_uint keep; - ap_uint<1> last; - axis() {} - axis(ap_uint data, ap_uint keep, ap_uint<1> last) - :data(data), keep(keep), last(last) {} -};*/ - -template -struct net_axis -{ - ap_uint data; - ap_uint keep; - ap_uint<1> last; - net_axis() {} - net_axis(ap_uint data, ap_uint keep, ap_uint<1> last) - :data(data), keep(keep), last(last) {} -}; - -#if defined( __VITIS_HLS__) -template -void convert_net_axis_to_axis(hls::stream >& input, - hls::stream >& output) -{ -#pragma HLS pipeline II=1 - - net_axis inputWord; - ap_axiu outputWord; - - if (!input.empty()) - { - inputWord = input.read(); - outputWord.data = inputWord.data; - outputWord.keep = inputWord.keep; - outputWord.last = inputWord.last; - output.write(outputWord); - } -} - - -template -void convert_axis_to_net_axis(hls::stream >& input, - hls::stream >& output) -{ -#pragma HLS pipeline II=1 - - ap_axiu inputWord; - net_axis outputWord; - - if (!input.empty()) - { - inputWord = input.read(); - outputWord.data = inputWord.data; - outputWord.keep = inputWord.keep; - outputWord.last = inputWord.last; - output.write(outputWord); - } -} -#endif -template -ap_uint reverse(const ap_uint& w) -{ - ap_uint temp; - for (int i = 0; i < D/8; i++) - { - #pragma HLS UNROLL - temp(i*8+7, i*8) = w(D-(i*8)-1, D-(i*8)-8); - } - return temp; -} - -template -ap_uint reverse_bits(const ap_uint& w) -{ - ap_uint temp; - for (int i = 0; i < D; i++) - { - #pragma HLS UNROLL - temp[i] = w[D-i-1]; - } - return temp; -} - -template -bool scan(std::istream& inputFile, ap_uint& data) -{ - uint16_t temp; - for (int i = 0; i < D/8; i++) - { - if (inputFile >> std::hex >> temp) - { - data(i*8+7, i*8) = temp; - } - else - { - //std::cerr << "[ERROR]: could not scan input" << std::endl; - return false; - } - } - return (bool) inputFile; -} - -template -bool scan(std::istream& inputFile, net_axis& word) -{ - uint16_t temp; - uint32_t keepTemp; - uint16_t lastTemp; - for (int i = 0; i < D/8; i++) - { - if (inputFile >> std::hex >> temp) - { - word.data(i*8+7, i*8) = temp; - } - else - { - //std::cerr << "[ERROR]: could not scan input" << std::endl; - return false; - } - } - inputFile >> keepTemp; - inputFile >> lastTemp; - word.keep = keepTemp; - word.last = lastTemp; - //if (!inputFile) - // std::cerr << "[ERROR]: could not scan input" << std::endl; - return (bool) inputFile; -} - -template -bool scanLE(std::istream& inputFile, ap_uint& data) -{ - uint16_t temp; - for (int i = (D/8)-1; i >= 0; i--) - { - if (inputFile >> std::hex >> temp) - { - data(i*8+7, i*8) = temp; - } - else - { - //std::cerr << "[ERROR]: could not scan input" << std::endl; - return false; - } - } - return (bool) inputFile; -} - -template -bool scanLE(std::istream& inputFile, net_axis& word) -{ - uint16_t temp; - uint32_t keepTemp; - uint16_t lastTemp; - for (int i = (D/8)-1; i >= 0; i--) - { - if (inputFile >> std::hex >> temp) - { - word.data(i*8+7, i*8) = temp; - } - else - { - //std::cerr << "[ERROR]: could not scan input" << std::endl; - return false; - } - } - inputFile >> keepTemp; - inputFile >> lastTemp; - word.keep = keepTemp; - word.last = lastTemp; - return (bool) inputFile; -} - -template -void print(std::ostream& output, ap_uint data) -{ - output << std::hex; - output << std::setfill('0'); - for (int i = 0; i < D/8; i++) - { - output << std::noshowbase << std::setw(2) << (uint16_t) data(i*8+7, i*8) << " "; - } -} - -template -void print(std::ostream& output, net_axis& word) -{ -#ifndef __SYNTHESIS__ - output << std::hex; - output << std::setfill('0'); - for (int i = 0; i < D/8; i++) - { - output << std::noshowbase << std::setw(2) << (uint16_t) word.data(i*8+7, i*8) << " "; - } - output << std::setw(D/8/4) << (uint64_t) word.keep << " "; - output << std::setw(1) << (uint16_t)word.last; -#endif -} - -template -void printLE(std::ostream& output, ap_uint& data) -{ -#ifndef __SYNTHESIS__ - output << std::hex; - output << std::setfill('0') ; - for (int i = (D/8)-1; i >= 0; i--) - { - output << std::noshowbase << std::setw(2) << (uint16_t) data(i*8+7, i*8) << " "; - } -#endif -} - -template -void printLE(std::ostream& output, net_axis& word) -{ -#ifndef __SYNTHESIS__ - output << std::hex; - output << std::setfill('0') ; - for (int i = (D/8)-1; i >= 0; i--) - { - output << std::noshowbase << std::setw(2) << (uint16_t) word.data(i*8+7, i*8) << " "; - } - output << std::setw(D/8/4) << (uint64_t) word.keep << " "; - output << std::setw(1) << (uint16_t)word.last; -#endif -} - -template -void increaseStreamWidth(hls::stream >& input, hls::stream >&output) -{ -#pragma HLS INLINE - - static int count = 0; - - static net_axis temp; - - if (!input.empty()) - { - net_axis currWord = input.read(); - temp.data((W*count)+W-1, (W*count)) = currWord.data; - temp.keep(((W/8)*count+(W/8)-1), ((W/8)*count)) = currWord.keep; - temp.last = currWord.last; - - count++; - if (currWord.last || count == D) - { - output.write(temp); - count = 0; -#ifndef __SYNTHESIS__ - temp.data = 0; -#endif - temp.keep = 0; - } - } - -} - -template -void reduceStreamWidth(hls::stream >& input, hls::stream >&output) -{ -#pragma HLS INLINE - - enum fsmStateType {FIRST, SECOND}; - static fsmStateType fsmState = FIRST; - static int count = 0; - - static net_axis currWord; - net_axis temp; - - switch (fsmState) - { - case FIRST: - if (!input.empty()) - { - input.read(currWord); - temp.data = currWord.data((W/D)-1, 0); - temp.keep = currWord.keep(((W/D)/8)-1, 0); - temp.last = (currWord.keep[(W/8)/D] == 0); //(currWord.keep((W/8)-1, (W/8)/2) == 0); - output.write(temp); - - if (currWord.keep[(W/8)/D]) - { - count = 1; - fsmState = SECOND; - } - - //shift word - currWord.data(W-(W/D)-1, 0) = currWord.data(W-1, W/D); - currWord.keep((W/8)-((W/8)/D)-1, 0) = currWord.keep((W/8)-1, (W/8)/D); - currWord.keep((W/8)-1, (W/8)-((W/8)/D)) = 0; - } - break; - case SECOND: - temp.data = currWord.data((W/D)-1, 0); - temp.keep = currWord.keep(((W/D)/8)-1, 0); - if (count < D-1) - { - temp.last = (currWord.keep[(W/8)/D] == 0); //(currWord.keep((W/8)-1, (W/8)/2) == 0); - } - else - { - temp.last = currWord.last; - } - output.write(temp); - //shift word - currWord.data(W-(W/D)-1, 0) = currWord.data(W-1, W/D); - currWord.keep((W/8)-((W/8)/D)-1, 0) = currWord.keep((W/8)-1, (W/8)/D); - currWord.keep((W/8)-1, (W/8)-((W/8)/D)) = 0; - - - count++; - if (count == D || temp.last) - { - - fsmState = FIRST; - } - break; - } -} - -template -void convertStreamWidth(hls::stream >& input, hls::stream >&output) -{ -#pragma HLS PIPELINE II=1 -#pragma HLS INLINE off - - if (!input.empty()) - { - output.write(input.read()); - } -} - -template -void convertStreamWidth(hls::stream >& input, hls::stream >&output) -{ -#pragma HLS PIPELINE II=1 -#pragma HLS INLINE off - - increaseStreamWidth(input, output); -} - -template -void convertStreamWidth(hls::stream >& input, hls::stream >&output) -{ -#pragma HLS PIPELINE II=1 -#pragma HLS INLINE off - - increaseStreamWidth(input, output); -} - -template -void convertStreamWidth(hls::stream >& input, hls::stream >&output) -{ -#pragma HLS PIPELINE II=1 -#pragma HLS INLINE off - - increaseStreamWidth(input, output); -} - -template -void convertStreamWidth(hls::stream >& input, hls::stream >&output) -{ -#pragma HLS PIPELINE II=1 -#pragma HLS INLINE off - - reduceStreamWidth(input, output); -} - -template -void convertStreamWidth(hls::stream >& input, hls::stream >&output) -{ -#pragma HLS PIPELINE II=1 -#pragma HLS INLINE off - - reduceStreamWidth(input, output); -} - -template -void convertStreamWidth(hls::stream >& input, hls::stream >&output) -{ -#pragma HLS PIPELINE II=1 -#pragma HLS INLINE off - - reduceStreamWidth(input, output); -} - -// The 2nd template parameter is a hack to use this function multiple times -template -void rshiftWordByOctet( uint16_t offset, - hls::stream& input, - hls::stream& output) -{ -#pragma HLS inline off -#pragma HLS pipeline II=1 //TODO this has a bug, the bug might come from how it is used - - enum fsmStateType {PKG, REMAINDER}; - static fsmStateType fsmState = PKG; - static bool rs_firstWord = (offset != 0); - static T prevWord; - - T currWord; - T sendWord; - - sendWord.last = 0; - switch (fsmState) - { - case PKG: - if (!input.empty()) - { - input.read(currWord); - - if (!rs_firstWord) - { - if (offset == 0) - { - sendWord = currWord; - } - else - { - sendWord.data((W-1)-(8*offset), 0) = prevWord.data((W-1), 8*offset); - sendWord.data((W-1), W-(8*offset)) = currWord.data((8*offset)-1, 0); - - sendWord.keep((W/8-1)-offset, 0) = prevWord.keep((W/8-1), offset); - sendWord.keep((W/8-1), (W/8)-offset) = currWord.keep(offset-1, 0); - - sendWord.last = (currWord.keep((W/8-1), offset) == 0); - //sendWord.dest = currWord.dest; - //assignDest(sendWord, currWord); - }//else offset - output.write(sendWord); - } - - prevWord = currWord; - rs_firstWord = false; - if (currWord.last) - { - rs_firstWord = (offset != 0); - //rs_writeRemainder = (sendWord.last == 0); - if (!sendWord.last) - { - fsmState = REMAINDER; - } - } - //}//else offset - } - break; - case REMAINDER: - sendWord.data((W-1)-(8*offset), 0) = prevWord.data((W-1), 8*offset); - sendWord.data((W-1), W-(8*offset)) = 0; - sendWord.keep((W/8-1)-offset, 0) = prevWord.keep((W/8-1), offset); - sendWord.keep((W/8-1), (W/8)-offset) = 0; - sendWord.last = 1; - //sendWord.dest = prevWord.dest; - //assignDest(sendWord, currWord); - - output.write(sendWord); - fsmState = PKG; - break; - } -} - -// The 2nd template parameter is a hack to use this function multiple times -template -void lshiftWordByOctet( uint16_t offset, - hls::stream >& input, - hls::stream >& output) -{ -#pragma HLS inline off -#pragma HLS pipeline II=1 - static bool ls_firstWord = true; - static bool ls_writeRemainder = false; - static net_axis prevWord; - - net_axis currWord; - net_axis sendWord; - - //TODO use states - if (ls_writeRemainder) - { - sendWord.data((8*offset)-1, 0) = prevWord.data((W-1), W-(8*offset)); - sendWord.data((W-1), (8*offset)) = 0; - sendWord.keep(offset-1, 0) = prevWord.keep((W/8-1), (W/8)-offset); - sendWord.keep((W/8-1), offset) = 0; - sendWord.last = 1; - - output.write(sendWord); - ls_writeRemainder = false; - } - else if (!input.empty()) - { - input.read(currWord); - - if (offset == 0) - { - output.write(currWord); - } - else - { - - if (ls_firstWord) - { - sendWord.data((8*offset)-1, 0) = 0; - sendWord.data((W-1), (8*offset)) = currWord.data((W-1)-(8*offset), 0); - sendWord.keep(offset-1, 0) = 0xFFFFFFFF; - sendWord.keep((W/8-1), offset) = currWord.keep((W/8-1)-offset, 0); - sendWord.last = (currWord.keep((W/8-1), (W/8)-offset) == 0); - } - else - { - sendWord.data((8*offset)-1, 0) = prevWord.data((W-1), W-(8*offset)); - sendWord.data((W-1), (8*offset)) = currWord.data((W-1)-(8*offset), 0); - - sendWord.keep(offset-1, 0) = prevWord.keep((W/8-1), (W/8)-offset); - sendWord.keep((W/8-1), offset) = currWord.keep((W/8-1)-offset, 0); - - sendWord.last = (currWord.keep((W/8-1), (W/8)-offset) == 0); - - } - output.write(sendWord); - - prevWord = currWord; - ls_firstWord = false; - if (currWord.last) - { - ls_firstWord = true; - ls_writeRemainder = !sendWord.last; - } - } //else offset - } - -} - -//TODO move to utils -template -void stream_merger(hls::stream& in1, hls::stream& in2, hls::stream& out) -{ -#pragma HLS PIPELINE II=1 -#pragma HLS inline off - - if (!in1.empty()) - { - out.write(in1.read()); - } - else if (!in2.empty()) - { - out.write(in2.read()); - } -} - -template -void stream_merger( hls::stream >& originIn, - hls::stream& input0, - hls::stream& input1, - hls::stream& output) -{ -#pragma HLS PIPELINE II=1 -#pragma HLS INLINE off - - enum stateType {IDLE, FWD0, FWD1}; - static stateType state = IDLE; - T word; - ap_uint<1> origin; - - switch (state) - { - case IDLE: - if (!originIn.empty()) - { - originIn.read(origin); - if (origin == 0) - { - if (!input0.empty()) - { - input0.read(word); - output.write(word); - } - else - { - state = FWD0; - } - } - else - { - if (!input1.empty()) - { - input1.read(word); - output.write(word); - } - else - { - state = FWD1; - } - } - } - break; - case FWD0: - if (!input0.empty()) - { - input0.read(word); - output.write(word); - state = IDLE; - } - break; - case FWD1: - if (!input1.empty()) - { - input1.read(word); - output.write(word); - state = IDLE; - } - break; - }//switch -} - -template -void fair_merger(hls::stream& in0, hls::stream& in1, hls::stream& out) -{ -#pragma HLS PIPELINE II=1 -#pragma HLS INLINE off - - static bool merge_pref = true; - - if (merge_pref) - { - if (!in0.empty()) - { - out.write(in0.read()); - merge_pref = false; - } - else if(!in1.empty()) - { - out.write(in1.read()); - } - } - else - { - if(!in1.empty()) - { - out.write(in1.read()); - merge_pref = true; - } - else if (!in0.empty()) - { - out.write(in0.read()); - } - } -} - -template -void fair_pkg_merger(hls::stream >& in0, hls::stream >& in1, hls::stream >& out) -{ -#pragma HLS PIPELINE II=1 -#pragma HLS INLINE off - - enum fpmStateType{IDLE, FWD0, FWD1}; - static fpmStateType state = IDLE; - static bool merge_pref = true; - net_axis currWord; - - currWord.last = 0; - switch (state) - { - case IDLE: - if (merge_pref) - { - if (!in0.empty()) - { - in0.read(currWord); - out.write(currWord); - state = FWD1; - - } - else if(!in1.empty()) - { - in1.read(currWord); - out.write(currWord); - state = FWD1; - } - } - else - { - if(!in1.empty()) - { - in1.read(currWord); - out.write(currWord); - state = FWD1; - - } - else if (!in0.empty()) - { - in0.read(currWord); - out.write(currWord); - state = FWD0; - } - } - if (currWord.last) - { - state = IDLE; - } - break; - case FWD0: - if (!in0.empty()) - { - in0.read(currWord); - out.write(currWord); - if (currWord.last) - { - merge_pref = false; - state = IDLE; - } - } - break; - case FWD1: - if (!in1.empty()) - { - in1.read(currWord); - out.write(currWord); - if (currWord.last) - { - merge_pref = true; - state = IDLE; - } - } - break; - }//switch -} - -template -void stream_pkg_merger( hls::stream >& originIn, - hls::stream >& input0, - hls::stream >& input1, - hls::stream >& output) -{ -#pragma HLS PIPELINE II=1 -#pragma HLS INLINE off - - enum stateType {IDLE, FWD0, FWD1}; - static stateType state = IDLE; - net_axis currWord; - ap_uint<1> origin; - - switch (state) - { - case IDLE: - if (!originIn.empty()) - { - originIn.read(origin); - if (origin == 0) - { - if (!input0.empty()) - { - input0.read(currWord); - output.write(currWord); - if (!currWord.last) - { - state = FWD0; - } - } - else - { - state = FWD0; - } - } - else - { - if (!input1.empty()) - { - input1.read(currWord); - output.write(currWord); - if (!currWord.last) - { - state = FWD1; - } - } - else - { - state = FWD1; - } - } - } - break; - case FWD0: - if (!input0.empty()) - { - input0.read(currWord); - output.write(currWord); - if (currWord.last) - { - state = IDLE; - } - } - break; - case FWD1: - if (!input1.empty()) - { - input1.read(currWord); - output.write(currWord); - if (currWord.last) - { - state = IDLE; - } - } - break; - }//switch -} - -template -void stream_pkg_splitter( hls::stream >& destIn, - hls::stream >& input, - hls::stream >& output0, - hls::stream >& output1) -{ -#pragma HLS PIPELINE II=1 -#pragma HLS INLINE off - - enum stateType {IDLE, FWD0, FWD1}; - static stateType state = IDLE; - net_axis currWord; - ap_uint<1> dest; - - switch (state) - { - case IDLE: - if (!destIn.empty()) - { - destIn.read(dest); - state = (dest == 0) ? FWD0 : FWD1; - if (!input.empty()) - { - input.read(currWord); - if (dest == 0) - { - output0.write(currWord); - } - else - { - output1.write(currWord); - - } - if (currWord.last) - { - state = IDLE; - } - } - } - break; - case FWD0: - if (!input.empty()) - { - input.read(currWord); - output0.write(currWord); - if (currWord.last) - { - state = IDLE; - } - } - break; - case FWD1: - if (!input.empty()) - { - input.read(currWord); - output1.write(currWord); - if (currWord.last) - { - state = IDLE; - } - } - break; - }//switch -} - - -template -void pass_valid_pkg(hls::stream& pkgValidIn, - hls::stream >& input, - hls::stream >& output) -{ - #pragma HLS PIPELINE II=1 - #pragma HLS INLINE off - - enum fsmStateType {VALID, FWD, DROP}; - static fsmStateType state = VALID; - - switch (state) - { - case VALID: - if (!pkgValidIn.empty() && !input.empty()) - { - bool valid = pkgValidIn.read(); - net_axis word = input.read(); - - if (valid) - { - output.write(word); - if (!word.last) - { - state = FWD; - } - } - else - { - if (!word.last) - { - state = DROP; - } - } - - } - break; - case FWD: - if (!input.empty()) - { - net_axis word = input.read(); - output.write(word); - if (word.last) - { - state = VALID; - } - } - break; - case DROP: - if (!input.empty()) - { - net_axis word = input.read(); - if (word.last) - { - state = VALID; - } - } - break; - } //switch -} - - -template -void toe_duplicate_stream( hls::stream& in, - hls::stream& out0, - hls::stream& out1) -{ - #pragma HLS PIPELINE II=1 - #pragma HLS INLINE off - - if (!in.empty()) - { - T item = in.read(); - out0.write(item); - out1.write(item); - } -} - -template -void ip_handler_duplicate_stream( hls::stream& in, - hls::stream& out0, - hls::stream& out1) -{ - #pragma HLS PIPELINE II=1 - #pragma HLS INLINE off - - if (!in.empty()) - { - T item = in.read(); - out0.write(item); - out1.write(item); - } -} - - -ap_uint<64> lenToKeep(ap_uint<6> length); -ap_uint<8> keepToLen(ap_uint<64> keepValue); - -template -net_axis alignWords(ap_uint<6> offset, net_axis prevWord, net_axis currWord) -{ - - net_axis alignedWord; - - alignedWord.data(WIDTH-1, WIDTH - (offset*8)) = currWord.data(offset*8-1, 0); - alignedWord.keep(WIDTH/8-1, WIDTH/8 - offset) = currWord.keep(offset - 1, 0); - alignedWord.data(WIDTH - (offset*8) -1, 0) = prevWord.data(WIDTH-1, offset*8); - alignedWord.keep(WIDTH/8 - offset - 1, 0) = prevWord.keep(WIDTH/8-1, offset); - //alignedWord.last = (currWord.keep[offset] == 0); - - return alignedWord; -} - - -// SOLUTION NEEDED -------------------------------------------------------------------------------------------------------------------------------------------------- - -// The 2nd template parameter is a hack to use this function multiple times -template -void udp_lshiftWordByOctet( uint16_t offset, - hls::stream >& input, - hls::stream >& output) -{ -#pragma HLS inline off -#pragma HLS pipeline II=1 - static bool ls_firstWord = true; - static bool ls_writeRemainder = false; - static net_axis prevWord; - - net_axis currWord; - net_axis sendWord; - - //TODO use states - if (ls_writeRemainder) - { - sendWord.data((8*offset)-1, 0) = prevWord.data((W-1), W-(8*offset)); - sendWord.data((W-1), (8*offset)) = 0; - sendWord.keep(offset-1, 0) = prevWord.keep((W/8-1), (W/8)-offset); - sendWord.keep((W/8-1), offset) = 0; - sendWord.last = 1; - - output.write(sendWord); - ls_writeRemainder = false; - } - else if (!input.empty()) - { - input.read(currWord); - - if (offset == 0) - { - output.write(currWord); - } - else - { - - if (ls_firstWord) - { - sendWord.data((8*offset)-1, 0) = 0; - sendWord.data((W-1), (8*offset)) = currWord.data((W-1)-(8*offset), 0); - sendWord.keep(offset-1, 0) = 0xFFFFFFFF; - sendWord.keep((W/8-1), offset) = currWord.keep((W/8-1)-offset, 0); - sendWord.last = (currWord.keep((W/8-1), (W/8)-offset) == 0); - } - else - { - sendWord.data((8*offset)-1, 0) = prevWord.data((W-1), W-(8*offset)); - sendWord.data((W-1), (8*offset)) = currWord.data((W-1)-(8*offset), 0); - - sendWord.keep(offset-1, 0) = prevWord.keep((W/8-1), (W/8)-offset); - sendWord.keep((W/8-1), offset) = currWord.keep((W/8-1)-offset, 0); - - sendWord.last = (currWord.keep((W/8-1), (W/8)-offset) == 0); - - } - output.write(sendWord); - - prevWord = currWord; - ls_firstWord = false; - if (currWord.last) - { - ls_firstWord = true; - ls_writeRemainder = !sendWord.last; - } - } //else offset - } - -} - -// The 2nd template parameter is a hack to use this function multiple times -template -void mac_lshiftWordByOctet( uint16_t offset, - hls::stream >& input, - hls::stream >& output) -{ -#pragma HLS inline off -#pragma HLS pipeline II=1 - static bool ls_firstWord = true; - static bool ls_writeRemainder = false; - static net_axis prevWord; - - net_axis currWord; - net_axis sendWord; - - //TODO use states - if (ls_writeRemainder) - { - sendWord.data((8*offset)-1, 0) = prevWord.data((W-1), W-(8*offset)); - sendWord.data((W-1), (8*offset)) = 0; - sendWord.keep(offset-1, 0) = prevWord.keep((W/8-1), (W/8)-offset); - sendWord.keep((W/8-1), offset) = 0; - sendWord.last = 1; - - output.write(sendWord); - ls_writeRemainder = false; - } - else if (!input.empty()) - { - input.read(currWord); - - if (offset == 0) - { - output.write(currWord); - } - else - { - - if (ls_firstWord) - { - sendWord.data((8*offset)-1, 0) = 0; - sendWord.data((W-1), (8*offset)) = currWord.data((W-1)-(8*offset), 0); - sendWord.keep(offset-1, 0) = 0xFFFFFFFF; - sendWord.keep((W/8-1), offset) = currWord.keep((W/8-1)-offset, 0); - sendWord.last = (currWord.keep((W/8-1), (W/8)-offset) == 0); - } - else - { - sendWord.data((8*offset)-1, 0) = prevWord.data((W-1), W-(8*offset)); - sendWord.data((W-1), (8*offset)) = currWord.data((W-1)-(8*offset), 0); - - sendWord.keep(offset-1, 0) = prevWord.keep((W/8-1), (W/8)-offset); - sendWord.keep((W/8-1), offset) = currWord.keep((W/8-1)-offset, 0); - - sendWord.last = (currWord.keep((W/8-1), (W/8)-offset) == 0); - - } - output.write(sendWord); - - prevWord = currWord; - ls_firstWord = false; - if (currWord.last) - { - ls_firstWord = true; - ls_writeRemainder = !sendWord.last; - } - } //else offset - } - -} - -// The 2nd template parameter is a hack to use this function multiple times -template -void ipv4_lshiftWordByOctet( uint16_t offset, - hls::stream >& input, - hls::stream >& output) -{ -#pragma HLS inline off -#pragma HLS pipeline II=1 - static bool ls_firstWord = true; - static bool ls_writeRemainder = false; - static net_axis prevWord; - - net_axis currWord; - net_axis sendWord; - - //TODO use states - if (ls_writeRemainder) - { - sendWord.data((8*offset)-1, 0) = prevWord.data((W-1), W-(8*offset)); - sendWord.data((W-1), (8*offset)) = 0; - sendWord.keep(offset-1, 0) = prevWord.keep((W/8-1), (W/8)-offset); - sendWord.keep((W/8-1), offset) = 0; - sendWord.last = 1; - - output.write(sendWord); - ls_writeRemainder = false; - } - else if (!input.empty()) - { - input.read(currWord); - - if (offset == 0) - { - output.write(currWord); - } - else - { - - if (ls_firstWord) - { - sendWord.data((8*offset)-1, 0) = 0; - sendWord.data((W-1), (8*offset)) = currWord.data((W-1)-(8*offset), 0); - sendWord.keep(offset-1, 0) = 0xFFFFFFFF; - sendWord.keep((W/8-1), offset) = currWord.keep((W/8-1)-offset, 0); - sendWord.last = (currWord.keep((W/8-1), (W/8)-offset) == 0); - } - else - { - sendWord.data((8*offset)-1, 0) = prevWord.data((W-1), W-(8*offset)); - sendWord.data((W-1), (8*offset)) = currWord.data((W-1)-(8*offset), 0); - - sendWord.keep(offset-1, 0) = prevWord.keep((W/8-1), (W/8)-offset); - sendWord.keep((W/8-1), offset) = currWord.keep((W/8-1)-offset, 0); - - sendWord.last = (currWord.keep((W/8-1), (W/8)-offset) == 0); - - } - output.write(sendWord); - - prevWord = currWord; - ls_firstWord = false; - if (currWord.last) - { - ls_firstWord = true; - ls_writeRemainder = !sendWord.last; - } - } //else offset - } - -} - -// The 2nd template parameter is a hack to use this function multiple times -template -void ip_handler_rshiftWordByOctet( uint16_t offset, - hls::stream& input, - hls::stream& output) -{ -#pragma HLS inline off -#pragma HLS pipeline II=1 //TODO this has a bug, the bug might come from how it is used - - enum fsmStateType {PKG, REMAINDER}; - static fsmStateType fsmState = PKG; - static bool rs_firstWord = (offset != 0); - static T prevWord; - - T currWord; - T sendWord; - - sendWord.last = 0; - switch (fsmState) - { - case PKG: - if (!input.empty()) - { - input.read(currWord); - - if (!rs_firstWord) - { - if (offset == 0) - { - sendWord = currWord; - } - else - { - sendWord.data((W-1)-(8*offset), 0) = prevWord.data((W-1), 8*offset); - sendWord.data((W-1), W-(8*offset)) = currWord.data((8*offset)-1, 0); - - sendWord.keep((W/8-1)-offset, 0) = prevWord.keep((W/8-1), offset); - sendWord.keep((W/8-1), (W/8)-offset) = currWord.keep(offset-1, 0); - - sendWord.last = (currWord.keep((W/8-1), offset) == 0); - //sendWord.dest = currWord.dest; - //assignDest(sendWord, currWord); - }//else offset - output.write(sendWord); - } - - prevWord = currWord; - rs_firstWord = false; - if (currWord.last) - { - rs_firstWord = (offset != 0); - //rs_writeRemainder = (sendWord.last == 0); - if (!sendWord.last) - { - fsmState = REMAINDER; - } - } - //}//else offset - } - break; - case REMAINDER: - sendWord.data((W-1)-(8*offset), 0) = prevWord.data((W-1), 8*offset); - sendWord.data((W-1), W-(8*offset)) = 0; - sendWord.keep((W/8-1)-offset, 0) = prevWord.keep((W/8-1), offset); - sendWord.keep((W/8-1), (W/8)-offset) = 0; - sendWord.last = 1; - //sendWord.dest = prevWord.dest; - //assignDest(sendWord, currWord); - - output.write(sendWord); - fsmState = PKG; - break; - } -} - -// The 2nd template parameter is a hack to use this function multiple times -template -void udp_rshiftWordByOctet( uint16_t offset, - hls::stream& input, - hls::stream& output) -{ -#pragma HLS inline off -#pragma HLS pipeline II=1 //TODO this has a bug, the bug might come from how it is used - - enum fsmStateType {PKG, REMAINDER}; - static fsmStateType fsmState = PKG; - static bool rs_firstWord = (offset != 0); - static T prevWord; - - T currWord; - T sendWord; - - sendWord.last = 0; - switch (fsmState) - { - case PKG: - if (!input.empty()) - { - input.read(currWord); - - if (!rs_firstWord) - { - if (offset == 0) - { - sendWord = currWord; - } - else - { - sendWord.data((W-1)-(8*offset), 0) = prevWord.data((W-1), 8*offset); - sendWord.data((W-1), W-(8*offset)) = currWord.data((8*offset)-1, 0); - - sendWord.keep((W/8-1)-offset, 0) = prevWord.keep((W/8-1), offset); - sendWord.keep((W/8-1), (W/8)-offset) = currWord.keep(offset-1, 0); - - sendWord.last = (currWord.keep((W/8-1), offset) == 0); - //sendWord.dest = currWord.dest; - //assignDest(sendWord, currWord); - }//else offset - output.write(sendWord); - } - - prevWord = currWord; - rs_firstWord = false; - if (currWord.last) - { - rs_firstWord = (offset != 0); - //rs_writeRemainder = (sendWord.last == 0); - if (!sendWord.last) - { - fsmState = REMAINDER; - } - } - //}//else offset - } - break; - case REMAINDER: - sendWord.data((W-1)-(8*offset), 0) = prevWord.data((W-1), 8*offset); - sendWord.data((W-1), W-(8*offset)) = 0; - sendWord.keep((W/8-1)-offset, 0) = prevWord.keep((W/8-1), offset); - sendWord.keep((W/8-1), (W/8)-offset) = 0; - sendWord.last = 1; - //sendWord.dest = prevWord.dest; - //assignDest(sendWord, currWord); - - output.write(sendWord); - fsmState = PKG; - break; - } -} diff --git a/examples_hw/apps/tcp_iperf/hls/make.tcl.in b/examples_hw/apps/tcp_iperf/hls/make.tcl.in deleted file mode 100644 index 2174797db..000000000 --- a/examples_hw/apps/tcp_iperf/hls/make.tcl.in +++ /dev/null @@ -1,34 +0,0 @@ - -open_project ${PROJECT_NAME}_prj - -open_solution "solution1" -set_part ${FPGA_PART} -create_clock -period ${CLOCK_PERIOD} -name default - -set_top ${PROJECT_NAME} - -add_files ${CMAKE_CURRENT_SOURCE_DIR}/send_recv.cpp -cflags "-I${CMAKE_CURRENT_BINARY_DIR}" - - -add_files -tb ${CMAKE_CURRENT_SOURCE_DIR}/test_send_recv.cpp - - -#Check which command -set command [lindex $argv 2] - -if {$command == "synthesis"} { - csynth_design -} elseif {$command == "csim"} { - csim_design -} elseif {$command == "ip"} { - export_design -format ip_catalog -ipname "send_recv" -display_name "send_recv" -vendor "ethz.systems.fpga" -version "1.0" -} elseif {$command == "services"} { - file mkdir ${IPREPO_DIR} - file delete -force ${IPREPO_DIR}/${PROJECT_NAME} - file copy -force ${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}_prj/solution1/impl/ip ${IPREPO_DIR}/${PROJECT_NAME}/ -} else { - puts "No valid command specified. Use vitis_hls -f make.tcl ." -} - - -exit diff --git a/examples_hw/apps/tcp_iperf/hls/packet.hpp b/examples_hw/apps/tcp_iperf/hls/packet.hpp deleted file mode 100644 index fc4fdd11d..000000000 --- a/examples_hw/apps/tcp_iperf/hls/packet.hpp +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright (c) 2019, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef PACKET_HPP -#define PACKET_HPP - -#include "stdint.h" -#include "axi_utils.hpp" - -using namespace hls; - -template -class packetHeader { -public: - bool ready; - uint16_t idx; - ap_uint header; - -public: - packetHeader() - :ready(false), idx(0) {} - packetHeader& operator=(const packetHeader& other) - { - ready = other.ready; - idx = other.idx; - header = other.header; - return *this; - } - - void parseWord(ap_uint& w) - { - if (ready) - return; - - if (idx*W+W < HEADER_SIZE) - { - header(idx*W+W-1, idx*W) = w; - } - else //(idx*W+W >= HEADER_SIZE) - { - header(HEADER_SIZE-1, idx*W) = w; - ready = true; - } - idx++; - /*(header(idx*W+W-1, idx*W) = w; - if (idx*W+W >= HEADER_SIZE) - { - ready = true; - }*/ - } - ap_uint<8> consumeWord(ap_uint& w) - { - if ((idx+1)*W <= HEADER_SIZE) - { - w = header(((idx+1)*W)-1, idx*W); - idx++; - return ((HEADER_SIZE - (idx*W)) / 8); - } - else if (idx*W < HEADER_SIZE) - { - w((HEADER_SIZE%W)-1, 0) = header(HEADER_SIZE-1, idx*W); - idx++; - return 0;//(HEADER_SIZE - (idx*W)); - } - return 0; - } - /*bool consumeWord(ap_uint& w) - { - if ((idx+2)*W <= HEADER_SIZE) - { - w = header(((idx+1)*W)-1, idx*W); - idx++; - return false; - /*if ((idx+1)*W > HEADER_SIZE) - { - return true; - } - else - { - return false; - }*//* - } - else if ((idx+1)*W <= HEADER_SIZE) - { - w = header(((idx+1)*W)-1, idx*W); - idx++; - return true; - } - return true; - }*/ - /*void consumePartialWord(ap_uint& w) - { - if (idx*W < HEADER_SIZE) - { - w((HEADER_SIZE%AXI_WIDTH)-1, 0) = header(HEADER_SIZE-1, idx*W); - idx++; - } - //return true; - } - /*bool consumeWord(ap_uint& w) - { - if ((idx+1)*W <= HEADER_SIZE) - { - w = header(((idx+1)*W)-1, idx*W); - idx++; - return true; - } - return false; - } - bool consumePartialWord(ap_uint& w) - { - if (idx*W < HEADER_SIZE) - { - w((HEADER_SIZE%AXI_WIDTH)-1, 0) = header(HEADER_SIZE-1, idx*W); - idx++; - return true; - } - return false; - }*/ - void setRawHeader(ap_uint h) - { - header = h; - } - ap_uint getRawHeader() - { - return header; - } - bool isReady() - { - return ready; - } - - void clear() - { -//#pragma HLS pipeline II=1 -#pragma HLS INLINE - //header = 0; - ready = false; - idx = 0; - } -}; - -#endif diff --git a/examples_hw/apps/tcp_iperf/hls/send_recv.cpp b/examples_hw/apps/tcp_iperf/hls/send_recv.cpp deleted file mode 100644 index a602131aa..000000000 --- a/examples_hw/apps/tcp_iperf/hls/send_recv.cpp +++ /dev/null @@ -1,470 +0,0 @@ - /************************************************ -Copyright (c) 2019, Systems Group, ETH Zurich. -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, -this list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation -and/or other materials provided with the distribution. - -3. Neither the name of the copyright holder nor the names of its contributors -may be used to endorse or promote products derived from this software -without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -************************************************/ -#include "send_recv_config.hpp" -#include "send_recv.hpp" -#include -#if defined( __VITIS_HLS__) -#include "ap_axi_sdata.h" -#endif - -//Buffers responses coming from the TCP stack -void status_handler(hls::stream& txStatus, - hls::stream& txStatusBuffer) -{ -#pragma HLS PIPELINE II=1 -#pragma HLS INLINE off - - if (!txStatus.empty()) - { - appTxRsp resp = txStatus.read(); - txStatusBuffer.write(resp); - } -} - -//Buffers open status coming from the TCP stack -void openStatus_handler(hls::stream& openConStatus, - hls::stream& openConStatusBuffer) -{ -#pragma HLS PIPELINE II=1 -#pragma HLS INLINE off - - if (!openConStatus.empty()) - { - openStatus resp = openConStatus.read(); - openConStatusBuffer.write(resp); - } -} - - -void txMetaData_handler(hls::stream& txMetaDataBuffer, - hls::stream& txMetaData) -{ -#pragma HLS PIPELINE II=1 -#pragma HLS INLINE off - - if (!txMetaDataBuffer.empty()) - { - appTxMeta metaDataReq = txMetaDataBuffer.read(); - txMetaData.write(metaDataReq); - } -} - -template -void txDataBuffer_handler(hls::stream >& txDataBuffer, - hls::stream >& txData) -{ - #pragma HLS PIPELINE II=1 - #pragma HLS INLINE off - - if (!txDataBuffer.empty()) - { - net_axis word = txDataBuffer.read(); - txData.write(word); - } -} - -template -void client( - hls::stream& txMetaDataBuffer, - hls::stream >& txDataBuffer, - hls::stream& txStatus, - ap_uint<32> pkgWordCount, - ap_uint<32> sessionID, - ap_uint<32> transferSize, - ap_uint<1> runTx - ) -{ -#pragma HLS PIPELINE II=1 -#pragma HLS INLINE off - - enum txHandlerStateType {WAIT_CMD, CHECK_REQ, WRITE_PKG}; - static txHandlerStateType txHandlerState = WAIT_CMD; - - // static ap_uint<32> sessionID; - // static ap_uint<32> transferSize; - // static ap_uint<32> pkgWordCount; - - static ap_uint<16> length; - static ap_uint<16> remaining_space; - static ap_uint<8> error; - static ap_uint<32> currentPkgWord = 0; - static ap_uint<32> wordCnt = 0; - - static ap_uint<32> sentByteCnt = 0; - - - static appTxMeta tx_meta_pkt; - - switch(txHandlerState) - { - case WAIT_CMD: - if (runTx) - { - tx_meta_pkt.sessionID = sessionID; - - if (pkgWordCount*(512/8) > transferSize) - tx_meta_pkt.length = transferSize; - else - tx_meta_pkt.length = pkgWordCount*(512/8); - - txMetaDataBuffer.write(tx_meta_pkt); - - txHandlerState = CHECK_REQ; - } - break; - case CHECK_REQ: - if (!txStatus.empty()) - { - appTxRsp txStatus_pkt = txStatus.read(); - sessionID = txStatus_pkt.sessionID; - length = txStatus_pkt.length; - remaining_space = txStatus_pkt.remaining_space; - error = txStatus_pkt.error; - currentPkgWord = (length + (512/8) -1 ) >> 6; //current packet word length - - //if no error, perpare the tx meta of the next packet - if (error == 0) - { - sentByteCnt = sentByteCnt + length; - - if (sentByteCnt < transferSize) - { - tx_meta_pkt.sessionID = sessionID; - - if (sentByteCnt + pkgWordCount*64 < transferSize ) - { - tx_meta_pkt.length = pkgWordCount*(512/8); - // currentPkgWord = pkgWordCount; - } - else - { - tx_meta_pkt.length = transferSize - sentByteCnt; - // currentPkgWord = (transferSize - sentByteCnt)>>6; - } - - txMetaDataBuffer.write(tx_meta_pkt); - } - txHandlerState = WRITE_PKG; - } - //if error, resend the tx meta of current packet - else - { - //Check if connection was torn down - if (error == 1) - { - // std::cout << "Connection was torn down. " << sessionID << std::endl; - } - else - { - tx_meta_pkt.sessionID = sessionID; - tx_meta_pkt.length = length; - txMetaDataBuffer.write(tx_meta_pkt); - } - } - } - break; - case WRITE_PKG: - wordCnt ++; - net_axis currPkt; - currPkt.data = 0xDEADBEEF; - currPkt.keep = 0xFFFFFFFFFFFFFFFF; - currPkt.last = (wordCnt == currentPkgWord); - txDataBuffer.write(currPkt); - if (wordCnt == currentPkgWord) - { - wordCnt = 0; - if (sentByteCnt >= transferSize) - { - sentByteCnt = 0; - currentPkgWord = 0; - txHandlerState = WAIT_CMD; - } - else - { - txHandlerState = CHECK_REQ; - } - } - break; - } - -} - - -template -void server( hls::stream >& listenPort, - hls::stream& listenPortStatus, - hls::stream& notifications, - hls::stream& readRequest, - hls::stream >& rxMetaData, - hls::stream >& rxData) -{ -#pragma HLS PIPELINE II=1 -#pragma HLS INLINE off - - enum listenFsmStateType {OPEN_PORT, WAIT_PORT_STATUS}; - static listenFsmStateType listenState = OPEN_PORT; - enum consumeFsmStateType {WAIT_PKG, CONSUME}; - static consumeFsmStateType serverFsmState = WAIT_PKG; - #pragma HLS RESET variable=listenState - - switch (listenState) - { - case OPEN_PORT: - // Open Port 5001 - listenPort.write(5001); - listenState = WAIT_PORT_STATUS; - break; - case WAIT_PORT_STATUS: - if (!listenPortStatus.empty()) - { - bool open = listenPortStatus.read(); - if (!open) - { - listenState = OPEN_PORT; - } - } - break; - } - - if (!notifications.empty()) - { - appNotification notification = notifications.read(); - - if (notification.length != 0) - { - readRequest.write(appReadRequest(notification.sessionID, notification.length)); - } - } - - switch (serverFsmState) - { - case WAIT_PKG: - if (!rxMetaData.empty() && !rxData.empty()) - { - rxMetaData.read(); - net_axis receiveWord = rxData.read(); - if (!receiveWord.last) - { - serverFsmState = CONSUME; - } - } - break; - case CONSUME: - if (!rxData.empty()) - { - net_axis receiveWord = rxData.read(); - if (receiveWord.last) - { - serverFsmState = WAIT_PKG; - } - } - break; - } -} - - -#if defined( __VITIS_HLS__) -void send_recv( hls::stream >& listenPort, - hls::stream& listenPortStatus, - hls::stream& notifications, - hls::stream& readRequest, - hls::stream >& rxMetaData, - hls::stream >& rxData, - hls::stream& txMetaData, - hls::stream >& txData, - hls::stream& txStatus, - ap_uint<32> pkgWordCount, - ap_uint<32> sessionID, - ap_uint<32> transferSize, - ap_uint<1> runTx - ) - -{ - #pragma HLS DATAFLOW disable_start_propagation - #pragma HLS INTERFACE ap_ctrl_none port=return - - #pragma HLS INTERFACE axis register port=listenPort name=m_axis_listen_port - #pragma HLS INTERFACE axis register port=listenPortStatus name=s_axis_listen_port_status - - #pragma HLS INTERFACE axis register port=notifications name=s_axis_notifications - #pragma HLS INTERFACE axis register port=readRequest name=m_axis_read_package - #pragma HLS aggregate compact=bit variable=notifications - #pragma HLS aggregate compact=bit variable=readRequest - - #pragma HLS INTERFACE axis register port=rxMetaData name=s_axis_rx_metadata - #pragma HLS INTERFACE axis register port=rxData name=s_axis_rx_data - - #pragma HLS INTERFACE axis register port=txMetaData name=m_axis_tx_metadata - #pragma HLS INTERFACE axis register port=txData name=m_axis_tx_data - #pragma HLS INTERFACE axis register port=txStatus name=s_axis_tx_status - #pragma HLS aggregate compact=bit variable=txMetaData - #pragma HLS aggregate compact=bit variable=txStatus - - #pragma HLS INTERFACE ap_none register port=pkgWordCount - #pragma HLS INTERFACE ap_none register port=sessionID - #pragma HLS INTERFACE ap_none register port=transferSize - #pragma HLS INTERFACE ap_none register port=runTx - - - //This is required to buffer up to 1024 reponses => supporting up to 1024 connections - static hls::stream txStatusBuffer("txStatusBuffer"); - #pragma HLS STREAM variable=txStatusBuffer depth=512 - - //This is required to buffer up to 512 tx_meta_data => supporting up to 512 connections - static hls::stream txMetaDataBuffer("txMetaDataBuffer"); - #pragma HLS STREAM variable=txMetaDataBuffer depth=512 - - //This is required to buffer up to MAX_SESSIONS txData - static hls::stream > txDataBuffer("txDataBuffer"); - #pragma HLS STREAM variable=txDataBuffer depth=512 - - static hls::stream > rxData_internal; - #pragma HLS STREAM depth=2 variable=rxData_internal - - static hls::stream > txData_internal; - #pragma HLS STREAM depth=2 variable=txData_internal - - /* - * Client - */ - status_handler(txStatus, txStatusBuffer); - txMetaData_handler(txMetaDataBuffer, txMetaData); - txDataBuffer_handler(txDataBuffer, txData_internal); - - convert_axis_to_net_axis(rxData, - rxData_internal); - - convert_net_axis_to_axis(txData_internal, - txData); - - client( - txMetaDataBuffer, - txDataBuffer, - txStatusBuffer, - pkgWordCount, - sessionID, - transferSize, - runTx - ); - - /* - * Server - */ - server( listenPort, - listenPortStatus, - notifications, - readRequest, - rxMetaData, - rxData_internal); - -} -#else -void send_recv( hls::stream >& listenPort, - hls::stream& listenPortStatus, - hls::stream& notifications, - hls::stream& readRequest, - hls::stream >& rxMetaData, - hls::stream >& rxData, - hls::stream& txMetaData, - hls::stream >& txData, - hls::stream& txStatus, - ap_uint<32> pkgWordCount, - ap_uint<32> sessionID, - ap_uint<32> transferSize, - ap_uint<1> runTx - ) - -{ - #pragma HLS DATAFLOW disable_start_propagation - #pragma HLS INTERFACE ap_ctrl_none port=return - - #pragma HLS INTERFACE axis register port=listenPort name=m_axis_listen_port - #pragma HLS INTERFACE axis register port=listenPortStatus name=s_axis_listen_port_status - - #pragma HLS INTERFACE axis register port=notifications name=s_axis_notifications - #pragma HLS INTERFACE axis register port=readRequest name=m_axis_read_package - #pragma HLS DATA_PACK variable=notifications - #pragma HLS DATA_PACK variable=readRequest - - #pragma HLS INTERFACE axis register port=rxMetaData name=s_axis_rx_metadata - #pragma HLS INTERFACE axis register port=rxData name=s_axis_rx_data - - #pragma HLS INTERFACE axis register port=txMetaData name=m_axis_tx_metadata - #pragma HLS INTERFACE axis register port=txData name=m_axis_tx_data - #pragma HLS INTERFACE axis register port=txStatus name=s_axis_tx_status - #pragma HLS DATA_PACK variable=txMetaData - #pragma HLS DATA_PACK variable=txStatus - - #pragma HLS INTERFACE ap_none register port=pkgWordCount - #pragma HLS INTERFACE ap_none register port=sessionID - #pragma HLS INTERFACE ap_none register port=transferSize - #pragma HLS INTERFACE ap_none register port=runTx - - - //This is required to buffer up to 1024 reponses => supporting up to 1024 connections - static hls::stream txStatusBuffer("txStatusBuffer"); - #pragma HLS STREAM variable=txStatusBuffer depth=512 - - //This is required to buffer up to 512 tx_meta_data => supporting up to 512 connections - static hls::stream txMetaDataBuffer("txMetaDataBuffer"); - #pragma HLS STREAM variable=txMetaDataBuffer depth=512 - - //This is required to buffer up to MAX_SESSIONS txData - static hls::stream > txDataBuffer("txDataBuffer"); - #pragma HLS STREAM variable=txDataBuffer depth=512 - - /* - * Client - */ - status_handler(txStatus, txStatusBuffer); - txMetaData_handler(txMetaDataBuffer, txMetaData); - txDataBuffer_handler(txDataBuffer, txData); - - client( - txMetaDataBuffer, - txDataBuffer, - txStatusBuffer, - pkgWordCount, - sessionID, - transferSize, - runTx - ); - - /* - * Server - */ - server( listenPort, - listenPortStatus, - notifications, - readRequest, - rxMetaData, - rxData); - -} -#endif \ No newline at end of file diff --git a/examples_hw/apps/tcp_iperf/hls/send_recv.hpp b/examples_hw/apps/tcp_iperf/hls/send_recv.hpp deleted file mode 100644 index 103bdc5c4..000000000 --- a/examples_hw/apps/tcp_iperf/hls/send_recv.hpp +++ /dev/null @@ -1,99 +0,0 @@ -/************************************************ -Copyright (c) 2019, Systems Group, ETH Zurich. -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, -this list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation -and/or other materials provided with the distribution. - -3. Neither the name of the copyright holder nor the names of its contributors -may be used to endorse or promote products derived from this software -without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -************************************************/ -#pragma once - -#include "send_recv_config.hpp" -#include "axi_utils.hpp" -#include "packet.hpp" -#include "toe.hpp" - -#ifndef __SYNTHESIS__ -static const ap_uint<32> END_TIME = 1000; //1000000; -static const ap_uint<40> END_TIME_120 = 1000; - -#else -static const ap_uint<32> END_TIME = 1546546546;//1501501501; -static const ap_uint<40> END_TIME_120 = 18750000000; -#endif - -const uint32_t IPERF_TCP_HEADER_SIZE = 512; - -/** - * iperf TCP Header - */ -template -class iperfTcpHeader : public packetHeader { - using packetHeader::header; - -public: - iperfTcpHeader() - { - header(63, 32) = 0x01000000; - header(79, 64) = 0x0000; - header(127, 96) = 0x00000000; - header(159, 128) = 0; - } - - void setDualMode(bool en) - { - if (en) - { - header(31, 0) = 0x01000080; - } - else - { - header(31, 0) = 0x00000000; - } - } - //This is used for dual tes - void setListenPort(ap_uint<16> port) - { - header(95, 80) = reverse(port); - } - void setSeconds(ap_uint<32> seconds) - { - header(191, 160) = reverse(seconds); - } -}; - - -void send_recv( hls::stream >& listenPort, - hls::stream& listenPortStatus, - hls::stream& notifications, - hls::stream& readRequest, - hls::stream >& rxMetaData, - hls::stream >& rxData, - hls::stream& txMetaData, - hls::stream >& txData, - hls::stream& txStatus, - ap_uint<32> pkgWordCount, - ap_uint<32> sessionID, - ap_uint<32> transferSize, - ap_uint<1> runTx - ); \ No newline at end of file diff --git a/examples_hw/apps/tcp_iperf/hls/send_recv_config.hpp.in b/examples_hw/apps/tcp_iperf/hls/send_recv_config.hpp.in deleted file mode 100644 index e6c018a8f..000000000 --- a/examples_hw/apps/tcp_iperf/hls/send_recv_config.hpp.in +++ /dev/null @@ -1,3 +0,0 @@ -#pragma once - -const unsigned DATA_WIDTH = ${DATA_WIDTH} * 8; diff --git a/examples_hw/apps/tcp_iperf/hls/test_send_recv.cpp b/examples_hw/apps/tcp_iperf/hls/test_send_recv.cpp deleted file mode 100644 index 8f79356fe..000000000 --- a/examples_hw/apps/tcp_iperf/hls/test_send_recv.cpp +++ /dev/null @@ -1,122 +0,0 @@ -/************************************************ -Copyright (c) 2018, Systems Group, ETH Zurich. -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, -this list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation -and/or other materials provided with the distribution. - -3. Neither the name of the copyright holder nor the names of its contributors -may be used to endorse or promote products derived from this software -without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -************************************************/ -#include "send_recv_config.hpp" -#include "send_recv.hpp" -#include - -using namespace hls; - - -int main() -{ - hls::stream > listenPort("listenPort"); - hls::stream listenPortStatus("listenPortStatus"); - hls::stream notifications("notifications"); - hls::stream readRequest("readRequest"); - hls::stream > rxMetaData("rxMetaData"); - hls::stream > rxData("rxData"); - hls::stream openConnection("openConnection"); - hls::stream openConStatus("openConStatus"); - hls::stream > closeConnection("closeConnection"); - hls::stream txMetaData("txMetaData"); - hls::stream > txData("txData"); - hls::stream txStatus("txStatus"); - ap_uint<1> runExperiment; - ap_uint<1> dualModeEn; - ap_uint<13> useConn; - ap_uint<8> pkgWordCount; - ap_uint<8> pkgGap; - ap_uint<32> timeInSeconds; - ap_uint<64> timeInCycles; - ap_uint<16> useIpAddr = 2; - ap_uint<16> regBasePort = 5001; - ap_uint<32> sessionID = 1; - ap_uint<32> transferSize = 2*1024; - - dualModeEn = 0; - pkgWordCount = 16; - pkgGap = 0; - timeInSeconds = 100; - timeInCycles = 1000; - - int count = 0; - while (count < 10000) - { - useConn = 2; - runExperiment = 0; - if (count == 20) - { - runExperiment = 1; - } - send_recv( listenPort, - listenPortStatus, - notifications, - readRequest, - rxMetaData, - rxData, - txMetaData, - txData, - txStatus, - pkgWordCount, - sessionID, - transferSize, - runExperiment - ); - - - if (!listenPort.empty()) - { - ap_uint<16> port = listenPort.read(); - std::cout << "Port " << port << " openend." << std::endl; - listenPortStatus.write(true); - } - - - if (!txMetaData.empty()) - { - appTxMeta meta = txMetaData.read(); - std::cout << "New Pkg: " << std::dec << meta.sessionID << ", length[B]: " << meta.length << std::endl; - // int toss = rand() % 2; - // toss = (toss == 0 || meta.length == IPERF_TCP_HEADER_SIZE/8) ? 0 : -1; - int toss = 0; - std::cout << "toss: " << toss << std::endl; - txStatus.write(appTxRsp(meta.sessionID, meta.length, 0xFFFF, toss)); - } - while (!txData.empty()) - { - net_axis currWord = txData.read(); - printLE(std::cout, currWord); - std::cout << std::endl; - - } - - count++; - } - return 0; -} diff --git a/examples_hw/apps/tcp_iperf/hls/toe.hpp b/examples_hw/apps/tcp_iperf/hls/toe.hpp deleted file mode 100755 index 8e0b732f8..000000000 --- a/examples_hw/apps/tcp_iperf/hls/toe.hpp +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (c) 2019, Systems Group, ETH Zurich - * Copyright (c) 2016, Xilinx, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef TOE_HPP_INCLUDED -#define TOE_HPP_INCLUDED - -#include "./axi_utils.hpp" - -const uint16_t TCP_PROTOCOL = 0x06; - -// Forward declarations. -struct rtlSessionUpdateRequest; -struct rtlSessionUpdateReply; -struct rtlSessionLookupReply; -struct rtlSessionLookupRequest; - -struct ipTuple -{ - ap_uint<32> ip_address; - ap_uint<16> ip_port; -}; - -struct mmCmd -{ - ap_uint<23> bbt; - ap_uint<1> type; - ap_uint<6> dsa; - ap_uint<1> eof; - ap_uint<1> drr; - ap_uint<32> saddr; - ap_uint<4> tag; - ap_uint<4> rsvd; - mmCmd() {} - mmCmd(ap_uint<32> addr, ap_uint<16> len) - :bbt(len), type(1), dsa(0), eof(1), drr(1), saddr(addr), tag(0), rsvd(0) {} - /*mm_cmd(ap_uint<32> addr, ap_uint<16> len, ap_uint<1> last) - :bbt(len), type(1), dsa(0), eof(last), drr(1), saddr(addr), tag(0), rsvd(0) {}*/ - /*mm_cmd(ap_uint<32> addr, ap_uint<16> len, ap_uint<4> dsa) - :bbt(len), type(1), dsa(dsa), eof(1), drr(1), saddr(addr), tag(0), rsvd(0) {}*/ -}; - -struct mmStatus -{ - ap_uint<4> tag; - ap_uint<1> interr; - ap_uint<1> decerr; - ap_uint<1> slverr; - ap_uint<1> okay; -}; - -//TODO is this required?? -struct mm_ibtt_status -{ - ap_uint<4> tag; - ap_uint<1> interr; - ap_uint<1> decerr; - ap_uint<1> slverr; - ap_uint<1> okay; - ap_uint<22> brc_vd; - ap_uint<1> eop; -}; - -struct openStatus -{ - ap_uint<16> sessionID; - ap_uint<8> success; - ap_uint<32> ip; - ap_uint<16> port; - openStatus() {} - openStatus(ap_uint<16> id, ap_uint<8> success) - :sessionID(id), success(success), ip(0), port(0) {} - openStatus(ap_uint<16> id, ap_uint<8> success, ap_uint<32> ip, ap_uint<16> port) - :sessionID(id), success(success), ip(ip), port(port) {} -}; - -struct appNotification -{ - ap_uint<16> sessionID; - ap_uint<16> length; - ap_uint<32> ipAddress; - ap_uint<16> dstPort; - bool closed; - appNotification() {} - appNotification(ap_uint<16> id, ap_uint<16> len, ap_uint<32> addr, ap_uint<16> port) - :sessionID(id), length(len), ipAddress(addr), dstPort(port), closed(false) {} - appNotification(ap_uint<16> id, bool closed) - :sessionID(id), length(0), ipAddress(0), dstPort(0), closed(closed) {} - appNotification(ap_uint<16> id, ap_uint<32> addr, ap_uint<16> port, bool closed) - :sessionID(id), length(0), ipAddress(addr), dstPort(port), closed(closed) {} - appNotification(ap_uint<16> id, ap_uint<16> len, ap_uint<32> addr, ap_uint<16> port, bool closed) - :sessionID(id), length(len), ipAddress(addr), dstPort(port), closed(closed) {} -}; - - -struct appReadRequest -{ - ap_uint<16> sessionID; - //ap_uint<16> address; - ap_uint<16> length; - appReadRequest() {} - appReadRequest(ap_uint<16> id, ap_uint<16> len) - :sessionID(id), length(len) {} -}; - -struct appTxMeta -{ - ap_uint<16> sessionID; - ap_uint<16> length; - appTxMeta() {} - appTxMeta(ap_uint<16> id, ap_uint<16> len) - :sessionID(id), length(len) {} -}; - -struct appTxRsp -{ - ap_uint<16> sessionID; - ap_uint<16> length; - ap_uint<30> remaining_space; - ap_uint<2> error; - appTxRsp() {} - appTxRsp(ap_uint<16> id, ap_uint<16> len, ap_uint<30> rem_space, ap_uint<2> err) - :sessionID(id), length(len), remaining_space(rem_space), error(err) {} -}; - - -template -void toe( // Data & Memory Interface - hls::stream >& ipRxData, - hls::stream& rxBufferWriteStatus, - hls::stream& txBufferWriteStatus, - hls::stream >& rxBufferReadData, - hls::stream >& txBufferReadData, - hls::stream >& ipTxData, - hls::stream& rxBufferWriteCmd, - hls::stream& rxBufferReadCmd, - hls::stream& txBufferWriteCmd, - hls::stream& txBufferReadCmd, - hls::stream >& rxBufferWriteData, - hls::stream >& txBufferWriteData, - // SmartCam Interface - hls::stream& sessionLookup_rsp, - hls::stream& sessionUpdate_rsp, - //hls::stream >& readFinSessionId, - hls::stream& sessionLookup_req, - hls::stream& sessionUpdate_req, - //hls::stream& sessionInsert_req, - //hls::stream& sessionDelete_req, - //hls::stream >& writeNewSessionId, - // Application Interface - hls::stream >& listenPortReq, - // This is disabled for the time being, due to complexity concerns - //hls::stream >& appClosePortIn, - hls::stream& rxDataReq, - hls::stream& openConnReq, - hls::stream >& closeConnReq, - hls::stream& txDataReqMeta, - hls::stream >& txDataReq, - - hls::stream& listenPortRsp, - hls::stream& notification, - hls::stream >& rxDataRspMeta, - hls::stream >& rxDataRsp, - hls::stream& openConnRsp, - hls::stream& txDataRsp, - //IP Address Input - ap_uint<32> myIpAddress, - //statistic - ap_uint<16>& regSessionCount); - - -#endif diff --git a/examples_hw/apps/tcp_iperf/perf_tcp_c0_0.svh b/examples_hw/apps/tcp_iperf/perf_tcp_c0_0.svh deleted file mode 100644 index 3184cb2fd..000000000 --- a/examples_hw/apps/tcp_iperf/perf_tcp_c0_0.svh +++ /dev/null @@ -1,56 +0,0 @@ -// Tie-off -always_comb axis_host_sink.tie_off_s(); -always_comb axis_host_src.tie_off_m(); - -// UL -send_recv_role #( - .C_S_AXI_CONTROL_DATA_WIDTH(AXIL_DATA_BITS), - .C_S_AXI_CONTROL_ADDR_WIDTH(AXI_ADDR_BITS) -)user_role ( - .ap_clk(aclk), - .ap_rst_n(aresetn), - - .axi_ctrl (axi_ctrl), - - .m_axis_tcp_listen_port_tvalid (tcp_0_listen_req.valid), - .m_axis_tcp_listen_port_tready (tcp_0_listen_req.ready), - .m_axis_tcp_listen_port_tdata (tcp_0_listen_req.data), - .s_axis_tcp_port_status_tvalid (tcp_0_listen_rsp.valid), - .s_axis_tcp_port_status_tready (tcp_0_listen_rsp.ready), - .s_axis_tcp_port_status_tdata (tcp_0_listen_rsp.data), - .m_axis_tcp_open_connection_tvalid (tcp_0_open_req.valid), - .m_axis_tcp_open_connection_tready (tcp_0_open_req.ready), - .m_axis_tcp_open_connection_tdata (tcp_0_open_req.data), - .s_axis_tcp_open_status_tvalid (tcp_0_open_rsp.valid), - .s_axis_tcp_open_status_tready (tcp_0_open_rsp.ready), - .s_axis_tcp_open_status_tdata (tcp_0_open_rsp.data), - .m_axis_tcp_close_connection_tvalid(tcp_0_close_req.valid), - .m_axis_tcp_close_connection_tready(tcp_0_close_req.ready), - .m_axis_tcp_close_connection_tdata (tcp_0_close_req.data), - .s_axis_tcp_notification_tvalid (tcp_0_notify.valid), - .s_axis_tcp_notification_tready (tcp_0_notify.ready), - .s_axis_tcp_notification_tdata (tcp_0_notify.data), - .m_axis_tcp_read_pkg_tvalid (tcp_0_rd_pkg.valid), - .m_axis_tcp_read_pkg_tready (tcp_0_rd_pkg.ready), - .m_axis_tcp_read_pkg_tdata (tcp_0_rd_pkg.data), - .s_axis_tcp_rx_meta_tvalid (tcp_0_rx_meta.valid), - .s_axis_tcp_rx_meta_tready (tcp_0_rx_meta.ready), - .s_axis_tcp_rx_meta_tdata (tcp_0_rx_meta.data), - .s_axis_tcp_rx_data_tvalid (axis_tcp_0_sink.tvalid), - .s_axis_tcp_rx_data_tready (axis_tcp_0_sink.tready), - .s_axis_tcp_rx_data_tdata (axis_tcp_0_sink.tdata), - .s_axis_tcp_rx_data_tkeep (axis_tcp_0_sink.tkeep), - .s_axis_tcp_rx_data_tlast (axis_tcp_0_sink.tlast), - .m_axis_tcp_tx_meta_tvalid (tcp_0_tx_meta.valid), - .m_axis_tcp_tx_meta_tready (tcp_0_tx_meta.ready), - .m_axis_tcp_tx_meta_tdata (tcp_0_tx_meta.data), - .m_axis_tcp_tx_data_tvalid (axis_tcp_0_src.tvalid), - .m_axis_tcp_tx_data_tready (axis_tcp_0_src.tready), - .m_axis_tcp_tx_data_tdata (axis_tcp_0_src.tdata), - .m_axis_tcp_tx_data_tkeep (axis_tcp_0_src.tkeep), - .m_axis_tcp_tx_data_tlast (axis_tcp_0_src.tlast), - .s_axis_tcp_tx_status_tvalid (tcp_0_tx_stat.valid), - .s_axis_tcp_tx_status_tready (tcp_0_tx_stat.ready), - .s_axis_tcp_tx_status_tdata (tcp_0_tx_stat.data) - -); \ No newline at end of file diff --git a/examples_hw/apps/tcp_iperf/send_recv.sv b/examples_hw/apps/tcp_iperf/send_recv.sv deleted file mode 100644 index 51d7c2a4a..000000000 --- a/examples_hw/apps/tcp_iperf/send_recv.sv +++ /dev/null @@ -1,116 +0,0 @@ -`timescale 1ns / 1ps - -`include "axi_macros.svh" -`include "lynx_macros.svh" - -import lynxTypes::*; - -/** - * User logic - * - */ -module design_user_logic_0 ( - // AXI4L CONTROL - // Slave control. Utilize this interface for any kind of CSR implementation. - AXI4L.s axi_ctrl, - - // TCP/IP - metaIntf.m tcp_listen_req, - metaIntf.s tcp_listen_rsp, - metaIntf.m tcp_open_req, - metaIntf.s tcp_open_rsp, - metaIntf.m tcp_close_req, - metaIntf.s tcp_notify, - metaIntf.m tcp_rd_package, - metaIntf.s tcp_rx_meta, - metaIntf.m tcp_tx_meta, - metaIntf.s tcp_tx_stat, - - // AXI4S TCP/IP data - AXI4S.m axis_tcp_src, - AXI4S.s axis_tcp_sink, - - // AXI4S host data - // Host streams. - AXI4S.m axis_host_src, - AXI4S.s axis_host_sink, - - // Clock and reset - input wire aclk, - input wire[0:0] aresetn -); - -/* -- Tie-off unused interfaces and signals ----------------------------- */ -// always_comb axi_ctrl.tie_off_s(); -// always_comb tcp_listen_req.tie_off_m(); -// always_comb tcp_listen_rsp.tie_off_s(); -// always_comb tcp_open_req.tie_off_m(); -// always_comb tcp_open_rsp.tie_off_s(); -// always_comb tcp_close_req.tie_off_m(); -// always_comb tcp_notify.tie_off_s(); -// always_comb tcp_rd_package.tie_off_m(); -// always_comb tcp_rx_meta.tie_off_s(); -// always_comb tcp_tx_meta.tie_off_m(); -// always_comb tcp_tx_stat.tie_off_s(); -// always_comb axis_tcp_src.tie_off_m(); -// always_comb axis_tcp_sink.tie_off_s(); -always_comb axis_host_src.tie_off_m(); -always_comb axis_host_sink.tie_off_s(); - -/* -- USER LOGIC -------------------------------------------------------- */ - - -send_recv_role #( - .C_S_AXI_CONTROL_DATA_WIDTH(AXIL_DATA_BITS), - .C_S_AXI_CONTROL_ADDR_WIDTH(AXI_ADDR_BITS) -)user_role ( - .ap_clk(aclk), - .ap_rst_n(aresetn), - - .axi_ctrl (axi_ctrl), - - .m_axis_tcp_listen_port_tvalid (tcp_listen_req.valid), - .m_axis_tcp_listen_port_tready (tcp_listen_req.ready), - .m_axis_tcp_listen_port_tdata (tcp_listen_req.data), - .s_axis_tcp_port_status_tvalid (tcp_listen_rsp.valid), - .s_axis_tcp_port_status_tready (tcp_listen_rsp.ready), - .s_axis_tcp_port_status_tdata (tcp_listen_rsp.data), - .m_axis_tcp_open_connection_tvalid (tcp_open_req.valid), - .m_axis_tcp_open_connection_tready (tcp_open_req.ready), - .m_axis_tcp_open_connection_tdata (tcp_open_req.data), - .s_axis_tcp_open_status_tvalid (tcp_open_rsp.valid), - .s_axis_tcp_open_status_tready (tcp_open_rsp.ready), - .s_axis_tcp_open_status_tdata (tcp_open_rsp.data), - .m_axis_tcp_close_connection_tvalid(tcp_close_req.valid), - .m_axis_tcp_close_connection_tready(tcp_close_req.ready), - .m_axis_tcp_close_connection_tdata (tcp_close_req.data), - .s_axis_tcp_notification_tvalid (tcp_notify.valid), - .s_axis_tcp_notification_tready (tcp_notify.ready), - .s_axis_tcp_notification_tdata (tcp_notify.data), - .m_axis_tcp_read_pkg_tvalid (tcp_rd_package.valid), - .m_axis_tcp_read_pkg_tready (tcp_rd_package.ready), - .m_axis_tcp_read_pkg_tdata (tcp_rd_package.data), - .s_axis_tcp_rx_meta_tvalid (tcp_rx_meta.valid), - .s_axis_tcp_rx_meta_tready (tcp_rx_meta.ready), - .s_axis_tcp_rx_meta_tdata (tcp_rx_meta.data), - .s_axis_tcp_rx_data_tvalid (axis_tcp_sink.tvalid), - .s_axis_tcp_rx_data_tready (axis_tcp_sink.tready), - .s_axis_tcp_rx_data_tdata (axis_tcp_sink.tdata), - .s_axis_tcp_rx_data_tkeep (axis_tcp_sink.tkeep), - .s_axis_tcp_rx_data_tlast (axis_tcp_sink.tlast), - .m_axis_tcp_tx_meta_tvalid (tcp_tx_meta.valid), - .m_axis_tcp_tx_meta_tready (tcp_tx_meta.ready), - .m_axis_tcp_tx_meta_tdata (tcp_tx_meta.data), - .m_axis_tcp_tx_data_tvalid (axis_tcp_src.tvalid), - .m_axis_tcp_tx_data_tready (axis_tcp_src.tready), - .m_axis_tcp_tx_data_tdata (axis_tcp_src.tdata), - .m_axis_tcp_tx_data_tkeep (axis_tcp_src.tkeep), - .m_axis_tcp_tx_data_tlast (axis_tcp_src.tlast), - .s_axis_tcp_tx_status_tvalid (tcp_tx_stat.valid), - .s_axis_tcp_tx_status_tready (tcp_tx_stat.ready), - .s_axis_tcp_tx_status_tdata (tcp_tx_stat.data) - -); - -endmodule - diff --git a/examples_hw/apps/tcp_iperf/send_recv_role.sv b/examples_hw/apps/tcp_iperf/send_recv_role.sv deleted file mode 100644 index f900392ed..000000000 --- a/examples_hw/apps/tcp_iperf/send_recv_role.sv +++ /dev/null @@ -1,630 +0,0 @@ -/* - * Copyright (c) 2019, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -`timescale 1ns / 1ps -`default_nettype none - -import lynxTypes::*; - -module send_recv_role - #( - parameter integer C_S_AXI_CONTROL_DATA_WIDTH = 32, - parameter integer C_S_AXI_CONTROL_ADDR_WIDTH = 12, - parameter integer NETWORK_STACK_WIDTH=512 -) -( - input wire ap_clk, - input wire ap_rst_n, - - AXI4L.s axi_ctrl, - - /* NETWORK - TCP/IP INTERFACE */ - //Network TCP/IP - output wire m_axis_tcp_listen_port_tvalid , - input wire m_axis_tcp_listen_port_tready , - output wire [16-1:0] m_axis_tcp_listen_port_tdata , - - input wire s_axis_tcp_port_status_tvalid , - output wire s_axis_tcp_port_status_tready , - input wire [8-1:0] s_axis_tcp_port_status_tdata , - - output wire m_axis_tcp_open_connection_tvalid , - input wire m_axis_tcp_open_connection_tready , - output wire [48-1:0] m_axis_tcp_open_connection_tdata , - - input wire s_axis_tcp_open_status_tvalid , - output wire s_axis_tcp_open_status_tready , - input wire [128-1:0] s_axis_tcp_open_status_tdata , - - output wire m_axis_tcp_close_connection_tvalid , - input wire m_axis_tcp_close_connection_tready , - output wire [16-1:0] m_axis_tcp_close_connection_tdata , - - input wire s_axis_tcp_notification_tvalid , - output wire s_axis_tcp_notification_tready , - input wire [88-1:0] s_axis_tcp_notification_tdata , - - output wire m_axis_tcp_read_pkg_tvalid , - input wire m_axis_tcp_read_pkg_tready , - output wire [32-1:0] m_axis_tcp_read_pkg_tdata , - - input wire s_axis_tcp_rx_meta_tvalid , - output wire s_axis_tcp_rx_meta_tready , - input wire [16-1:0] s_axis_tcp_rx_meta_tdata , - - input wire s_axis_tcp_rx_data_tvalid , - output wire s_axis_tcp_rx_data_tready , - input wire [NETWORK_STACK_WIDTH-1:0] s_axis_tcp_rx_data_tdata , - input wire [NETWORK_STACK_WIDTH/8-1:0] s_axis_tcp_rx_data_tkeep , - input wire s_axis_tcp_rx_data_tlast , - - output wire m_axis_tcp_tx_meta_tvalid , - input wire m_axis_tcp_tx_meta_tready , - output wire [32-1:0] m_axis_tcp_tx_meta_tdata , - - output wire m_axis_tcp_tx_data_tvalid , - input wire m_axis_tcp_tx_data_tready , - output wire [NETWORK_STACK_WIDTH-1:0] m_axis_tcp_tx_data_tdata , - output wire [NETWORK_STACK_WIDTH/8-1:0] m_axis_tcp_tx_data_tkeep , - output wire m_axis_tcp_tx_data_tlast , - - input wire s_axis_tcp_tx_status_tvalid , - output wire s_axis_tcp_tx_status_tready , - input wire [64-1:0] s_axis_tcp_tx_status_tdata - - - -); - -wire ap_start, ap_done, ap_ready, ap_idle, interrupt; -wire [63:0] axi00_ptr0; -logic ap_start_pulse; -logic ap_start_r = 1'b0; -logic ap_idle_r = 1'b1; - -logic runExperiment; -logic finishExperiment; -logic runTx, sentRunTx; -logic openConnectionSuccess; - -// create pulse when ap_start transitions to 1 -always @(posedge ap_clk) begin - begin - ap_start_r <= ap_start; - end -end - -assign ap_start_pulse = ap_start & ~ap_start_r; -assign runExperiment = ap_start_pulse; - -// ap_idle is asserted when done is asserted, it is de-asserted when ap_start_pulse -// is asserted -always @(posedge ap_clk) begin - if (~ap_rst_n) begin - ap_idle_r <= 1'b1; - end - else begin - ap_idle_r <= ap_done ? 1'b1 : - ap_start_pulse ? 1'b0 : ap_idle; - end -end - -assign ap_idle = ap_idle_r; - -// Done logic - -assign ap_done = finishExperiment; - -// Ready Logic (non-pipelined case) -assign ap_ready = ap_done; - - -/* - * TCP/IP Benchmark - */ - - - -logic[7:0] listenCounter; -logic[7:0] openReqCounter; -logic[7:0] closeReqCounter; -logic[7:0] successOpenCounter; -logic[7:0] openStatusCounter; -logic[63:0] execution_cycles; -logic[63:0] openCon_cycles; -logic[31:0] connections; -logic running; - -wire [31:0] useConn, useIpAddr, pkgWordCount, basePort ,baseIpAddress; - -logic[31:0] timeInSeconds, transferSize, isServer; -logic[63:0] timeInCycles; - -logic [15:0] UseIpAddrReg; -logic [15:0] useConnReg; -logic [15:0] regBasePort; -logic [15:0] pkgWordCountReg; -logic [31:0] baseIpAddressReg; - -reg[63:0] consumed_bytes; -reg[63:0] produced_bytes; - -reg [47:0] rdRqstByteCnt; -reg [31:0] rcvPktCnt; - -reg [31:0] tx_meta_down; -reg [31:0] tx_status_down; -reg [31:0] tx_data_down; - -logic [15:0] sessionID; - - - - -// send open connection request when it is runExperiment and not server -assign m_axis_tcp_open_connection_tvalid = (!isServer) & runExperiment; -assign m_axis_tcp_open_connection_tdata = {regBasePort[15:0], baseIpAddress}; - -assign m_axis_tcp_close_connection_tvalid = 1'b0; -assign s_axis_tcp_open_status_tready = 1'b1; - -always @ (posedge ap_clk) begin - if (~ap_rst_n) begin - baseIpAddressReg <= '0; - regBasePort <= '0; - pkgWordCountReg <= '0; - UseIpAddrReg <= '0; - useConnReg <= '0; - end - else begin - baseIpAddressReg <= baseIpAddress ; - regBasePort <= basePort ; - pkgWordCountReg <= pkgWordCount; - UseIpAddrReg <= useIpAddr; - useConnReg <= useConn ; - end - -end - -always @(posedge ap_clk) begin - if (~ap_rst_n) begin - running <= 1'b0; - listenCounter <= '0; - openReqCounter <= '0; - closeReqCounter <= '0; - successOpenCounter <= '0; - connections <= '0; - openStatusCounter <= '0; - finishExperiment <= 1'b0; - rdRqstByteCnt <= '0; - rcvPktCnt <= '0; - tx_meta_down <= '0; - tx_data_down <= '0; - tx_status_down <= '0; - runTx <= 1'b0; - sentRunTx <= 1'b0; - sessionID <= 0; - openCon_cycles <= '0; - end - else begin - if (runExperiment) begin - finishExperiment <= 1'b0; - running <= 1'b1; - execution_cycles <= '0; - closeReqCounter <= '0; - openReqCounter <= '0; - successOpenCounter <= '0; - openStatusCounter <= '0; - rdRqstByteCnt <= '0; - rcvPktCnt <= '0; - tx_meta_down <= '0; - tx_data_down <= '0; - tx_status_down <= '0; - runTx <= 1'b0; - sentRunTx <= 1'b0; - sessionID <= 0; - openCon_cycles <= '0; - end - - if (running & isServer) begin - if (s_axis_tcp_rx_meta_tvalid & s_axis_tcp_rx_meta_tready) begin - sessionID <= s_axis_tcp_rx_meta_tdata; - end - end - else if (running & !isServer) begin - if (s_axis_tcp_open_status_tvalid & s_axis_tcp_open_status_tready & s_axis_tcp_open_status_tdata[16] ) begin - sessionID <= s_axis_tcp_open_status_tdata[15:0]; - end - end - - // if server node, run tx when receive expected amount of bytes - if (running) begin - if (isServer) begin - runTx <= (consumed_bytes >= transferSize) & !sentRunTx; - end - // if not server node, run tx when receiving open connection status - else begin - runTx <= s_axis_tcp_open_status_tvalid & s_axis_tcp_open_status_tready & s_axis_tcp_open_status_tdata[16] & !sentRunTx; - end - end - - if (runTx) begin - sentRunTx <= 1'b1; - end - - if (running) begin - execution_cycles <= execution_cycles + 1; - end - if (m_axis_tcp_listen_port_tvalid && m_axis_tcp_listen_port_tready) begin - listenCounter <= listenCounter +1; - end - if (m_axis_tcp_close_connection_tvalid && m_axis_tcp_close_connection_tready) begin - closeReqCounter <= closeReqCounter + 1; - end - - if ( running & (consumed_bytes >= transferSize) & (produced_bytes >= transferSize) ) begin - running <= 1'b0; - finishExperiment <= 1'b1; - end - - if (m_axis_tcp_open_connection_tvalid && m_axis_tcp_open_connection_tready) begin - openReqCounter <= openReqCounter + 1; - end - if (s_axis_tcp_open_status_tvalid & s_axis_tcp_open_status_tready ) begin - openStatusCounter <= openStatusCounter + 1'b1; - if (s_axis_tcp_open_status_tdata[16]) begin - successOpenCounter <= successOpenCounter + 1'b1; - end - end - - if (running & successOpenCounter== 0 ) begin - openCon_cycles <= openCon_cycles + 1; - end - - if (m_axis_tcp_read_pkg_tvalid & m_axis_tcp_read_pkg_tready) begin - rdRqstByteCnt <= rdRqstByteCnt + m_axis_tcp_read_pkg_tdata[31:16]; - end - - if (s_axis_tcp_rx_data_tvalid & s_axis_tcp_rx_data_tready & s_axis_tcp_rx_data_tlast) begin - rcvPktCnt <= rcvPktCnt + 1'b1; - end - - if (m_axis_tcp_tx_meta_tvalid & ~m_axis_tcp_tx_meta_tready) begin - tx_meta_down <= tx_meta_down + 1'b1; - end - - if (s_axis_tcp_tx_status_tvalid & ~s_axis_tcp_tx_status_tready) begin - tx_status_down <= tx_status_down + 1'b1; - end - - if (m_axis_tcp_tx_data_tvalid & ~m_axis_tcp_tx_data_tready) begin - tx_data_down <= tx_data_down + 1'b1; - end - - connections <= {listenCounter,openReqCounter,successOpenCounter,closeReqCounter}; - end -end - -`ifdef VITIS_HLS -send_recv_ip send_recv ( - // .m_axis_close_connection_V_V_TVALID(m_axis_tcp_close_connection_tvalid), // output wire m_axis_close_connection_TVALID - // .m_axis_close_connection_V_V_TREADY(m_axis_tcp_close_connection_tready), // input wire m_axis_close_connection_TREADY - // .m_axis_close_connection_V_V_TDATA(m_axis_tcp_close_connection_tdata), // output wire [15 : 0] m_axis_close_connection_TDATA - .m_axis_listen_port_TVALID(m_axis_tcp_listen_port_tvalid), // output wire m_axis_listen_port_TVALID - .m_axis_listen_port_TREADY(m_axis_tcp_listen_port_tready), // input wire m_axis_listen_port_TREADY - .m_axis_listen_port_TDATA(m_axis_tcp_listen_port_tdata), // output wire [15 : 0] m_axis_listen_port_TDATA - // .m_axis_open_connection_V_TVALID(m_axis_tcp_open_connection_tvalid), // output wire m_axis_open_connection_TVALID - // .m_axis_open_connection_V_TREADY(m_axis_tcp_open_connection_tready), // input wire m_axis_open_connection_TREADY - // .m_axis_open_connection_V_TDATA(m_axis_tcp_open_connection_tdata), // output wire [47 : 0] m_axis_open_connection_TDATA - .m_axis_read_package_TVALID(m_axis_tcp_read_pkg_tvalid), // output wire m_axis_read_package_TVALID - .m_axis_read_package_TREADY(m_axis_tcp_read_pkg_tready), // input wire m_axis_read_package_TREADY - .m_axis_read_package_TDATA(m_axis_tcp_read_pkg_tdata), // output wire [31 : 0] m_axis_read_package_TDATA - .m_axis_tx_data_TVALID(m_axis_tcp_tx_data_tvalid), // output wire m_axis_tx_data_TVALID - .m_axis_tx_data_TREADY(m_axis_tcp_tx_data_tready), // input wire m_axis_tx_data_TREADY - .m_axis_tx_data_TDATA(m_axis_tcp_tx_data_tdata), // output wire [63 : 0] m_axis_tx_data_TDATA - .m_axis_tx_data_TKEEP(m_axis_tcp_tx_data_tkeep), // output wire [7 : 0] m_axis_tx_data_TKEEP - .m_axis_tx_data_TLAST(m_axis_tcp_tx_data_tlast), // output wire [0 : 0] m_axis_tx_data_TLAST - .m_axis_tx_metadata_TVALID(m_axis_tcp_tx_meta_tvalid), // output wire m_axis_tx_metadata_TVALID - .m_axis_tx_metadata_TREADY(m_axis_tcp_tx_meta_tready), // input wire m_axis_tx_metadata_TREADY - .m_axis_tx_metadata_TDATA(m_axis_tcp_tx_meta_tdata), // output wire [15 : 0] m_axis_tx_metadata_TDATA - .s_axis_listen_port_status_TVALID(s_axis_tcp_port_status_tvalid), // input wire s_axis_listen_port_status_TVALID - .s_axis_listen_port_status_TREADY(s_axis_tcp_port_status_tready), // output wire s_axis_listen_port_status_TREADY - .s_axis_listen_port_status_TDATA(s_axis_tcp_port_status_tdata), // input wire [7 : 0] s_axis_listen_port_status_TDATA - .s_axis_notifications_TVALID(s_axis_tcp_notification_tvalid), // input wire s_axis_notifications_TVALID - .s_axis_notifications_TREADY(s_axis_tcp_notification_tready), // output wire s_axis_notifications_TREADY - .s_axis_notifications_TDATA(s_axis_tcp_notification_tdata), // input wire [87 : 0] s_axis_notifications_TDATA - // .s_axis_open_status_TVALID(s_axis_tcp_open_status_tvalid), // input wire s_axis_open_status_TVALID - // .s_axis_open_status_TREADY(s_axis_tcp_open_status_tready), // output wire s_axis_open_status_TREADY - // .s_axis_open_status_TDATA(s_axis_tcp_open_status_tdata), // input wire [23 : 0] s_axis_open_status_TDATA - .s_axis_rx_data_TVALID(s_axis_tcp_rx_data_tvalid), // input wire s_axis_rx_data_TVALID - .s_axis_rx_data_TREADY(s_axis_tcp_rx_data_tready), // output wire s_axis_rx_data_TREADY - .s_axis_rx_data_TDATA(s_axis_tcp_rx_data_tdata), // input wire [63 : 0] s_axis_rx_data_TDATA - .s_axis_rx_data_TKEEP(s_axis_tcp_rx_data_tkeep), // input wire [7 : 0] s_axis_rx_data_TKEEP - .s_axis_rx_data_TLAST(s_axis_tcp_rx_data_tlast), // input wire [0 : 0] s_axis_rx_data_TLAST - .s_axis_rx_metadata_TVALID(s_axis_tcp_rx_meta_tvalid), // input wire s_axis_rx_metadata_TVALID - .s_axis_rx_metadata_TREADY(s_axis_tcp_rx_meta_tready), // output wire s_axis_rx_metadata_TREADY - .s_axis_rx_metadata_TDATA(s_axis_tcp_rx_meta_tdata), // input wire [15 : 0] s_axis_rx_metadata_TDATA - .s_axis_tx_status_TVALID(s_axis_tcp_tx_status_tvalid), // input wire s_axis_tx_status_TVALID - .s_axis_tx_status_TREADY(s_axis_tcp_tx_status_tready), // output wire s_axis_tx_status_TREADY - .s_axis_tx_status_TDATA(s_axis_tcp_tx_status_tdata), // input wire [23 : 0] s_axis_tx_status_TDATA - - //Client only - .runTx(runTx), - .transferSize(transferSize), // input wire [0 : 0] transferSize_V - .sessionID(sessionID), // input wire [7 : 0] sessionID_V - .pkgWordCount(pkgWordCountReg), // input wire [7 : 0] pkgWordCount_V - .ap_clk(ap_clk), // input wire aclk - .ap_rst_n(ap_rst_n) // input wire aresetn - ); -`else -send_recv_ip send_recv ( - // .m_axis_close_connection_V_V_TVALID(m_axis_tcp_close_connection_tvalid), // output wire m_axis_close_connection_TVALID - // .m_axis_close_connection_V_V_TREADY(m_axis_tcp_close_connection_tready), // input wire m_axis_close_connection_TREADY - // .m_axis_close_connection_V_V_TDATA(m_axis_tcp_close_connection_tdata), // output wire [15 : 0] m_axis_close_connection_TDATA - .m_axis_listen_port_V_V_TVALID(m_axis_tcp_listen_port_tvalid), // output wire m_axis_listen_port_TVALID - .m_axis_listen_port_V_V_TREADY(m_axis_tcp_listen_port_tready), // input wire m_axis_listen_port_TREADY - .m_axis_listen_port_V_V_TDATA(m_axis_tcp_listen_port_tdata), // output wire [15 : 0] m_axis_listen_port_TDATA - // .m_axis_open_connection_V_TVALID(m_axis_tcp_open_connection_tvalid), // output wire m_axis_open_connection_TVALID - // .m_axis_open_connection_V_TREADY(m_axis_tcp_open_connection_tready), // input wire m_axis_open_connection_TREADY - // .m_axis_open_connection_V_TDATA(m_axis_tcp_open_connection_tdata), // output wire [47 : 0] m_axis_open_connection_TDATA - .m_axis_read_package_V_TVALID(m_axis_tcp_read_pkg_tvalid), // output wire m_axis_read_package_TVALID - .m_axis_read_package_V_TREADY(m_axis_tcp_read_pkg_tready), // input wire m_axis_read_package_TREADY - .m_axis_read_package_V_TDATA(m_axis_tcp_read_pkg_tdata), // output wire [31 : 0] m_axis_read_package_TDATA - .m_axis_tx_data_TVALID(m_axis_tcp_tx_data_tvalid), // output wire m_axis_tx_data_TVALID - .m_axis_tx_data_TREADY(m_axis_tcp_tx_data_tready), // input wire m_axis_tx_data_TREADY - .m_axis_tx_data_TDATA(m_axis_tcp_tx_data_tdata), // output wire [63 : 0] m_axis_tx_data_TDATA - .m_axis_tx_data_TKEEP(m_axis_tcp_tx_data_tkeep), // output wire [7 : 0] m_axis_tx_data_TKEEP - .m_axis_tx_data_TLAST(m_axis_tcp_tx_data_tlast), // output wire [0 : 0] m_axis_tx_data_TLAST - .m_axis_tx_metadata_V_TVALID(m_axis_tcp_tx_meta_tvalid), // output wire m_axis_tx_metadata_TVALID - .m_axis_tx_metadata_V_TREADY(m_axis_tcp_tx_meta_tready), // input wire m_axis_tx_metadata_TREADY - .m_axis_tx_metadata_V_TDATA(m_axis_tcp_tx_meta_tdata), // output wire [15 : 0] m_axis_tx_metadata_TDATA - .s_axis_listen_port_status_V_TVALID(s_axis_tcp_port_status_tvalid), // input wire s_axis_listen_port_status_TVALID - .s_axis_listen_port_status_V_TREADY(s_axis_tcp_port_status_tready), // output wire s_axis_listen_port_status_TREADY - .s_axis_listen_port_status_V_TDATA(s_axis_tcp_port_status_tdata), // input wire [7 : 0] s_axis_listen_port_status_TDATA - .s_axis_notifications_V_TVALID(s_axis_tcp_notification_tvalid), // input wire s_axis_notifications_TVALID - .s_axis_notifications_V_TREADY(s_axis_tcp_notification_tready), // output wire s_axis_notifications_TREADY - .s_axis_notifications_V_TDATA(s_axis_tcp_notification_tdata), // input wire [87 : 0] s_axis_notifications_TDATA - // .s_axis_open_status_V_TVALID(s_axis_tcp_open_status_tvalid), // input wire s_axis_open_status_TVALID - // .s_axis_open_status_V_TREADY(s_axis_tcp_open_status_tready), // output wire s_axis_open_status_TREADY - // .s_axis_open_status_V_TDATA(s_axis_tcp_open_status_tdata), // input wire [23 : 0] s_axis_open_status_TDATA - .s_axis_rx_data_TVALID(s_axis_tcp_rx_data_tvalid), // input wire s_axis_rx_data_TVALID - .s_axis_rx_data_TREADY(s_axis_tcp_rx_data_tready), // output wire s_axis_rx_data_TREADY - .s_axis_rx_data_TDATA(s_axis_tcp_rx_data_tdata), // input wire [63 : 0] s_axis_rx_data_TDATA - .s_axis_rx_data_TKEEP(s_axis_tcp_rx_data_tkeep), // input wire [7 : 0] s_axis_rx_data_TKEEP - .s_axis_rx_data_TLAST(s_axis_tcp_rx_data_tlast), // input wire [0 : 0] s_axis_rx_data_TLAST - .s_axis_rx_metadata_V_V_TVALID(s_axis_tcp_rx_meta_tvalid), // input wire s_axis_rx_metadata_TVALID - .s_axis_rx_metadata_V_V_TREADY(s_axis_tcp_rx_meta_tready), // output wire s_axis_rx_metadata_TREADY - .s_axis_rx_metadata_V_V_TDATA(s_axis_tcp_rx_meta_tdata), // input wire [15 : 0] s_axis_rx_metadata_TDATA - .s_axis_tx_status_V_TVALID(s_axis_tcp_tx_status_tvalid), // input wire s_axis_tx_status_TVALID - .s_axis_tx_status_V_TREADY(s_axis_tcp_tx_status_tready), // output wire s_axis_tx_status_TREADY - .s_axis_tx_status_V_TDATA(s_axis_tcp_tx_status_tdata), // input wire [23 : 0] s_axis_tx_status_TDATA - - //Client only - .runTx_V(runTx), - .transferSize_V(transferSize), // input wire [0 : 0] transferSize_V - .sessionID_V(sessionID), // input wire [7 : 0] sessionID_V - .pkgWordCount_V(pkgWordCountReg), // input wire [7 : 0] pkgWordCount_V - .ap_clk(ap_clk), // input wire aclk - .ap_rst_n(ap_rst_n) // input wire aresetn - ); -`endif - -/* - * Role Controller - */ - -// AXI4-Lite slave interface - -send_recv_slave send_recv_slave_inst ( - .aclk (ap_clk), - .aresetn (ap_rst_n), - .axi_ctrl (axi_ctrl), - .ap_start (ap_start), - .ap_done (ap_done), - .useConn (useConn), - .useIpAddr (useIpAddr), - .pkgWordCount (pkgWordCount), - .basePort (basePort), - .baseIpAddress(baseIpAddress), - .transferSize (transferSize), - .isServer (isServer), - .timeInSeconds(timeInSeconds), - .timeInCycles (timeInCycles), - .execution_cycles(execution_cycles), - .consumed_bytes (consumed_bytes), - .produced_bytes (produced_bytes), - .openCon_cycles (openCon_cycles) -); - - -/* - * Statistics - */ - - -always @(posedge ap_clk) begin - if (~ap_rst_n) begin - consumed_bytes <= '0; - produced_bytes <= '0; - end - else begin - if (ap_start_pulse) begin - consumed_bytes <= '0; - produced_bytes <= '0; - end - - if (s_axis_tcp_rx_data_tvalid && s_axis_tcp_rx_data_tready) begin - case (s_axis_tcp_rx_data_tkeep) - 64'h1: consumed_bytes <= consumed_bytes + 1; - 64'h3: consumed_bytes <= consumed_bytes + 2; - 64'h7: consumed_bytes <= consumed_bytes + 4; - 64'hF: consumed_bytes <= consumed_bytes + 4; - 64'h1F: consumed_bytes <= consumed_bytes + 5; - 64'h3F: consumed_bytes <= consumed_bytes + 6; - 64'h7F: consumed_bytes <= consumed_bytes + 7; - 64'hFF: consumed_bytes <= consumed_bytes + 8; - 64'hFFFF: consumed_bytes <= consumed_bytes + 16; - 64'hFFFFF: consumed_bytes <= consumed_bytes + 20; - 64'hFFFFFF: consumed_bytes <= consumed_bytes + 24; - 64'hFFFFFFF: consumed_bytes <= consumed_bytes + 28; - 64'hFFFFFFFF: consumed_bytes <= consumed_bytes + 32; - 64'hFFFFFFFFF: consumed_bytes <= consumed_bytes + 36; - 64'hFFFFFFFFFF: consumed_bytes <= consumed_bytes + 40; - 64'hFFFFFFFFFFF: consumed_bytes <= consumed_bytes + 44; - 64'hFFFFFFFFFFFF: consumed_bytes <= consumed_bytes + 48; - 64'hFFFFFFFFFFFFF: consumed_bytes <= consumed_bytes + 52; - 64'hFFFFFFFFFFFFFF: consumed_bytes <= consumed_bytes + 56; - 64'hFFFFFFFFFFFFFFF: consumed_bytes <= consumed_bytes + 60; - 64'hFFFFFFFFFFFFFFFF: consumed_bytes <= consumed_bytes + 64; - endcase - end - - if (m_axis_tcp_tx_data_tvalid && m_axis_tcp_tx_data_tready) begin - case (m_axis_tcp_tx_data_tkeep) - 64'hF: produced_bytes <= produced_bytes + 4; - 64'hFF: produced_bytes <= produced_bytes + 8; - 64'hFFFF: produced_bytes <= produced_bytes + 16; - 64'hFFFFF: produced_bytes <= produced_bytes + 20; - 64'hFFFFFF: produced_bytes <= produced_bytes + 24; - 64'hFFFFFFF: produced_bytes <= produced_bytes + 28; - 64'hFFFFFFFF: produced_bytes <= produced_bytes + 32; - 64'hFFFFFFFFF: produced_bytes <= produced_bytes + 36; - 64'hFFFFFFFFFF: produced_bytes <= produced_bytes + 40; - 64'hFFFFFFFFFFF: produced_bytes <= produced_bytes + 44; - 64'hFFFFFFFFFFFF: produced_bytes <= produced_bytes + 48; - 64'hFFFFFFFFFFFFF: produced_bytes <= produced_bytes + 52; - 64'hFFFFFFFFFFFFFF: produced_bytes <= produced_bytes + 56; - 64'hFFFFFFFFFFFFFFF: produced_bytes <= produced_bytes + 60; - 64'hFFFFFFFFFFFFFFFF: produced_bytes <= produced_bytes + 64; - endcase - end - - end -end - - -logic[31:0] tx_cmd_counter; -logic[31:0] tx_pkg_counter; -logic[31:0] tx_sts_counter; -logic[31:0] tx_sts_good_counter; -always @(posedge ap_clk) begin - if (~ap_rst_n | runExperiment) begin - tx_cmd_counter <= '0; - tx_pkg_counter <= '0; - tx_sts_counter <= '0; - tx_sts_good_counter <= '0; - end - else begin - if (m_axis_tcp_tx_meta_tvalid && m_axis_tcp_tx_meta_tready) begin - tx_cmd_counter <= tx_cmd_counter + 1; - end - if (m_axis_tcp_tx_data_tvalid && m_axis_tcp_tx_data_tready && m_axis_tcp_tx_data_tlast) begin - tx_pkg_counter <= tx_pkg_counter + 1; - end - if (s_axis_tcp_tx_status_tvalid && s_axis_tcp_tx_status_tready) begin - tx_sts_counter <= tx_sts_counter + 1; - if (s_axis_tcp_tx_status_tdata[63:62] == 0) begin - tx_sts_good_counter <= tx_sts_good_counter + 1; - end - end - end -end - -`define DEBUG -`ifdef DEBUG - -ila_controller controller_debug -( -.clk(ap_clk), // input wire clk - .probe0(ap_start_pulse), //1 - .probe1(isServer), // 1 - .probe2(useConnReg), // 16 - .probe3(pkgWordCountReg), // 16 - .probe4(baseIpAddress), //32 - .probe5(transferSize), //32 - .probe6(timeInCycles), //64 - .probe7(regBasePort), //16 - .probe8(UseIpAddrReg), //16 - .probe9(ap_start), //1 - .probe10(ap_done) //1 -); - - -ila_perf benchmark_debug ( - .clk(ap_clk), // input wire clk - - .probe0(m_axis_tcp_open_connection_tvalid), // input wire [0:0] probe0 - .probe1(m_axis_tcp_open_connection_tready), // input wire [0:0] probe1 - .probe2(s_axis_tcp_open_status_tvalid), // input wire [0:0] probe2 - .probe3(s_axis_tcp_open_status_tready), // input wire [0:0] probe3 - .probe4(s_axis_tcp_rx_data_tvalid), // input wire [0:0] probe4 - .probe5(s_axis_tcp_rx_data_tready), // input wire [0:0] probe5 - .probe6(finishExperiment), // input wire [0:0] probe6 - .probe7(runTx), // input wire [0:0] probe7 - .probe8(m_axis_tcp_tx_data_tvalid), //1 - .probe9(m_axis_tcp_tx_data_tready),//1 - .probe10(m_axis_tcp_tx_meta_tvalid),//1 - .probe11(m_axis_tcp_tx_meta_tready),//1 - .probe12(s_axis_tcp_tx_status_tvalid),//1 - .probe13(s_axis_tcp_tx_status_tready), //1 - .probe14(s_axis_tcp_open_status_tdata[16]), //1 - .probe15(s_axis_tcp_tx_status_tdata[63:62]), //2 - .probe16(m_axis_tcp_open_connection_tdata[31:0]), // 32 - .probe17(produced_bytes[63:0]), // 64 - .probe18(consumed_bytes[63:0]),// 64 - .probe19(sessionID[15:0]), // input wire [15:0] - .probe20(tx_cmd_counter[31:0]), // input wire [31:0] - .probe21(m_axis_tcp_open_connection_tdata[47:32]), // input wire [15:0] - .probe22(running), //1 - .probe23(s_axis_tcp_notification_tvalid), //1 - .probe24(s_axis_tcp_notification_tready), //1 - .probe25(s_axis_tcp_tx_status_tdata[61:32]), //30 - .probe26(execution_cycles[63:0]), //64 - .probe27(transferSize[15:0]), //16 - .probe28(tx_pkg_counter[31:0]),//32 - .probe29(s_axis_tcp_open_status_tdata[15:0]), //16 - .probe30(tx_sts_good_counter[31:0]), //32 - - .probe31(s_axis_tcp_port_status_tvalid), // 1 - .probe32(s_axis_tcp_port_status_tready), // 1 - .probe33(m_axis_tcp_listen_port_tvalid), // 1 - .probe34(m_axis_tcp_listen_port_tready), //1 - .probe35(s_axis_tcp_rx_meta_tvalid), // 1 - .probe36(s_axis_tcp_rx_meta_tready), // 1 - .probe37(m_axis_tcp_read_pkg_tvalid), // 1 - .probe38(m_axis_tcp_read_pkg_tready), //1 - .probe39(tx_sts_counter), //32 - .probe40(tx_meta_down), //32 - .probe41(tx_status_down), //32 - .probe42(tx_data_down) //32 -); - - -`endif - - -endmodule -`default_nettype wire diff --git a/examples_hw/apps/tcp_iperf/send_recv_slave.sv b/examples_hw/apps/tcp_iperf/send_recv_slave.sv deleted file mode 100644 index b1a90ebc0..000000000 --- a/examples_hw/apps/tcp_iperf/send_recv_slave.sv +++ /dev/null @@ -1,372 +0,0 @@ -import lynxTypes::*; - -/** - * PT Config Slave - */ -module send_recv_slave ( - input logic aclk, - input logic aresetn, - - AXI4L.s axi_ctrl, - - output logic ap_start, - input logic ap_done, - output logic [31:0] useConn, - output logic [31:0] useIpAddr, - output logic [31:0] pkgWordCount, - output logic [31:0] basePort, - output logic [31:0] baseIpAddress, - output logic [31:0] transferSize, - output logic [31:0] isServer, - output logic [31:0] timeInSeconds, - output logic [63:0] timeInCycles, - input logic [63:0] execution_cycles, - input logic [63:0] consumed_bytes, - input logic [63:0] produced_bytes, - input logic [63:0] openCon_cycles -); - -// `define DEBUG_CNFG_SLAVE - -// -- Decl ---------------------------------------------------------- -// ------------------------------------------------------------------ - -// Constants -localparam integer N_REGS = 15; -localparam integer ADDR_LSB = $clog2(AXIL_DATA_BITS/8); -localparam integer ADDR_MSB = $clog2(N_REGS); -localparam integer AXIL_ADDR_BITS = ADDR_LSB + ADDR_MSB; - -// Internal registers -logic [AXIL_ADDR_BITS-1:0] axi_awaddr; -logic axi_awready; -logic [AXIL_ADDR_BITS-1:0] axi_araddr; -logic axi_arready; -logic [1:0] axi_bresp; -logic axi_bvalid; -logic axi_wready; -logic [AXIL_DATA_BITS-1:0] axi_rdata; -logic [1:0] axi_rresp; -logic axi_rvalid; - -// Registers -logic [N_REGS-1:0][AXIL_DATA_BITS-1:0] slv_reg; -logic slv_reg_rden; -logic slv_reg_wren; -logic aw_en; - -// -- Def ----------------------------------------------------------- -// ------------------------------------------------------------------ - -/* -- Register map ----------------------------------------------------------------------- -/ 0 (WO) : Control -/ 1 (RO) : Status -/ 2 (RW) : useConn -/ 3 (RW) : useIpAddr -/ 4 (RW) : pkgWordCount -/ 5 (RW) : basePort -/ 6 (RW) : baseIpAddr -/ 7 (RW) : transferSize -/ 8 (RW) : isServer -/ 9 (RW) : timeInSeconds -/ 10 (RW) : timeInCycles -/ 11 (R) : execution_cycles -/ 12 (R) : consumed_bytes -/ 13 (R) : produced_bytes -/ 14 (R) : openCon_cycles -*/ - -// Write process -assign slv_reg_wren = axi_wready && axi_ctrl.wvalid && axi_awready && axi_ctrl.awvalid; - -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) begin - slv_reg <= 0; - end - else begin - slv_reg[0][0] <= 0; - - if(slv_reg_wren) begin - case (axi_awaddr[ADDR_LSB+:ADDR_MSB]) - 4'h0: // Control - for (int i = 0; i < 1; i++) begin - if(axi_ctrl.wstrb[i]) begin - slv_reg[0][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8]; - end - end - 4'h2: // useConn - for (int i = 0; i < AXIL_DATA_BITS/8; i++) begin - if(axi_ctrl.wstrb[i]) begin - slv_reg[2][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8]; - end - end - 4'h3: // useIpAddr - for (int i = 0; i < AXIL_DATA_BITS/8; i++) begin - if(axi_ctrl.wstrb[i]) begin - slv_reg[3][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8]; - end - end - 4'h4: // pkgWordCount - for (int i = 0; i < AXIL_DATA_BITS/8; i++) begin - if(axi_ctrl.wstrb[i]) begin - slv_reg[4][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8]; - end - end - 4'h5: // basePort - for (int i = 0; i < AXIL_DATA_BITS/8; i++) begin - if(axi_ctrl.wstrb[i]) begin - slv_reg[5][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8]; - end - end - 4'h6: // baseIpAddr - for (int i = 0; i < AXIL_DATA_BITS/8; i++) begin - if(axi_ctrl.wstrb[i]) begin - slv_reg[6][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8]; - end - end - 4'h7: // transferSize - for (int i = 0; i < AXIL_DATA_BITS/8; i++) begin - if(axi_ctrl.wstrb[i]) begin - slv_reg[7][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8]; - end - end - 4'h8: // isServer - for (int i = 0; i < AXIL_DATA_BITS/8; i++) begin - if(axi_ctrl.wstrb[i]) begin - slv_reg[8][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8]; - end - end - 4'h9: // timeInSeconds - for (int i = 0; i < AXIL_DATA_BITS/8; i++) begin - if(axi_ctrl.wstrb[i]) begin - slv_reg[9][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8]; - end - end - 4'ha: // timeInCycles - for (int i = 0; i < AXIL_DATA_BITS/8; i++) begin - if(axi_ctrl.wstrb[i]) begin - slv_reg[10][(i*8)+:8] <= axi_ctrl.wdata[(i*8)+:8]; - end - end - default : ; - endcase - end - end -end - -// Output -always_comb begin - ap_start = slv_reg[0][0]; - - useConn = slv_reg[2]; - useIpAddr = slv_reg[3]; - pkgWordCount = slv_reg[4]; - basePort = slv_reg[5]; - baseIpAddress = slv_reg[6]; - transferSize = slv_reg[7]; - isServer = slv_reg[8]; - timeInSeconds = slv_reg[9]; - timeInCycles = slv_reg[10]; -end - -// Read process -assign slv_reg_rden = axi_arready & axi_ctrl.arvalid & ~axi_rvalid; - -always_ff @(posedge aclk) begin - if( aresetn == 1'b0 ) begin - axi_rdata <= 0; - end - else begin - if(slv_reg_rden) begin - axi_rdata <= 0; - - case (axi_araddr[ADDR_LSB+:ADDR_MSB]) - 4'h1: // Status - axi_rdata[0] <= ap_done; - 4'h2: // useConn - axi_rdata <= slv_reg[2]; - 4'h3: // useIpAddr - axi_rdata <= slv_reg[3]; - 4'h4: // pkgWordCount - axi_rdata <= slv_reg[4]; - 4'h5: // basePort - axi_rdata <= slv_reg[5]; - 4'h6: // baseIpAddr - axi_rdata <= slv_reg[6]; - 4'h7: // transferSize - axi_rdata <= slv_reg[7]; - 4'h8: // isServer - axi_rdata <= slv_reg[8]; - 4'h9: // timeInSeconds - axi_rdata <= slv_reg[9]; - 4'ha: // timeInCycles - axi_rdata <= slv_reg[10]; - 4'hb: //execution_cycles - axi_rdata <= execution_cycles; - 4'hc: //consumed_bytes - axi_rdata <= consumed_bytes; - 4'hd: //produced_bytes - axi_rdata <= produced_bytes; - 4'he: //openCon_cycles - axi_rdata <= openCon_cycles; - default: ; - endcase - end - end -end - -//`define DEBUG_CNFG_SLAVE -`ifdef DEBUG_CNFG_SLAVE -ila_slave ila_slave -( - .clk(aclk), - .probe0(slv_reg_rden), - .probe1(slv_reg_wren), - .probe2(axi_ctrl.arvalid), - .probe3(axi_ctrl.arready), - .probe4(axi_ctrl.araddr), // 64 - .probe5(axi_ctrl.awvalid), - .probe6(axi_ctrl.awready), - .probe7(axi_ctrl.awaddr), // 64 - .probe8(axi_ctrl.rvalid), - .probe9(axi_ctrl.rready), - .probe10(axi_ctrl.rdata), // 64 - .probe11(axi_ctrl.wvalid), - .probe12(axi_ctrl.wready), - .probe13(axi_ctrl.wdata), // 64 - .probe14(axi_ctrl.wstrb), // 8 - .probe15(axi_ctrl.bvalid), - .probe16(axi_ctrl.bready) - ); -`endif - -// -------------------------------------------------------------------------------------- -// AXI CTRL -// -------------------------------------------------------------------------------------- -// Don't edit - -// I/O -assign axi_ctrl.awready = axi_awready; -assign axi_ctrl.arready = axi_arready; -assign axi_ctrl.bresp = axi_bresp; -assign axi_ctrl.bvalid = axi_bvalid; -assign axi_ctrl.wready = axi_wready; -assign axi_ctrl.rdata = axi_rdata; -assign axi_ctrl.rresp = axi_rresp; -assign axi_ctrl.rvalid = axi_rvalid; - -// awready and awaddr -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) - begin - axi_awready <= 1'b0; - axi_awaddr <= 0; - aw_en <= 1'b1; - end - else - begin - if (~axi_awready && axi_ctrl.awvalid && axi_ctrl.wvalid && aw_en) - begin - axi_awready <= 1'b1; - aw_en <= 1'b0; - axi_awaddr <= axi_ctrl.awaddr; - end - else if (axi_ctrl.bready && axi_bvalid) - begin - aw_en <= 1'b1; - axi_awready <= 1'b0; - end - else - begin - axi_awready <= 1'b0; - end - end -end - -// arready and araddr -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) - begin - axi_arready <= 1'b0; - axi_araddr <= 0; - end - else - begin - if (~axi_arready && axi_ctrl.arvalid) - begin - axi_arready <= 1'b1; - axi_araddr <= axi_ctrl.araddr; - end - else - begin - axi_arready <= 1'b0; - end - end -end - -// bvalid and bresp -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) - begin - axi_bvalid <= 0; - axi_bresp <= 2'b0; - end - else - begin - if (axi_awready && axi_ctrl.awvalid && ~axi_bvalid && axi_wready && axi_ctrl.wvalid) - begin - axi_bvalid <= 1'b1; - axi_bresp <= 2'b0; - end - else - begin - if (axi_ctrl.bready && axi_bvalid) - begin - axi_bvalid <= 1'b0; - end - end - end -end - -// wready -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) - begin - axi_wready <= 1'b0; - end - else - begin - if (~axi_wready && axi_ctrl.wvalid && axi_ctrl.awvalid && aw_en ) - begin - axi_wready <= 1'b1; - end - else - begin - axi_wready <= 1'b0; - end - end -end - -// rvalid and rresp (1Del?) -always_ff @(posedge aclk) begin - if ( aresetn == 1'b0 ) - begin - axi_rvalid <= 0; - axi_rresp <= 0; - end - else - begin - if (axi_arready && axi_ctrl.arvalid && ~axi_rvalid) - begin - axi_rvalid <= 1'b1; - axi_rresp <= 2'b0; - end - else if (axi_rvalid && axi_ctrl.rready) - begin - axi_rvalid <= 1'b0; - end - end -end - - -endmodule // cnfg_slave \ No newline at end of file diff --git a/examples_hw/apps/tcp_iperf/set_ila.tcl b/examples_hw/apps/tcp_iperf/set_ila.tcl deleted file mode 100644 index bb2faa8db..000000000 --- a/examples_hw/apps/tcp_iperf/set_ila.tcl +++ /dev/null @@ -1,33 +0,0 @@ -create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_perf -set_property -dict [list CONFIG.C_PROBE42_WIDTH {32} CONFIG.C_PROBE41_WIDTH {32} CONFIG.C_PROBE40_WIDTH {32} CONFIG.C_PROBE39_WIDTH {32} CONFIG.C_PROBE30_WIDTH {32} CONFIG.C_PROBE29_WIDTH {16} CONFIG.C_PROBE28_WIDTH {32} CONFIG.C_PROBE27_WIDTH {16} CONFIG.C_PROBE26_WIDTH {64} CONFIG.C_PROBE25_WIDTH {30} CONFIG.C_PROBE21_WIDTH {16} CONFIG.C_PROBE20_WIDTH {32} CONFIG.C_PROBE19_WIDTH {16} CONFIG.C_PROBE18_WIDTH {64} CONFIG.C_PROBE17_WIDTH {64} CONFIG.C_PROBE16_WIDTH {32} CONFIG.C_PROBE15_WIDTH {2} CONFIG.C_NUM_OF_PROBES {43} CONFIG.Component_Name {ila_perf} CONFIG.C_INPUT_PIPE_STAGES {1} CONFIG.ALL_PROBE_SAME_MU_CNT {5}] [get_ips ila_perf] - -create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_mem_inf -set_property -dict [list CONFIG.C_PROBE13_WIDTH {32} CONFIG.C_PROBE10_WIDTH {32} CONFIG.C_PROBE7_WIDTH {23} CONFIG.C_PROBE6_WIDTH {64} CONFIG.C_PROBE3_WIDTH {23} CONFIG.C_PROBE2_WIDTH {64} CONFIG.C_NUM_OF_PROBES {31} CONFIG.Component_Name {ila_mem_inf} CONFIG.C_INPUT_PIPE_STAGES {1}] [get_ips ila_mem_inf] - -create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_network_statistic -set_property -dict [list CONFIG.C_PROBE10_WIDTH {8} CONFIG.C_PROBE9_WIDTH {16} CONFIG.C_PROBE8_WIDTH {16} CONFIG.C_PROBE7_WIDTH {16} CONFIG.C_PROBE6_WIDTH {16} CONFIG.C_PROBE5_WIDTH {16} CONFIG.C_PROBE4_WIDTH {16} CONFIG.C_PROBE3_WIDTH {16} CONFIG.C_PROBE2_WIDTH {16} CONFIG.C_PROBE1_WIDTH {16} CONFIG.C_PROBE0_WIDTH {16} CONFIG.C_NUM_OF_PROBES {11} CONFIG.Component_Name {ila_network_statistic} CONFIG.C_INPUT_PIPE_STAGES {1}] [get_ips ila_network_statistic] - -create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_controller -set_property -dict [list CONFIG.C_PROBE8_WIDTH {16} CONFIG.C_PROBE7_WIDTH {16} CONFIG.C_PROBE6_WIDTH {64} CONFIG.C_PROBE5_WIDTH {32} CONFIG.C_PROBE4_WIDTH {32} CONFIG.C_PROBE3_WIDTH {16} CONFIG.C_PROBE2_WIDTH {16} CONFIG.C_NUM_OF_PROBES {11} CONFIG.Component_Name {ila_controller} CONFIG.C_INPUT_PIPE_STAGES {1}] [get_ips ila_controller] - - -set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/s_axis_tcp_port_status_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xcvu9p_0] -filter {CELL_NAME=~"inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/benchmark_debug"}]] -set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/m_axis_tcp_listen_port_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xcvu9p_0] -filter {CELL_NAME=~"inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/benchmark_debug"}]] -set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/m_axis_tcp_open_connection_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xcvu9p_0] -filter {CELL_NAME=~"inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/benchmark_debug"}]] -set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/m_axis_tcp_read_pkg_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xcvu9p_0] -filter {CELL_NAME=~"inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/benchmark_debug"}]] -set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/m_axis_tcp_tx_meta_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xcvu9p_0] -filter {CELL_NAME=~"inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/benchmark_debug"}]] -set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/running -of_objects [get_hw_ilas -of_objects [get_hw_devices xcvu9p_0] -filter {CELL_NAME=~"inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/benchmark_debug"}]] -set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/s_axis_tcp_notification_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xcvu9p_0] -filter {CELL_NAME=~"inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/benchmark_debug"}]] -set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/s_axis_tcp_open_status_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xcvu9p_0] -filter {CELL_NAME=~"inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/benchmark_debug"}]] -set_property TRIGGER_COMPARE_VALUE {eq1'b1 eq1'b1} [get_hw_probes inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/s_axis_tcp_port_status_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xcvu9p_0] -filter {CELL_NAME=~"inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/benchmark_debug"}]] -set_property TRIGGER_COMPARE_VALUE {eq1'b1 eq1'b1} [get_hw_probes inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/s_axis_tcp_port_status_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xcvu9p_0] -filter {CELL_NAME=~"inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/benchmark_debug"}]] -set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/s_axis_tcp_port_status_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xcvu9p_0] -filter {CELL_NAME=~"inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/benchmark_debug"}]] -set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/s_axis_tcp_rx_meta_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xcvu9p_0] -filter {CELL_NAME=~"inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/benchmark_debug"}]] -set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/s_axis_tcp_tx_status_tvalid -of_objects [get_hw_ilas -of_objects [get_hw_devices xcvu9p_0] -filter {CELL_NAME=~"inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/benchmark_debug"}]] -set_property CONTROL.TRIGGER_CONDITION OR [get_hw_ilas -of_objects [get_hw_devices xcvu9p_0] -filter {CELL_NAME=~"inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/benchmark_debug"}] -startgroup -set_property CONTROL.DATA_DEPTH 16 [get_hw_ilas -of_objects [get_hw_devices xcvu9p_0] -filter {CELL_NAME=~"inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/benchmark_debug"}] -set_property CONTROL.TRIGGER_POSITION 15 [get_hw_ilas -of_objects [get_hw_devices xcvu9p_0] -filter {CELL_NAME=~"inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/benchmark_debug"}] -set_property CONTROL.WINDOW_COUNT 64 [get_hw_ilas -of_objects [get_hw_devices xcvu9p_0] -filter {CELL_NAME=~"inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/benchmark_debug"}] -endgroup -set_property CONTROL.TRIGGER_POSITION 1 [get_hw_ilas -of_objects [get_hw_devices xcvu9p_0] -filter {CELL_NAME=~"inst_dynamic/inst_user_wrapper_0/inst_user_c0_0/user_role/benchmark_debug"}] diff --git a/examples_hw/floorplans/streaming_fplan_u55c.xdc b/examples_hw/floorplans/streaming_fplan_u55c.xdc deleted file mode 100644 index 721bdd1a3..000000000 --- a/examples_hw/floorplans/streaming_fplan_u55c.xdc +++ /dev/null @@ -1,9 +0,0 @@ -create_pblock pblock_inst_user_wrapper_0 -add_cells_to_pblock [get_pblocks pblock_inst_user_wrapper_0] [get_cells -quiet [list inst_shell/inst_dynamic/inst_user_wrapper_0]] -resize_pblock [get_pblocks pblock_inst_user_wrapper_0] -add {SLICE_X0Y660:SLICE_X116Y719} -resize_pblock [get_pblocks pblock_inst_user_wrapper_0] -add {DSP48E2_X0Y258:DSP48E2_X15Y281} -resize_pblock [get_pblocks pblock_inst_user_wrapper_0] -add {RAMB18_X0Y264:RAMB18_X7Y287} -resize_pblock [get_pblocks pblock_inst_user_wrapper_0] -add {RAMB36_X0Y132:RAMB36_X7Y143} -resize_pblock [get_pblocks pblock_inst_user_wrapper_0] -add {URAM288_X0Y176:URAM288_X1Y191} -resize_pblock [get_pblocks pblock_inst_user_wrapper_0] -add {CLOCKREGION_X0Y7:CLOCKREGION_X5Y10 CLOCKREGION_X0Y0:CLOCKREGION_X3Y6} -set_property SNAPPING_MODE ON [get_pblocks pblock_inst_user_wrapper_0] \ No newline at end of file diff --git a/examples_sw/CMakeLists.txt b/examples_sw/CMakeLists.txt deleted file mode 100644 index 4da8133e5..000000000 --- a/examples_sw/CMakeLists.txt +++ /dev/null @@ -1,116 +0,0 @@ -cmake_minimum_required(VERSION 3.5) -project(test) - -set(CYT_DIR ${CMAKE_SOURCE_DIR}/../) -set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CYT_DIR}/cmake) - -find_package(CoyoteSW REQUIRED) - -# -# Pass an additional command-line argument to specify the verbosity of the compilation -# If VERBOSITY is passed as an argument, VERBOSE is set as preprocessor-macro -# - -set(VERBOSITY OFF CACHE BOOL "Enable VERBOSITY for compilation") - -if (VERBOSITY) - message("You selected VERBOSITY for compilation") - add_compile_definitions(VERBOSE) -else() - message("VERBOSITY is not selected for compilation") -endif() - - -# -# Shell reconfiguration -# -if(EXAMPLE STREQUAL "reconfigure_shell") - set(TARGET_DIR "${CYT_DIR}/examples_sw/apps/reconfigure_shell") - message("** Shell load") -endif() - -# -# TEST -# -if(EXAMPLE STREQUAL "perf_gpu") - set(TARGET_DIR "${CYT_DIR}/examples_sw/apps/perf_gpu") - message("** Example: Validation tests - GPU perf") -endif() - -if(EXAMPLE STREQUAL "hls_vadd") - set(TARGET_DIR "${CYT_DIR}/examples_sw/apps/hls_vadd") - message("** Example: HLS vector addition") -endif() - -# -# Example builds -# - -# Used in conjunction with the default shell -if(EXAMPLE STREQUAL "perf_local") - set(TARGET_DIR "${CYT_DIR}/examples_sw/apps/perf_local") - message("** Example: Validation tests - Link perf") -endif() - -if(EXAMPLE STREQUAL "interrupts") - set(TARGET_DIR "${CYT_DIR}/examples_sw/apps/user_interrupts") - message("** Example: User interrupts") -endif() - -# FPGA perf benchmark -if(EXAMPLE STREQUAL "perf_fpga") - set(TARGET_DIR "${CYT_DIR}/examples_sw/apps/perf_fpga") - message("** Example: FPGA perf benchmark") -endif() - -# Streaming services example -if(EXAMPLE STREQUAL "streaming_server") - set(TARGET_DIR "${CYT_DIR}/examples_sw/apps/streaming_service/server") - message("** Example: Streaming service - Server (Coyote daemon)") - include_directories(${TARGET_DIR}/../include ${TARGET_DIR}/include) -endif() - -if(EXAMPLE STREQUAL "streaming_client") - set(TARGET_DIR "${CYT_DIR}/examples_sw/apps/streaming_service/client") - message("** Example: Streaming service - Client") - include_directories(${TARGET_DIR}/../include) -endif() - -if(EXAMPLE STREQUAL "multithreading") - set(TARGET_DIR "${CYT_DIR}/examples_sw/apps/multithreading") - message("** Example: Multithreading") -endif() - -# Network - RDMA -if(EXAMPLE STREQUAL "rdma_server") - set(TARGET_DIR "${CYT_DIR}/examples_sw/apps/rdma_service/server") - message("** Example: RDMA service - Server (Coyote daemon)") - include_directories(${TARGET_DIR}/../include) -endif() - -if(EXAMPLE STREQUAL "rdma_client") - set(TARGET_DIR "${CYT_DIR}/examples_sw/apps/rdma_service/client") - message("** Example: RDMA service - Client") - include_directories(${TARGET_DIR}/../include) -endif() - -# Network - TCP -if(EXAMPLE STREQUAL "tcp_iperf") - set(TARGET_DIR "${CYT_DIR}/examples_sw/apps/tcp_iperf") - message("** Example: TCP - iperf") -endif() - -# -# Create build targets -# -set(EXEC test) -add_executable(${EXEC} ${TARGET_DIR}/main.cpp) -target_link_libraries(${EXEC} PUBLIC Coyote) -target_link_directories(${EXEC} PUBLIC /usr/local/lib) - -if(EN_GPU) - set(AMD_GPU "gfx908" CACHE STRING "AMD GPU device to use") - set_property(TARGET ${EXEC} PROPERTY HIP_ARCHITECTURES ${AMD_GPU}) - set_target_properties(${EXEC} PROPERTIES LINKER_LANGUAGE CXX) - target_link_libraries(${EXEC} PUBLIC hip::device numa pthread drm drm_amdgpu rt dl hsa-runtime64 hsakmt) -endif() \ No newline at end of file diff --git a/examples_sw/apps/streaming_service/client/main.cpp b/examples_sw/apps/streaming_service/client/main.cpp deleted file mode 100644 index 209cd8747..000000000 --- a/examples_sw/apps/streaming_service/client/main.cpp +++ /dev/null @@ -1,142 +0,0 @@ -/** - * Copyright (c) 2021, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cLib.hpp" -#include "types.hpp" - -using namespace std; -using namespace fpga; - -// Runtime -constexpr auto const defRunHLL = false; -constexpr auto const defRunDtrees = false; -constexpr auto const defNTuples = 128 * 1024; -constexpr auto const defNFeatures = 5; - -int main(int argc, char *argv[]) -{ - - - // Read arguments - boost::program_options::options_description programDescription("Options:"); - programDescription.add_options() - ("tuples,t", boost::program_options::value(), "Number of tuples") - ("features,f", boost::program_options::value(), "Number of features") - ("hloglog,h", boost::program_options::value(), "Run HyperLogLog") - ("dtrees,d", boost::program_options::value(), "Run Decision Trees"); - - boost::program_options::variables_map commandLineArgs; - boost::program_options::store(boost::program_options::parse_command_line(argc, argv, programDescription), commandLineArgs); - boost::program_options::notify(commandLineArgs); - - bool runHLL = defRunHLL; - bool runDtrees = defRunDtrees; - uint32_t n_tuples = defNTuples; - uint32_t n_features = defNFeatures; - - if(commandLineArgs.count("hloglog") > 0) runHLL = commandLineArgs["hloglog"].as(); - if(commandLineArgs.count("dtrees") > 0) runDtrees = commandLineArgs["dtrees"].as(); - if(commandLineArgs.count("tuples") > 0) n_tuples = commandLineArgs["tuples"].as(); - if(commandLineArgs.count("features") > 0) n_features = commandLineArgs["features"].as(); - - // - // HyperLogLog operator - // - if(runHLL) { - // Connect to service - cLib clib_hll("/tmp/coyote-daemon-vfid-0-streaming", fidHLL); - - // Let's get some buffers and fill it with some random data ... - uint32_t* dMem = (uint32_t*) memalign(axiDataWidth, n_tuples * defDW); - uint32_t* rMem = (uint32_t*) memalign(axiDataWidth, defDW); - - for(int i = 0; i < n_tuples; i++) { - dMem[i] = rand(); - } - - // Execute the HLL - // This is the only place of interaction with Coyote ... - double cmpl_ev = clib_hll.task(opPriority, (uint64_t)dMem, (uint64_t)rMem, n_tuples); - - PR_HEADER("Hyper-Log-Log"); - std::cout << std::fixed << std::setprecision(2) << std::dec; - std::cout << "Estimation completed, run time: " << cmpl_ev << " us" << std::endl; - std::cout << "Estimated cardinality: " << ((float*)rMem)[0] << std::endl << std::endl; - - free(dMem); - free(rMem); - } - - // - // Decision trees operator - // - if(runDtrees) { - // Connect to service - cLib clib_dtrees("/tmp/coyote-daemon-vfid-0-streaming", fidDtrees); - - // Buffers ... - uint32_t* dMem = (uint32_t*) mmap(NULL, n_tuples * n_features * defDW, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS | MAP_HUGETLB, -1, 0); - uint32_t* rMem = (uint32_t*) memalign(axiDataWidth, n_tuples * defDW); - - for (int i = 0; i < n_tuples; ++i) { - for (int j = 0; j < n_features; ++j) { - dMem[i * n_features + j] = ((float)(i+1))/((float)(j+i+1)); - } - } - - // Execute the Decision trees - // This is the only place of interaction with Coyote ... - double cmpl_ev = clib_dtrees.task(opPriority, (uint64_t)dMem, (uint64_t)rMem, n_tuples, n_features); - - PR_HEADER("GBM Decision Trees"); - std::cout << std::fixed << std::setprecision(2) << std::dec; - std::cout << "Estimation completed, run time: " << cmpl_ev << " us" << std::endl; - std::cout << "Throughput achieved: " << ((double) n_tuples / (double)cmpl_ev) << ", MT/s" << std::endl << std::endl; - - munmap(dMem, n_tuples * n_features * defDW); - munmap(rMem, n_tuples * defDW); - } - - return (EXIT_SUCCESS); -} diff --git a/examples_sw/apps/streaming_service/include/types.hpp b/examples_sw/apps/streaming_service/include/types.hpp deleted file mode 100644 index 0097e4ca7..000000000 --- a/examples_sw/apps/streaming_service/include/types.hpp +++ /dev/null @@ -1,23 +0,0 @@ -#include - -#include "cDefs.hpp" - -#include -#include -#include - -using namespace fpga; - -// Runtime -constexpr auto const fidHLL = 1; -constexpr auto const fidDtrees = 2; - -constexpr auto const operatorHLL = 1; -constexpr auto const operatorDtrees = 2; - -constexpr auto const opPriority = 1; - -constexpr auto const defDevice = 0; -constexpr auto const defTargetVfid = 0; - -constexpr auto const defDW = 4; \ No newline at end of file diff --git a/examples_sw/apps/streaming_service/server/include/gbm_dtrees.hpp b/examples_sw/apps/streaming_service/server/include/gbm_dtrees.hpp deleted file mode 100644 index 65a862df2..000000000 --- a/examples_sw/apps/streaming_service/server/include/gbm_dtrees.hpp +++ /dev/null @@ -1,179 +0,0 @@ -#include - -#include "cDefs.hpp" -#include "cTask.hpp" - -#include -#include -#include - -using namespace fpga; - -void initTrees(uint* trees, int numtrees, int numnodes, int depth); - -// -// Util -// - -/////////////////////////////////////////////////////////////////////////////////////////////////////////////// -/////////////////////////////////////////////////////////////////////////////////////////////////////////////// -/////////////////////////////////////////////////////////////////////////////////////////////////////////////// -/////////////////////////////////////////////////////////////////////////////////////////////////////////////// -uint find_node_index(uint nd, uint* indexes, uint* pnodes) -{ - int parent = nd/2; - - if (nd%2 != 0) return indexes[parent] + 1; - else return indexes[parent-1] + pnodes[parent-1] + 1; - - return 0; -} -/////////////////////////////////////////////////////////////////////////////////////////////////////////////// -/////////////////////////////////////////////////////////////////////////////////////////////////////////////// -/////////////////////////////////////////////////////////////////////////////////////////////////////////////// -/////////////////////////////////////////////////////////////////////////////////////////////////////////////// -uint find_depth(uint nd, uint depth) -{ - uint currLevel = depth -1; - - while(1) - { - int nd1 = pow(2, currLevel) - 1; - - if (nd >= nd1) return currLevel; - else currLevel = currLevel - 1; - } - return 0; -} -/////////////////////////////////////////////////////////////////////////////////////////////////////////////// -/////////////////////////////////////////////////////////////////////////////////////////////////////////////// -/////////////////////////////////////////////////////////////////////////////////////////////////////////////// -/////////////////////////////////////////////////////////////////////////////////////////////////////////////// -void initTrees(uint* trees, int numtrees, int numnodes, int depth) -{ - uint node_t; - uint curr_tree_offset = 0; - - uint* nodes_ids = new uint[numnodes]; - uint* nodes_size = new uint[numnodes]; - uint* indexes = new uint[numnodes]; - uint* pnodes = new uint[numnodes]; - - // set root - nodes_ids[0] = 0; - nodes_size[0] = 2; - indexes[0] = 0; - pnodes[0] = numnodes/2; - - int lastLevelNodeID = numnodes/2; - - for (int i = 1; i < numnodes; ++i) - { - int idx = find_node_index(i, indexes, pnodes); - nodes_ids[idx] = i; - nodes_size[idx] = (i < lastLevelNodeID)? 2 : 10; - indexes[i] = idx; - - uint ndLevel = find_depth(i, depth); - pnodes[i] = pow(2, (depth-1-ndLevel) ) - 1; - } - - for(int i = 0; i < numnodes; i++) printf("(%d, %d)", nodes_ids[i], nodes_size[i]); - printf("\n"); - - delete [] pnodes; - delete [] indexes; - - // - for (int i = 0; i < numtrees; ++i) - { - // initialize tree i - uint tree_i[4096]; - uint node_off = 0; - for (int j = 0; j < numnodes; ++j) - { - // initialize node j; - // Node type - node_t = 0; - - uint op_type = (nodes_ids[j] >= lastLevelNodeID)? 3 : (i%2 == 0)? 0 : 2; - uint left_child = (nodes_ids[j] >= lastLevelNodeID)? 0 : 1; - uint right_child = (nodes_ids[j] >= lastLevelNodeID)? 0 : 1; - uint findex = nodes_ids[j]%25; - uint split_dir = 2; - - uint rc_id = nodes_ids[j]*2 + 2; - - uint rc_off = 0; - for (int f = j+1; f < numnodes; ++f) - { - if (nodes_ids[f] != rc_id) rc_off += nodes_size[f]; - else break; - } - - uint rchild_offset = (nodes_ids[j] >= lastLevelNodeID)? 0 : rc_off; - - node_t = (node_t & 0xFFFFFFFC) | ((op_type << 0) & 0x00000003); - node_t = (node_t & 0xFFFFFFFB) | ((left_child << 2) & 0x00000004); - node_t = (node_t & 0xFFFFFFF7) | ((right_child << 3) & 0x00000008); - node_t = (node_t & 0xFFFFF00F) | ((findex << 4) & 0x00000FF0); - node_t = (node_t & 0xFFFF0FFF) | ((split_dir << 12) & 0x0000F000); - node_t = (node_t & 0x0000FFFF) | ((rchild_offset << 16) & 0xFFFF0000); - - tree_i[node_off] = node_t; - node_off += 1; - - // split value/set - float sval = 1.5; - if (nodes_ids[j] < lastLevelNodeID) - { - if (i%2 == 0) // split value - { - memcpy( &(tree_i[node_off]), &sval, 4); - } - else // small split Set - { - tree_i[node_off] = 0xAAAAAAAA; - } - node_off += 1; - } - else - { - // large split set offset and length - tree_i[node_off] = 0x00000006; - node_off += 1; - // - float val = 2.5; - memcpy( &(tree_i[node_off]), &val, 4); - val = 0.5; - memcpy( &(tree_i[node_off+1]), &val, 4); - - for (int s = 0; s < 6; ++s) // large split set words - { - tree_i[node_off + 2 + s] = 0x55555555; - } - - node_off += 8; - } - - } - // trees - trees[curr_tree_offset] = node_off; - for (uint32_t t = 0; t < node_off; ++t) - { - trees[curr_tree_offset+1+t] = tree_i[t]; - } - - curr_tree_offset += node_off + 1; - - printf("Tree Size = %d\n", curr_tree_offset); - - curr_tree_offset = curr_tree_offset + (((curr_tree_offset%16) != 0)? 16 - (curr_tree_offset%16) : 0); - } - - // - delete [] nodes_ids; - delete [] nodes_size; - - printf("Initialization done!\n"); fflush(stdout); -} diff --git a/examples_sw/apps/streaming_service/server/main.cpp b/examples_sw/apps/streaming_service/server/main.cpp deleted file mode 100644 index d766dc725..000000000 --- a/examples_sw/apps/streaming_service/server/main.cpp +++ /dev/null @@ -1,257 +0,0 @@ -/** - * Copyright (c) 2021, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cService.hpp" -#include "cFunc.hpp" -#include "gbm_dtrees.hpp" -#include "types.hpp" - -using namespace std; -using namespace fpga; - -/** - * @brief Main - * - */ -int main(int argc, char *argv[]) -{ - /* Args */ - boost::program_options::options_description programDescription("Options:"); - programDescription.add_options() - ("device,d", boost::program_options::value(), "Target device") - ("vfid,i", boost::program_options::value(), "Target vFPGA"); - - boost::program_options::variables_map commandLineArgs; - boost::program_options::store(boost::program_options::parse_command_line(argc, argv, programDescription), commandLineArgs); - boost::program_options::notify(commandLineArgs); - - uint32_t cs_dev = defDevice; - uint32_t vfid = defTargetVfid; - - if(commandLineArgs.count("device") > 0) cs_dev = commandLineArgs["device"].as(); - if(commandLineArgs.count("vfid") > 0) vfid = commandLineArgs["vfid"].as(); - - /** - * @brief Load all service functions and start the server - */ - cService *cservice = cService::getInstance("streaming", false, vfid, cs_dev); - std::cout << std::endl << "Shell loading ..." << std::endl << std::endl; - cservice->shellReconfigure("shell_bstream.bin"); - - /** - * @brief Load all operators (partial images) into the scheduler and start the operation - * - */ - - cservice->addBitstream("app_bstream_hloglog.bin", operatorHLL); - cservice->addBitstream("app_bstream_dtrees.bin", operatorDtrees); - - // The Hyper-Log-Log task - cservice->addFunction(fidHLL, std::unique_ptr(new cFunc(operatorHLL, - [=] (cThread *cthread, uint64_t d_mem, uint64_t r_mem, uint32_t n_tuples) -> double { // returns time - void* dMem = (void*) d_mem; - void* rMem = (void*) r_mem; - - syslog(LOG_NOTICE, "Executing HLL task, params: dMem %lx, rMem %lx, tuples %d", (uint64_t)dMem, (uint64_t)rMem, n_tuples); - - // SG entries -------------------------------------------------------------------------------------------------- - // ------------------------------------------------------------------------------------------------------------- - sgEntry sg; - memset(&sg, 0, sizeof(localSg)); - sg.local.src_addr = dMem; sg.local.src_len = n_tuples * defDW; - sg.local.dst_addr = rMem; sg.local.dst_len = defDW; - - // User map ---------------------------------------------------------------------------------------------------- - // ------------------------------------------------------------------------------------------------------------- - cthread->userMap(dMem, n_tuples * defDW); - cthread->userMap(rMem, defDW); - - // Lock vFPGA (scheduler will load the required bitstream if necessary) ---------------------------------------- - // ------------------------------------------------------------------------------------------------------------- - cthread->pLock(operatorHLL, opPriority); - - // Invoke (move the data) -------------------------------------------------------------------------------------- - // ------------------------------------------------------------------------------------------------------------- - auto begin_time = chrono::high_resolution_clock::now(); - cthread->invoke(CoyoteOper::LOCAL_TRANSFER, &sg, {true, true, true}); - auto end_time = chrono::high_resolution_clock::now(); - - // Unlock vFPGA ------------------------------------------------------------------------------------------------ - // ------------------------------------------------------------------------------------------------------------- - cthread->pUnlock(); - - // User unmap - cthread->userUnmap(dMem); - cthread->userUnmap(rMem); - - double time = chrono::duration_cast(end_time - begin_time).count(); - syslog(LOG_NOTICE, "Task HLL executed, time %f", time); - - return { time }; - } - ))); - - // Load Decision trees task - cservice->addFunction(fidDtrees, std::unique_ptr(new cFunc(operatorDtrees, - [=] (cThread *cthread, uint64_t d_mem, uint64_t r_mem, int32_t n_tuples, int32_t n_features) -> double { // returns time - void* dMem = (void*) d_mem; - void* rMem = (void*) r_mem; - - syslog(LOG_NOTICE, "Executing D-trees task, params: dMem %lx, rMem %lx, tuples %d, features %d", (uint64_t)dMem, (uint64_t)rMem, n_tuples, n_features); - - // Prep the dtrees parameters ---------------------------------------------------------------------------------- - // ------------------------------------------------------------------------------------------------------------- - int32_t depth = 5; - int32_t numTrees = 109; - - int32_t result_size = defDW * n_tuples; - int32_t data_size = n_features * n_tuples * defDW; - - uint outputNumCLs = result_size/64 + ((result_size%64 > 0)? 1 : 0); - - unsigned char puTrees = numTrees/28 + ((numTrees%28 == 0)? 0 : 1); - - int numnodes = pow(2, depth) - 1; - int tree_size = 2*(pow(2,depth-1) - 1) + 10*pow(2,depth-1) + 1; - tree_size = tree_size + ( ((tree_size%16) > 0)? 16 - (tree_size%16) : 0); - - int trees_size = tree_size*numTrees*4; - - //uint64_t n_trees_pages = trees_size/hugePageSize + ((trees_size%hugePageSize > 0)? 1 : 0); - short lastOutLineMask = ((n_tuples%16) > 0)? 0xFFFF << (n_tuples%16) : 0x0000; - - // Initialize the trees ---------------------------------------------------------------------------------------- - // ------------------------------------------------------------------------------------------------------------- - std::unique_ptr> cthread_model; - void* tMem; - - // Allocate Trees Memory - try { - // Thread to offload the model - cthread_model = std::make_unique>(vfid, getpid(), cs_dev); - } catch(...) { - return { 0 }; - } - - tMem = cthread_model->getMem({CoyoteAlloc::HPF, (uint32_t)trees_size}); - initTrees(((uint32_t*)(tMem)), numTrees, numnodes, depth); - - // User map ---------------------------------------------------------------------------------------------------- - // ------------------------------------------------------------------------------------------------------------- - cthread->userMap(dMem, n_tuples * n_features * defDW); - cthread->userMap(rMem, n_tuples * defDW); - - // SG entries (prep for model offload) ------------------------------------------------------------------------- - // ------------------------------------------------------------------------------------------------------------- - sgEntry sg; - memset(&sg, 0, sizeof(localSg)); - sg.local.src_addr = tMem; sg.local.src_len = (uint32_t) trees_size; - - // Lock vFPGA (scheduler will load the required bitstream if necessary) ---------------------------------------- - // ------------------------------------------------------------------------------------------------------------- - cthread->pLock(operatorDtrees, opPriority); - - // Set HW kernel params ---------------------------------------------------------------------------------------- - // ------------------------------------------------------------------------------------------------------------- - cthread->setCSR(n_features, 1); - cthread->setCSR(depth, 2); - cthread->setCSR(puTrees, 3); - cthread->setCSR(outputNumCLs, 4); - cthread->setCSR(lastOutLineMask, 5); - cthread->setCSR(0x1, 0); // ap_start - - // Push trees to the FPGA, blocking, returns when all trees have been streamed to the FPGA --------------------- - // ------------------------------------------------------------------------------------------------------------- - //cthread->invoke(cs_invoke); - cthread_model->invoke(CoyoteOper::LOCAL_READ, &sg, {true, true, true}); - - - // Stream data into the FPGA, blocking, initiate transfer in both directions (results writen back) ------------- - // ------------------------------------------------------------------------------------------------------------- - sg.local.src_addr = dMem; // Read - sg.local.src_len = (uint32_t) data_size; - sg.local.dst_addr = rMem; - sg.local.src_len = (uint32_t) result_size; - - auto begin_time = chrono::high_resolution_clock::now(); - cthread->invoke(CoyoteOper::LOCAL_TRANSFER, &sg, {true, true, true}); - auto end_time = chrono::high_resolution_clock::now(); - - // Unlock vFPGA ------------------------------------------------------------------------------------------------ - // ------------------------------------------------------------------------------------------------------------- - cthread->pUnlock(); - - // User unmap -------------------------------------------------------------------------------------------------- - // ------------------------------------------------------------------------------------------------------------- - cthread->userUnmap(dMem); - cthread->userUnmap(rMem); - cthread_model->freeMem(tMem); - - double time = chrono::duration_cast(end_time - begin_time).count(); - syslog(LOG_NOTICE, "Task D-trees executed, time %f", time); - - return { time }; - }))); - - // - // Start a daemon - // - std::cout << "Forking ..." << std::endl << std::endl; - cservice->start(); -} - diff --git a/examples_sw/apps/tcp_iperf/main.cpp b/examples_sw/apps/tcp_iperf/main.cpp deleted file mode 100644 index 0980a55b7..000000000 --- a/examples_sw/apps/tcp_iperf/main.cpp +++ /dev/null @@ -1,179 +0,0 @@ -/** - * Copyright (c) 2021, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "cDefs.hpp" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "cBench.hpp" -#include "cThread.hpp" - -using namespace std; -using namespace std::chrono; -using namespace fpga; - -/* Def params */ -constexpr auto const defDevice = 0; -constexpr auto const targetRegion = 0; -constexpr auto const freq = 300; // MHz - -/** - * @brief TCP benchmarking - * - */ -int main(int argc, char *argv[]) -{ - // --------------------------------------------------------------- - // Initialization - // --------------------------------------------------------------- - // const char* masterAddr = "10.1.212.121"; - - // Read arguments - boost::program_options::options_description programDescription("Options:"); - programDescription.add_options() - ("device,d", boost::program_options::value(), "Device") - ("useConn,c", boost::program_options::value(), "Number of connections") - ("useIpAddr,i", boost::program_options::value(), "Number of IP addresses") - ("port,p", boost::program_options::value(), "Port number") - ("pkgWordCount,w", boost::program_options::value(), "Number of 512-bit work in a packet") - ("timeInSeconds,t", boost::program_options::value(), "Time in second") - ("transferBytes,b", boost::program_options::value(), "TransferBytes") - ("server,s", boost::program_options::value(), "Run as iperf server") - ("target,r", boost::program_options::value(), "Target IP"); - - boost::program_options::variables_map commandLineArgs; - boost::program_options::store(boost::program_options::parse_command_line(argc, argv, programDescription), commandLineArgs); - boost::program_options::notify(commandLineArgs); - - // Stat - uint32_t cs_dev = defDevice; - uint32_t target_ip = 0x0A01D498; - uint64_t useConn = 1; - uint64_t useIpAddr = 1; - uint64_t port = 5001; - uint64_t pkgWordCount = 64; - uint64_t timeInSeconds = 1; - uint64_t timeInCycles; - uint64_t dualModeEn = 64; - uint64_t packetGap = 0; - uint64_t server = 0; - uint64_t transferBytes = 1024; - - // Runs - char const* env_var_ip = std::getenv("FPGA_0_IP_ADDRESS"); - if(env_var_ip == nullptr) - throw std::runtime_error("Local IP address not provided"); - - string local_ip(env_var_ip); - if(commandLineArgs.count("device") > 0) cs_dev = commandLineArgs["device"].as(); - if(commandLineArgs.count("useConn") > 0) useConn = commandLineArgs["useConn"].as(); - if(commandLineArgs.count("useIpAddr") > 0) useIpAddr = commandLineArgs["useIpAddr"].as(); - if(commandLineArgs.count("port") > 0) port = commandLineArgs["port"].as(); - if(commandLineArgs.count("pkgWordCount") > 0) pkgWordCount = commandLineArgs["pkgWordCount"].as(); - if(commandLineArgs.count("timeInSeconds") > 0) timeInSeconds = commandLineArgs["timeInSeconds"].as(); - if(commandLineArgs.count("server") > 0) server = commandLineArgs["server"].as(); - if(commandLineArgs.count("transferBytes") > 0) transferBytes = commandLineArgs["transferBytes"].as(); - if(commandLineArgs.count("target") > 0) target_ip = commandLineArgs["target"].as(); - - timeInCycles = timeInSeconds * freq * 1000000; - - printf("usecon:%ld, useIP:%ld, pkgWordCount:%ld,port:%ld, local ip:%s, target ip:%x, time:%ld, is server:%ld, transferBytes:%ld\n", useConn, useIpAddr, pkgWordCount, port, local_ip, target_ip, timeInCycles, server, transferBytes); - - // FPGA handles - cThread cthread(targetRegion, getpid(), cs_dev); - -/** - * -- Register map - * 0 (WO) : Control - * 1 (RO) : Status - * 2 (RW) : useConn - * 3 (RW) : useIpAddr - * 4 (RW) : pkgWordCount - * 5 (RW) : basePort - * 6 (RW) : baseIpAddr - * 7 (RW) : transferSize - * 8 (RW) : isServer - * 9 (RW) : timeInSeconds - * 10 (RW) : timeInCycles - * 11 (R) : execution_cycles - * 12 (R) : consumed_bytes - * 13 (R) : produced_bytes - * 14 (R) : openCon_cycles - */ - cthread.setCSR(useConn, 2); - cthread.setCSR(useIpAddr, 3); - cthread.setCSR(pkgWordCount, 4); - cthread.setCSR(port, 5); - cthread.setCSR(target_ip, 6); - cthread.setCSR(transferBytes, 7); - cthread.setCSR(server, 8); - cthread.setCSR(timeInSeconds, 9); - cthread.setCSR(timeInCycles, 10); - std::cout << "Start" << std::endl; - auto start = std::chrono::high_resolution_clock::now(); - - //set the control bit to start the kernel - cthread.setCSR(1, 0); - - //Probe the done signal - while (cthread.getCSR(1) != 1) {} - // std::this_thread::sleep_for(1s); - - auto end = std::chrono::high_resolution_clock::now(); - double durationUs = 0.0; - durationUs = (std::chrono::duration_cast(end - start).count() / 1000.0); - cout<< "Experiment finished durationUs: " << durationUs << endl; - - if(server == 0) { - uint64_t tx_bytes = cthread.getCSR(13); - uint64_t openCon_cycles = cthread.getCSR(14); - uint64_t total_cycles = cthread.getCSR(11); - uint64_t cycles = (total_cycles - openCon_cycles) / 2; - - cout << "tx_bytes: " << tx_bytes << " open con cycles: " << openCon_cycles << " total_cycles: " << total_cycles << " single trip transfer cycle: " << cycles << endl; - double throughput = (double)tx_bytes * 8.0 * freq / ((double)cycles*1000.0); - double latency = (double)cycles / freq; - cout << "throughput [gbps]: " << throughput << " latency[us]: " << latency << endl; - } - - return EXIT_SUCCESS; -} - From 8fa45f0fe80b58377e3dd1effc9040603d5f12a5 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Thu, 8 May 2025 03:46:19 +0200 Subject: [PATCH 02/52] changed the linked network service (submodule) --- .gitmodules | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitmodules b/.gitmodules index be6de654e..2d31cd238 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,4 +1,4 @@ [submodule "hw/services/network"] path = hw/services/network - url = https://github.com/fpgasystems/fpga-network-stack.git + url = https://github.com/pomsi/fpga-network-stack.git branch = coyote-TCP-RDMA From 801198829a2f612c83149dd2f59160c5d000b3b4 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Wed, 21 May 2025 04:49:16 +0200 Subject: [PATCH 03/52] forward ecn to flow control --- hw/hdl/network/rdma/roce_stack.sv | 3 +++ scripts/wr_hdl/template_gen/lynx_pkg_tmplt.txt | 5 ++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/hdl/network/rdma/roce_stack.sv b/hw/hdl/network/rdma/roce_stack.sv index 543aa530f..299b6a509 100644 --- a/hw/hdl/network/rdma/roce_stack.sv +++ b/hw/hdl/network/rdma/roce_stack.sv @@ -122,6 +122,9 @@ assign rdma_ack.data.ack.dest = ack_meta_data[32+RDMA_QPN_BITS+1+:DEST_BITS]; assign rdma_ack.data.ack.strm = ack_meta_data[32+RDMA_QPN_BITS+1+DEST_BITS+:STRM_BITS]; assign rdma_ack.data.ack.rsrvd = 0; assign rdma_ack.data.last = ack_meta_data[32+RDMA_QPN_BITS+1+DEST_BITS+STRM_BITS+:1]; +//MT added +assign rdma_ack.data.ecn = ack_meta_data[32+RDMA_QPN_BITS+1+DEST_BITS+STRM_BITS+1+:ECN_BITS]; + rdma_flow inst_rdma_flow ( .aclk(nclk), diff --git a/scripts/wr_hdl/template_gen/lynx_pkg_tmplt.txt b/scripts/wr_hdl/template_gen/lynx_pkg_tmplt.txt index bb4344bf6..ac52c24ea 100644 --- a/scripts/wr_hdl/template_gen/lynx_pkg_tmplt.txt +++ b/scripts/wr_hdl/template_gen/lynx_pkg_tmplt.txt @@ -194,6 +194,8 @@ package lynxTypes; parameter integer STRM_RDMA = 2; parameter integer STRM_TCP = 3; + parameter integer ECN_BITS = 2; //MT added + // Queue depth parameter integer QUEUE_DEPTH = 8; @@ -427,7 +429,8 @@ package lynxTypes; logic [DEST_BITS-1:0] dest; logic [PID_BITS-1:0] pid; logic [DEST_BITS-1:0] vfid; - logic [32-OPCODE_BITS-STRM_BITS-2-DEST_BITS-PID_BITS-DEST_BITS-1:0] rsrvd; + logic [ECN_BITS-1:0] ecn; // MT added + logic [32-OPCODE_BITS-STRM_BITS-2-DEST_BITS-PID_BITS-DEST_BITS-ECN_BITS-1:0] rsrvd; } ack_t; typedef struct packed { From 7eb956008f45dea2355c577eee6a168b866a6078 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Thu, 29 May 2025 01:27:28 +0200 Subject: [PATCH 04/52] bug fix --- hw/hdl/network/rdma/roce_stack.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/hdl/network/rdma/roce_stack.sv b/hw/hdl/network/rdma/roce_stack.sv index 299b6a509..c768d2965 100644 --- a/hw/hdl/network/rdma/roce_stack.sv +++ b/hw/hdl/network/rdma/roce_stack.sv @@ -123,7 +123,7 @@ assign rdma_ack.data.ack.strm = ack_meta_data[32+RDMA_QPN_BITS+1+DEST_BITS+:STRM assign rdma_ack.data.ack.rsrvd = 0; assign rdma_ack.data.last = ack_meta_data[32+RDMA_QPN_BITS+1+DEST_BITS+STRM_BITS+:1]; //MT added -assign rdma_ack.data.ecn = ack_meta_data[32+RDMA_QPN_BITS+1+DEST_BITS+STRM_BITS+1+:ECN_BITS]; +assign rdma_ack.data.ack.ecn = ack_meta_data[32+RDMA_QPN_BITS+1+DEST_BITS+STRM_BITS+1+:ECN_BITS]; rdma_flow inst_rdma_flow ( From 98e5cdea27cedd90bcc0f7bcd64da648f0bf4905 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Thu, 5 Jun 2025 12:38:49 +0200 Subject: [PATCH 05/52] added ila cores (hopefully) --- hw/hdl/network/rdma/init_ip.tcl | 2 ++ hw/hdl/network/rdma/roce_stack.sv | 11 ++++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) create mode 100644 hw/hdl/network/rdma/init_ip.tcl diff --git a/hw/hdl/network/rdma/init_ip.tcl b/hw/hdl/network/rdma/init_ip.tcl new file mode 100644 index 000000000..a65554048 --- /dev/null +++ b/hw/hdl/network/rdma/init_ip.tcl @@ -0,0 +1,2 @@ +create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_rdma +set_property -dict [list CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_NUM_OF_PROBES {5} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_rdma] \ No newline at end of file diff --git a/hw/hdl/network/rdma/roce_stack.sv b/hw/hdl/network/rdma/roce_stack.sv index c768d2965..117ecd8ec 100644 --- a/hw/hdl/network/rdma/roce_stack.sv +++ b/hw/hdl/network/rdma/roce_stack.sv @@ -107,7 +107,8 @@ always_comb begin end // -// FC and CQ +// FC and CQ .probe0(s_rdma_qp_interface.valid), + // metaIntf #(.STYPE(dack_t)) rdma_ack (); @@ -223,6 +224,14 @@ assign rdma_wr_req.ready = m_rdma_wr_req.ready; // RoCE stack // +ila_rdma inst_ila_rdma ( + .clk(nclk), + .probe6(rdma_ack.valid), + .probe7(rdma_ack.ready), + .probe8(rdma_ack.data.ack), // 32 + .probe9(rdma_ack.data.last), +); + /* ila_rdma inst_ila_rdma ( .clk(nclk), .probe0(s_rdma_qp_interface.valid), From e03ba0da458c4e3d02bd960d4d19158a0a5e764d Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Thu, 5 Jun 2025 15:06:10 +0200 Subject: [PATCH 06/52] typos --- hw/hdl/network/rdma/roce_stack.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/hdl/network/rdma/roce_stack.sv b/hw/hdl/network/rdma/roce_stack.sv index 117ecd8ec..6e3204fc9 100644 --- a/hw/hdl/network/rdma/roce_stack.sv +++ b/hw/hdl/network/rdma/roce_stack.sv @@ -226,10 +226,10 @@ assign rdma_wr_req.ready = m_rdma_wr_req.ready; ila_rdma inst_ila_rdma ( .clk(nclk), - .probe6(rdma_ack.valid), - .probe7(rdma_ack.ready), - .probe8(rdma_ack.data.ack), // 32 - .probe9(rdma_ack.data.last), + .probe0(rdma_ack.valid), + .probe1(rdma_ack.ready), + .probe2(rdma_ack.data.ack), // 32 + .probe3(rdma_ack.data.last) ); /* ila_rdma inst_ila_rdma ( From 381749e480e0222154d5c0f865596f930ae38187 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Thu, 5 Jun 2025 16:38:10 +0200 Subject: [PATCH 07/52] ila fix try --- hw/hdl/network/rdma/init_ip.tcl | 2 -- scripts/ip_inst/network_infrastructure.tcl | 13 +++++++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) delete mode 100644 hw/hdl/network/rdma/init_ip.tcl diff --git a/hw/hdl/network/rdma/init_ip.tcl b/hw/hdl/network/rdma/init_ip.tcl deleted file mode 100644 index a65554048..000000000 --- a/hw/hdl/network/rdma/init_ip.tcl +++ /dev/null @@ -1,2 +0,0 @@ -create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_rdma -set_property -dict [list CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_NUM_OF_PROBES {5} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_rdma] \ No newline at end of file diff --git a/scripts/ip_inst/network_infrastructure.tcl b/scripts/ip_inst/network_infrastructure.tcl index 54f21485e..952dfdb7e 100644 --- a/scripts/ip_inst/network_infrastructure.tcl +++ b/scripts/ip_inst/network_infrastructure.tcl @@ -131,6 +131,19 @@ if {$cfg(en_rdma) eq 1} { create_ip -name rocev2 -vendor ethz.systems.fpga -library hls -version 0.82 -module_name rocev2_ip } +# MT_pomsarc added +create_ip -name rdma_ack -vendor xilinx.com -library ip -version 2.0 -module_name ila_rdma_ack +set_property -dict [list + CONFIG.C_NUM_OF_PROBES {4} + CONFIG.C_DATA_DEPTH {2048} + CONFIG.C_INPUT_PIPE_STAGES {2} + CONFIG.C_PROBE0_WIDTH {1} + CONFIG.C_PROBE1_WIDTH {1} + CONFIG.C_PROBE2_WIDTH {32} + CONFIG.C_PROBE3_WIDTH {1} +] [get_ips ila_rdma_ack] + + # Cmd create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_req_512_used set_property -dict [list CONFIG.TDATA_NUM_BYTES {64} CONFIG.FIFO_DEPTH {32} CONFIG.HAS_WR_DATA_COUNT {1} ] [get_ips axis_data_fifo_req_512_used] From ba5fbdf27b5965aea090d872b1e328314b74785e Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Thu, 5 Jun 2025 16:45:23 +0200 Subject: [PATCH 08/52] ... --- hw/hdl/network/rdma/roce_stack.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/hdl/network/rdma/roce_stack.sv b/hw/hdl/network/rdma/roce_stack.sv index 6e3204fc9..5cd9a80f2 100644 --- a/hw/hdl/network/rdma/roce_stack.sv +++ b/hw/hdl/network/rdma/roce_stack.sv @@ -224,7 +224,8 @@ assign rdma_wr_req.ready = m_rdma_wr_req.ready; // RoCE stack // -ila_rdma inst_ila_rdma ( +//MT_pomsarc added +ila_rdma_ack inst_ila_rdma_ack ( .clk(nclk), .probe0(rdma_ack.valid), .probe1(rdma_ack.ready), From 0c3323e18af2bec44792202764ca793bbcb95acd Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Thu, 5 Jun 2025 16:57:08 +0200 Subject: [PATCH 09/52] :q --- scripts/ip_inst/common_infrastructure.tcl | 12 ++++++++++++ scripts/ip_inst/network_infrastructure.tcl | 12 ------------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/scripts/ip_inst/common_infrastructure.tcl b/scripts/ip_inst/common_infrastructure.tcl index c03818ee3..83d5c380d 100644 --- a/scripts/ip_inst/common_infrastructure.tcl +++ b/scripts/ip_inst/common_infrastructure.tcl @@ -190,3 +190,15 @@ eval $cmd create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axisr_data_fifo_512 set cmd "set_property -dict \[list CONFIG.TDATA_NUM_BYTES {64} CONFIG.FIFO_DEPTH {$nn512} CONFIG.HAS_TKEEP {1} CONFIG.HAS_TLAST {1} CONFIG.TID_WIDTH {6}] \[get_ips axisr_data_fifo_512]" eval $cmd + +# MT_pomsarc added +create_ip -name ila -vendor xilinx.com -library ip -version 2.0 -module_name ila_rdma_ack +set_property -dict [list + CONFIG.C_NUM_OF_PROBES {4} + CONFIG.C_DATA_DEPTH {2048} + CONFIG.C_INPUT_PIPE_STAGES {2} + CONFIG.C_PROBE0_WIDTH {1} + CONFIG.C_PROBE1_WIDTH {1} + CONFIG.C_PROBE2_WIDTH {32} + CONFIG.C_PROBE3_WIDTH {1} +] [get_ips ila_rdma_ack] diff --git a/scripts/ip_inst/network_infrastructure.tcl b/scripts/ip_inst/network_infrastructure.tcl index 952dfdb7e..4c7ed2d15 100644 --- a/scripts/ip_inst/network_infrastructure.tcl +++ b/scripts/ip_inst/network_infrastructure.tcl @@ -131,18 +131,6 @@ if {$cfg(en_rdma) eq 1} { create_ip -name rocev2 -vendor ethz.systems.fpga -library hls -version 0.82 -module_name rocev2_ip } -# MT_pomsarc added -create_ip -name rdma_ack -vendor xilinx.com -library ip -version 2.0 -module_name ila_rdma_ack -set_property -dict [list - CONFIG.C_NUM_OF_PROBES {4} - CONFIG.C_DATA_DEPTH {2048} - CONFIG.C_INPUT_PIPE_STAGES {2} - CONFIG.C_PROBE0_WIDTH {1} - CONFIG.C_PROBE1_WIDTH {1} - CONFIG.C_PROBE2_WIDTH {32} - CONFIG.C_PROBE3_WIDTH {1} -] [get_ips ila_rdma_ack] - # Cmd create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_data_fifo_req_512_used From 86384ea5bdd2acfb8f36cafc8f3f8581191c382e Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Mon, 23 Jun 2025 01:14:04 +0200 Subject: [PATCH 10/52] safety backup --- scripts/ip_inst/common_infrastructure.tcl | 11 ----------- scripts/ip_inst/network_infrastructure.tcl | 6 +++++- 2 files changed, 5 insertions(+), 12 deletions(-) diff --git a/scripts/ip_inst/common_infrastructure.tcl b/scripts/ip_inst/common_infrastructure.tcl index 83d5c380d..f7157bd4f 100644 --- a/scripts/ip_inst/common_infrastructure.tcl +++ b/scripts/ip_inst/common_infrastructure.tcl @@ -191,14 +191,3 @@ create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -modu set cmd "set_property -dict \[list CONFIG.TDATA_NUM_BYTES {64} CONFIG.FIFO_DEPTH {$nn512} CONFIG.HAS_TKEEP {1} CONFIG.HAS_TLAST {1} CONFIG.TID_WIDTH {6}] \[get_ips axisr_data_fifo_512]" eval $cmd -# MT_pomsarc added -create_ip -name ila -vendor xilinx.com -library ip -version 2.0 -module_name ila_rdma_ack -set_property -dict [list - CONFIG.C_NUM_OF_PROBES {4} - CONFIG.C_DATA_DEPTH {2048} - CONFIG.C_INPUT_PIPE_STAGES {2} - CONFIG.C_PROBE0_WIDTH {1} - CONFIG.C_PROBE1_WIDTH {1} - CONFIG.C_PROBE2_WIDTH {32} - CONFIG.C_PROBE3_WIDTH {1} -] [get_ips ila_rdma_ack] diff --git a/scripts/ip_inst/network_infrastructure.tcl b/scripts/ip_inst/network_infrastructure.tcl index 4c7ed2d15..090314bc7 100644 --- a/scripts/ip_inst/network_infrastructure.tcl +++ b/scripts/ip_inst/network_infrastructure.tcl @@ -579,4 +579,8 @@ set_property -dict [list CONFIG.TDATA_NUM_BYTES {4} CONFIG.FIFO_DEPTH {128} ] [g #create_ip -name dhcp_client -vendor xilinx.labs -library hls -version 1.05 -module_name dhcp_client_ip -#update_compile_order -fileset sources_1 \ No newline at end of file +#update_compile_order -fileset sources_1 + +# MT_pomsarc added +create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_rdma_ack +set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_NUM_OF_PROBES {4} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_rdma_ack] From 71f8bc99f1673d3aa76996d7afd055deb28c9776 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Fri, 4 Jul 2025 17:33:40 +0200 Subject: [PATCH 11/52] test --- hw/hdl/network/rdma/roce_stack.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/hdl/network/rdma/roce_stack.sv b/hw/hdl/network/rdma/roce_stack.sv index 5cd9a80f2..2342707f7 100644 --- a/hw/hdl/network/rdma/roce_stack.sv +++ b/hw/hdl/network/rdma/roce_stack.sv @@ -123,8 +123,8 @@ assign rdma_ack.data.ack.dest = ack_meta_data[32+RDMA_QPN_BITS+1+:DEST_BITS]; assign rdma_ack.data.ack.strm = ack_meta_data[32+RDMA_QPN_BITS+1+DEST_BITS+:STRM_BITS]; assign rdma_ack.data.ack.rsrvd = 0; assign rdma_ack.data.last = ack_meta_data[32+RDMA_QPN_BITS+1+DEST_BITS+STRM_BITS+:1]; -//MT added -assign rdma_ack.data.ack.ecn = ack_meta_data[32+RDMA_QPN_BITS+1+DEST_BITS+STRM_BITS+1+:ECN_BITS]; +//MT added changr back +assign rdma_ack.data.ack.ecn = 3;//ack_meta_data[32+RDMA_QPN_BITS+1+DEST_BITS+STRM_BITS+1+:ECN_BITS]; rdma_flow inst_rdma_flow ( From b5dd9dd4d6b8a69e4fed23cee8bd0783f9bf6399 Mon Sep 17 00:00:00 2001 From: pomsarc Date: Sat, 19 Jul 2025 18:11:17 +0200 Subject: [PATCH 12/52] added readable parts :) --- .../rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv | 170 ++++++++++++++++++ hw/hdl/network/rdma/roce_stack.sv | 4 +- 2 files changed, 172 insertions(+), 2 deletions(-) create mode 100644 hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv new file mode 100644 index 000000000..208e9f6a4 --- /dev/null +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv @@ -0,0 +1,170 @@ +import lynxTypes::*; + +module cc_queue +( + input logic aclk, + input logic aresetn, + + input logic ecn_mark, + input logic ecn_valid, + output logic ecn_ready, + + + metaIntf.s s_req, + metaIntf.m m_req +); + +localparam integer RDMA_N_OST = RDMA_N_WR_OUTSTANDING; +localparam integer RDMA_OST_BITS = $clog2(RDMA_N_OST); +localparam integer RD_OP = 0; +localparam integer WR_OP = 1; + +localparam integer Rt_default = 100000; +localparam integer Rc_default = 100000; +localparam integer N_min_time_between_ecn_marks = 50; +localparam integer Rai = 50; + +localparam integer S1 = 128; // 1 << 8 +localparam integer Sg = 8; // (1/16) << 8 +localparam integer F = 5; + +localparam integer time_threshhold = 100; +localparam integer byte_threshhold = 10; + + + +logic[31:0] Rt; +logic[31:0] Rc; +logic[31:0] Sa; +logic[31:0] timer; + +logic[31:0] timer_send_rate; + +logic[31:0] time_of_last_marked_packet; +logic[31:0] time_last_update; + +logic[31:0] byte_counter; +logic[31:0] time_counter; + +logic[4:0] step_counter; + + +//typedef enum logic[2:0] {ST_IDLE, ST_CALC_SR, ST_ADD_TO_QUEUE} state_t; +logic [2:0] state_C, state_N; +metaIntf #(.STYPE(dreq_t)) queue_in(); +metaIntf #(.STYPE(dreq_t)) queue_out(); + +logic ecn_data; + + + + +always_ff @(posedge aclk) begin + if (aresetn == 1'b0) begin + state_C <= ST_IDLE; + + Rt <= Rt_default; + Rc <= Rc_default; + Sa <= S1; + timer <= 0; + + timer_send_rate = 0; + + byte_counter <= 0; + time_counter <= 0 + + ecn_ready <= 1; + + step_counter <= 0; + + + end + else begin + timer <= timer + 1; + time_counter = time_counter + 1; + + ecn_ready <= 1'b0; + ecn_data <= ecn_mark; + + s_ack.ready <= 1'b0; + + s_req.ready <= 1'b0; + req_out.valid <= 1'b0; + req_out.data <= s_req.data; + + if(ecn_valid) begin + ecn_ready <= 1'b1; + byte_counter <= bytecounter + 1; + if(ecn_data == 1'b1) begin // Marked Packet arrived + if(timer - time_last_update > N_min_time_between_ecn_marks) begin + Rt <= Rc; + Rc <= (Rc << 8) / (S1 - (Sa>>1)); + alpha <= (((S1-Sg)*Sa)>> 8) + Sg; + time_last_update <= timer + end + time_of_last_marked_packet <= timer + end + end + + if (timer - time_of_last_marked_packet > N_min_time_between_ecn_marks) begin + alpha <= (((S1-Sg)*alpha)>> 8); + + end + + if(time_counter >= F || byte_counter >= F) begin + + if(time_counter >= F && byte_counter >=F) begin + // case Hyper Increse + // Still missing + // + + time_counter <= 0; + byte_counter <= 0; + end + else begin + // case Additive Increase + Rt <= Rt + Rai; + Rc <= (Rt + Rc) >> 1; + if(time_counter >= F)begin + time_counter <= 0; + end + else begin + byte_counter <= 0; + end + end + else begin + // case Fast Recovery + Rc = (Rt + Rc) >> 1 + end + + + + + + + if(s_req.valid & queue_in.ready) begin + if(timer_send_rate > Rc) begin + timer_send_rate <= 0; + req_out.valid <= 1'b1; + s_req.ready <= 1'b1; + end + end + + + end +end +end + + + +queue_meta #( + .QDEPTH(RDMA_N_OST) +) inst_cq ( + .aclk(aclk), + .aresetn(aresetn), + .s_meta(queue_in), + .m_meta(m_req) +); + + +endmodule \ No newline at end of file diff --git a/hw/hdl/network/rdma/roce_stack.sv b/hw/hdl/network/rdma/roce_stack.sv index 2342707f7..3a90c7800 100644 --- a/hw/hdl/network/rdma/roce_stack.sv +++ b/hw/hdl/network/rdma/roce_stack.sv @@ -123,8 +123,8 @@ assign rdma_ack.data.ack.dest = ack_meta_data[32+RDMA_QPN_BITS+1+:DEST_BITS]; assign rdma_ack.data.ack.strm = ack_meta_data[32+RDMA_QPN_BITS+1+DEST_BITS+:STRM_BITS]; assign rdma_ack.data.ack.rsrvd = 0; assign rdma_ack.data.last = ack_meta_data[32+RDMA_QPN_BITS+1+DEST_BITS+STRM_BITS+:1]; -//MT added changr back -assign rdma_ack.data.ack.ecn = 3;//ack_meta_data[32+RDMA_QPN_BITS+1+DEST_BITS+STRM_BITS+1+:ECN_BITS]; +//MT_pomsarc added +assign rdma_ack.data.ack.ecn = ack_meta_data[32+RDMA_QPN_BITS+1+DEST_BITS+STRM_BITS+1+:ECN_BITS]; rdma_flow inst_rdma_flow ( From 8f54baff008329495f5a4b85ef36db496d98d94c Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Fri, 8 Aug 2025 05:24:59 +0200 Subject: [PATCH 13/52] added DCQCN bench --- examples/MT_pomsarc_09_CC_Testbench/README.md | 186 ++++++++++++++++ .../hw/CMakeLists.txt | 32 +++ .../hw/src/init_ip.tcl | 2 + .../hw/src/vfpga_top.svh | 71 +++++++ .../img/rdma_results_read.png | Bin 0 -> 130953 bytes .../img/rdma_results_write.png | Bin 0 -> 131862 bytes .../img/rdma_system_overview.svg | 1 + .../img/rdma_traffic_pattern.svg | 1 + .../sw/CMakeLists.txt | 26 +++ .../sw/src/client/main.cpp | 140 ++++++++++++ .../sw/src/include/constants.hpp | 9 + .../sw/src/server/main.cpp | 118 +++++++++++ .../rdma/MT_pomsarc_CC_queue_wrapper.sv | 199 ++++++++++++++++++ hw/hdl/network/rdma/MT_pomsarc_benchy.sv | 135 ++++++++++++ hw/hdl/network/rdma/MT_pomsarc_new _flow.sv | 189 +++++++++++++++++ scripts/ip_inst/network_infrastructure.tcl | 3 + 16 files changed, 1112 insertions(+) create mode 100644 examples/MT_pomsarc_09_CC_Testbench/README.md create mode 100644 examples/MT_pomsarc_09_CC_Testbench/hw/CMakeLists.txt create mode 100644 examples/MT_pomsarc_09_CC_Testbench/hw/src/init_ip.tcl create mode 100644 examples/MT_pomsarc_09_CC_Testbench/hw/src/vfpga_top.svh create mode 100644 examples/MT_pomsarc_09_CC_Testbench/img/rdma_results_read.png create mode 100644 examples/MT_pomsarc_09_CC_Testbench/img/rdma_results_write.png create mode 100644 examples/MT_pomsarc_09_CC_Testbench/img/rdma_system_overview.svg create mode 100644 examples/MT_pomsarc_09_CC_Testbench/img/rdma_traffic_pattern.svg create mode 100644 examples/MT_pomsarc_09_CC_Testbench/sw/CMakeLists.txt create mode 100644 examples/MT_pomsarc_09_CC_Testbench/sw/src/client/main.cpp create mode 100644 examples/MT_pomsarc_09_CC_Testbench/sw/src/include/constants.hpp create mode 100644 examples/MT_pomsarc_09_CC_Testbench/sw/src/server/main.cpp create mode 100644 hw/hdl/network/rdma/MT_pomsarc_CC_queue_wrapper.sv create mode 100644 hw/hdl/network/rdma/MT_pomsarc_benchy.sv create mode 100644 hw/hdl/network/rdma/MT_pomsarc_new _flow.sv diff --git a/examples/MT_pomsarc_09_CC_Testbench/README.md b/examples/MT_pomsarc_09_CC_Testbench/README.md new file mode 100644 index 000000000..f5387b7fd --- /dev/null +++ b/examples/MT_pomsarc_09_CC_Testbench/README.md @@ -0,0 +1,186 @@ +# Coyote Example 8: Using the FPGA as a SmartNIC for Remote Direct Memory Access (RDMA) +Welcome to the eigth Coyote example! If you've made it to this point, you've already learnt all the essential concepts of FPGA-CPU interaction for data movement and control flow. Thus, we're adding a new component by demonstrating how Coyote can be used to turn the FPGA into a SmartNIC for 100G RDMA-over-Converged-Ethernet (RoCE v2), allowing for efficient, high-performance data exchange between remote processing nodes and FPGA-offloaded preprocessing of the data streams. As with all Coyote examples, a brief description of the core Coyote concepts covered in this example is included below. + +##### Table of Contents +[RDMA Overview](#rdma-overview) + +[Example Overview](#example-overview) + +[Hardware Concepts](#hardware-concepts) + +[Software Concepts](#software-concepts) + +[Additional Information](#additional-information) + +## RDMA Overview +Remote Direct Memory Access over Converged Ethernet (RoCE v2) is a high-performance networking protocol originally developed for High-Performance Computing. It aims to combine high throughput, low latency and low CPU-utilization by offloading the network stack and direct memory access to the Network Interface Card (NIC), thus grounding its performance claims on host-bypassing and zero-copy: applications running on the host CPUs directly expose memory buffers for DMA to the NIC, so that data can be exchanged without including the host CPU or the OS running on it. In this example, we demonstrate how Coyote can be configured to use the FPGA in the role of such a NIC, allowing for fully protocol-compliant RoCE v2-traffic at 100 Gbps. +For further understanding of the RDMA example, we need to shed some light on the intrinsics of this network standard. +For RDMA communication, two nodes are connected via a so-called Queue Pair (QP), based on previously exchanged information such as respective IP-addresses, location and size of the allocated memory buffers and access keys, and comprising of the idea of queues for work commands and data. The initial exchange of RDMA operations are managed through so-called InfiniBand-verbs, which describe the form of memory transaction between the remote nodes. We have to separate between *one-sided operations* that initiate data transfers over the network without a previous request for consent, and *two-sided operations* where every data transaction is preceeded by an additional exchange between the communicating nodes. Coyote implements the two one-sided RDMA operations: +- ```RDMA WRITE```: One node writes data of certain length to a remote buffer in the other node. Every sent WRITE packet has to be explicitly acked by the receiving node. +- ```RDMA READ```: One node requests to read data of certain length from a remote buffer in the other node. The READ REQUEST packet is implicitly ACK'ed when the remote node sends back RDMA RESPONSE packets with the requested data. + +**IMPORTANT TERMINOLOGY:** +To have a better understanding of this example and the following descriptions, a short overview of the RDMA-specific terminology is very helpful: +- *QPN*: Queue Pair Number. Identifies a RDMA connection between two remote nodes. +- *vaddr*: Virtual address of the remote exposed buffer. For setting up a Queue Pair, a node has to share the virtual address of its exposed buffer with the remote node. +- *rkey*: Remote key for accessing the exposed buffer of the remote node. The remote key is communicated alongside the virtual address as a form of access control. +- *PSN*: Packet Sequence Number used to organize and structure a communication flow between remote RDMA-nodes. Normally, PSN-sequencing is handled by the FPGA-offloaded network stack and thus is not visible to the user. However, following the PSN order is very helpful for debugging RDMA networks. The initial PSN is agreed upon between the remote nodes as part of the initialization of the QP. +- *MTU*: Maximum Transmission Unit, defines the maximum size of a packet. Since RDMA operates on the notion of buffer transmission, the length of the data to be transmitted determines the number of MTU-sized packets that are required for the operation. While the MTU is a compile-time parameter in Coyote, the default size is 4 KB. This means that a ```RDMA WRITE``` of a buffer of up to 4 KB size results in a single packet with ```RDMA WRITE ONLY``` opcode, while a buffer of 8 KB size would be transmitted in two packets, one carrying ```RDMA WRITE FIRST```, the other with ```RDMA WRITE LAST```. For even longer buffers, an arbitrary number of ```RDMA WRITE MIDDLE``` packets is inserted in the exchange. + +## Example Overview +This example measures throughput and latency of RDMA data exchange between two remode nodes via a 100G switched network with both ```RDMA WRITE``` and ```RDMA READ``` operations. Assuming the simpler write functionality, we can very generally think about the process as moving of a data buffer from the host CPU to the local FPGA, where it is streamed to the FPGA-offloaded RDMA stack and then sent via the network to the remote FPGA. There, data is received and then written to the previously specified address of the remote buffer of this remote host CPU. Different to all previous examples, this requires two servers with FPGAs, which also run different software application. The active node, which initiates communication exchange, is referred to as the "client", while the remote node is used as "server". An example of the dataflow is given in the figure below; and as shown in the figure, the steps are the following: +1) *QP Exchange*: As explained above, the RDMA connection in form of a Queue Pair needs to be set up between the remote nodes before the actual benchmarking test can begin. Since RDMA cannot be bootstrapped, this requires out-of-band communication between the two remote CPUs via classic TCP sockets. In the context of the HACC, we are using the 10G management network for this purpose. Using ```ifconfig```, the IP address of the CPU determined to be the server can be evaluated and then given to the experiment code as a parameter. The two nodes follow a standardized protocol to exchange relevant start-up information, such as the IP- addresses of the FPGAs in the 100G data network, the initial PSN and the address and access key of the network exposed data buffers. +2) *QP Setup*: After having exchanged these essential pieces of information, both CPUs forward the aggregated QP data to the FPGAs to create the endpoints of the RDMA flow in the hardware-offloaded network stack. This means making information such as the target IP address or buffer virtual address retrievable by the QPN as essential key. +3) *REMOTE WRITE*: In case of a WRITE-based benchmark, the client now begins with a ```REMOTE WRITE``` Coyote operation to transmit a local buffer via the network to the remote node. For this, both data and commands traverse the RDMA-allocated vFGPA and reach the RDMA stack on the FPGA, where RoCE v2 packets are created and then sent out via the network. +4) *Receiving data*: In the above example, the server FPGA receives the incoming RDMA packets and automatically checks for correctness of the PSN-sequence and QP-specific information. If the received packet fits into the expected communication flow, it gets ACK'ed: an ```RDMA ACK``` is sent back to the client as a reply. At the same time, the server FPGA sends the received data as a ```LOCAL WRITE``` (see Example 1) to the local buffer on the CPU. +5) *Processing ACKs & creating completions*: The client FPGA is constantly listening to the network for ACKs for its outstanding packets. If an ACK is received, the original work command for this transaction is marked as completed, which is also communicated to the local client CPU. If no ACK is received within a certain time interval after sending out a packet, a retransmission is issued. In this case, the same packet is sent again, assuming that it was originally lost in the network or not properly received by the server. + +

+ +Generally speaking, throughput and latency tests behave vastly different, also depending on the chosen mode of operation (WRITE vs. READ). The different cases are depicted in the figure below and can be understood as following: +- *Latency* for ```RDMA WRITE```: The client issues a single WRITE of a buffer of specified length to the remote server. Upon reception, the server ACKs and then writes back this very buffer to the client, thus creating a typical "ping-pong pattern" of communication, for which the two-way latency can be measured from sending out a buffer to receiving it back. Depending on the specified experimental arguments, this exchange is repeated for a certain number of times before the average latency of all transmissions is reported. +- *Throughput* for ```RDMA WRITE```: The client issues *n* WRITEs (depending on specification of the argument in experiment execution) of a buffer of specified length to the remote server and waits for all required ACKs. Upon reception, the server writes back the same buffer *n* times again. +- *Latency* for ```RDMA READ```: The client issues a single READ of a buffer of specified length from the remote server. Instead of ACK'ing the server sends the requested data via ```RDMA READ RESPONSEs```. +- *Throughput* for ```RDMA READ``` In this case, the client issues *n* READs (depending on specification of the argument in experiment execution) of a buffer of specified length from the remote server and waits for data delivery via ```RDMA READ RESPONSEs``` from there. The server in this case does not issue reflective READs to the client. + +
+ +
+ +**IMPORTANT:** When executing RDMA benchmarks, it's important to always start the server's software first before doing the same on the client. The reason for this lies in the intrinsics of the QP exchange: The server software is constructed to listening for incoming TCP connections from the client to then take the passive role in the off-channel exchange of information. + + +## Hardware Concepts +The core complexity for RDMA in Coyote is hidden from the user within the network stack. The RDMA-dedicated vFPGA is mainly used for connecting interfaces without any additional user logic required. +The previously introduced send- and receive-queues are connected as following in the vFPGA: +```Verilog +always_comb begin + /* + * CONTROL SIGNALS + * + * rq_(wr|rd) are two more Coyote interfaces, which act as inputs to the user application + * They corresponds to network write/read requests, set from the host software and driver + * Here, they are used to set Coyote's generic send queues, previously discussed in Example 7. + */ + // Write + sq_wr.valid = rq_wr.valid; + rq_wr.ready = sq_wr.ready; + sq_wr.data = rq_wr.data; // Data field holds information such as remote, virtual address, buffer length etc. + sq_wr.data.strm = STRM_HOST; // For RDMA, by definition data is always on the host + sq_wr.data.dest = is_opcode_rd_resp(rq_wr.data.opcode) ? 0 : 1; + + // Reads + sq_rd.valid = rq_rd.valid; + rq_rd.ready = sq_rd.ready; + sq_rd.data = rq_rd.data; // Data field holds information such as remote, virtual address, buffer length etc. + sq_rd.data.strm = STRM_HOST; // For RDMA, by definition data is always on the host + sq_rd.data.dest = 1; +end +``` + +On the other hand, the data interfaces are connected as following in the module: + +```Verilog +/* + * DATA SIGNALS + * + */ +// Data streams for outgoing RDMA WRITEs (from local host to network stack to remote node) +`AXISR_ASSIGN(axis_host_recv[0], axis_rreq_send[0]) + +// Data streams for incoming RDMA READ RESPONSEs (from remote node to network stack to local host) +`AXISR_ASSIGN(axis_rreq_recv[0], axis_host_send[0]) + +// Data streams for outgoing RDMA READ RESPONSEs (from local host to network stack to remote node) +`AXISR_ASSIGN(axis_host_recv[1], axis_rrsp_send[0]) + +// Data streams for incoming RDMA WRITEs (from remote node to network stack to local host) +`AXISR_ASSIGN(axis_rrsp_recv[0], axis_host_send[1]) +``` + +Thinking one step further, beyond the scope of this performance benchmark, it becomes obvious how any pipelined user logic can be placed on these interfaces to process incoming or outgoing RDMA traffic. Placing customized user logic directly on these datapaths is one of the key benefits of a FPGA-based SmartNIC such as Coyote with the network configuration. + + +## Software Concepts +As described above, the main notion of logic abstraction in RDMA is the Queue-Pair (QP), which connects two remote nodes. Both nodes first form their own local Queue, which again is directly linked to the memory buffer that is exposed via the network. Afterwards, an off-channel exchange via TCP/IP is started to exchange the local queues and then form a QP. + +In Coyote, the notion of a QP is directly linked to a ``coyoteThread``. Thus, the first step of setting up RDMA in Coyote is creating such a thread: +```C++ +coyote::cThread coyote_thread(DEFAULT_VFPGA_ID, getpid(), 0); +```` + +Following the creation of the thread, it's necessary to call the function ```initRDMA()```, which allocates an RDMA buffer of the requested size and performs the QP exchange between the client and server. Importantly, the client needs to pass the server's IP address, while the server code leaves this field blank (nullptr, indicating that it's the server). The function return a pointer to the memory buffer to be used for RDMA communication. +```C++ +int *mem = (int *) coyote_thread.initRDMA(max_size, coyote::defPort, server_ip.c_str()); +``` + +After the setup is completed, we follow the standard approach in Coyote: creating a scatter-gather entry and issuing an ``ìnvoke(...)``` call, but this time indicating a remote operation: +```C++ +coyote::sgEntry sg; +sg.rdma = { .len = curr_size }; +coyote_thread.invoke(coyote::CoyoteOper::REMOTE_RDMA_WRITE, &sg); +``` + + +## Additional Information + +### Special remarks on building Coyote for RDMA experiments +Since different software versions are required for server and client to run a benchmark, two cmake builds have to be triggered to obtain the correct executables. In order to build the server code, one needs to specify `-DINSTANCE=server`, while a build of the client software is specified with `-DINSTANCE=client`: +```bash +cd sw/ + +mkdir build_server && cd build_server +cmake ../../ -DINSTANCE=server && make + +cd ../ +mkdir build_client && cd build_client +cmake ../../ -DINSTANCE=client && make +``` + +### Command line parameters and hints on running the experiment +As said above, it's crucial to start the software for experiments first on the node that we want to use as server, before doing the same for the client. Furthermore, it's important that the IP address specified as argument on the client machine **belongs to the server-CPU (not the client CPU, not the server FPGA)**. The different available network interfaces can be explored with ```ifconfig```. +The following description helps to match the relevant command line parameters to details of the experiment execution described before: + +- `[--ip_address | -i] ` IP address of the server CPU for out-of-band QP-exchange via TCP-sockets before the actual RDMA experiment can begin. +- `[--operation | -o] ` Decides whether the benchmark is performed for WRITE (1) or READ (0) operations. Default: 0 +- `[--min_size | -x] ` Minimum size of transferred buffer in the experiment. Default: 64 [B] +- `[--max_size | -X] ` Maximum size of transferred buffer in the experiment. Default: 1048576 [B] ~ 1 [MB] +- `[--runs | -r] ` Number of test runs, to obtain statistically significant results For latency-tests, `r` ping-pong exchanges will be executed. For throughput tests, `r` independent exchanges of 64 messages are executed. + +### Network debugging +Coyote provides tooling to check the status of network transmissions and identify potential problems, most notable packet losses and retransmissions. These statistics can be queried via +`cat /sys/kernel/coyote_sysfs_0/cyt_attr_nstats`. + +A typical output for this could look like this: +``` + -- NET STATS QSFP0 + +RX pkgs: 316 +TX pkgs: 242 +ARP RX pkgs: 4 +ARP TX pkgs: 2 +ICMP RX pkgs: 0 +ICMP TX pkgs: 0 +TCP RX pkgs: 0 +TCP TX pkgs: 0 +ROCE RX pkgs: 245 +ROCE TX pkgs: 240 +IBV RX pkgs: 240 +IBV TX pkgs: 240 +PSN drop cnt: 0 +Retrans cnt: 0 +TCP session cnt: 0 +STRM down: 0 +``` +In this case, 240 RDMA packets have been received and sent (``IBV RX/TX``), no packet has been lost or retransmitted. A major problem would be indicated by ``STRM down: 1``, as this would signal a complete shutdown of the networking stack. In such a case, only a hard reset including reprogramming the FPGA can save the user. +Apart from these Coyote-provided utilities, standard network debugging tools such as switch- or external NIC-based traffic capturing can be used to understand traffic issues and patterns. As described in the next example, we also offer a 100G-capable traffic sniffer for Coyote that directly produces pcap-files compatible to any standard network analysis tool such as wireshark. If even this low-level debugging capabilities are not deemed satisfactory, also classic ILA-based probing directly on data- and controlpaths of the FPGA-design is possible. + +### Expeted results +The following results are expected for reads (left) and writes (right): + +

+ + +

\ No newline at end of file diff --git a/examples/MT_pomsarc_09_CC_Testbench/hw/CMakeLists.txt b/examples/MT_pomsarc_09_CC_Testbench/hw/CMakeLists.txt new file mode 100644 index 000000000..e729f3666 --- /dev/null +++ b/examples/MT_pomsarc_09_CC_Testbench/hw/CMakeLists.txt @@ -0,0 +1,32 @@ +# CMake configuration +cmake_minimum_required(VERSION 3.5) +set(CYT_DIR ${CMAKE_SOURCE_DIR}/../../../) +set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CYT_DIR}/cmake) +find_package(CoyoteHW REQUIRED) + +project(example_08_perf_rdma) +message("*** Coyote Example 8: Remote Direct Memory Access (RDMA) [Hardware Build] ***") + +# Enables two streams from host memory (1 for requests, 1 for response) +set(EN_STRM 1) +set(N_STRM_AXI 2) + +# Incldue Coyote's RDMA stack during synthesis +set(EN_RDMA 1) + +# Number of vFPGAs (user applications) +set(N_REGIONS 1) + +# Build with optimization, since timing closure with RDMA can be difficult +set(BUILD_OPT 1) + +# Confirm that the selected options are allowed +validation_checks_hw() + +# Load a user application in Configuration #0, Region #0 +load_apps ( + VFPGA_C0_0 "src" +) + +# Create the hardware project +create_hw() diff --git a/examples/MT_pomsarc_09_CC_Testbench/hw/src/init_ip.tcl b/examples/MT_pomsarc_09_CC_Testbench/hw/src/init_ip.tcl new file mode 100644 index 000000000..64dc40e3d --- /dev/null +++ b/examples/MT_pomsarc_09_CC_Testbench/hw/src/init_ip.tcl @@ -0,0 +1,2 @@ +create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_perf_rdma +set_property -dict [list CONFIG.C_PROBE17_WIDTH {128} CONFIG.C_PROBE14_WIDTH {128} CONFIG.C_NUM_OF_PROBES {18} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_perf_rdma] \ No newline at end of file diff --git a/examples/MT_pomsarc_09_CC_Testbench/hw/src/vfpga_top.svh b/examples/MT_pomsarc_09_CC_Testbench/hw/src/vfpga_top.svh new file mode 100644 index 000000000..240e06b7e --- /dev/null +++ b/examples/MT_pomsarc_09_CC_Testbench/hw/src/vfpga_top.svh @@ -0,0 +1,71 @@ +always_comb begin + /* + * CONTROL SIGNALS + * + * rq_(wr|rd) are two more Coyote interfaces, which act as inputs to the user application + * They corresponds to network write/read requests, set from the host software and driver + * Here, they are used to set Coyote's generic send queues, previously discussed in Example 7. + */ + // Write + sq_wr.valid = rq_wr.valid; + rq_wr.ready = sq_wr.ready; + sq_wr.data = rq_wr.data; // Data field holds information such as remote, virtual address, buffer length etc. + sq_wr.data.strm = STRM_HOST; // For RDMA, by definition data is always on the host + sq_wr.data.dest = is_opcode_rd_resp(rq_wr.data.opcode) ? 0 : 1; + + // Reads + sq_rd.valid = rq_rd.valid; + rq_rd.ready = sq_rd.ready; + sq_rd.data = rq_rd.data; // Data field holds information such as remote, virtual address, buffer length etc. + sq_rd.data.strm = STRM_HOST; // For RDMA, by definition data is always on the host + sq_rd.data.dest = 1; +end + +/* + * DATA SIGNALS + * + */ +// Data streams for outgoing RDMA WRITEs (from local host to network stack to remote node) +`AXISR_ASSIGN(axis_host_recv[0], axis_rreq_send[0]) + +// Data streams for incoming RDMA READ RESPONSEs (from remote node to network stack to local host) +`AXISR_ASSIGN(axis_rreq_recv[0], axis_host_send[0]) + +// Data streams for outgoing RDMA READ RESPONSEs (from local host to network stack to remote node) +`AXISR_ASSIGN(axis_host_recv[1], axis_rrsp_send[0]) + +// Data streams for incoming RDMA WRITEs (from remote node to network stack to local host) +`AXISR_ASSIGN(axis_rrsp_recv[0], axis_host_send[1]) + +// Tie off unused interfaces +always_comb axi_ctrl.tie_off_s(); +always_comb notify.tie_off_m(); +always_comb cq_rd.tie_off_s(); +always_comb cq_wr.tie_off_s(); + +// ILA for debugging +ila_perf_rdma inst_ila_perf_rdma ( + .clk(aclk), + .probe0(axis_host_recv[0].tvalid), // 1 + .probe1(axis_host_recv[0].tready), // 1 + .probe2(axis_host_recv[0].tlast), // 1 + + .probe3(axis_host_recv[1].tvalid), // 1 + .probe4(axis_host_recv[1].tready), // 1 + .probe5(axis_host_recv[1].tlast), // 1 + + .probe6(axis_host_send[0].tvalid), // 1 + .probe7(axis_host_send[0].tready), // 1 + .probe8(axis_host_send[0].tlast), // 1 + + .probe9(axis_host_send[1].tvalid), // 1 + .probe10(axis_host_send[1].tready), // 1 + .probe11(axis_host_send[1].tlast), // 1 + + .probe12(sq_wr.valid), // 1 + .probe13(sq_wr.ready), // 1 + .probe14(sq_wr.data), // 128 + .probe15(sq_rd.valid), // 1 + .probe16(sq_rd.ready), // 1 + .probe17(sq_rd.data) // 128 +); diff --git a/examples/MT_pomsarc_09_CC_Testbench/img/rdma_results_read.png b/examples/MT_pomsarc_09_CC_Testbench/img/rdma_results_read.png new file mode 100644 index 0000000000000000000000000000000000000000..efc149483e13286d8c1704987b5085e0bb1f47c4 GIT binary patch literal 130953 zcmeFZRaBhM5;%wjx1b@xNzj48f?Lqw76|Tx1a}`GxCe*ePH=a3CwOpo*TLDz_07G% zm)(8XhyQTqOn==~UESqf{T+f8fvrbIg!bS?XFkKg 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vaddr…34OUTGOING: Command & DataREMOTEWRITEdata={1, 2, 3, …}INCOMING: Command & DataLOCAL WRITEdata={1, 2, 3, …}5INCOMING: CompletionDataHeader \ No newline at end of file diff --git a/examples/MT_pomsarc_09_CC_Testbench/img/rdma_traffic_pattern.svg b/examples/MT_pomsarc_09_CC_Testbench/img/rdma_traffic_pattern.svg new file mode 100644 index 000000000..cc7223ad0 --- /dev/null +++ b/examples/MT_pomsarc_09_CC_Testbench/img/rdma_traffic_pattern.svg @@ -0,0 +1 @@ +LATENCYTHROUGHPUTRDMA WRITERDMA READCPUFPGACPUFPGACPUFPGACPUFPGACPUFPGACPUFPGACPUFPGACPUFPGARDMA WRITEACKRDMA WRITEACKRDMA WRITE…RDMA WRITERDMA WRITEACKACKRDMA WRITERDMA WRITE…READ REQUESTREAD RESPONSE…READ REQUESTREAD REQUESTREAD REQUESTREAD RESPONSEREAD RESPONSEREAD RESPONSEREAD REQUESTREAD RESPONSE \ No newline at end of file diff --git a/examples/MT_pomsarc_09_CC_Testbench/sw/CMakeLists.txt b/examples/MT_pomsarc_09_CC_Testbench/sw/CMakeLists.txt new file mode 100644 index 000000000..c3e977433 --- /dev/null +++ b/examples/MT_pomsarc_09_CC_Testbench/sw/CMakeLists.txt @@ -0,0 +1,26 @@ +# CMake configuration +cmake_minimum_required(VERSION 3.5) +project(example_08_perf_rdma) + +set(CYT_DIR ${CMAKE_SOURCE_DIR}/../../../) +set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CYT_DIR}/cmake) +find_package(CoyoteSW REQUIRED) + +# Add source files +set(INSTANCE "client" CACHE STRING "RDMA software build targe: client or server") +if(INSTANCE STREQUAL "server") + set(TARGET_DIR "${CMAKE_SOURCE_DIR}/src/server") + message("*** Coyote Example 8: RDMA Server [Software Build] ***") + include_directories("${CMAKE_SOURCE_DIR}/src/include") +endif() +if(INSTANCE STREQUAL "client") + set(TARGET_DIR "${CMAKE_SOURCE_DIR}/src/client") + message("*** Coyote Example 8: RDMA Client [Software Build] ***") + include_directories("${CMAKE_SOURCE_DIR}/src/include") +endif() + +# Create build targets and link against required libraries +set(EXEC test) +add_executable(${EXEC} ${TARGET_DIR}/main.cpp) +target_link_libraries(${EXEC} PUBLIC Coyote) +target_link_directories(${EXEC} PUBLIC /usr/local/lib) diff --git a/examples/MT_pomsarc_09_CC_Testbench/sw/src/client/main.cpp b/examples/MT_pomsarc_09_CC_Testbench/sw/src/client/main.cpp new file mode 100644 index 000000000..1f2dbac0a --- /dev/null +++ b/examples/MT_pomsarc_09_CC_Testbench/sw/src/client/main.cpp @@ -0,0 +1,140 @@ +/** + * Copyright (c) 2021-2024, Systems Group, ETH Zurich + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +// External library for easier parsing of CLI arguments by the executable +#include + +// Coyote-specific includes +#include "cBench.hpp" +#include "cThread.hpp" +#include "constants.hpp" + +constexpr bool const IS_CLIENT = true; + +double run_bench( + coyote::cThread &coyote_thread, coyote::sgEntry &sg, + int *mem, uint transfers, uint n_runs, bool operation +) { + // When writing, the server asserts the written payload is correct (which the client sets) + // When reading, the client asserts the read payload is correct (which the server sets) + for (int i = 0; i < sg.rdma.len / sizeof(int); i++) { + mem[i] = operation ? i : 0; + } + + // Before every benchmark, clear previous completion flags and sync with server + // Sync is in a way equivalent to MPI_Barrier() + auto prep_fn = [&]() { + coyote_thread.clearCompleted(); + coyote_thread.connSync(IS_CLIENT); + }; + + /* Benchmark function; as eplained in the README + * For RDMA_WRITEs, the client writes multiple times to the server and then the server writes the same content back + * For RDMA READs, the client reads from the server multiple times + * In boths cases, that means there will be n_transfers completed writes to local memory (LOCAL_WRITE) + */ + coyote::CoyoteOper coyote_operation = operation ? coyote::CoyoteOper::REMOTE_RDMA_WRITE : coyote::CoyoteOper::REMOTE_RDMA_READ; + auto bench_fn = [&]() { + for (int i = 0; i < transfers; i++) { + coyote_thread.invoke(coyote_operation, &sg); + } + + while (coyote_thread.checkCompleted(coyote::CoyoteOper::LOCAL_WRITE) != transfers) {} + }; + + // Execute benchmark + coyote::cBench bench(n_runs, 0); + bench.execute(bench_fn, prep_fn); + + // Functional correctness check + if (!operation) { + for (int i = 0; i < sg.rdma.len / sizeof(int); i++) { + assert(mem[i] == i); + } + } + + // For writes, divide by 2, since that is sent two ways (from client to server and then from server to client) + // Reads are one way, so no need to scale + return bench.getAvg() / (1. + (double) operation); +} + +int main(int argc, char *argv[]) { + // CLI arguments + bool operation; + std::string server_ip; + unsigned int min_size, max_size, n_runs; + + boost::program_options::options_description runtime_options("Coyote Perf RDMA Options"); + runtime_options.add_options() + ("ip_address,i", boost::program_options::value(&server_ip), "Server's IP address") + ("operation,o", boost::program_options::value(&operation)->default_value(false), "Benchmark operation: READ(0) or WRITE(1)") + ("runs,r", boost::program_options::value(&n_runs)->default_value(10), "Number of times to repeat the test") + ("min_size,x", boost::program_options::value(&min_size)->default_value(64), "Starting (minimum) transfer size") + ("max_size,X", boost::program_options::value(&max_size)->default_value(1 * 1024 * 1024), "Ending (maximum) transfer size"); + boost::program_options::variables_map command_line_arguments; + boost::program_options::store(boost::program_options::parse_command_line(argc, argv, runtime_options), command_line_arguments); + boost::program_options::notify(command_line_arguments); + + PR_HEADER("CLI PARAMETERS:"); + std::cout << "Server's TCP address: " << server_ip << std::endl; + std::cout << "Benchmark operation: " << (operation ? "WRITE" : "READ") << std::endl; + std::cout << "Number of test runs: " << n_runs << std::endl; + std::cout << "Starting transfer size: " << min_size << std::endl; + std::cout << "Ending transfer size: " << max_size << std::endl << std::endl; + + /* Coyote completely abstracts the complexity behind exchanging QPs and setting up an RDMA connection + * Instead, given a cThread, the target RDMA buffer size and the remote server's TCP address, + * One can use the function initRDMA, which will allocate the buffer and + * Exchange the necessary information with the server; the server calls the equivalent function but without the IP address + */ + coyote::cThread coyote_thread(DEFAULT_VFPGA_ID, getpid(), 0); + int *mem = (int *) coyote_thread.initRDMA(max_size, coyote::defPort, server_ip.c_str()); + if (!mem) { throw std::runtime_error("Could not allocate memory; exiting..."); } + + // Benchmark sweep of latency and throughput + PR_HEADER("RDMA BENCHMARK: CLIENT"); + unsigned int curr_size = max_size; + std::cout << "Size: " << std::setw(8) << curr_size << "; "; + + coyote::sgEntry sg; + sg.rdma = { .len = curr_size }; + + double throughput_time = run_bench(coyote_thread, sg, mem, N_THROUGHPUT_REPS, n_runs, operation); + double throughput = ((double) N_THROUGHPUT_REPS * (double) curr_size) / (1024.0 * 1024.0 * throughput_time * 1e-9); + std::cout << "Average throughput: " << std::setw(8) << throughput << " MB/s; "; + + double latency_time = run_bench(coyote_thread, sg, mem, N_LATENCY_REPS, n_runs, operation); + std::cout << "Average latency: " << std::setw(8) << latency_time / 1e3 << " us" << std::endl; + + // Final sync and exit + coyote_thread.connSync(IS_CLIENT); + return EXIT_SUCCESS; +} \ No newline at end of file diff --git a/examples/MT_pomsarc_09_CC_Testbench/sw/src/include/constants.hpp b/examples/MT_pomsarc_09_CC_Testbench/sw/src/include/constants.hpp new file mode 100644 index 000000000..225739d5f --- /dev/null +++ b/examples/MT_pomsarc_09_CC_Testbench/sw/src/include/constants.hpp @@ -0,0 +1,9 @@ +// Constants shared by both client and server; +// Placed in separate file to avoid any weird changes in one file not reflect in the other + +// Benchmark parameters +#define N_LATENCY_REPS 1 +#define N_THROUGHPUT_REPS 64 + +// Default vFPGA to assign cThreads to; for designs with one region (vFPGA) this is the only possible value +#define DEFAULT_VFPGA_ID 0 \ No newline at end of file diff --git a/examples/MT_pomsarc_09_CC_Testbench/sw/src/server/main.cpp b/examples/MT_pomsarc_09_CC_Testbench/sw/src/server/main.cpp new file mode 100644 index 000000000..20b6b984e --- /dev/null +++ b/examples/MT_pomsarc_09_CC_Testbench/sw/src/server/main.cpp @@ -0,0 +1,118 @@ +/** + * Copyright (c) 2021-2024, Systems Group, ETH Zurich + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +// External library for easier parsing of CLI arguments by the executable +#include + +// Coyote-specific includes +#include "cThread.hpp" +#include "constants.hpp" + +constexpr bool const IS_CLIENT = false; + +void run_bench( + coyote::cThread &coyote_thread, coyote::sgEntry &sg, + int *mem, uint transfers, uint n_runs, bool operation +) { + // When writing, the server asserts the written payload is correct (which the client sets) + // When reading, the client asserts the read payload is correct (which the server sets) + for (int i = 0; i < sg.rdma.len / sizeof(int); i++) { + mem[i] = operation ? 0 : i; + } + + for (int i = 0; i < n_runs; i++) { + // Clear previous completion flags and sync with client + coyote_thread.clearCompleted(); + coyote_thread.connSync(IS_CLIENT); + + // For writes, wait until client has written the targer number of messages; then write them back + if (operation) { + while (coyote_thread.checkCompleted(coyote::CoyoteOper::LOCAL_WRITE) != transfers) {} + + for (int i = 0; i < transfers; i++) { + coyote_thread.invoke(coyote::CoyoteOper::REMOTE_RDMA_WRITE, &sg); + } + // For reads, the server is completely passive + } else { + + } + } + + // Functional correctness check + if (operation) { + for (int i = 0; i < sg.rdma.len / sizeof(int); i++) { + assert(mem[i] == i); + } + } +} + +int main(int argc, char *argv[]) { + // CLI arguments + bool operation; + unsigned int min_size, max_size, n_runs; + + boost::program_options::options_description runtime_options("Coyote Perf RDMA Options"); + runtime_options.add_options() + ("operation,o", boost::program_options::value(&operation)->default_value(false), "Benchmark operation: READ(0) or WRITE(1)") + ("runs,r", boost::program_options::value(&n_runs)->default_value(10), "Number of times to repeat the test") + ("min_size,x", boost::program_options::value(&min_size)->default_value(64), "Starting (minimum) transfer size") + ("max_size,X", boost::program_options::value(&max_size)->default_value(1 * 1024 * 1024), "Ending (maximum) transfer size"); + boost::program_options::variables_map command_line_arguments; + boost::program_options::store(boost::program_options::parse_command_line(argc, argv, runtime_options), command_line_arguments); + boost::program_options::notify(command_line_arguments); + + PR_HEADER("CLI PARAMETERS:"); + std::cout << "Benchmark operation: " << (operation ? "WRITE" : "READ") << std::endl; + std::cout << "Number of test runs: " << n_runs << std::endl; + std::cout << "Starting transfer size: " << min_size << std::endl; + std::cout << "Ending transfer size: " << max_size << std::endl << std::endl; + + // Allocate Coyothe threa and set-up RDMA connections, buffer etc. + // initRDMA is explained in more detail in client/main.cpp + coyote::cThread coyote_thread(DEFAULT_VFPGA_ID, getpid(), 0); + int *mem = (int *) coyote_thread.initRDMA(max_size, coyote::defPort); + if (!mem) { throw std::runtime_error("Could not allocate memory; exiting..."); } + + // Benchmark sweep; exactly like done in the client code + PR_HEADER("RDMA BENCHMARK: SERVER"); + unsigned int curr_size = min_size; + while(curr_size <= max_size) { + coyote::sgEntry sg; + sg.rdma = { .len = curr_size }; + run_bench(coyote_thread, sg, mem, N_THROUGHPUT_REPS, n_runs, operation); + run_bench(coyote_thread, sg, mem, N_LATENCY_REPS, n_runs, operation); + curr_size *= 2; + } + + // Final sync and exit + coyote_thread.connSync(IS_CLIENT); + return EXIT_SUCCESS; +} \ No newline at end of file diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_queue_wrapper.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_queue_wrapper.sv new file mode 100644 index 000000000..ceb193d54 --- /dev/null +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_queue_wrapper.sv @@ -0,0 +1,199 @@ +import lynxTypes::*; + +module cc_queue +( + input logic aclk, + input logic aresetn, + + input logic ecn_mark, + input logic ecn_valid, + output logic ecn_ready, + + + metaIntf.s s_req, + metaIntf.m m_req +); + +localparam integer RDMA_N_OST = RDMA_N_WR_OUTSTANDING; +localparam integer RDMA_OST_BITS = $clog2(RDMA_N_OST); +localparam integer RD_OP = 0; +localparam integer WR_OP = 1; + +localparam integer Rt_default = 100000; +localparam integer Rc_default = 100000; +localparam integer N_min_time_between_ecn_marks = 50; +localparam integer Rai = 50; +localparam integer g = 8; +localparam integer F = 5; + +localparam integer time_threshhold = 100; +localparam integer byte_threshhold = 10; + +logic[31:0] Rt; +logic[31:0] Rc; +logic[31:0] alpha; +logic[31:0] timer; + +logic[31:0] timer_send_rate; + +logic[31:0] time_of_last_marked_packet; +logic[31:0] time_last_update; + +logic[31:0] byte_counter; +logic[31:0] time_counter; + +logic[4:0] step_counter; + + +//typedef enum logic[2:0] {ST_IDLE, ST_CALC_SR, ST_ADD_TO_QUEUE} state_t; +logic [2:0] state_C, state_N; +metaIntf #(.STYPE(dreq_t)) queue_in(); +metaIntf #(.STYPE(dreq_t)) queue_out(); + +logic ecn_data; + + + + +always_ff @(posedge aclk) begin + if (aresetn == 1'b0) begin + state_C <= ST_IDLE; + + Rt <= Rt_default; + Rc <= Rc_default; + alpha <= 1; + timer <= 0; + + timer_send_rate = 0; + + byte_counter <= 0; + time_counter <= 0 + + ecn_ready <= 1; + + step_counter <= 0; + + + end + else begin + timer <= timer + 1; + time_counter = time_counter + 1; + + ecn_ready <= 1'b0; + ecn_data <= ecn_mark; + + s_ack.ready <= 1'b0; + + s_req.ready <= 1'b0; + req_out.valid <= 1'b0; + req_out.data <= s_req.data; + + if(ecn_valid) begin + ecn_ready <= 1'b1; + byte_counter <= bytecounter + 1; + if(ecn_data == 1'b1) begin // Marked Packet arrived + Rt = Rc; + Rc = Rc(1-(alpha/2)); + alpha = (1-g)*alpha+g; + end + end + + if(time_counter >) + + + if(s_req.valid & queue_in.ready) begin + if(timer_send_rate > Rc) begin + timer_send_rate = 0; + req_out.valid = 1'b1; + s_req.ready = 1'b1; + end + end + + + end +end + + + + + +/* +always_ff @(posedge aclk) begin: PROC_REG + if (aresetn == 1'b0) begin + state_C <= ST_IDLE; + + Rt <= Rt_default; + Rc <= Rc_default; + alpha <= 1; + byte_counter <= 0; + timer <= 0; + ecn_ready <= 1; + end + else begin + state_C <= state_N; + addr_C <= addr_N; + end +end + +// NSL +always_comb begin: NSL + state_N = state_C; + + case(state_C) + ST_CALC_SR: + state_N = (ecn_valid) ? ST_CALC_SR : (s_req.valid & queue_in.ready ? ST_ADD_TO_QUEUE : ST_CALC_SR); + ST_ADD_TO_QUEUE: + state_N = ST_CALC_SR; + + endcase // state_C +end + + +always_comb begin: DP + + s_ack.ready = 1'b0; + + s_req.ready = 1'b0; + req_out.valid = 1'b0; + req_out.data = s_req.data; + + ecn_ready = 1'b0; + ecn_data = ecn_mark; + + case(state_C): + ST_CALC_SR: begin + if(ecn_valid) begin + ecn_ready = 1'b1; + byte_counter = bytecounter + 1; + if(ecn_data == 1'b1) begin // Marked Packet arrived + Rt = Rc; + Rc = Rc(1-(alpha/2)); + alpha = (1-g)*alpha+g; + end + end + end + + ST_ADD_TO_QUEUE: begin + req_out.valid = 1'b1; + s_req.ready = 1'b1; + end + + + + endcase + +end +*/ + + +queue_meta #( + .QDEPTH(RDMA_N_OST) +) inst_cq ( + .aclk(aclk), + .aresetn(aresetn), + .s_meta(queue_in), + .m_meta(m_req) +); + + +endmodule \ No newline at end of file diff --git a/hw/hdl/network/rdma/MT_pomsarc_benchy.sv b/hw/hdl/network/rdma/MT_pomsarc_benchy.sv new file mode 100644 index 000000000..ae82f2447 --- /dev/null +++ b/hw/hdl/network/rdma/MT_pomsarc_benchy.sv @@ -0,0 +1,135 @@ +`timescale 1ns / 1ps + +`define DBG_IBV + +import lynxTypes::*; + +/** + * @brief RoCE instantiation + * + * RoCE stack + */ +module benchy +( + input logic aclk, + input logic aresetn, + + metaIntf.s s_req, + metaIntf.m m_req +); + +localparam integer packet_gap = 5; //inverse of marked percentage +localparam integer measurement_gap + + +localparam integer max_timer = 10000; + +logic[31:0] timer; +logic[31:0] packet_counter; + +logic[31:0] packet_gap_counter; + + + +logic running; + +logic ecn, ecn_v, ecn_r; + +logic[31:0] measurement_gap_timer; + +always_ff @(posedge aclk) begin + if (aresetn == 1'b0) begin + timer <= 0; + measurement_gap_timer <= 0; + packet_counter <= 0; + packet_gap_counter <=0; + + ecn <= 0; + ecn_v <= 0; + running <= 0; + measurement_gap_timer <=0; + measurement_trigger <=0; + + end + else begin + timer <= timer + 1; + + if(timer >= max_timer) begin + timer <= 0; + measurement_gap_timer <= 0; + packet_counter <= 0; + packet_gap_counter <=0; + + ecn <= 0; + ecn_v <= 0; + running <= 0; + measurement_gap_timer <=0; + measurement_trigger <=0; + end + else begin + measurement_gap_timer <= measurement_gap_timer + 1; + ecn_v <= 0; + ecn <= 0; + if(s_req.valid == 1) begin + if(running == 0) begin + running <= 1; + measurement_gap_timer <= 0; + end + + ecn_v <= 1; + + if(packet_gap_counter < packet_gap) begin + ecn <= 0; + end + else begin + ecn <= 1 + end + if(s_req.ready) begin + if(packet_gap_counter >= packet_gap) begin + packet_gap_counter <=0; + end + else begin + packet_gap_counter <= packet_gap_counter + 1; + end + packet_counter = packet_counter + 1; + + end + end + + if(measurement_gap_timer >= measurement_gap) begin + measurement_gap_timer <= 0; + end + end + + end +end + +ila_testbench_CC inst_ila_testbench_CC( + .clk(nclk), + .probe0(timer), + .probe1(measurement_gap_timer), + .probe2(running), + .probe3(ecn) + .probe5(ecn_v) + .probe6(ecn_r) +); + + + +cc_queue inst_cc_queue( + .aclk(aclk), + .aresetn(aresetn), + + .ecn_mark(ecn), + .ecn_valid(ecn_v), + .ecn_ready(ecn_r), + + + .s_req(s_req), + .m_req(m_req) +); + + + + +endmodule \ No newline at end of file diff --git a/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv b/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv new file mode 100644 index 000000000..02910c647 --- /dev/null +++ b/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv @@ -0,0 +1,189 @@ +import lynxTypes::*; + +module rdma_flow ( + metaIntf.s s_req, + metaIntf.m m_req, + + metaIntf.s s_ack, + metaIntf.m m_ack, + + input logic aclk, + input logic aresetn +); + +localparam integer RDMA_N_OST = RDMA_N_WR_OUTSTANDING; +localparam integer RDMA_OST_BITS = $clog2(RDMA_N_OST); +localparam integer RD_OP = 0; +localparam integer WR_OP = 1; + +// -- FSM +typedef enum logic[2:0] {ST_IDLE, ST_ACK_LUP_WAIT, ST_REQ_LUP_WAIT, ST_ACK_LUP, ST_REQ_LUP} state_t; +logic [2:0] state_C, state_N; +logic [1+N_REGIONS_BITS+PID_BITS-1:0] addr_C, addr_N; + +logic [1:0] ssn_wr; +logic [1+N_REGIONS_BITS+PID_BITS-1:0] ssn_addr; +logic [15:0] ssn_in; +logic [15:0] ssn_out; + +metaIntf #(.STYPE(ack_t)) ack_que_in (); +metaIntf #(.STYPE(dreq_t)) req_out (); + +logic [RDMA_OST_BITS-1:0] tail, tail_next; +logic [RDMA_OST_BITS-1:0] head, head_next; +logic issued, issued_next; + + +// Pointer table +ram_sp_nc #( + .ADDR_BITS(1+N_REGIONS_BITS+PID_BITS), + .DATA_BITS(16) +) inst_pntr_table ( + .clk(aclk), + .a_en(1'b1), + .a_we(ssn_wr), + .a_addr(ssn_addr), + .a_data_in(ssn_in), + .a_data_out(ssn_out) +); + +// REG +always_ff @(posedge aclk) begin: PROC_REG + if (aresetn == 1'b0) begin + state_C <= ST_IDLE; + addr_C <= 'X; + end + else begin + state_C <= state_N; + addr_C <= addr_N; + end +end + +// NSL +always_comb begin: NSL + state_N = state_C; + + case(state_C) + ST_IDLE: + state_N = (s_ack.valid) ? ST_ACK_LUP_WAIT : (s_req.valid & req_out.ready ? ST_REQ_LUP_WAIT : ST_IDLE); + + ST_ACK_LUP_WAIT: + state_N = ST_ACK_LUP; + + ST_REQ_LUP_WAIT: + state_N = ST_REQ_LUP; + + ST_REQ_LUP: + state_N = ST_IDLE; + + ST_ACK_LUP: + state_N = ST_IDLE; + + endcase // state_C +end + +// DP +assign ssn_in = {7'h00, issued_next, head_next, tail_next}; +assign issued = ssn_out[2*RDMA_OST_BITS]; +assign head = ssn_out[RDMA_OST_BITS+:RDMA_OST_BITS]; +assign tail = ssn_out[0+:RDMA_OST_BITS]; + +always_comb begin: DP + addr_N = addr_C; + + // ACKs + s_ack.ready = 1'b0; + + ack_que_in.valid = 1'b0; + ack_que_in.data = s_ack.data.ack; + + // Req + s_req.ready = 1'b0; + req_out.valid = 1'b0; + req_out.data = s_req.data; + req_out.data.req_1.offs = head; + + // Table + ssn_wr = 0; + ssn_addr = 0; + + // Pointers + head_next = 0; + tail_next = 0; + issued_next = 0; + + case(state_C) + ST_IDLE: begin + if(s_ack.valid & ) begin + s_ack.ready = 1'b1; + ack_que_in.valid = s_ack.data.last; + + ssn_addr = {is_opcode_rd_resp(s_ack.data.ack.opcode), s_ack.data.ack.vfid[N_REGIONS_BITS-1:0], s_ack.data.ack.pid}; + addr_N = ssn_addr; + end + else if(s_req.valid & req_out.ready) begin + ssn_addr = {is_opcode_rd_req(s_req.data.req_1.opcode), s_req.data.req_1.vfid[N_REGIONS_BITS-1:0], s_req.data.req_1.pid}; + addr_N = ssn_addr; + end + end + + ST_ACK_LUP: begin + head_next = head; + tail_next = tail + 1; + if(head == tail_next) + issued_next = 1'b0; + else + issued_next = issued; + + ssn_wr = ~0; + ssn_addr = addr_C; + end + + ST_REQ_LUP: begin + if(!issued || (head != tail)) begin + req_out.valid = 1'b1; + s_req.ready = 1'b1; + + head_next = head + 1; + tail_next = tail; + issued_next = 1'b1; + + ssn_wr = ~0; + ssn_addr = addr_C; + end + end + + endcase + +end + +// ACK queue +queue_meta #( + .QDEPTH(RDMA_N_OST) +) inst_cq ( + .aclk(aclk), + .aresetn(aresetn), + .s_meta(ack_que_in), + .m_meta(m_ack) +); + +// REQ queue +/* +queue_meta #( + .QDEPTH(RDMA_N_OST) +) inst_sq ( + .aclk(aclk), + .aresetn(aresetn), + .s_meta(req_out), + .m_meta(m_req) +);*/ + +benchy inst_cc_bench( + .aclk(aclk), + .aresetn(aresetn), + + .s_req(req_out), + .m_req(m_req) +); + +endmodule \ No newline at end of file diff --git a/scripts/ip_inst/network_infrastructure.tcl b/scripts/ip_inst/network_infrastructure.tcl index 090314bc7..4af1e10f8 100644 --- a/scripts/ip_inst/network_infrastructure.tcl +++ b/scripts/ip_inst/network_infrastructure.tcl @@ -584,3 +584,6 @@ set_property -dict [list CONFIG.TDATA_NUM_BYTES {4} CONFIG.FIFO_DEPTH {128} ] [g # MT_pomsarc added create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_rdma_ack set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_NUM_OF_PROBES {4} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_rdma_ack] + +create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_testbench_CC +set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_NUM_OF_PROBES {7} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_rdma_ack] \ No newline at end of file From 21ef62462e7a05937db50409492c9203302505a7 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Fri, 8 Aug 2025 06:27:57 +0200 Subject: [PATCH 14/52] fix typos --- .../rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv | 24 +++++++------------ 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv index 208e9f6a4..daf68e85f 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv @@ -61,8 +61,6 @@ logic ecn_data; always_ff @(posedge aclk) begin if (aresetn == 1'b0) begin - state_C <= ST_IDLE; - Rt <= Rt_default; Rc <= Rc_default; Sa <= S1; @@ -71,7 +69,7 @@ always_ff @(posedge aclk) begin timer_send_rate = 0; byte_counter <= 0; - time_counter <= 0 + time_counter <= 0; ecn_ready <= 1; @@ -94,20 +92,20 @@ always_ff @(posedge aclk) begin if(ecn_valid) begin ecn_ready <= 1'b1; - byte_counter <= bytecounter + 1; + byte_counter <= byte_counter + 1; if(ecn_data == 1'b1) begin // Marked Packet arrived if(timer - time_last_update > N_min_time_between_ecn_marks) begin Rt <= Rc; Rc <= (Rc << 8) / (S1 - (Sa>>1)); - alpha <= (((S1-Sg)*Sa)>> 8) + Sg; - time_last_update <= timer + Sa <= (((S1-Sg)*Sa)>> 8) + Sg; + time_last_update <= timer; end - time_of_last_marked_packet <= timer + time_of_last_marked_packet <= timer; end end if (timer - time_of_last_marked_packet > N_min_time_between_ecn_marks) begin - alpha <= (((S1-Sg)*alpha)>> 8); + Sa <= (((S1-Sg)*Sa)>> 8); end @@ -115,8 +113,8 @@ always_ff @(posedge aclk) begin if(time_counter >= F && byte_counter >=F) begin // case Hyper Increse - // Still missing - // + //replaced by fast recovery + Rc = (Rt + Rc) >> 1; time_counter <= 0; byte_counter <= 0; @@ -134,13 +132,9 @@ always_ff @(posedge aclk) begin end else begin // case Fast Recovery - Rc = (Rt + Rc) >> 1 + Rc = (Rt + Rc) >> 1; end - - - - if(s_req.valid & queue_in.ready) begin if(timer_send_rate > Rc) begin From edef0734d35101af03c2f3951a7e76109deeb096 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Mon, 11 Aug 2025 03:02:37 +0200 Subject: [PATCH 15/52] :) --- .../rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv | 1 + hw/hdl/network/rdma/MT_pomsarc_benchy.sv | 29 +++++++++---------- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv index daf68e85f..eb29d2e28 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv @@ -130,6 +130,7 @@ always_ff @(posedge aclk) begin byte_counter <= 0; end end + end else begin // case Fast Recovery Rc = (Rt + Rc) >> 1; diff --git a/hw/hdl/network/rdma/MT_pomsarc_benchy.sv b/hw/hdl/network/rdma/MT_pomsarc_benchy.sv index ae82f2447..4a65cf4f1 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_benchy.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_benchy.sv @@ -19,14 +19,13 @@ module benchy ); localparam integer packet_gap = 5; //inverse of marked percentage -localparam integer measurement_gap +localparam integer measurement_gap = 50; -localparam integer max_timer = 10000; +//localparam integer max_timer = 10000000000; logic[31:0] timer; logic[31:0] packet_counter; - logic[31:0] packet_gap_counter; @@ -47,25 +46,25 @@ always_ff @(posedge aclk) begin ecn <= 0; ecn_v <= 0; running <= 0; - measurement_gap_timer <=0; - measurement_trigger <=0; + measurement_gap_timer <= 0; + //measurement_trigger <= 0; end else begin timer <= timer + 1; - if(timer >= max_timer) begin + /*if(timer >= max_timer) begin timer <= 0; measurement_gap_timer <= 0; packet_counter <= 0; - packet_gap_counter <=0; + packet_gap_counter <= 0; ecn <= 0; ecn_v <= 0; running <= 0; - measurement_gap_timer <=0; - measurement_trigger <=0; - end + measurement_gap_timer <= 0; + //measurement_trigger <= 0; + end*/ else begin measurement_gap_timer <= measurement_gap_timer + 1; ecn_v <= 0; @@ -82,16 +81,16 @@ always_ff @(posedge aclk) begin ecn <= 0; end else begin - ecn <= 1 + ecn <= 1; end if(s_req.ready) begin if(packet_gap_counter >= packet_gap) begin - packet_gap_counter <=0; + packet_gap_counter <= 0; end else begin packet_gap_counter <= packet_gap_counter + 1; end - packet_counter = packet_counter + 1; + packet_counter <= packet_counter + 1; end end @@ -109,8 +108,8 @@ ila_testbench_CC inst_ila_testbench_CC( .probe0(timer), .probe1(measurement_gap_timer), .probe2(running), - .probe3(ecn) - .probe5(ecn_v) + .probe3(ecn), + .probe5(ecn_v), .probe6(ecn_r) ); From f147a2bed4d4d35d34ac3b0b95ccea54585abbcd Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Mon, 11 Aug 2025 04:53:20 +0200 Subject: [PATCH 16/52] :) --- hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv | 10 +++++----- hw/hdl/network/rdma/MT_pomsarc_benchy.sv | 8 ++++---- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv index eb29d2e28..de6c036c7 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv @@ -79,7 +79,7 @@ always_ff @(posedge aclk) begin end else begin timer <= timer + 1; - time_counter = time_counter + 1; + time_counter <= time_counter + 1; ecn_ready <= 1'b0; ecn_data <= ecn_mark; @@ -114,7 +114,7 @@ always_ff @(posedge aclk) begin if(time_counter >= F && byte_counter >=F) begin // case Hyper Increse //replaced by fast recovery - Rc = (Rt + Rc) >> 1; + Rc <= (Rt + Rc) >> 1; time_counter <= 0; byte_counter <= 0; @@ -123,7 +123,7 @@ always_ff @(posedge aclk) begin // case Additive Increase Rt <= Rt + Rai; Rc <= (Rt + Rc) >> 1; - if(time_counter >= F)begin + if(time_counter >= F) begin time_counter <= 0; end else begin @@ -133,7 +133,7 @@ always_ff @(posedge aclk) begin end else begin // case Fast Recovery - Rc = (Rt + Rc) >> 1; + Rc <= (Rt + Rc) >> 1; end @@ -148,7 +148,7 @@ always_ff @(posedge aclk) begin end end -end + diff --git a/hw/hdl/network/rdma/MT_pomsarc_benchy.sv b/hw/hdl/network/rdma/MT_pomsarc_benchy.sv index 4a65cf4f1..062ed8d8c 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_benchy.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_benchy.sv @@ -64,8 +64,8 @@ always_ff @(posedge aclk) begin running <= 0; measurement_gap_timer <= 0; //measurement_trigger <= 0; - end*/ - else begin + end + else begin*/ measurement_gap_timer <= measurement_gap_timer + 1; ecn_v <= 0; ecn <= 0; @@ -98,13 +98,13 @@ always_ff @(posedge aclk) begin if(measurement_gap_timer >= measurement_gap) begin measurement_gap_timer <= 0; end - end + //end end end ila_testbench_CC inst_ila_testbench_CC( - .clk(nclk), + .clk(aclk), .probe0(timer), .probe1(measurement_gap_timer), .probe2(running), From 0c4ab1de3624fde434cf897e89edf0c6c9af8922 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Mon, 11 Aug 2025 06:43:41 +0200 Subject: [PATCH 17/52] removed superfluous file --- .../rdma/MT_pomsarc_CC_queue_wrapper.sv | 199 ------------------ scripts/ip_inst/network_infrastructure.tcl | 2 +- 2 files changed, 1 insertion(+), 200 deletions(-) delete mode 100644 hw/hdl/network/rdma/MT_pomsarc_CC_queue_wrapper.sv diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_queue_wrapper.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_queue_wrapper.sv deleted file mode 100644 index ceb193d54..000000000 --- a/hw/hdl/network/rdma/MT_pomsarc_CC_queue_wrapper.sv +++ /dev/null @@ -1,199 +0,0 @@ -import lynxTypes::*; - -module cc_queue -( - input logic aclk, - input logic aresetn, - - input logic ecn_mark, - input logic ecn_valid, - output logic ecn_ready, - - - metaIntf.s s_req, - metaIntf.m m_req -); - -localparam integer RDMA_N_OST = RDMA_N_WR_OUTSTANDING; -localparam integer RDMA_OST_BITS = $clog2(RDMA_N_OST); -localparam integer RD_OP = 0; -localparam integer WR_OP = 1; - -localparam integer Rt_default = 100000; -localparam integer Rc_default = 100000; -localparam integer N_min_time_between_ecn_marks = 50; -localparam integer Rai = 50; -localparam integer g = 8; -localparam integer F = 5; - -localparam integer time_threshhold = 100; -localparam integer byte_threshhold = 10; - -logic[31:0] Rt; -logic[31:0] Rc; -logic[31:0] alpha; -logic[31:0] timer; - -logic[31:0] timer_send_rate; - -logic[31:0] time_of_last_marked_packet; -logic[31:0] time_last_update; - -logic[31:0] byte_counter; -logic[31:0] time_counter; - -logic[4:0] step_counter; - - -//typedef enum logic[2:0] {ST_IDLE, ST_CALC_SR, ST_ADD_TO_QUEUE} state_t; -logic [2:0] state_C, state_N; -metaIntf #(.STYPE(dreq_t)) queue_in(); -metaIntf #(.STYPE(dreq_t)) queue_out(); - -logic ecn_data; - - - - -always_ff @(posedge aclk) begin - if (aresetn == 1'b0) begin - state_C <= ST_IDLE; - - Rt <= Rt_default; - Rc <= Rc_default; - alpha <= 1; - timer <= 0; - - timer_send_rate = 0; - - byte_counter <= 0; - time_counter <= 0 - - ecn_ready <= 1; - - step_counter <= 0; - - - end - else begin - timer <= timer + 1; - time_counter = time_counter + 1; - - ecn_ready <= 1'b0; - ecn_data <= ecn_mark; - - s_ack.ready <= 1'b0; - - s_req.ready <= 1'b0; - req_out.valid <= 1'b0; - req_out.data <= s_req.data; - - if(ecn_valid) begin - ecn_ready <= 1'b1; - byte_counter <= bytecounter + 1; - if(ecn_data == 1'b1) begin // Marked Packet arrived - Rt = Rc; - Rc = Rc(1-(alpha/2)); - alpha = (1-g)*alpha+g; - end - end - - if(time_counter >) - - - if(s_req.valid & queue_in.ready) begin - if(timer_send_rate > Rc) begin - timer_send_rate = 0; - req_out.valid = 1'b1; - s_req.ready = 1'b1; - end - end - - - end -end - - - - - -/* -always_ff @(posedge aclk) begin: PROC_REG - if (aresetn == 1'b0) begin - state_C <= ST_IDLE; - - Rt <= Rt_default; - Rc <= Rc_default; - alpha <= 1; - byte_counter <= 0; - timer <= 0; - ecn_ready <= 1; - end - else begin - state_C <= state_N; - addr_C <= addr_N; - end -end - -// NSL -always_comb begin: NSL - state_N = state_C; - - case(state_C) - ST_CALC_SR: - state_N = (ecn_valid) ? ST_CALC_SR : (s_req.valid & queue_in.ready ? ST_ADD_TO_QUEUE : ST_CALC_SR); - ST_ADD_TO_QUEUE: - state_N = ST_CALC_SR; - - endcase // state_C -end - - -always_comb begin: DP - - s_ack.ready = 1'b0; - - s_req.ready = 1'b0; - req_out.valid = 1'b0; - req_out.data = s_req.data; - - ecn_ready = 1'b0; - ecn_data = ecn_mark; - - case(state_C): - ST_CALC_SR: begin - if(ecn_valid) begin - ecn_ready = 1'b1; - byte_counter = bytecounter + 1; - if(ecn_data == 1'b1) begin // Marked Packet arrived - Rt = Rc; - Rc = Rc(1-(alpha/2)); - alpha = (1-g)*alpha+g; - end - end - end - - ST_ADD_TO_QUEUE: begin - req_out.valid = 1'b1; - s_req.ready = 1'b1; - end - - - - endcase - -end -*/ - - -queue_meta #( - .QDEPTH(RDMA_N_OST) -) inst_cq ( - .aclk(aclk), - .aresetn(aresetn), - .s_meta(queue_in), - .m_meta(m_req) -); - - -endmodule \ No newline at end of file diff --git a/scripts/ip_inst/network_infrastructure.tcl b/scripts/ip_inst/network_infrastructure.tcl index 4af1e10f8..c305a410e 100644 --- a/scripts/ip_inst/network_infrastructure.tcl +++ b/scripts/ip_inst/network_infrastructure.tcl @@ -586,4 +586,4 @@ create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_NUM_OF_PROBES {4} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_rdma_ack] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_testbench_CC -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_NUM_OF_PROBES {7} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_rdma_ack] \ No newline at end of file +set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_NUM_OF_PROBES {7} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_testbench_CC] \ No newline at end of file From 37cc18fcdb329dc2bb1a0def3146bb9e02fa3045 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Mon, 1 Sep 2025 16:06:06 +0200 Subject: [PATCH 18/52] ... --- .../rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv | 59 ++++-- .../rdma/MT_pomsarc_CC_QP_unit_Timely.sv | 0 hw/hdl/network/rdma/MT_pomsarc_benchy.sv | 4 +- hw/hdl/network/rdma/MT_pomsarc_new _flow.sv | 4 +- .../rdma/MT_pomsarc_new_flow_multiqueue.sv | 0 hw/hdl/network/rdma/rdma_flow.sv | 180 ------------------ scripts/ip_inst/network_infrastructure.tcl | 5 +- 7 files changed, 48 insertions(+), 204 deletions(-) create mode 100644 hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_Timely.sv create mode 100644 hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv delete mode 100644 hw/hdl/network/rdma/rdma_flow.sv diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv index de6c036c7..600d7ee5d 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv @@ -14,15 +14,16 @@ module cc_queue metaIntf.m m_req ); -localparam integer RDMA_N_OST = RDMA_N_WR_OUTSTANDING; +//localparam integer RDMA_N_OST = RDMA_N_WR_OUTSTANDING; +localparam integer RDMA_N_OST = 20; localparam integer RDMA_OST_BITS = $clog2(RDMA_N_OST); localparam integer RD_OP = 0; localparam integer WR_OP = 1; localparam integer Rt_default = 100000; localparam integer Rc_default = 100000; -localparam integer N_min_time_between_ecn_marks = 50; -localparam integer Rai = 50; +localparam integer N_min_time_between_ecn_marks = 12500; +localparam integer Rai = 6250; localparam integer S1 = 128; // 1 << 8 localparam integer Sg = 8; // (1/16) << 8 @@ -50,15 +51,13 @@ logic[4:0] step_counter; //typedef enum logic[2:0] {ST_IDLE, ST_CALC_SR, ST_ADD_TO_QUEUE} state_t; -logic [2:0] state_C, state_N; -metaIntf #(.STYPE(dreq_t)) queue_in(); +//logic [2:0] state_C, state_N; +//metaIntf #(.STYPE(dreq_t)) queue_in(); metaIntf #(.STYPE(dreq_t)) queue_out(); logic ecn_data; - - always_ff @(posedge aclk) begin if (aresetn == 1'b0) begin Rt <= Rt_default; @@ -66,15 +65,21 @@ always_ff @(posedge aclk) begin Sa <= S1; timer <= 0; - timer_send_rate = 0; + timer_send_rate <= 0; + + time_of_last_marked_packet <= 0; + time_last_update <= 0; byte_counter <= 0; time_counter <= 0; - - ecn_ready <= 1; step_counter <= 0; + ecn_ready <= 1; + ecn_data <= 0; + + m_req.valid <= 0; + end else begin @@ -84,11 +89,12 @@ always_ff @(posedge aclk) begin ecn_ready <= 1'b0; ecn_data <= ecn_mark; - s_ack.ready <= 1'b0; + //s_ack.ready <= 1'b0; - s_req.ready <= 1'b0; - req_out.valid <= 1'b0; - req_out.data <= s_req.data; + m_req.valid <= 1'b0; + m_req.data <= queue_out.data; + queue_out.ready <= 1'b0; + //req_out.data <= s_req.data; if(ecn_valid) begin ecn_ready <= 1'b1; @@ -115,7 +121,6 @@ always_ff @(posedge aclk) begin // case Hyper Increse //replaced by fast recovery Rc <= (Rt + Rc) >> 1; - time_counter <= 0; byte_counter <= 0; end @@ -137,10 +142,11 @@ always_ff @(posedge aclk) begin end - if(s_req.valid & queue_in.ready) begin + if(queue_out.valid) begin if(timer_send_rate > Rc) begin + timer_send_rate <= 0; - req_out.valid <= 1'b1; + queue_in.valid <= 1'b1; s_req.ready <= 1'b1; end end @@ -150,6 +156,21 @@ always_ff @(posedge aclk) begin end +ila_DCQCN inst_ila_DCQCN( + .clk(aclk), + .probe0(timer), + .probe1(Rt), + .probe2(Rc), + .probe3(Sa), + .probe4(byte_counter), + .probe5(time_counter), + .probe6(step_counter), + .probe7(timer_send_rate), + .probe8(ecn_valid), + .probe9(ecn_mark) +); + + queue_meta #( @@ -157,8 +178,8 @@ queue_meta #( ) inst_cq ( .aclk(aclk), .aresetn(aresetn), - .s_meta(queue_in), - .m_meta(m_req) + .s_meta(s_req), + .m_meta(queue_out) ); diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_Timely.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_Timely.sv new file mode 100644 index 000000000..e69de29bb diff --git a/hw/hdl/network/rdma/MT_pomsarc_benchy.sv b/hw/hdl/network/rdma/MT_pomsarc_benchy.sv index 062ed8d8c..709ee4228 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_benchy.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_benchy.sv @@ -109,8 +109,8 @@ ila_testbench_CC inst_ila_testbench_CC( .probe1(measurement_gap_timer), .probe2(running), .probe3(ecn), - .probe5(ecn_v), - .probe6(ecn_r) + .probe4(ecn_v), + .probe5(ecn_r) ); diff --git a/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv b/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv index 02910c647..ec549d812 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv @@ -114,7 +114,7 @@ always_comb begin: DP case(state_C) ST_IDLE: begin - if(s_ack.valid & ) begin + if(s_ack.valid) begin s_ack.ready = 1'b1; ack_que_in.valid = s_ack.data.last; @@ -186,4 +186,4 @@ benchy inst_cc_bench( .m_req(m_req) ); -endmodule \ No newline at end of file +endmodule diff --git a/hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv b/hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv new file mode 100644 index 000000000..e69de29bb diff --git a/hw/hdl/network/rdma/rdma_flow.sv b/hw/hdl/network/rdma/rdma_flow.sv deleted file mode 100644 index 9486ed1a9..000000000 --- a/hw/hdl/network/rdma/rdma_flow.sv +++ /dev/null @@ -1,180 +0,0 @@ -import lynxTypes::*; - -module rdma_flow ( - metaIntf.s s_req, - metaIntf.m m_req, - - metaIntf.s s_ack, - metaIntf.m m_ack, - - input logic aclk, - input logic aresetn -); - -localparam integer RDMA_N_OST = RDMA_N_WR_OUTSTANDING; -localparam integer RDMA_OST_BITS = $clog2(RDMA_N_OST); -localparam integer RD_OP = 0; -localparam integer WR_OP = 1; - -// -- FSM -typedef enum logic[2:0] {ST_IDLE, ST_ACK_LUP_WAIT, ST_REQ_LUP_WAIT, ST_ACK_LUP, ST_REQ_LUP} state_t; -logic [2:0] state_C, state_N; -logic [1+N_REGIONS_BITS+PID_BITS-1:0] addr_C, addr_N; - -logic [1:0] ssn_wr; -logic [1+N_REGIONS_BITS+PID_BITS-1:0] ssn_addr; -logic [15:0] ssn_in; -logic [15:0] ssn_out; - -metaIntf #(.STYPE(ack_t)) ack_que_in (); -metaIntf #(.STYPE(dreq_t)) req_out (); - -logic [RDMA_OST_BITS-1:0] tail, tail_next; -logic [RDMA_OST_BITS-1:0] head, head_next; -logic issued, issued_next; - - -// Pointer table -ram_sp_nc #( - .ADDR_BITS(1+N_REGIONS_BITS+PID_BITS), - .DATA_BITS(16) -) inst_pntr_table ( - .clk(aclk), - .a_en(1'b1), - .a_we(ssn_wr), - .a_addr(ssn_addr), - .a_data_in(ssn_in), - .a_data_out(ssn_out) -); - -// REG -always_ff @(posedge aclk) begin: PROC_REG - if (aresetn == 1'b0) begin - state_C <= ST_IDLE; - addr_C <= 'X; - end - else begin - state_C <= state_N; - addr_C <= addr_N; - end -end - -// NSL -always_comb begin: NSL - state_N = state_C; - - case(state_C) - ST_IDLE: - state_N = (s_ack.valid) ? ST_ACK_LUP_WAIT : (s_req.valid & req_out.ready ? ST_REQ_LUP_WAIT : ST_IDLE); - - ST_ACK_LUP_WAIT: - state_N = ST_ACK_LUP; - - ST_REQ_LUP_WAIT: - state_N = ST_REQ_LUP; - - ST_REQ_LUP: - state_N = ST_IDLE; - - ST_ACK_LUP: - state_N = ST_IDLE; - - endcase // state_C -end - -// DP -assign ssn_in = {7'h00, issued_next, head_next, tail_next}; -assign issued = ssn_out[2*RDMA_OST_BITS]; -assign head = ssn_out[RDMA_OST_BITS+:RDMA_OST_BITS]; -assign tail = ssn_out[0+:RDMA_OST_BITS]; - -always_comb begin: DP - addr_N = addr_C; - - // ACKs - s_ack.ready = 1'b0; - - ack_que_in.valid = 1'b0; - ack_que_in.data = s_ack.data.ack; - - // Req - s_req.ready = 1'b0; - req_out.valid = 1'b0; - req_out.data = s_req.data; - req_out.data.req_1.offs = head; - - // Table - ssn_wr = 0; - ssn_addr = 0; - - // Pointers - head_next = 0; - tail_next = 0; - issued_next = 0; - - case(state_C) - ST_IDLE: begin - if(s_ack.valid) begin - s_ack.ready = 1'b1; - ack_que_in.valid = s_ack.data.last; - - ssn_addr = {is_opcode_rd_resp(s_ack.data.ack.opcode), s_ack.data.ack.vfid[N_REGIONS_BITS-1:0], s_ack.data.ack.pid}; - addr_N = ssn_addr; - end - else if(s_req.valid & req_out.ready) begin - ssn_addr = {is_opcode_rd_req(s_req.data.req_1.opcode), s_req.data.req_1.vfid[N_REGIONS_BITS-1:0], s_req.data.req_1.pid}; - addr_N = ssn_addr; - end - end - - ST_ACK_LUP: begin - head_next = head; - tail_next = tail + 1; - if(head == tail_next) - issued_next = 1'b0; - else - issued_next = issued; - - ssn_wr = ~0; - ssn_addr = addr_C; - end - - ST_REQ_LUP: begin - if(!issued || (head != tail)) begin - req_out.valid = 1'b1; - s_req.ready = 1'b1; - - head_next = head + 1; - tail_next = tail; - issued_next = 1'b1; - - ssn_wr = ~0; - ssn_addr = addr_C; - end - end - - endcase - -end - -// ACK queue -queue_meta #( - .QDEPTH(RDMA_N_OST) -) inst_cq ( - .aclk(aclk), - .aresetn(aresetn), - .s_meta(ack_que_in), - .m_meta(m_ack) -); - -// REQ queue -queue_meta #( - .QDEPTH(RDMA_N_OST) -) inst_sq ( - .aclk(aclk), - .aresetn(aresetn), - .s_meta(req_out), - .m_meta(m_req) -); - -endmodule \ No newline at end of file diff --git a/scripts/ip_inst/network_infrastructure.tcl b/scripts/ip_inst/network_infrastructure.tcl index c305a410e..816fc22e7 100644 --- a/scripts/ip_inst/network_infrastructure.tcl +++ b/scripts/ip_inst/network_infrastructure.tcl @@ -586,4 +586,7 @@ create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_NUM_OF_PROBES {4} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_rdma_ack] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_testbench_CC -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_NUM_OF_PROBES {7} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_testbench_CC] \ No newline at end of file +set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_NUM_OF_PROBES {6} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_testbench_CC] + +create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_DCQCN +set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {32} CONFIG.C_PROBE4_WIDTH {32} CONFIG.C_PROBE5_WIDTH {32} CONFIG.C_PROBE6_WIDTH {5} CONFIG.C_PROBE7_WIDTH {32} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_NUM_OF_PROBES {10} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_DCQCN] \ No newline at end of file From 78a9cf3afc126c41b8a5a4ff799f330c242ca1ee Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Wed, 3 Sep 2025 01:04:29 +0200 Subject: [PATCH 19/52] submodule changes --- hw/services/network | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/services/network b/hw/services/network index 4928877fa..0032c5545 160000 --- a/hw/services/network +++ b/hw/services/network @@ -1 +1 @@ -Subproject commit 4928877faf472a06d41a7b111403c820c731a311 +Subproject commit 0032c5545507f15005386200759c7d4c10f94635 From 8031c9a025626e25be93c4b501370d93bdbc90b9 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Fri, 5 Sep 2025 13:03:40 +0200 Subject: [PATCH 20/52] commented out CC --- hw/hdl/network/rdma/MT_pomsarc_new _flow.sv | 8 ++++---- hw/hdl/network/rdma/roce_stack.sv | 13 ++++++++++++- scripts/ip_inst/network_infrastructure.tcl | 2 +- 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv b/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv index ec549d812..d5bd9e581 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv @@ -168,7 +168,7 @@ queue_meta #( ); // REQ queue -/* + queue_meta #( .QDEPTH(RDMA_N_OST) ) inst_sq ( @@ -176,14 +176,14 @@ queue_meta #( .aresetn(aresetn), .s_meta(req_out), .m_meta(m_req) -);*/ +); -benchy inst_cc_bench( +/*benchy inst_cc_bench( .aclk(aclk), .aresetn(aresetn), .s_req(req_out), .m_req(m_req) -); +);/* endmodule diff --git a/hw/hdl/network/rdma/roce_stack.sv b/hw/hdl/network/rdma/roce_stack.sv index 3a90c7800..4d3f8100a 100644 --- a/hw/hdl/network/rdma/roce_stack.sv +++ b/hw/hdl/network/rdma/roce_stack.sv @@ -230,9 +230,20 @@ ila_rdma_ack inst_ila_rdma_ack ( .probe0(rdma_ack.valid), .probe1(rdma_ack.ready), .probe2(rdma_ack.data.ack), // 32 - .probe3(rdma_ack.data.last) + .probe3(rdma_ack.data.last), + .probe4(s_axis_rx.tvalid), + .probe5(s_axis_rx.tready), + .probe6(s_axis_rx.tdata), // 512 + .probe7(s_axis_rx.tkeep), // 64 + .probe8(s_axis_rx.tlast), + .probe9(m_axis_tx.tvalid), + .probe10(m_axis_tx.tready), + .probe11(m_axis_tx.tdata), // 512 + .probe12(m_axis_tx.tkeep), // 64 + .probe13(m_axis_tx.tlast) ); + /* ila_rdma inst_ila_rdma ( .clk(nclk), .probe0(s_rdma_qp_interface.valid), diff --git a/scripts/ip_inst/network_infrastructure.tcl b/scripts/ip_inst/network_infrastructure.tcl index 816fc22e7..2246934a3 100644 --- a/scripts/ip_inst/network_infrastructure.tcl +++ b/scripts/ip_inst/network_infrastructure.tcl @@ -583,7 +583,7 @@ set_property -dict [list CONFIG.TDATA_NUM_BYTES {4} CONFIG.FIFO_DEPTH {128} ] [g # MT_pomsarc added create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_rdma_ack -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_NUM_OF_PROBES {4} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_rdma_ack] +set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_PROBE6_WIDTH {512} CONFIG.C_PROBE7_WIDTH {64} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {512} CONFIG.C_PROBE12_WIDTH {64} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_NUM_OF_PROBES {14} CONFIG.C_DATA_DEPTH {8096} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_rdma_ack] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_testbench_CC set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_NUM_OF_PROBES {6} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_testbench_CC] From bd401bca614557c75ce4990f93913a9cac4057a5 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Sun, 7 Sep 2025 03:31:28 +0200 Subject: [PATCH 21/52] more ilas in flowcontrol --- hw/hdl/network/rdma/MT_pomsarc_new _flow.sv | 50 ++++++++++++++++++++- hw/hdl/network/rdma/roce_stack.sv | 1 - scripts/ip_inst/network_infrastructure.tcl | 9 ++-- 3 files changed, 54 insertions(+), 6 deletions(-) diff --git a/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv b/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv index d5bd9e581..91e74f8e3 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv @@ -157,6 +157,36 @@ always_comb begin: DP end + +ila_rdma_ack ila_flowcontrol ( + .clk(aclk), + .probe0(ack_que_in.valid), + .probe1(ack_que_in.ready), + //.probe2(ack_que_in.data), // 32 + + .probe2(s_ack.valid), + .probe3(s_ack.ready), + //.probe5(s_ack.data.ack), // 32 + //.probe6(s_ack.data.last), + + .probe4(m_ack.valid), + .probe5(m_ack.ready), + //.probe9(m_ack.data.ack), // 32 + //.probe10(m_ack.data.last), + + .probe6(req_out.valid), + .probe7(req_out.ready), + //.probe8(s_rdma_sq.data), + + .probe8(s_req.valid), + .probe9(s_req.ready), + //.probe8(s_rdma_sq.data), + + .probe10(m_req.valid), + .probe11(m_req.ready) + //.probe8(s_rdma_sq.data), +); + // ACK queue queue_meta #( .QDEPTH(RDMA_N_OST) @@ -168,7 +198,6 @@ queue_meta #( ); // REQ queue - queue_meta #( .QDEPTH(RDMA_N_OST) ) inst_sq ( @@ -178,12 +207,29 @@ queue_meta #( .m_meta(m_req) ); + +/* +cc_queue +( + .aclk(aclk), + .aresetn(aresetn), + + .ecn_mark(), + .ecn_valid, + .ecn_ready, + + + .s_req(req_out), + .m_req(m_req) +);*/ + + /*benchy inst_cc_bench( .aclk(aclk), .aresetn(aresetn), .s_req(req_out), .m_req(m_req) -);/* +);*/ endmodule diff --git a/hw/hdl/network/rdma/roce_stack.sv b/hw/hdl/network/rdma/roce_stack.sv index 4d3f8100a..b2ee04326 100644 --- a/hw/hdl/network/rdma/roce_stack.sv +++ b/hw/hdl/network/rdma/roce_stack.sv @@ -243,7 +243,6 @@ ila_rdma_ack inst_ila_rdma_ack ( .probe13(m_axis_tx.tlast) ); - /* ila_rdma inst_ila_rdma ( .clk(nclk), .probe0(s_rdma_qp_interface.valid), diff --git a/scripts/ip_inst/network_infrastructure.tcl b/scripts/ip_inst/network_infrastructure.tcl index 2246934a3..8e81e9b12 100644 --- a/scripts/ip_inst/network_infrastructure.tcl +++ b/scripts/ip_inst/network_infrastructure.tcl @@ -583,10 +583,13 @@ set_property -dict [list CONFIG.TDATA_NUM_BYTES {4} CONFIG.FIFO_DEPTH {128} ] [g # MT_pomsarc added create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_rdma_ack -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_PROBE6_WIDTH {512} CONFIG.C_PROBE7_WIDTH {64} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {512} CONFIG.C_PROBE12_WIDTH {64} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_NUM_OF_PROBES {14} CONFIG.C_DATA_DEPTH {8096} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_rdma_ack] +set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_PROBE6_WIDTH {512} CONFIG.C_PROBE7_WIDTH {64} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {512} CONFIG.C_PROBE12_WIDTH {64} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_NUM_OF_PROBES {14} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_rdma_ack] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_testbench_CC -set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_NUM_OF_PROBES {6} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_testbench_CC] +set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_NUM_OF_PROBES {6} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_testbench_CC] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_DCQCN -set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {32} CONFIG.C_PROBE4_WIDTH {32} CONFIG.C_PROBE5_WIDTH {32} CONFIG.C_PROBE6_WIDTH {5} CONFIG.C_PROBE7_WIDTH {32} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_NUM_OF_PROBES {10} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_DCQCN] \ No newline at end of file +set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {32} CONFIG.C_PROBE4_WIDTH {32} CONFIG.C_PROBE5_WIDTH {32} CONFIG.C_PROBE6_WIDTH {5} CONFIG.C_PROBE7_WIDTH {32} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_NUM_OF_PROBES {10} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_DCQCN] + +create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_flowcontrol +set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_PROBE6_WIDTH {1} CONFIG.C_PROBE7_WIDTH {1} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {1} CONFIG.C_NUM_OF_PROBES {12} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_flowcontrol] \ No newline at end of file From 3b8f3b975649d5cb5c692ead1d95f2050dfa7eb5 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Sun, 7 Sep 2025 03:37:17 +0200 Subject: [PATCH 22/52] update submodule link --- hw/services/network | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/services/network b/hw/services/network index 0032c5545..ef47e1f81 160000 --- a/hw/services/network +++ b/hw/services/network @@ -1 +1 @@ -Subproject commit 0032c5545507f15005386200759c7d4c10f94635 +Subproject commit ef47e1f81e6a7fbe8177103add8866edc7f0405c From b8c29d9a7ea70c796f8de1f482156d57965ee7a8 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Sun, 7 Sep 2025 12:06:46 +0200 Subject: [PATCH 23/52] ila fix --- hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv | 6 +++--- hw/hdl/network/rdma/MT_pomsarc_new _flow.sv | 10 +--------- 2 files changed, 4 insertions(+), 12 deletions(-) diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv index 600d7ee5d..627f7a518 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv @@ -142,12 +142,12 @@ always_ff @(posedge aclk) begin end - if(queue_out.valid) begin + if(queue_out.valid & m_req.ready) begin if(timer_send_rate > Rc) begin timer_send_rate <= 0; - queue_in.valid <= 1'b1; - s_req.ready <= 1'b1; + m_req.valid <= 1'b1; + queue_out.ready <= 1'b1; end end diff --git a/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv b/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv index 91e74f8e3..0214c47c3 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv @@ -158,33 +158,25 @@ always_comb begin: DP end -ila_rdma_ack ila_flowcontrol ( +ila_flowcontrol inst_ila_flowcontrol ( .clk(aclk), .probe0(ack_que_in.valid), .probe1(ack_que_in.ready), - //.probe2(ack_que_in.data), // 32 .probe2(s_ack.valid), .probe3(s_ack.ready), - //.probe5(s_ack.data.ack), // 32 - //.probe6(s_ack.data.last), .probe4(m_ack.valid), .probe5(m_ack.ready), - //.probe9(m_ack.data.ack), // 32 - //.probe10(m_ack.data.last), .probe6(req_out.valid), .probe7(req_out.ready), - //.probe8(s_rdma_sq.data), .probe8(s_req.valid), .probe9(s_req.ready), - //.probe8(s_rdma_sq.data), .probe10(m_req.valid), .probe11(m_req.ready) - //.probe8(s_rdma_sq.data), ); // ACK queue From 9f004d2a87d8e033c5a1c8a5138b89e30dce1bf4 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Mon, 8 Sep 2025 01:36:31 +0200 Subject: [PATCH 24/52] added DCQCN back on --- .../rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv | 48 +++++++++---------- hw/hdl/network/rdma/MT_pomsarc_benchy.sv | 7 ++- hw/hdl/network/rdma/MT_pomsarc_new _flow.sv | 31 +++++++----- scripts/ip_inst/network_infrastructure.tcl | 4 +- 4 files changed, 48 insertions(+), 42 deletions(-) diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv index 627f7a518..c00adcc01 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv @@ -6,9 +6,7 @@ module cc_queue input logic aresetn, input logic ecn_mark, - input logic ecn_valid, - output logic ecn_ready, - + input logic ecn_write_rdy, metaIntf.s s_req, metaIntf.m m_req @@ -53,10 +51,8 @@ logic[4:0] step_counter; //typedef enum logic[2:0] {ST_IDLE, ST_CALC_SR, ST_ADD_TO_QUEUE} state_t; //logic [2:0] state_C, state_N; //metaIntf #(.STYPE(dreq_t)) queue_in(); -metaIntf #(.STYPE(dreq_t)) queue_out(); - -logic ecn_data; +metaIntf #(.STYPE(dreq_t)) queue_out; always_ff @(posedge aclk) begin if (aresetn == 1'b0) begin @@ -72,22 +68,18 @@ always_ff @(posedge aclk) begin byte_counter <= 0; time_counter <= 0; - step_counter <= 0; - ecn_ready <= 1; - ecn_data <= 0; - - m_req.valid <= 0; + m_req.valid <= 1'b0; + queue_out.ready <= 1'b0; end else begin timer <= timer + 1; time_counter <= time_counter + 1; + timer_send_rate <= timer_send_rate + 1; - ecn_ready <= 1'b0; - ecn_data <= ecn_mark; //s_ack.ready <= 1'b0; @@ -96,10 +88,9 @@ always_ff @(posedge aclk) begin queue_out.ready <= 1'b0; //req_out.data <= s_req.data; - if(ecn_valid) begin - ecn_ready <= 1'b1; + if(ecn_write_rdy) begin byte_counter <= byte_counter + 1; - if(ecn_data == 1'b1) begin // Marked Packet arrived + if(ecn_mark == 1'b1) begin // Marked Packet arrived if(timer - time_last_update > N_min_time_between_ecn_marks) begin Rt <= Rc; Rc <= (Rc << 8) / (S1 - (Sa>>1)); @@ -141,14 +132,15 @@ always_ff @(posedge aclk) begin Rc <= (Rt + Rc) >> 1; end - - if(queue_out.valid & m_req.ready) begin - if(timer_send_rate > Rc) begin - + // CHANGE BACK + //if(timer_send_rate > Rc) begin + if(timer_send_rate > 1) begin + m_req.valid <= queue_out.valid; + queue_out.ready <= m_req.ready; + if(queue_out.valid & m_req.ready) begin timer_send_rate <= 0; - m_req.valid <= 1'b1; - queue_out.ready <= 1'b1; end + end @@ -166,13 +158,17 @@ ila_DCQCN inst_ila_DCQCN( .probe5(time_counter), .probe6(step_counter), .probe7(timer_send_rate), - .probe8(ecn_valid), - .probe9(ecn_mark) + .probe8(s_req.valid), + .probe9(s_req.ready), + .probe10(m_req.valid), + .probe11(m_req.ready), + .probe12(queue_out.valid), + .probe13(queue_out.ready), + .probe14(ecn_mark), + .probe15(ecn_write_rdy) ); - - queue_meta #( .QDEPTH(RDMA_N_OST) ) inst_cq ( diff --git a/hw/hdl/network/rdma/MT_pomsarc_benchy.sv b/hw/hdl/network/rdma/MT_pomsarc_benchy.sv index 709ee4228..a08dead5f 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_benchy.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_benchy.sv @@ -1,4 +1,4 @@ -`timescale 1ns / 1ps +/*`timescale 1ns / 1ps `define DBG_IBV @@ -9,6 +9,7 @@ import lynxTypes::*; * * RoCE stack */ +/* module benchy ( input logic aclk, @@ -66,6 +67,7 @@ always_ff @(posedge aclk) begin //measurement_trigger <= 0; end else begin*/ +/* measurement_gap_timer <= measurement_gap_timer + 1; ecn_v <= 0; ecn <= 0; @@ -131,4 +133,5 @@ cc_queue inst_cc_queue( -endmodule \ No newline at end of file +endmodule +*/ \ No newline at end of file diff --git a/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv b/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv index 0214c47c3..8eb32281f 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv @@ -176,7 +176,12 @@ ila_flowcontrol inst_ila_flowcontrol ( .probe9(s_req.ready), .probe10(m_req.valid), - .probe11(m_req.ready) + .probe11(m_req.ready), + + .probe12(ecn_marked), + .probe13(ecn_consumed), + .probe14(s_ack.data.ack.ecn), + .probe15(s_ack.data.last) ); // ACK queue @@ -189,7 +194,7 @@ queue_meta #( .m_meta(m_ack) ); -// REQ queue +/*// REQ queue queue_meta #( .QDEPTH(RDMA_N_OST) ) inst_sq ( @@ -197,23 +202,25 @@ queue_meta #( .aresetn(aresetn), .s_meta(req_out), .m_meta(m_req) -); +);*/ -/* -cc_queue -( - .aclk(aclk), - .aresetn(aresetn), +logic ecn_marked; +assign ecn_marked = (s_ack.data.ack.ecn == 3); +logic ecn_consumed; +assign ecn_consumed = (s_ack.valid & s_ack.ready) & s_ack.data.last; - .ecn_mark(), - .ecn_valid, - .ecn_ready, +cc_queue inst_DCQCN( + .aclk(aclk), + .aresetn(aresetn), + .ecn_mark(ecn_marked), + .ecn_write_rdy(ecn_consumed), + .s_req(req_out), .m_req(m_req) -);*/ +); /*benchy inst_cc_bench( diff --git a/scripts/ip_inst/network_infrastructure.tcl b/scripts/ip_inst/network_infrastructure.tcl index 8e81e9b12..0622a923a 100644 --- a/scripts/ip_inst/network_infrastructure.tcl +++ b/scripts/ip_inst/network_infrastructure.tcl @@ -589,7 +589,7 @@ create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_NUM_OF_PROBES {6} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_testbench_CC] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_DCQCN -set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {32} CONFIG.C_PROBE4_WIDTH {32} CONFIG.C_PROBE5_WIDTH {32} CONFIG.C_PROBE6_WIDTH {5} CONFIG.C_PROBE7_WIDTH {32} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_NUM_OF_PROBES {10} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_DCQCN] +set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {32} CONFIG.C_PROBE4_WIDTH {32} CONFIG.C_PROBE5_WIDTH {32} CONFIG.C_PROBE6_WIDTH {5} CONFIG.C_PROBE7_WIDTH {32} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {1} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_NUM_OF_PROBES {16} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_DCQCN] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_flowcontrol -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_PROBE6_WIDTH {1} CONFIG.C_PROBE7_WIDTH {1} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {1} CONFIG.C_NUM_OF_PROBES {12} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_flowcontrol] \ No newline at end of file +set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_PROBE6_WIDTH {1} CONFIG.C_PROBE7_WIDTH {1} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {1} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1}CONFIG.C_NUM_OF_PROBES {16} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_flowcontrol] \ No newline at end of file From c6307d55b447a40e3f08bde3c8b36c3f759c23dd Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Mon, 8 Sep 2025 14:41:55 +0200 Subject: [PATCH 25/52] ... --- .../rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv | 32 ++++++++----------- hw/hdl/network/rdma/MT_pomsarc_new _flow.sv | 7 ++-- scripts/ip_inst/network_infrastructure.tcl | 7 ++-- 3 files changed, 23 insertions(+), 23 deletions(-) diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv index c00adcc01..1876ea200 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv @@ -48,11 +48,7 @@ logic[31:0] time_counter; logic[4:0] step_counter; -//typedef enum logic[2:0] {ST_IDLE, ST_CALC_SR, ST_ADD_TO_QUEUE} state_t; -//logic [2:0] state_C, state_N; -//metaIntf #(.STYPE(dreq_t)) queue_in(); - -metaIntf #(.STYPE(dreq_t)) queue_out; +metaIntf #(.STYPE(dreq_t)) queue_out (); always_ff @(posedge aclk) begin if (aresetn == 1'b0) begin @@ -72,6 +68,7 @@ always_ff @(posedge aclk) begin m_req.valid <= 1'b0; queue_out.ready <= 1'b0; + m_req.data <= 0; end @@ -81,7 +78,7 @@ always_ff @(posedge aclk) begin timer_send_rate <= timer_send_rate + 1; - //s_ack.ready <= 1'b0; + step_counter <= 0; m_req.valid <= 1'b0; m_req.data <= queue_out.data; @@ -126,8 +123,7 @@ always_ff @(posedge aclk) begin byte_counter <= 0; end end - end - else begin + end else begin // case Fast Recovery Rc <= (Rt + Rc) >> 1; end @@ -137,7 +133,7 @@ always_ff @(posedge aclk) begin if(timer_send_rate > 1) begin m_req.valid <= queue_out.valid; queue_out.ready <= m_req.ready; - if(queue_out.valid & m_req.ready) begin + if(queue_out.valid && m_req.ready) begin timer_send_rate <= 0; end @@ -150,14 +146,14 @@ end ila_DCQCN inst_ila_DCQCN( .clk(aclk), - .probe0(timer), - .probe1(Rt), - .probe2(Rc), - .probe3(Sa), - .probe4(byte_counter), - .probe5(time_counter), - .probe6(step_counter), - .probe7(timer_send_rate), + .probe0(timer), //32 + .probe1(Rt), //32 + .probe2(Rc), //32 + .probe3(Sa), //32 + .probe4(byte_counter), //32 + .probe5(time_counter), //32 + .probe6(step_counter), //5 + .probe7(timer_send_rate), //32 .probe8(s_req.valid), .probe9(s_req.ready), .probe10(m_req.valid), @@ -166,7 +162,7 @@ ila_DCQCN inst_ila_DCQCN( .probe13(queue_out.ready), .probe14(ecn_mark), .probe15(ecn_write_rdy) -); +); queue_meta #( diff --git a/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv b/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv index 8eb32281f..6644a9683 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv @@ -184,6 +184,7 @@ ila_flowcontrol inst_ila_flowcontrol ( .probe15(s_ack.data.last) ); + // ACK queue queue_meta #( .QDEPTH(RDMA_N_OST) @@ -194,7 +195,8 @@ queue_meta #( .m_meta(m_ack) ); -/*// REQ queue +/* +// REQ queue queue_meta #( .QDEPTH(RDMA_N_OST) ) inst_sq ( @@ -202,7 +204,8 @@ queue_meta #( .aresetn(aresetn), .s_meta(req_out), .m_meta(m_req) -);*/ +); +*/ logic ecn_marked; diff --git a/scripts/ip_inst/network_infrastructure.tcl b/scripts/ip_inst/network_infrastructure.tcl index 0622a923a..53ac0fd0b 100644 --- a/scripts/ip_inst/network_infrastructure.tcl +++ b/scripts/ip_inst/network_infrastructure.tcl @@ -585,11 +585,12 @@ set_property -dict [list CONFIG.TDATA_NUM_BYTES {4} CONFIG.FIFO_DEPTH {128} ] [g create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_rdma_ack set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_PROBE6_WIDTH {512} CONFIG.C_PROBE7_WIDTH {64} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {512} CONFIG.C_PROBE12_WIDTH {64} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_NUM_OF_PROBES {14} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_rdma_ack] -create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_testbench_CC -set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_NUM_OF_PROBES {6} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_testbench_CC] + +#create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_testbench_CC +#set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_NUM_OF_PROBES {6} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_testbench_CC] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_DCQCN set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {32} CONFIG.C_PROBE4_WIDTH {32} CONFIG.C_PROBE5_WIDTH {32} CONFIG.C_PROBE6_WIDTH {5} CONFIG.C_PROBE7_WIDTH {32} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {1} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_NUM_OF_PROBES {16} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_DCQCN] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_flowcontrol -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_PROBE6_WIDTH {1} CONFIG.C_PROBE7_WIDTH {1} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {1} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1}CONFIG.C_NUM_OF_PROBES {16} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_flowcontrol] \ No newline at end of file +set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_PROBE6_WIDTH {1} CONFIG.C_PROBE7_WIDTH {1} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {1} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_NUM_OF_PROBES {16} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_flowcontrol] From df182a2a00eda4abd63c2ee70bfd3b90efcf20cb Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Tue, 9 Sep 2025 01:33:28 +0200 Subject: [PATCH 26/52] submodule adjusted --- hw/services/network | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/services/network b/hw/services/network index ef47e1f81..c1f85bbf4 160000 --- a/hw/services/network +++ b/hw/services/network @@ -1 +1 @@ -Subproject commit ef47e1f81e6a7fbe8177103add8866edc7f0405c +Subproject commit c1f85bbf483bbdad6e103946886a55963722fe3c From fcf4a56e784308bc9ccae49d47d447a57a50f99a Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Tue, 9 Sep 2025 10:48:22 +0200 Subject: [PATCH 27/52] fix DCQCN --- .../rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv | 95 ++++++++++++------- scripts/ip_inst/network_infrastructure.tcl | 2 +- 2 files changed, 61 insertions(+), 36 deletions(-) diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv index 1876ea200..62626024c 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv @@ -21,6 +21,7 @@ localparam integer WR_OP = 1; localparam integer Rt_default = 100000; localparam integer Rc_default = 100000; localparam integer N_min_time_between_ecn_marks = 12500; +localparam integer K = 13750; localparam integer Rai = 6250; localparam integer S1 = 128; // 1 << 8 @@ -45,7 +46,10 @@ logic[31:0] time_last_update; logic[31:0] byte_counter; logic[31:0] time_counter; -logic[4:0] step_counter; +logic[4:0] tC_C; //timecounter counter +logic[4:0] bC_C; //bytecounter counter + +logic rate_increase_event; metaIntf #(.STYPE(dreq_t)) queue_out (); @@ -64,7 +68,11 @@ always_ff @(posedge aclk) begin byte_counter <= 0; time_counter <= 0; - step_counter <= 0; + + bC_C <= 0; + tC_C <= 0; + + rate_increase_event <= 0; m_req.valid <= 1'b0; queue_out.ready <= 1'b0; @@ -77,13 +85,12 @@ always_ff @(posedge aclk) begin time_counter <= time_counter + 1; timer_send_rate <= timer_send_rate + 1; + rate_increase_event <= 0; - step_counter <= 0; m_req.valid <= 1'b0; m_req.data <= queue_out.data; queue_out.ready <= 1'b0; - //req_out.data <= s_req.data; if(ecn_write_rdy) begin byte_counter <= byte_counter + 1; @@ -93,44 +100,60 @@ always_ff @(posedge aclk) begin Rc <= (Rc << 8) / (S1 - (Sa>>1)); Sa <= (((S1-Sg)*Sa)>> 8) + Sg; time_last_update <= timer; + + time_counter <= 0; + byte_counter <= 0; + bC_C <= 0; + tC_C <= 0; + end time_of_last_marked_packet <= timer; end end - if (timer - time_of_last_marked_packet > N_min_time_between_ecn_marks) begin + if (timer - time_of_last_marked_packet > K) begin Sa <= (((S1-Sg)*Sa)>> 8); end + + if(time_counter > time_threshhold) begin + time_counter <= 0; + rate_increase_event <= 1; + if(tC_C < F) begin + tC_C <= tC_C + 1; + end + end - if(time_counter >= F || byte_counter >= F) begin - - if(time_counter >= F && byte_counter >=F) begin - // case Hyper Increse - //replaced by fast recovery - Rc <= (Rt + Rc) >> 1; - time_counter <= 0; - byte_counter <= 0; + if(byte_counter > byte_threshhold) begin + byte_counter <= 0; + rate_increase_event <= 1; + if(bC_C < F) begin + bC_C <= bC_C + 1; end - else begin - // case Additive Increase - Rt <= Rt + Rai; - Rc <= (Rt + Rc) >> 1; - if(time_counter >= F) begin - time_counter <= 0; + end + + if(rate_increase_event) begin + if(tC_C >= F || bC_C >= F) begin + + if(tC_C >= F && bC_C >= F) begin + // case Hyper Increse + //replaced by fast recovery + Rc <= (Rt + Rc) >> 1; end else begin - byte_counter <= 0; + // case Additive Increase + Rt <= Rt + Rai; + Rc <= (Rt + Rc) >> 1; end + end else begin + // case Fast Recovery + Rc <= (Rt + Rc) >> 1; end - end else begin - // case Fast Recovery - Rc <= (Rt + Rc) >> 1; end // CHANGE BACK - //if(timer_send_rate > Rc) begin - if(timer_send_rate > 1) begin + if(timer_send_rate > Rc) begin + //if(timer_send_rate > 1) begin m_req.valid <= queue_out.valid; queue_out.ready <= m_req.ready; if(queue_out.valid && m_req.ready) begin @@ -152,16 +175,18 @@ ila_DCQCN inst_ila_DCQCN( .probe3(Sa), //32 .probe4(byte_counter), //32 .probe5(time_counter), //32 - .probe6(step_counter), //5 - .probe7(timer_send_rate), //32 - .probe8(s_req.valid), - .probe9(s_req.ready), - .probe10(m_req.valid), - .probe11(m_req.ready), - .probe12(queue_out.valid), - .probe13(queue_out.ready), - .probe14(ecn_mark), - .probe15(ecn_write_rdy) + .probe6(TC_C), //5 + .probe7(BC_C), //5 + .probe8(rate_increase_event), + .probe9(timer_send_rate), //32 + .probe10(s_req.valid), + .probe11(s_req.ready), + .probe12(m_req.valid), + .probe13(m_req.ready), + .probe14(queue_out.valid), + .probe15(queue_out.ready), + .probe16(ecn_mark), + .probe17(ecn_write_rdy) ); diff --git a/scripts/ip_inst/network_infrastructure.tcl b/scripts/ip_inst/network_infrastructure.tcl index 53ac0fd0b..87eaeac72 100644 --- a/scripts/ip_inst/network_infrastructure.tcl +++ b/scripts/ip_inst/network_infrastructure.tcl @@ -590,7 +590,7 @@ set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CON #set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_NUM_OF_PROBES {6} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_testbench_CC] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_DCQCN -set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {32} CONFIG.C_PROBE4_WIDTH {32} CONFIG.C_PROBE5_WIDTH {32} CONFIG.C_PROBE6_WIDTH {5} CONFIG.C_PROBE7_WIDTH {32} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {1} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_NUM_OF_PROBES {16} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_DCQCN] +set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {32} CONFIG.C_PROBE4_WIDTH {32} CONFIG.C_PROBE5_WIDTH {32} CONFIG.C_PROBE6_WIDTH {5} CONFIG.C_PROBE7_WIDTH {5} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {32} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {1} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_PROBE16_WIDTH {1} CONFIG.C_PROBE17_WIDTH {1} CONFIG.C_NUM_OF_PROBES {18} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_DCQCN] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_flowcontrol set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_PROBE6_WIDTH {1} CONFIG.C_PROBE7_WIDTH {1} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {1} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_NUM_OF_PROBES {16} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_flowcontrol] From 88f52c06522e59c55029332178d52c3c582ed1c1 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Wed, 10 Sep 2025 11:27:09 +0200 Subject: [PATCH 28/52] more ILAS in CC module --- .../rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv | 154 +++++++++++++++--- scripts/ip_inst/network_infrastructure.tcl | 2 +- 2 files changed, 133 insertions(+), 23 deletions(-) diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv index 62626024c..e55610cab 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv @@ -33,24 +33,42 @@ localparam integer byte_threshhold = 10; -logic[31:0] Rt; -logic[31:0] Rc; -logic[31:0] Sa; -logic[31:0] timer; +logic[63:0] Rt; +logic[63:0] Rc; +logic[63:0] Sa; +logic[63:0] timer; -logic[31:0] timer_send_rate; +logic[63:0] timer_send_rate; -logic[31:0] time_of_last_marked_packet; -logic[31:0] time_last_update; +logic[63:0] time_of_last_marked_packet; +logic[63:0] time_last_update; -logic[31:0] byte_counter; -logic[31:0] time_counter; +logic[63:0] byte_counter; +logic[63:0] time_counter; logic[4:0] tC_C; //timecounter counter logic[4:0] bC_C; //bytecounter counter logic rate_increase_event; +//debug signals +logic z_ack_arrives; +logic z_marked_packet_triggers; +logic z_alpha_decrease; + +logic z_time_counter_expires; +logic z_byte_counter_expires; + +logic z_hyper_increase; +logic z_additive_increase; +logic z_fast_recovery; + +logic z_next_req_ready; + +//simul part +//logic ecn_flood; +//logic[31:0] ecn_flood_counter; + metaIntf #(.STYPE(dreq_t)) queue_out (); @@ -78,6 +96,22 @@ always_ff @(posedge aclk) begin queue_out.ready <= 1'b0; m_req.data <= 0; + z_ack_arrives <= 0; + z_marked_packet_triggers <= 0; + z_alpha_decrease <= 0; + + z_time_counter_expires <= 0; + z_byte_counter_expires <= 0; + + z_hyper_increase <= 0; + z_additive_increase <= 0; + z_fast_recovery <= 0; + + z_next_req_ready <= 0; + + //ecn_flood <= 0; + //ecn_flood_counter <= 0; + end else begin @@ -92,10 +126,39 @@ always_ff @(posedge aclk) begin m_req.data <= queue_out.data; queue_out.ready <= 1'b0; + z_ack_arrives <= 0; + z_marked_packet_triggers <= 0; + z_alpha_decrease <= 0; + + z_time_counter_expires <= 0; + z_byte_counter_expires <= 0; + + z_hyper_increase <= 0; + z_additive_increase <= 0; + z_fast_recovery <= 0; + + z_next_req_ready <= 0; + + //symul-par + /* + ecn_flood_counter <= ecn_flood_counter + 1; + if(ecn_flood_counter > 250000000 ) begin + ecn_flood_counter <= 0; + ecn_flood <= ~ecn_flood; + end*/ + if(ecn_write_rdy) begin + //===Debug Signal=== + z_ack_arrives <= 1; + //================== byte_counter <= byte_counter + 1; + //CHANGE BACK THE ECN_FLOOD + //if(ecn_mark == 1'b1/* || ecn_flood == 1'b*/) begin if(ecn_mark == 1'b1) begin // Marked Packet arrived if(timer - time_last_update > N_min_time_between_ecn_marks) begin + //===Debug Signal=== + z_marked_packet_triggers <= 1; + //================== Rt <= Rc; Rc <= (Rc << 8) / (S1 - (Sa>>1)); Sa <= (((S1-Sg)*Sa)>> 8) + Sg; @@ -112,11 +175,21 @@ always_ff @(posedge aclk) begin end if (timer - time_of_last_marked_packet > K) begin - Sa <= (((S1-Sg)*Sa)>> 8); - + //===Debug Signal=== + z_alpha_decrease <= 1; + //================== + if(Sa <= 1) begin + Sa <= 1; + end + else begin + Sa <= (((S1-Sg)*Sa)>> 8); + end end if(time_counter > time_threshhold) begin + //===Debug Signal=== + z_time_counter_expires <= 1; + //================== time_counter <= 0; rate_increase_event <= 1; if(tC_C < F) begin @@ -125,6 +198,9 @@ always_ff @(posedge aclk) begin end if(byte_counter > byte_threshhold) begin + //===Debug Signal=== + z_byte_counter_expires <= 1; + //================== byte_counter <= 0; rate_increase_event <= 1; if(bC_C < F) begin @@ -138,15 +214,29 @@ always_ff @(posedge aclk) begin if(tC_C >= F && bC_C >= F) begin // case Hyper Increse //replaced by fast recovery + //===Debug Signal=== + z_hyper_increase <= 1; + //================== Rc <= (Rt + Rc) >> 1; end else begin // case Additive Increase - Rt <= Rt + Rai; + //===Debug Signal=== + z_additive_increase <= 1; + //================== + if(Rt + 3 < Rai) begin + Rt <= 1; + end + else begin + Rt <= Rt - Rai; + end Rc <= (Rt + Rc) >> 1; end end else begin // case Fast Recovery + //===Debug Signal=== + z_fast_recovery <= 1; + //================== Rc <= (Rt + Rc) >> 1; end end @@ -154,6 +244,10 @@ always_ff @(posedge aclk) begin // CHANGE BACK if(timer_send_rate > Rc) begin //if(timer_send_rate > 1) begin + + //===Debug Signal=== + z_next_req_ready <= 1; + //================== m_req.valid <= queue_out.valid; queue_out.ready <= m_req.ready; if(queue_out.valid && m_req.ready) begin @@ -175,18 +269,34 @@ ila_DCQCN inst_ila_DCQCN( .probe3(Sa), //32 .probe4(byte_counter), //32 .probe5(time_counter), //32 - .probe6(TC_C), //5 - .probe7(BC_C), //5 + .probe6(tC_C), //5 + .probe7(bC_C), //5 .probe8(rate_increase_event), .probe9(timer_send_rate), //32 - .probe10(s_req.valid), - .probe11(s_req.ready), - .probe12(m_req.valid), - .probe13(m_req.ready), - .probe14(queue_out.valid), - .probe15(queue_out.ready), - .probe16(ecn_mark), - .probe17(ecn_write_rdy) + .probe10(time_last_update), //32 + .probe11(time_of_last_marked_packet), //32 + + .probe12(s_req.valid), + .probe13(s_req.ready), + .probe14(m_req.valid), + .probe15(m_req.ready), + .probe16(queue_out.valid), + .probe17(queue_out.ready), + .probe18(ecn_mark), + .probe19(ecn_write_rdy), + + .probe20(z_ack_arrives), + .probe21(z_marked_packet_triggers), + .probe22(z_alpha_decrease), + .probe23(z_time_counter_expires), + .probe24(z_byte_counter_expires), + .probe25(z_hyper_increase), + .probe26(z_additive_increase), + .probe27(z_fast_recovery), + .probe28(z_next_req_ready) + /* + .probe29(ecn_flood), + .probe30(ecn_flood_counter)*/ ); diff --git a/scripts/ip_inst/network_infrastructure.tcl b/scripts/ip_inst/network_infrastructure.tcl index 87eaeac72..067c55906 100644 --- a/scripts/ip_inst/network_infrastructure.tcl +++ b/scripts/ip_inst/network_infrastructure.tcl @@ -590,7 +590,7 @@ set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CON #set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_NUM_OF_PROBES {6} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_testbench_CC] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_DCQCN -set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {32} CONFIG.C_PROBE4_WIDTH {32} CONFIG.C_PROBE5_WIDTH {32} CONFIG.C_PROBE6_WIDTH {5} CONFIG.C_PROBE7_WIDTH {5} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {32} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {1} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_PROBE16_WIDTH {1} CONFIG.C_PROBE17_WIDTH {1} CONFIG.C_NUM_OF_PROBES {18} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_DCQCN] +set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {32} CONFIG.C_PROBE4_WIDTH {32} CONFIG.C_PROBE5_WIDTH {32} CONFIG.C_PROBE6_WIDTH {5} CONFIG.C_PROBE7_WIDTH {5} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {32} CONFIG.C_PROBE10_WIDTH {32} CONFIG.C_PROBE11_WIDTH {32} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_PROBE16_WIDTH {1} CONFIG.C_PROBE17_WIDTH {1} CONFIG.C_PROBE18_WIDTH {1} CONFIG.C_PROBE19_WIDTH {1} CONFIG.C_PROBE20_WIDTH {1} CONFIG.C_PROBE21_WIDTH {1} CONFIG.C_PROBE22_WIDTH {1} CONFIG.C_PROBE23_WIDTH {1} CONFIG.C_PROBE24_WIDTH {1} CONFIG.C_PROBE25_WIDTH {1} CONFIG.C_PROBE26_WIDTH {1} CONFIG.C_PROBE27_WIDTH {1} CONFIG.C_PROBE28_WIDTH {1} CONFIG.C_NUM_OF_PROBES {29} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_DCQCN] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_flowcontrol set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_PROBE6_WIDTH {1} CONFIG.C_PROBE7_WIDTH {1} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {1} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_NUM_OF_PROBES {16} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_flowcontrol] From 19a8a940def1c9fe6befdcf38f308896a0380d6c Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Thu, 11 Sep 2025 11:40:23 +0200 Subject: [PATCH 29/52] stepsized alphas added to remove division --- .../rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv | 97 ++++++++++++++----- scripts/ip_inst/network_infrastructure.tcl | 2 +- 2 files changed, 74 insertions(+), 25 deletions(-) diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv index e55610cab..b51240f63 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv @@ -18,19 +18,31 @@ localparam integer RDMA_OST_BITS = $clog2(RDMA_N_OST); localparam integer RD_OP = 0; localparam integer WR_OP = 1; -localparam integer Rt_default = 100000; -localparam integer Rc_default = 100000; -localparam integer N_min_time_between_ecn_marks = 12500; -localparam integer K = 13750; -localparam integer Rai = 6250; +//localparam integer Rt_default = 100000; +localparam integer Rt_default = 128; +localparam integer Rc_default = 8192; +localparam integer N_min_time_between_ecn_marks = 200; +localparam integer K = 600; +//localparam integer Rai = 6250; +localparam integer Rai = 60; localparam integer S1 = 128; // 1 << 8 localparam integer Sg = 8; // (1/16) << 8 localparam integer F = 5; -localparam integer time_threshhold = 100; +localparam integer time_threshhold = 150; localparam integer byte_threshhold = 10; +localparam integer Max_Sa_index = 3; +//coarse_grained +localparam integer Sa_fixed[0:3] = {16, 8, 3, 2}; +//finegrained +//localparam integer Sa_fixed[0:28] = {256, 241, 228, 218, 209, 201, 194, 188, 182, 178, 173, 170, 166, 163, 161, 158, 156, 154, 152, 150, 148, 147, 146, 144, 143, 142, 141, 140, 139}; + +logic[3:0] Sa_index; +//logic[8:0] Sa_index; + + logic[63:0] Rt; @@ -66,8 +78,8 @@ logic z_fast_recovery; logic z_next_req_ready; //simul part -//logic ecn_flood; -//logic[31:0] ecn_flood_counter; +logic[31:0] ecn_counter; +logic ecn_alternator; metaIntf #(.STYPE(dreq_t)) queue_out (); @@ -109,8 +121,10 @@ always_ff @(posedge aclk) begin z_next_req_ready <= 0; - //ecn_flood <= 0; - //ecn_flood_counter <= 0; + Sa_index <= 0; + + ecn_alternator <= 1; + ecn_counter <= 0; end @@ -139,29 +153,53 @@ always_ff @(posedge aclk) begin z_next_req_ready <= 0; - //symul-par - /* - ecn_flood_counter <= ecn_flood_counter + 1; - if(ecn_flood_counter > 250000000 ) begin - ecn_flood_counter <= 0; - ecn_flood <= ~ecn_flood; - end*/ if(ecn_write_rdy) begin //===Debug Signal=== z_ack_arrives <= 1; //================== byte_counter <= byte_counter + 1; - //CHANGE BACK THE ECN_FLOOD - //if(ecn_mark == 1'b1/* || ecn_flood == 1'b*/) begin - if(ecn_mark == 1'b1) begin // Marked Packet arrived + + /* + if(ecn_counter >= 20) begin + ecn_counter <= 0; + ecn_alternator <= ~ecn_alternator; + end/* + else begin + ecn_counter <= ecn_counter + 1; + end*/ + + + + + if(ecn_mark == 1'b1/* && ecn_alternator == 1*/) begin // Marked Packet arrived if(timer - time_last_update > N_min_time_between_ecn_marks) begin //===Debug Signal=== z_marked_packet_triggers <= 1; //================== Rt <= Rc; + + //Rc mul by 2 every time + /* + if(Rc <= 8192) begin + Rc <= Rc << 2; + end + */ + //fixed size Sa + + if(Rc <= 8192) begin + Rc <= (Rc * Sa_fixed[Sa_index]); + end + if(!(Sa_index == 0)) begin + Sa_index <= Sa_index - 1; + end + + + /* Rc <= (Rc << 8) / (S1 - (Sa>>1)); Sa <= (((S1-Sg)*Sa)>> 8) + Sg; + + */ time_last_update <= timer; time_counter <= 0; @@ -178,12 +216,21 @@ always_ff @(posedge aclk) begin //===Debug Signal=== z_alpha_decrease <= 1; //================== + /* if(Sa <= 1) begin Sa <= 1; end else begin Sa <= (((S1-Sg)*Sa)>> 8); end + */ + + + if(!(Sa_index == Max_Sa_index)) begin + Sa_index <= Sa_index + 1; + end + + end if(time_counter > time_threshhold) begin @@ -248,6 +295,7 @@ always_ff @(posedge aclk) begin //===Debug Signal=== z_next_req_ready <= 1; //================== + m_req.valid <= queue_out.valid; queue_out.ready <= m_req.ready; if(queue_out.valid && m_req.ready) begin @@ -293,10 +341,11 @@ ila_DCQCN inst_ila_DCQCN( .probe25(z_hyper_increase), .probe26(z_additive_increase), .probe27(z_fast_recovery), - .probe28(z_next_req_ready) - /* - .probe29(ecn_flood), - .probe30(ecn_flood_counter)*/ + .probe28(z_next_req_ready), + + .probe29(Sa_index), + .probe30(ecn_alternator), + .probe31(ecn_counter) ); diff --git a/scripts/ip_inst/network_infrastructure.tcl b/scripts/ip_inst/network_infrastructure.tcl index 067c55906..4ded341ad 100644 --- a/scripts/ip_inst/network_infrastructure.tcl +++ b/scripts/ip_inst/network_infrastructure.tcl @@ -590,7 +590,7 @@ set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CON #set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_NUM_OF_PROBES {6} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_testbench_CC] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_DCQCN -set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {32} CONFIG.C_PROBE4_WIDTH {32} CONFIG.C_PROBE5_WIDTH {32} CONFIG.C_PROBE6_WIDTH {5} CONFIG.C_PROBE7_WIDTH {5} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {32} CONFIG.C_PROBE10_WIDTH {32} CONFIG.C_PROBE11_WIDTH {32} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_PROBE16_WIDTH {1} CONFIG.C_PROBE17_WIDTH {1} CONFIG.C_PROBE18_WIDTH {1} CONFIG.C_PROBE19_WIDTH {1} CONFIG.C_PROBE20_WIDTH {1} CONFIG.C_PROBE21_WIDTH {1} CONFIG.C_PROBE22_WIDTH {1} CONFIG.C_PROBE23_WIDTH {1} CONFIG.C_PROBE24_WIDTH {1} CONFIG.C_PROBE25_WIDTH {1} CONFIG.C_PROBE26_WIDTH {1} CONFIG.C_PROBE27_WIDTH {1} CONFIG.C_PROBE28_WIDTH {1} CONFIG.C_NUM_OF_PROBES {29} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_DCQCN] +set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {32} CONFIG.C_PROBE4_WIDTH {32} CONFIG.C_PROBE5_WIDTH {32} CONFIG.C_PROBE6_WIDTH {5} CONFIG.C_PROBE7_WIDTH {5} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {32} CONFIG.C_PROBE10_WIDTH {32} CONFIG.C_PROBE11_WIDTH {32} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_PROBE16_WIDTH {1} CONFIG.C_PROBE17_WIDTH {1} CONFIG.C_PROBE18_WIDTH {1} CONFIG.C_PROBE19_WIDTH {1} CONFIG.C_PROBE20_WIDTH {1} CONFIG.C_PROBE21_WIDTH {1} CONFIG.C_PROBE22_WIDTH {1} CONFIG.C_PROBE23_WIDTH {1} CONFIG.C_PROBE24_WIDTH {1} CONFIG.C_PROBE25_WIDTH {1} CONFIG.C_PROBE26_WIDTH {1} CONFIG.C_PROBE27_WIDTH {1} CONFIG.C_PROBE28_WIDTH {1} CONFIG.C_PROBE29_WIDTH {4} CONFIG.C_PROBE30_WIDTH {1} CONFIG.C_PROBE31_WIDTH {32} CONFIG.C_NUM_OF_PROBES {32} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_DCQCN] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_flowcontrol set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_PROBE6_WIDTH {1} CONFIG.C_PROBE7_WIDTH {1} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {1} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_NUM_OF_PROBES {16} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_flowcontrol] From 8d8108f8b059643fcbfc4a88f7e540021ced3a09 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Fri, 12 Sep 2025 07:52:50 +0200 Subject: [PATCH 30/52] submodule ref update --- hw/services/network | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/services/network b/hw/services/network index c1f85bbf4..ffd8b038b 160000 --- a/hw/services/network +++ b/hw/services/network @@ -1 +1 @@ -Subproject commit c1f85bbf483bbdad6e103946886a55963722fe3c +Subproject commit ffd8b038b2b7145c266fed2dd9d706f24b8e7869 From a0d0be4590117ad77998443f43a2df74751507c9 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Fri, 12 Sep 2025 10:58:40 +0200 Subject: [PATCH 31/52] ... --- .../rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv | 24 ++++++++++++------- scripts/ip_inst/network_infrastructure.tcl | 2 +- 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv index b51240f63..a9de28667 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv @@ -33,14 +33,16 @@ localparam integer F = 5; localparam integer time_threshhold = 150; localparam integer byte_threshhold = 10; -localparam integer Max_Sa_index = 3; +localparam integer ecn_alternation_timeframe = 10000; + +localparam integer Max_Sa_index = 28; //coarse_grained -localparam integer Sa_fixed[0:3] = {16, 8, 3, 2}; +//localparam integer Sa_fixed[0:3] = {16, 8, 3, 2}; //finegrained -//localparam integer Sa_fixed[0:28] = {256, 241, 228, 218, 209, 201, 194, 188, 182, 178, 173, 170, 166, 163, 161, 158, 156, 154, 152, 150, 148, 147, 146, 144, 143, 142, 141, 140, 139}; +localparam integer Sa_fixed[0:28] = {256, 241, 228, 218, 209, 201, 194, 188, 182, 178, 173, 170, 166, 163, 161, 158, 156, 154, 152, 150, 148, 147, 146, 144, 143, 142, 141, 140, 139}; -logic[3:0] Sa_index; -//logic[8:0] Sa_index; +//logic[3:0] Sa_index; +logic[8:0] Sa_index; @@ -78,7 +80,7 @@ logic z_fast_recovery; logic z_next_req_ready; //simul part -logic[31:0] ecn_counter; +//logic[31:0] ecn_counter; logic ecn_alternator; @@ -169,10 +171,14 @@ always_ff @(posedge aclk) begin ecn_counter <= ecn_counter + 1; end*/ + if(timer % ecn_alternation_timeframe == 0) begin + ecn_alternator <= ~ecn_alternator; + end + - if(ecn_mark == 1'b1/* && ecn_alternator == 1*/) begin // Marked Packet arrived + if(ecn_mark == 1'b1 && ecn_alternator == 1) begin // Marked Packet arrived if(timer - time_last_update > N_min_time_between_ecn_marks) begin //===Debug Signal=== z_marked_packet_triggers <= 1; @@ -187,8 +193,8 @@ always_ff @(posedge aclk) begin */ //fixed size Sa - if(Rc <= 8192) begin - Rc <= (Rc * Sa_fixed[Sa_index]); + if(Rc <= 4096) begin + Rc <= (Rc * Sa_fixed[Sa_index]) >> 7; end if(!(Sa_index == 0)) begin Sa_index <= Sa_index - 1; diff --git a/scripts/ip_inst/network_infrastructure.tcl b/scripts/ip_inst/network_infrastructure.tcl index 4ded341ad..aed4fb44b 100644 --- a/scripts/ip_inst/network_infrastructure.tcl +++ b/scripts/ip_inst/network_infrastructure.tcl @@ -590,7 +590,7 @@ set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CON #set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_NUM_OF_PROBES {6} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_testbench_CC] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_DCQCN -set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {32} CONFIG.C_PROBE4_WIDTH {32} CONFIG.C_PROBE5_WIDTH {32} CONFIG.C_PROBE6_WIDTH {5} CONFIG.C_PROBE7_WIDTH {5} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {32} CONFIG.C_PROBE10_WIDTH {32} CONFIG.C_PROBE11_WIDTH {32} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_PROBE16_WIDTH {1} CONFIG.C_PROBE17_WIDTH {1} CONFIG.C_PROBE18_WIDTH {1} CONFIG.C_PROBE19_WIDTH {1} CONFIG.C_PROBE20_WIDTH {1} CONFIG.C_PROBE21_WIDTH {1} CONFIG.C_PROBE22_WIDTH {1} CONFIG.C_PROBE23_WIDTH {1} CONFIG.C_PROBE24_WIDTH {1} CONFIG.C_PROBE25_WIDTH {1} CONFIG.C_PROBE26_WIDTH {1} CONFIG.C_PROBE27_WIDTH {1} CONFIG.C_PROBE28_WIDTH {1} CONFIG.C_PROBE29_WIDTH {4} CONFIG.C_PROBE30_WIDTH {1} CONFIG.C_PROBE31_WIDTH {32} CONFIG.C_NUM_OF_PROBES {32} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_DCQCN] +set_property -dict [list CONFIG.C_PROBE0_WIDTH {64} CONFIG.C_PROBE1_WIDTH {64} CONFIG.C_PROBE2_WIDTH {64} CONFIG.C_PROBE3_WIDTH {64} CONFIG.C_PROBE4_WIDTH {64} CONFIG.C_PROBE5_WIDTH {64} CONFIG.C_PROBE6_WIDTH {5} CONFIG.C_PROBE7_WIDTH {5} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {64} CONFIG.C_PROBE10_WIDTH {64} CONFIG.C_PROBE11_WIDTH {64} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_PROBE16_WIDTH {1} CONFIG.C_PROBE17_WIDTH {1} CONFIG.C_PROBE18_WIDTH {1} CONFIG.C_PROBE19_WIDTH {1} CONFIG.C_PROBE20_WIDTH {1} CONFIG.C_PROBE21_WIDTH {1} CONFIG.C_PROBE22_WIDTH {1} CONFIG.C_PROBE23_WIDTH {1} CONFIG.C_PROBE24_WIDTH {1} CONFIG.C_PROBE25_WIDTH {1} CONFIG.C_PROBE26_WIDTH {1} CONFIG.C_PROBE27_WIDTH {1} CONFIG.C_PROBE28_WIDTH {1} CONFIG.C_PROBE29_WIDTH {9} CONFIG.C_PROBE30_WIDTH {1} CONFIG.C_PROBE31_WIDTH {32} CONFIG.C_NUM_OF_PROBES {32} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_DCQCN] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_flowcontrol set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_PROBE6_WIDTH {1} CONFIG.C_PROBE7_WIDTH {1} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {1} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_NUM_OF_PROBES {16} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_flowcontrol] From df2d0d9fbdfe2bbcba2ba2ca8cbdc3271a6b934b Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Mon, 15 Sep 2025 22:53:00 +0200 Subject: [PATCH 32/52] ... --- .../README.md | 186 ++++++++++++++++++ .../hw/CMakeLists.txt | 32 +++ .../hw/src/init_ip.tcl | 2 + .../hw/src/vfpga_top.svh | 71 +++++++ .../img/rdma_results_read.png | Bin 0 -> 130953 bytes .../img/rdma_results_write.png | Bin 0 -> 131862 bytes .../img/rdma_system_overview.svg | 1 + .../img/rdma_traffic_pattern.svg | 1 + .../sw/CMakeLists.txt | 26 +++ .../sw/src/client/main.cpp | 147 ++++++++++++++ .../sw/src/include/constants.hpp | 9 + .../sw/src/server/main.cpp | 120 +++++++++++ .../rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv | 70 +++---- scripts/ip_inst/network_infrastructure.tcl | 2 +- 14 files changed, 627 insertions(+), 40 deletions(-) create mode 100644 examples/MT_pomsarc_10_single_sided_writes/README.md create mode 100644 examples/MT_pomsarc_10_single_sided_writes/hw/CMakeLists.txt create mode 100644 examples/MT_pomsarc_10_single_sided_writes/hw/src/init_ip.tcl create mode 100644 examples/MT_pomsarc_10_single_sided_writes/hw/src/vfpga_top.svh create mode 100644 examples/MT_pomsarc_10_single_sided_writes/img/rdma_results_read.png create mode 100644 examples/MT_pomsarc_10_single_sided_writes/img/rdma_results_write.png create mode 100644 examples/MT_pomsarc_10_single_sided_writes/img/rdma_system_overview.svg create mode 100644 examples/MT_pomsarc_10_single_sided_writes/img/rdma_traffic_pattern.svg create mode 100644 examples/MT_pomsarc_10_single_sided_writes/sw/CMakeLists.txt create mode 100644 examples/MT_pomsarc_10_single_sided_writes/sw/src/client/main.cpp create mode 100644 examples/MT_pomsarc_10_single_sided_writes/sw/src/include/constants.hpp create mode 100644 examples/MT_pomsarc_10_single_sided_writes/sw/src/server/main.cpp diff --git a/examples/MT_pomsarc_10_single_sided_writes/README.md b/examples/MT_pomsarc_10_single_sided_writes/README.md new file mode 100644 index 000000000..f5387b7fd --- /dev/null +++ b/examples/MT_pomsarc_10_single_sided_writes/README.md @@ -0,0 +1,186 @@ +# Coyote Example 8: Using the FPGA as a SmartNIC for Remote Direct Memory Access (RDMA) +Welcome to the eigth Coyote example! If you've made it to this point, you've already learnt all the essential concepts of FPGA-CPU interaction for data movement and control flow. Thus, we're adding a new component by demonstrating how Coyote can be used to turn the FPGA into a SmartNIC for 100G RDMA-over-Converged-Ethernet (RoCE v2), allowing for efficient, high-performance data exchange between remote processing nodes and FPGA-offloaded preprocessing of the data streams. As with all Coyote examples, a brief description of the core Coyote concepts covered in this example is included below. + +##### Table of Contents +[RDMA Overview](#rdma-overview) + +[Example Overview](#example-overview) + +[Hardware Concepts](#hardware-concepts) + +[Software Concepts](#software-concepts) + +[Additional Information](#additional-information) + +## RDMA Overview +Remote Direct Memory Access over Converged Ethernet (RoCE v2) is a high-performance networking protocol originally developed for High-Performance Computing. It aims to combine high throughput, low latency and low CPU-utilization by offloading the network stack and direct memory access to the Network Interface Card (NIC), thus grounding its performance claims on host-bypassing and zero-copy: applications running on the host CPUs directly expose memory buffers for DMA to the NIC, so that data can be exchanged without including the host CPU or the OS running on it. In this example, we demonstrate how Coyote can be configured to use the FPGA in the role of such a NIC, allowing for fully protocol-compliant RoCE v2-traffic at 100 Gbps. +For further understanding of the RDMA example, we need to shed some light on the intrinsics of this network standard. +For RDMA communication, two nodes are connected via a so-called Queue Pair (QP), based on previously exchanged information such as respective IP-addresses, location and size of the allocated memory buffers and access keys, and comprising of the idea of queues for work commands and data. The initial exchange of RDMA operations are managed through so-called InfiniBand-verbs, which describe the form of memory transaction between the remote nodes. We have to separate between *one-sided operations* that initiate data transfers over the network without a previous request for consent, and *two-sided operations* where every data transaction is preceeded by an additional exchange between the communicating nodes. Coyote implements the two one-sided RDMA operations: +- ```RDMA WRITE```: One node writes data of certain length to a remote buffer in the other node. Every sent WRITE packet has to be explicitly acked by the receiving node. +- ```RDMA READ```: One node requests to read data of certain length from a remote buffer in the other node. The READ REQUEST packet is implicitly ACK'ed when the remote node sends back RDMA RESPONSE packets with the requested data. + +**IMPORTANT TERMINOLOGY:** +To have a better understanding of this example and the following descriptions, a short overview of the RDMA-specific terminology is very helpful: +- *QPN*: Queue Pair Number. Identifies a RDMA connection between two remote nodes. +- *vaddr*: Virtual address of the remote exposed buffer. For setting up a Queue Pair, a node has to share the virtual address of its exposed buffer with the remote node. +- *rkey*: Remote key for accessing the exposed buffer of the remote node. The remote key is communicated alongside the virtual address as a form of access control. +- *PSN*: Packet Sequence Number used to organize and structure a communication flow between remote RDMA-nodes. Normally, PSN-sequencing is handled by the FPGA-offloaded network stack and thus is not visible to the user. However, following the PSN order is very helpful for debugging RDMA networks. The initial PSN is agreed upon between the remote nodes as part of the initialization of the QP. +- *MTU*: Maximum Transmission Unit, defines the maximum size of a packet. Since RDMA operates on the notion of buffer transmission, the length of the data to be transmitted determines the number of MTU-sized packets that are required for the operation. While the MTU is a compile-time parameter in Coyote, the default size is 4 KB. This means that a ```RDMA WRITE``` of a buffer of up to 4 KB size results in a single packet with ```RDMA WRITE ONLY``` opcode, while a buffer of 8 KB size would be transmitted in two packets, one carrying ```RDMA WRITE FIRST```, the other with ```RDMA WRITE LAST```. For even longer buffers, an arbitrary number of ```RDMA WRITE MIDDLE``` packets is inserted in the exchange. + +## Example Overview +This example measures throughput and latency of RDMA data exchange between two remode nodes via a 100G switched network with both ```RDMA WRITE``` and ```RDMA READ``` operations. Assuming the simpler write functionality, we can very generally think about the process as moving of a data buffer from the host CPU to the local FPGA, where it is streamed to the FPGA-offloaded RDMA stack and then sent via the network to the remote FPGA. There, data is received and then written to the previously specified address of the remote buffer of this remote host CPU. Different to all previous examples, this requires two servers with FPGAs, which also run different software application. The active node, which initiates communication exchange, is referred to as the "client", while the remote node is used as "server". An example of the dataflow is given in the figure below; and as shown in the figure, the steps are the following: +1) *QP Exchange*: As explained above, the RDMA connection in form of a Queue Pair needs to be set up between the remote nodes before the actual benchmarking test can begin. Since RDMA cannot be bootstrapped, this requires out-of-band communication between the two remote CPUs via classic TCP sockets. In the context of the HACC, we are using the 10G management network for this purpose. Using ```ifconfig```, the IP address of the CPU determined to be the server can be evaluated and then given to the experiment code as a parameter. The two nodes follow a standardized protocol to exchange relevant start-up information, such as the IP- addresses of the FPGAs in the 100G data network, the initial PSN and the address and access key of the network exposed data buffers. +2) *QP Setup*: After having exchanged these essential pieces of information, both CPUs forward the aggregated QP data to the FPGAs to create the endpoints of the RDMA flow in the hardware-offloaded network stack. This means making information such as the target IP address or buffer virtual address retrievable by the QPN as essential key. +3) *REMOTE WRITE*: In case of a WRITE-based benchmark, the client now begins with a ```REMOTE WRITE``` Coyote operation to transmit a local buffer via the network to the remote node. For this, both data and commands traverse the RDMA-allocated vFGPA and reach the RDMA stack on the FPGA, where RoCE v2 packets are created and then sent out via the network. +4) *Receiving data*: In the above example, the server FPGA receives the incoming RDMA packets and automatically checks for correctness of the PSN-sequence and QP-specific information. If the received packet fits into the expected communication flow, it gets ACK'ed: an ```RDMA ACK``` is sent back to the client as a reply. At the same time, the server FPGA sends the received data as a ```LOCAL WRITE``` (see Example 1) to the local buffer on the CPU. +5) *Processing ACKs & creating completions*: The client FPGA is constantly listening to the network for ACKs for its outstanding packets. If an ACK is received, the original work command for this transaction is marked as completed, which is also communicated to the local client CPU. If no ACK is received within a certain time interval after sending out a packet, a retransmission is issued. In this case, the same packet is sent again, assuming that it was originally lost in the network or not properly received by the server. + +
+ +
+ +Generally speaking, throughput and latency tests behave vastly different, also depending on the chosen mode of operation (WRITE vs. READ). The different cases are depicted in the figure below and can be understood as following: +- *Latency* for ```RDMA WRITE```: The client issues a single WRITE of a buffer of specified length to the remote server. Upon reception, the server ACKs and then writes back this very buffer to the client, thus creating a typical "ping-pong pattern" of communication, for which the two-way latency can be measured from sending out a buffer to receiving it back. Depending on the specified experimental arguments, this exchange is repeated for a certain number of times before the average latency of all transmissions is reported. +- *Throughput* for ```RDMA WRITE```: The client issues *n* WRITEs (depending on specification of the argument in experiment execution) of a buffer of specified length to the remote server and waits for all required ACKs. Upon reception, the server writes back the same buffer *n* times again. +- *Latency* for ```RDMA READ```: The client issues a single READ of a buffer of specified length from the remote server. Instead of ACK'ing the server sends the requested data via ```RDMA READ RESPONSEs```. +- *Throughput* for ```RDMA READ``` In this case, the client issues *n* READs (depending on specification of the argument in experiment execution) of a buffer of specified length from the remote server and waits for data delivery via ```RDMA READ RESPONSEs``` from there. The server in this case does not issue reflective READs to the client. + +
+ +
+ +**IMPORTANT:** When executing RDMA benchmarks, it's important to always start the server's software first before doing the same on the client. The reason for this lies in the intrinsics of the QP exchange: The server software is constructed to listening for incoming TCP connections from the client to then take the passive role in the off-channel exchange of information. + + +## Hardware Concepts +The core complexity for RDMA in Coyote is hidden from the user within the network stack. The RDMA-dedicated vFPGA is mainly used for connecting interfaces without any additional user logic required. +The previously introduced send- and receive-queues are connected as following in the vFPGA: +```Verilog +always_comb begin + /* + * CONTROL SIGNALS + * + * rq_(wr|rd) are two more Coyote interfaces, which act as inputs to the user application + * They corresponds to network write/read requests, set from the host software and driver + * Here, they are used to set Coyote's generic send queues, previously discussed in Example 7. + */ + // Write + sq_wr.valid = rq_wr.valid; + rq_wr.ready = sq_wr.ready; + sq_wr.data = rq_wr.data; // Data field holds information such as remote, virtual address, buffer length etc. + sq_wr.data.strm = STRM_HOST; // For RDMA, by definition data is always on the host + sq_wr.data.dest = is_opcode_rd_resp(rq_wr.data.opcode) ? 0 : 1; + + // Reads + sq_rd.valid = rq_rd.valid; + rq_rd.ready = sq_rd.ready; + sq_rd.data = rq_rd.data; // Data field holds information such as remote, virtual address, buffer length etc. + sq_rd.data.strm = STRM_HOST; // For RDMA, by definition data is always on the host + sq_rd.data.dest = 1; +end +``` + +On the other hand, the data interfaces are connected as following in the module: + +```Verilog +/* + * DATA SIGNALS + * + */ +// Data streams for outgoing RDMA WRITEs (from local host to network stack to remote node) +`AXISR_ASSIGN(axis_host_recv[0], axis_rreq_send[0]) + +// Data streams for incoming RDMA READ RESPONSEs (from remote node to network stack to local host) +`AXISR_ASSIGN(axis_rreq_recv[0], axis_host_send[0]) + +// Data streams for outgoing RDMA READ RESPONSEs (from local host to network stack to remote node) +`AXISR_ASSIGN(axis_host_recv[1], axis_rrsp_send[0]) + +// Data streams for incoming RDMA WRITEs (from remote node to network stack to local host) +`AXISR_ASSIGN(axis_rrsp_recv[0], axis_host_send[1]) +``` + +Thinking one step further, beyond the scope of this performance benchmark, it becomes obvious how any pipelined user logic can be placed on these interfaces to process incoming or outgoing RDMA traffic. Placing customized user logic directly on these datapaths is one of the key benefits of a FPGA-based SmartNIC such as Coyote with the network configuration. + + +## Software Concepts +As described above, the main notion of logic abstraction in RDMA is the Queue-Pair (QP), which connects two remote nodes. Both nodes first form their own local Queue, which again is directly linked to the memory buffer that is exposed via the network. Afterwards, an off-channel exchange via TCP/IP is started to exchange the local queues and then form a QP. + +In Coyote, the notion of a QP is directly linked to a ``coyoteThread``. Thus, the first step of setting up RDMA in Coyote is creating such a thread: +```C++ +coyote::cThread coyote_thread(DEFAULT_VFPGA_ID, getpid(), 0); +```` + +Following the creation of the thread, it's necessary to call the function ```initRDMA()```, which allocates an RDMA buffer of the requested size and performs the QP exchange between the client and server. Importantly, the client needs to pass the server's IP address, while the server code leaves this field blank (nullptr, indicating that it's the server). The function return a pointer to the memory buffer to be used for RDMA communication. +```C++ +int *mem = (int *) coyote_thread.initRDMA(max_size, coyote::defPort, server_ip.c_str()); +``` + +After the setup is completed, we follow the standard approach in Coyote: creating a scatter-gather entry and issuing an ``ìnvoke(...)``` call, but this time indicating a remote operation: +```C++ +coyote::sgEntry sg; +sg.rdma = { .len = curr_size }; +coyote_thread.invoke(coyote::CoyoteOper::REMOTE_RDMA_WRITE, &sg); +``` + + +## Additional Information + +### Special remarks on building Coyote for RDMA experiments +Since different software versions are required for server and client to run a benchmark, two cmake builds have to be triggered to obtain the correct executables. In order to build the server code, one needs to specify `-DINSTANCE=server`, while a build of the client software is specified with `-DINSTANCE=client`: +```bash +cd sw/ + +mkdir build_server && cd build_server +cmake ../../ -DINSTANCE=server && make + +cd ../ +mkdir build_client && cd build_client +cmake ../../ -DINSTANCE=client && make +``` + +### Command line parameters and hints on running the experiment +As said above, it's crucial to start the software for experiments first on the node that we want to use as server, before doing the same for the client. Furthermore, it's important that the IP address specified as argument on the client machine **belongs to the server-CPU (not the client CPU, not the server FPGA)**. The different available network interfaces can be explored with ```ifconfig```. +The following description helps to match the relevant command line parameters to details of the experiment execution described before: + +- `[--ip_address | -i] ` IP address of the server CPU for out-of-band QP-exchange via TCP-sockets before the actual RDMA experiment can begin. +- `[--operation | -o] ` Decides whether the benchmark is performed for WRITE (1) or READ (0) operations. Default: 0 +- `[--min_size | -x] ` Minimum size of transferred buffer in the experiment. Default: 64 [B] +- `[--max_size | -X] ` Maximum size of transferred buffer in the experiment. Default: 1048576 [B] ~ 1 [MB] +- `[--runs | -r] ` Number of test runs, to obtain statistically significant results For latency-tests, `r` ping-pong exchanges will be executed. For throughput tests, `r` independent exchanges of 64 messages are executed. + +### Network debugging +Coyote provides tooling to check the status of network transmissions and identify potential problems, most notable packet losses and retransmissions. These statistics can be queried via +`cat /sys/kernel/coyote_sysfs_0/cyt_attr_nstats`. + +A typical output for this could look like this: +``` + -- NET STATS QSFP0 + +RX pkgs: 316 +TX pkgs: 242 +ARP RX pkgs: 4 +ARP TX pkgs: 2 +ICMP RX pkgs: 0 +ICMP TX pkgs: 0 +TCP RX pkgs: 0 +TCP TX pkgs: 0 +ROCE RX pkgs: 245 +ROCE TX pkgs: 240 +IBV RX pkgs: 240 +IBV TX pkgs: 240 +PSN drop cnt: 0 +Retrans cnt: 0 +TCP session cnt: 0 +STRM down: 0 +``` +In this case, 240 RDMA packets have been received and sent (``IBV RX/TX``), no packet has been lost or retransmitted. A major problem would be indicated by ``STRM down: 1``, as this would signal a complete shutdown of the networking stack. In such a case, only a hard reset including reprogramming the FPGA can save the user. +Apart from these Coyote-provided utilities, standard network debugging tools such as switch- or external NIC-based traffic capturing can be used to understand traffic issues and patterns. As described in the next example, we also offer a 100G-capable traffic sniffer for Coyote that directly produces pcap-files compatible to any standard network analysis tool such as wireshark. If even this low-level debugging capabilities are not deemed satisfactory, also classic ILA-based probing directly on data- and controlpaths of the FPGA-design is possible. + +### Expeted results +The following results are expected for reads (left) and writes (right): + +

+ + +

\ No newline at end of file diff --git a/examples/MT_pomsarc_10_single_sided_writes/hw/CMakeLists.txt b/examples/MT_pomsarc_10_single_sided_writes/hw/CMakeLists.txt new file mode 100644 index 000000000..e729f3666 --- /dev/null +++ b/examples/MT_pomsarc_10_single_sided_writes/hw/CMakeLists.txt @@ -0,0 +1,32 @@ +# CMake configuration +cmake_minimum_required(VERSION 3.5) +set(CYT_DIR ${CMAKE_SOURCE_DIR}/../../../) +set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CYT_DIR}/cmake) +find_package(CoyoteHW REQUIRED) + +project(example_08_perf_rdma) +message("*** Coyote Example 8: Remote Direct Memory Access (RDMA) [Hardware Build] ***") + +# Enables two streams from host memory (1 for requests, 1 for response) +set(EN_STRM 1) +set(N_STRM_AXI 2) + +# Incldue Coyote's RDMA stack during synthesis +set(EN_RDMA 1) + +# Number of vFPGAs (user applications) +set(N_REGIONS 1) + +# Build with optimization, since timing closure with RDMA can be difficult +set(BUILD_OPT 1) + +# Confirm that the selected options are allowed +validation_checks_hw() + +# Load a user application in Configuration #0, Region #0 +load_apps ( + VFPGA_C0_0 "src" +) + +# Create the hardware project +create_hw() diff --git a/examples/MT_pomsarc_10_single_sided_writes/hw/src/init_ip.tcl b/examples/MT_pomsarc_10_single_sided_writes/hw/src/init_ip.tcl new file mode 100644 index 000000000..64dc40e3d --- /dev/null +++ b/examples/MT_pomsarc_10_single_sided_writes/hw/src/init_ip.tcl @@ -0,0 +1,2 @@ +create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_perf_rdma +set_property -dict [list CONFIG.C_PROBE17_WIDTH {128} CONFIG.C_PROBE14_WIDTH {128} CONFIG.C_NUM_OF_PROBES {18} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_perf_rdma] \ No newline at end of file diff --git a/examples/MT_pomsarc_10_single_sided_writes/hw/src/vfpga_top.svh b/examples/MT_pomsarc_10_single_sided_writes/hw/src/vfpga_top.svh new file mode 100644 index 000000000..240e06b7e --- /dev/null +++ b/examples/MT_pomsarc_10_single_sided_writes/hw/src/vfpga_top.svh @@ -0,0 +1,71 @@ +always_comb begin + /* + * CONTROL SIGNALS + * + * rq_(wr|rd) are two more Coyote interfaces, which act as inputs to the user application + * They corresponds to network write/read requests, set from the host software and driver + * Here, they are used to set Coyote's generic send queues, previously discussed in Example 7. + */ + // Write + sq_wr.valid = rq_wr.valid; + rq_wr.ready = sq_wr.ready; + sq_wr.data = rq_wr.data; // Data field holds information such as remote, virtual address, buffer length etc. + sq_wr.data.strm = STRM_HOST; // For RDMA, by definition data is always on the host + sq_wr.data.dest = is_opcode_rd_resp(rq_wr.data.opcode) ? 0 : 1; + + // Reads + sq_rd.valid = rq_rd.valid; + rq_rd.ready = sq_rd.ready; + sq_rd.data = rq_rd.data; // Data field holds information such as remote, virtual address, buffer length etc. + sq_rd.data.strm = STRM_HOST; // For RDMA, by definition data is always on the host + sq_rd.data.dest = 1; +end + +/* + * DATA SIGNALS + * + */ +// Data streams for outgoing RDMA WRITEs (from local host to network stack to remote node) +`AXISR_ASSIGN(axis_host_recv[0], axis_rreq_send[0]) + +// Data streams for incoming RDMA READ RESPONSEs (from remote node to network stack to local host) +`AXISR_ASSIGN(axis_rreq_recv[0], axis_host_send[0]) + +// Data streams for outgoing RDMA READ RESPONSEs (from local host to network stack to remote node) +`AXISR_ASSIGN(axis_host_recv[1], axis_rrsp_send[0]) + +// Data streams for incoming RDMA WRITEs (from remote node to network stack to local host) +`AXISR_ASSIGN(axis_rrsp_recv[0], axis_host_send[1]) + +// Tie off unused interfaces +always_comb axi_ctrl.tie_off_s(); +always_comb notify.tie_off_m(); +always_comb cq_rd.tie_off_s(); +always_comb cq_wr.tie_off_s(); + +// ILA for debugging +ila_perf_rdma inst_ila_perf_rdma ( + .clk(aclk), + .probe0(axis_host_recv[0].tvalid), // 1 + .probe1(axis_host_recv[0].tready), // 1 + .probe2(axis_host_recv[0].tlast), // 1 + + .probe3(axis_host_recv[1].tvalid), // 1 + .probe4(axis_host_recv[1].tready), // 1 + .probe5(axis_host_recv[1].tlast), // 1 + + .probe6(axis_host_send[0].tvalid), // 1 + .probe7(axis_host_send[0].tready), // 1 + .probe8(axis_host_send[0].tlast), // 1 + + .probe9(axis_host_send[1].tvalid), // 1 + .probe10(axis_host_send[1].tready), // 1 + .probe11(axis_host_send[1].tlast), // 1 + + .probe12(sq_wr.valid), // 1 + .probe13(sq_wr.ready), // 1 + .probe14(sq_wr.data), // 128 + .probe15(sq_rd.valid), // 1 + .probe16(sq_rd.ready), // 1 + .probe17(sq_rd.data) // 128 +); diff --git a/examples/MT_pomsarc_10_single_sided_writes/img/rdma_results_read.png b/examples/MT_pomsarc_10_single_sided_writes/img/rdma_results_read.png new file mode 100644 index 0000000000000000000000000000000000000000..efc149483e13286d8c1704987b5085e0bb1f47c4 GIT binary patch literal 130953 zcmeFZRaBhM5;%wjx1b@xNzj48f?Lqw76|Tx1a}`GxCe*ePH=a3CwOpo*TLDz_07G% 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vaddr…34OUTGOING: Command & DataREMOTEWRITEdata={1, 2, 3, …}INCOMING: Command & DataLOCAL WRITEdata={1, 2, 3, …}5INCOMING: CompletionDataHeader \ No newline at end of file diff --git a/examples/MT_pomsarc_10_single_sided_writes/img/rdma_traffic_pattern.svg b/examples/MT_pomsarc_10_single_sided_writes/img/rdma_traffic_pattern.svg new file mode 100644 index 000000000..cc7223ad0 --- /dev/null +++ b/examples/MT_pomsarc_10_single_sided_writes/img/rdma_traffic_pattern.svg @@ -0,0 +1 @@ +LATENCYTHROUGHPUTRDMA WRITERDMA READCPUFPGACPUFPGACPUFPGACPUFPGACPUFPGACPUFPGACPUFPGACPUFPGARDMA WRITEACKRDMA WRITEACKRDMA WRITE…RDMA WRITERDMA WRITEACKACKRDMA WRITERDMA WRITE…READ REQUESTREAD RESPONSE…READ REQUESTREAD REQUESTREAD REQUESTREAD RESPONSEREAD RESPONSEREAD RESPONSEREAD REQUESTREAD RESPONSE \ No newline at end of file diff --git a/examples/MT_pomsarc_10_single_sided_writes/sw/CMakeLists.txt b/examples/MT_pomsarc_10_single_sided_writes/sw/CMakeLists.txt new file mode 100644 index 000000000..c3e977433 --- /dev/null +++ b/examples/MT_pomsarc_10_single_sided_writes/sw/CMakeLists.txt @@ -0,0 +1,26 @@ +# CMake configuration +cmake_minimum_required(VERSION 3.5) +project(example_08_perf_rdma) + +set(CYT_DIR ${CMAKE_SOURCE_DIR}/../../../) +set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CYT_DIR}/cmake) +find_package(CoyoteSW REQUIRED) + +# Add source files +set(INSTANCE "client" CACHE STRING "RDMA software build targe: client or server") +if(INSTANCE STREQUAL "server") + set(TARGET_DIR "${CMAKE_SOURCE_DIR}/src/server") + message("*** Coyote Example 8: RDMA Server [Software Build] ***") + include_directories("${CMAKE_SOURCE_DIR}/src/include") +endif() +if(INSTANCE STREQUAL "client") + set(TARGET_DIR "${CMAKE_SOURCE_DIR}/src/client") + message("*** Coyote Example 8: RDMA Client [Software Build] ***") + include_directories("${CMAKE_SOURCE_DIR}/src/include") +endif() + +# Create build targets and link against required libraries +set(EXEC test) +add_executable(${EXEC} ${TARGET_DIR}/main.cpp) +target_link_libraries(${EXEC} PUBLIC Coyote) +target_link_directories(${EXEC} PUBLIC /usr/local/lib) diff --git a/examples/MT_pomsarc_10_single_sided_writes/sw/src/client/main.cpp b/examples/MT_pomsarc_10_single_sided_writes/sw/src/client/main.cpp new file mode 100644 index 000000000..8bdb04fdc --- /dev/null +++ b/examples/MT_pomsarc_10_single_sided_writes/sw/src/client/main.cpp @@ -0,0 +1,147 @@ +/** + * Copyright (c) 2021-2024, Systems Group, ETH Zurich + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +// External library for easier parsing of CLI arguments by the executable +#include + +// Coyote-specific includes +#include "cBench.hpp" +#include "cThread.hpp" +#include "constants.hpp" + +constexpr bool const IS_CLIENT = true; + +double run_bench( + coyote::cThread &coyote_thread, coyote::sgEntry &sg, + int *mem, uint transfers, uint n_runs, bool operation +) { + // When writing, the server asserts the written payload is correct (which the client sets) + // When reading, the client asserts the read payload is correct (which the server sets) + for (int i = 0; i < sg.rdma.len / sizeof(int); i++) { + mem[i] = operation ? i : 0; + } + + // Before every benchmark, clear previous completion flags and sync with server + // Sync is in a way equivalent to MPI_Barrier() + auto prep_fn = [&]() { + coyote_thread.clearCompleted(); + coyote_thread.connSync(IS_CLIENT); + }; + + /* Benchmark function; as eplained in the README + * For RDMA_WRITEs, the client writes multiple times to the server and then the server writes the same content back + * For RDMA READs, the client reads from the server multiple times + * In boths cases, that means there will be n_transfers completed writes to local memory (LOCAL_WRITE) + */ + coyote::CoyoteOper coyote_operation = operation ? coyote::CoyoteOper::REMOTE_RDMA_WRITE : coyote::CoyoteOper::REMOTE_RDMA_READ; + auto bench_fn = [&]() { + for (int i = 0; i < transfers; i++) { + coyote_thread.invoke(coyote_operation, &sg); + } + /* + while (coyote_thread.checkCompleted(coyote::CoyoteOper::LOCAL_WRITE) != transfers) {} + */ + }; + + // Execute benchmark + coyote::cBench bench(n_runs, 0); + bench.execute(bench_fn, prep_fn); + + // Functional correctness check + /* + if (!operation) { + for (int i = 0; i < sg.rdma.len / sizeof(int); i++) { + assert(mem[i] == i); + } + }*/ + + // For writes, divide by 2, since that is sent two ways (from client to server and then from server to client) + // Reads are one way, so no need to scale + return bench.getAvg(); +} + +int main(int argc, char *argv[]) { + // CLI arguments + bool operation; + std::string server_ip; + unsigned int min_size, max_size, n_runs; + + boost::program_options::options_description runtime_options("Coyote Perf RDMA Options"); + runtime_options.add_options() + ("ip_address,i", boost::program_options::value(&server_ip), "Server's IP address") + ("operation,o", boost::program_options::value(&operation)->default_value(false), "Benchmark operation: READ(0) or WRITE(1)") + ("runs,r", boost::program_options::value(&n_runs)->default_value(10), "Number of times to repeat the test") + ("min_size,x", boost::program_options::value(&min_size)->default_value(64), "Starting (minimum) transfer size") + ("max_size,X", boost::program_options::value(&max_size)->default_value(1 * 1024 * 1024), "Ending (maximum) transfer size"); + boost::program_options::variables_map command_line_arguments; + boost::program_options::store(boost::program_options::parse_command_line(argc, argv, runtime_options), command_line_arguments); + boost::program_options::notify(command_line_arguments); + + PR_HEADER("CLI PARAMETERS:"); + std::cout << "SINGLE SIDED WRITE MT_ex 10: " << n_runs << std::endl; + std::cout << "Server's TCP address: " << server_ip << std::endl; + std::cout << "Benchmark operation: " << (operation ? "WRITE" : "READ") << std::endl; + std::cout << "Number of test runs: " << n_runs << std::endl; + std::cout << "Starting transfer size: " << min_size << std::endl; + std::cout << "Ending transfer size: " << max_size << std::endl << std::endl; + + /* Coyote completely abstracts the complexity behind exchanging QPs and setting up an RDMA connection + * Instead, given a cThread, the target RDMA buffer size and the remote server's TCP address, + * One can use the function initRDMA, which will allocate the buffer and + * Exchange the necessary information with the server; the server calls the equivalent function but without the IP address + */ + coyote::cThread coyote_thread(DEFAULT_VFPGA_ID, getpid(), 0); + int *mem = (int *) coyote_thread.initRDMA(max_size, coyote::defPort, server_ip.c_str()); + if (!mem) { throw std::runtime_error("Could not allocate memory; exiting..."); } + + // Benchmark sweep of latency and throughput + PR_HEADER("RDMA BENCHMARK: CLIENT"); + unsigned int curr_size = min_size; + while(curr_size <= max_size) { + std::cout << "Size: " << std::setw(8) << curr_size << "; "; + + coyote::sgEntry sg; + sg.rdma = { .len = curr_size }; + + double throughput_time = run_bench(coyote_thread, sg, mem, N_THROUGHPUT_REPS, n_runs, operation); + double throughput = ((double) N_THROUGHPUT_REPS * (double) curr_size) / (1024.0 * 1024.0 * throughput_time * 1e-9); + std::cout << "Average throughput: " << std::setw(8) << throughput << " MB/s; "; + + double latency_time = run_bench(coyote_thread, sg, mem, N_LATENCY_REPS, n_runs, operation); + std::cout << "Average latency: " << std::setw(8) << latency_time / 1e3 << " us" << std::endl; + + curr_size *= 2; + } + + // Final sync and exit + coyote_thread.connSync(IS_CLIENT); + return EXIT_SUCCESS; +} \ No newline at end of file diff --git a/examples/MT_pomsarc_10_single_sided_writes/sw/src/include/constants.hpp b/examples/MT_pomsarc_10_single_sided_writes/sw/src/include/constants.hpp new file mode 100644 index 000000000..225739d5f --- /dev/null +++ b/examples/MT_pomsarc_10_single_sided_writes/sw/src/include/constants.hpp @@ -0,0 +1,9 @@ +// Constants shared by both client and server; +// Placed in separate file to avoid any weird changes in one file not reflect in the other + +// Benchmark parameters +#define N_LATENCY_REPS 1 +#define N_THROUGHPUT_REPS 64 + +// Default vFPGA to assign cThreads to; for designs with one region (vFPGA) this is the only possible value +#define DEFAULT_VFPGA_ID 0 \ No newline at end of file diff --git a/examples/MT_pomsarc_10_single_sided_writes/sw/src/server/main.cpp b/examples/MT_pomsarc_10_single_sided_writes/sw/src/server/main.cpp new file mode 100644 index 000000000..de55dbf72 --- /dev/null +++ b/examples/MT_pomsarc_10_single_sided_writes/sw/src/server/main.cpp @@ -0,0 +1,120 @@ +/** + * Copyright (c) 2021-2024, Systems Group, ETH Zurich + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +// External library for easier parsing of CLI arguments by the executable +#include + +// Coyote-specific includes +#include "cThread.hpp" +#include "constants.hpp" + +constexpr bool const IS_CLIENT = false; + +void run_bench( + coyote::cThread &coyote_thread, coyote::sgEntry &sg, + int *mem, uint transfers, uint n_runs, bool operation +) { + // When writing, the server asserts the written payload is correct (which the client sets) + // When reading, the client asserts the read payload is correct (which the server sets) + for (int i = 0; i < sg.rdma.len / sizeof(int); i++) { + mem[i] = operation ? 0 : i; + } + + for (int i = 0; i < n_runs; i++) { + // Clear previous completion flags and sync with client + coyote_thread.clearCompleted(); + coyote_thread.connSync(IS_CLIENT); + + // For writes, wait until client has written the targer number of messages; then write them back + if (operation) { + while (coyote_thread.checkCompleted(coyote::CoyoteOper::LOCAL_WRITE) != transfers) {} + + /* + for (int i = 0; i < transfers; i++) { + coyote_thread.invoke(coyote::CoyoteOper::REMOTE_RDMA_WRITE, &sg); + }*/ + // For reads, the server is completely passive + } else { + + } + } + + // Functional correctness check + if (operation) { + for (int i = 0; i < sg.rdma.len / sizeof(int); i++) { + assert(mem[i] == i); + } + } +} + +int main(int argc, char *argv[]) { + // CLI arguments + bool operation; + unsigned int min_size, max_size, n_runs; + + boost::program_options::options_description runtime_options("Coyote Perf RDMA Options"); + runtime_options.add_options() + ("operation,o", boost::program_options::value(&operation)->default_value(false), "Benchmark operation: READ(0) or WRITE(1)") + ("runs,r", boost::program_options::value(&n_runs)->default_value(10), "Number of times to repeat the test") + ("min_size,x", boost::program_options::value(&min_size)->default_value(64), "Starting (minimum) transfer size") + ("max_size,X", boost::program_options::value(&max_size)->default_value(1 * 1024 * 1024), "Ending (maximum) transfer size"); + boost::program_options::variables_map command_line_arguments; + boost::program_options::store(boost::program_options::parse_command_line(argc, argv, runtime_options), command_line_arguments); + boost::program_options::notify(command_line_arguments); + + PR_HEADER("CLI PARAMETERS:"); + std::cout << "SINGLE SIDED WRITE MT_ex 10: " << n_runs << std::endl; + std::cout << "Benchmark operation: " << (operation ? "WRITE" : "READ") << std::endl; + std::cout << "Number of test runs: " << n_runs << std::endl; + std::cout << "Starting transfer size: " << min_size << std::endl; + std::cout << "Ending transfer size: " << max_size << std::endl << std::endl; + + // Allocate Coyothe threa and set-up RDMA connections, buffer etc. + // initRDMA is explained in more detail in client/main.cpp + coyote::cThread coyote_thread(DEFAULT_VFPGA_ID, getpid(), 0); + int *mem = (int *) coyote_thread.initRDMA(max_size, coyote::defPort); + if (!mem) { throw std::runtime_error("Could not allocate memory; exiting..."); } + + // Benchmark sweep; exactly like done in the client code + PR_HEADER("RDMA BENCHMARK: SERVER"); + unsigned int curr_size = min_size; + while(curr_size <= max_size) { + coyote::sgEntry sg; + sg.rdma = { .len = curr_size }; + run_bench(coyote_thread, sg, mem, N_THROUGHPUT_REPS, n_runs, operation); + run_bench(coyote_thread, sg, mem, N_LATENCY_REPS, n_runs, operation); + curr_size *= 2; + } + + // Final sync and exit + coyote_thread.connSync(IS_CLIENT); + return EXIT_SUCCESS; +} \ No newline at end of file diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv index a9de28667..f349db77f 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv @@ -42,26 +42,26 @@ localparam integer Max_Sa_index = 28; localparam integer Sa_fixed[0:28] = {256, 241, 228, 218, 209, 201, 194, 188, 182, 178, 173, 170, 166, 163, 161, 158, 156, 154, 152, 150, 148, 147, 146, 144, 143, 142, 141, 140, 139}; //logic[3:0] Sa_index; -logic[8:0] Sa_index; +logic[4:0] Sa_index; -logic[63:0] Rt; -logic[63:0] Rc; -logic[63:0] Sa; -logic[63:0] timer; +logic[15:0] Rt; +logic[15:0] Rc; +//logic[63:0] Sa; +logic[31:0] timer; -logic[63:0] timer_send_rate; +logic[31:0] timer_send_rate; -logic[63:0] time_of_last_marked_packet; -logic[63:0] time_last_update; +logic[31:0] time_of_last_marked_packet; +logic[31:0] time_last_update; -logic[63:0] byte_counter; -logic[63:0] time_counter; +logic[7:0] byte_counter; +logic[7:0] time_counter; -logic[4:0] tC_C; //timecounter counter -logic[4:0] bC_C; //bytecounter counter +logic[2:0] tC_C; //timecounter counter +logic[2:0] bC_C; //bytecounter counter logic rate_increase_event; @@ -80,7 +80,6 @@ logic z_fast_recovery; logic z_next_req_ready; //simul part -//logic[31:0] ecn_counter; logic ecn_alternator; @@ -90,7 +89,7 @@ always_ff @(posedge aclk) begin if (aresetn == 1'b0) begin Rt <= Rt_default; Rc <= Rc_default; - Sa <= S1; + //Sa <= S1; timer <= 0; timer_send_rate <= 0; @@ -126,7 +125,6 @@ always_ff @(posedge aclk) begin Sa_index <= 0; ecn_alternator <= 1; - ecn_counter <= 0; end @@ -162,22 +160,10 @@ always_ff @(posedge aclk) begin //================== byte_counter <= byte_counter + 1; - /* - if(ecn_counter >= 20) begin - ecn_counter <= 0; - ecn_alternator <= ~ecn_alternator; - end/* - else begin - ecn_counter <= ecn_counter + 1; - end*/ - if(timer % ecn_alternation_timeframe == 0) begin ecn_alternator <= ~ecn_alternator; end - - - if(ecn_mark == 1'b1 && ecn_alternator == 1) begin // Marked Packet arrived if(timer - time_last_update > N_min_time_between_ecn_marks) begin //===Debug Signal=== @@ -193,7 +179,7 @@ always_ff @(posedge aclk) begin */ //fixed size Sa - if(Rc <= 4096) begin + if(Rc <= 2048) begin Rc <= (Rc * Sa_fixed[Sa_index]) >> 7; end if(!(Sa_index == 0)) begin @@ -235,6 +221,8 @@ always_ff @(posedge aclk) begin if(!(Sa_index == Max_Sa_index)) begin Sa_index <= Sa_index + 1; end + + time_of_last_marked_packet <= timer; end @@ -294,6 +282,13 @@ always_ff @(posedge aclk) begin end end + if(Rc < 50) begin + Rc <= 50; + end + if(Rt < 50) begin + Rt <= 50; + end + // CHANGE BACK if(timer_send_rate > Rc) begin //if(timer_send_rate > 1) begin @@ -318,13 +313,13 @@ end ila_DCQCN inst_ila_DCQCN( .clk(aclk), .probe0(timer), //32 - .probe1(Rt), //32 - .probe2(Rc), //32 - .probe3(Sa), //32 - .probe4(byte_counter), //32 - .probe5(time_counter), //32 - .probe6(tC_C), //5 - .probe7(bC_C), //5 + .probe1(Rt), //16 + .probe2(Rc), //16 + .probe3(Sa_index), //5 + .probe4(byte_counter), //8 + .probe5(time_counter), //8 + .probe6(tC_C), //3 + .probe7(bC_C), //3 .probe8(rate_increase_event), .probe9(timer_send_rate), //32 .probe10(time_last_update), //32 @@ -348,10 +343,7 @@ ila_DCQCN inst_ila_DCQCN( .probe26(z_additive_increase), .probe27(z_fast_recovery), .probe28(z_next_req_ready), - - .probe29(Sa_index), - .probe30(ecn_alternator), - .probe31(ecn_counter) + .probe29(ecn_alternator) ); diff --git a/scripts/ip_inst/network_infrastructure.tcl b/scripts/ip_inst/network_infrastructure.tcl index aed4fb44b..b517448a2 100644 --- a/scripts/ip_inst/network_infrastructure.tcl +++ b/scripts/ip_inst/network_infrastructure.tcl @@ -590,7 +590,7 @@ set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CON #set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_NUM_OF_PROBES {6} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_testbench_CC] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_DCQCN -set_property -dict [list CONFIG.C_PROBE0_WIDTH {64} CONFIG.C_PROBE1_WIDTH {64} CONFIG.C_PROBE2_WIDTH {64} CONFIG.C_PROBE3_WIDTH {64} CONFIG.C_PROBE4_WIDTH {64} CONFIG.C_PROBE5_WIDTH {64} CONFIG.C_PROBE6_WIDTH {5} CONFIG.C_PROBE7_WIDTH {5} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {64} CONFIG.C_PROBE10_WIDTH {64} CONFIG.C_PROBE11_WIDTH {64} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_PROBE16_WIDTH {1} CONFIG.C_PROBE17_WIDTH {1} CONFIG.C_PROBE18_WIDTH {1} CONFIG.C_PROBE19_WIDTH {1} CONFIG.C_PROBE20_WIDTH {1} CONFIG.C_PROBE21_WIDTH {1} CONFIG.C_PROBE22_WIDTH {1} CONFIG.C_PROBE23_WIDTH {1} CONFIG.C_PROBE24_WIDTH {1} CONFIG.C_PROBE25_WIDTH {1} CONFIG.C_PROBE26_WIDTH {1} CONFIG.C_PROBE27_WIDTH {1} CONFIG.C_PROBE28_WIDTH {1} CONFIG.C_PROBE29_WIDTH {9} CONFIG.C_PROBE30_WIDTH {1} CONFIG.C_PROBE31_WIDTH {32} CONFIG.C_NUM_OF_PROBES {32} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_DCQCN] +set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {16} CONFIG.C_PROBE2_WIDTH {16} CONFIG.C_PROBE3_WIDTH {5} CONFIG.C_PROBE4_WIDTH {8} CONFIG.C_PROBE5_WIDTH {8} CONFIG.C_PROBE6_WIDTH {3} CONFIG.C_PROBE7_WIDTH {3} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {32} CONFIG.C_PROBE10_WIDTH {32} CONFIG.C_PROBE11_WIDTH {32} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_PROBE16_WIDTH {1} CONFIG.C_PROBE17_WIDTH {1} CONFIG.C_PROBE18_WIDTH {1} CONFIG.C_PROBE19_WIDTH {1} CONFIG.C_PROBE20_WIDTH {1} CONFIG.C_PROBE21_WIDTH {1} CONFIG.C_PROBE22_WIDTH {1} CONFIG.C_PROBE23_WIDTH {1} CONFIG.C_PROBE24_WIDTH {1} CONFIG.C_PROBE25_WIDTH {1} CONFIG.C_PROBE26_WIDTH {1} CONFIG.C_PROBE27_WIDTH {1} CONFIG.C_PROBE28_WIDTH {1} CONFIG.C_PROBE29_WIDTH {9} CONFIG.C_NUM_OF_PROBES {30} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_DCQCN] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_flowcontrol set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_PROBE6_WIDTH {1} CONFIG.C_PROBE7_WIDTH {1} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {1} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_NUM_OF_PROBES {16} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_flowcontrol] From ce9db7d9fce1eb60ba114a4aa2ac562be49ece93 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Tue, 16 Sep 2025 12:09:31 +0200 Subject: [PATCH 33/52] ex10 changed --- .../sw/src/client/main.cpp | 12 ++++++------ .../sw/src/include/constants.hpp | 4 ++-- .../sw/src/server/main.cpp | 9 +++++---- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/examples/MT_pomsarc_10_single_sided_writes/sw/src/client/main.cpp b/examples/MT_pomsarc_10_single_sided_writes/sw/src/client/main.cpp index 8bdb04fdc..09e4f9344 100644 --- a/examples/MT_pomsarc_10_single_sided_writes/sw/src/client/main.cpp +++ b/examples/MT_pomsarc_10_single_sided_writes/sw/src/client/main.cpp @@ -124,8 +124,8 @@ int main(int argc, char *argv[]) { // Benchmark sweep of latency and throughput PR_HEADER("RDMA BENCHMARK: CLIENT"); - unsigned int curr_size = min_size; - while(curr_size <= max_size) { + unsigned int curr_size = 4096; + //while(curr_size <= max_size) { std::cout << "Size: " << std::setw(8) << curr_size << "; "; coyote::sgEntry sg; @@ -135,11 +135,11 @@ int main(int argc, char *argv[]) { double throughput = ((double) N_THROUGHPUT_REPS * (double) curr_size) / (1024.0 * 1024.0 * throughput_time * 1e-9); std::cout << "Average throughput: " << std::setw(8) << throughput << " MB/s; "; - double latency_time = run_bench(coyote_thread, sg, mem, N_LATENCY_REPS, n_runs, operation); - std::cout << "Average latency: " << std::setw(8) << latency_time / 1e3 << " us" << std::endl; + //double latency_time = run_bench(coyote_thread, sg, mem, N_LATENCY_REPS, n_runs, operation); + //std::cout << "Average latency: " << std::setw(8) << latency_time / 1e3 << " us" << std::endl; + std::cout << std::endl; - curr_size *= 2; - } + //} // Final sync and exit coyote_thread.connSync(IS_CLIENT); diff --git a/examples/MT_pomsarc_10_single_sided_writes/sw/src/include/constants.hpp b/examples/MT_pomsarc_10_single_sided_writes/sw/src/include/constants.hpp index 225739d5f..2b753a69a 100644 --- a/examples/MT_pomsarc_10_single_sided_writes/sw/src/include/constants.hpp +++ b/examples/MT_pomsarc_10_single_sided_writes/sw/src/include/constants.hpp @@ -2,8 +2,8 @@ // Placed in separate file to avoid any weird changes in one file not reflect in the other // Benchmark parameters -#define N_LATENCY_REPS 1 -#define N_THROUGHPUT_REPS 64 +#define N_LATENCY_REPS 1000 +#define N_THROUGHPUT_REPS 1000 // Default vFPGA to assign cThreads to; for designs with one region (vFPGA) this is the only possible value #define DEFAULT_VFPGA_ID 0 \ No newline at end of file diff --git a/examples/MT_pomsarc_10_single_sided_writes/sw/src/server/main.cpp b/examples/MT_pomsarc_10_single_sided_writes/sw/src/server/main.cpp index de55dbf72..4aad7635e 100644 --- a/examples/MT_pomsarc_10_single_sided_writes/sw/src/server/main.cpp +++ b/examples/MT_pomsarc_10_single_sided_writes/sw/src/server/main.cpp @@ -105,16 +105,17 @@ int main(int argc, char *argv[]) { // Benchmark sweep; exactly like done in the client code PR_HEADER("RDMA BENCHMARK: SERVER"); - unsigned int curr_size = min_size; - while(curr_size <= max_size) { + unsigned int curr_size = 4096; + //while(curr_size <= max_size) { coyote::sgEntry sg; sg.rdma = { .len = curr_size }; run_bench(coyote_thread, sg, mem, N_THROUGHPUT_REPS, n_runs, operation); - run_bench(coyote_thread, sg, mem, N_LATENCY_REPS, n_runs, operation); + //run_bench(coyote_thread, sg, mem, N_LATENCY_REPS, n_runs, operation); curr_size *= 2; - } + //} // Final sync and exit coyote_thread.connSync(IS_CLIENT); + return EXIT_SUCCESS; } \ No newline at end of file From c0e76de4cf0412c3aa5ac27cddf897f98327ce40 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Tue, 16 Sep 2025 18:58:04 +0200 Subject: [PATCH 34/52] ... --- .../rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv | 111 +++++++++--------- scripts/ip_inst/network_infrastructure.tcl | 2 +- 2 files changed, 56 insertions(+), 57 deletions(-) diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv index f349db77f..3d997111f 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv @@ -33,7 +33,7 @@ localparam integer F = 5; localparam integer time_threshhold = 150; localparam integer byte_threshhold = 10; -localparam integer ecn_alternation_timeframe = 10000; +localparam integer ecn_alternation_timeframe = 5000; localparam integer Max_Sa_index = 28; //coarse_grained @@ -50,12 +50,12 @@ logic[4:0] Sa_index; logic[15:0] Rt; logic[15:0] Rc; //logic[63:0] Sa; -logic[31:0] timer; +logic[23:0] timer; -logic[31:0] timer_send_rate; +logic[23:0] timer_send_rate; -logic[31:0] time_of_last_marked_packet; -logic[31:0] time_last_update; +logic[23:0] time_of_last_marked_packet; +logic[23:0] time_last_update; logic[7:0] byte_counter; logic[7:0] time_counter; @@ -66,18 +66,18 @@ logic[2:0] bC_C; //bytecounter counter logic rate_increase_event; //debug signals -logic z_ack_arrives; -logic z_marked_packet_triggers; -logic z_alpha_decrease; +//logic z_ack_arrives; +//logic z_marked_packet_triggers; +//logic z_alpha_decrease; -logic z_time_counter_expires; -logic z_byte_counter_expires; +//logic z_time_counter_expires; +//logic z_byte_counter_expires; -logic z_hyper_increase; -logic z_additive_increase; -logic z_fast_recovery; +//logic z_hyper_increase; +//logic z_additive_increase; +//logic z_fast_recovery; -logic z_next_req_ready; +//logic z_next_req_ready; //simul part logic ecn_alternator; @@ -108,7 +108,7 @@ always_ff @(posedge aclk) begin m_req.valid <= 1'b0; queue_out.ready <= 1'b0; m_req.data <= 0; - + /* z_ack_arrives <= 0; z_marked_packet_triggers <= 0; z_alpha_decrease <= 0; @@ -121,7 +121,7 @@ always_ff @(posedge aclk) begin z_fast_recovery <= 0; z_next_req_ready <= 0; - + */ Sa_index <= 0; ecn_alternator <= 1; @@ -129,7 +129,7 @@ always_ff @(posedge aclk) begin end else begin - timer <= timer + 1; + timer = timer + 1; time_counter <= time_counter + 1; timer_send_rate <= timer_send_rate + 1; @@ -140,34 +140,35 @@ always_ff @(posedge aclk) begin m_req.data <= queue_out.data; queue_out.ready <= 1'b0; - z_ack_arrives <= 0; - z_marked_packet_triggers <= 0; - z_alpha_decrease <= 0; + //z_ack_arrives <= 0; + //z_marked_packet_triggers <= 0; + //z_alpha_decrease <= 0; - z_time_counter_expires <= 0; - z_byte_counter_expires <= 0; + //z_time_counter_expires <= 0; + //z_byte_counter_expires <= 0; - z_hyper_increase <= 0; - z_additive_increase <= 0; - z_fast_recovery <= 0; + //z_hyper_increase <= 0; + //z_additive_increase <= 0; + //z_fast_recovery <= 0; - z_next_req_ready <= 0; + //z_next_req_ready <= 0; + + if(timer % ecn_alternation_timeframe == 0) begin + ecn_alternator <= ~ecn_alternator; + end if(ecn_write_rdy) begin //===Debug Signal=== - z_ack_arrives <= 1; + //z_ack_arrives <= 1; //================== byte_counter <= byte_counter + 1; - if(timer % ecn_alternation_timeframe == 0) begin - ecn_alternator <= ~ecn_alternator; - end - + if(ecn_mark == 1'b1 && ecn_alternator == 1) begin // Marked Packet arrived if(timer - time_last_update > N_min_time_between_ecn_marks) begin //===Debug Signal=== - z_marked_packet_triggers <= 1; + //z_marked_packet_triggers <= 1; //================== Rt <= Rc; @@ -179,7 +180,7 @@ always_ff @(posedge aclk) begin */ //fixed size Sa - if(Rc <= 2048) begin + if(Rc <= 8192) begin Rc <= (Rc * Sa_fixed[Sa_index]) >> 7; end if(!(Sa_index == 0)) begin @@ -206,7 +207,7 @@ always_ff @(posedge aclk) begin if (timer - time_of_last_marked_packet > K) begin //===Debug Signal=== - z_alpha_decrease <= 1; + //z_alpha_decrease <= 1; //================== /* if(Sa <= 1) begin @@ -222,14 +223,12 @@ always_ff @(posedge aclk) begin Sa_index <= Sa_index + 1; end - time_of_last_marked_packet <= timer; - - + time_of_last_marked_packet <= timer; end if(time_counter > time_threshhold) begin //===Debug Signal=== - z_time_counter_expires <= 1; + //z_time_counter_expires <= 1; //================== time_counter <= 0; rate_increase_event <= 1; @@ -240,7 +239,7 @@ always_ff @(posedge aclk) begin if(byte_counter > byte_threshhold) begin //===Debug Signal=== - z_byte_counter_expires <= 1; + //z_byte_counter_expires <= 1; //================== byte_counter <= 0; rate_increase_event <= 1; @@ -256,14 +255,14 @@ always_ff @(posedge aclk) begin // case Hyper Increse //replaced by fast recovery //===Debug Signal=== - z_hyper_increase <= 1; + //z_hyper_increase <= 1; //================== Rc <= (Rt + Rc) >> 1; end else begin // case Additive Increase //===Debug Signal=== - z_additive_increase <= 1; + //z_additive_increase <= 1; //================== if(Rt + 3 < Rai) begin Rt <= 1; @@ -276,17 +275,17 @@ always_ff @(posedge aclk) begin end else begin // case Fast Recovery //===Debug Signal=== - z_fast_recovery <= 1; + //z_fast_recovery <= 1; //================== Rc <= (Rt + Rc) >> 1; end end - if(Rc < 50) begin - Rc <= 50; + if(Rc < 200) begin + Rc <= 200; end - if(Rt < 50) begin - Rt <= 50; + if(Rt < 200) begin + Rt <= 200; end // CHANGE BACK @@ -294,7 +293,7 @@ always_ff @(posedge aclk) begin //if(timer_send_rate > 1) begin //===Debug Signal=== - z_next_req_ready <= 1; + //z_next_req_ready <= 1; //================== m_req.valid <= queue_out.valid; @@ -312,18 +311,18 @@ end ila_DCQCN inst_ila_DCQCN( .clk(aclk), - .probe0(timer), //32 - .probe1(Rt), //16 - .probe2(Rc), //16 + .probe0(timer), //24 + .probe1(Rt), //13 + .probe2(Rc), //13 .probe3(Sa_index), //5 .probe4(byte_counter), //8 .probe5(time_counter), //8 .probe6(tC_C), //3 .probe7(bC_C), //3 .probe8(rate_increase_event), - .probe9(timer_send_rate), //32 - .probe10(time_last_update), //32 - .probe11(time_of_last_marked_packet), //32 + .probe9(timer_send_rate), //24 + .probe10(time_last_update), //24 + .probe11(time_of_last_marked_packet), //24 .probe12(s_req.valid), .probe13(s_req.ready), @@ -332,7 +331,7 @@ ila_DCQCN inst_ila_DCQCN( .probe16(queue_out.valid), .probe17(queue_out.ready), .probe18(ecn_mark), - .probe19(ecn_write_rdy), + .probe19(ecn_write_rdy),/*, .probe20(z_ack_arrives), .probe21(z_marked_packet_triggers), @@ -342,8 +341,8 @@ ila_DCQCN inst_ila_DCQCN( .probe25(z_hyper_increase), .probe26(z_additive_increase), .probe27(z_fast_recovery), - .probe28(z_next_req_ready), - .probe29(ecn_alternator) + .probe28(z_next_req_ready),*/ + .probe20(ecn_alternator) ); diff --git a/scripts/ip_inst/network_infrastructure.tcl b/scripts/ip_inst/network_infrastructure.tcl index b517448a2..4035c27c3 100644 --- a/scripts/ip_inst/network_infrastructure.tcl +++ b/scripts/ip_inst/network_infrastructure.tcl @@ -590,7 +590,7 @@ set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CON #set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_NUM_OF_PROBES {6} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_testbench_CC] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_DCQCN -set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {16} CONFIG.C_PROBE2_WIDTH {16} CONFIG.C_PROBE3_WIDTH {5} CONFIG.C_PROBE4_WIDTH {8} CONFIG.C_PROBE5_WIDTH {8} CONFIG.C_PROBE6_WIDTH {3} CONFIG.C_PROBE7_WIDTH {3} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {32} CONFIG.C_PROBE10_WIDTH {32} CONFIG.C_PROBE11_WIDTH {32} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_PROBE16_WIDTH {1} CONFIG.C_PROBE17_WIDTH {1} CONFIG.C_PROBE18_WIDTH {1} CONFIG.C_PROBE19_WIDTH {1} CONFIG.C_PROBE20_WIDTH {1} CONFIG.C_PROBE21_WIDTH {1} CONFIG.C_PROBE22_WIDTH {1} CONFIG.C_PROBE23_WIDTH {1} CONFIG.C_PROBE24_WIDTH {1} CONFIG.C_PROBE25_WIDTH {1} CONFIG.C_PROBE26_WIDTH {1} CONFIG.C_PROBE27_WIDTH {1} CONFIG.C_PROBE28_WIDTH {1} CONFIG.C_PROBE29_WIDTH {9} CONFIG.C_NUM_OF_PROBES {30} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_DCQCN] +set_property -dict [list CONFIG.C_PROBE0_WIDTH {24} CONFIG.C_PROBE1_WIDTH {16} CONFIG.C_PROBE2_WIDTH {16} CONFIG.C_PROBE3_WIDTH {5} CONFIG.C_PROBE4_WIDTH {8} CONFIG.C_PROBE5_WIDTH {8} CONFIG.C_PROBE6_WIDTH {3} CONFIG.C_PROBE7_WIDTH {3} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {24} CONFIG.C_PROBE10_WIDTH {24} CONFIG.C_PROBE11_WIDTH {24} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_PROBE16_WIDTH {1} CONFIG.C_PROBE17_WIDTH {1} CONFIG.C_PROBE18_WIDTH {1} CONFIG.C_PROBE19_WIDTH {1} CONFIG.C_PROBE20_WIDTH {1} CONFIG.C_NUM_OF_PROBES {21} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_DCQCN] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_flowcontrol set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_PROBE6_WIDTH {1} CONFIG.C_PROBE7_WIDTH {1} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {1} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_NUM_OF_PROBES {16} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_flowcontrol] From f7488bb398f2656846e51006148226eb0798f408 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Tue, 23 Sep 2025 09:20:00 +0200 Subject: [PATCH 35/52] ... --- .../rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv | 139 ++++++++++++------ scripts/ip_inst/network_infrastructure.tcl | 2 +- 2 files changed, 98 insertions(+), 43 deletions(-) diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv index 3d997111f..d37679e84 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv @@ -19,21 +19,19 @@ localparam integer RD_OP = 0; localparam integer WR_OP = 1; //localparam integer Rt_default = 100000; -localparam integer Rt_default = 128; +localparam integer Rt_default = 200; localparam integer Rc_default = 8192; -localparam integer N_min_time_between_ecn_marks = 200; -localparam integer K = 600; +localparam integer N_min_time_between_ecn_marks = 12500; +localparam integer K = 13750; //localparam integer Rai = 6250; -localparam integer Rai = 60; +localparam integer Rai = 128; localparam integer S1 = 128; // 1 << 8 localparam integer Sg = 8; // (1/16) << 8 localparam integer F = 5; -localparam integer time_threshhold = 150; -localparam integer byte_threshhold = 10; - -localparam integer ecn_alternation_timeframe = 5000; +localparam integer time_threshhold = 50000; +localparam integer byte_threshhold = 35; localparam integer Max_Sa_index = 28; //coarse_grained @@ -58,7 +56,7 @@ logic[23:0] time_of_last_marked_packet; logic[23:0] time_last_update; logic[7:0] byte_counter; -logic[7:0] time_counter; +logic[15:0] time_counter; logic[2:0] tC_C; //timecounter counter logic[2:0] bC_C; //bytecounter counter @@ -80,7 +78,26 @@ logic rate_increase_event; //logic z_next_req_ready; //simul part +logic[23:0] ecn_timer; +localparam integer ecn_timer_trigger_threshhold = 5000000; logic ecn_alternator; +logic[15:0] ecn_counter; +//1 +//localparam integer Ecn_rates[0:6] = {9999, 1, 9 ,99, 999, 9999}; +//2 +//localparam integer Ecn_rates[0:6] = {9999, 1, 9, 49 ,99, 999, 9999}; +//3 +//localparam integer Ecn_rates[0:6] = {9999, 1, 9, 14 , 19, 24, 9999}; +//4 +localparam integer Ecn_rates[0:7] = {9999, 99, 29, 24, 19, 9, 29, 39}; + +logic ecn_test_starter; +localparam Ecn_rates_max_index = 7; +logic[2:0] ecn_rates_index; + +logic[15:0] ila_readout_timer; +localparam integer Ila_readout_timer_threshhold = 40000; +logic ila_trigger; metaIntf #(.STYPE(dreq_t)) queue_out (); @@ -124,7 +141,15 @@ always_ff @(posedge aclk) begin */ Sa_index <= 0; - ecn_alternator <= 1; + + //simul + ecn_alternator <= 0; + ecn_counter <= 0; + ecn_test_starter <= 0; + ecn_timer <= 0; + ecn_rates_index <= 0; + ila_readout_timer <= 0; + ila_trigger <= 0; end @@ -140,6 +165,16 @@ always_ff @(posedge aclk) begin m_req.data <= queue_out.data; queue_out.ready <= 1'b0; + if(ila_readout_timer >= Ila_readout_timer_threshhold) begin + ila_readout_timer <= 0; + ila_trigger = 1; + end else begin + ila_readout_timer <= ila_readout_timer + 1; + ila_trigger = 0; + end + + + //z_ack_arrives <= 0; //z_marked_packet_triggers <= 0; //z_alpha_decrease <= 0; @@ -152,18 +187,47 @@ always_ff @(posedge aclk) begin //z_fast_recovery <= 0; //z_next_req_ready <= 0; + if(ecn_test_starter == 1) begin + - if(timer % ecn_alternation_timeframe == 0) begin - ecn_alternator <= ~ecn_alternator; + if(ecn_timer > ecn_timer_trigger_threshhold) begin + if(!(ecn_rates_index == Ecn_rates_max_index)) begin + ecn_rates_index <= ecn_rates_index + 1; + end + ecn_timer <= 0; + end + else begin + ecn_timer <= ecn_timer + 1; + end end + + + if(ecn_write_rdy) begin //===Debug Signal=== //z_ack_arrives <= 1; + //================== byte_counter <= byte_counter + 1; + //======simul====== + ecn_test_starter <= 1; + + + if(ecn_counter >= Ecn_rates[ecn_rates_index]) begin + ecn_counter <= 0; + ecn_alternator = 1; + end + else begin + ecn_counter <= ecn_counter + 1; + ecn_alternator = 0; + end + + + //=============================== + if(ecn_mark == 1'b1 && ecn_alternator == 1) begin // Marked Packet arrived if(timer - time_last_update > N_min_time_between_ecn_marks) begin @@ -171,28 +235,14 @@ always_ff @(posedge aclk) begin //z_marked_packet_triggers <= 1; //================== Rt <= Rc; - - //Rc mul by 2 every time - /* - if(Rc <= 8192) begin - Rc <= Rc << 2; - end - */ - //fixed size Sa - if(Rc <= 8192) begin + if(Rc <= 16384) begin Rc <= (Rc * Sa_fixed[Sa_index]) >> 7; end if(!(Sa_index == 0)) begin Sa_index <= Sa_index - 1; end - - /* - Rc <= (Rc << 8) / (S1 - (Sa>>1)); - Sa <= (((S1-Sg)*Sa)>> 8) + Sg; - - */ time_last_update <= timer; time_counter <= 0; @@ -201,7 +251,7 @@ always_ff @(posedge aclk) begin tC_C <= 0; end - time_of_last_marked_packet <= timer; + time_of_last_marked_packet = timer; end end @@ -209,15 +259,7 @@ always_ff @(posedge aclk) begin //===Debug Signal=== //z_alpha_decrease <= 1; //================== - /* - if(Sa <= 1) begin - Sa <= 1; - end - else begin - Sa <= (((S1-Sg)*Sa)>> 8); - end - */ - + if(!(Sa_index == Max_Sa_index)) begin Sa_index <= Sa_index + 1; @@ -257,7 +299,13 @@ always_ff @(posedge aclk) begin //===Debug Signal=== //z_hyper_increase <= 1; //================== - Rc <= (Rt + Rc) >> 1; + if(Rt + 3 < Rai) begin + Rt <= 1; + end + else begin + Rt <= Rt - Rai; + end + Rc <= (Rt + Rc) >> 1; end else begin // case Additive Increase @@ -312,11 +360,11 @@ end ila_DCQCN inst_ila_DCQCN( .clk(aclk), .probe0(timer), //24 - .probe1(Rt), //13 - .probe2(Rc), //13 + .probe1(Rt), //16 + .probe2(Rc), //16 .probe3(Sa_index), //5 .probe4(byte_counter), //8 - .probe5(time_counter), //8 + .probe5(time_counter), //16 .probe6(tC_C), //3 .probe7(bC_C), //3 .probe8(rate_increase_event), @@ -342,7 +390,14 @@ ila_DCQCN inst_ila_DCQCN( .probe26(z_additive_increase), .probe27(z_fast_recovery), .probe28(z_next_req_ready),*/ - .probe20(ecn_alternator) + .probe20(ecn_alternator), //1 + .probe21(ecn_counter), //16 + .probe22(ecn_timer), //24 + .probe23(ecn_test_starter), + .probe24(ecn_rates_index), // 3 + .probe25(ila_readout_timer), //16 + .probe26(ila_trigger) + ); diff --git a/scripts/ip_inst/network_infrastructure.tcl b/scripts/ip_inst/network_infrastructure.tcl index 4035c27c3..50e1ba829 100644 --- a/scripts/ip_inst/network_infrastructure.tcl +++ b/scripts/ip_inst/network_infrastructure.tcl @@ -590,7 +590,7 @@ set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CON #set_property -dict [list CONFIG.C_PROBE0_WIDTH {32} CONFIG.C_PROBE1_WIDTH {32} CONFIG.C_PROBE2_WIDTH {32} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_NUM_OF_PROBES {6} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_testbench_CC] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_DCQCN -set_property -dict [list CONFIG.C_PROBE0_WIDTH {24} CONFIG.C_PROBE1_WIDTH {16} CONFIG.C_PROBE2_WIDTH {16} CONFIG.C_PROBE3_WIDTH {5} CONFIG.C_PROBE4_WIDTH {8} CONFIG.C_PROBE5_WIDTH {8} CONFIG.C_PROBE6_WIDTH {3} CONFIG.C_PROBE7_WIDTH {3} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {24} CONFIG.C_PROBE10_WIDTH {24} CONFIG.C_PROBE11_WIDTH {24} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_PROBE16_WIDTH {1} CONFIG.C_PROBE17_WIDTH {1} CONFIG.C_PROBE18_WIDTH {1} CONFIG.C_PROBE19_WIDTH {1} CONFIG.C_PROBE20_WIDTH {1} CONFIG.C_NUM_OF_PROBES {21} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_DCQCN] +set_property -dict [list CONFIG.C_PROBE0_WIDTH {24} CONFIG.C_PROBE1_WIDTH {16} CONFIG.C_PROBE2_WIDTH {16} CONFIG.C_PROBE3_WIDTH {5} CONFIG.C_PROBE4_WIDTH {8} CONFIG.C_PROBE5_WIDTH {16} CONFIG.C_PROBE6_WIDTH {3} CONFIG.C_PROBE7_WIDTH {3} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {24} CONFIG.C_PROBE10_WIDTH {24} CONFIG.C_PROBE11_WIDTH {24} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_PROBE16_WIDTH {1} CONFIG.C_PROBE17_WIDTH {1} CONFIG.C_PROBE18_WIDTH {1} CONFIG.C_PROBE19_WIDTH {1} CONFIG.C_PROBE20_WIDTH {1} CONFIG.C_PROBE21_WIDTH {16} CONFIG.C_PROBE22_WIDTH {24} CONFIG.C_PROBE23_WIDTH {1} CONFIG.C_PROBE24_WIDTH {3} CONFIG.C_PROBE25_WIDTH {16} CONFIG.C_PROBE26_WIDTH {1} CONFIG.C_NUM_OF_PROBES {27} CONFIG.C_DATA_DEPTH {16384} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_DCQCN] create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_flowcontrol set_property -dict [list CONFIG.C_PROBE0_WIDTH {1} CONFIG.C_PROBE1_WIDTH {1} CONFIG.C_PROBE2_WIDTH {1} CONFIG.C_PROBE3_WIDTH {1} CONFIG.C_PROBE4_WIDTH {1} CONFIG.C_PROBE5_WIDTH {1} CONFIG.C_PROBE6_WIDTH {1} CONFIG.C_PROBE7_WIDTH {1} CONFIG.C_PROBE8_WIDTH {1} CONFIG.C_PROBE9_WIDTH {1} CONFIG.C_PROBE10_WIDTH {1} CONFIG.C_PROBE11_WIDTH {1} CONFIG.C_PROBE12_WIDTH {1} CONFIG.C_PROBE13_WIDTH {1} CONFIG.C_PROBE14_WIDTH {1} CONFIG.C_PROBE15_WIDTH {1} CONFIG.C_NUM_OF_PROBES {16} CONFIG.C_DATA_DEPTH {8192} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_flowcontrol] From 04b5a122a35c3e0ba486b0aa354bb0cbde5e7183 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Thu, 30 Oct 2025 23:21:03 +0100 Subject: [PATCH 36/52] safety commit --- .../rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv | 231 ++++++++ .../rdma/MT_pomsarc_CC_QP_unit_Timely.sv | 0 hw/hdl/network/rdma/MT_pomsarc_new _flow.sv | 552 ++++++++++++------ .../rdma/MT_pomsarc_new_flow_multiqueue.sv | 319 ++++++++++ 4 files changed, 914 insertions(+), 188 deletions(-) delete mode 100644 hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_Timely.sv diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv index d37679e84..de90a3fb2 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv @@ -411,4 +411,235 @@ queue_meta #( ); +endmodule + + + +// NO TEST PART + + + +import lynxTypes::*; + +module cc_queue +( + input logic aclk, + input logic aresetn, + + input logic ecn_mark, + input logic ecn_write_rdy, + + metaIntf.s s_req, + metaIntf.m m_req +); + +//localparam integer RDMA_N_OST = RDMA_N_WR_OUTSTANDING; +//localparam integer RDMA_N_OST = 20; +//localparam integer RDMA_OST_BITS = $clog2(RDMA_N_OST); + +localparam integer RDMA_N_OST = 100; +localparam integer RDMA_OST_BITS = $clog2(RDMA_N_OST); + +localparam integer RD_OP = 0; +localparam integer WR_OP = 1; + +//localparam integer Rt_default = 100000; +localparam integer Rt_default = 200; +localparam integer Rc_default = 8192; +localparam integer N_min_time_between_ecn_marks = 12500; +localparam integer K = 13750; +//localparam integer Rai = 6250; +localparam integer Rai = 128; + +localparam integer S1 = 128; // 1 << 8 +localparam integer Sg = 8; // (1/16) << 8 +localparam integer F = 5; + +localparam integer time_threshhold = 50000; +localparam integer byte_threshhold = 35; + +localparam integer Max_Sa_index = 28; +//coarse_grained +//localparam integer Sa_fixed[0:3] = {16, 8, 3, 2}; +//finegrained +localparam integer Sa_fixed[0:28] = {256, 241, 228, 218, 209, 201, 194, 188, 182, 178, 173, 170, 166, 163, 161, 158, 156, 154, 152, 150, 148, 147, 146, 144, 143, 142, 141, 140, 139}; + +//logic[3:0] Sa_index; +logic[4:0] Sa_index; + + + + +logic[15:0] Rt; +logic[15:0] Rc; +//logic[63:0] Sa; +logic[23:0] timer; + +logic[23:0] timer_send_rate; + +logic[23:0] time_of_last_marked_packet; +logic[23:0] time_last_update; + +logic[7:0] byte_counter; +logic[15:0] time_counter; + +logic[2:0] tC_C; //timecounter counter +logic[2:0] bC_C; //bytecounter counter + +logic rate_increase_event; + + +metaIntf #(.STYPE(dreq_t)) queue_out (); + +always_ff @(posedge aclk) begin + if (aresetn == 1'b0) begin + Rt <= Rt_default; + Rc <= Rc_default; + + timer <= 0; + + timer_send_rate <= 0; + + time_of_last_marked_packet <= 0; + time_last_update <= 0; + + byte_counter <= 0; + time_counter <= 0; + + bC_C <= 0; + tC_C <= 0; + + rate_increase_event <= 0; + + m_req.valid <= 1'b0; + queue_out.ready <= 1'b0; + m_req.data <= 0; + + + Sa_index <= 0; + + + end + else begin + timer = timer + 1; + time_counter <= time_counter + 1; + timer_send_rate <= timer_send_rate + 1; + + rate_increase_event <= 0; + + + m_req.valid <= 1'b0; + m_req.data <= queue_out.data; + queue_out.ready <= 1'b0; + + + + if(ecn_write_rdy) begin + byte_counter <= byte_counter + 1; + + + if(ecn_mark == 1'b1) begin // Marked Packet arrived + if(timer - time_last_update > N_min_time_between_ecn_marks) begin + Rt <= Rc; + + if(Rc <= 16384) begin + Rc <= (Rc * Sa_fixed[Sa_index]) >> 7; + end + if(!(Sa_index == 0)) begin + Sa_index <= Sa_index - 1; + end + + time_last_update <= timer; + + time_counter <= 0; + byte_counter <= 0; + bC_C <= 0; + tC_C <= 0; + + end + time_of_last_marked_packet = timer; + end + end + + if (timer - time_of_last_marked_packet > K) begin + if(!(Sa_index == Max_Sa_index)) begin + Sa_index <= Sa_index + 1; + end + time_of_last_marked_packet <= timer; + end + + if(time_counter > time_threshhold) begin + time_counter <= 0; + rate_increase_event <= 1; + if(tC_C < F) begin + tC_C <= tC_C + 1; + end + end + + if(byte_counter > byte_threshhold) begin + byte_counter <= 0; + rate_increase_event <= 1; + if(bC_C < F) begin + bC_C <= bC_C + 1; + end + end + + if(rate_increase_event) begin + if(tC_C >= F || bC_C >= F) begin + + if(tC_C >= F && bC_C >= F) begin + if(Rt + 3 < Rai) begin + Rt <= 1; + end + else begin + Rt <= Rt - Rai; + end + Rc <= (Rt + Rc) >> 1; + end + else begin + if(Rt + 3 < Rai) begin + Rt <= 1; + end + else begin + Rt <= Rt - Rai; + end + Rc <= (Rt + Rc) >> 1; + end + end else begin + Rc <= (Rt + Rc) >> 1; + end + end + + if(Rc < 200) begin + Rc <= 200; + end + if(Rt < 200) begin + Rt <= 200; + end + + if(timer_send_rate > Rc) begin + + m_req.valid <= queue_out.valid; + queue_out.ready <= m_req.ready; + if(queue_out.valid && m_req.ready) begin + timer_send_rate <= 0; + end + + end + + + end +end + + +queue_meta #( + .QDEPTH(RDMA_N_OST) +) inst_cq ( + .aclk(aclk), + .aresetn(aresetn), + .s_meta(s_req), + .m_meta(queue_out) +); + + endmodule \ No newline at end of file diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_Timely.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_Timely.sv deleted file mode 100644 index e69de29bb..000000000 diff --git a/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv b/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv index 6644a9683..2f9e9312d 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv @@ -1,237 +1,413 @@ import lynxTypes::*; -module rdma_flow ( - metaIntf.s s_req, - metaIntf.m m_req, +module cc_queue +( + input logic aclk, + input logic aresetn, - metaIntf.s s_ack, - metaIntf.m m_ack, + input logic ecn_mark, + input logic ecn_write_rdy, - input logic aclk, - input logic aresetn + metaIntf.s s_req, + metaIntf.m m_req ); -localparam integer RDMA_N_OST = RDMA_N_WR_OUTSTANDING; -localparam integer RDMA_OST_BITS = $clog2(RDMA_N_OST); -localparam integer RD_OP = 0; -localparam integer WR_OP = 1; - -// -- FSM -typedef enum logic[2:0] {ST_IDLE, ST_ACK_LUP_WAIT, ST_REQ_LUP_WAIT, ST_ACK_LUP, ST_REQ_LUP} state_t; -logic [2:0] state_C, state_N; -logic [1+N_REGIONS_BITS+PID_BITS-1:0] addr_C, addr_N; - -logic [1:0] ssn_wr; -logic [1+N_REGIONS_BITS+PID_BITS-1:0] ssn_addr; -logic [15:0] ssn_in; -logic [15:0] ssn_out; - -metaIntf #(.STYPE(ack_t)) ack_que_in (); -metaIntf #(.STYPE(dreq_t)) req_out (); - -logic [RDMA_OST_BITS-1:0] tail, tail_next; -logic [RDMA_OST_BITS-1:0] head, head_next; -logic issued, issued_next; - - -// Pointer table -ram_sp_nc #( - .ADDR_BITS(1+N_REGIONS_BITS+PID_BITS), - .DATA_BITS(16) -) inst_pntr_table ( - .clk(aclk), - .a_en(1'b1), - .a_we(ssn_wr), - .a_addr(ssn_addr), - .a_data_in(ssn_in), - .a_data_out(ssn_out) -); +//======================================================== +// DCQCN PARAMETERS +//======================================================== + +localparam integer REQ_QUEUE_SIZE = 10; + +//localparam integer Rt_default = 100000; +localparam integer Rt_default = 200; +localparam integer Rc_default = 8192; +localparam integer N_min_time_between_ecn_marks = 12500; +localparam integer K = 13750; +localparam integer Rai = 128; + + + +localparam integer S1 = 128; // 1 << 8 +localparam integer Sg = 8; // (1/16) << 8 +localparam integer F = 5; + +//normal +localparam integer time_threshhold = 50000; +//increased T test +//localparam integer time_threshhold = 100000; + +localparam integer byte_threshhold = 35; + + +localparam integer Max_Sa_index = 28; +localparam integer Sa_fixed[0:28] = {256, 241, 228, 218, 209, 201, 194, 188, 182, 178, 173, 170, 166, 163, 161, 158, 156, 154, 152, 150, 148, 147, 146, 144, 143, 142, 141, 140, 139}; +logic[4:0] Sa_index; + + + + +logic[15:0] Rt; +logic[15:0] Rc; +logic[23:0] timer; + +logic[23:0] timer_send_rate; + +logic[23:0] time_of_last_marked_packet; +logic[23:0] time_last_update; + +logic[7:0] byte_counter; +logic[15:0] time_counter; + +logic[2:0] tC_C; //timecounter counter +logic[2:0] bC_C; //bytecounter counter -// REG -always_ff @(posedge aclk) begin: PROC_REG +logic rate_increase_event; + +//debug signals +//logic z_ack_arrives; +//logic z_marked_packet_triggers; +//logic z_alpha_decrease; + +//logic z_time_counter_expires; +//logic z_byte_counter_expires; + +//logic z_hyper_increase; +//logic z_additive_increase; +//logic z_fast_recovery; + +//logic z_next_req_ready; + +//simul part +logic[23:0] ecn_timer; +localparam integer ecn_timer_trigger_threshhold = 5000000; +logic ecn_alternator; +logic[15:0] ecn_counter; +//1 +//localparam integer Ecn_rates[0:6] = {9999, 1, 9 ,99, 999, 9999}; +//2 +//localparam integer Ecn_rates[0:6] = {9999, 1, 9, 49 ,99, 999, 9999}; +//3 +//localparam integer Ecn_rates[0:6] = {9999, 1, 9, 14 , 19, 24, 9999}; +//4 +localparam integer Ecn_rates[0:15] = {9999, 99, 29, 24, 19, 9, 29, 39, 39, 99, 99, 149, 149,199,199,9999}; + +logic ecn_test_starter; +localparam Ecn_rates_max_index = 15; +logic[4:0] ecn_rates_index; + +logic[15:0] ila_readout_timer; +localparam integer Ila_readout_timer_threshhold = 40000; +logic ila_trigger; + + +metaIntf #(.STYPE(dreq_t)) queue_out (); + +always_ff @(posedge aclk) begin if (aresetn == 1'b0) begin - state_C <= ST_IDLE; - addr_C <= 'X; - end - else begin - state_C <= state_N; - addr_C <= addr_N; - end -end + Rt <= Rt_default; + Rc <= Rc_default; + timer <= 0; -// NSL -always_comb begin: NSL - state_N = state_C; + timer_send_rate <= 0; - case(state_C) - ST_IDLE: - state_N = (s_ack.valid) ? ST_ACK_LUP_WAIT : (s_req.valid & req_out.ready ? ST_REQ_LUP_WAIT : ST_IDLE); + time_of_last_marked_packet <= 0; + time_last_update <= 0; - ST_ACK_LUP_WAIT: - state_N = ST_ACK_LUP; + byte_counter <= 0; + time_counter <= 0; + + bC_C <= 0; + tC_C <= 0; - ST_REQ_LUP_WAIT: - state_N = ST_REQ_LUP; + rate_increase_event <= 0; - ST_REQ_LUP: - state_N = ST_IDLE; + m_req.valid <= 1'b0; + queue_out.ready <= 1'b0; + m_req.data <= 0; + /* + z_ack_arrives <= 0; + z_marked_packet_triggers <= 0; + z_alpha_decrease <= 0; - ST_ACK_LUP: - state_N = ST_IDLE; + z_time_counter_expires <= 0; + z_byte_counter_expires <= 0; - endcase // state_C -end + z_hyper_increase <= 0; + z_additive_increase <= 0; + z_fast_recovery <= 0; + + z_next_req_ready <= 0; + */ + Sa_index <= 0; -// DP -assign ssn_in = {7'h00, issued_next, head_next, tail_next}; -assign issued = ssn_out[2*RDMA_OST_BITS]; -assign head = ssn_out[RDMA_OST_BITS+:RDMA_OST_BITS]; -assign tail = ssn_out[0+:RDMA_OST_BITS]; - -always_comb begin: DP - addr_N = addr_C; - - // ACKs - s_ack.ready = 1'b0; - - ack_que_in.valid = 1'b0; - ack_que_in.data = s_ack.data.ack; - - // Req - s_req.ready = 1'b0; - req_out.valid = 1'b0; - req_out.data = s_req.data; - req_out.data.req_1.offs = head; - - // Table - ssn_wr = 0; - ssn_addr = 0; - - // Pointers - head_next = 0; - tail_next = 0; - issued_next = 0; - - case(state_C) - ST_IDLE: begin - if(s_ack.valid) begin - s_ack.ready = 1'b1; - ack_que_in.valid = s_ack.data.last; - - ssn_addr = {is_opcode_rd_resp(s_ack.data.ack.opcode), s_ack.data.ack.vfid[N_REGIONS_BITS-1:0], s_ack.data.ack.pid}; - addr_N = ssn_addr; - end - else if(s_req.valid & req_out.ready) begin - ssn_addr = {is_opcode_rd_req(s_req.data.req_1.opcode), s_req.data.req_1.vfid[N_REGIONS_BITS-1:0], s_req.data.req_1.pid}; - addr_N = ssn_addr; - end - end - ST_ACK_LUP: begin - head_next = head; - tail_next = tail + 1; - if(head == tail_next) - issued_next = 1'b0; - else - issued_next = issued; + //simul + ecn_alternator <= 0; + ecn_counter <= 0; + ecn_test_starter <= 0; + ecn_timer <= 0; + ecn_rates_index <= 0; + ila_readout_timer <= 0; + ila_trigger <= 0; - ssn_wr = ~0; - ssn_addr = addr_C; + + end + else begin + timer = timer + 1; + time_counter <= time_counter + 1; + timer_send_rate <= timer_send_rate + 1; + + rate_increase_event <= 0; + + + m_req.valid <= 1'b0; + m_req.data <= queue_out.data; + queue_out.ready <= 1'b0; + + if(ila_readout_timer >= Ila_readout_timer_threshhold) begin + ila_readout_timer <= 0; + ila_trigger = 1; + end else begin + ila_readout_timer <= ila_readout_timer + 1; + ila_trigger = 0; end - ST_REQ_LUP: begin - if(!issued || (head != tail)) begin - req_out.valid = 1'b1; - s_req.ready = 1'b1; - head_next = head + 1; - tail_next = tail; - issued_next = 1'b1; - ssn_wr = ~0; - ssn_addr = addr_C; + //z_ack_arrives <= 0; + //z_marked_packet_triggers <= 0; + //z_alpha_decrease <= 0; + + //z_time_counter_expires <= 0; + //z_byte_counter_expires <= 0; + + //z_hyper_increase <= 0; + //z_additive_increase <= 0; + //z_fast_recovery <= 0; + + //z_next_req_ready <= 0; + if(ecn_test_starter == 1) begin + + + if(ecn_timer > ecn_timer_trigger_threshhold) begin + if(!(ecn_rates_index == Ecn_rates_max_index)) begin + ecn_rates_index <= ecn_rates_index + 1; + end + ecn_timer <= 0; + end + else begin + ecn_timer <= ecn_timer + 1; end end - endcase -end -ila_flowcontrol inst_ila_flowcontrol ( - .clk(aclk), - .probe0(ack_que_in.valid), - .probe1(ack_que_in.ready), - .probe2(s_ack.valid), - .probe3(s_ack.ready), + if(ecn_write_rdy) begin + //===Debug Signal=== + //z_ack_arrives <= 1; - .probe4(m_ack.valid), - .probe5(m_ack.ready), + //================== + byte_counter <= byte_counter + 1; - .probe6(req_out.valid), - .probe7(req_out.ready), + //======simul====== + ecn_test_starter <= 1; - .probe8(s_req.valid), - .probe9(s_req.ready), + + if(ecn_counter >= Ecn_rates[ecn_rates_index]) begin + ecn_counter <= 0; + ecn_alternator = 1; + end + else begin + ecn_counter <= ecn_counter + 1; + ecn_alternator = 0; + end - .probe10(m_req.valid), - .probe11(m_req.ready), + + //=============================== + + + if(ecn_mark == 1'b1 && ecn_alternator == 1) begin // Marked Packet arrived + if(timer - time_last_update > N_min_time_between_ecn_marks) begin + //===Debug Signal=== + //z_marked_packet_triggers <= 1; + //================== + Rt <= Rc; + + if(Rc <= 16384) begin + Rc <= (Rc * Sa_fixed[Sa_index]) >> 7; + end + if(!(Sa_index == 0)) begin + Sa_index <= Sa_index - 1; + end + + time_last_update <= timer; + + time_counter <= 0; + byte_counter <= 0; + bC_C <= 0; + tC_C <= 0; + + end + time_of_last_marked_packet = timer; + end + end - .probe12(ecn_marked), - .probe13(ecn_consumed), - .probe14(s_ack.data.ack.ecn), - .probe15(s_ack.data.last) -); + if (timer - time_of_last_marked_packet > K) begin + //===Debug Signal=== + //z_alpha_decrease <= 1; + //================== + + + if(!(Sa_index == Max_Sa_index)) begin + Sa_index <= Sa_index + 1; + end + + time_of_last_marked_packet <= timer; + end + + if(time_counter > time_threshhold) begin + //===Debug Signal=== + //z_time_counter_expires <= 1; + //================== + time_counter <= 0; + rate_increase_event <= 1; + if(tC_C < F) begin + tC_C <= tC_C + 1; + end + end + if(byte_counter > byte_threshhold) begin + //===Debug Signal=== + //z_byte_counter_expires <= 1; + //================== + byte_counter <= 0; + rate_increase_event <= 1; + if(bC_C < F) begin + bC_C <= bC_C + 1; + end + end -// ACK queue -queue_meta #( - .QDEPTH(RDMA_N_OST) -) inst_cq ( - .aclk(aclk), - .aresetn(aresetn), - .s_meta(ack_que_in), - .m_meta(m_ack) -); + if(rate_increase_event) begin + if(tC_C >= F || bC_C >= F) begin + + if(tC_C >= F && bC_C >= F) begin + // case Hyper Increse + //replaced by fast recovery + //===Debug Signal=== + //z_hyper_increase <= 1; + //================== + if(Rt + 3 < Rai) begin + Rt <= 1; + end + else begin + Rt <= Rt - Rai; + end + Rc <= (Rt + Rc) >> 1; + end + else begin + // case Additive Increase + //===Debug Signal=== + //z_additive_increase <= 1; + //================== + if(Rt + 3 < Rai) begin + Rt <= 1; + end + else begin + Rt <= Rt - Rai; + end + Rc <= (Rt + Rc) >> 1; + end + end else begin + // case Fast Recovery + //===Debug Signal=== + //z_fast_recovery <= 1; + //================== + Rc <= (Rt + Rc) >> 1; + end + end -/* -// REQ queue -queue_meta #( - .QDEPTH(RDMA_N_OST) -) inst_sq ( - .aclk(aclk), - .aresetn(aresetn), - .s_meta(req_out), - .m_meta(m_req) -); -*/ + if(Rc < 200) begin + Rc <= 200; + end + if(Rt < 200) begin + Rt <= 200; + end + // CHANGE BACK + if(timer_send_rate > Rc) begin + //if(timer_send_rate > 1) begin -logic ecn_marked; -assign ecn_marked = (s_ack.data.ack.ecn == 3); -logic ecn_consumed; -assign ecn_consumed = (s_ack.valid & s_ack.ready) & s_ack.data.last; + //===Debug Signal=== + //z_next_req_ready <= 1; + //================== + m_req.valid <= queue_out.valid; + queue_out.ready <= m_req.ready; + if(queue_out.valid && m_req.ready) begin + timer_send_rate <= 0; + end -cc_queue inst_DCQCN( - .aclk(aclk), - .aresetn(aresetn), + end + + + end +end + + +ila_DCQCN inst_ila_DCQCN( + .clk(aclk), + .probe0(timer), //24 + .probe1(Rt), //16 + .probe2(Rc), //16 + .probe3(Sa_index), //5 + .probe4(byte_counter), //8 + .probe5(time_counter), //16 + .probe6(tC_C), //3 + .probe7(bC_C), //3 + .probe8(rate_increase_event), + .probe9(timer_send_rate), //24 + .probe10(time_last_update), //24 + .probe11(time_of_last_marked_packet), //24 + + .probe12(s_req.valid), + .probe13(s_req.ready), + .probe14(m_req.valid), + .probe15(m_req.ready), + .probe16(queue_out.valid), + .probe17(queue_out.ready), + .probe18(ecn_mark), + .probe19(ecn_write_rdy), + + //.probe20(z_ack_arrives), + //.probe21(z_marked_packet_triggers), + //.probe22(z_alpha_decrease), + //.probe23(z_time_counter_expires), + //.probe24(z_byte_counter_expires), + //.probe25(z_hyper_increase), + //.probe26(z_additive_increase), + //.probe27(z_fast_recovery), + //.probe28(z_next_req_ready), + .probe20(ecn_alternator), //1 + .probe21(ecn_counter), //16 + .probe22(ecn_timer), //24 + .probe23(ecn_test_starter), + .probe24(ecn_rates_index), // 5 + .probe25(ila_readout_timer), //16 + .probe26(ila_trigger) - .ecn_mark(ecn_marked), - .ecn_write_rdy(ecn_consumed), - - .s_req(req_out), - .m_req(m_req) ); -/*benchy inst_cc_bench( +queue_meta #( + .QDEPTH(REQ_QUEUE_SIZE) +) inst_cq ( .aclk(aclk), .aresetn(aresetn), + .s_meta(s_req), + .m_meta(queue_out) +); - .s_req(req_out), - .m_req(m_req) -);*/ -endmodule +endmodule \ No newline at end of file diff --git a/hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv b/hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv index e69de29bb..953afe93f 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv @@ -0,0 +1,319 @@ +import lynxTypes::*; + +module rdma_flow ( + metaIntf.s s_req, + metaIntf.m m_req, + + metaIntf.s s_ack, + metaIntf.m m_ack, + + input logic aclk, + input logic aresetn +); + +localparam integer RDMA_N_OST = RDMA_N_WR_OUTSTANDING; +localparam integer RDMA_OST_BITS = $clog2(RDMA_N_OST); +localparam integer RD_OP = 0; +localparam integer WR_OP = 1; + +// -- FSM +typedef enum logic[2:0] {ST_IDLE, ST_ACK_LUP_WAIT, ST_REQ_LUP_WAIT, ST_ACK_LUP, ST_REQ_LUP} state_t; +logic [2:0] state_C, state_N; +logic [1+N_REGIONS_BITS+PID_BITS-1:0] addr_C, addr_N; + +logic [1:0] ssn_wr; +logic [1+N_REGIONS_BITS+PID_BITS-1:0] ssn_addr; +logic [15:0] ssn_in; +logic [15:0] ssn_out; + +metaIntf #(.STYPE(ack_t)) ack_que_in (); +metaIntf #(.STYPE(dreq_t)) req_out (); + +logic [RDMA_OST_BITS-1:0] tail, tail_next; +logic [RDMA_OST_BITS-1:0] head, head_next; +logic issued, issued_next; + + +// Pointer table +ram_sp_nc #( + .ADDR_BITS(1+N_REGIONS_BITS+PID_BITS), + .DATA_BITS(16) +) inst_pntr_table ( + .clk(aclk), + .a_en(1'b1), + .a_we(ssn_wr), + .a_addr(ssn_addr), + .a_data_in(ssn_in), + .a_data_out(ssn_out) +); + +// REG +always_ff @(posedge aclk) begin: PROC_REG + if (aresetn == 1'b0) begin + state_C <= ST_IDLE; + addr_C <= 'X; + end + else begin + state_C <= state_N; + addr_C <= addr_N; + end +end + +// NSL +always_comb begin: NSL + state_N = state_C; + + case(state_C) + ST_IDLE: + state_N = (s_ack.valid) ? ST_ACK_LUP_WAIT : (s_req.valid & req_out.ready ? ST_REQ_LUP_WAIT : ST_IDLE); + + ST_ACK_LUP_WAIT: + state_N = ST_ACK_LUP; + + ST_REQ_LUP_WAIT: + state_N = ST_REQ_LUP; + + ST_REQ_LUP: + state_N = ST_IDLE; + + ST_ACK_LUP: + state_N = ST_IDLE; + + endcase // state_C +end + +// DP +assign ssn_in = {7'h00, issued_next, head_next, tail_next}; +assign issued = ssn_out[2*RDMA_OST_BITS]; +assign head = ssn_out[RDMA_OST_BITS+:RDMA_OST_BITS]; +assign tail = ssn_out[0+:RDMA_OST_BITS]; + +always_comb begin: DP + addr_N = addr_C; + + // ACKs + s_ack.ready = 1'b0; + + ack_que_in.valid = 1'b0; + ack_que_in.data = s_ack.data.ack; + + // Req + s_req.ready = 1'b0; + req_out.valid = 1'b0; + req_out.data = s_req.data; + req_out.data.req_1.offs = head; + + // Table + ssn_wr = 0; + ssn_addr = 0; + + // Pointers + head_next = 0; + tail_next = 0; + issued_next = 0; + + case(state_C) + ST_IDLE: begin + if(s_ack.valid) begin + s_ack.ready = 1'b1; + ack_que_in.valid = s_ack.data.last; + + ssn_addr = {is_opcode_rd_resp(s_ack.data.ack.opcode), s_ack.data.ack.vfid[N_REGIONS_BITS-1:0], s_ack.data.ack.pid}; + addr_N = ssn_addr; + end + else if(s_req.valid & req_out.ready) begin + ssn_addr = {is_opcode_rd_req(s_req.data.req_1.opcode), s_req.data.req_1.vfid[N_REGIONS_BITS-1:0], s_req.data.req_1.pid}; + addr_N = ssn_addr; + end + end + + ST_ACK_LUP: begin + head_next = head; + tail_next = tail + 1; + if(head == tail_next) + issued_next = 1'b0; + else + issued_next = issued; + + ssn_wr = ~0; + ssn_addr = addr_C; + end + + ST_REQ_LUP: begin + if(!issued || (head != tail)) begin + req_out.valid = 1'b1; + s_req.ready = 1'b1; + + head_next = head + 1; + tail_next = tail; + issued_next = 1'b1; + + ssn_wr = ~0; + ssn_addr = addr_C; + end + end + + endcase + +end + +/* +ila_flowcontrol inst_ila_flowcontrol ( + .clk(aclk), + .probe0(ack_que_in.valid), + .probe1(ack_que_in.ready), + + .probe2(s_ack.valid), + .probe3(s_ack.ready), + + .probe4(m_ack.valid), + .probe5(m_ack.ready), + + .probe6(req_out.valid), + .probe7(req_out.ready), + + .probe8(s_req.valid), + .probe9(s_req.ready), + + .probe10(m_req.valid), + .probe11(m_req.ready), + + .probe12(ecn_marked), + .probe13(ecn_consumed), + .probe14(s_ack.data.ack.ecn), + .probe15(s_ack.data.last) +); +*/ + +// ACK queue +queue_meta #( + .QDEPTH(RDMA_N_OST) +) inst_cq ( + .aclk(aclk), + .aresetn(aresetn), + .s_meta(ack_que_in), + .m_meta(m_ack) +); + + +localparam integer N_QUEUES = 4; +localparam integer QUEUE_SEL_BITS = $clog2(N_QUEUES); + + +logic [DEST_BITS+PID_BITS-1:0] routing_key; +logic [QUEUE_SEL_BITS-1:0] queue_idx; + +logic [DEST_BITS+PID_BITS-1:0] ack_routing_key; +logic [QUEUE_SEL_BITS-1:0] ack_queue_idx; + +logic [N_QUEUES-1:0] ecn_mark_queue; +logic [N_QUEUES-1:0] ecn_write_rdy_queue; + +metaIntf #(.STYPE(dreq_t)) ccq_s_req [N_QUEUES] (); +metaIntf #(.STYPE(dreq_t)) ccq_m_req [N_QUEUES] (); + +assign routing_key = {s_req.data.req_1.vfid, s_req.data.req_1.pid}; +assign queue_idx = routing_key[DEST_BITS+PID_BITS-1 -: QUEUE_SEL_BITS]; + +assign ack_routing_key = {s_ack.data.ack.vfid, s_ack.data.ack.pid}; +assign ack_queue_idx = ack_routing_key[DEST_BITS+PID_BITS-1 -: QUEUE_SEL_BITS]; + +logic ecn_marked; +assign ecn_marked = (s_ack.data.ack.ecn == 3); + +logic ecn_consumed; +assign ecn_consumed = (s_ack.valid & s_ack.ready) & s_ack.data.last; + +always_comb begin + ecn_mark_queue = 0; + ecn_write_rdy_queue = 0; + + if (ecn_marked) + ecn_mark_queue[ack_queue_idx] = 1'b1; + + if (ecn_consumed) + ecn_write_rdy_queue[ack_queue_idx] = 1'b1; +end + +always_comb begin + req_out.ready = 0; + ccq_s_req[0].valid = 0; + ccq_s_req[0].data = 0; + ccq_s_req[1].valid = 0; + ccq_s_req[1].data = 0; + ccq_s_req[2].valid = 0; + ccq_s_req[2].data = 0; + ccq_s_req[3].valid = 0; + ccq_s_req[3].data = 0; + + if (req_out.valid && (queue_idx == 0) && ccq_s_req[0].ready) begin + ccq_s_req[0].valid = 1; + ccq_s_req[0].data = req_out.data; + req_out.ready = 1; + end else if (req_out.valid && (queue_idx == 1) && ccq_s_req[1].ready) begin + ccq_s_req[1].valid = 1; + ccq_s_req[1].data = req_out.data; + req_out.ready = 1; + + end else if (req_out.valid && (queue_idx == 2) && ccq_s_req[2].ready) begin + ccq_s_req[2].valid = 1; + ccq_s_req[2].data = req_out.data; + req_out.ready = 1; + + end else if (req_out.valid && (queue_idx == 3) && ccq_s_req[3].ready) begin + ccq_s_req[3].valid = 1; + ccq_s_req[3].data = req_out.data; + req_out.ready = 1; + end +end + + +always_comb begin + m_req.valid = 0; + m_req.data = 0; + + ccq_m_req[0].ready = 0; + ccq_m_req[1].ready = 0; + ccq_m_req[2].ready = 0; + ccq_m_req[3].ready = 0; + + if (ccq_m_req[0].valid) begin + m_req.valid = 1; + m_req.data = ccq_m_req[0].data; + ccq_m_req[0].ready = m_req.ready; + end else if (ccq_m_req[1].valid) begin + m_req.valid = 1; + m_req.data = ccq_m_req[1].data; + ccq_m_req[1].ready = m_req.ready; + end else if (ccq_m_req[2].valid) begin + m_req.valid = 1; + m_req.data = ccq_m_req[2].data; + ccq_m_req[2].ready = m_req.ready; + end else if (ccq_m_req[3].valid) begin + m_req.valid = 1; + m_req.data = ccq_m_req[3].data; + ccq_m_req[3].ready = m_req.ready; + end +end + + + + +genvar i_gen; +generate + for (i_gen = 0; i_gen < N_QUEUES; i_gen++) begin: gen_ccq + cc_queue inst_ccq ( + .aclk(aclk), + .aresetn(aresetn), + + .ecn_mark(ecn_mark_queue[i_gen]), + .ecn_write_rdy(ecn_write_rdy_queue[i_gen]), + + .s_req(ccq_s_req[i_gen]), + .m_req(ccq_m_req[i_gen]) + ); + end +endgenerate + + +endmodule From f1ee77925174243ad20d989bc0bcfe5ab14f54c7 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Fri, 31 Oct 2025 18:52:05 +0100 Subject: [PATCH 37/52] ... --- .../rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv | 254 ++------- hw/hdl/network/rdma/MT_pomsarc_new _flow.sv | 536 ++++++------------ .../rdma/MT_pomsarc_new_flow_multiqueue.sv | 7 +- 3 files changed, 222 insertions(+), 575 deletions(-) diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv index de90a3fb2..3ad7d2865 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv @@ -1,5 +1,7 @@ import lynxTypes::*; +`define CC_TEST + module cc_queue ( input logic aclk, @@ -18,28 +20,28 @@ localparam integer RDMA_OST_BITS = $clog2(RDMA_N_OST); localparam integer RD_OP = 0; localparam integer WR_OP = 1; -//localparam integer Rt_default = 100000; + localparam integer Rt_default = 200; localparam integer Rc_default = 8192; + +localparam integer R_MIN = 200; +localparam integer R_CAP = 16384; + localparam integer N_min_time_between_ecn_marks = 12500; localparam integer K = 13750; -//localparam integer Rai = 6250; -localparam integer Rai = 128; -localparam integer S1 = 128; // 1 << 8 -localparam integer Sg = 8; // (1/16) << 8 +localparam integer R_ADDITIVE_INCREASE = 128; +localparam integer R_HYPER_INCREASE = 128; + + +localparam integer Sg = 8; localparam integer F = 5; localparam integer time_threshhold = 50000; localparam integer byte_threshhold = 35; localparam integer Max_Sa_index = 28; -//coarse_grained -//localparam integer Sa_fixed[0:3] = {16, 8, 3, 2}; -//finegrained localparam integer Sa_fixed[0:28] = {256, 241, 228, 218, 209, 201, 194, 188, 182, 178, 173, 170, 166, 163, 161, 158, 156, 154, 152, 150, 148, 147, 146, 144, 143, 142, 141, 140, 139}; - -//logic[3:0] Sa_index; logic[4:0] Sa_index; @@ -63,19 +65,10 @@ logic[2:0] bC_C; //bytecounter counter logic rate_increase_event; -//debug signals -//logic z_ack_arrives; -//logic z_marked_packet_triggers; -//logic z_alpha_decrease; - -//logic z_time_counter_expires; -//logic z_byte_counter_expires; +metaIntf #(.STYPE(dreq_t)) queue_out (); -//logic z_hyper_increase; -//logic z_additive_increase; -//logic z_fast_recovery; +`ifdef CC_TEST -//logic z_next_req_ready; //simul part logic[23:0] ecn_timer; @@ -100,13 +93,10 @@ localparam integer Ila_readout_timer_threshhold = 40000; logic ila_trigger; -metaIntf #(.STYPE(dreq_t)) queue_out (); - always_ff @(posedge aclk) begin if (aresetn == 1'b0) begin Rt <= Rt_default; Rc <= Rc_default; - //Sa <= S1; timer <= 0; timer_send_rate <= 0; @@ -125,20 +115,7 @@ always_ff @(posedge aclk) begin m_req.valid <= 1'b0; queue_out.ready <= 1'b0; m_req.data <= 0; - /* - z_ack_arrives <= 0; - z_marked_packet_triggers <= 0; - z_alpha_decrease <= 0; - - z_time_counter_expires <= 0; - z_byte_counter_expires <= 0; - - z_hyper_increase <= 0; - z_additive_increase <= 0; - z_fast_recovery <= 0; - - z_next_req_ready <= 0; - */ + Sa_index <= 0; @@ -174,19 +151,6 @@ always_ff @(posedge aclk) begin end - - //z_ack_arrives <= 0; - //z_marked_packet_triggers <= 0; - //z_alpha_decrease <= 0; - - //z_time_counter_expires <= 0; - //z_byte_counter_expires <= 0; - - //z_hyper_increase <= 0; - //z_additive_increase <= 0; - //z_fast_recovery <= 0; - - //z_next_req_ready <= 0; if(ecn_test_starter == 1) begin @@ -206,10 +170,7 @@ always_ff @(posedge aclk) begin if(ecn_write_rdy) begin - //===Debug Signal=== - //z_ack_arrives <= 1; - - //================== + byte_counter <= byte_counter + 1; //======simul====== @@ -224,19 +185,15 @@ always_ff @(posedge aclk) begin ecn_counter <= ecn_counter + 1; ecn_alternator = 0; end - - //=============================== - if(ecn_mark == 1'b1 && ecn_alternator == 1) begin // Marked Packet arrived + if(ecn_alternator == 1) begin // Marked Packet arrived if(timer - time_last_update > N_min_time_between_ecn_marks) begin - //===Debug Signal=== - //z_marked_packet_triggers <= 1; - //================== + Rt <= Rc; - if(Rc <= 16384) begin + if(Rc <= R_CAP) begin Rc <= (Rc * Sa_fixed[Sa_index]) >> 7; end if(!(Sa_index == 0)) begin @@ -256,10 +213,6 @@ always_ff @(posedge aclk) begin end if (timer - time_of_last_marked_packet > K) begin - //===Debug Signal=== - //z_alpha_decrease <= 1; - //================== - if(!(Sa_index == Max_Sa_index)) begin Sa_index <= Sa_index + 1; @@ -269,9 +222,6 @@ always_ff @(posedge aclk) begin end if(time_counter > time_threshhold) begin - //===Debug Signal=== - //z_time_counter_expires <= 1; - //================== time_counter <= 0; rate_increase_event <= 1; if(tC_C < F) begin @@ -280,9 +230,7 @@ always_ff @(posedge aclk) begin end if(byte_counter > byte_threshhold) begin - //===Debug Signal=== - //z_byte_counter_expires <= 1; - //================== + byte_counter <= 0; rate_increase_event <= 1; if(bC_C < F) begin @@ -294,56 +242,38 @@ always_ff @(posedge aclk) begin if(tC_C >= F || bC_C >= F) begin if(tC_C >= F && bC_C >= F) begin - // case Hyper Increse - //replaced by fast recovery - //===Debug Signal=== - //z_hyper_increase <= 1; - //================== - if(Rt + 3 < Rai) begin + + if(Rt + 3 < R_HYPER_INCREASE) begin Rt <= 1; end else begin - Rt <= Rt - Rai; + Rt <= Rt - R_HYPER_INCREASE; end Rc <= (Rt + Rc) >> 1; end else begin - // case Additive Increase - //===Debug Signal=== - //z_additive_increase <= 1; - //================== - if(Rt + 3 < Rai) begin + if(Rt + 3 < R_ADDITIVE_INCREASE) begin Rt <= 1; end else begin - Rt <= Rt - Rai; + Rt <= Rt - R_ADDITIVE_INCREASE; end Rc <= (Rt + Rc) >> 1; end end else begin - // case Fast Recovery - //===Debug Signal=== - //z_fast_recovery <= 1; - //================== Rc <= (Rt + Rc) >> 1; end end - if(Rc < 200) begin - Rc <= 200; + if(Rc < R_MIN) begin + Rc <= R_MIN; end - if(Rt < 200) begin - Rt <= 200; + if(Rt < R_MIN) begin + Rt <= R_MIN; end // CHANGE BACK if(timer_send_rate > Rc) begin - //if(timer_send_rate > 1) begin - - //===Debug Signal=== - //z_next_req_ready <= 1; - //================== - m_req.valid <= queue_out.valid; queue_out.ready <= m_req.ready; if(queue_out.valid && m_req.ready) begin @@ -379,17 +309,8 @@ ila_DCQCN inst_ila_DCQCN( .probe16(queue_out.valid), .probe17(queue_out.ready), .probe18(ecn_mark), - .probe19(ecn_write_rdy),/*, - - .probe20(z_ack_arrives), - .probe21(z_marked_packet_triggers), - .probe22(z_alpha_decrease), - .probe23(z_time_counter_expires), - .probe24(z_byte_counter_expires), - .probe25(z_hyper_increase), - .probe26(z_additive_increase), - .probe27(z_fast_recovery), - .probe28(z_next_req_ready),*/ + .probe19(ecn_write_rdy), + .probe20(ecn_alternator), //1 .probe21(ecn_counter), //16 .probe22(ecn_timer), //24 @@ -401,96 +322,10 @@ ila_DCQCN inst_ila_DCQCN( ); -queue_meta #( - .QDEPTH(RDMA_N_OST) -) inst_cq ( - .aclk(aclk), - .aresetn(aresetn), - .s_meta(s_req), - .m_meta(queue_out) -); - - -endmodule - - +`else // NO TEST PART - - -import lynxTypes::*; - -module cc_queue -( - input logic aclk, - input logic aresetn, - - input logic ecn_mark, - input logic ecn_write_rdy, - - metaIntf.s s_req, - metaIntf.m m_req -); - -//localparam integer RDMA_N_OST = RDMA_N_WR_OUTSTANDING; -//localparam integer RDMA_N_OST = 20; -//localparam integer RDMA_OST_BITS = $clog2(RDMA_N_OST); - -localparam integer RDMA_N_OST = 100; -localparam integer RDMA_OST_BITS = $clog2(RDMA_N_OST); - -localparam integer RD_OP = 0; -localparam integer WR_OP = 1; - -//localparam integer Rt_default = 100000; -localparam integer Rt_default = 200; -localparam integer Rc_default = 8192; -localparam integer N_min_time_between_ecn_marks = 12500; -localparam integer K = 13750; -//localparam integer Rai = 6250; -localparam integer Rai = 128; - -localparam integer S1 = 128; // 1 << 8 -localparam integer Sg = 8; // (1/16) << 8 -localparam integer F = 5; - -localparam integer time_threshhold = 50000; -localparam integer byte_threshhold = 35; - -localparam integer Max_Sa_index = 28; -//coarse_grained -//localparam integer Sa_fixed[0:3] = {16, 8, 3, 2}; -//finegrained -localparam integer Sa_fixed[0:28] = {256, 241, 228, 218, 209, 201, 194, 188, 182, 178, 173, 170, 166, 163, 161, 158, 156, 154, 152, 150, 148, 147, 146, 144, 143, 142, 141, 140, 139}; - -//logic[3:0] Sa_index; -logic[4:0] Sa_index; - - - - -logic[15:0] Rt; -logic[15:0] Rc; -//logic[63:0] Sa; -logic[23:0] timer; - -logic[23:0] timer_send_rate; - -logic[23:0] time_of_last_marked_packet; -logic[23:0] time_last_update; - -logic[7:0] byte_counter; -logic[15:0] time_counter; - -logic[2:0] tC_C; //timecounter counter -logic[2:0] bC_C; //bytecounter counter - -logic rate_increase_event; - - -metaIntf #(.STYPE(dreq_t)) queue_out (); - always_ff @(posedge aclk) begin if (aresetn == 1'b0) begin Rt <= Rt_default; @@ -542,7 +377,7 @@ always_ff @(posedge aclk) begin if(timer - time_last_update > N_min_time_between_ecn_marks) begin Rt <= Rc; - if(Rc <= 16384) begin + if(Rc <= R_CAP) begin Rc <= (Rc * Sa_fixed[Sa_index]) >> 7; end if(!(Sa_index == 0)) begin @@ -588,20 +423,20 @@ always_ff @(posedge aclk) begin if(tC_C >= F || bC_C >= F) begin if(tC_C >= F && bC_C >= F) begin - if(Rt + 3 < Rai) begin + if(Rt + 3 < R_HYPER_INCREASE) begin Rt <= 1; end else begin - Rt <= Rt - Rai; + Rt <= Rt - R_HYPER_INCREASE; end Rc <= (Rt + Rc) >> 1; end else begin - if(Rt + 3 < Rai) begin + if(Rt + 3 < R_ADDITIVE_INCREASE) begin Rt <= 1; end else begin - Rt <= Rt - Rai; + Rt <= Rt - R_ADDITIVE_INCREASE; end Rc <= (Rt + Rc) >> 1; end @@ -610,11 +445,11 @@ always_ff @(posedge aclk) begin end end - if(Rc < 200) begin - Rc <= 200; + if(Rc < R_MIN) begin + Rc <= R_MIN; end - if(Rt < 200) begin - Rt <= 200; + if(Rt < R_MIN) begin + Rt <= R_MIN; end if(timer_send_rate > Rc) begin @@ -632,6 +467,12 @@ always_ff @(posedge aclk) begin end +`endif + + + + + queue_meta #( .QDEPTH(RDMA_N_OST) ) inst_cq ( @@ -642,4 +483,5 @@ queue_meta #( ); + endmodule \ No newline at end of file diff --git a/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv b/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv index 2f9e9312d..0418c4c1d 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_new _flow.sv @@ -1,413 +1,217 @@ import lynxTypes::*; -module cc_queue -( - input logic aclk, - input logic aresetn, - - input logic ecn_mark, - input logic ecn_write_rdy, - +module rdma_flow ( metaIntf.s s_req, - metaIntf.m m_req -); - -//======================================================== -// DCQCN PARAMETERS -//======================================================== - -localparam integer REQ_QUEUE_SIZE = 10; - -//localparam integer Rt_default = 100000; -localparam integer Rt_default = 200; -localparam integer Rc_default = 8192; -localparam integer N_min_time_between_ecn_marks = 12500; -localparam integer K = 13750; -localparam integer Rai = 128; - - - -localparam integer S1 = 128; // 1 << 8 -localparam integer Sg = 8; // (1/16) << 8 -localparam integer F = 5; - -//normal -localparam integer time_threshhold = 50000; -//increased T test -//localparam integer time_threshhold = 100000; - -localparam integer byte_threshhold = 35; - - -localparam integer Max_Sa_index = 28; -localparam integer Sa_fixed[0:28] = {256, 241, 228, 218, 209, 201, 194, 188, 182, 178, 173, 170, 166, 163, 161, 158, 156, 154, 152, 150, 148, 147, 146, 144, 143, 142, 141, 140, 139}; -logic[4:0] Sa_index; - - - - -logic[15:0] Rt; -logic[15:0] Rc; -logic[23:0] timer; - -logic[23:0] timer_send_rate; - -logic[23:0] time_of_last_marked_packet; -logic[23:0] time_last_update; - -logic[7:0] byte_counter; -logic[15:0] time_counter; + metaIntf.m m_req, -logic[2:0] tC_C; //timecounter counter -logic[2:0] bC_C; //bytecounter counter - -logic rate_increase_event; - -//debug signals -//logic z_ack_arrives; -//logic z_marked_packet_triggers; -//logic z_alpha_decrease; - -//logic z_time_counter_expires; -//logic z_byte_counter_expires; - -//logic z_hyper_increase; -//logic z_additive_increase; -//logic z_fast_recovery; - -//logic z_next_req_ready; - -//simul part -logic[23:0] ecn_timer; -localparam integer ecn_timer_trigger_threshhold = 5000000; -logic ecn_alternator; -logic[15:0] ecn_counter; -//1 -//localparam integer Ecn_rates[0:6] = {9999, 1, 9 ,99, 999, 9999}; -//2 -//localparam integer Ecn_rates[0:6] = {9999, 1, 9, 49 ,99, 999, 9999}; -//3 -//localparam integer Ecn_rates[0:6] = {9999, 1, 9, 14 , 19, 24, 9999}; -//4 -localparam integer Ecn_rates[0:15] = {9999, 99, 29, 24, 19, 9, 29, 39, 39, 99, 99, 149, 149,199,199,9999}; - -logic ecn_test_starter; -localparam Ecn_rates_max_index = 15; -logic[4:0] ecn_rates_index; - -logic[15:0] ila_readout_timer; -localparam integer Ila_readout_timer_threshhold = 40000; -logic ila_trigger; + metaIntf.s s_ack, + metaIntf.m m_ack, + input logic aclk, + input logic aresetn +); -metaIntf #(.STYPE(dreq_t)) queue_out (); +localparam integer RDMA_N_OST = RDMA_N_WR_OUTSTANDING; +localparam integer RDMA_OST_BITS = $clog2(RDMA_N_OST); +localparam integer RD_OP = 0; +localparam integer WR_OP = 1; + +// -- FSM +typedef enum logic[2:0] {ST_IDLE, ST_ACK_LUP_WAIT, ST_REQ_LUP_WAIT, ST_ACK_LUP, ST_REQ_LUP} state_t; +logic [2:0] state_C, state_N; +logic [1+N_REGIONS_BITS+PID_BITS-1:0] addr_C, addr_N; + +logic [1:0] ssn_wr; +logic [1+N_REGIONS_BITS+PID_BITS-1:0] ssn_addr; +logic [15:0] ssn_in; +logic [15:0] ssn_out; + +metaIntf #(.STYPE(ack_t)) ack_que_in (); +metaIntf #(.STYPE(dreq_t)) req_out (); + +logic [RDMA_OST_BITS-1:0] tail, tail_next; +logic [RDMA_OST_BITS-1:0] head, head_next; +logic issued, issued_next; + + +// Pointer table +ram_sp_nc #( + .ADDR_BITS(1+N_REGIONS_BITS+PID_BITS), + .DATA_BITS(16) +) inst_pntr_table ( + .clk(aclk), + .a_en(1'b1), + .a_we(ssn_wr), + .a_addr(ssn_addr), + .a_data_in(ssn_in), + .a_data_out(ssn_out) +); -always_ff @(posedge aclk) begin +// REG +always_ff @(posedge aclk) begin: PROC_REG if (aresetn == 1'b0) begin - Rt <= Rt_default; - Rc <= Rc_default; - timer <= 0; - - timer_send_rate <= 0; - - time_of_last_marked_packet <= 0; - time_last_update <= 0; - - byte_counter <= 0; - time_counter <= 0; - - bC_C <= 0; - tC_C <= 0; - - rate_increase_event <= 0; - - m_req.valid <= 1'b0; - queue_out.ready <= 1'b0; - m_req.data <= 0; - /* - z_ack_arrives <= 0; - z_marked_packet_triggers <= 0; - z_alpha_decrease <= 0; - - z_time_counter_expires <= 0; - z_byte_counter_expires <= 0; - - z_hyper_increase <= 0; - z_additive_increase <= 0; - z_fast_recovery <= 0; - - z_next_req_ready <= 0; - */ - Sa_index <= 0; - - - //simul - ecn_alternator <= 0; - ecn_counter <= 0; - ecn_test_starter <= 0; - ecn_timer <= 0; - ecn_rates_index <= 0; - ila_readout_timer <= 0; - ila_trigger <= 0; - - + state_C <= ST_IDLE; + addr_C <= 'X; end else begin - timer = timer + 1; - time_counter <= time_counter + 1; - timer_send_rate <= timer_send_rate + 1; - - rate_increase_event <= 0; - - - m_req.valid <= 1'b0; - m_req.data <= queue_out.data; - queue_out.ready <= 1'b0; - - if(ila_readout_timer >= Ila_readout_timer_threshhold) begin - ila_readout_timer <= 0; - ila_trigger = 1; - end else begin - ila_readout_timer <= ila_readout_timer + 1; - ila_trigger = 0; - end - - - - //z_ack_arrives <= 0; - //z_marked_packet_triggers <= 0; - //z_alpha_decrease <= 0; - - //z_time_counter_expires <= 0; - //z_byte_counter_expires <= 0; - - //z_hyper_increase <= 0; - //z_additive_increase <= 0; - //z_fast_recovery <= 0; - - //z_next_req_ready <= 0; - if(ecn_test_starter == 1) begin - - - if(ecn_timer > ecn_timer_trigger_threshhold) begin - if(!(ecn_rates_index == Ecn_rates_max_index)) begin - ecn_rates_index <= ecn_rates_index + 1; - end - ecn_timer <= 0; - end - else begin - ecn_timer <= ecn_timer + 1; - end - end + state_C <= state_N; + addr_C <= addr_N; + end +end +// NSL +always_comb begin: NSL + state_N = state_C; + case(state_C) + ST_IDLE: + state_N = (s_ack.valid) ? ST_ACK_LUP_WAIT : (s_req.valid & req_out.ready ? ST_REQ_LUP_WAIT : ST_IDLE); + ST_ACK_LUP_WAIT: + state_N = ST_ACK_LUP; + ST_REQ_LUP_WAIT: + state_N = ST_REQ_LUP; - if(ecn_write_rdy) begin - //===Debug Signal=== - //z_ack_arrives <= 1; + ST_REQ_LUP: + state_N = ST_IDLE; - //================== - byte_counter <= byte_counter + 1; + ST_ACK_LUP: + state_N = ST_IDLE; - //======simul====== - ecn_test_starter <= 1; + endcase // state_C +end - - if(ecn_counter >= Ecn_rates[ecn_rates_index]) begin - ecn_counter <= 0; - ecn_alternator = 1; - end - else begin - ecn_counter <= ecn_counter + 1; - ecn_alternator = 0; +// DP +assign ssn_in = {7'h00, issued_next, head_next, tail_next}; +assign issued = ssn_out[2*RDMA_OST_BITS]; +assign head = ssn_out[RDMA_OST_BITS+:RDMA_OST_BITS]; +assign tail = ssn_out[0+:RDMA_OST_BITS]; + +always_comb begin: DP + addr_N = addr_C; + + // ACKs + s_ack.ready = 1'b0; + + ack_que_in.valid = 1'b0; + ack_que_in.data = s_ack.data.ack; + + // Req + s_req.ready = 1'b0; + req_out.valid = 1'b0; + req_out.data = s_req.data; + req_out.data.req_1.offs = head; + + // Table + ssn_wr = 0; + ssn_addr = 0; + + // Pointers + head_next = 0; + tail_next = 0; + issued_next = 0; + + case(state_C) + ST_IDLE: begin + if(s_ack.valid) begin + s_ack.ready = 1'b1; + ack_que_in.valid = s_ack.data.last; + + ssn_addr = {is_opcode_rd_resp(s_ack.data.ack.opcode), s_ack.data.ack.vfid[N_REGIONS_BITS-1:0], s_ack.data.ack.pid}; + addr_N = ssn_addr; end - - - //=============================== - - - if(ecn_mark == 1'b1 && ecn_alternator == 1) begin // Marked Packet arrived - if(timer - time_last_update > N_min_time_between_ecn_marks) begin - //===Debug Signal=== - //z_marked_packet_triggers <= 1; - //================== - Rt <= Rc; - - if(Rc <= 16384) begin - Rc <= (Rc * Sa_fixed[Sa_index]) >> 7; - end - if(!(Sa_index == 0)) begin - Sa_index <= Sa_index - 1; - end - - time_last_update <= timer; - - time_counter <= 0; - byte_counter <= 0; - bC_C <= 0; - tC_C <= 0; - - end - time_of_last_marked_packet = timer; + else if(s_req.valid & req_out.ready) begin + ssn_addr = {is_opcode_rd_req(s_req.data.req_1.opcode), s_req.data.req_1.vfid[N_REGIONS_BITS-1:0], s_req.data.req_1.pid}; + addr_N = ssn_addr; end end - if (timer - time_of_last_marked_packet > K) begin - //===Debug Signal=== - //z_alpha_decrease <= 1; - //================== - - - if(!(Sa_index == Max_Sa_index)) begin - Sa_index <= Sa_index + 1; - end - - time_of_last_marked_packet <= timer; - end - - if(time_counter > time_threshhold) begin - //===Debug Signal=== - //z_time_counter_expires <= 1; - //================== - time_counter <= 0; - rate_increase_event <= 1; - if(tC_C < F) begin - tC_C <= tC_C + 1; - end - end + ST_ACK_LUP: begin + head_next = head; + tail_next = tail + 1; + if(head == tail_next) + issued_next = 1'b0; + else + issued_next = issued; - if(byte_counter > byte_threshhold) begin - //===Debug Signal=== - //z_byte_counter_expires <= 1; - //================== - byte_counter <= 0; - rate_increase_event <= 1; - if(bC_C < F) begin - bC_C <= bC_C + 1; - end + ssn_wr = ~0; + ssn_addr = addr_C; end - if(rate_increase_event) begin - if(tC_C >= F || bC_C >= F) begin - - if(tC_C >= F && bC_C >= F) begin - // case Hyper Increse - //replaced by fast recovery - //===Debug Signal=== - //z_hyper_increase <= 1; - //================== - if(Rt + 3 < Rai) begin - Rt <= 1; - end - else begin - Rt <= Rt - Rai; - end - Rc <= (Rt + Rc) >> 1; - end - else begin - // case Additive Increase - //===Debug Signal=== - //z_additive_increase <= 1; - //================== - if(Rt + 3 < Rai) begin - Rt <= 1; - end - else begin - Rt <= Rt - Rai; - end - Rc <= (Rt + Rc) >> 1; - end - end else begin - // case Fast Recovery - //===Debug Signal=== - //z_fast_recovery <= 1; - //================== - Rc <= (Rt + Rc) >> 1; + ST_REQ_LUP: begin + if(!issued || (head != tail)) begin + req_out.valid = 1'b1; + s_req.ready = 1'b1; + + head_next = head + 1; + tail_next = tail; + issued_next = 1'b1; + + ssn_wr = ~0; + ssn_addr = addr_C; end end - if(Rc < 200) begin - Rc <= 200; - end - if(Rt < 200) begin - Rt <= 200; - end + endcase - // CHANGE BACK - if(timer_send_rate > Rc) begin - //if(timer_send_rate > 1) begin +end - //===Debug Signal=== - //z_next_req_ready <= 1; - //================== - m_req.valid <= queue_out.valid; - queue_out.ready <= m_req.ready; - if(queue_out.valid && m_req.ready) begin - timer_send_rate <= 0; - end +ila_flowcontrol inst_ila_flowcontrol ( + .clk(aclk), + .probe0(ack_que_in.valid), + .probe1(ack_que_in.ready), - end + .probe2(s_ack.valid), + .probe3(s_ack.ready), + .probe4(m_ack.valid), + .probe5(m_ack.ready), - end -end + .probe6(req_out.valid), + .probe7(req_out.ready), + .probe8(s_req.valid), + .probe9(s_req.ready), -ila_DCQCN inst_ila_DCQCN( - .clk(aclk), - .probe0(timer), //24 - .probe1(Rt), //16 - .probe2(Rc), //16 - .probe3(Sa_index), //5 - .probe4(byte_counter), //8 - .probe5(time_counter), //16 - .probe6(tC_C), //3 - .probe7(bC_C), //3 - .probe8(rate_increase_event), - .probe9(timer_send_rate), //24 - .probe10(time_last_update), //24 - .probe11(time_of_last_marked_packet), //24 - - .probe12(s_req.valid), - .probe13(s_req.ready), - .probe14(m_req.valid), - .probe15(m_req.ready), - .probe16(queue_out.valid), - .probe17(queue_out.ready), - .probe18(ecn_mark), - .probe19(ecn_write_rdy), - - //.probe20(z_ack_arrives), - //.probe21(z_marked_packet_triggers), - //.probe22(z_alpha_decrease), - //.probe23(z_time_counter_expires), - //.probe24(z_byte_counter_expires), - //.probe25(z_hyper_increase), - //.probe26(z_additive_increase), - //.probe27(z_fast_recovery), - //.probe28(z_next_req_ready), - .probe20(ecn_alternator), //1 - .probe21(ecn_counter), //16 - .probe22(ecn_timer), //24 - .probe23(ecn_test_starter), - .probe24(ecn_rates_index), // 5 - .probe25(ila_readout_timer), //16 - .probe26(ila_trigger) + .probe10(m_req.valid), + .probe11(m_req.ready), + .probe12(ecn_marked), + .probe13(ecn_consumed), + .probe14(s_ack.data.ack.ecn), + .probe15(s_ack.data.last) ); +// ACK queue queue_meta #( - .QDEPTH(REQ_QUEUE_SIZE) + .QDEPTH(RDMA_N_OST) ) inst_cq ( .aclk(aclk), .aresetn(aresetn), - .s_meta(s_req), - .m_meta(queue_out) + .s_meta(ack_que_in), + .m_meta(m_ack) +); + + +logic ecn_marked; +assign ecn_marked = (s_ack.data.ack.ecn == 3); +logic ecn_consumed; +assign ecn_consumed = (s_ack.valid & s_ack.ready) & s_ack.data.last; + + +cc_queue inst_DCQCN( + .aclk(aclk), + .aresetn(aresetn), + + .ecn_mark(ecn_marked), + .ecn_write_rdy(ecn_consumed), + + .s_req(req_out), + .m_req(m_req) ); -endmodule \ No newline at end of file +endmodule diff --git a/hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv b/hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv index 953afe93f..f13108712 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv @@ -1,4 +1,4 @@ -import lynxTypes::*; +/*import lynxTypes::*; module rdma_flow ( metaIntf.s s_req, @@ -156,7 +156,7 @@ always_comb begin: DP endcase end - +*/ /* ila_flowcontrol inst_ila_flowcontrol ( .clk(aclk), @@ -184,7 +184,7 @@ ila_flowcontrol inst_ila_flowcontrol ( .probe15(s_ack.data.last) ); */ - +/* // ACK queue queue_meta #( .QDEPTH(RDMA_N_OST) @@ -317,3 +317,4 @@ endgenerate endmodule +*/ \ No newline at end of file From 5b5f16fc5b79376743e683a2bba36d02f2c440f7 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Fri, 31 Oct 2025 21:08:37 +0100 Subject: [PATCH 38/52] ... --- .../rdma/MT_pomsarc_new_flow_multiqueue.sv | 136 ++++++++++-------- 1 file changed, 79 insertions(+), 57 deletions(-) diff --git a/hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv b/hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv index f13108712..78cfd82c3 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv @@ -158,6 +158,7 @@ always_comb begin: DP end */ /* + ila_flowcontrol inst_ila_flowcontrol ( .clk(aclk), .probe0(ack_que_in.valid), @@ -185,6 +186,7 @@ ila_flowcontrol inst_ila_flowcontrol ( ); */ /* + // ACK queue queue_meta #( .QDEPTH(RDMA_N_OST) @@ -228,75 +230,95 @@ always_comb begin ecn_mark_queue = 0; ecn_write_rdy_queue = 0; - if (ecn_marked) + if (ecn_marked) begin ecn_mark_queue[ack_queue_idx] = 1'b1; - - if (ecn_consumed) + end + if (ecn_consumed) begin ecn_write_rdy_queue[ack_queue_idx] = 1'b1; + end end -always_comb begin - req_out.ready = 0; - ccq_s_req[0].valid = 0; - ccq_s_req[0].data = 0; - ccq_s_req[1].valid = 0; - ccq_s_req[1].data = 0; - ccq_s_req[2].valid = 0; - ccq_s_req[2].data = 0; - ccq_s_req[3].valid = 0; - ccq_s_req[3].data = 0; - - if (req_out.valid && (queue_idx == 0) && ccq_s_req[0].ready) begin - ccq_s_req[0].valid = 1; - ccq_s_req[0].data = req_out.data; - req_out.ready = 1; - end else if (req_out.valid && (queue_idx == 1) && ccq_s_req[1].ready) begin - ccq_s_req[1].valid = 1; - ccq_s_req[1].data = req_out.data; - req_out.ready = 1; - - end else if (req_out.valid && (queue_idx == 2) && ccq_s_req[2].ready) begin - ccq_s_req[2].valid = 1; - ccq_s_req[2].data = req_out.data; - req_out.ready = 1; - - end else if (req_out.valid && (queue_idx == 3) && ccq_s_req[3].ready) begin - ccq_s_req[3].valid = 1; - ccq_s_req[3].data = req_out.data; - req_out.ready = 1; +logic [N_QUEUES-1:0] in_ready; + +genvar i_gen_in; +generate + for (i_gen_in = 0; i_gen_in < N_QUEUES; i_gen_in++) begin: gen_in + always_comb begin + ccq_s_req[i_gen_in].valid = 0; + ccq_s_req[i_gen_in].data = 0; + in_ready[i_gen_in] = 0; + if (queue_idx == i_gen_in) begin + ccq_s_req[i_gen_in].valid = req_out.valid; + ccq_s_req[i_gen_in].data = req_out.data; + in_ready[i_gen_in] = ccq_s_req[i_gen_in].ready; + end + end end -end +endgenerate +assign req_out.ready = |in_ready; -always_comb begin - m_req.valid = 0; - m_req.data = 0; - ccq_m_req[0].ready = 0; - ccq_m_req[1].ready = 0; - ccq_m_req[2].ready = 0; - ccq_m_req[3].ready = 0; - - if (ccq_m_req[0].valid) begin - m_req.valid = 1; - m_req.data = ccq_m_req[0].data; - ccq_m_req[0].ready = m_req.ready; - end else if (ccq_m_req[1].valid) begin - m_req.valid = 1; - m_req.data = ccq_m_req[1].data; - ccq_m_req[1].ready = m_req.ready; - end else if (ccq_m_req[2].valid) begin - m_req.valid = 1; - m_req.data = ccq_m_req[2].data; - ccq_m_req[2].ready = m_req.ready; - end else if (ccq_m_req[3].valid) begin - m_req.valid = 1; - m_req.data = ccq_m_req[3].data; - ccq_m_req[3].ready = m_req.ready; +logic [QUEUE_SEL_BITS-1:0] readout_counter; +logic [N_QUEUES-1:0] ccq_m_req_valid; +logic state; + +genvar i_gen_out_valid; +generate + for (i_gen_out_valid = 0; i_gen_out_valid < N_QUEUES; i_gen_out_valid++) begin + assign ccq_m_req_valid[i_gen_out_valid] = ccq_m_req[i_gen_out_valid].valid; + end +endgenerate + + +always_ff @(posedge aclk) begin + if (aresetn == 1'b0) begin + readout_counter <= 0; + state <= 0; + end + else begin + if(state == 0) begin + if(ccq_m_req_valid[readout_counter]) begin + state <= 1; + end + else begin + if(readout_counter == N_QUEUES-1) begin + readout_counter <= 0; + end + else begin + readout_counter <= readout_counter + 1; + end + end + end + else begin + if(m_req.ready == 1) begin + if(readout_counter == N_QUEUES-1) begin + readout_counter <= 0; + end + else begin + readout_counter <= readout_counter + 1; + end + end + end end end +genvar i_gen_out; +generate + for (i_gen_out = 0; i_gen_out < N_QUEUES; i_gen_out++) begin: gen_out + always_comb begin + ccq_m_req[i_gen_out].ready = 0; + + if(readout_conter == i_gen_out) begin + ccq_s_req[i_gen_in].ready = m_req.ready; + end + end + end +endgenerate + +assign m_req.data = ccq_m_req[readout_counter].data; +assign m_req.valid = ccq_m_req[readout_counter].valid; genvar i_gen; From db9a9e94a61533c7780e0dc8a92c791b7423a6e1 Mon Sep 17 00:00:00 2001 From: pomsarc Date: Fri, 7 Nov 2025 13:14:57 +0100 Subject: [PATCH 39/52] added comments --- .../README.md | 0 .../hw/CMakeLists.txt | 0 .../hw/src/init_ip.tcl | 0 .../hw/src/vfpga_top.svh | 0 .../img/rdma_results_read.png | Bin .../img/rdma_results_write.png | Bin .../img/rdma_system_overview.svg | 0 .../img/rdma_traffic_pattern.svg | 0 .../sw/CMakeLists.txt | 0 .../sw/src/client/main.cpp | 0 .../sw/src/include/constants.hpp | 4 +- .../sw/src/server/main.cpp | 0 .../sw/src/client/main.cpp | 140 ------------- .../sw/src/include/constants.hpp | 9 - .../sw/src/server/main.cpp | 118 ----------- .../README.md | 186 ------------------ .../hw/CMakeLists.txt | 32 --- .../hw/src/init_ip.tcl | 2 - .../hw/src/vfpga_top.svh | 71 ------- .../img/rdma_results_read.png | Bin 130953 -> 0 bytes .../img/rdma_results_write.png | Bin 131862 -> 0 bytes .../img/rdma_system_overview.svg | 1 - .../img/rdma_traffic_pattern.svg | 1 - .../sw/CMakeLists.txt | 26 --- .../rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv | 58 ++++-- 25 files changed, 45 insertions(+), 603 deletions(-) rename examples/{MT_pomsarc_09_CC_Testbench => Congestion_Control_Test}/README.md (100%) rename examples/{MT_pomsarc_09_CC_Testbench => Congestion_Control_Test}/hw/CMakeLists.txt (100%) rename examples/{MT_pomsarc_09_CC_Testbench => Congestion_Control_Test}/hw/src/init_ip.tcl (100%) rename examples/{MT_pomsarc_09_CC_Testbench => Congestion_Control_Test}/hw/src/vfpga_top.svh (100%) rename examples/{MT_pomsarc_09_CC_Testbench => Congestion_Control_Test}/img/rdma_results_read.png (100%) rename examples/{MT_pomsarc_09_CC_Testbench => Congestion_Control_Test}/img/rdma_results_write.png (100%) rename examples/{MT_pomsarc_09_CC_Testbench => Congestion_Control_Test}/img/rdma_system_overview.svg (100%) rename examples/{MT_pomsarc_09_CC_Testbench => Congestion_Control_Test}/img/rdma_traffic_pattern.svg (100%) rename examples/{MT_pomsarc_09_CC_Testbench => Congestion_Control_Test}/sw/CMakeLists.txt (100%) rename examples/{MT_pomsarc_10_single_sided_writes => Congestion_Control_Test}/sw/src/client/main.cpp (100%) rename examples/{MT_pomsarc_10_single_sided_writes => Congestion_Control_Test}/sw/src/include/constants.hpp (82%) rename examples/{MT_pomsarc_10_single_sided_writes => Congestion_Control_Test}/sw/src/server/main.cpp (100%) delete mode 100644 examples/MT_pomsarc_09_CC_Testbench/sw/src/client/main.cpp delete mode 100644 examples/MT_pomsarc_09_CC_Testbench/sw/src/include/constants.hpp delete mode 100644 examples/MT_pomsarc_09_CC_Testbench/sw/src/server/main.cpp delete mode 100644 examples/MT_pomsarc_10_single_sided_writes/README.md delete mode 100644 examples/MT_pomsarc_10_single_sided_writes/hw/CMakeLists.txt delete mode 100644 examples/MT_pomsarc_10_single_sided_writes/hw/src/init_ip.tcl delete mode 100644 examples/MT_pomsarc_10_single_sided_writes/hw/src/vfpga_top.svh delete mode 100644 examples/MT_pomsarc_10_single_sided_writes/img/rdma_results_read.png delete mode 100644 examples/MT_pomsarc_10_single_sided_writes/img/rdma_results_write.png delete mode 100644 examples/MT_pomsarc_10_single_sided_writes/img/rdma_system_overview.svg delete mode 100644 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examples/Congestion_Control_Test/sw/src/client/main.cpp diff --git a/examples/MT_pomsarc_10_single_sided_writes/sw/src/include/constants.hpp b/examples/Congestion_Control_Test/sw/src/include/constants.hpp similarity index 82% rename from examples/MT_pomsarc_10_single_sided_writes/sw/src/include/constants.hpp rename to examples/Congestion_Control_Test/sw/src/include/constants.hpp index 2b753a69a..2cffcfb43 100644 --- a/examples/MT_pomsarc_10_single_sided_writes/sw/src/include/constants.hpp +++ b/examples/Congestion_Control_Test/sw/src/include/constants.hpp @@ -2,8 +2,8 @@ // Placed in separate file to avoid any weird changes in one file not reflect in the other // Benchmark parameters -#define N_LATENCY_REPS 1000 -#define N_THROUGHPUT_REPS 1000 +#define N_LATENCY_REPS 100000 +#define N_THROUGHPUT_REPS 100000 // Default vFPGA to assign cThreads to; for designs with one region (vFPGA) this is the only possible value #define DEFAULT_VFPGA_ID 0 \ No newline at end of file diff --git a/examples/MT_pomsarc_10_single_sided_writes/sw/src/server/main.cpp b/examples/Congestion_Control_Test/sw/src/server/main.cpp similarity index 100% rename from examples/MT_pomsarc_10_single_sided_writes/sw/src/server/main.cpp rename to examples/Congestion_Control_Test/sw/src/server/main.cpp diff --git a/examples/MT_pomsarc_09_CC_Testbench/sw/src/client/main.cpp b/examples/MT_pomsarc_09_CC_Testbench/sw/src/client/main.cpp deleted file mode 100644 index 1f2dbac0a..000000000 --- a/examples/MT_pomsarc_09_CC_Testbench/sw/src/client/main.cpp +++ /dev/null @@ -1,140 +0,0 @@ -/** - * Copyright (c) 2021-2024, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - -// External library for easier parsing of CLI arguments by the executable -#include - -// Coyote-specific includes -#include "cBench.hpp" -#include "cThread.hpp" -#include "constants.hpp" - -constexpr bool const IS_CLIENT = true; - -double run_bench( - coyote::cThread &coyote_thread, coyote::sgEntry &sg, - int *mem, uint transfers, uint n_runs, bool operation -) { - // When writing, the server asserts the written payload is correct (which the client sets) - // When reading, the client asserts the read payload is correct (which the server sets) - for (int i = 0; i < sg.rdma.len / sizeof(int); i++) { - mem[i] = operation ? i : 0; - } - - // Before every benchmark, clear previous completion flags and sync with server - // Sync is in a way equivalent to MPI_Barrier() - auto prep_fn = [&]() { - coyote_thread.clearCompleted(); - coyote_thread.connSync(IS_CLIENT); - }; - - /* Benchmark function; as eplained in the README - * For RDMA_WRITEs, the client writes multiple times to the server and then the server writes the same content back - * For RDMA READs, the client reads from the server multiple times - * In boths cases, that means there will be n_transfers completed writes to local memory (LOCAL_WRITE) - */ - coyote::CoyoteOper coyote_operation = operation ? coyote::CoyoteOper::REMOTE_RDMA_WRITE : coyote::CoyoteOper::REMOTE_RDMA_READ; - auto bench_fn = [&]() { - for (int i = 0; i < transfers; i++) { - coyote_thread.invoke(coyote_operation, &sg); - } - - while (coyote_thread.checkCompleted(coyote::CoyoteOper::LOCAL_WRITE) != transfers) {} - }; - - // Execute benchmark - coyote::cBench bench(n_runs, 0); - bench.execute(bench_fn, prep_fn); - - // Functional correctness check - if (!operation) { - for (int i = 0; i < sg.rdma.len / sizeof(int); i++) { - assert(mem[i] == i); - } - } - - // For writes, divide by 2, since that is sent two ways (from client to server and then from server to client) - // Reads are one way, so no need to scale - return bench.getAvg() / (1. + (double) operation); -} - -int main(int argc, char *argv[]) { - // CLI arguments - bool operation; - std::string server_ip; - unsigned int min_size, max_size, n_runs; - - boost::program_options::options_description runtime_options("Coyote Perf RDMA Options"); - runtime_options.add_options() - ("ip_address,i", boost::program_options::value(&server_ip), "Server's IP address") - ("operation,o", boost::program_options::value(&operation)->default_value(false), "Benchmark operation: READ(0) or WRITE(1)") - ("runs,r", boost::program_options::value(&n_runs)->default_value(10), "Number of times to repeat the test") - ("min_size,x", boost::program_options::value(&min_size)->default_value(64), "Starting (minimum) transfer size") - ("max_size,X", boost::program_options::value(&max_size)->default_value(1 * 1024 * 1024), "Ending (maximum) transfer size"); - boost::program_options::variables_map command_line_arguments; - boost::program_options::store(boost::program_options::parse_command_line(argc, argv, runtime_options), command_line_arguments); - boost::program_options::notify(command_line_arguments); - - PR_HEADER("CLI PARAMETERS:"); - std::cout << "Server's TCP address: " << server_ip << std::endl; - std::cout << "Benchmark operation: " << (operation ? "WRITE" : "READ") << std::endl; - std::cout << "Number of test runs: " << n_runs << std::endl; - std::cout << "Starting transfer size: " << min_size << std::endl; - std::cout << "Ending transfer size: " << max_size << std::endl << std::endl; - - /* Coyote completely abstracts the complexity behind exchanging QPs and setting up an RDMA connection - * Instead, given a cThread, the target RDMA buffer size and the remote server's TCP address, - * One can use the function initRDMA, which will allocate the buffer and - * Exchange the necessary information with the server; the server calls the equivalent function but without the IP address - */ - coyote::cThread coyote_thread(DEFAULT_VFPGA_ID, getpid(), 0); - int *mem = (int *) coyote_thread.initRDMA(max_size, coyote::defPort, server_ip.c_str()); - if (!mem) { throw std::runtime_error("Could not allocate memory; exiting..."); } - - // Benchmark sweep of latency and throughput - PR_HEADER("RDMA BENCHMARK: CLIENT"); - unsigned int curr_size = max_size; - std::cout << "Size: " << std::setw(8) << curr_size << "; "; - - coyote::sgEntry sg; - sg.rdma = { .len = curr_size }; - - double throughput_time = run_bench(coyote_thread, sg, mem, N_THROUGHPUT_REPS, n_runs, operation); - double throughput = ((double) N_THROUGHPUT_REPS * (double) curr_size) / (1024.0 * 1024.0 * throughput_time * 1e-9); - std::cout << "Average throughput: " << std::setw(8) << throughput << " MB/s; "; - - double latency_time = run_bench(coyote_thread, sg, mem, N_LATENCY_REPS, n_runs, operation); - std::cout << "Average latency: " << std::setw(8) << latency_time / 1e3 << " us" << std::endl; - - // Final sync and exit - coyote_thread.connSync(IS_CLIENT); - return EXIT_SUCCESS; -} \ No newline at end of file diff --git a/examples/MT_pomsarc_09_CC_Testbench/sw/src/include/constants.hpp b/examples/MT_pomsarc_09_CC_Testbench/sw/src/include/constants.hpp deleted file mode 100644 index 225739d5f..000000000 --- a/examples/MT_pomsarc_09_CC_Testbench/sw/src/include/constants.hpp +++ /dev/null @@ -1,9 +0,0 @@ -// Constants shared by both client and server; -// Placed in separate file to avoid any weird changes in one file not reflect in the other - -// Benchmark parameters -#define N_LATENCY_REPS 1 -#define N_THROUGHPUT_REPS 64 - -// Default vFPGA to assign cThreads to; for designs with one region (vFPGA) this is the only possible value -#define DEFAULT_VFPGA_ID 0 \ No newline at end of file diff --git a/examples/MT_pomsarc_09_CC_Testbench/sw/src/server/main.cpp b/examples/MT_pomsarc_09_CC_Testbench/sw/src/server/main.cpp deleted file mode 100644 index 20b6b984e..000000000 --- a/examples/MT_pomsarc_09_CC_Testbench/sw/src/server/main.cpp +++ /dev/null @@ -1,118 +0,0 @@ -/** - * Copyright (c) 2021-2024, Systems Group, ETH Zurich - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - -// External library for easier parsing of CLI arguments by the executable -#include - -// Coyote-specific includes -#include "cThread.hpp" -#include "constants.hpp" - -constexpr bool const IS_CLIENT = false; - -void run_bench( - coyote::cThread &coyote_thread, coyote::sgEntry &sg, - int *mem, uint transfers, uint n_runs, bool operation -) { - // When writing, the server asserts the written payload is correct (which the client sets) - // When reading, the client asserts the read payload is correct (which the server sets) - for (int i = 0; i < sg.rdma.len / sizeof(int); i++) { - mem[i] = operation ? 0 : i; - } - - for (int i = 0; i < n_runs; i++) { - // Clear previous completion flags and sync with client - coyote_thread.clearCompleted(); - coyote_thread.connSync(IS_CLIENT); - - // For writes, wait until client has written the targer number of messages; then write them back - if (operation) { - while (coyote_thread.checkCompleted(coyote::CoyoteOper::LOCAL_WRITE) != transfers) {} - - for (int i = 0; i < transfers; i++) { - coyote_thread.invoke(coyote::CoyoteOper::REMOTE_RDMA_WRITE, &sg); - } - // For reads, the server is completely passive - } else { - - } - } - - // Functional correctness check - if (operation) { - for (int i = 0; i < sg.rdma.len / sizeof(int); i++) { - assert(mem[i] == i); - } - } -} - -int main(int argc, char *argv[]) { - // CLI arguments - bool operation; - unsigned int min_size, max_size, n_runs; - - boost::program_options::options_description runtime_options("Coyote Perf RDMA Options"); - runtime_options.add_options() - ("operation,o", boost::program_options::value(&operation)->default_value(false), "Benchmark operation: READ(0) or WRITE(1)") - ("runs,r", boost::program_options::value(&n_runs)->default_value(10), "Number of times to repeat the test") - ("min_size,x", boost::program_options::value(&min_size)->default_value(64), "Starting (minimum) transfer size") - ("max_size,X", boost::program_options::value(&max_size)->default_value(1 * 1024 * 1024), "Ending (maximum) transfer size"); - boost::program_options::variables_map command_line_arguments; - boost::program_options::store(boost::program_options::parse_command_line(argc, argv, runtime_options), command_line_arguments); - boost::program_options::notify(command_line_arguments); - - PR_HEADER("CLI PARAMETERS:"); - std::cout << "Benchmark operation: " << (operation ? "WRITE" : "READ") << std::endl; - std::cout << "Number of test runs: " << n_runs << std::endl; - std::cout << "Starting transfer size: " << min_size << std::endl; - std::cout << "Ending transfer size: " << max_size << std::endl << std::endl; - - // Allocate Coyothe threa and set-up RDMA connections, buffer etc. - // initRDMA is explained in more detail in client/main.cpp - coyote::cThread coyote_thread(DEFAULT_VFPGA_ID, getpid(), 0); - int *mem = (int *) coyote_thread.initRDMA(max_size, coyote::defPort); - if (!mem) { throw std::runtime_error("Could not allocate memory; exiting..."); } - - // Benchmark sweep; exactly like done in the client code - PR_HEADER("RDMA BENCHMARK: SERVER"); - unsigned int curr_size = min_size; - while(curr_size <= max_size) { - coyote::sgEntry sg; - sg.rdma = { .len = curr_size }; - run_bench(coyote_thread, sg, mem, N_THROUGHPUT_REPS, n_runs, operation); - run_bench(coyote_thread, sg, mem, N_LATENCY_REPS, n_runs, operation); - curr_size *= 2; - } - - // Final sync and exit - coyote_thread.connSync(IS_CLIENT); - return EXIT_SUCCESS; -} \ No newline at end of file diff --git a/examples/MT_pomsarc_10_single_sided_writes/README.md b/examples/MT_pomsarc_10_single_sided_writes/README.md deleted file mode 100644 index f5387b7fd..000000000 --- a/examples/MT_pomsarc_10_single_sided_writes/README.md +++ /dev/null @@ -1,186 +0,0 @@ -# Coyote Example 8: Using the FPGA as a SmartNIC for Remote Direct Memory Access (RDMA) -Welcome to the eigth Coyote example! If you've made it to this point, you've already learnt all the essential concepts of FPGA-CPU interaction for data movement and control flow. Thus, we're adding a new component by demonstrating how Coyote can be used to turn the FPGA into a SmartNIC for 100G RDMA-over-Converged-Ethernet (RoCE v2), allowing for efficient, high-performance data exchange between remote processing nodes and FPGA-offloaded preprocessing of the data streams. As with all Coyote examples, a brief description of the core Coyote concepts covered in this example is included below. - -##### Table of Contents -[RDMA Overview](#rdma-overview) - -[Example Overview](#example-overview) - -[Hardware Concepts](#hardware-concepts) - -[Software Concepts](#software-concepts) - -[Additional Information](#additional-information) - -## RDMA Overview -Remote Direct Memory Access over Converged Ethernet (RoCE v2) is a high-performance networking protocol originally developed for High-Performance Computing. It aims to combine high throughput, low latency and low CPU-utilization by offloading the network stack and direct memory access to the Network Interface Card (NIC), thus grounding its performance claims on host-bypassing and zero-copy: applications running on the host CPUs directly expose memory buffers for DMA to the NIC, so that data can be exchanged without including the host CPU or the OS running on it. In this example, we demonstrate how Coyote can be configured to use the FPGA in the role of such a NIC, allowing for fully protocol-compliant RoCE v2-traffic at 100 Gbps. -For further understanding of the RDMA example, we need to shed some light on the intrinsics of this network standard. -For RDMA communication, two nodes are connected via a so-called Queue Pair (QP), based on previously exchanged information such as respective IP-addresses, location and size of the allocated memory buffers and access keys, and comprising of the idea of queues for work commands and data. The initial exchange of RDMA operations are managed through so-called InfiniBand-verbs, which describe the form of memory transaction between the remote nodes. We have to separate between *one-sided operations* that initiate data transfers over the network without a previous request for consent, and *two-sided operations* where every data transaction is preceeded by an additional exchange between the communicating nodes. Coyote implements the two one-sided RDMA operations: -- ```RDMA WRITE```: One node writes data of certain length to a remote buffer in the other node. Every sent WRITE packet has to be explicitly acked by the receiving node. -- ```RDMA READ```: One node requests to read data of certain length from a remote buffer in the other node. The READ REQUEST packet is implicitly ACK'ed when the remote node sends back RDMA RESPONSE packets with the requested data. - -**IMPORTANT TERMINOLOGY:** -To have a better understanding of this example and the following descriptions, a short overview of the RDMA-specific terminology is very helpful: -- *QPN*: Queue Pair Number. Identifies a RDMA connection between two remote nodes. -- *vaddr*: Virtual address of the remote exposed buffer. For setting up a Queue Pair, a node has to share the virtual address of its exposed buffer with the remote node. -- *rkey*: Remote key for accessing the exposed buffer of the remote node. The remote key is communicated alongside the virtual address as a form of access control. -- *PSN*: Packet Sequence Number used to organize and structure a communication flow between remote RDMA-nodes. Normally, PSN-sequencing is handled by the FPGA-offloaded network stack and thus is not visible to the user. However, following the PSN order is very helpful for debugging RDMA networks. The initial PSN is agreed upon between the remote nodes as part of the initialization of the QP. -- *MTU*: Maximum Transmission Unit, defines the maximum size of a packet. Since RDMA operates on the notion of buffer transmission, the length of the data to be transmitted determines the number of MTU-sized packets that are required for the operation. While the MTU is a compile-time parameter in Coyote, the default size is 4 KB. This means that a ```RDMA WRITE``` of a buffer of up to 4 KB size results in a single packet with ```RDMA WRITE ONLY``` opcode, while a buffer of 8 KB size would be transmitted in two packets, one carrying ```RDMA WRITE FIRST```, the other with ```RDMA WRITE LAST```. For even longer buffers, an arbitrary number of ```RDMA WRITE MIDDLE``` packets is inserted in the exchange. - -## Example Overview -This example measures throughput and latency of RDMA data exchange between two remode nodes via a 100G switched network with both ```RDMA WRITE``` and ```RDMA READ``` operations. Assuming the simpler write functionality, we can very generally think about the process as moving of a data buffer from the host CPU to the local FPGA, where it is streamed to the FPGA-offloaded RDMA stack and then sent via the network to the remote FPGA. There, data is received and then written to the previously specified address of the remote buffer of this remote host CPU. Different to all previous examples, this requires two servers with FPGAs, which also run different software application. The active node, which initiates communication exchange, is referred to as the "client", while the remote node is used as "server". An example of the dataflow is given in the figure below; and as shown in the figure, the steps are the following: -1) *QP Exchange*: As explained above, the RDMA connection in form of a Queue Pair needs to be set up between the remote nodes before the actual benchmarking test can begin. Since RDMA cannot be bootstrapped, this requires out-of-band communication between the two remote CPUs via classic TCP sockets. In the context of the HACC, we are using the 10G management network for this purpose. Using ```ifconfig```, the IP address of the CPU determined to be the server can be evaluated and then given to the experiment code as a parameter. The two nodes follow a standardized protocol to exchange relevant start-up information, such as the IP- addresses of the FPGAs in the 100G data network, the initial PSN and the address and access key of the network exposed data buffers. -2) *QP Setup*: After having exchanged these essential pieces of information, both CPUs forward the aggregated QP data to the FPGAs to create the endpoints of the RDMA flow in the hardware-offloaded network stack. This means making information such as the target IP address or buffer virtual address retrievable by the QPN as essential key. -3) *REMOTE WRITE*: In case of a WRITE-based benchmark, the client now begins with a ```REMOTE WRITE``` Coyote operation to transmit a local buffer via the network to the remote node. For this, both data and commands traverse the RDMA-allocated vFGPA and reach the RDMA stack on the FPGA, where RoCE v2 packets are created and then sent out via the network. -4) *Receiving data*: In the above example, the server FPGA receives the incoming RDMA packets and automatically checks for correctness of the PSN-sequence and QP-specific information. If the received packet fits into the expected communication flow, it gets ACK'ed: an ```RDMA ACK``` is sent back to the client as a reply. At the same time, the server FPGA sends the received data as a ```LOCAL WRITE``` (see Example 1) to the local buffer on the CPU. -5) *Processing ACKs & creating completions*: The client FPGA is constantly listening to the network for ACKs for its outstanding packets. If an ACK is received, the original work command for this transaction is marked as completed, which is also communicated to the local client CPU. If no ACK is received within a certain time interval after sending out a packet, a retransmission is issued. In this case, the same packet is sent again, assuming that it was originally lost in the network or not properly received by the server. - -
- -
- -Generally speaking, throughput and latency tests behave vastly different, also depending on the chosen mode of operation (WRITE vs. READ). The different cases are depicted in the figure below and can be understood as following: -- *Latency* for ```RDMA WRITE```: The client issues a single WRITE of a buffer of specified length to the remote server. Upon reception, the server ACKs and then writes back this very buffer to the client, thus creating a typical "ping-pong pattern" of communication, for which the two-way latency can be measured from sending out a buffer to receiving it back. Depending on the specified experimental arguments, this exchange is repeated for a certain number of times before the average latency of all transmissions is reported. -- *Throughput* for ```RDMA WRITE```: The client issues *n* WRITEs (depending on specification of the argument in experiment execution) of a buffer of specified length to the remote server and waits for all required ACKs. Upon reception, the server writes back the same buffer *n* times again. -- *Latency* for ```RDMA READ```: The client issues a single READ of a buffer of specified length from the remote server. Instead of ACK'ing the server sends the requested data via ```RDMA READ RESPONSEs```. -- *Throughput* for ```RDMA READ``` In this case, the client issues *n* READs (depending on specification of the argument in experiment execution) of a buffer of specified length from the remote server and waits for data delivery via ```RDMA READ RESPONSEs``` from there. The server in this case does not issue reflective READs to the client. - -
- -
- -**IMPORTANT:** When executing RDMA benchmarks, it's important to always start the server's software first before doing the same on the client. The reason for this lies in the intrinsics of the QP exchange: The server software is constructed to listening for incoming TCP connections from the client to then take the passive role in the off-channel exchange of information. - - -## Hardware Concepts -The core complexity for RDMA in Coyote is hidden from the user within the network stack. The RDMA-dedicated vFPGA is mainly used for connecting interfaces without any additional user logic required. -The previously introduced send- and receive-queues are connected as following in the vFPGA: -```Verilog -always_comb begin - /* - * CONTROL SIGNALS - * - * rq_(wr|rd) are two more Coyote interfaces, which act as inputs to the user application - * They corresponds to network write/read requests, set from the host software and driver - * Here, they are used to set Coyote's generic send queues, previously discussed in Example 7. - */ - // Write - sq_wr.valid = rq_wr.valid; - rq_wr.ready = sq_wr.ready; - sq_wr.data = rq_wr.data; // Data field holds information such as remote, virtual address, buffer length etc. - sq_wr.data.strm = STRM_HOST; // For RDMA, by definition data is always on the host - sq_wr.data.dest = is_opcode_rd_resp(rq_wr.data.opcode) ? 0 : 1; - - // Reads - sq_rd.valid = rq_rd.valid; - rq_rd.ready = sq_rd.ready; - sq_rd.data = rq_rd.data; // Data field holds information such as remote, virtual address, buffer length etc. - sq_rd.data.strm = STRM_HOST; // For RDMA, by definition data is always on the host - sq_rd.data.dest = 1; -end -``` - -On the other hand, the data interfaces are connected as following in the module: - -```Verilog -/* - * DATA SIGNALS - * - */ -// Data streams for outgoing RDMA WRITEs (from local host to network stack to remote node) -`AXISR_ASSIGN(axis_host_recv[0], axis_rreq_send[0]) - -// Data streams for incoming RDMA READ RESPONSEs (from remote node to network stack to local host) -`AXISR_ASSIGN(axis_rreq_recv[0], axis_host_send[0]) - -// Data streams for outgoing RDMA READ RESPONSEs (from local host to network stack to remote node) -`AXISR_ASSIGN(axis_host_recv[1], axis_rrsp_send[0]) - -// Data streams for incoming RDMA WRITEs (from remote node to network stack to local host) -`AXISR_ASSIGN(axis_rrsp_recv[0], axis_host_send[1]) -``` - -Thinking one step further, beyond the scope of this performance benchmark, it becomes obvious how any pipelined user logic can be placed on these interfaces to process incoming or outgoing RDMA traffic. Placing customized user logic directly on these datapaths is one of the key benefits of a FPGA-based SmartNIC such as Coyote with the network configuration. - - -## Software Concepts -As described above, the main notion of logic abstraction in RDMA is the Queue-Pair (QP), which connects two remote nodes. Both nodes first form their own local Queue, which again is directly linked to the memory buffer that is exposed via the network. Afterwards, an off-channel exchange via TCP/IP is started to exchange the local queues and then form a QP. - -In Coyote, the notion of a QP is directly linked to a ``coyoteThread``. Thus, the first step of setting up RDMA in Coyote is creating such a thread: -```C++ -coyote::cThread coyote_thread(DEFAULT_VFPGA_ID, getpid(), 0); -```` - -Following the creation of the thread, it's necessary to call the function ```initRDMA()```, which allocates an RDMA buffer of the requested size and performs the QP exchange between the client and server. Importantly, the client needs to pass the server's IP address, while the server code leaves this field blank (nullptr, indicating that it's the server). The function return a pointer to the memory buffer to be used for RDMA communication. -```C++ -int *mem = (int *) coyote_thread.initRDMA(max_size, coyote::defPort, server_ip.c_str()); -``` - -After the setup is completed, we follow the standard approach in Coyote: creating a scatter-gather entry and issuing an ``ìnvoke(...)``` call, but this time indicating a remote operation: -```C++ -coyote::sgEntry sg; -sg.rdma = { .len = curr_size }; -coyote_thread.invoke(coyote::CoyoteOper::REMOTE_RDMA_WRITE, &sg); -``` - - -## Additional Information - -### Special remarks on building Coyote for RDMA experiments -Since different software versions are required for server and client to run a benchmark, two cmake builds have to be triggered to obtain the correct executables. In order to build the server code, one needs to specify `-DINSTANCE=server`, while a build of the client software is specified with `-DINSTANCE=client`: -```bash -cd sw/ - -mkdir build_server && cd build_server -cmake ../../ -DINSTANCE=server && make - -cd ../ -mkdir build_client && cd build_client -cmake ../../ -DINSTANCE=client && make -``` - -### Command line parameters and hints on running the experiment -As said above, it's crucial to start the software for experiments first on the node that we want to use as server, before doing the same for the client. Furthermore, it's important that the IP address specified as argument on the client machine **belongs to the server-CPU (not the client CPU, not the server FPGA)**. The different available network interfaces can be explored with ```ifconfig```. -The following description helps to match the relevant command line parameters to details of the experiment execution described before: - -- `[--ip_address | -i] ` IP address of the server CPU for out-of-band QP-exchange via TCP-sockets before the actual RDMA experiment can begin. -- `[--operation | -o] ` Decides whether the benchmark is performed for WRITE (1) or READ (0) operations. Default: 0 -- `[--min_size | -x] ` Minimum size of transferred buffer in the experiment. Default: 64 [B] -- `[--max_size | -X] ` Maximum size of transferred buffer in the experiment. Default: 1048576 [B] ~ 1 [MB] -- `[--runs | -r] ` Number of test runs, to obtain statistically significant results For latency-tests, `r` ping-pong exchanges will be executed. For throughput tests, `r` independent exchanges of 64 messages are executed. - -### Network debugging -Coyote provides tooling to check the status of network transmissions and identify potential problems, most notable packet losses and retransmissions. These statistics can be queried via -`cat /sys/kernel/coyote_sysfs_0/cyt_attr_nstats`. - -A typical output for this could look like this: -``` - -- NET STATS QSFP0 - -RX pkgs: 316 -TX pkgs: 242 -ARP RX pkgs: 4 -ARP TX pkgs: 2 -ICMP RX pkgs: 0 -ICMP TX pkgs: 0 -TCP RX pkgs: 0 -TCP TX pkgs: 0 -ROCE RX pkgs: 245 -ROCE TX pkgs: 240 -IBV RX pkgs: 240 -IBV TX pkgs: 240 -PSN drop cnt: 0 -Retrans cnt: 0 -TCP session cnt: 0 -STRM down: 0 -``` -In this case, 240 RDMA packets have been received and sent (``IBV RX/TX``), no packet has been lost or retransmitted. A major problem would be indicated by ``STRM down: 1``, as this would signal a complete shutdown of the networking stack. In such a case, only a hard reset including reprogramming the FPGA can save the user. -Apart from these Coyote-provided utilities, standard network debugging tools such as switch- or external NIC-based traffic capturing can be used to understand traffic issues and patterns. As described in the next example, we also offer a 100G-capable traffic sniffer for Coyote that directly produces pcap-files compatible to any standard network analysis tool such as wireshark. If even this low-level debugging capabilities are not deemed satisfactory, also classic ILA-based probing directly on data- and controlpaths of the FPGA-design is possible. - -### Expeted results -The following results are expected for reads (left) and writes (right): - -

- - -

\ No newline at end of file diff --git a/examples/MT_pomsarc_10_single_sided_writes/hw/CMakeLists.txt b/examples/MT_pomsarc_10_single_sided_writes/hw/CMakeLists.txt deleted file mode 100644 index e729f3666..000000000 --- a/examples/MT_pomsarc_10_single_sided_writes/hw/CMakeLists.txt +++ /dev/null @@ -1,32 +0,0 @@ -# CMake configuration -cmake_minimum_required(VERSION 3.5) -set(CYT_DIR ${CMAKE_SOURCE_DIR}/../../../) -set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CYT_DIR}/cmake) -find_package(CoyoteHW REQUIRED) - -project(example_08_perf_rdma) -message("*** Coyote Example 8: Remote Direct Memory Access (RDMA) [Hardware Build] ***") - -# Enables two streams from host memory (1 for requests, 1 for response) -set(EN_STRM 1) -set(N_STRM_AXI 2) - -# Incldue Coyote's RDMA stack during synthesis -set(EN_RDMA 1) - -# Number of vFPGAs (user applications) -set(N_REGIONS 1) - -# Build with optimization, since timing closure with RDMA can be difficult -set(BUILD_OPT 1) - -# Confirm that the selected options are allowed -validation_checks_hw() - -# Load a user application in Configuration #0, Region #0 -load_apps ( - VFPGA_C0_0 "src" -) - -# Create the hardware project -create_hw() diff --git a/examples/MT_pomsarc_10_single_sided_writes/hw/src/init_ip.tcl b/examples/MT_pomsarc_10_single_sided_writes/hw/src/init_ip.tcl deleted file mode 100644 index 64dc40e3d..000000000 --- a/examples/MT_pomsarc_10_single_sided_writes/hw/src/init_ip.tcl +++ /dev/null @@ -1,2 +0,0 @@ -create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_perf_rdma -set_property -dict [list CONFIG.C_PROBE17_WIDTH {128} CONFIG.C_PROBE14_WIDTH {128} CONFIG.C_NUM_OF_PROBES {18} CONFIG.C_EN_STRG_QUAL {1} CONFIG.ALL_PROBE_SAME_MU_CNT {2}] [get_ips ila_perf_rdma] \ No newline at end of file diff --git a/examples/MT_pomsarc_10_single_sided_writes/hw/src/vfpga_top.svh b/examples/MT_pomsarc_10_single_sided_writes/hw/src/vfpga_top.svh deleted file mode 100644 index 240e06b7e..000000000 --- a/examples/MT_pomsarc_10_single_sided_writes/hw/src/vfpga_top.svh +++ /dev/null @@ -1,71 +0,0 @@ -always_comb begin - /* - * CONTROL SIGNALS - * - * rq_(wr|rd) are two more Coyote interfaces, which act as inputs to the user application - * They corresponds to network write/read requests, set from the host software and driver - * Here, they are used to set Coyote's generic send queues, previously discussed in Example 7. - */ - // Write - sq_wr.valid = rq_wr.valid; - rq_wr.ready = sq_wr.ready; - sq_wr.data = rq_wr.data; // Data field holds information such as remote, virtual address, buffer length etc. - sq_wr.data.strm = STRM_HOST; // For RDMA, by definition data is always on the host - sq_wr.data.dest = is_opcode_rd_resp(rq_wr.data.opcode) ? 0 : 1; - - // Reads - sq_rd.valid = rq_rd.valid; - rq_rd.ready = sq_rd.ready; - sq_rd.data = rq_rd.data; // Data field holds information such as remote, virtual address, buffer length etc. - sq_rd.data.strm = STRM_HOST; // For RDMA, by definition data is always on the host - sq_rd.data.dest = 1; -end - -/* - * DATA SIGNALS - * - */ -// Data streams for outgoing RDMA WRITEs (from local host to network stack to remote node) -`AXISR_ASSIGN(axis_host_recv[0], axis_rreq_send[0]) - -// Data streams for incoming RDMA READ RESPONSEs (from remote node to network stack to local host) -`AXISR_ASSIGN(axis_rreq_recv[0], axis_host_send[0]) - -// Data streams for outgoing RDMA READ RESPONSEs (from local host to network stack to remote node) -`AXISR_ASSIGN(axis_host_recv[1], axis_rrsp_send[0]) - -// Data streams for incoming RDMA WRITEs (from remote node to network stack to local host) -`AXISR_ASSIGN(axis_rrsp_recv[0], axis_host_send[1]) - -// Tie off unused interfaces -always_comb axi_ctrl.tie_off_s(); -always_comb notify.tie_off_m(); -always_comb cq_rd.tie_off_s(); -always_comb cq_wr.tie_off_s(); - -// ILA for debugging -ila_perf_rdma inst_ila_perf_rdma ( - .clk(aclk), - .probe0(axis_host_recv[0].tvalid), // 1 - .probe1(axis_host_recv[0].tready), // 1 - .probe2(axis_host_recv[0].tlast), // 1 - - .probe3(axis_host_recv[1].tvalid), // 1 - .probe4(axis_host_recv[1].tready), // 1 - .probe5(axis_host_recv[1].tlast), // 1 - - .probe6(axis_host_send[0].tvalid), // 1 - .probe7(axis_host_send[0].tready), // 1 - .probe8(axis_host_send[0].tlast), // 1 - - .probe9(axis_host_send[1].tvalid), // 1 - .probe10(axis_host_send[1].tready), // 1 - .probe11(axis_host_send[1].tlast), // 1 - - .probe12(sq_wr.valid), // 1 - .probe13(sq_wr.ready), // 1 - .probe14(sq_wr.data), // 128 - .probe15(sq_rd.valid), // 1 - .probe16(sq_rd.ready), // 1 - .probe17(sq_rd.data) // 128 -); diff --git a/examples/MT_pomsarc_10_single_sided_writes/img/rdma_results_read.png b/examples/MT_pomsarc_10_single_sided_writes/img/rdma_results_read.png deleted file mode 100644 index efc149483e13286d8c1704987b5085e0bb1f47c4..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 130953 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vaddr…34OUTGOING: Command & DataREMOTEWRITEdata={1, 2, 3, …}INCOMING: Command & DataLOCAL WRITEdata={1, 2, 3, …}5INCOMING: CompletionDataHeader \ No newline at end of file diff --git a/examples/MT_pomsarc_10_single_sided_writes/img/rdma_traffic_pattern.svg b/examples/MT_pomsarc_10_single_sided_writes/img/rdma_traffic_pattern.svg deleted file mode 100644 index cc7223ad0..000000000 --- a/examples/MT_pomsarc_10_single_sided_writes/img/rdma_traffic_pattern.svg +++ /dev/null @@ -1 +0,0 @@ -LATENCYTHROUGHPUTRDMA WRITERDMA READCPUFPGACPUFPGACPUFPGACPUFPGACPUFPGACPUFPGACPUFPGACPUFPGARDMA WRITEACKRDMA WRITEACKRDMA WRITE…RDMA WRITERDMA WRITEACKACKRDMA WRITERDMA WRITE…READ REQUESTREAD RESPONSE…READ REQUESTREAD REQUESTREAD REQUESTREAD RESPONSEREAD RESPONSEREAD RESPONSEREAD REQUESTREAD RESPONSE \ No newline at end of file diff --git a/examples/MT_pomsarc_10_single_sided_writes/sw/CMakeLists.txt b/examples/MT_pomsarc_10_single_sided_writes/sw/CMakeLists.txt deleted file mode 100644 index c3e977433..000000000 --- a/examples/MT_pomsarc_10_single_sided_writes/sw/CMakeLists.txt +++ /dev/null @@ -1,26 +0,0 @@ -# CMake configuration -cmake_minimum_required(VERSION 3.5) -project(example_08_perf_rdma) - -set(CYT_DIR ${CMAKE_SOURCE_DIR}/../../../) -set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CYT_DIR}/cmake) -find_package(CoyoteSW REQUIRED) - -# Add source files -set(INSTANCE "client" CACHE STRING "RDMA software build targe: client or server") -if(INSTANCE STREQUAL "server") - set(TARGET_DIR "${CMAKE_SOURCE_DIR}/src/server") - message("*** Coyote Example 8: RDMA Server [Software Build] ***") - include_directories("${CMAKE_SOURCE_DIR}/src/include") -endif() -if(INSTANCE STREQUAL "client") - set(TARGET_DIR "${CMAKE_SOURCE_DIR}/src/client") - message("*** Coyote Example 8: RDMA Client [Software Build] ***") - include_directories("${CMAKE_SOURCE_DIR}/src/include") -endif() - -# Create build targets and link against required libraries -set(EXEC test) -add_executable(${EXEC} ${TARGET_DIR}/main.cpp) -target_link_libraries(${EXEC} PUBLIC Coyote) -target_link_directories(${EXEC} PUBLIC /usr/local/lib) diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv index 3ad7d2865..e00eb64e7 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv @@ -1,5 +1,7 @@ import lynxTypes::*; + +// defines wether simulated ECN markings should be generated and also add test readout signals as ILAs `define CC_TEST module cc_queue @@ -14,42 +16,55 @@ module cc_queue metaIntf.m m_req ); + +//============ DCQCN PARAMETERS ================ +//(Test setup parameters after the ifdef CC_TEST) + +//defines the queue size //localparam integer RDMA_N_OST = RDMA_N_WR_OUTSTANDING; localparam integer RDMA_N_OST = 20; -localparam integer RDMA_OST_BITS = $clog2(RDMA_N_OST); -localparam integer RD_OP = 0; -localparam integer WR_OP = 1; - +//Send Rate default values (do not set too low or rounding might prevent rate increases (~100 cycles should be safe)) +//IMPORTANT: send rate is expressed here as the number of cycles between two packets, higher Rc/Rt -> lower send rate +//Same with R_MIN below localparam integer Rt_default = 200; localparam integer Rc_default = 8192; localparam integer R_MIN = 200; + +//R_CAP is the maximum after which Rc/Rt will no longer be increased. Current value is just chosen to fit nicely in the simulation localparam integer R_CAP = 16384; +//Time interval after a rate decrease in which no further rate decrease can happen (to give the network some time to adjust to new rate) localparam integer N_min_time_between_ecn_marks = 12500; +//Timeout values for the lowering of the rate reduction factor (num cycles needs to be higher than N_min_time_between_ecn_marks) localparam integer K = 13750; +//constant values by which send rate is adjusted in an additive rate increase step (higher value can be chosen for the hyper increase phase) localparam integer R_ADDITIVE_INCREASE = 128; localparam integer R_HYPER_INCREASE = 128; +//precision of rate reduction factor (do not change without changing all Sa values) +localparam integer Sg = 7; -localparam integer Sg = 8; +//Number of steps of recovery steps before additive rate increase sets in localparam integer F = 5; +//time out values for the time and byte counter in num cycles and num packets respectively localparam integer time_threshhold = 50000; localparam integer byte_threshhold = 35; +//Precomputed Rate reduction factors localparam integer Max_Sa_index = 28; localparam integer Sa_fixed[0:28] = {256, 241, 228, 218, 209, 201, 194, 188, 182, 178, 173, 170, 166, 163, 161, 158, 156, 154, 152, 150, 148, 147, 146, 144, 143, 142, 141, 140, 139}; -logic[4:0] Sa_index; +//================================================ +logic[4:0] Sa_index; logic[15:0] Rt; logic[15:0] Rc; -//logic[63:0] Sa; logic[23:0] timer; logic[23:0] timer_send_rate; @@ -70,11 +85,13 @@ metaIntf #(.STYPE(dreq_t)) queue_out (); `ifdef CC_TEST -//simul part -logic[23:0] ecn_timer; +//============ TEST PARAMETERS ================ + +//number of cycles after ECN rate is changed to the next entry in the ECN_rates list localparam integer ecn_timer_trigger_threshhold = 5000000; -logic ecn_alternator; -logic[15:0] ecn_counter; + +// List containing ECN rates during a test run, value indicates number of non marked packets after a marked packet. + //1 //localparam integer Ecn_rates[0:6] = {9999, 1, 9 ,99, 999, 9999}; //2 @@ -84,12 +101,23 @@ logic[15:0] ecn_counter; //4 localparam integer Ecn_rates[0:7] = {9999, 99, 29, 24, 19, 9, 29, 39}; -logic ecn_test_starter; +//needs to be number of different ECN rate steps - 1 localparam Ecn_rates_max_index = 7; + +// trigger interval for ila_trigger signal to view results in Vivado +localparam integer Ila_readout_timer_threshhold = 40000; + +//================================================ + +logic[23:0] ecn_timer; +logic ecn_alternator; +logic[15:0] ecn_counter; +logic ecn_test_starter; + logic[2:0] ecn_rates_index; logic[15:0] ila_readout_timer; -localparam integer Ila_readout_timer_threshhold = 40000; + logic ila_trigger; @@ -194,7 +222,7 @@ always_ff @(posedge aclk) begin Rt <= Rc; if(Rc <= R_CAP) begin - Rc <= (Rc * Sa_fixed[Sa_index]) >> 7; + Rc <= (Rc * Sa_fixed[Sa_index]) >> Sg; end if(!(Sa_index == 0)) begin Sa_index <= Sa_index - 1; @@ -378,7 +406,7 @@ always_ff @(posedge aclk) begin Rt <= Rc; if(Rc <= R_CAP) begin - Rc <= (Rc * Sa_fixed[Sa_index]) >> 7; + Rc <= (Rc * Sa_fixed[Sa_index]) >> Sg; end if(!(Sa_index == 0)) begin Sa_index <= Sa_index - 1; From 35fc67262760d9986fa08fcdb5b7598ea0fdd993 Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Mon, 10 Nov 2025 00:05:27 +0100 Subject: [PATCH 40/52] submodule update --- .../rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv | 7 +- hw/hdl/network/rdma/MT_pomsarc_benchy.sv | 137 ------------------ hw/services/network | 2 +- 3 files changed, 5 insertions(+), 141 deletions(-) delete mode 100644 hw/hdl/network/rdma/MT_pomsarc_benchy.sv diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv index e00eb64e7..5161bc2f7 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv @@ -99,10 +99,11 @@ localparam integer ecn_timer_trigger_threshhold = 5000000; //3 //localparam integer Ecn_rates[0:6] = {9999, 1, 9, 14 , 19, 24, 9999}; //4 -localparam integer Ecn_rates[0:7] = {9999, 99, 29, 24, 19, 9, 29, 39}; - +//localparam integer Ecn_rates[0:7] = {9999, 99, 29, 24, 19, 9, 29, 39}; +//5 +localparam integer Ecn_rates[0:15] = {9999, 99, 29, 24, 19, 9, 29, 39, 39, 99, 99, 149, 149,199,199,9999}; //needs to be number of different ECN rate steps - 1 -localparam Ecn_rates_max_index = 7; +localparam Ecn_rates_max_index = 15; // trigger interval for ila_trigger signal to view results in Vivado localparam integer Ila_readout_timer_threshhold = 40000; diff --git a/hw/hdl/network/rdma/MT_pomsarc_benchy.sv b/hw/hdl/network/rdma/MT_pomsarc_benchy.sv deleted file mode 100644 index a08dead5f..000000000 --- a/hw/hdl/network/rdma/MT_pomsarc_benchy.sv +++ /dev/null @@ -1,137 +0,0 @@ -/*`timescale 1ns / 1ps - -`define DBG_IBV - -import lynxTypes::*; - -/** - * @brief RoCE instantiation - * - * RoCE stack - */ -/* -module benchy -( - input logic aclk, - input logic aresetn, - - metaIntf.s s_req, - metaIntf.m m_req -); - -localparam integer packet_gap = 5; //inverse of marked percentage -localparam integer measurement_gap = 50; - - -//localparam integer max_timer = 10000000000; - -logic[31:0] timer; -logic[31:0] packet_counter; -logic[31:0] packet_gap_counter; - - - -logic running; - -logic ecn, ecn_v, ecn_r; - -logic[31:0] measurement_gap_timer; - -always_ff @(posedge aclk) begin - if (aresetn == 1'b0) begin - timer <= 0; - measurement_gap_timer <= 0; - packet_counter <= 0; - packet_gap_counter <=0; - - ecn <= 0; - ecn_v <= 0; - running <= 0; - measurement_gap_timer <= 0; - //measurement_trigger <= 0; - - end - else begin - timer <= timer + 1; - - /*if(timer >= max_timer) begin - timer <= 0; - measurement_gap_timer <= 0; - packet_counter <= 0; - packet_gap_counter <= 0; - - ecn <= 0; - ecn_v <= 0; - running <= 0; - measurement_gap_timer <= 0; - //measurement_trigger <= 0; - end - else begin*/ -/* - measurement_gap_timer <= measurement_gap_timer + 1; - ecn_v <= 0; - ecn <= 0; - if(s_req.valid == 1) begin - if(running == 0) begin - running <= 1; - measurement_gap_timer <= 0; - end - - ecn_v <= 1; - - if(packet_gap_counter < packet_gap) begin - ecn <= 0; - end - else begin - ecn <= 1; - end - if(s_req.ready) begin - if(packet_gap_counter >= packet_gap) begin - packet_gap_counter <= 0; - end - else begin - packet_gap_counter <= packet_gap_counter + 1; - end - packet_counter <= packet_counter + 1; - - end - end - - if(measurement_gap_timer >= measurement_gap) begin - measurement_gap_timer <= 0; - end - //end - - end -end - -ila_testbench_CC inst_ila_testbench_CC( - .clk(aclk), - .probe0(timer), - .probe1(measurement_gap_timer), - .probe2(running), - .probe3(ecn), - .probe4(ecn_v), - .probe5(ecn_r) -); - - - -cc_queue inst_cc_queue( - .aclk(aclk), - .aresetn(aresetn), - - .ecn_mark(ecn), - .ecn_valid(ecn_v), - .ecn_ready(ecn_r), - - - .s_req(s_req), - .m_req(m_req) -); - - - - -endmodule -*/ \ No newline at end of file diff --git a/hw/services/network b/hw/services/network index ffd8b038b..4214e4c86 160000 --- a/hw/services/network +++ b/hw/services/network @@ -1 +1 @@ -Subproject commit ffd8b038b2b7145c266fed2dd9d706f24b8e7869 +Subproject commit 4214e4c8652bfb8a63a38e52d37c00018fc9646c From 24c25b4945cca4036af340efdd8f462ed266c0df Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Mon, 10 Nov 2025 00:22:49 +0100 Subject: [PATCH 41/52] added last example and scripts --- .../Output_Grap_Script-checkpoint.ipynb | 151 ++++++++++++++++++ ...duction_factor_calc_scrip-checkpoint.ipynb | 75 +++++++++ .../Test_script/Output_Grap_Script.ipynb | 134 ++++++++++++++++ .../Reduction_factor_calc_scrip.ipynb | 75 +++++++++ .../Test_script/example_graph.png | Bin 0 -> 378223 bytes 5 files changed, 435 insertions(+) create mode 100644 examples/Congestion_Control_Test/Test_script/.ipynb_checkpoints/Output_Grap_Script-checkpoint.ipynb create mode 100644 examples/Congestion_Control_Test/Test_script/.ipynb_checkpoints/Reduction_factor_calc_scrip-checkpoint.ipynb create mode 100644 examples/Congestion_Control_Test/Test_script/Output_Grap_Script.ipynb create mode 100644 examples/Congestion_Control_Test/Test_script/Reduction_factor_calc_scrip.ipynb create mode 100644 examples/Congestion_Control_Test/Test_script/example_graph.png diff --git a/examples/Congestion_Control_Test/Test_script/.ipynb_checkpoints/Output_Grap_Script-checkpoint.ipynb b/examples/Congestion_Control_Test/Test_script/.ipynb_checkpoints/Output_Grap_Script-checkpoint.ipynb new file mode 100644 index 000000000..483283ad3 --- /dev/null +++ b/examples/Congestion_Control_Test/Test_script/.ipynb_checkpoints/Output_Grap_Script-checkpoint.ipynb @@ -0,0 +1,151 @@ +{ + "cells": [ + { + "cell_type": "code", + "execution_count": 1, + "id": "f5274104-49ba-4f8d-9509-5322e1aa2ca5", + "metadata": {}, + "outputs": [], + "source": [ + "import matplotlib.pyplot as plt\n", + "import pandas as pd\n", + "import numpy as np\n", + "import sys" + ] + }, + { + "cell_type": "code", + "execution_count": 2, + "id": "8af48534-32bc-4d73-98a1-eba531c0bafe", + "metadata": {}, + "outputs": [ + { + "ename": "FileNotFoundError", + "evalue": "[Errno 2] No such file or directory: './ila_example.csv'", + "output_type": "error", + "traceback": [ + "\u001b[31m---------------------------------------------------------------------------\u001b[39m", + "\u001b[31mFileNotFoundError\u001b[39m Traceback (most recent call last)", + "\u001b[36mCell\u001b[39m\u001b[36m \u001b[39m\u001b[32mIn[2]\u001b[39m\u001b[32m, line 6\u001b[39m\n\u001b[32m 4\u001b[39m rates = [(\u001b[32m1\u001b[39m/\u001b[32m10000\u001b[39m), (\u001b[32m1\u001b[39m/\u001b[32m100\u001b[39m), (\u001b[32m1\u001b[39m/\u001b[32m30\u001b[39m), (\u001b[32m1\u001b[39m/\u001b[32m25\u001b[39m), (\u001b[32m1\u001b[39m/\u001b[32m20\u001b[39m), (\u001b[32m1\u001b[39m/\u001b[32m10\u001b[39m), (\u001b[32m1\u001b[39m/\u001b[32m30\u001b[39m), (\u001b[32m1\u001b[39m/\u001b[32m40\u001b[39m), (\u001b[32m1\u001b[39m/\u001b[32m40\u001b[39m) ,(\u001b[32m1\u001b[39m/\u001b[32m100\u001b[39m), (\u001b[32m1\u001b[39m/\u001b[32m100\u001b[39m), (\u001b[32m1\u001b[39m/\u001b[32m150\u001b[39m), (\u001b[32m1\u001b[39m/\u001b[32m150\u001b[39m), (\u001b[32m1\u001b[39m/\u001b[32m200\u001b[39m), (\u001b[32m1\u001b[39m/\u001b[32m200\u001b[39m), (\u001b[32m1\u001b[39m/\u001b[32m10000\u001b[39m)]\n\u001b[32m 5\u001b[39m ila_tigger_interval = \u001b[32m40000\u001b[39m\n\u001b[32m----> \u001b[39m\u001b[32m6\u001b[39m df = \u001b[43mpd\u001b[49m\u001b[43m.\u001b[49m\u001b[43mread_csv\u001b[49m\u001b[43m(\u001b[49m\u001b[43mpath\u001b[49m\u001b[43m)\u001b[49m\n", + "\u001b[36mFile \u001b[39m\u001b[32m~/.local/lib/python3.12/site-packages/pandas/io/parsers/readers.py:1026\u001b[39m, in \u001b[36mread_csv\u001b[39m\u001b[34m(filepath_or_buffer, sep, delimiter, header, names, index_col, usecols, dtype, engine, converters, true_values, false_values, skipinitialspace, skiprows, skipfooter, nrows, na_values, keep_default_na, na_filter, verbose, skip_blank_lines, parse_dates, infer_datetime_format, keep_date_col, date_parser, date_format, dayfirst, cache_dates, iterator, chunksize, compression, thousands, decimal, lineterminator, quotechar, quoting, doublequote, escapechar, comment, encoding, encoding_errors, dialect, on_bad_lines, delim_whitespace, low_memory, memory_map, float_precision, storage_options, dtype_backend)\u001b[39m\n\u001b[32m 1013\u001b[39m kwds_defaults = _refine_defaults_read(\n\u001b[32m 1014\u001b[39m dialect,\n\u001b[32m 1015\u001b[39m delimiter,\n\u001b[32m (...)\u001b[39m\u001b[32m 1022\u001b[39m dtype_backend=dtype_backend,\n\u001b[32m 1023\u001b[39m )\n\u001b[32m 1024\u001b[39m kwds.update(kwds_defaults)\n\u001b[32m-> \u001b[39m\u001b[32m1026\u001b[39m \u001b[38;5;28;01mreturn\u001b[39;00m \u001b[43m_read\u001b[49m\u001b[43m(\u001b[49m\u001b[43mfilepath_or_buffer\u001b[49m\u001b[43m,\u001b[49m\u001b[43m \u001b[49m\u001b[43mkwds\u001b[49m\u001b[43m)\u001b[49m\n", + "\u001b[36mFile \u001b[39m\u001b[32m~/.local/lib/python3.12/site-packages/pandas/io/parsers/readers.py:620\u001b[39m, in \u001b[36m_read\u001b[39m\u001b[34m(filepath_or_buffer, kwds)\u001b[39m\n\u001b[32m 617\u001b[39m _validate_names(kwds.get(\u001b[33m\"\u001b[39m\u001b[33mnames\u001b[39m\u001b[33m\"\u001b[39m, \u001b[38;5;28;01mNone\u001b[39;00m))\n\u001b[32m 619\u001b[39m \u001b[38;5;66;03m# Create the parser.\u001b[39;00m\n\u001b[32m--> \u001b[39m\u001b[32m620\u001b[39m parser = \u001b[43mTextFileReader\u001b[49m\u001b[43m(\u001b[49m\u001b[43mfilepath_or_buffer\u001b[49m\u001b[43m,\u001b[49m\u001b[43m \u001b[49m\u001b[43m*\u001b[49m\u001b[43m*\u001b[49m\u001b[43mkwds\u001b[49m\u001b[43m)\u001b[49m\n\u001b[32m 622\u001b[39m \u001b[38;5;28;01mif\u001b[39;00m chunksize \u001b[38;5;129;01mor\u001b[39;00m iterator:\n\u001b[32m 623\u001b[39m \u001b[38;5;28;01mreturn\u001b[39;00m parser\n", + "\u001b[36mFile \u001b[39m\u001b[32m~/.local/lib/python3.12/site-packages/pandas/io/parsers/readers.py:1620\u001b[39m, in \u001b[36mTextFileReader.__init__\u001b[39m\u001b[34m(self, f, engine, **kwds)\u001b[39m\n\u001b[32m 1617\u001b[39m \u001b[38;5;28mself\u001b[39m.options[\u001b[33m\"\u001b[39m\u001b[33mhas_index_names\u001b[39m\u001b[33m\"\u001b[39m] = kwds[\u001b[33m\"\u001b[39m\u001b[33mhas_index_names\u001b[39m\u001b[33m\"\u001b[39m]\n\u001b[32m 1619\u001b[39m \u001b[38;5;28mself\u001b[39m.handles: IOHandles | \u001b[38;5;28;01mNone\u001b[39;00m = \u001b[38;5;28;01mNone\u001b[39;00m\n\u001b[32m-> \u001b[39m\u001b[32m1620\u001b[39m \u001b[38;5;28mself\u001b[39m._engine = \u001b[38;5;28;43mself\u001b[39;49m\u001b[43m.\u001b[49m\u001b[43m_make_engine\u001b[49m\u001b[43m(\u001b[49m\u001b[43mf\u001b[49m\u001b[43m,\u001b[49m\u001b[43m \u001b[49m\u001b[38;5;28;43mself\u001b[39;49m\u001b[43m.\u001b[49m\u001b[43mengine\u001b[49m\u001b[43m)\u001b[49m\n", + "\u001b[36mFile \u001b[39m\u001b[32m~/.local/lib/python3.12/site-packages/pandas/io/parsers/readers.py:1880\u001b[39m, in \u001b[36mTextFileReader._make_engine\u001b[39m\u001b[34m(self, f, engine)\u001b[39m\n\u001b[32m 1878\u001b[39m \u001b[38;5;28;01mif\u001b[39;00m \u001b[33m\"\u001b[39m\u001b[33mb\u001b[39m\u001b[33m\"\u001b[39m \u001b[38;5;129;01mnot\u001b[39;00m \u001b[38;5;129;01min\u001b[39;00m mode:\n\u001b[32m 1879\u001b[39m mode += \u001b[33m\"\u001b[39m\u001b[33mb\u001b[39m\u001b[33m\"\u001b[39m\n\u001b[32m-> \u001b[39m\u001b[32m1880\u001b[39m \u001b[38;5;28mself\u001b[39m.handles = \u001b[43mget_handle\u001b[49m\u001b[43m(\u001b[49m\n\u001b[32m 1881\u001b[39m \u001b[43m \u001b[49m\u001b[43mf\u001b[49m\u001b[43m,\u001b[49m\n\u001b[32m 1882\u001b[39m \u001b[43m \u001b[49m\u001b[43mmode\u001b[49m\u001b[43m,\u001b[49m\n\u001b[32m 1883\u001b[39m \u001b[43m \u001b[49m\u001b[43mencoding\u001b[49m\u001b[43m=\u001b[49m\u001b[38;5;28;43mself\u001b[39;49m\u001b[43m.\u001b[49m\u001b[43moptions\u001b[49m\u001b[43m.\u001b[49m\u001b[43mget\u001b[49m\u001b[43m(\u001b[49m\u001b[33;43m\"\u001b[39;49m\u001b[33;43mencoding\u001b[39;49m\u001b[33;43m\"\u001b[39;49m\u001b[43m,\u001b[49m\u001b[43m \u001b[49m\u001b[38;5;28;43;01mNone\u001b[39;49;00m\u001b[43m)\u001b[49m\u001b[43m,\u001b[49m\n\u001b[32m 1884\u001b[39m \u001b[43m \u001b[49m\u001b[43mcompression\u001b[49m\u001b[43m=\u001b[49m\u001b[38;5;28;43mself\u001b[39;49m\u001b[43m.\u001b[49m\u001b[43moptions\u001b[49m\u001b[43m.\u001b[49m\u001b[43mget\u001b[49m\u001b[43m(\u001b[49m\u001b[33;43m\"\u001b[39;49m\u001b[33;43mcompression\u001b[39;49m\u001b[33;43m\"\u001b[39;49m\u001b[43m,\u001b[49m\u001b[43m \u001b[49m\u001b[38;5;28;43;01mNone\u001b[39;49;00m\u001b[43m)\u001b[49m\u001b[43m,\u001b[49m\n\u001b[32m 1885\u001b[39m \u001b[43m \u001b[49m\u001b[43mmemory_map\u001b[49m\u001b[43m=\u001b[49m\u001b[38;5;28;43mself\u001b[39;49m\u001b[43m.\u001b[49m\u001b[43moptions\u001b[49m\u001b[43m.\u001b[49m\u001b[43mget\u001b[49m\u001b[43m(\u001b[49m\u001b[33;43m\"\u001b[39;49m\u001b[33;43mmemory_map\u001b[39;49m\u001b[33;43m\"\u001b[39;49m\u001b[43m,\u001b[49m\u001b[43m \u001b[49m\u001b[38;5;28;43;01mFalse\u001b[39;49;00m\u001b[43m)\u001b[49m\u001b[43m,\u001b[49m\n\u001b[32m 1886\u001b[39m \u001b[43m \u001b[49m\u001b[43mis_text\u001b[49m\u001b[43m=\u001b[49m\u001b[43mis_text\u001b[49m\u001b[43m,\u001b[49m\n\u001b[32m 1887\u001b[39m \u001b[43m \u001b[49m\u001b[43merrors\u001b[49m\u001b[43m=\u001b[49m\u001b[38;5;28;43mself\u001b[39;49m\u001b[43m.\u001b[49m\u001b[43moptions\u001b[49m\u001b[43m.\u001b[49m\u001b[43mget\u001b[49m\u001b[43m(\u001b[49m\u001b[33;43m\"\u001b[39;49m\u001b[33;43mencoding_errors\u001b[39;49m\u001b[33;43m\"\u001b[39;49m\u001b[43m,\u001b[49m\u001b[43m \u001b[49m\u001b[33;43m\"\u001b[39;49m\u001b[33;43mstrict\u001b[39;49m\u001b[33;43m\"\u001b[39;49m\u001b[43m)\u001b[49m\u001b[43m,\u001b[49m\n\u001b[32m 1888\u001b[39m \u001b[43m \u001b[49m\u001b[43mstorage_options\u001b[49m\u001b[43m=\u001b[49m\u001b[38;5;28;43mself\u001b[39;49m\u001b[43m.\u001b[49m\u001b[43moptions\u001b[49m\u001b[43m.\u001b[49m\u001b[43mget\u001b[49m\u001b[43m(\u001b[49m\u001b[33;43m\"\u001b[39;49m\u001b[33;43mstorage_options\u001b[39;49m\u001b[33;43m\"\u001b[39;49m\u001b[43m,\u001b[49m\u001b[43m \u001b[49m\u001b[38;5;28;43;01mNone\u001b[39;49;00m\u001b[43m)\u001b[49m\u001b[43m,\u001b[49m\n\u001b[32m 1889\u001b[39m \u001b[43m\u001b[49m\u001b[43m)\u001b[49m\n\u001b[32m 1890\u001b[39m \u001b[38;5;28;01massert\u001b[39;00m \u001b[38;5;28mself\u001b[39m.handles \u001b[38;5;129;01mis\u001b[39;00m \u001b[38;5;129;01mnot\u001b[39;00m \u001b[38;5;28;01mNone\u001b[39;00m\n\u001b[32m 1891\u001b[39m f = \u001b[38;5;28mself\u001b[39m.handles.handle\n", + "\u001b[36mFile \u001b[39m\u001b[32m~/.local/lib/python3.12/site-packages/pandas/io/common.py:873\u001b[39m, in \u001b[36mget_handle\u001b[39m\u001b[34m(path_or_buf, mode, encoding, compression, memory_map, is_text, errors, storage_options)\u001b[39m\n\u001b[32m 868\u001b[39m \u001b[38;5;28;01melif\u001b[39;00m \u001b[38;5;28misinstance\u001b[39m(handle, \u001b[38;5;28mstr\u001b[39m):\n\u001b[32m 869\u001b[39m \u001b[38;5;66;03m# Check whether the filename is to be opened in binary mode.\u001b[39;00m\n\u001b[32m 870\u001b[39m \u001b[38;5;66;03m# Binary mode does not support 'encoding' and 'newline'.\u001b[39;00m\n\u001b[32m 871\u001b[39m \u001b[38;5;28;01mif\u001b[39;00m ioargs.encoding \u001b[38;5;129;01mand\u001b[39;00m \u001b[33m\"\u001b[39m\u001b[33mb\u001b[39m\u001b[33m\"\u001b[39m \u001b[38;5;129;01mnot\u001b[39;00m \u001b[38;5;129;01min\u001b[39;00m ioargs.mode:\n\u001b[32m 872\u001b[39m \u001b[38;5;66;03m# Encoding\u001b[39;00m\n\u001b[32m--> \u001b[39m\u001b[32m873\u001b[39m handle = \u001b[38;5;28;43mopen\u001b[39;49m\u001b[43m(\u001b[49m\n\u001b[32m 874\u001b[39m \u001b[43m \u001b[49m\u001b[43mhandle\u001b[49m\u001b[43m,\u001b[49m\n\u001b[32m 875\u001b[39m \u001b[43m \u001b[49m\u001b[43mioargs\u001b[49m\u001b[43m.\u001b[49m\u001b[43mmode\u001b[49m\u001b[43m,\u001b[49m\n\u001b[32m 876\u001b[39m \u001b[43m \u001b[49m\u001b[43mencoding\u001b[49m\u001b[43m=\u001b[49m\u001b[43mioargs\u001b[49m\u001b[43m.\u001b[49m\u001b[43mencoding\u001b[49m\u001b[43m,\u001b[49m\n\u001b[32m 877\u001b[39m \u001b[43m \u001b[49m\u001b[43merrors\u001b[49m\u001b[43m=\u001b[49m\u001b[43merrors\u001b[49m\u001b[43m,\u001b[49m\n\u001b[32m 878\u001b[39m \u001b[43m \u001b[49m\u001b[43mnewline\u001b[49m\u001b[43m=\u001b[49m\u001b[33;43m\"\u001b[39;49m\u001b[33;43m\"\u001b[39;49m\u001b[43m,\u001b[49m\n\u001b[32m 879\u001b[39m \u001b[43m \u001b[49m\u001b[43m)\u001b[49m\n\u001b[32m 880\u001b[39m \u001b[38;5;28;01melse\u001b[39;00m:\n\u001b[32m 881\u001b[39m \u001b[38;5;66;03m# Binary mode\u001b[39;00m\n\u001b[32m 882\u001b[39m handle = \u001b[38;5;28mopen\u001b[39m(handle, ioargs.mode)\n", + "\u001b[31mFileNotFoundError\u001b[39m: [Errno 2] No such file or directory: './ila_example.csv'" + ] + } + ], + "source": [ + "#enter path to csv file\n", + "path = './ila_example.csv'\n", + "savepath = '/home/cyril/Desktop/example_graph.png'\n", + "rates = [(1/10000), (1/100), (1/30), (1/25), (1/20), (1/10), (1/30), (1/40), (1/40) ,(1/100), (1/100), (1/150), (1/150), (1/200), (1/200), (1/10000)]\n", + "ila_tigger_interval = 40000\n", + "df = pd.read_csv(path)" + ] + }, + { + "cell_type": "code", + "execution_count": 4, + "id": "b6981655-142b-4371-82fc-d0be6ecf0613", + "metadata": {}, + "outputs": [ + { + "data": { + "text/plain": [ + "Text(0.5, 1.0, 'Default Parameters, Sending rate')" + ] + }, + "execution_count": 4, + "metadata": {}, + "output_type": "execute_result" + }, + { + "data": { + "image/png": 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8km2dQ4cOWStUqJD599GkSRNrYmKide3atdnWXbBggVPloysHDhzIrO4sV66cdcWKFS7X279/v/WSSy7J3O+WLVuyreNYkT1x4kQPz4gxf/78zIrNNm3aWPfv3+9yvWXLllnj4+Otkqw1atRwWS3r+Hek/68IdvWatlrN67BkyZJWSdaLLrrI49/O6dOnXT63gZSUlGRNTEzMjL1s2bLW5557zrp+/Xq3P4MnGzZssMbExGT+vbn6XVmtVuvmzZutlSpVskqyxsfHW48fP55tnaxVuf3797empqZmW+/TTz/NXKdRo0Yu97ds2bLM33dcXJx16dKl2dY5cOCAtX79+k77DEQltv6/cvjUqVPZ1lu0aFFmhXaZMmWsaWlp2db566+/rNHR0VZJ1ujoaOusWbOyrZOcnGy9/PLL3VZJ+yrrt33i4uKsP//8s8fHHD9+3OXzmnW7devWtUqylixZ0pqUlORyPV+P+Y899ljm+sOGDbOmpKS4XG/s2LGZ69188805bhcAAOQdktgAAASIP0nsO++8023yecOGDZn33X777Tluq3379pkn/K4SON4msb3l+HX0F1980eU6hSmJff78eevdd9/tlMzJ2t7FGx06dLBKstauXdvl/VmT2N9++63P+3Bn/PjxmdtdtmyZy3Uck9iO7VKyevHFF53inDZtmtt1L7vsssz19u7dm+3+Bx54IPP+JUuWePwZtmzZkpnsu/vuu7Pd72sSu1mzZplJW1cJVEcfffSRx5/X8e+oWbNmHj8oOnjwYOa6Dz/8cI5x5ocZM2a4bHVRrFgxa7t27awjRoywTp8+3Xrs2LEct9W3b1+rZFqF/P333x7X/fHHHzP39corr2S73/F1X7duXZfHP5vWrVtnruvqAwlbXJKs7733ntvtbNiwwem5CEQSu3Tp0h6fu/79+3t8fTq2UXn88cfdbufo0aPWhISEPEliv/XWW7neVlY///xz5nY/++wzl+v4csw/fPhwZqus7t2757j/m266KfMDMXcfXgEAgLzHxI4AAISAUqVKZY6PHz/udJ/jhFWPPPJIjtu69dZbJZlJ0n777bcARehe7dq1VaFCBUnSypUr83x/oWLZsmWaOXNm5mX69Ol6+eWX1aRJE33wwQeZ6z333HO5al/SoUMHSear+Vn/JrKqXr26rr32Wp/3kdO+Je9+p/fdd59X2ypfvrz69evndl3H1hu21jk2VqtVU6ZMkSS1bds2xzYd9evXV6tWrSSZifn88ccff2jt2rWSpDvuuEOlS5f2uP5NN92U2TYhp30PHz5cERHu35IXK1Ysc2yLIdj69u2rRYsWqVmzZk63nz17Vr/++qveeecd9e/fXxUrVtT111+vP//80+V2Tp06lTnBYt++fZ1albhy+eWXq2LFipJyfl7vuecexcbGetyWTdb40tLSNHfuXEmmFdAdd9zhdjuXXnqprrjiCo+x+OrWW29VYmKi2/s9xS5JM2fOlCRFRERoxIgRbrdTpkwZ3XLLLbkP1I2iRYt6fM585evxKCfTp09XamqqJOnhhx/Ocf3BgwdLki5cuKAFCxb4vX8AAJA79MQGACAEWK3WzLHFYnG6b8mSJZKkIkWKaPPmzdmSe1n9888/mePNmzerU6dOfsV24MABffrpp1qwYIE2b96skydP6uzZsy7X3b9/v1/7CidPP/20x/ujo6M1evRojRo1Ktt958+f14wZMzRz5kytX79eBw4cUFJSktv+tPv37/eY1Grfvn22vxtP1q9fr88++0wrVqzQ33//rTNnzigtLc3tvj2Ji4tz6quele0DDklq3ry5x4St47onT550um/z5s2ZyfxSpUplJuo8iYyMlCTt2rVLqampmT3ifWV7DUomkeXNvosXL65Tp07l+HrNKRlfokQJtWnTRitXrtSCBQt0zTXX6N5771WXLl0UExPjVfx5oUOHDvr999/122+/aebMmVq+fLnWrl2r5OTkzHXS09M1Y8YMfffdd/rggw80dOhQp20sX748828+NjbWq+c1Pj5eBw8ezPF5bdu2rcf7q1SpkjnO+re2YcMGnTt3TpJ5bXlKhkvSZZddpvnz53tcxxf+xH748OHMHt0NGjRwek250rVr18ze8IHStGlTFS9e3Ov1t2/frilTpmjJkiX666+/dPr0aaWkpLhcNxD/Yxxfz4cPH87x7y7r/1QAABAcJLEBAAgBjomIrMnK3bt3SzKT8vXt29en7Z44ccKvuD788EM9+OCDbpPWWZ05c8av/YWzmJgYJSQkqF69eurcubOGDh2qWrVqZVvvr7/+0nXXXedTMiSn59UxqeXJ+fPnNXz4cH388cdOH5z4s+/SpUt7TKA7JgA9JeKzrmurlLSxvQ4kad68eZo3b57HbWV14sQJVapUyafHuNq3r5OX5vQa9OZ3N27cOHXr1k2nT5/WnDlzNGfOHBUtWlQtW7ZUu3bt1K1bN3Xt2tVp0rz80rp1a7Vu3VqSmQx269atWrFihWbPnq3vvvtOGRkZmROF1q5d2ylp7/i8Tpo0SZMmTfJ6vzk9rzl9+8HT39qBAwcyxzlVh3u7ji8CFftFF12U475cHaP85e3xSJJGjx6tl156SefPn/dq/UD8j3H8u7N9c8lb/v5PBQAAuUcSGwCAEOB4Ul22bFmn+06dOpXr7dqqCXPjq6++0t133515vW3bturcubNq1qypkiVLOiVS7rzzTh09elQXLlzI9f7CzcKFC9WlSxefHnP69Gl169YtM9FUqVIlXX311WrQoIHKly+vIkWKZFYqT5s2TdOnT5ekHJ/XokWLerX/kSNH6qOPPpJkKsV79OihVq1aqUqVKoqLi1N0dLQk6ciRI7rrrru82renymp/1s3Kn9eB5N9rIS9fg9787po1a6YNGzboueee05dffqnk5GSlpKRoyZIlWrJkiV555RWVL19ejz32mEaMGOHX8+yPiIgINWzYUA0bNtTtt9+u9evX64orrsg8Njz//PP66aefMtf353lNT0/PMZbc+vfffzPHju1c3ImLi8v1vlzxJ3bHSvhgxC55fzx6/fXX9dxzz0kyP3PXrl3Vvn17VatWTfHx8U7fNLB9gBuI/zHB+p8KAAD8QxIbAIAgy8jIcOpdbatqtLG1JShdunSOvZED6YknnpBkWjJ8++236t27t9t1hw0bFrD9FuRE+HvvvZeZwL755ps1YcIEty0hli9fHtB979u3L7NXd+XKlbVw4ULVqVPH5bqbNm0K6L4DwbE9wYMPPqg333wzKPuePXu2x9dCXqlevbomTJig999/X7/99ptWrFihZcuWadGiRfr33391+PBhPfDAA9qwYYMmTpyY7/G50qRJE40dO1Y33XSTJGnx4sVKT0/P/LDE8Xl95513PPZWz0+OcXnzLRTHxHGwOSalQzn21NRUPf/885LM871gwYLMHvZZBTpGx9/vmTNnFB8fH9DtAwCAvMHEjgAABNmcOXMyvyJdvHhxNW/e3Ol+21ezT5065VQhmJd27dql7du3S5L69OnjMWl35syZHL9i7Vi1nVMl27Fjx3yINLz8+OOPkqSoqCi9++67Hnsa79q1K6D7/vnnnzP7Dz/22GNuE9h5se9AcGxRYOv5Wxj2nVVsbKw6deqkRx99VHPmzNHRo0f14YcfZiaGJ02apN9//z2oMTrq3r175jg9Pd3p9R1Kz6ujypUrZ45tx0FPvFknvzi2zNmxY0eO6+/cuTMvw3FrxYoVmf/P7rrrLrcJbCnwx6NQ/bsDAACekcQGACCI0tPT9eKLL2ZeHzJkSLa+tp07d5ZkKrZ/+OGHfInr0KFDmeOc+r3+8MMPbicktClVqlTm2HGSLFdWrFjhRYSeOX4d39vez/nB9rwmJiY6PSdZpaamatGiRXmybynn32kgJ6kLlCZNmqhkyZKSTCsXdxNResuXvxHba1AKveemSJEiuvPOO3XPPfdk3rZ06dIgRuTMlly3cayC7dixY2Y/9e+//z5f4/Lk0ksvzfzgbfny5Tn+rS1YsCA/wvJK+fLlVbVqVUnSli1bnF73rixcuDA/wsom0MejgvJ6BgAA7pHEBgAgSC5cuKB7771Xa9askWT6iD722GPZ1nOceOr555/PNpFXXnD8SrqnKsNz5845JeHdufjiizPHP//8s9v1FixYoA0bNngZpXuOibJQ/Kr/kSNHPE5QNnbs2IC3jvH2d7pz505Nnjw5oPsOhMjISN18882STLX+mDFj/NqeL38jzZs31yWXXCJJmjt3bsBbvQRCzZo1M8feTpKXG8eOHcvxQytHs2bNyhxXr17dqXVDuXLldNVVV0mS/vjjD02dOjVwgfohNjZWPXv2lGT62E+YMMHtun/++WfmNyxCxbXXXivJfPD5zjvvuF3v2LFj+vTTT/MrLCfeHo9Onjypt99+O8ft+fJ6HjBgQOaHFGPGjCnQ3/4BAKAgIYkNAEAQrFq1SpdddlnmJHsWi0WTJ092+hq7TatWrdSvXz9J0saNG3Xttdfq6NGjbrdttVq1fPlyPfTQQ7mOr379+plJgdmzZ7usjk5JSdGgQYO0cePGHLdnS1RJ0ksvveQy/k2bNjkl7P3hmNBbu3ZtQLYZCC1btpRkfkdPPvmky3WmTp2qp59+Os/2LUlvvPGGyyT53r171bt375BK/Dt64oknlJCQIEl66qmn9Pbbb3tMqCYnJ2v8+PEuk6O+/I1YLBa98sorkszvrk+fPh4/jJGkAwcOaPTo0V69PjxZt26dnnvuOR08eNDtOsnJyZoyZUrm9SZNmvi1T0++/vpr1a9fXx988EGObYQWLlyoBx54IPP6Lbfckm2dl156KbOtzh133JFjIvvEiRMaM2ZMjs+/v0aNGpVZJf7oo4+6PAYePnxY/fv3D7k+/vfee29mBfwbb7yh2bNnZ1vn7Nmzuummm/yeMDW3WrRokfn8jh8/3mXrkxMnTqhPnz6Z8wh44svruUqVKhoxYoQk8zq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GAAAIKySxgRDVrZs5rxozRlq+POf1f/3V9NG2WKTLLgtICBwWgDDSqJFUo4b5x75hQ7CjARByqMQGAABAGCOJDYSoxx4zbQLS0kxS+v77pfXrnQuGrFZz2wMPmKR3aqoUE2MeGwBRAdkKgHxTrpy0e7d0+nSwIwEQskhiGzwPAAAAYYUkNhCi6teXJk+WBg2Szp2T3n3XXGJipNKlzbnX8ePmPskktKOipIkTzWMDgMMCEGbi480yKSm4cQAIQbTNcI3nBQAAICzY3raRxAZC0I03mlYizZubF6vVaiqzDx6UDhwwY9vtzZpJy5ZJAwYEbPdUYoeQcePGady4cTpn+9QCcME2uSNJbADZ0E4EAAAAYYxKbCDEtWwprV4trVkj/fyz9Mcf0okT5r5SpUwf3O7dzXoBRhI7hAwfPlzDhw/X/v37VbVq1WCHgxBlq8T+99/gxgEAIY+JHQEAAMKKLYlNTQYQ4lq0MJd8xGdbQJihnQgAt6jEBgAAQBijEhuAO1RiA2GGJDYAeIlKbAAAgLBCEhsII/v3S4cOSWfPmvYhRYvm6e44LABhhiQ2ALeoxAYAAEAYI4kNhLikJOnpp6WqVaXq1aXWraWuXaVdu5zXmzbNTAQ5bFjAdk0lNhBm6IkNwC2S2M54HgAAAMIKSWwghP39t9Szp7Rzp/O3XV2dd7VpIw0aZNYbPFjq0MHv3XNYAMIMldgA4CPaiQAAAIQFkthAiEpNla6+WtqxQypWTHrkEem779yvX6OGqdCWpNmzAxICldhAmCle3CxJYgPIhkpsAAAAhDGS2ECIev99aft2KS5OWrpUatIk58dcdZW0YIG0YkVAQuCwAISZ0qXN8p9/ghsHAIQ8JnYEAAAIK7a3bSSxgRAzY4Y5vxo50rsEtiQ1bmyWf/8dkBA4LABhpmVL8w99xw4S2QCyoBIbAAAAYcxWic3bWSDEbNlilldc4f1jEhPN8tSpgIRAEhsIMyVLSs2amfGiRUENBQBCG5XYAAAAYYV2IkCI+vdfs7T1uPVGWppZRkcHJAQOC0AY6tLFLBcuDGoYAEINldgAAAAIYySxgRBlq6revdv7x2zaZJYVKgQkBA4LQBiyTfBKJTYAJySxnfE8AAAAhBWS2ECIsrUEWLLE+8dMmWLOydq2DUgIHBaAMNShgxQZafpi79sX7GgAAAAAAPAfSWwgRN1wgyma+ugjae/enNd/+217wnvgwICEwGEBCEMlSkjNm5sxLUUAZKISGwAAAGGMJDYQom65Rbr0Uik11fS4nT/fee4hi8VcX71auvlmadQoc1vHjtJVVwUkBA4LQJhybCmSliYdPx7UcAAg9Dgm85ncEQAAIOSRxAZCVESENHu2VKWK6Yvdq5epsLSdc3XpIsXFSW3aSNOmmfOvWrWkL78MXAgB2xKAfOU4uWOvXlKlSr711wdQAFGJDQAAgDBmeztLEhsIQdWqSevXm/YgERFScrJ50Vqt0tGjpkrb9iK+8UZp1SqpXLmA7T4qYFuC38aNG6dx48bp3LlzwQ4FYaBDBykqyiSubcnrsWOlt94KZlQAQgJJbCNrJTbPCwAAQEizVWLztg0IUaVLS59/Lr38sjR3rrRmjXTkiHThgpSYKDVtKvXuLdWtG/Bdk8QOIcOHD9fw4cO1f/9+Va1aNdjhIMQVLy61bCmtWGG/7c8/gxcPgBBAywwAAACEMdqJACHqzBnTPsSmenXpnnu8e+yiRfZ2An7gsACEsazHgA0byGEBhRrtRJzxPAAAAIQVkthAiLr6atMuxFc//2x64AYAhwUgjNkmd7Q5elTaujU4sQBASOMTPgAAgJBHEhsIUcuXS9dfL50/7/1jfvxRuuYaKSUlICFwWADCWLt2UnS0823r1gUnFgAhgEpsAAAAhDGS2ECIioyUvv9euvVW79afN0/q08dUb1eqFJAQOCwAYSwuTmrVyvm2PXuCEwsAhJysEzsCAAAgpJHEBkLUhAlmOX269J//eF53zhxTtZ2aKlWpIi1cGJAQOCwAYS5rS5Hdu4MSBoBQQCU2AAAAwhhJbCBE3XKLNGaMOef86CPpiSdcrzdrltSvn5SWJlWrZiZ1rF07ICFwWADC3H/+I/XvL91xh7lOEhsASez/RyU2AABAWLG9ZSOJDYSgkSOlp582L9RXX5XefNP5/m++kW68UTp3TqpRwySwa9UK2O45LABhrlIlado06aabzPXt24MbD4AgIlELAACAMGarxKYmAyFjzx5p1Cipfn3T07V0aallS+n116WzZwO3n/nzpb59TfuN2Fiz7NvX3O6tFSuk226T6tWTihc326lYUbrySunjj01y2V/PPScNH27OPR95xN5m5MsvTWIqPd0krhctMonsAIoK6NYABE3jxma5c6d05IhUrlxw4wEQBLQTccbzAAAAEFZoJ4KQMmeONGiQdOaM/bazZ6U1a8xl/Hhp7lz/2mVkZEh33il98onz7f/8Yy4zZ5qv3n/4ofsXhtVqqqTffTf7fYcOmcuPP0pjx5oJF6tVy328ktnPyZPSF19Id90lrVtn4jt/3jwXCxZIVav6tw8XOCwABUTp0lLDhmb866/BjQUAQg5V6gAAACGPJDZCxrp1pnfrmTOmqvmll0yyZcECadgws862bdLVV0tJSbnfz5NP2hPYTZtKU6dKq1aZZdOm5vbx46WnnnK/jVdesSew4+OlZ581Setff5UmTpQuucTct2mTiff8+dzHazN5stnWhQvS//5ntlmnjpnEMQ8S2BJJbKBAadLELGkpAhRSVGIDAAAgjJHERsgYOVJKSZGiokxC+IknpLZtpW7dzMSGr71m1tu2LXtvaG9t2ya98YYZt2ghLV8uDRhg2pUMGCAtW2Zul0z7ElfJnvR0eywxMdKSJdLo0dLll5t4hwwxCfnWrc06f/5pqrv9FRkpffWV1KmTOQ+tX19avFiqXNn/bbtBOxGgAClf3iyPHAluHAAQEpjYEQAAIKyQxEZIWLVKWrrUjG+/3SSDsxo1ylQ5b9li2nQ8+aQUHe3bft5+214V/e67UtGizvcXK2Zub9vWrPfWW9K4cc7rbNkinTplxr162asbHUVFmST8tdea6ytWSDfc4Dqmbt18+xmSk815V1SUfbK2rCwWU8HuJ5LYQAFi64N99Ghw4wAQJFRiAwAAIIyRxEZIcKxUHjrU9ToREdKtt0qPP26SyAsXSldc4f0+rFZp1iwzrl9fatPG9Xpt2piJGv/6y6z/3nvO53uOkzXWquV+fxdd5PoxWS1aZLbvbRGQbd1Nm7I/xnZfgM5PSWIDBYgtib1kidS9u/T001LnzsGNCUAQkMQ2qMQGAAAIKySxERKWLTPLuDipeXP36zkmXJYv9y2JvWuXdOBA9u24289ff5mJHnfvlmrWtN9Xp449Wbxzp/tt7NhhH9er5369Tp1C9nySJDZQgNiS2Dt3msuCBeRtgEKFFzwAAADCGElshIQtW8yydm3TJsOd+vWzP8Zbmze73o43+3FMYpcsKQ0cKH3xhfTdd9LGjdKllzo//vx56b//dV7fnUWLvAo/GEhiAwVI2bLBjgBAUNFOxBnPAwAAQFjh7SzyRFKSdOaM/XpsrLm4kpoqHTtmxlWqeN5uqVKmWjs5Wdq3z7eY9u+3j3PaT9Wq9rGr/YwZI23dKq1dK3XsaPp1t2snFS9uKrjfekvasMH02J4yRUpM9C3WEEESGyhAKlYMdgQAEKKoUgcAAAh5VGIjL5Ro2ND5hmeflUaPdr1yUpJ9XLx4zhu3JbH//de3oHzZT1ycfexqP+XLm4koP/7YVFw/+6zz/RaLdMcdJrmdU9W3O7fdZpZXXSX165e7bfiJJDZQgFStahLZBw/ab/v+e6lxYxLcQKFA6QoAAADCGEls5IUzmzerROXK9hvcVWFLphLbJiYm543btpWS4ltQvuzHMV53+/nlF+mzz6TDh7PfZ5tEMjFRev55736urCZPNsv+/X1/bIBwWAgh48aNU8OGDdWlS5dgh4IwZbFIWf98rrpKyvqhI4ACjiS2wcSOAAAAYcPx7RpJbARUfLxUooT94imJXaSIfXzuXM7bTkszy6JFfYvJl/3Y9uFuP2PHStdcI61ZYyZm/Okn6fRp87jNm6WHHpJOnJBefVXq1s33qnHJ3r+2fHnfHxsgHBZCyPDhw7V582YtCuEm6gh9Xbtmv+3UKXO8cmwBBaAAIlELAACAMGWrwpZIYiOI4uPtY2+SvcnJZulN65Hc7se2D1f72bhRevBBcy7YvbupyO7e3STrY2KkBg2k11+XPvrIrL98efZ2I96wVUfu2eP7YwOEwwJQwHTu7Pr2xESpQgXpwoX8jQdAEFCJbVCJDQAAEDZIYiMkFClin/jQcfJFV06etCeYHSdf9IbjZI457cdxMses+5k40f7iee45KTLS9TZuu02qU8eMJ03y/fxo0CDzGFtbkSDgsAAUMHXqSMOGue7Vn5Li3C8bQAFDohYAAABhiiQ2Qoat6nj7dun8effrbd1qHzdokLt9ZN2Or/vZssU+btbM83Zs9584IR05knOMjoYOlS67zPTWHj06KOeeTOwIFDAWi/mWyL59UrVq2e/fs8f5Az8ABQgTOzqjEhsAACBskMRGyOjQQVq61FRZ//671Lq16/UWL7aP27f3bR81a0qVKkkHDjhvx5UlS8yycmWpRg3n+6IcUrueEu6SlJ7u+nHeWLrU9NY+elR64QVp+nQzyeOll0qlSrmvALfp1Mm3/blAEhsooNz12t+92/djKwAAAAAAecmx5oCaDARVnz7Sf/9rxhMnuk5iZ2RIU6aYcUKC6wnKPLFYpGuvld5/31Rar1wptWmTfb2VK+2V2Ndem/3FUbOmfbx0qXTVVa73l54urVhhxiVLSqVL+xZvly7O+962zSSzvWGx5Jxg9wKfbQEFVEyM69sffdR8WOY4uS2AAoJKbAAAAIQpKrERMlq1kjp2NONPPrEnfx29+aa9lcfIkVJ0tPP9ixaZ8zKLRRoyxPV+7r/fXsF8332mB6yjlBRzu2Qqp++/P/s2eve2jx97TDpzxvW+nn3W3l+2Z8/cnTNarbm/BACV2EAh888/0pdfmg8J77472NEAyBMksQ3aiQAAAIQNktgIKWPHmq+xp6RIV1whPfGESaSkpEjTppk+rpJUt640alTu9lG3rvTww9Irr0hr1pj9PfqodNFF0o4d0quvSuvWmXUfftg+MaOjK66QunWTfvlF2rhRatLEJNVbtTKTVG7fLk2YIH3/vVk/Ls4ktH21cGHufsYAIokNFGBbtkhr10o33+z6PgAFDIlaAAAAhCmS2AgpTZuavs+DBpnq5ieeyL5O3brS3LlSfHzu9/PSS2aSxQkTTMJ6wIDs69x+u/Tii+638fXX0vXXm0Tzrl2uK7YlqWxZ6YsvpHr1fI+zc2ffHxNgHBaAAqx+femmm1zf9/XX0g03mMpsAAUMldgGldgAAABhgyQ2Qk7v3qa6+YEHTMK6WDHT/7pFC3uVdO3a/u0jIsK0LJk71/S8rlTJ9IetVMlcnzdPGj/e84uiVClpwQJp5kzpxhtNn+yiRU2Lk7JlTT/rV181vbW7d/cv3iCiEhsoBCIinN8QSGYC3G++kf791/6tEgBhjkQtAAAAwhRJbISk6tWlMWPMxRdduvh2ftazp7nklm2iyGuvzf02QhyHBaAQWLPG/TwCP/wgPfQQuS+gQGBiR2dUYgMAAIQNxyQ2b2cBZEUlNlAING0qTZwoLV5s2iNl9eab9suDD+Z/fAAAAACAws2WxLZYSGIDIW3HDmn2bGnDBunYMTPZpaeiIYvFtDvxE0lsoBCpVct1Ettm1CiS2EBYoxIbAAAAYYq3skCIO3tWGj5c+vTT7ElrqzX7izfAL2raiQCFyEcfSR07BjsKAHmOd/4G7UQAAADChq0Sm37YQAiyWqW+faUpU8yLNTFRatzYfp7VsaPUsKEUGWm/rV49qXNnqVOngITAoQEoRGrVkpYskSpUcL/Oa69JaWn5FxOAACJRCwAAgDBFEhsIYV99Jf30kxk/+6x06JBJaNssXiz98Yd08qSZBDMuTjpxQnrhBWnhwoCEwKEBKITq13d/36OPSs8/n3+xAMgDVGIbVGIDAACEDZLYQAj74guzbNvWJLEjIlyfd8bFSfffb3pgJyVJ110nHTgQkBA4NACF0MSJUvny7u9//XVp7978iwdAgJCoBQAAQJgiiQ2EsDVrTNJ62DDv1m/ZUvrPf8zEj++8E5AQODQAhVCNGtK+fe7vT0+XqlenrQgQdpgNxxmV2AAAAGGDJDYQwo4dM8tatey3RUfbxykp2R9z9dVm+d13AQmBQwNQSEVHS/PmSaVKuV9n+3YpNZXcDwAAAAAgb5HEBkJYVJRZxsfbb3McHzqU/TElS5qlpypKH3BoAAqxq66Sjh93f//cuWbC2Xvvzb+YAPiBSmwAAACEKZLYQAirVMksjx6131ahglS0qBmvXZv9MX//bZbnzwckBA4NQCFnsUh33+36vkcflc6elf73v/yNCYCfSGIbtBMBAAAIG7YkNm9lgRDUuLFZ/vGH/TaLRWrd2oyzJo7S06UxY8y4Tp2AhEASG4Def196+GHP69SuLW3YkD/xAMglErUAAAAIU7a3slRiAyGoWzfzIv3+e+fbb7vN3L5okdSlizRunPTaa1KrVvbJIG+8MSAhcGgAIMm0DClWzP39O3ZIN92Uf/EA8APlKwaV2AAAAGGDdiJACOvb15xfLVwo7dxpv33QIKlHD3O+tXSpNGKE9Pjj0saN5v4mTaQHHwxICBwaAEiSqlWTjhzxvM7u3fkSCoDcIlELAACAMEUSGwhhFSqYFiGpqVKtWs73ffut9OSTUvny5pzUajWTOg4fbpLeRYoEJAQODSFk3Lhxatiwobp06RLsUFBIxcWZD9DcOXvWfDPk1lsD1pcfQCAxsaMzKrEBAADCBklsIMRFREiRkdlvj42VXnhBOnBAOnZMOnRIOn5cevddqUSJwO0+YFuC34YPH67Nmzdr0aJFwQ4FhdjUqdJHH7m//957pU8/NR+0AQhRJLEBAAAQZkhiAwVA6dJSuXJ5ck7q1aEhMjLvL1FRAf/ZAORCQoJ0xx05r/fPP3keCgBfUW3sjGQ+AABA2CCJDcATrw4NtnYmeX0BEBosFumzzzyvk5wsPfKI56ptAEFC8jY73mgAAACENJLYADzxuv7ZYpHuvttUhAfSkSPS++8HdpsA/HfzzaaF0ciRru//4Qcz8axkKrd5owGEABK1AAAACFO2JDb1GEAIO3ZM+vxzkxDauVNKSpIuXPD8GItF2rHD71371MRj+HCpYUO/9+lk0yaS2ECoGjHC9Oe/++7s99kS2JL5MKpChfyLC0AOeOefHQl+AACAkGZ7u0aBFBCipk6V/vMfk7iWvD/HCtD5KZ2oAXg0cKD02mvmAzZ3tm+XVq6U2reXypbNv9gAZEGiFgAAAGGKdiJACPvlF2nQIPs5Z/Xq0qWXmonV8ulF61USu1MnkzSPiwt8AHFx9u0DCD0lSpgktadj0kMPSb/9Zl7Hp09L8fH5Fx8AB7Y3FPxTtbNYmHwDAAAgDJDEBkLYK6+Yc6qEBNNO5Kqr8j0Er5LYixblXQA1auTt9gH4z2KRJkyQbrvN9f2//WaWVqvUoYO0YUP+xQbABZLYAAAACDMksYEQtnq1Oc987rmgJLAliUMDAK8MHSp9+WXOubGNG/MnHgAuUG2cHQl9AACAsEASGwhhthdo+/ZBC4FDAwCv9etn79/vyfnzeR8LAA9I3GZHgh8AACCkkcQGQthFF5llcnLQQvDr0LBkibn8/bf3jzl71v44AOEnLk664QbP6xw+nD+xAMiCRC0AAADCFElsIIQNGGDON3/4IWgh+HVo6NJF6tpVatTI9Mv1xq5d5nHduvmzZwDBNHWq1KKF+/u//VaqVEkqUkSaPz//4gLw/6jEtrM9FyT4AQAAQpotic1bWSAE3XOP1LCh9Pbb0po1QQkhIJ9vnTsnDRsmPfig9+eInEsC4Ssqynyb4ttvXd9/333SwYNSWprUs6c0a1b+xgcUWvxzBQAAQJiyvZWlEhsIQcWLS/PmSfXrS506SU8+aSZFS03NtxACcmioWtUcbMaOla6+WjpzJhBbBRDKihb1fkLaPn2kr7/O03AASPZ3/pSv2FGJDQAAEBZoJwKEuGrVpMmTpfh46ZVXpKZNTc/ZyEjPl6iogOw+IIeGb74xE77ZWqO0bSvt2BGILQMIZbGxpkWQN/r1y9tYADggiQ0AAIAwQxIbCHFjx0pNmkjHjpkksC+XAAhIKrxYMWn6dNMa5fnnpa1bpVatpK++ovc1UNDVqGFai3TqlPO66elSdHSehwQUXlQbZ0dCHwAAICyQxAZC2Lx50gMPmHFEhNSxo9S4sZSQkG8v2sDUc/+/Z581ieyhQ6WTJ6UePUy/73vuCeReAISajh2l5cul//zHtERyZ/9+qWbN/IsLKLRI3GZHgh8AACCkkcQGQtjrr5tl5comod2oUb6HEPBDQ79+piqzShXp/Hkzwds990gXLgR6TwBCSbt20gsveF5nz578iQUotEjUAgAAIEyRxAZC2MaNpljq+eeDksCW8iCJLUnNmkm//Sa1bGnOpz/8ULrySlOdDaDg6tlTuvhi9/f//Xf+xQIUSkzsmB0TOwIAAIQFkthACLNVJzdpErQQ8uzQULGiqcgeMMCcNy5cKLVuLW3enFd7BBBsUVHShg3mte7KnXdKM2bkb0wAAAAAgNBnS2JTjwGEoDp1zDKIFcp5+vlWbKz0xRf2FgM7dkg335yXewQQbJGR0sqVpj++TUKCfXz99dL775vx+fMURwIBRSV2dlRiAwAAhAUqsYEQNnCgOaeaOTNoIeTLoeHJJ6Wvv5aKFaM3NlBYrF9v+mRHRpre+I7uuUd65BGpRg3puuuCER1QwJHEBgAAQJix1RyQxAZC0H33Sa1amZ7Rc+YEJYQofx58663mPLlUqZzX7dtXWrpUuuYaaf9+f/YKIBxER5uWQmfPSj//nP1+28S2//wj3XijNH06eTfAb1QbZ8eBBQAAICxQiQ2EsIMHpY8/Nn1i+/aV+vc3l7p1TdVyTqpV8zsEv5LYkyb5tn6TJtLevf7sEUA4iYyU4uOd24m48tVX5lsaX39NvgkICF5I2ZHgBwAACGkksYEQVqOGc6vGadPMxRsWi+kn6ycODQDyXN26Oa8zY4ZpP0LLIcAPJGoBAAAQpkhiAyHOarWfc9rG3l4CwK9KbADwRuXK0uLFUufOntdbuVL65hvTXgRALjCxY3ZM7AgAABAWbEls3soCIWjixGBHQBIbQP7o1En65RepWzfP6x0+nD/xAAUa7/wBAAAQZmzdBqLIVAGhZ/DgYEfgfTuRyMjAXjgoAYVP167Shg2e11m5koJJINd48WRHJTYAAEBYSE83y+jo4MYBIDR5ncT2tdVJPrVDARBmLr1UWrvW/f1ffCFNnZp/8QAFEpXYAAAACDMksQF44nU9dKdOns+Jk5OlNWvMOp06BSI0AAVV06bS+vVSkyau77/5ZikhQerZMx+DAgoCPiHOjoQ+AABAWCCJDcATr5PYixZ5vn/TJqlRIzNeuNCPiAqxcePGady4cTp37lywQwHyXOPG0rJlUocOru+/+mrpq6+kG27I37iAAoHEbXYk+AEAAEKaLRVCEhuAK163E0HeGz58uDZv3qxFOX1iABQQ7dubyR7d6dcv/2IBCgQStQAAAAhTVGID8IQkNoCg6tpVWrAg2FEABYQtiU0lth0TOwIAAIQFWxI7Jia4cQAITSSxAQRdt27S8uXBjgIoQEhiAwAAIMxQiQ3AE5LYAEJCu3amR7YjPoEHfES1cXZUYgMAAIQFktgAPCGJDSBktG8vzZ1rv37hgpSREbx4gLBFJTYAAADCDElsAJ6QxAYQUnr2lObPN+MLF6QTJ4IbDxBWqDbOjoQ+AABAWCCJDcATktgAQk6PHlLx4mZ86lRQQwHCE4nb7EjwAwAAhDSS2AA8IYkNICQlJJglSWzAByRqAQAAEKZIYgPwJMrbFadM8Xz/P/94v67Nrbd6u3cAhU1CgrR/P0lswCe2JDaV2HZM7AgAABAWSGIDIeL55wO/zWee8XsTXiexhwzJ+ZzYdv/QoTlvz2IhiQ3AvZIlzfL06eDGAYQlktgAAAAIMySxgRAxenTgzynzM4ktUcQEIP/QTgTIBf5RZ0clNgAAQFggiQ2EkECePwUoIe51EnvixIDsDwC8QhIb8AOV2AAAAAgzJLGBELFrV+4fa7VK33wjvfqqdPx4QJPhXiexBw8O2D4BIEe2JDbtRAAfUG2cHQl9AACAsEASGwgR1avn7nFz5kjPPitt2GCuW61S5crSk08GJCyf2okAQH6x9cSmEhvIBRK32ZHgBwAACGkksYEw9cMPpuf1mjXmutUqlS8vPf64dNddUmxsQHZDEhtASCpRwiypxAZ8YEvUksQGAABAmDl3zixJYgNh4pdfTPJ6xQpz3WqVypSRHn1UuuceqWjRgO6OJDaAkGQ71qWlBTcOIKxQbZwdEzsCAACEBSqxgTCxbJn09NPSkiXmutUqlSolPfSQNGKEFBeXJ7v1Kom9d69ZVq4sRUYGNoALF6R//jHjatUCu20A4atIEbNMTQ1uHEBYohIbAAAAYYYkNhDifvvNJK8XLDDXrVbTC/aBB8wlPj5Pd+9VErtGDSkiQtq4UWrYMLABbN0qNWpktn/+fGC3DSB8kcQGcoFq4+yoxAYAAAgLtiR2TExw4wCQxdq1pm3I/PnmutUqFS9uqq4fekhKSMiXMLxuJ5LX536cWwJwRBIb8AOV2AAAAAgzVGIDIeaPP0zyevZsc91qlYoVk4YPlx55REpMzNdwfOqJzTkxgPxim7yWntiAD/hEODvevAAAAIQFkthAiNiyRRo9WvrmG3OOabWaSsO77pIef1wqVy4oYfmUxL7iisAfTGwHKQBwRCU24AcSt9mR4AcAAAhpJLGBENGokT15HRsr3XGH9MQTUsWKQQ3Lp3YitgkYASCvkcQGcsGWqCWJDQAAgDBDEhsIERkZ5pzSYjFJ7LlzzSW3LBZpxw6/w/IqiT14sN/7AQCfkMQGcoFq4+yY2BEAACAskMQGQozVKp05Yy7+CFCRlVdJ7IkTA7IvAPAaSWzAD1RiAwAAIMzYzv1s54IAgqRTp5A8p/SpJzYA5BeS2EAuUG2cHZXYAAAAIc9qlVJSzLho0eDGAhR6ixYFOwKXIoIdAAC4EhtrlmlpwY0DCEsh+Kk5AAAA4I7jeR9JbACukMQGEJIcK7EpoAS8xIslOxL6AAAAIc9WhS2RxAbgGklsACHJlsS2Wu0TfADwEonb7EjwAwAAhCxbEjsigokdAbhGEhtASHKczIO+2ICXbIlaktgAAAAII479sHkrC4SAyZOl0qXN5bPPfHvsZ5+ZxyUmSl9+GbCQSGIDCEm2ntgSSWzAa1QbZ8fEjgAAACGPSR2BEHL+vPTkk9Lp09KVV0qDBvn2+EGDzONOnpQee0zKyAhIWCSxAYQki8WeyCaJDfiI8hUAAACEEZLYCFl79kijRkn160txcabCuGVL6fXXpbNnA7ef+fOlvn2lKlVMMqRKFXN9/nzftpOeLk2aJF19tVStmtlWmTJSo0bSHXdIX32V8zbmzpUOHJBiYqRXX83Vj6PXXjP73rNHmjcvd9vIIiogWwGAPBAba2apdpypGoAHVBtnRyU2AABAyCOJjZA0Z46pKj5zxn7b2bPSmjXmMn68SfjWrp37fWRkSHfeKX3yifPt//xjLjNnmuTzhx+apvGebNwo3Xyz9OefzrcfP24uf/4pff211K+f5+3Mnm2WtkR4blStKvXuLX3zjTRrltSrV+6244BKbAAhy/YGJjk5uHEAYYdKbAAAAIQRktgIOevWSf37mwR28eLSSy9Jv/4qLVggDRtm1tm2zSR6k5Jyv58nn7QnsJs2laZOlVatMsumTc3t48dLTz3leTsbN0pdu5pEdZEi0r33mmT0779LK1ZIU6ZIN90klSiRc0yrV5tzyp49c/9zSdJVV5liolWr/NvO/6MSG0DISkiQDh82bZgAeIFq4+xI6AMAAIQ8ktgIOSNHmj/MqCjpxx+ltm3t93XrJtWpIz3yiElkv/mmNHq07/vYtk164w0zbtFCWrLE/iJo2VK65hqpc2dT9f3669Jtt7mu+k5NNdXVJ06YyumffzbxOWrTRrrlFuncuZzj+ucfs7zoIt9/Jke1apnl/v3+bef/UYkNIGSVLGmWJLEBH5G4zY4EPwAAQMgiiY2QsmqVtHSpGd9+u3MC22bUKKlBAzMeO9b0ovbV22+bSRQl6d13s78AihUzt0tmvbfecr2dN94wCfGICOnLL7MnsB3FxOQcl62y3JaUyS3b4//917/t/L+AJbEzMkxF/Ysvmor1226TDh50XufcOdM6hv62ALyRkGCWp04FMwogjNgStSSxAQAAEEZIYiOkzJxpHw8d6nqdiAjp1lvN+NQpaeFC3/ZhtZpe0ZKZNLJNG9frtWkj1atnxrNmZS/OuXBB+uADM+7eXWrd2rc4XClVyiyPH/dvOydOmKUtueOngCSxv/vOVLNfcYX07LPS++9LkydLJ086rzd+vBQfL5UrR49bADkjiQ34iGrj7JjYEQAAIOSRxEZIWbbMLOPipObN3a/XubN9vHy5b/vYtUs6cCD7djzt559/pN27ne/79Vd7+49rrrHfnpoq7dhh7rtwwbfYypc3y/XrfXtcVrbH27bnJ797Yn/8sXT33fZzwzJlpGPHXBeB3XGH6UN++rT07bdmgk8AcMeWxKadCOAjKrEBAEABcfKkKYg7e1a6/37p++/NnGODB5tvxc+ebYoUe/a0F9ONGGHyOosXmxawUVHS55+bb4fffrs0d67JA113nSk0XLrUdAVo1UqaPt0UWA4fLs2bZ+Z2GzLEFOJ9/bUpimzb1sQUHW1i+uEHadMmM2eaxWLmT2vXzlzGjzfbu+ceUwC4YYPJjZw6JX31lRQZaQo9v/xSOnLE5En+/FNau9bsp2pVUxRavLjZxhdfmLzU3Xeb5bx5Zu60OnXMvsqUMevNmCHt3Gn2deyY2X6PHqbg8+OPTU5p0CBp2jTzXAwfLv39t3k+S5QwP8vnn5s57YYONa16t26VrrzSxDRpkilQHDJEmjjRxH7ffdLKlWbdG28025kyxfx+Bg8289Tt3Wu+vb95s4m9Xz8T8/PPm983SWyEhC1bzLJ2bXMAcad+/eyP8dbmza63481+ata0X1+50j5u1Mi8kB97TJozx97ipGRJk+B+9lnv+ly3a2cORDNmmLYpufX11+ag2K5d7rfhyOqHbdus1uhoqzUiwmq97DKrdcsWc7vFYm7btCn7Y+64w9x/yy3+7Llg27dvn1WSdd++fcEOBQiqhx+2WiWr9cEHgx0JECZKlDAvmm3bgh1J6KhSxTwna9YEOxIAAOCjPXus1rJlzb9yyf5vXTK3R0ebcXS01TpwoP2+QYPs46uuct5GIC4Wi31ctap93KyZ1VqsmBknJlqtPXva7xs82D6+/nr7eoG4REZarRUquI6pfXv7+OKLTYy267fcYh8PHGi1RkV5v7+c1ilRwmotXtx+/cor7eObbrKPO3WyWmvUsF+///5g/9WhIMnMr23ebLWePm2/pKa6f1BKiv0P8uqrc95JXJxZt00b34J7/337fr76yvO6X31lX/eDD5zvGzLEft+HH9rjcXWJj7daf/op59hmz7Ynd2fM8O3nsvnmG/s25szJ3Tay8KudyFtvmb7iF19sPkHL6YMDSerY0SzXrfNnzwAKA9qJALlEJTYAACgAJk+Wjh61X9+/3z4+etReZJiebqp8bT77zD6eP995G4Hg2KVs3z77eO1aUzEumQrvefPs902ebB9/8419vUC4cEE6dMh1TI4dDjZtMjHafPqpfTx1qn1+OW/2l5MzZ5zncvvhB/v4iy/s4yVLTCV4XJz09NPSI494FwPgixING5pqZNvlv/91v7JtUkPJfAUiJ3FxZunr5IW+7Me2D1f7sfWdlqSRI83XRh54wFRkp6WZr2w8/LA5R0xKMl9/2LvX8/569ZIuucQc7AYPtrdX8dbSpeZxFovZTq9evj3eDb+S2L/8YuK5/37vJreUTCW+5HxQBQBXaCcC+IiJHbPjuQAAIGx9951ZVqpkvy3CIYsRHe39thy34TiOjDRtMXJaLz7eOc/kLqYSJXIXU8WK9nHJks5tNdzFVLmy8/Yc4wj08+Q49hRH1vW8fSs2fLhpKeL4PACBcmbzZpNYsF0ef9z9yqmp9rE3yc7YWLO0NXb3li/7se3D1X4cJx1MTTUvpDFjTAI2JkaqVUt67TXppZfMOqdOeU7iS+aF++675uCRnCx17WoS47t2eX7czp0mSdytm3lcdLT03nueH+MDv5LYtk9BGzf2/jG2Dw8C+akjgIKpZEmzpBIbgN+Y2BEAgLCzZ49Zdu1qv23gQPu4USPTC9omPt79thy34TiuWNFebJf1vi5d7OOGDaXERNfrOcbUubPnONzF1K2bfXzJJfZzIU+xt2rlvL0bbnAdU79+3sXjaV/t2zuv16aNfez4PDk+pkIF58fdfLP7/TZt6n2MgM/i480nTLaLY1I4qyJF7ONz53LedlqaWfra0N2X/dj24Wo/jtspU0Z69FHX23j4YfOilEyT/JzOjzp3lj74wCS0MzKkd94xB9yLL5ZuvVV66CHTY/uhh8zkAxdfLNWta5LfFy6YT9I+/NDekiMA/Epi2z5R8yUhffy4WToekAHAFdqJAD6iEhsAABQQGRlmQkLJOVHtOC5d2jkP8+CD9nHz5s7bc3ycY9I6Jsa5wtrdvsqUcW6jUauW6/XKlnWuxs4ahyPHOLJuw7G1R40a7tdzZDt/yrqe4xxwktSsmet4YmLMpI2+7svx53CcMy462jmh77i9rM9L1u0DQeP4R+tNixBbJbQ3rUdyux/Hauus+3HcTpcu7qu6o6Kkyy4z4xMnTNV0ToYONb2Aypc3B9uMDDPD6+efmx7TL75oll98YW7PyDDrVagg/fijaSkSQH4lsW1fGfHm57axtVFxPOADgCsksQEfUW2cnS2hz3MDAEBIS0kxbVPfeMN8G712bXvS2DFJ6jguUsS5gNExEWrL1bh6nGPLipgY98lpx8cUK+a8L8eqbMf1ypZ1Lpp0rFIuX94+johwv6/4eOd9lSrlfl+OHIsFHddzbJcimQp2VzGVLes+OZ11X46JesfktK3QUzLPreNbMMcEd9bfD0lshIwiRewvcMdG/K6cPGlPMDt+AuSNKlXs45z249iTOet+HK/nFIPj/d5OFnDZZaav9jvvmE/ALBbX00ZaLOb+d9816zt+vSRAovx5cJcu0rZtZoICb5Lrp0/bK9Hz4GcJe+PGjdO4ceN0zpuvKwCFAD2xgVyiEhsAAISZjz6S5s41l6wcE62O/ZdjYuyTO0rOCdis1cbuErLR0c7bcLzPsQI663ruqp4TEpyLcBxjr1NHOnzYjBMTnZPTjgntrPtyTE5nrUR3FBnper2cKrZtMZUt635fZcrILW+fW8dkesOGpjDUVnFOEhshpWFDMznh9u3mjzTKTfp061b7uEED3/fhaju+7ufii+3jnGZddbzf3c/kStGi0r33mktSkvTHH6bVRlKS+dQtMdF8OuZtL6Vc8qsS+667zHny4sXSpEme1z1+XOrTx8yYGxUl3X23P3sumIYPH67Nmzdr0aJFwQ4FCAmOPbEpogS8wAslOyqxAQAIC54KER2Trp6SpI7rXXKJ8zYcH+ftNjyt59iGNmsLDcdWIO6S3YmJzvc5Jruz7ssx1+S4jaxtfR0f45jsd/w5SpZ0H1PWRLLjfVnb8DruK2s1t42n57ZGDdN5wMZTkhzIdx06mGVysvT77+7XW7zYPs7aOD4nNWvaZ0J13I4rS5aYZeXKzp+uSVKnTvZxTq0yduywj7PODOut+HipXTupd2/pppvMsl27PE9gS34msZs2lUaONOeFt98u9e9veoPb/PqraYsyfLj5ZG7JEnMu+fTTUvXq/oYOoKCzvck5f57JYAGfUIkNAADCjOP7/SJFnKt24+LsY8ckadZKbEdZ8zyOFcaOFdBZt+GYnPa0L8exY0V01na07iqbixY1SV53+3JMhLtLBGfdl7vqbcfnLyHBfUxly3q3r6zPheP2HNuMZF3PMceVNYnt+FwAQdenj308caLrdTIypClTzDghwXlWU29YLNK115rx1q3SypWu11u50l6Jfe212c/1ata0z4y6cKH7r7InJUk//2zGF13k3FcpTPiVxJakN9+U/vMfk8j++mszA67t+bzrLjNB5QcfmOfQajVJ76ee8nevAAqDuDj7V+JoKQJ4gYkds+O5AAAgLDjOW5aQYP/2du3azlW6jgnjrl2lG28042bNpGrV7PfFxdlbzrZq5ZxorVDB3vK2Vy/p6qvttzsmzx2TuJ07SwMGmHGbNlK9evb7HN9uNG0qXXGFGffr51zsWLeufVynjnMOyXGuto4dTYGjbezYLcBxX5deai/+HDTIxOX489tUrWpvV3LTTc6teFu0sI+rV3ful+24r4svllq2tO/LsejUMXFdqZL9ObzmGumqq8y4bFnn32PlyvbJHX1tJQzkuVatzItPkj75RFqxIvs6b74pbdlixiNHZv8kZtEi8yKyWKQhQ1zv5/777UmP++4zkwM4Skkxt0vmKxn33+96O489ZpbJye7XefBB6cwZM86pPcaZM/Z1/fHvv9Ls2eYSAH71xJbM72LcOPMhxSuvmAp4x0/TbOu0bWuS17YDGADkxGIxbxyPHzctRWzftAEAn9FOBACAkGW1Sj/8YL8eHS09+aR5/9+jh0mAzp1rJleMijJFicuXm7m5brjBJEP79DFtLb780l6FPWeOeVy/fuZxv/wipaaaZOqaNdJPP5ltZGSYpOqVV5p9zpljErMRESZHtWKF/VvzbdtKffuaRO306fbk8O+/mznDOnSQPvtM+uYbU+RXooTJgaWlmaTu0qXmcsstJpk8a5ZJzFss0qZN0qpV5me64grTJeC668zPP3WqPQm+erXpCtC6tTRjhvTtt2ZfxYubn69NG3vr1zNnzH4WLZLmzzc/ry2PU7So1L27NG+e9Oef0m23meT+55/b2/WuWiXt3m0+JJgzR5o50zwXcXGmvW67diYHt3ChqaYvX9485scfpVtvNduoUME8t2XLSt99Z+KMirI/T7165fmfGOC7sWPNpzUpKeYF+cQT5pOzlBRp2jTTyF8yL8xRo3K3j7p1pYcfNgnVNWvM/h591FRK79ghvfqqtG6dWffhh52/OuHoxhvNhIXz5pl+zwcPmorjatXMpJAffmjuk8wnbffe6zmuhARzANy40bl3t82BAybJa7GYA5w7e/aYg3NEhPPXS3LJYrUG9qwuKck8v0eOmANaYqLUpAn9jXyxf/9+Va1aVfv27VMVx49IgULoootMW6fly80bJAAeFC1qzlz27HEuRSrMatY0Z14rV5ozPQAAEFL++sskd7dts99Wq5Zz61YAyA2/82tz5pivHrirSq5b13xS5ji7qc2iRfYWI4MHu59MMCNDGjZMmjDBfRy3326S5hEeGmr8+690/fXmEyR3WrY0VdEVKrhfRzL7sVjMBI6uktibNpmvbVgsnieT9HY9L/ldiZ1VfLxzT3EA8IftK3yOM3wDcINq4+yY2BEAgJD29tvOCWyJ/sgAQkTv3qYaeexYk6zev980e69d23zF4957zVdE/BERYaqZr7/eJKpXr5aOHTPVwC1bml7N3rS1KF5c+v578xWRyZOl9evN19oTEkx18cCB5usRtvYlYcivJPbzz5vlPfd4X2l98qT07rtm/Mwz/uwdQGFgS2LTExvwAX2gAQBAGLBaTXsKycylZWvTmnXCQgAImurVpTFjzMUXXbr4VkjTs6e5+MNiMc37bQ38Cxi/JnYcPVp67jnTOsRbJ07YHwcAObFNwEIlNuAFqo2zoxIbAICQ9e+/0qFDZnzzzfbbqcQGAGTlVxIbAPIa7USAXKASGwAAhIGjR82yaFHzTfjhw831//43eDEBAEJTviex09PNkk9WAXiDdiKAD2zVxiSx7XguAAAIWbYkdtmyZvnuu9Lhw9IVVwQvJgBAaMr3JPb69WZp+ycFAJ5QiQ0gIGgnAgBAyMmaxLZYpHLlghcPACB0+TSx45Qprm+fNUtas8bzY9PSpB07pAkTzD+mli192TOAwoqe2IAPqMQGAABh5MEHzZIiNwBATnxKYg8Zkv282GqVnnrK+21YrVJEhDRypC97BlBYUYkN+IBq4+yY2BEAgJC0d6/0999mfPx4cGMBALgQYsVRPiWxJdfngN6eF8bEmArsxx+XOnf2dc8ACiN6YgO5EGJvNgAAALLavds+rlcvaGEAANy55BL399nOOSMj8ycW+ZjE3rXLPrZapVq1TMw//CDVqeP+cRaLVKSIlJiYrz8bgAKAdiKAD6g2zo5KbAAAQtK+ffbxf/8bvDgAAG6E2DmUT0ns6tVd316pkvv7AMAftBMBcoFKbAAAEOJsSexbbpGqVAluLAAAB506heQ5pc/tRBxlZAQqDABwjXYigA+Y2DE7ngsAAEKK1Sq99ZZpMypJ1aoFNx4AQBaLFgU7Apcigh0AAHhiS2KnpEhpaUENBUA4C7GvwgEAUFj99JM0apT9eps2wYsFABA+SGIDCGnx8fYx1dhADqjEBgAAIW76dLPs2VP6+2+pV6/gxgMACA9+tRNxtGOHNHu2tGGDdOyYqZr0VPRksUgLFgRq7wAKqshIqUQJ6cwZk8QuVy7YEQEIK0zsCABASFm61CxHjJBq1w5uLACA8OF3EvvsWWn4cOnTT7OfH1qt2YvBKBID4KuEBJPEZnJHwEv8kwUAACHq8GGzrFEjqGEAAMKMX0lsq1Xq21f6+WczLlPGzCq8fr05f+7YUTpxQvrrL+n8eXNbvXpShQoBih5AoVCypFmSxAY8cPwkmSS2HZXYAACEjLQ0U5wiSWXLBjcWAEB48asn9ldfmUkZJOnZZ6VDh6QpU+z3L14s/fGHdPKkNGaMFBdnktovvCAtXOjPngEUJrbJHUliAwAAAOHr2DGzjIy0v8cHAMAbfiWxv/jCLNu2NUnsiAjXxV9xcdL995se2ElJ0nXXSQcO+LNnAIWJ7Q0uEzsCHlCJ7RrPBQAAIePoUbMsU8bkDwAA8JZf/zbWrDHnhsOGebd+y5bSf/5jPn195x1/9gygMKESG/AC7TI84/kBACDobElsWokAAHzlVxLb9lWgWrXst0VH28cpKdkfc/XVZvndd/7sGUBhQk9swEdUHwMAgBB0991mSRIbAOArv5LYUf8/LWR8vP02x/GhQ9kfY0tG7dvnz54BFCa0EwG8QKWxa0zsCABASDh+XNq504ybNAlqKACAMBTlz4MrVZJ27LB/JUiSKlSQihaVUlOltWulmjWdH/P332Z5/rw/ewZQmNBOBPARldgAgAJg3z7p00+liy+WeveWJkyQVqyQbrlFKl5cmjVLqldPGjDAjDdulEaNkrZvl6ZMkYoVk554Qpo8WTp4ULrnHrPNr76SrrlGatrUrLdunXTnndK5c9L8+VLz5tKVV0rjxpnbHn1UWr3afJt46FCpdGlp7FjzzeSnn5aWLjXbuP568y3lTz81+x461MQ1f750+eVmu9Ommfvuv1/67DNpyxbpvvvMt5gnTDBzSD37rDR3rrlv0CApJkb65BPTnrN3bxP/zp3Sww9Lmzeb+ypVku69V5o4UTpxwmz/0CGzvx49pPr1pUmTzDbvv9/MUbVwodSpk9S5s1nv8GHpoYekJUukL7+UGjSQbrrJPO7sWXPf4sXmcYMHm2rqTz81+x44UJo61cyDdd11Uo0aJs4KFcxz+/335ueUTL7gjTeC9VcFAAhXfiWxGzc2Sew//jD/lCVz3ty6tfnn9r//mX/kNunp0pgxZlynjj97BlCY0E4E8AITO7pGJTYAhKVdu+xtK8uUMQna0aPN9cmTzfLCBXOYnzFD+vZbc9vGjdLMmfbtvPWWKbCSpOnTTYJbkmbPlooUMeeykknGnjtnf1yjRvb7NmyQvv7ajA8cMInj1avN9YkT7dv/4QfzzUFbtfH8+fa4PvnEFGbY3s+OH28SyraYFy60t+P8+GP7NqdMMcnyc+dMMvuKK+ytOePipCeftK/78ssm2Wzb5qxZ9p81Kcke16efSmlpZvzKK+aDgK1bzfXVq83zafPss/ZvQ06bZl/v11/N+MQJ01L06FGTHJdMMr5IEXtcCxbYnz9JuusuJnUEgAJrxw7zj6tGDal8+YBu2mK15v6s7v33peHDpe7dpR9/tN/+2WfSrbeaNxQdO0r9+knJyeaT2Q0bzO0vvGA+FUd2+/fvV9WqVbVv3z5VqVIl2OEAQff11+Y40qGDqXQB4EJ6ujm7laSTJ+1fYSjsLrlE2rTJnEF36xbsaAAAXnrxRVPlbBMT45xkRvi5/XapVSupf397kQoA5CXyawF05Ij9E8mbb85+IN++3Rzg16831y0W6dprzae2pUoFJAS/Pv/s29fEtHCh/VNdyXzlqUcPU/S0dKk0YoT0+OPm02DJ9L968EF/9gygMKEnNuAFKrFd47kAgLBkqza2OXfOtBCxiYoyFcDu2Kq4JdO+w52LLrKP4+Kc7yta1P3jHNf1tP2s7TWz7sNdLI7bdPy5c4rF2+17yifExkoVK7repqfnpEQJ5+uO65YuLX3wgWktQgIbAMLQjBnma1Fjx2Y/kKelSVddZRLYVqu5ZGSYr0Zde23AQvAriV2hgin8Sk11fpMgma9NPfmkqRy3xV+ypKncXrjQfL0IALxhS2L/8Ye0bVtQQwFCF+0yPOP5AYCQtXOn+TbvhQvSqlWmaOu337Kvd9119nHduqblhyuRkabFpc0NN9jHWROtN95oHzdvLpUrZ7/er5/7mB3bZjpuP6vGjZ2v9+5tHzvmACIinH8+x202by5Vq+Z6++XKmW8ruoorK8f1unRxTk47Pi8dOkiVK7vepqfnpE8f+zg62nwr26Z7d/PBAwAgTP34oykQ6ts3+32TJpk2IpKZdGLsWPMPz2qVli83/bwCwO9OVBER5k1CVrGxpmXIgQOmFcqhQ2Y24nffzf7GAQA8qVHDPp4yJWhhAOGD6mMAQBipU8dM1njxxSb5PGyYub1GDeeKYMd5leLinDtntW1rH5cp41xp7Pi4Zs2c9+2YVC5b1hRp2Tgmjtu1yx6zq7FkJmB03Kaj0qVdx9y0qfP+HLdZtqz7nzXrfY6Pyxpz7drOj4uPd73NTp2ci87c/azx8eZ3ZuOY+I6JcY6rUycBAMLZX3+ZZZs22e/74guz7NbNVF/fd5+ZmKF7d5PInjYtICH4lcTeu9dcTpzwvF7p0uYTYs6pAeRGmTL2k5k9e4IbCxCyqDR2jYkdASDkZWSYpe382KZZM+dEqGNhQ3S0cyXzZZfZx+XKOd/nKeHsmISNj3dOYjsmwh23n3U7ji1DSpaUHNuuOlZ2S84/T4sW9nHWnzVrstixdYpjLGXLOt/n+LiOHZ0LzrImxm2TQErOFePNm7tP5jtuo0EDKTHReZs20dHOP0/z5gIAhLOjR80ya2/xlBRp5Upz3nXnnc733XabWa5dG5AQ/Epi16hh/mEHKKEOAG7Z5mMjiQ14gU+NAQBhIiXF/X01azono7MmSdPS7NcdW4uULevcusJdwlly7jcdHe08eaTjvps0sY+jopzP4R3jKlXKfcyetlmzpnPS17FdZ0yMdOqU/Xr16s7bd4zZMa5atdwn8xMSpDNn7NcdK8Rr1nTepru4PP2sMTHOfb2zPu8AgDBj+0cUkSWVvHKl+eTTYjGV145sB/8jRwISgl9JbNtEDY5flwKAvGCrANm7N7hxACGLiR1doxIbAELarl3O1596yj6uVs05gZo1SXrypOv7srYFqVTJeZs2xYs7n4vHxDgnbx3bbThWKsfGuo+rVCn392XluM3q1Z0TwuXL28fR0c4/a9btO/6sWSvXHSuxHSd2jI11H1f16s7bdBeXp581JsY5SZ61Ih0AEGZsn/oeOuR8+6JFZtmwYfZZg21fFQrQpAh+JbFtPa8uXAhEKADgnq3iZP9+6fz54MYCAAAA/y1blr1oy7FndVyc50psx+rkrMlUd5XEju0vHG+3bdORY7sNT61MHONKSPCcxHaM2bFqukwZ58+gc/uzOsaVNRntODdV1p/Vcftxcc7bdBeXp581a8x8vg4AYa5+fbP8/nvn27/5xhzkO3fO/hhbwtvxE1A/+JXEvuIKs1y2LBChAIB7FSuaN8MXLpgJYwFkQSW2azwXABCSrFZp4EDp4EHn2x2rptu1s38TOTraVPPaWmLcdJO91WbXrlLVqvbH1a0r9ehhxvHxzpMUXnqpvU3dyJH2dSSpVy/7bQMHOvdxjoy0T4zYubNzMrxMGXtv7dtuc654rl1bGjDAjB94wN7PukQJ57gaNXJ+XNGiznE9+KA9LsfWHHXrSv3728eOcVWrZvpiS+Z5c/yX2L69NGiQGd9/v/3DBFsS/I47zLJTJ+cJIYsWte/j+uud24tUry516WLG//mPud8WFwAgzF19tfnn/dFH0vvvS3/+KT30kLR5s7n/uuuyP8bWC9tx5l8/+FXPPXKkNGmS9MYb5p9pgGICgGwiIky1yq5dpqWI41dBAYh2GTnh+QGAkHLwoPmGnSS9+qr06KNmXLastHOnKVpo0MC0F2nc2CSJY2OlX3+V1q0zSdcLF0zyt00bk3z97TfzPrF3b7PuL7/YC8e2bpWSkkySfMYMacUK6fLLzX1//WXu79pV6tBBuvJKk6guVkxautSeIP/pJ3P9qqtMMnfDBvMetUgR823qtWvNNi9cMN+6LlPGJJzHj5duvdUkz2Nissf177+mYEOSVq2yJ5Id42rf3jy+UydTKb1kiXTihMkpRERIFSpITZs6x1W0qDRhgjR/vnmcJO3ebZ73Ro2kDz4wHwa4iuuBB0zC3/bcrlplr7reuNHEZnu+qlQxCezERGnmTPPcdu9uYihb1sQFAAhz994r/e9/5h/4vfc639e2rfmnkNWcOeYT1AD1obZYrf6d1c2ebT7BLVnSvPm44QbzDxC5t3//flWtWlX79u1TlayzfgKFWNeu5gThs8+km28OdjRAiElOtvcpS052nk2pMGvSxJzN//CD/StkAICgSUqSpk0zl19+MRXCjz9ur6o+c8a5FzUAALlFfi3AtmyRbrnFXmEtma/8TJ3q/FUqyZyDNW1qktjz5plPiP3kVyW27WtYZcua6shbbpFuv928ESlVynkSiawsFmnBAn/2DqCwsfXF3rMnuHEAIYlKY9eY2BEAQsbq1aaK+fhx+20NGzr3bbZ9HgsAAEJMgwbSmjUmCXzokPkakeOkEVlNnGiWtgSyn/xKYi9a5NxXy2qV0tJMWxR3LBazHi0qAfjKlsTeuze4cQAhj3+yAIAQNGKEcwJbMv2SHXs88y8MAIAQV7Om8z9vVxo3NpcA8iuJ3akTbzIA5B9bH2wqsSHJfGo6ZgwzfdqcO2cf88/ZjkpsAAgJFy5I69eb8X33Se++a8Y1a5r+yW++GfBzXQAAECjPP2+W99xjJn3wxsmT9n/4zzzjdwh+V2IDQH6hEhtOfvpJeuKJYEcReooV89zPCwCAINizR0pNNfMnXXaZ/Zy2Rg3zeeODDwY1PAAA4Mno0eYf9g03eJ/EPnHC/rhgJ7EBID/Zktg7d9KWCDIzP0nm7PeWW4IaSkjp1EmKjg52FKGDAwUAhIStW82ybl3n9pmeWmkCAADYkMQGEDaqVjXL1FTpv/+lCLfQu3DBLOvWtX+1CXCHdiIAEDQrV0pXX23GdetKlSvb77O1iwMAAAWMbebmABVZRQRkKwCQD4oUkUqWNOOffgpuLAgBtiQ2rTMAAAhpQ4bYxzVrmm8hT5okffGFFBcXrKgAAECesk2GUbZsQDZHJTaAsPLdd1LHjvTFhkhiwztM7AgAQbd/v31sax8yeHBQQgEAAN6YMsX17bNmSWvWeH5sWpq0Y4c0YYI5H2vZMiAhkcQGEFZsfbH37ZMyMqQIvk9SeGVkmCVJbAAAQlZSkpScbL9evnzwYgEAAF4aMiT7/EJWq/TUU95vw2o1SZuRIwMSEukfAGGlUiWTs0xPlw4eDHY0CCpbJTafZMATKrEBIGj++Udq0MD5tjp1ghMLAADwkdVqv7i6zdMlOlpq316aPVvq3Dkg4VCJDSCsREZKVapIe/aYi+PEQChkaCcCAEBIe+wxk8guWlTq0kW6+WapSZNgRwUAAHK0a5d9bLVKtWqZAqEffvD8ibTFYiY0S0wM+Lk6SWwAYad6dXsSu127YEeDoCGJDW9QiQ0AQbFnj5m4UZKWLpWaNw9uPAAAwAe2Xq5ZVark/r48RhIbQNixHS/37AluHAgyktgAAISsn34y01e0a0cCGwCAsGebkyqIaCQKIOzYkth79wY3DgQZSWwAAELW0qVm2bVrcOMAAAAFA5XYAMKOLYn9/vvS7t3SJ59IFSsGNSQEA0lseIN2IgAQFOvXm2Xr1kENAwAABNrp09LXX0srVkiHDklnz0oTJzq3GTlwQDp1yvTHrlUrILsliQ0g7LRpYx/Pny898IA0bVrw4kGQkMQGACBk2dq+XXRRcOMAAAAB9N570pNPSv/+a65braZwKDnZeb1Fi6RBg0wSe/9+qXRpv3ftVxJ7yhTfH2ObpLJkSTOZZc2a/kQAoDC65BLp6quluXPN9b//Dm48CBJbTy6S2PCESmwAyHenTpkiLSlocz8BAIBAe/ZZ6cUXzblVbKzUqJG0Zo3rdQcMkB56SDp8WPrmG2nYML9371cSe8gQ+7lhbpUtKw0eLD32mFSqlH/bAlB4tGtnT2InJAQ1FASLrRI7gukdAAAIJbt3m2XZslJcXFBDAQAAgfD77yaBLZkK63ffNRXK7s7HIyKkfv3Mej/9FJAktt9n/larf5cjR6Q33jCVlRs3+v3zACgkSpa0j0liF1K0E4E3qMQGgHy3c6dZUoUNAEAB8d575pyqbVvTmsMxKeNO27Zm+ccfAQnBryT2rl3SunX2yTqaNZPeesvMRL11q7ksXWpua9bMrNO6tUner1snffqp1LOneQ4OHjTtAbK2UAEAVxwncjx/PnhxIIhIYgMAEJL+/NMsGzYMbhwAACBAliwxBUL33uv9Y2rUMMt//glICH4lsStVku66S1q1SnrzTdMGZeRIqX17qW5dc2nf3ty2Zo30+uvSb79Jd94pNWgg3Xyz9N130kcfme0dOCB9+GEgfiwABd2119o/+Dt1KqihIFhIYgMAEJJs37Bt3Di4cQAAgAA5eNAs69Xz/jFFiphlWlpAQvAriT1unElg33yz9MADOa8/apRZd+1aaexY++133GESUlarNHu2PxEFT40a5gMJV5cuXYIdHVDwREZK06ebsW3iIBQyJLHhDdqJAEC+s31ruFGj4MYBAAACJCbGLH2pIjx82CwD1APWr4kdP//cnBsOGuT9Y265xTxu2jTp4Yfttw8YIM2aJW3Z4k9EwVWypHT//dlvt1XPAwgs23GQSuxCiiQ2AAAhJyPDPrFjnTpBDQUAAARKtWrSpk3S339LXbt695hffjFLX6q3PfArib19u1mWLev9Y2zr7tjhfPtFF5llOCejEhKk0aODHQVQeNiS2Hv2SN9+K/XtG9RwkN9IYsMbVGIDQL46ckQ6d06KiJAqVw52NAAAICAuu8xMevHBB6ZPdE7++cf0j7ZYpCuuCEgIfrUTycgwS1sy2xu2dbOeS0b8fyTx8f5EBKAwKV3aPr7uOnPShELE9k+IJDYAACFjzx6zrFRJio4ObiwAACBA7r3X/GPfsEF64QXP6/71l9Sjh+n9WqyYmVAxAPxKYtevb5bvvefd+lar9M47Zpy1ktz2ZseXqm7JJK2++0565hnpqqukMmXsvaiHDPFtW3v2mL7d9etLcXEmQdaypZmQ8uzZnB+fliZNmiS9/LJ5Tn77zbf9A/BNmTLO10+eDE4cCBJbJXaEX//KUNBRiQ0A+WrvXrOsVi24cQAAgAC66CLppZfMedXo0VKbNtJrr9nv/+orkxC9+mrpkkukzZvNudjbb/ue7HXDr3YiN98srV4tLVsm3Xij9P77UmKi63WPH5fuvltavtx1H+1Fi8yyYUPfYihf3uewXZozx8R05oz9trNnpTVrzGX8eGnuXKl2bffbOHRIGjrU+baWLaWpU+3tUgAEji03ZcMEj4UM7UQAAAg5tm/e1qwZ3DgAAECAPfSQSWI/9ZS0apVJCtsSM88/b1/PajXn6W+8Id1+e8B271f52vDhUuvWJrZvvpGqV5duuEH6739N0nf8eDO+4QZz34wZ5nGtWpnH2qSmmokeLRbpyitzH0+1arlrs7JundS/v0lgFy9uPlj49VdpwQJp2DCzzrZt5sOEpCTX2xg61Kx/+LCUnGy2ecst5vd52WXuHwcgcEhiFzIksQEACDkbNphlo0bBjQMAAOSBhx+W1q83idAyZUxS2PFSooQ0cKBJjI4cGdBd+1WJHRkp/fijSQB//72pXP72W3PJyvYt3iuukKZPd845nDhhr0Dv3du3GJ55xlQ7t2xpqrJ37/b9U/+RI6WUFCkqyvw8bdva7+vWzcyq/cgjJpH95puuJ2989lnn602aSFOmmPGnn0offyw9+KBvcQHwzRVXmNdykSLBjgT5giQ2vEE7EQDIN3/9Zc71JKlx4+DGAgAA8kiDBtInn5jx3r2m1/OFC6Y9R61a2Vt+nj9vkq5+8ruRaHy8NG+eSVz36GGSR1mT8LGxJrn0zTcm2V2ypPM2KlWSBg82F8eJ2rzx3HNSr165byuyapW0dKkZ3367cwLbZtQo8/uRpLFjpfR077dv612+fHnu4gPg2fz5nq+jACOJDQBAyPjjD/ONW8mcpzZrFtx4AABAAE2d6vr2atWkFi1Mq47atbMnsNPTpeuvD0gIAZsN69prTTL7zBlp61ZpxQpz2brVtNL4/nupb99A7S1wZs60j7P2s7aJiJBuvdWMT52SFi70fvu2ieeSk3MTHYCc9OhhLjYB+HAP4YIkNrxBJTYA5IvXXjPngk2amPmOypULdkQAACBghgwxyV1fpKebZPB33wUkhICneyIjpbp1A73VvLNsmVnGxUnNm7tfr3Nn+3j5cu97b//2m1nWqJGr8AB44dQp+zglJWhhIL+RxAYAIGT8+adZPvec1L59cGMBAAABlp5uJj384Qfv/tGfO2cqnn/4wV5Y5KeAVWKHqy1bzLJ2bc8VnPXrZ3+Mzdatph94Vlu3So8+asY33eRfnADcO3nSPv7xx+DFgXyWkWGWJLHhCZXYAJDnLlwwczxJUsOGQQ0FAADkhdatTfKzVy/7LM7upKaa9X74wVx/+OGAhFCok9ipqdKxY2ZcpYrndUuVMtXakrRvn/N906ZJFSqY38/w4WYSyD59pEsvlQ4dkh5/XOrUyf2209LMV+9sl6SkXP9IQKHUrZt9/Mkn0uLFwYsF+chWiZ215xYAAMg36enmPEgycyHVrBnceAAAQB6YP1+6+GLp9GnT03X7dtfrpaSYNwY//2yuP/649MorAQkhIO1Ejh+XPvvMTJC4c6dJwtpyC+5YLNKOHYHYe+45JouLF895/bg409v633+db+/a1VRnr1tnnoOzZ00v7J49pXvuybn1yH//a752ByB3/vtf6f337dfnzXNuAYQCinYi8EaAvroGAHDthhvsLTKbNuXfMgAABVJCgqms7tBB2r1buvxy02+5UiX7OsnJJoFtqyx8+umAJjz9TmJ/9ZV0552mgljy/tu6oXBOmZpqH8fE5Lx+bKxZZu2527mzfwmzxx+XHnzQfv2ff/gaHuCLkiWlhx6S3njDXE9ICGo4yC8kseEL2okAQJ6YPds+/uST4MUBAADyWKVK0k8/SR07Snv3mkT2kiVSYqKp+L36alPdK0mjR0vPPBPQ3fuVxP7tN9PrOSPDnBtWqmQ+fS9dOjy+3V2kiH187lzO66elmWXRooGNIzbWniCX7B8IAPDe6dP2cTgcfxAAJLEBAAgqx6IgSapePThxAACAfHLRRaYiu0sXMxngVVdJ334r3XijtGKFWefFF6Unngj4rv1KYr/6qskhFC0qffxx+E1eGB9vH2dtEeJKcrJZetN6BED+ckxiP/aYNGSIVL580MJBfiCJDW8wsSMA5Jn9+52v2+YQAgAABVijRtKcOaZ/8u+/S3Xq2D/Zfvllk5TJA37VK/76qzk3fOyx8EtgS6YSOzHRjLO+Acvq5El7Ertq1byNC4DvHn/c+fqTTwYnDuQjktgAAASV44T3jRsHLw4AAJDP2rWTvvlGio42CWyLRXr99TxLYEt+VmKfOmWWV14ZgEiCpGFD065l+3bp/Hkpys0zsnWrfdygQf7EBsB7TZqYdkvPP2+u//NPUMNBfiCJDW9QiQ0AecaWxC5VSvrll+DGAgAAAmDJEu/XLVpUGjZMGjdOuu46qWVL94/v1Mnv0PxKYlesaPp4h8IkjbnVoYNJYicnmwr41q1dr2ebWFOS2rfPn9gA+MbxWxKlSgUvDuSTjAyzpAk6AABBYUti9+lj5kUCAABhrksX3xO9Fos0Y4a5uLv//Hm/Q/PrzL97d7P8/Xe/4wiaPn3s44kTXa+TkSFNmWLGCQlS1655HRWA3EhJsY9tE7GiAKMSG94I50/aASDE2ZLYtFsEAKAAsVoDfwkAvyqxH3pI+uIL6Y03pEGDwnPCw1atpI4dTTX2J59IgwdLbds6r/Pmm9KWLWY8cqRp9wIg9JQsaR/PmCF99ZXUr1/w4kEeI4kNX9BOBAACjiQ2AAAFzMKFwY7ALb+S2PXqSZ9/biZ1vOwyacIE6eKLAxWad5YtM/2sbY4ds4+3b5cmTXJef8iQ7NsYO9a0CElJMRNrPvGEqbZOSZGmTZM++sisV7euNGpUoH8CAIEyYIB5jdtyVUOHksQu0EhiAwAQVCSxAQAF3p490jvvSHPnmn98sbHSRRdJN94oDR8uFSsWmP3Mn28SkKtXS0ePSmXLmh7Td94pXXVV7ra5caPUvLm9lcfgwdkTpVl17py7feUDv5LYt91mlg0bmuf40kulRo2k+vVz/h1aLKby2V/jx0uTJ7u+b/lyc3HkKondtKk0fbqpJj9zxiSxs6pb1/y9xsf7HTKAPBITYybHve46c52+2AUcSWx4g4kdASDP7N9vliSxAQAF0pw59mShzdmz0po15jJ+vEkW1q6d+31kZJhEddYk6T//mMvMmdIdd0gffujbfFAZGWbSxQD0og4VfiWxJ02ynxtaLOb88I8/zMUTqzVwSexA6d3bfEAxdqz5+9u/3yTEatc2lZz33hu4D1cA5B3HliIJCUELA/mBJDYAAEFz7px08qQZV6gQ3FgAAAi4deuk/v1Nm4bixaXHH3du2/Dxx9K2bdLVV5uEdm6rXp980p4gbdpUeuQRU+m9Y4f02msmjvHjTWX2yy97v9333pNWrZLKlZOOHMldbCHGryR2tWrBny9p0qScK+G9Vb26NGaMuQTDuHHjNG7cOJ07dy44AQAFgOMx6c8/pV27pJo1gxcP8hBJbHiDSmwAyBO28+GoKAoHAAAF0MiRJmEdFSX9+KPzBHrdukl16piE87ZtZjK90aN938e2bWaiQUlq0UJaskQqWtRcb9lSuuYa095jzRrp9ddNSwxvqr7375eeesqcC73+umkj4q/Tp03lr2QqvCtW9Lz+wYMm0S+Z3sxxcX6H4EMdena7d5sEUW4vcDZ8+HBt3rxZixYtCnYoQNhq0MD5+rXXBicO5AOS2AAABM3hw2ZZrpxv324GACDkrVolLV1qxrff7pzAthk1yp6AGDtWSk/3fT9vv21v9/Huu/YEtk2xYuZ2yaz31lvebXf4cCkpyfRU7tTJ97hc+fxzk6j//POcE9iS+ZrW559Lzz1nKtcDgLcbAAqUChWk//3Pfj2n9kYIYxkZZsmZMzwJ9lfGAKCAslVilysX3DgAAAi4mTPt46FDXa8TESHdeqsZnzolLVzo2z6sVmnWLDOuX19q08b1em3aSPXqmfGsWTl/w/Trr6XZs6XERFOFHSjz55tzqxtv9G59i0UaMMDEO2dOQELgzB9AgePu2I8Chkps+IJ2IgACZP58843foUPNoeW776QbbpC6dJH++ssUbvXvL/XpY755u3+/dP/9po3mvHnSsWOmkKl/f/Nh+7lz0osvmjmdjhyRUlOlCRPMnDw//WQ+s/3mG+mBB8wcPpL5VvFDD9nbKu7ZY9pk2s6fd+wwLRI3bzbXDx+Wpk61n0OmppqJ7X/7zVzPyDDflP76ayktzdy2dq35WaxWc/n9d2nLFvvzsGmTWZYvnydPMwAAwbNsmVnGxUnNm7tfr3Nn+3j5ct/2sWuXdOBA9u142s8//5i2GO6cPi2NGGHGr71mEtmBsn69WbZr5/1jbBXstsf6ya+e2MD/tXff4VGUXR/HfxtKqCF06aGFIiAgVbqoCIpg7wI2VOz1sSDWx97BSrWXRwUbolKVDiKCiHSkS5USevb947yT2U02ySbZbEm+n+vaa+rOnOiwu3Pmvs8NRCPqMhYSJLEBAGE2YYJ0/vn2FbRwoY2p8+ij7vbGjf33f/VV6ym8a5ctz5ljX1sHDthy2bKWYP7mG1uuWdMafy1aZMvvvSdVry4tX27La9dKTZtKTz3lnuOrr6Qvv7T5ChXsWM795f/+Z72dr7zSynpK0qxZ0j332L12iRL2d1x2mbR4sW2/6SZLks+bZ8tTpthxXn/dyoIuXy4NHWpJcYmW2ACAAsh5atuggX35Zcb3i9/3SW8wnCfN6Y8TzHkyG/jrvvusFnWXLpm3IM8tpwtWMKVEHM7Iz04NsjwiiQ2gwClXzn/55ZetBVTM++ADt9kTpJ07bUoSG1lhYEcAebRpkzR5spWpvPtu9xmq5J/ADuSxx9xSl5K1gPY1apT/8gsvSHv3ust79/ov//KL2/PY4SSwJUuW9+njLq9YYWM5OQlsSTr7bDepfuiQdN551oLc4VuWTbK/+ddfbf7YMUt4OwnuJk1sbCcAAAqMQ4es25RkT5ezUr68tdY+cEDasCFn59m40Z3P7jy1arnzmZ1n5kzp7belYsWkN94IfVnFEiWk/fullJTg3+PsG6J79qCS2M65PB7/H2F5iSH9sQAgVMqXl1q0cLvc3nFHAUhir1snXXFFpKOITumfWgAAECLvv2/jOR054q6rXNnKYPo2KrrtNhvTSbIxmC68UBo3zr3fGTxYeustd//0y+XKWQ9gJ2E9cKBbKkSynwDvv+8+vz35ZNt35Upb7t1b+v57e163Z4/7Pmf/cuWkli2l6dPdBLbDSWCffrqVL3HUrWstv50EtsNJYL/xhnTDDQIAIPrt2+f/VDg+3l6Z7esoUyb7YztJ7P37cx5TsOcpXdqdD3SeI0esLpnXK915p3TiiTmLJRjVqtkPjwULgi8psmCBTZ0W2XkUVBI7s8ZLNGoCEI08HmullFkPm5i0e7dNS5emyZOvxo2l5ORIR4FoRktsAEHYudMaGJUubR8XO3dKxYvbV65vAluSevWSli51k9iJif5fRY0b2wN1X6ec4p+07tjRf3nIEKtp7ejc2T+J3aWLJbEdLVpYDL77z5pliXDJ6mkPH+5ub9nSSo34xrN3r3sMj0c67TQ3iV2rlnTWWf7HSK9798y3AQAQTRKaNvVfMWyYDVARiG+3qeLFsz+4kwz37fYUjJycxzfhHug8Tz9t5UmSkqSHH85ZHMHq0sW6eL3+unTjjdbiOytHj9q+Ho/9UAmBoJLYw4blbD0ARFqBq4vtNOWqVEl66aXIxgIAQAGyY4c1LjrxRLvve+QRG3CxaVO7v6xYUWrb1lo6S3YP59uTt0kT/6R1kyYZf4f4DjpdubJUr5673KyZ/7JkA0f6at/ef7lJE/9eyE2auK25JalfP/8EdJMm7oCNkiWgp093l+vW9W8kFehvaNtWmj/f5osVk+rXFwAAMWHvsmVKqFHDXZFZK2zJnmo70j/JDsT5gi1ZMmdB5eQ8vl/i6c/z11/uk/DXXrMuYflh0CCrg7ZypdUWGzcu83OlpEhXXWVJb48nZPW5SWIDKJASEvyXP/7YuvbGbPnko0dtmt3TTgD+Ql0LDkCB8/nn9qx48WK7J3PuE53xllq2lKpWdfdv1sw/wduggX9lqwYN/LfXqyfVru0uV63qv3+rVhkTxg0a+C/7lsKUpDPPdMt6SNYSPDXVXT7lFLvHdRprNWok/f23u719e+m339zlpk39Y2jUKGNMLVq4Sez69flJAgCIIWXLZkwSZLWvI5gSIc5ozcGUHsnteZxzpD+P12s1yg4fls491wa+yC+nnCJdcoklV774wn6IXHedPd13BnvcskWaMUMaOdKetns80gUXSN26hSQEBnYEUCDFxfkvX3qp3TD27h2ZePLMaYmd1cjIADJHOREA/2/KFOsF+/rrlqz94AN3m29DJ0eTJv5fv0lJ/gneQMu+xo3zb2xVvrz//nXr+i9XqeJf+lLyv+/u2VNq3tx/e1KSW3lMsoZRiYluErtuXbeVtmSJdd+PxffftyS+b0y+99bDh/snwQtUyTYAAHyVKGHdsHbu9O/2FMju3W6COf0T5+z4DuaY3Xl8u4D5nmfOHLdr1SmnWII5ve3b3fm1a919mjWzV06MHm1d2H76yWLOrHWz8yPj9NPth1CIkA0BUGBNmSKdeqq77HvzFXNIYgMAEBI9e9r0rLOstEf6+8YBA/zvt5KTpeXL3eUTTvBvSZ2UlHF5xw7/ZV+Jif5J60DHS7+/79e/0yrcNyntjCnlq1w5axAlSXXq+Cep0ye9y5XLGMPx4+5y167S119nHiMAAAVK06bSzz9Lq1bZvXhm9+G+PxCaNMn5OQIdJyfn8X36fs892Z9zxgx7SZaAzmkSu0QJadIkK1vy/POZJ99r1bJ4hgwJac/YuOx3AYDYlL7Hiu/NXsyhnAiQOwzsCBR677wj3XuvfQz4PtA+fNjuvdLXo+7f3/9etW5dK+3oiIvL2PLat6V0nTr++zs9bB2Jif49gdMntQMlsQMt+yahA0nfetz3d1CZMtKePZmfJynJvwRbnTpZxwgAQIHiDER44IC0cGHm+/kOMNGpU87OUbeuVL16xuME4iSea9SI/JewxyPdequ0fr39txk50gaWfPppm//1V2ndOhtlOsSlHYNq0vfuuyE9Z5qrrsqf48aqESNGaMSIEToSTOF4ANlKX1Ik/c1aTKElNgAAOZaSIl1/vc3XqRO4kdLw4VbScdMmW+7c2VpoO62Yk5Kku++2khsDBti61q1tWqqU1Yr2Lb1Rs6Z775uY6CaDmzSR/vzTjuH7G6VjR+u1HBdnda2dUiEnn2z3htdd5x9vr1427d1bWrDA7VV82mnWu9cpnVa9urR0qRtHcrL/cdq2tYZdzvhQvknqWrWkbdvc5YQEqUIFdznS988AAOSr/v2lp56y+TFjMo6wLNmXtpMwTUyUevTI2Tk8HhuJ+Y037At5zhz/kaAdc+a4LbH79fNPDHfvnn1jnXXr3DpgAwZIY8fmLM7MeDw2sEerVqE5XhCCyoYMHBj6cZE8HpLY6Q0ZMkRDhgzRxo0bVSuntXQAZOupp+wzu1GjSEeSCySxgdyhJTZQqBw9aknpM8+0pPG0ae62m2/OuH+pUpb89X3QXamSFB/vLtepY0nqHTvcFtf9+llZybJlLQEtWdK7SBHrNFWvnt1vVq7sHmfmTOuV3LatLa9ZI+3a5SaE58yRVqywcZkk6bvvrGFW//62vHy5lQTp29eW77/fGmSddZYtv/++1fd2Eu0vv2wNos4805avvlr65x/pjDNs+cUXrTTJ1Vfbcrly0rPPWjK9UiXb78Yb3XjPPNNiiYuL4TFGAAAIRrt2NmDhzz9Lo0bZl2vHjv77vPCCPZ2WpNtuy9hreto0N7GdWfL49tult9+2Gl633GItrp2ny5INbnHLLTZftKjtX4h5vN7s7+rSt2YMyYk9/nXW4HKS2Bs2bFBN30LvAHLshhukt95yl3v0sFrZMed//5MuvNC+SJ2uRACyd9ZZlgkaPVoaNCjS0QDIZw8/LD3+uCVkGza0lsq+KlSw8iLnn2/LPXta62XfBjter/1ecBLgPAMDACA25Sm/tmiRlQg5eNDqcD3wgP1AOHjQBkd8+23bLznZfnD4dsuSgktiS/ZU+umnbb5VK+m++6T69aXVq6VnnrE4nP3++9+c/Q1S/rXEjoCgmvStXZv5tt27pcGDpfnzrR74gAH2wMIZcGTbNts2bpy0ZIk9yX/rLRuVGwDy25tvSm3auF1xfQdaiilOS2xqYgM5E+quZACihtcrffut1LKllfA4cMAS2JLVf06fwJasBbVvh0endEd6w4fbs68+fUIeNgAAiAWtWkmffCJdcYW0d68lsdNLTrYfI+kT2Dnx5JPWVWr0aEtYX3JJxn2uuUZ64oncnyPUvF7pt9+si9iOHZbYz+6p/8MP5/m0QSWx69QJvP7IEWvFsGiR9Nhj0oMPZrxXTE62hoN33GEPDIYOtWTSzJl5DR0AguN085UyDo4UMygnAuQNTSmBAufDD+2+8sQTpeeeky6/POM+AwZYqZAJE2y5Wzdrpe1wSnnEx9tAj5Uq2fKJJ1ovYQAAUIj17Sv9/rv0yiuWrN64USpeXGrQwHpK33yz1SbLi7g4K1ly/vnWunv+fEsMV6pkLYEHD46uOl7jxkmPPmoDO+ZEuJLYmXntNRt08qKLpIceynpfj8eS3EuWSJ99Zv//Aw2sAgD5adUqafNmdxDgmHH0qE1JYgMAIEl6/nmb/vGH3Y/s359xn/S9Zlu1yjiAoSRNmiT95z/SiBH5FS0AAIhJderYQBIvvpiz9wUz6KKvPn3ypwtYUlLoGvQ8+KCVPgnmeB5PyBsS5ana9YcfWkwDBwb/nkGD7G/4+OO8nBkAgufbEnvLFqlxY+tyHFMoJwLkDgM7AgWO12s9en/7zV23f7/Vu163zl1XrJjUoYMNtuhISvJviV2hgk27dZNmz5Zat87HwAEAAGLV3LnSU0/Z/Omn2w+xX3+1ZWfgw+3bpYkTpXPOsR9snTtbEiY1NSQh5CmJvXq1TZ3618GoUsX/vQCQ37p0kdq3d5f37ct5z5eIo5wIAACSrLW0cw/l6+STpcqV3eW6daWSJa0+tiMhwUqHnHSSjdHTrl3+xwsAABDz3njDpnXqWGmVFi38G9l5PNaCsFcvafx4+8H2yy/SmWdaPeoQyFMS22nUtHJl8O9x9qVBFIBw8Xgy3uyeeKKUkhKZeHKFciJA7tASGyhQjh+3XqySdO+9/tuaNLGktcNpZb1nT8bjzJ1rZS3zWsYSAACgUJg1y+6tbr01uLzEjTdane/ff5defz0kIeQpid2kiU1ffjm4luGpqdJLL/m/FwDCIdCAjl9+GfYwco9yIgCAQuzYMenuu6VOnaRNm6xF9bBh/vs0auQ/yLzz3X/FFTZt29bdFh9PAhsAACBoW7bY9MQT3XVxPmllp+GdryuvtMZEn3wSkhDylMS+6iqLZe5cqX9/aevWzPfdtk067zzb1+Ox9wJAuAS6Ub3uOhvs6ZFHpH/+CXdEOUQ5ESB3fDNaAGLWDz9IL7xg9xKSlQorVUoqW9bdp25d//c4SewBA6TJk+0YAAAAyAUnSe3UiZakMmXc+e3bM76nZk2brloVkhDylA254QYboPGXX6wcSr160hlnWCuHKlXsvnHbNmn+fPvRePiwva9TJ3svAIRLrVoZ1x08aIPNStLatdK4ceGNKUcoJwLkDeVEgJi2aJH/8imn2LRcORvrQrJBG3316GHTuDjp1FPzNTwAAICCrXJlafNmae9ed13VqjaCdmqq9OefUvXq/u9xWm87P9byKE/ZkLg4G3Ty8sulr76SDh2Svv7aXuk59459+0offODf4hwA8lupUtZb5KST7OFaerNnhz+mHKElNgCgEPv9d//lBg0y7lOnjk1//VWaMUO69tr8jwsAAKBQOPFES2IvX25d4iSpeHFbv2SJlQzp2dP/Pe+9Z9P0ye1cynMquXRpG3Ty66+lPn1sMBWv1/9VooTUu7cluidM8G9tDgDhUrWqdMklgbc1bRreWHKMmthA7jCwI1AgLFjgv+y0uq5UyV3nlA5r1Uq67TYazQAAAIRMly52TzV1qv/6iy+29aNH24Alf/whzZsn3XST9Omndj/Wu3dIQgjZT7uzzpK++cZalf/1l7VqnD3bEvR791q5kbPPDtXZACB3Hn888Pqoz2/REhsAUEgtXy6tWeO/zkliv/qq3Tt9/nnYwwIAACg8+ve3qZP8ddx2m/0wS02VnnhCatFC6thReust216+vHT//SEJIeTZkLg4qWHDUB+1cBgxYoRGjBihI0eORDoUoMAqW9Y+Y195xX/9V19Z75eLL45MXNmiJjaQO7TEBmLa9u3W2zO9ypVt2qWL26MVAAAA+eTEE60V9rFjbiM7ybrCTZ0qXXGFNHOm/3uaNbOSIs4Aj3lENiSKDBkyREOGDNHGjRtVK9AodABC4v77pYULbVBaX5dcEsVJbMqJAAAKoWHDbPDlatWsLOG4cVYCzHk+BQAAgDDp1i3w+jp1pJ9/ttIcf/xh+YuGDa3GWwiRxAZQ6FStap+vgW6Ab79deu65KMwVU04EyB0yXUDM2r5dGjPG5j/4QGrb1l4AAACIQo0a2SufhCQbsnOn9P77lhRas0bat086fjzr93g80urVoTg7AOTOPfdYwtrXK69IJ50kDRoUmZgyRTkRIG8oJwLElMcflx5+2OarV5e6d49oOAAAAIiwPGdDPvtMuv56t6Z3sPeINIwCEGnPPCNdeaWNO+Dr2WelU06RNmyQOneWSpSITHx+aIkNAChEnAS2ZD1XuXcAAACIIseOSb/+Ki1ZIu3aZesqVLA62K1b50v39jxlQ+bOlS67zAag9HqtlUSrVhZzXFyoQgSA/OHxSMnJGdcvXy41bmzz990nPf10eOMKiJrYQO4wsCMQc9L/c23ZMiJhAAAAIL0DB6zL3KhRbvI6vfLlpWuukR56SCpbNmSnzlMS+5lnrGxIyZLSO+9YQhsAYkl8vPT111LfvoG3P/OM9NRTUdACjHIiAIBC4qmn/Jfr1o1MHAAAAPDx11/SmWdKf/+ddSOhXbuk55+XPvlEmjQpZHWy85QNmTXLEjv/+Q8JbACx6+yzs95eu7b0++/2MDFiKCcC5A4tsYGY89ln/stJSREJAwAAAI5//5V69pS2bLF7q2bNpAEDpHbtpKpVbZ9t26T586Vx46zMyN9/S6edJi1dKpUrl+cQ8lT0Y88em/bqlec4ACCiXnwx820bN0pTp4YvloAoJwIAKCTWr/dfJokNAAAQYc88I23ebPOPPy4tXizddZfUpYvVaU1Otvk775R++0164gnbd/Nme28I5CmJXa2aTSPezR4A8uiOO6xXSWZuuUV6//3wxZMB5USA3OFHChBT9u2Tdu/2X1epUmRiAQAAwP/78ku7t7roIunBB7O+z/J4pAcekC6+2Fptf/llSELIUzbktNOk0aOlhQultm1DEg8AmP/8R/r227Ce8tGj0uWeTKoObJZ0paTQPEDMuXXrbEoSG8idJ56Q3ngj0lFEh2LFpEcfzXwwACDMpk2zxjGNGkkrV9q68uWlH3+0sYB4FgUAABBhTle5gQODf8/AgVYXO303u1zKUzbk7rulDz+0Wt1XXCGVKROSmAAUdsePh6y7SU4Ul9Qsu52WhiGQrNSvH+EAgBjjjAi3ZYu9YN56iyQ2osLvv0s9etj82rXSySfbfJ067jwAAAAirGxZ6fBhqUqV4N/j7BuihHGektiNGkkffGCDOvbsaa2yTzwxJHEBKMxSU9358ePtwzKMHnhAmjM38+2XXCxdf3344klzwglS06YRODEQw/77X6lfP/vBBWva+vTTbokiIMJ++MGdHzbMpsWLW4lFAAAARInmzW2wsJUrpVatgnuP08WuefOQhJCnJPbVV9u0aVMbfLJFC4urcWOpVKms3+vxSKNG5eXsAAos3yR29+4hGcU2J+79XvrmG+nKKwNvXzpFuv7jsIYEILeKFpU6dYp0FNFj61abOoPFAhG2caM7/+67Nv34Y+nccyMTDwAAAAIYPFiaMkV6+WXpggukuGyGWUxNlV56yRLAIWoFmKck9tixbo06z//XkV2yxF5Z8XpJYgPIgm9R6ggUwkxMlC6/PPMkdosWYQ0HAELHqat//Hhk4wD+X6ASib17hz8OAAAAZOHCC6Xvv5fGjJH695feftt6iweybZslvefOlQYNsgEeQyBPSezatRloBUA+iHAS2znt8OHSzTdn3FayZPjjAYCQKFLEprTERpT47Tf/5dmzpRIlIhIKAAAAMvPuu1K3btLSpdZ1vV496YwzpLZtrfa1x2PJ6/nzrV7c4cO2rVs3t7tdIFddFXQIHq/XN1uESBoxYoRGjBihI0eOaPXq1dqwYYNq1qwZ6bCA8EtJkUqXtvl9+yI6auzNN0sjRmRc37+/fdaOGZP1A0gAiCoTJtgHWIcOli0EImjnTqlSJf91hw9bTWwAAIC82rhxo2rVqkV+LRTi4vwbGTplNgLJapsvjydHjWuyKWCCcBoyZIiWLVumadOmRToUILJ8a2JnV2cpn915p1ShQsb148dL550nff21lXkCgJjgtMSmnAiiwMKFGdeRwAYAAIhSXq/7Sr8c7LZA+wYpT+VEACBfREE5EUe9etL27W7eJ5AffpDOPFPq0SN8cQFArjg1sSkngiiwYEGkIwAAAEBQ1q6NdAShT2Knpkq7dlk1gBo1sk78AEBAUZTElqwx+NlnW9mnQH77TTr1VOnIEalYsbCGBgA5Q0tsRBGS2AAAADGiTp1IRxCaciLHj0ujRkldukilSklVq1rrxb/+8t/vm2+ke++VnnwyFGcFUGBFWRJbkj76SPr006z3WbMmx71hACC8aImNCPr3X/fSO3ZMmjHDf/vpp4c/JgAAAMSGPCex//nHktfXXy/NnGktETMra5KUJD3/vPTwwxlHIgeANFGYxC5TRurXL+t9GjeWhg0LTzwAkCu0xEaErF9vA9dfcIEls7t2dQd2XLxYuuWWrAeuBwAAQOGWpyT28eNS377SnDmWZ7roImn48Mz3b9ZMat/e5r/8Mi9nBlCgRdHAjr6KF7deJ9WrZ77P44+HLx4AyDEniU1LbITZq69aY5cJE6xX5uzZtv6mm6QWLWz7CSdENkYAAABErzxlh8aNk+bPtxqw334rffyx/RDNyjnnWCPLX37Jy5kBFGhR2BLbcfXV1pskK+eea71OACDqOOVEaImNMFu3zp1/7jmbDh8uPfpoRMIBAABAjMlTEvujjyy/NHiw1KtXcO9p1cqm6etlA0CaKE5iS9Jpp0k1a2a+ffx46Z57whYOAASPltiIEN8ktuOqq8IeBgAAAGJUnpLYv/9u03POCf49VarYdOfOvJwZQIEW5Uns+vWlDRukiROz3u+11/isAxBlaImNCPB6pbVr/dd9/rlUtmxk4gEAAEDsyVMSe88em1asGPx7nHsmpyEQAGTgWxM7CpPYjpYts95+663SvfeGJRQACA4DOyICtmyRdu/2X3f22ZGJBQAAALEpT0nsChVsumFD8O9ZudKmlSvn5cwACjSnJXYUJ7AlG4BqzZqs9/nqK7t5J18EICo4LbEpJ4IwWrQo47rixcMfBwAAAGJXnpLYJ55o0/nzg3/PJ59YXqpt27ycGUCBFiNJbEmqW1fq2zfz7Tt3StWrSzffHL6YACBTtMRGBMyZ479MAhsAACBK7d1rryiUpyR2//6Waxo+PGMXwUD+9z/p669t/vzz83JmAAVaDCWxJentt6WhQwNvc/6UN98MXzwAkCkGdkQEzJ7tv5yYGJEwAAAAkJ3ERCu9sWyZ//p337VXBBPceUpiX3edVLu2xX/GGRn/Psc//0gPPihddpnlpJo1ky66KC9nBlCgOTWxYySJfcIJ0mOPZb9fx47SunX5Hg4AZI6BHRFmx45Jc+f6r6tfPzKxAAAAIAhOazxfAwdKgwZJGzeGPRxHnpLY8fHShAlSQoK0cKHUvLnUtKm7/YorpORk60r/9NP2I7ZCBRuNPEZyUwAiwfnAjMvTR1TYPfKI1K5d5tvnzJGefTZs4QBARrTERpgtXSrt32/3C++/b+UIR4+OdFQAAAAIyLlfOHIksnEEkOcM0UknWU3sjh0t77R8ubtt8WJp1SprVOn1WnJn7lypQYO8nhVAgRZj5UQcw4ZlbG2W3r590pNPRvThJYDCjJbYCLOpU23avr10+eWW1G7cOLIxAQAAIBOVKtk0s3IbEVQ0FAdp0ECaOVP65Rfpq6+kBQushMjx41LFilKrVtI550innx6KswEo8GI0ie248UbpjTcCb3v/fZtOny798EP4YgIASW7LCq/XWhnEWI8XxJZJk6Q777T5rAZBBgAAQJTo2FEaP1667z7p33+txEaxYu72+fOlHTtyftyuXfMcmsfrDVToBJG0ceNG1apVSxs2bFDNmjUjHQ4QfuvWSXXrSiVLSikpkY4mx44ftxJL7dtnvd+KFVLNmvZnAkBY7N5ttd0k6yLo+4MUCKEvvpAuuMCel5QpI61d6zbsAQAACAfya7kwc6bUvbs7VpkjL40NPZ6QlDOk+Q2A6ON8WMZoC8EiRaSTT85+v+Rk6dJL7bOc8rQAwsJpiS1RUgT5YsMGacsW6e677V7niiushAgJbAAAgBjQqZO1Rqhf337MOS+H77qcvEIgJOVEsrJzpyXcnUY/yNyIESM0YsQIHYnC4ulAWMV4ORHJ8kRffWWDWV12Web7TZhgtUErVrSBH2P4TwYQC4r6/PTj6RlCbNo0qUcPd7lCBemtt6RSpSIWEgAAAHKqb197bdggbdokHToknXqqJSxGjbKe8xGQL0nsbdukoUMtcb97t61LSJD69ZMee0yqXTs/zhr7hgwZoiFDhqR1dwAKrQKQxJbc+p9ZJbElafVqe1WqZN8FM2Zwww8gn9ASG/no22/9l087je8zAACAmFWrlr18tWsnNW0akXCC7qu/caNUvbq9MhuwTJLWrLFu9KNGSbt2ua3G//1Xeu89G+Txt99CEDmAgquAJLEdr70W3H67dlkt7RNPtMFwt27N37gAFEK+SWxaYiPE5s/3X+7SJTJxAAAAIMSuuspe5ctHLISgW2J//70lVIoXly66KPP9LrlE2rzZXa5VyxLfy5ZJ+/ZZy+xLL5WWLPHv0QoAaWK8JnZ6N98sde5sD/GCsW6dvc47T2rTRrr9dqlevXwMEEDhQUts5BNnUGNfzZpFJhYAAACE2NixkY4g+JbYs2fbtEcPq90ayDffSAsWuDWwv/9eWr/e3rt1qzRokO23YoX0+ed5DR1AgVXAWmJLloROSMjZe2bPtlbc118vvfyylRwBgDzxeNwHhLTERggtX27jQPhKSopIKAAAAAgHr9cSFfPn22v16pAN4hhI0EnsJUvsvuf00zPf54MP3PkXXpDOOMNdLllSGjlSat7clidMyGmoAAqNApjETkiwckt//pnz906eLN1xh/V0WbgwX78TABQGTlc4WmIjhNKXEpGkmjXDHwcAAADy2aRJNghYQoKUnCx16GCv5GRbd8450g8/hPy0QSex162z6UknZb7PtGk2LVcu8EBmHo909dWWgFm8OPggARQyBTCJLVkvlsaNc//+BQusvMh774UuJgCFkFNShCQ2QijQQ1pKBwIAABQgR45YwrdPH+m776QDB9zBEJ3XgQM22nfv3rbvkSMhO33QPy337rVppUqBt69bJ23bZjmnrl2lYsUC7+fUhPWtmw0AfgpoEtsxY4a0ZYt08cW5e/+LL9p4CgCQK05mkXIiCKG//7bpzTdLY8ZIV1wR2XgAAAAQYpddJn35peVsiha1ch3t20snnGDbt26V5s2TfvxROnpU+uQTu+f49NOQnD7oJLaTS8osgT5vnjvfpk3mx0lMtOmBA8GeGUChU8AGdkyvSxebVq1qn+mffCLt2hX8+48etQFzn3jCercAQI7QEhv5YMMGm3btKj3/vBQfH9l4AAAAEELffit98YUliHv0kEaPlurUCbzv339bsmLKFBsU8bvvrPV2HgWdIXIGc1yxIvD2WbPc+bZtMz/Ovn02LVEi2DMDKHQKeEtsR7du0uuv20PKU091e6pkZ9kya8l9zTX5Gx+AAoqW2MgHTkvs2rVJYAMAABQ4Y8fa9KSTpO+/zzyBLdkPwokTpZYtbXnMmJCEEHQS26mF/fnnGbd5vdJXX9l80aJSp06ZH2f9eptWrRrsmQEUOoUkie1o3doGb/z8cxsEKycPKO+8Uzp4MP9iA1AA0RIbIXbkiLRpk83Xrh3ZWAAAAJAP5syxHM1dd2VeQ9pXsWLS3XdbfmfOnJCEEHQS+5xz7LwTJmQcVOz5560mtscjnXaaVKZM5seZPdumjRrlIloAhUMhS2I76ta17tiffGK9X5o3z/49L70kvftu/scGoABxkti0xEaIfP65VQKrXJmGKgAAAAXS9u02bdo0+Pc0bmzTHTtCEkLQSewrr5Rq1bL5gQOtbvfll1sLwv/8x93vzjszP4bXK40fb3mpDh1yFzCAQqCA18TOTpky9mBw4UK3139Wtm2zkiQhHPQXQEHmfLDQEhshsGmTjfEjSWeeWWi/ugEAAAq20qVtunNn8O/ZvdumpUqFJISgf2aWKiV9/LElV7xeacECW1682G00efXVUs+emR/ju+/croannZaXsAEUaIW0JbavMmWs983ff0tLl0pVqmS+77Bh0hlnSM89F774AMQwyokgRPbvl846y12+9dbIxQIAAIB85JTU+OST4N/j7Buichw5aivRsaMlr88/3wZm9HrtVaeOlRR5++2s3//44zY94QRaYgPIAknsNNWqSSeeaCWk7rkn631feUU6dCg8cQGIYQzsiBB5+GFr0OLx2Pg+bdpEOiIAAADkC6fO9Jgx7iCPWXnvPWn0aPuh2L9/SELweL1OtihnUlOtHErx4lL58sG958ABmxYtyqjlWdm4caNq1aqlDRs2qGbNmpEOBwi/+fOldu1sdChnNFho82apRo2s9/F4pKeeku67LzwxAYhBTZpIy5dbiwSnVTaQXtWq0g8/SPXr+63eskV66y1ryP/EE7bu/fetzCAAAEA0Ib8WQgcOSMnJ0tattty7t5XkaN/euo57PFbrdO5cS15PnGhJ7xo1pL/+CklJkSCqrQYWF5fzgVuc8ikAkCVaYgdUvbp0++1SQoL02GOB9/F6pS++IIkNIAvt2lkSm64byMqaNdL06RmS2H36SL/95i6ffLJbExsAAAAFVOnS0jffWH3o3bstST1xYub7e73W6vmbb0JWEzvXSWwAyDeFfGDHrLz0kk0zS2JL0rx50oAB0osvShUrhicuADFk7Fjp0Ufdz1ogveuvlyZPdh8q/7/UVP8EtiR9+y3PnAEAAAqFVq2kJUuk226Txo/PfIydIkWkc8+1BEZ23clzgCQ2gOhDS+xsXXih9NlnmW9/91172FmjhjRwoETPKQBpPB4pKSnSUSCalSlj03QPOh54wH+3s8/Oec9MAAAAxLDq1S0ZsWWLNG2atHSptGuXbatQQWrWTOre3Qb4CjGS2ACiD0nsbH3yiXTllTa2QmbefNOms2ZJgwdLrVtLtWqFJz4AQAxzekKlS2J//bX/bk2bhikeAAAARJdq1aRLLw3rKemrDyD6kMTOlsdjYyoEY+JEGwz49NOlDRtsUF4AADIVIIm9c6e0bJn/bjToBwAAQLiQxAYQfaiJHZRGjaTvvrPa18H46y+pdm1rkf3vv4zpBgDIRIAk9tKlNi1SxN2tTp0wxgQAAIBCjQwRgOhDS+yg9e4t3XRTzt6zcaOUmGgJ7X//zZewAACxLEASe906m7Zv7+5WpUr4QgIAAEDhRk1sANGHJHaOxMdLzz5rLasffjj4923fbsnspCRp0qTgy5MAAAq4LJLYJ55orbF37JBatAh/aAAAACicaIkNIPqQxM6xe+6Rhg7N3XvXrZNOPlnq2VNasCCkYQEAYlEWSeykJBuIfskSqXjxcAcGAACAwookdhQZMWKEmjZtqu7du0c6FCCynJtmktg5dscduXvf/v3SlCnSxRdL118vzZoV2rgAADHE+f71SWIvX27TpCTLcfvWxgYAAADyG0nsKDJkyBAtW7ZM06ZNi3QoQGQ5LbEZ2DHHXnxR2rlTKl06d+9fs0Z65x3p/POll16SZs8ObXwAgBiQriX2v/9K8+fbqlNOiVBMAAAAKNSoiQ0g+lBOJE8qVJDWrpV275YaNcrdMbZule68UypVyo61c6fUpElo4wQARCknif3/38dTpkjHj9vYCUlJkQsLAAAAhRdJbADRhyR2nlWubK81a6wFXfv20pEjOT9OSopUtarNr19vA0EmJNixPB6pWLGQhg0AiAY+LbGPHpWuu84WzzgjciEBAACgcKOvPoDoQxI7ZOrWlVq2tAG43nxTat4898fq3VsqX16aPl3q3l2qWVPaty9UkQIAooZPEvvtt603jiT16hW5kAAAAFC40RIbQPRxBpKiJnbIJCfb67TTrNb1hg3SV1/l7BjLltnUd+zZIUNsEMgpU6TatUMWLgAgknyS2B9+aLNNmkh9+kQuJAAAAESRo0elX3+Vli6Vdu2ydRUqSM2aSa1b50u3bTJEAKIPLbHzTf360vDhNnhjnz6WhM6L996TVq+WPv44NPEBAPKX8xUr2f1Gu3bS/ffb8m+/ST17SqvW2i3CujWpmjVLKlJE+uknni0DAIBCaP166a67pMaNpdKlLVHbtq303HNWfzNUJk6Uzj3XujzHx9v03HNtfXa2bZNGjpQuu0xq2lQqU0YqXlyqVk0680zp7belgwdDE2dKiv14rFbNRvy+/nrpP/+x1/XX27pq1aQHHgjtfx/REhtANCKJne+qVJG+/VY6fFiaOdMelr7/fu6PN3y4tHy59NBD0pYtduxHH6VmNgBEWkqKdXAqU0Y6dEjq0MHGNpg+XbrvPmn+fHvt32+f5ZL0a6U4NZD07ljrGTVggFS9euT+BgAAgIj4+mvpiiukvXvddSkp0oIF9ho50m5+GzTI/TlSUy35O2qU//pNm+w1frx07bXSW28FblHwzjvSjTfaKNzpbd1qr0mTpOefl/73P6lFi9zH+vff1r179Wr/lhHp7dolPfOM9Pnn0uTJlpAPAZLYAKIPSeywiY+XFi2y+RUrrHZ2bh7QbtggjRkjlSghvfGGratf376PL77YEiYAgPy3b581GGrWzL5OO3eW1q2T1q6VPvxQWrzY9rvxRrvvcjgJbEnatuP/b5C8qera1cpQAQAAFCqLFtnN7MGD1hrg/vulHj1s+eOPLXm8YoV01lmW0C5bNnfnefBBN4HdqpV07712M716tfTssxbHyJFS5crSf/+b8f3btlkCu3hx6eyzbSTuJk0sntWrLc4ffpBWrrQE9K+/5i6pfPSoDZS1apUtN24sDRoktW8vnXCCrdu6VZo3Txo71uqRrlxp71m0SCqa9xQ0SWwA0cepiU0SO6x+/tlaZvftay30cuOdd9z5a6+16bZt1kIbABB6+/db45pzzrHeLx07Sn/8YfcKS5a4DyrPP98awjjeeivjsYoXl44ckVL/v+Jg3dqpmjTJHlACAAAUKrfdZgnrokUtCdyxo7vt1FOlhg0t4bxihfTCC9Ijj+T8HCtWWAtpSWrTRpoxQypZ0pbbtrUfeN26WZL8ueekq6/O2Oq7dGnrXnfXXZbo9tWqlXTBBbbtxRel7dulhx+WRo/OeawjR0p//ml5mgcesL+3SBH/fZKTpa5dpTvvtO1PPGHJ7JEjpRtuyPk506GyHYDo47TEpvhmWBUvbg9rv/nGviMvvTTnxzh2LOO6r7+2hIrzbGL37rzFCQBwnXKK3ZuMGWNlof74w9afdZZ01VXufr4JbEfr1v7LTz9tUyeJfeYZqSSwAQBA4TNvnrXykqRrrvFPYDvuustaPEvSK69YS+Wcevll9yb6tdfcBLajVClbL9l+gbrH3XGH/YhLn8D29dRTVqdakr74wr05z4nPPrMEdv/+0uOPZ0xg+4qLkx57zGp6e7323hAgQwQg+lBOJKLKlJFOPtnKgowebeMz5MW8edat/Y47rE52hQqWKAcA5Ny2bdZa2uu1z9UlS2z94MHSlVe6+23enPG9zZr5N965/nr/7X362NRJYleqkIsbHAAAgFg3frw7P2hQ4H3i4twWA3v2SFOn5uwcXq80YYLNN25sA5cE0qGD1KiRzU+YkHUt6swULy516mTz//4r7dyZ82MsXWrTq68O/j3XXGNT5wdrHpHEBhB9SGJHhXLl7Pv64YctkT1uXN6O9913bg+rvB4LAAqqjz6yQeT37LGvw48/tnrVXq90++1WcrB5c+nTT63xTlZq1LAyhI5zzrHPdkfnzv77165tU6/s+9fjJYkNAAAKoV9+sWnp0tbCKzPdurnzM2fm7Bxr17qtDnyPk9V5Nm2ywU5y4/Bhdz6rVtSZ+fdfm+ZktG+n9bfvwJh5QBIbQPQhiR1VSpa03kdXXml1rnv0sNZ8malYMfB6Z/wHyQZFbt7cWmRPnCj17GkDHQNAYfPZZ5ZsnjPH7i0uu8xqXI8ZY0nrSy+VbrlFGjHCeqpKVj7xgQcyHis+3r/cYI8e1vvF0amT//1Lw4b+73dKhzgtsXPV0gcAACDW/fmnTRs0yHpAwsaNM74nWMuWBT5OqM8jWamT2bNtvmpV/x+IwXLes3Zt8O9x9s3N+QIgiQ0g+jj1maiJHVU8Hhu4ccoUK6OVnGytBdNr0SK44y1daq0I+/SxY772mvTJJ1ZyhLwJgMJg8WLpoousEc6gQfa56liyRHr1VXc5/QC5a9bYdOhQd1379v6NYzp29G95nZxsLbwdxYu786VLu8+O05LYuamXCAAAEMsOHZJ27LD5mjWz3rd8efsRJUkbNuTsPBs3uvPZnadWLXc+p+eRpLffdv+mCy/M+fslG0zF67WWFcF6/XX7gdmqVe7OmQ4ZIgDRh5bYUa9hQ+mvv6zbe6VKUvfu7rY6dYI/ju9AY5s3S5dcYiVHvvvOvu9yMzYGAMSCv/+2wdsdy5f790gZM8Z/f6cHp6+6df17xnToICUmussNG/p/jtaq5Z/E9uX7PpLYAACgQNm3z0paOC/frmmB9nWUKZP9sZ0k9v79OY8p2PM458jNedaskR580D3P/ffn7P2OSy+16bRpVhf7wIHM901JsW7cU6bY8mWX5e6c6WTRJh4AIoQkdsxITLQHwcWL2+v4cXfMiZz68EN3/uyzbVqunNVs3bvXyo8AQCw7ftzKhxQvbr/pA5UHbNDAv/ySr1KlrDfpr7/actu2/snn+vXdkiCSlJTkn7SOj89YAvGZZ6w0yfvv23KXLlLqzySxAQBAwZHQtKn/imHD3AGb0jt0yJ337baWmfh4mx48mLOgcnIe5xw5PU9KinTeeW5riNdey1lNa1+XXy69+aY0a5YNcvXdd9alsH17qUoVy99s2ybNnWuDt2zfbu/r1MneGwIksQFEH5LYMcVJmGzebN+R27aF7tjz5klXXGFlyLZssQozZctKxYqF7hwAkJ927bLPxcaNbQD7Dz+0zzLnc+yCC2ycAMlqY191lQ2o6zjrLOnbb22+eXP/cQfq1fMvF5KU5N8ztXZtS3z7+vRTawzz1lu2fO+90s03u/tNmiQdvDdOGi6S2AAAoEDYu2yZEmrUcFf4JoXT820RcORI9gd3WnWXLJmzoHJyHt+W48Ge59gxKx2yeLEt33ijNHBgjkL04/FIX39tP07nzJH++cdKiwQqL+LkdDp2lCZMyP0506GcCIDoQ03smFSliiVQ2re3hMuSJXk/5nvv2fTYMemHH6xUyVln2TrqZgOIdkePWsvq5s2lvn3dHiepqXYvEh8vnXOOu3+XLv4tq5OTpSZN3OW6df2T2ElJGZPYvknr+HjpscesxbbzeXrGGdYw5vzz3f1831OypFShIi2xAQBAAVK2rJSQ4L6ySmKXLevOB1O6wymrEUzpkdyex7d0RzDn8XotYf3dd7Z80UXS8OE5iy+Q8uWlX36xFt1Nmth5Ar2aNLHz/fyzvSdEaIkNIPrQEjvm9elj008/tUTNbbdZa8Sc2r3bnXd6IP34ozR9uiVgnn3WynEBQLTweu3rKyXFSiM5n2NOa2pfbdtKJ5zgLp94on8Se9Qo++3vqFPHv+dp+iR27dqW6L7iCnesgtq1rVeLr2y/XuNIYgMAgEKqRAlrNbBzp38Xt0B273YTzL6DLwbDdzDH7M7jO5hjMOcZMkT64AOb793b6saFqpFgXJwdf8gQ6y69dKl7s1+hgg3YUq1aaM6VDklsANGHJHaB4Qx8XKKEdV3v29cS2pmpXNktnZUVJzlz110ksQFEj7VrrTX1xRdbGaSpUzPu07Kl9NtvNt+oUcaW1L7j9iQlSX/84b/s2xAnOdnuEV5+2RrzOL1SnVbXuUYSGwAAFGZNm1pLglWrrFtw0UzSp8uXu/O+3eeCPUeg4+T1PPfdJ73xhs137Sp9/nn+1eOsVi3fEtaBkMQGEH1IYhc4F1xgL6/XWlGXKOE/kKPjxBNtsONg7dljrb4HDZLWrbPfFnfcEaKgASAHtmyxGtWS9OKLbk/PokXt3keyZPPMmW4SOynJv+V1UpJ9ljmqVbNyJI4WLex+5/Bht9W1lPXDwVwhiQ0AAAqzzp0tiX3ggLRwodXMDGT6dHe+U6ecnaNuXRtkcfNm/+MEMmOGTWvUsB+MmXniCeuuLFmXv2++yXmt7ihGEhtA9CGJXWB5PPYgWJKKFLHWgj16uK0VfWu9BmviRHs5WraUVqyQrr+eSwhAeKSmWk8TX/v3233GWWdJb79t6046SVq50t0nKcnKMjpq13bvS2rXts/JU0+1UiRxcTY2jscjPfBAfv41IokNAAAKt/79paeesvkxYwInsVNTpXfftfnERLuxzQmPR+rXz1pNL19ugyV26JBxvzlz3JbY/fplfpP7yivS0KE237y59P33/nW3CwCS2ACiDwM7Fgrjxtn3bNGilsQpUiQ0/8tPPdWmDRpIBw9KvXrlX+8pAIXXsmVWJmnFCktgL1yYcZ9u3aw0oKNuXRsE15GUZGWUmjWzz8CaNe1zcMMGt4W2x+OOMxA2JLEBAEBh1q6d1Yj7+WcbpGTAAGtN4OuFF6Q//7T5227LeNM5bZqb2B4wQBo7NuN5br/dWjscPy7dcou1uPZtOX3woK2X7Mb59tsDxztmjNslOTnZBpLy/RGaE4895s4//HDg9bnhe6xcIokNIPrQErtQ8HjcgYo3b7YSI99+K332WWiOf9ppNh071n4zAECorFpl9zF799ry99/b9KabpNdfd/c7/3xp1ix3uUYNa0Dz7rs2oGObNpa8XrTIPhOd3LHvOD8R4Xz/ksQGAACF1SuvWImQgwelM86wrnA9etjyxx+7Xe2Sk22wptxITpbuuUd6+mlpwQI73333SfXrS6tXS888Yz8UJduvYcOMxxg/XrruOsujJCRY3Nu3Zz3YVN26/gOx+HrkEfe3oG/i2Xd9bpDEBlAgkcQudJyxIC67zBLbVarYw+9Q+O47Sxr51p0FgOzMmSMNHCg9/7x09tn2WfLJJ9bbY9o0N4Htq3dv/yT2eedJkya5y0WLWkmRVav835fZWEER42TTne9jAACAwqZVK/vxd8UV9sMvUD235GRriZWXsh1PPin98480erQlrC+5JOM+11xj9a4DGT/eWnJLFmfv3tmfc+pUqXv3zLdn9hswwr8N6asPIPqQxC604uKsfmzbttLIkdJDD0kXXpi3Y376qSXGX3opNDECKBy6dZP++ssGpR03zj6b3n3XBpL96CPbp1cv//eccoo7n5xs0yuusGnbtvkfc8hQTgQAAMBqxv3+u5XqSE6WSpWy1lFt2ritpH1H4c6NuDgrWfLtt9b6qnp1qXhxm/brZy0pRo4MX7nV1FT3ldn63LxCINrafQAANbEhyR42S9KOHVKZMtLVV1tZMsnGqViyJGfHu/NOG6j5hhukYcNCGyuA2PfCC9b6+sMP7RnqkSO2/vBh6e673f28XluXmCidc47b0rpCBf/Sg06DnC5dpKVLpTp1wvJnhAZJbAAAAFOnjvTii/bKie7dc9ZyuU+f3A2EMnZs4HrbBRBJbADRh5bY8FGpkvWskqQJE2w8iXfflU48MefH2rrV3l+smJSSknmPLACFy5EjbqL6+uulN9/0375jhw3CuG+ftHOnrTvlFLcUkmTbJSk+3pLcvj05c/N5FVEksQEAABBlSGIDiD4ksZGJc86xl2Rd9KdNkzZuzNkxUlOlBx+0+Q4dpOXLrXfYF1/Y4JJ9+4Y0ZAAx4H//c+cHDZI2bcq4T9++Vj7QSWI3aSJVruxud5LYixZJX31lg9THLJLYAAAA8HXqqZajGT06+C6GmzfbjbvHI02enOcQSGIDiD4ksRGE996z/Mqtt0ojRuTuGE7CeudOGxBashq4GzfadzSAgmnDBmnlSvt3fttt0quvutucBHa3btL06e56pyyIIylJqlrVf1my5HaTJvkVeZiQxAYAAICvadMsR3PgQPDvOXjQfV8IUHA2iowYMUJNmzZV96xGCAUKA+emmSQ2shEXZ8mnv//OW51rJ4EtSY0aST17WjIbQMGzc6dUu7b9O3/nHf8Etq/nn/dfPuccqUoVd7lOHRvH59prpa5drQV3gUESGwAAAFGGJHYUGTJkiJYtW6Zp06ZFOhQgspyW2AzsiCDExUm1akkPPGADrI0ZE5rjrlxpD44l6dgx6fjx0BwXQPht3mz/nrdutTJCjttvt+k110hXXumuf/NNqUYNd/mxx6zWdfryIR6PJcKnT5eaNcvPvyDMSGIDAAAgr5xW2yVKhORwZIgARB/KiSAXiheXzjhDuuoq6Y03pO+/z9vxHnpISkiw3k99+kg1a0p794YkVABhNGeOPeg6+2ypc2dp1Sp3W0qKTS+/XEpMdNefdJL/cqVKNj3rLKlUKal1a+u1UWCRxAYAAEBeTZxo05o1Q3I4amIDiD4ksZEHcXHSDTfY/DPPSGXLSjfdlPPjLF5s0x493HVLl0qnnJL3GAGEz4ABloudMsVdV7++tHq1zRcrJrVvbz05HElJ/g1GnIT2mWdK+/bZ11OB/ooiiQ0AAFC4XX114PUPPeTf2iOQw4ftx/b8+fajuVu3kIREEhtA9CGJjRC5916bHjhgLaq//TZvx+vVywZ3GzNGevddGwDupZe4VIFo9fLL0ooV/uvOPFNq2FB67TVbbtTIWlfv2+fuU7Wq/bvu1ElatMje4ygUla5IYgMAABRuY8dmvNH1eqUJE4J7v5PXqVBBuv/+kIREEhtA9HFumgtFpgDhcPfd9nr9dWnoUGnXrtwdZ/9+6xH1+OPSiBG2rmNHadkyeyBdrFjoYgaQcwcOSNdfb8nnKlWkO+7IuM8HH/gP5li3rk337HHXOb/Xp061hiRlyuRbyNHJ+Q9AEhsAAKBwql3bP4m9fr0tV6uW9Y2vx2NdGqtVs27MN94oVa8ekpBIYgOIPrTERj656Sb7Dv3f/6SLLpKaNJH+/DPnx3ES2JJ0ySU2bdTIWnempISstxSAHBo6VPrwQ3s5brtNeuUVmy9WzBqDVKzobk9Ksum119r7fEsIFStWSB9OOQ+Rne9jAAAAFC7r1vkvO78Pf/hBato07OFIDOwIIBqRxEY+8nikCy+UtmyRPv44dMddvFhq107q3t1adP75Z+5bfAPI3sGD9sDotttsedUqK++T3qOPuvMJCTatUMFd5ySxe/SQli/Pe9mhAoFyIgAAAPDVtau9SpeOWAgksQFEH5LYCIMTTpBatJB+/tkeJl96ad6O51ue4OWX7eH0JZdYou3YsbwdG0BGH30kzZhh//bWrrXSPulNniyVK+culy1r00aN3HUnneTON2oklSyZP/HGFJLYAAAA8DVtmtXaq1MnYiFQTgRA9HFumkliIww6d7ZpmzZWsmvLFum//835cQ4dcuedlp8//miJ8rg4q5tdpEje4wVgfv/dnW/WzEr5NG8uLVnirnf+fTucJHabNvYA6+hR6z2BdEhiAwAAIMqQxAYQfZyW2AzsiDAqX166+WZLRh8+bEmxQYMy379aNUt4Z2fVKpsuXCgNHChddpkNAgkg93btkqZMcZdTUmw6apSV9XEUL27TTp2kmTOlIUPcbekT3PBBEhsAAABRhgwRgOhDORFEUIkS0vPPSwMGSFdfLbVvb62p03Pq6Aarc2erkz10qPTrr9IZZ9gUQM588IENcO7b4lqSrrxSatvWXfbt+fD111Y26LrrwhNjzCOJDQAAgECOHJHGjJH69bOb4jJl7Id3Vq+ioWlDTUtsANGHJDaigMdjrTolafVq6dRTpSZNpEmTbJ0zQFywjh51508+2aYHDlj5g2LFpOeeswQ6gIx27rTa8kWLSoMHW2+JxEQbRNXx9NP+7/H9N1q+vHT66eGItIAgiQ0AAID0VqyQ+veX/vrLzduEEUlsANGHJDaiTP360vr10t69Ur16UoMGbvmCvJg1y16SlUDYt0+6/HL/geiAwm7RIisHcuiQdNZZ9vCnZUsr0ePb2rp6df/3BepBgSCRxAYAAICvAwek3r1tRPW4OGuJXbmy9M47lrt56CGr+bdggTR3rq3r2DGkLUlIYgOIPs5NMzWxEWUSEqR166zF9Kef2sBwxYr5t7LOrauusumOHVa3d+1aG3wOKGy8Xmn3bqlCBWnOHOnMM6WDB23bN9/Y9MorM/+K+OEH69nw9tvhibdAIokNAAAAX2++aTepRYpY9+RTT5X++MOS2JL06KPuvosW2Q/2OXOkSy6xwadCgAwRgOhDS2xEsTJlrKTBpZdK8+fbg+ZQmjbNSou1bWu/Cfbts9IJQGHx5JNSxYrS6NFWS/7ffzPu061b5u8//XRLZOe0bj18kMQGAACAr6+/thzNRRdZAjsrrVpJU6dKVapId95pXShDgCQ2gOhDEhsxwOOxltItWkhffGEPpi+7zLblpbb1kiXS/v02P3261LixdNJJ5JJQeAwdatNrrpGOH7cyIY884m6Pi8tYKoSOOyFGEhsAAAC+li2z6bnnBt6e/ndj5cqWwD52TBo+PCQh8JMfQPQhiY0Yc+65Ntjca69J998v/fpr7o+1Y4c7/8wz0ubNNm7GggVS3brWSvXQIemzz6wsmdcrffWVDT4JxJqUFBvg3PHFFxn3eeklu/YdNWtaGR9JevFFm37ySf7FWCg5378ksQEAACC5I6rXqeOui4935w8cyPieTp1sOn16SEIgiQ0g+lATGzGqQgXpv/+VmjSxcgb9+wcepLFUKXe+cuXMj/f33+58+/ZWj/uhh6SePa0X1+uvS7fcYmNqDBhgCe9t20L11wD5a88e+w3cvbstT55spfN8nXaaXetVqrjrfMuE3HGHjR9zwQX5HGxh43z/RmDUeQAAAEQh5ybWt7FhYqI773vzmt7WrSEJgQwRgOhDS2wUAKefLn35pY150aiRtZZ2+CbhmjfP+bFnzbLpK69II0bY/MyZUo0a0sknW48tINp98YX1PJg928rk9eljLbN9tWtn08yS2JJUvny+hlk4UU4EAAAAvpyukZs3u+sqVbKWXJLdkKbn1MIuXjwkIZDEBhB9SGKjAGnfXlq+XOrbV3rwQauXPW6cu71Wrdwfe9OmwOucnl5ANPvrL3e+TRsrK3LmmdKHH7rr69WzqW+vxdw8+EEOkcQGAACArzZtbLpggf/6nj0th/Pcc9ZF0rFmjfT005bXadkyJCGQxAYQfUhio4B64glLMLdpI5UsaesaNQr9eUhiI9p5vdZLIb1XX/Vvae0krytWtB4IH3wgDRkSlhALN5LYAAAA8HX66e6ATL5uvdWma9ZIycnShRdaF8uWLd1W29dfH5IQSGIDiD4ksVGAOWNfbNggbdxoNX9DjSQ2otnOndJ//iMtXuy//tlnpYYN/cuD+Ca0O3aULrvMfQCEfEQSGwAAAL7OPlvq2lUqW1Zavdpd36mT9PDDlsfZtctqBk6aJO3fb9sHDbIf8SFQNCRHAYBQYmBHFAIVK9q0Rg0bBLJWLRsQUrJE9+HDuT/2FVdI770ntW2b9ziBvEpNld54w67vpCSpQwdp+/aM+w0YYNNKldx1eSm3gzwgiQ0AAABfpUpJ06YF3vbII1KXLtLIkdIff9ggTQ0bSlddJZ1/fshCIIkNIPrQEhuFzOmn2/Tzz22Qu4YNpcGDg3tvmTLuQ27HX3/ZgHjOPyUgkl5/XbrlFpu/9FJLYJcpIz30kDRsmPvAxhm8sVIl6bPPpNKl3Z4LCDOS2AAAAMiJnj3tlY9IYgOIPiSxUUidd569Dh+2wZ0PHpQSEqRRozJ/T5069rA7kJ9+st8R/FNCpKSm2oCmjs8+s+n06VLr1lZWJJALLsj/2JAFktgAAADw9e67Nm3USGrfPiIh0FcfQPQhiY1CLj5eGjdO+vRT6ZprpPr1pV69pFNOse2lSrn7Vq2a+XFOPz3zHl9AOLz2mrR3r7t87Jg9eGndOnIxIQgksQEAAOBr4ECrb71+fcRCIIkNIPpQExtI07GjtGqV9P33lth+8klrpd2pkz3nufDCrN+/fHl44gS8Xmn4cBugceVK6dRTpdtvz7hfly4Z1/k+mEEUIIkNAAAAX+XK2bRhw4iFQIYIQPShJTYQUIMG0gMPSC1bSjNmSP/+K91wgzR/vnTnndKtt2Z8z003SbNmhT1UFEKTJ1vt6/vuk5KTpalTbf3dd/sP1tiihTv/7bfW02DSpPDGimyQxAYAAICvunVtunt3xEIgiQ0g+pDEBrIVFyeVLWvzbdpIL7wgXX994FauN90U3thQOE2fnnHd669Lzz3nDtooSUlJ7nyfPtbToHPnfA8POeF8/5LEBgAAgCSde67lar7+OmIhkMQGEH1IYgO5cuKJ1kI7vcWLpUceCXs4KES8XhtI1FeTJtKNN9p8hQruet8kNqKU0xLb+T4GAABA4XbbbTa4zRtvWBfMCCCJDSD6OC2/SGIDuRKoTvajj0rr1oU9FBQCXq/0wQfSnDn+67t2dedLl3bn69QJT1zIA8qJAAAAwFdCgvTjj1LjxtKZZ1o34GnTpF27wtbwoWhYzgIga5s22YcBLZ7M0qU2ZWBHIFc+/ljq0SNjGZEPP5Suvda/tAOQU16vDTTavLlUrJjUu7e0aJFtK1NG2r/f5n1rX59yitW9btBAqlw5/DEjh5zv35QUacyYyMaC6NamjX0YAACAgq1IEXfe65VGjbJXMDwe6dixPIdAEhuIBpdcIv3yS6SjiD7Fi0c6AiAmxcVJ7dtnXP/gg9J770l//hn+mFBwvPSSdNddUq9elpB2EtiXXGLrBg2yZWfsF0kaOlQ6/3wrJUInmxhQooRN9++Xrr46srEgupUtK23fLsXHRzoSAACQn9I3uoxAI0yS2EA02LLFph07SuXLRzaWaJGQIA0YEOkogJjVurU0bJiVEfG1fLl06JCbowJy4vhxS2BL1rLaaZAxe7bUoYOtc/jWvvZ4rGY7YkTdutIDD0i//RbpSBDNvvtO2rdP2ruXLhYAABR0w4ZFOgKS2EBUOH7cpi+9FLj5JADkwjXXZExiSzbI3s8/SyefHP6YENvee89/+fhxqyTQoYMt+/YypPZ1DPN4pCefjHQUiHbx8dKRI9LBg5GOBAAA5LcoSGJTcBaIBk4S2/fuHwDyqGZN6Y47Mq4/eFCaMSP88SC2jBljra6dnoLLlkkPPZRxv27d3HmnDnaJElKpUvkfI4AIKlnSpiSxAQBAGJDEBqIBSWwA+cDjkV58MXBr7DvvlB57LPwxITYcPmylkF98UZo/X7rhBisHsmmTVL26/76+LfqrVJHWrJE2bgxvvAAiwKlLdehQZOMAAACFAklsIBqQxAaQj7p0kYoGKCA2bJi0Z0/Yw0EMWLDAnR8/XnrrLZtv21b68Uf/muq+Azg6yxUr5nuIACKNltgAACCMSGID0YAkNoB81KOHtHNn4G2PPSZt2xbeeBD9Pv3UnX/qKZvefrs0b57UtKmUmOhu9x3AEUAh4iSxaYkNAADCgCQ2EA1IYgPIZwkJUvnyGde/9JJ0663hjwfRa/Vq6Y03Mq6/6ip3/sgRd75GjfyPCUAUcrpk0BIbAACEAUlsIBqQxAYQBr/9Jt12W8b1CxdK+/eHPRxEGa/XBnNs1Uo6etR/W0KCO2ijJLVubdOaNQOXqgFQCFBOBAAAhBFJbCAakMQGEAa1a0uXX55x/erVUqVK0u+/hz8mRNacOVLnzjZ97jkbzHHfPqlMGalbN3e/k07y/4oaPVp65RVp0qTwxwwgSlBOBAAAhBFJbCAakMQGECZt2lht4/QOH5Zmzw57OIig1FSpY0dp5kzpxhulRx+19bfdJv35p9Sunbtv+sEba9WyMjRNm4YvXgBRhnIiAAAgjOgACkSD1FSbxvFcCUD+8nisDvZ772Uc7PGGG2yQx9q1rWXuiBE8WyvIvvjCnf/tN5u2aGHXh8fD4I0AskFLbAAAEEYksaPIiBEjNGLECB3xHS0JhQMtsQGE2fvvS/37WwtsX8OGufMXXCCddlpYw0KYHD4s/ec/Gdf37WsJbEkqV85dTxIbQAbUxAYAAGFEs88oMmTIEC1btkzTpk2LdCgIN5LYAMLszDOzH8zx66+lVavCEw/C5/hx6cEHrRZ6el27uvP16rnzvoM6AoAkyokAAICwIokNRJpTSkQiiQ0grIoWlUqVynz7q6/610VGbNqzRxo/3pLXf/whNWkivfCCbbvxRv99e/Z053v1kr79VvrpJ+nkk8MVLYCYQTkRAAAQRpQTASLNaYUtkcQGEHbLl0tPPCG9/Xbg7bt3W+mJ+PjwxoXQOH7cBmXcs0f68ENrgb12rQ3BcMcd0rXXSm+8Yfu+9JL/11BcnNSnT0TCBhALnCT2/v0Za1MBDo9HKl480lEAAAoAkthApJHEBhBBtWpZ7evMktiSVKaM9NlnVkMb0W33bqlsWWtl/8030uDBlsCWpAcekNatk6pUsRbZlSpJ27e7761VKxIRA4hZTjmRV1+1FxCIxyM99ZR0332RjgQAEOMoJwJEGklsABF22mnSXXdlvv3Ysay3Izp8+KFUrZrUu7c0Y4Y9dNi82d2+bp1Nr73WEtiSlJjobvedB4Bsde3qJrKBzHi9NsgGAAB5REtsINJIYgOIMI9Hev55K2s6YkTgfYoWlc4/X7ruOhsUEtHj+HHp8celRx+15Z9+ko4csfXnnitVqCCNGuXuf+qp7nyxYlK3btKGDVKnTuGNG0CMO/VU6/5x5EikI0G0mj5dOuccu04AAMgjkthApJHEBhAlevWSRo4MXNp0xQp7ffGFNapC5KxdK/XoYf+fJk+2Bw+vv+6/z4wZ9nDitdekL7/039axo//ylCk2xnBRfhUCyKkSJWiNjczVqGFTktgAgBCgnAgQaSSxAUSJvn2lvXulAQOy3u/jj63ECPJfSorVtR471pb37JGuuEJav17autWS2U4C+8UX/d/bvLnlDypUcNc9/bRUqpT/fnFxJLABAPnA+QIiiQ0ACAGS2ECkpaa683H8kwQQWcWLW9mQrFx6qdVfRv67+mobdHPQIOndd6W6daVZs9zt//xj0wsvlO64w/+9PXrYtHx5d12XLvkbLwAAaZwvoEOHpIMHIxsLACDmkTEDIs1piU0CG0CUOPtsK0eRlVmzpP37wxNPYXD4sPTYY9K0abZ86JB02WXSJ5+4+wwcaC2xa9WSOnf2f/8bb2Q85oMP2jQhwV1Xp04IgwYAICtly7r3OLTGBgDkEVkzINKcJDalRABECY8n+xa706fbveno0eGJqaC7+mpp2DDp8sulXbukDh2kjz7y38frlRITpfnz7UGD45ZbpIoVMx6zcmWbli3rrqtWLeShAwAQWFyc2xqbJDYAII+ogAhEGklsAFFqwQLpiSek8eMzblu+3KbXXWcJWATnyBErD9Ktm9WsPn5cGjfOLc+yebN0xhnS4sWWmB4+3Mq3ON54Q6pa1b/OdfPmGc/jW+O6eXNLkNepQ6cfAECYlS8v7dwp9e7NIKDIXOXK9vS+du1IRwIgipHEBiKNJDaAKHXyyZZgLVcu831SU6V27aS77pIuvjh8scWqK6+UPv1U6tpVmjBBOvNMae5c/30WLrTpZ59ZXWvfJLbTQt63znVSUsbz1K3rzns80iOPhCJ6AABy6KSTpFWrpA0bIh0JotnKldJ330k33BDpSABEMZLYQKSRxAYQxcqWtUTrtGlWpzmQ+fMtSUoSO3OpqdJ771kCW7Ka4/fcYwnsEiWk7t2l77939z/lFFuXXo0aNs0sif3JJ1YL27eWNgAAEfPBB/ak23cwe8DXsGHS5MnWXQ0AskASG4g0ktgAopjHI02c6M5nZv16adQoG4ywZMnwxBbN9u+XXn1V6tfP6lD37i3Nm+duL1HCWrlL0qRJUseOUvHi7vYJE7L+7+31uvO+PW8vusheAABEhfh4+5IDMlO9uk1JYgPIBklsINJIYgOIEQ0aWI/gQA4elK691gYlvOee8MYVjU4/XZozR/rlF6tfPW+eJalbtLBa406r9iZNrLRIepUqZVznW8+6fXsr81K3ruUHAAAAYpLzFJ8kNoBsMLwPEGkksQHEiLlzpZdeynqf6dOlHTv8WwoXJv/+K512miWwJWvF/tFHNj9jhtuq3dGtW8ZjJCQEPrZvCZGyZa28qG/rbgAAgJhDEhtAkEhiA5FGEhtAjKhQQerVK+t9Fi2yAeafey48MUXaCy9I559vgzGuWWMtrSdP9t8nNVVq29ZtPe3rwgszHjMx0X/5ggts+tBD/uvLlpWKFctT+AAAAJHl/JghiQ0gGySxgUgjiQ0ghjRuLP33v9LllwfevnmzTe+7T6pXz6YF1VdfSXffLX3xhQ1s2bmz9PffVqP66af993UGafRNOlerJp16asbj+ra4lqx29i+/SLfeGsroAQAAogAtsQEEiSQ2EGnOSN1x/HMEEP08Hun++6V3381+37VrpWeflVq3lm6/Pd9DC5vUVOnHH6WrrnLXffONtGWLVLSolVS58kr/9/Tvn/E49er5LzdoYNMrrvBfX6qU1KkTXxMAAKAAIokNIEjcDgGRRktsADEoLs4StV26ZL/vokXSK69Il14q3Xuv+7EXK774wgZQHDjQBmQ89VTpjDOs/nV6t9wiJSX5t6Zu21Y65ZSM+6YvGzJ9uvTBBwUr4Q8AAJAlJ4l99Ghk4wAQ9YpGOgCg0COJDSBGOa2xPZ7g9v/4Y5vu2yc1aiRdf721Mo5ma9ZY8nrfPmndOktQT59u284/31pj9+tny1WqWI1sSSpZ0j1GcnLgY6evL169unTZZSEMHgAAINrREhtAkEhiA5FGEhtAjOvaVZoxI/j933zTplu2SB06WKvm0qXzJ7ac2LXLGgFVrSodO2YtsB96yBLYjqeesukbb0g33CAtX+5ua9MmcEI/IcF/eelSacoU6aabQv83AAAAxBSS2ACCRDkRINJIYgOIcRMnSu+/n/P3PfusdN550gMPSMuWWeI4Un7/XapVywZb/PFH6eabpYsvllautHVOPeojRyxRffHFtly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+ "text/plain": [ + "
" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], + "source": [ + "only_trigger_df = df[df['TRIGGER'] == '1']\n", + "rate_index = pd.to_numeric(only_trigger_df['inst_shell/inst_network_top/inst_network_stack/inst_roce_stack/inst_rdma_flow/inst_DCQCN/ecn_rates_index[4:0]']).to_list()\n", + "RC_gap_cycles = pd.to_numeric(only_trigger_df['inst_shell/inst_network_top/inst_network_stack/inst_roce_stack/inst_rdma_flow/inst_DCQCN/Rc[15:0]']).to_list()\n", + "RC_rate_hz = [1/((4*i)/1000000000) for i in RC_gap_cycles]\n", + "\n", + "rate_list = [rates[i] for i in rate_index]\n", + "\n", + "fig, ax1 = plt.subplots(figsize=(16, 7))\n", + "\n", + "x_pre = range(len(RC_gap_cycles))\n", + "x = [(i * (ila_tigger_interval)* 4)/1000000000 for i in x_pre]\n", + "\n", + "ax1.plot(x, RC_rate_hz, color='blue', label='Line 1 (left)')\n", + "ax1.set_ylabel('Sending rate [Hz]', color='blue', fontsize=20)\n", + "ax1.set_yscale('log')\n", + "ax1.tick_params(axis='y', colors='blue', labelsize=20)\n", + "\n", + "# For printing packet gap in cycles instead of sendrate\n", + "\n", + "#ax1.plot(x, RC_gap_cycles, color='blue', label='Line 1 (left)')\n", + "#ax1.set_ylabel('time between outgoing packets [cycles]', color='blue', fontsize=20)\n", + "#ax1.tick_params(axis='y', colors='blue', labelsize=20)\n", + "\n", + "ax2 = ax1.twinx()\n", + "\n", + "ax2.plot(x, rate_list, color='red', label='Line 2 (right)')\n", + "ax2.set_ylabel('ratio of packets ECN marked', color='red', fontsize=20)\n", + "ax2.tick_params(axis='y', colors='red', labelsize=20)\n", + "\n", + "# Labels and title\n", + "ax1.set_xlabel('Time [s]', fontsize=20)\n", + "ax1.tick_params(axis='x', labelsize=20)\n", + "plt.title('Default Parameters, Sending rate', fontsize=22)" + ] + }, + { + "cell_type": "code", + "execution_count": 5, + "id": "e625b037-0c5f-4e47-bd6b-166350989e4d", + "metadata": {}, + "outputs": [], + "source": [ + "fig.savefig(savepath, dpi=400)" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "82e26e2a-0bee-458c-8e86-ab051748ff38", + "metadata": {}, + "outputs": [], + "source": [] + } + ], + "metadata": { + "kernelspec": { + "display_name": "Python 3 (ipykernel)", + "language": "python", + "name": "python3" + }, + "language_info": { + "codemirror_mode": { + "name": "ipython", + "version": 3 + }, + "file_extension": ".py", + "mimetype": "text/x-python", + "name": "python", + "nbconvert_exporter": "python", + "pygments_lexer": "ipython3", + "version": "3.12.3" + } + }, + "nbformat": 4, + "nbformat_minor": 5 +} diff --git a/examples/Congestion_Control_Test/Test_script/.ipynb_checkpoints/Reduction_factor_calc_scrip-checkpoint.ipynb b/examples/Congestion_Control_Test/Test_script/.ipynb_checkpoints/Reduction_factor_calc_scrip-checkpoint.ipynb new file mode 100644 index 000000000..d89f93525 --- /dev/null +++ b/examples/Congestion_Control_Test/Test_script/.ipynb_checkpoints/Reduction_factor_calc_scrip-checkpoint.ipynb @@ -0,0 +1,75 @@ +{ + "cells": [ + { + "cell_type": "code", + "execution_count": 5, + "id": "e1ead512-fdcf-4470-886e-f076ae17f3a2", + "metadata": {}, + "outputs": [], + "source": [ + "#Generator Parameter\n", + "g = 1/16\n", + "#Number of bits for left shift (used to circumvent floating point calculations)\n", + "precision_bits = 7\n", + "#number of steps to print\n", + "reduction_steps = 29" + ] + }, + { + "cell_type": "code", + "execution_count": 7, + "id": "34f5498c-decc-48ff-b3a0-41dbb827c04f", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "[256, 241, 228, 218, 209, 201, 194, 188, 182, 178, 173, 170, 166, 163, 161, 158, 156, 154, 152, 150, 148, 147, 146, 144, 143, 142, 141, 140, 139, ]\n" + ] + } + ], + "source": [ + "a = 1.0\n", + "j = 1\n", + "prec = 2**precision_bits\n", + "str_list = \"\"\n", + "for i in range(0,reduction_steps):\n", + " str_list += str(round(prec *(1/(1-(a/2))))) + \", \"\n", + " a = (1-g)*a\n", + "\n", + "print('[' + str_list + ']')\n", + "#remove the last comma :)" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "e8bc9f64-7430-4096-bd68-41c1fe4f8e82", + "metadata": {}, + "outputs": [], + "source": [] + } + ], + "metadata": { + "kernelspec": { + "display_name": "Python 3 (ipykernel)", + "language": "python", + "name": "python3" + }, + "language_info": { + "codemirror_mode": { + "name": "ipython", + "version": 3 + }, + "file_extension": ".py", + "mimetype": "text/x-python", + "name": "python", + "nbconvert_exporter": "python", + "pygments_lexer": "ipython3", + "version": "3.12.3" + } + }, + "nbformat": 4, + "nbformat_minor": 5 +} diff --git a/examples/Congestion_Control_Test/Test_script/Output_Grap_Script.ipynb b/examples/Congestion_Control_Test/Test_script/Output_Grap_Script.ipynb new file mode 100644 index 000000000..86e2cadbd --- /dev/null +++ b/examples/Congestion_Control_Test/Test_script/Output_Grap_Script.ipynb @@ -0,0 +1,134 @@ +{ + "cells": [ + { + "cell_type": "code", + "execution_count": 1, + "id": "f5274104-49ba-4f8d-9509-5322e1aa2ca5", + "metadata": {}, + "outputs": [], + "source": [ + "import matplotlib.pyplot as plt\n", + "import pandas as pd\n", + "import numpy as np\n", + "import sys" + ] + }, + { + "cell_type": "code", + "execution_count": 5, + "id": "8af48534-32bc-4d73-98a1-eba531c0bafe", + "metadata": {}, + "outputs": [], + "source": [ + "#enter path to csv file\n", + "path = './example_ila.csv'\n", + "savepath = './example_graph.png'\n", + "rates = [(1/10000), (1/100), (1/30), (1/25), (1/20), (1/10), (1/30), (1/40), (1/40) ,(1/100), (1/100), (1/150), (1/150), (1/200), (1/200), (1/10000)]\n", + "ila_tigger_interval = 40000\n", + "df = pd.read_csv(path)" + ] + }, + { + "cell_type": "code", + "execution_count": 6, + "id": "b6981655-142b-4371-82fc-d0be6ecf0613", + "metadata": {}, + "outputs": [ + { + "data": { + "text/plain": [ + "Text(0.5, 1.0, 'Default Parameters, Sending rate')" + ] + }, + "execution_count": 6, + "metadata": {}, + "output_type": "execute_result" + }, + { + "data": { + "image/png": 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8km2dQ4cOWStUqJD599GkSRNrYmKide3atdnWXbBggVPloysHDhzIrO4sV66cdcWKFS7X279/v/WSSy7J3O+WLVuyreNYkT1x4kQPz4gxf/78zIrNNm3aWPfv3+9yvWXLllnj4+Otkqw1atRwWS3r+Hek/68IdvWatlrN67BkyZJWSdaLLrrI49/O6dOnXT63gZSUlGRNTEzMjL1s2bLW5557zrp+/Xq3P4MnGzZssMbExGT+vbn6XVmtVuvmzZutlSpVskqyxsfHW48fP55tnaxVuf3797empqZmW+/TTz/NXKdRo0Yu97ds2bLM33dcXJx16dKl2dY5cOCAtX79+k77DEQltv6/cvjUqVPZ1lu0aFFmhXaZMmWsaWlp2db566+/rNHR0VZJ1ujoaOusWbOyrZOcnGy9/PLL3VZJ+yrrt33i4uKsP//8s8fHHD9+3OXzmnW7devWtUqylixZ0pqUlORyPV+P+Y899ljm+sOGDbOmpKS4XG/s2LGZ69188805bhcAAOQdktgAAASIP0nsO++8023yecOGDZn33X777Tluq3379pkn/K4SON4msb3l+HX0F1980eU6hSmJff78eevdd9/tlMzJ2t7FGx06dLBKstauXdvl/VmT2N9++63P+3Bn/PjxmdtdtmyZy3Uck9iO7VKyevHFF53inDZtmtt1L7vsssz19u7dm+3+Bx54IPP+JUuWePwZtmzZkpnsu/vuu7Pd72sSu1mzZplJW1cJVEcfffSRx5/X8e+oWbNmHj8oOnjwYOa6Dz/8cI5x5ocZM2a4bHVRrFgxa7t27awjRoywTp8+3Xrs2LEct9W3b1+rZFqF/P333x7X/fHHHzP39corr2S73/F1X7duXZfHP5vWrVtnruvqAwlbXJKs7733ntvtbNiwwem5CEQSu3Tp0h6fu/79+3t8fTq2UXn88cfdbufo0aPWhISEPEliv/XWW7neVlY///xz5nY/++wzl+v4csw/fPhwZqus7t2757j/m266KfMDMXcfXgEAgLzHxI4AAISAUqVKZY6PHz/udJ/jhFWPPPJIjtu69dZbJZlJ0n777bcARehe7dq1VaFCBUnSypUr83x/oWLZsmWaOXNm5mX69Ol6+eWX1aRJE33wwQeZ6z333HO5al/SoUMHSear+Vn/JrKqXr26rr32Wp/3kdO+Je9+p/fdd59X2ypfvrz69evndl3H1hu21jk2VqtVU6ZMkSS1bds2xzYd9evXV6tWrSSZifn88ccff2jt2rWSpDvuuEOlS5f2uP5NN92U2TYhp30PHz5cERHu35IXK1Ysc2yLIdj69u2rRYsWqVmzZk63nz17Vr/++qveeecd9e/fXxUrVtT111+vP//80+V2Tp06lTnBYt++fZ1albhy+eWXq2LFipJyfl7vuecexcbGetyWTdb40tLSNHfuXEmmFdAdd9zhdjuXXnqprrjiCo+x+OrWW29VYmKi2/s9xS5JM2fOlCRFRERoxIgRbrdTpkwZ3XLLLbkP1I2iRYt6fM585evxKCfTp09XamqqJOnhhx/Ocf3BgwdLki5cuKAFCxb4vX8AAJA79MQGACAEWK3WzLHFYnG6b8mSJZKkIkWKaPPmzdmSe1n9888/mePNmzerU6dOfsV24MABffrpp1qwYIE2b96skydP6uzZsy7X3b9/v1/7CidPP/20x/ujo6M1evRojRo1Ktt958+f14wZMzRz5kytX79eBw4cUFJSktv+tPv37/eY1Grfvn22vxtP1q9fr88++0wrVqzQ33//rTNnzigtLc3tvj2Ji4tz6quele0DDklq3ry5x4St47onT550um/z5s2ZyfxSpUplJuo8iYyMlCTt2rVLqampmT3ifWV7DUomkeXNvosXL65Tp07l+HrNKRlfokQJtWnTRitXrtSCBQt0zTXX6N5771WXLl0UExPjVfx5oUOHDvr999/122+/aebMmVq+fLnWrl2r5OTkzHXS09M1Y8YMfffdd/rggw80dOhQp20sX748828+NjbWq+c1Pj5eBw8ezPF5bdu2rcf7q1SpkjnO+re2YcMGnTt3TpJ5bXlKhkvSZZddpvnz53tcxxf+xH748OHMHt0NGjRwek250rVr18ze8IHStGlTFS9e3Ov1t2/frilTpmjJkiX666+/dPr0aaWkpLhcNxD/Yxxfz4cPH87x7y7r/1QAABAcJLEBAAgBjomIrMnK3bt3SzKT8vXt29en7Z44ccKvuD788EM9+OCDbpPWWZ05c8av/YWzmJgYJSQkqF69eurcubOGDh2qWrVqZVvvr7/+0nXXXedTMiSn59UxqeXJ+fPnNXz4cH388cdOH5z4s+/SpUt7TKA7JgA9JeKzrmurlLSxvQ4kad68eZo3b57HbWV14sQJVapUyafHuNq3r5OX5vQa9OZ3N27cOHXr1k2nT5/WnDlzNGfOHBUtWlQtW7ZUu3bt1K1bN3Xt2tVp0rz80rp1a7Vu3VqSmQx269atWrFihWbPnq3vvvtOGRkZmROF1q5d2ylp7/i8Tpo0SZMmTfJ6vzk9rzl9+8HT39qBAwcyxzlVh3u7ji8CFftFF12U475cHaP85e3xSJJGjx6tl156SefPn/dq/UD8j3H8u7N9c8lb/v5PBQAAuUcSGwCAEOB4Ul22bFmn+06dOpXr7dqqCXPjq6++0t133515vW3bturcubNq1qypkiVLOiVS7rzzTh09elQXLlzI9f7CzcKFC9WlSxefHnP69Gl169YtM9FUqVIlXX311WrQoIHKly+vIkWKZFYqT5s2TdOnT5ekHJ/XokWLerX/kSNH6qOPPpJkKsV79OihVq1aqUqVKoqLi1N0dLQk6ciRI7rrrru82renymp/1s3Kn9eB5N9rIS9fg9787po1a6YNGzboueee05dffqnk5GSlpKRoyZIlWrJkiV555RWVL19ejz32mEaMGOHX8+yPiIgINWzYUA0bNtTtt9+u9evX64orrsg8Njz//PP66aefMtf353lNT0/PMZbc+vfffzPHju1c3ImLi8v1vlzxJ3bHSvhgxC55fzx6/fXX9dxzz0kyP3PXrl3Vvn17VatWTfHx8U7fNLB9gBuI/zHB+p8KAAD8QxIbAIAgy8jIcOpdbatqtLG1JShdunSOvZED6YknnpBkWjJ8++236t27t9t1hw0bFrD9FuRE+HvvvZeZwL755ps1YcIEty0hli9fHtB979u3L7NXd+XKlbVw4ULVqVPH5bqbNm0K6L4DwbE9wYMPPqg333wzKPuePXu2x9dCXqlevbomTJig999/X7/99ptWrFihZcuWadGiRfr33391+PBhPfDAA9qwYYMmTpyY7/G50qRJE40dO1Y33XSTJGnx4sVKT0/P/LDE8Xl95513PPZWz0+OcXnzLRTHxHGwOSalQzn21NRUPf/885LM871gwYLMHvZZBTpGx9/vmTNnFB8fH9DtAwCAvMHEjgAABNmcOXMyvyJdvHhxNW/e3Ol+21ezT5065VQhmJd27dql7du3S5L69OnjMWl35syZHL9i7Vi1nVMl27Fjx3yINLz8+OOPkqSoqCi9++67Hnsa79q1K6D7/vnnnzP7Dz/22GNuE9h5se9AcGxRYOv5Wxj2nVVsbKw6deqkRx99VHPmzNHRo0f14YcfZiaGJ02apN9//z2oMTrq3r175jg9Pd3p9R1Kz6ujypUrZ45tx0FPvFknvzi2zNmxY0eO6+/cuTMvw3FrxYoVmf/P7rrrLrcJbCnwx6NQ/bsDAACekcQGACCI0tPT9eKLL2ZeHzJkSLa+tp07d5ZkKrZ/+OGHfInr0KFDmeOc+r3+8MMPbicktClVqlTm2HGSLFdWrFjhRYSeOX4d39vez/nB9rwmJiY6PSdZpaamatGiRXmybynn32kgJ6kLlCZNmqhkyZKSTCsXdxNResuXvxHba1AKveemSJEiuvPOO3XPPfdk3rZ06dIgRuTMlly3cayC7dixY2Y/9e+//z5f4/Lk0ksvzfzgbfny5Tn+rS1YsCA/wvJK+fLlVbVqVUnSli1bnF73rixcuDA/wsom0MejgvJ6BgAA7pHEBgAgSC5cuKB7771Xa9askWT6iD722GPZ1nOceOr555/PNpFXXnD8SrqnKsNz5845JeHdufjiizPHP//8s9v1FixYoA0bNngZpXuOibJQ/Kr/kSNHPE5QNnbs2IC3jvH2d7pz505Nnjw5oPsOhMjISN18882STLX+mDFj/NqeL38jzZs31yWXXCJJmjt3bsBbvQRCzZo1M8feTpKXG8eOHcvxQytHs2bNyhxXr17dqXVDuXLldNVVV0mS/vjjD02dOjVwgfohNjZWPXv2lGT62E+YMMHtun/++WfmNyxCxbXXXivJfPD5zjvvuF3v2LFj+vTTT/MrLCfeHo9Onjypt99+O8ft+fJ6HjBgQOaHFGPGjCnQ3/4BAKAgIYkNAEAQrFq1SpdddlnmJHsWi0WTJ092+hq7TatWrdSvXz9J0saNG3Xttdfq6NGjbrdttVq1fPlyPfTQQ7mOr379+plJgdmzZ7usjk5JSdGgQYO0cePGHLdnS1RJ0ksvveQy/k2bNjkl7P3hmNBbu3ZtQLYZCC1btpRkfkdPPvmky3WmTp2qp59+Os/2LUlvvPGGyyT53r171bt375BK/Dt64oknlJCQIEl66qmn9Pbbb3tMqCYnJ2v8+PEuk6O+/I1YLBa98sorkszvrk+fPh4/jJGkAwcOaPTo0V69PjxZt26dnnvuOR08eNDtOsnJyZoyZUrm9SZNmvi1T0++/vpr1a9fXx988EGObYQWLlyoBx54IPP6Lbfckm2dl156KbOtzh133JFjIvvEiRMaM2ZMjs+/v0aNGpVZJf7oo4+6PAYePnxY/fv3D7k+/vfee29mBfwbb7yh2bNnZ1vn7Nmzuummm/yeMDW3WrRokfn8jh8/3mXrkxMnTqhPnz6Z8wh44svruUqVKhoxYoQk8zq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GAAAIKySxgRDVrZs5rxozRlq+POf1f/3V9NG2WKTLLgtICBwWgDDSqJFUo4b5x75hQ7CjARByqMQGAABAGCOJDYSoxx4zbQLS0kxS+v77pfXrnQuGrFZz2wMPmKR3aqoUE2MeGwBRAdkKgHxTrpy0e7d0+nSwIwEQskhiGzwPAAAAYYUkNhCi6teXJk+WBg2Szp2T3n3XXGJipNKlzbnX8ePmPskktKOipIkTzWMDgMMCEGbi480yKSm4cQAIQbTNcI3nBQAAICzY3raRxAZC0I03mlYizZubF6vVaiqzDx6UDhwwY9vtzZpJy5ZJAwYEbPdUYoeQcePGady4cTpn+9QCcME2uSNJbADZ0E4EAAAAYYxKbCDEtWwprV4trVkj/fyz9Mcf0okT5r5SpUwf3O7dzXoBRhI7hAwfPlzDhw/X/v37VbVq1WCHgxBlq8T+99/gxgEAIY+JHQEAAMKKLYlNTQYQ4lq0MJd8xGdbQJihnQgAt6jEBgAAQBijEhuAO1RiA2GGJDYAeIlKbAAAgLBCEhsII/v3S4cOSWfPmvYhRYvm6e44LABhhiQ2ALeoxAYAAEAYI4kNhLikJOnpp6WqVaXq1aXWraWuXaVdu5zXmzbNTAQ5bFjAdk0lNhBm6IkNwC2S2M54HgAAAMIKSWwghP39t9Szp7Rzp/O3XV2dd7VpIw0aZNYbPFjq0MHv3XNYAMIMldgA4CPaiQAAAIQFkthAiEpNla6+WtqxQypWTHrkEem779yvX6OGqdCWpNmzAxICldhAmCle3CxJYgPIhkpsAAAAhDGS2ECIev99aft2KS5OWrpUatIk58dcdZW0YIG0YkVAQuCwAISZ0qXN8p9/ghsHAIQ8JnYEAAAIK7a3bSSxgRAzY4Y5vxo50rsEtiQ1bmyWf/8dkBA4LABhpmVL8w99xw4S2QCyoBIbAAAAYcxWic3bWSDEbNlilldc4f1jEhPN8tSpgIRAEhsIMyVLSs2amfGiRUENBQBCG5XYAAAAYYV2IkCI+vdfs7T1uPVGWppZRkcHJAQOC0AY6tLFLBcuDGoYAEINldgAAAAIYySxgRBlq6revdv7x2zaZJYVKgQkBA4LQBiyTfBKJTYAJySxnfE8AAAAhBWS2ECIsrUEWLLE+8dMmWLOydq2DUgIHBaAMNShgxQZafpi79sX7GgAAAAAAPAfSWwgRN1wgyma+ugjae/enNd/+217wnvgwICEwGEBCEMlSkjNm5sxLUUAZKISGwAAAGGMJDYQom65Rbr0Uik11fS4nT/fee4hi8VcX71auvlmadQoc1vHjtJVVwUkBA4LQJhybCmSliYdPx7UcAAg9Dgm85ncEQAAIOSRxAZCVESENHu2VKWK6Yvdq5epsLSdc3XpIsXFSW3aSNOmmfOvWrWkL78MXAgB2xKAfOU4uWOvXlKlSr711wdQAFGJDQAAgDBmeztLEhsIQdWqSevXm/YgERFScrJ50Vqt0tGjpkrb9iK+8UZp1SqpXLmA7T4qYFuC38aNG6dx48bp3LlzwQ4FYaBDBykqyiSubcnrsWOlt94KZlQAQgJJbCNrJTbPCwAAQEizVWLztg0IUaVLS59/Lr38sjR3rrRmjXTkiHThgpSYKDVtKvXuLdWtG/Bdk8QOIcOHD9fw4cO1f/9+Va1aNdjhIMQVLy61bCmtWGG/7c8/gxcPgBBAywwAAACEMdqJACHqzBnTPsSmenXpnnu8e+yiRfZ2An7gsACEsazHgA0byGEBhRrtRJzxPAAAAIQVkthAiLr6atMuxFc//2x64AYAhwUgjNkmd7Q5elTaujU4sQBASOMTPgAAgJBHEhsIUcuXS9dfL50/7/1jfvxRuuYaKSUlICFwWADCWLt2UnS0823r1gUnFgAhgEpsAAAAhDGS2ECIioyUvv9euvVW79afN0/q08dUb1eqFJAQOCwAYSwuTmrVyvm2PXuCEwsAhJysEzsCAAAgpJHEBkLUhAlmOX269J//eF53zhxTtZ2aKlWpIi1cGJAQOCwAYS5rS5Hdu4MSBoBQQCU2AAAAwhhJbCBE3XKLNGaMOef86CPpiSdcrzdrltSvn5SWJlWrZiZ1rF07ICFwWADC3H/+I/XvL91xh7lOEhsASez/RyU2AABAWLG9ZSOJDYSgkSOlp582L9RXX5XefNP5/m++kW68UTp3TqpRwySwa9UK2O45LABhrlIlado06aabzPXt24MbD4AgIlELAACAMGarxKYmAyFjzx5p1Cipfn3T07V0aallS+n116WzZwO3n/nzpb59TfuN2Fiz7NvX3O6tFSuk226T6tWTihc326lYUbrySunjj01y2V/PPScNH27OPR95xN5m5MsvTWIqPd0krhctMonsAIoK6NYABE3jxma5c6d05IhUrlxw4wEQBLQTccbzAAAAEFZoJ4KQMmeONGiQdOaM/bazZ6U1a8xl/Hhp7lz/2mVkZEh33il98onz7f/8Yy4zZ5qv3n/4ofsXhtVqqqTffTf7fYcOmcuPP0pjx5oJF6tVy328ktnPyZPSF19Id90lrVtn4jt/3jwXCxZIVav6tw8XOCwABUTp0lLDhmb866/BjQUAQg5V6gAAACGPJDZCxrp1pnfrmTOmqvmll0yyZcECadgws862bdLVV0tJSbnfz5NP2hPYTZtKU6dKq1aZZdOm5vbx46WnnnK/jVdesSew4+OlZ581Setff5UmTpQuucTct2mTiff8+dzHazN5stnWhQvS//5ntlmnjpnEMQ8S2BJJbKBAadLELGkpAhRSVGIDAAAgjJHERsgYOVJKSZGiokxC+IknpLZtpW7dzMSGr71m1tu2LXtvaG9t2ya98YYZt2ghLV8uDRhg2pUMGCAtW2Zul0z7ElfJnvR0eywxMdKSJdLo0dLll5t4hwwxCfnWrc06f/5pqrv9FRkpffWV1KmTOQ+tX19avFiqXNn/bbtBOxGgAClf3iyPHAluHAAQEpjYEQAAIKyQxEZIWLVKWrrUjG+/3SSDsxo1ylQ5b9li2nQ8+aQUHe3bft5+214V/e67UtGizvcXK2Zub9vWrPfWW9K4cc7rbNkinTplxr162asbHUVFmST8tdea6ytWSDfc4Dqmbt18+xmSk815V1SUfbK2rCwWU8HuJ5LYQAFi64N99Ghw4wAQJFRiAwAAIIyRxEZIcKxUHjrU9ToREdKtt0qPP26SyAsXSldc4f0+rFZp1iwzrl9fatPG9Xpt2piJGv/6y6z/3nvO53uOkzXWquV+fxdd5PoxWS1aZLbvbRGQbd1Nm7I/xnZfgM5PSWIDBYgtib1kidS9u/T001LnzsGNCUAQkMQ2qMQGAAAIKySxERKWLTPLuDipeXP36zkmXJYv9y2JvWuXdOBA9u24289ff5mJHnfvlmrWtN9Xp449Wbxzp/tt7NhhH9er5369Tp1C9nySJDZQgNiS2Dt3msuCBeRtgEKFFzwAAADCGElshIQtW8yydm3TJsOd+vWzP8Zbmze73o43+3FMYpcsKQ0cKH3xhfTdd9LGjdKllzo//vx56b//dV7fnUWLvAo/GEhiAwVI2bLBjgBAUNFOxBnPAwAAQFjh7SzyRFKSdOaM/XpsrLm4kpoqHTtmxlWqeN5uqVKmWjs5Wdq3z7eY9u+3j3PaT9Wq9rGr/YwZI23dKq1dK3XsaPp1t2snFS9uKrjfekvasMH02J4yRUpM9C3WEEESGyhAKlYMdgQAEKKoUgcAAAh5VGIjL5Ro2ND5hmeflUaPdr1yUpJ9XLx4zhu3JbH//de3oHzZT1ycfexqP+XLm4koP/7YVFw/+6zz/RaLdMcdJrmdU9W3O7fdZpZXXSX165e7bfiJJDZQgFStahLZBw/ab/v+e6lxYxLcQKFA6QoAAADCGEls5IUzmzerROXK9hvcVWFLphLbJiYm543btpWS4ltQvuzHMV53+/nlF+mzz6TDh7PfZ5tEMjFRev55736urCZPNsv+/X1/bIBwWAgh48aNU8OGDdWlS5dgh4IwZbFIWf98rrpKyvqhI4ACjiS2wcSOAAAAYcPx7RpJbARUfLxUooT94imJXaSIfXzuXM7bTkszy6JFfYvJl/3Y9uFuP2PHStdcI61ZYyZm/Okn6fRp87jNm6WHHpJOnJBefVXq1s33qnHJ3r+2fHnfHxsgHBZCyPDhw7V582YtCuEm6gh9Xbtmv+3UKXO8cmwBBaAAIlELAACAMGWrwpZIYiOI4uPtY2+SvcnJZulN65Hc7se2D1f72bhRevBBcy7YvbupyO7e3STrY2KkBg2k11+XPvrIrL98efZ2I96wVUfu2eP7YwOEwwJQwHTu7Pr2xESpQgXpwoX8jQdAEFCJbVCJDQAAEDZIYiMkFClin/jQcfJFV06etCeYHSdf9IbjZI457cdxMses+5k40f7iee45KTLS9TZuu02qU8eMJ03y/fxo0CDzGFtbkSDgsAAUMHXqSMOGue7Vn5Li3C8bQAFDohYAAABhiiQ2Qoat6nj7dun8effrbd1qHzdokLt9ZN2Or/vZssU+btbM83Zs9584IR05knOMjoYOlS67zPTWHj06KOeeTOwIFDAWi/mWyL59UrVq2e/fs8f5Az8ABQgTOzqjEhsAACBskMRGyOjQQVq61FRZ//671Lq16/UWL7aP27f3bR81a0qVKkkHDjhvx5UlS8yycmWpRg3n+6IcUrueEu6SlJ7u+nHeWLrU9NY+elR64QVp+nQzyeOll0qlSrmvALfp1Mm3/blAEhsooNz12t+92/djKwAAAAAAecmx5oCaDARVnz7Sf/9rxhMnuk5iZ2RIU6aYcUKC6wnKPLFYpGuvld5/31Rar1wptWmTfb2VK+2V2Ndem/3FUbOmfbx0qXTVVa73l54urVhhxiVLSqVL+xZvly7O+962zSSzvWGx5Jxg9wKfbQEFVEyM69sffdR8WOY4uS2AAoJKbAAAAIQpKrERMlq1kjp2NONPPrEnfx29+aa9lcfIkVJ0tPP9ixaZ8zKLRRoyxPV+7r/fXsF8332mB6yjlBRzu2Qqp++/P/s2eve2jx97TDpzxvW+nn3W3l+2Z8/cnTNarbm/BACV2EAh888/0pdfmg8J77472NEAyBMksQ3aiQAAAIQNktgIKWPHmq+xp6RIV1whPfGESaSkpEjTppk+rpJUt640alTu9lG3rvTww9Irr0hr1pj9PfqodNFF0o4d0quvSuvWmXUfftg+MaOjK66QunWTfvlF2rhRatLEJNVbtTKTVG7fLk2YIH3/vVk/Ls4ktH21cGHufsYAIokNFGBbtkhr10o33+z6PgAFDIlaAAAAhCmS2AgpTZuavs+DBpnq5ieeyL5O3brS3LlSfHzu9/PSS2aSxQkTTMJ6wIDs69x+u/Tii+638fXX0vXXm0Tzrl2uK7YlqWxZ6YsvpHr1fI+zc2ffHxNgHBaAAqx+femmm1zf9/XX0g03mMpsAAUMldgGldgAAABhgyQ2Qk7v3qa6+YEHTMK6WDHT/7pFC3uVdO3a/u0jIsK0LJk71/S8rlTJ9IetVMlcnzdPGj/e84uiVClpwQJp5kzpxhtNn+yiRU2Lk7JlTT/rV181vbW7d/cv3iCiEhsoBCIinN8QSGYC3G++kf791/6tEgBhjkQtAAAAwhRJbISk6tWlMWPMxRdduvh2ftazp7nklm2iyGuvzf02QhyHBaAQWLPG/TwCP/wgPfQQuS+gQGBiR2dUYgMAAIQNxyQ2b2cBZEUlNlAING0qTZwoLV5s2iNl9eab9suDD+Z/fAAAAACAws2WxLZYSGIDIW3HDmn2bGnDBunYMTPZpaeiIYvFtDvxE0lsoBCpVct1Ettm1CiS2EBYoxIbAAAAYYq3skCIO3tWGj5c+vTT7ElrqzX7izfAL2raiQCFyEcfSR07BjsKAHmOd/4G7UQAAADChq0Sm37YQAiyWqW+faUpU8yLNTFRatzYfp7VsaPUsKEUGWm/rV49qXNnqVOngITAoQEoRGrVkpYskSpUcL/Oa69JaWn5FxOAACJRCwAAgDBFEhsIYV99Jf30kxk/+6x06JBJaNssXiz98Yd08qSZBDMuTjpxQnrhBWnhwoCEwKEBKITq13d/36OPSs8/n3+xAMgDVGIbVGIDAACEDZLYQAj74guzbNvWJLEjIlyfd8bFSfffb3pgJyVJ110nHTgQkBA4NACF0MSJUvny7u9//XVp7978iwdAgJCoBQAAQJgiiQ2EsDVrTNJ62DDv1m/ZUvrPf8zEj++8E5AQODQAhVCNGtK+fe7vT0+XqlenrQgQdpgNxxmV2AAAAGGDJDYQwo4dM8tatey3RUfbxykp2R9z9dVm+d13AQmBQwNQSEVHS/PmSaVKuV9n+3YpNZXcDwAAAAAgb5HEBkJYVJRZxsfbb3McHzqU/TElS5qlpypKH3BoAAqxq66Sjh93f//cuWbC2Xvvzb+YAPiBSmwAAACEKZLYQAirVMksjx6131ahglS0qBmvXZv9MX//bZbnzwckBA4NQCFnsUh33+36vkcflc6elf73v/yNCYCfSGIbtBMBAAAIG7YkNm9lgRDUuLFZ/vGH/TaLRWrd2oyzJo7S06UxY8y4Tp2AhEASG4Def196+GHP69SuLW3YkD/xAMglErUAAAAIU7a3slRiAyGoWzfzIv3+e+fbb7vN3L5okdSlizRunPTaa1KrVvbJIG+8MSAhcGgAIMm0DClWzP39O3ZIN92Uf/EA8APlKwaV2AAAAGGDdiJACOvb15xfLVwo7dxpv33QIKlHD3O+tXSpNGKE9Pjj0saN5v4mTaQHHwxICBwaAEiSqlWTjhzxvM7u3fkSCoDcIlELAACAMEUSGwhhFSqYFiGpqVKtWs73ffut9OSTUvny5pzUajWTOg4fbpLeRYoEJAQODSFk3Lhxatiwobp06RLsUFBIxcWZD9DcOXvWfDPk1lsD1pcfQCAxsaMzKrEBAADCBklsIMRFREiRkdlvj42VXnhBOnBAOnZMOnRIOn5cevddqUSJwO0+YFuC34YPH67Nmzdr0aJFwQ4FhdjUqdJHH7m//957pU8/NR+0AQhRJLEBAAAQZkhiAwVA6dJSuXJ5ck7q1aEhMjLvL1FRAf/ZAORCQoJ0xx05r/fPP3keCgBfUW3sjGQ+AABA2CCJDcATrw4NtnYmeX0BEBosFumzzzyvk5wsPfKI56ptAEFC8jY73mgAAACENJLYADzxuv7ZYpHuvttUhAfSkSPS++8HdpsA/HfzzaaF0ciRru//4Qcz8axkKrd5owGEABK1AAAACFO2JDb1GEAIO3ZM+vxzkxDauVNKSpIuXPD8GItF2rHD71371MRj+HCpYUO/9+lk0yaS2ECoGjHC9Oe/++7s99kS2JL5MKpChfyLC0AOeOefHQl+AACAkGZ7u0aBFBCipk6V/vMfk7iWvD/HCtD5KZ2oAXg0cKD02mvmAzZ3tm+XVq6U2reXypbNv9gAZEGiFgAAAGGKdiJACPvlF2nQIPs5Z/Xq0qWXmonV8ulF61USu1MnkzSPiwt8AHFx9u0DCD0lSpgktadj0kMPSb/9Zl7Hp09L8fH5Fx8AB7Y3FPxTtbNYmHwDAAAgDJDEBkLYK6+Yc6qEBNNO5Kqr8j0Er5LYixblXQA1auTt9gH4z2KRJkyQbrvN9f2//WaWVqvUoYO0YUP+xQbABZLYAAAACDMksYEQtnq1Oc987rmgJLAliUMDAK8MHSp9+WXOubGNG/MnHgAuUG2cHQl9AACAsEASGwhhthdo+/ZBC4FDAwCv9etn79/vyfnzeR8LAA9I3GZHgh8AACCkkcQGQthFF5llcnLQQvDr0LBkibn8/bf3jzl71v44AOEnLk664QbP6xw+nD+xAMiCRC0AAADCFElsIIQNGGDON3/4IWgh+HVo6NJF6tpVatTI9Mv1xq5d5nHduvmzZwDBNHWq1KKF+/u//VaqVEkqUkSaPz//4gLw/6jEtrM9FyT4AQAAQpotic1bWSAE3XOP1LCh9Pbb0po1QQkhIJ9vnTsnDRsmPfig9+eInEsC4Ssqynyb4ttvXd9/333SwYNSWprUs6c0a1b+xgcUWvxzBQAAQJiyvZWlEhsIQcWLS/PmSfXrS506SU8+aSZFS03NtxACcmioWtUcbMaOla6+WjpzJhBbBRDKihb1fkLaPn2kr7/O03AASPZ3/pSv2FGJDQAAEBZoJwKEuGrVpMmTpfh46ZVXpKZNTc/ZyEjPl6iogOw+IIeGb74xE77ZWqO0bSvt2BGILQMIZbGxpkWQN/r1y9tYADggiQ0AAIAwQxIbCHFjx0pNmkjHjpkksC+XAAhIKrxYMWn6dNMa5fnnpa1bpVatpK++ovc1UNDVqGFai3TqlPO66elSdHSehwQUXlQbZ0dCHwAAICyQxAZC2Lx50gMPmHFEhNSxo9S4sZSQkG8v2sDUc/+/Z581ieyhQ6WTJ6UePUy/73vuCeReAISajh2l5cul//zHtERyZ/9+qWbN/IsLKLRI3GZHgh8AACCkkcQGQtjrr5tl5comod2oUb6HEPBDQ79+piqzShXp/Hkzwds990gXLgR6TwBCSbt20gsveF5nz578iQUotEjUAgAAIEyRxAZC2MaNpljq+eeDksCW8iCJLUnNmkm//Sa1bGnOpz/8ULrySlOdDaDg6tlTuvhi9/f//Xf+xQIUSkzsmB0TOwIAAIQFkthACLNVJzdpErQQ8uzQULGiqcgeMMCcNy5cKLVuLW3enFd7BBBsUVHShg3mte7KnXdKM2bkb0wAAAAAgNBnS2JTjwGEoDp1zDKIFcp5+vlWbKz0xRf2FgM7dkg335yXewQQbJGR0sqVpj++TUKCfXz99dL775vx+fMURwIBRSV2dlRiAwAAhAUqsYEQNnCgOaeaOTNoIeTLoeHJJ6Wvv5aKFaM3NlBYrF9v+mRHRpre+I7uuUd65BGpRg3puuuCER1QwJHEBgAAQJix1RyQxAZC0H33Sa1amZ7Rc+YEJYQofx58663mPLlUqZzX7dtXWrpUuuYaaf9+f/YKIBxER5uWQmfPSj//nP1+28S2//wj3XijNH06eTfAb1QbZ8eBBQAAICxQiQ2EsIMHpY8/Nn1i+/aV+vc3l7p1TdVyTqpV8zsEv5LYkyb5tn6TJtLevf7sEUA4iYyU4uOd24m48tVX5lsaX39NvgkICF5I2ZHgBwAACGkksYEQVqOGc6vGadPMxRsWi+kn6ycODQDyXN26Oa8zY4ZpP0LLIcAPJGoBAAAQpkhiAyHOarWfc9rG3l4CwK9KbADwRuXK0uLFUufOntdbuVL65hvTXgRALjCxY3ZM7AgAABAWbEls3soCIWjixGBHQBIbQP7o1En65RepWzfP6x0+nD/xAAUa7/wBAAAQZmzdBqLIVAGhZ/DgYEfgfTuRyMjAXjgoAYVP167Shg2e11m5koJJINd48WRHJTYAAEBYSE83y+jo4MYBIDR5ncT2tdVJPrVDARBmLr1UWrvW/f1ffCFNnZp/8QAFEpXYAAAACDMksQF44nU9dKdOns+Jk5OlNWvMOp06BSI0AAVV06bS+vVSkyau77/5ZikhQerZMx+DAgoCPiHOjoQ+AABAWCCJDcATr5PYixZ5vn/TJqlRIzNeuNCPiAqxcePGady4cTp37lywQwHyXOPG0rJlUocOru+/+mrpq6+kG27I37iAAoHEbXYk+AEAAEKaLRVCEhuAK163E0HeGz58uDZv3qxFOX1iABQQ7dubyR7d6dcv/2IBCgQStQAAAAhTVGID8IQkNoCg6tpVWrAg2FEABYQtiU0lth0TOwIAAIQFWxI7Jia4cQAITSSxAQRdt27S8uXBjgIoQEhiAwAAIMxQiQ3AE5LYAEJCu3amR7YjPoEHfES1cXZUYgMAAIQFktgAPCGJDSBktG8vzZ1rv37hgpSREbx4gLBFJTYAAADCDElsAJ6QxAYQUnr2lObPN+MLF6QTJ4IbDxBWqDbOjoQ+AABAWCCJDcATktgAQk6PHlLx4mZ86lRQQwHCE4nb7EjwAwAAhDSS2AA8IYkNICQlJJglSWzAByRqAQAAEKZIYgPwJMrbFadM8Xz/P/94v67Nrbd6u3cAhU1CgrR/P0lswCe2JDaV2HZM7AgAABAWSGIDIeL55wO/zWee8XsTXiexhwzJ+ZzYdv/QoTlvz2IhiQ3AvZIlzfL06eDGAYQlktgAAAAIMySxgRAxenTgzynzM4ktUcQEIP/QTgTIBf5RZ0clNgAAQFggiQ2EkECePwUoIe51EnvixIDsDwC8QhIb8AOV2AAAAAgzJLGBELFrV+4fa7VK33wjvfqqdPx4QJPhXiexBw8O2D4BIEe2JDbtRAAfUG2cHQl9AACAsEASGwgR1avn7nFz5kjPPitt2GCuW61S5crSk08GJCyf2okAQH6x9cSmEhvIBRK32ZHgBwAACGkksYEw9cMPpuf1mjXmutUqlS8vPf64dNddUmxsQHZDEhtASCpRwiypxAZ8YEvUksQGAABAmDl3zixJYgNh4pdfTPJ6xQpz3WqVypSRHn1UuuceqWjRgO6OJDaAkGQ71qWlBTcOIKxQbZwdEzsCAACEBSqxgTCxbJn09NPSkiXmutUqlSolPfSQNGKEFBeXJ7v1Kom9d69ZVq4sRUYGNoALF6R//jHjatUCu20A4atIEbNMTQ1uHEBYohIbAAAAYYYkNhDifvvNJK8XLDDXrVbTC/aBB8wlPj5Pd+9VErtGDSkiQtq4UWrYMLABbN0qNWpktn/+fGC3DSB8kcQGcoFq4+yoxAYAAAgLtiR2TExw4wCQxdq1pm3I/PnmutUqFS9uqq4fekhKSMiXMLxuJ5LX536cWwJwRBIb8AOV2AAAAAgzVGIDIeaPP0zyevZsc91qlYoVk4YPlx55REpMzNdwfOqJzTkxgPxim7yWntiAD/hEODvevAAAAIQFkthAiNiyRRo9WvrmG3OOabWaSsO77pIef1wqVy4oYfmUxL7iisAfTGwHKQBwRCU24AcSt9mR4AcAAAhpJLGBENGokT15HRsr3XGH9MQTUsWKQQ3Lp3YitgkYASCvkcQGcsGWqCWJDQAAgDBDEhsIERkZ5pzSYjFJ7LlzzSW3LBZpxw6/w/IqiT14sN/7AQCfkMQGcoFq4+yY2BEAACAskMQGQozVKp05Yy7+CFCRlVdJ7IkTA7IvAPAaSWzAD1RiAwAAIMzYzv1s54IAgqRTp5A8p/SpJzYA5BeS2EAuUG2cHZXYAAAAIc9qlVJSzLho0eDGAhR6ixYFOwKXIoIdAAC4EhtrlmlpwY0DCEsh+Kk5AAAA4I7jeR9JbACukMQGEJIcK7EpoAS8xIslOxL6AAAAIc9WhS2RxAbgGklsACHJlsS2Wu0TfADwEonb7EjwAwAAhCxbEjsigokdAbhGEhtASHKczIO+2ICXbIlaktgAAAAII479sHkrC4SAyZOl0qXN5bPPfHvsZ5+ZxyUmSl9+GbCQSGIDCEm2ntgSSWzAa1QbZ8fEjgAAACGPSR2BEHL+vPTkk9Lp09KVV0qDBvn2+EGDzONOnpQee0zKyAhIWCSxAYQki8WeyCaJDfiI8hUAAACEEZLYCFl79kijRkn160txcabCuGVL6fXXpbNnA7ef+fOlvn2lKlVMMqRKFXN9/nzftpOeLk2aJF19tVStmtlWmTJSo0bSHXdIX32V8zbmzpUOHJBiYqRXX83Vj6PXXjP73rNHmjcvd9vIIiogWwGAPBAba2apdpypGoAHVBtnRyU2AABAyCOJjZA0Z46pKj5zxn7b2bPSmjXmMn68SfjWrp37fWRkSHfeKX3yifPt//xjLjNnmuTzhx+apvGebNwo3Xyz9OefzrcfP24uf/4pff211K+f5+3Mnm2WtkR4blStKvXuLX3zjTRrltSrV+6244BKbAAhy/YGJjk5uHEAYYdKbAAAAIQRktgIOevWSf37mwR28eLSSy9Jv/4qLVggDRtm1tm2zSR6k5Jyv58nn7QnsJs2laZOlVatMsumTc3t48dLTz3leTsbN0pdu5pEdZEi0r33mmT0779LK1ZIU6ZIN90klSiRc0yrV5tzyp49c/9zSdJVV5liolWr/NvO/6MSG0DISkiQDh82bZgAeIFq4+xI6AMAAIQ8ktgIOSNHmj/MqCjpxx+ltm3t93XrJtWpIz3yiElkv/mmNHq07/vYtk164w0zbtFCWrLE/iJo2VK65hqpc2dT9f3669Jtt7mu+k5NNdXVJ06YyumffzbxOWrTRrrlFuncuZzj+ucfs7zoIt9/Jke1apnl/v3+bef/UYkNIGSVLGmWJLEBH5G4zY4EPwAAQMgiiY2QsmqVtHSpGd9+u3MC22bUKKlBAzMeO9b0ovbV22+bSRQl6d13s78AihUzt0tmvbfecr2dN94wCfGICOnLL7MnsB3FxOQcl62y3JaUyS3b4//917/t/L+AJbEzMkxF/Ysvmor1226TDh50XufcOdM6hv62ALyRkGCWp04FMwogjNgStSSxAQAAEEZIYiOkzJxpHw8d6nqdiAjp1lvN+NQpaeFC3/ZhtZpe0ZKZNLJNG9frtWkj1atnxrNmZS/OuXBB+uADM+7eXWrd2rc4XClVyiyPH/dvOydOmKUtueOngCSxv/vOVLNfcYX07LPS++9LkydLJ086rzd+vBQfL5UrR49bADkjiQ34iGrj7JjYEQAAIOSRxEZIWbbMLOPipObN3a/XubN9vHy5b/vYtUs6cCD7djzt559/pN27ne/79Vd7+49rrrHfnpoq7dhh7rtwwbfYypc3y/XrfXtcVrbH27bnJ797Yn/8sXT33fZzwzJlpGPHXBeB3XGH6UN++rT07bdmgk8AcMeWxKadCOAjKrEBAEABcfKkKYg7e1a6/37p++/NnGODB5tvxc+ebYoUe/a0F9ONGGHyOosXmxawUVHS55+bb4fffrs0d67JA113nSk0XLrUdAVo1UqaPt0UWA4fLs2bZ+Z2GzLEFOJ9/bUpimzb1sQUHW1i+uEHadMmM2eaxWLmT2vXzlzGjzfbu+ceUwC4YYPJjZw6JX31lRQZaQo9v/xSOnLE5En+/FNau9bsp2pVUxRavLjZxhdfmLzU3Xeb5bx5Zu60OnXMvsqUMevNmCHt3Gn2deyY2X6PHqbg8+OPTU5p0CBp2jTzXAwfLv39t3k+S5QwP8vnn5s57YYONa16t26VrrzSxDRpkilQHDJEmjjRxH7ffdLKlWbdG28025kyxfx+Bg8289Tt3Wu+vb95s4m9Xz8T8/PPm983SWyEhC1bzLJ2bXMAcad+/eyP8dbmza63481+ata0X1+50j5u1Mi8kB97TJozx97ipGRJk+B+9lnv+ly3a2cORDNmmLYpufX11+ag2K5d7rfhyOqHbdus1uhoqzUiwmq97DKrdcsWc7vFYm7btCn7Y+64w9x/yy3+7Llg27dvn1WSdd++fcEOBQiqhx+2WiWr9cEHgx0JECZKlDAvmm3bgh1J6KhSxTwna9YEOxIAAOCjPXus1rJlzb9yyf5vXTK3R0ebcXS01TpwoP2+QYPs46uuct5GIC4Wi31ctap93KyZ1VqsmBknJlqtPXva7xs82D6+/nr7eoG4REZarRUquI6pfXv7+OKLTYy267fcYh8PHGi1RkV5v7+c1ilRwmotXtx+/cor7eObbrKPO3WyWmvUsF+///5g/9WhIMnMr23ebLWePm2/pKa6f1BKiv0P8uqrc95JXJxZt00b34J7/337fr76yvO6X31lX/eDD5zvGzLEft+HH9rjcXWJj7daf/op59hmz7Ynd2fM8O3nsvnmG/s25szJ3Tay8KudyFtvmb7iF19sPkHL6YMDSerY0SzXrfNnzwAKA9qJALlEJTYAACgAJk+Wjh61X9+/3z4+etReZJiebqp8bT77zD6eP995G4Hg2KVs3z77eO1aUzEumQrvefPs902ebB9/8419vUC4cEE6dMh1TI4dDjZtMjHafPqpfTx1qn1+OW/2l5MzZ5zncvvhB/v4iy/s4yVLTCV4XJz09NPSI494FwPgixING5pqZNvlv/91v7JtUkPJfAUiJ3FxZunr5IW+7Me2D1f7sfWdlqSRI83XRh54wFRkp6WZr2w8/LA5R0xKMl9/2LvX8/569ZIuucQc7AYPtrdX8dbSpeZxFovZTq9evj3eDb+S2L/8YuK5/37vJreUTCW+5HxQBQBXaCcC+IiJHbPjuQAAIGx9951ZVqpkvy3CIYsRHe39thy34TiOjDRtMXJaLz7eOc/kLqYSJXIXU8WK9nHJks5tNdzFVLmy8/Yc4wj08+Q49hRH1vW8fSs2fLhpKeL4PACBcmbzZpNYsF0ef9z9yqmp9rE3yc7YWLO0NXb3li/7se3D1X4cJx1MTTUvpDFjTAI2JkaqVUt67TXppZfMOqdOeU7iS+aF++675uCRnCx17WoS47t2eX7czp0mSdytm3lcdLT03nueH+MDv5LYtk9BGzf2/jG2Dw8C+akjgIKpZEmzpBIbgN+Y2BEAgLCzZ49Zdu1qv23gQPu4USPTC9omPt79thy34TiuWNFebJf1vi5d7OOGDaXERNfrOcbUubPnONzF1K2bfXzJJfZzIU+xt2rlvL0bbnAdU79+3sXjaV/t2zuv16aNfez4PDk+pkIF58fdfLP7/TZt6n2MgM/i480nTLaLY1I4qyJF7ONz53LedlqaWfra0N2X/dj24Wo/jtspU0Z69FHX23j4YfOilEyT/JzOjzp3lj74wCS0MzKkd94xB9yLL5ZuvVV66CHTY/uhh8zkAxdfLNWta5LfFy6YT9I+/NDekiMA/Epi2z5R8yUhffy4WToekAHAFdqJAD6iEhsAABQQGRlmQkLJOVHtOC5d2jkP8+CD9nHz5s7bc3ycY9I6Jsa5wtrdvsqUcW6jUauW6/XKlnWuxs4ahyPHOLJuw7G1R40a7tdzZDt/yrqe4xxwktSsmet4YmLMpI2+7svx53CcMy462jmh77i9rM9L1u0DQeP4R+tNixBbJbQ3rUdyux/Hauus+3HcTpcu7qu6o6Kkyy4z4xMnTNV0ToYONb2Aypc3B9uMDDPD6+efmx7TL75oll98YW7PyDDrVagg/fijaSkSQH4lsW1fGfHm57axtVFxPOADgCsksQEfUW2cnS2hz3MDAEBIS0kxbVPfeMN8G712bXvS2DFJ6jguUsS5gNExEWrL1bh6nGPLipgY98lpx8cUK+a8L8eqbMf1ypZ1Lpp0rFIuX94+johwv6/4eOd9lSrlfl+OHIsFHddzbJcimQp2VzGVLes+OZ11X46JesfktK3QUzLPreNbMMcEd9bfD0lshIwiRewvcMdG/K6cPGlPMDt+AuSNKlXs45z249iTOet+HK/nFIPj/d5OFnDZZaav9jvvmE/ALBbX00ZaLOb+d9816zt+vSRAovx5cJcu0rZtZoICb5Lrp0/bK9Hz4GcJe+PGjdO4ceN0zpuvKwCFAD2xgVyiEhsAAISZjz6S5s41l6wcE62O/ZdjYuyTO0rOCdis1cbuErLR0c7bcLzPsQI663ruqp4TEpyLcBxjr1NHOnzYjBMTnZPTjgntrPtyTE5nrUR3FBnper2cKrZtMZUt635fZcrILW+fW8dkesOGpjDUVnFOEhshpWFDMznh9u3mjzTKTfp061b7uEED3/fhaju+7ufii+3jnGZddbzf3c/kStGi0r33mktSkvTHH6bVRlKS+dQtMdF8OuZtL6Vc8qsS+667zHny4sXSpEme1z1+XOrTx8yYGxUl3X23P3sumIYPH67Nmzdr0aJFwQ4FCAmOPbEpogS8wAslOyqxAQAIC54KER2Trp6SpI7rXXKJ8zYcH+ftNjyt59iGNmsLDcdWIO6S3YmJzvc5Jruz7ssx1+S4jaxtfR0f45jsd/w5SpZ0H1PWRLLjfVnb8DruK2s1t42n57ZGDdN5wMZTkhzIdx06mGVysvT77+7XW7zYPs7aOD4nNWvaZ0J13I4rS5aYZeXKzp+uSVKnTvZxTq0yduywj7PODOut+HipXTupd2/pppvMsl27PE9gS34msZs2lUaONOeFt98u9e9veoPb/PqraYsyfLj5ZG7JEnMu+fTTUvXq/oYOoKCzvck5f57JYAGfUIkNAADCjOP7/SJFnKt24+LsY8ckadZKbEdZ8zyOFcaOFdBZt+GYnPa0L8exY0V01na07iqbixY1SV53+3JMhLtLBGfdl7vqbcfnLyHBfUxly3q3r6zPheP2HNuMZF3PMceVNYnt+FwAQdenj308caLrdTIypClTzDghwXlWU29YLNK115rx1q3SypWu11u50l6Jfe212c/1ata0z4y6cKH7r7InJUk//2zGF13k3FcpTPiVxJakN9+U/vMfk8j++mszA67t+bzrLjNB5QcfmOfQajVJ76ee8nevAAqDuDj7V+JoKQJ4gYkds+O5AAAgLDjOW5aQYP/2du3azlW6jgnjrl2lG28042bNpGrV7PfFxdlbzrZq5ZxorVDB3vK2Vy/p6qvttzsmzx2TuJ07SwMGmHGbNlK9evb7HN9uNG0qXXGFGffr51zsWLeufVynjnMOyXGuto4dTYGjbezYLcBxX5deai/+HDTIxOX489tUrWpvV3LTTc6teFu0sI+rV3ful+24r4svllq2tO/LsejUMXFdqZL9ObzmGumqq8y4bFnn32PlyvbJHX1tJQzkuVatzItPkj75RFqxIvs6b74pbdlixiNHZv8kZtEi8yKyWKQhQ1zv5/777UmP++4zkwM4Skkxt0vmKxn33+96O489ZpbJye7XefBB6cwZM86pPcaZM/Z1/fHvv9Ls2eYSAH71xJbM72LcOPMhxSuvmAp4x0/TbOu0bWuS17YDGADkxGIxbxyPHzctRWzftAEAn9FOBACAkGW1Sj/8YL8eHS09+aR5/9+jh0mAzp1rJleMijJFicuXm7m5brjBJEP79DFtLb780l6FPWeOeVy/fuZxv/wipaaaZOqaNdJPP5ltZGSYpOqVV5p9zpljErMRESZHtWKF/VvzbdtKffuaRO306fbk8O+/mznDOnSQPvtM+uYbU+RXooTJgaWlmaTu0qXmcsstJpk8a5ZJzFss0qZN0qpV5me64grTJeC668zPP3WqPQm+erXpCtC6tTRjhvTtt2ZfxYubn69NG3vr1zNnzH4WLZLmzzc/ry2PU7So1L27NG+e9Oef0m23meT+55/b2/WuWiXt3m0+JJgzR5o50zwXcXGmvW67diYHt3ChqaYvX9485scfpVtvNduoUME8t2XLSt99Z+KMirI/T7165fmfGOC7sWPNpzUpKeYF+cQT5pOzlBRp2jTTyF8yL8xRo3K3j7p1pYcfNgnVNWvM/h591FRK79ghvfqqtG6dWffhh52/OuHoxhvNhIXz5pl+zwcPmorjatXMpJAffmjuk8wnbffe6zmuhARzANy40bl3t82BAybJa7GYA5w7e/aYg3NEhPPXS3LJYrUG9qwuKck8v0eOmANaYqLUpAn9jXyxf/9+Va1aVfv27VMVx49IgULoootMW6fly80bJAAeFC1qzlz27HEuRSrMatY0Z14rV5ozPQAAEFL++sskd7dts99Wq5Zz61YAyA2/82tz5pivHrirSq5b13xS5ji7qc2iRfYWI4MHu59MMCNDGjZMmjDBfRy3326S5hEeGmr8+690/fXmEyR3WrY0VdEVKrhfRzL7sVjMBI6uktibNpmvbVgsnieT9HY9L/ldiZ1VfLxzT3EA8IftK3yOM3wDcINq4+yY2BEAgJD29tvOCWyJ/sgAQkTv3qYaeexYk6zev980e69d23zF4957zVdE/BERYaqZr7/eJKpXr5aOHTPVwC1bml7N3rS1KF5c+v578xWRyZOl9evN19oTEkx18cCB5usRtvYlYcivJPbzz5vlPfd4X2l98qT07rtm/Mwz/uwdQGFgS2LTExvwAX2gAQBAGLBaTXsKycylZWvTmnXCQgAImurVpTFjzMUXXbr4VkjTs6e5+MNiMc37bQ38Cxi/JnYcPVp67jnTOsRbJ07YHwcAObFNwEIlNuAFqo2zoxIbAICQ9e+/0qFDZnzzzfbbqcQGAGTlVxIbAPIa7USAXKASGwAAhIGjR82yaFHzTfjhw831//43eDEBAEJTviex09PNkk9WAXiDdiKAD2zVxiSx7XguAAAIWbYkdtmyZvnuu9Lhw9IVVwQvJgBAaMr3JPb69WZp+ycFAJ5QiQ0gIGgnAgBAyMmaxLZYpHLlghcPACB0+TSx45Qprm+fNUtas8bzY9PSpB07pAkTzD+mli192TOAwoqe2IAPqMQGAABh5MEHzZIiNwBATnxKYg8Zkv282GqVnnrK+21YrVJEhDRypC97BlBYUYkN+IBq4+yY2BEAgJC0d6/0999mfPx4cGMBALgQYsVRPiWxJdfngN6eF8bEmArsxx+XOnf2dc8ACiN6YgO5EGJvNgAAALLavds+rlcvaGEAANy55BL399nOOSMj8ycW+ZjE3rXLPrZapVq1TMw//CDVqeP+cRaLVKSIlJiYrz8bgAKAdiKAD6g2zo5KbAAAQtK+ffbxf/8bvDgAAG6E2DmUT0ns6tVd316pkvv7AMAftBMBcoFKbAAAEOJsSexbbpGqVAluLAAAB506heQ5pc/tRBxlZAQqDABwjXYigA+Y2DE7ngsAAEKK1Sq99ZZpMypJ1aoFNx4AQBaLFgU7Apcigh0AAHhiS2KnpEhpaUENBUA4C7GvwgEAUFj99JM0apT9eps2wYsFABA+SGIDCGnx8fYx1dhADqjEBgAAIW76dLPs2VP6+2+pV6/gxgMACA9+tRNxtGOHNHu2tGGDdOyYqZr0VPRksUgLFgRq7wAKqshIqUQJ6cwZk8QuVy7YEQEIK0zsCABASFm61CxHjJBq1w5uLACA8OF3EvvsWWn4cOnTT7OfH1qt2YvBKBID4KuEBJPEZnJHwEv8kwUAACHq8GGzrFEjqGEAAMKMX0lsq1Xq21f6+WczLlPGzCq8fr05f+7YUTpxQvrrL+n8eXNbvXpShQoBih5AoVCypFmSxAY8cPwkmSS2HZXYAACEjLQ0U5wiSWXLBjcWAEB48asn9ldfmUkZJOnZZ6VDh6QpU+z3L14s/fGHdPKkNGaMFBdnktovvCAtXOjPngEUJrbJHUliAwAAAOHr2DGzjIy0v8cHAMAbfiWxv/jCLNu2NUnsiAjXxV9xcdL995se2ElJ0nXXSQcO+LNnAIWJ7Q0uEzsCHlCJ7RrPBQAAIePoUbMsU8bkDwAA8JZf/zbWrDHnhsOGebd+y5bSf/5jPn195x1/9gygMKESG/AC7TI84/kBACDobElsWokAAHzlVxLb9lWgWrXst0VH28cpKdkfc/XVZvndd/7sGUBhQk9swEdUHwMAgBB0991mSRIbAOArv5LYUf8/LWR8vP02x/GhQ9kfY0tG7dvnz54BFCa0EwG8QKWxa0zsCABASDh+XNq504ybNAlqKACAMBTlz4MrVZJ27LB/JUiSKlSQihaVUlOltWulmjWdH/P332Z5/rw/ewZQmNBOBPARldgAgAJg3z7p00+liy+WeveWJkyQVqyQbrlFKl5cmjVLqldPGjDAjDdulEaNkrZvl6ZMkYoVk554Qpo8WTp4ULrnHrPNr76SrrlGatrUrLdunXTnndK5c9L8+VLz5tKVV0rjxpnbHn1UWr3afJt46FCpdGlp7FjzzeSnn5aWLjXbuP568y3lTz81+x461MQ1f750+eVmu9Ommfvuv1/67DNpyxbpvvvMt5gnTDBzSD37rDR3rrlv0CApJkb65BPTnrN3bxP/zp3Sww9Lmzeb+ypVku69V5o4UTpxwmz/0CGzvx49pPr1pUmTzDbvv9/MUbVwodSpk9S5s1nv8GHpoYekJUukL7+UGjSQbrrJPO7sWXPf4sXmcYMHm2rqTz81+x44UJo61cyDdd11Uo0aJs4KFcxz+/335ueUTL7gjTeC9VcFAAhXfiWxGzc2Sew//jD/lCVz3ty6tfnn9r//mX/kNunp0pgxZlynjj97BlCY0E4E8AITO7pGJTYAhKVdu+xtK8uUMQna0aPN9cmTzfLCBXOYnzFD+vZbc9vGjdLMmfbtvPWWKbCSpOnTTYJbkmbPlooUMeeykknGnjtnf1yjRvb7NmyQvv7ajA8cMInj1avN9YkT7dv/4QfzzUFbtfH8+fa4PvnEFGbY3s+OH28SyraYFy60t+P8+GP7NqdMMcnyc+dMMvuKK+ytOePipCeftK/78ssm2Wzb5qxZ9p81Kcke16efSmlpZvzKK+aDgK1bzfXVq83zafPss/ZvQ06bZl/v11/N+MQJ01L06FGTHJdMMr5IEXtcCxbYnz9JuusuJnUEgAJrxw7zj6tGDal8+YBu2mK15v6s7v33peHDpe7dpR9/tN/+2WfSrbeaNxQdO0r9+knJyeaT2Q0bzO0vvGA+FUd2+/fvV9WqVbVv3z5VqVIl2OEAQff11+Y40qGDqXQB4EJ6ujm7laSTJ+1fYSjsLrlE2rTJnEF36xbsaAAAXnrxRVPlbBMT45xkRvi5/XapVSupf397kQoA5CXyawF05Ij9E8mbb85+IN++3Rzg16831y0W6dprzae2pUoFJAS/Pv/s29fEtHCh/VNdyXzlqUcPU/S0dKk0YoT0+OPm02DJ9L968EF/9gygMKEnNuAFKrFd47kAgLBkqza2OXfOtBCxiYoyFcDu2Kq4JdO+w52LLrKP4+Kc7yta1P3jHNf1tP2s7TWz7sNdLI7bdPy5c4rF2+17yifExkoVK7repqfnpEQJ5+uO65YuLX3wgWktQgIbAMLQjBnma1Fjx2Y/kKelSVddZRLYVqu5ZGSYr0Zde23AQvAriV2hgin8Sk11fpMgma9NPfmkqRy3xV+ypKncXrjQfL0IALxhS2L/8Ye0bVtQQwFCF+0yPOP5AYCQtXOn+TbvhQvSqlWmaOu337Kvd9119nHduqblhyuRkabFpc0NN9jHWROtN95oHzdvLpUrZ7/er5/7mB3bZjpuP6vGjZ2v9+5tHzvmACIinH8+x202by5Vq+Z6++XKmW8ruoorK8f1unRxTk47Pi8dOkiVK7vepqfnpE8f+zg62nwr26Z7d/PBAwAgTP34oykQ6ts3+32TJpk2IpKZdGLsWPMPz2qVli83/bwCwO9OVBER5k1CVrGxpmXIgQOmFcqhQ2Y24nffzf7GAQA8qVHDPp4yJWhhAOGD6mMAQBipU8dM1njxxSb5PGyYub1GDeeKYMd5leLinDtntW1rH5cp41xp7Pi4Zs2c9+2YVC5b1hRp2Tgmjtu1yx6zq7FkJmB03Kaj0qVdx9y0qfP+HLdZtqz7nzXrfY6Pyxpz7drOj4uPd73NTp2ci87c/azx8eZ3ZuOY+I6JcY6rUycBAMLZX3+ZZZs22e/74guz7NbNVF/fd5+ZmKF7d5PInjYtICH4lcTeu9dcTpzwvF7p0uYTYs6pAeRGmTL2k5k9e4IbCxCyqDR2jYkdASDkZWSYpe382KZZM+dEqGNhQ3S0cyXzZZfZx+XKOd/nKeHsmISNj3dOYjsmwh23n3U7ji1DSpaUHNuuOlZ2S84/T4sW9nHWnzVrstixdYpjLGXLOt/n+LiOHZ0LzrImxm2TQErOFePNm7tP5jtuo0EDKTHReZs20dHOP0/z5gIAhLOjR80ya2/xlBRp5Upz3nXnnc733XabWa5dG5AQ/Epi16hh/mEHKKEOAG7Z5mMjiQ14gU+NAQBhIiXF/X01azono7MmSdPS7NcdW4uULevcusJdwlly7jcdHe08eaTjvps0sY+jopzP4R3jKlXKfcyetlmzpnPS17FdZ0yMdOqU/Xr16s7bd4zZMa5atdwn8xMSpDNn7NcdK8Rr1nTepru4PP2sMTHOfb2zPu8AgDBj+0cUkSWVvHKl+eTTYjGV145sB/8jRwISgl9JbNtEDY5flwKAvGCrANm7N7hxACGLiR1doxIbAELarl3O1596yj6uVs05gZo1SXrypOv7srYFqVTJeZs2xYs7n4vHxDgnbx3bbThWKsfGuo+rVCn392XluM3q1Z0TwuXL28fR0c4/a9btO/6sWSvXHSuxHSd2jI11H1f16s7bdBeXp581JsY5SZ61Ih0AEGZsn/oeOuR8+6JFZtmwYfZZg21fFQrQpAh+JbFtPa8uXAhEKADgnq3iZP9+6fz54MYCAAAA/y1blr1oy7FndVyc50psx+rkrMlUd5XEju0vHG+3bdORY7sNT61MHONKSPCcxHaM2bFqukwZ58+gc/uzOsaVNRntODdV1p/Vcftxcc7bdBeXp581a8x8vg4AYa5+fbP8/nvn27/5xhzkO3fO/hhbwtvxE1A/+JXEvuIKs1y2LBChAIB7FSuaN8MXLpgJYwFkQSW2azwXABCSrFZp4EDp4EHn2x2rptu1s38TOTraVPPaWmLcdJO91WbXrlLVqvbH1a0r9ehhxvHxzpMUXnqpvU3dyJH2dSSpVy/7bQMHOvdxjoy0T4zYubNzMrxMGXtv7dtuc654rl1bGjDAjB94wN7PukQJ57gaNXJ+XNGiznE9+KA9LsfWHHXrSv3728eOcVWrZvpiS+Z5c/yX2L69NGiQGd9/v/3DBFsS/I47zLJTJ+cJIYsWte/j+uud24tUry516WLG//mPud8WFwAgzF19tfnn/dFH0vvvS3/+KT30kLR5s7n/uuuyP8bWC9tx5l8/+FXPPXKkNGmS9MYb5p9pgGICgGwiIky1yq5dpqWI41dBAYh2GTnh+QGAkHLwoPmGnSS9+qr06KNmXLastHOnKVpo0MC0F2nc2CSJY2OlX3+V1q0zSdcLF0zyt00bk3z97TfzPrF3b7PuL7/YC8e2bpWSkkySfMYMacUK6fLLzX1//WXu79pV6tBBuvJKk6guVkxautSeIP/pJ3P9qqtMMnfDBvMetUgR823qtWvNNi9cMN+6LlPGJJzHj5duvdUkz2Nissf177+mYEOSVq2yJ5Id42rf3jy+UydTKb1kiXTihMkpRERIFSpITZs6x1W0qDRhgjR/vnmcJO3ebZ73Ro2kDz4wHwa4iuuBB0zC3/bcrlplr7reuNHEZnu+qlQxCezERGnmTPPcdu9uYihb1sQFAAhz994r/e9/5h/4vfc639e2rfmnkNWcOeYT1AD1obZYrf6d1c2ebT7BLVnSvPm44QbzDxC5t3//flWtWlX79u1TlayzfgKFWNeu5gThs8+km28OdjRAiElOtvcpS052nk2pMGvSxJzN//CD/StkAICgSUqSpk0zl19+MRXCjz9ur6o+c8a5FzUAALlFfi3AtmyRbrnFXmEtma/8TJ3q/FUqyZyDNW1qktjz5plPiP3kVyW27WtYZcua6shbbpFuv928ESlVynkSiawsFmnBAn/2DqCwsfXF3rMnuHEAIYlKY9eY2BEAQsbq1aaK+fhx+20NGzr3bbZ9HgsAAEJMgwbSmjUmCXzokPkakeOkEVlNnGiWtgSyn/xKYi9a5NxXy2qV0tJMWxR3LBazHi0qAfjKlsTeuze4cQAhj3+yAIAQNGKEcwJbMv2SHXs88y8MAIAQV7Om8z9vVxo3NpcA8iuJ3akTbzIA5B9bH2wqsSHJfGo6ZgwzfdqcO2cf88/ZjkpsAAgJFy5I69eb8X33Se++a8Y1a5r+yW++GfBzXQAAECjPP2+W99xjJn3wxsmT9n/4zzzjdwh+V2IDQH6hEhtOfvpJeuKJYEcReooV89zPCwCAINizR0pNNfMnXXaZ/Zy2Rg3zeeODDwY1PAAA4Mno0eYf9g03eJ/EPnHC/rhgJ7EBID/Zktg7d9KWCDIzP0nm7PeWW4IaSkjp1EmKjg52FKGDAwUAhIStW82ybl3n9pmeWmkCAADYkMQGEDaqVjXL1FTpv/+lCLfQu3DBLOvWtX+1CXCHdiIAEDQrV0pXX23GdetKlSvb77O1iwMAAAWMbebmABVZRQRkKwCQD4oUkUqWNOOffgpuLAgBtiQ2rTMAAAhpQ4bYxzVrmm8hT5okffGFFBcXrKgAAECesk2GUbZsQDZHJTaAsPLdd1LHjvTFhkhiwztM7AgAQbd/v31sax8yeHBQQgEAAN6YMsX17bNmSWvWeH5sWpq0Y4c0YYI5H2vZMiAhkcQGEFZsfbH37ZMyMqQIvk9SeGVkmCVJbAAAQlZSkpScbL9evnzwYgEAAF4aMiT7/EJWq/TUU95vw2o1SZuRIwMSEukfAGGlUiWTs0xPlw4eDHY0CCpbJTafZMATKrEBIGj++Udq0MD5tjp1ghMLAADwkdVqv7i6zdMlOlpq316aPVvq3Dkg4VCJDSCsREZKVapIe/aYi+PEQChkaCcCAEBIe+wxk8guWlTq0kW6+WapSZNgRwUAAHK0a5d9bLVKtWqZAqEffvD8ibTFYiY0S0wM+Lk6SWwAYad6dXsSu127YEeDoCGJDW9QiQ0AQbFnj5m4UZKWLpWaNw9uPAAAwAe2Xq5ZVark/r48RhIbQNixHS/37AluHAgyktgAAISsn34y01e0a0cCGwCAsGebkyqIaCQKIOzYkth79wY3DgQZSWwAAELW0qVm2bVrcOMAAAAFA5XYAMKOLYn9/vvS7t3SJ59IFSsGNSQEA0lseIN2IgAQFOvXm2Xr1kENAwAABNrp09LXX0srVkiHDklnz0oTJzq3GTlwQDp1yvTHrlUrILsliQ0g7LRpYx/Pny898IA0bVrw4kGQkMQGACBk2dq+XXRRcOMAAAAB9N570pNPSv/+a65braZwKDnZeb1Fi6RBg0wSe/9+qXRpv3ftVxJ7yhTfH2ObpLJkSTOZZc2a/kQAoDC65BLp6quluXPN9b//Dm48CBJbTy6S2PCESmwAyHenTpkiLSlocz8BAIBAe/ZZ6cUXzblVbKzUqJG0Zo3rdQcMkB56SDp8WPrmG2nYML9371cSe8gQ+7lhbpUtKw0eLD32mFSqlH/bAlB4tGtnT2InJAQ1FASLrRI7gukdAAAIJbt3m2XZslJcXFBDAQAAgfD77yaBLZkK63ffNRXK7s7HIyKkfv3Mej/9FJAktt9n/larf5cjR6Q33jCVlRs3+v3zACgkSpa0j0liF1K0E4E3qMQGgHy3c6dZUoUNAEAB8d575pyqbVvTmsMxKeNO27Zm+ccfAQnBryT2rl3SunX2yTqaNZPeesvMRL11q7ksXWpua9bMrNO6tUner1snffqp1LOneQ4OHjTtAbK2UAEAVxwncjx/PnhxIIhIYgMAEJL+/NMsGzYMbhwAACBAliwxBUL33uv9Y2rUMMt//glICH4lsStVku66S1q1SnrzTdMGZeRIqX17qW5dc2nf3ty2Zo30+uvSb79Jd94pNWgg3Xyz9N130kcfme0dOCB9+GEgfiwABd2119o/+Dt1KqihIFhIYgMAEJJs37Bt3Di4cQAAgAA5eNAs69Xz/jFFiphlWlpAQvAriT1unElg33yz9MADOa8/apRZd+1aaexY++133GESUlarNHu2PxEFT40a5gMJV5cuXYIdHVDwREZK06ebsW3iIBQyJLHhDdqJAEC+s31ruFGj4MYBAAACJCbGLH2pIjx82CwD1APWr4kdP//cnBsOGuT9Y265xTxu2jTp4Yfttw8YIM2aJW3Z4k9EwVWypHT//dlvt1XPAwgs23GQSuxCiiQ2AAAhJyPDPrFjnTpBDQUAAARKtWrSpk3S339LXbt695hffjFLX6q3PfArib19u1mWLev9Y2zr7tjhfPtFF5llOCejEhKk0aODHQVQeNiS2Hv2SN9+K/XtG9RwkN9IYsMbVGIDQL46ckQ6d06KiJAqVw52NAAAICAuu8xMevHBB6ZPdE7++cf0j7ZYpCuuCEgIfrUTycgwS1sy2xu2dbOeS0b8fyTx8f5EBKAwKV3aPr7uOnPShELE9k+IJDYAACFjzx6zrFRJio4ObiwAACBA7r3X/GPfsEF64QXP6/71l9Sjh+n9WqyYmVAxAPxKYtevb5bvvefd+lar9M47Zpy1ktz2ZseXqm7JJK2++0565hnpqqukMmXsvaiHDPFtW3v2mL7d9etLcXEmQdaypZmQ8uzZnB+fliZNmiS9/LJ5Tn77zbf9A/BNmTLO10+eDE4cCBJbJXaEX//KUNBRiQ0A+WrvXrOsVi24cQAAgAC66CLppZfMedXo0VKbNtJrr9nv/+orkxC9+mrpkkukzZvNudjbb/ue7HXDr3YiN98srV4tLVsm3Xij9P77UmKi63WPH5fuvltavtx1H+1Fi8yyYUPfYihf3uewXZozx8R05oz9trNnpTVrzGX8eGnuXKl2bffbOHRIGjrU+baWLaWpU+3tUgAEji03ZcMEj4UM7UQAAAg5tm/e1qwZ3DgAAECAPfSQSWI/9ZS0apVJCtsSM88/b1/PajXn6W+8Id1+e8B271f52vDhUuvWJrZvvpGqV5duuEH6739N0nf8eDO+4QZz34wZ5nGtWpnH2qSmmokeLRbpyitzH0+1arlrs7JundS/v0lgFy9uPlj49VdpwQJp2DCzzrZt5sOEpCTX2xg61Kx/+LCUnGy2ecst5vd52WXuHwcgcEhiFzIksQEACDkbNphlo0bBjQMAAOSBhx+W1q83idAyZUxS2PFSooQ0cKBJjI4cGdBd+1WJHRkp/fijSQB//72pXP72W3PJyvYt3iuukKZPd845nDhhr0Dv3du3GJ55xlQ7t2xpqrJ37/b9U/+RI6WUFCkqyvw8bdva7+vWzcyq/cgjJpH95puuJ2989lnn602aSFOmmPGnn0offyw9+KBvcQHwzRVXmNdykSLBjgT5giQ2vEE7EQDIN3/9Zc71JKlx4+DGAgAA8kiDBtInn5jx3r2m1/OFC6Y9R61a2Vt+nj9vkq5+8ruRaHy8NG+eSVz36GGSR1mT8LGxJrn0zTcm2V2ypPM2KlWSBg82F8eJ2rzx3HNSr165byuyapW0dKkZ3367cwLbZtQo8/uRpLFjpfR077dv612+fHnu4gPg2fz5nq+jACOJDQBAyPjjD/ONW8mcpzZrFtx4AABAAE2d6vr2atWkFi1Mq47atbMnsNPTpeuvD0gIAZsN69prTTL7zBlp61ZpxQpz2brVtNL4/nupb99A7S1wZs60j7P2s7aJiJBuvdWMT52SFi70fvu2ieeSk3MTHYCc9OhhLjYB+HAP4YIkNrxBJTYA5IvXXjPngk2amPmOypULdkQAACBghgwxyV1fpKebZPB33wUkhICneyIjpbp1A73VvLNsmVnGxUnNm7tfr3Nn+3j5cu97b//2m1nWqJGr8AB44dQp+zglJWhhIL+RxAYAIGT8+adZPvec1L59cGMBAAABlp5uJj384Qfv/tGfO2cqnn/4wV5Y5KeAVWKHqy1bzLJ2bc8VnPXrZ3+Mzdatph94Vlu3So8+asY33eRfnADcO3nSPv7xx+DFgXyWkWGWJLHhCZXYAJDnLlwwczxJUsOGQQ0FAADkhdatTfKzVy/7LM7upKaa9X74wVx/+OGAhFCok9ipqdKxY2ZcpYrndUuVMtXakrRvn/N906ZJFSqY38/w4WYSyD59pEsvlQ4dkh5/XOrUyf2209LMV+9sl6SkXP9IQKHUrZt9/Mkn0uLFwYsF+chWiZ215xYAAMg36enmPEgycyHVrBnceAAAQB6YP1+6+GLp9GnT03X7dtfrpaSYNwY//2yuP/649MorAQkhIO1Ejh+XPvvMTJC4c6dJwtpyC+5YLNKOHYHYe+45JouLF895/bg409v633+db+/a1VRnr1tnnoOzZ00v7J49pXvuybn1yH//a752ByB3/vtf6f337dfnzXNuAYQCinYi8EaAvroGAHDthhvsLTKbNuXfMgAABVJCgqms7tBB2r1buvxy02+5UiX7OsnJJoFtqyx8+umAJjz9TmJ/9ZV0552mgljy/tu6oXBOmZpqH8fE5Lx+bKxZZu2527mzfwmzxx+XHnzQfv2ff/gaHuCLkiWlhx6S3njDXE9ICGo4yC8kseEL2okAQJ6YPds+/uST4MUBAADyWKVK0k8/SR07Snv3mkT2kiVSYqKp+L36alPdK0mjR0vPPBPQ3fuVxP7tN9PrOSPDnBtWqmQ+fS9dOjy+3V2kiH187lzO66elmWXRooGNIzbWniCX7B8IAPDe6dP2cTgcfxAAJLEBAAgqx6IgSapePThxAACAfHLRRaYiu0sXMxngVVdJ334r3XijtGKFWefFF6Unngj4rv1KYr/6qskhFC0qffxx+E1eGB9vH2dtEeJKcrJZetN6BED+ckxiP/aYNGSIVL580MJBfiCJDW8wsSMA5Jn9+52v2+YQAgAABVijRtKcOaZ/8u+/S3Xq2D/Zfvllk5TJA37VK/76qzk3fOyx8EtgS6YSOzHRjLO+Acvq5El7Ertq1byNC4DvHn/c+fqTTwYnDuQjktgAAASV44T3jRsHLw4AAJDP2rWTvvlGio42CWyLRXr99TxLYEt+VmKfOmWWV14ZgEiCpGFD065l+3bp/Hkpys0zsnWrfdygQf7EBsB7TZqYdkvPP2+u//NPUMNBfiCJDW9QiQ0AecaWxC5VSvrll+DGAgAAAmDJEu/XLVpUGjZMGjdOuu46qWVL94/v1Mnv0PxKYlesaPp4h8IkjbnVoYNJYicnmwr41q1dr2ebWFOS2rfPn9gA+MbxWxKlSgUvDuSTjAyzpAk6AABBYUti9+lj5kUCAABhrksX3xO9Fos0Y4a5uLv//Hm/Q/PrzL97d7P8/Xe/4wiaPn3s44kTXa+TkSFNmWLGCQlS1655HRWA3EhJsY9tE7GiAKMSG94I50/aASDE2ZLYtFsEAKAAsVoDfwkAvyqxH3pI+uIL6Y03pEGDwnPCw1atpI4dTTX2J59IgwdLbds6r/Pmm9KWLWY8cqRp9wIg9JQsaR/PmCF99ZXUr1/w4kEeI4kNX9BOBAACjiQ2AAAFzMKFwY7ALb+S2PXqSZ9/biZ1vOwyacIE6eKLAxWad5YtM/2sbY4ds4+3b5cmTXJef8iQ7NsYO9a0CElJMRNrPvGEqbZOSZGmTZM++sisV7euNGpUoH8CAIEyYIB5jdtyVUOHksQu0EhiAwAQVCSxAQAF3p490jvvSHPnmn98sbHSRRdJN94oDR8uFSsWmP3Mn28SkKtXS0ePSmXLmh7Td94pXXVV7ra5caPUvLm9lcfgwdkTpVl17py7feUDv5LYt91mlg0bmuf40kulRo2k+vVz/h1aLKby2V/jx0uTJ7u+b/lyc3HkKondtKk0fbqpJj9zxiSxs6pb1/y9xsf7HTKAPBITYybHve46c52+2AUcSWx4g4kdASDP7N9vliSxAQAF0pw59mShzdmz0po15jJ+vEkW1q6d+31kZJhEddYk6T//mMvMmdIdd0gffujbfFAZGWbSxQD0og4VfiWxJ02ynxtaLOb88I8/zMUTqzVwSexA6d3bfEAxdqz5+9u/3yTEatc2lZz33hu4D1cA5B3HliIJCUELA/mBJDYAAEFz7px08qQZV6gQ3FgAAAi4deuk/v1Nm4bixaXHH3du2/Dxx9K2bdLVV5uEdm6rXp980p4gbdpUeuQRU+m9Y4f02msmjvHjTWX2yy97v9333pNWrZLKlZOOHMldbCHGryR2tWrBny9p0qScK+G9Vb26NGaMuQTDuHHjNG7cOJ07dy44AQAFgOMx6c8/pV27pJo1gxcP8hBJbHiDSmwAyBO28+GoKAoHAAAF0MiRJmEdFSX9+KPzBHrdukl16piE87ZtZjK90aN938e2bWaiQUlq0UJaskQqWtRcb9lSuuYa095jzRrp9ddNSwxvqr7375eeesqcC73+umkj4q/Tp03lr2QqvCtW9Lz+wYMm0S+Z3sxxcX6H4EMdena7d5sEUW4vcDZ8+HBt3rxZixYtCnYoQNhq0MD5+rXXBicO5AOS2AAABM3hw2ZZrpxv324GACDkrVolLV1qxrff7pzAthk1yp6AGDtWSk/3fT9vv21v9/Huu/YEtk2xYuZ2yaz31lvebXf4cCkpyfRU7tTJ97hc+fxzk6j//POcE9iS+ZrW559Lzz1nKtcDgLcbAAqUChWk//3Pfj2n9kYIYxkZZsmZMzwJ9lfGAKCAslVilysX3DgAAAi4mTPt46FDXa8TESHdeqsZnzolLVzo2z6sVmnWLDOuX19q08b1em3aSPXqmfGsWTl/w/Trr6XZs6XERFOFHSjz55tzqxtv9G59i0UaMMDEO2dOQELgzB9AgePu2I8Chkps+IJ2IgACZP58843foUPNoeW776QbbpC6dJH++ssUbvXvL/XpY755u3+/dP/9po3mvHnSsWOmkKl/f/Nh+7lz0osvmjmdjhyRUlOlCRPMnDw//WQ+s/3mG+mBB8wcPpL5VvFDD9nbKu7ZY9pk2s6fd+wwLRI3bzbXDx+Wpk61n0OmppqJ7X/7zVzPyDDflP76ayktzdy2dq35WaxWc/n9d2nLFvvzsGmTWZYvnydPMwAAwbNsmVnGxUnNm7tfr3Nn+3j5ct/2sWuXdOBA9u142s8//5i2GO6cPi2NGGHGr71mEtmBsn69WbZr5/1jbBXstsf6ya+e2MD/tXff4VGUXR/HfxtKqCF06aGFIiAgVbqoCIpg7wI2VOz1sSDWx97BSrWXRwUbolKVDiKCiHSkS5USevb947yT2U02ySbZbEm+n+vaa+rOnOiwu3Pmvs8NRCPqMhYSJLEBAGE2YYJ0/vn2FbRwoY2p8+ij7vbGjf33f/VV6ym8a5ctz5ljX1sHDthy2bKWYP7mG1uuWdMafy1aZMvvvSdVry4tX27La9dKTZtKTz3lnuOrr6Qvv7T5ChXsWM795f/+Z72dr7zSynpK0qxZ0j332L12iRL2d1x2mbR4sW2/6SZLks+bZ8tTpthxXn/dyoIuXy4NHWpJcYmW2ACAAsh5atuggX35Zcb3i9/3SW8wnCfN6Y8TzHkyG/jrvvusFnWXLpm3IM8tpwtWMKVEHM7Iz04NsjwiiQ2gwClXzn/55ZetBVTM++ADt9kTpJ07bUoSG1lhYEcAebRpkzR5spWpvPtu9xmq5J/ADuSxx9xSl5K1gPY1apT/8gsvSHv3ust79/ov//KL2/PY4SSwJUuW9+njLq9YYWM5OQlsSTr7bDepfuiQdN551oLc4VuWTbK/+ddfbf7YMUt4OwnuJk1sbCcAAAqMQ4es25RkT5ezUr68tdY+cEDasCFn59m40Z3P7jy1arnzmZ1n5kzp7belYsWkN94IfVnFEiWk/fullJTg3+PsG6J79qCS2M65PB7/H2F5iSH9sQAgVMqXl1q0cLvc3nFHAUhir1snXXFFpKOITumfWgAAECLvv2/jOR054q6rXNnKYPo2KrrtNhvTSbIxmC68UBo3zr3fGTxYeustd//0y+XKWQ9gJ2E9cKBbKkSynwDvv+8+vz35ZNt35Upb7t1b+v57e163Z4/7Pmf/cuWkli2l6dPdBLbDSWCffrqVL3HUrWstv50EtsNJYL/xhnTDDQIAIPrt2+f/VDg+3l6Z7esoUyb7YztJ7P37cx5TsOcpXdqdD3SeI0esLpnXK915p3TiiTmLJRjVqtkPjwULgi8psmCBTZ0W2XkUVBI7s8ZLNGoCEI08HmullFkPm5i0e7dNS5emyZOvxo2l5ORIR4FoRktsAEHYudMaGJUubR8XO3dKxYvbV65vAluSevWSli51k9iJif5fRY0b2wN1X6ec4p+07tjRf3nIEKtp7ejc2T+J3aWLJbEdLVpYDL77z5pliXDJ6mkPH+5ub9nSSo34xrN3r3sMj0c67TQ3iV2rlnTWWf7HSK9798y3AQAQTRKaNvVfMWyYDVARiG+3qeLFsz+4kwz37fYUjJycxzfhHug8Tz9t5UmSkqSHH85ZHMHq0sW6eL3+unTjjdbiOytHj9q+Ho/9UAmBoJLYw4blbD0ARFqBq4vtNOWqVEl66aXIxgIAQAGyY4c1LjrxRLvve+QRG3CxaVO7v6xYUWrb1lo6S3YP59uTt0kT/6R1kyYZf4f4DjpdubJUr5673KyZ/7JkA0f6at/ef7lJE/9eyE2auK25JalfP/8EdJMm7oCNkiWgp093l+vW9W8kFehvaNtWmj/f5osVk+rXFwAAMWHvsmVKqFHDXZFZK2zJnmo70j/JDsT5gi1ZMmdB5eQ8vl/i6c/z11/uk/DXXrMuYflh0CCrg7ZypdUWGzcu83OlpEhXXWVJb48nZPW5SWIDKJASEvyXP/7YuvbGbPnko0dtmt3TTgD+Ql0LDkCB8/nn9qx48WK7J3PuE53xllq2lKpWdfdv1sw/wduggX9lqwYN/LfXqyfVru0uV63qv3+rVhkTxg0a+C/7lsKUpDPPdMt6SNYSPDXVXT7lFLvHdRprNWok/f23u719e+m339zlpk39Y2jUKGNMLVq4Sez69flJAgCIIWXLZkwSZLWvI5gSIc5ozcGUHsnteZxzpD+P12s1yg4fls491wa+yC+nnCJdcoklV774wn6IXHedPd13BnvcskWaMUMaOdKetns80gUXSN26hSQEBnYEUCDFxfkvX3qp3TD27h2ZePLMaYmd1cjIADJHOREA/2/KFOsF+/rrlqz94AN3m29DJ0eTJv5fv0lJ/gneQMu+xo3zb2xVvrz//nXr+i9XqeJf+lLyv+/u2VNq3tx/e1KSW3lMsoZRiYluErtuXbeVtmSJdd+PxffftyS+b0y+99bDh/snwQtUyTYAAHyVKGHdsHbu9O/2FMju3W6COf0T5+z4DuaY3Xl8u4D5nmfOHLdr1SmnWII5ve3b3fm1a919mjWzV06MHm1d2H76yWLOrHWz8yPj9NPth1CIkA0BUGBNmSKdeqq77HvzFXNIYgMAEBI9e9r0rLOstEf6+8YBA/zvt5KTpeXL3eUTTvBvSZ2UlHF5xw7/ZV+Jif5J60DHS7+/79e/0yrcNyntjCnlq1w5axAlSXXq+Cep0ye9y5XLGMPx4+5y167S119nHiMAAAVK06bSzz9Lq1bZvXhm9+G+PxCaNMn5OQIdJyfn8X36fs892Z9zxgx7SZaAzmkSu0QJadIkK1vy/POZJ99r1bJ4hgwJac/YuOx3AYDYlL7Hiu/NXsyhnAiQOwzsCBR677wj3XuvfQz4PtA+fNjuvdLXo+7f3/9etW5dK+3oiIvL2PLat6V0nTr++zs9bB2Jif49gdMntQMlsQMt+yahA0nfetz3d1CZMtKePZmfJynJvwRbnTpZxwgAQIHiDER44IC0cGHm+/kOMNGpU87OUbeuVL16xuME4iSea9SI/JewxyPdequ0fr39txk50gaWfPppm//1V2ndOhtlOsSlHYNq0vfuuyE9Z5qrrsqf48aqESNGaMSIEToSTOF4ANlKX1Ik/c1aTKElNgAAOZaSIl1/vc3XqRO4kdLw4VbScdMmW+7c2VpoO62Yk5Kku++2khsDBti61q1tWqqU1Yr2Lb1Rs6Z775uY6CaDmzSR/vzTjuH7G6VjR+u1HBdnda2dUiEnn2z3htdd5x9vr1427d1bWrDA7VV82mnWu9cpnVa9urR0qRtHcrL/cdq2tYZdzvhQvknqWrWkbdvc5YQEqUIFdznS988AAOSr/v2lp56y+TFjMo6wLNmXtpMwTUyUevTI2Tk8HhuJ+Y037At5zhz/kaAdc+a4LbH79fNPDHfvnn1jnXXr3DpgAwZIY8fmLM7MeDw2sEerVqE5XhCCyoYMHBj6cZE8HpLY6Q0ZMkRDhgzRxo0bVSuntXQAZOupp+wzu1GjSEeSCySxgdyhJTZQqBw9aknpM8+0pPG0ae62m2/OuH+pUpb89X3QXamSFB/vLtepY0nqHTvcFtf9+llZybJlLQEtWdK7SBHrNFWvnt1vVq7sHmfmTOuV3LatLa9ZI+3a5SaE58yRVqywcZkk6bvvrGFW//62vHy5lQTp29eW77/fGmSddZYtv/++1fd2Eu0vv2wNos4805avvlr65x/pjDNs+cUXrTTJ1Vfbcrly0rPPWjK9UiXb78Yb3XjPPNNiiYuL4TFGAAAIRrt2NmDhzz9Lo0bZl2vHjv77vPCCPZ2WpNtuy9hreto0N7GdWfL49tult9+2Gl633GItrp2ny5INbnHLLTZftKjtX4h5vN7s7+rSt2YMyYk9/nXW4HKS2Bs2bFBN30LvAHLshhukt95yl3v0sFrZMed//5MuvNC+SJ2uRACyd9ZZlgkaPVoaNCjS0QDIZw8/LD3+uCVkGza0lsq+KlSw8iLnn2/LPXta62XfBjter/1ecBLgPAMDACA25Sm/tmiRlQg5eNDqcD3wgP1AOHjQBkd8+23bLznZfnD4dsuSgktiS/ZU+umnbb5VK+m++6T69aXVq6VnnrE4nP3++9+c/Q1S/rXEjoCgmvStXZv5tt27pcGDpfnzrR74gAH2wMIZcGTbNts2bpy0ZIk9yX/rLRuVGwDy25tvSm3auF1xfQdaiilOS2xqYgM5E+quZACihtcrffut1LKllfA4cMAS2JLVf06fwJasBbVvh0endEd6w4fbs68+fUIeNgAAiAWtWkmffCJdcYW0d68lsdNLTrYfI+kT2Dnx5JPWVWr0aEtYX3JJxn2uuUZ64oncnyPUvF7pt9+si9iOHZbYz+6p/8MP5/m0QSWx69QJvP7IEWvFsGiR9Nhj0oMPZrxXTE62hoN33GEPDIYOtWTSzJl5DR0AguN085UyDo4UMygnAuQNTSmBAufDD+2+8sQTpeeeky6/POM+AwZYqZAJE2y5Wzdrpe1wSnnEx9tAj5Uq2fKJJ1ovYQAAUIj17Sv9/rv0yiuWrN64USpeXGrQwHpK33yz1SbLi7g4K1ly/vnWunv+fEsMV6pkLYEHD46uOl7jxkmPPmoDO+ZEuJLYmXntNRt08qKLpIceynpfj8eS3EuWSJ99Zv//Aw2sAgD5adUqafNmdxDgmHH0qE1JYgMAIEl6/nmb/vGH3Y/s359xn/S9Zlu1yjiAoSRNmiT95z/SiBH5FS0AAIhJderYQBIvvpiz9wUz6KKvPn3ypwtYUlLoGvQ8+KCVPgnmeB5PyBsS5ana9YcfWkwDBwb/nkGD7G/4+OO8nBkAgufbEnvLFqlxY+tyHFMoJwLkDgM7AgWO12s9en/7zV23f7/Vu163zl1XrJjUoYMNtuhISvJviV2hgk27dZNmz5Zat87HwAEAAGLV3LnSU0/Z/Omn2w+xX3+1ZWfgw+3bpYkTpXPOsR9snTtbEiY1NSQh5CmJvXq1TZ3618GoUsX/vQCQ37p0kdq3d5f37ct5z5eIo5wIAACSrLW0cw/l6+STpcqV3eW6daWSJa0+tiMhwUqHnHSSjdHTrl3+xwsAABDz3njDpnXqWGmVFi38G9l5PNaCsFcvafx4+8H2yy/SmWdaPeoQyFMS22nUtHJl8O9x9qVBFIBw8Xgy3uyeeKKUkhKZeHKFciJA7tASGyhQjh+3XqySdO+9/tuaNLGktcNpZb1nT8bjzJ1rZS3zWsYSAACgUJg1y+6tbr01uLzEjTdane/ff5defz0kIeQpid2kiU1ffjm4luGpqdJLL/m/FwDCIdCAjl9+GfYwco9yIgCAQuzYMenuu6VOnaRNm6xF9bBh/vs0auQ/yLzz3X/FFTZt29bdFh9PAhsAACBoW7bY9MQT3XVxPmllp+GdryuvtMZEn3wSkhDylMS+6iqLZe5cqX9/aevWzPfdtk067zzb1+Ox9wJAuAS6Ub3uOhvs6ZFHpH/+CXdEOUQ5ESB3fDNaAGLWDz9IL7xg9xKSlQorVUoqW9bdp25d//c4SewBA6TJk+0YAAAAyAUnSe3UiZakMmXc+e3bM76nZk2brloVkhDylA254QYboPGXX6wcSr160hlnWCuHKlXsvnHbNmn+fPvRePiwva9TJ3svAIRLrVoZ1x08aIPNStLatdK4ceGNKUcoJwLkDeVEgJi2aJH/8imn2LRcORvrQrJBG3316GHTuDjp1FPzNTwAAICCrXJlafNmae9ed13VqjaCdmqq9OefUvXq/u9xWm87P9byKE/ZkLg4G3Ty8sulr76SDh2Svv7aXuk59459+0offODf4hwA8lupUtZb5KST7OFaerNnhz+mHKElNgCgEPv9d//lBg0y7lOnjk1//VWaMUO69tr8jwsAAKBQOPFES2IvX25d4iSpeHFbv2SJlQzp2dP/Pe+9Z9P0ye1cynMquXRpG3Ty66+lPn1sMBWv1/9VooTUu7cluidM8G9tDgDhUrWqdMklgbc1bRreWHKMmthA7jCwI1AgLFjgv+y0uq5UyV3nlA5r1Uq67TYazQAAAIRMly52TzV1qv/6iy+29aNH24Alf/whzZsn3XST9Omndj/Wu3dIQgjZT7uzzpK++cZalf/1l7VqnD3bEvR791q5kbPPDtXZACB3Hn888Pqoz2/REhsAUEgtXy6tWeO/zkliv/qq3Tt9/nnYwwIAACg8+ve3qZP8ddx2m/0wS02VnnhCatFC6thReust216+vHT//SEJIeTZkLg4qWHDUB+1cBgxYoRGjBihI0eORDoUoMAqW9Y+Y195xX/9V19Z75eLL45MXNmiJjaQO7TEBmLa9u3W2zO9ypVt2qWL26MVAAAA+eTEE60V9rFjbiM7ybrCTZ0qXXGFNHOm/3uaNbOSIs4Aj3lENiSKDBkyREOGDNHGjRtVK9AodABC4v77pYULbVBaX5dcEsVJbMqJAAAKoWHDbPDlatWsLOG4cVYCzHk+BQAAgDDp1i3w+jp1pJ9/ttIcf/xh+YuGDa3GWwiRxAZQ6FStap+vgW6Ab79deu65KMwVU04EyB0yXUDM2r5dGjPG5j/4QGrb1l4AAACIQo0a2SufhCQbsnOn9P77lhRas0bat086fjzr93g80urVoTg7AOTOPfdYwtrXK69IJ50kDRoUmZgyRTkRIG8oJwLElMcflx5+2OarV5e6d49oOAAAAIiwPGdDPvtMuv56t6Z3sPeINIwCEGnPPCNdeaWNO+Dr2WelU06RNmyQOneWSpSITHx+aIkNAChEnAS2ZD1XuXcAAACIIseOSb/+Ki1ZIu3aZesqVLA62K1b50v39jxlQ+bOlS67zAag9HqtlUSrVhZzXFyoQgSA/OHxSMnJGdcvXy41bmzz990nPf10eOMKiJrYQO4wsCMQc9L/c23ZMiJhAAAAIL0DB6zL3KhRbvI6vfLlpWuukR56SCpbNmSnzlMS+5lnrGxIyZLSO+9YQhsAYkl8vPT111LfvoG3P/OM9NRTUdACjHIiAIBC4qmn/Jfr1o1MHAAAAPDx11/SmWdKf/+ddSOhXbuk55+XPvlEmjQpZHWy85QNmTXLEjv/+Q8JbACx6+yzs95eu7b0++/2MDFiKCcC5A4tsYGY89ln/stJSREJAwAAAI5//5V69pS2bLF7q2bNpAEDpHbtpKpVbZ9t26T586Vx46zMyN9/S6edJi1dKpUrl+cQ8lT0Y88em/bqlec4ACCiXnwx820bN0pTp4YvloAoJwIAKCTWr/dfJokNAAAQYc88I23ebPOPPy4tXizddZfUpYvVaU1Otvk775R++0164gnbd/Nme28I5CmJXa2aTSPezR4A8uiOO6xXSWZuuUV6//3wxZMB5USA3OFHChBT9u2Tdu/2X1epUmRiAQAAwP/78ku7t7roIunBB7O+z/J4pAcekC6+2Fptf/llSELIUzbktNOk0aOlhQultm1DEg8AmP/8R/r227Ce8tGj0uWeTKoObJZ0paTQPEDMuXXrbEoSG8idJ56Q3ngj0lFEh2LFpEcfzXwwACDMpk2zxjGNGkkrV9q68uWlH3+0sYB4FgUAABBhTle5gQODf8/AgVYXO303u1zKUzbk7rulDz+0Wt1XXCGVKROSmAAUdsePh6y7SU4Ul9Qsu52WhiGQrNSvH+EAgBjjjAi3ZYu9YN56iyQ2osLvv0s9etj82rXSySfbfJ067jwAAAAirGxZ6fBhqUqV4N/j7BuihHGektiNGkkffGCDOvbsaa2yTzwxJHEBKMxSU9358ePtwzKMHnhAmjM38+2XXCxdf3344klzwglS06YRODEQw/77X6lfP/vBBWva+vTTbokiIMJ++MGdHzbMpsWLW4lFAAAARInmzW2wsJUrpVatgnuP08WuefOQhJCnJPbVV9u0aVMbfLJFC4urcWOpVKms3+vxSKNG5eXsAAos3yR29+4hGcU2J+79XvrmG+nKKwNvXzpFuv7jsIYEILeKFpU6dYp0FNFj61abOoPFAhG2caM7/+67Nv34Y+nccyMTDwAAAAIYPFiaMkV6+WXpggukuGyGWUxNlV56yRLAIWoFmKck9tixbo06z//XkV2yxF5Z8XpJYgPIgm9R6ggUwkxMlC6/PPMkdosWYQ0HAELHqat//Hhk4wD+X6ASib17hz8OAAAAZOHCC6Xvv5fGjJH695feftt6iweybZslvefOlQYNsgEeQyBPSezatRloBUA+iHAS2znt8OHSzTdn3FayZPjjAYCQKFLEprTERpT47Tf/5dmzpRIlIhIKAAAAMvPuu1K3btLSpdZ1vV496YwzpLZtrfa1x2PJ6/nzrV7c4cO2rVs3t7tdIFddFXQIHq/XN1uESBoxYoRGjBihI0eOaPXq1dqwYYNq1qwZ6bCA8EtJkUqXtvl9+yI6auzNN0sjRmRc37+/fdaOGZP1A0gAiCoTJtgHWIcOli0EImjnTqlSJf91hw9bTWwAAIC82rhxo2rVqkV+LRTi4vwbGTplNgLJapsvjydHjWuyKWCCcBoyZIiWLVumadOmRToUILJ8a2JnV2cpn915p1ShQsb148dL550nff21lXkCgJjgtMSmnAiiwMKFGdeRwAYAAIhSXq/7Sr8c7LZA+wYpT+VEACBfREE5EUe9etL27W7eJ5AffpDOPFPq0SN8cQFArjg1sSkngiiwYEGkIwAAAEBQ1q6NdAShT2Knpkq7dlk1gBo1sk78AEBAUZTElqwx+NlnW9mnQH77TTr1VOnIEalYsbCGBgA5Q0tsRBGS2AAAADGiTp1IRxCaciLHj0ujRkldukilSklVq1rrxb/+8t/vm2+ke++VnnwyFGcFUGBFWRJbkj76SPr006z3WbMmx71hACC8aImNCPr3X/fSO3ZMmjHDf/vpp4c/JgAAAMSGPCex//nHktfXXy/NnGktETMra5KUJD3/vPTwwxlHIgeANFGYxC5TRurXL+t9GjeWhg0LTzwAkCu0xEaErF9vA9dfcIEls7t2dQd2XLxYuuWWrAeuBwAAQOGWpyT28eNS377SnDmWZ7roImn48Mz3b9ZMat/e5r/8Mi9nBlCgRdHAjr6KF7deJ9WrZ77P44+HLx4AyDEniU1LbITZq69aY5cJE6xX5uzZtv6mm6QWLWz7CSdENkYAAABErzxlh8aNk+bPtxqw334rffyx/RDNyjnnWCPLX37Jy5kBFGhR2BLbcfXV1pskK+eea71OACDqOOVEaImNMFu3zp1/7jmbDh8uPfpoRMIBAABAjMlTEvujjyy/NHiw1KtXcO9p1cqm6etlA0CaKE5iS9Jpp0k1a2a+ffx46Z57whYOAASPltiIEN8ktuOqq8IeBgAAAGJUnpLYv/9u03POCf49VarYdOfOvJwZQIEW5Uns+vWlDRukiROz3u+11/isAxBlaImNCPB6pbVr/dd9/rlUtmxk4gEAAEDsyVMSe88em1asGPx7nHsmpyEQAGTgWxM7CpPYjpYts95+663SvfeGJRQACA4DOyICtmyRdu/2X3f22ZGJBQAAALEpT0nsChVsumFD8O9ZudKmlSvn5cwACjSnJXYUJ7AlG4BqzZqs9/nqK7t5J18EICo4LbEpJ4IwWrQo47rixcMfBwAAAGJXnpLYJ55o0/nzg3/PJ59YXqpt27ycGUCBFiNJbEmqW1fq2zfz7Tt3StWrSzffHL6YACBTtMRGBMyZ479MAhsAACBK7d1rryiUpyR2//6Waxo+PGMXwUD+9z/p669t/vzz83JmAAVaDCWxJentt6WhQwNvc/6UN98MXzwAkCkGdkQEzJ7tv5yYGJEwAAAAkJ3ERCu9sWyZ//p337VXBBPceUpiX3edVLu2xX/GGRn/Psc//0gPPihddpnlpJo1ky66KC9nBlCgOTWxYySJfcIJ0mOPZb9fx47SunX5Hg4AZI6BHRFmx45Jc+f6r6tfPzKxAAAAIAhOazxfAwdKgwZJGzeGPRxHnpLY8fHShAlSQoK0cKHUvLnUtKm7/YorpORk60r/9NP2I7ZCBRuNPEZyUwAiwfnAjMvTR1TYPfKI1K5d5tvnzJGefTZs4QBARrTERpgtXSrt32/3C++/b+UIR4+OdFQAAAAIyLlfOHIksnEEkOcM0UknWU3sjh0t77R8ubtt8WJp1SprVOn1WnJn7lypQYO8nhVAgRZj5UQcw4ZlbG2W3r590pNPRvThJYDCjJbYCLOpU23avr10+eWW1G7cOLIxAQAAIBOVKtk0s3IbEVQ0FAdp0ECaOVP65Rfpq6+kBQushMjx41LFilKrVtI550innx6KswEo8GI0ie248UbpjTcCb3v/fZtOny798EP4YgIASW7LCq/XWhnEWI8XxJZJk6Q777T5rAZBBgAAQJTo2FEaP1667z7p33+txEaxYu72+fOlHTtyftyuXfMcmsfrDVToBJG0ceNG1apVSxs2bFDNmjUjHQ4QfuvWSXXrSiVLSikpkY4mx44ftxJL7dtnvd+KFVLNmvZnAkBY7N5ttd0k6yLo+4MUCKEvvpAuuMCel5QpI61d6zbsAQAACAfya7kwc6bUvbs7VpkjL40NPZ6QlDOk+Q2A6ON8WMZoC8EiRaSTT85+v+Rk6dJL7bOc8rQAwsJpiS1RUgT5YsMGacsW6e677V7niiushAgJbAAAgBjQqZO1Rqhf337MOS+H77qcvEIgJOVEsrJzpyXcnUY/yNyIESM0YsQIHYnC4ulAWMV4ORHJ8kRffWWDWV12Web7TZhgtUErVrSBH2P4TwYQC4r6/PTj6RlCbNo0qUcPd7lCBemtt6RSpSIWEgAAAHKqb197bdggbdokHToknXqqJSxGjbKe8xGQL0nsbdukoUMtcb97t61LSJD69ZMee0yqXTs/zhr7hgwZoiFDhqR1dwAKrQKQxJbc+p9ZJbElafVqe1WqZN8FM2Zwww8gn9ASG/no22/9l087je8zAACAmFWrlr18tWsnNW0akXCC7qu/caNUvbq9MhuwTJLWrLFu9KNGSbt2ua3G//1Xeu89G+Txt99CEDmAgquAJLEdr70W3H67dlkt7RNPtMFwt27N37gAFEK+SWxaYiPE5s/3X+7SJTJxAAAAIMSuuspe5ctHLISgW2J//70lVIoXly66KPP9LrlE2rzZXa5VyxLfy5ZJ+/ZZy+xLL5WWLPHv0QoAaWK8JnZ6N98sde5sD/GCsW6dvc47T2rTRrr9dqlevXwMEEDhQUts5BNnUGNfzZpFJhYAAACE2NixkY4g+JbYs2fbtEcPq90ayDffSAsWuDWwv/9eWr/e3rt1qzRokO23YoX0+ed5DR1AgVXAWmJLloROSMjZe2bPtlbc118vvfyylRwBgDzxeNwHhLTERggtX27jQPhKSopIKAAAAAgHr9cSFfPn22v16pAN4hhI0EnsJUvsvuf00zPf54MP3PkXXpDOOMNdLllSGjlSat7clidMyGmoAAqNApjETkiwckt//pnz906eLN1xh/V0WbgwX78TABQGTlc4WmIjhNKXEpGkmjXDHwcAAADy2aRJNghYQoKUnCx16GCv5GRbd8450g8/hPy0QSex162z6UknZb7PtGk2LVcu8EBmHo909dWWgFm8OPggARQyBTCJLVkvlsaNc//+BQusvMh774UuJgCFkFNShCQ2QijQQ1pKBwIAABQgR45YwrdPH+m776QDB9zBEJ3XgQM22nfv3rbvkSMhO33QPy337rVppUqBt69bJ23bZjmnrl2lYsUC7+fUhPWtmw0AfgpoEtsxY4a0ZYt08cW5e/+LL9p4CgCQK05mkXIiCKG//7bpzTdLY8ZIV1wR2XgAAAAQYpddJn35peVsiha1ch3t20snnGDbt26V5s2TfvxROnpU+uQTu+f49NOQnD7oJLaTS8osgT5vnjvfpk3mx0lMtOmBA8GeGUChU8AGdkyvSxebVq1qn+mffCLt2hX8+48etQFzn3jCercAQI7QEhv5YMMGm3btKj3/vBQfH9l4AAAAEELffit98YUliHv0kEaPlurUCbzv339bsmLKFBsU8bvvrPV2HgWdIXIGc1yxIvD2WbPc+bZtMz/Ovn02LVEi2DMDKHQKeEtsR7du0uuv20PKU091e6pkZ9kya8l9zTX5Gx+AAoqW2MgHTkvs2rVJYAMAABQ4Y8fa9KSTpO+/zzyBLdkPwokTpZYtbXnMmJCEEHQS26mF/fnnGbd5vdJXX9l80aJSp06ZH2f9eptWrRrsmQEUOoUkie1o3doGb/z8cxsEKycPKO+8Uzp4MP9iA1AA0RIbIXbkiLRpk83Xrh3ZWAAAAJAP5syxHM1dd2VeQ9pXsWLS3XdbfmfOnJCEEHQS+5xz7LwTJmQcVOz5560mtscjnXaaVKZM5seZPdumjRrlIloAhUMhS2I76ta17tiffGK9X5o3z/49L70kvftu/scGoABxkti0xEaIfP65VQKrXJmGKgAAAAXS9u02bdo0+Pc0bmzTHTtCEkLQSewrr5Rq1bL5gQOtbvfll1sLwv/8x93vzjszP4bXK40fb3mpDh1yFzCAQqCA18TOTpky9mBw4UK3139Wtm2zkiQhHPQXQEHmfLDQEhshsGmTjfEjSWeeWWi/ugEAAAq20qVtunNn8O/ZvdumpUqFJISgf2aWKiV9/LElV7xeacECW1682G00efXVUs+emR/ju+/croannZaXsAEUaIW0JbavMmWs983ff0tLl0pVqmS+77Bh0hlnSM89F774AMQwyokgRPbvl846y12+9dbIxQIAAIB85JTU+OST4N/j7Buichw5aivRsaMlr88/3wZm9HrtVaeOlRR5++2s3//44zY94QRaYgPIAknsNNWqSSeeaCWk7rkn631feUU6dCg8cQGIYQzsiBB5+GFr0OLx2Pg+bdpEOiIAAADkC6fO9Jgx7iCPWXnvPWn0aPuh2L9/SELweL1OtihnUlOtHErx4lL58sG958ABmxYtyqjlWdm4caNq1aqlDRs2qGbNmpEOBwi/+fOldu1sdChnNFho82apRo2s9/F4pKeeku67LzwxAYhBTZpIy5dbiwSnVTaQXtWq0g8/SPXr+63eskV66y1ryP/EE7bu/fetzCAAAEA0Ib8WQgcOSMnJ0tattty7t5XkaN/euo57PFbrdO5cS15PnGhJ7xo1pL/+CklJkSCqrQYWF5fzgVuc8ikAkCVaYgdUvbp0++1SQoL02GOB9/F6pS++IIkNIAvt2lkSm64byMqaNdL06RmS2H36SL/95i6ffLJbExsAAAAFVOnS0jffWH3o3bstST1xYub7e73W6vmbb0JWEzvXSWwAyDeFfGDHrLz0kk0zS2JL0rx50oAB0osvShUrhicuADFk7Fjp0Ufdz1ogveuvlyZPdh8q/7/UVP8EtiR9+y3PnAEAAAqFVq2kJUuk226Txo/PfIydIkWkc8+1BEZ23clzgCQ2gOhDS+xsXXih9NlnmW9/91172FmjhjRwoETPKQBpPB4pKSnSUSCalSlj03QPOh54wH+3s8/Oec9MAAAAxLDq1S0ZsWWLNG2atHSptGuXbatQQWrWTOre3Qb4CjGS2ACiD0nsbH3yiXTllTa2QmbefNOms2ZJgwdLrVtLtWqFJz4AQAxzekKlS2J//bX/bk2bhikeAAAARJdq1aRLLw3rKemrDyD6kMTOlsdjYyoEY+JEGwz49NOlDRtsUF4AADIVIIm9c6e0bJn/bjToBwAAQLiQxAYQfaiJHZRGjaTvvrPa18H46y+pdm1rkf3vv4zpBgDIRIAk9tKlNi1SxN2tTp0wxgQAAIBCjQwRgOhDS+yg9e4t3XRTzt6zcaOUmGgJ7X//zZewAACxLEASe906m7Zv7+5WpUr4QgIAAEDhRk1sANGHJHaOxMdLzz5rLasffjj4923fbsnspCRp0qTgy5MAAAq4LJLYJ55orbF37JBatAh/aAAAACicaIkNIPqQxM6xe+6Rhg7N3XvXrZNOPlnq2VNasCCkYQEAYlEWSeykJBuIfskSqXjxcAcGAACAwookdhQZMWKEmjZtqu7du0c6FCCynJtmktg5dscduXvf/v3SlCnSxRdL118vzZoV2rgAADHE+f71SWIvX27TpCTLcfvWxgYAAADyG0nsKDJkyBAtW7ZM06ZNi3QoQGQ5LbEZ2DHHXnxR2rlTKl06d+9fs0Z65x3p/POll16SZs8ObXwAgBiQriX2v/9K8+fbqlNOiVBMAAAAKNSoiQ0g+lBOJE8qVJDWrpV275YaNcrdMbZule68UypVyo61c6fUpElo4wQARCknif3/38dTpkjHj9vYCUlJkQsLAAAAhRdJbADRhyR2nlWubK81a6wFXfv20pEjOT9OSopUtarNr19vA0EmJNixPB6pWLGQhg0AiAY+LbGPHpWuu84WzzgjciEBAACgcKOvPoDoQxI7ZOrWlVq2tAG43nxTat4898fq3VsqX16aPl3q3l2qWVPaty9UkQIAooZPEvvtt603jiT16hW5kAAAAFC40RIbQPRxBpKiJnbIJCfb67TTrNb1hg3SV1/l7BjLltnUd+zZIUNsEMgpU6TatUMWLgAgknyS2B9+aLNNmkh9+kQuJAAAAESRo0elX3+Vli6Vdu2ydRUqSM2aSa1b50u3bTJEAKIPLbHzTf360vDhNnhjnz6WhM6L996TVq+WPv44NPEBAPKX8xUr2f1Gu3bS/ffb8m+/ST17SqvW2i3CujWpmjVLKlJE+uknni0DAIBCaP166a67pMaNpdKlLVHbtq303HNWfzNUJk6Uzj3XujzHx9v03HNtfXa2bZNGjpQuu0xq2lQqU0YqXlyqVk0680zp7belgwdDE2dKiv14rFbNRvy+/nrpP/+x1/XX27pq1aQHHgjtfx/REhtANCKJne+qVJG+/VY6fFiaOdMelr7/fu6PN3y4tHy59NBD0pYtduxHH6VmNgBEWkqKdXAqU0Y6dEjq0MHGNpg+XbrvPmn+fHvt32+f5ZL0a6U4NZD07ljrGTVggFS9euT+BgAAgIj4+mvpiiukvXvddSkp0oIF9ho50m5+GzTI/TlSUy35O2qU//pNm+w1frx07bXSW28FblHwzjvSjTfaKNzpbd1qr0mTpOefl/73P6lFi9zH+vff1r179Wr/lhHp7dolPfOM9Pnn0uTJlpAPAZLYAKIPSeywiY+XFi2y+RUrrHZ2bh7QbtggjRkjlSghvfGGratf376PL77YEiYAgPy3b581GGrWzL5OO3eW1q2T1q6VPvxQWrzY9rvxRrvvcjgJbEnatuP/b5C8qera1cpQAQAAFCqLFtnN7MGD1hrg/vulHj1s+eOPLXm8YoV01lmW0C5bNnfnefBBN4HdqpV07712M716tfTssxbHyJFS5crSf/+b8f3btlkCu3hx6eyzbSTuJk0sntWrLc4ffpBWrrQE9K+/5i6pfPSoDZS1apUtN24sDRoktW8vnXCCrdu6VZo3Txo71uqRrlxp71m0SCqa9xQ0SWwA0cepiU0SO6x+/tlaZvftay30cuOdd9z5a6+16bZt1kIbABB6+/db45pzzrHeLx07Sn/8YfcKS5a4DyrPP98awjjeeivjsYoXl44ckVL/v+Jg3dqpmjTJHlACAAAUKrfdZgnrokUtCdyxo7vt1FOlhg0t4bxihfTCC9Ijj+T8HCtWWAtpSWrTRpoxQypZ0pbbtrUfeN26WZL8ueekq6/O2Oq7dGnrXnfXXZbo9tWqlXTBBbbtxRel7dulhx+WRo/OeawjR0p//ml5mgcesL+3SBH/fZKTpa5dpTvvtO1PPGHJ7JEjpRtuyPk506GyHYDo47TEpvhmWBUvbg9rv/nGviMvvTTnxzh2LOO6r7+2hIrzbGL37rzFCQBwnXKK3ZuMGWNlof74w9afdZZ01VXufr4JbEfr1v7LTz9tUyeJfeYZqSSwAQBA4TNvnrXykqRrrvFPYDvuustaPEvSK69YS+Wcevll9yb6tdfcBLajVClbL9l+gbrH3XGH/YhLn8D29dRTVqdakr74wr05z4nPPrMEdv/+0uOPZ0xg+4qLkx57zGp6e7323hAgQwQg+lBOJKLKlJFOPtnKgowebeMz5MW8edat/Y47rE52hQqWKAcA5Ny2bdZa2uu1z9UlS2z94MHSlVe6+23enPG9zZr5N965/nr/7X362NRJYleqkIsbHAAAgFg3frw7P2hQ4H3i4twWA3v2SFOn5uwcXq80YYLNN25sA5cE0qGD1KiRzU+YkHUt6swULy516mTz//4r7dyZ82MsXWrTq68O/j3XXGNT5wdrHpHEBhB9SGJHhXLl7Pv64YctkT1uXN6O9913bg+rvB4LAAqqjz6yQeT37LGvw48/tnrVXq90++1WcrB5c+nTT63xTlZq1LAyhI5zzrHPdkfnzv77165tU6/s+9fjJYkNAAAKoV9+sWnp0tbCKzPdurnzM2fm7Bxr17qtDnyPk9V5Nm2ywU5y4/Bhdz6rVtSZ+fdfm+ZktG+n9bfvwJh5QBIbQPQhiR1VSpa03kdXXml1rnv0sNZ8malYMfB6Z/wHyQZFbt7cWmRPnCj17GkDHQNAYfPZZ5ZsnjPH7i0uu8xqXI8ZY0nrSy+VbrlFGjHCeqpKVj7xgQcyHis+3r/cYI8e1vvF0amT//1Lw4b+73dKhzgtsXPV0gcAACDW/fmnTRs0yHpAwsaNM74nWMuWBT5OqM8jWamT2bNtvmpV/x+IwXLes3Zt8O9x9s3N+QIgiQ0g+jj1maiJHVU8Hhu4ccoUK6OVnGytBdNr0SK44y1daq0I+/SxY772mvTJJ1ZyhLwJgMJg8WLpoousEc6gQfa56liyRHr1VXc5/QC5a9bYdOhQd1379v6NYzp29G95nZxsLbwdxYu786VLu8+O05LYuamXCAAAEMsOHZJ27LD5mjWz3rd8efsRJUkbNuTsPBs3uvPZnadWLXc+p+eRpLffdv+mCy/M+fslG0zF67WWFcF6/XX7gdmqVe7OmQ4ZIgDRh5bYUa9hQ+mvv6zbe6VKUvfu7rY6dYI/ju9AY5s3S5dcYiVHvvvOvu9yMzYGAMSCv/+2wdsdy5f790gZM8Z/f6cHp6+6df17xnToICUmussNG/p/jtaq5Z/E9uX7PpLYAACgQNm3z0paOC/frmmB9nWUKZP9sZ0k9v79OY8p2PM458jNedaskR580D3P/ffn7P2OSy+16bRpVhf7wIHM901JsW7cU6bY8mWX5e6c6WTRJh4AIoQkdsxITLQHwcWL2+v4cXfMiZz68EN3/uyzbVqunNVs3bvXyo8AQCw7ftzKhxQvbr/pA5UHbNDAv/ySr1KlrDfpr7/actu2/snn+vXdkiCSlJTkn7SOj89YAvGZZ6w0yfvv23KXLlLqzySxAQBAwZHQtKn/imHD3AGb0jt0yJ337baWmfh4mx48mLOgcnIe5xw5PU9KinTeeW5riNdey1lNa1+XXy69+aY0a5YNcvXdd9alsH17qUoVy99s2ybNnWuDt2zfbu/r1MneGwIksQFEH5LYMcVJmGzebN+R27aF7tjz5klXXGFlyLZssQozZctKxYqF7hwAkJ927bLPxcaNbQD7Dz+0zzLnc+yCC2ycAMlqY191lQ2o6zjrLOnbb22+eXP/cQfq1fMvF5KU5N8ztXZtS3z7+vRTawzz1lu2fO+90s03u/tNmiQdvDdOGi6S2AAAoEDYu2yZEmrUcFf4JoXT820RcORI9gd3WnWXLJmzoHJyHt+W48Ge59gxKx2yeLEt33ijNHBgjkL04/FIX39tP07nzJH++cdKiwQqL+LkdDp2lCZMyP0506GcCIDoQ03smFSliiVQ2re3hMuSJXk/5nvv2fTYMemHH6xUyVln2TrqZgOIdkePWsvq5s2lvn3dHiepqXYvEh8vnXOOu3+XLv4tq5OTpSZN3OW6df2T2ElJGZPYvknr+HjpscesxbbzeXrGGdYw5vzz3f1831OypFShIi2xAQBAAVK2rJSQ4L6ySmKXLevOB1O6wymrEUzpkdyex7d0RzDn8XotYf3dd7Z80UXS8OE5iy+Q8uWlX36xFt1Nmth5Ar2aNLHz/fyzvSdEaIkNIPrQEjvm9elj008/tUTNbbdZa8Sc2r3bnXd6IP34ozR9uiVgnn3WynEBQLTweu3rKyXFSiM5n2NOa2pfbdtKJ5zgLp94on8Se9Qo++3vqFPHv+dp+iR27dqW6L7iCnesgtq1rVeLr2y/XuNIYgMAgEKqRAlrNbBzp38Xt0B273YTzL6DLwbDdzDH7M7jO5hjMOcZMkT64AOb793b6saFqpFgXJwdf8gQ6y69dKl7s1+hgg3YUq1aaM6VDklsANGHJHaB4Qx8XKKEdV3v29cS2pmpXNktnZUVJzlz110ksQFEj7VrrTX1xRdbGaSpUzPu07Kl9NtvNt+oUcaW1L7j9iQlSX/84b/s2xAnOdnuEV5+2RrzOL1SnVbXuUYSGwAAFGZNm1pLglWrrFtw0UzSp8uXu/O+3eeCPUeg4+T1PPfdJ73xhs137Sp9/nn+1eOsVi3fEtaBkMQGEH1IYhc4F1xgL6/XWlGXKOE/kKPjxBNtsONg7dljrb4HDZLWrbPfFnfcEaKgASAHtmyxGtWS9OKLbk/PokXt3keyZPPMmW4SOynJv+V1UpJ9ljmqVbNyJI4WLex+5/Bht9W1lPXDwVwhiQ0AAAqzzp0tiX3ggLRwodXMDGT6dHe+U6ecnaNuXRtkcfNm/+MEMmOGTWvUsB+MmXniCeuuLFmXv2++yXmt7ihGEhtA9CGJXWB5PPYgWJKKFLHWgj16uK0VfWu9BmviRHs5WraUVqyQrr+eSwhAeKSmWk8TX/v3233GWWdJb79t6046SVq50t0nKcnKMjpq13bvS2rXts/JU0+1UiRxcTY2jscjPfBAfv41IokNAAAKt/79paeesvkxYwInsVNTpXfftfnERLuxzQmPR+rXz1pNL19ugyV26JBxvzlz3JbY/fplfpP7yivS0KE237y59P33/nW3CwCS2ACiDwM7Fgrjxtn3bNGilsQpUiQ0/8tPPdWmDRpIBw9KvXrlX+8pAIXXsmVWJmnFCktgL1yYcZ9u3aw0oKNuXRsE15GUZGWUmjWzz8CaNe1zcMMGt4W2x+OOMxA2JLEBAEBh1q6d1Yj7+WcbpGTAAGtN4OuFF6Q//7T5227LeNM5bZqb2B4wQBo7NuN5br/dWjscPy7dcou1uPZtOX3woK2X7Mb59tsDxztmjNslOTnZBpLy/RGaE4895s4//HDg9bnhe6xcIokNIPrQErtQ8HjcgYo3b7YSI99+K332WWiOf9ppNh071n4zAECorFpl9zF799ry99/b9KabpNdfd/c7/3xp1ix3uUYNa0Dz7rs2oGObNpa8XrTIPhOd3LHvOD8R4Xz/ksQGAACF1SuvWImQgwelM86wrnA9etjyxx+7Xe2Sk22wptxITpbuuUd6+mlpwQI73333SfXrS6tXS888Yz8UJduvYcOMxxg/XrruOsujJCRY3Nu3Zz3YVN26/gOx+HrkEfe3oG/i2Xd9bpDEBlAgkcQudJyxIC67zBLbVarYw+9Q+O47Sxr51p0FgOzMmSMNHCg9/7x09tn2WfLJJ9bbY9o0N4Htq3dv/yT2eedJkya5y0WLWkmRVav835fZWEER42TTne9jAACAwqZVK/vxd8UV9sMvUD235GRriZWXsh1PPin98480erQlrC+5JOM+11xj9a4DGT/eWnJLFmfv3tmfc+pUqXv3zLdn9hswwr8N6asPIPqQxC604uKsfmzbttLIkdJDD0kXXpi3Y376qSXGX3opNDECKBy6dZP++ssGpR03zj6b3n3XBpL96CPbp1cv//eccoo7n5xs0yuusGnbtvkfc8hQTgQAAMBqxv3+u5XqSE6WSpWy1lFt2ritpH1H4c6NuDgrWfLtt9b6qnp1qXhxm/brZy0pRo4MX7nV1FT3ldn63LxCINrafQAANbEhyR42S9KOHVKZMtLVV1tZMsnGqViyJGfHu/NOG6j5hhukYcNCGyuA2PfCC9b6+sMP7RnqkSO2/vBh6e673f28XluXmCidc47b0rpCBf/Sg06DnC5dpKVLpTp1wvJnhAZJbAAAAFOnjvTii/bKie7dc9ZyuU+f3A2EMnZs4HrbBRBJbADRh5bY8FGpkvWskqQJE2w8iXfflU48MefH2rrV3l+smJSSknmPLACFy5EjbqL6+uulN9/0375jhw3CuG+ftHOnrTvlFLcUkmTbJSk+3pLcvj05c/N5FVEksQEAABBlSGIDiD4ksZGJc86xl2Rd9KdNkzZuzNkxUlOlBx+0+Q4dpOXLrXfYF1/Y4JJ9+4Y0ZAAx4H//c+cHDZI2bcq4T9++Vj7QSWI3aSJVruxud5LYixZJX31lg9THLJLYAAAA8HXqqZajGT06+C6GmzfbjbvHI02enOcQSGIDiD4ksRGE996z/Mqtt0ojRuTuGE7CeudOGxBashq4GzfadzSAgmnDBmnlSvt3fttt0quvutucBHa3btL06e56pyyIIylJqlrVf1my5HaTJvkVeZiQxAYAAICvadMsR3PgQPDvOXjQfV8IUHA2iowYMUJNmzZV96xGCAUKA+emmSQ2shEXZ8mnv//OW51rJ4EtSY0aST17WjIbQMGzc6dUu7b9O3/nHf8Etq/nn/dfPuccqUoVd7lOHRvH59prpa5drQV3gUESGwAAAFGGJHYUGTJkiJYtW6Zp06ZFOhQgspyW2AzsiCDExUm1akkPPGADrI0ZE5rjrlxpD44l6dgx6fjx0BwXQPht3mz/nrdutTJCjttvt+k110hXXumuf/NNqUYNd/mxx6zWdfryIR6PJcKnT5eaNcvPvyDMSGIDAAAgr5xW2yVKhORwZIgARB/KiSAXiheXzjhDuuoq6Y03pO+/z9vxHnpISkiw3k99+kg1a0p794YkVABhNGeOPeg6+2ypc2dp1Sp3W0qKTS+/XEpMdNefdJL/cqVKNj3rLKlUKal1a+u1UWCRxAYAAEBeTZxo05o1Q3I4amIDiD4ksZEHcXHSDTfY/DPPSGXLSjfdlPPjLF5s0x493HVLl0qnnJL3GAGEz4ABloudMsVdV7++tHq1zRcrJrVvbz05HElJ/g1GnIT2mWdK+/bZ11OB/ooiiQ0AAFC4XX114PUPPeTf2iOQw4ftx/b8+fajuVu3kIREEhtA9CGJjRC5916bHjhgLaq//TZvx+vVywZ3GzNGevddGwDupZe4VIFo9fLL0ooV/uvOPFNq2FB67TVbbtTIWlfv2+fuU7Wq/bvu1ElatMje4ygUla5IYgMAABRuY8dmvNH1eqUJE4J7v5PXqVBBuv/+kIREEhtA9HFumgtFpgDhcPfd9nr9dWnoUGnXrtwdZ/9+6xH1+OPSiBG2rmNHadkyeyBdrFjoYgaQcwcOSNdfb8nnKlWkO+7IuM8HH/gP5li3rk337HHXOb/Xp061hiRlyuRbyNHJ+Q9AEhsAAKBwql3bP4m9fr0tV6uW9Y2vx2NdGqtVs27MN94oVa8ekpBIYgOIPrTERj656Sb7Dv3f/6SLLpKaNJH+/DPnx3ES2JJ0ySU2bdTIWnempISstxSAHBo6VPrwQ3s5brtNeuUVmy9WzBqDVKzobk9Ksum119r7fEsIFStWSB9OOQ+Rne9jAAAAFC7r1vkvO78Pf/hBato07OFIDOwIIBqRxEY+8nikCy+UtmyRPv44dMddvFhq107q3t1adP75Z+5bfAPI3sGD9sDotttsedUqK++T3qOPuvMJCTatUMFd5ySxe/SQli/Pe9mhAoFyIgAAAPDVtau9SpeOWAgksQFEH5LYCIMTTpBatJB+/tkeJl96ad6O51ue4OWX7eH0JZdYou3YsbwdG0BGH30kzZhh//bWrrXSPulNniyVK+culy1r00aN3HUnneTON2oklSyZP/HGFJLYAAAA8DVtmtXaq1MnYiFQTgRA9HFumkliIww6d7ZpmzZWsmvLFum//835cQ4dcuedlp8//miJ8rg4q5tdpEje4wVgfv/dnW/WzEr5NG8uLVnirnf+fTucJHabNvYA6+hR6z2BdEhiAwAAIMqQxAYQfZyW2AzsiDAqX166+WZLRh8+bEmxQYMy379aNUt4Z2fVKpsuXCgNHChddpkNAgkg93btkqZMcZdTUmw6apSV9XEUL27TTp2kmTOlIUPcbekT3PBBEhsAAABRhgwRgOhDORFEUIkS0vPPSwMGSFdfLbVvb62p03Pq6Aarc2erkz10qPTrr9IZZ9gUQM588IENcO7b4lqSrrxSatvWXfbt+fD111Y26LrrwhNjzCOJDQAAgECOHJHGjJH69bOb4jJl7Id3Vq+ioWlDTUtsANGHJDaigMdjrTolafVq6dRTpSZNpEmTbJ0zQFywjh51508+2aYHDlj5g2LFpOeeswQ6gIx27rTa8kWLSoMHW2+JxEQbRNXx9NP+7/H9N1q+vHT66eGItIAgiQ0AAID0VqyQ+veX/vrLzduEEUlsANGHJDaiTP360vr10t69Ur16UoMGbvmCvJg1y16SlUDYt0+6/HL/geiAwm7RIisHcuiQdNZZ9vCnZUsr0ePb2rp6df/3BepBgSCRxAYAAICvAwek3r1tRPW4OGuJXbmy9M47lrt56CGr+bdggTR3rq3r2DGkLUlIYgOIPs5NMzWxEWUSEqR166zF9Kef2sBwxYr5t7LOrauusumOHVa3d+1aG3wOKGy8Xmn3bqlCBWnOHOnMM6WDB23bN9/Y9MorM/+K+OEH69nw9tvhibdAIokNAAAAX2++aTepRYpY9+RTT5X++MOS2JL06KPuvosW2Q/2OXOkSy6xwadCgAwRgOhDS2xEsTJlrKTBpZdK8+fbg+ZQmjbNSou1bWu/Cfbts9IJQGHx5JNSxYrS6NFWS/7ffzPu061b5u8//XRLZOe0bj18kMQGAACAr6+/thzNRRdZAjsrrVpJU6dKVapId95pXShDgCQ2gOhDEhsxwOOxltItWkhffGEPpi+7zLblpbb1kiXS/v02P3261LixdNJJ5JJQeAwdatNrrpGOH7cyIY884m6Pi8tYKoSOOyFGEhsAAAC+li2z6bnnBt6e/ndj5cqWwD52TBo+PCQh8JMfQPQhiY0Yc+65Ntjca69J998v/fpr7o+1Y4c7/8wz0ubNNm7GggVS3brWSvXQIemzz6wsmdcrffWVDT4JxJqUFBvg3PHFFxn3eeklu/YdNWtaGR9JevFFm37ySf7FWCg5378ksQEAACC5I6rXqeOui4935w8cyPieTp1sOn16SEIgiQ0g+lATGzGqQgXpv/+VmjSxcgb9+wcepLFUKXe+cuXMj/f33+58+/ZWj/uhh6SePa0X1+uvS7fcYmNqDBhgCe9t20L11wD5a88e+w3cvbstT55spfN8nXaaXetVqrjrfMuE3HGHjR9zwQX5HGxh43z/RmDUeQAAAEQh5ybWt7FhYqI773vzmt7WrSEJgQwRgOhDS2wUAKefLn35pY150aiRtZZ2+CbhmjfP+bFnzbLpK69II0bY/MyZUo0a0sknW48tINp98YX1PJg928rk9eljLbN9tWtn08yS2JJUvny+hlk4UU4EAAAAvpyukZs3u+sqVbKWXJLdkKbn1MIuXjwkIZDEBhB9SGKjAGnfXlq+XOrbV3rwQauXPW6cu71Wrdwfe9OmwOucnl5ANPvrL3e+TRsrK3LmmdKHH7rr69WzqW+vxdw8+EEOkcQGAACArzZtbLpggf/6nj0th/Pcc9ZF0rFmjfT005bXadkyJCGQxAYQfUhio4B64glLMLdpI5UsaesaNQr9eUhiI9p5vdZLIb1XX/Vvae0krytWtB4IH3wgDRkSlhALN5LYAAAA8HX66e6ATL5uvdWma9ZIycnShRdaF8uWLd1W29dfH5IQSGIDiD4ksVGAOWNfbNggbdxoNX9DjSQ2otnOndJ//iMtXuy//tlnpYYN/cuD+Ca0O3aULrvMfQCEfEQSGwAAAL7OPlvq2lUqW1Zavdpd36mT9PDDlsfZtctqBk6aJO3fb9sHDbIf8SFQNCRHAYBQYmBHFAIVK9q0Rg0bBLJWLRsQUrJE9+HDuT/2FVdI770ntW2b9ziBvEpNld54w67vpCSpQwdp+/aM+w0YYNNKldx1eSm3gzwgiQ0AAABfpUpJ06YF3vbII1KXLtLIkdIff9ggTQ0bSlddJZ1/fshCIIkNIPrQEhuFzOmn2/Tzz22Qu4YNpcGDg3tvmTLuQ27HX3/ZgHjOPyUgkl5/XbrlFpu/9FJLYJcpIz30kDRsmPvAxhm8sVIl6bPPpNKl3Z4LCDOS2AAAAMiJnj3tlY9IYgOIPiSxUUidd569Dh+2wZ0PHpQSEqRRozJ/T5069rA7kJ9+st8R/FNCpKSm2oCmjs8+s+n06VLr1lZWJJALLsj/2JAFktgAAADw9e67Nm3USGrfPiIh0FcfQPQhiY1CLj5eGjdO+vRT6ZprpPr1pV69pFNOse2lSrn7Vq2a+XFOPz3zHl9AOLz2mrR3r7t87Jg9eGndOnIxIQgksQEAAOBr4ECrb71+fcRCIIkNIPpQExtI07GjtGqV9P33lth+8klrpd2pkz3nufDCrN+/fHl44gS8Xmn4cBugceVK6dRTpdtvz7hfly4Z1/k+mEEUIIkNAAAAX+XK2bRhw4iFQIYIQPShJTYQUIMG0gMPSC1bSjNmSP/+K91wgzR/vnTnndKtt2Z8z003SbNmhT1UFEKTJ1vt6/vuk5KTpalTbf3dd/sP1tiihTv/7bfW02DSpPDGimyQxAYAAICvunVtunt3xEIgiQ0g+pDEBrIVFyeVLWvzbdpIL7wgXX994FauN90U3thQOE2fnnHd669Lzz3nDtooSUlJ7nyfPtbToHPnfA8POeF8/5LEBgAAgCSde67lar7+OmIhkMQGEH1IYgO5cuKJ1kI7vcWLpUceCXs4KES8XhtI1FeTJtKNN9p8hQruet8kNqKU0xLb+T4GAABA4XbbbTa4zRtvWBfMCCCJDSD6OC2/SGIDuRKoTvajj0rr1oU9FBQCXq/0wQfSnDn+67t2dedLl3bn69QJT1zIA8qJAAAAwFdCgvTjj1LjxtKZZ1o34GnTpF27wtbwoWhYzgIga5s22YcBLZ7M0qU2ZWBHIFc+/ljq0SNjGZEPP5Suvda/tAOQU16vDTTavLlUrJjUu7e0aJFtK1NG2r/f5n1rX59yitW9btBAqlw5/DEjh5zv35QUacyYyMaC6NamjX0YAACAgq1IEXfe65VGjbJXMDwe6dixPIdAEhuIBpdcIv3yS6SjiD7Fi0c6AiAmxcVJ7dtnXP/gg9J770l//hn+mFBwvPSSdNddUq9elpB2EtiXXGLrBg2yZWfsF0kaOlQ6/3wrJUInmxhQooRN9++Xrr46srEgupUtK23fLsXHRzoSAACQn9I3uoxAI0yS2EA02LLFph07SuXLRzaWaJGQIA0YEOkogJjVurU0bJiVEfG1fLl06JCbowJy4vhxS2BL1rLaaZAxe7bUoYOtc/jWvvZ4rGY7YkTdutIDD0i//RbpSBDNvvtO2rdP2ruXLhYAABR0w4ZFOgKS2EBUOH7cpi+9FLj5JADkwjXXZExiSzbI3s8/SyefHP6YENvee89/+fhxqyTQoYMt+/YypPZ1DPN4pCefjHQUiHbx8dKRI9LBg5GOBAAA5LcoSGJTcBaIBk4S2/fuHwDyqGZN6Y47Mq4/eFCaMSP88SC2jBljra6dnoLLlkkPPZRxv27d3HmnDnaJElKpUvkfI4AIKlnSpiSxAQBAGJDEBqIBSWwA+cDjkV58MXBr7DvvlB57LPwxITYcPmylkF98UZo/X7rhBisHsmmTVL26/76+LfqrVJHWrJE2bgxvvAAiwKlLdehQZOMAAACFAklsIBqQxAaQj7p0kYoGKCA2bJi0Z0/Yw0EMWLDAnR8/XnrrLZtv21b68Uf/muq+Azg6yxUr5nuIACKNltgAACCMSGID0YAkNoB81KOHtHNn4G2PPSZt2xbeeBD9Pv3UnX/qKZvefrs0b57UtKmUmOhu9x3AEUAh4iSxaYkNAADCgCQ2EA1IYgPIZwkJUvnyGde/9JJ0663hjwfRa/Vq6Y03Mq6/6ip3/sgRd75GjfyPCUAUcrpk0BIbAACEAUlsIBqQxAYQBr/9Jt12W8b1CxdK+/eHPRxEGa/XBnNs1Uo6etR/W0KCO2ijJLVubdOaNQOXqgFQCFBOBAAAhBFJbCAakMQGEAa1a0uXX55x/erVUqVK0u+/hz8mRNacOVLnzjZ97jkbzHHfPqlMGalbN3e/k07y/4oaPVp65RVp0qTwxwwgSlBOBAAAhBFJbCAakMQGECZt2lht4/QOH5Zmzw57OIig1FSpY0dp5kzpxhulRx+19bfdJv35p9Sunbtv+sEba9WyMjRNm4YvXgBRhnIiAAAgjOgACkSD1FSbxvFcCUD+8nisDvZ772Uc7PGGG2yQx9q1rWXuiBE8WyvIvvjCnf/tN5u2aGHXh8fD4I0AskFLbAAAEEYksaPIiBEjNGLECB3xHS0JhQMtsQGE2fvvS/37WwtsX8OGufMXXCCddlpYw0KYHD4s/ec/Gdf37WsJbEkqV85dTxIbQAbUxAYAAGFEs88oMmTIEC1btkzTpk2LdCgIN5LYAMLszDOzH8zx66+lVavCEw/C5/hx6cEHrRZ6el27uvP16rnzvoM6AoAkyokAAICwIokNRJpTSkQiiQ0grIoWlUqVynz7q6/610VGbNqzRxo/3pLXf/whNWkivfCCbbvxRv99e/Z053v1kr79VvrpJ+nkk8MVLYCYQTkRAAAQRpQTASLNaYUtkcQGEHbLl0tPPCG9/Xbg7bt3W+mJ+PjwxoXQOH7cBmXcs0f68ENrgb12rQ3BcMcd0rXXSm+8Yfu+9JL/11BcnNSnT0TCBhALnCT2/v0Za1MBDo9HKl480lEAAAoAkthApJHEBhBBtWpZ7evMktiSVKaM9NlnVkMb0W33bqlsWWtl/8030uDBlsCWpAcekNatk6pUsRbZlSpJ27e7761VKxIRA4hZTjmRV1+1FxCIxyM99ZR0332RjgQAEOMoJwJEGklsABF22mnSXXdlvv3Ysay3Izp8+KFUrZrUu7c0Y4Y9dNi82d2+bp1Nr73WEtiSlJjobvedB4Bsde3qJrKBzHi9NsgGAAB5REtsINJIYgOIMI9Hev55K2s6YkTgfYoWlc4/X7ruOhsUEtHj+HHp8celRx+15Z9+ko4csfXnnitVqCCNGuXuf+qp7nyxYlK3btKGDVKnTuGNG0CMO/VU6/5x5EikI0G0mj5dOuccu04AAMgjkthApJHEBhAlevWSRo4MXNp0xQp7ffGFNapC5KxdK/XoYf+fJk+2Bw+vv+6/z4wZ9nDitdekL7/039axo//ylCk2xnBRfhUCyKkSJWiNjczVqGFTktgAgBCgnAgQaSSxAUSJvn2lvXulAQOy3u/jj63ECPJfSorVtR471pb37JGuuEJav17autWS2U4C+8UX/d/bvLnlDypUcNc9/bRUqpT/fnFxJLABAPnA+QIiiQ0ACAGS2ECkpaa683H8kwQQWcWLW9mQrFx6qdVfRv67+mobdHPQIOndd6W6daVZs9zt//xj0wsvlO64w/+9PXrYtHx5d12XLvkbLwAAaZwvoEOHpIMHIxsLACDmkTEDIs1piU0CG0CUOPtsK0eRlVmzpP37wxNPYXD4sPTYY9K0abZ86JB02WXSJ5+4+wwcaC2xa9WSOnf2f/8bb2Q85oMP2jQhwV1Xp04IgwYAICtly7r3OLTGBgDkEVkzINKcJDalRABECY8n+xa706fbveno0eGJqaC7+mpp2DDp8sulXbukDh2kjz7y38frlRITpfnz7UGD45ZbpIoVMx6zcmWbli3rrqtWLeShAwAQWFyc2xqbJDYAII+ogAhEGklsAFFqwQLpiSek8eMzblu+3KbXXWcJWATnyBErD9Ktm9WsPn5cGjfOLc+yebN0xhnS4sWWmB4+3Mq3ON54Q6pa1b/OdfPmGc/jW+O6eXNLkNepQ6cfAECYlS8v7dwp9e7NIKDIXOXK9vS+du1IRwIgipHEBiKNJDaAKHXyyZZgLVcu831SU6V27aS77pIuvjh8scWqK6+UPv1U6tpVmjBBOvNMae5c/30WLrTpZ59ZXWvfJLbTQt63znVSUsbz1K3rzns80iOPhCJ6AABy6KSTpFWrpA0bIh0JotnKldJ330k33BDpSABEMZLYQKSRxAYQxcqWtUTrtGlWpzmQ+fMtSUoSO3OpqdJ771kCW7Ka4/fcYwnsEiWk7t2l77939z/lFFuXXo0aNs0sif3JJ1YL27eWNgAAEfPBB/ak23cwe8DXsGHS5MnWXQ0AskASG4g0ktgAopjHI02c6M5nZv16adQoG4ywZMnwxBbN9u+XXn1V6tfP6lD37i3Nm+duL1HCWrlL0qRJUseOUvHi7vYJE7L+7+31uvO+PW8vusheAABEhfh4+5IDMlO9uk1JYgPIBklsINJIYgOIEQ0aWI/gQA4elK691gYlvOee8MYVjU4/XZozR/rlF6tfPW+eJalbtLBa406r9iZNrLRIepUqZVznW8+6fXsr81K3ruUHAAAAYpLzFJ8kNoBsMLwPEGkksQHEiLlzpZdeynqf6dOlHTv8WwoXJv/+K512miWwJWvF/tFHNj9jhtuq3dGtW8ZjJCQEPrZvCZGyZa28qG/rbgAAgJhDEhtAkEhiA5FGEhtAjKhQQerVK+t9Fi2yAeafey48MUXaCy9I559vgzGuWWMtrSdP9t8nNVVq29ZtPe3rwgszHjMx0X/5ggts+tBD/uvLlpWKFctT+AAAAJHl/JghiQ0gGySxgUgjiQ0ghjRuLP33v9LllwfevnmzTe+7T6pXz6YF1VdfSXffLX3xhQ1s2bmz9PffVqP66af993UGafRNOlerJp16asbj+ra4lqx29i+/SLfeGsroAQAAogAtsQEEiSQ2EGnOSN1x/HMEEP08Hun++6V3381+37VrpWeflVq3lm6/Pd9DC5vUVOnHH6WrrnLXffONtGWLVLSolVS58kr/9/Tvn/E49er5LzdoYNMrrvBfX6qU1KkTXxMAAKAAIokNIEjcDgGRRktsADEoLs4StV26ZL/vokXSK69Il14q3Xuv+7EXK774wgZQHDjQBmQ89VTpjDOs/nV6t9wiJSX5t6Zu21Y65ZSM+6YvGzJ9uvTBBwUr4Q8AAJAlJ4l99Ghk4wAQ9YpGOgCg0COJDSBGOa2xPZ7g9v/4Y5vu2yc1aiRdf721Mo5ma9ZY8nrfPmndOktQT59u284/31pj9+tny1WqWI1sSSpZ0j1GcnLgY6evL169unTZZSEMHgAAINrREhtAkEhiA5FGEhtAjOvaVZoxI/j933zTplu2SB06WKvm0qXzJ7ac2LXLGgFVrSodO2YtsB96yBLYjqeesukbb0g33CAtX+5ua9MmcEI/IcF/eelSacoU6aabQv83AAAAxBSS2ACCRDkRINJIYgOIcRMnSu+/n/P3PfusdN550gMPSMuWWeI4Un7/XapVywZb/PFH6eabpYsvllautHVOPeojRyxRffHFtly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+ "text/plain": [ + "
" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], + "source": [ + "only_trigger_df = df[df['TRIGGER'] == '1']\n", + "rate_index = pd.to_numeric(only_trigger_df['inst_shell/inst_network_top/inst_network_stack/inst_roce_stack/inst_rdma_flow/inst_DCQCN/ecn_rates_index[4:0]']).to_list()\n", + "RC_gap_cycles = pd.to_numeric(only_trigger_df['inst_shell/inst_network_top/inst_network_stack/inst_roce_stack/inst_rdma_flow/inst_DCQCN/Rc[15:0]']).to_list()\n", + "RC_rate_hz = [1/((4*i)/1000000000) for i in RC_gap_cycles]\n", + "\n", + "rate_list = [rates[i] for i in rate_index]\n", + "\n", + "fig, ax1 = plt.subplots(figsize=(16, 7))\n", + "\n", + "x_pre = range(len(RC_gap_cycles))\n", + "x = [(i * (ila_tigger_interval)* 4)/1000000000 for i in x_pre]\n", + "\n", + "ax1.plot(x, RC_rate_hz, color='blue', label='Line 1 (left)')\n", + "ax1.set_ylabel('Sending rate [Hz]', color='blue', fontsize=20)\n", + "ax1.set_yscale('log')\n", + "ax1.tick_params(axis='y', colors='blue', labelsize=20)\n", + "\n", + "# For printing packet gap in cycles instead of sendrate\n", + "\n", + "#ax1.plot(x, RC_gap_cycles, color='blue', label='Line 1 (left)')\n", + "#ax1.set_ylabel('time between outgoing packets [cycles]', color='blue', fontsize=20)\n", + "#ax1.tick_params(axis='y', colors='blue', labelsize=20)\n", + "\n", + "ax2 = ax1.twinx()\n", + "\n", + "ax2.plot(x, rate_list, color='red', label='Line 2 (right)')\n", + "ax2.set_ylabel('ratio of packets ECN marked', color='red', fontsize=20)\n", + "ax2.tick_params(axis='y', colors='red', labelsize=20)\n", + "\n", + "# Labels and title\n", + "ax1.set_xlabel('Time [s]', fontsize=20)\n", + "ax1.tick_params(axis='x', labelsize=20)\n", + "plt.title('Default Parameters, Sending rate', fontsize=22)" + ] + }, + { + "cell_type": "code", + "execution_count": 7, + "id": "e625b037-0c5f-4e47-bd6b-166350989e4d", + "metadata": {}, + "outputs": [], + "source": [ + "fig.savefig(savepath, dpi=400)" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "82e26e2a-0bee-458c-8e86-ab051748ff38", + "metadata": {}, + "outputs": [], + "source": [] + } + ], + "metadata": { + "kernelspec": { + "display_name": "Python 3 (ipykernel)", + "language": "python", + "name": "python3" + }, + "language_info": { + "codemirror_mode": { + "name": "ipython", + "version": 3 + }, + "file_extension": ".py", + "mimetype": "text/x-python", + "name": "python", + "nbconvert_exporter": "python", + "pygments_lexer": "ipython3", + "version": "3.12.3" + } + }, + "nbformat": 4, + "nbformat_minor": 5 +} diff --git a/examples/Congestion_Control_Test/Test_script/Reduction_factor_calc_scrip.ipynb b/examples/Congestion_Control_Test/Test_script/Reduction_factor_calc_scrip.ipynb new file mode 100644 index 000000000..d89f93525 --- /dev/null +++ b/examples/Congestion_Control_Test/Test_script/Reduction_factor_calc_scrip.ipynb @@ -0,0 +1,75 @@ +{ + "cells": [ + { + "cell_type": "code", + "execution_count": 5, + "id": "e1ead512-fdcf-4470-886e-f076ae17f3a2", + "metadata": {}, + "outputs": [], + "source": [ + "#Generator Parameter\n", + "g = 1/16\n", + "#Number of bits for left shift (used to circumvent floating point calculations)\n", + "precision_bits = 7\n", + "#number of steps to print\n", + "reduction_steps = 29" + ] + }, + { + "cell_type": "code", + "execution_count": 7, + "id": "34f5498c-decc-48ff-b3a0-41dbb827c04f", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "[256, 241, 228, 218, 209, 201, 194, 188, 182, 178, 173, 170, 166, 163, 161, 158, 156, 154, 152, 150, 148, 147, 146, 144, 143, 142, 141, 140, 139, ]\n" + ] + } + ], + "source": [ + "a = 1.0\n", + "j = 1\n", + "prec = 2**precision_bits\n", + "str_list = \"\"\n", + "for i in range(0,reduction_steps):\n", + " str_list += str(round(prec *(1/(1-(a/2))))) + \", \"\n", + " a = (1-g)*a\n", + "\n", + "print('[' + str_list + ']')\n", + "#remove the last comma :)" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "e8bc9f64-7430-4096-bd68-41c1fe4f8e82", + "metadata": {}, + "outputs": [], + "source": [] + } + ], + "metadata": { + "kernelspec": { + "display_name": "Python 3 (ipykernel)", + "language": "python", + "name": "python3" + }, + "language_info": { + "codemirror_mode": { + "name": "ipython", + "version": 3 + }, + "file_extension": ".py", + "mimetype": "text/x-python", + "name": "python", + "nbconvert_exporter": "python", + "pygments_lexer": "ipython3", + "version": "3.12.3" + } + }, + "nbformat": 4, + "nbformat_minor": 5 +} diff --git a/examples/Congestion_Control_Test/Test_script/example_graph.png b/examples/Congestion_Control_Test/Test_script/example_graph.png new file mode 100644 index 0000000000000000000000000000000000000000..97f437adee44711c725725426afca3b73e6cbd93 GIT binary patch literal 378223 zcmeFag>c71*B1lt%x9v zNC=34bT@qG@_A;)_x;U#9N!->`#9!N1opn~wXQhhTKD5|R$gkuTDr9q3T4CTQ<91l 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zj*?`9JpBC?@{DbChzx@C<*nsxu+x}-Zr}kq-LIZ}Fv6}dl>%Dq1w?cCarQPuwh7F4 z3iHTH10B$S+0%G+b#bBnUT|1v0(xgb9PT)6>Il4>{0s1&NNYMtq$G zqvQL6=P>X;(z!!CW|80tiVXIrd7L9LbMDLfRZG0^T2zaMijS6tG_kZEKX*d3{JSTqT_0SRAK}~3tnQ6L*Ps5s z7o~i~Oo?X21CjD<_QvO&DLq?_-5PAJ&tV?opRbgglHKJV|NIEwJ@xLs2fO}o@mDp~ z|EE8j|Bvpu>*x6U`+2rsH=Td~2;cl$NZIvnbou^&LIBp~w?v|U|6aG-@%R7y`@Z~r iE4qF2|BL(5&@PG_Jv}CIaBrcSTe47BBW(Up2mdcj^irAt literal 0 HcmV?d00001 From 59db350210f79135fc338f1db354e8dd15402f22 Mon Sep 17 00:00:00 2001 From: pomsi <72771413+pomsi@users.noreply.github.com> Date: Mon, 10 Nov 2025 06:43:44 +0100 Subject: [PATCH 42/52] Update README.md --- examples/Congestion_Control_Test/README.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/examples/Congestion_Control_Test/README.md b/examples/Congestion_Control_Test/README.md index f5387b7fd..a59b5850e 100644 --- a/examples/Congestion_Control_Test/README.md +++ b/examples/Congestion_Control_Test/README.md @@ -1,6 +1,6 @@ -# Coyote Example 8: Using the FPGA as a SmartNIC for Remote Direct Memory Access (RDMA) -Welcome to the eigth Coyote example! If you've made it to this point, you've already learnt all the essential concepts of FPGA-CPU interaction for data movement and control flow. Thus, we're adding a new component by demonstrating how Coyote can be used to turn the FPGA into a SmartNIC for 100G RDMA-over-Converged-Ethernet (RoCE v2), allowing for efficient, high-performance data exchange between remote processing nodes and FPGA-offloaded preprocessing of the data streams. As with all Coyote examples, a brief description of the core Coyote concepts covered in this example is included below. - +# Changed Files +- **(added) hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv:** DCQCN implementation, tunable parameters for algorithm and for the test run described in file. **`define CC_TEST ** controls wether to compile with the test setting or without. +- **(added) hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv:** ##### Table of Contents [RDMA Overview](#rdma-overview) @@ -183,4 +183,4 @@ The following results are expected for reads (left) and writes (right):

-

\ No newline at end of file +

From 07ec4adaca15f85412de531566f035cc2239abf3 Mon Sep 17 00:00:00 2001 From: pomsi <72771413+pomsi@users.noreply.github.com> Date: Mon, 10 Nov 2025 06:45:48 +0100 Subject: [PATCH 43/52] Update MT_pomsarc_CC_QP_unit_DCQCN.sv Made the dcqcn without test the default case --- hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv index 5161bc2f7..6c4090aa4 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv @@ -2,7 +2,7 @@ import lynxTypes::*; // defines wether simulated ECN markings should be generated and also add test readout signals as ILAs -`define CC_TEST +//`define CC_TEST module cc_queue ( @@ -513,4 +513,4 @@ queue_meta #( -endmodule \ No newline at end of file +endmodule From 945166714f2d13d57a4f10ecdbb2134b9c42fdd6 Mon Sep 17 00:00:00 2001 From: pomsi <72771413+pomsi@users.noreply.github.com> Date: Mon, 10 Nov 2025 07:08:30 +0100 Subject: [PATCH 44/52] Update README.md --- examples/Congestion_Control_Test/README.md | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/examples/Congestion_Control_Test/README.md b/examples/Congestion_Control_Test/README.md index a59b5850e..168eae553 100644 --- a/examples/Congestion_Control_Test/README.md +++ b/examples/Congestion_Control_Test/README.md @@ -1,6 +1,11 @@ # Changed Files - **(added) hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv:** DCQCN implementation, tunable parameters for algorithm and for the test run described in file. **`define CC_TEST ** controls wether to compile with the test setting or without. -- **(added) hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv:** +- **(added) hw/hdl/network/rdma/MT_pomsarc_new _flow.sv:** replaces the old flow control by replacing the request queue with the dcqcn module. This flow control is the "default case" (changes starting Line 160) +- **(added) hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv:** the multiqueue version of the flow control commented out. to use thus version comment aut the whole previous file (MT_pomsarc_new _flow.sv) **!!SEE [1] BELOW FOR NOTES** +- **hw/hdl/network/rdma/roce_stack.sv:** added the ecn forward (Line 126, 228 (ila) ) + +- **scripts/wr_hdl/template_gen/lynx_pkg_tmplt.txt:** adjusted the ack interface (Line 197, 432) +- **scripts/ip_inst/network_infrastructure.tcl:** added more ILAs at the bottom ##### Table of Contents [RDMA Overview](#rdma-overview) From 3561c425fa26cb9f3c77bcdc9993d08607d72213 Mon Sep 17 00:00:00 2001 From: pomsi <72771413+pomsi@users.noreply.github.com> Date: Mon, 10 Nov 2025 07:16:36 +0100 Subject: [PATCH 45/52] Update README.md --- examples/Congestion_Control_Test/README.md | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/examples/Congestion_Control_Test/README.md b/examples/Congestion_Control_Test/README.md index 168eae553..efce905d9 100644 --- a/examples/Congestion_Control_Test/README.md +++ b/examples/Congestion_Control_Test/README.md @@ -1,4 +1,4 @@ -# Changed Files +# Changed Files (Coyote) - **(added) hw/hdl/network/rdma/MT_pomsarc_CC_QP_unit_DCQCN.sv:** DCQCN implementation, tunable parameters for algorithm and for the test run described in file. **`define CC_TEST ** controls wether to compile with the test setting or without. - **(added) hw/hdl/network/rdma/MT_pomsarc_new _flow.sv:** replaces the old flow control by replacing the request queue with the dcqcn module. This flow control is the "default case" (changes starting Line 160) - **(added) hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv:** the multiqueue version of the flow control commented out. to use thus version comment aut the whole previous file (MT_pomsarc_new _flow.sv) **!!SEE [1] BELOW FOR NOTES** @@ -6,6 +6,16 @@ - **scripts/wr_hdl/template_gen/lynx_pkg_tmplt.txt:** adjusted the ack interface (Line 197, 432) - **scripts/ip_inst/network_infrastructure.tcl:** added more ILAs at the bottom + +# Changed Files (HLS stack) +- **hls/ipv4/ipv4.cpp:** +- **hls/ipv4/ipv4.hpp:** +- **hls/udp/udp.cpp:** +- **hls/udp/udp.hpp:** +- **hls/ib_transport_protocol/ib_transport_protocol.cpp:** +- **hls/ib_transport_protocol/ib_transport_protocol.hpp:** + + ##### Table of Contents [RDMA Overview](#rdma-overview) From 5ba8117613512ef256bb74d030301ab4fdc487a5 Mon Sep 17 00:00:00 2001 From: pomsi <72771413+pomsi@users.noreply.github.com> Date: Mon, 10 Nov 2025 07:23:22 +0100 Subject: [PATCH 46/52] Update README.md --- examples/Congestion_Control_Test/README.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/examples/Congestion_Control_Test/README.md b/examples/Congestion_Control_Test/README.md index efce905d9..83bf47381 100644 --- a/examples/Congestion_Control_Test/README.md +++ b/examples/Congestion_Control_Test/README.md @@ -15,6 +15,9 @@ - **hls/ib_transport_protocol/ib_transport_protocol.cpp:** - **hls/ib_transport_protocol/ib_transport_protocol.hpp:** +# Running a Test +To run a test make sure the CC_TEST variable is set in the MT_pomsarc_CC_QP_unit_DCQCN.sv file. compile sw of the Congestion_Control_Test example, exactly the same as example 08. when running set the -o flag to 1 (write) and the -i flag (didnt make sure wether the other flags behave). + ##### Table of Contents [RDMA Overview](#rdma-overview) From b6ab326520e96bf2bbfe54149d71bf688be7ba8b Mon Sep 17 00:00:00 2001 From: pomsi <72771413+pomsi@users.noreply.github.com> Date: Mon, 10 Nov 2025 07:41:37 +0100 Subject: [PATCH 47/52] Update README.md --- examples/Congestion_Control_Test/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/Congestion_Control_Test/README.md b/examples/Congestion_Control_Test/README.md index 83bf47381..6932d07e0 100644 --- a/examples/Congestion_Control_Test/README.md +++ b/examples/Congestion_Control_Test/README.md @@ -16,7 +16,7 @@ - **hls/ib_transport_protocol/ib_transport_protocol.hpp:** # Running a Test -To run a test make sure the CC_TEST variable is set in the MT_pomsarc_CC_QP_unit_DCQCN.sv file. compile sw of the Congestion_Control_Test example, exactly the same as example 08. when running set the -o flag to 1 (write) and the -i flag (didnt make sure wether the other flags behave). +To run a test make sure the CC_TEST variable is set in the MT_pomsarc_CC_QP_unit_DCQCN.sv file. compile sw of the Congestion_Control_Test example, exactly the same as example 08. when running set the -o flag to 1 (write) and the -i flag (didnt make sure wether the other flags behave). Run Vivado from the client side. switch to ila 3 (i think, the one with Rc and Rt). select a good amount of trigger windows (i usualy take 2048) and trigger on the 'ila_trigger' AND 'ecn_tedt_starter' signals equal to 1. run the test and export as CSV. CSV file can be input directly to the python script for plotting. ##### Table of Contents From edfcd4dac0d3f296cb691556e1b9a4a454316cfe Mon Sep 17 00:00:00 2001 From: Cyril Pomsar Date: Sun, 16 Nov 2025 18:49:20 +0100 Subject: [PATCH 48/52] replaced program hacc ocal with new version --- util/program_hacc_local.sh | 126 ++++++++++++++++++++----------------- 1 file changed, 67 insertions(+), 59 deletions(-) diff --git a/util/program_hacc_local.sh b/util/program_hacc_local.sh index 3bd1b6ce0..b7b30045f 100644 --- a/util/program_hacc_local.sh +++ b/util/program_hacc_local.sh @@ -1,75 +1,83 @@ -## -## Read in the arguments for programming the FPGA -## +#!/bin/bash -# Required arguments: Bitstream-path, driver-path and qsfp-port (assigned automatically if not provided) +###################################################################################### +# This file is part of the Coyote +# +# MIT Licence +# Copyright (c) 2025, Systems Group, ETH Zurich +# All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +###################################################################################### + +### A utility script to program a local FPGA with a Coyote bitstream and insert the driver on the ETHZ HACC cluster +### This script should be executed from the node where the FPGA is (e.g., alveo-u55c-05, alveo-box-01, etc.) and from the Coyote/util directory + +# Check Vivado is available + if ! [ -x "$(command -v vivado)" ]; then + echo "Vivado not found. Please make sure Vivado is installed." + exit 1 +fi + +# Arguments: bistream path, driver path and device ID (optional) if [ "$1" == "-h" ]; then echo "Usage: $0 " >&2 exit 0 fi -if ! [ -x "$(command -v vivado)" ]; then - echo "Vivado does NOT exist in the system." - exit 1 -fi - -# Get the current basepath of the script -BASE_PATH=$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd ) - -# Set relevant parameters for FPGA-programming -PROGRAM_FPGA=1 -DRV_INSERT=1 - -BIT_PATH=$1 -DRV_PATH=$2 - +BITSTREAM_PATH=$1 +DRIVER_PATH=$2 if [ -z "$3" ]; then - DEVICE=1 + DEVICE=1 else - DEVICE=$3 + DEVICE=$3 fi -## -## Program the FPGA via the hdev call - only work locally for the server that you are currently logged in to -## - -if [ $PROGRAM_FPGA -eq 1 ]; then - echo "***" - echo "** Programming the FPGA with $BIT_PATH" - echo "***" - hdev program vivado -b $BIT_PATH -d $DEVICE - echo "***" - echo "** FPGA programmed" - echo "***" -fi -echo " " -echo " " +# Environment set-up --- get IP and MAC address of the FPGA; convert to hex +CLI_PATH=/opt/hdev/cli +IP_ADDRESS=$($CLI_PATH/hdev get network -d 1 | awk '$1 == "1:" {print $2}') +MAC_ADDRESS=$($CLI_PATH/hdev get network -d 1 | awk '$1 == "1:" {print $3}' | tr -d '()') +IP_HEX=$($CLI_PATH/common/address_to_hex IP $IP_ADDRESS) +MAC_HEX=$($CLI_PATH/common/address_to_hex MAC $MAC_ADDRESS) -## -## Insert the driver for the FPGA with the required IP- and MAC-Address -## +# First, remove any drivers from before +# This causes the DMA core to shut down gracefully, leading to less problems with PCIe hotplug. +hdev program driver --remove coyote_driver -if [ $DRV_INSERT -eq 1 ]; then - echo "***" - echo "** Inserting the driver from $DRV_PATH" - echo "***" - echo "** IP_ADDRESS: $DEVICE_1_IP_ADDRESS_HEX_0" - echo "** MAC_ADDRESS: $DEVICE_1_MAC_ADDRESS_0" - hdev program driver -i $DRV_PATH -p ip_addr=$DEVICE_1_IP_ADDRESS_HEX_0,mac_addr=$DEVICE_1_MAC_ADDRESS_0 - # hdev program driver -m $DRV_PATH - echo "***" - echo "** Driver loaded " - echo "***" -fi -echo " " -echo " " +# Bitstream loading +echo "** Programming the FPGA with $BITSTREAM_PATH" +$CLI_PATH/hdev program vivado -b $BITSTREAM_PATH -d $DEVICE +if [ $? -ne 0 ]; then + echo "Error: Failed to program the FPGA with the bitstream." + exit 1 +fi -## -## Final greetings -## +# Driver insertion +echo "** Inserting the driver from $DRIVER_PATH" +echo "** FPGA IP_ADDRESS: $IP_HEX" +echo "** FPGA MAC_ADDRESS: $MAC_HEX" +echo "y" | $CLI_PATH/hdev program driver -i $DRIVER_PATH -p ip_addr=$IP_HEX,mac_addr=$MAC_HEX +if [ $? -ne 0 ]; then + echo "Error: Failed to insert Coyote driver." + exit 1 +fi -echo "***" +# Final greetings echo "** It's Coyote after all, so thoughts & prayers!" echo "** Lasciate ogni speranza, voi ch'entrate - Ihr, die ihr hier eintretet, lasst alle Hoffnung fahren" -echo "***" - From 3ec58f96baccfc0ab45f7ea4acc0629b881f1178 Mon Sep 17 00:00:00 2001 From: pomsi <72771413+pomsi@users.noreply.github.com> Date: Mon, 17 Nov 2025 19:20:58 +0100 Subject: [PATCH 49/52] Update MT_pomsarc_new_flow_multiqueue.sv --- hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv b/hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv index 78cfd82c3..4e7135c5d 100644 --- a/hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv +++ b/hw/hdl/network/rdma/MT_pomsarc_new_flow_multiqueue.sv @@ -307,12 +307,8 @@ end genvar i_gen_out; generate for (i_gen_out = 0; i_gen_out < N_QUEUES; i_gen_out++) begin: gen_out - always_comb begin - ccq_m_req[i_gen_out].ready = 0; - - if(readout_conter == i_gen_out) begin - ccq_s_req[i_gen_in].ready = m_req.ready; - end + always_comb + ccq_m_req[i_gen_out].ready = (readout_counter == i_gen_out) ? m_req.ready : 1'b0; end end endgenerate @@ -339,4 +335,4 @@ endgenerate endmodule -*/ \ No newline at end of file +*/ From 04d5d56209cbcf828aae9a883e170953bbfd7219 Mon Sep 17 00:00:00 2001 From: pomsi <72771413+pomsi@users.noreply.github.com> Date: Mon, 17 Nov 2025 19:48:05 +0100 Subject: [PATCH 50/52] Update README.md --- examples/Congestion_Control_Test/README.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/examples/Congestion_Control_Test/README.md b/examples/Congestion_Control_Test/README.md index 6932d07e0..090b02084 100644 --- a/examples/Congestion_Control_Test/README.md +++ b/examples/Congestion_Control_Test/README.md @@ -18,6 +18,10 @@ # Running a Test To run a test make sure the CC_TEST variable is set in the MT_pomsarc_CC_QP_unit_DCQCN.sv file. compile sw of the Congestion_Control_Test example, exactly the same as example 08. when running set the -o flag to 1 (write) and the -i flag (didnt make sure wether the other flags behave). Run Vivado from the client side. switch to ila 3 (i think, the one with Rc and Rt). select a good amount of trigger windows (i usualy take 2048) and trigger on the 'ila_trigger' AND 'ecn_tedt_starter' signals equal to 1. run the test and export as CSV. CSV file can be input directly to the python script for plotting. +# Notes + +- [1] To compile with multiqueue the dreq_t interface a(Lines 281, 316/317) + ##### Table of Contents [RDMA Overview](#rdma-overview) From c23493ca6187a2d9aa627817fe3db1d617c8ecd4 Mon Sep 17 00:00:00 2001 From: pomsi <72771413+pomsi@users.noreply.github.com> Date: Mon, 17 Nov 2025 20:24:21 +0100 Subject: [PATCH 51/52] Update README.md --- examples/Congestion_Control_Test/README.md | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/examples/Congestion_Control_Test/README.md b/examples/Congestion_Control_Test/README.md index 090b02084..5beb6cfd7 100644 --- a/examples/Congestion_Control_Test/README.md +++ b/examples/Congestion_Control_Test/README.md @@ -7,20 +7,20 @@ - **scripts/wr_hdl/template_gen/lynx_pkg_tmplt.txt:** adjusted the ack interface (Line 197, 432) - **scripts/ip_inst/network_infrastructure.tcl:** added more ILAs at the bottom +- **hls/ipv4/ipv4.cpp:** added ecn marks to outgoing ecn packets and forward ecn from incoming packets. (Lines: 59, 111, 212) # Changed Files (HLS stack) -- **hls/ipv4/ipv4.cpp:** -- **hls/ipv4/ipv4.hpp:** -- **hls/udp/udp.cpp:** -- **hls/udp/udp.hpp:** -- **hls/ib_transport_protocol/ib_transport_protocol.cpp:** -- **hls/ib_transport_protocol/ib_transport_protocol.hpp:** +- **hls/ipv4/ipv4.hpp:** adjusted interface and set/get ecn function (Lines 36, 657) +- **hls/udp/udp.cpp:** same as ipv4 (Lines 173, 195) +- **hls/udp/udp.hpp:** same as ipv4 (Lines 47) +- **hls/ib_transport_protocol/ib_transport_protocol.cpp:** Added the incoming ecn -> outgoing marked ack path and the ecn forwarding to the flow control (Lines: 78, 592, 615, 656, 689, 1533, 1636, 1657, 1687, 1728, 1742, 1779, 2115, 2125, 2365, 2741, 2770) +- **hls/ib_transport_protocol/ib_transport_protocol.hpp:** same as ipv4 (Lines 240, 259, 281) # Running a Test -To run a test make sure the CC_TEST variable is set in the MT_pomsarc_CC_QP_unit_DCQCN.sv file. compile sw of the Congestion_Control_Test example, exactly the same as example 08. when running set the -o flag to 1 (write) and the -i flag (didnt make sure wether the other flags behave). Run Vivado from the client side. switch to ila 3 (i think, the one with Rc and Rt). select a good amount of trigger windows (i usualy take 2048) and trigger on the 'ila_trigger' AND 'ecn_tedt_starter' signals equal to 1. run the test and export as CSV. CSV file can be input directly to the python script for plotting. +To run a test make sure the CC_TEST variable is set in the MT_pomsarc_CC_QP_unit_DCQCN.sv file (not by default). set the Ecn_rates to the different phases, an entry in that array corresponds to the amount of acks not marked between the marked ones. To simulate no marked packets just use a high value (eg. 9999). also adjust the Ecn_rates_max_index variable. compile sw of the Congestion_Control_Test example, exactly the same as example 08. when running set the -o flag to 1 (write) and the -i flag (didnt make sure wether the other flags behave). Run Vivado from the client side. switch to ila 3 (i think, the one with Rc and Rt). select a good amount of trigger windows (i usualy take 2048) and trigger on the 'ila_trigger' AND 'ecn_test_starter' signals equal to 1. ila_trigger goes to 1 in a defined cycle interval and ecn_test_started goes and stays at 1 as soon as the first ack arives. Run the test and export as CSV. CSV file can be input directly to the python script for plotting. # Notes -- [1] To compile with multiqueue the dreq_t interface a(Lines 281, 316/317) +- [1] To compile with multiqueue the dreq_t interface array needs to be changed because of non constant indexing (Lines 281, 316/317) im not 100% sure how to fix this (and also cant test it anymore :( ) ##### Table of Contents From 417f4e512cdb80566e6bc584addc6f8485a7241e Mon Sep 17 00:00:00 2001 From: pomsi <72771413+pomsi@users.noreply.github.com> Date: Mon, 17 Nov 2025 20:28:36 +0100 Subject: [PATCH 52/52] Update README.md --- examples/Congestion_Control_Test/README.md | 185 --------------------- 1 file changed, 185 deletions(-) diff --git a/examples/Congestion_Control_Test/README.md b/examples/Congestion_Control_Test/README.md index 5beb6cfd7..c98ca4388 100644 --- a/examples/Congestion_Control_Test/README.md +++ b/examples/Congestion_Control_Test/README.md @@ -21,188 +21,3 @@ To run a test make sure the CC_TEST variable is set in the MT_pomsarc_CC_QP_unit # Notes - [1] To compile with multiqueue the dreq_t interface array needs to be changed because of non constant indexing (Lines 281, 316/317) im not 100% sure how to fix this (and also cant test it anymore :( ) - - -##### Table of Contents -[RDMA Overview](#rdma-overview) - -[Example Overview](#example-overview) - -[Hardware Concepts](#hardware-concepts) - -[Software Concepts](#software-concepts) - -[Additional Information](#additional-information) - -## RDMA Overview -Remote Direct Memory Access over Converged Ethernet (RoCE v2) is a high-performance networking protocol originally developed for High-Performance Computing. It aims to combine high throughput, low latency and low CPU-utilization by offloading the network stack and direct memory access to the Network Interface Card (NIC), thus grounding its performance claims on host-bypassing and zero-copy: applications running on the host CPUs directly expose memory buffers for DMA to the NIC, so that data can be exchanged without including the host CPU or the OS running on it. In this example, we demonstrate how Coyote can be configured to use the FPGA in the role of such a NIC, allowing for fully protocol-compliant RoCE v2-traffic at 100 Gbps. -For further understanding of the RDMA example, we need to shed some light on the intrinsics of this network standard. -For RDMA communication, two nodes are connected via a so-called Queue Pair (QP), based on previously exchanged information such as respective IP-addresses, location and size of the allocated memory buffers and access keys, and comprising of the idea of queues for work commands and data. The initial exchange of RDMA operations are managed through so-called InfiniBand-verbs, which describe the form of memory transaction between the remote nodes. We have to separate between *one-sided operations* that initiate data transfers over the network without a previous request for consent, and *two-sided operations* where every data transaction is preceeded by an additional exchange between the communicating nodes. Coyote implements the two one-sided RDMA operations: -- ```RDMA WRITE```: One node writes data of certain length to a remote buffer in the other node. Every sent WRITE packet has to be explicitly acked by the receiving node. -- ```RDMA READ```: One node requests to read data of certain length from a remote buffer in the other node. The READ REQUEST packet is implicitly ACK'ed when the remote node sends back RDMA RESPONSE packets with the requested data. - -**IMPORTANT TERMINOLOGY:** -To have a better understanding of this example and the following descriptions, a short overview of the RDMA-specific terminology is very helpful: -- *QPN*: Queue Pair Number. Identifies a RDMA connection between two remote nodes. -- *vaddr*: Virtual address of the remote exposed buffer. For setting up a Queue Pair, a node has to share the virtual address of its exposed buffer with the remote node. -- *rkey*: Remote key for accessing the exposed buffer of the remote node. The remote key is communicated alongside the virtual address as a form of access control. -- *PSN*: Packet Sequence Number used to organize and structure a communication flow between remote RDMA-nodes. Normally, PSN-sequencing is handled by the FPGA-offloaded network stack and thus is not visible to the user. However, following the PSN order is very helpful for debugging RDMA networks. The initial PSN is agreed upon between the remote nodes as part of the initialization of the QP. -- *MTU*: Maximum Transmission Unit, defines the maximum size of a packet. Since RDMA operates on the notion of buffer transmission, the length of the data to be transmitted determines the number of MTU-sized packets that are required for the operation. While the MTU is a compile-time parameter in Coyote, the default size is 4 KB. This means that a ```RDMA WRITE``` of a buffer of up to 4 KB size results in a single packet with ```RDMA WRITE ONLY``` opcode, while a buffer of 8 KB size would be transmitted in two packets, one carrying ```RDMA WRITE FIRST```, the other with ```RDMA WRITE LAST```. For even longer buffers, an arbitrary number of ```RDMA WRITE MIDDLE``` packets is inserted in the exchange. - -## Example Overview -This example measures throughput and latency of RDMA data exchange between two remode nodes via a 100G switched network with both ```RDMA WRITE``` and ```RDMA READ``` operations. Assuming the simpler write functionality, we can very generally think about the process as moving of a data buffer from the host CPU to the local FPGA, where it is streamed to the FPGA-offloaded RDMA stack and then sent via the network to the remote FPGA. There, data is received and then written to the previously specified address of the remote buffer of this remote host CPU. Different to all previous examples, this requires two servers with FPGAs, which also run different software application. The active node, which initiates communication exchange, is referred to as the "client", while the remote node is used as "server". An example of the dataflow is given in the figure below; and as shown in the figure, the steps are the following: -1) *QP Exchange*: As explained above, the RDMA connection in form of a Queue Pair needs to be set up between the remote nodes before the actual benchmarking test can begin. Since RDMA cannot be bootstrapped, this requires out-of-band communication between the two remote CPUs via classic TCP sockets. In the context of the HACC, we are using the 10G management network for this purpose. Using ```ifconfig```, the IP address of the CPU determined to be the server can be evaluated and then given to the experiment code as a parameter. The two nodes follow a standardized protocol to exchange relevant start-up information, such as the IP- addresses of the FPGAs in the 100G data network, the initial PSN and the address and access key of the network exposed data buffers. -2) *QP Setup*: After having exchanged these essential pieces of information, both CPUs forward the aggregated QP data to the FPGAs to create the endpoints of the RDMA flow in the hardware-offloaded network stack. This means making information such as the target IP address or buffer virtual address retrievable by the QPN as essential key. -3) *REMOTE WRITE*: In case of a WRITE-based benchmark, the client now begins with a ```REMOTE WRITE``` Coyote operation to transmit a local buffer via the network to the remote node. For this, both data and commands traverse the RDMA-allocated vFGPA and reach the RDMA stack on the FPGA, where RoCE v2 packets are created and then sent out via the network. -4) *Receiving data*: In the above example, the server FPGA receives the incoming RDMA packets and automatically checks for correctness of the PSN-sequence and QP-specific information. If the received packet fits into the expected communication flow, it gets ACK'ed: an ```RDMA ACK``` is sent back to the client as a reply. At the same time, the server FPGA sends the received data as a ```LOCAL WRITE``` (see Example 1) to the local buffer on the CPU. -5) *Processing ACKs & creating completions*: The client FPGA is constantly listening to the network for ACKs for its outstanding packets. If an ACK is received, the original work command for this transaction is marked as completed, which is also communicated to the local client CPU. If no ACK is received within a certain time interval after sending out a packet, a retransmission is issued. In this case, the same packet is sent again, assuming that it was originally lost in the network or not properly received by the server. - -
- -
- -Generally speaking, throughput and latency tests behave vastly different, also depending on the chosen mode of operation (WRITE vs. READ). The different cases are depicted in the figure below and can be understood as following: -- *Latency* for ```RDMA WRITE```: The client issues a single WRITE of a buffer of specified length to the remote server. Upon reception, the server ACKs and then writes back this very buffer to the client, thus creating a typical "ping-pong pattern" of communication, for which the two-way latency can be measured from sending out a buffer to receiving it back. Depending on the specified experimental arguments, this exchange is repeated for a certain number of times before the average latency of all transmissions is reported. -- *Throughput* for ```RDMA WRITE```: The client issues *n* WRITEs (depending on specification of the argument in experiment execution) of a buffer of specified length to the remote server and waits for all required ACKs. Upon reception, the server writes back the same buffer *n* times again. -- *Latency* for ```RDMA READ```: The client issues a single READ of a buffer of specified length from the remote server. Instead of ACK'ing the server sends the requested data via ```RDMA READ RESPONSEs```. -- *Throughput* for ```RDMA READ``` In this case, the client issues *n* READs (depending on specification of the argument in experiment execution) of a buffer of specified length from the remote server and waits for data delivery via ```RDMA READ RESPONSEs``` from there. The server in this case does not issue reflective READs to the client. - -
- -
- -**IMPORTANT:** When executing RDMA benchmarks, it's important to always start the server's software first before doing the same on the client. The reason for this lies in the intrinsics of the QP exchange: The server software is constructed to listening for incoming TCP connections from the client to then take the passive role in the off-channel exchange of information. - - -## Hardware Concepts -The core complexity for RDMA in Coyote is hidden from the user within the network stack. The RDMA-dedicated vFPGA is mainly used for connecting interfaces without any additional user logic required. -The previously introduced send- and receive-queues are connected as following in the vFPGA: -```Verilog -always_comb begin - /* - * CONTROL SIGNALS - * - * rq_(wr|rd) are two more Coyote interfaces, which act as inputs to the user application - * They corresponds to network write/read requests, set from the host software and driver - * Here, they are used to set Coyote's generic send queues, previously discussed in Example 7. - */ - // Write - sq_wr.valid = rq_wr.valid; - rq_wr.ready = sq_wr.ready; - sq_wr.data = rq_wr.data; // Data field holds information such as remote, virtual address, buffer length etc. - sq_wr.data.strm = STRM_HOST; // For RDMA, by definition data is always on the host - sq_wr.data.dest = is_opcode_rd_resp(rq_wr.data.opcode) ? 0 : 1; - - // Reads - sq_rd.valid = rq_rd.valid; - rq_rd.ready = sq_rd.ready; - sq_rd.data = rq_rd.data; // Data field holds information such as remote, virtual address, buffer length etc. - sq_rd.data.strm = STRM_HOST; // For RDMA, by definition data is always on the host - sq_rd.data.dest = 1; -end -``` - -On the other hand, the data interfaces are connected as following in the module: - -```Verilog -/* - * DATA SIGNALS - * - */ -// Data streams for outgoing RDMA WRITEs (from local host to network stack to remote node) -`AXISR_ASSIGN(axis_host_recv[0], axis_rreq_send[0]) - -// Data streams for incoming RDMA READ RESPONSEs (from remote node to network stack to local host) -`AXISR_ASSIGN(axis_rreq_recv[0], axis_host_send[0]) - -// Data streams for outgoing RDMA READ RESPONSEs (from local host to network stack to remote node) -`AXISR_ASSIGN(axis_host_recv[1], axis_rrsp_send[0]) - -// Data streams for incoming RDMA WRITEs (from remote node to network stack to local host) -`AXISR_ASSIGN(axis_rrsp_recv[0], axis_host_send[1]) -``` - -Thinking one step further, beyond the scope of this performance benchmark, it becomes obvious how any pipelined user logic can be placed on these interfaces to process incoming or outgoing RDMA traffic. Placing customized user logic directly on these datapaths is one of the key benefits of a FPGA-based SmartNIC such as Coyote with the network configuration. - - -## Software Concepts -As described above, the main notion of logic abstraction in RDMA is the Queue-Pair (QP), which connects two remote nodes. Both nodes first form their own local Queue, which again is directly linked to the memory buffer that is exposed via the network. Afterwards, an off-channel exchange via TCP/IP is started to exchange the local queues and then form a QP. - -In Coyote, the notion of a QP is directly linked to a ``coyoteThread``. Thus, the first step of setting up RDMA in Coyote is creating such a thread: -```C++ -coyote::cThread coyote_thread(DEFAULT_VFPGA_ID, getpid(), 0); -```` - -Following the creation of the thread, it's necessary to call the function ```initRDMA()```, which allocates an RDMA buffer of the requested size and performs the QP exchange between the client and server. Importantly, the client needs to pass the server's IP address, while the server code leaves this field blank (nullptr, indicating that it's the server). The function return a pointer to the memory buffer to be used for RDMA communication. -```C++ -int *mem = (int *) coyote_thread.initRDMA(max_size, coyote::defPort, server_ip.c_str()); -``` - -After the setup is completed, we follow the standard approach in Coyote: creating a scatter-gather entry and issuing an ``ìnvoke(...)``` call, but this time indicating a remote operation: -```C++ -coyote::sgEntry sg; -sg.rdma = { .len = curr_size }; -coyote_thread.invoke(coyote::CoyoteOper::REMOTE_RDMA_WRITE, &sg); -``` - - -## Additional Information - -### Special remarks on building Coyote for RDMA experiments -Since different software versions are required for server and client to run a benchmark, two cmake builds have to be triggered to obtain the correct executables. In order to build the server code, one needs to specify `-DINSTANCE=server`, while a build of the client software is specified with `-DINSTANCE=client`: -```bash -cd sw/ - -mkdir build_server && cd build_server -cmake ../../ -DINSTANCE=server && make - -cd ../ -mkdir build_client && cd build_client -cmake ../../ -DINSTANCE=client && make -``` - -### Command line parameters and hints on running the experiment -As said above, it's crucial to start the software for experiments first on the node that we want to use as server, before doing the same for the client. Furthermore, it's important that the IP address specified as argument on the client machine **belongs to the server-CPU (not the client CPU, not the server FPGA)**. The different available network interfaces can be explored with ```ifconfig```. -The following description helps to match the relevant command line parameters to details of the experiment execution described before: - -- `[--ip_address | -i] ` IP address of the server CPU for out-of-band QP-exchange via TCP-sockets before the actual RDMA experiment can begin. -- `[--operation | -o] ` Decides whether the benchmark is performed for WRITE (1) or READ (0) operations. Default: 0 -- `[--min_size | -x] ` Minimum size of transferred buffer in the experiment. Default: 64 [B] -- `[--max_size | -X] ` Maximum size of transferred buffer in the experiment. Default: 1048576 [B] ~ 1 [MB] -- `[--runs | -r] ` Number of test runs, to obtain statistically significant results For latency-tests, `r` ping-pong exchanges will be executed. For throughput tests, `r` independent exchanges of 64 messages are executed. - -### Network debugging -Coyote provides tooling to check the status of network transmissions and identify potential problems, most notable packet losses and retransmissions. These statistics can be queried via -`cat /sys/kernel/coyote_sysfs_0/cyt_attr_nstats`. - -A typical output for this could look like this: -``` - -- NET STATS QSFP0 - -RX pkgs: 316 -TX pkgs: 242 -ARP RX pkgs: 4 -ARP TX pkgs: 2 -ICMP RX pkgs: 0 -ICMP TX pkgs: 0 -TCP RX pkgs: 0 -TCP TX pkgs: 0 -ROCE RX pkgs: 245 -ROCE TX pkgs: 240 -IBV RX pkgs: 240 -IBV TX pkgs: 240 -PSN drop cnt: 0 -Retrans cnt: 0 -TCP session cnt: 0 -STRM down: 0 -``` -In this case, 240 RDMA packets have been received and sent (``IBV RX/TX``), no packet has been lost or retransmitted. A major problem would be indicated by ``STRM down: 1``, as this would signal a complete shutdown of the networking stack. In such a case, only a hard reset including reprogramming the FPGA can save the user. -Apart from these Coyote-provided utilities, standard network debugging tools such as switch- or external NIC-based traffic capturing can be used to understand traffic issues and patterns. As described in the next example, we also offer a 100G-capable traffic sniffer for Coyote that directly produces pcap-files compatible to any standard network analysis tool such as wireshark. If even this low-level debugging capabilities are not deemed satisfactory, also classic ILA-based probing directly on data- and controlpaths of the FPGA-design is possible. - -### Expeted results -The following results are expected for reads (left) and writes (right): - -

- - -