Bug + fix: ap_ctrl_none + io_parallel causes permanent TREADY=0 deadlock in Vitis HLS 2022.2

[saiprashanth802]

Summary
When using hls4ml with VivadoAccelerator backend, io_parallel, and ap_ctrl_none on the
return port in Vitis HLS 2022.2, the generated IP permanently asserts TREADY=0 on the
input AXI stream. The AXI DMA MM2S channel hangs indefinitely with no error flags.

Symptom
DMA status registers at offset 0x04 and 0x34 both read 0x00000000 after transfer
initiation — no error flags, halted bit clear — but the transfer never completes even
for a 1-word send.

Root cause
ap_ctrl_none removes the ap_start port. Without ap_start, the IP never enters a
data-accepting state, permanently holding TREADY=0.

Diagnosis steps

1. Read DMA status after hang → 0x00000000 (DMA healthy — not the problem)
2. Try 1-word send with no recv armed → still hangs (rules out recv-side issue)
3. Read ap_ctrl register at offset 0x00 after 5s timeout → ap_done=1 (IP ran,
   DMA never saw it)
4. Conclusion: IP asserts TREADY=0 from start — DMA cannot push data

Fix
Replace ap_ctrl_none with s_axilite on the return port in myproject_axi.cpp:

#pragma HLS INTERFACE axis      port=in
#pragma HLS INTERFACE axis      port=out
#pragma HLS INTERFACE s_axilite port=return bundle=control

Then add an AXI Interconnect in Vivado connecting PS M_AXI_HPM0_LPD →
myproject_axi_0/s_axi_control, and pulse ap_start from the PS before each inference.

Environment

• hls4ml 1.3.0
• Vitis HLS 2022.2 + Vivado 2022.2
• Board: RFSoC 4x2 (xczu48dr-ffvg1517-2-e)
• Backend: VivadoAccelerator, io_parallel, io_stream incompatible with Direct Register DMA

Full reproduction guide + context
https://github.com/saiprashanth802/hls4ml-rfsoc4x2

Not documented anywhere in hls4ml literature or Xilinx forums as of May 2026.