MultiClockSpec chiselTest fails with recent Verilator version

[maartenboersma]

Type of issue: Bug Report

Please provide the steps to reproduce the problem:

Install Verilator >= v5.046, then run ./mill chisel[].test.testOnly chiselTests.MultiClockSpec

[40] %Error: ClockDividerTest_Verification_Assert.sv:72: Assertion failed in TOP.svsimTestbench.dut.verification_assert: Assertion failed at MultiClockSpec.scala:26

Problem not flagged by CI, because the Chisel CI pipeline uses a nightly build from verilator, provided by oss-cad-suite on 2023-06-21.

./verilator --version
Verilator 5.013 devel rev v5.012-12-g9ee5fd058

I confirmed that the testcase passes if using Verilator <= v5.044.

What is the expected behavior?
The ClockDividerTest should pass, independent of simulator version.

Please tell us about your environment:
Verilator v5.046 on linux-x64.

[maartenboersma]

Recreated in CI on PR #5419, which bumps Verilator.
https://github.com/chipsalliance/chisel/actions/runs/27614823121/job/81647975884?pr=5419#step:11:2922

[seldridge]

Thanks for opening this bug report.

Very weirdly, it doesn't trigger on macOS with Verilator 5.048 (unless I made some mistake in the environment setup).