Bump to 9c2190eb5dacfb7991f616c83a9e87740c1c6d49 [Apr 25] - #1199
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Bump to 9c2190eb5dacfb7991f616c83a9e87740c1c6d49 [Apr 25]#1199jorickert wants to merge 1789 commits into
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Reverts llvm/llvm-project#130013 due to failures with expensive checks on.
Updates a test that I forgot to update in #136699. Failing bot: * https://lab.llvm.org/buildbot/#/builders/143/builds/7166
This PR is modified cherry-pick of intel/llvm@cba338e5fb1c This PR sets OpenCL language version to be the same, which is 3.0, for every target and device, in order to unify the build process. Target should define supported extensions and features via setSupportedOpenCLOpts API. llvm-diff shows one change to amdgcn--amdhsa.bc: * ctz symbols are added since they are now enabled for amdgcn.
…'t known scale factors (#136680)
…#130933) Add lowering in tablegen for PARTIAL_REDUCE_U/SMLA ISD nodes. Only happens when the combine has been performed on the ISD node. Also adds in check to only do the DAG combine when the node can then eventually be lowered, so changes neon tests too. --------- Co-authored-by: James Chesterman <james.chesterman@arm.com>
…36313) Make the FAIL clause contain OmpMemoryOrderType enumeration instead of OmpClause. This simplifies the semantic checks of the FAIL clause.
Implement all mf8 FMOP4A instructions in clang and llvm following the acle in https://github.com/ARM-software/acle/pull/381/files. It also updates previous mop4 instructions from IntrNoMem to IntrInaccessibleMemOnly
Summary: We treated the missing kernel environment as a unique mode, but it was kind of this random bool that was doing the same thing and it explicitly expects the kernel environment to be zero. It broke after the previous change since it used to default to SPMD and didn't handle zero in any of the other cases despite being used. This fixes that and queries for it without needing to consume an error.
Summary: This was accidentally kept in the old location when we moved to the new `lib/<triple>/` location for the DeviceRTL. Move this to reduce the delta with llvm/llvm-project#136729.
Avoid performing AA queries on non-pointers.
In order for the instruction result to alias with the pointer it needs to be a pointer.
No longer needed with opaque pointers.
Not needed with opaque pointers.
Fixes #130469
Now uses REV32/REV64 instructions to complete operation.
New Output:
```
G1:
rev64 v0.4s, v0.4s
ret
G2:
rev32 v0.8h, v0.8h
ret
G3:
rev16 v0.16b, v0.16b
ret
G4:
rev32 v0.4h, v0.4h
ret
G5:
rev16 v0.8b, v0.8b
ret
```
Old Output:
```
G1:
shl v1.2d, v0.2d, #32
usra v1.2d, v0.2d, #32
mov v0.16b, v1.16b
ret
G2:
shl v1.4s, v0.4s, #16
usra v1.4s, v0.4s, #16
mov v0.16b, v1.16b
ret
G3:
rev16 v0.16b, v0.16b
ret
G4:
shl v1.2s, v0.2s, #16
usra v1.2s, v0.2s, #16
fmov d0, d1
ret
G5:
rev16 v0.8b, v0.8b
ret
```
These are all pointer bitcasts, which are no longer necessary with opaque pointers.
`acc.set`, `acc.init`, and `acc.shutdown` take a `device_num` operand. However, this was named inconsistently. Give it the same consistent name for all aforementioned operations. --------- Co-authored-by: erichkeane <ekeane@nvidia.com>
With opaque pointers, these are all the same type. Consolidate to just PtrTy.
Not needed with opaque pointers.
…galization (#134904) Precommit tests for vector load/store legalization changes. This exposes a miscompile in LegalizerHelper::reduceLoadStoreWidth for non-byte-sized vector elements, which will be fixed in a follow-up patch. The other tests are potential miscompilations due to unclear semantics of vector load/stores, which will be addressed in a follow-up discussion.
…er parameters
I noticed that there are test-cases that are commented out. But the
manglings for them seem to be impossible to generate from valid C++. I
added two test-cases generated from following C++ program:
```
struct X {
int func() const && { return 5; }
const int &&func2() { return 5; }
const int &&func3(const int &x) volatile { return 5; }
};
void f(int (X::*)() const &&, int const && (X::*)(),
int const && (X::*)(const int &) volatile) {}
int main() {
f(&X::func, &X::func2, &X::func3);
return 0;
}
```
Patch corrects output_zp in case of usigned output
let constructor is legacy (do not use in tree!) since the tableGen
backend emits most of the glue logic to build a pass.
Note: The following constructor has been retired:
```cpp
std::unique_ptr<Pass> createExpandReallocPass(bool emitDeallocs = true);
```
To update your codebase, replace it with the new options-based API:
```cpp
memref::ExpandReallocPassOptions expandAllocPassOptions{
/*emitDeallocs=*/false};
pm.addPass(memref::createExpandReallocPass(expandAllocPassOptions));
```
Commit 8292e05 which switched the OpenCL C version to 3.0 exposed this issue, which wasn't caught in pre-commit CI.
libclc is now clean of code that triggers the bitwise-conditional-parentheses warning, so we can finally remove the workaround.
… channel Currently the data-formatters log to either DataFormatters or Types. The former is probably more sensible, so log there consistently from all formatters.
…(#137211)
This should be fine as long as we're not reading from it.
Note that this regresses
CXX/special/class.init/class.inhctor.init/p1.cpp, which used to work
fine with the bytecode interpreter.
That's because this code now fails:
```c++
struct Param;
struct A {
constexpr A(Param);
int a;
};
struct B : A { B(); using A::A; int b = 2; };
struct Wrap1 : B { constexpr Wrap1(); };
struct Wrap2 : Wrap1 {};
extern const Wrap2 b;
struct Param {
constexpr Param(int c) : n(4 * b.a + b.b + c) {}
int n;
};
```
and reports that the Param() constructor is never a valid constant
expression. But that's true and the current interpeter should report
that as well. It also fails when calling at compile time.
…ags (#137131) RFC link: https://discourse.llvm.org/t/rfc-clarify-the-behavior-of-select-with-fp-poison-generating-flags/85974 Actually, it does not conflict with the definition of FMF if we interpret a select as `applyFMF(select cond, applyFMF(TrueArm), applyFMF(FalseArm))`.
Support for Ziccamoc is added in this pr. Specification link: https://drive.google.com/file/d/12QKRm92cLcEk8-5J9NI91m0fAQOxqNAq/view --------- Co-authored-by: Tie <Tie@llvm.com>
…9c2190eb5dacfb7991f616c83a9e87740c1c6d49
Following "[mlir] Remove deprecated cast member functions (#135556) (0078cf7)", `Type::cast` and `Attribute::cast` are no longer available. Update ProcessDerivedPDLValue to use `mlir::cast<T>(baseValue)` when adapting PDL values for native rewrite functions with derived argument types. Add a regression test for a rewrite function taking `ShapedType` and `IntegerAttr`. Signed-off-by: Jonas Rickert <jonas.rickert@amd.com>
Following "[mlir] Remove deprecated cast member functions (#135556) (0078cf7)", `Type::cast` and `Attribute::cast` are no longer available. Update ProcessDerivedPDLValue to use `mlir::cast<T>(baseValue)`. Add a regression test for a rewrite function taking `ShapedType` and `IntegerAttr`. Signed-off-by: Jonas Rickert <jonas.rickert@amd.com>
Signed-off-by: Jonas Rickert <jonas.rickert@amd.com>
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marked this pull request as ready for review
July 30, 2026 08:20
jorickert
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July 30, 2026 08:20
jorickert
marked this pull request as draft
July 30, 2026 08:21
Base automatically changed from
bump_to_1d2f5ead05e85057b8d0c6198203b392e9f855f8
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July 30, 2026 09:56
…b5dacfb7991f616c83a9e87740c1c6d49
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Skipped/reverted commits:
e98a61d 2025-04-24 [mlir][tosa] Add verifier check for Concat Op
(#136047)
8158d43 2025-04-23 [TOSA] Rescale output_zp fix (#136116)
3c3fb35 2025-04-23 [mlir][tosa] Enhance CONV3D & DEPTHWISE_CONV2D
verifier (#135738)
8e9ff8e 2025-04-23 [mlir][tosa] Align Variable ops to match with
TOSA v1.0 spec (#130680)
d41bd1f 2025-04-17 [mlir][tosa] Remove trailing whitespaces
(#136031)
42ad82b 2025-04-16 [mlir][tosa] Add verifier check for Slice Op
(#135853)
96064e1 2025-04-15 [mlir][tosa] Add table size check for Table Op
(#135262)
bd9c511 2025-04-15 [mlir][tosa] Add error_if checks for Transpose
(#135219)
5d489f4 2025-04-14 [mlir][tosa] Align AbsOp example variable
names (#135268)
45aba51 2025-04-14 [mlir][tosa] Align AddOp examples to spec
(#135266)
f9b8971 2025-04-14 [mlir][tosa] Align RFFT2d and FFT2d operator
examples (#135261)
95d526f 2025-04-14 [MLIR][Tosa] Fix argmax NaN propagate lowering
(#133074)
543351b 2025-04-13 [tosa] : Re-enable PR #135429 with ASAN fix
(#135560)
d6e2aee 2025-04-13 Revert "[tosa]: canonicalize dynamic size of
tosa.slice to static output shape" (#135525)
60b1d44 2025-04-12 [tosa]: canonicalize dynamic size of
tosa.slice to static output shape (#135429)
d78b486 2025-04-11 [mlir][tosa] Add error_if checks for Mul Op
(#135075)
b39ab7a 2025-04-11 [mlir][tosa] Add error_if checks to clamp op
verifier (#134224)
ccdbd3b 2025-04-10 [mlir][tosa] Rename int_div to intdiv
(#135080)
b17bd73 2025-04-10 [mlir][tosa] Add more negative tests for rank0
tensors, negate, and sub (#135061)
2bbe8e8 2025-04-10 [mlir][tosa] Add more level_check tests for
tensor_dim and tensor_size (#135062)
751c3f5 2025-04-09 [mlir][tosa] Update TileOp infer shape
(#134732)
20d1888 2025-04-09 [mlir][tosa] Update the description of
rescaleandvariableops (#134815)interesting commits:
llvm/llvm-project#133626 [Github] Bump workflows depending on CI container to ubuntu 24.04
llvm/llvm-project#134117 [AArch64] Generalize integer FPR lane stores for all types
llvm/llvm-project#136668 [TTI] Make the rest of TTI::Concept/TTI::Model methods const (NFC)
2bc6f9d — 2025-04-24 — [TableGen] Only store direct superclasses in Record (#123072)
llvm/llvm-project#135510 [NFC][TableGen] Refactor DecoderEmitter.cpp
c239acb MCFixup: Make FixupKindInfo smaller and change getFixupKindInfo to return value
0c61b24 — [mlir] add a fluent API to GreedyRewriterConfig (#137122)
0078cf7 — [mlir] Remove deprecated cast member functions (#135556)
a625bc6 — 2025-04-10 — [HLSL][SPIR-V] Add hlsl_private addressspace for SPIR-V (#133464)
c073c22 — 2025-04-22 — [HLSL] Use hlsl_device address space for getpointer. (#127675)
[llvm][CodeGen] avoid repeated interval calculation in window scheduler (llvm/llvm-project#132352)