1717#ifdef BSP_USING_HW_I2C
1818
1919#define DRV_DEBUG
20- #define LOG_TAG "drv.hwi2c"
20+ #define LOG_TAG "drv.hwi2c"
2121#include <drv_log.h>
2222
2323#include <hal_data.h>
2424
25- #ifndef BIT
26- #define BIT (idx ) (1ul << (idx))
27- #endif
25+ #define RA_SCI_EVENT_ABORTED 0x01
26+ #define RA_SCI_EVENT_RX_COMPLETE 0x02
27+ #define RA_SCI_EVENT_TX_COMPLETE 0x04
28+ #define RA_SCI_EVENT_ERROR 0x08
29+ #define RA_SCI_EVENT_ALL 0x0F
2830
29- #ifndef BITS
30- #define BITS (b ,e ) ((((uint32_t)-1)<<(b))&(((uint32_t)-1)>>(31-(e))))
31- #endif
31+ #if defined(SOC_SERIES_R7FA2E2 )
32+
33+ #define R_IIC_MASTER_Open R_IIC_B_MASTER_Open
34+ #define R_IIC_MASTER_Write R_IIC_B_MASTER_Write
35+ #define R_IIC_MASTER_Read R_IIC_B_MASTER_Read
36+ #define R_IIC_MASTER_SlaveAddressSet R_IIC_B_MASTER_SlaveAddressSet
37+ #define R_IIC_MASTER_CallbackSet R_IIC_B_MASTER_CallbackSet
38+
39+ #elif defined(SOC_SERIES_R7SA6W1 )
40+
41+ #define R_IIC_MASTER_Open R_I2C_MASTER_W_Open
42+ #define R_IIC_MASTER_Write R_I2C_MASTER_W_Write
43+ #define R_IIC_MASTER_Read R_I2C_MASTER_W_Read
44+ #define R_IIC_MASTER_SlaveAddressSet R_I2C_MASTER_W_SlaveAddressSet
45+ #define R_IIC_MASTER_CallbackSet R_I2C_MASTER_W_CallbackSet
3246
33- #define RA_SCI_EVENT_ABORTED BIT(0)
34- #define RA_SCI_EVENT_RX_COMPLETE BIT(1)
35- #define RA_SCI_EVENT_TX_COMPLETE BIT(2)
36- #define RA_SCI_EVENT_ERROR BIT(3)
37- #define RA_SCI_EVENT_ALL BITS(0,3)
38-
39- #ifdef SOC_SERIES_R7FA2E2
40- #define R_IIC_MASTER_Open R_IIC_B_MASTER_Open
41- #define R_IIC_MASTER_Write R_IIC_B_MASTER_Write
42- #define R_IIC_MASTER_Read R_IIC_B_MASTER_Read
43- #define R_IIC_MASTER_SlaveAddressSet R_IIC_B_MASTER_SlaveAddressSet
44- #define R_IIC_MASTER_CallbackSet R_IIC_B_MASTER_CallbackSet
4547#endif
4648
4749struct ra_i2c_handle
@@ -53,16 +55,27 @@ struct ra_i2c_handle
5355 struct rt_event event ;
5456};
5557
56- static struct ra_i2c_handle ra_i2cs [] =
57- {
58+ static struct ra_i2c_handle ra_i2cs [] = {
5859#ifdef BSP_USING_HW_I2C0
59- {.bus_name = "i2c0" , .i2c_cfg = & g_i2c_master0_cfg , .i2c_ctrl = & g_i2c_master0_ctrl ,},
60+ {
61+ .bus_name = "i2c0" ,
62+ .i2c_cfg = & g_i2c_master0_cfg ,
63+ .i2c_ctrl = & g_i2c_master0_ctrl ,
64+ },
6065#endif
6166#ifdef BSP_USING_HW_I2C1
62- {.bus_name = "i2c1" , .i2c_cfg = & g_i2c_master1_cfg , .i2c_ctrl = & g_i2c_master1_ctrl ,},
67+ {
68+ .bus_name = "i2c1" ,
69+ .i2c_cfg = & g_i2c_master1_cfg ,
70+ .i2c_ctrl = & g_i2c_master1_ctrl ,
71+ },
6372#endif
6473#ifdef BSP_USING_HW_I2C2
65- {.bus_name = "i2c2" , .i2c_cfg = & g_i2c_master2_cfg , .i2c_ctrl = & g_i2c_master2_ctrl ,},
74+ {
75+ .bus_name = "i2c2" ,
76+ .i2c_cfg = & g_i2c_master2_cfg ,
77+ .i2c_ctrl = & g_i2c_master2_ctrl ,
78+ },
6679#endif
6780};
6881
@@ -177,16 +190,15 @@ static rt_ssize_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
177190 return (rt_ssize_t )i ;
178191}
179192
180- static const struct rt_i2c_bus_device_ops ra_i2c_ops =
181- {
182- .master_xfer = ra_i2c_mst_xfer ,
183- .slave_xfer = RT_NULL ,
184- .i2c_bus_control = RT_NULL
193+ static const struct rt_i2c_bus_device_ops ra_i2c_ops = {
194+ .master_xfer = ra_i2c_mst_xfer ,
195+ .slave_xfer = RT_NULL ,
196+ .i2c_bus_control = RT_NULL
185197};
186198
187199int ra_hw_i2c_init (void )
188200{
189- fsp_err_t err = FSP_SUCCESS ;
201+ fsp_err_t err = FSP_SUCCESS ;
190202 for (rt_uint32_t i = 0 ; i < sizeof (ra_i2cs ) / sizeof (ra_i2cs [0 ]); i ++ )
191203 {
192204 ra_i2cs [i ].bus .ops = & ra_i2c_ops ;
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