diff --git a/crates/transpiler/src/passes/constrained_reschedule.rs b/crates/transpiler/src/passes/constrained_reschedule.rs
index 04f356f71a18..581cb7387bce 100644
--- a/crates/transpiler/src/passes/constrained_reschedule.rs
+++ b/crates/transpiler/src/passes/constrained_reschedule.rs
@@ -80,7 +80,7 @@ fn push_node_back(
         | OperationRef::StandardInstruction(StandardInstruction::Measure) => Some(acquire_align),
         OperationRef::StandardInstruction(StandardInstruction::Delay(_)) => None,
         _ => {
-            if !op_view.directive() {
+            if op_view.directive() {
                 None
             } else {
                 return Err(TranspilerError::new_err(format!(
diff --git a/releasenotes/notes/constrained-reschedule-barrier-76cc2d270bd5ba15.yaml b/releasenotes/notes/constrained-reschedule-barrier-76cc2d270bd5ba15.yaml
new file mode 100644
index 000000000000..ba95a24d8d88
--- /dev/null
+++ b/releasenotes/notes/constrained-reschedule-barrier-76cc2d270bd5ba15.yaml
@@ -0,0 +1,5 @@
+---
+fixes:
+  - |
+    Fixed :class:`.ConstrainedReschedule` raising a :class:`.TranspilerError`
+    when rescheduling a circuit containing a :class:`.Barrier`.
diff --git a/test/python/transpiler/test_scheduling_padding_pass.py b/test/python/transpiler/test_scheduling_padding_pass.py
index 2b6c90571ff5..d4e7485512ac 100644
--- a/test/python/transpiler/test_scheduling_padding_pass.py
+++ b/test/python/transpiler/test_scheduling_padding_pass.py
@@ -23,7 +23,9 @@
 from qiskit.transpiler.passes import (
     ASAPScheduleAnalysis,
     ALAPScheduleAnalysis,
+    ConstrainedReschedule,
     PadDelay,
+    TimeUnitConversion,
 )
 from qiskit.transpiler.passmanager import PassManager
 from qiskit.transpiler.exceptions import TranspilerError
@@ -311,6 +313,25 @@ def test_parallel_gate_different_length_with_barrier(self):
 
         self.assertEqual(qc_asap, asap_expected)
 
+    def test_constrained_reschedule_accepts_barrier(self):
+        """Test that ConstrainedReschedule allows compiler directives."""
+        qc = QuantumCircuit(2)
+        qc.cx(0, 1)
+        qc.barrier(0)
+
+        target = Target(num_qubits=2, dt=1, pulse_alignment=1, acquire_alignment=1)
+        target.add_instruction(CXGate(), {(0, 1): InstructionProperties(duration=100)})
+
+        pm = PassManager(
+            [
+                TimeUnitConversion(target.durations()),
+                ALAPScheduleAnalysis(target=target),
+                ConstrainedReschedule(target=target),
+            ]
+        )
+
+        self.assertEqual(qc, pm.run(qc))
+
     def test_padding_not_working_without_scheduling(self):
         """Test padding fails when un-scheduled DAG is input."""
         qc = QuantumCircuit(1, 1)