diff --git a/demos/ES32/ES32VF2264/Makefile b/demos/ES32/ES32VF2264/Makefile new file mode 100644 index 0000000000..99df1b867a --- /dev/null +++ b/demos/ES32/ES32VF2264/Makefile @@ -0,0 +1,177 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -Os -g2 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x800 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU_ARCH = rv32emc +MCU_ABI = ilp32e +MCU_CMODEL = medlow + +# Imported source files and paths. +CHIBIOS := ../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../ +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep +BOARDDIR := $(CHIBIOS_CONTRIB)/os/hal/boards/ES32VF2264 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/RISCV-CLIC/compilers/GCC/mk/startup_ES32VF2264.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/ES32VF2264/platform.mk +include $(BOARDDIR)/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS_CONTRIB)/os/common/ports/RISCV-CLIC/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +include $(CHIBIOS)/os/test/test.mk +include $(CHIBIOS)/test/rt/rt_test.mk +include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD_CONTRIB)/ES32VF2264.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes -Wno-unused-function + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef -Wno-unused-function + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -DPORT_IGNORE_GCC_VERSION_CHECK + +# Define ASM defines here +UADEFS = -DPORT_IGNORE_GCC_VERSION_CHECK + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS_CONTRIB)/os/common/startup/RISCV-CLIC/compilers/GCC/mk +include $(RULESPATH)/riscv64-unknown-elf.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/demos/ES32/ES32VF2264/cfg/chconf.h b/demos/ES32/ES32VF2264/cfg/chconf.h new file mode 100644 index 0000000000..093a1bae36 --- /dev/null +++ b/demos/ES32/ES32VF2264/cfg/chconf.h @@ -0,0 +1,834 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM FALSE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time time stamps APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP FALSE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/demos/ES32/ES32VF2264/cfg/halconf.h b/demos/ES32/ES32VF2264/cfg/halconf.h new file mode 100644 index 0000000000..165aedf025 --- /dev/null +++ b/demos/ES32/ES32VF2264/cfg/halconf.h @@ -0,0 +1,532 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE FALSE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS FALSE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING FALSE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT TRUE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/demos/ES32/ES32VF2264/cfg/halconf_community.h b/demos/ES32/ES32VF2264/cfg/halconf_community.h new file mode 100644 index 0000000000..34677960f8 --- /dev/null +++ b/demos/ES32/ES32VF2264/cfg/halconf_community.h @@ -0,0 +1,180 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY FALSE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/demos/ES32/ES32VF2264/cfg/mcuconf.h b/demos/ES32/ES32VF2264/cfg/mcuconf.h new file mode 100644 index 0000000000..ca5d09f8b5 --- /dev/null +++ b/demos/ES32/ES32VF2264/cfg/mcuconf.h @@ -0,0 +1,212 @@ +/* + Copyright (C) 2021 essemi + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define ES32_ES32VF2264_MCUCONF + +/** + * @name Internal clock sources + * @{ + */ +#define ES32_PLLCLK 72000000 +#define ES32_HRCCLK 48000000 +#define ES32_LSECLK 32768 + +/* + * HAL driver system settings. + */ +#define ES32_NO_INIT FALSE + +/*system_clk select + +MD_RCU_SW_SYSCLK_HRC = HRC selected as system clock +MD_RCU_SW_SYSCLK_HOSC = HOSC selected as system clock +MD_RCU_SW_SYSCLK_PLL0 = PLL0 selected as system clock +MD_RCU_SW_SYSCLK_HRC48 = HRC48 selected as system clock +*/ +#define ES32_SYSCLK_SOURSE_SELECT MD_RCU_SW_SYSCLK_PLL0 + +/*external clk config*/ +#define ES32_HOSC_CLK_EN FALSE +#define ES32_HOSC_CLK_FREQ 8 + +/*pll clk config + +MD_RCU_PLLSRC_HRC = HRC selected as PLL reference clock +MD_RCU_PLLSRC_HOSC = HOSC selected as PLL reference clock +MD_RCU_PLLSRC_HRC48 = HRC48 selected as PLL reference clock + +MD_RCU_PLLCLK_PASS = 0 +MD_RCU_PLLCLK_4M = 4000000 +MD_RCU_PLLCLK_8M = 8000000 +MD_RCU_PLLCLK_12M = 12000000 +MD_RCU_PLLCLK_16M = 16000000 +MD_RCU_PLLCLK_24M = 24000000 +MD_RCU_PLLCLK_32M = 32000000 +MD_RCU_PLLCLK_36M = 36000000 +MD_RCU_PLLCLK_40M = 40000000 +MD_RCU_PLLCLK_48M = 48000000 +MD_RCU_PLLCLK_64M = 64000000 +MD_RCU_PLLCLK_72M = 72000000 +*/ +#define ES32_PLL_CLK_EN TRUE +#define ES32_PLL_SOURSE_SELECT MD_RCU_PLLSRC_HRC48 +#define ES32_PLL_CLK_FREQ MD_RCU_PLLCLK_72M + +/*bus clk config + +MD_RCU_HPRE_SYSCLK_DIV_1 = SYSCLK not divided +MD_RCU_HPRE_SYSCLK_DIV_2 = SYSCLK divided by 2 +MD_RCU_HPRE_SYSCLK_DIV_4 = SYSCLK divided by 4 +MD_RCU_HPRE_SYSCLK_DIV_8 = SYSCLK divided by 8 +MD_RCU_HPRE_SYSCLK_DIV_16 = SYSCLK divided by 16 +MD_RCU_HPRE_SYSCLK_DIV_64 = SYSCLK divided by 64 +MD_RCU_HPRE_SYSCLK_DIV_128 = SYSCLK divided by 128 +MD_RCU_HPRE_SYSCLK_DIV_256 = SYSCLK divided by 256 +MD_RCU_HPRE_SYSCLK_DIV_512 = @brief SYSCLK divided by 512 + +MD_RCU_PPRE_HCLK_DIV_1 = HCLK not divided +MD_RCU_PPRE_HCLK_DIV_2 = HCLK divided by 2 +MD_RCU_PPRE_HCLK_DIV_4 = HCLK divided by 4 +MD_RCU_PPRE_HCLK_DIV_8 = HCLK divided by 8 +MD_RCU_PPRE_HCLK_DIV_16 = HCLK divided by 16 +*/ +#define ES32_BUS_DIV_HPRE MD_RCU_HPRE_SYSCLK_DIV_1 +#define ES32_BUS_DIV_PPRE MD_RCU_PPRE_HCLK_DIV_1 + +/* + * EXTI driver system settings. + */ +#define ES32_IRQ_EXTI0_PRIORITY 6 +#define ES32_IRQ_EXTI1_PRIORITY 6 +#define ES32_IRQ_EXTI2_PRIORITY 6 +#define ES32_IRQ_EXTI3_PRIORITY 6 +#define ES32_IRQ_EXTI4_PRIORITY 6 +#define ES32_IRQ_EXTI5_9_PRIORITY 6 +#define ES32_IRQ_EXTI10_15_PRIORITY 6 +#define ES32_IRQ_EXTI16_PRIORITY 6 +#define ES32_IRQ_EXTI17_PRIORITY 6 +#define ES32_IRQ_EXTI18_PRIORITY 6 +#define ES32_IRQ_EXTI19_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define ES32_TIM_MAX_CHANNELS 4 +#define ES32_GPT_USE_TIM1 FALSE +#define ES32_GPT_USE_TIM2 FALSE +#define ES32_GPT_USE_TIM3 FALSE +#define ES32_GPT_USE_TIM4 FALSE +#define ES32_GPT_TIM1_IRQ_PRIORITY 7 +#define ES32_GPT_TIM2_IRQ_PRIORITY 7 +#define ES32_GPT_TIM3_IRQ_PRIORITY 7 +#define ES32_GPT_TIM4_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define ES32_ICU_USE_TIM1 FALSE +#define ES32_ICU_USE_TIM2 FALSE +#define ES32_ICU_USE_TIM3 FALSE +#define ES32_ICU_USE_TIM4 FALSE +#define ES32_ICU_TIM1_IRQ_PRIORITY 7 +#define ES32_ICU_TIM2_IRQ_PRIORITY 7 +#define ES32_ICU_TIM3_IRQ_PRIORITY 7 +#define ES32_ICU_TIM4_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define ES32_PWM_USE_AD16C4T1 TRUE +#define ES32_PWM_USE_GP32C4T1 TRUE +#define ES32_PWM_USE_GP16C4T1 TRUE +#define ES32_PWM_USE_GP16C4T2 TRUE +#define ES32_PWM_USE_GP16C4T3 TRUE +#define ES32_PWM_USE_GP16C2T1 TRUE +#define ES32_PWM_USE_GP16C2T2 TRUE +#define ES32_PWM_USE_GP16C2T3 TRUE +#define ES32_PWM_USE_GP16C2T4 TRUE +#define ES32_PWM_AD16C4T1_IRQ_PRIORITY 7 +#define ES32_PWM_GP32C4T1_IRQ_PRIORITY 7 +#define ES32_PWM_GP16C4T1_IRQ_PRIORITY 7 +#define ES32_PWM_GP16C4T2_IRQ_PRIORITY 7 +#define ES32_PWM_GP16C4T3_IRQ_PRIORITY 7 +#define ES32_PWM_GP16C2T1_IRQ_PRIORITY 7 +#define ES32_PWM_GP16C2T2_IRQ_PRIORITY 7 +#define ES32_PWM_GP16C2T3_IRQ_PRIORITY 7 +#define ES32_PWM_GP16C2T4_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define ES32_I2C_USE_I2C1 FALSE +#define ES32_I2C_USE_I2C2 FALSE +#define ES32_I2C_BUSY_TIMEOUT 50 +#define ES32_I2C_I2C1_IRQ_PRIORITY 5 +#define ES32_I2C_I2C2_IRQ_PRIORITY 5 + +/* + * SERIAL driver system settings. + */ +#define ES32_SERIAL_USE_UART1 TRUE +#define ES32_SERIAL_USE_UART2 TRUE +#define ES32_SERIAL_USE_UART3 TRUE +#define ES32_SERIAL_USE_UART4 TRUE +#define ES32_SERIAL_USART1_PRIORITY 7 +#define ES32_SERIAL_USART1_PRIORITY 7 +#define ES32_SERIAL_USART1_PRIORITY 7 +#define ES32_SERIAL_USART1_PRIORITY 7 + +/* + * SPI driver system settings. + */ +#define ES32_SPI_USE_SPI1 TRUE +#define ES32_SPI_USE_SPI2 TRUE + +/* + * ST driver system settings. + */ +#define ES32_ST_IRQ_PRIORITY 8 +#define ES32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define ES32_UART_USE_UART1 FALSE +#define ES32_UART_USE_UART2 FALSE +#define ES32_UART_USE_UART3 FALSE +#define ES32_UART_UART1_IRQ_PRIORITY 12 +#define ES32_UART_UART2_IRQ_PRIORITY 12 +#define ES32_UART_UART3_IRQ_PRIORITY 12 + +/* + * USB driver system settings. + */ +#define ES32_USB_USE_USB1 TRUE +#define ES32_USB_USB1_IRQ_PRIORITY 13 +#define ES32_USB_HOST_WAKEUP_DURATION 10 +#define ES32_USE_USB_SOF_TRIM_HRC48 TRUE + +/* + * ADC driver system settings. + */ +#define ES32_ADC_USE_ADC1 FALSE +#define ES32_ADC_ADC1_DMA_PRIORITY 2 +#define ES32_ADC_ADC1_IRQ_PRIORITY 6 + +#endif /* MCUCONF_H */ diff --git a/demos/ES32/ES32VF2264/main.c b/demos/ES32/ES32VF2264/main.c new file mode 100644 index 0000000000..81c4668f55 --- /dev/null +++ b/demos/ES32/ES32VF2264/main.c @@ -0,0 +1,70 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include +#include + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Generic code. */ +/*===========================================================================*/ + +/* + * Red LED blinker thread, times are in milliseconds. + */ +static THD_WORKING_AREA(waThread1, 128); +static THD_FUNCTION(Thread1, arg) { + + (void)arg; + while (true) { + palClearLine(2); + chThdSleepMilliseconds(500); + palSetLine(2); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + chThdSleepMilliseconds(1000); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), 5, Thread1, NULL); + + /* + * Normal main() thread activity, spawning shells. + */ + while (true) { + chThdSleepMilliseconds(1000); + } +} diff --git a/demos/ES32/ES32VF2264/readme.txt b/demos/ES32/ES32VF2264/readme.txt new file mode 100644 index 0000000000..1e5a64db31 --- /dev/null +++ b/demos/ES32/ES32VF2264/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/HAL - driver demo for ES32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ES-PDS ES32F0283_FS026 board. + +** The Demo ** + +The application demonstrates the use of the ES32F0283_FS026 drivers. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +essemi and are licensed under a different license. +Also note that not all the files present in the essemi library are distributed +with ChibiOS/RT, you can find the whole library on the essemi web site: + + http://www.essemi.com diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_adc.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_adc.h new file mode 100644 index 0000000000..22032b7171 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_adc.h @@ -0,0 +1,420 @@ +/********************************************************************************** + * + * @file reg_adc.h + * @brief ADC Head File + * + * @date 26 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 26 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_ADC_H__ +#define __REG_ADC_H__ + +/* Includes ------------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ +/* Exported Macros ----------------------------------------------------------- */ + +/****************** Bit definition for ADC_STAT register ************************/ + +#define ADC_STAT_ICHS_POS 9U +#define ADC_STAT_ICHS_MSK BIT(ADC_STAT_ICHS_POS) + +#define ADC_STAT_NCHS_POS 8U +#define ADC_STAT_NCHS_MSK BIT(ADC_STAT_NCHS_POS) + +#define ADC_STAT_OVR_POS 3U +#define ADC_STAT_OVR_MSK BIT(ADC_STAT_OVR_POS) + +#define ADC_STAT_ICHE_POS 2U +#define ADC_STAT_ICHE_MSK BIT(ADC_STAT_ICHE_POS) + +#define ADC_STAT_NCHE_POS 1U +#define ADC_STAT_NCHE_MSK BIT(ADC_STAT_NCHE_POS) + +#define ADC_STAT_AWDF_POS 0U +#define ADC_STAT_AWDF_MSK BIT(ADC_STAT_AWDF_POS) + +/****************** Bit definition for ADC_CLR register ************************/ + +#define ADC_CLR_ICHS_POS 9U +#define ADC_CLR_ICHS_MSK BIT(ADC_CLR_ICHS_POS) + +#define ADC_CLR_NCHS_POS 8U +#define ADC_CLR_NCHS_MSK BIT(ADC_CLR_NCHS_POS) + +#define ADC_CLR_OVR_POS 3U +#define ADC_CLR_OVR_MSK BIT(ADC_CLR_OVR_POS) + +#define ADC_CLR_ICHE_POS 2U +#define ADC_CLR_ICHE_MSK BIT(ADC_CLR_ICHE_POS) + +#define ADC_CLR_NCHE_POS 1U +#define ADC_CLR_NCHE_MSK BIT(ADC_CLR_NCHE_POS) + +#define ADC_CLR_AWDF_POS 0U +#define ADC_CLR_AWDF_MSK BIT(ADC_CLR_AWDF_POS) + +/****************** Bit definition for ADC_CON0 register ************************/ + +#define ADC_CON0_OVRIE_POS 26U +#define ADC_CON0_OVRIE_MSK BIT(ADC_CON0_OVRIE_POS) + +#define ADC_CON0_RSEL_POSS 24U +#define ADC_CON0_RSEL_POSE 25U +#define ADC_CON0_RSEL_MSK BITS(ADC_CON0_RSEL_POSS,ADC_CON0_RSEL_POSE) + +#define ADC_CON0_NCHWDEN_POS 23U +#define ADC_CON0_NCHWDEN_MSK BIT(ADC_CON0_NCHWDEN_POS) + +#define ADC_CON0_ICHWDTEN_POS 22U +#define ADC_CON0_ICHWDTEN_MSK BIT(ADC_CON0_ICHWDTEN_POS) + +#define ADC_CON0_CNTW_POSS 16U +#define ADC_CON0_CNTW_POSE 18U +#define ADC_CON0_CNTW_MSK BITS(ADC_CON0_CNTW_POSS,ADC_CON0_CNTW_POSE) + +#define ADC_CON0_ETRGN_POSS 13U +#define ADC_CON0_ETRGN_POSE 15U +#define ADC_CON0_ETRGN_MSK BITS(ADC_CON0_ETRGN_POSS,ADC_CON0_ETRGN_POSE) + +#define ADC_CON0_ICHDCEN_POS 12U +#define ADC_CON0_ICHDCEN_MSK BIT(ADC_CON0_ICHDCEN_POS) + +#define ADC_CON0_NCHDCEN_POS 11U +#define ADC_CON0_NCHDCEN_MSK BIT(ADC_CON0_NCHDCEN_POS) + +#define ADC_CON0_IAUTO_POS 10U +#define ADC_CON0_IAUTO_MSK BIT(ADC_CON0_IAUTO_POS) + +#define ADC_CON0_AWDSGL_POS 9U +#define ADC_CON0_AWDSGL_MSK BIT(ADC_CON0_AWDSGL_POS) + +#define ADC_CON0_SCANEN_POS 8U +#define ADC_CON0_SCANEN_MSK BIT(ADC_CON0_SCANEN_POS) + +#define ADC_CON0_ICHEIE_POS 7U +#define ADC_CON0_ICHEIE_MSK BIT(ADC_CON0_ICHEIE_POS) + +#define ADC_CON0_AWDIE_POS 6U +#define ADC_CON0_AWDIE_MSK BIT(ADC_CON0_AWDIE_POS) + +#define ADC_CON0_NCHEIE_POS 5U +#define ADC_CON0_NCHEIE_MSK BIT(ADC_CON0_NCHEIE_POS) + +#define ADC_CON0_AWDCH_POSS 0U +#define ADC_CON0_AWDCH_POSE 4U +#define ADC_CON0_AWDCH_MSK BITS(ADC_CON0_AWDCH_POSS,ADC_CON0_AWDCH_POSE) + +/****************** Bit definition for ADC_CON1 register ************************/ + +#define ADC_CON1_NCHTRG_POS 30U +#define ADC_CON1_NCHTRG_MSK BIT(ADC_CON1_NCHTRG_POS) + +#define ADC_CON1_NETS_POSS 28U +#define ADC_CON1_NETS_POSE 29U +#define ADC_CON1_NETS_MSK BITS(ADC_CON1_NETS_POSS,ADC_CON1_NETS_POSE) + +#define ADC_CON1_ICHTRG_POS 22U +#define ADC_CON1_ICHTRG_MSK BIT(ADC_CON1_ICHTRG_POS) + +#define ADC_CON1_IETS_POSS 20U +#define ADC_CON1_IETS_POSE 21U +#define ADC_CON1_IETS_MSK BITS(ADC_CON1_IETS_POSS,ADC_CON1_IETS_POSE) + +#define ADC_CON1_ALIGN_POS 11U +#define ADC_CON1_ALIGN_MSK BIT(ADC_CON1_ALIGN_POS) + +#define ADC_CON1_NCHESEL_POS 10U +#define ADC_CON1_NCHESEL_MSK BIT(ADC_CON1_NCHESEL_POS) + +#define ADC_CON1_DMA_POS 8U +#define ADC_CON1_DMA_MSK BIT(ADC_CON1_DMA_POS) + +#define ADC_CON1_CM_POS 1U +#define ADC_CON1_CM_MSK BIT(ADC_CON1_CM_POS) + +#define ADC_CON1_ADCEN_POS 0U +#define ADC_CON1_ADCEN_MSK BIT(ADC_CON1_ADCEN_POS) + +/****************** Bit definition for ADC_SMPT1 register ************************/ + +#define ADC_SMPT1_CHT_POSS 0U +#define ADC_SMPT1_CHT_POSE 31U +#define ADC_SMPT1_CHT_MSK BITS(ADC_SMPT1_CHT_POSS,ADC_SMPT1_CHT_POSE) + +/****************** Bit definition for ADC_SMPT2 register ************************/ + +#define ADC_SMPT2_CHT_POSS 0U +#define ADC_SMPT2_CHT_POSE 31U +#define ADC_SMPT2_CHT_MSK BITS(ADC_SMPT2_CHT_POSS,ADC_SMPT2_CHT_POSE) + +/****************** Bit definition for ADC_SMPT3 register ************************/ + +#define ADC_SMPT3_SMP_POSS 0U +#define ADC_SMPT3_SMP_POSE 31U +#define ADC_SMPT3_SMP_MSK BITS(ADC_SMPT3_SMP_POSS,ADC_SMPT3_SMP_POSE) + +/****************** Bit definition for ADC_NCHOFF register ************************/ + +#define ADC_NCHOFF_NOFF_POSS 0U +#define ADC_NCHOFF_NOFF_POSE 11U +#define ADC_NCHOFF_NOFF_MSK BITS(ADC_NCHOFF_NOFF_POSS,ADC_NCHOFF_NOFF_POSE) + +/****************** Bit definition for ADC_ICHOFF1 register ************************/ + +#define ADC_ICHOFF1_IOFF1_POSS 0U +#define ADC_ICHOFF1_IOFF1_POSE 11U +#define ADC_ICHOFF1_IOFF1_MSK BITS(ADC_ICHOFF1_IOFF1_POSS,ADC_ICHOFF1_IOFF1_POSE) + +/****************** Bit definition for ADC_ICHOFF2 register ************************/ + +#define ADC_ICHOFF2_IOFF2_POSS 0U +#define ADC_ICHOFF2_IOFF2_POSE 11U +#define ADC_ICHOFF2_IOFF2_MSK BITS(ADC_ICHOFF2_IOFF2_POSS,ADC_ICHOFF2_IOFF2_POSE) + +/****************** Bit definition for ADC_ICHOFF3 register ************************/ + +#define ADC_ICHOFF3_IOFF3_POSS 0U +#define ADC_ICHOFF3_IOFF3_POSE 11U +#define ADC_ICHOFF3_IOFF3_MSK BITS(ADC_ICHOFF3_IOFF3_POSS,ADC_ICHOFF3_IOFF3_POSE) + +/****************** Bit definition for ADC_ICHOFF4 register ************************/ + +#define ADC_ICHOFF4_IOFF4_POSS 0U +#define ADC_ICHOFF4_IOFF4_POSE 11U +#define ADC_ICHOFF4_IOFF4_MSK BITS(ADC_ICHOFF4_IOFF4_POSS,ADC_ICHOFF4_IOFF4_POSE) + +/****************** Bit definition for ADC_NCHS1 register ************************/ + +#define ADC_NCHS1_NS4_POSS 24U +#define ADC_NCHS1_NS4_POSE 28U +#define ADC_NCHS1_NS4_MSK BITS(ADC_NCHS1_NS4_POSS,ADC_NCHS1_NS4_POSE) + +#define ADC_NCHS1_NS3_POSS 16U +#define ADC_NCHS1_NS3_POSE 20U +#define ADC_NCHS1_NS3_MSK BITS(ADC_NCHS1_NS3_POSS,ADC_NCHS1_NS3_POSE) + +#define ADC_NCHS1_NS2_POSS 8U +#define ADC_NCHS1_NS2_POSE 12U +#define ADC_NCHS1_NS2_MSK BITS(ADC_NCHS1_NS2_POSS,ADC_NCHS1_NS2_POSE) + +#define ADC_NCHS1_NS1_POSS 0U +#define ADC_NCHS1_NS1_POSE 4U +#define ADC_NCHS1_NS1_MSK BITS(ADC_NCHS1_NS1_POSS,ADC_NCHS1_NS1_POSE) + +/****************** Bit definition for ADC_NCHS2 register ************************/ + +#define ADC_NCHS2_NS8_POSS 24U +#define ADC_NCHS2_NS8_POSE 28U +#define ADC_NCHS2_NS8_MSK BITS(ADC_NCHS2_NS8_POSS,ADC_NCHS2_NS8_POSE) + +#define ADC_NCHS2_NS7_POSS 16U +#define ADC_NCHS2_NS7_POSE 20U +#define ADC_NCHS2_NS7_MSK BITS(ADC_NCHS2_NS7_POSS,ADC_NCHS2_NS7_POSE) + +#define ADC_NCHS2_NS6_POSS 8U +#define ADC_NCHS2_NS6_POSE 12U +#define ADC_NCHS2_NS6_MSK BITS(ADC_NCHS2_NS6_POSS,ADC_NCHS2_NS6_POSE) + +#define ADC_NCHS2_NS5_POSS 0U +#define ADC_NCHS2_NS5_POSE 4U +#define ADC_NCHS2_NS5_MSK BITS(ADC_NCHS2_NS5_POSS,ADC_NCHS2_NS5_POSE) + +/****************** Bit definition for ADC_NCHS3 register ************************/ + +#define ADC_NCHS3_NS12_POSS 24U +#define ADC_NCHS3_NS12_POSE 28U +#define ADC_NCHS3_NS12_MSK BITS(ADC_NCHS3_NS12_POSS,ADC_NCHS3_NS12_POSE) + +#define ADC_NCHS3_NS11_POSS 16U +#define ADC_NCHS3_NS11_POSE 20U +#define ADC_NCHS3_NS11_MSK BITS(ADC_NCHS3_NS11_POSS,ADC_NCHS3_NS11_POSE) + +#define ADC_NCHS3_NS10_POSS 8U +#define ADC_NCHS3_NS10_POSE 12U +#define ADC_NCHS3_NS10_MSK BITS(ADC_NCHS3_NS10_POSS,ADC_NCHS3_NS10_POSE) + +#define ADC_NCHS3_NS9_POSS 0U +#define ADC_NCHS3_NS9_POSE 4U +#define ADC_NCHS3_NS9_MSK BITS(ADC_NCHS3_NS9_POSS,ADC_NCHS3_NS9_POSE) + +/****************** Bit definition for ADC_NCHS4 register ************************/ + +#define ADC_NCHS4_NS16_POSS 24U +#define ADC_NCHS4_NS16_POSE 28U +#define ADC_NCHS4_NS16_MSK BITS(ADC_NCHS4_NS16_POSS,ADC_NCHS4_NS16_POSE) + +#define ADC_NCHS4_NS15_POSS 16U +#define ADC_NCHS4_NS15_POSE 20U +#define ADC_NCHS4_NS15_MSK BITS(ADC_NCHS4_NS15_POSS,ADC_NCHS4_NS15_POSE) + +#define ADC_NCHS4_NS14_POSS 8U +#define ADC_NCHS4_NS14_POSE 12U +#define ADC_NCHS4_NS14_MSK BITS(ADC_NCHS4_NS14_POSS,ADC_NCHS4_NS14_POSE) + +#define ADC_NCHS4_NS13_POSS 0U +#define ADC_NCHS4_NS13_POSE 4U +#define ADC_NCHS4_NS13_MSK BITS(ADC_NCHS4_NS13_POSS,ADC_NCHS4_NS13_POSE) + +/****************** Bit definition for ADC_ICHS register ************************/ + +#define ADC_ICHS_IS4_POSS 24U +#define ADC_ICHS_IS4_POSE 28U +#define ADC_ICHS_IS4_MSK BITS(ADC_ICHS_IS4_POSS,ADC_ICHS_IS4_POSE) + +#define ADC_ICHS_IS3_POSS 16U +#define ADC_ICHS_IS3_POSE 20U +#define ADC_ICHS_IS3_MSK BITS(ADC_ICHS_IS3_POSS,ADC_ICHS_IS3_POSE) + +#define ADC_ICHS_IS2_POSS 8U +#define ADC_ICHS_IS2_POSE 12U +#define ADC_ICHS_IS2_MSK BITS(ADC_ICHS_IS2_POSS,ADC_ICHS_IS2_POSE) + +#define ADC_ICHS_IS1_POSS 0U +#define ADC_ICHS_IS1_POSE 4U +#define ADC_ICHS_IS1_MSK BITS(ADC_ICHS_IS1_POSS,ADC_ICHS_IS1_POSE) + +/****************** Bit definition for ADC_CHSL register ************************/ + +#define ADC_CHSL_ISL_POSS 8U +#define ADC_CHSL_ISL_POSE 9U +#define ADC_CHSL_ISL_MSK BITS(ADC_CHSL_ISL_POSS,ADC_CHSL_ISL_POSE) + +#define ADC_CHSL_NSL_POSS 0U +#define ADC_CHSL_NSL_POSE 3U +#define ADC_CHSL_NSL_MSK BITS(ADC_CHSL_NSL_POSS,ADC_CHSL_NSL_POSE) + +/****************** Bit definition for ADC_WDTH register ************************/ + +#define ADC_WDTH_HT_POSS 0U +#define ADC_WDTH_HT_POSE 11U +#define ADC_WDTH_HT_MSK BITS(ADC_WDTH_HT_POSS,ADC_WDTH_HT_POSE) + +/****************** Bit definition for ADC_WDTL register ************************/ + +#define ADC_WDTL_LT_POSS 0U +#define ADC_WDTL_LT_POSE 11U +#define ADC_WDTL_LT_MSK BITS(ADC_WDTL_LT_POSS,ADC_WDTL_LT_POSE) + +/****************** Bit definition for ADC_ICHDR1 register ************************/ + +#define ADC_ICHDR1_VAL_POSS 0U +#define ADC_ICHDR1_VAL_POSE 15U +#define ADC_ICHDR1_VAL_MSK BITS(ADC_ICHDR1_VAL_POSS,ADC_ICHDR1_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR2 register ************************/ + +#define ADC_ICHDR2_VAL_POSS 0U +#define ADC_ICHDR2_VAL_POSE 15U +#define ADC_ICHDR2_VAL_MSK BITS(ADC_ICHDR2_VAL_POSS,ADC_ICHDR2_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR3 register ************************/ + +#define ADC_ICHDR3_VAL_POSS 0U +#define ADC_ICHDR3_VAL_POSE 15U +#define ADC_ICHDR3_VAL_MSK BITS(ADC_ICHDR3_VAL_POSS,ADC_ICHDR3_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR4 register ************************/ + +#define ADC_ICHDR4_VAL_POSS 0U +#define ADC_ICHDR4_VAL_POSE 15U +#define ADC_ICHDR4_VAL_MSK BITS(ADC_ICHDR4_VAL_POSS,ADC_ICHDR4_VAL_POSE) + +/****************** Bit definition for ADC_NCHDR register ************************/ + +#define ADC_NCHDR_VAL_POSS 0U +#define ADC_NCHDR_VAL_POSE 15U +#define ADC_NCHDR_VAL_MSK BITS(ADC_NCHDR_VAL_POSS,ADC_NCHDR_VAL_POSE) + +/****************** Bit definition for ADC_CCR register ************************/ + +#define ADC_CCR_CALZERO_POS 29U +#define ADC_CCR_CALZERO_MSK BIT(ADC_CCR_CALZERO_POS) + +#define ADC_CCR_TRMEN_POS 28U +#define ADC_CCR_TRMEN_MSK BIT(ADC_CCR_TRMEN_POS) + +#define ADC_CCR_TSEN_POS 20U +#define ADC_CCR_TSEN_MSK BIT(ADC_CCR_TSEN_POS) + +#define ADC_CCR_VRNSEL_POS 18U +#define ADC_CCR_VRNSEL_MSK BIT(ADC_CCR_VRNSEL_POS) + +#define ADC_CCR_VRPSEL_POS 17U +#define ADC_CCR_VRPSEL_MSK BIT(ADC_CCR_VRPSEL_POS) + +#define ADC_CCR_PWRMODSEL_POS 15U +#define ADC_CCR_PWRMODSEL_MSK BIT(ADC_CCR_PWRMODSEL_POS) + +#define ADC_CCR_IREFEN_POS 11U +#define ADC_CCR_IREFEN_MSK BIT(ADC_CCR_IREFEN_POS) + +#define ADC_CCR_VREFEN_POS 8U +#define ADC_CCR_VREFEN_MSK BIT(ADC_CCR_VREFEN_POS) + +#define ADC_CCR_PREDIV_POS 3U +#define ADC_CCR_PREDIV_MSK BIT(ADC_CCR_PREDIV_POS) + +#define ADC_CCR_POSDIV_POSS 0U +#define ADC_CCR_POSDIV_POSE 2U +#define ADC_CCR_POSDIV_MSK BITS(ADC_CCR_POSDIV_POSS,ADC_CCR_POSDIV_POSE) + +/* Exported Types ------------------------------------------------------------ */ + +typedef struct +{ + __I uint32_t STAT; + __O uint32_t CLR; + __IO uint32_t CON0; + __IO uint32_t CON1; + __IO uint32_t SMPT1; + __IO uint32_t SMPT2; + __IO uint32_t SMPT3; + __IO uint32_t NCHOFF; + __IO uint32_t ICHOFF1; + __IO uint32_t ICHOFF2; + __IO uint32_t ICHOFF3; + __IO uint32_t ICHOFF4; + __IO uint32_t NCHS1; + __IO uint32_t NCHS2; + __IO uint32_t NCHS3; + __IO uint32_t NCHS4; + __IO uint32_t ICHS; + __IO uint32_t CHSL; + __IO uint32_t WDTH; + __IO uint32_t WDTL; + __I uint32_t ICHDR1; + __I uint32_t ICHDR2; + __I uint32_t ICHDR3; + __I uint32_t ICHDR4; + __I uint32_t NCHDR; + __IO uint32_t CCR; +} ADC_TypeDef; + +#endif /* __REG_ADC_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_cmu.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_cmu.h new file mode 100644 index 0000000000..bb35a7cb89 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_cmu.h @@ -0,0 +1,358 @@ +/********************************************************************************** + * + * @file reg_cmu.h + * @brief CMU Head File + * + * @date 14 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 14 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_CMU_H__ +#define __REG_CMU_H__ + +/* Includes ------------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ +/* Exported Macros ----------------------------------------------------------- */ + +/****************** Bit definition for CMU_CSR register ************************/ + +#define CMU_CSR_CFT_RDYN_POS 25U +#define CMU_CSR_CFT_RDYN_MSK BIT(CMU_CSR_CFT_RDYN_POS) + +#define CMU_CSR_CFT_STU_POS 24U +#define CMU_CSR_CFT_STU_MSK BIT(CMU_CSR_CFT_STU_POS) + +#define CMU_CSR_CFT_CMD_POSS 16U +#define CMU_CSR_CFT_CMD_POSE 23U +#define CMU_CSR_CFT_CMD_MSK BITS(CMU_CSR_CFT_CMD_POSS,CMU_CSR_CFT_CMD_POSE) + +#define CMU_CSR_SYS_RDYN_POS 12U +#define CMU_CSR_SYS_RDYN_MSK BIT(CMU_CSR_SYS_RDYN_POS) + +#define CMU_CSR_SYS_STU_POSS 8U +#define CMU_CSR_SYS_STU_POSE 10U +#define CMU_CSR_SYS_STU_MSK BITS(CMU_CSR_SYS_STU_POSS,CMU_CSR_SYS_STU_POSE) + +#define CMU_CSR_SYS_CMD_POSS 0U +#define CMU_CSR_SYS_CMD_POSE 2U +#define CMU_CSR_SYS_CMD_MSK BITS(CMU_CSR_SYS_CMD_POSS,CMU_CSR_SYS_CMD_POSE) + +/****************** Bit definition for CMU_CFGR register ************************/ + +#define CMU_CFGR_PCLKDIV_POSS 16U +#define CMU_CFGR_PCLKDIV_POSE 19U +#define CMU_CFGR_PCLKDIV_MSK BITS(CMU_CFGR_PCLKDIV_POSS,CMU_CFGR_PCLKDIV_POSE) + +#define CMU_CFGR_SYSDIV_POSS 12U +#define CMU_CFGR_SYSDIV_POSE 15U +#define CMU_CFGR_SYSDIV_MSK BITS(CMU_CFGR_SYSDIV_POSS,CMU_CFGR_SYSDIV_POSE) + +#define CMU_CFGR_USBSW_POS 4U +#define CMU_CFGR_USBSW_MSK BIT(CMU_CFGR_USBSW_POS) + +#define CMU_CFGR_I2SSW_POS 0U +#define CMU_CFGR_I2SSW_MSK BIT(CMU_CFGR_I2SSW_POS) + +/****************** Bit definition for CMU_CLKENR register ************************/ + +#define CMU_CLKENR_HOSCFLYBPS_POS 10U +#define CMU_CLKENR_HOSCFLYBPS_MSK BIT(CMU_CLKENR_HOSCFLYBPS_POS) + +#define CMU_CLKENR_HOSCBPS_POS 9U +#define CMU_CLKENR_HOSCBPS_MSK BIT(CMU_CLKENR_HOSCBPS_POS) + +#define CMU_CLKENR_HOSC32K_POS 8U +#define CMU_CLKENR_HOSC32K_MSK BIT(CMU_CLKENR_HOSC32K_POS) + +#define CMU_CLKENR_USBCKEN_POS 7U +#define CMU_CLKENR_USBCKEN_MSK BIT(CMU_CLKENR_USBCKEN_POS) + +#define CMU_CLKENR_I2SCKEN_POS 6U +#define CMU_CLKENR_I2SCKEN_MSK BIT(CMU_CLKENR_I2SCKEN_POS) + +#define CMU_CLKENR_HRC48MFLYBPS_POS 4U +#define CMU_CLKENR_HRC48MFLYBPS_MSK BIT(CMU_CLKENR_HRC48MFLYBPS_POS) + +#define CMU_CLKENR_PLLEN_POS 3U +#define CMU_CLKENR_PLLEN_MSK BIT(CMU_CLKENR_PLLEN_POS) + +#define CMU_CLKENR_HRC4MEN_POS 2U +#define CMU_CLKENR_HRC4MEN_MSK BIT(CMU_CLKENR_HRC4MEN_POS) + +#define CMU_CLKENR_HRC48MEN_POS 1U +#define CMU_CLKENR_HRC48MEN_MSK BIT(CMU_CLKENR_HRC48MEN_POS) + +#define CMU_CLKENR_HOSCEN_POS 0U +#define CMU_CLKENR_HOSCEN_MSK BIT(CMU_CLKENR_HOSCEN_POS) + +/****************** Bit definition for CMU_CLKSR register ************************/ + +#define CMU_CLKSR_PLLRDY_POS 24U +#define CMU_CLKSR_PLLRDY_MSK BIT(CMU_CLKSR_PLLRDY_POS) + +#define CMU_CLKSR_LRCRDY_POS 19U +#define CMU_CLKSR_LRCRDY_MSK BIT(CMU_CLKSR_LRCRDY_POS) + +#define CMU_CLKSR_HRC48MRDY_POS 18U +#define CMU_CLKSR_HRC48MRDY_MSK BIT(CMU_CLKSR_HRC48MRDY_POS) + +#define CMU_CLKSR_HRC4MRDY_POS 17U +#define CMU_CLKSR_HRC4MRDY_MSK BIT(CMU_CLKSR_HRC4MRDY_POS) + +#define CMU_CLKSR_HOSCRDY_POS 16U +#define CMU_CLKSR_HOSCRDY_MSK BIT(CMU_CLKSR_HOSCRDY_POS) + +#define CMU_CLKSR_HRC48MACT_POS 3U +#define CMU_CLKSR_HRC48MACT_MSK BIT(CMU_CLKSR_HRC48MACT_POS) + +#define CMU_CLKSR_HRC4MACT_POS 2U +#define CMU_CLKSR_HRC4MACT_MSK BIT(CMU_CLKSR_HRC4MACT_POS) + +#define CMU_CLKSR_PLLACT_POS 1U +#define CMU_CLKSR_PLLACT_MSK BIT(CMU_CLKSR_PLLACT_POS) + +#define CMU_CLKSR_HOSCACT_POS 0U +#define CMU_CLKSR_HOSCACT_MSK BIT(CMU_CLKSR_HOSCACT_POS) + +/****************** Bit definition for CMU_PLLCFG register ************************/ + +#define CMU_PLLCFG_REFS_POSS 2U +#define CMU_PLLCFG_REFS_POSE 3U +#define CMU_PLLCFG_REFS_MSK BITS(CMU_PLLCFG_REFS_POSS,CMU_PLLCFG_REFS_POSE) + +#define CMU_PLLCFG_CLKOS_POSS 0U +#define CMU_PLLCFG_CLKOS_POSE 1U +#define CMU_PLLCFG_CLKOS_MSK BITS(CMU_PLLCFG_CLKOS_POSS,CMU_PLLCFG_CLKOS_POSE) + +/****************** Bit definition for CMU_HOSCCFG register ************************/ + +#define CMU_HOSCCFG_FREQ_POSS 0U +#define CMU_HOSCCFG_FREQ_POSE 2U +#define CMU_HOSCCFG_FREQ_MSK BITS(CMU_HOSCCFG_FREQ_POSS,CMU_HOSCCFG_FREQ_POSE) + +/****************** Bit definition for CMU_HOSMCR register ************************/ + +#define CMU_HOSMCR_NMIE_POS 20U +#define CMU_HOSMCR_NMIE_MSK BIT(CMU_HOSMCR_NMIE_POS) + +#define CMU_HOSMCR_STPIF_POS 19U +#define CMU_HOSMCR_STPIF_MSK BIT(CMU_HOSMCR_STPIF_POS) + +#define CMU_HOSMCR_STRIF_POS 18U +#define CMU_HOSMCR_STRIF_MSK BIT(CMU_HOSMCR_STRIF_POS) + +#define CMU_HOSMCR_STPIE_POS 17U +#define CMU_HOSMCR_STPIE_MSK BIT(CMU_HOSMCR_STPIE_POS) + +#define CMU_HOSMCR_STRIE_POS 16U +#define CMU_HOSMCR_STRIE_MSK BIT(CMU_HOSMCR_STRIE_POS) + +#define CMU_HOSMCR_FRQS_POSS 8U +#define CMU_HOSMCR_FRQS_POSE 10U +#define CMU_HOSMCR_FRQS_MSK BITS(CMU_HOSMCR_FRQS_POSS,CMU_HOSMCR_FRQS_POSE) + +#define CMU_HOSMCR_FLAG_POS 1U +#define CMU_HOSMCR_FLAG_MSK BIT(CMU_HOSMCR_FLAG_POS) + +#define CMU_HOSMCR_EN_POS 0U +#define CMU_HOSMCR_EN_MSK BIT(CMU_HOSMCR_EN_POS) + +/****************** Bit definition for CMU_PULMCR register ************************/ + +#define CMU_PULMCR_NMIE_POS 20U +#define CMU_PULMCR_NMIE_MSK BIT(CMU_PULMCR_NMIE_POS) + +#define CMU_PULMCR_ULKIF_POS 19U +#define CMU_PULMCR_ULKIF_MSK BIT(CMU_PULMCR_ULKIF_POS) + +#define CMU_PULMCR_LCKIF_POS 18U +#define CMU_PULMCR_LCKIF_MSK BIT(CMU_PULMCR_LCKIF_POS) + +#define CMU_PULMCR_ULKIE_POS 17U +#define CMU_PULMCR_ULKIE_MSK BIT(CMU_PULMCR_ULKIE_POS) + +#define CMU_PULMCR_LCKIE_POS 16U +#define CMU_PULMCR_LCKIE_MSK BIT(CMU_PULMCR_LCKIE_POS) + +#define CMU_PULMCR_MODE_POSS 8U +#define CMU_PULMCR_MODE_POSE 9U +#define CMU_PULMCR_MODE_MSK BITS(CMU_PULMCR_MODE_POSS,CMU_PULMCR_MODE_POSE) + +#define CMU_PULMCR_CLKS_POS 1U +#define CMU_PULMCR_CLKS_MSK BIT(CMU_PULMCR_CLKS_POS) + +#define CMU_PULMCR_EN_POS 0U +#define CMU_PULMCR_EN_MSK BIT(CMU_PULMCR_EN_POS) + +/****************** Bit definition for CMU_CLKOCR register ************************/ + +#define CMU_CLKOCR_LSCOS_POSS 24U +#define CMU_CLKOCR_LSCOS_POSE 25U +#define CMU_CLKOCR_LSCOS_MSK BITS(CMU_CLKOCR_LSCOS_POSS,CMU_CLKOCR_LSCOS_POSE) + +#define CMU_CLKOCR_LSCOEN_POS 16U +#define CMU_CLKOCR_LSCOEN_MSK BIT(CMU_CLKOCR_LSCOEN_POS) + +#define CMU_CLKOCR_HSCODIV_POSS 12U +#define CMU_CLKOCR_HSCODIV_POSE 14U +#define CMU_CLKOCR_HSCODIV_MSK BITS(CMU_CLKOCR_HSCODIV_POSS,CMU_CLKOCR_HSCODIV_POSE) + +#define CMU_CLKOCR_HSCOS_POSS 8U +#define CMU_CLKOCR_HSCOS_POSE 11U +#define CMU_CLKOCR_HSCOS_MSK BITS(CMU_CLKOCR_HSCOS_POSS,CMU_CLKOCR_HSCOS_POSE) + +#define CMU_CLKOCR_HSCOEN_POS 0U +#define CMU_CLKOCR_HSCOEN_MSK BIT(CMU_CLKOCR_HSCOEN_POS) + +/****************** Bit definition for CMU_BUZZCR register ************************/ + +#define CMU_BUZZCR_DAT_POSS 16U +#define CMU_BUZZCR_DAT_POSE 31U +#define CMU_BUZZCR_DAT_MSK BITS(CMU_BUZZCR_DAT_POSS,CMU_BUZZCR_DAT_POSE) + +#define CMU_BUZZCR_DIV_POSS 8U +#define CMU_BUZZCR_DIV_POSE 10U +#define CMU_BUZZCR_DIV_MSK BITS(CMU_BUZZCR_DIV_POSS,CMU_BUZZCR_DIV_POSE) + +#define CMU_BUZZCR_EN_POS 0U +#define CMU_BUZZCR_EN_MSK BIT(CMU_BUZZCR_EN_POS) + +/****************** Bit definition for CMU_AHBENR register ************************/ +#define CMU_AHBENR_CSUEN_POS 7U +#define CMU_AHBENR_CSUEN_MSK BIT(CMU_AHBENR_CSUEN_POS) + +#define CMU_AHBENR_USBEN_POS 6U +#define CMU_AHBENR_USBEN_MSK BIT(CMU_AHBENR_USBEN_POS) + +#define CMU_AHBENR_PISEN_POS 5U +#define CMU_AHBENR_PISEN_MSK BIT(CMU_AHBENR_PISEN_POS) + +#define CMU_AHBENR_DMAEN_POS 2U +#define CMU_AHBENR_DMAEN_MSK BIT(CMU_AHBENR_DMAEN_POS) + +#define CMU_AHBENR_CRCEN_POS 1U +#define CMU_AHBENR_CRCEN_MSK BIT(CMU_AHBENR_CRCEN_POS) + +#define CMU_AHBENR_GPIOEN_POS 0U +#define CMU_AHBENR_GPIOEN_MSK BIT(CMU_AHBENR_GPIOEN_POS) + +/****************** Bit definition for CMU_APBENR register ************************/ + +#define CMU_APBENR_ADCEN_POS 25U +#define CMU_APBENR_ADCEN_MSK BIT(CMU_APBENR_ADCEN_POS) + +#define CMU_APBENR_DBGCEN_POS 24U +#define CMU_APBENR_DBGCEN_MSK BIT(CMU_APBENR_DBGCEN_POS) + +#define CMU_APBENR_IWDTEN_POS 23U +#define CMU_APBENR_IWDTEN_MSK BIT(CMU_APBENR_IWDTEN_POS) + +#define CMU_APBENR_WWDTEN_POS 22U +#define CMU_APBENR_WWDTEN_MSK BIT(CMU_APBENR_WWDTEN_POS) + +#define CMU_APBENR_I2C1EN_POS 21U +#define CMU_APBENR_I2C1EN_MSK BIT(CMU_APBENR_I2C1EN_POS) + +#define CMU_APBENR_I2C0EN_POS 20U +#define CMU_APBENR_I2C0EN_MSK BIT(CMU_APBENR_I2C0EN_POS) + +#define CMU_APBENR_SPI1EN_POS 17U +#define CMU_APBENR_SPI1EN_MSK BIT(CMU_APBENR_SPI1EN_POS) + +#define CMU_APBENR_SPI0EN_POS 16U +#define CMU_APBENR_SPI0EN_MSK BIT(CMU_APBENR_SPI0EN_POS) + +#define CMU_APBENR_CUART2EN_POS 14U +#define CMU_APBENR_CUART2EN_MSK BIT(CMU_APBENR_CUART2EN_POS) + +#define CMU_APBENR_CUART1EN_POS 13U +#define CMU_APBENR_CUART1EN_MSK BIT(CMU_APBENR_CUART1EN_POS) + +#define CMU_APBENR_CUART0EN_POS 12U +#define CMU_APBENR_CUART0EN_MSK BIT(CMU_APBENR_CUART0EN_POS) + +#define CMU_APBENR_EUART1EN_POS 9U +#define CMU_APBENR_EUART1EN_MSK BIT(CMU_APBENR_EUART1EN_POS) + +#define CMU_APBENR_EUART0EN_POS 8U +#define CMU_APBENR_EUART0EN_MSK BIT(CMU_APBENR_EUART0EN_POS) + +#define CMU_APBENR_GP16C4T2EN_POS 4U +#define CMU_APBENR_GP16C4T2EN_MSK BIT(CMU_APBENR_GP16C4T2EN_POS) + +#define CMU_APBENR_GP16C4T1EN_POS 3U +#define CMU_APBENR_GP16C4T1EN_MSK BIT(CMU_APBENR_GP16C4T1EN_POS) + +#define CMU_APBENR_GP16C4T0EN_POS 2U +#define CMU_APBENR_GP16C4T0EN_MSK BIT(CMU_APBENR_GP16C4T0EN_POS) + +#define CMU_APBENR_BS16T0EN_POS 1U +#define CMU_APBENR_BS16T0EN_MSK BIT(CMU_APBENR_BS16T0EN_POS) + +#define CMU_APBENR_AD16C4T0EN_POS 0U +#define CMU_APBENR_AD16C4T0EN_MSK BIT(CMU_APBENR_AD16C4T0EN_POS) + +/****************** Bit definition for CMU_LPENR register ************************/ + +#define CMU_LPENR_HOSCEN_POS 3U +#define CMU_LPENR_HOSCEN_MSK BIT(CMU_LPENR_HOSCEN_POS) + +#define CMU_LPENR_HRC48MEN_POS 2U +#define CMU_LPENR_HRC48MEN_MSK BIT(CMU_LPENR_HRC48MEN_POS) + +#define CMU_LPENR_HRC4MEN_POS 1U +#define CMU_LPENR_HRC4MEN_MSK BIT(CMU_LPENR_HRC4MEN_POS) + +#define CMU_LPENR_PLLEN_POS 0U +#define CMU_LPENR_PLLEN_MSK BIT(CMU_LPENR_PLLEN_POS) + +/* Exported Types ------------------------------------------------------------ */ + +typedef struct +{ + __O uint32_t CSR; + __IO uint32_t CFGR; + uint32_t RESERVED0[2] ; + __IO uint32_t CLKENR; + __I uint32_t CLKSR; + __IO uint32_t PLLCFG; + __IO uint32_t HOSCCFG; + __IO uint32_t HOSMCR; + uint32_t RESERVED1[1] ; + __IO uint32_t PULMCR; + uint32_t RESERVED2[1] ; + __IO uint32_t CLKOCR; + __IO uint32_t BUZZCR; + uint32_t RESERVED3[2] ; + __IO uint32_t AHBENR; + uint32_t RESERVED4[3] ; + __IO uint32_t APBENR; + uint32_t RESERVED5[3] ; + __IO uint32_t LPENR; +} CMU_TypeDef; + +#endif /*__REG_CMU_H__*/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_crc.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_crc.h new file mode 100644 index 0000000000..a3ad55b948 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_crc.h @@ -0,0 +1,109 @@ +/********************************************************************************** + * + * @file reg_crc.h + * @brief CRC Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_CRC_H__ +#define __REG_CRC_H__ + +/* Includes ------------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ +/* Exported Macros ----------------------------------------------------------- */ + +/****************** Bit definition for CRC_CR register ************************/ + +#define CRC_CR_BYTORD_POS 24U +#define CRC_CR_BYTORD_MSK BIT(CRC_CR_BYTORD_POS) + +#define CRC_CR_DATLEN_POSS 22U +#define CRC_CR_DATLEN_POSE 23U +#define CRC_CR_DATLEN_MSK BITS(CRC_CR_DATLEN_POSS,CRC_CR_DATLEN_POSE) + +#define CRC_CR_MODE_POSS 20U +#define CRC_CR_MODE_POSE 21U +#define CRC_CR_MODE_MSK BITS(CRC_CR_MODE_POSS,CRC_CR_MODE_POSE) + +#define CRC_CR_CHSINV_POS 19U +#define CRC_CR_CHSINV_MSK BIT(CRC_CR_CHSINV_POS) + +#define CRC_CR_DATINV_POS 18U +#define CRC_CR_DATINV_MSK BIT(CRC_CR_DATINV_POS) + +#define CRC_CR_CHSREV_POS 17U +#define CRC_CR_CHSREV_MSK BIT(CRC_CR_CHSREV_POS) + +#define CRC_CR_DATREV_POS 16U +#define CRC_CR_DATREV_MSK BIT(CRC_CR_DATREV_POS) + +#define CRC_CR_DMAEN_POS 4U +#define CRC_CR_DMAEN_MSK BIT(CRC_CR_DMAEN_POS) + +#define CRC_CR_CWERR_POS 3U +#define CRC_CR_CWERR_MSK BIT(CRC_CR_CWERR_POS) + +#define CRC_CR_WERR_POS 2U +#define CRC_CR_WERR_MSK BIT(CRC_CR_WERR_POS) + +#define CRC_CR_RST_POS 1U +#define CRC_CR_RST_MSK BIT(CRC_CR_RST_POS) + +#define CRC_CR_EN_POS 0U +#define CRC_CR_EN_MSK BIT(CRC_CR_EN_POS) + +/****************** Bit definition for CRC_DATA register ************************/ + +#define CRC_DATA_DATA_POSS 0U +#define CRC_DATA_DATA_POSE 31U +#define CRC_DATA_DATA_MSK BITS(CRC_DATA_DATA_POSS,CRC_DATA_DATA_POSE) + +/****************** Bit definition for CRC_SEED register ************************/ + +#define CRC_SEED_SEED_POSS 0U +#define CRC_SEED_SEED_POSE 31U +#define CRC_SEED_SEED_MSK BITS(CRC_SEED_SEED_POSS,CRC_SEED_SEED_POSE) + +/****************** Bit definition for CRC_CHECKSUM register ************************/ + +#define CRC_CHECKSUM_CHECKSUM_POSS 0U +#define CRC_CHECKSUM_CHECKSUM_POSE 31U +#define CRC_CHECKSUM_CHECKSUM_MSK BITS(CRC_CHECKSUM_CHECKSUM_POSS,CRC_CHECKSUM_CHECKSUM_POSE) + +/* Exported Types ------------------------------------------------------------ */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t DATA; + __IO uint32_t SEED; + __I uint32_t CHECKSUM; +} CRC_TypeDef; + +#endif /* __REG_CRC_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_csu.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_csu.h new file mode 100644 index 0000000000..5e96c80a72 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_csu.h @@ -0,0 +1,229 @@ +/********************************************************************************** + * + * @file reg_csu.h + * @brief CSU Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_CSU_H__ +#define __REG_CSU_H__ + +/* Includes ------------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ +/* Exported Macros ----------------------------------------------------------- */ + +/****************** Bit definition for CSU_CON register ************************/ + +#define CSU_CON_TRIM_POSS 8U +#define CSU_CON_TRIM_POSE 16U +#define CSU_CON_TRIM_MSK BITS(CSU_CON_TRIM_POSS,CSU_CON_TRIM_POSE) + +#define CSU_CON_SYNCGEN_POS 2U +#define CSU_CON_SYNCGEN_MSK BIT(CSU_CON_SYNCGEN_POS) + +#define CSU_CON_AUTOEN_POS 1U +#define CSU_CON_AUTOEN_MSK BIT(CSU_CON_AUTOEN_POS) + +#define CSU_CON_CNTEN_POS 0U +#define CSU_CON_CNTEN_MSK BIT(CSU_CON_CNTEN_POS) + +/****************** Bit definition for CSU_CFG register ************************/ + +#define CSU_CFG_TRIMSEL_POS 31U +#define CSU_CFG_TRIMSEL_MSK BIT(CSU_CFG_TRIMSEL_POS) + +#define CSU_CFG_POLSEL_POS 30U +#define CSU_CFG_POLSEL_MSK BIT(CSU_CFG_POLSEL_POS) + +#define CSU_CFG_SYNCSRC_POSS 28U +#define CSU_CFG_SYNCSRC_POSE 29U +#define CSU_CFG_SYNCSRC_MSK BITS(CSU_CFG_SYNCSRC_POSS,CSU_CFG_SYNCSRC_POSE) + +#define CSU_CFG_SYNCDIV_POSS 24U +#define CSU_CFG_SYNCDIV_POSE 26U +#define CSU_CFG_SYNCDIV_MSK BITS(CSU_CFG_SYNCDIV_POSS,CSU_CFG_SYNCDIV_POSE) + +#define CSU_CFG_CNTTH_POSS 16U +#define CSU_CFG_CNTTH_POSE 23U +#define CSU_CFG_CNTTH_MSK BITS(CSU_CFG_CNTTH_POSS,CSU_CFG_CNTTH_POSE) + +#define CSU_CFG_RELOAD_POSS 0U +#define CSU_CFG_RELOAD_POSE 15U +#define CSU_CFG_RELOAD_MSK BITS(CSU_CFG_RELOAD_POSS,CSU_CFG_RELOAD_POSE) + +/****************** Bit definition for CSU_STAT register ************************/ + +#define CSU_STAT_OPT_TRIM_POSS 23U +#define CSU_STAT_OPT_TRIM_POSE 31U +#define CSU_STAT_OPT_TRIM_MSK BITS(CSU_STAT_OPT_TRIM_POSS,CSU_STAT_OPT_TRIM_POSE) + +#define CSU_STAT_CNTDIR_POS 16U +#define CSU_STAT_CNTDIR_MSK BIT(CSU_STAT_CNTDIR_POS) + +#define CSU_STAT_CNTCAP_POSS 0U +#define CSU_STAT_CNTCAP_POSE 15U +#define CSU_STAT_CNTCAP_MSK BITS(CSU_STAT_CNTCAP_POSS,CSU_STAT_CNTCAP_POSE) + +/****************** Bit definition for CSU_IER register ************************/ + +#define CSU_IER_FHIT_POS 5U +#define CSU_IER_FHIT_MSK BIT(CSU_IER_FHIT_POS) + +#define CSU_IER_TRIMERR_POS 4U +#define CSU_IER_TRIMERR_MSK BIT(CSU_IER_TRIMERR_POS) + +#define CSU_IER_FFAULT_POS 3U +#define CSU_IER_FFAULT_MSK BIT(CSU_IER_FFAULT_POS) + +#define CSU_IER_FERROR_POS 2U +#define CSU_IER_FERROR_MSK BIT(CSU_IER_FERROR_POS) + +#define CSU_IER_FWARN_POS 1U +#define CSU_IER_FWARN_MSK BIT(CSU_IER_FWARN_POS) + +#define CSU_IER_FMATCH_POS 0U +#define CSU_IER_FMATCH_MSK BIT(CSU_IER_FMATCH_POS) + +/****************** Bit definition for CSU_IDR register ************************/ + +#define CSU_IDR_FHIT_POS 5U +#define CSU_IDR_FHIT_MSK BIT(CSU_IDR_FHIT_POS) + +#define CSU_IDR_TRIMERR_POS 4U +#define CSU_IDR_TRIMERR_MSK BIT(CSU_IDR_TRIMERR_POS) + +#define CSU_IDR_FFAULT_POS 3U +#define CSU_IDR_FFAULT_MSK BIT(CSU_IDR_FFAULT_POS) + +#define CSU_IDR_FERROR_POS 2U +#define CSU_IDR_FERROR_MSK BIT(CSU_IDR_FERROR_POS) + +#define CSU_IDR_FWARN_POS 1U +#define CSU_IDR_FWARN_MSK BIT(CSU_IDR_FWARN_POS) + +#define CSU_IDR_FMATCH_POS 0U +#define CSU_IDR_FMATCH_MSK BIT(CSU_IDR_FMATCH_POS) + +/****************** Bit definition for CSU_IVS register ************************/ + +#define CSU_IVS_FHIT_POS 5U +#define CSU_IVS_FHIT_MSK BIT(CSU_IVS_FHIT_POS) + +#define CSU_IVS_TRIMERR_POS 4U +#define CSU_IVS_TRIMERR_MSK BIT(CSU_IVS_TRIMERR_POS) + +#define CSU_IVS_FFAULT_POS 3U +#define CSU_IVS_FFAULT_MSK BIT(CSU_IVS_FFAULT_POS) + +#define CSU_IVS_FERROR_POS 2U +#define CSU_IVS_FERROR_MSK BIT(CSU_IVS_FERROR_POS) + +#define CSU_IVS_FWARN_POS 1U +#define CSU_IVS_FWARN_MSK BIT(CSU_IVS_FWARN_POS) + +#define CSU_IVS_FMATCH_POS 0U +#define CSU_IVS_FMATCH_MSK BIT(CSU_IVS_FMATCH_POS) + +/****************** Bit definition for CSU_RIF register ************************/ + +#define CSU_RIF_FHIT_POS 5U +#define CSU_RIF_FHIT_MSK BIT(CSU_RIF_FHIT_POS) + +#define CSU_RIF_TRIMERR_POS 4U +#define CSU_RIF_TRIMERR_MSK BIT(CSU_RIF_TRIMERR_POS) + +#define CSU_RIF_FFAULT_POS 3U +#define CSU_RIF_FFAULT_MSK BIT(CSU_RIF_FFAULT_POS) + +#define CSU_RIF_FERROR_POS 2U +#define CSU_RIF_FERROR_MSK BIT(CSU_RIF_FERROR_POS) + +#define CSU_RIF_FWARN_POS 1U +#define CSU_RIF_FWARN_MSK BIT(CSU_RIF_FWARN_POS) + +#define CSU_RIF_FMATCH_POS 0U +#define CSU_RIF_FMATCH_MSK BIT(CSU_RIF_FMATCH_POS) + +/****************** Bit definition for CSU_IFM register ************************/ + +#define CSU_IFM_FHIT_POS 5U +#define CSU_IFM_FHIT_MSK BIT(CSU_IFM_FHIT_POS) + +#define CSU_IFM_TRIMERR_POS 4U +#define CSU_IFM_TRIMERR_MSK BIT(CSU_IFM_TRIMERR_POS) + +#define CSU_IFM_FFAULT_POS 3U +#define CSU_IFM_FFAULT_MSK BIT(CSU_IFM_FFAULT_POS) + +#define CSU_IFM_FERROR_POS 2U +#define CSU_IFM_FERROR_MSK BIT(CSU_IFM_FERROR_POS) + +#define CSU_IFM_FWARN_POS 1U +#define CSU_IFM_FWARN_MSK BIT(CSU_IFM_FWARN_POS) + +#define CSU_IFM_FMATCH_POS 0U +#define CSU_IFM_FMATCH_MSK BIT(CSU_IFM_FMATCH_POS) + +/****************** Bit definition for CSU_ICR register ************************/ + +#define CSU_ICR_FHIT_POS 5U +#define CSU_ICR_FHIT_MSK BIT(CSU_ICR_FHIT_POS) + +#define CSU_ICR_TRIMERR_POS 4U +#define CSU_ICR_TRIMERR_MSK BIT(CSU_ICR_TRIMERR_POS) + +#define CSU_ICR_FFAULT_POS 3U +#define CSU_ICR_FFAULT_MSK BIT(CSU_ICR_FFAULT_POS) + +#define CSU_ICR_FERROR_POS 2U +#define CSU_ICR_FERROR_MSK BIT(CSU_ICR_FERROR_POS) + +#define CSU_ICR_FWARN_POS 1U +#define CSU_ICR_FWARN_MSK BIT(CSU_ICR_FWARN_POS) + +#define CSU_ICR_FMATCH_POS 0U +#define CSU_ICR_FMATCH_MSK BIT(CSU_ICR_FMATCH_POS) + +/* Exported Types ------------------------------------------------------------ */ + +typedef struct +{ + __IO uint32_t CON; + __IO uint32_t CFG; + __I uint32_t STAT; + uint32_t RESERVED0 ; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} CSU_TypeDef; + +#endif /* __REG_CSU_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_dbg.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_dbg.h new file mode 100644 index 0000000000..f7cb287481 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_dbg.h @@ -0,0 +1,95 @@ +/********************************************************************************** + * + * @file reg_dbg.h + * @brief DBG Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_DBG_H__ +#define __REG_DBG_H__ + +/* Includes ------------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ +/* Exported Macros ----------------------------------------------------------- */ + +/****************** Bit definition for DBGC_IDCODE register ************************/ + +#define DBGC_IDCODE_REV_ID_POSS 16U +#define DBGC_IDCODE_REV_ID_POSE 31U +#define DBGC_IDCODE_REV_ID_MSK BITS(DBGC_IDCODE_REV_ID_POSS,DBGC_IDCODE_REV_ID_POSE) + +#define DBGC_IDCODE_CORE_ID_POSS 12U +#define DBGC_IDCODE_CORE_ID_POSE 15U +#define DBGC_IDCODE_CORE_ID_MSK BITS(DBGC_IDCODE_CORE_ID_POSS,DBGC_IDCODE_CORE_ID_POSE) + +#define DBGC_IDCODE_DEV_ID_POSS 0U +#define DBGC_IDCODE_DEV_ID_POSE 11U +#define DBGC_IDCODE_DEV_ID_MSK BITS(DBGC_IDCODE_DEV_ID_POSS,DBGC_IDCODE_DEV_ID_POSE) + +/****************** Bit definition for DBGC_APB1FZ register ************************/ + +#define DBGC_APB1FZ_GP16C2T2_STOP_POS 4U +#define DBGC_APB1FZ_GP16C2T2_STOP_MSK BIT(DBGC_APB1FZ_GP16C2T2_STOP_POS) + +#define DBGC_APB1FZ_GP16C2T1_STOP_POS 3U +#define DBGC_APB1FZ_GP16C2T1_STOP_MSK BIT(DBGC_APB1FZ_GP16C2T1_STOP_POS) + +#define DBGC_APB1FZ_GP16C2T0_STOP_POS 2U +#define DBGC_APB1FZ_GP16C2T0_STOP_MSK BIT(DBGC_APB1FZ_GP16C2T0_STOP_POS) + +#define DBGC_APB1FZ_BS16T0_STOP_POS 1U +#define DBGC_APB1FZ_BS16T0_STOP_MSK BIT(DBGC_APB1FZ_BS16T0_STOP_POS) + +#define DBGC_APB1FZ_AD16C4T0_STOP_POS 0U +#define DBGC_APB1FZ_AD16C4T0_STOP_MSK BIT(DBGC_APB1FZ_AD16C4T0_STOP_POS) + +/****************** Bit definition for DBGC_APB2FZ register ************************/ + +#define DBGC_APB2FZ_WWDT_STOP_POS 9U +#define DBGC_APB2FZ_WWDT_STOP_MSK BIT(DBGC_APB2FZ_WWDT_STOP_POS) + +#define DBGC_APB2FZ_IWDT_STOP_POS 8U +#define DBGC_APB2FZ_IWDT_STOP_MSK BIT(DBGC_APB2FZ_IWDT_STOP_POS) + +#define DBGC_APB2FZ_I2C0_STOP_POS 0U +#define DBGC_APB2FZ_I2C0_STOP_MSK BIT(DBGC_APB2FZ_I2C0_STOP_POS) + +/* Exported Types ------------------------------------------------------------ */ + +typedef struct +{ + __I uint32_t IDCODE; + uint32_t RESERVED0 ; + __IO uint32_t APB1FZ; + __IO uint32_t APB2FZ; +} DBGC_TypeDef; + +#endif /* __REG_DBG_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_dma.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_dma.h new file mode 100644 index 0000000000..4b28d711ab --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_dma.h @@ -0,0 +1,156 @@ +/********************************************************************************** + * + * @file reg_dma.h + * @brief DMA Head File + * + * @date 19 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 12 July 2022 Lisq the first version + * 19 July 2022 Shiwa the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_DMA_H__ +#define __REG_DMA_H__ + +/* Includes ------------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ +/* Exported Macros ----------------------------------------------------------- */ + +#define DMA_CHANNELS 7 + +#define DMA_CH0_TC_POS 0U +#define DMA_CH0_TC_MSK BIT(DMA_CH0_TC_POS) +#define DMA_CH0_HT_POS 1U +#define DMA_CH0_HT_MSK BIT(DMA_CH0_HT_POS) + +#define DMA_CH1_TC_POS 2U +#define DMA_CH1_TC_MSK BIT(DMA_CH1_TC_POS) +#define DMA_CH1_HT_POS 3U +#define DMA_CH1_HT_MSK BIT(DMA_CH1_HT_POS) + +#define DMA_CH2_TC_POS 4U +#define DMA_CH2_TC_MSK BIT(DMA_CH2_TC_POS) +#define DMA_CH2_HT_POS 5U +#define DMA_CH2_HT_MSK BIT(DMA_CH2_HT_POS) + +#define DMA_CH3_TC_POS 6U +#define DMA_CH3_TC_MSK BIT(DMA_CH3_TC_POS) +#define DMA_CH3_HT_POS 7U +#define DMA_CH3_HT_MSK BIT(DMA_CH3_HT_POS) + +#define DMA_CH4_TC_POS 8U +#define DMA_CH4_TC_MSK BIT(DMA_CH4_TC_POS) +#define DMA_CH4_HT_POS 9U +#define DMA_CH4_HT_MSK BIT(DMA_CH4_HT_POS) + +#define DMA_CH5_TC_POS 10U +#define DMA_CH5_TC_MSK BIT(DMA_CH5_TC_POS) +#define DMA_CH5_HT_POS 11U +#define DMA_CH5_HT_MSK BIT(DMA_CH5_HT_POS) + +#define DMA_CH6_TC_POS 12U +#define DMA_CH6_TC_MSK BIT(DMA_CH6_TC_POS) +#define DMA_CH6_HT_POS 13U +#define DMA_CH6_HT_MSK BIT(DMA_CH6_HT_POS) + +#define DMA_SELCON_MSEL_POSS 8U +#define DMA_SELCON_MSEL_POSE 12U +#define DMA_SELCON_MSEL_MSK BITS(DMA_SELCON_MSEL_POSS,DMA_SELCON_MSEL_POSE) + +#define DMA_SELCON_MSIGSEL_POSS 0U +#define DMA_SELCON_MSIGSEL_POSE 3U +#define DMA_SELCON_MSIGSEL_MSK BITS(DMA_SELCON_MSIGSEL_POSS,DMA_SELCON_MSIGSEL_POSE) + +#define DMA_CON_MAX_BURST_POSS 16U +#define DMA_CON_MAX_BURST_POSE 19U +#define DMA_CON_MAX_BURST_MSK BITS(DMA_CON_MAX_BURST_POSS,DMA_CON_MAX_BURST_POSE) + +#define DMA_CON_DDWSEL_POSS 13U +#define DMA_CON_DDWSEL_POSE 14U +#define DMA_CON_DDWSEL_MSK BITS(DMA_CON_DDWSEL_POSS,DMA_CON_DDWSEL_POSE) + +#define DMA_CON_DINC_POS 12U +#define DMA_CON_DINC_MSK BIT(DMA_CON_DINC_POS) + +#define DMA_CON_SDWSEL_POSS 9U +#define DMA_CON_SDWSEL_POSE 10U +#define DMA_CON_SDWSEL_MSK BITS(DMA_CON_SDWSEL_POSS,DMA_CON_SDWSEL_POSE) + +#define DMA_CON_SINC_POS 8U +#define DMA_CON_SINC_MSK BIT(DMA_CON_SINC_POS) + +#define DMA_CON_CHPRI_POSS 4U +#define DMA_CON_CHPRI_POSE 5U +#define DMA_CON_CHPRI_MSK BITS(DMA_CON_CHPRI_POSS,DMA_CON_CHPRI_POSE) + +#define DMA_CON_M2M_POS 3U +#define DMA_CON_M2M_MSK BIT(DMA_CON_M2M_POS) + +#define DMA_CON_DIR_POS 2U +#define DMA_CON_DIR_MSK BIT(DMA_CON_DIR_POS) + +#define DMA_CON_CIRC_POS 1U +#define DMA_CON_CIRC_MSK BIT(DMA_CON_CIRC_POS) + +#define DMA_CON_CHEN_POS 0U +#define DMA_CON_CHEN_MSK BIT(DMA_CON_CHEN_POS) + +#define DMA_NDT_NRDT_POSS 16U +#define DMA_NDT_NRDT_POSE 31U +#define DMA_NDT_NRDT_MSK BITS(DMA_NDT_NRDT_POSS,DMA_NDT_NRDT_POSE) + +#define DMA_NDT_TNDT_POSS 0U +#define DMA_NDT_TNDT_POSE 15U +#define DMA_NDT_TNDT_MSK BITS(DMA_NDT_TNDT_POSS,DMA_NDT_TNDT_POSE) + +/* Exported Types ------------------------------------------------------------ */ + +typedef struct +{ + __IO uint32_t CON; + __IO uint32_t SAR; + __IO uint32_t DAR; + __IO uint32_t NDT; +} DMA_CHANNEL_Typedef; + +typedef struct +{ + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; + __I uint32_t RESERVED[2]; + DMA_CHANNEL_Typedef CHANNEL[DMA_CHANNELS]; +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CH_SELCON[DMA_CHANNELS]; +} DMA_MUX_Typedef; + +#endif /* __REG_DMA_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_gpio.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_gpio.h new file mode 100644 index 0000000000..00f6c70b25 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_gpio.h @@ -0,0 +1,338 @@ +/********************************************************************************** + * + * @file reg_gpio.h + * @brief gpio Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_GPIO_H__ +#define __REG_GPIO_H__ + +/* Includes ------------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ +/* Exported Macros ----------------------------------------------------------- */ + +/****************** Bit definition for GPIO_DIN register ************************/ + +#define GPIO_DIN_DIN_POSS 0U +#define GPIO_DIN_DIN_POSE 15U +#define GPIO_DIN_DIN_MSK BITS(GPIO_DIN_DIN_POSS,GPIO_DIN_DIN_POSE) + +/****************** Bit definition for GPIO_DOUT register ************************/ + +#define GPIO_DOUT_DOUT_POSS 0U +#define GPIO_DOUT_DOUT_POSE 15U +#define GPIO_DOUT_DOUT_MSK BITS(GPIO_DOUT_DOUT_POSS,GPIO_DOUT_DOUT_POSE) + +/****************** Bit definition for GPIO_BSRR register ************************/ + +#define GPIO_BSRR_BRR_POSS 16U +#define GPIO_BSRR_BRR_POSE 31U +#define GPIO_BSRR_BRR_MSK BITS(GPIO_BSRR_BRR_POSS,GPIO_BSRR_BRR_POSE) + +#define GPIO_BSRR_BSR_POSS 0U +#define GPIO_BSRR_BSR_POSE 15U +#define GPIO_BSRR_BSR_MSK BITS(GPIO_BSRR_BSR_POSS,GPIO_BSRR_BSR_POSE) + +/****************** Bit definition for GPIO_BIR register ************************/ + +#define GPIO_BIR_BIR_POSS 0U +#define GPIO_BIR_BIR_POSE 15U +#define GPIO_BIR_BIR_MSK BITS(GPIO_BIR_BIR_POSS,GPIO_BIR_BIR_POSE) + +/****************** Bit definition for GPIO_MODE register ************************/ + +#define GPIO_MODE_MODE_POSS 0U +#define GPIO_MODE_MODE_POSE 31U +#define GPIO_MODE_MODE_MSK BITS(GPIO_MODE_MODE_POSS,GPIO_MODE_MODE_POSE) + +/****************** Bit definition for GPIO_OD register ************************/ + +#define GPIO_OD_OD_POSS 0U +#define GPIO_OD_OD_POSE 31U +#define GPIO_OD_OD_MSK BITS(GPIO_OD_OD_POSS,GPIO_OD_OD_POSE) + +/****************** Bit definition for GPIO_PUPD register ************************/ + +#define GPIO_PUPD_PUPD_POSS 0U +#define GPIO_PUPD_PUPD_POSE 31U +#define GPIO_PUPD_PUPD_MSK BITS(GPIO_PUPD_PUPD_POSS,GPIO_PUPD_PUPD_POSE) + +/****************** Bit definition for GPIO_ODRV register ************************/ + +#define GPIO_ODRV_ODRV_POSS 0U +#define GPIO_ODRV_ODRV_POSE 31U +#define GPIO_ODRV_ODRV_MSK BITS(GPIO_ODRV_ODRV_POSS,GPIO_ODRV_ODRV_POSE) + +/****************** Bit definition for GPIO_FLT register ************************/ + +#define GPIO_FLT_FLT_POSS 0U +#define GPIO_FLT_FLT_POSE 15U +#define GPIO_FLT_FLT_MSK BITS(GPIO_FLT_FLT_POSS,GPIO_FLT_FLT_POSE) + +/****************** Bit definition for GPIO_TYPE register ************************/ + +#define GPIO_TYPE_TYPE_POSS 0U +#define GPIO_TYPE_TYPE_POSE 15U +#define GPIO_TYPE_TYPE_MSK BITS(GPIO_TYPE_TYPE_POSS,GPIO_TYPE_TYPE_POSE) + +/****************** Bit definition for GPIO_FUNC0 register ************************/ + +#define GPIO_FUNC0_FSEL_IO7_POSS 28U +#define GPIO_FUNC0_FSEL_IO7_POSE 31U +#define GPIO_FUNC0_FSEL_IO7_MSK BITS(GPIO_FUNC0_FSEL_IO7_POSS,GPIO_FUNC0_FSEL_IO7_POSE) + +#define GPIO_FUNC0_FSEL_IO6_POSS 24U +#define GPIO_FUNC0_FSEL_IO6_POSE 27U +#define GPIO_FUNC0_FSEL_IO6_MSK BITS(GPIO_FUNC0_FSEL_IO6_POSS,GPIO_FUNC0_FSEL_IO6_POSE) + +#define GPIO_FUNC0_FSEL_IO5_POSS 20U +#define GPIO_FUNC0_FSEL_IO5_POSE 23U +#define GPIO_FUNC0_FSEL_IO5_MSK BITS(GPIO_FUNC0_FSEL_IO5_POSS,GPIO_FUNC0_FSEL_IO5_POSE) + +#define GPIO_FUNC0_FSEL_IO4_POSS 16U +#define GPIO_FUNC0_FSEL_IO4_POSE 19U +#define GPIO_FUNC0_FSEL_IO4_MSK BITS(GPIO_FUNC0_FSEL_IO4_POSS,GPIO_FUNC0_FSEL_IO4_POSE) + +#define GPIO_FUNC0_FSEL_IO3_POSS 12U +#define GPIO_FUNC0_FSEL_IO3_POSE 15U +#define GPIO_FUNC0_FSEL_IO3_MSK BITS(GPIO_FUNC0_FSEL_IO3_POSS,GPIO_FUNC0_FSEL_IO3_POSE) + +#define GPIO_FUNC0_FSEL_IO2_POSS 8U +#define GPIO_FUNC0_FSEL_IO2_POSE 11U +#define GPIO_FUNC0_FSEL_IO2_MSK BITS(GPIO_FUNC0_FSEL_IO2_POSS,GPIO_FUNC0_FSEL_IO2_POSE) + +#define GPIO_FUNC0_FSEL_IO1_POSS 4U +#define GPIO_FUNC0_FSEL_IO1_POSE 7U +#define GPIO_FUNC0_FSEL_IO1_MSK BITS(GPIO_FUNC0_FSEL_IO1_POSS,GPIO_FUNC0_FSEL_IO1_POSE) + +#define GPIO_FUNC0_FSEL_IO0_POSS 0U +#define GPIO_FUNC0_FSEL_IO0_POSE 3U +#define GPIO_FUNC0_FSEL_IO0_MSK BITS(GPIO_FUNC0_FSEL_IO0_POSS,GPIO_FUNC0_FSEL_IO0_POSE) + +/****************** Bit definition for GPIO_FUNC1 register ************************/ + +#define GPIO_FUNC1_FSEL_IO15_POSS 28U +#define GPIO_FUNC1_FSEL_IO15_POSE 31U +#define GPIO_FUNC1_FSEL_IO15_MSK BITS(GPIO_FUNC1_FSEL_IO15_POSS,GPIO_FUNC1_FSEL_IO15_POSE) + +#define GPIO_FUNC1_FSEL_IO14_POSS 24U +#define GPIO_FUNC1_FSEL_IO14_POSE 27U +#define GPIO_FUNC1_FSEL_IO14_MSK BITS(GPIO_FUNC1_FSEL_IO14_POSS,GPIO_FUNC1_FSEL_IO14_POSE) + +#define GPIO_FUNC1_FSEL_IO13_POSS 20U +#define GPIO_FUNC1_FSEL_IO13_POSE 23U +#define GPIO_FUNC1_FSEL_IO13_MSK BITS(GPIO_FUNC1_FSEL_IO13_POSS,GPIO_FUNC1_FSEL_IO13_POSE) + +#define GPIO_FUNC1_FSEL_IO12_POSS 16U +#define GPIO_FUNC1_FSEL_IO12_POSE 19U +#define GPIO_FUNC1_FSEL_IO12_MSK BITS(GPIO_FUNC1_FSEL_IO12_POSS,GPIO_FUNC1_FSEL_IO12_POSE) + +#define GPIO_FUNC1_FSEL_IO11_POSS 12U +#define GPIO_FUNC1_FSEL_IO11_POSE 15U +#define GPIO_FUNC1_FSEL_IO11_MSK BITS(GPIO_FUNC1_FSEL_IO11_POSS,GPIO_FUNC1_FSEL_IO11_POSE) + +#define GPIO_FUNC1_FSEL_IO10_POSS 8U +#define GPIO_FUNC1_FSEL_IO10_POSE 11U +#define GPIO_FUNC1_FSEL_IO10_MSK BITS(GPIO_FUNC1_FSEL_IO10_POSS,GPIO_FUNC1_FSEL_IO10_POSE) + +#define GPIO_FUNC1_FSEL_IO9_POSS 4U +#define GPIO_FUNC1_FSEL_IO9_POSE 7U +#define GPIO_FUNC1_FSEL_IO9_MSK BITS(GPIO_FUNC1_FSEL_IO9_POSS,GPIO_FUNC1_FSEL_IO9_POSE) + +#define GPIO_FUNC1_FSEL_IO8_POSS 0U +#define GPIO_FUNC1_FSEL_IO8_POSE 3U +#define GPIO_FUNC1_FSEL_IO8_MSK BITS(GPIO_FUNC1_FSEL_IO8_POSS,GPIO_FUNC1_FSEL_IO8_POSE) + +/****************** Bit definition for GPIO_LOCK register ************************/ + +#define GPIO_LOCK_KEY_POSS 16U +#define GPIO_LOCK_KEY_POSE 31U +#define GPIO_LOCK_KEY_MSK BITS(GPIO_LOCK_KEY_POSS,GPIO_LOCK_KEY_POSE) + +#define GPIO_LOCK_LOCK_POSS 0U +#define GPIO_LOCK_LOCK_POSE 15U +#define GPIO_LOCK_LOCK_MSK BITS(GPIO_LOCK_LOCK_POSS,GPIO_LOCK_LOCK_POSE) + +/****************** Bit definition for GPIO_EXTIRER register ************************/ + +#define GPIO_EXTIRER_EXTIRER_POSS 0U +#define GPIO_EXTIRER_EXTIRER_POSE 15U +#define GPIO_EXTIRER_EXTIRER_MSK BITS(GPIO_EXTIRER_EXTIRER_POSS,GPIO_EXTIRER_EXTIRER_POSE) + +/****************** Bit definition for GPIO_EXTIFER register ************************/ + +#define GPIO_EXTIFER_EXTIFER_POSS 0U +#define GPIO_EXTIFER_EXTIFER_POSE 15U +#define GPIO_EXTIFER_EXTIFER_MSK BITS(GPIO_EXTIFER_EXTIFER_POSS,GPIO_EXTIFER_EXTIFER_POSE) + +/****************** Bit definition for GPIO_EXTIEN register ************************/ + +#define GPIO_EXTIEN_EXTIEN_POSS 0U +#define GPIO_EXTIEN_EXTIEN_POSE 15U +#define GPIO_EXTIEN_EXTIEN_MSK BITS(GPIO_EXTIEN_EXTIEN_POSS,GPIO_EXTIEN_EXTIEN_POSE) + +/****************** Bit definition for GPIO_EXTIFLAG register ************************/ + +#define GPIO_EXTIFLAG_EXTIFLAG_POSS 0U +#define GPIO_EXTIFLAG_EXTIFLAG_POSE 15U +#define GPIO_EXTIFLAG_EXTIFLAG_MSK BITS(GPIO_EXTIFLAG_EXTIFLAG_POSS,GPIO_EXTIFLAG_EXTIFLAG_POSE) + +/****************** Bit definition for GPIO_EXTISFR register ************************/ + +#define GPIO_EXTISFR_EXTISFR_POSS 0U +#define GPIO_EXTISFR_EXTISFR_POSE 15U +#define GPIO_EXTISFR_EXTISFR_MSK BITS(GPIO_EXTISFR_EXTISFR_POSS,GPIO_EXTISFR_EXTISFR_POSE) + +/****************** Bit definition for GPIO_EXTICFR register ************************/ + +#define GPIO_EXTICFR_EXTICFR_POSS 0U +#define GPIO_EXTICFR_EXTICFR_POSE 15U +#define GPIO_EXTICFR_EXTICFR_MSK BITS(GPIO_EXTICFR_EXTICFR_POSS,GPIO_EXTICFR_EXTICFR_POSE) + +/****************** Bit definition for GPIO_EXTIPSR0 register ************************/ + +#define GPIO_EXTIPSR0_EXTIS7_POSS 28U +#define GPIO_EXTIPSR0_EXTIS7_POSE 31U +#define GPIO_EXTIPSR0_EXTIS7_MSK BITS(GPIO_EXTIPSR0_EXTIS7_POSS,GPIO_EXTIPSR0_EXTIS7_POSE) + +#define GPIO_EXTIPSR0_EXTIS6_POSS 24U +#define GPIO_EXTIPSR0_EXTIS6_POSE 27U +#define GPIO_EXTIPSR0_EXTIS6_MSK BITS(GPIO_EXTIPSR0_EXTIS6_POSS,GPIO_EXTIPSR0_EXTIS6_POSE) + +#define GPIO_EXTIPSR0_EXTIS5_POSS 20U +#define GPIO_EXTIPSR0_EXTIS5_POSE 23U +#define GPIO_EXTIPSR0_EXTIS5_MSK BITS(GPIO_EXTIPSR0_EXTIS5_POSS,GPIO_EXTIPSR0_EXTIS5_POSE) + +#define GPIO_EXTIPSR0_EXTIS4_POSS 16U +#define GPIO_EXTIPSR0_EXTIS4_POSE 19U +#define GPIO_EXTIPSR0_EXTIS4_MSK BITS(GPIO_EXTIPSR0_EXTIS4_POSS,GPIO_EXTIPSR0_EXTIS4_POSE) + +#define GPIO_EXTIPSR0_EXTIS3_POSS 12U +#define GPIO_EXTIPSR0_EXTIS3_POSE 15U +#define GPIO_EXTIPSR0_EXTIS3_MSK BITS(GPIO_EXTIPSR0_EXTIS3_POSS,GPIO_EXTIPSR0_EXTIS3_POSE) + +#define GPIO_EXTIPSR0_EXTIS2_POSS 8U +#define GPIO_EXTIPSR0_EXTIS2_POSE 11U +#define GPIO_EXTIPSR0_EXTIS2_MSK BITS(GPIO_EXTIPSR0_EXTIS2_POSS,GPIO_EXTIPSR0_EXTIS2_POSE) + +#define GPIO_EXTIPSR0_EXTIS1_POSS 4U +#define GPIO_EXTIPSR0_EXTIS1_POSE 7U +#define GPIO_EXTIPSR0_EXTIS1_MSK BITS(GPIO_EXTIPSR0_EXTIS1_POSS,GPIO_EXTIPSR0_EXTIS1_POSE) + +#define GPIO_EXTIPSR0_EXTIS0_POSS 0U +#define GPIO_EXTIPSR0_EXTIS0_POSE 3U +#define GPIO_EXTIPSR0_EXTIS0_MSK BITS(GPIO_EXTIPSR0_EXTIS0_POSS,GPIO_EXTIPSR0_EXTIS0_POSE) + +/****************** Bit definition for GPIO_EXTIPSR1 register ************************/ + +#define GPIO_EXTIPSR1_EXTIS15_POSS 28U +#define GPIO_EXTIPSR1_EXTIS15_POSE 31U +#define GPIO_EXTIPSR1_EXTIS15_MSK BITS(GPIO_EXTIPSR1_EXTIS15_POSS,GPIO_EXTIPSR1_EXTIS15_POSE) + +#define GPIO_EXTIPSR1_EXTIS14_POSS 24U +#define GPIO_EXTIPSR1_EXTIS14_POSE 27U +#define GPIO_EXTIPSR1_EXTIS14_MSK BITS(GPIO_EXTIPSR1_EXTIS14_POSS,GPIO_EXTIPSR1_EXTIS14_POSE) + +#define GPIO_EXTIPSR1_EXTIS13_POSS 20U +#define GPIO_EXTIPSR1_EXTIS13_POSE 23U +#define GPIO_EXTIPSR1_EXTIS13_MSK BITS(GPIO_EXTIPSR1_EXTIS13_POSS,GPIO_EXTIPSR1_EXTIS13_POSE) + +#define GPIO_EXTIPSR1_EXTIS12_POSS 16U +#define GPIO_EXTIPSR1_EXTIS12_POSE 19U +#define GPIO_EXTIPSR1_EXTIS12_MSK BITS(GPIO_EXTIPSR1_EXTIS12_POSS,GPIO_EXTIPSR1_EXTIS12_POSE) + +#define GPIO_EXTIPSR1_EXTIS11_POSS 12U +#define GPIO_EXTIPSR1_EXTIS11_POSE 15U +#define GPIO_EXTIPSR1_EXTIS11_MSK BITS(GPIO_EXTIPSR1_EXTIS11_POSS,GPIO_EXTIPSR1_EXTIS11_POSE) + +#define GPIO_EXTIPSR1_EXTIS10_POSS 8U +#define GPIO_EXTIPSR1_EXTIS10_POSE 11U +#define GPIO_EXTIPSR1_EXTIS10_MSK BITS(GPIO_EXTIPSR1_EXTIS10_POSS,GPIO_EXTIPSR1_EXTIS10_POSE) + +#define GPIO_EXTIPSR1_EXTIS9_POSS 4U +#define GPIO_EXTIPSR1_EXTIS9_POSE 7U +#define GPIO_EXTIPSR1_EXTIS9_MSK BITS(GPIO_EXTIPSR1_EXTIS9_POSS,GPIO_EXTIPSR1_EXTIS9_POSE) + +#define GPIO_EXTIPSR1_EXTIS8_POSS 0U +#define GPIO_EXTIPSR1_EXTIS8_POSE 3U +#define GPIO_EXTIPSR1_EXTIS8_MSK BITS(GPIO_EXTIPSR1_EXTIS8_POSS,GPIO_EXTIPSR1_EXTIS8_POSE) + +/****************** Bit definition for GPIO_EXTIFLTCR register ************************/ + +#define GPIO_EXTIFLTCR_FLTSEL_POSS 16U +#define GPIO_EXTIFLTCR_FLTSEL_POSE 23U +#define GPIO_EXTIFLTCR_FLTSEL_MSK BITS(GPIO_EXTIFLTCR_FLTSEL_POSS,GPIO_EXTIFLTCR_FLTSEL_POSE) + +#define GPIO_EXTIFLTCR_FLTEN_POSS 0U +#define GPIO_EXTIFLTCR_FLTEN_POSE 15U +#define GPIO_EXTIFLTCR_FLTEN_MSK BITS(GPIO_EXTIFLTCR_FLTEN_POSS,GPIO_EXTIFLTCR_FLTEN_POSE) + +typedef struct +{ + __I uint32_t DIN; + __IO uint32_t DOUT; + __O uint32_t BSRR; + __O uint32_t BIR; + __IO uint32_t MODE; + __IO uint32_t OD; + __IO uint32_t PUPD; + __IO uint32_t ODRV; + __IO uint32_t FLT; + __IO uint32_t TYPE; + __IO uint32_t FUNC0; + __IO uint32_t FUNC1; + __IO uint32_t LOCK; +} GPIO_TypeDef; + +/* Exported Types ------------------------------------------------------------ */ + +typedef struct +{ + __IO uint32_t EXTIRER; + uint32_t RESERVED1 ; + __IO uint32_t EXTIFER; + uint32_t RESERVED2 ; + __IO uint32_t EXTIEN; + uint32_t RESERVED3 ; + __I uint32_t EXTIFLAG; + uint32_t RESERVED4 ; + __O uint32_t EXTISFR; + uint32_t RESERVED5 ; + __O uint32_t EXTICFR; + uint32_t RESERVED6 ; + __IO uint32_t EXTIPSR0; + __IO uint32_t EXTIPSR1; + uint32_t RESERVED7[2] ; + __IO uint32_t EXTIFLTCR; +} EXTI_TypeDef; + +#endif /* __REG_GPIO_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_i2c.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_i2c.h new file mode 100644 index 0000000000..c551379aad --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_i2c.h @@ -0,0 +1,568 @@ +/********************************************************************************** + * + * @file reg_i2c.h + * @brief I2C Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_I2C_H__ +#define __REG_I2C_H__ + +/* Includes ------------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ +/* Exported Macros ----------------------------------------------------------- */ + +/****************** Bit definition for I2C_CON1 register ************************/ + +# define I2C_CON1_NBYTES_POSS 24U +# define I2C_CON1_NBYTES_POSE 31U +# define I2C_CON1_NBYTES_MSK BITS(I2C_CON1_NBYTES_POSS, I2C_CON1_NBYTES_POSE) + +# define I2C_CON1_PECEN_POS 23U +# define I2C_CON1_PECEN_MSK BIT(I2C_CON1_PECEN_POS) + +# define I2C_CON1_ALERTEN_POS 22U +# define I2C_CON1_ALERTEN_MSK BIT(I2C_CON1_ALERTEN_POS) + +# define I2C_CON1_SMBDEN_POS 21U +# define I2C_CON1_SMBDEN_MSK BIT(I2C_CON1_SMBDEN_POS) + +# define I2C_CON1_SMBHEN_POS 20U +# define I2C_CON1_SMBHEN_MSK BIT(I2C_CON1_SMBHEN_POS) + +# define I2C_CON1_GCEN_POS 19U +# define I2C_CON1_GCEN_MSK BIT(I2C_CON1_GCEN_POS) + +# define I2C_CON1_NOSTRETCH_POS 17U +# define I2C_CON1_NOSTRETCH_MSK BIT(I2C_CON1_NOSTRETCH_POS) + +# define I2C_CON1_SBC_POS 16U +# define I2C_CON1_SBC_MSK BIT(I2C_CON1_SBC_POS) + +# define I2C_CON1_RXDMAEN_POS 15U +# define I2C_CON1_RXDMAEN_MSK BIT(I2C_CON1_RXDMAEN_POS) + +# define I2C_CON1_TXDMAEN_POS 14U +# define I2C_CON1_TXDMAEN_MSK BIT(I2C_CON1_TXDMAEN_POS) + +# define I2C_CON1_DNF_POSS 8U +# define I2C_CON1_DNF_POSE 11U +# define I2C_CON1_DNF_MSK BITS(I2C_CON1_DNF_POSS, I2C_CON1_DNF_POSE) + +# define I2C_CON1_PE_POS 0U +# define I2C_CON1_PE_MSK BIT(I2C_CON1_PE_POS) + +/****************** Bit definition for I2C_CON2 register ************************/ + +# define I2C_CON2_ACK_UPD_POS 29U +# define I2C_CON2_ACK_UPD_MSK BIT(I2C_CON2_ACK_UPD_POS) + +# define I2C_CON2_HOLDACK_POS 28U +# define I2C_CON2_HOLDACK_MSK BIT(I2C_CON2_HOLDACK_POS) + +# define I2C_CON2_PECBYTE_POS 26U +# define I2C_CON2_PECBYTE_MSK BIT(I2C_CON2_PECBYTE_POS) + +# define I2C_CON2_AUTOEND_POS 25U +# define I2C_CON2_AUTOEND_MSK BIT(I2C_CON2_AUTOEND_POS) + +# define I2C_CON2_RELOAD_POS 24U +# define I2C_CON2_RELOAD_MSK BIT(I2C_CON2_RELOAD_POS) + +# define I2C_CON2_NBYTES_POSS 16U +# define I2C_CON2_NBYTES_POSE 23U +# define I2C_CON2_NBYTES_MSK BITS(I2C_CON2_NBYTES_POSS, I2C_CON2_NBYTES_POSE) + +# define I2C_CON2_NACK_POS 15U +# define I2C_CON2_NACK_MSK BIT(I2C_CON2_NACK_POS) + +# define I2C_CON2_STOP_POS 14U +# define I2C_CON2_STOP_MSK BIT(I2C_CON2_STOP_POS) + +# define I2C_CON2_START_POS 13U +# define I2C_CON2_START_MSK BIT(I2C_CON2_START_POS) + +# define I2C_CON2_HEAD10R_POS 12U +# define I2C_CON2_HEAD10R_MSK BIT(I2C_CON2_HEAD10R_POS) + +# define I2C_CON2_ADD10_POS 11U +# define I2C_CON2_ADD10_MSK BIT(I2C_CON2_ADD10_POS) + +# define I2C_CON2_RD_WRN_POS 10U +# define I2C_CON2_RD_WRN_MSK BIT(I2C_CON2_RD_WRN_POS) + +# define I2C_CON2_SADD_POSS 0U +# define I2C_CON2_SADD_POSE 9U +# define I2C_CON2_SADD_MSK BITS(I2C_CON2_SADD_POSS, I2C_CON2_SADD_POSE) + +/****************** Bit definition for I2C_ADDR1 register ************************/ + +# define I2C_ADDR1_OA1EN_POS 15U +# define I2C_ADDR1_OA1EN_MSK BIT(I2C_ADDR1_OA1EN_POS) + +# define I2C_ADDR1_OA1MODE_POS 10U +# define I2C_ADDR1_OA1MODE_MSK BIT(I2C_ADDR1_OA1MODE_POS) + +# define I2C_ADDR1_OA1_POSS 0U +# define I2C_ADDR1_OA1_POSE 9U +# define I2C_ADDR1_OA1_MSK BITS(I2C_ADDR1_OA1_POSS, I2C_ADDR1_OA1_POSE) + +/****************** Bit definition for I2C_ADDR2 register ************************/ + +# define I2C_ADDR2_OA2EN_POS 15U +# define I2C_ADDR2_OA2EN_MSK BIT(I2C_ADDR2_OA2EN_POS) + +# define I2C_ADDR2_OA2MSK_POSS 8U +# define I2C_ADDR2_OA2MSK_POSE 10U +# define I2C_ADDR2_OA2MSK_MSK BITS(I2C_ADDR2_OA2MSK_POSS, I2C_ADDR2_OA2MSK_POSE) + +# define I2C_ADDR2_OA2_POSS 1U +# define I2C_ADDR2_OA2_POSE 7U +# define I2C_ADDR2_OA2_MSK BITS(I2C_ADDR2_OA2_POSS, I2C_ADDR2_OA2_POSE) + +/****************** Bit definition for I2C_TIMINGR register ************************/ + +# define I2C_TIMINGR_PRESC_POSS 28U +# define I2C_TIMINGR_PRESC_POSE 31U +# define I2C_TIMINGR_PRESC_MSK BITS(I2C_TIMINGR_PRESC_POSS, I2C_TIMINGR_PRESC_POSE) + +# define I2C_TIMINGR_SCLDEL_POSS 20U +# define I2C_TIMINGR_SCLDEL_POSE 23U +# define I2C_TIMINGR_SCLDEL_MSK BITS(I2C_TIMINGR_SCLDEL_POSS, I2C_TIMINGR_SCLDEL_POSE) + +# define I2C_TIMINGR_SDADEL_POSS 16U +# define I2C_TIMINGR_SDADEL_POSE 19U +# define I2C_TIMINGR_SDADEL_MSK BITS(I2C_TIMINGR_SDADEL_POSS, I2C_TIMINGR_SDADEL_POSE) + +# define I2C_TIMINGR_SCLH_POSS 8U +# define I2C_TIMINGR_SCLH_POSE 15U +# define I2C_TIMINGR_SCLH_MSK BITS(I2C_TIMINGR_SCLH_POSS, I2C_TIMINGR_SCLH_POSE) + +# define I2C_TIMINGR_SCLL_POSS 0U +# define I2C_TIMINGR_SCLL_POSE 7U +# define I2C_TIMINGR_SCLL_MSK BITS(I2C_TIMINGR_SCLL_POSS, I2C_TIMINGR_SCLL_POSE) + +/****************** Bit definition for I2C_TIMEOUTR register ************************/ + +# define I2C_TIMEOUTR_TEXTEN_POS 31U +# define I2C_TIMEOUTR_TEXTEN_MSK BIT(I2C_TIMEOUTR_TEXTEN_POS) + +# define I2C_TIMEOUTR_TIMEOUTB_POSS 16U +# define I2C_TIMEOUTR_TIMEOUTB_POSE 27U +# define I2C_TIMEOUTR_TIMEOUTB_MSK BITS(I2C_TIMEOUTR_TIMEOUTB_POSS, I2C_TIMEOUTR_TIMEOUTB_POSE) + +# define I2C_TIMEOUTR_TIMEOUTEN_POS 15U +# define I2C_TIMEOUTR_TIMEOUTEN_MSK BIT(I2C_TIMEOUTR_TIMEOUTEN_POS) + +# define I2C_TIMEOUTR_TIDLE_POS 12U +# define I2C_TIMEOUTR_TIDLE_MSK BIT(I2C_TIMEOUTR_TIDLE_POS) + +# define I2C_TIMEOUTR_TIMEOUTA_POSS 0U +# define I2C_TIMEOUTR_TIMEOUTA_POSE 11U +# define I2C_TIMEOUTR_TIMEOUTA_MSK BITS(I2C_TIMEOUTR_TIMEOUTA_POSS, I2C_TIMEOUTR_TIMEOUTA_POSE) + +/****************** Bit definition for I2C_STAT register ************************/ + +# define I2C_STAT_ADDCODE_POSS 17U +# define I2C_STAT_ADDCODE_POSE 23U +# define I2C_STAT_ADDCODE_MSK BITS(I2C_STAT_ADDCODE_POSS, I2C_STAT_ADDCODE_POSE) + +# define I2C_STAT_DIR_POS 16U +# define I2C_STAT_DIR_MSK BIT(I2C_STAT_DIR_POS) + +# define I2C_STAT_BUSY_POS 15U +# define I2C_STAT_BUSY_MSK BIT(I2C_STAT_BUSY_POS) + +# define I2C_STAT_TCR_POS 11U +# define I2C_STAT_TCR_MSK BIT(I2C_STAT_TCR_POS) + +# define I2C_STAT_TC_POS 10U +# define I2C_STAT_TC_MSK BIT(I2C_STAT_TC_POS) + +# define I2C_STAT_RXUD_POS 8U +# define I2C_STAT_RXUD_MSK BIT(I2C_STAT_RXUD_POS) + +# define I2C_STAT_RXOV_POS 7U +# define I2C_STAT_RXOV_MSK BIT(I2C_STAT_RXOV_POS) + +# define I2C_STAT_RXNE_POS 5U +# define I2C_STAT_RXNE_MSK BIT(I2C_STAT_RXNE_POS) + +# define I2C_STAT_TXUD_POS 3U +# define I2C_STAT_TXUD_MSK BIT(I2C_STAT_TXUD_POS) + +# define I2C_STAT_TXOV_POS 2U +# define I2C_STAT_TXOV_MSK BIT(I2C_STAT_TXOV_POS) + +# define I2C_STAT_TXE_POS 0U +# define I2C_STAT_TXE_MSK BIT(I2C_STAT_TXE_POS) + +/****************** Bit definition for I2C_PECR register ************************/ + +# define I2C_PECR_PEC_POSS 0U +# define I2C_PECR_PEC_POSE 7U +# define I2C_PECR_PEC_MSK BITS(I2C_PECR_PEC_POSS, I2C_PECR_PEC_POSE) + +/****************** Bit definition for I2C_RXDATA register ************************/ + +# define I2C_RXDATA_RXDATA_POSS 0U +# define I2C_RXDATA_RXDATA_POSE 7U +# define I2C_RXDATA_RXDATA_MSK BITS(I2C_RXDATA_RXDATA_POSS, I2C_RXDATA_RXDATA_POSE) + +/****************** Bit definition for I2C_TXDATA register ************************/ + +# define I2C_TXDATA_TXDATA_POSS 0U +# define I2C_TXDATA_TXDATA_POSE 7U +# define I2C_TXDATA_TXDATA_MSK BITS(I2C_TXDATA_TXDATA_POSS, I2C_TXDATA_TXDATA_POSE) + +/****************** Bit definition for I2C_IER register ************************/ + +# define I2C_IER_ALERT_POS 20U +# define I2C_IER_ALERT_MSK BIT(I2C_IER_ALERT_POS) + +# define I2C_IER_TOUT_POS 19U +# define I2C_IER_TOUT_MSK BIT(I2C_IER_TOUT_POS) + +# define I2C_IER_PECE_POS 18U +# define I2C_IER_PECE_MSK BIT(I2C_IER_PECE_POS) + +# define I2C_IER_ARLO_POS 17U +# define I2C_IER_ARLO_MSK BIT(I2C_IER_ARLO_POS) + +# define I2C_IER_BERR_POS 16U +# define I2C_IER_BERR_MSK BIT(I2C_IER_BERR_POS) + +# define I2C_IER_STOP_POS 14U +# define I2C_IER_STOP_MSK BIT(I2C_IER_STOP_POS) + +# define I2C_IER_NACK_POS 13U +# define I2C_IER_NACK_MSK BIT(I2C_IER_NACK_POS) + +# define I2C_IER_ADDR_POS 12U +# define I2C_IER_ADDR_MSK BIT(I2C_IER_ADDR_POS) + +# define I2C_IER_TCR_POS 11U +# define I2C_IER_TCR_MSK BIT(I2C_IER_TCR_POS) + +# define I2C_IER_TC_POS 10U +# define I2C_IER_TC_MSK BIT(I2C_IER_TC_POS) + +# define I2C_IER_RXUD_POS 8U +# define I2C_IER_RXUD_MSK BIT(I2C_IER_RXUD_POS) + +# define I2C_IER_RXOV_POS 7U +# define I2C_IER_RXOV_MSK BIT(I2C_IER_RXOV_POS) + +# define I2C_IER_RXNE_POS 5U +# define I2C_IER_RXNE_MSK BIT(I2C_IER_RXNE_POS) + +# define I2C_IER_TXUD_POS 3U +# define I2C_IER_TXUD_MSK BIT(I2C_IER_TXUD_POS) + +# define I2C_IER_TXOV_POS 2U +# define I2C_IER_TXOV_MSK BIT(I2C_IER_TXOV_POS) + +# define I2C_IER_TXE_POS 0U +# define I2C_IER_TXE_MSK BIT(I2C_IER_TXE_POS) + +/****************** Bit definition for I2C_IDR register ************************/ + +# define I2C_IDR_ALERT_POS 20U +# define I2C_IDR_ALERT_MSK BIT(I2C_IDR_ALERT_POS) + +# define I2C_IDR_TOUT_POS 19U +# define I2C_IDR_TOUT_MSK BIT(I2C_IDR_TOUT_POS) + +# define I2C_IDR_PECE_POS 18U +# define I2C_IDR_PECE_MSK BIT(I2C_IDR_PECE_POS) + +# define I2C_IDR_ARLO_POS 17U +# define I2C_IDR_ARLO_MSK BIT(I2C_IDR_ARLO_POS) + +# define I2C_IDR_BERR_POS 16U +# define I2C_IDR_BERR_MSK BIT(I2C_IDR_BERR_POS) + +# define I2C_IDR_STOP_POS 14U +# define I2C_IDR_STOP_MSK BIT(I2C_IDR_STOP_POS) + +# define I2C_IDR_NACK_POS 13U +# define I2C_IDR_NACK_MSK BIT(I2C_IDR_NACK_POS) + +# define I2C_IDR_ADDR_POS 12U +# define I2C_IDR_ADDR_MSK BIT(I2C_IDR_ADDR_POS) + +# define I2C_IDR_TCR_POS 11U +# define I2C_IDR_TCR_MSK BIT(I2C_IDR_TCR_POS) + +# define I2C_IDR_TC_POS 10U +# define I2C_IDR_TC_MSK BIT(I2C_IDR_TC_POS) + +# define I2C_IDR_RXUD_POS 8U +# define I2C_IDR_RXUD_MSK BIT(I2C_IDR_RXUD_POS) + +# define I2C_IDR_RXOV_POS 7U +# define I2C_IDR_RXOV_MSK BIT(I2C_IDR_RXOV_POS) + +# define I2C_IDR_RXNE_POS 5U +# define I2C_IDR_RXNE_MSK BIT(I2C_IDR_RXNE_POS) + +# define I2C_IDR_TXUD_POS 3U +# define I2C_IDR_TXUD_MSK BIT(I2C_IDR_TXUD_POS) + +# define I2C_IDR_TXOV_POS 2U +# define I2C_IDR_TXOV_MSK BIT(I2C_IDR_TXOV_POS) + +# define I2C_IDR_TXE_POS 0U +# define I2C_IDR_TXE_MSK BIT(I2C_IDR_TXE_POS) +/****************** Bit definition for I2C_IVS register ************************/ + +# define I2C_IVS_ALERT_POS 20U +# define I2C_IVS_ALERT_MSK BIT(I2C_IVS_ALERT_POS) + +# define I2C_IVS_TOUT_POS 19U +# define I2C_IVS_TOUT_MSK BIT(I2C_IVS_TOUT_POS) + +# define I2C_IVS_PECE_POS 18U +# define I2C_IVS_PECE_MSK BIT(I2C_IVS_PECE_POS) + +# define I2C_IVS_ARLO_POS 17U +# define I2C_IVS_ARLO_MSK BIT(I2C_IVS_ARLO_POS) + +# define I2C_IVS_BERR_POS 16U +# define I2C_IVS_BERR_MSK BIT(I2C_IVS_BERR_POS) + +# define I2C_IVS_STOP_POS 14U +# define I2C_IVS_STOP_MSK BIT(I2C_IVS_STOP_POS) + +# define I2C_IVS_NACK_POS 13U +# define I2C_IVS_NACK_MSK BIT(I2C_IVS_NACK_POS) + +# define I2C_IVS_ADDR_POS 12U +# define I2C_IVS_ADDR_MSK BIT(I2C_IVS_ADDR_POS) + +# define I2C_IVS_TCR_POS 11U +# define I2C_IVS_TCR_MSK BIT(I2C_IVS_TCR_POS) + +# define I2C_IVS_TC_POS 10U +# define I2C_IVS_TC_MSK BIT(I2C_IVS_TC_POS) + +# define I2C_IVS_RXUD_POS 8U +# define I2C_IVS_RXUD_MSK BIT(I2C_IVS_RXUD_POS) + +# define I2C_IVS_RXOV_POS 7U +# define I2C_IVS_RXOV_MSK BIT(I2C_IVS_RXOV_POS) + +# define I2C_IVS_RXNE_POS 5U +# define I2C_IVS_RXNE_MSK BIT(I2C_IVS_RXNE_POS) + +# define I2C_IVS_TXUD_POS 3U +# define I2C_IVS_TXUD_MSK BIT(I2C_IVS_TXUD_POS) + +# define I2C_IVS_TXOV_POS 2U +# define I2C_IVS_TXOV_MSK BIT(I2C_IVS_TXOV_POS) + +# define I2C_IVS_TXE_POS 0U +# define I2C_IVS_TXE_MSK BIT(I2C_IVS_TXE_POS) + +/****************** Bit definition for I2C_RIF register ************************/ + +# define I2C_RIF_ALERT_POS 20U +# define I2C_RIF_ALERT_MSK BIT(I2C_RIF_ALERT_POS) + +# define I2C_RIF_TOUT_POS 19U +# define I2C_RIF_TOUT_MSK BIT(I2C_RIF_TOUT_POS) + +# define I2C_RIF_PECE_POS 18U +# define I2C_RIF_PECE_MSK BIT(I2C_RIF_PECE_POS) + +# define I2C_RIF_ARLO_POS 17U +# define I2C_RIF_ARLO_MSK BIT(I2C_RIF_ARLO_POS) + +# define I2C_RIF_BERR_POS 16U +# define I2C_RIF_BERR_MSK BIT(I2C_RIF_BERR_POS) + +# define I2C_RIF_STOP_POS 14U +# define I2C_RIF_STOP_MSK BIT(I2C_RIF_STOP_POS) + +# define I2C_RIF_NACK_POS 13U +# define I2C_RIF_NACK_MSK BIT(I2C_RIF_NACK_POS) + +# define I2C_RIF_ADDR_POS 12U +# define I2C_RIF_ADDR_MSK BIT(I2C_RIF_ADDR_POS) + +# define I2C_RIF_TCR_POS 11U +# define I2C_RIF_TCR_MSK BIT(I2C_RIF_TCR_POS) + +# define I2C_RIF_TC_POS 10U +# define I2C_RIF_TC_MSK BIT(I2C_RIF_TC_POS) + +# define I2C_RIF_RXUD_POS 8U +# define I2C_RIF_RXUD_MSK BIT(I2C_RIF_RXUD_POS) + +# define I2C_RIF_RXOV_POS 7U +# define I2C_RIF_RXOV_MSK BIT(I2C_RIF_RXOV_POS) + +# define I2C_RIF_RXNE_POS 5U +# define I2C_RIF_RXNE_MSK BIT(I2C_RIF_RXNE_POS) + +# define I2C_RIF_TXUD_POS 3U +# define I2C_RIF_TXUD_MSK BIT(I2C_RIF_TXUD_POS) + +# define I2C_RIF_TXOV_POS 2U +# define I2C_RIF_TXOV_MSK BIT(I2C_RIF_TXOV_POS) + +# define I2C_RIF_TXE_POS 0U +# define I2C_RIF_TXE_MSK BIT(I2C_RIF_TXE_POS) + +/****************** Bit definition for I2C_IFM register ************************/ + +# define I2C_IFM_ALERT_POS 20U +# define I2C_IFM_ALERT_MSK BIT(I2C_IFM_ALERT_POS) + +# define I2C_IFM_TOUT_POS 19U +# define I2C_IFM_TOUT_MSK BIT(I2C_IFM_TOUT_POS) + +# define I2C_IFM_PECE_POS 18U +# define I2C_IFM_PECE_MSK BIT(I2C_IFM_PECE_POS) + +# define I2C_IFM_ARLO_POS 17U +# define I2C_IFM_ARLO_MSK BIT(I2C_IFM_ARLO_POS) + +# define I2C_IFM_BERR_POS 16U +# define I2C_IFM_BERR_MSK BIT(I2C_IFM_BERR_POS) + +# define I2C_IFM_STOP_POS 14U +# define I2C_IFM_STOP_MSK BIT(I2C_IFM_STOP_POS) + +# define I2C_IFM_NACK_POS 13U +# define I2C_IFM_NACK_MSK BIT(I2C_IFM_NACK_POS) + +# define I2C_IFM_ADDR_POS 12U +# define I2C_IFM_ADDR_MSK BIT(I2C_IFM_ADDR_POS) + +# define I2C_IFM_TCR_POS 11U +# define I2C_IFM_TCR_MSK BIT(I2C_IFM_TCR_POS) + +# define I2C_IFM_TC_POS 10U +# define I2C_IFM_TC_MSK BIT(I2C_IFM_TC_POS) + +# define I2C_IFM_RXUD_POS 8U +# define I2C_IFM_RXUD_MSK BIT(I2C_IFM_RXUD_POS) + +# define I2C_IFM_RXOV_POS 7U +# define I2C_IFM_RXOV_MSK BIT(I2C_IFM_RXOV_POS) + +# define I2C_IFM_RXNE_POS 5U +# define I2C_IFM_RXNE_MSK BIT(I2C_IFM_RXNE_POS) + +# define I2C_IFM_TXUD_POS 3U +# define I2C_IFM_TXUD_MSK BIT(I2C_IFM_TXUD_POS) + +# define I2C_IFM_TXOV_POS 2U +# define I2C_IFM_TXOV_MSK BIT(I2C_IFM_TXOV_POS) + +# define I2C_IFM_TXE_POS 0U +# define I2C_IFM_TXE_MSK BIT(I2C_IFM_TXE_POS) + +/****************** Bit definition for I2C_ICR register ************************/ + +# define I2C_ICR_ALERT_POS 20U +# define I2C_ICR_ALERT_MSK BIT(I2C_ICR_ALERT_POS) + +# define I2C_ICR_TOUT_POS 19U +# define I2C_ICR_TOUT_MSK BIT(I2C_ICR_TOUT_POS) + +# define I2C_ICR_PECE_POS 18U +# define I2C_ICR_PECE_MSK BIT(I2C_ICR_PECE_POS) + +# define I2C_ICR_ARLO_POS 17U +# define I2C_ICR_ARLO_MSK BIT(I2C_ICR_ARLO_POS) + +# define I2C_ICR_BERR_POS 16U +# define I2C_ICR_BERR_MSK BIT(I2C_ICR_BERR_POS) + +# define I2C_ICR_STOP_POS 14U +# define I2C_ICR_STOP_MSK BIT(I2C_ICR_STOP_POS) + +# define I2C_ICR_NACK_POS 13U +# define I2C_ICR_NACK_MSK BIT(I2C_ICR_NACK_POS) + +# define I2C_ICR_ADDR_POS 12U +# define I2C_ICR_ADDR_MSK BIT(I2C_ICR_ADDR_POS) + +# define I2C_ICR_TCR_POS 11U +# define I2C_ICR_TCR_MSK BIT(I2C_ICR_TCR_POS) + +# define I2C_ICR_TC_POS 10U +# define I2C_ICR_TC_MSK BIT(I2C_ICR_TC_POS) + +# define I2C_ICR_RXUD_POS 8U +# define I2C_ICR_RXUD_MSK BIT(I2C_ICR_RXUD_POS) + +# define I2C_ICR_RXOV_POS 7U +# define I2C_ICR_RXOV_MSK BIT(I2C_ICR_RXOV_POS) + +# define I2C_ICR_RXNE_POS 5U +# define I2C_ICR_RXNE_MSK BIT(I2C_ICR_RXNE_POS) + +# define I2C_ICR_TXUD_POS 3U +# define I2C_ICR_TXUD_MSK BIT(I2C_ICR_TXUD_POS) + +# define I2C_ICR_TXOV_POS 2U +# define I2C_ICR_TXOV_MSK BIT(I2C_ICR_TXOV_POS) + +# define I2C_ICR_TXE_POS 0U +# define I2C_ICR_TXE_MSK BIT(I2C_ICR_TXE_POS) + +/* Exported Types ------------------------------------------------------------ */ + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t ADDR1; + __IO uint32_t ADDR2; + __IO uint32_t TIMINGR; + __IO uint32_t TIMEOUTR; + __I uint32_t STAT; + __IO uint32_t RESERVED0; + __IO uint32_t PECR; + __I uint32_t RXDATA; + __O uint32_t TXDATA; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} I2C_TypeDef; + +#endif /* __REG_I2C_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_iwdt.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_iwdt.h new file mode 100644 index 0000000000..82c223d180 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_iwdt.h @@ -0,0 +1,98 @@ +/********************************************************************************** + * + * @file reg_iwdt.h + * @brief IWDT Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_IWDT_H__ +#define __REG_IWDT_H__ + +/* Includes ------------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ +/* Exported Macros ----------------------------------------------------------- */ + +/****************** Bit definition for IWDT_LOAD register ************************/ + +#define IWDT_LOAD_LOAD_POSS 0U +#define IWDT_LOAD_LOAD_POSE 31U +#define IWDT_LOAD_LOAD_MSK BITS(IWDT_LOAD_LOAD_POSS,IWDT_LOAD_LOAD_POSE) + +/****************** Bit definition for IWDT_VALUE register ************************/ + +#define IWDT_VALUE_VALUE_POSS 0U +#define IWDT_VALUE_VALUE_POSE 31U +#define IWDT_VALUE_VALUE_MSK BITS(IWDT_VALUE_VALUE_POSS,IWDT_VALUE_VALUE_POSE) + +/****************** Bit definition for IWDT_CON register ************************/ + +#define IWDT_CON_CLKS_POS 3U +#define IWDT_CON_CLKS_MSK BIT(IWDT_CON_CLKS_POS) + +#define IWDT_CON_RSTEN_POS 2U +#define IWDT_CON_RSTEN_MSK BIT(IWDT_CON_RSTEN_POS) + +#define IWDT_CON_IE_POS 1U +#define IWDT_CON_IE_MSK BIT(IWDT_CON_IE_POS) + +#define IWDT_CON_EN_POS 0U +#define IWDT_CON_EN_MSK BIT(IWDT_CON_EN_POS) + +/****************** Bit definition for IWDT_INTCLR register ************************/ + +#define IWDT_INTCLR_INTCLR_POSS 0U +#define IWDT_INTCLR_INTCLR_POSE 31U +#define IWDT_INTCLR_INTCLR_MSK BITS(IWDT_INTCLR_INTCLR_POSS,IWDT_INTCLR_INTCLR_POSE) + +/****************** Bit definition for IWDT_RIS register ************************/ + +#define IWDT_RIS_WDTIF_POS 0U +#define IWDT_RIS_WDTIF_MSK BIT(IWDT_RIS_WDTIF_POS) + +/****************** Bit definition for IWDT_LOCK register ************************/ + +#define IWDT_LOCK_LOCK_POS 0U +#define IWDT_LOCK_LOCK_MSK BIT(IWDT_LOCK_LOCK_POS) + +/* Exported Types ------------------------------------------------------------ */ + +typedef struct +{ + __O uint32_t LOAD_; + __I uint32_t VALUE; + __IO uint32_t CON; + __O uint32_t INTCLR; + __I uint32_t RIS; + uint32_t RESERVED0[59] ; + __IO uint32_t LOCK; +} IWDT_TypeDef; + +#endif /* __REG_IWDT_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_msc.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_msc.h new file mode 100644 index 0000000000..ab4ea1fef3 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_msc.h @@ -0,0 +1,180 @@ +/********************************************************************************** + * + * @file reg_msc.h + * @brief MSC Head File + * + * @date 27 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 27 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_MSC_H__ +#define __REG_MSC_H__ + +/* Includes ------------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ +/* Exported Macros ----------------------------------------------------------- */ + +/****************** Bit definition for MSC_FLASHKEY register ************************/ + +#define MSC_FLASHKEY_STATUS_POSS 0U +#define MSC_FLASHKEY_STATUS_POSE 1U +#define MSC_FLASHKEY_STATUS_MSK BITS(MSC_FLASHKEY_STATUS_POSS,MSC_FLASHKEY_STATUS_POSE) + +/****************** Bit definition for MSC_INFOKEY register ************************/ + +#define MSC_INFOKEY_STATUS_POSS 0U +#define MSC_INFOKEY_STATUS_POSE 1U +#define MSC_INFOKEY_STATUS_MSK BITS(MSC_INFOKEY_STATUS_POSS,MSC_INFOKEY_STATUS_POSE) + +/****************** Bit definition for MSC_FLASHADDR register ************************/ + +#define MSC_FLASHADDR_IFREN_POS 18U +#define MSC_FLASHADDR_IFREN_MSK BIT(MSC_FLASHADDR_IFREN_POS) + +#define MSC_FLASHADDR_ADDR_POSS 0U +#define MSC_FLASHADDR_ADDR_POSE 17U +#define MSC_FLASHADDR_ADDR_MSK BITS(MSC_FLASHADDR_ADDR_POSS,MSC_FLASHADDR_ADDR_POSE) + +/****************** Bit definition for MSC_FLASHFIFO register ************************/ + +#define MSC_FLASHFIFO_FIFO_POSS 0U +#define MSC_FLASHFIFO_FIFO_POSE 31U +#define MSC_FLASHFIFO_FIFO_MSK BITS(MSC_FLASHFIFO_FIFO_POSS,MSC_FLASHFIFO_FIFO_POSE) + +/****************** Bit definition for MSC_FLASHDR register ************************/ + +#define MSC_FLASHDR_DATA_POSS 0U +#define MSC_FLASHDR_DATA_POSE 31U +#define MSC_FLASHDR_DATA_MSK BITS(MSC_FLASHDR_DATA_POSS,MSC_FLASHDR_DATA_POSE) + +/****************** Bit definition for MSC_FLASHCMD register ************************/ + +#define MSC_FLASHCMD_CMD_POSS 0U +#define MSC_FLASHCMD_CMD_POSE 31U +#define MSC_FLASHCMD_CMD_MSK BITS(MSC_FLASHCMD_CMD_POSS,MSC_FLASHCMD_CMD_POSE) + +/****************** Bit definition for MSC_FLASHCR register ************************/ + +#define MSC_FLASHCR_PGSZ_POS 8U +#define MSC_FLASHCR_PGSZ_MSK BIT(MSC_FLASHCR_PGSZ_POS) + +#define MSC_FLASHCR_FIFODF_POS 7U +#define MSC_FLASHCR_FIFODF_MSK BIT(MSC_FLASHCR_FIFODF_POS) + +#define MSC_FLASHCR_FIFOEN_POS 5U +#define MSC_FLASHCR_FIFOEN_MSK BIT(MSC_FLASHCR_FIFOEN_POS) + +#define MSC_FLASHCR_FLASHREQ_POS 4U +#define MSC_FLASHCR_FLASHREQ_MSK BIT(MSC_FLASHCR_FLASHREQ_POS) + +#define MSC_FLASHCR_OTFEN_POS 2U +#define MSC_FLASHCR_OTFEN_MSK BIT(MSC_FLASHCR_OTFEN_POS) + +#define MSC_FLASHCR_IAPRST_POS 1U +#define MSC_FLASHCR_IAPRST_MSK BIT(MSC_FLASHCR_IAPRST_POS) + +#define MSC_FLASHCR_IAPEN_POS 0U +#define MSC_FLASHCR_IAPEN_MSK BIT(MSC_FLASHCR_IAPEN_POS) + +/****************** Bit definition for MSC_FLASHSR register ************************/ + +#define MSC_FLASHSR_UPCEUL_POS 25U +#define MSC_FLASHSR_UPCEUL_MSK BIT(MSC_FLASHSR_UPCEUL_POS) + +#define MSC_FLASHSR_MASEUL_POS 24U +#define MSC_FLASHSR_MASEUL_MSK BIT(MSC_FLASHSR_MASEUL_POS) + +#define MSC_FLASHSR_ADDERR_POS 23U +#define MSC_FLASHSR_ADDERR_MSK BIT(MSC_FLASHSR_ADDERR_POS) + +#define MSC_FLASHSR_UPCEDONE_POS 17U +#define MSC_FLASHSR_UPCEDONE_MSK BIT(MSC_FLASHSR_UPCEDONE_POS) + +#define MSC_FLASHSR_UPCEBUSY_POS 16U +#define MSC_FLASHSR_UPCEBUSY_MSK BIT(MSC_FLASHSR_UPCEBUSY_POS) + +#define MSC_FLASHSR_TIMEOUT_POS 7U +#define MSC_FLASHSR_TIMEOUT_MSK BIT(MSC_FLASHSR_TIMEOUT_POS) + +#define MSC_FLASHSR_PROG_POS 6U +#define MSC_FLASHSR_PROG_MSK BIT(MSC_FLASHSR_PROG_POS) + +#define MSC_FLASHSR_SERA_POS 5U +#define MSC_FLASHSR_SERA_MSK BIT(MSC_FLASHSR_SERA_POS) + +#define MSC_FLASHSR_MASE_POS 4U +#define MSC_FLASHSR_MASE_MSK BIT(MSC_FLASHSR_MASE_POS) + +#define MSC_FLASHSR_WAE_POS 3U +#define MSC_FLASHSR_WAE_MSK BIT(MSC_FLASHSR_WAE_POS) + +#define MSC_FLASHSR_WPE_POS 2U +#define MSC_FLASHSR_WPE_MSK BIT(MSC_FLASHSR_WPE_POS) + +#define MSC_FLASHSR_BUSY_POS 1U +#define MSC_FLASHSR_BUSY_MSK BIT(MSC_FLASHSR_BUSY_POS) + +#define MSC_FLASHSR_FLASHACK_POS 0U +#define MSC_FLASHSR_FLASHACK_MSK BIT(MSC_FLASHSR_FLASHACK_POS) + +/****************** Bit definition for MSC_MEMWAIT register ************************/ + +#define MSC_MEMWAIT_SRAM_W_POSS 8U +#define MSC_MEMWAIT_SRAM_W_POSE 9U +#define MSC_MEMWAIT_SRAM_W_MSK BITS(MSC_MEMWAIT_SRAM_W_POSS,MSC_MEMWAIT_SRAM_W_POSE) + +#define MSC_MEMWAIT_FLASH_W_POSS 0U +#define MSC_MEMWAIT_FLASH_W_POSE 1U +#define MSC_MEMWAIT_FLASH_W_MSK BITS(MSC_MEMWAIT_FLASH_W_POSS,MSC_MEMWAIT_FLASH_W_POSE) + +/****************** Bit definition for MSC_FLASHADDINV register ************************/ + +#define MSC_FLASHADDINV_ADDRINV_POSS 0U +#define MSC_FLASHADDINV_ADDRINV_POSE 17U +#define MSC_FLASHADDINV_ADDRINV_MSK BITS(MSC_FLASHADDINV_ADDRINV_POSS,MSC_FLASHADDINV_ADDRINV_POSE) + +/* Exported Types ------------------------------------------------------------ */ + +typedef struct +{ + __IO uint32_t FLASHKEY; + __I uint32_t INFOKEY; + __IO uint32_t FLASHADDR; + __O uint32_t FLASHFIFO; + __IO uint32_t FLASHDR; + uint32_t RESERVED0 ; + __O uint32_t FLASHCMD; + __IO uint32_t FLASHCR; + __I uint32_t FLASHSR; + uint32_t RESERVED1 ; + __IO uint32_t MEMWAIT; + __IO uint32_t FLASHADDINV; +} MSC_TypeDef; + +#endif /* __REG_MSC_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_pis.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_pis.h new file mode 100644 index 0000000000..f6bfd64ea2 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_pis.h @@ -0,0 +1,469 @@ +/********************************************************************************** + * + * @file reg_pis.h + * @brief PIS Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_PIS_H__ +#define __REG_PIS_H__ + +/* Includes ------------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ +/* Exported Macros ----------------------------------------------------------- */ + +/****************** Bit definition for PIS_CH0_CON register ************************/ + +#define PIS_CH0_CON_LEVEL_POS 31U +#define PIS_CH0_CON_LEVEL_MSK BIT(PIS_CH0_CON_LEVEL_POS) + +#define PIS_CH0_CON_PULSE_POS 30U +#define PIS_CH0_CON_PULSE_MSK BIT(PIS_CH0_CON_PULSE_POS) + +#define PIS_CH0_CON_SYNCSEL_POSS 24U +#define PIS_CH0_CON_SYNCSEL_POSE 26U +#define PIS_CH0_CON_SYNCSEL_MSK BITS(PIS_CH0_CON_SYNCSEL_POSS,PIS_CH0_CON_SYNCSEL_POSE) + +#define PIS_CH0_CON_TSCKS_POSS 18U +#define PIS_CH0_CON_TSCKS_POSE 19U +#define PIS_CH0_CON_TSCKS_MSK BITS(PIS_CH0_CON_TSCKS_POSS,PIS_CH0_CON_TSCKS_POSE) + +#define PIS_CH0_CON_EDGS_POSS 16U +#define PIS_CH0_CON_EDGS_POSE 17U +#define PIS_CH0_CON_EDGS_MSK BITS(PIS_CH0_CON_EDGS_POSS,PIS_CH0_CON_EDGS_POSE) + +#define PIS_CH0_CON_SRCS_POSS 8U +#define PIS_CH0_CON_SRCS_POSE 13U +#define PIS_CH0_CON_SRCS_MSK BITS(PIS_CH0_CON_SRCS_POSS,PIS_CH0_CON_SRCS_POSE) + +#define PIS_CH0_CON_MSIGS_POSS 0U +#define PIS_CH0_CON_MSIGS_POSE 3U +#define PIS_CH0_CON_MSIGS_MSK BITS(PIS_CH0_CON_MSIGS_POSS,PIS_CH0_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH1_CON register ************************/ + +#define PIS_CH1_CON_LEVEL_POS 31U +#define PIS_CH1_CON_LEVEL_MSK BIT(PIS_CH1_CON_LEVEL_POS) + +#define PIS_CH1_CON_PULSE_POS 30U +#define PIS_CH1_CON_PULSE_MSK BIT(PIS_CH1_CON_PULSE_POS) + +#define PIS_CH1_CON_SYNCSEL_POSS 24U +#define PIS_CH1_CON_SYNCSEL_POSE 26U +#define PIS_CH1_CON_SYNCSEL_MSK BITS(PIS_CH1_CON_SYNCSEL_POSS,PIS_CH1_CON_SYNCSEL_POSE) + +#define PIS_CH1_CON_TSCKS_POSS 18U +#define PIS_CH1_CON_TSCKS_POSE 19U +#define PIS_CH1_CON_TSCKS_MSK BITS(PIS_CH1_CON_TSCKS_POSS,PIS_CH1_CON_TSCKS_POSE) + +#define PIS_CH1_CON_EDGS_POSS 16U +#define PIS_CH1_CON_EDGS_POSE 17U +#define PIS_CH1_CON_EDGS_MSK BITS(PIS_CH1_CON_EDGS_POSS,PIS_CH1_CON_EDGS_POSE) + +#define PIS_CH1_CON_SRCS_POSS 8U +#define PIS_CH1_CON_SRCS_POSE 13U +#define PIS_CH1_CON_SRCS_MSK BITS(PIS_CH1_CON_SRCS_POSS,PIS_CH1_CON_SRCS_POSE) + +#define PIS_CH1_CON_MSIGS_POSS 0U +#define PIS_CH1_CON_MSIGS_POSE 3U +#define PIS_CH1_CON_MSIGS_MSK BITS(PIS_CH1_CON_MSIGS_POSS,PIS_CH1_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH2_CON register ************************/ + +#define PIS_CH2_CON_LEVEL_POS 31U +#define PIS_CH2_CON_LEVEL_MSK BIT(PIS_CH2_CON_LEVEL_POS) + +#define PIS_CH2_CON_PULSE_POS 30U +#define PIS_CH2_CON_PULSE_MSK BIT(PIS_CH2_CON_PULSE_POS) + +#define PIS_CH2_CON_SYNCSEL_POSS 24U +#define PIS_CH2_CON_SYNCSEL_POSE 26U +#define PIS_CH2_CON_SYNCSEL_MSK BITS(PIS_CH2_CON_SYNCSEL_POSS,PIS_CH2_CON_SYNCSEL_POSE) + +#define PIS_CH2_CON_TSCKS_POSS 18U +#define PIS_CH2_CON_TSCKS_POSE 19U +#define PIS_CH2_CON_TSCKS_MSK BITS(PIS_CH2_CON_TSCKS_POSS,PIS_CH2_CON_TSCKS_POSE) + +#define PIS_CH2_CON_EDGS_POSS 16U +#define PIS_CH2_CON_EDGS_POSE 17U +#define PIS_CH2_CON_EDGS_MSK BITS(PIS_CH2_CON_EDGS_POSS,PIS_CH2_CON_EDGS_POSE) + +#define PIS_CH2_CON_SRCS_POSS 8U +#define PIS_CH2_CON_SRCS_POSE 13U +#define PIS_CH2_CON_SRCS_MSK BITS(PIS_CH2_CON_SRCS_POSS,PIS_CH2_CON_SRCS_POSE) + +#define PIS_CH2_CON_MSIGS_POSS 0U +#define PIS_CH2_CON_MSIGS_POSE 3U +#define PIS_CH2_CON_MSIGS_MSK BITS(PIS_CH2_CON_MSIGS_POSS,PIS_CH2_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH3_CON register ************************/ + +#define PIS_CH3_CON_LEVEL_POS 31U +#define PIS_CH3_CON_LEVEL_MSK BIT(PIS_CH3_CON_LEVEL_POS) + +#define PIS_CH3_CON_PULSE_POS 30U +#define PIS_CH3_CON_PULSE_MSK BIT(PIS_CH3_CON_PULSE_POS) + +#define PIS_CH3_CON_SYNCSEL_POSS 24U +#define PIS_CH3_CON_SYNCSEL_POSE 26U +#define PIS_CH3_CON_SYNCSEL_MSK BITS(PIS_CH3_CON_SYNCSEL_POSS,PIS_CH3_CON_SYNCSEL_POSE) + +#define PIS_CH3_CON_TSCKS_POSS 18U +#define PIS_CH3_CON_TSCKS_POSE 19U +#define PIS_CH3_CON_TSCKS_MSK BITS(PIS_CH3_CON_TSCKS_POSS,PIS_CH3_CON_TSCKS_POSE) + +#define PIS_CH3_CON_EDGS_POSS 16U +#define PIS_CH3_CON_EDGS_POSE 17U +#define PIS_CH3_CON_EDGS_MSK BITS(PIS_CH3_CON_EDGS_POSS,PIS_CH3_CON_EDGS_POSE) + +#define PIS_CH3_CON_SRCS_POSS 8U +#define PIS_CH3_CON_SRCS_POSE 13U +#define PIS_CH3_CON_SRCS_MSK BITS(PIS_CH3_CON_SRCS_POSS,PIS_CH3_CON_SRCS_POSE) + +#define PIS_CH3_CON_MSIGS_POSS 0U +#define PIS_CH3_CON_MSIGS_POSE 3U +#define PIS_CH3_CON_MSIGS_MSK BITS(PIS_CH3_CON_MSIGS_POSS,PIS_CH3_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH4_CON register ************************/ + +#define PIS_CH4_CON_LEVEL_POS 31U +#define PIS_CH4_CON_LEVEL_MSK BIT(PIS_CH4_CON_LEVEL_POS) + +#define PIS_CH4_CON_PULSE_POS 30U +#define PIS_CH4_CON_PULSE_MSK BIT(PIS_CH4_CON_PULSE_POS) + +#define PIS_CH4_CON_SYNCSEL_POSS 24U +#define PIS_CH4_CON_SYNCSEL_POSE 26U +#define PIS_CH4_CON_SYNCSEL_MSK BITS(PIS_CH4_CON_SYNCSEL_POSS,PIS_CH4_CON_SYNCSEL_POSE) + +#define PIS_CH4_CON_TSCKS_POSS 18U +#define PIS_CH4_CON_TSCKS_POSE 19U +#define PIS_CH4_CON_TSCKS_MSK BITS(PIS_CH4_CON_TSCKS_POSS,PIS_CH4_CON_TSCKS_POSE) + +#define PIS_CH4_CON_EDGS_POSS 16U +#define PIS_CH4_CON_EDGS_POSE 17U +#define PIS_CH4_CON_EDGS_MSK BITS(PIS_CH4_CON_EDGS_POSS,PIS_CH4_CON_EDGS_POSE) + +#define PIS_CH4_CON_SRCS_POSS 8U +#define PIS_CH4_CON_SRCS_POSE 13U +#define PIS_CH4_CON_SRCS_MSK BITS(PIS_CH4_CON_SRCS_POSS,PIS_CH4_CON_SRCS_POSE) + +#define PIS_CH4_CON_MSIGS_POSS 0U +#define PIS_CH4_CON_MSIGS_POSE 3U +#define PIS_CH4_CON_MSIGS_MSK BITS(PIS_CH4_CON_MSIGS_POSS,PIS_CH4_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH5_CON register ************************/ + +#define PIS_CH5_CON_LEVEL_POS 31U +#define PIS_CH5_CON_LEVEL_MSK BIT(PIS_CH5_CON_LEVEL_POS) + +#define PIS_CH5_CON_PULSE_POS 30U +#define PIS_CH5_CON_PULSE_MSK BIT(PIS_CH5_CON_PULSE_POS) + +#define PIS_CH5_CON_SYNCSEL_POSS 24U +#define PIS_CH5_CON_SYNCSEL_POSE 26U +#define PIS_CH5_CON_SYNCSEL_MSK BITS(PIS_CH5_CON_SYNCSEL_POSS,PIS_CH5_CON_SYNCSEL_POSE) + +#define PIS_CH5_CON_TSCKS_POSS 18U +#define PIS_CH5_CON_TSCKS_POSE 19U +#define PIS_CH5_CON_TSCKS_MSK BITS(PIS_CH5_CON_TSCKS_POSS,PIS_CH5_CON_TSCKS_POSE) + +#define PIS_CH5_CON_EDGS_POSS 16U +#define PIS_CH5_CON_EDGS_POSE 17U +#define PIS_CH5_CON_EDGS_MSK BITS(PIS_CH5_CON_EDGS_POSS,PIS_CH5_CON_EDGS_POSE) + +#define PIS_CH5_CON_SRCS_POSS 8U +#define PIS_CH5_CON_SRCS_POSE 13U +#define PIS_CH5_CON_SRCS_MSK BITS(PIS_CH5_CON_SRCS_POSS,PIS_CH5_CON_SRCS_POSE) + +#define PIS_CH5_CON_MSIGS_POSS 0U +#define PIS_CH5_CON_MSIGS_POSE 3U +#define PIS_CH5_CON_MSIGS_MSK BITS(PIS_CH5_CON_MSIGS_POSS,PIS_CH5_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH6_CON register ************************/ + +#define PIS_CH6_CON_LEVEL_POS 31U +#define PIS_CH6_CON_LEVEL_MSK BIT(PIS_CH6_CON_LEVEL_POS) + +#define PIS_CH6_CON_PULSE_POS 30U +#define PIS_CH6_CON_PULSE_MSK BIT(PIS_CH6_CON_PULSE_POS) + +#define PIS_CH6_CON_SYNCSEL_POSS 24U +#define PIS_CH6_CON_SYNCSEL_POSE 26U +#define PIS_CH6_CON_SYNCSEL_MSK BITS(PIS_CH6_CON_SYNCSEL_POSS,PIS_CH6_CON_SYNCSEL_POSE) + +#define PIS_CH6_CON_TSCKS_POSS 18U +#define PIS_CH6_CON_TSCKS_POSE 19U +#define PIS_CH6_CON_TSCKS_MSK BITS(PIS_CH6_CON_TSCKS_POSS,PIS_CH6_CON_TSCKS_POSE) + +#define PIS_CH6_CON_EDGS_POSS 16U +#define PIS_CH6_CON_EDGS_POSE 17U +#define PIS_CH6_CON_EDGS_MSK BITS(PIS_CH6_CON_EDGS_POSS,PIS_CH6_CON_EDGS_POSE) + +#define PIS_CH6_CON_SRCS_POSS 8U +#define PIS_CH6_CON_SRCS_POSE 13U +#define PIS_CH6_CON_SRCS_MSK BITS(PIS_CH6_CON_SRCS_POSS,PIS_CH6_CON_SRCS_POSE) + +#define PIS_CH6_CON_MSIGS_POSS 0U +#define PIS_CH6_CON_MSIGS_POSE 3U +#define PIS_CH6_CON_MSIGS_MSK BITS(PIS_CH6_CON_MSIGS_POSS,PIS_CH6_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH7_CON register ************************/ + +#define PIS_CH7_CON_LEVEL_POS 31U +#define PIS_CH7_CON_LEVEL_MSK BIT(PIS_CH7_CON_LEVEL_POS) + +#define PIS_CH7_CON_PULSE_POS 30U +#define PIS_CH7_CON_PULSE_MSK BIT(PIS_CH7_CON_PULSE_POS) + +#define PIS_CH7_CON_SYNCSEL_POSS 24U +#define PIS_CH7_CON_SYNCSEL_POSE 26U +#define PIS_CH7_CON_SYNCSEL_MSK BITS(PIS_CH7_CON_SYNCSEL_POSS,PIS_CH7_CON_SYNCSEL_POSE) + +#define PIS_CH7_CON_TSCKS_POSS 18U +#define PIS_CH7_CON_TSCKS_POSE 19U +#define PIS_CH7_CON_TSCKS_MSK BITS(PIS_CH7_CON_TSCKS_POSS,PIS_CH7_CON_TSCKS_POSE) + +#define PIS_CH7_CON_EDGS_POSS 16U +#define PIS_CH7_CON_EDGS_POSE 17U +#define PIS_CH7_CON_EDGS_MSK BITS(PIS_CH7_CON_EDGS_POSS,PIS_CH7_CON_EDGS_POSE) + +#define PIS_CH7_CON_SRCS_POSS 8U +#define PIS_CH7_CON_SRCS_POSE 13U +#define PIS_CH7_CON_SRCS_MSK BITS(PIS_CH7_CON_SRCS_POSS,PIS_CH7_CON_SRCS_POSE) + +#define PIS_CH7_CON_MSIGS_POSS 0U +#define PIS_CH7_CON_MSIGS_POSE 3U +#define PIS_CH7_CON_MSIGS_MSK BITS(PIS_CH7_CON_MSIGS_POSS,PIS_CH7_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH_OER register ************************/ + +#define PIS_CH_OER_CH7OE_POS 7U +#define PIS_CH_OER_CH7OE_MSK BIT(PIS_CH_OER_CH7OE_POS) + +#define PIS_CH_OER_CH6OE_POS 6U +#define PIS_CH_OER_CH6OE_MSK BIT(PIS_CH_OER_CH6OE_POS) + +#define PIS_CH_OER_CH5OE_POS 5U +#define PIS_CH_OER_CH5OE_MSK BIT(PIS_CH_OER_CH5OE_POS) + +#define PIS_CH_OER_CH4OE_POS 4U +#define PIS_CH_OER_CH4OE_MSK BIT(PIS_CH_OER_CH4OE_POS) + +#define PIS_CH_OER_CH3OE_POS 3U +#define PIS_CH_OER_CH3OE_MSK BIT(PIS_CH_OER_CH3OE_POS) + +#define PIS_CH_OER_CH2OE_POS 2U +#define PIS_CH_OER_CH2OE_MSK BIT(PIS_CH_OER_CH2OE_POS) + +#define PIS_CH_OER_CH1OE_POS 1U +#define PIS_CH_OER_CH1OE_MSK BIT(PIS_CH_OER_CH1OE_POS) + +#define PIS_CH_OER_CH0OE_POS 0U +#define PIS_CH_OER_CH0OE_MSK BIT(PIS_CH_OER_CH0OE_POS) + +/****************** Bit definition for PIS_TAR_CON0 register ************************/ + +#define PIS_TAR_CON0_TIM3_ETRIN_SEL_POS 28U +#define PIS_TAR_CON0_TIM3_ETRIN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_ETRIN_SEL_POS) + +#define PIS_TAR_CON0_TIM3_CH4IN_SEL_POS 27U +#define PIS_TAR_CON0_TIM3_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH4IN_SEL_POS) + +#define PIS_TAR_CON0_TIM3_CH3IN_SEL_POS 26U +#define PIS_TAR_CON0_TIM3_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH3IN_SEL_POS) + +#define PIS_TAR_CON0_TIM3_CH2IN_SEL_POS 25U +#define PIS_TAR_CON0_TIM3_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM3_CH1IN_SEL_POS 24U +#define PIS_TAR_CON0_TIM3_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH1IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_ETRIN_SEL_POS 20U +#define PIS_TAR_CON0_TIM2_ETRIN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_ETRIN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH4IN_SEL_POS 19U +#define PIS_TAR_CON0_TIM2_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH4IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH3IN_SEL_POS 18U +#define PIS_TAR_CON0_TIM2_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH3IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH2IN_SEL_POS 17U +#define PIS_TAR_CON0_TIM2_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH1IN_SEL_POS 16U +#define PIS_TAR_CON0_TIM2_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH1IN_SEL_POS) + +#define PIS_TAR_CON0_TIM1_ETRIN_SEL_POS 12U +#define PIS_TAR_CON0_TIM1_ETRIN_SEL_MSK BIT(PIS_TAR_CON0_TIM1_ETRIN_SEL_POS) + +#define PIS_TAR_CON0_TIM1_CH4IN_SEL_POS 11U +#define PIS_TAR_CON0_TIM1_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM1_CH4IN_SEL_POS) + +#define PIS_TAR_CON0_TIM1_CH3IN_SEL_POS 10U +#define PIS_TAR_CON0_TIM1_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM1_CH3IN_SEL_POS) + +#define PIS_TAR_CON0_TIM1_CH2IN_SEL_POS 9U +#define PIS_TAR_CON0_TIM1_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM1_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM1_CH1IN_SEL_POS 8U +#define PIS_TAR_CON0_TIM1_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM1_CH1IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_ETRIN_SEL_POS 5U +#define PIS_TAR_CON0_TIM0_ETRIN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_ETRIN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_BRKIN_SEL_POS 4U +#define PIS_TAR_CON0_TIM0_BRKIN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_BRKIN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH4IN_SEL_POS 3U +#define PIS_TAR_CON0_TIM0_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH4IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH3IN_SEL_POS 2U +#define PIS_TAR_CON0_TIM0_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH3IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH2IN_SEL_POS 1U +#define PIS_TAR_CON0_TIM0_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH1IN_SEL_POS 0U +#define PIS_TAR_CON0_TIM0_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH1IN_SEL_POS) + +/****************** Bit definition for PIS_TAR_CON1 register ************************/ + +#define PIS_TAR_CON1_SPI1_CLK_SEL_POS 15U +#define PIS_TAR_CON1_SPI1_CLK_SEL_MSK BIT(PIS_TAR_CON1_SPI1_CLK_SEL_POS) + +#define PIS_TAR_CON1_SPI1_RX_SEL_POS 14U +#define PIS_TAR_CON1_SPI1_RX_SEL_MSK BIT(PIS_TAR_CON1_SPI1_RX_SEL_POS) + +#define PIS_TAR_CON1_SPI0_CLK_SEL_POS 13U +#define PIS_TAR_CON1_SPI0_CLK_SEL_MSK BIT(PIS_TAR_CON1_SPI0_CLK_SEL_POS) + +#define PIS_TAR_CON1_SPI0_RX_SEL_POS 12U +#define PIS_TAR_CON1_SPI0_RX_SEL_MSK BIT(PIS_TAR_CON1_SPI0_RX_SEL_POS) + +#define PIS_TAR_CON1_UART4_RXD_SEL_POS 4U +#define PIS_TAR_CON1_UART4_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART4_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART3_RXD_SEL_POS 3U +#define PIS_TAR_CON1_UART3_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART3_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART2_RXD_SEL_POS 2U +#define PIS_TAR_CON1_UART2_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART2_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART1_RXD_SEL_POS 1U +#define PIS_TAR_CON1_UART1_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART1_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART0_RXD_SEL_POS 0U +#define PIS_TAR_CON1_UART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART0_RXD_SEL_POS) + +/****************** Bit definition for PIS_UART0_TXMCR register ************************/ + +#define PIS_UART0_TXMCR_TXMLVLS_POS 8U +#define PIS_UART0_TXMCR_TXMLVLS_MSK BIT(PIS_UART0_TXMCR_TXMLVLS_POS) + +#define PIS_UART0_TXMCR_TXMSS_POSS 4U +#define PIS_UART0_TXMCR_TXMSS_POSE 7U +#define PIS_UART0_TXMCR_TXMSS_MSK BITS(PIS_UART0_TXMCR_TXMSS_POSS,PIS_UART0_TXMCR_TXMSS_POSE) + +#define PIS_UART0_TXMCR_TXSIGS_POSS 0U +#define PIS_UART0_TXMCR_TXSIGS_POSE 3U +#define PIS_UART0_TXMCR_TXSIGS_MSK BITS(PIS_UART0_TXMCR_TXSIGS_POSS,PIS_UART0_TXMCR_TXSIGS_POSE) + +/****************** Bit definition for PIS_UART1_TXMCR register ************************/ + +#define PIS_UART1_TXMCR_TXMLVLS_POS 8U +#define PIS_UART1_TXMCR_TXMLVLS_MSK BIT(PIS_UART1_TXMCR_TXMLVLS_POS) + +#define PIS_UART1_TXMCR_TXMSS_POSS 4U +#define PIS_UART1_TXMCR_TXMSS_POSE 7U +#define PIS_UART1_TXMCR_TXMSS_MSK BITS(PIS_UART1_TXMCR_TXMSS_POSS,PIS_UART1_TXMCR_TXMSS_POSE) + +#define PIS_UART1_TXMCR_TXSIGS_POSS 0U +#define PIS_UART1_TXMCR_TXSIGS_POSE 3U +#define PIS_UART1_TXMCR_TXSIGS_MSK BITS(PIS_UART1_TXMCR_TXSIGS_POSS,PIS_UART1_TXMCR_TXSIGS_POSE) + +/****************** Bit definition for PIS_UART2_TXMCR register ************************/ + +#define PIS_UART2_TXMCR_TXMLVLS_POS 8U +#define PIS_UART2_TXMCR_TXMLVLS_MSK BIT(PIS_UART2_TXMCR_TXMLVLS_POS) + +#define PIS_UART2_TXMCR_TXMSS_POSS 4U +#define PIS_UART2_TXMCR_TXMSS_POSE 7U +#define PIS_UART2_TXMCR_TXMSS_MSK BITS(PIS_UART2_TXMCR_TXMSS_POSS,PIS_UART2_TXMCR_TXMSS_POSE) + +#define PIS_UART2_TXMCR_TXSIGS_POSS 0U +#define PIS_UART2_TXMCR_TXSIGS_POSE 3U +#define PIS_UART2_TXMCR_TXSIGS_MSK BITS(PIS_UART2_TXMCR_TXSIGS_POSS,PIS_UART2_TXMCR_TXSIGS_POSE) + +/****************** Bit definition for PIS_UART3_TXMCR register ************************/ + +#define PIS_UART3_TXMCR_TXMLVLS_POS 8U +#define PIS_UART3_TXMCR_TXMLVLS_MSK BIT(PIS_UART3_TXMCR_TXMLVLS_POS) + +#define PIS_UART3_TXMCR_TXMSS_POSS 4U +#define PIS_UART3_TXMCR_TXMSS_POSE 7U +#define PIS_UART3_TXMCR_TXMSS_MSK BITS(PIS_UART3_TXMCR_TXMSS_POSS,PIS_UART3_TXMCR_TXMSS_POSE) + +#define PIS_UART3_TXMCR_TXSIGS_POSS 0U +#define PIS_UART3_TXMCR_TXSIGS_POSE 3U +#define PIS_UART3_TXMCR_TXSIGS_MSK BITS(PIS_UART3_TXMCR_TXSIGS_POSS,PIS_UART3_TXMCR_TXSIGS_POSE) + +/****************** Bit definition for PIS_UART4_TXMCR register ************************/ + +#define PIS_UART4_TXMCR_TXMLVLS_POS 8U +#define PIS_UART4_TXMCR_TXMLVLS_MSK BIT(PIS_UART4_TXMCR_TXMLVLS_POS) + +#define PIS_UART4_TXMCR_TXMSS_POSS 4U +#define PIS_UART4_TXMCR_TXMSS_POSE 7U +#define PIS_UART4_TXMCR_TXMSS_MSK BITS(PIS_UART4_TXMCR_TXMSS_POSS,PIS_UART4_TXMCR_TXMSS_POSE) + +#define PIS_UART4_TXMCR_TXSIGS_POSS 0U +#define PIS_UART4_TXMCR_TXSIGS_POSE 3U +#define PIS_UART4_TXMCR_TXSIGS_MSK BITS(PIS_UART4_TXMCR_TXSIGS_POSS,PIS_UART4_TXMCR_TXSIGS_POSE) + +/* Exported Types ------------------------------------------------------------ */ + +typedef struct +{ + __IO uint32_t CH_CON[8]; + uint32_t RESERVED0[8] ; + __IO uint32_t CH_OER; + __IO uint32_t TAR_CON0; + __IO uint32_t TAR_CON1; + uint32_t RESERVED1[5] ; + __IO uint32_t UART0_TXMCR; + __IO uint32_t UART1_TXMCR; + __IO uint32_t UART2_TXMCR; + __IO uint32_t UART3_TXMCR; + __IO uint32_t UART4_TXMCR; +} PIS_TypeDef; + +#endif /* __REG_PIS_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_pmu.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_pmu.h new file mode 100644 index 0000000000..f19bf1553d --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_pmu.h @@ -0,0 +1,131 @@ +/********************************************************************************** + * + * @file reg_pmu.h + * @brief PMU Head File + * + * @date 15 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 15 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_PMU_H__ +#define __REG_PMU_H__ + +/* Includes ------------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ +/* Exported Macros ----------------------------------------------------------- */ + +/****************** Bit definition for PMU_CR register ************************/ + +#define PMU_CR_WKEVNSEL_POSS 24U +#define PMU_CR_WKEVNSEL_POSE 28U +#define PMU_CR_WKEVNSEL_MSK BITS(PMU_CR_WKEVNSEL_POSS,PMU_CR_WKEVNSEL_POSE) + +#define PMU_CR_FSTOP_POS 23U +#define PMU_CR_FSTOP_MSK BIT(PMU_CR_FSTOP_POS) + +#define PMU_CR_BGSTOP_POS 21U +#define PMU_CR_BGSTOP_MSK BIT(PMU_CR_BGSTOP_POS) + +#define PMU_CR_LPSTOP_POS 20U +#define PMU_CR_LPSTOP_MSK BIT(PMU_CR_LPSTOP_POS) + +#define PMU_CR_LPRUN_POS 19U +#define PMU_CR_LPRUN_MSK BIT(PMU_CR_LPRUN_POS) + +#define PMU_CR_LPVS_POSS 16U +#define PMU_CR_LPVS_POSE 17U +#define PMU_CR_LPVS_MSK BITS(PMU_CR_LPVS_POSS,PMU_CR_LPVS_POSE) + +#define PMU_CR_VROSCEN_POS 7U +#define PMU_CR_VROSCEN_MSK BIT(PMU_CR_VROSCEN_POS) + +#define PMU_CR_NORRTNEN_POS 6U +#define PMU_CR_NORRTNEN_MSK BIT(PMU_CR_NORRTNEN_POS) + +#define PMU_CR_STPRTNEN_POS 5U +#define PMU_CR_STPRTNEN_MSK BIT(PMU_CR_STPRTNEN_POS) + +#define PMU_CR_CWUF_POS 2U +#define PMU_CR_CWUF_MSK BIT(PMU_CR_CWUF_POS) + +#define PMU_CR_LPM_POSS 0U +#define PMU_CR_LPM_POSE 1U +#define PMU_CR_LPM_MSK BITS(PMU_CR_LPM_POSS,PMU_CR_LPM_POSE) + +/****************** Bit definition for PMU_SR register ************************/ + +#define PMU_SR_WUF_POS 0U +#define PMU_SR_WUF_MSK BIT(PMU_SR_WUF_POS) + +/****************** Bit definition for PMU_LVDCR register ************************/ + +#define PMU_LVDCR_LVDO_POS 15U +#define PMU_LVDCR_LVDO_MSK BIT(PMU_LVDCR_LVDO_POS) + +#define PMU_LVDCR_LVDFLT_POS 11U +#define PMU_LVDCR_LVDFLT_MSK BIT(PMU_LVDCR_LVDFLT_POS) + +#define PMU_LVDCR_LVDIFS_POSS 8U +#define PMU_LVDCR_LVDIFS_POSE 10U +#define PMU_LVDCR_LVDIFS_MSK BITS(PMU_LVDCR_LVDIFS_POSS,PMU_LVDCR_LVDIFS_POSE) + +#define PMU_LVDCR_LVDS_POSS 4U +#define PMU_LVDCR_LVDS_POSE 7U +#define PMU_LVDCR_LVDS_MSK BITS(PMU_LVDCR_LVDS_POSS,PMU_LVDCR_LVDS_POSE) + +#define PMU_LVDCR_LVDCIF_POS 3U +#define PMU_LVDCR_LVDCIF_MSK BIT(PMU_LVDCR_LVDCIF_POS) + +#define PMU_LVDCR_LVDIF_POS 2U +#define PMU_LVDCR_LVDIF_MSK BIT(PMU_LVDCR_LVDIF_POS) + +#define PMU_LVDCR_LVDIE_POS 1U +#define PMU_LVDCR_LVDIE_MSK BIT(PMU_LVDCR_LVDIE_POS) + +#define PMU_LVDCR_LVDEN_POS 0U +#define PMU_LVDCR_LVDEN_MSK BIT(PMU_LVDCR_LVDEN_POS) + +/****************** Bit definition for PMU_TWUR register ************************/ + +#define PMU_TWUR_TWU_POSS 0U +#define PMU_TWUR_TWU_POSE 11U +#define PMU_TWUR_TWU_MSK BITS(PMU_TWUR_TWU_POSS,PMU_TWUR_TWU_POSE) + +/* Exported Types ------------------------------------------------------------ */ + +typedef struct +{ + __IO uint32_t CR; + __I uint32_t SR; + __IO uint32_t LVDCR; + uint32_t RESERVED0 ; + __IO uint32_t TWUR; +} PMU_TypeDef; + +#endif /* __REG_PMU_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_rmu.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_rmu.h new file mode 100644 index 0000000000..ca18adb501 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_rmu.h @@ -0,0 +1,224 @@ +/********************************************************************************** + * + * @file reg_rmu.h + * @brief RMU Head File + * + * @date 16 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 16 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_RMU_H__ +#define __REG_RMU_H__ + +/* Includes ------------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ +/* Exported Macros ----------------------------------------------------------- */ + +/****************** Bit definition for RMU_CR register ************************/ + +#define RMU_CR_BORVS_POSS 4U +#define RMU_CR_BORVS_POSE 6U +#define RMU_CR_BORVS_MSK BITS(RMU_CR_BORVS_POSS,RMU_CR_BORVS_POSE) + +#define RMU_CR_BORFLT_POSS 1U +#define RMU_CR_BORFLT_POSE 3U +#define RMU_CR_BORFLT_MSK BITS(RMU_CR_BORFLT_POSS,RMU_CR_BORFLT_POSE) + +#define RMU_CR_BOREN_POS 0U +#define RMU_CR_BOREN_MSK BIT(RMU_CR_BOREN_POS) + +/****************** Bit definition for RMU_RSTSR register ************************/ + +#define RMU_RSTSR_CFGERR_POS 16U +#define RMU_RSTSR_CFGERR_MSK BIT(RMU_RSTSR_CFGERR_POS) + +#define RMU_RSTSR_CFG_POS 10U +#define RMU_RSTSR_CFG_MSK BIT(RMU_RSTSR_CFG_POS) + +#define RMU_RSTSR_CPU_POS 9U +#define RMU_RSTSR_CPU_MSK BIT(RMU_RSTSR_CPU_POS) + +#define RMU_RSTSR_MCU_POS 8U +#define RMU_RSTSR_MCU_MSK BIT(RMU_RSTSR_MCU_POS) + +#define RMU_RSTSR_CHIP_POS 7U +#define RMU_RSTSR_CHIP_MSK BIT(RMU_RSTSR_CHIP_POS) + +#define RMU_RSTSR_LOCKUP_POS 6U +#define RMU_RSTSR_LOCKUP_MSK BIT(RMU_RSTSR_LOCKUP_POS) + +#define RMU_RSTSR_WWDT_POS 5U +#define RMU_RSTSR_WWDT_MSK BIT(RMU_RSTSR_WWDT_POS) + +#define RMU_RSTSR_IWDT_POS 4U +#define RMU_RSTSR_IWDT_MSK BIT(RMU_RSTSR_IWDT_POS) + +#define RMU_RSTSR_NMRST_POS 3U +#define RMU_RSTSR_NMRST_MSK BIT(RMU_RSTSR_NMRST_POS) + +#define RMU_RSTSR_BOR_POS 2U +#define RMU_RSTSR_BOR_MSK BIT(RMU_RSTSR_BOR_POS) + +#define RMU_RSTSR_WAKEUP_POS 1U +#define RMU_RSTSR_WAKEUP_MSK BIT(RMU_RSTSR_WAKEUP_POS) + +#define RMU_RSTSR_POR_POS 0U +#define RMU_RSTSR_POR_MSK BIT(RMU_RSTSR_POR_POS) + +/****************** Bit definition for RMU_CRSTSR register ************************/ + +#define RMU_CRSTSR_CFG_POS 10U +#define RMU_CRSTSR_CFG_MSK BIT(RMU_CRSTSR_CFG_POS) + +#define RMU_CRSTSR_CPU_POS 9U +#define RMU_CRSTSR_CPU_MSK BIT(RMU_CRSTSR_CPU_POS) + +#define RMU_CRSTSR_MCU_POS 8U +#define RMU_CRSTSR_MCU_MSK BIT(RMU_CRSTSR_MCU_POS) + +#define RMU_CRSTSR_CHIP_POS 7U +#define RMU_CRSTSR_CHIP_MSK BIT(RMU_CRSTSR_CHIP_POS) + +#define RMU_CRSTSR_LOCKUP_POS 6U +#define RMU_CRSTSR_LOCKUP_MSK BIT(RMU_CRSTSR_LOCKUP_POS) + +#define RMU_CRSTSR_WWDT_POS 5U +#define RMU_CRSTSR_WWDT_MSK BIT(RMU_CRSTSR_WWDT_POS) + +#define RMU_CRSTSR_IWDT_POS 4U +#define RMU_CRSTSR_IWDT_MSK BIT(RMU_CRSTSR_IWDT_POS) + +#define RMU_CRSTSR_NMRST_POS 3U +#define RMU_CRSTSR_NMRST_MSK BIT(RMU_CRSTSR_NMRST_POS) + +#define RMU_CRSTSR_BOR_POS 2U +#define RMU_CRSTSR_BOR_MSK BIT(RMU_CRSTSR_BOR_POS) + +#define RMU_CRSTSR_POR_POS 0U +#define RMU_CRSTSR_POR_MSK BIT(RMU_CRSTSR_POR_POS) + +/****************** Bit definition for RMU_AHB1RSTR register ************************/ +#define RMU_AHB1RSTR_CSURST_POS 7U +#define RMU_AHB1RSTR_CSURST_MSK BIT(RMU_AHB1RSTR_CSURST_POS) + +#define RMU_AHB1RSTR_USBRST_POS 6U +#define RMU_AHB1RSTR_USBRST_MSK BIT(RMU_AHB1RSTR_USBRST_POS) + +#define RMU_AHB1RSTR_PISRST_POS 5U +#define RMU_AHB1RSTR_PISRST_MSK BIT(RMU_AHB1RSTR_PISRST_POS) + +#define RMU_AHB1RSTR_DMARST_POS 2U +#define RMU_AHB1RSTR_DMARST_MSK BIT(RMU_AHB1RSTR_DMARST_POS) + +#define RMU_AHB1RSTR_CRCRST_POS 1U +#define RMU_AHB1RSTR_CRCRST_MSK BIT(RMU_AHB1RSTR_CRCRST_POS) + +#define RMU_AHB1RSTR_GPIORST_POS 0U +#define RMU_AHB1RSTR_GPIORST_MSK BIT(RMU_AHB1RSTR_GPIORST_POS) + +/****************** Bit definition for RMU_AHB2RSTR register ************************/ + +#define RMU_AHB2RSTR_CPURST_POS 1U +#define RMU_AHB2RSTR_CPURST_MSK BIT(RMU_AHB2RSTR_CPURST_POS) + +#define RMU_AHB2RSTR_CHIPRST_POS 0U +#define RMU_AHB2RSTR_CHIPRST_MSK BIT(RMU_AHB2RSTR_CHIPRST_POS) + +/****************** Bit definition for RMU_APBRSTR register ************************/ + +#define RMU_APBRSTR_ADCRST_POS 25U +#define RMU_APBRSTR_ADCRST_MSK BIT(RMU_APBRSTR_ADCRST_POS) + +#define RMU_APBRSTR_DBGCONRST_POS 24U +#define RMU_APBRSTR_DBGCONRST_MSK BIT(RMU_APBRSTR_DBGCONRST_POS) + +#define RMU_APBRSTR_IWDTRST_POS 23U +#define RMU_APBRSTR_IWDTRST_MSK BIT(RMU_APBRSTR_IWDTRST_POS) + +#define RMU_APBRSTR_WWDTRST_POS 22U +#define RMU_APBRSTR_WWDTRST_MSK BIT(RMU_APBRSTR_WWDTRST_POS) + +#define RMU_APBRSTR_I2C1RST_POS 21U +#define RMU_APBRSTR_I2C1RST_MSK BIT(RMU_APBRSTR_I2C1RST_POS) + +#define RMU_APBRSTR_I2C0RST_POS 20U +#define RMU_APBRSTR_I2C0RST_MSK BIT(RMU_APBRSTR_I2C0RST_POS) + +#define RMU_APBRSTR_SPI1RST_POS 17U +#define RMU_APBRSTR_SPI1RST_MSK BIT(RMU_APBRSTR_SPI1RST_POS) + +#define RMU_APBRSTR_SPI0RST_POS 16U +#define RMU_APBRSTR_SPI0RST_MSK BIT(RMU_APBRSTR_SPI0RST_POS) + +#define RMU_APBRSTR_CUART2RST_POS 14U +#define RMU_APBRSTR_CUART2RST_MSK BIT(RMU_APBRSTR_CUART2RST_POS) + +#define RMU_APBRSTR_CUART1RST_POS 13U +#define RMU_APBRSTR_CUART1RST_MSK BIT(RMU_APBRSTR_CUART1RST_POS) + +#define RMU_APBRSTR_CUART0RST_POS 12U +#define RMU_APBRSTR_CUART0RST_MSK BIT(RMU_APBRSTR_CUART0RST_POS) + +#define RMU_APBRSTR_EUART1RST_POS 9U +#define RMU_APBRSTR_EUART1RST_MSK BIT(RMU_APBRSTR_EUART1RST_POS) + +#define RMU_APBRSTR_EUART0RST_POS 8U +#define RMU_APBRSTR_EUART0RST_MSK BIT(RMU_APBRSTR_EUART0RST_POS) + +#define RMU_APBRSTR_GP16C4T2RST_POS 4U +#define RMU_APBRSTR_GP16C4T2RST_MSK BIT(RMU_APBRSTR_GP16C4T2RST_POS) + +#define RMU_APBRSTR_GP16C4T1RST_POS 3U +#define RMU_APBRSTR_GP16C4T1RST_MSK BIT(RMU_APBRSTR_GP16C4T1RST_POS) + +#define RMU_APBRSTR_GP16C4T0RST_POS 2U +#define RMU_APBRSTR_GP16C4T0RST_MSK BIT(RMU_APBRSTR_GP16C4T0RST_POS) + +#define RMU_APBRSTR_BS16T0RST_POS 1U +#define RMU_APBRSTR_BS16T0RST_MSK BIT(RMU_APBRSTR_BS16T0RST_POS) + +#define RMU_APBRSTR_AD16C4T0RST_POS 0U +#define RMU_APBRSTR_AD16C4T0RST_MSK BIT(RMU_APBRSTR_AD16C4T0RST_POS) + +/* Exported Types ------------------------------------------------------------ */ + +typedef struct +{ + __IO uint32_t CR; + uint32_t RESERVED0[3] ; + __I uint32_t RSTSR; + __O uint32_t CRSTSR; + uint32_t RESERVED1[2] ; + __IO uint32_t AHB1RSTR; + __IO uint32_t AHB2RSTR; + uint32_t RESERVED2[2] ; + __IO uint32_t APBRSTR; +} RMU_TypeDef; + +#endif /* __REG_RMU_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_spi.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_spi.h new file mode 100644 index 0000000000..33a2e0d0d9 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_spi.h @@ -0,0 +1,476 @@ +/********************************************************************************** + * + * @file reg_spi.h + * @brief SPI Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_SPI_H__ +#define __REG_SPI_H__ + +/* Includes ------------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ +/* Exported Macros ----------------------------------------------------------- */ + +/****************** Bit definition for SPI_CON1 register ************************/ + +#define SPI_CON1_BIDEN_POS 15U +#define SPI_CON1_BIDEN_MSK BIT(SPI_CON1_BIDEN_POS) + +#define SPI_CON1_BIDOEN_POS 14U +#define SPI_CON1_BIDOEN_MSK BIT(SPI_CON1_BIDOEN_POS) + +#define SPI_CON1_CRCEN_POS 13U +#define SPI_CON1_CRCEN_MSK BIT(SPI_CON1_CRCEN_POS) + +#define SPI_CON1_NXTCRC_POS 12U +#define SPI_CON1_NXTCRC_MSK BIT(SPI_CON1_NXTCRC_POS) + +#define SPI_CON1_FLEN_POS 11U +#define SPI_CON1_FLEN_MSK BIT(SPI_CON1_FLEN_POS) + +#define SPI_CON1_RXO_POS 10U +#define SPI_CON1_RXO_MSK BIT(SPI_CON1_RXO_POS) + +#define SPI_CON1_SSEN_POS 9U +#define SPI_CON1_SSEN_MSK BIT(SPI_CON1_SSEN_POS) + +#define SPI_CON1_SSOUT_POS 8U +#define SPI_CON1_SSOUT_MSK BIT(SPI_CON1_SSOUT_POS) + +#define SPI_CON1_LSBFST_POS 7U +#define SPI_CON1_LSBFST_MSK BIT(SPI_CON1_LSBFST_POS) + +#define SPI_CON1_SPIEN_POS 6U +#define SPI_CON1_SPIEN_MSK BIT(SPI_CON1_SPIEN_POS) + +#define SPI_CON1_BAUD_POSS 3U +#define SPI_CON1_BAUD_POSE 5U +#define SPI_CON1_BAUD_MSK BITS(SPI_CON1_BAUD_POSS,SPI_CON1_BAUD_POSE) + +#define SPI_CON1_MSTREN_POS 2U +#define SPI_CON1_MSTREN_MSK BIT(SPI_CON1_MSTREN_POS) + +#define SPI_CON1_CPOL_POS 1U +#define SPI_CON1_CPOL_MSK BIT(SPI_CON1_CPOL_POS) + +#define SPI_CON1_CPHA_POS 0U +#define SPI_CON1_CPHA_MSK BIT(SPI_CON1_CPHA_POS) + +/****************** Bit definition for SPI_CON2 register ************************/ + +#define SPI_CON2_RXFTH_POSS 14U +#define SPI_CON2_RXFTH_POSE 15U +#define SPI_CON2_RXFTH_MSK BITS(SPI_CON2_RXFTH_POSS,SPI_CON2_RXFTH_POSE) + +#define SPI_CON2_TXFTH_POSS 12U +#define SPI_CON2_TXFTH_POSE 13U +#define SPI_CON2_TXFTH_MSK BITS(SPI_CON2_TXFTH_POSS,SPI_CON2_TXFTH_POSE) + +#define SPI_CON2_FRF_POS 4U +#define SPI_CON2_FRF_MSK BIT(SPI_CON2_FRF_POS) + +#define SPI_CON2_NSSP_POS 3U +#define SPI_CON2_NSSP_MSK BIT(SPI_CON2_NSSP_POS) + +#define SPI_CON2_NSSOE_POS 2U +#define SPI_CON2_NSSOE_MSK BIT(SPI_CON2_NSSOE_POS) + +#define SPI_CON2_TXDMA_POS 1U +#define SPI_CON2_TXDMA_MSK BIT(SPI_CON2_TXDMA_POS) + +#define SPI_CON2_RXDMA_POS 0U +#define SPI_CON2_RXDMA_MSK BIT(SPI_CON2_RXDMA_POS) + +/****************** Bit definition for SPI_STAT register ************************/ + +#define SPI_STAT_RXFLV_POSS 24U +#define SPI_STAT_RXFLV_POSE 28U +#define SPI_STAT_RXFLV_MSK BITS(SPI_STAT_RXFLV_POSS,SPI_STAT_RXFLV_POSE) + +#define SPI_STAT_TXFLV_POSS 16U +#define SPI_STAT_TXFLV_POSE 20U +#define SPI_STAT_TXFLV_MSK BITS(SPI_STAT_TXFLV_POSS,SPI_STAT_TXFLV_POSE) + +#define SPI_STAT_BUSY_POS 15U +#define SPI_STAT_BUSY_MSK BIT(SPI_STAT_BUSY_POS) + +#define SPI_STAT_CHSIDE_POS 14U +#define SPI_STAT_CHSIDE_MSK BIT(SPI_STAT_CHSIDE_POS) + +#define SPI_STAT_RXTH_POS 12U +#define SPI_STAT_RXTH_MSK BIT(SPI_STAT_RXTH_POS) + +#define SPI_STAT_RXUD_POS 11U +#define SPI_STAT_RXUD_MSK BIT(SPI_STAT_RXUD_POS) + +#define SPI_STAT_RXOV_POS 10U +#define SPI_STAT_RXOV_MSK BIT(SPI_STAT_RXOV_POS) + +#define SPI_STAT_RXF_POS 9U +#define SPI_STAT_RXF_MSK BIT(SPI_STAT_RXF_POS) + +#define SPI_STAT_RXNE_POS 8U +#define SPI_STAT_RXNE_MSK BIT(SPI_STAT_RXNE_POS) + +#define SPI_STAT_TXTH_POS 4U +#define SPI_STAT_TXTH_MSK BIT(SPI_STAT_TXTH_POS) + +#define SPI_STAT_TXUD_POS 3U +#define SPI_STAT_TXUD_MSK BIT(SPI_STAT_TXUD_POS) + +#define SPI_STAT_TXOV_POS 2U +#define SPI_STAT_TXOV_MSK BIT(SPI_STAT_TXOV_POS) + +#define SPI_STAT_TXF_POS 1U +#define SPI_STAT_TXF_MSK BIT(SPI_STAT_TXF_POS) + +#define SPI_STAT_TXE_POS 0U +#define SPI_STAT_TXE_MSK BIT(SPI_STAT_TXE_POS) + +/****************** Bit definition for SPI_DATA register ************************/ + +#define SPI_DATA_DATA_POSS 0U +#define SPI_DATA_DATA_POSE 15U +#define SPI_DATA_DATA_MSK BITS(SPI_DATA_DATA_POSS,SPI_DATA_DATA_POSE) + +/****************** Bit definition for SPI_CRCPOLY register ************************/ + +#define SPI_CRCPOLY_CRCPOLY_POSS 0U +#define SPI_CRCPOLY_CRCPOLY_POSE 15U +#define SPI_CRCPOLY_CRCPOLY_MSK BITS(SPI_CRCPOLY_CRCPOLY_POSS,SPI_CRCPOLY_CRCPOLY_POSE) + +/****************** Bit definition for SPI_RXCRC register ************************/ + +#define SPI_RXCRC_RXCRC_POSS 0U +#define SPI_RXCRC_RXCRC_POSE 15U +#define SPI_RXCRC_RXCRC_MSK BITS(SPI_RXCRC_RXCRC_POSS,SPI_RXCRC_RXCRC_POSE) + +/****************** Bit definition for SPI_TXCRC register ************************/ + +#define SPI_TXCRC_TXCRC_POSS 0U +#define SPI_TXCRC_TXCRC_POSE 15U +#define SPI_TXCRC_TXCRC_MSK BITS(SPI_TXCRC_TXCRC_POSS,SPI_TXCRC_TXCRC_POSE) + +/****************** Bit definition for SPI_I2SCFG register ************************/ + +#define SPI_I2SCFG_I2SMOD_POS 12U +#define SPI_I2SCFG_I2SMOD_MSK BIT(SPI_I2SCFG_I2SMOD_POS) + +#define SPI_I2SCFG_I2SE_POS 11U +#define SPI_I2SCFG_I2SE_MSK BIT(SPI_I2SCFG_I2SE_POS) + +#define SPI_I2SCFG_I2SCFG_POSS 8U +#define SPI_I2SCFG_I2SCFG_POSE 10U +#define SPI_I2SCFG_I2SCFG_MSK BITS(SPI_I2SCFG_I2SCFG_POSS,SPI_I2SCFG_I2SCFG_POSE) + +#define SPI_I2SCFG_PCMSYNC_POS 7U +#define SPI_I2SCFG_PCMSYNC_MSK BIT(SPI_I2SCFG_PCMSYNC_POS) + +#define SPI_I2SCFG_I2SSTD_POSS 4U +#define SPI_I2SCFG_I2SSTD_POSE 5U +#define SPI_I2SCFG_I2SSTD_MSK BITS(SPI_I2SCFG_I2SSTD_POSS,SPI_I2SCFG_I2SSTD_POSE) + +#define SPI_I2SCFG_CKPOL_POS 3U +#define SPI_I2SCFG_CKPOL_MSK BIT(SPI_I2SCFG_CKPOL_POS) + +#define SPI_I2SCFG_DATLEN_POSS 1U +#define SPI_I2SCFG_DATLEN_POSE 2U +#define SPI_I2SCFG_DATLEN_MSK BITS(SPI_I2SCFG_DATLEN_POSS,SPI_I2SCFG_DATLEN_POSE) + +#define SPI_I2SCFG_CHLEN_POS 0U +#define SPI_I2SCFG_CHLEN_MSK BIT(SPI_I2SCFG_CHLEN_POS) + +/****************** Bit definition for SPI_I2SPR register ************************/ + +#define SPI_I2SPR_EXTCKEN_POS 10U +#define SPI_I2SPR_EXTCKEN_MSK BIT(SPI_I2SPR_EXTCKEN_POS) + +#define SPI_I2SPR_MCKOE_POS 9U +#define SPI_I2SPR_MCKOE_MSK BIT(SPI_I2SPR_MCKOE_POS) + +#define SPI_I2SPR_ODD_POS 8U +#define SPI_I2SPR_ODD_MSK BIT(SPI_I2SPR_ODD_POS) + +#define SPI_I2SPR_I2SDIV_POSS 0U +#define SPI_I2SPR_I2SDIV_POSE 7U +#define SPI_I2SPR_I2SDIV_MSK BITS(SPI_I2SPR_I2SDIV_POSS,SPI_I2SPR_I2SDIV_POSE) + +/****************** Bit definition for SPI_IER register ************************/ + +#define SPI_IER_FRE_POS 18U +#define SPI_IER_FRE_MSK BIT(SPI_IER_FRE_POS) + +#define SPI_IER_MODF_POS 17U +#define SPI_IER_MODF_MSK BIT(SPI_IER_MODF_POS) + +#define SPI_IER_CRCERR_POS 16U +#define SPI_IER_CRCERR_MSK BIT(SPI_IER_CRCERR_POS) + +#define SPI_IER_RXTH_POS 12U +#define SPI_IER_RXTH_MSK BIT(SPI_IER_RXTH_POS) + +#define SPI_IER_RXUD_POS 11U +#define SPI_IER_RXUD_MSK BIT(SPI_IER_RXUD_POS) + +#define SPI_IER_RXOV_POS 10U +#define SPI_IER_RXOV_MSK BIT(SPI_IER_RXOV_POS) + +#define SPI_IER_RXF_POS 9U +#define SPI_IER_RXF_MSK BIT(SPI_IER_RXF_POS) + +#define SPI_IER_RXNE_POS 8U +#define SPI_IER_RXNE_MSK BIT(SPI_IER_RXNE_POS) + +#define SPI_IER_TXTH_POS 4U +#define SPI_IER_TXTH_MSK BIT(SPI_IER_TXTH_POS) + +#define SPI_IER_TXUD_POS 3U +#define SPI_IER_TXUD_MSK BIT(SPI_IER_TXUD_POS) + +#define SPI_IER_TXOV_POS 2U +#define SPI_IER_TXOV_MSK BIT(SPI_IER_TXOV_POS) + +#define SPI_IER_TXE_POS 0U +#define SPI_IER_TXE_MSK BIT(SPI_IER_TXE_POS) + +/****************** Bit definition for SPI_IDR register ************************/ + +#define SPI_IDR_FRE_POS 18U +#define SPI_IDR_FRE_MSK BIT(SPI_IDR_FRE_POS) + +#define SPI_IDR_MODF_POS 17U +#define SPI_IDR_MODF_MSK BIT(SPI_IDR_MODF_POS) + +#define SPI_IDR_CRCERR_POS 16U +#define SPI_IDR_CRCERR_MSK BIT(SPI_IDR_CRCERR_POS) + +#define SPI_IDR_RXTH_POS 12U +#define SPI_IDR_RXTH_MSK BIT(SPI_IDR_RXTH_POS) + +#define SPI_IDR_RXUD_POS 11U +#define SPI_IDR_RXUD_MSK BIT(SPI_IDR_RXUD_POS) + +#define SPI_IDR_RXOV_POS 10U +#define SPI_IDR_RXOV_MSK BIT(SPI_IDR_RXOV_POS) + +#define SPI_IDR_RXF_POS 9U +#define SPI_IDR_RXF_MSK BIT(SPI_IDR_RXF_POS) + +#define SPI_IDR_RXNE_POS 8U +#define SPI_IDR_RXNE_MSK BIT(SPI_IDR_RXNE_POS) + +#define SPI_IDR_TXTH_POS 4U +#define SPI_IDR_TXTH_MSK BIT(SPI_IDR_TXTH_POS) + +#define SPI_IDR_TXUD_POS 3U +#define SPI_IDR_TXUD_MSK BIT(SPI_IDR_TXUD_POS) + +#define SPI_IDR_TXOV_POS 2U +#define SPI_IDR_TXOV_MSK BIT(SPI_IDR_TXOV_POS) + +#define SPI_IDR_TXE_POS 0U +#define SPI_IDR_TXE_MSK BIT(SPI_IDR_TXE_POS) + +/****************** Bit definition for SPI_IVS register ************************/ + +#define SPI_IVS_FRE_POS 18U +#define SPI_IVS_FRE_MSK BIT(SPI_IVS_FRE_POS) + +#define SPI_IVS_MODF_POS 17U +#define SPI_IVS_MODF_MSK BIT(SPI_IVS_MODF_POS) + +#define SPI_IVS_CRCERR_POS 16U +#define SPI_IVS_CRCERR_MSK BIT(SPI_IVS_CRCERR_POS) + +#define SPI_IVS_RXTH_POS 12U +#define SPI_IVS_RXTH_MSK BIT(SPI_IVS_RXTH_POS) + +#define SPI_IVS_RXUD_POS 11U +#define SPI_IVS_RXUD_MSK BIT(SPI_IVS_RXUD_POS) + +#define SPI_IVS_RXOV_POS 10U +#define SPI_IVS_RXOV_MSK BIT(SPI_IVS_RXOV_POS) + +#define SPI_IVS_RXF_POS 9U +#define SPI_IVS_RXF_MSK BIT(SPI_IVS_RXF_POS) + +#define SPI_IVS_RXNE_POS 8U +#define SPI_IVS_RXNE_MSK BIT(SPI_IVS_RXNE_POS) + +#define SPI_IVS_TXTH_POS 4U +#define SPI_IVS_TXTH_MSK BIT(SPI_IVS_TXTH_POS) + +#define SPI_IVS_TXUD_POS 3U +#define SPI_IVS_TXUD_MSK BIT(SPI_IVS_TXUD_POS) + +#define SPI_IVS_TXOV_POS 2U +#define SPI_IVS_TXOV_MSK BIT(SPI_IVS_TXOV_POS) + +#define SPI_IVS_TXE_POS 0U +#define SPI_IVS_TXE_MSK BIT(SPI_IVS_TXE_POS) + +/****************** Bit definition for SPI_RIF register ************************/ + +#define SPI_RIF_FRE_POS 18U +#define SPI_RIF_FRE_MSK BIT(SPI_RIF_FRE_POS) + +#define SPI_RIF_MODF_POS 17U +#define SPI_RIF_MODF_MSK BIT(SPI_RIF_MODF_POS) + +#define SPI_RIF_CRCERR_POS 16U +#define SPI_RIF_CRCERR_MSK BIT(SPI_RIF_CRCERR_POS) + +#define SPI_RIF_RXTH_POS 12U +#define SPI_RIF_RXTH_MSK BIT(SPI_RIF_RXTH_POS) + +#define SPI_RIF_RXUD_POS 11U +#define SPI_RIF_RXUD_MSK BIT(SPI_RIF_RXUD_POS) + +#define SPI_RIF_RXOV_POS 10U +#define SPI_RIF_RXOV_MSK BIT(SPI_RIF_RXOV_POS) + +#define SPI_RIF_RXF_POS 9U +#define SPI_RIF_RXF_MSK BIT(SPI_RIF_RXF_POS) + +#define SPI_RIF_RXNE_POS 8U +#define SPI_RIF_RXNE_MSK BIT(SPI_RIF_RXNE_POS) + +#define SPI_RIF_TXTH_POS 4U +#define SPI_RIF_TXTH_MSK BIT(SPI_RIF_TXTH_POS) + +#define SPI_RIF_TXUD_POS 3U +#define SPI_RIF_TXUD_MSK BIT(SPI_RIF_TXUD_POS) + +#define SPI_RIF_TXOV_POS 2U +#define SPI_RIF_TXOV_MSK BIT(SPI_RIF_TXOV_POS) + +#define SPI_RIF_TXE_POS 0U +#define SPI_RIF_TXE_MSK BIT(SPI_RIF_TXE_POS) + +/****************** Bit definition for SPI_IFM register ************************/ + +#define SPI_IFM_FRE_POS 18U +#define SPI_IFM_FRE_MSK BIT(SPI_IFM_FRE_POS) + +#define SPI_IFM_MODF_POS 17U +#define SPI_IFM_MODF_MSK BIT(SPI_IFM_MODF_POS) + +#define SPI_IFM_CRCERR_POS 16U +#define SPI_IFM_CRCERR_MSK BIT(SPI_IFM_CRCERR_POS) + +#define SPI_IFM_RXTH_POS 12U +#define SPI_IFM_RXTH_MSK BIT(SPI_IFM_RXTH_POS) + +#define SPI_IFM_RXUD_POS 11U +#define SPI_IFM_RXUD_MSK BIT(SPI_IFM_RXUD_POS) + +#define SPI_IFM_RXOV_POS 10U +#define SPI_IFM_RXOV_MSK BIT(SPI_IFM_RXOV_POS) + +#define SPI_IFM_RXF_POS 9U +#define SPI_IFM_RXF_MSK BIT(SPI_IFM_RXF_POS) + +#define SPI_IFM_RXNE_POS 8U +#define SPI_IFM_RXNE_MSK BIT(SPI_IFM_RXNE_POS) + +#define SPI_IFM_TXTH_POS 4U +#define SPI_IFM_TXTH_MSK BIT(SPI_IFM_TXTH_POS) + +#define SPI_IFM_TXUD_POS 3U +#define SPI_IFM_TXUD_MSK BIT(SPI_IFM_TXUD_POS) + +#define SPI_IFM_TXOV_POS 2U +#define SPI_IFM_TXOV_MSK BIT(SPI_IFM_TXOV_POS) + +#define SPI_IFM_TXE_POS 0U +#define SPI_IFM_TXE_MSK BIT(SPI_IFM_TXE_POS) + +/****************** Bit definition for SPI_ICR register ************************/ + +#define SPI_ICR_FRE_POS 18U +#define SPI_ICR_FRE_MSK BIT(SPI_ICR_FRE_POS) + +#define SPI_ICR_MODF_POS 17U +#define SPI_ICR_MODF_MSK BIT(SPI_ICR_MODF_POS) + +#define SPI_ICR_CRCERR_POS 16U +#define SPI_ICR_CRCERR_MSK BIT(SPI_ICR_CRCERR_POS) + +#define SPI_ICR_RXTH_POS 12U +#define SPI_ICR_RXTH_MSK BIT(SPI_ICR_RXTH_POS) + +#define SPI_ICR_RXUD_POS 11U +#define SPI_ICR_RXUD_MSK BIT(SPI_ICR_RXUD_POS) + +#define SPI_ICR_RXOV_POS 10U +#define SPI_ICR_RXOV_MSK BIT(SPI_ICR_RXOV_POS) + +#define SPI_ICR_RXF_POS 9U +#define SPI_ICR_RXF_MSK BIT(SPI_ICR_RXF_POS) + +#define SPI_ICR_RXNE_POS 8U +#define SPI_ICR_RXNE_MSK BIT(SPI_ICR_RXNE_POS) + +#define SPI_ICR_TXTH_POS 4U +#define SPI_ICR_TXTH_MSK BIT(SPI_ICR_TXTH_POS) + +#define SPI_ICR_TXUD_POS 3U +#define SPI_ICR_TXUD_MSK BIT(SPI_ICR_TXUD_POS) + +#define SPI_ICR_TXOV_POS 2U +#define SPI_ICR_TXOV_MSK BIT(SPI_ICR_TXOV_POS) + +#define SPI_ICR_TXE_POS 0U +#define SPI_ICR_TXE_MSK BIT(SPI_ICR_TXE_POS) + +/* Exported Types ------------------------------------------------------------ */ + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __I uint32_t STAT; + __IO uint32_t DATA; + __IO uint32_t CRCPOLY; + __I uint32_t RXCRC; + __I uint32_t TXCRC; + __IO uint32_t I2SCFG; + __IO uint32_t I2SPR; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} SPI_I2S_TypeDef; + +#endif /* __REG_SPI_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_syscfg.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_syscfg.h new file mode 100644 index 0000000000..066a0d4019 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_syscfg.h @@ -0,0 +1,146 @@ +/********************************************************************************** + * + * @file reg_syscfg.h + * @brief SYSCFG Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_SYSCFG_H__ +#define __REG_SYSCFG_H__ + +/* Includes ------------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ +/* Exported Macros ----------------------------------------------------------- */ + +/****************** Bit definition for SYSCFG_PROT register ************************/ + +#define SYSCFG_PROT_KEY_POSS 1U +#define SYSCFG_PROT_KEY_POSE 31U +#define SYSCFG_PROT_KEY_MSK BITS(SYSCFG_PROT_KEY_POSS,SYSCFG_PROT_KEY_POSE) + +#define SYSCFG_PROT_PROT_POS 0U +#define SYSCFG_PROT_PROT_MSK BIT(SYSCFG_PROT_PROT_POS) + +/****************** Bit definition for SYSCFG_BTADDR register ************************/ + +#define SYSCFG_BTADDR_BTADDR_POSS 0U +#define SYSCFG_BTADDR_BTADDR_POSE 17U +#define SYSCFG_BTADDR_BTADDR_MSK BITS(SYSCFG_BTADDR_BTADDR_POSS,SYSCFG_BTADDR_BTADDR_POSE) + +/****************** Bit definition for SYSCFG_TBKCFG register ************************/ + +#define SYSCFG_TBKCFG_CLUBKE_POS 2U +#define SYSCFG_TBKCFG_CLUBKE_MSK BIT(SYSCFG_TBKCFG_CLUBKE_POS) + +#define SYSCFG_TBKCFG_LVDBKE_POS 1U +#define SYSCFG_TBKCFG_LVDBKE_MSK BIT(SYSCFG_TBKCFG_LVDBKE_POS) + +#define SYSCFG_TBKCFG_CCSBKE_POS 0U +#define SYSCFG_TBKCFG_CCSBKE_MSK BIT(SYSCFG_TBKCFG_CCSBKE_POS) + +/****************** Bit definition for SYSCFG_PISIOCFG register ************************/ + +#define SYSCFG_PISIOCFG_IO15SEL_POSS 30U +#define SYSCFG_PISIOCFG_IO15SEL_POSE 31U +#define SYSCFG_PISIOCFG_IO15SEL_MSK BITS(SYSCFG_PISIOCFG_IO15SEL_POSS,SYSCFG_PISIOCFG_IO15SEL_POSE) + +#define SYSCFG_PISIOCFG_IO14SEL_POSS 28U +#define SYSCFG_PISIOCFG_IO14SEL_POSE 29U +#define SYSCFG_PISIOCFG_IO14SEL_MSK BITS(SYSCFG_PISIOCFG_IO14SEL_POSS,SYSCFG_PISIOCFG_IO14SEL_POSE) + +#define SYSCFG_PISIOCFG_IO13SEL_POSS 26U +#define SYSCFG_PISIOCFG_IO13SEL_POSE 27U +#define SYSCFG_PISIOCFG_IO13SEL_MSK BITS(SYSCFG_PISIOCFG_IO13SEL_POSS,SYSCFG_PISIOCFG_IO13SEL_POSE) + +#define SYSCFG_PISIOCFG_IO12SEL_POSS 24U +#define SYSCFG_PISIOCFG_IO12SEL_POSE 25U +#define SYSCFG_PISIOCFG_IO12SEL_MSK BITS(SYSCFG_PISIOCFG_IO12SEL_POSS,SYSCFG_PISIOCFG_IO12SEL_POSE) + +#define SYSCFG_PISIOCFG_IO11SEL_POSS 22U +#define SYSCFG_PISIOCFG_IO11SEL_POSE 23U +#define SYSCFG_PISIOCFG_IO11SEL_MSK BITS(SYSCFG_PISIOCFG_IO11SEL_POSS,SYSCFG_PISIOCFG_IO11SEL_POSE) + +#define SYSCFG_PISIOCFG_IO10SEL_POSS 20U +#define SYSCFG_PISIOCFG_IO10SEL_POSE 21U +#define SYSCFG_PISIOCFG_IO10SEL_MSK BITS(SYSCFG_PISIOCFG_IO10SEL_POSS,SYSCFG_PISIOCFG_IO10SEL_POSE) + +#define SYSCFG_PISIOCFG_IO9SEL_POSS 18U +#define SYSCFG_PISIOCFG_IO9SEL_POSE 19U +#define SYSCFG_PISIOCFG_IO9SEL_MSK BITS(SYSCFG_PISIOCFG_IO9SEL_POSS,SYSCFG_PISIOCFG_IO9SEL_POSE) + +#define SYSCFG_PISIOCFG_IO8SEL_POSS 16U +#define SYSCFG_PISIOCFG_IO8SEL_POSE 17U +#define SYSCFG_PISIOCFG_IO8SEL_MSK BITS(SYSCFG_PISIOCFG_IO8SEL_POSS,SYSCFG_PISIOCFG_IO8SEL_POSE) + +#define SYSCFG_PISIOCFG_IO7SEL_POSS 14U +#define SYSCFG_PISIOCFG_IO7SEL_POSE 15U +#define SYSCFG_PISIOCFG_IO7SEL_MSK BITS(SYSCFG_PISIOCFG_IO7SEL_POSS,SYSCFG_PISIOCFG_IO7SEL_POSE) + +#define SYSCFG_PISIOCFG_IO6SEL_POSS 12U +#define SYSCFG_PISIOCFG_IO6SEL_POSE 13U +#define SYSCFG_PISIOCFG_IO6SEL_MSK BITS(SYSCFG_PISIOCFG_IO6SEL_POSS,SYSCFG_PISIOCFG_IO6SEL_POSE) + +#define SYSCFG_PISIOCFG_IO5SEL_POSS 10U +#define SYSCFG_PISIOCFG_IO5SEL_POSE 11U +#define SYSCFG_PISIOCFG_IO5SEL_MSK BITS(SYSCFG_PISIOCFG_IO5SEL_POSS,SYSCFG_PISIOCFG_IO5SEL_POSE) + +#define SYSCFG_PISIOCFG_IO4SEL_POSS 8U +#define SYSCFG_PISIOCFG_IO4SEL_POSE 9U +#define SYSCFG_PISIOCFG_IO4SEL_MSK BITS(SYSCFG_PISIOCFG_IO4SEL_POSS,SYSCFG_PISIOCFG_IO4SEL_POSE) + +#define SYSCFG_PISIOCFG_IO3SEL_POSS 6U +#define SYSCFG_PISIOCFG_IO3SEL_POSE 7U +#define SYSCFG_PISIOCFG_IO3SEL_MSK BITS(SYSCFG_PISIOCFG_IO3SEL_POSS,SYSCFG_PISIOCFG_IO3SEL_POSE) + +#define SYSCFG_PISIOCFG_IO2SEL_POSS 4U +#define SYSCFG_PISIOCFG_IO2SEL_POSE 5U +#define SYSCFG_PISIOCFG_IO2SEL_MSK BITS(SYSCFG_PISIOCFG_IO2SEL_POSS,SYSCFG_PISIOCFG_IO2SEL_POSE) + +#define SYSCFG_PISIOCFG_IO1SEL_POSS 2U +#define SYSCFG_PISIOCFG_IO1SEL_POSE 3U +#define SYSCFG_PISIOCFG_IO1SEL_MSK BITS(SYSCFG_PISIOCFG_IO1SEL_POSS,SYSCFG_PISIOCFG_IO1SEL_POSE) + +#define SYSCFG_PISIOCFG_IO0SEL_POSS 0U +#define SYSCFG_PISIOCFG_IO0SEL_POSE 1U +#define SYSCFG_PISIOCFG_IO0SEL_MSK BITS(SYSCFG_PISIOCFG_IO0SEL_POSS,SYSCFG_PISIOCFG_IO0SEL_POSE) + +/* Exported Types ------------------------------------------------------------ */ + +typedef struct +{ + __IO uint32_t PROT; + uint32_t RESERVED0 ; + __IO uint32_t BTADDR; + __IO uint32_t TBKCFG; + __IO uint32_t PISIOCFG; +} SYSCFG_TypeDef; + +#endif /* __REG_SYSCFG_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_timer.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_timer.h new file mode 100644 index 0000000000..1aa46823c6 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_timer.h @@ -0,0 +1,638 @@ +/********************************************************************************** + * + * @file reg_timer.h + * @brief TIMER Head File + * + * @date 06 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 06 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_TIMER_H__ +#define __REG_TIMER_H__ + +/* Includes ------------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ +/* Exported Macros ----------------------------------------------------------- */ + +/****************** Bit definition for TIMER_CON1 register ************************/ + +#define TIMER_CON1_DBGSEL_POS 15U +#define TIMER_CON1_DBGSEL_MSK BIT(TIMER_CON1_DBGSEL_POS) + +#define TIMER_CON1_OCCISS_POSS 11U +#define TIMER_CON1_OCCISS_POSE 13U +#define TIMER_CON1_OCCISS_MSK BITS(TIMER_CON1_OCCISS_POSS,TIMER_CON1_OCCISS_POSE) + +#define TIMER_CON1_OCCISP_POS 10U +#define TIMER_CON1_OCCISP_MSK BIT(TIMER_CON1_OCCISP_POS) + +#define TIMER_CON1_DFCKSEL_POSS 8U +#define TIMER_CON1_DFCKSEL_POSE 9U +#define TIMER_CON1_DFCKSEL_MSK BITS(TIMER_CON1_DFCKSEL_POSS,TIMER_CON1_DFCKSEL_POSE) + +#define TIMER_CON1_ARPEN_POS 7U +#define TIMER_CON1_ARPEN_MSK BIT(TIMER_CON1_ARPEN_POS) + +#define TIMER_CON1_CMSEL_POSS 5U +#define TIMER_CON1_CMSEL_POSE 6U +#define TIMER_CON1_CMSEL_MSK BITS(TIMER_CON1_CMSEL_POSS,TIMER_CON1_CMSEL_POSE) + +#define TIMER_CON1_DIRSEL_POS 4U +#define TIMER_CON1_DIRSEL_MSK BIT(TIMER_CON1_DIRSEL_POS) + +#define TIMER_CON1_SPMEN_POS 3U +#define TIMER_CON1_SPMEN_MSK BIT(TIMER_CON1_SPMEN_POS) + +#define TIMER_CON1_UERSEL_POS 2U +#define TIMER_CON1_UERSEL_MSK BIT(TIMER_CON1_UERSEL_POS) + +#define TIMER_CON1_DISUE_POS 1U +#define TIMER_CON1_DISUE_MSK BIT(TIMER_CON1_DISUE_POS) + +#define TIMER_CON1_CNTEN_POS 0U +#define TIMER_CON1_CNTEN_MSK BIT(TIMER_CON1_CNTEN_POS) + +/****************** Bit definition for TIMER_CON2 register ************************/ + +#define TIMER_CON2_OISS4_POS 14U +#define TIMER_CON2_OISS4_MSK BIT(TIMER_CON2_OISS4_POS) + +#define TIMER_CON2_OISS3N_POS 13U +#define TIMER_CON2_OISS3N_MSK BIT(TIMER_CON2_OISS3N_POS) + +#define TIMER_CON2_OISS3_POS 12U +#define TIMER_CON2_OISS3_MSK BIT(TIMER_CON2_OISS3_POS) + +#define TIMER_CON2_OISS2N_POS 11U +#define TIMER_CON2_OISS2N_MSK BIT(TIMER_CON2_OISS2N_POS) + +#define TIMER_CON2_OISS2_POS 10U +#define TIMER_CON2_OISS2_MSK BIT(TIMER_CON2_OISS2_POS) + +#define TIMER_CON2_OISS1N_POS 9U +#define TIMER_CON2_OISS1N_MSK BIT(TIMER_CON2_OISS1N_POS) + +#define TIMER_CON2_OISS1_POS 8U +#define TIMER_CON2_OISS1_MSK BIT(TIMER_CON2_OISS1_POS) + +#define TIMER_CON2_I1FSEL_POS 7U +#define TIMER_CON2_I1FSEL_MSK BIT(TIMER_CON2_I1FSEL_POS) + +#define TIMER_CON2_TRGOSEL_POSS 4U +#define TIMER_CON2_TRGOSEL_POSE 6U +#define TIMER_CON2_TRGOSEL_MSK BITS(TIMER_CON2_TRGOSEL_POSS,TIMER_CON2_TRGOSEL_POSE) + +#define TIMER_CON2_CCDMASEL_POS 3U +#define TIMER_CON2_CCDMASEL_MSK BIT(TIMER_CON2_CCDMASEL_POS) + +#define TIMER_CON2_CCUSEL_POS 2U +#define TIMER_CON2_CCUSEL_MSK BIT(TIMER_CON2_CCUSEL_POS) + +#define TIMER_CON2_CCPCEN_POS 0U +#define TIMER_CON2_CCPCEN_MSK BIT(TIMER_CON2_CCPCEN_POS) + +/****************** Bit definition for TIMER_SMCON register ************************/ + +#define TIMER_SMCON_ETPOL_POS 15U +#define TIMER_SMCON_ETPOL_MSK BIT(TIMER_SMCON_ETPOL_POS) + +#define TIMER_SMCON_ECM2EN_POS 14U +#define TIMER_SMCON_ECM2EN_MSK BIT(TIMER_SMCON_ECM2EN_POS) + +#define TIMER_SMCON_ETPSEL_POSS 12U +#define TIMER_SMCON_ETPSEL_POSE 13U +#define TIMER_SMCON_ETPSEL_MSK BITS(TIMER_SMCON_ETPSEL_POSS,TIMER_SMCON_ETPSEL_POSE) + +#define TIMER_SMCON_ETFLT_POSS 8U +#define TIMER_SMCON_ETFLT_POSE 11U +#define TIMER_SMCON_ETFLT_MSK BITS(TIMER_SMCON_ETFLT_POSS,TIMER_SMCON_ETFLT_POSE) + +#define TIMER_SMCON_MSCFG_POS 7U +#define TIMER_SMCON_MSCFG_MSK BIT(TIMER_SMCON_MSCFG_POS) + +#define TIMER_SMCON_TSSEL_POSS 4U +#define TIMER_SMCON_TSSEL_POSE 6U +#define TIMER_SMCON_TSSEL_MSK BITS(TIMER_SMCON_TSSEL_POSS,TIMER_SMCON_TSSEL_POSE) + +#define TIMER_SMCON_OCCS_POS 3U +#define TIMER_SMCON_OCCS_MSK BIT(TIMER_SMCON_OCCS_POS) + +#define TIMER_SMCON_SMODS_POSS 0U +#define TIMER_SMCON_SMODS_POSE 2U +#define TIMER_SMCON_SMODS_MSK BITS(TIMER_SMCON_SMODS_POSS,TIMER_SMCON_SMODS_POSE) + +/****************** Bit definition for TIMER_IER register ************************/ + +#define TIMER_IER_BRKIT_POS 7U +#define TIMER_IER_BRKIT_MSK BIT(TIMER_IER_BRKIT_POS) + +#define TIMER_IER_TRGIT_POS 6U +#define TIMER_IER_TRGIT_MSK BIT(TIMER_IER_TRGIT_POS) + +#define TIMER_IER_COMIT_POS 5U +#define TIMER_IER_COMIT_MSK BIT(TIMER_IER_COMIT_POS) + +#define TIMER_IER_CC4IT_POS 4U +#define TIMER_IER_CC4IT_MSK BIT(TIMER_IER_CC4IT_POS) + +#define TIMER_IER_CC3IT_POS 3U +#define TIMER_IER_CC3IT_MSK BIT(TIMER_IER_CC3IT_POS) + +#define TIMER_IER_CC2IT_POS 2U +#define TIMER_IER_CC2IT_MSK BIT(TIMER_IER_CC2IT_POS) + +#define TIMER_IER_CC1IT_POS 1U +#define TIMER_IER_CC1IT_MSK BIT(TIMER_IER_CC1IT_POS) + +#define TIMER_IER_UIT_POS 0U +#define TIMER_IER_UIT_MSK BIT(TIMER_IER_UIT_POS) + +/****************** Bit definition for TIMER_IDR register ************************/ + +#define TIMER_IDR_BRKI_POS 7U +#define TIMER_IDR_BRKI_MSK BIT(TIMER_IDR_BRKI_POS) + +#define TIMER_IDR_TRGI_POS 6U +#define TIMER_IDR_TRGI_MSK BIT(TIMER_IDR_TRGI_POS) + +#define TIMER_IDR_COMI_POS 5U +#define TIMER_IDR_COMI_MSK BIT(TIMER_IDR_COMI_POS) + +#define TIMER_IDR_CC4I_POS 4U +#define TIMER_IDR_CC4I_MSK BIT(TIMER_IDR_CC4I_POS) + +#define TIMER_IDR_CC3I_POS 3U +#define TIMER_IDR_CC3I_MSK BIT(TIMER_IDR_CC3I_POS) + +#define TIMER_IDR_CC2I_POS 2U +#define TIMER_IDR_CC2I_MSK BIT(TIMER_IDR_CC2I_POS) + +#define TIMER_IDR_CC1I_POS 1U +#define TIMER_IDR_CC1I_MSK BIT(TIMER_IDR_CC1I_POS) + +#define TIMER_IDR_UI_POS 0U +#define TIMER_IDR_UI_MSK BIT(TIMER_IDR_UI_POS) + +/****************** Bit definition for TIMER_IVS register ************************/ + +#define TIMER_IVS_BKI_POS 7U +#define TIMER_IVS_BKI_MSK BIT(TIMER_IVS_BKI_POS) + +#define TIMER_IVS_TRGI_POS 6U +#define TIMER_IVS_TRGI_MSK BIT(TIMER_IVS_TRGI_POS) + +#define TIMER_IVS_COMI_POS 5U +#define TIMER_IVS_COMI_MSK BIT(TIMER_IVS_COMI_POS) + +#define TIMER_IVS_CC4I_POS 4U +#define TIMER_IVS_CC4I_MSK BIT(TIMER_IVS_CC4I_POS) + +#define TIMER_IVS_CC3I_POS 3U +#define TIMER_IVS_CC3I_MSK BIT(TIMER_IVS_CC3I_POS) + +#define TIMER_IVS_CC2I_POS 2U +#define TIMER_IVS_CC2I_MSK BIT(TIMER_IVS_CC2I_POS) + +#define TIMER_IVS_CC1I_POS 1U +#define TIMER_IVS_CC1I_MSK BIT(TIMER_IVS_CC1I_POS) + +#define TIMER_IVS_UEI_POS 0U +#define TIMER_IVS_UEI_MSK BIT(TIMER_IVS_UEI_POS) + +/****************** Bit definition for TIMER_RIF register ************************/ + +#define TIMER_RIF_CH4OVIF_POS 12U +#define TIMER_RIF_CH4OVIF_MSK BIT(TIMER_RIF_CH4OVIF_POS) + +#define TIMER_RIF_CH3OVIF_POS 11U +#define TIMER_RIF_CH3OVIF_MSK BIT(TIMER_RIF_CH3OVIF_POS) + +#define TIMER_RIF_CH2OVIF_POS 10U +#define TIMER_RIF_CH2OVIF_MSK BIT(TIMER_RIF_CH2OVIF_POS) + +#define TIMER_RIF_CH1OVIF_POS 9U +#define TIMER_RIF_CH1OVIF_MSK BIT(TIMER_RIF_CH1OVIF_POS) + +#define TIMER_RIF_BRKIF_POS 7U +#define TIMER_RIF_BRKIF_MSK BIT(TIMER_RIF_BRKIF_POS) + +#define TIMER_RIF_TRGIF_POS 6U +#define TIMER_RIF_TRGIF_MSK BIT(TIMER_RIF_TRGIF_POS) + +#define TIMER_RIF_COMIF_POS 5U +#define TIMER_RIF_COMIF_MSK BIT(TIMER_RIF_COMIF_POS) + +#define TIMER_RIF_CH4IF_POS 4U +#define TIMER_RIF_CH4IF_MSK BIT(TIMER_RIF_CH4IF_POS) + +#define TIMER_RIF_CH3IF_POS 3U +#define TIMER_RIF_CH3IF_MSK BIT(TIMER_RIF_CH3IF_POS) + +#define TIMER_RIF_CH2IF_POS 2U +#define TIMER_RIF_CH2IF_MSK BIT(TIMER_RIF_CH2IF_POS) + +#define TIMER_RIF_CH1IF_POS 1U +#define TIMER_RIF_CH1IF_MSK BIT(TIMER_RIF_CH1IF_POS) + +#define TIMER_RIF_UEVTIF_POS 0U +#define TIMER_RIF_UEVTIF_MSK BIT(TIMER_RIF_UEVTIF_POS) + +/****************** Bit definition for TIMER_IFM register ************************/ + +#define TIMER_IFM_BRKIM_POS 7U +#define TIMER_IFM_BRKIM_MSK BIT(TIMER_IFM_BRKIM_POS) + +#define TIMER_IFM_TRGI_POS 6U +#define TIMER_IFM_TRGI_MSK BIT(TIMER_IFM_TRGI_POS) + +#define TIMER_IFM_COMI_POS 5U +#define TIMER_IFM_COMI_MSK BIT(TIMER_IFM_COMI_POS) + +#define TIMER_IFM_CH4CCI_POS 4U +#define TIMER_IFM_CH4CCI_MSK BIT(TIMER_IFM_CH4CCI_POS) + +#define TIMER_IFM_CH3CCI_POS 3U +#define TIMER_IFM_CH3CCI_MSK BIT(TIMER_IFM_CH3CCI_POS) + +#define TIMER_IFM_CH2CCI_POS 2U +#define TIMER_IFM_CH2CCI_MSK BIT(TIMER_IFM_CH2CCI_POS) + +#define TIMER_IFM_CH1CCI_POS 1U +#define TIMER_IFM_CH1CCI_MSK BIT(TIMER_IFM_CH1CCI_POS) + +#define TIMER_IFM_UEI_POS 0U +#define TIMER_IFM_UEI_MSK BIT(TIMER_IFM_UEI_POS) + +/****************** Bit definition for TIMER_ICR register ************************/ + +#define TIMER_ICR_BRKIC_POS 7U +#define TIMER_ICR_BRKIC_MSK BIT(TIMER_ICR_BRKIC_POS) + +#define TIMER_ICR_TRGIC_POS 6U +#define TIMER_ICR_TRGIC_MSK BIT(TIMER_ICR_TRGIC_POS) + +#define TIMER_ICR_COMIC_POS 5U +#define TIMER_ICR_COMIC_MSK BIT(TIMER_ICR_COMIC_POS) + +#define TIMER_ICR_CH4CCIC_POS 4U +#define TIMER_ICR_CH4CCIC_MSK BIT(TIMER_ICR_CH4CCIC_POS) + +#define TIMER_ICR_CH3CCIC_POS 3U +#define TIMER_ICR_CH3CCIC_MSK BIT(TIMER_ICR_CH3CCIC_POS) + +#define TIMER_ICR_CH2CCIC_POS 2U +#define TIMER_ICR_CH2CCIC_MSK BIT(TIMER_ICR_CH2CCIC_POS) + +#define TIMER_ICR_CH1CCIC_POS 1U +#define TIMER_ICR_CH1CCIC_MSK BIT(TIMER_ICR_CH1CCIC_POS) + +#define TIMER_ICR_UEIC_POS 0U +#define TIMER_ICR_UEIC_MSK BIT(TIMER_ICR_UEIC_POS) + +/****************** Bit definition for TIMER_SGE register ************************/ + +#define TIMER_SGE_SGBRK_POS 7U +#define TIMER_SGE_SGBRK_MSK BIT(TIMER_SGE_SGBRK_POS) + +#define TIMER_SGE_SGTRG_POS 6U +#define TIMER_SGE_SGTRG_MSK BIT(TIMER_SGE_SGTRG_POS) + +#define TIMER_SGE_SGCOM_POS 5U +#define TIMER_SGE_SGCOM_MSK BIT(TIMER_SGE_SGCOM_POS) + +#define TIMER_SGE_SGCC4E_POS 4U +#define TIMER_SGE_SGCC4E_MSK BIT(TIMER_SGE_SGCC4E_POS) + +#define TIMER_SGE_SGCC3E_POS 3U +#define TIMER_SGE_SGCC3E_MSK BIT(TIMER_SGE_SGCC3E_POS) + +#define TIMER_SGE_SGCC2E_POS 2U +#define TIMER_SGE_SGCC2E_MSK BIT(TIMER_SGE_SGCC2E_POS) + +#define TIMER_SGE_SGCC1E_POS 1U +#define TIMER_SGE_SGCC1E_MSK BIT(TIMER_SGE_SGCC1E_POS) + +#define TIMER_SGE_SGU_POS 0U +#define TIMER_SGE_SGU_MSK BIT(TIMER_SGE_SGU_POS) + +/****************** Bit definition for TIMER_CHMR1 register ************************/ +/* Output */ +#define TIMER_CHMR1_CH2OCLREN_POS 15U +#define TIMER_CHMR1_CH2OCLREN_MSK BIT(TIMER_CHMR1_CH2OCLREN_POS) + +#define TIMER_CHMR1_CH2OMOD_POSS 12U +#define TIMER_CHMR1_CH2OMOD_POSE 14U +#define TIMER_CHMR1_CH2OMOD_MSK BITS(TIMER_CHMR1_CH2OMOD_POSS,TIMER_CHMR1_CH2OMOD_POSE) + +#define TIMER_CHMR1_CH2OPEN_POS 11U +#define TIMER_CHMR1_CH2OPEN_MSK BIT(TIMER_CHMR1_CH2OPEN_POS) + +#define TIMER_CHMR1_CH2OFEN_POS 10U +#define TIMER_CHMR1_CH2OFEN_MSK BIT(TIMER_CHMR1_CH2OFEN_POS) + +#define TIMER_CHMR1_CC2SSEL_POSS 8U +#define TIMER_CHMR1_CC2SSEL_POSE 9U +#define TIMER_CHMR1_CC2SSEL_MSK BITS(TIMER_CHMR1_CC2SSEL_POSS,TIMER_CHMR1_CC2SSEL_POSE) + +#define TIMER_CHMR1_CH1OCLREN_POS 7U +#define TIMER_CHMR1_CH1OCLREN_MSK BIT(TIMER_CHMR1_CH1OCLREN_POS) + +#define TIMER_CHMR1_CH1OMOD_POSS 4U +#define TIMER_CHMR1_CH1OMOD_POSE 6U +#define TIMER_CHMR1_CH1OMOD_MSK BITS(TIMER_CHMR1_CH1OMOD_POSS,TIMER_CHMR1_CH1OMOD_POSE) + +#define TIMER_CHMR1_CH1OPREN_POS 3U +#define TIMER_CHMR1_CH1OPREN_MSK BIT(TIMER_CHMR1_CH1OPREN_POS) + +#define TIMER_CHMR1_CH1OHSEN_POS 2U +#define TIMER_CHMR1_CH1OHSEN_MSK BIT(TIMER_CHMR1_CH1OHSEN_POS) + +#define TIMER_CHMR1_CC1SSEL_POSS 0U +#define TIMER_CHMR1_CC1SSEL_POSE 1U +#define TIMER_CHMR1_CC1SSEL_MSK BITS(TIMER_CHMR1_CC1SSEL_POSS,TIMER_CHMR1_CC1SSEL_POSE) + +/* Input */ +#define TIMER_CHMR1_I2FLT_POSS 12U +#define TIMER_CHMR1_I2FLT_POSE 15U +#define TIMER_CHMR1_I2FLT_MSK BITS(TIMER_CHMR1_I2FLT_POSS,TIMER_CHMR1_I2FLT_POSE) + +#define TIMER_CHMR1_IC2PRES_POSS 10U +#define TIMER_CHMR1_IC2PRES_POSE 11U +#define TIMER_CHMR1_IC2PRES_MSK BITS(TIMER_CHMR1_IC2PRES_POSS,TIMER_CHMR1_IC2PRES_POSE) + +#define TIMER_CHMR1_CC2SEL_POSS 8U +#define TIMER_CHMR1_CC2SEL_POSE 9U +#define TIMER_CHMR1_CC2SEL_MSK BITS(TIMER_CHMR1_CC2SEL_POSS,TIMER_CHMR1_CC2SEL_POSE) + +#define TIMER_CHMR1_I1FLT_POSS 4U +#define TIMER_CHMR1_I1FLT_POSE 7U +#define TIMER_CHMR1_I1FLT_MSK BITS(TIMER_CHMR1_I1FLT_POSS,TIMER_CHMR1_I1FLT_POSE) + +#define TIMER_CHMR1_IC1PRES_POSS 2U +#define TIMER_CHMR1_IC1PRES_POSE 3U +#define TIMER_CHMR1_IC1PRES_MSK BITS(TIMER_CHMR1_IC1PRES_POSS,TIMER_CHMR1_IC1PRES_POSE) + +#define TIMER_CHMR1_CC1SSEL_POSS 0U +#define TIMER_CHMR1_CC1SSEL_POSE 1U +#define TIMER_CHMR1_CC1SSEL_MSK BITS(TIMER_CHMR1_CC1SSEL_POSS,TIMER_CHMR1_CC1SSEL_POSE) + +/****************** Bit definition for TIMER_CHMR2 register ************************/ +/* Output */ +#define TIMER_CHMR2_CH4OCLREN_POS 15U +#define TIMER_CHMR2_CH4OCLREN_MSK BIT(TIMER_CHMR2_CH4OCLREN_POS) + +#define TIMER_CHMR2_CH4OMOD_POSS 12U +#define TIMER_CHMR2_CH4OMOD_POSE 14U +#define TIMER_CHMR2_CH4OMOD_MSK BITS(TIMER_CHMR2_CH4OMOD_POSS,TIMER_CHMR2_CH4OMOD_POSE) + +#define TIMER_CHMR2_CH4OPEN_POS 11U +#define TIMER_CHMR2_CH4OPEN_MSK BIT(TIMER_CHMR2_CH4OPEN_POS) + +#define TIMER_CHMR2_CH4OHSEN_POS 10U +#define TIMER_CHMR2_CH4OHSEN_MSK BIT(TIMER_CHMR2_CH4OHSEN_POS) + +#define TIMER_CHMR2_CC4SSEL_POSS 8U +#define TIMER_CHMR2_CC4SSEL_POSE 9U +#define TIMER_CHMR2_CC4SSEL_MSK BITS(TIMER_CHMR2_CC4SSEL_POSS,TIMER_CHMR2_CC4SSEL_POSE) + +#define TIMER_CHMR2_CH3OCLREN_POS 7U +#define TIMER_CHMR2_CH3OCLREN_MSK BIT(TIMER_CHMR2_CH3OCLREN_POS) + +#define TIMER_CHMR2_CH3OMOD_POSS 4U +#define TIMER_CHMR2_CH3OMOD_POSE 6U +#define TIMER_CHMR2_CH3OMOD_MSK BITS(TIMER_CHMR2_CH3OMOD_POSS,TIMER_CHMR2_CH3OMOD_POSE) + +#define TIMER_CHMR2_CH3OPEN_POS 3U +#define TIMER_CHMR2_CH3OPEN_MSK BIT(TIMER_CHMR2_CH3OPEN_POS) + +#define TIMER_CHMR2_CH3OFEN_POS 2U +#define TIMER_CHMR2_CH3OFEN_MSK BIT(TIMER_CHMR2_CH3OFEN_POS) + +#define TIMER_CHMR2_CC3SSEL_POSS 0U +#define TIMER_CHMR2_CC3SSEL_POSE 1U +#define TIMER_CHMR2_CC3SSEL_MSK BITS(TIMER_CHMR2_CC3SSEL_POSS,TIMER_CHMR2_CC3SSEL_POSE) + +/* Input */ +#define TIMER_CHMR2_I4FLT_POSS 12U +#define TIMER_CHMR2_I4FLT_POSE 15U +#define TIMER_CHMR2_I4FLT_MSK BITS(TIMER_CHMR2_I4FLT_POSS,TIMER_CHMR2_I4FLT_POSE) + +#define TIMER_CHMR2_IC4PRES_POSS 10U +#define TIMER_CHMR2_IC4PRES_POSE 11U +#define TIMER_CHMR2_IC4PRES_MSK BITS(TIMER_CHMR2_IC4PRES_POSS,TIMER_CHMR2_IC4PRES_POSE) + +#define TIMER_CHMR2_CC4SSEL_POSS 8U +#define TIMER_CHMR2_CC4SSEL_POSE 9U +#define TIMER_CHMR2_CC4SSEL_MSK BITS(TIMER_CHMR2_CC4SSEL_POSS,TIMER_CHMR2_CC4SSEL_POSE) + +#define TIMER_CHMR2_I3FLT_POSS 4U +#define TIMER_CHMR2_I3FLT_POSE 7U +#define TIMER_CHMR2_I3FLT_MSK BITS(TIMER_CHMR2_I3FLT_POSS,TIMER_CHMR2_I3FLT_POSE) + +#define TIMER_CHMR2_IC3PRES_POSS 2U +#define TIMER_CHMR2_IC3PRES_POSE 3U +#define TIMER_CHMR2_IC3PRES_MSK BITS(TIMER_CHMR2_IC3PRES_POSS,TIMER_CHMR2_IC3PRES_POSE) + +#define TIMER_CHMR2_CC3SSEL_POSS 0U +#define TIMER_CHMR2_CC3SSEL_POSE 1U +#define TIMER_CHMR2_CC3SSEL_MSK BITS(TIMER_CHMR2_CC3SSEL_POSS,TIMER_CHMR2_CC3SSEL_POSE) + +/****************** Bit definition for TIMER_CCEP register ************************/ + +#define TIMER_CCEP_CC4POL_POS 13U +#define TIMER_CCEP_CC4POL_MSK BIT(TIMER_CCEP_CC4POL_POS) + +#define TIMER_CCEP_CC4EN_POS 12U +#define TIMER_CCEP_CC4EN_MSK BIT(TIMER_CCEP_CC4EN_POS) + +#define TIMER_CCEP_CC3NPOL_POS 11U +#define TIMER_CCEP_CC3NPOL_MSK BIT(TIMER_CCEP_CC3NPOL_POS) + +#define TIMER_CCEP_CC3NE_POS 10U +#define TIMER_CCEP_CC3NE_MSK BIT(TIMER_CCEP_CC3NE_POS) + +#define TIMER_CCEP_CC3POL_POS 9U +#define TIMER_CCEP_CC3POL_MSK BIT(TIMER_CCEP_CC3POL_POS) + +#define TIMER_CCEP_CC3EN_POS 8U +#define TIMER_CCEP_CC3EN_MSK BIT(TIMER_CCEP_CC3EN_POS) + +#define TIMER_CCEP_CC2NPOL_POS 7U +#define TIMER_CCEP_CC2NPOL_MSK BIT(TIMER_CCEP_CC2NPOL_POS) + +#define TIMER_CCEP_CC2NE_POS 6U +#define TIMER_CCEP_CC2NE_MSK BIT(TIMER_CCEP_CC2NE_POS) + +#define TIMER_CCEP_CC2POL_POS 5U +#define TIMER_CCEP_CC2POL_MSK BIT(TIMER_CCEP_CC2POL_POS) + +#define TIMER_CCEP_CC2EN_POS 4U +#define TIMER_CCEP_CC2EN_MSK BIT(TIMER_CCEP_CC2EN_POS) + +#define TIMER_CCEP_CC1NPOL_POS 3U +#define TIMER_CCEP_CC1NPOL_MSK BIT(TIMER_CCEP_CC1NPOL_POS) + +#define TIMER_CCEP_CC1NE_POS 2U +#define TIMER_CCEP_CC1NE_MSK BIT(TIMER_CCEP_CC1NE_POS) + +#define TIMER_CCEP_CC1POL_POS 1U +#define TIMER_CCEP_CC1POL_MSK BIT(TIMER_CCEP_CC1POL_POS) + +#define TIMER_CCEP_CC1EN_POS 0U +#define TIMER_CCEP_CC1EN_MSK BIT(TIMER_CCEP_CC1EN_POS) + +/****************** Bit definition for TIMER_COUNT register ************************/ + +#define TIMER_COUNT_CNTV_POSS 0U +#define TIMER_COUNT_CNTV_POSE 15U +#define TIMER_COUNT_CNTV_MSK BITS(TIMER_COUNT_CNTV_POSS,TIMER_COUNT_CNTV_POSE) + +/****************** Bit definition for TIMER_PRES register ************************/ + +#define TIMER_PRES_PSCV_POSS 0U +#define TIMER_PRES_PSCV_POSE 15U +#define TIMER_PRES_PSCV_MSK BITS(TIMER_PRES_PSCV_POSS,TIMER_PRES_PSCV_POSE) + +/****************** Bit definition for TIMER_AR register ************************/ + +#define TIMER_AR_ARRV_POSS 0U +#define TIMER_AR_ARRV_POSE 15U +#define TIMER_AR_ARRV_MSK BITS(TIMER_AR_ARRV_POSS,TIMER_AR_ARRV_POSE) + +/****************** Bit definition for TIMER_REPAR register ************************/ + +#define TIMER_REPAR_REPV_POSS 0U +#define TIMER_REPAR_REPV_POSE 7U +#define TIMER_REPAR_REPV_MSK BITS(TIMER_REPAR_REPV_POSS,TIMER_REPAR_REPV_POSE) + +/****************** Bit definition for TIMER_CCVAL1 register ************************/ + +#define TIMER_CCVAL1_CCRV1_POSS 0U +#define TIMER_CCVAL1_CCRV1_POSE 15U +#define TIMER_CCVAL1_CCRV1_MSK BITS(TIMER_CCVAL1_CCRV1_POSS,TIMER_CCVAL1_CCRV1_POSE) + +/****************** Bit definition for TIMER_CCVAL2 register ************************/ + +#define TIMER_CCVAL2_CCRV2_POSS 0U +#define TIMER_CCVAL2_CCRV2_POSE 15U +#define TIMER_CCVAL2_CCRV2_MSK BITS(TIMER_CCVAL2_CCRV2_POSS,TIMER_CCVAL2_CCRV2_POSE) + +/****************** Bit definition for TIMER_CCVAL3 register ************************/ + +#define TIMER_CCVAL3_CCRV3_POSS 0U +#define TIMER_CCVAL3_CCRV3_POSE 15U +#define TIMER_CCVAL3_CCRV3_MSK BITS(TIMER_CCVAL3_CCRV3_POSS,TIMER_CCVAL3_CCRV3_POSE) + +/****************** Bit definition for TIMER_CCVAL4 register ************************/ + +#define TIMER_CCVAL4_CCRV4_POSS 0U +#define TIMER_CCVAL4_CCRV4_POSE 15U +#define TIMER_CCVAL4_CCRV4_MSK BITS(TIMER_CCVAL4_CCRV4_POSS,TIMER_CCVAL4_CCRV4_POSE) + +/****************** Bit definition for TIMER_BDCFG register ************************/ + +#define TIMER_BDCFG_GOEN_POS 15U +#define TIMER_BDCFG_GOEN_MSK BIT(TIMER_BDCFG_GOEN_POS) + +#define TIMER_BDCFG_AOEN_POS 14U +#define TIMER_BDCFG_AOEN_MSK BIT(TIMER_BDCFG_AOEN_POS) + +#define TIMER_BDCFG_BRKP_POS 13U +#define TIMER_BDCFG_BRKP_MSK BIT(TIMER_BDCFG_BRKP_POS) + +#define TIMER_BDCFG_BRKEN_POS 12U +#define TIMER_BDCFG_BRKEN_MSK BIT(TIMER_BDCFG_BRKEN_POS) + +#define TIMER_BDCFG_OFFSSR_POS 11U +#define TIMER_BDCFG_OFFSSR_MSK BIT(TIMER_BDCFG_OFFSSR_POS) + +#define TIMER_BDCFG_OFFSSI_POS 10U +#define TIMER_BDCFG_OFFSSI_MSK BIT(TIMER_BDCFG_OFFSSI_POS) + +#define TIMER_BDCFG_LOCKLVL_POSS 8U +#define TIMER_BDCFG_LOCKLVL_POSE 9U +#define TIMER_BDCFG_LOCKLVL_MSK BITS(TIMER_BDCFG_LOCKLVL_POSS,TIMER_BDCFG_LOCKLVL_POSE) + +#define TIMER_BDCFG_DT_POSS 0U +#define TIMER_BDCFG_DT_POSE 7U +#define TIMER_BDCFG_DT_MSK BITS(TIMER_BDCFG_DT_POSS,TIMER_BDCFG_DT_POSE) + +/****************** Bit definition for TIMER_DMAEN register ************************/ + +#define TIMER_DMAEN_TDS_POS 6U +#define TIMER_DMAEN_TDS_MSK BIT(TIMER_DMAEN_TDS_POS) + +#define TIMER_DMAEN_COMDS_POS 5U +#define TIMER_DMAEN_COMDS_MSK BIT(TIMER_DMAEN_COMDS_POS) + +#define TIMER_DMAEN_CC4DS_POS 4U +#define TIMER_DMAEN_CC4DS_MSK BIT(TIMER_DMAEN_CC4DS_POS) + +#define TIMER_DMAEN_CC3DS_POS 3U +#define TIMER_DMAEN_CC3DS_MSK BIT(TIMER_DMAEN_CC3DS_POS) + +#define TIMER_DMAEN_CC2DS_POS 2U +#define TIMER_DMAEN_CC2DS_MSK BIT(TIMER_DMAEN_CC2DS_POS) + +#define TIMER_DMAEN_CC1DS_POS 1U +#define TIMER_DMAEN_CC1DS_MSK BIT(TIMER_DMAEN_CC1DS_POS) + +#define TIMER_DMAEN_UDS_POS 0U +#define TIMER_DMAEN_UDS_MSK BIT(TIMER_DMAEN_UDS_POS) + +/* Exported Types ------------------------------------------------------------ */ + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t SMCON; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; + __O uint32_t SGE; + __IO uint32_t CHMR1; + __IO uint32_t CHMR2; + __IO uint32_t CCEP; + __IO uint32_t COUNT; + __IO uint32_t PRES; + __IO uint32_t AR; + __IO uint32_t REPAR; + __IO uint32_t CCVAL1; + __IO uint32_t CCVAL2; + __IO uint32_t CCVAL3; + __IO uint32_t CCVAL4; + __IO uint32_t BDCFG; + __IO uint32_t DMAEN; +} TIMER_TypeDef; + +#endif /* __REG_TIMER_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_uart.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_uart.h new file mode 100644 index 0000000000..65dfe5055a --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_uart.h @@ -0,0 +1,551 @@ +/********************************************************************************** + * + * @file reg_uart.h + * @brief UART Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_UART_H__ +#define __REG_UART_H__ + +/* Includes ------------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ +/* Exported Macros ----------------------------------------------------------- */ + +/****************** Bit definition for UART_RXBUF register ************************/ + +#define UART_RXBUF_RXBUF_POSS 0U +#define UART_RXBUF_RXBUF_POSE 8U +#define UART_RXBUF_RXBUF_MSK BITS(UART_RXBUF_RXBUF_POSS,UART_RXBUF_RXBUF_POSE) + +/****************** Bit definition for UART_TXBUF register ************************/ + +#define UART_TXBUF_TXBUF_POSS 0U +#define UART_TXBUF_TXBUF_POSE 8U +#define UART_TXBUF_TXBUF_MSK BITS(UART_TXBUF_TXBUF_POSS,UART_TXBUF_TXBUF_POSE) + +/****************** Bit definition for UART_BRR register ************************/ + +#define UART_BRR_BRR_POSS 0U +#define UART_BRR_BRR_POSE 15U +#define UART_BRR_BRR_MSK BITS(UART_BRR_BRR_POSS,UART_BRR_BRR_POSE) + +/****************** Bit definition for UART_LCON register ************************/ + +#define UART_LCON_TXEN_POS 15U +#define UART_LCON_TXEN_MSK BIT(UART_LCON_TXEN_POS) + +#define UART_LCON_RXEN_POS 14U +#define UART_LCON_RXEN_MSK BIT(UART_LCON_RXEN_POS) + +#define UART_LCON_DBCEN_POS 13U +#define UART_LCON_DBCEN_MSK BIT(UART_LCON_DBCEN_POS) + +#define UART_LCON_BREAK_POS 10U +#define UART_LCON_BREAK_MSK BIT(UART_LCON_BREAK_POS) + +#define UART_LCON_SWAP_POS 9U +#define UART_LCON_SWAP_MSK BIT(UART_LCON_SWAP_POS) + +#define UART_LCON_TXINV_POS 8U +#define UART_LCON_TXINV_MSK BIT(UART_LCON_TXINV_POS) + +#define UART_LCON_RXINV_POS 7U +#define UART_LCON_RXINV_MSK BIT(UART_LCON_RXINV_POS) + +#define UART_LCON_DATAINV_POS 6U +#define UART_LCON_DATAINV_MSK BIT(UART_LCON_DATAINV_POS) + +#define UART_LCON_MSB_POS 5U +#define UART_LCON_MSB_MSK BIT(UART_LCON_MSB_POS) + +#define UART_LCON_PS_POS 4U +#define UART_LCON_PS_MSK BIT(UART_LCON_PS_POS) + +#define UART_LCON_PE_POS 3U +#define UART_LCON_PE_MSK BIT(UART_LCON_PE_POS) + +#define UART_LCON_STOP_POS 2U +#define UART_LCON_STOP_MSK BIT(UART_LCON_STOP_POS) + +#define UART_LCON_DLS_POSS 0U +#define UART_LCON_DLS_POSE 1U +#define UART_LCON_DLS_MSK BITS(UART_LCON_DLS_POSS,UART_LCON_DLS_POSE) + +/****************** Bit definition for UART_MCON register ************************/ + +#define UART_MCON_TXFLOAT_POS 16U +#define UART_MCON_TXFLOAT_MSK BIT(UART_MCON_TXFLOAT_POS) + +#define UART_MCON_TXDMAEN_POS 15U +#define UART_MCON_TXDMAEN_MSK BIT(UART_MCON_TXDMAEN_POS) + +#define UART_MCON_RXDMAEN_POS 14U +#define UART_MCON_RXDMAEN_MSK BIT(UART_MCON_RXDMAEN_POS) + +#define UART_MCON_ABRREPT_POS 11U +#define UART_MCON_ABRREPT_MSK BIT(UART_MCON_ABRREPT_POS) + +#define UART_MCON_ABRMOD_POSS 9U +#define UART_MCON_ABRMOD_POSE 10U +#define UART_MCON_ABRMOD_MSK BITS(UART_MCON_ABRMOD_POSS,UART_MCON_ABRMOD_POSE) + +#define UART_MCON_ABREN_POS 8U +#define UART_MCON_ABREN_MSK BIT(UART_MCON_ABREN_POS) + +#define UART_MCON_BKREQ_POS 5U +#define UART_MCON_BKREQ_MSK BIT(UART_MCON_BKREQ_POS) + +#define UART_MCON_HDEN_POS 4U +#define UART_MCON_HDEN_MSK BIT(UART_MCON_HDEN_POS) + +#define UART_MCON_IREN_POS 3U +#define UART_MCON_IREN_MSK BIT(UART_MCON_IREN_POS) + +#define UART_MCON_AFCEN_POS 2U +#define UART_MCON_AFCEN_MSK BIT(UART_MCON_AFCEN_POS) + +#define UART_MCON_RTSSET_POS 1U +#define UART_MCON_RTSSET_MSK BIT(UART_MCON_RTSSET_POS) + +#define UART_MCON_LPBKEN_POS 0U +#define UART_MCON_LPBKEN_MSK BIT(UART_MCON_LPBKEN_POS) + +/****************** Bit definition for UART_RS485 register ************************/ + +#define UART_RS485_DLY_POSS 16U +#define UART_RS485_DLY_POSE 23U +#define UART_RS485_DLY_MSK BITS(UART_RS485_DLY_POSS,UART_RS485_DLY_POSE) + +#define UART_RS485_ADDR_POSS 8U +#define UART_RS485_ADDR_POSE 15U +#define UART_RS485_ADDR_MSK BITS(UART_RS485_ADDR_POSS,UART_RS485_ADDR_POSE) + +#define UART_RS485_AADINV_POS 3U +#define UART_RS485_AADINV_MSK BIT(UART_RS485_AADINV_POS) + +#define UART_RS485_AADACEN_POS 2U +#define UART_RS485_AADACEN_MSK BIT(UART_RS485_AADACEN_POS) + +#define UART_RS485_AADNEN_POS 1U +#define UART_RS485_AADNEN_MSK BIT(UART_RS485_AADNEN_POS) + +#define UART_RS485_AADEN_POS 0U +#define UART_RS485_AADEN_MSK BIT(UART_RS485_AADEN_POS) + +/****************** Bit definition for UART_SCARD register ************************/ + +#define UART_SCARD_BLEN_POSS 24U +#define UART_SCARD_BLEN_POSE 31U +#define UART_SCARD_BLEN_MSK BITS(UART_SCARD_BLEN_POSS,UART_SCARD_BLEN_POSE) + +#define UART_SCARD_GT_POSS 16U +#define UART_SCARD_GT_POSE 23U +#define UART_SCARD_GT_MSK BITS(UART_SCARD_GT_POSS,UART_SCARD_GT_POSE) + +#define UART_SCARD_PSC_POSS 8U +#define UART_SCARD_PSC_POSE 15U +#define UART_SCARD_PSC_MSK BITS(UART_SCARD_PSC_POSS,UART_SCARD_PSC_POSE) + +#define UART_SCARD_SCCNT_POSS 3U +#define UART_SCARD_SCCNT_POSE 5U +#define UART_SCARD_SCCNT_MSK BITS(UART_SCARD_SCCNT_POSS,UART_SCARD_SCCNT_POSE) + +#define UART_SCARD_SCLKEN_POS 2U +#define UART_SCARD_SCLKEN_MSK BIT(UART_SCARD_SCLKEN_POS) + +#define UART_SCARD_SCNACK_POS 1U +#define UART_SCARD_SCNACK_MSK BIT(UART_SCARD_SCNACK_POS) + +#define UART_SCARD_SCEN_POS 0U +#define UART_SCARD_SCEN_MSK BIT(UART_SCARD_SCEN_POS) + +/****************** Bit definition for UART_LIN register ************************/ + +#define UART_LIN_LINBKREQ_POS 2U +#define UART_LIN_LINBKREQ_MSK BIT(UART_LIN_LINBKREQ_POS) + +#define UART_LIN_LINBDL_POS 1U +#define UART_LIN_LINBDL_MSK BIT(UART_LIN_LINBDL_POS) + +#define UART_LIN_LINEN_POS 0U +#define UART_LIN_LINEN_MSK BIT(UART_LIN_LINEN_POS) + +/****************** Bit definition for UART_RTOR register ************************/ + +#define UART_RTOR_RTOEN_POS 24U +#define UART_RTOR_RTOEN_MSK BIT(UART_RTOR_RTOEN_POS) + +#define UART_RTOR_RTO_POSS 0U +#define UART_RTOR_RTO_POSE 23U +#define UART_RTOR_RTO_MSK BITS(UART_RTOR_RTO_POSS,UART_RTOR_RTO_POSE) + +/****************** Bit definition for UART_STAT register ************************/ + +#define UART_STAT_TFOERR_POS 18U +#define UART_STAT_TFOERR_MSK BIT(UART_STAT_TFOERR_POS) + +#define UART_STAT_TFEMPTY_POS 16U +#define UART_STAT_TFEMPTY_MSK BIT(UART_STAT_TFEMPTY_POS) + +#define UART_STAT_TSBUSY_POS 14U +#define UART_STAT_TSBUSY_MSK BIT(UART_STAT_TSBUSY_POS) + +#define UART_STAT_RFUERR_POS 13U +#define UART_STAT_RFUERR_MSK BIT(UART_STAT_RFUERR_POS) + +#define UART_STAT_RFOERR_POS 12U +#define UART_STAT_RFOERR_MSK BIT(UART_STAT_RFOERR_POS) + +#define UART_STAT_RFNEMPTY_POS 10U +#define UART_STAT_RFNEMPTY_MSK BIT(UART_STAT_RFNEMPTY_POS) + +#define UART_STAT_RSBUSY_POS 8U +#define UART_STAT_RSBUSY_MSK BIT(UART_STAT_RSBUSY_POS) + +#define UART_STAT_CTSSTA_POS 3U +#define UART_STAT_CTSSTA_MSK BIT(UART_STAT_CTSSTA_POS) + +#define UART_STAT_BKERR_POS 2U +#define UART_STAT_BKERR_MSK BIT(UART_STAT_BKERR_POS) + +#define UART_STAT_FERR_POS 1U +#define UART_STAT_FERR_MSK BIT(UART_STAT_FERR_POS) + +#define UART_STAT_PERR_POS 0U +#define UART_STAT_PERR_MSK BIT(UART_STAT_PERR_POS) + +/****************** Bit definition for UART_IER register ************************/ + +#define UART_IER_TFOERR_POS 18U +#define UART_IER_TFOERR_MSK BIT(UART_IER_TFOERR_POS) + +#define UART_IER_TFEMPTY_POS 16U +#define UART_IER_TFEMPTY_MSK BIT(UART_IER_TFEMPTY_POS) + +#define UART_IER_TBC_POS 14U +#define UART_IER_TBC_MSK BIT(UART_IER_TBC_POS) + +#define UART_IER_RFUERR_POS 13U +#define UART_IER_RFUERR_MSK BIT(UART_IER_RFUERR_POS) + +#define UART_IER_RFOERR_POS 12U +#define UART_IER_RFOERR_MSK BIT(UART_IER_RFOERR_POS) + +#define UART_IER_RFNEMPTY_POS 10U +#define UART_IER_RFNEMPTY_MSK BIT(UART_IER_RFNEMPTY_POS) + +#define UART_IER_NOISE_POS 8U +#define UART_IER_NOISE_MSK BIT(UART_IER_NOISE_POS) + +#define UART_IER_EOB_POS 7U +#define UART_IER_EOB_MSK BIT(UART_IER_EOB_POS) + +#define UART_IER_LINBK_POS 6U +#define UART_IER_LINBK_MSK BIT(UART_IER_LINBK_POS) + +#define UART_IER_ADDRM_POS 5U +#define UART_IER_ADDRM_MSK BIT(UART_IER_ADDRM_POS) + +#define UART_IER_RXTO_POS 4U +#define UART_IER_RXTO_MSK BIT(UART_IER_RXTO_POS) + +#define UART_IER_DCTS_POS 3U +#define UART_IER_DCTS_MSK BIT(UART_IER_DCTS_POS) + +#define UART_IER_ABTO_POS 2U +#define UART_IER_ABTO_MSK BIT(UART_IER_ABTO_POS) + +#define UART_IER_ABEND_POS 1U +#define UART_IER_ABEND_MSK BIT(UART_IER_ABEND_POS) + +#define UART_IER_RXBERR_POS 0U +#define UART_IER_RXBERR_MSK BIT(UART_IER_RXBERR_POS) + +/****************** Bit definition for UART_IDR register ************************/ + +#define UART_IDR_TFOVER_POS 18U +#define UART_IDR_TFOVER_MSK BIT(UART_IDR_TFOVER_POS) + +#define UART_IDR_TFEMPTY_POS 16U +#define UART_IDR_TFEMPTY_MSK BIT(UART_IDR_TFEMPTY_POS) + +#define UART_IDR_TBC_POS 14U +#define UART_IDR_TBC_MSK BIT(UART_IDR_TBC_POS) + +#define UART_IDR_RFUERR_POS 13U +#define UART_IDR_RFUERR_MSK BIT(UART_IDR_RFUERR_POS) + +#define UART_IDR_RFOERR_POS 12U +#define UART_IDR_RFOERR_MSK BIT(UART_IDR_RFOERR_POS) + +#define UART_IDR_RFNEMPTY_POS 10U +#define UART_IDR_RFNEMPTY_MSK BIT(UART_IDR_RFNEMPTY_POS) + +#define UART_IDR_NOISE_POS 8U +#define UART_IDR_NOISE_MSK BIT(UART_IDR_NOISE_POS) + +#define UART_IDR_EOB_POS 7U +#define UART_IDR_EOB_MSK BIT(UART_IDR_EOB_POS) + +#define UART_IDR_LINBK_POS 6U +#define UART_IDR_LINBK_MSK BIT(UART_IDR_LINBK_POS) + +#define UART_IDR_ADDRM_POS 5U +#define UART_IDR_ADDRM_MSK BIT(UART_IDR_ADDRM_POS) + +#define UART_IDR_RXTO_POS 4U +#define UART_IDR_RXTO_MSK BIT(UART_IDR_RXTO_POS) + +#define UART_IDR_DCTS_POS 3U +#define UART_IDR_DCTS_MSK BIT(UART_IDR_DCTS_POS) + +#define UART_IDR_ABTO_POS 2U +#define UART_IDR_ABTO_MSK BIT(UART_IDR_ABTO_POS) + +#define UART_IDR_ABEND_POS 1U +#define UART_IDR_ABEND_MSK BIT(UART_IDR_ABEND_POS) + +#define UART_IDR_RXBERR_POS 0U +#define UART_IDR_RXBERR_MSK BIT(UART_IDR_RXBERR_POS) + +/****************** Bit definition for UART_IVS register ************************/ + +#define UART_IVS_TFOVER_POS 18U +#define UART_IVS_TFOVER_MSK BIT(UART_IVS_TFOVER_POS) + +#define UART_IVS_TFEMPTY_POS 16U +#define UART_IVS_TFEMPTY_MSK BIT(UART_IVS_TFEMPTY_POS) + +#define UART_IVS_TBC_POS 14U +#define UART_IVS_TBC_MSK BIT(UART_IVS_TBC_POS) + +#define UART_IVS_RFUERR_POS 13U +#define UART_IVS_RFUERR_MSK BIT(UART_IVS_RFUERR_POS) + +#define UART_IVS_RFOERR_POS 12U +#define UART_IVS_RFOERR_MSK BIT(UART_IVS_RFOERR_POS) + +#define UART_IVS_RFNEMPTY_POS 10U +#define UART_IVS_RFNEMPTY_MSK BIT(UART_IVS_RFNEMPTY_POS) + +#define UART_IVS_NOISE_POS 8U +#define UART_IVS_NOISE_MSK BIT(UART_IVS_NOISE_POS) + +#define UART_IVS_EOB_POS 7U +#define UART_IVS_EOB_MSK BIT(UART_IVS_EOB_POS) + +#define UART_IVS_LINBK_POS 6U +#define UART_IVS_LINBK_MSK BIT(UART_IVS_LINBK_POS) + +#define UART_IVS_ADDRM_POS 5U +#define UART_IVS_ADDRM_MSK BIT(UART_IVS_ADDRM_POS) + +#define UART_IVS_RXTO_POS 4U +#define UART_IVS_RXTO_MSK BIT(UART_IVS_RXTO_POS) + +#define UART_IVS_DCTS_POS 3U +#define UART_IVS_DCTS_MSK BIT(UART_IVS_DCTS_POS) + +#define UART_IVS_ABTO_POS 2U +#define UART_IVS_ABTO_MSK BIT(UART_IVS_ABTO_POS) + +#define UART_IVS_ABEND_POS 1U +#define UART_IVS_ABEND_MSK BIT(UART_IVS_ABEND_POS) + +#define UART_IVS_RXBERR_POS 0U +#define UART_IVS_RXBERR_MSK BIT(UART_IVS_RXBERR_POS) + +/****************** Bit definition for UART_RIF register ************************/ + +#define UART_RIF_TFOVER_POS 18U +#define UART_RIF_TFOVER_MSK BIT(UART_RIF_TFOVER_POS) + +#define UART_RIF_TFEMPTY_POS 16U +#define UART_RIF_TFEMPTY_MSK BIT(UART_RIF_TFEMPTY_POS) + +#define UART_RIF_TBC_POS 14U +#define UART_RIF_TBC_MSK BIT(UART_RIF_TBC_POS) + +#define UART_RIF_RFUERR_POS 13U +#define UART_RIF_RFUERR_MSK BIT(UART_RIF_RFUERR_POS) + +#define UART_RIF_RFOERR_POS 12U +#define UART_RIF_RFOERR_MSK BIT(UART_RIF_RFOERR_POS) + +#define UART_RIF_RFNEMPTY_POS 10U +#define UART_RIF_RFNEMPTY_MSK BIT(UART_RIF_RFNEMPTY_POS) + +#define UART_RIF_NOISE_POS 8U +#define UART_RIF_NOISE_MSK BIT(UART_RIF_NOISE_POS) + +#define UART_RIF_EOB_POS 7U +#define UART_RIF_EOB_MSK BIT(UART_RIF_EOB_POS) + +#define UART_RIF_LINBK_POS 6U +#define UART_RIF_LINBK_MSK BIT(UART_RIF_LINBK_POS) + +#define UART_RIF_ADDRM_POS 5U +#define UART_RIF_ADDRM_MSK BIT(UART_RIF_ADDRM_POS) + +#define UART_RIF_RXTO_POS 4U +#define UART_RIF_RXTO_MSK BIT(UART_RIF_RXTO_POS) + +#define UART_RIF_DCTS_POS 3U +#define UART_RIF_DCTS_MSK BIT(UART_RIF_DCTS_POS) + +#define UART_RIF_ABTO_POS 2U +#define UART_RIF_ABTO_MSK BIT(UART_RIF_ABTO_POS) + +#define UART_RIF_ABEND_POS 1U +#define UART_RIF_ABEND_MSK BIT(UART_RIF_ABEND_POS) + +#define UART_RIF_RXBERR_POS 0U +#define UART_RIF_RXBERR_MSK BIT(UART_RIF_RXBERR_POS) + +/****************** Bit definition for UART_IFM register ************************/ + +#define UART_IFM_TFOVER_POS 18U +#define UART_IFM_TFOVER_MSK BIT(UART_IFM_TFOVER_POS) + +#define UART_IFM_TFEMPTY_POS 16U +#define UART_IFM_TFEMPTY_MSK BIT(UART_IFM_TFEMPTY_POS) + +#define UART_IFM_TBC_POS 14U +#define UART_IFM_TBC_MSK BIT(UART_IFM_TBC_POS) + +#define UART_IFM_RFUERR_POS 13U +#define UART_IFM_RFUERR_MSK BIT(UART_IFM_RFUERR_POS) + +#define UART_IFM_RFOERR_POS 12U +#define UART_IFM_RFOERR_MSK BIT(UART_IFM_RFOERR_POS) + +#define UART_IFM_RFNEMPTY_POS 10U +#define UART_IFM_RFNEMPTY_MSK BIT(UART_IFM_RFNEMPTY_POS) + +#define UART_IFM_NOISE_POS 8U +#define UART_IFM_NOISE_MSK BIT(UART_IFM_NOISE_POS) + +#define UART_IFM_EOB_POS 7U +#define UART_IFM_EOB_MSK BIT(UART_IFM_EOB_POS) + +#define UART_IFM_LINBK_POS 6U +#define UART_IFM_LINBK_MSK BIT(UART_IFM_LINBK_POS) + +#define UART_IFM_ADDRM_POS 5U +#define UART_IFM_ADDRM_MSK BIT(UART_IFM_ADDRM_POS) + +#define UART_IFM_RXTO_POS 4U +#define UART_IFM_RXTO_MSK BIT(UART_IFM_RXTO_POS) + +#define UART_IFM_DCTS_POS 3U +#define UART_IFM_DCTS_MSK BIT(UART_IFM_DCTS_POS) + +#define UART_IFM_ABTO_POS 2U +#define UART_IFM_ABTO_MSK BIT(UART_IFM_ABTO_POS) + +#define UART_IFM_ABEND_POS 1U +#define UART_IFM_ABEND_MSK BIT(UART_IFM_ABEND_POS) + +#define UART_IFM_RXBERR_POS 0U +#define UART_IFM_RXBERR_MSK BIT(UART_IFM_RXBERR_POS) + +/****************** Bit definition for UART_ICR register ************************/ + +#define UART_ICR_TFOVER_POS 18U +#define UART_ICR_TFOVER_MSK BIT(UART_ICR_TFOVER_POS) + +#define UART_ICR_TFEMPTY_POS 16U +#define UART_ICR_TFEMPTY_MSK BIT(UART_ICR_TFEMPTY_POS) + +#define UART_ICR_TBC_POS 14U +#define UART_ICR_TBC_MSK BIT(UART_ICR_TBC_POS) + +#define UART_ICR_RFUERC_W1_POS 13U +#define UART_ICR_RFUERC_W1_MSK BIT(UART_ICR_RFUERC_W1_POS) + +#define UART_ICR_RFOERC_W1_POS 12U +#define UART_ICR_RFOERC_W1_MSK BIT(UART_ICR_RFOERC_W1_POS) + +#define UART_ICR_RFNEMPTY_POS 10U +#define UART_ICR_RFNEMPTY_MSK BIT(UART_ICR_RFNEMPTY_POS) + +#define UART_ICR_NOISE_POS 8U +#define UART_ICR_NOISE_MSK BIT(UART_ICR_NOISE_POS) + +#define UART_ICR_EOB_POS 7U +#define UART_ICR_EOB_MSK BIT(UART_ICR_EOB_POS) + +#define UART_ICR_LINBK_POS 6U +#define UART_ICR_LINBK_MSK BIT(UART_ICR_LINBK_POS) + +#define UART_ICR_ADDRM_POS 5U +#define UART_ICR_ADDRM_MSK BIT(UART_ICR_ADDRM_POS) + +#define UART_ICR_RXTO_POS 4U +#define UART_ICR_RXTO_MSK BIT(UART_ICR_RXTO_POS) + +#define UART_ICR_DCTS_POS 3U +#define UART_ICR_DCTS_MSK BIT(UART_ICR_DCTS_POS) + +#define UART_ICR_ABTO_POS 2U +#define UART_ICR_ABTO_MSK BIT(UART_ICR_ABTO_POS) + +#define UART_ICR_ABEND_POS 1U +#define UART_ICR_ABEND_MSK BIT(UART_ICR_ABEND_POS) + +#define UART_ICR_RXBERR_POS 0U +#define UART_ICR_RXBERR_MSK BIT(UART_ICR_RXBERR_POS) + +/* Exported Types ------------------------------------------------------------ */ + +typedef struct +{ + __I uint32_t RXBUF; + __IO uint32_t TXBUF; + __IO uint32_t BRR; + __IO uint32_t LCON; + __IO uint32_t MCON; + __IO uint32_t RS485; + __IO uint32_t SCARD; + __IO uint32_t LIN; + __IO uint32_t RTOR; + uint32_t RESERVED0 ; + __I uint32_t STAT; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} UART_TypeDef; + +#endif /* __REG_UART_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_usb.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_usb.h new file mode 100644 index 0000000000..f6bf6840dd --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_usb.h @@ -0,0 +1,993 @@ +/********************************************************************************** + * + * @file .h + * @brief Header file + * + * @date + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 2022.11.30 liuhy the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_USB_H__ +#define __REG_USB_H__ + +/* Includes ------------------------------------------------------------------ */ +/* Exported Macros ----------------------------------------------------------- */ + +/******************************************************************************/ +/* USB */ +/******************************************************************************/ + +/* USB */ +/* #pragma anon_unions */ + +/****************** Bit definition for USB_FADDR register ************************/ + +#define USB_FADDR_ADDR_POSS 0U +#define USB_FADDR_ADDR_POSE 6U +#define USB_FADDR_ADDR_MSK BITS(USB_FADDR_ADDR_POSS,USB_FADDR_ADDR_POSE) + +/****************** Bit definition for USB_POWER register ************************/ + +/* device/host mode */ +#define USB_POWER_ISOUDT_POS 7U +#define USB_POWER_ISOUDT_MSK BIT(USB_POWER_ISOUDT_POS) + +/* device mode */ +#define USB_POWER_RESET_POS 3U +#define USB_POWER_RESET_MSK BIT(USB_POWER_RESET_POS) + +#define USB_POWER_RESUME_POS 2U +#define USB_POWER_RESUME_MSK BIT(USB_POWER_RESUME_POS) + +#define USB_POWER_SUSPEND_POS 1U +#define USB_POWER_SUSPEND_MSK BIT(USB_POWER_SUSPEND_POS) + +/* device mode */ +#define USB_POWER_SUSPENDEN_POS 0U +#define USB_POWER_SUSPENDEN_MSK BIT(USB_POWER_SUSPENDEN_POS) + +/****************** Bit definition for USB_DPDMCON register ************************/ + +#define USB_DPDMCON_DPPUD_POSS 3U +#define USB_DPDMCON_DPPUD_POSE 4U +#define USB_DPDMCON_DPPUD_MSK BITS(USB_DPDMCON_DPPUD_POSS,USB_DPDMCON_DPPUD_POSE) + +#define USB_DPDMCON_DMPUD_POSS 1U +#define USB_DPDMCON_DMPUD_POSE 2U +#define USB_DPDMCON_DMPUD_MSK BITS(USB_DPDMCON_DMPUD_POSS,USB_DPDMCON_DMPUD_POSE) + +#define USB_DPDMCON_PHYPWREN_POS 0U +#define USB_DPDMCON_PHYPWREN_MSK BIT(USB_DPDMCON_PHYPWREN_POS) + +/****************** Bit definition for USB_SWCID register ************************/ + +#define USB_SWCID_HOST_POS 1U +#define USB_SWCID_HOST_MSK BIT(USB_SWCID_HOST_POS) + +#define USB_SWCID_CIDCTRL_POS 0U +#define USB_SWCID_CIDCTRL_MSK BIT(USB_SWCID_CIDCTRL_POS) + +/****************** Bit definition for USB_SWVBUS register ************************/ + +#define USB_SWVBUS_VALTH_POS 3U +#define USB_SWVBUS_VALTH_MSK BIT(USB_SWVBUS_VALTH_POS) + +#define USB_SWVBUS_SESVALTH_POS 2U +#define USB_SWVBUS_SESVALTH_MSK BIT(USB_SWVBUS_SESVALTH_POS) + +#define USB_SWVBUS_SESENDTH_POS 1U +#define USB_SWVBUS_SESENDTH_MSK BIT(USB_SWVBUS_SESENDTH_POS) + +#define USB_SWVBUS_SIGCTRL_POS 0U +#define USB_SWVBUS_SIGCTRL_MSK BIT(USB_SWVBUS_SIGCTRL_POS) + +/****************** Bit definition for USB_TMODE register ************************/ + +#define USB_TMODE_PROTECT_POSS 2U +#define USB_TMODE_PROTECT_POSE 7U +#define USB_TMODE_PROTECT_MSK BITS(USB_TMODE_PROTECT_POSS,USB_TMODE_PROTECT_POSE) + +#define USB_TMODE_MEMTST_EN_POS 1U +#define USB_TMODE_MEMTST_EN_MSK BIT(USB_TMODE_MEMTST_EN_POS) +#define USB_TMODE_MEMTST_EN USB_TMODE_MEMTST_EN_MSK + +#define USB_TMODE_ENABLE_POS 0U +#define USB_TMODE_ENABLE_MSK BIT(USB_TMODE_ENABLE_POS) + +/****************** Bit definition for USB_FRAME1 register ************************/ + +#define USB_FRAME1_LOWFRAME_POSS 0U +#define USB_FRAME1_LOWFRAME_POSE 7U +#define USB_FRAME1_LOWFRAME_MSK BITS(USB_FRAME1_LOWFRAME_POSS,USB_FRAME1_LOWFRAME_POSE) + +/****************** Bit definition for USB_FRAME2 register ************************/ + +#define USB_FRAME2_UPFRAME_POSS 0U +#define USB_FRAME2_UPFRAME_POSE 2U +#define USB_FRAME2_UPFRAME_MSK BITS(USB_FRAME2_UPFRAME_POSS,USB_FRAME2_UPFRAME_POSE) + +/****************** Bit definition for USB_INDEX register ************************/ + +#define USB_INDEX_EPTIDX_POSS 0U +#define USB_INDEX_EPTIDX_POSE 3U +#define USB_INDEX_EPTIDX_MSK BITS(USB_INDEX_EPTIDX_POSS,USB_INDEX_EPTIDX_POSE) + +/****************** Bit definition for USB_DEVCON register ************************/ + +#define USB_DEVCON_FSDEV_POS 6U +#define USB_DEVCON_FSDEV_MSK BIT(USB_DEVCON_FSDEV_POS) + +#define USB_DEVCON_LSDEV_POS 5U +#define USB_DEVCON_LSDEV_MSK BIT(USB_DEVCON_LSDEV_POS) + +#define USB_DEVCON_HOST_POS 2U +#define USB_DEVCON_HOST_MSK BIT(USB_DEVCON_HOST_POS) + +#define USB_DEVCON_HOSTREQ_POS 1U +#define USB_DEVCON_HOSTREQ_MSK BIT(USB_DEVCON_HOSTREQ_POS) + +#define USB_DEVCON_SESSION_POS 0U +#define USB_DEVCON_SESSION_MSK BIT(USB_DEVCON_SESSION_POS) + +/****************** Bit definition for USB_TXMAXP register ************************/ + +#define USB_TXMAXP_MAXSIZE_POSS 0U +#define USB_TXMAXP_MAXSIZE_POSE 7U +#define USB_TXMAXP_MAXSIZE_MSK BITS(USB_TXMAXP_MAXSIZE_POSS,USB_TXMAXP_MAXSIZE_POSE) + +/****************** Bit definition for USB_CSR0L_TXCSRL register ************************/ + +/* Endpoint 0 */ +/* device mode */ +#define USB_CSR0L_SETENDC_POS 7U +#define USB_CSR0L_SETENDC_MSK BIT(USB_CSR0L_SETENDC_POS) + +#define USB_CSR0L_RXRDYC_POS 6U +#define USB_CSR0L_RXRDYC_MSK BIT(USB_CSR0L_RXRDYC_POS) + +#define USB_CSR0L_STALL_POS 5U +#define USB_CSR0L_STALL_MSK BIT(USB_CSR0L_STALL_POS) + +#define USB_CSR0L_SETEND_POS 4U +#define USB_CSR0L_SETEND_MSK BIT(USB_CSR0L_SETEND_POS) + +#define USB_CSR0L_DATAEND_POS 3U +#define USB_CSR0L_DATAEND_MSK BIT(USB_CSR0L_DATAEND_POS) + +/* host mode */ +#define USB_CSR0L_NAKTO_POS 7U +#define USB_CSR0L_NAKTO_MSK BIT(USB_CSR0L_NAKTO_POS) + +#define USB_CSR0L_STATUSPKT_POS 6U +#define USB_CSR0L_STATUSPKT_MSK BIT(USB_CSR0L_STATUSPKT_POS) + +#define USB_CSR0L_REQPKT_POS 5U +#define USB_CSR0L_REQPKT_MSK BIT(USB_CSR0L_REQPKT_POS) + +#define USB_CSR0L_ERROR_POS 4U +#define USB_CSR0L_ERROR_MSK BIT(USB_CSR0L_ERROR_POS) + +#define USB_CSR0L_SETUPPKT_POS 3U +#define USB_CSR0L_SETUPPKT_MSK BIT(USB_CSR0L_SETUPPKT_POS) + +/* device/host mode */ +#define USB_CSR0L_STALLED_POS 2U +#define USB_CSR0L_STALLED_MSK BIT(USB_CSR0L_STALLED_POS) + +#define USB_CSR0L_TXRDY_POS 1U +#define USB_CSR0L_TXRDY_MSK BIT(USB_CSR0L_TXRDY_POS) + +#define USB_CSR0L_RXRDY_POS 0U +#define USB_CSR0L_RXRDY_MSK BIT(USB_CSR0L_RXRDY_POS) + +/* Endpoint 1-6 */ +/* host mode */ +#define USB_TXCSRL_NAKTO_POS 7U +#define USB_TXCSRL_NAKTO_MSK BIT(USB_TXCSRL_NAKTO_POS) + +/* device/host mode */ +#define USB_TXCSRL_CLRDT_POS 6U +#define USB_TXCSRL_CLRDT_MSK BIT(USB_TXCSRL_CLRDT_POS) + +#define USB_TXCSRL_STALLED_POS 5U +#define USB_TXCSRL_STALLED_MSK BIT(USB_TXCSRL_STALLED_POS) + +/* device mode */ +#define USB_TXCSRL_STALL_POS 4U +#define USB_TXCSRL_STALL_MSK BIT(USB_TXCSRL_STALL_POS) + +/* device/host mode */ +#define USB_TXCSRL_FLUSH_POS 3U +#define USB_TXCSRL_FLUSH_MSK BIT(USB_TXCSRL_FLUSH_POS) + +/* device mode */ +#define USB_TXCSRL_UNDRUN_POS 2U +#define USB_TXCSRL_UNDRUN_MSK BIT(USB_TXCSRL_UNDRUN_POS) + +/* host mode */ +#define USB_TXCSRL_ERROR_POS 2U +#define USB_TXCSRL_ERROR_MSK BIT(USB_TXCSRL_ERROR_POS) + +/* device/host mode */ +#define USB_TXCSRL_FIFONE_POS 1U +#define USB_TXCSRL_FIFONE_MSK BIT(USB_TXCSRL_FIFONE_POS) + +#define USB_TXCSRL_TXRDY_POS 0U +#define USB_TXCSRL_TXRDY_MSK BIT(USB_TXCSRL_TXRDY_POS) + +/****************** Bit definition for USB_CSR0H_TXCSRH register ************************/ + +/* Endpoint 0 */ +/* device/host mode */ +#define USB_CSR0H_FLUSH_POS 0U +#define USB_CSR0H_FLUSH_MSK BIT(USB_CSR0H_FLUSH_POS) + +/* For endpoint 1-6 */ +/* device/host mode */ +#define USB_TXCSRH_AUTOSET_POS 7U +#define USB_TXCSRH_AUTOSET_MSK BIT(USB_TXCSRH_AUTOSET_POS) + +#define USB_TXCSRH_ISO_POS 6U +#define USB_TXCSRH_ISO_MSK BIT(USB_TXCSRH_ISO_POS) + +#define USB_TXCSRH_MODE_POS 5U +#define USB_TXCSRH_MODE_MSK BIT(USB_TXCSRH_MODE_POS) + +#define USB_TXCSRH_FDT_POS 3U +#define USB_TXCSRH_FDT_MSK BIT(USB_TXCSRH_FDT_POS) + +/****************** Bit definition for USB_RXMAXP register ************************/ + +#define USB_RXMAXP_MAXSIZE_POSS 0U +#define USB_RXMAXP_MAXSIZE_POSE 7U +#define USB_RXMAXP_MAXSIZE_MSK BITS(USB_RXMAXP_MAXSIZE_POSS,USB_RXMAXP_MAXSIZE_POSE) + +/****************** Bit definition for USB_RXCSRL register ************************/ + +/* device/host mode */ +#define USB_RXCSRL_CLRDT_POS 7U +#define USB_RXCSRL_CLRDT_MSK BIT(USB_RXCSRL_CLRDT_POS) + +#define USB_RXCSRL_STALLED_POS 6U +#define USB_RXCSRL_STALLED_MSK BIT(USB_RXCSRL_STALLED_POS) + +/* device mode */ +#define USB_RXCSRL_STALL_POS 5U +#define USB_RXCSRL_STALL_MSK BIT(USB_RXCSRL_STALL_POS) + +/* host mode */ +#define USB_RXCSRL_REQPKT_POS 5U +#define USB_RXCSRL_REQPKT_MSK BIT(USB_RXCSRL_REQPKT_POS) + +/* device/host mode */ +#define USB_RXCSRL_FLUSH_POS 4U +#define USB_RXCSRL_FLUSH_MSK BIT(USB_RXCSRL_FLUSH_POS) + +/* device/host mode */ +#define USB_RXCSRL_DATAERR_POS 3U +#define USB_RXCSRL_DATAERR_MSK BIT(USB_RXCSRL_DATAERR_POS) + +/* host mode */ +#define USB_RXCSRL_NAKTO_POS 3U +#define USB_RXCSRL_NAKTO_MSK BIT(USB_RXCSRL_NAKTO_POS) + +/* device mode */ +#define USB_RXCSRL_OVERRUN_POS 2U +#define USB_RXCSRL_OVERRUN_MSK BIT(USB_RXCSRL_OVERRUN_POS) + +/* host mode */ +#define USB_RXCSRL_ERROR_POS 2U +#define USB_RXCSRL_ERROR_MSK BIT(USB_RXCSRL_ERROR_POS) + +/* device/host mode */ +#define USB_RXCSRL_FULL_POS 1U +#define USB_RXCSRL_FULL_MSK BIT(USB_RXCSRL_FULL_POS) + +#define USB_RXCSRL_RXRDY_POS 0U +#define USB_RXCSRL_RXRDY_MSK BIT(USB_RXCSRL_RXRDY_POS) + +/****************** Bit definition for USB_RXCSRH register ************************/ + +/* device/host mode */ +#define USB_RXCSRH_AUTOCLR_POS 7U +#define USB_RXCSRH_AUTOCLR_MSK BIT(USB_RXCSRH_AUTOCLR_POS) + +/* device mode */ +#define USB_RXCSRH_ISO_POS 6U +#define USB_RXCSRH_ISO_MSK BIT(USB_RXCSRH_ISO_POS) + +/* host mode */ +#define USB_RXCSRH_AUTOREQ_POS 6U +#define USB_RXCSRH_AUTOREQ_MSK BIT(USB_RXCSRH_AUTOREQ_POS) + +/****************** Bit definition for USB_COUNT0_RX1 register ************************/ + +/* Endpoint 0 */ +#define USB_COUNT0_COUNT_POSS 0U +#define USB_COUNT0_COUNT_POSE 6U +#define USB_COUNT0_COUNT_MSK BITS(USB_COUNT0_COUNT_POSS,USB_COUNT0_COUNT_POSE) + +/* +For endpoint 1-6 +*/ +#define USB_RX1_PKTLOW_POSS 0U +#define USB_RX1_PKTLOW_POSE 7U +#define USB_RX1_PKTLOW_MSK BITS(USB_RX1_PKTLOW_POSS,USB_RX1_PKTLOW_POSE) + +/****************** Bit definition for USB_RXCOUNT2 register ************************/ + +#define USB_RXCOUNT2_PKTHIGH_POSS 0U +#define USB_RXCOUNT2_PKTHIGH_POSE 2U +#define USB_RXCOUNT2_PKTHIGH_MSK BITS(USB_RXCOUNT2_PKTHIGH_POSS,USB_RXCOUNT2_PKTHIGH_POSE) + +/****************** Bit definition for USB_TXTYPE register ************************/ + +#define USB_TXTYPE_PROTOCOL_POSS 4U +#define USB_TXTYPE_PROTOCOL_POSE 5U +#define USB_TXTYPE_PROTOCOL_MSK BITS(USB_TXTYPE_PROTOCOL_POSS,USB_TXTYPE_PROTOCOL_POSE) + +#define USB_TXTYPE_TEPN_POSS 0U +#define USB_TXTYPE_TEPN_POSE 3U +#define USB_TXTYPE_TEPN_MSK BITS(USB_TXTYPE_TEPN_POSS,USB_TXTYPE_TEPN_POSE) + +/****************** Bit definition for USB_NAKLIMIT0_TXINTERVAL register ************************/ + +/* Endpoint 0 */ +#define USB_NAKLIMIT0_NAKLMT_POSS 0U +#define USB_NAKLIMIT0_NAKLMT_POSE 7U +#define USB_NAKLIMIT0_NAKLMT_MSK BITS(USB_NAKLIMIT0_NAKLMT_POSS,USB_NAKLIMIT0_NAKLMT_POSE) + +/* For endpoint 1-6 */ +#define USB_TXINTERVAL_TXPOLL_POSS 0U +#define USB_TXINTERVAL_TXPOLL_POSE 7U +#define USB_TXINTERVAL_TXPOLL_MSK BITS(USB_TXINTERVAL_TXPOLL_POSS,USB_TXINTERVAL_TXPOLL_POSE) + +#define USB_TXINTERVAL_NAKLMT_POSS 0U +#define USB_TXINTERVAL_NAKLMT_POSE 7U +#define USB_TXINTERVAL_NAKLMT_MSK BITS(USB_TXINTERVAL_NAKLMT_POSS,USB_TXINTERVAL_NAKLMT_POSE) + +/****************** Bit definition for USB_RXTYPE register ************************/ + +#define USB_RXTYPE_PROTOCOL_POSS 4U +#define USB_RXTYPE_PROTOCOL_POSE 5U +#define USB_RXTYPE_PROTOCOL_MSK BITS(USB_RXTYPE_PROTOCOL_POSS,USB_RXTYPE_PROTOCOL_POSE) + +#define USB_RXTYPE_TEPN_POSS 0U +#define USB_RXTYPE_TEPN_POSE 3U +#define USB_RXTYPE_TEPN_MSK BITS(USB_RXTYPE_TEPN_POSS,USB_RXTYPE_TEPN_POSE) + +/****************** Bit definition for USB_RXINTERVAL register ************************/ + +#define USB_RXINTERVAL_RXPOLL_POSS 0U +#define USB_RXINTERVAL_RXPOLL_POSE 7U +#define USB_RXINTERVAL_RXPOLL_MSK BITS(USB_RXINTERVAL_RXPOLL_POSS,USB_RXINTERVAL_RXPOLL_POSE) + +#define USB_RXINTERVAL_NAKLMT_POSS 0U +#define USB_RXINTERVAL_NAKLMT_POSE 7U +#define USB_RXINTERVAL_NAKLMT_MSK BITS(USB_RXINTERVAL_NAKLMT_POSS,USB_RXINTERVAL_NAKLMT_POSE) + +/****************** Bit definition for USB_TXFIFO1 register ************************/ + +#define USB_TXFIFO1_ADDRL_POSS 0U +#define USB_TXFIFO1_ADDRL_POSE 7U +#define USB_TXFIFO1_ADDRL_MSK BITS(USB_TXFIFO1_ADDRL_POSS,USB_TXFIFO1_ADDRL_POSE) + +/****************** Bit definition for USB_TXFIFO2 register ************************/ + +#define USB_TXFIFO2_MAXPKTSIZE_POSS 5U +#define USB_TXFIFO2_MAXPKTSIZE_POSE 7U +#define USB_TXFIFO2_MAXPKTSIZE_MSK BITS(USB_TXFIFO2_MAXPKTSIZE_POSS,USB_TXFIFO2_MAXPKTSIZE_POSE) + +#define USB_TXFIFO2_DPB_POS 4U +#define USB_TXFIFO2_DPB_MSK BIT(USB_TXFIFO2_DPB_POS) + +#define USB_TXFIFO2_ADDRH_POSS 0U +#define USB_TXFIFO2_ADDRH_POSE 3U +#define USB_TXFIFO2_ADDRH_MSK BITS(USB_TXFIFO2_ADDRH_POSS,USB_TXFIFO2_ADDRH_POSE) + +/****************** Bit definition for USB_RXFIFO1 register ************************/ + +#define USB_RXFIFO1_ADDRL_POSS 0U +#define USB_RXFIFO1_ADDRL_POSE 7U +#define USB_RXFIFO1_ADDRL_MSK BITS(USB_RXFIFO1_ADDRL_POSS,USB_RXFIFO1_ADDRL_POSE) + +/****************** Bit definition for USB_RXFIFO2 register ************************/ + +#define USB_RXFIFO2_MAXPKTSIZE_POSS 5U +#define USB_RXFIFO2_MAXPKTSIZE_POSE 7U +#define USB_RXFIFO2_MAXPKTSIZE_MSK BITS(USB_RXFIFO2_MAXPKTSIZE_POSS,USB_RXFIFO2_MAXPKTSIZE_POSE) + +#define USB_RXFIFO2_DPB_POS 4U +#define USB_RXFIFO2_DPB_MSK BIT(USB_RXFIFO2_DPB_POS) + +#define USB_RXFIFO2_ADDRH_POSS 0U +#define USB_RXFIFO2_ADDRH_POSE 3U +#define USB_RXFIFO2_ADDRH_MSK BITS(USB_RXFIFO2_ADDRH_POSS,USB_RXFIFO2_ADDRH_POSE) + +/************* Bit definition for USB_EP0FIFO/USB_EPxFIFO register *****************/ + +#define USB_EP0FIFO_FIFO0_POSS 0U +#define USB_EP0FIFO_FIFO0_POSE 7U +#define USB_EP0FIFO_FIFO0_MSK BITS(USB_EP0FIFO_FIFO0_POSS,USB_EP0FIFO_FIFO0_POSE) + +#define USB_EP1FIFO_FIFO1_POSS 0U +#define USB_EP1FIFO_FIFO1_POSE 7U +#define USB_EP1FIFO_FIFO1_MSK BITS(USB_EP1FIFO_FIFO1_POSS,USB_EP1FIFO_FIFO1_POSE) + +#define USB_EP2FIFO_FIFO2_POSS 0U +#define USB_EP2FIFO_FIFO2_POSE 7U +#define USB_EP2FIFO_FIFO2_MSK BITS(USB_EP2FIFO_FIFO2_POSS,USB_EP2FIFO_FIFO2_POSE) + +#define USB_EP3FIFO_FIFO3_POSS 0U +#define USB_EP3FIFO_FIFO3_POSE 7U +#define USB_EP3FIFO_FIFO3_MSK BITS(USB_EP3FIFO_FIFO3_POSS,USB_EP3FIFO_FIFO3_POSE) + +#define USB_EP4FIFO_FIFO4_POSS 0U +#define USB_EP4FIFO_FIFO4_POSE 7U +#define USB_EP4FIFO_FIFO4_MSK BITS(USB_EP4FIFO_FIFO4_POSS,USB_EP4FIFO_FIFO4_POSE) + +#define USB_EP5FIFO_FIFO5_POSS 0U +#define USB_EP5FIFO_FIFO5_POSE 7U +#define USB_EP5FIFO_FIFO5_MSK BITS(USB_EP5FIFO_FIFO5_POSS,USB_EP5FIFO_FIFO5_POSE) + +#define USB_EP6FIFO_FIFO6_POSS 0U +#define USB_EP6FIFO_FIFO6_POSE 7U +#define USB_EP6FIFO_FIFO6_MSK BITS(USB_EP6FIFO_FIFO6_POSS,USB_EP6FIFO_FIFO6_POSE) + +#define USB_EPxFIFO_FIFOx_POSS 0U +#define USB_EPxFIFO_FIFOx_POSE 7U +#define USB_EPxFIFO_FIFOx_MSK BITS(USB_EPxFIFO_FIFOx_POSS,USB_EPxFIFO_FIFOx_POSE) + +/****************** Bit definition for USB_TXIER register ************************/ + +#define USB_TXIER_EP6IE_POS 6U +#define USB_TXIER_EP6IE_MSK BIT(USB_TXIER_EP6IE_POS) + +#define USB_TXIER_EP5IE_POS 5U +#define USB_TXIER_EP5IE_MSK BIT(USB_TXIER_EP5IE_POS) + +#define USB_TXIER_EP4IE_POS 4U +#define USB_TXIER_EP4IE_MSK BIT(USB_TXIER_EP4IE_POS) + +#define USB_TXIER_EP3IE_POS 3U +#define USB_TXIER_EP3IE_MSK BIT(USB_TXIER_EP3IE_POS) + +#define USB_TXIER_EP2IE_POS 2U +#define USB_TXIER_EP2IE_MSK BIT(USB_TXIER_EP2IE_POS) + +#define USB_TXIER_EP1IE_POS 1U +#define USB_TXIER_EP1IE_MSK BIT(USB_TXIER_EP1IE_POS) + +#define USB_TXIER_EP0IE_POS 0U +#define USB_TXIER_EP0IE_MSK BIT(USB_TXIER_EP0IE_POS) + +/****************** Bit definition for USB_RXIER register ************************/ + +#define USB_RXIER_EP6IE_POS 6U +#define USB_RXIER_EP6IE_MSK BIT(USB_RXIER_EP6IE_POS) + +#define USB_RXIER_EP5IE_POS 5U +#define USB_RXIER_EP5IE_MSK BIT(USB_RXIER_EP5IE_POS) + +#define USB_RXIER_EP4IE_POS 4U +#define USB_RXIER_EP4IE_MSK BIT(USB_RXIER_EP4IE_POS) + +#define USB_RXIER_EP3IE_POS 3U +#define USB_RXIER_EP3IE_MSK BIT(USB_RXIER_EP3IE_POS) + +#define USB_RXIER_EP2IE_POS 2U +#define USB_RXIER_EP2IE_MSK BIT(USB_RXIER_EP2IE_POS) + +#define USB_RXIER_EP1IE_POS 1U +#define USB_RXIER_EP1IE_MSK BIT(USB_RXIER_EP1IE_POS) + +/****************** Bit definition for USB_TXIDR register ************************/ + +#define USB_TXIDR_EP6ID_POS 6U +#define USB_TXIDR_EP6ID_MSK BIT(USB_TXIDR_EP6ID_POS) + +#define USB_TXIDR_EP5ID_POS 5U +#define USB_TXIDR_EP5ID_MSK BIT(USB_TXIDR_EP5ID_POS) + +#define USB_TXIDR_EP4ID_POS 4U +#define USB_TXIDR_EP4ID_MSK BIT(USB_TXIDR_EP4ID_POS) + +#define USB_TXIDR_EP3ID_POS 3U +#define USB_TXIDR_EP3ID_MSK BIT(USB_TXIDR_EP3ID_POS) + +#define USB_TXIDR_EP2ID_POS 2U +#define USB_TXIDR_EP2ID_MSK BIT(USB_TXIDR_EP2ID_POS) + +#define USB_TXIDR_EP1ID_POS 1U +#define USB_TXIDR_EP1ID_MSK BIT(USB_TXIDR_EP1ID_POS) + +#define USB_TXIDR_EP0ID_POS 0U +#define USB_TXIDR_EP0ID_MSK BIT(USB_TXIDR_EP0ID_POS) + +/****************** Bit definition for USB_RXIDR register ************************/ + +#define USB_RXIDR_EP6ID_POS 6U +#define USB_RXIDR_EP6ID_MSK BIT(USB_RXIDR_EP6ID_POS) + +#define USB_RXIDR_EP5ID_POS 5U +#define USB_RXIDR_EP5ID_MSK BIT(USB_RXIDR_EP5ID_POS) + +#define USB_RXIDR_EP4ID_POS 4U +#define USB_RXIDR_EP4ID_MSK BIT(USB_RXIDR_EP4ID_POS) + +#define USB_RXIDR_EP3ID_POS 3U +#define USB_RXIDR_EP3ID_MSK BIT(USB_RXIDR_EP3ID_POS) + +#define USB_RXIDR_EP2ID_POS 2U +#define USB_RXIDR_EP2ID_MSK BIT(USB_RXIDR_EP2ID_POS) + +#define USB_RXIDR_EP1ID_POS 1U +#define USB_RXIDR_EP1ID_MSK BIT(USB_RXIDR_EP1ID_POS) + +/****************** Bit definition for USB_TXIVS register ************************/ + +#define USB_TXIVS_EP6IVS_POS 6U +#define USB_TXIVS_EP6IVS_MSK BIT(USB_TXIVS_EP6IVS_POS) + +#define USB_TXIVS_EP5IVS_POS 5U +#define USB_TXIVS_EP5IVS_MSK BIT(USB_TXIVS_EP5IVS_POS) + +#define USB_TXIVS_EP4IVS_POS 4U +#define USB_TXIVS_EP4IVS_MSK BIT(USB_TXIVS_EP4IVS_POS) + +#define USB_TXIVS_EP3IVS_POS 3U +#define USB_TXIVS_EP3IVS_MSK BIT(USB_TXIVS_EP3IVS_POS) + +#define USB_TXIVS_EP2IVS_POS 2U +#define USB_TXIVS_EP2IVS_MSK BIT(USB_TXIVS_EP2IVS_POS) + +#define USB_TXIVS_EP1IVS_POS 1U +#define USB_TXIVS_EP1IVS_MSK BIT(USB_TXIVS_EP1IVS_POS) + +#define USB_TXIVS_EP0IVS_POS 0U +#define USB_TXIVS_EP0IVS_MSK BIT(USB_TXIVS_EP0IVS_POS) + +/****************** Bit definition for USB_RXIVS register ************************/ + +#define USB_RXIVS_EP6IVS_POS 6U +#define USB_RXIVS_EP6IVS_MSK BIT(USB_RXIVS_EP6IVS_POS) + +#define USB_RXIVS_EP5IVS_POS 5U +#define USB_RXIVS_EP5IVS_MSK BIT(USB_RXIVS_EP5IVS_POS) + +#define USB_RXIVS_EP4IVS_POS 4U +#define USB_RXIVS_EP4IVS_MSK BIT(USB_RXIVS_EP4IVS_POS) + +#define USB_RXIVS_EP3IVS_POS 3U +#define USB_RXIVS_EP3IVS_MSK BIT(USB_RXIVS_EP3IVS_POS) + +#define USB_RXIVS_EP2IVS_POS 2U +#define USB_RXIVS_EP2IVS_MSK BIT(USB_RXIVS_EP2IVS_POS) + +#define USB_RXIVS_EP1IVS_POS 1U +#define USB_RXIVS_EP1IVS_MSK BIT(USB_RXIVS_EP1IVS_POS) + +/****************** Bit definition for USB_TXRIF register ************************/ + +#define USB_TXRIF_EP6RIF_POS 6U +#define USB_TXRIF_EP6RIF_MSK BIT(USB_TXRIF_EP6RIF_POS) + +#define USB_TXRIF_EP5RIF_POS 5U +#define USB_TXRIF_EP5RIF_MSK BIT(USB_TXRIF_EP5RIF_POS) + +#define USB_TXRIF_EP4RIF_POS 4U +#define USB_TXRIF_EP4RIF_MSK BIT(USB_TXRIF_EP4RIF_POS) + +#define USB_TXRIF_EP3RIF_POS 3U +#define USB_TXRIF_EP3RIF_MSK BIT(USB_TXRIF_EP3RIF_POS) + +#define USB_TXRIF_EP2RIF_POS 2U +#define USB_TXRIF_EP2RIF_MSK BIT(USB_TXRIF_EP2RIF_POS) + +#define USB_TXRIF_EP1RIF_POS 1U +#define USB_TXRIF_EP1RIF_MSK BIT(USB_TXRIF_EP1RIF_POS) + +#define USB_TXRIF_EP0RIF_POS 0U +#define USB_TXRIF_EP0RIF_MSK BIT(USB_TXRIF_EP0RIF_POS) + +/****************** Bit definition for USB_RXRIF register ************************/ + +#define USB_RXRIF_EP6RIF_POS 6U +#define USB_RXRIF_EP6RIF_MSK BIT(USB_RXRIF_EP6RIF_POS) + +#define USB_RXRIF_EP5RIF_POS 5U +#define USB_RXRIF_EP5RIF_MSK BIT(USB_RXRIF_EP5RIF_POS) + +#define USB_RXRIF_EP4RIF_POS 4U +#define USB_RXRIF_EP4RIF_MSK BIT(USB_RXRIF_EP4RIF_POS) + +#define USB_RXRIF_EP3RIF_POS 3U +#define USB_RXRIF_EP3RIF_MSK BIT(USB_RXRIF_EP3RIF_POS) + +#define USB_RXRIF_EP2RIF_POS 2U +#define USB_RXRIF_EP2RIF_MSK BIT(USB_RXRIF_EP2RIF_POS) + +#define USB_RXRIF_EP1RIF_POS 1U +#define USB_RXRIF_EP1RIF_MSK BIT(USB_RXRIF_EP1RIF_POS) + +/****************** Bit definition for USB_TXIFM register ************************/ + +#define USB_TXIFM_EP6IFM_POS 6U +#define USB_TXIFM_EP6IFM_MSK BIT(USB_TXIFM_EP6IFM_POS) + +#define USB_TXIFM_EP5IFM_POS 5U +#define USB_TXIFM_EP5IFM_MSK BIT(USB_TXIFM_EP5IFM_POS) + +#define USB_TXIFM_EP4IFM_POS 4U +#define USB_TXIFM_EP4IFM_MSK BIT(USB_TXIFM_EP4IFM_POS) + +#define USB_TXIFM_EP3IFM_POS 3U +#define USB_TXIFM_EP3IFM_MSK BIT(USB_TXIFM_EP3IFM_POS) + +#define USB_TXIFM_EP2IFM_POS 2U +#define USB_TXIFM_EP2IFM_MSK BIT(USB_TXIFM_EP2IFM_POS) + +#define USB_TXIFM_EP1IFM_POS 1U +#define USB_TXIFM_EP1IFM_MSK BIT(USB_TXIFM_EP1IFM_POS) + +#define USB_TXIFM_EP0IFM_POS 0U +#define USB_TXIFM_EP0IFM_MSK BIT(USB_TXIFM_EP0IFM_POS) + +/****************** Bit definition for USB_RXIFM register ************************/ + +#define USB_RXIFM_EP6IFM_POS 6U +#define USB_RXIFM_EP6IFM_MSK BIT(USB_RXIFM_EP6IFM_POS) + +#define USB_RXIFM_EP5IFM_POS 5U +#define USB_RXIFM_EP5IFM_MSK BIT(USB_RXIFM_EP5IFM_POS) + +#define USB_RXIFM_EP4IFM_POS 4U +#define USB_RXIFM_EP4IFM_MSK BIT(USB_RXIFM_EP4IFM_POS) + +#define USB_RXIFM_EP3IFM_POS 3U +#define USB_RXIFM_EP3IFM_MSK BIT(USB_RXIFM_EP3IFM_POS) + +#define USB_RXIFM_EP2IFM_POS 2U +#define USB_RXIFM_EP2IFM_MSK BIT(USB_RXIFM_EP2IFM_POS) + +#define USB_RXIFM_EP1IFM_POS 1U +#define USB_RXIFM_EP1IFM_MSK BIT(USB_RXIFM_EP1IFM_POS) + +/****************** Bit definition for USB_TXICR register ************************/ + +#define USB_TXICR_EP6ICR_POS 6U +#define USB_TXICR_EP6ICR_MSK BIT(USB_TXICR_EP6ICR_POS) + +#define USB_TXICR_EP5ICR_POS 5U +#define USB_TXICR_EP5ICR_MSK BIT(USB_TXICR_EP5ICR_POS) + +#define USB_TXICR_EP4ICR_POS 4U +#define USB_TXICR_EP4ICR_MSK BIT(USB_TXICR_EP4ICR_POS) + +#define USB_TXICR_EP3ICR_POS 3U +#define USB_TXICR_EP3ICR_MSK BIT(USB_TXICR_EP3ICR_POS) + +#define USB_TXICR_EP2ICR_POS 2U +#define USB_TXICR_EP2ICR_MSK BIT(USB_TXICR_EP2ICR_POS) + +#define USB_TXICR_EP1ICR_POS 1U +#define USB_TXICR_EP1ICR_MSK BIT(USB_TXICR_EP1ICR_POS) + +#define USB_TXICR_EP0ICR_POS 0U +#define USB_TXICR_EP0ICR_MSK BIT(USB_TXICR_EP0ICR_POS) + +/****************** Bit definition for USB_RXICR register ************************/ + +#define USB_RXICR_EP6ICR_POS 6U +#define USB_RXICR_EP6ICR_MSK BIT(USB_RXICR_EP6ICR_POS) + +#define USB_RXICR_EP5ICR_POS 5U +#define USB_RXICR_EP5ICR_MSK BIT(USB_RXICR_EP5ICR_POS) + +#define USB_RXICR_EP4ICR_POS 4U +#define USB_RXICR_EP4ICR_MSK BIT(USB_RXICR_EP4ICR_POS) + +#define USB_RXICR_EP3ICR_POS 3U +#define USB_RXICR_EP3ICR_MSK BIT(USB_RXICR_EP3ICR_POS) + +#define USB_RXICR_EP2ICR_POS 2U +#define USB_RXICR_EP2ICR_MSK BIT(USB_RXICR_EP2ICR_POS) + +#define USB_RXICR_EP1ICR_POS 1U +#define USB_RXICR_EP1ICR_MSK BIT(USB_RXICR_EP1ICR_POS) + +/****************** Bit definition for USB_IER register ************************/ + +/* device/host mode */ +#define USB_IER_SESREQIE_POS 6U +#define USB_IER_SESREQIE_MSK BIT(USB_IER_SESREQIE_POS) + +#define USB_IER_DISCONIE_POS 5U +#define USB_IER_DISCONIE_MSK BIT(USB_IER_DISCONIE_POS) + +/* host mode */ +#define USB_IER_CONIE_POS 4U +#define USB_IER_CONIE_MSK BIT(USB_IER_CONIE_POS) + +/* device/host mode */ +#define USB_IER_SOFIE_POS 3U +#define USB_IER_SOFIE_MSK BIT(USB_IER_SOFIE_POS) + +/* device mode */ +#define USB_IER_RESTIE_POS 2U +#define USB_IER_RESTIE_MSK BIT(USB_IER_RESTIE_POS) + +/* host mode */ +#define USB_IER_BABIE_POS 2U +#define USB_IER_BABIE_MSK BIT(USB_IER_BABIE_POS) + +/* device/host mode */ +#define USB_IER_RESIE_POS 1U +#define USB_IER_RESIE_MSK BIT(USB_IER_RESIE_POS) + +#define USB_IER_SUSPDIE_POS 0U +#define USB_IER_SUSPDIE_MSK BIT(USB_IER_SUSPDIE_POS) + +/****************** Bit definition for USB_IDR register ************************/ + +/* device/host mode */ +#define USB_IDR_SESREQID_POS 6U +#define USB_IDR_SESREQID_MSK BIT(USB_IDR_SESREQID_POS) + +#define USB_IDR_DISCONID_POS 5U +#define USB_IDR_DISCONID_MSK BIT(USB_IDR_DISCONID_POS) + +/* host mode */ +#define USB_IDR_CONID_POS 4U +#define USB_IDR_CONID_MSK BIT(USB_IDR_CONID_POS) + +/* device/host mode */ +#define USB_IDR_SOFID_POS 3U +#define USB_IDR_SOFID_MSK BIT(USB_IDR_SOFID_POS) + +/* device mode */ +#define USB_IDR_RESTID_POS 2U +#define USB_IDR_RESTID_MSK BIT(USB_IDR_RESTID_POS) + +/* host mode */ +#define USB_IDR_BABID_POS 2U +#define USB_IDR_BABID_MSK BIT(USB_IDR_BABID_POS) + +/* device/host mode */ +#define USB_IDR_RESID_POS 1U +#define USB_IDR_RESID_MSK BIT(USB_IDR_RESID_POS) + +#define USB_IDR_SUSPDID_POS 0U +#define USB_IDR_SUSPDID_MSK BIT(USB_IDR_SUSPDID_POS) + +/****************** Bit definition for USB_IVS register ************************/ + +/* device/host mode */ +#define USB_IVS_SESREQIVS_POS 6U +#define USB_IVS_SESREQIVS_MSK BIT(USB_IVS_SESREQIVS_POS) + +#define USB_IVS_DISCONIVS_POS 5U +#define USB_IVS_DISCONIVS_MSK BIT(USB_IVS_DISCONIVS_POS) + +/* host mode */ +#define USB_IVS_CONIVS_POS 4U +#define USB_IVS_CONIVS_MSK BIT(USB_IVS_CONIVS_POS) + +/* device/host mode */ +#define USB_IVS_SOFIVS_POS 3U +#define USB_IVS_SOFIVS_MSK BIT(USB_IVS_SOFIVS_POS) + +/* device mode */ +#define USB_IVS_RESTIVS_POS 2U +#define USB_IVS_RESTIVS_MSK BIT(USB_IVS_RESTIVS_POS) + +/* host mode */ +#define USB_IVS_BABIVS_POS 2U +#define USB_IVS_BABIVS_MSK BIT(USB_IVS_BABIVS_POS) + +/* device/host mode */ +#define USB_IVS_RESIVS_POS 1U +#define USB_IVS_RESIVS_MSK BIT(USB_IVS_RESIVS_POS) + +#define USB_IVS_SUSPDIVS_POS 0U +#define USB_IVS_SUSPDIVS_MSK BIT(USB_IVS_SUSPDIVS_POS) + +/****************** Bit definition for USB_RIF register ************************/ + +/* device/host mode */ +#define USB_RIF_SESREQRIF_POS 6U +#define USB_RIF_SESREQRIF_MSK BIT(USB_RIF_SESREQRIF_POS) + +#define USB_RIF_DISCONRIF_POS 5U +#define USB_RIF_DISCONRIF_MSK BIT(USB_RIF_DISCONRIF_POS) + +/* host mode */ +#define USB_RIF_CONRIF_POS 4U +#define USB_RIF_CONRIF_MSK BIT(USB_RIF_CONRIF_POS) + +/* device/host mode */ +#define USB_RIF_SOFRIF_POS 3U +#define USB_RIF_SOFRIF_MSK BIT(USB_RIF_SOFRIF_POS) + +/* device mode */ +#define USB_RIF_RESTRIF_POS 2U +#define USB_RIF_RESTRIF_MSK BIT(USB_RIF_RESTRIF_POS) + +/* host mode */ +#define USB_RIF_BABRIF_POS 2U +#define USB_RIF_BABRIF_MSK BIT(USB_RIF_BABRIF_POS) + +/* device/host mode */ +#define USB_RIF_RESRIF_POS 1U +#define USB_RIF_RESRIF_MSK BIT(USB_RIF_RESRIF_POS) + +#define USB_RIF_SUSPDRIF_POS 0U +#define USB_RIF_SUSPDRIF_MSK BIT(USB_RIF_SUSPDRIF_POS) + +/****************** Bit definition for USB_IFM register ************************/ + +/* device/host mode */ +#define USB_IFM_SESREQIFM_POS 6U +#define USB_IFM_SESREQIFM_MSK BIT(USB_IFM_SESREQIFM_POS) + +#define USB_IFM_DISCONIFM_POS 5U +#define USB_IFM_DISCONIFM_MSK BIT(USB_IFM_DISCONIFM_POS) + +/* host mode */ +#define USB_IFM_CONIFM_POS 4U +#define USB_IFM_CONIFM_MSK BIT(USB_IFM_CONIFM_POS) + +/* device/host mode */ +#define USB_IFM_SOFIFM_POS 3U +#define USB_IFM_SOFIFM_MSK BIT(USB_IFM_SOFIFM_POS) + +/* device mode */ +#define USB_IFM_RESTIFM_POS 2U +#define USB_IFM_RESTIFM_MSK BIT(USB_IFM_RESTIFM_POS) + +/* host mode */ +#define USB_IFM_BABIFM_POS 2U +#define USB_IFM_BABIFM_MSK BIT(USB_IFM_BABIFM_POS) + +/* device/host mode */ +#define USB_IFM_RESIFM_POS 1U +#define USB_IFM_RESIFM_MSK BIT(USB_IFM_RESIFM_POS) + +#define USB_IFM_SUSPDIFM_POS 0U +#define USB_IFM_SUSPDIFM_MSK BIT(USB_IFM_SUSPDIFM_POS) + +/****************** Bit definition for USB_ICR register ************************/ + +/* device/host mode */ +#define USB_ICR_SESREQICR_POS 6U +#define USB_ICR_SESREQICR_MSK BIT(USB_ICR_SESREQICR_POS) + +#define USB_ICR_DISCONICR_POS 5U +#define USB_ICR_DISCONICR_MSK BIT(USB_ICR_DISCONICR_POS) + +/* host mode */ +#define USB_ICR_CONICR_POS 4U +#define USB_ICR_CONICR_MSK BIT(USB_ICR_CONICR_POS) + +/* device/host mode */ +#define USB_ICR_SOFICR_POS 3U +#define USB_ICR_SOFICR_MSK BIT(USB_ICR_SOFICR_POS) + +/* device mode */ +#define USB_ICR_RESTICR_POS 2U +#define USB_ICR_RESTICR_MSK BIT(USB_ICR_RESTICR_POS) + +/* host mode */ +#define USB_ICR_BABICR_POS 2U +#define USB_ICR_BABICR_MSK BIT(USB_ICR_BABICR_POS) + +/* device/host mode */ +#define USB_ICR_RESICR_POS 1U +#define USB_ICR_RESICR_MSK BIT(USB_ICR_RESICR_POS) + +#define USB_ICR_SUSPDICR_POS 0U +#define USB_ICR_SUSPDICR_MSK BIT(USB_ICR_SUSPDICR_POS) + +/* Exported Types ------------------------------------------------------------ */ +typedef struct +{ + __IO uint8_t FADDR ; /*0x0000 Function address register.*/ + __IO uint8_t POWER ; /*0x0001 Power management register.*/ + __IO uint8_t DPDMCON ; /*0x0002 DP DM Control register.*/ + __IO uint8_t SWCID ; /*0x0003 Softwave CID register.*/ + __IO uint8_t SWVBUS ; /*0x0004 Softwave VBUS register.*/ + __IO uint8_t TMODE ; /*0x0005 Test Mode register.*/ + __IO uint8_t RES002[6] ; /*0x0006~0x0B, Reserved*/ + __IO uint8_t FRAME1 ; /*0x000C, Frame number bits 0 to 7.*/ + __IO uint8_t FRAME2 ; /*0x000D, Frame number bits 8 to 10.*/ + __IO uint8_t INDEX ; /*0x000E, Index register for selecting the endp*/ + __IO uint8_t DEVCON ; /*0x000F, USB device control register.*/ + __IO uint8_t TXMAXP ; /*0x0010, Peripheral mode - Maximum packet size*/ + __IO uint8_t CSR0L_TXCSRL ;/*0x0011, Peripheral mode - Control Status regi*/ + __IO uint8_t CSR0H_TXCSRH ;/*0x0012, Peripheral mode - Control Status regi*/ + __IO uint8_t RXMAXP ; /*0x0013, Peripheral mode - Maximum packet size*/ + __IO uint8_t RXCSRL ; /*0x0014, Peripheral mode - Control Status regi*/ + __IO uint8_t RXCSRH ; /*0x0015, Peripheral mode - Control Status regi*/ + __IO uint8_t COUNT0_RX1 ; /*0x0016, Peripheral mode - Number of bytes in*/ + __IO uint8_t RXCOUNT2 ; /*0x0017, Peripheral mode - Number of bytes in*/ + __IO uint8_t TXTYPE ; /*0x0018, Peripheral mode - */ + __IO uint8_t NAKLIMIT0_TXINTERVAL ; /*0x0019, Peripheral mode - */ + __IO uint8_t RXTYPE ; /*0x001A, Peripheral mode - */ + __IO uint8_t RXINTERVAL ; /*0x001B, Peripheral mode - */ + __IO uint8_t TXFIFO1 ; /*0x001C, Tx Endpoint FIFO details*/ + __IO uint8_t TXFIFO2 ; /*0x001D, Tx Endpoint FIFO details*/ + __IO uint8_t RXFIFO1 ; /*0x001E, Rx Endpoint FIFO details*/ + __IO uint8_t RXFIFO2 ; /*0x001F, Rx Endpoint FIFO details*/ + __IO uint8_t EP0FIFO ; /*0x0020, FIFOs for Endpoints 0.*/ + __IO uint8_t RES021[3] ; /*0x0021~0x23, Reserved*/ + __IO uint8_t EP1FIFO ; /*0x0024, FIFOs for Endpoints 1.*/ + __IO uint8_t RES025[3] ; /*0x0025~0x27, Reserved*/ + __IO uint8_t EP2FIFO ; /*0x0028, FIFOs for Endpoints 2.*/ + __IO uint8_t RES029[3] ; /*0x0029~0x2B, Reserved*/ + __IO uint8_t EP3FIFO ; /*0x002C, FIFOs for Endpoints 3.*/ + __IO uint8_t RES02D[3] ; /*0x002D~0x2F, Reserved*/ + __IO uint8_t EP4FIFO ; /*0x0030, FIFOs for Endpoints 4.*/ + __IO uint8_t RES031[3] ; /*0x0031~0x33, Reserved*/ + __IO uint8_t EP5FIFO ; /*0x0034, FIFOs for Endpoints 5.*/ + __IO uint8_t RES035[3] ; /*0x0035~0x37, Reserved*/ + __IO uint8_t EP6FIFO ; /*0x0038, FIFOs for Endpoints 6.*/ + __IO uint8_t RES039[71] ; /*0x0039~0x7C, Reserved*/ + __IO uint8_t TXIER ; /*0x0080, TX Endpoint 0~6 Interrupt Enable*/ + __IO uint8_t RES081 ; /*0x0081, Reserved*/ + __IO uint8_t RXIER ; /*0x0082, RX Endpoint 0~6 Interrupt Enable*/ + __IO uint8_t RES083 ; /*0x0083, Reserved*/ + __IO uint8_t TXIDR ; /*0x0084, TX Endpoint 0~6 Interrupt Disable*/ + __IO uint8_t RES085 ; /*0x0085, Reserved*/ + __IO uint8_t RXIDR ; /*0x0086, RX Endpoint 0~6 Interrupt Disable*/ + __IO uint8_t RES087 ; /*0x0087, Reserved*/ + __IO uint8_t TXIVS ; /*0x0088, TX Endpoint 0~6 Interrupt Valid Status*/ + __IO uint8_t RES089 ; /*0x0089, Reserved*/ + __IO uint8_t RXIVS ; /*0x008A, RX Endpoint 0~6 Interrupt Valid Status*/ + __IO uint8_t RES08B ; /*0x008B, Reserved*/ + __IO uint8_t TXRIF ; /*0x008C, TX Endpoint 0~6 Raw Interrupt Flag Status*/ + __IO uint8_t RES08D ; /*0x008D, Reserved*/ + __IO uint8_t RXRIF ; /*0x008E, RX Endpoint 0~6 Raw Interrupt Flag Status*/ + __IO uint8_t RES08F ; /*0x008F, Reserved*/ + __IO uint8_t TXIFM ; /*0x0090, TX Endpoint 0~6 Interrupt Flag Masked Status*/ + __IO uint8_t RES091 ; /*0x0091, Reserved*/ + __IO uint8_t RXIFM ; /*0x0092, RX Endpoint 0~6 Interrupt Flag Masked Status*/ + __IO uint8_t RES093 ; /*0x0093, Reserved*/ + __IO uint8_t TXICR ; /*0x0094, TX Endpoint 0~6 Interrupt Clear Register*/ + __IO uint8_t RES095 ; /*0x0095, Reserved*/ + __IO uint8_t RXICR ; /*0x0096, RX Endpoint 0~6 Interrupt Clear Register*/ + __IO uint8_t RES097[9] ; /*0x0097~0x9C, Reserved*/ + __O uint32_t IER ; /*0x00A0, USB Interrupt Enable Register*/ + __O uint32_t IDR ; /*0x00A4, USB Interrupt Disable Register*/ + __I uint32_t IVS ; /*0x00A8, USB Interrupt Valid Register*/ + __I uint32_t RIF ; /*0x00AC, USB Raw Interrupt Flag Status Register*/ + __I uint32_t IFM ; /*0x00B0, USB Interrupt Flag Masked Status*/ + __O uint32_t ICR ; /*0x00B4, USB Interrupt Clear Register*/ +} USB_TypeDef; + +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ + +#endif/*__REG_USB_H__*/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_wwdt.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_wwdt.h new file mode 100644 index 0000000000..8f33e92f4f --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264/reg_wwdt.h @@ -0,0 +1,102 @@ +/********************************************************************************** + * + * @file reg_wwdt.h + * @brief WWDT Head File + * + * @date 07 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __REG_WWDT_H__ +#define __REG_WWDT_H__ + +/* Includes ------------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ +/* Exported Macros ----------------------------------------------------------- */ + +/****************** Bit definition for WWDT_LOAD register ************************/ + +#define WWDT_LOAD_LOAD_POSS 0U +#define WWDT_LOAD_LOAD_POSE 31U +#define WWDT_LOAD_LOAD_MSK BITS(WWDT_LOAD_LOAD_POSS,WWDT_LOAD_LOAD_POSE) + +/****************** Bit definition for WWDT_VALUE register ************************/ + +#define WWDT_VALUE_VALUE_POSS 0U +#define WWDT_VALUE_VALUE_POSE 31U +#define WWDT_VALUE_VALUE_MSK BITS(WWDT_VALUE_VALUE_POSS,WWDT_VALUE_VALUE_POSE) + +/****************** Bit definition for WWDT_CON register ************************/ + +#define WWDT_CON_WWDTWIN_POSS 4U +#define WWDT_CON_WWDTWIN_POSE 5U +#define WWDT_CON_WWDTWIN_MSK BITS(WWDT_CON_WWDTWIN_POSS,WWDT_CON_WWDTWIN_POSE) + +#define WWDT_CON_CLKS_POS 3U +#define WWDT_CON_CLKS_MSK BIT(WWDT_CON_CLKS_POS) + +#define WWDT_CON_RSTEN_POS 2U +#define WWDT_CON_RSTEN_MSK BIT(WWDT_CON_RSTEN_POS) + +#define WWDT_CON_IE_POS 1U +#define WWDT_CON_IE_MSK BIT(WWDT_CON_IE_POS) + +#define WWDT_CON_EN_POS 0U +#define WWDT_CON_EN_MSK BIT(WWDT_CON_EN_POS) + +/****************** Bit definition for WWDT_INTCLR register ************************/ + +#define WWDT_INTCLR_INTCLR_POSS 0U +#define WWDT_INTCLR_INTCLR_POSE 31U +#define WWDT_INTCLR_INTCLR_MSK BITS(WWDT_INTCLR_INTCLR_POSS,WWDT_INTCLR_INTCLR_POSE) + +/****************** Bit definition for WWDT_RIS register ************************/ + +#define WWDT_RIS_WWDTIF_POS 0U +#define WWDT_RIS_WWDTIF_MSK BIT(WWDT_RIS_WWDTIF_POS) + +/****************** Bit definition for WWDT_LOCK register ************************/ + +#define WWDT_LOCK_LOCK_POS 0U +#define WWDT_LOCK_LOCK_MSK BIT(WWDT_LOCK_LOCK_POS) + +/* Exported Types ------------------------------------------------------------ */ + +typedef struct +{ + __O uint32_t LOAD_; + __I uint32_t VALUE; + __IO uint32_t CON; + __O uint32_t INTCLR; + __I uint32_t RIS; + uint32_t RESERVED0[59] ; + __IO uint32_t LOCK; +} WWDT_TypeDef; + +#endif /* __REG_WWDT_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_adc.c b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_adc.c new file mode 100644 index 0000000000..031fadda69 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_adc.c @@ -0,0 +1,1151 @@ +/** + ****************************************************************************** + * @file ald_adc.c + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) + * peripheral: + * + Initialization functions + * ++ Initialization and Configuration of ADC + * + Operation functions + * ++ Start, stop, get result of conversions of normal + * group, using 3 possible modes: polling, interruption or DMA. + * + Control functions + * ++ Channels configuration on normal group + * ++ Channels configuration on insert group + * ++ Analog Watchdog configuration + * + State functions + * ++ ADC state machine management + * ++ Interrupts and flags management + * + * @version V1.0 + * @date 06 Mar. 2023 + * @author AE Team. + * @note + * Change Logs: + * Date Author Notes + * 06 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_adc.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC module driver + * @{ + */ + +/** @addtogroup ADC_Private_Functions + * @{ + */ +static void adc_dma_normal_conv_cplt(void *arg); +/** + * @} + */ + +/** @defgroup ADC_Public_Functions ADC Public Functions + * @{ + */ + +/** @defgroup ADC_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Initializes the ADC peripheral and normal group according to + * parameters specified in structure "adc_handle_t". + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_init(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_DATA_ALIGN_TYPE(hperh->init.align)); + assert_param(IS_FUNC_STATE(hperh->init.scan)); + assert_param(IS_ADC_CLK_DIV_TYPE(hperh->init.div)); + assert_param(IS_ADC_NEG_REF_VOLTAGE_TYPE(hperh->init.n_ref)); + assert_param(IS_POS_REF_VOLTAGE_TYPE(hperh->init.p_ref)); + assert_param(IS_ADC_CONV_BIT_TYPE(hperh->init.data_bit)); + assert_param(IS_ADC_NCH_NR_TYPE(hperh->init.nch_nr)); + assert_param(IS_ADC_DISC_NR_TYPE(hperh->init.disc_nr)); + assert_param(IS_FUNC_STATE(hperh->init.cont)); + assert_param(IS_ADC_NCHESEL_MODE_TYPE(hperh->init.nche_sel)); + + if (hperh->state == ALD_ADC_STATE_RESET) + { + hperh->error_code = ALD_ADC_ERROR_NONE; + hperh->lock = UNLOCK; + } + + ALD_ADC_DISABLE(hperh); + ald_adc_reset(hperh); + hperh->state = ALD_ADC_STATE_BUSY; + MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, hperh->init.align << ADC_CON1_ALIGN_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, hperh->init.data_bit << ADC_CON0_RSEL_POSS); + + /* Enable discontinuous mode only if continuous mode is disable */ + if (hperh->init.disc == ALD_ADC_NCH_DISC_EN) + { + hperh->init.scan = ENABLE; + hperh->init.cont = DISABLE; + SET_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nr << ADC_CON0_ETRGN_POSS); + } + else if (hperh->init.disc == ALD_ADC_ICH_DISC_EN) + { + hperh->init.scan = ENABLE; + hperh->init.cont = DISABLE; + SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nr << ADC_CON0_ETRGN_POSS); + } + else + { + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); + } + + if ((hperh->init.scan == ENABLE) || (hperh->init.disc == ALD_ADC_NCH_DISC_EN)) + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.nch_nr << ADC_CHSL_NSL_POSS); + + MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, hperh->init.cont << ADC_CON1_CM_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_SCANEN_MSK, hperh->init.scan << ADC_CON0_SCANEN_POS); + + WRITE_REG(hperh->perh->CCR, 0x0); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_PWRMODSEL_MSK, DISABLE << ADC_CCR_PWRMODSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_POSDIV_MSK, hperh->init.div << ADC_CCR_POSDIV_POSS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_sel << ADC_CON1_NCHESEL_POS); + ALD_ADC_ENABLE(hperh); + + hperh->error_code = ALD_ADC_ERROR_NONE; + hperh->state = ALD_ADC_STATE_READY; + return ALD_OK; +} + +/** + * @brief Deinitialize the ADC peripheral registers to their default reset + * values. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_reset(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ALD_ADC_DISABLE(hperh); + WRITE_REG(hperh->perh->CLR, 0x30F); + WRITE_REG(hperh->perh->CON0, 0x0); + WRITE_REG(hperh->perh->CON1, 0x0); + WRITE_REG(hperh->perh->CCR, 0x0); + WRITE_REG(hperh->perh->WDTH, 0xFFF); + WRITE_REG(hperh->perh->WDTL, 0x0); + WRITE_REG(hperh->perh->NCHOFF, 0x0); + WRITE_REG(hperh->perh->ICHOFF1, 0x0); + WRITE_REG(hperh->perh->ICHOFF2, 0x0); + WRITE_REG(hperh->perh->ICHOFF3, 0x0); + WRITE_REG(hperh->perh->ICHOFF4, 0x0); + WRITE_REG(hperh->perh->ICHS, 0x0); + WRITE_REG(hperh->perh->NCHS1, 0x0); + WRITE_REG(hperh->perh->NCHS2, 0x0); + WRITE_REG(hperh->perh->NCHS3, 0x0); + WRITE_REG(hperh->perh->NCHS4, 0x0); + WRITE_REG(hperh->perh->SMPT1, 0x0); + WRITE_REG(hperh->perh->SMPT2, 0x0); + WRITE_REG(hperh->perh->SMPT3, 0x0); + WRITE_REG(hperh->perh->CHSL, 0x0); + + hperh->state = ALD_ADC_STATE_RESET; + hperh->error_code = ALD_ADC_ERROR_NONE; + return ALD_OK; +} +/** + * @} + */ + +/** @defgroup ADC_Public_Functions_Group2 IO operation functions + * @brief Input and Output operation functions + * @{ + */ + +/** + * @brief Enables ADC, starts conversion of normal group. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_start(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ALD_ADC_ENABLE(hperh); + WRITE_REG(hperh->perh->CLR, ALD_ADC_FLAG_NCH | ALD_ADC_FLAG_NCHS); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + return ALD_OK; +} + +/** + * @brief Stop ADC conversion of normal group (and insert channels in + * case of auto_injection mode), disable ADC peripheral. + * @note: ADC peripheral disable is forcing stop of potential + * conversion on insert group. If insert group is under use, it + * should be preliminarily stopped using ald_adc_insert_stop function. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_stop(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ALD_ADC_DISABLE(hperh); + hperh->state = ALD_ADC_STATE_READY; + + return ALD_OK; +} + +/** + * @brief Wait for normal group conversion to be completed. + * @note This function cannot be used in a particular setup: ADC configured in DMA mode. + * In this case, DMA resets the flag EOC and polling cannot be performed on each conversion. + * @note When use this function,you should be pay attention to the hperh->init.reocs_mode, + * if it is ADC_REOCS_MODE_ALL, it means the function will wait all normal rank conversion finished. + * if it is ADC_REOCS_MODE_ONE, it means the funcion will wait every normal rank conversion finished. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param timeout: Timeout value in millisecond. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_poll_for_conversion(ald_adc_handle_t *hperh, uint32_t timeout) +{ + uint32_t _tick; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + _tick = ald_get_tick(); + + while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK))) + { + if (timeout != ALD_MAX_DELAY) + { + if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) + { + hperh->state = ALD_ADC_STATE_TIMEOUT; + return ALD_TIMEOUT; + } + } + } + + WRITE_REG(hperh->perh->CLR, ALD_ADC_FLAG_NCHS | ALD_ADC_FLAG_NCH); + return ALD_OK; +} + +/** + * @brief Poll for conversion event. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param event_type: the ADC event type. + * This parameter can be one of the following values: + * ADC_awd_event: ADC Analog watchdog event. + * @param timeout: Timeout value in millisecond. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_poll_for_event(ald_adc_handle_t *hperh, ald_adc_event_type_t event_type, uint32_t timeout) +{ + uint32_t _tick; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_EVENT_TYPE(event_type)); + + _tick = ald_get_tick(); + + while (ald_adc_get_flag_status(hperh, (ald_adc_flag_t)event_type) == RESET) + { + if (timeout != ALD_MAX_DELAY) + { + if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) + { + hperh->state = ALD_ADC_STATE_TIMEOUT; + return ALD_TIMEOUT; + } + } + } + + CLEAR_BIT(hperh->state, ALD_ADC_STATE_BUSY_WDG); + return ALD_OK; +} + +/** + * @brief Enables ADC, starts conversion of normal group with interruption. + * Interruptions enabled in this function: + * - REOC (end of conversion of normal group) + * Each of these interruptions has its dedicated callback function. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_start_by_it(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + SET_BIT(hperh->state, ALD_ADC_STATE_BUSY_N); + ALD_ADC_ENABLE(hperh); + WRITE_REG(hperh->perh->CLR, ALD_ADC_FLAG_NCH); + ald_adc_interrupt_config(hperh, ALD_ADC_IT_NCH, ENABLE); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + return ALD_OK; +} + +/** + * @brief Stop ADC conversion of normal group (and insert group in + * case of auto_injection mode), disable interrution of + * end-of-conversion, disable ADC peripheral. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_stop_by_it(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ALD_ADC_DISABLE(hperh); + ald_adc_interrupt_config(hperh, ALD_ADC_IT_NCH, DISABLE); + CLEAR_BIT(hperh->state, ALD_ADC_STATE_BUSY_N); + + return ALD_OK; +} + +/** + * @brief Enables ADC, starts conversion of normal group and transfers result + * through DMA. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param buf: The destination Buffer address. + * @param size: The length of data to be transferred from ADC peripheral to memory. + * @param channel: The DMA channel + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_start_by_dma(ald_adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) +{ + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + SET_BIT(hperh->state, ALD_ADC_STATE_BUSY_N); + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA; + + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + hperh->hdma.cplt_tc_cbk = adc_dma_normal_conv_cplt; + hperh->hdma.cplt_tc_arg = hperh; + ald_dma_config_struct(&hperh->hdma.config); + hperh->hdma.config.src = (void *)&hperh->perh->NCHDR; + hperh->hdma.config.dst = (void *)buf; + hperh->hdma.config.size = size; + hperh->hdma.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdma.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdma.config.msel = ALD_DMA_MSEL_ADC; + hperh->hdma.config.msigsel = ALD_DMA_MSIGSEL_ADC; + hperh->hdma.config.circle_mode = DISABLE; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&hperh->hdma); + + SET_BIT(hperh->perh->CON1, ADC_CON1_DMA_MSK); + + ALD_ADC_ENABLE(hperh); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + return ALD_OK; +} + +/** + * @brief Stop ADC conversion of normal group (and insert group in + * case of auto_insert mode), disable ADC DMA transfer, disable + * ADC peripheral. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param channel: The DMA channel + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_stop_by_dma(ald_adc_handle_t *hperh, uint8_t channel) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ALD_ADC_DISABLE(hperh); + CLEAR_BIT(hperh->perh->CON1, ADC_CON1_DMA_MSK); + ald_dma_channel_config(channel, DISABLE); + CLEAR_BIT(hperh->state, ALD_ADC_STATE_BUSY_N); + + return ALD_OK; +} + +/** + * @brief DMA transfer complete callback. + * @param arg: argument of the call back. + * @retval None + */ +static void adc_dma_timer_trigger_cplt(void *arg) +{ + ald_adc_timer_config_t *hperh = (ald_adc_timer_config_t *)arg; + + ald_timer_base_stop(&hperh->h_timer); + CLEAR_BIT(hperh->h_adc.perh->CON1, ADC_CON1_DMA_MSK); + ALD_ADC_DISABLE(&hperh->h_adc); + ald_dma_channel_config(hperh->dma_ch, DISABLE); + CLEAR_BIT(hperh->h_adc.state, ALD_ADC_STATE_BUSY_N); + + if (hperh->h_adc.normal_cplt_cbk) + hperh->h_adc.normal_cplt_cbk(&hperh->h_adc); + + return; +} + +/** + * @brief Config timer trigger adc insert channel conversion. + * @param config: Pointer to a adc_timer_config_t structure that + * contains the configuration information for the specified function. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_timer_trigger_insert(ald_adc_timer_config_t *config) +{ + config->h_pis.perh = PIS; + config->h_pis.init.producer_clk = ALD_PIS_CLK_PCLK; + config->h_pis.init.producer_edge = ALD_PIS_EDGE_NONE; + config->h_pis.init.consumer_clk = ALD_PIS_CLK_PCLK; + + if (config->p_timer == AD16C4T) + config->h_pis.init.producer_src = ALD_PIS_TIMER0_UPDATA; + else if (config->p_timer == GP16C4T0) + config->h_pis.init.producer_src = ALD_PIS_TIMER5_UPDATA; + else if (config->p_timer == GP16C4T1) + config->h_pis.init.producer_src = ALD_PIS_TIMER6_UPDATA; + else if (config->p_timer == GP16C4T2) + config->h_pis.init.producer_src = ALD_PIS_TIMER7_UPDATA; + else + return ALD_ERROR; + + config->h_pis.init.consumer_trig = ALD_PIS_CH5_ADC0_INSERT; + + ald_pis_create(&config->h_pis); + + /* Initialize TIMER */ + config->h_timer.perh = config->p_timer; + config->h_timer.init.prescaler = 0; + config->h_timer.init.mode = ALD_TIMER_CNT_MODE_UP; + config->h_timer.init.period = ((ald_cmu_get_pclk_clock() / 1000000) * config->time); + config->h_timer.init.clk_div = ALD_TIMER_CLOCK_DIV1; + config->h_timer.init.re_cnt = 0; + ald_timer_base_init(&config->h_timer); + + config->h_adc.perh = config->p_adc; + config->h_adc.init.align = ALD_ADC_DATAALIGN_RIGHT; + config->h_adc.init.scan = DISABLE; + config->h_adc.init.cont = DISABLE; + config->h_adc.init.ich_nr = ALD_ADC_ICH_NR_1; + config->h_adc.init.disc = ALD_ADC_ALL_DISABLE; + config->h_adc.init.disc_nr = ALD_ADC_DISC_NR_1; + config->h_adc.init.data_bit = ALD_ADC_CONV_BIT_12; + config->h_adc.init.div = ALD_ADC_CKDIV_128; + config->h_adc.init.nche_sel = ALD_ADC_NCHESEL_MODE_ONE; + config->h_adc.init.n_ref = config->n_ref; + config->h_adc.init.p_ref = config->p_ref; + config->h_adc.normal_cplt_cbk = config->cplt_cbk; + config->h_adc.insert_cplt_cbk = NULL; + config->h_adc.wdg_cbk = NULL; + config->h_adc.error_cbk = NULL; + config->h_adc.ovr_cbk = NULL; + ald_adc_init(&config->h_adc); + + config->h_adc.perh->CON1 |= 0x00100000; /* rising edge trigger insert channel convert */ + config->i_config.ch = config->adc_ch; + config->i_config.idx = ALD_ADC_ICH_IDX_1; + config->i_config.samp = ALD_ADC_SAMPLETIME_4; + config->i_config.nr = ALD_ADC_ICH_NR_1; + config->i_config.auto_m = DISABLE; + ald_adc_insert_channel_config(&config->h_adc, &config->i_config); + + ALD_ADC_ENABLE(&config->h_adc); + ald_timer_base_start(&config->h_timer); + + return ALD_OK; +} + +/** + * @brief Config Timer trigger adc function + * @param config: Pointer to a adc_timer_config_t structure that + * contains the configuration information for the specified function. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_timer_trigger_adc_by_dma(ald_adc_timer_config_t *config) +{ + config->h_pis.perh = PIS; + config->h_pis.init.producer_clk = ALD_PIS_CLK_PCLK; + config->h_pis.init.producer_edge = ALD_PIS_EDGE_NONE; + config->h_pis.init.consumer_clk = ALD_PIS_CLK_PCLK; + + if (config->p_timer == AD16C4T) + config->h_pis.init.producer_src = ALD_PIS_TIMER0_UPDATA; + else if (config->p_timer == GP16C4T0) + config->h_pis.init.producer_src = ALD_PIS_TIMER5_UPDATA; + else if (config->p_timer == GP16C4T1) + config->h_pis.init.producer_src = ALD_PIS_TIMER6_UPDATA; + else if (config->p_timer == GP16C4T2) + config->h_pis.init.producer_src = ALD_PIS_TIMER7_UPDATA; + else + return ALD_ERROR; + + config->h_pis.init.consumer_trig = ALD_PIS_CH4_ADC0_NORMAL; + + ald_pis_create(&config->h_pis); + + /* Initialize TIMER */ + config->h_timer.perh = config->p_timer; + config->h_timer.init.prescaler = 0; + config->h_timer.init.mode = ALD_TIMER_CNT_MODE_UP; + config->h_timer.init.period = ((ald_cmu_get_pclk_clock() / 1000000) * config->time); + config->h_timer.init.clk_div = ALD_TIMER_CLOCK_DIV1; + config->h_timer.init.re_cnt = 0; + ald_timer_base_init(&config->h_timer); + + config->h_adc.perh = config->p_adc; + config->h_adc.init.align = ALD_ADC_DATAALIGN_RIGHT; + config->h_adc.init.scan = DISABLE; + config->h_adc.init.cont = DISABLE; + config->h_adc.init.nch_nr = ALD_ADC_NCH_NR_1; + config->h_adc.init.disc = ALD_ADC_ALL_DISABLE; + config->h_adc.init.disc_nr = ALD_ADC_DISC_NR_1; + config->h_adc.init.data_bit = ALD_ADC_CONV_BIT_12; + config->h_adc.init.div = ALD_ADC_CKDIV_128; + config->h_adc.init.nche_sel = ALD_ADC_NCHESEL_MODE_ONE; + config->h_adc.init.n_ref = config->n_ref; + config->h_adc.init.p_ref = config->p_ref; + config->h_adc.normal_cplt_cbk = config->cplt_cbk; + config->h_adc.insert_cplt_cbk = NULL; + config->h_adc.wdg_cbk = NULL; + config->h_adc.error_cbk = NULL; + config->h_adc.ovr_cbk = NULL; + ald_adc_init(&config->h_adc); + + config->h_adc.perh->CON1 |= 0x10000000; + config->config.ch = config->adc_ch; + config->config.idx = ALD_ADC_NCH_IDX_1; + config->config.samp = ALD_ADC_SAMPLETIME_4; + ald_adc_normal_channel_config(&config->h_adc, &config->config); + + config->h_dma.cplt_tc_cbk = adc_dma_timer_trigger_cplt; + config->h_dma.cplt_tc_arg = config; + + ald_dma_config_struct(&config->h_dma.config); + config->h_dma.perh = DMA; + config->h_dma.config.src = (void *)&config->h_adc.perh->NCHDR; + config->h_dma.config.dst = (void *)config->buf; + config->h_dma.config.size = config->size; + config->h_dma.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + config->h_dma.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + config->h_dma.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + config->h_dma.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + config->h_dma.config.msel = ALD_DMA_MSEL_ADC; + config->h_dma.config.msigsel = ALD_DMA_MSIGSEL_ADC; + config->h_dma.config.channel = config->dma_ch; + ald_dma_config_basic(&config->h_dma); + ald_dma_interrupt_config(config->dma_ch, ALD_DMA_IT_FLAG_TC, ENABLE); + + SET_BIT(config->h_adc.perh->CON1, ADC_CON1_DMA_MSK); + ALD_ADC_ENABLE(&config->h_adc); + ald_timer_base_start(&config->h_timer); + + return ALD_OK; +} + +/** + * @brief Get ADC normal group conversion result. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval ADC group normal conversion data + */ +uint32_t ald_adc_normal_get_value(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + return hperh->perh->NCHDR; +} + +/** + * @brief Enables ADC, starts conversion of insert group. + * Interruptions enabled in this function: None. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_insert_start(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ALD_ADC_ENABLE(hperh); + WRITE_REG(hperh->perh->CLR, ALD_ADC_FLAG_ICH); + + if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) + SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); + + return ALD_OK; +} + +/** + * @brief Stop conversion of insert channels. Disable ADC peripheral if + * no normal conversion is on going. + * @note If ADC must be disabled and if conversion is on going on + * normal group, function ald_adc_normal_stop must be used to stop both + * insert and normal groups, and disable the ADC. + * @note If insert group mode auto-injection is enabled, + * function ald_adc_normal_stop must be used. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_insert_stop(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ALD_ADC_DISABLE(hperh); + hperh->state = ALD_ADC_STATE_READY; + return ALD_OK; +} + +/** + * @brief Wait for insert group conversion to be completed. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param timeout: Timeout value in millisecond. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_insert_poll_for_conversion(ald_adc_handle_t *hperh, uint32_t timeout) +{ + uint32_t _tick; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + _tick = ald_get_tick(); + + while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_ICHE_MSK))) + { + if (timeout != ALD_MAX_DELAY) + { + if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) + { + hperh->state |= ALD_ADC_STATE_TIMEOUT; + return ALD_TIMEOUT; + } + } + } + + WRITE_REG(hperh->perh->CLR, ALD_ADC_FLAG_ICHS | ALD_ADC_FLAG_ICH); + return ALD_OK; +} + +/** + * @brief Enables ADC, starts conversion of insert group with interruption. + * - JEOC (end of conversion of insert group) + * Each of these interruptions has its dedicated callback function. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t.. + */ +ald_status_t ald_adc_insert_start_by_it(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + SET_BIT(hperh->state, ALD_ADC_STATE_BUSY_I); + ALD_ADC_ENABLE(hperh); + WRITE_REG(hperh->perh->CLR, ALD_ADC_FLAG_ICHS | ALD_ADC_FLAG_ICH); + ald_adc_interrupt_config(hperh, ALD_ADC_IT_ICH, ENABLE); + + if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) + SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); + + return ALD_OK; +} + +/** + * @brief Stop conversion of insert channels, disable interruption of + * end-of-conversion. Disable ADC peripheral if no normal conversion + * is on going. + * @note If ADC must be disabled and if conversion is on going on + * normal group, function ald_adc_normal_stop must be used to stop both + * insert and normal groups, and disable the ADC. + * @note If insert group mode auto-injection is enabled, + * function ald_adc_normal_stop must be used. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval None + */ +ald_status_t ald_adc_insert_stop_by_it(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + CLEAR_BIT(hperh->state, ALD_ADC_STATE_BUSY_I); + ALD_ADC_DISABLE(hperh); + ald_adc_interrupt_config(hperh, ALD_ADC_IT_ICH, DISABLE); + return ALD_OK; +} + +/** + * @brief Get ADC insert group conversion result. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param idx: Index of converted ADC insert channel. + * @retval ADC group insert conversion data + */ +uint32_t ald_adc_insert_get_value(ald_adc_handle_t *hperh, ald_adc_ich_idx_t idx) +{ + uint32_t tmp; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_ICH_IDX_TYPE(idx)); + + switch (idx) + { + case ALD_ADC_ICH_IDX_1: + tmp = hperh->perh->ICHDR1; + break; + + case ALD_ADC_ICH_IDX_2: + tmp = hperh->perh->ICHDR2; + break; + + case ALD_ADC_ICH_IDX_3: + tmp = hperh->perh->ICHDR3; + break; + + case ALD_ADC_ICH_IDX_4: + tmp = hperh->perh->ICHDR4; + break; + + default: + tmp = hperh->perh->ICHDR1; + break; + } + + return tmp; +} + +/** + * @brief Handles ADC interrupt request + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval None + */ +void ald_adc_irq_handler(ald_adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + if (ald_adc_get_it_status(hperh, ALD_ADC_IT_NCH) && ald_adc_get_flag_status(hperh, ALD_ADC_FLAG_NCH)) + { + WRITE_REG(hperh->perh->CLR, ALD_ADC_FLAG_NCH | ALD_ADC_FLAG_NCHS); + CLEAR_BIT(hperh->state, ALD_ADC_STATE_BUSY_N); + + if (hperh->normal_cplt_cbk) + hperh->normal_cplt_cbk(hperh); + } + + if (ald_adc_get_it_status(hperh, ALD_ADC_IT_ICH) && ald_adc_get_flag_status(hperh, ALD_ADC_FLAG_ICH)) + { + WRITE_REG(hperh->perh->CLR, ALD_ADC_FLAG_ICH | ALD_ADC_FLAG_ICHS); + CLEAR_BIT(hperh->state, ALD_ADC_STATE_BUSY_I); + + if (hperh->insert_cplt_cbk) + hperh->insert_cplt_cbk(hperh); + } + + if (ald_adc_get_it_status(hperh, ALD_ADC_IT_AWD) && ald_adc_get_flag_status(hperh, ALD_ADC_FLAG_AWD)) + { + CLEAR_BIT(hperh->state, ALD_ADC_STATE_BUSY_WDG); + WRITE_REG(hperh->perh->CLR, ALD_ADC_FLAG_AWD); + + if (hperh->wdg_cbk) + hperh->wdg_cbk(hperh); + } + + if (ald_adc_get_it_status(hperh, ALD_ADC_IT_OVR) && ald_adc_get_flag_status(hperh, ALD_ADC_FLAG_OVR)) + { + WRITE_REG(hperh->perh->CLR, ALD_ADC_FLAG_OVR); + hperh->error_code |= ALD_ADC_ERROR_OVR; + hperh->state |= ALD_ADC_STATE_ERROR; + + if (hperh->ovr_cbk) + hperh->ovr_cbk(hperh); + } +} + +/** + * @} + */ + +/** @defgroup ADC_Public_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ + +/** + * @brief Configures the the selected channel to be linked to the normal + * group. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param config: Structure of ADC channel for normal group. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_channel_config(ald_adc_handle_t *hperh, ald_adc_nch_conf_t *config) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); + assert_param(IS_ADC_NCH_IDX_TYPE(config->idx)); + assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp)); + + if (config->idx <= ALD_ADC_NCH_IDX_4) + { + hperh->perh->NCHS1 &= ~(0x1f << (uint32_t)((config->idx - 1) << 3)); + hperh->perh->NCHS1 |= (config->ch << (uint32_t)((config->idx - 1) << 3)); + } + else if (config->idx <= ALD_ADC_NCH_IDX_8) + { + hperh->perh->NCHS2 &= ~(0x1f << (uint32_t)((config->idx - 5) << 3)); + hperh->perh->NCHS2 |= (config->ch << (uint32_t)((config->idx - 5) << 3)); + } + else if (config->idx <= ALD_ADC_NCH_IDX_12) + { + hperh->perh->NCHS3 &= ~(0x1f << (uint32_t)((config->idx - 9) << 3)); + hperh->perh->NCHS3 |= (config->ch << (uint32_t)((config->idx - 9) << 3)); + } + else + { + hperh->perh->NCHS4 &= ~(0x1f << (uint32_t)((config->idx - 13) << 3)); + hperh->perh->NCHS4 |= (config->ch << (uint32_t)((config->idx - 13) << 3)); + } + + if (config->ch < 8) + { + hperh->perh->SMPT1 &= ~(0x0f << (uint32_t)(config->ch << 2)); + hperh->perh->SMPT1 |= config->samp << (uint32_t)(config->ch << 2); + } + else if (config->ch < 16) + { + hperh->perh->SMPT2 &= ~(0x0f << (uint32_t)((config->ch - 8) << 2)); + hperh->perh->SMPT2 |= config->samp << (uint32_t)((config->ch - 8) << 2); + } + else + { + hperh->perh->SMPT3 &= ~(0x0f << (uint32_t)((config->ch - 16) << 2)); + hperh->perh->SMPT3 |= config->samp << (uint32_t)((config->ch - 16) << 2); + } + + return ALD_OK; +} + +/** + * @brief Configures the the selected channel to be linked to the insert + * group. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param config: Structure of ADC channel for insert group. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_insert_channel_config(ald_adc_handle_t *hperh, ald_adc_ich_conf_t *config) +{ + ald_status_t tmp_status = ALD_OK; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); + assert_param(IS_ADC_ICH_IDX_TYPE(config->idx)); + assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp)); + assert_param(IS_ADC_IST_OFFSET_TYPE(config->offset)); + assert_param(IS_ADC_ICH_NR_TYPE(config->nr)); + assert_param(IS_FUNC_STATE(config->auto_m)); + + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->nr << ADC_CHSL_ISL_POSS); + hperh->perh->ICHS &= ~(0x1f << (uint32_t)((config->idx - 1) << 3)); + hperh->perh->ICHS |= config->ch << (uint32_t)((config->idx - 1) << 3); + + if (config->auto_m == ENABLE) + SET_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); + else + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); + + if (hperh->init.disc == ALD_ADC_ICH_DISC_EN) + { + if (config->auto_m == DISABLE) + { + SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); + } + else + { + hperh->state |= ALD_ADC_STATE_ERROR; + hperh->error_code |= ALD_ADC_ERROR_INTERNAL; + tmp_status = ALD_ERROR; + } + } + + if (config->ch < 8) + { + hperh->perh->SMPT1 &= ~(0x0f << (uint32_t)(config->ch << 2)); + hperh->perh->SMPT1 |= config->samp << (uint32_t)(config->ch << 2); + } + else if (config->ch < 16) + { + hperh->perh->SMPT2 &= ~(0x0f << (uint32_t)((config->ch - 8) << 2)); + hperh->perh->SMPT2 |= config->samp << (uint32_t)((config->ch - 8) << 2); + } + else + { + hperh->perh->SMPT3 &= ~(0x0f << (uint32_t)((config->ch - 16) << 2)); + hperh->perh->SMPT3 |= config->samp << (uint32_t)((config->ch - 16) << 2); + } + + switch (config->idx) + { + case ALD_ADC_ICH_IDX_1: + hperh->perh->ICHOFF1 = config->offset; + break; + + case ALD_ADC_ICH_IDX_2: + hperh->perh->ICHOFF2 = config->offset; + break; + + case ALD_ADC_ICH_IDX_3: + hperh->perh->ICHOFF3 = config->offset; + break; + + case ALD_ADC_ICH_IDX_4: + hperh->perh->ICHOFF4 = config->offset; + break; + + default: + break; + } + + return tmp_status; +} + +/** + * @brief Configures the analog watchdog. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param config: Structure of ADC analog watchdog configuration + * @retval ALD status + */ +ald_status_t ald_adc_analog_wdg_config(ald_adc_handle_t *hperh, ald_adc_analog_wdg_conf_t *config) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_ANALOG_WTD_MODE_TYPE(config->mode)); + assert_param(IS_FUNC_STATE(config->interrupt)); + assert_param(IS_HTR_TYPE(config->high_thrd)); + assert_param(IS_LTR_TYPE(config->low_thrd)); + + if ((config->mode == ALD_ADC_ANAWTD_SING_NM) + || (config->mode == ALD_ADC_ANAWTD_SING_IST) + || (config->mode == ALD_ADC_ANAWTD_SING_NMIST)) + assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); + + if (config->interrupt == DISABLE) + ald_adc_interrupt_config(hperh, ALD_ADC_IT_AWD, DISABLE); + else + ald_adc_interrupt_config(hperh, ALD_ADC_IT_AWD, ENABLE); + + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHWDTEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHWDEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK); + hperh->perh->CON0 |= config->mode; + + if (READ_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK)) + MODIFY_REG(hperh->perh->CON0, ADC_CON0_AWDCH_MSK, config->ch << ADC_CON0_AWDCH_POSS); + + WRITE_REG(hperh->perh->WDTL, config->low_thrd); + WRITE_REG(hperh->perh->WDTH, config->high_thrd); + SET_BIT(hperh->state, ALD_ADC_STATE_BUSY_WDG); + + return ALD_OK; +} + +/** + * @brief Enables or disables the specified ADC interrupts. + * @param hperh: Pointer to a adc_handle_t structure. + * @param it: Specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref adc_it_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_adc_interrupt_config(ald_adc_handle_t *hperh, ald_adc_it_t it, type_func_t state) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_IT_TYPE(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT(hperh->perh->CON0, it); + else + CLEAR_BIT(hperh->perh->CON0, it); + + return; +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param hperh: Pointer to a adc_handle_t structure. + * @param it: Specifies the ADC interrupt source to check. + * This parameter can be one of the @ref adc_it_t. + * @retval Status + * - SET + * - RESET + */ +it_status_t ald_adc_get_it_status(ald_adc_handle_t *hperh, ald_adc_it_t it) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_IT_TYPE(it)); + + if (READ_BIT(hperh->perh->CON0, it)) + return SET; + + return RESET; +} + +/** @brief Check whether the specified ADC flag is set or not. + * @param hperh: Pointer to a adc_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref adc_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t ald_adc_get_flag_status(ald_adc_handle_t *hperh, ald_adc_flag_t flag) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_FLAGS_TYPE(flag)); + + if (READ_BIT(hperh->perh->STAT, flag)) + return SET; + + return RESET; +} + +/** @brief Clear the specified ADC pending flags. + * @param hperh: Pointer to a adc_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref adc_flag_t. + * @retval None + */ +void ald_adc_clear_flag_status(ald_adc_handle_t *hperh, ald_adc_flag_t flag) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_FLAGS_TYPE(flag)); + + WRITE_REG(hperh->perh->CLR, flag); + return; +} +/** + * @} + */ + +/** @defgroup ADC_Public_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * @{ + */ + +/** + * @brief return the ADC state + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval state + */ +uint32_t ald_adc_get_state(ald_adc_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Return the ADC error code + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval ADC Error Code + */ +uint32_t ald_adc_get_error(ald_adc_handle_t *hperh) +{ + return hperh->error_code; +} + +/** + *@} + */ + +/** + *@} + */ + +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ + +/** + * @brief DMA transfer complete callback. + * @param arg: argument of the call back. + * @retval None + */ +static void adc_dma_normal_conv_cplt(void *arg) +{ + ald_adc_handle_t *hperh = (ald_adc_handle_t *)arg; + + CLEAR_BIT(hperh->perh->CON1, ADC_CON1_DMA_MSK); + + if (hperh->normal_cplt_cbk) + hperh->normal_cplt_cbk(hperh); + +} + +/** + *@} + */ +/** + *@} + */ + +/** + *@} + */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_adc.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_adc.h new file mode 100644 index 0000000000..d3f5ff4c7b --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_adc.h @@ -0,0 +1,615 @@ +/** + ****************************************************************************** + * @file ald_adc.h + * @brief Header file of ADC Module library. + * + * @version V1.0 + * @date 06 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 06 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_ADC_H__ +#define __ALD_ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_utils.h" +#include "ald_dma.h" +#include "ald_pis.h" +#include "ald_timer.h" + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Constants -------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup ADC_Pubulic_Types ADC Pubulic Types + * @{ + */ + +/** + * @brief ADC State structures definition + */ +typedef enum +{ + ALD_ADC_STATE_RESET = 0x0U, /**< ADC not yet initialized or disabled */ + ALD_ADC_STATE_READY = 0x1U, /**< ADC peripheral ready for use */ + ALD_ADC_STATE_BUSY = 0x2U, /**< ADC is busy to internal process */ + ALD_ADC_STATE_TIMEOUT = 0x4U, /**< TimeOut occurrence */ + ALD_ADC_STATE_ERROR = 0x8U, /**< Internal error occurrence */ + ALD_ADC_STATE_BUSY_N = 0x10U, /**< Normal channel busy */ + ALD_ADC_STATE_BUSY_I = 0x20U, /**< Insert channel busy */ + ALD_ADC_STATE_BUSY_WDG = 0x40U, /**< AWDT busy */ +} ald_adc_state_t; + +/** + *@brief ADC Error Code + */ +typedef enum +{ + ALD_ADC_ERROR_NONE = 0x0U, /**< No error */ + ALD_ADC_ERROR_INTERNAL = 0x1U, /**< ADC IP internal error*/ + ALD_ADC_ERROR_OVR = 0x2U, /**< Overrun error */ + ALD_ADC_ERROR_DMA = 0x4U, /**< DMA transfer error */ +} ald_adc_error_t; + +/** + *@brief ADC data alignment + */ +typedef enum +{ + ALD_ADC_DATAALIGN_RIGHT = 0x0U, /**< ADC data alignment right */ + ALD_ADC_DATAALIGN_LEFT = 0x1U, /**< ADC data alignment left */ +} ald_adc_align_t; + +/** + *@brief ADC config hannal trigger the EOC IT mode + */ +typedef enum +{ + ALD_ADC_NCHESEL_MODE_ALL = 0x0U, /**< ADC set RCHE after convert sequence finish */ + ALD_ADC_NCHESEL_MODE_ONE = 0x1U, /**< ADC set RCHE after one convert finish */ +} ald_adc_nchesel_t; + +/** + *@brief ADC channels + */ +typedef enum +{ + ALD_ADC_CHANNEL_0 = 0x0U, /**< ADC channel 0 */ + ALD_ADC_CHANNEL_1 = 0x1U, /**< ADC channel 1 */ + ALD_ADC_CHANNEL_2 = 0x2U, /**< ADC channel 2 */ + ALD_ADC_CHANNEL_3 = 0x3U, /**< ADC channel 3 */ + ALD_ADC_CHANNEL_4 = 0x4U, /**< ADC channel 4 */ + ALD_ADC_CHANNEL_5 = 0x5U, /**< ADC channel 5 */ + ALD_ADC_CHANNEL_6 = 0x6U, /**< ADC channel 6 */ + ALD_ADC_CHANNEL_7 = 0x7U, /**< ADC channel 7 */ + ALD_ADC_CHANNEL_8 = 0x8U, /**< ADC channel 8 */ + ALD_ADC_CHANNEL_9 = 0x9U, /**< ADC channel 9 */ + ALD_ADC_CHANNEL_10 = 0xAU, /**< ADC channel 10 */ + ALD_ADC_CHANNEL_11 = 0xBU, /**< ADC channel 11 */ + ALD_ADC_CHANNEL_12 = 0xCU, /**< ADC channel 12 */ + ALD_ADC_CHANNEL_13 = 0xDU, /**< ADC channel 13 */ + ALD_ADC_CHANNEL_14 = 0xEU, /**< ADC channel 14 */ + ALD_ADC_CHANNEL_15 = 0xFU, /**< ADC channel 15 */ + ALD_ADC_CHANNEL_16 = 0x10U, /**< ADC channel 16 */ + ALD_ADC_CHANNEL_17 = 0x11U, /**< ADC channel 17 */ + ALD_ADC_CHANNEL_18 = 0x12U, /**< ADC channel 18 */ + ALD_ADC_CHANNEL_19 = 0x13U, /**< ADC channel 19 */ +} ald_adc_channel_t; + +/** + *@brief ADC sampling times + */ +typedef enum +{ + ALD_ADC_SAMPLETIME_4 = 0x0U, /**< ADC sampling times 4 clk */ + ALD_ADC_SAMPLETIME_6 = 0x1U, /**< ADC sampling times 6 clk */ + ALD_ADC_SAMPLETIME_10 = 0x2U, /**< ADC sampling times 10 clk */ + ALD_ADC_SAMPLETIME_18 = 0x3U, /**< ADC sampling times 18 clk */ +} ald_adc_samp_t; + +/** + *@brief ADC index channel in normal group + */ +typedef enum +{ + ALD_ADC_NCH_IDX_1 = 0x1U, /**< ADC normal channel index 1 */ + ALD_ADC_NCH_IDX_2 = 0x2U, /**< ADC normal channel index 2 */ + ALD_ADC_NCH_IDX_3 = 0x3U, /**< ADC normal channel index 3 */ + ALD_ADC_NCH_IDX_4 = 0x4U, /**< ADC normal channel index 4 */ + ALD_ADC_NCH_IDX_5 = 0x5U, /**< ADC normal channel index 5 */ + ALD_ADC_NCH_IDX_6 = 0x6U, /**< ADC normal channel index 6 */ + ALD_ADC_NCH_IDX_7 = 0x7U, /**< ADC normal channel index 7 */ + ALD_ADC_NCH_IDX_8 = 0x8U, /**< ADC normal channel index 8 */ + ALD_ADC_NCH_IDX_9 = 0x9U, /**< ADC normal channel index 9 */ + ALD_ADC_NCH_IDX_10 = 0xAU, /**< ADC normal channel index 10 */ + ALD_ADC_NCH_IDX_11 = 0xBU, /**< ADC normal channel index 11 */ + ALD_ADC_NCH_IDX_12 = 0xCU, /**< ADC normal channel index 12 */ + ALD_ADC_NCH_IDX_13 = 0xDU, /**< ADC normal channel index 13 */ + ALD_ADC_NCH_IDX_14 = 0xEU, /**< ADC normal channel index 14 */ + ALD_ADC_NCH_IDX_15 = 0xFU, /**< ADC normal channel index 15 */ + ALD_ADC_NCH_IDX_16 = 0x10U, /**< ADC normal channel index 16 */ +} ald_adc_nch_idx_t; + +/** + * @brief ADC index channel in insert group + */ +typedef enum +{ + ALD_ADC_ICH_IDX_1 = 0x1U, /**< ADC insert channel index 1 */ + ALD_ADC_ICH_IDX_2 = 0x2U, /**< ADC insert channel index 2 */ + ALD_ADC_ICH_IDX_3 = 0x3U, /**< ADC insert channel index 3 */ + ALD_ADC_ICH_IDX_4 = 0x4U, /**< ADC insert channel index 4 */ +} ald_adc_ich_idx_t; + +/** + * @brief ADC analog watchdog mode + */ +typedef enum +{ + ALD_ADC_ANAWTD_NONE = 0x0U, /**< No watch dog */ + ALD_ADC_ANAWTD_SING_NM = 0x800200U, /**< One normal channel watch dog */ + ALD_ADC_ANAWTD_SING_IST = 0x400200U, /**< One insert channel Injec watch dog */ + ALD_ADC_ANAWTD_SING_NMIST = 0xC00200U, /**< One normal and insert channel watch dog */ + ALD_ADC_ANAWTD_ALL_NM = 0x800000U, /**< All normal channel watch dog */ + ALD_ADC_ANAWTD_ALL_IST = 0x400000U, /**< All insert channel watch dog */ + ALD_ADC_ANAWTD_ALL_NMIST = 0xC00000U, /**< All normal and insert channel watch dog */ +} ald_adc_ana_wdg_t; + +/** + * @brief ADC Event type + */ +typedef enum +{ + ALD_ADC_AWD_EVENT = (1U << 0), /**< ADC analog watch dog event */ +} ald_adc_event_type_t; + +/** + * @brief ADC interrupts definition + */ +typedef enum +{ + ALD_ADC_IT_NCH = (1U << 5), /**< ADC it normal */ + ALD_ADC_IT_AWD = (1U << 6), /**< ADC it awd */ + ALD_ADC_IT_ICH = (1U << 7), /**< ADC it insert */ + ALD_ADC_IT_OVR = (1U << 26), /**< ADC it overring */ +} ald_adc_it_t; + +/** + * @brief ADC flags definition + */ +typedef enum +{ + ALD_ADC_FLAG_AWD = (1U << 0), /**perh->CON1, ADC_CON1_ADCEN_MSK)) +#define ALD_ADC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK)) +#define ALD_ADC_NH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK)) +#define ALD_ADC_IH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK)) +#define ALD_ADC_RESET_HANDLE_STATE(handle) ((handle)->state = ADC_STATE_RESET) +#define ALD_ADC_VREF_OUT_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +#define ALD_ADC_VREF_OUT_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +#define ALD_ADC_NETS_ENABLE(handle, mode) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, (mode) << ADC_CON1_NETS_POSS)) +#define ALD_ADC_IETS_ENABLE(handle, mode) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, (mode) << ADC_CON1_IETS_POSS)) +#define ALD_ADC_NETS_DISABLE(handle) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, 0 << ADC_CON1_NETS_POSS)) +#define ALD_ADC_IETS_DISABLE(handle) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, 0 << ADC_CON1_IETS_POSS)) +#define ALD_ADC_SPEED_HIGH_DISABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK)) +#define ALD_ADC_SPEED_HIGH_ENABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK)) +#define ALD_ADC_TEMP_SENSE_ENABLE(x) (SET_BIT((x)->CCR, ADC_CCR_TSEN_MSK)) +#define ALD_ADC_TEMP_SENSE_DISABLE(x) (CLEAR_BIT((x)->CCR, ADC_CCR_TSEN_MSK)) +#define ALD_ADC_PREDIV_ENABLE(x) (SET_BIT((x)->CCR, ADC_CCR_PREDIV_MSK)) +#define ALD_ADC_PREDIV_DISABLE(x) (CLEAR_BIT((x)->CCR, ADC_CCR_PREDIV_MSK)) +/** + * @} + */ + +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ +#define IS_ADC_ICH_IDX_TYPE(x) ((x) <= ALD_ADC_ICH_IDX_4) +#define IS_ADC_NCH_IDX_TYPE(x) ((x) <= ALD_ADC_NCH_IDX_16) +#define IS_ADC_SAMPLING_TIMES_TYPE(x) (((x) == ALD_ADC_SAMPLETIME_4) || \ + ((x) == ALD_ADC_SAMPLETIME_6) || \ + ((x) == ALD_ADC_SAMPLETIME_10) || \ + ((x) == ALD_ADC_SAMPLETIME_18)) +#define IS_ADC_CHANNELS_TYPE(x) ((x) <= ALD_ADC_CHANNEL_19) +#define IS_ADC_DATA_ALIGN_TYPE(x) (((x) == ALD_ADC_DATAALIGN_RIGHT) || \ + ((x) == ALD_ADC_DATAALIGN_LEFT)) +#define IS_ADC_ANALOG_WTD_MODE_TYPE(x) (((x) == ALD_ADC_ANAWTD_NONE) || \ + ((x) == ALD_ADC_ANAWTD_SING_NM) || \ + ((x) == ALD_ADC_ANAWTD_SING_IST) || \ + ((x) == ALD_ADC_ANAWTD_SING_NMIST) || \ + ((x) == ALD_ADC_ANAWTD_ALL_NM) || \ + ((x) == ALD_ADC_ANAWTD_ALL_IST) || \ + ((x) == ALD_ADC_ANAWTD_ALL_NMIST)) +#define IS_ADC_IT_TYPE(x) (((x) == ALD_ADC_IT_NCH) || \ + ((x) == ALD_ADC_IT_AWD) || \ + ((x) == ALD_ADC_IT_ICH) || \ + ((x) == ALD_ADC_IT_OVR )) +#define IS_ADC_FLAGS_TYPE(x) (((x) == ALD_ADC_FLAG_AWD) || \ + ((x) == ALD_ADC_FLAG_NCH) || \ + ((x) == ALD_ADC_FLAG_ICH) || \ + ((x) == ALD_ADC_FLAG_OVR) || \ + ((x) == ALD_ADC_FLAG_NCHS) || \ + ((x) == ALD_ADC_FLAG_ICHS)) +#define IS_ADC_CLK_DIV_TYPE(x) (((x) == ALD_ADC_CKDIV_2) || \ + ((x) == ALD_ADC_CKDIV_4) || \ + ((x) == ALD_ADC_CKDIV_8) || \ + ((x) == ALD_ADC_CKDIV_16) || \ + ((x) == ALD_ADC_CKDIV_32) || \ + ((x) == ALD_ADC_CKDIV_64) || \ + ((x) == ALD_ADC_CKDIV_128) || \ + ((x) == ALD_ADC_CKDIV_256)) +#define IS_ADC_NEG_REF_VOLTAGE_TYPE(x) (((x) == ALD_ADC_NEG_REF_VSS ) || \ + ((x) == ALD_ADC_NEG_REF_VREFN )) +#define IS_POS_REF_VOLTAGE_TYPE(x) (((x) == ALD_ADC_POS_REF_VDD) || \ + ((x) == ALD_ADC_POS_REF_VREEFP)) +#define IS_ADC_NCH_NR_TYPE(x) ((x) <= ALD_ADC_NCH_NR_16) +#define IS_ADC_ICH_NR_TYPE(x) ((x) <= ALD_ADC_ICH_NR_4) +#define IS_ADC_DISC_NR_TYPE(x) ((x) <= ALD_ADC_DISC_NR_8) +#define IS_ADC_CONV_BIT_TYPE(x) (((x) == ALD_ADC_CONV_BIT_6) || \ + ((x) == ALD_ADC_CONV_BIT_8) || \ + ((x) == ALD_ADC_CONV_BIT_10) || \ + ((x) == ALD_ADC_CONV_BIT_12)) +#define IS_ADC_TYPE(x) (((x) == ADC)) +#define IS_ADC_NCHESEL_MODE_TYPE(x) (((x) == ALD_ADC_NCHESEL_MODE_ALL) || \ + ((x) == ALD_ADC_NCHESEL_MODE_ONE)) +#define IS_ADC_EVENT_TYPE(x) ((x) == ALD_ADC_AWD_EVENT) +#define IS_ADC_NCH_OFFSET_TYPE(x) ((x) <= 0xfff) +#define IS_ADC_IST_OFFSET_TYPE(x) ((x) <= 0xfff) +#define IS_HTR_TYPE(x) ((x) <= 0xfff) +#define IS_LTR_TYPE(x) ((x) <= 0xfff) +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @addtogroup ADC_Public_Functions + * @{ + */ + +/** @addtogroup ADC_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_adc_init(ald_adc_handle_t *hperh); +ald_status_t ald_adc_reset(ald_adc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group2 + * @{ + */ +ald_status_t ald_adc_normal_start(ald_adc_handle_t *hperh); +ald_status_t ald_adc_normal_stop(ald_adc_handle_t *hperh); +ald_status_t ald_adc_normal_poll_for_conversion(ald_adc_handle_t *hperh, uint32_t timeout); +ald_status_t ald_adc_poll_for_event(ald_adc_handle_t *hperh, ald_adc_event_type_t event_type, uint32_t timeout); +ald_status_t ald_adc_normal_start_by_it(ald_adc_handle_t *hperh); +ald_status_t ald_adc_normal_stop_by_it(ald_adc_handle_t *hperh); + +ald_status_t ald_adc_start_by_dma(ald_adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_adc_stop_by_dma(ald_adc_handle_t *hperh, uint8_t channel); +ald_status_t ald_adc_timer_trigger_adc_by_dma(ald_adc_timer_config_t *config); +ald_status_t ald_adc_timer_trigger_insert(ald_adc_timer_config_t *config); + +uint32_t ald_adc_normal_get_value(ald_adc_handle_t *hperh); +ald_status_t ald_adc_insert_start(ald_adc_handle_t *hperh); +ald_status_t ald_adc_insert_stop(ald_adc_handle_t *hperh); +ald_status_t ald_adc_insert_poll_for_conversion(ald_adc_handle_t *hperh, uint32_t timeout); +ald_status_t ald_adc_insert_start_by_it(ald_adc_handle_t *hperh); +ald_status_t ald_adc_insert_stop_by_it(ald_adc_handle_t *hperh); +uint32_t ald_adc_insert_get_value(ald_adc_handle_t *hperh, ald_adc_ich_idx_t ih_rank); +void ald_adc_irq_handler(ald_adc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group3 + * @{ + */ +ald_status_t ald_adc_normal_channel_config(ald_adc_handle_t *hperh, ald_adc_nch_conf_t *config); +ald_status_t ald_adc_insert_channel_config(ald_adc_handle_t *hperh, ald_adc_ich_conf_t *config); +ald_status_t ald_adc_analog_wdg_config(ald_adc_handle_t *hperh, ald_adc_analog_wdg_conf_t *config); +void ald_adc_interrupt_config(ald_adc_handle_t *hperh, ald_adc_it_t it, type_func_t state); +it_status_t ald_adc_get_it_status(ald_adc_handle_t *hperh, ald_adc_it_t it); +flag_status_t ald_adc_get_flag_status(ald_adc_handle_t *hperh, ald_adc_flag_t flag); +void ald_adc_clear_flag_status(ald_adc_handle_t *hperh, ald_adc_flag_t flag); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group4 + * @{ + */ +uint32_t ald_adc_get_state(ald_adc_handle_t *hperh); +uint32_t ald_adc_get_error(ald_adc_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_ADC_H */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_cmu.c b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_cmu.c new file mode 100644 index 0000000000..1d11fa253c --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_cmu.c @@ -0,0 +1,921 @@ +/** + ********************************************************************************* + * + * @file ald_cmu.c + * @brief CMU module driver. + * + * @version V1.0 + * @date 13 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 13 Feb. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + *** System clock configure *** + ================================= + [..] + (+) If you don't change system clock, you can using ald_cmu_clock_config_default() API. + It will select HRC as system clock. The system clock is 48MHz. + (+) If you want to change system clock, you can using ald_cmu_clock_config() API. + You can select one of the following as system clock: + @ref CMU_CLOCK_HRC 4MHz or 48MHz + @ref CMU_CLOCK_LRC 32000Hz + @ref CMU_CLOCK_PLL 48MHz, 64MHz or 72MHz + @ref CMU_CLOCK_HOSC 32000Hz, 4MHz, 8MHz, 12MHz, 16MHz, 20MHz, 24MHz + (+) If you select CMU_CLOCK_PLL as system clock, it must config the PLL + using ald_cmu_pll_config() API. + (+) If you get current clock, you can using ald_cmu_get_clock() API. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_conf.h" + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup CMU CMU + * @brief CMU module driver + * @{ + */ + +/* Private Variables --------------------------------------------------------- */ + +/** + * @defgroup CMU_Private_Variables CMU Private Variables + * @{ + */ +uint32_t __system_clock = 48000000U; +/** + * @} + */ + +/* Private Macros ------------------------------------------------------------ */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ +/* Private Function ---------------------------------------------------------- */ + +/** @defgroup CMU_Private_Functions CMU Private Functions + * @{ + */ + +/** + * @brief Update the current system clock. This function + * will be invoked, when system clock has changed. + * @param clock: The new clock. + * @retval None + */ + +static void cmu_clock_update(uint32_t clock) +{ + __system_clock = clock; + + if (clock > 1000000) + ald_tick_init(TICK_INT_PRIORITY); + + return; +} + +/** + * @brief CMU module interrupt handler + * @retval None + */ +void ald_cmu_irq_handler(void) +{ + /* HOSC stop */ + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK)) + { + ALD_SYSCFG_UNLOCK(); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); + ALD_SYSCFG_LOCK(); + + if ((READ_BIT(CMU->HOSMCR, CMU_HOSMCR_FLAG_MSK)) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 3) + || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) + cmu_clock_update(4000000); /* HRC4M */ + + ald_cmu_irq_cbk(ALD_CMU_HOSC_STOP); + } + + /* HOSC start */ + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIE_MSK)) + { + ALD_SYSCFG_UNLOCK(); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK); + ALD_SYSCFG_LOCK(); + + if (!(READ_BIT(CMU->HOSMCR, CMU_HOSMCR_FLAG_MSK)) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 3))) + { + if (READ_BITS(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, CMU_HOSCCFG_FREQ_POSS) > 0x5) + cmu_clock_update(4000000); /* HOSC4M */ + else + cmu_clock_update((READ_BITS(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, CMU_HOSCCFG_FREQ_POSS) + 1) * 4000000); + } + + ald_cmu_irq_cbk(ALD_CMU_HOSC_START); + } + + /* PLL unlock */ + if (READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK) && READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK)) + { + ALD_SYSCFG_UNLOCK(); + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); + ALD_SYSCFG_LOCK(); + + if (READ_BIT(CMU->PULMCR, CMU_PULMCR_CLKS_MSK) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 3) + || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) + cmu_clock_update(4000000); /* HRC4M */ + + ald_cmu_irq_cbk(ALD_CMU_PLL_UNLOCK); + } + + return; +} +/** + * @} + */ + +/** @defgroup CMU_Public_Functions CMU Public Functions + * @{ + */ + +/** @defgroup CMU_Public_Functions_Group1 System clock configuration + * @brief System clock configuration functions + * + ============================================================================== + ##### System clock Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure system clock using default parameters. + (+) Configure system clock using specified parameters. + (+) Configure PLL using specified parameters. + (+) Get system clock. + * @{ + */ + +/** + * @brief Configure system clock using default. + * Select CMU_CLOCK_HRC(48MHz) as system clock and + * enable CMU_CLOCK_LRC(32000Hz). + * @retval The status of ALD. + */ +ald_status_t ald_cmu_clock_config_default(void) +{ + uint32_t cnt = 4000U, tmp; + + ald_flash_wait_config(2); + + ALD_SYSCFG_UNLOCK(); + + WRITE_REG(CMU->CFGR, 0x0); + + tmp = READ_REG(CMU->CLKENR); + /* Enable HRC48M */ + SET_BIT(tmp, CMU_CLKENR_HRC48MEN_MSK); + WRITE_REG(CMU->CLKENR, tmp); + + for (cnt = 4000; cnt; --cnt); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC48MACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC48MRDY_MSK))) && (--cnt)); + + /* Select HRC48M */ + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, ALD_CMU_CLOCK_HRC48M << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != ALD_CMU_CLOCK_HRC48M) + { + ALD_SYSCFG_LOCK(); + return ALD_ERROR; + } + + cmu_clock_update(48000000); + + ALD_SYSCFG_LOCK(); + + return ALD_OK; +} + +/** + * @brief Configure system clock using specified parameters + * @param clk: The parameter can be one of the following: + * @arg @ref CMU_CLOCK_HRC 4MHz or 48MHz + * @arg @ref CMU_CLOCK_LRC 32kHz + * @arg @ref CMU_CLOCK_PLL 48MHz, 64MHz, 72MHz + * @arg @ref CMU_CLOCK_HOSC 4MHz, 8MHz, 12MHz + * @param clock: The clock which will be set. the value depends + * on the parameter of clk. + * @retval The status of ALD. + */ +ald_status_t ald_cmu_clock_config(ald_cmu_clock_t clk, uint32_t clock) +{ + uint32_t cnt = 8000U; + + ald_flash_wait_config(2); + + assert_param(IS_CMU_CLOCK(clk)); + ALD_SYSCFG_UNLOCK(); + + switch (clk) + { + case ALD_CMU_CLOCK_HRC48M: + assert_param(clock == 48000000); + + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC48MEN_MSK); + + for (cnt = 4000; cnt; --cnt); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC48MACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC48MRDY_MSK))) && (--cnt)); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, ALD_CMU_CLOCK_HRC48M << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != ALD_CMU_CLOCK_HRC48M) + { + ALD_SYSCFG_LOCK(); + return ALD_ERROR; + } + + cmu_clock_update(clock); + + break; + + case ALD_CMU_CLOCK_LRC: + + assert_param(clock == 32000); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCRDY_MSK))) && (--cnt)); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, ALD_CMU_CLOCK_LRC << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != ALD_CMU_CLOCK_LRC) + { + ALD_SYSCFG_LOCK(); + return ALD_ERROR; + } + + cmu_clock_update(clock); + + break; + + case ALD_CMU_CLOCK_HOSC: + assert_param(clock == 4000000 || clock == 8000000 || clock == 12000000); + + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); + + MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 4000000 - 1); + + for (cnt = 8000; cnt; --cnt); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt)); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, ALD_CMU_CLOCK_HOSC << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != ALD_CMU_CLOCK_HOSC) + { + ALD_SYSCFG_LOCK(); + return ALD_ERROR; + } + + cmu_clock_update(clock); + break; + + case ALD_CMU_CLOCK_PLL: + assert_param(clock == 72000000 || clock == 64000000 || clock == 48000000); + + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLLEN_MSK); + + for (cnt = 4000; cnt; --cnt); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLLACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLLRDY_MSK))) && (--cnt)); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, ALD_CMU_CLOCK_PLL << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != ALD_CMU_CLOCK_PLL) + { + ALD_SYSCFG_LOCK(); + return ALD_ERROR; + } + + cmu_clock_update(clock); + + break; + + case ALD_CMU_CLOCK_HRC4M: + assert_param(clock == 4000000); + + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC4MEN_MSK); + + for (cnt = 4000; cnt; --cnt); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC4MACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC4MRDY_MSK))) && (--cnt)); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, ALD_CMU_CLOCK_HRC4M << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != ALD_CMU_CLOCK_HRC4M) + { + ALD_SYSCFG_LOCK(); + return ALD_ERROR; + } + + cmu_clock_update(clock); + + break; + + default: + break; + } + + ALD_SYSCFG_LOCK(); + return ALD_OK; +} + +/** + * @brief Configure PLL using specified parameters. + * @param input: The input clock type. + * @param output: The output clock which can be 48MHz/64MHz/72MHz. + * @retval None + */ +void ald_cmu_pll_config(ald_cmu_pll_input_t input, ald_cmu_pll_output_t output) +{ + uint32_t cnt = 4000U; + + assert_param(IS_CMU_PLL_INPUT(input)); + assert_param(IS_CMU_PLL_OUTPUT(output)); + + ALD_SYSCFG_UNLOCK(); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == ALD_CMU_CLOCK_PLL) + { + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC48MEN_MSK); + + for (cnt = 4000; cnt; --cnt); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC48MACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC48MRDY_MSK))) && (--cnt)); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, ALD_CMU_CLOCK_HRC48M << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + } + + if (input == ALD_CMU_PLL_INPUT_HRC4M) + { + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC4MEN_MSK); + } + else + { + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); + + if (input == ALD_CMU_PLL_INPUT_HOSC4M) + { + MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, 0); + } + else if (input == ALD_CMU_PLL_INPUT_HOSC8M) + { + MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, 1); + } + else + { + + } + + cnt = 20000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt)); + } + + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLLEN_MSK); + + MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_REFS_MSK, input << CMU_PLLCFG_REFS_POSS); + MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_CLKOS_MSK, output << CMU_PLLCFG_CLKOS_POSS); + + SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); + MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 0x2 << CMU_PULMCR_MODE_POSS); + + ALD_SYSCFG_LOCK(); + return; +} + +/** + * @brief Gets current system clock. + * @retval The value of system clock. + */ +uint32_t ald_cmu_get_clock(void) +{ + return __system_clock; +} + +/** + * @} + */ + +/** @defgroup CMU_Public_Functions_Group2 BUS division control + * @brief BUS division control functions + * + ============================================================================== + ##### BUS division control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure system clock div specified parameters. + (+) Get SYS clock. + (+) Get APB clock. + * @{ + */ + +/** + * @brief Configure the bus division. + * @param bus: The type of bus: + * @arg CMU_SYS + * @arg CMU_PCLK + * @param clk_div: The value of divider. + * @retval None + */ +void ald_cmu_div_config(ald_cmu_bus_t bus, ald_cmu_div_t clk_div) +{ + assert_param(IS_CMU_BUS(bus)); + assert_param(IS_CMU_DIV(clk_div)); + + ALD_SYSCFG_UNLOCK(); + + switch (bus) + { + case ALD_CMU_SYS: + MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, clk_div << CMU_CFGR_SYSDIV_POSS); + ald_tick_init(TICK_INT_PRIORITY); + break; + + case ALD_CMU_PCLK: + MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLKDIV_MSK, clk_div << CMU_CFGR_PCLKDIV_POSS); + break; + + default: + break; + } + + ALD_SYSCFG_LOCK(); + return; +} + +/** + * @brief Get SYS clock. + * @retval The value of SYS clock. + */ +uint32_t ald_cmu_get_sys_clock(void) +{ + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + + return __system_clock >> sys_div; +} + +/** + * @brief Get APB clock. + * @retval The value of APB clock. + */ +uint32_t ald_cmu_get_pclk_clock(void) +{ + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t apb_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLKDIV_MSK, CMU_CFGR_PCLKDIV_POSS); + + return (__system_clock >> sys_div) >> apb_div; +} + +/** + * @} + */ + +/** @defgroup CMU_Public_Functions_Group3 Clock safe configure + * @brief Clock safe configure functions + * + * @verbatim + ============================================================================== + ##### Clock safe configure functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable outer high crystal safe mode. + (+) Enable/Disable outer low crystal safe mode. + (+) Enable/Disable PLL safe mode. + (+) Interrupt callback function. + + @endverbatim + * @{ + */ + +/** + * @brief Enable/Disable outer high crystal safe mode. + * @param clock: the value of outer crystal frequency. + * @param status: The new status. + * @retval None + */ +void ald_cmu_hosc_safe_config(ald_cmu_hosc_range_t clock, type_func_t status) +{ + assert_param(IS_CMU_HOSC_RANGE(clock)); + assert_param(IS_FUNC_STATE(status)); + + ALD_SYSCFG_UNLOCK(); + + if (status) + { + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); + MODIFY_REG(CMU->HOSMCR, CMU_HOSMCR_FRQS_MSK, clock << CMU_HOSMCR_FRQS_POSS); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); + + ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); + } + else + { + CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); + CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); + + if (READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) + ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); + } + + ALD_SYSCFG_LOCK(); + return; +} + +/** + * @brief Enable/Disable PLL1 safe mode. + * @param status: The new status. + * @retval None + */ +void ald_cmu_pll_safe_config(type_func_t status) +{ + assert_param(IS_FUNC_STATE(status)); + ALD_SYSCFG_UNLOCK(); + + if (status) + { + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); + MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 2 << CMU_PULMCR_MODE_POSS); + SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); + + ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); + } + else + { + CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); + CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); + + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0) + ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); + } + + ALD_SYSCFG_LOCK(); + return; +} + +/** + * @brief Get current clock source. + * @retval Status: + * - 0: Current clock is PLL + * - 1: Current clock is HRC + */ +uint32_t ald_cmu_pulmcr_current_clock_source_get(void) +{ + return READ_BITS(CMU->PULMCR, CMU_PULMCR_CLKS_MSK, CMU_PULMCR_CLKS_POS); +} + +/** + * @brief Get clock state. + * @param sr: The state type, see @ref cmu_clock_state_t. + * @retval SET/RESET + */ +flag_status_t ald_cmu_get_clock_state(ald_cmu_clock_state_t sr) +{ + assert_param(IS_CMU_CLOCK_STATE(sr)); + + if (READ_BIT(CMU->CLKSR, sr)) + return SET; + + return RESET; +} + +/** + * @brief Interrupt callback function. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void ald_cmu_irq_cbk(ald_cmu_security_t se) +{ + return; +} +/** + * @} + */ + +/** @defgroup CMU_Public_Functions_Group4 Clock output configure + * @brief Clock output configure functions + * + * @verbatim + ============================================================================== + ##### Clock output configure functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure the high-speed clock output. + (+) Configure the low-speed clock output. + + @endverbatim + * @{ + */ + +/** + * @brief Configure the high-speed clock output. + * @param sel: Select the source: + * @arg CMU_OUTPUT_HIGH_SEL_HOSC + * @arg CMU_OUTPUT_HIGH_SEL_HOSM + * @arg CMU_OUTPUT_HIGH_SEL_HRC4M + * @arg CMU_OUTPUT_HIGH_SEL_LRC + * @arg CMU_OUTPUT_HIGH_SEL_SYSCLK + * @arg CMU_OUTPUT_HIGH_SEL_HOSC32K + * @arg CMU_OUTPUT_HIGH_SEL_HRC48M + * @arg CMU_OUTPUT_HIGH_SEL_PLL + * @param clk_div: The value of divider: + * @arg CMU_OUTPUT_DIV_1 + * @arg CMU_OUTPUT_DIV_2 + * @arg CMU_OUTPUT_DIV_4 + * @arg CMU_OUTPUT_DIV_8 + * @arg CMU_OUTPUT_DIV_16 + * @arg CMU_OUTPUT_DIV_32 + * @arg CMU_OUTPUT_DIV_64 + * @arg CMU_OUTPUT_DIV_128 + * @param status: The new status. + * @retval None + */ +void ald_cmu_output_high_clock_config(ald_cmu_output_high_sel_t sel, + ald_cmu_output_high_div_t clk_div, type_func_t status) +{ + assert_param(IS_CMU_OUTPUT_HIGH_SEL(sel)); + assert_param(IS_CMU_OUTPUT_HIGH_DIV(clk_div)); + assert_param(IS_FUNC_STATE(status)); + + ALD_SYSCFG_UNLOCK(); + + if (status) + { + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCOS_MSK, sel << CMU_CLKOCR_HSCOS_POSS); + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCODIV_MSK, clk_div << CMU_CLKOCR_HSCODIV_POSS); + SET_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); + } + else + { + CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); + } + + ALD_SYSCFG_LOCK(); + return; +} + +/** + * @brief Configure the low-speed clock output. + * @param sel: Select the source: + * @arg CMU_OUTPUT_LOW_SEL_LRC + * @arg CMU_OUTPUT_LOW_SEL_BUZZ + * @param status: The new status. + * @retval None + */ +void ald_cmu_output_low_clock_config(ald_cmu_output_low_sel_t sel, type_func_t status) +{ + assert_param(IS_CMU_OUTPUT_LOW_SEL(sel)); + assert_param(IS_FUNC_STATE(status)); + + ALD_SYSCFG_UNLOCK(); + + if (status) + { + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_LSCOS_MSK, sel << CMU_CLKOCR_LSCOS_POSS); + SET_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); + } + else + { + CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); + } + + ALD_SYSCFG_LOCK(); + return; +} +/** + * @} + */ + +/** @defgroup CMU_Public_Functions_Group5 Peripheral Clock configure + * @brief Peripheral clock configure functions + * + * @verbatim + ============================================================================== + ##### Peripheral clock configure functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure buzz clock. + (+) Enable/Disable peripheral clock. + + @endverbatim + * @{ + */ + +/** + * @brief Configure buzz clock. + * freq = sysclk / (2^(clk_div + 1) * (dat + 1)) + * @param clk_div: The value of divider. + * @param dat: The value of coefficient. + * @param status: The new status. + * @retval None + */ +void ald_cmu_buzz_config(ald_cmu_buzz_div_t clk_div, uint16_t dat, type_func_t status) +{ + assert_param(IS_CMU_BUZZ_DIV(clk_div)); + assert_param(IS_FUNC_STATE(status)); + + ALD_SYSCFG_UNLOCK(); + + if (status) + { + MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DIV_MSK, clk_div << CMU_BUZZCR_DIV_POSS); + MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DAT_MSK, dat << CMU_BUZZCR_DAT_POSS); + SET_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); + } + else + { + CLEAR_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); + } + + ALD_SYSCFG_LOCK(); + return; +} + +/** + * @brief Enable/Disable peripheral clock. + * @param perh: The type of peripheral, you can see @ref cmu_perh_t + * @param status: The new status. + * @retval None + */ +void ald_cmu_perh_clock_config(ald_cmu_perh_t perh, type_func_t status) +{ + uint32_t idx, pos; + + assert_param(IS_CMU_PERH(perh)); + assert_param(IS_FUNC_STATE(status)); + + ALD_SYSCFG_UNLOCK(); + + if (perh == ALD_CMU_PERH_ALL) + { + if (status) + { + WRITE_REG(CMU->AHBENR, ~0); + WRITE_REG(CMU->APBENR, ~0); + } + else + { + WRITE_REG(CMU->AHBENR, 0); + WRITE_REG(CMU->APBENR, 0); + } + + ALD_SYSCFG_LOCK(); + return; + } + + idx = ((uint32_t)perh >> 27) & 0x1; + pos = perh & ~(0x1 << 27); + + if (status) + { + switch (idx) + { + case 0: + SET_BIT(CMU->AHBENR, pos); + break; + + case 1: + SET_BIT(CMU->APBENR, pos); + break; + + default: + break; + } + } + else + { + switch (idx) + { + case 0: + CLEAR_BIT(CMU->AHBENR, pos); + break; + + case 1: + CLEAR_BIT(CMU->APBENR, pos); + break; + + default: + break; + } + } + + ALD_SYSCFG_LOCK(); + return; +} + +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_cmu.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_cmu.h new file mode 100644 index 0000000000..ea5f11217b --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_cmu.h @@ -0,0 +1,435 @@ +/** + ********************************************************************************* + * + * @file ald_cmu.h + * @brief Header file of CMU module driver. + * + * @version V1.0 + * @date 30 Jan. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 30 Jan. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_CMU_H__ +#define __ALD_CMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_syscfg.h" + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Constants -------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup CMU + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup CMU_Public_Types CMU Public Types + * @{ + */ +/** + * @brief CMU state structure definition + */ +typedef enum +{ + ALD_CMU_CLOCK_HRC48M = 0x1U, /**< HRC48M */ + ALD_CMU_CLOCK_LRC = 0x2U, /**< LRC */ + ALD_CMU_CLOCK_HOSC = 0x3U, /**< HOSC */ + ALD_CMU_CLOCK_PLL = 0x4U, /**< PLL */ + ALD_CMU_CLOCK_HRC4M = 0x5U, /**< HRC4M */ +} ald_cmu_clock_t; + +/** + * @brief PLL output clock + */ +typedef enum +{ + ALD_CMU_PLL_OUTPUT_72M = 0x0U, /**< 72MHz */ + ALD_CMU_PLL_OUTPUT_64M = 0x2U, /**< 64MHz */ + ALD_CMU_PLL_OUTPUT_48M = 0x3U, /**< 48MHz */ +} ald_cmu_pll_output_t; + +/** + * @brief PLL referance clock + */ +typedef enum +{ + ALD_CMU_PLL_INPUT_HRC4M = 0x0U, /**< HRC4M */ + ALD_CMU_PLL_INPUT_HOSC4M = 0x1U, /**< HOSC4M */ + ALD_CMU_PLL_INPUT_HOSC8M = 0x2U, /**< HOSC8M */ +} ald_cmu_pll_input_t; + +/** + * @brief HOSC range + */ +typedef enum +{ + ALD_CMU_HOSC_1M_2M = 0x0U, /**< 1~2MHz */ + ALD_CMU_HOSC_2M_4M = 0x1U, /**< 2~4MHz */ + ALD_CMU_HOSC_4M_8M = 0x2U, /**< 4~8MHz */ + ALD_CMU_HOSC_8M_12M = 0x3U, /**< 8~12MHz */ +} ald_cmu_hosc_range_t; + +/** + * @brief Frequency division select bit + */ +typedef enum +{ + ALD_CMU_DIV_1 = 0x0U, /**< Division by 1 */ + ALD_CMU_DIV_2 = 0x1U, /**< Division by 2 */ + ALD_CMU_DIV_4 = 0x2U, /**< Division by 4 */ + ALD_CMU_DIV_8 = 0x3U, /**< Division by 8 */ + ALD_CMU_DIV_16 = 0x4U, /**< Division by 16 */ + ALD_CMU_DIV_32 = 0x5U, /**< Division by 32 */ + ALD_CMU_DIV_64 = 0x6U, /**< Division by 64 */ + ALD_CMU_DIV_128 = 0x7U, /**< Division by 128 */ + ALD_CMU_DIV_256 = 0x8U, /**< Division by 256 */ + ALD_CMU_DIV_512 = 0x9U, /**< Division by 512 */ + ALD_CMU_DIV_1024 = 0xAU, /**< Division by 1024 */ + ALD_CMU_DIV_2048 = 0xBU, /**< Division by 2048 */ + ALD_CMU_DIV_4096 = 0xCU, /**< Division by 4096 */ +} ald_cmu_div_t; + +/** + * @brief BUZZ frequency division + */ +typedef enum +{ + ALD_CMU_BUZZ_DIV_2 = 0x0U, /**< Division by 2 */ + ALD_CMU_BUZZ_DIV_4 = 0x1U, /**< Division by 4 */ + ALD_CMU_BUZZ_DIV_8 = 0x2U, /**< Division by 8 */ + ALD_CMU_BUZZ_DIV_16 = 0x3U, /**< Division by 16 */ + ALD_CMU_BUZZ_DIV_32 = 0x4U, /**< Division by 32 */ + ALD_CMU_BUZZ_DIV_64 = 0x5U, /**< Division by 64 */ + ALD_CMU_BUZZ_DIV_128 = 0x6U, /**< Division by 128 */ + ALD_CMU_BUZZ_DIV_256 = 0x7U, /**< Division by 256 */ +} ald_cmu_buzz_div_t; + +/** + * @brief Safe clock source type + */ +typedef enum +{ + ALD_CMU_SAFE_CLK_PLL = 0x0U, /**< PLL */ +} ald_cmu_clock_safe_type_t; + +/** + * @brief Bus type + */ +typedef enum +{ + ALD_CMU_SYS = 0x1U, /**< SYS bus */ + ALD_CMU_PCLK = 0x2U, /**< APB bus */ +} ald_cmu_bus_t; + +/** + * @brief Output frequency division + */ +typedef enum +{ + ALD_CMU_OUTPUT_DIV_1 = 0x0U, /**< Division by 1 */ + ALD_CMU_OUTPUT_DIV_2 = 0x1U, /**< Division by 2 */ + ALD_CMU_OUTPUT_DIV_4 = 0x2U, /**< Division by 4 */ + ALD_CMU_OUTPUT_DIV_8 = 0x3U, /**< Division by 8 */ + ALD_CMU_OUTPUT_DIV_16 = 0x4U, /**< Division by 16 */ + ALD_CMU_OUTPUT_DIV_32 = 0x5U, /**< Division by 32 */ + ALD_CMU_OUTPUT_DIV_64 = 0x6U, /**< Division by 64 */ + ALD_CMU_OUTPUT_DIV_128 = 0x7U, /**< Division by 128 */ +} ald_cmu_output_high_div_t; + +/** + * @brief Output high clock select + */ +typedef enum +{ + ALD_CMU_OUTPUT_HIGH_SEL_HOSC = 0x0U, /**< Select HOSC */ + ALD_CMU_OUTPUT_HIGH_SEL_HOSM = 0x1U, /**< Select HOSM */ + ALD_CMU_OUTPUT_HIGH_SEL_HRC4M = 0x2U, /**< Select HRC4M */ + ALD_CMU_OUTPUT_HIGH_SEL_LRC = 0x3U, /**< Select LRC */ + ALD_CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x4U, /**< Select SYSCLK */ + ALD_CMU_OUTPUT_HIGH_SEL_HOSC32K = 0x5U, /**< Select HOSC32K */ + ALD_CMU_OUTPUT_HIGH_SEL_HRC48M = 0x6U, /**< Select HRC48M */ + ALD_CMU_OUTPUT_HIGH_SEL_PLL = 0x7U, /**< Select PLL */ +} ald_cmu_output_high_sel_t; + +/** + * @brief Output low clock select + */ +typedef enum +{ + ALD_CMU_OUTPUT_LOW_SEL_LRC = 0x0U, /**< Select LRC */ + ALD_CMU_OUTPUT_LOW_SEL_BUZZ = 0x1U, /**< Select BUZZ */ +} ald_cmu_output_low_sel_t; + +/** + * @brief Peripheral clock enable/disable + */ +typedef enum +{ + ALD_CMU_PERH_GPIO = (1U << 0), /**< GPIO */ + ALD_CMU_PERH_CRC = (1U << 1), /**< CRC */ + ALD_CMU_PERH_DMA = (1U << 2), /**< DMA */ + ALD_CMU_PERH_PIS = (1U << 5), /**< PIS */ + ALD_CMU_PERH_USB = (1U << 6), /**< USB */ + ALD_CMU_PERH_CSU = (1U << 7), /**< CSU */ + ALD_CMU_PERH_AD16C4T0 = (1U << 0) | (1U << 27), /**< AD16C4T0 */ + ALD_CMU_PERH_BS16T0 = (1U << 1) | (1U << 27), /**< BS16T0 */ + ALD_CMU_PERH_GP16C4T0 = (1U << 2) | (1U << 27), /**< CP16C4T0 */ + ALD_CMU_PERH_GP16C4T1 = (1U << 3) | (1U << 27), /**< GP16C4T1 */ + ALD_CMU_PERH_GP16C4T2 = (1U << 4) | (1U << 27), /**< GP16C4T2 */ + ALD_CMU_PERH_EUART0 = (1U << 8) | (1U << 27), /**< EUART0 */ + ALD_CMU_PERH_EUART1 = (1U << 9) | (1U << 27), /**< EUART1 */ + ALD_CMU_PERH_CUART0 = (1U << 12) | (1U << 27), /**< CUART0 */ + ALD_CMU_PERH_CUART1 = (1U << 13) | (1U << 27), /**< CUART1 */ + ALD_CMU_PERH_CUART2 = (1U << 14) | (1U << 27), /**< CUART2 */ + ALD_CMU_PERH_SPI0 = (1U << 16) | (1U << 27), /**< SPI0 */ + ALD_CMU_PERH_SPI1 = (1U << 17) | (1U << 27), /**< SPI1 */ + ALD_CMU_PERH_I2C0 = (1U << 20) | (1U << 27), /**< I2C0 */ + ALD_CMU_PERH_I2C1 = (1U << 21) | (1U << 27), /**< I2C1 */ + ALD_CMU_PERH_WWDT = (1U << 22) | (1U << 27), /**< WWDT */ + ALD_CMU_PERH_IWDT = (1U << 23) | (1U << 27), /**< IWDT */ + ALD_CMU_PERH_DBGC = (1U << 24) | (1U << 27), /**< DBGC */ + ALD_CMU_PERH_ADC = (1U << 25) | (1U << 27), /**< ADC */ + ALD_CMU_PERH_ALL = (0x7FFFFFFFU), /**< ALL */ +} ald_cmu_perh_t; + +/** + * @brief CMU interrupt type + */ +typedef enum +{ + ALD_CMU_HOSC_STOP = 0x0U, /**< HOSC STOP INTERRUPT */ + ALD_CMU_PLL_UNLOCK = 0x1U, /**< PLL UNLOCK INTERRUPT */ + ALD_CMU_HOSC_START = 0x2U, /**< HOSC START INTERRUPT */ +} ald_cmu_security_t; + +/** + * @brief CMU clock state type + */ +typedef enum +{ + ALD_CMU_CLOCK_STATE_HOSCACT = (1U << 0), /**< HOSC active */ + ALD_CMU_CLOCK_STATE_PLLACT = (1U << 1), /**< PLL active */ + ALD_CMU_CLOCK_STATE_HRC4MACT = (1U << 2), /**< HRC4M active */ + ALD_CMU_CLOCK_STATE_HRC48MACT = (1U << 3), /**< HRC48M active */ + ALD_CMU_CLOCK_STATE_HOSCRDY = (1U << 16), /**< HOSC ready */ + ALD_CMU_CLOCK_STATE_HRC4MRDY = (1U << 17), /**< HRC4M ready */ + ALD_CMU_CLOCK_STATE_HRC48MRDY = (1U << 18), /**< HRC48M ready */ + ALD_CMU_CLOCK_STATE_LRCRDY = (1U << 19), /**< LRC ready */ + ALD_CMU_CLOCK_STATE_PLLRDY = (1U << 24), /**< PLL ready */ +} ald_cmu_clock_state_t; + +/** + * @} + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** + * @defgroup CMU_Private_Macros CMU Private Macros + * @{ + */ +#define IS_CMU_CLOCK(x) (((x) == ALD_CMU_CLOCK_HRC48M) || \ + ((x) == ALD_CMU_CLOCK_LRC) || \ + ((x) == ALD_CMU_CLOCK_HOSC) || \ + ((x) == ALD_CMU_CLOCK_PLL) || \ + ((x) == ALD_CMU_CLOCK_HRC4M)) +#define IS_CMU_PLL_INPUT(x) (((x) == ALD_CMU_PLL_INPUT_HRC4M) || \ + ((x) == ALD_CMU_PLL_INPUT_HOSC4M) || \ + ((x) == ALD_CMU_PLL_INPUT_HOSC8M)) +#define IS_CMU_PLL_OUTPUT(x) (((x) == ALD_CMU_PLL_OUTPUT_48M) || \ + ((x) == ALD_CMU_PLL_OUTPUT_64M) || \ + ((x) == ALD_CMU_PLL_OUTPUT_72M)) +#define IS_CMU_HOSC_RANGE(x) (((x) == ALD_CMU_HOSC_1M_2M) || \ + ((x) == ALD_CMU_HOSC_2M_4M) || \ + ((x) == ALD_CMU_HOSC_4M_8M) || \ + ((x) == ALD_CMU_HOSC_8M_12M)) +#define IS_CMU_DIV(x) (((x) == ALD_CMU_DIV_1) || \ + ((x) == ALD_CMU_DIV_2) || \ + ((x) == ALD_CMU_DIV_4) || \ + ((x) == ALD_CMU_DIV_8) || \ + ((x) == ALD_CMU_DIV_16) || \ + ((x) == ALD_CMU_DIV_32) || \ + ((x) == ALD_CMU_DIV_64) || \ + ((x) == ALD_CMU_DIV_128) || \ + ((x) == ALD_CMU_DIV_256) || \ + ((x) == ALD_CMU_DIV_512) || \ + ((x) == ALD_CMU_DIV_1024) || \ + ((x) == ALD_CMU_DIV_2048) || \ + ((x) == ALD_CMU_DIV_4096)) +#define IS_CMU_BUS(x) (((x) == ALD_CMU_PCLK) || \ + ((x) == ALD_CMU_SYS)) +#define IS_CMU_OUTPUT_HIGH_SEL(x) (((x) == ALD_CMU_OUTPUT_HIGH_SEL_HOSC) || \ + ((x) == ALD_CMU_OUTPUT_HIGH_SEL_HOSM) || \ + ((x) == ALD_CMU_OUTPUT_HIGH_SEL_HRC4M) || \ + ((x) == ALD_CMU_OUTPUT_HIGH_SEL_LRC) || \ + ((x) == ALD_CMU_OUTPUT_HIGH_SEL_SYSCLK) || \ + ((x) == ALD_CMU_OUTPUT_HIGH_SEL_HOSC32K) || \ + ((x) == ALD_CMU_OUTPUT_HIGH_SEL_HRC48M) || \ + ((x) == ALD_CMU_OUTPUT_HIGH_SEL_PLL)) +#define IS_CMU_OUTPUT_HIGH_DIV(x) (((x) == ALD_CMU_OUTPUT_DIV_1) || \ + ((x) == ALD_CMU_OUTPUT_DIV_2) || \ + ((x) == ALD_CMU_OUTPUT_DIV_4) || \ + ((x) == ALD_CMU_OUTPUT_DIV_8) || \ + ((x) == ALD_CMU_OUTPUT_DIV_16) || \ + ((x) == ALD_CMU_OUTPUT_DIV_32) || \ + ((x) == ALD_CMU_OUTPUT_DIV_64) || \ + ((x) == ALD_CMU_OUTPUT_DIV_128)) +#define IS_CMU_OUTPUT_LOW_SEL(x) (((x) == ALD_CMU_OUTPUT_LOW_SEL_LRC) || \ + ((x) == ALD_CMU_OUTPUT_LOW_SEL_BUZZ)) +#define IS_CMU_SAFE_CLOCK_TYPE(x) (((x) == ALD_CMU_SAFE_CLK_PLL)) +#define IS_CMU_BUZZ_DIV(x) (((x) == ALD_CMU_BUZZ_DIV_2) || \ + ((x) == ALD_CMU_BUZZ_DIV_4) || \ + ((x) == ALD_CMU_BUZZ_DIV_8) || \ + ((x) == ALD_CMU_BUZZ_DIV_16) || \ + ((x) == ALD_CMU_BUZZ_DIV_32) || \ + ((x) == ALD_CMU_BUZZ_DIV_64) || \ + ((x) == ALD_CMU_BUZZ_DIV_128) || \ + ((x) == ALD_CMU_BUZZ_DIV_256)) +#define IS_CMU_PERH(x) (((x) == ALD_CMU_PERH_GPIO) || \ + ((x) == ALD_CMU_PERH_CRC) || \ + ((x) == ALD_CMU_PERH_DMA) || \ + ((x) == ALD_CMU_PERH_PIS) || \ + ((x) == ALD_CMU_PERH_USB) || \ + ((x) == ALD_CMU_PERH_CSU) || \ + ((x) == ALD_CMU_PERH_AD16C4T0) || \ + ((x) == ALD_CMU_PERH_BS16T0) || \ + ((x) == ALD_CMU_PERH_GP16C4T0) || \ + ((x) == ALD_CMU_PERH_GP16C4T1) || \ + ((x) == ALD_CMU_PERH_GP16C4T2) || \ + ((x) == ALD_CMU_PERH_EUART0) || \ + ((x) == ALD_CMU_PERH_EUART1) || \ + ((x) == ALD_CMU_PERH_CUART0) || \ + ((x) == ALD_CMU_PERH_CUART1) || \ + ((x) == ALD_CMU_PERH_CUART2) || \ + ((x) == ALD_CMU_PERH_SPI0) || \ + ((x) == ALD_CMU_PERH_SPI1) || \ + ((x) == ALD_CMU_PERH_I2C0) || \ + ((x) == ALD_CMU_PERH_I2C1) || \ + ((x) == ALD_CMU_PERH_WWDT) || \ + ((x) == ALD_CMU_PERH_IWDT) || \ + ((x) == ALD_CMU_PERH_DBGC) || \ + ((x) == ALD_CMU_PERH_ADC) || \ + ((x) == ALD_CMU_PERH_ALL)) +#define IS_CMU_CLOCK_STATE(x) (((x) == ALD_CMU_CLOCK_STATE_HOSCACT) || \ + ((x) == ALD_CMU_CLOCK_STATE_PLLACT) || \ + ((x) == ALD_CMU_CLOCK_STATE_HRC4MACT) || \ + ((x) == ALD_CMU_CLOCK_STATE_HRC48MACT) || \ + ((x) == ALD_CMU_CLOCK_STATE_HOSCRDY) || \ + ((x) == ALD_CMU_CLOCK_STATE_HRC4MRDY) || \ + ((x) == ALD_CMU_CLOCK_STATE_HRC48MRDY) || \ + ((x) == ALD_CMU_CLOCK_STATE_LRCRDY) || \ + ((x) == ALD_CMU_CLOCK_STATE_PLLRDY)) +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @addtogroup CMU_Public_Functions + * @{ + */ +/** @addtogroup CMU_Public_Functions_Group1 Initialization functions + * @{ + */ +/* System clock configure */ +ald_status_t ald_cmu_clock_config_default(void); +ald_status_t ald_cmu_clock_config(ald_cmu_clock_t clk, uint32_t clock); +void ald_cmu_pll_config(ald_cmu_pll_input_t input, ald_cmu_pll_output_t output); +uint32_t ald_cmu_get_clock(void); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group2 + * @{ + */ +/* BUS division control */ +void ald_cmu_div_config(ald_cmu_bus_t bus, ald_cmu_div_t clk_div); +uint32_t ald_cmu_get_sys_clock(void); +uint32_t ald_cmu_get_pclk_clock(void); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group3 + * @{ + */ +/* Clock safe configure */ +void ald_cmu_hosc_safe_config(ald_cmu_hosc_range_t clock, type_func_t status); +void ald_cmu_pll_safe_config(type_func_t status); +uint32_t ald_cmu_pulmcr_current_clock_source_get(void); +flag_status_t ald_cmu_get_clock_state(ald_cmu_clock_state_t sr); +void ald_cmu_irq_handler(void); +void ald_cmu_irq_cbk(ald_cmu_security_t se); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group4 + * @{ + */ +/* Clock output configure */ +void ald_cmu_output_high_clock_config(ald_cmu_output_high_sel_t sel, + ald_cmu_output_high_div_t clk_div, type_func_t status); +void ald_cmu_output_low_clock_config(ald_cmu_output_low_sel_t sel, type_func_t status); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group5 + * @{ + */ +/* Peripheral Clock configure */ +void ald_cmu_buzz_config(ald_cmu_buzz_div_t clk_div, uint16_t dat, type_func_t status); +void ald_cmu_perh_clock_config(ald_cmu_perh_t perh, type_func_t status); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_CMU_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_conf.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_conf.h new file mode 100644 index 0000000000..b83f5204d3 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_conf.h @@ -0,0 +1,136 @@ +/********************************************************************************** + * + * @file ald_conf.h + * @brief Enable/Disable the peripheral module. + * + * @date + * @author + * @note + * Change Logs: + * Date Author Notes + * + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ +#ifndef __ALD_CONF_H__ +#define __ALD_CONF_H__ + +/* Exported Macros ----------------------------------------------------------- */ +/* Includes ------------------------------------------------------------------ */ +/* #define ALD_I2C */ +/* #define ALD_GPIO */ +/* #define ALD_TIMER */ +/* #define ALD_ADC */ +/* #define ALD_DMA */ +/* #define ALD_SPI */ +/* #define ALD_WDT */ +/* #define ALD_CRC */ +/* #define ALD_UART */ +#define ALD_CMU +/* #define ALD_DBGC */ +/* #define ALD_PIS */ +/* #define ALD_PMU */ +/* #define ALD_RMU */ +/* #define ALD_SYSCFG */ +/* #define ALD_TYPE */ +#define ALD_UTILS +#define ALD_USB + +#ifdef ALD_USB + #include "ald_usb.h" +#endif /* ALD_USB */ + +#ifdef ALD_I2C + #include "ald_i2c.h" +#endif /* ALD_I2C */ + +#ifdef ALD_GPIO + #include "ald_gpio.h" +#endif /* MD_GPIO */ + +#ifdef ALD_TIMER + #include "ald_timer.h" +#endif /* ALD_TIMER */ + +#ifdef ALD_ADC + #include "ald_adc.h" +#endif /* ALD_ADC */ + +#ifdef ALD_DMA + #include "ald_dma.h" +#endif /* ALD_DMA */ + +#ifdef ALD_SPI + #include "ald_spi.h" +#endif /* ALD_SPI */ +#ifdef ALD_WDT + #include "ald_wdt.h" +#endif /* ALD_WDT */ + +#ifdef ALD_CRC + #include "ald_crc.h" +#endif /* ALD_CRC */ + +#ifdef ALD_UART + #include "ald_uart.h" +#endif /* ALD_UART */ + +#ifdef ALD_CMU + #include "ald_cmu.h" +#endif /* ALD_CMU */ + +#ifdef ALD_DBGC + #include "ald_dbgc.h" +#endif /* ALD_DBGC */ + +#ifdef ALD_PIS + #include "ald_pis.h" +#endif /* ALD_PIS */ + +#ifdef ALD_PMU + #include "ald_pmu.h" +#endif /* ALD_PMU */ + +#ifdef ALD_RMU + #include "ald_rmu.h" +#endif /* ALD_RMU */ + +#ifdef ALD_SYSCFG + #include "ald_syscfg.h" +#endif /* ALD_SYSCFG */ + +#ifdef ALD_UTILS + #include "ald_utils.h" +#endif /* ALD_UTILS */ + +#ifdef ALD_TYPE + #include "type.h" +#endif /* ALD_TYPE */ + +#define TICK_INT_PRIORITY 3 + +/* Exported Types ------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ + +#endif /*__MD_CONF_H__*/ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ + diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_crc.c b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_crc.c new file mode 100644 index 0000000000..975a016369 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_crc.c @@ -0,0 +1,513 @@ +/** + ********************************************************************************* + * + * @file ald_crc.c + * @brief CRC module driver. + * + * @version V1.0 + * @date 06 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 06 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_crc.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/* Private function prototypes ----------------------------------------------- */ + +/** @defgroup CRC CRC + * @brief CRC module driver + * @{ + */ +/** @addtogroup CRC_Private_Functions CRC Private Functions + * @{ + */ +void ald_crc_reset(ald_crc_handle_t *hperh); +static void crc_dma_calculate_cplt(void *arg); +/** + * @} + */ + +/* Private Function ---------------------------------------------------------- */ + +/** @defgroup CRC_Public_Functions CRC Public Functions + * @{ + */ + +/** @defgroup CRC_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Initializes the CRC mode according to the specified parameters in + * the crc_handle_t and create the associated handle. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_init(ald_crc_handle_t *hperh) +{ + uint32_t tmp = 0U; + + if (hperh == NULL) + return ALD_ERROR; + + assert_param(IS_CRC(hperh->perh)); + assert_param(IS_CRC_MODE(hperh->init.mode)); + assert_param(IS_FUNC_STATE(hperh->init.chs_rev)); + assert_param(IS_FUNC_STATE(hperh->init.data_inv)); + assert_param(IS_FUNC_STATE(hperh->init.data_rev)); + assert_param(IS_FUNC_STATE(hperh->init.chs_inv)); + + ald_crc_reset(hperh); + __LOCK(hperh); + + ALD_CRC_ENABLE(hperh); + + tmp = hperh->perh->CR; + + tmp |= ((hperh->init.chs_rev << CRC_CR_CHSREV_POS) | (hperh->init.data_inv << CRC_CR_DATINV_POS) | + (hperh->init.chs_inv << CRC_CR_CHSINV_POS) | (hperh->init.mode << CRC_CR_MODE_POSS) | + (ALD_CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS) | (hperh->init.data_rev << CRC_CR_DATREV_POS) | + (0 << CRC_CR_BYTORD_POS)); + + hperh->perh->CR = tmp; + hperh->perh->SEED = hperh->init.seed; + ALD_CRC_RESET(hperh); + + hperh->state = ALD_CRC_STATE_READY; + + __UNLOCK(hperh); + return ALD_OK; +} + +/** + * @} + */ + +/** @defgroup CRC_Public_Functions_Group2 Calculate functions + * @brief Calculate functions + * @{ + */ + +/** + * @brief Calculate the crc value of data by byte. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param size: The size of data to be calculate + * @retval result, the result of a amount data + */ +uint32_t ald_crc_calculate(ald_crc_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + uint32_t i; + uint32_t ret; + + assert_param(IS_CRC(hperh->perh)); + + if (buf == NULL || size == 0) + return 0; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, ALD_CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); + hperh->state = ALD_CRC_STATE_BUSY; + + for (i = 0; i < size; i++) + *((volatile uint8_t *) & (hperh->perh->DATA)) = buf[i]; + + ret = CRC->CHECKSUM; + hperh->state = ALD_CRC_STATE_READY; + __UNLOCK(hperh); + + return ret; +} + +/** + * @brief Calculate the crc value of data by halfword. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param size: The size of data to be calculate,width is 2 bytes. + * @retval result, the result of a amount data + */ +uint32_t ald_crc_calculate_halfword(ald_crc_handle_t *hperh, uint16_t *buf, uint32_t size) +{ + uint32_t i; + uint32_t ret; + + assert_param(IS_CRC(hperh->perh)); + + if (buf == NULL || size == 0) + return 0; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, ALD_CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); + hperh->state = ALD_CRC_STATE_BUSY; + + for (i = 0; i < size; i++) + *((volatile uint16_t *) & (hperh->perh->DATA)) = buf[i]; + + ret = CRC->CHECKSUM; + hperh->state = ALD_CRC_STATE_READY; + __UNLOCK(hperh); + + return ret; +} + +/** + * @brief Calculate the crc value of data by word. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param size: The size of data to be calculate,width is 4 bytes + * @retval result, the result of a amount data + */ +uint32_t ald_crc_calculate_word(ald_crc_handle_t *hperh, uint32_t *buf, uint32_t size) +{ + uint32_t i; + uint32_t ret; + + assert_param(IS_CRC(hperh->perh)); + + if (buf == NULL || size == 0) + return 0; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, ALD_CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); + hperh->state = ALD_CRC_STATE_BUSY; + + for (i = 0; i < size; i++) + CRC->DATA = buf[i]; + + for (i = 0; i < 3; i++); + + ret = CRC->CHECKSUM; + hperh->state = ALD_CRC_STATE_READY; + __UNLOCK(hperh); + + return ret; +} + +/** + * @} + */ + +/** @defgroup CRC_Public_Functions_Group3 DMA operation functions + * @brief DMA operation functions + * @{ + */ + +/** + * @brief Calculate an amount of data used dma channel + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param res: Pointer to result + * @param size: Amount of data to be Calculate + * @param channel: DMA channel as CRC transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_calculate_by_dma(ald_crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel) +{ + if (hperh->state != ALD_CRC_STATE_READY) + return ALD_BUSY; + + if (buf == NULL || size == 0) + return ALD_ERROR; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, ALD_CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); + + hperh->state = ALD_CRC_STATE_BUSY; + + hperh->cal_buf = buf; + hperh->cal_res = res; + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA; + + hperh->hdma.cplt_tc_arg = (void *)hperh; + hperh->hdma.cplt_tc_cbk = &crc_dma_calculate_cplt; + + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.src_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdma.config.dst_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdma.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdma.config.msel = ALD_DMA_MSEL_CRC; + hperh->hdma.config.msigsel = ALD_DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&(hperh->hdma)); + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + + __UNLOCK(hperh); + ALD_CRC_DMA_ENABLE(hperh); + + return ALD_OK; +} + +/** + * @brief Calculate an amount of data used dma channel,data width is half-word. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to half_word data buffer + * @param res: Pointer to result + * @param size: Amount of half_word data to be Calculate + * @param channel: DMA channel as CRC transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_calculate_halfword_by_dma(ald_crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel) +{ + if (hperh->state != ALD_CRC_STATE_READY) + return ALD_BUSY; + + if (buf == NULL || size == 0) + return ALD_ERROR; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, ALD_CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); + + hperh->state = ALD_CRC_STATE_BUSY; + + hperh->cal_buf = (uint8_t *)buf; + hperh->cal_res = res; + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA; + + hperh->hdma.cplt_tc_arg = (void *)hperh; + hperh->hdma.cplt_tc_cbk = &crc_dma_calculate_cplt; + + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdma.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdma.config.msel = ALD_DMA_MSEL_CRC; + hperh->hdma.config.msigsel = ALD_DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&(hperh->hdma)); + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + + __UNLOCK(hperh); + ALD_CRC_DMA_ENABLE(hperh); + + return ALD_OK; +} + +/** + * @brief Calculate an amount of data used dma channel,data width is word. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to word data buffer + * @param res: Pointer to result + * @param size: Amount of word data to be Calculate + * @param channel: DMA channel as CRC transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_calculate_word_by_dma(ald_crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel) +{ + if (hperh->state != ALD_CRC_STATE_READY) + return ALD_BUSY; + + if (buf == NULL || size == 0) + return ALD_ERROR; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, ALD_CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); + + hperh->state = ALD_CRC_STATE_BUSY; + + hperh->cal_buf = (uint8_t *)buf; + hperh->cal_res = res; + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA; + + hperh->hdma.cplt_tc_arg = (void *)hperh; + hperh->hdma.cplt_tc_cbk = &crc_dma_calculate_cplt; + + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.src_data_width = ALD_DMA_DATA_SIZE_WORD; + hperh->hdma.config.dst_data_width = ALD_DMA_DATA_SIZE_WORD; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdma.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdma.config.msel = ALD_DMA_MSEL_CRC; + hperh->hdma.config.msigsel = ALD_DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&(hperh->hdma)); + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + + __UNLOCK(hperh); + ALD_CRC_DMA_ENABLE(hperh); + + return ALD_OK; +} + + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_dma_pause(ald_crc_handle_t *hperh) +{ + __LOCK(hperh); + ALD_CRC_DMA_DISABLE(hperh); + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_dma_resume(ald_crc_handle_t *hperh) +{ + __LOCK(hperh); + ALD_CRC_DMA_ENABLE(hperh); + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_dma_stop(ald_crc_handle_t *hperh) +{ + __LOCK(hperh); + ALD_CRC_DMA_DISABLE(hperh); + __UNLOCK(hperh); + + hperh->state = ALD_CRC_STATE_READY; + return ALD_OK; +} + +/** + * @} + */ + +/** @defgroup CRC_Public_Functions_Group4 Peripheral State and Errors functions + * @brief CRC State and Errors functions + * @{ + */ + +/** + * @brief Returns the CRC state. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval CRC state + */ +ald_crc_state_t ald_crc_get_state(ald_crc_handle_t *hperh) +{ + assert_param(IS_CRC(hperh->perh)); + + return hperh->state; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Functions CRC Private Functions + * @brief CRC Private functions + * @{ + */ + +/** + * @brief Reset the CRC peripheral. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval None + */ +void ald_crc_reset(ald_crc_handle_t *hperh) +{ + hperh->perh->DATA = 0x0; + hperh->perh->CR = 0x2; + hperh->perh->SEED = 0xFFFFFFFF; + + hperh->state = ALD_CRC_STATE_READY; + __UNLOCK(hperh); + return; +} + +/** + * @brief DMA CRC calculate process complete callback. + * @param arg: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval None + */ +static void crc_dma_calculate_cplt(void *arg) +{ + ald_crc_handle_t *hperh = (ald_crc_handle_t *)arg; + + *(hperh->cal_res) = CRC->CHECKSUM; + ALD_CRC_DMA_DISABLE(hperh); + + hperh->state = ALD_CRC_STATE_READY; + + if (hperh->cal_cplt_cbk) + hperh->cal_cplt_cbk(hperh); +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_crc.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_crc.h new file mode 100644 index 0000000000..415cf64a78 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_crc.h @@ -0,0 +1,230 @@ +/** + ********************************************************************************* + * + * @file ald_crc.h + * @brief Header file of CRC module driver. + * + * @version V1.0 + * @date 06 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 06 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_CRC_H__ +#define __ALD_CRC_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_utils.h" +#include "ald_dma.h" + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Constants -------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/** @defgroup CRC_Public_Types CRC Public Types + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** + * @brief CRC mode + */ +typedef enum +{ + ALD_CRC_MODE_CCITT = 0U, /**< CCITT */ + ALD_CRC_MODE_8 = 1U, /**< CRC8 */ + ALD_CRC_MODE_16 = 2U, /**< CRC16 */ + ALD_CRC_MODE_32 = 3U, /**< CRC32 */ +} ald_crc_mode_t; + +/** + * @brief CRC input length + */ +typedef enum +{ + ALD_CRC_LEN_AUTO = 0U, /**< Auto */ + ALD_CRC_DATASIZE_8 = 1U, /**< Byte */ + ALD_CRC_DATASIZE_16 = 2U, /**< Half word */ + ALD_CRC_DATASIZE_32 = 3U, /**< Word */ +} ald_crc_datasize_t; + +/** + * @brief CRC whether write error or no + */ +typedef enum +{ + ALD_CRC_WERR_NO = 0U, /**< No error */ + ALD_CRC_WERR_ERR = 1U, /**< Error */ +} ald_crc_werr_t; + +/** + * @brief CRC state structures definition + */ +typedef enum +{ + ALD_CRC_STATE_RESET = 0x0U, /**< Peripheral is not initialized */ + ALD_CRC_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ + ALD_CRC_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ + ALD_CRC_STATE_ERROR = 0x4U, /**< Error */ +} ald_crc_state_t; + +/** + * @brief CRC init structure definition + */ +typedef struct +{ + ald_crc_mode_t mode; /**< CRC mode */ + type_func_t data_rev; /**< CRC data reverse or no */ + type_func_t data_inv; /**< CRC data inverse or no */ + type_func_t chs_rev; /**< CRC check sum reverse or no */ + type_func_t chs_inv; /**< CRC check sum inverse or no */ + uint32_t seed; /**< CRC seed */ +} ald_crc_init_t; + +/** + * @brief CRC Handle Structure definition + */ +typedef struct ald_crc_handle_s +{ + CRC_TypeDef *perh; /**< Register base address */ + ald_crc_init_t init; /**< CRC required parameters */ + uint8_t *cal_buf; /**< The pointer of preparing buffer */ + uint32_t *cal_res; /**< The pointer of result */ + + ald_dma_handle_t hdma; /**< CRC DMA handle parameters */ + + lock_state_t lock; /**< Locking object */ + ald_crc_state_t state; /**< CRC operation state */ + + void (*cal_cplt_cbk)(struct ald_crc_handle_s *arg); /**< Calculate completed callback */ + void (*err_cplt_cbk)(struct ald_crc_handle_s *arg); /**< Calculate error callback */ +} ald_crc_handle_t; +/** + * @} + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** @defgroup CRC_Public_Macros CRC Public Macros + * @{ + */ +#define ALD_CRC_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK)) +#define ALD_CRC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK)) +#define ALD_CRC_RESET(handle) (SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK)) +#define ALD_CRC_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK)) +#define ALD_CRC_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK)) +#define ALD_CRC_CLEAR_ERROR_FLAG(handle) (SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK)) +/** + * @} + */ + +/** @defgroup CRC_Private_Macros CRC Private Macros + * @{ + */ +#define IS_CRC(x) ((x) == CRC) +#define IS_CRC_MODE(x) (((x) == ALD_CRC_MODE_CCITT) || \ + ((x) == ALD_CRC_MODE_8) || \ + ((x) == ALD_CRC_MODE_16) || \ + ((x) == ALD_CRC_MODE_32)) +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @addtogroup CRC_Public_Functions + * @{ + */ + +/** @addtogroup CRC_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_crc_init(ald_crc_handle_t *hperh); +void ald_crc_reset(ald_crc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup CRC_Public_Functions_Group2 + * @{ + */ +uint32_t ald_crc_calculate(ald_crc_handle_t *hperh, uint8_t *buf, uint32_t size); +uint32_t ald_crc_calculate_halfword(ald_crc_handle_t *hperh, uint16_t *buf, uint32_t size); +uint32_t ald_crc_calculate_word(ald_crc_handle_t *hperh, uint32_t *buf, uint32_t size); +/** + * @} + */ + + +/** @addtogroup CRC_Public_Functions_Group3 + * @{ + */ +ald_status_t ald_crc_calculate_by_dma(ald_crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel); +ald_status_t ald_crc_calculate_halfword_by_dma(ald_crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel); +ald_status_t ald_crc_calculate_word_by_dma(ald_crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel); +ald_status_t ald_crc_dma_pause(ald_crc_handle_t *hperh); +ald_status_t ald_crc_dma_resume(ald_crc_handle_t *hperh); +ald_status_t ald_crc_dma_stop(ald_crc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup CRC_Public_Functions_Group4 + * @{ + */ +ald_crc_state_t ald_crc_get_state(ald_crc_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_CRC_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_dma.c b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_dma.c new file mode 100644 index 0000000000..dc421653fc --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_dma.c @@ -0,0 +1,464 @@ +/** + ********************************************************************************* + * + * @file ald_dma.c + * @brief DMA module driver. + * + * @version V1.0 + * @date 17 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 17 Feb. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ + +#include +#include "ald_dma.h" + +/* Private Macros ------------------------------------------------------------ */ +#define IS_PERH_ADDR(x) (((uint32_t)(x))>=0x40000000) +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA module driver + * @{ + */ + +/* Private Variables --------------------------------------------------------- */ + +/** @defgroup DMA_Private_Variables DMA Private Variables + * @{ + */ +ald_dma_call_back_t dma_cbk[7]; +/** + * @}DMA_Private_Variables + */ + +/* Private Function ---------------------------------------------------------- */ + +/** @defgroup DMA_Private_Functions DMA Private Functions + * @{ + */ + +/** + * @brief Configure DMA channel using dma_config_t structure + * @param None + * @param config: Pointer to dma_config_t which contains + * DMA channel parameter. see @ref dma_config_t + * @retval None + */ +void ald_dma_config_base(ald_dma_config_t *config) +{ + assert_param(config->src != NULL); + assert_param(config->dst != NULL); + assert_param(IS_DMA_DATA_SIZE(config->size)); + assert_param(IS_DMA_DATASIZE_TYPE(config->src_data_width)); + assert_param(IS_DMA_DATASIZE_TYPE(config->dst_data_width)); + assert_param(IS_DMA_DATAINC_TYPE(config->src_inc)); + assert_param(IS_DMA_DATAINC_TYPE(config->dst_inc)); + assert_param(IS_DMA_ARBITERCONFIG_TYPE(config->R_power)); + assert_param(IS_DMA_PRIORITY_TYPE(config->priority)); + assert_param(IS_DMA_MSEL_TYPE(config->msel)); + assert_param(IS_DMA_MSIGSEL_TYPE(config->msigsel)); + assert_param(IS_DMA_CHANNEL(config->channel)); + + WRITE_REG(DMA->CHANNEL[config->channel].SAR, (uint32_t)config->src); + MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_SDWSEL_MSK, config->src_data_width << DMA_CON_SDWSEL_POSS); + MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_SINC_MSK, config->src_inc << DMA_CON_SINC_POS); + WRITE_REG(DMA->CHANNEL[config->channel].DAR, (uint32_t)config->dst); + MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_DDWSEL_MSK, config->dst_data_width << DMA_CON_DDWSEL_POSS); + MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_DINC_MSK, config->dst_inc << DMA_CON_DINC_POS); + MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_CIRC_MSK, config->circle_mode << DMA_CON_CIRC_POS); + MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_M2M_MSK, config->mem_to_mem << DMA_CON_M2M_POS); + MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_CHPRI_MSK, config->priority << DMA_CON_CHPRI_POSS); + MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_MAX_BURST_MSK, config->R_power << DMA_CON_MAX_BURST_POSS); + MODIFY_REG(DMA->CHANNEL[config->channel].NDT, DMA_NDT_TNDT_MSK, config->size << DMA_NDT_TNDT_POSS); + MODIFY_REG(DMA_MUX->CH_SELCON[config->channel], DMA_SELCON_MSEL_MSK, config->msel << DMA_SELCON_MSEL_POSS); + MODIFY_REG(DMA_MUX->CH_SELCON[config->channel], DMA_SELCON_MSIGSEL_MSK, config->msigsel << DMA_SELCON_MSIGSEL_POSS); + + if (IS_PERH_ADDR(config->dst)&&!IS_PERH_ADDR(config->src)) + { + SET_BIT(DMA->CHANNEL[config->channel].CON, DMA_CON_DIR_MSK); + } + else + { + CLEAR_BIT(DMA->CHANNEL[config->channel].CON, DMA_CON_DIR_MSK); + } + + return; +} + +/** + * @brief Configure DMA channel according to the specified parameter + * in the dma_handle_t structure. The DMA mode is basic. + * This mode is used to carry data from peripheral to memory + * or from memory to peripheral. + * @param hperh: Pointer to dma_handle_t structure that contains + * configuration information for specified DMA channel. + * @retval None + */ +void ald_dma_config_basic(ald_dma_handle_t *hperh) +{ + dma_cbk[hperh->config.channel].cplt_tc_cbk = hperh->cplt_tc_cbk; + dma_cbk[hperh->config.channel].cplt_ht_cbk = hperh->cplt_ht_cbk; + dma_cbk[hperh->config.channel].cplt_tc_arg = hperh->cplt_tc_arg; + dma_cbk[hperh->config.channel].cplt_ht_arg = hperh->cplt_ht_arg; + + ald_dma_clear_flag_status(hperh->config.channel, ALD_DMA_IT_FLAG_TC); + ald_dma_clear_flag_status(hperh->config.channel, ALD_DMA_IT_FLAG_HT); + ald_dma_config_base(&hperh->config); + ald_dma_channel_config(hperh->config.channel, ENABLE); + + return; +} + +/** + * @brief Configure DMA channel according to the specified parameter. + * The DMA mode is basic. This mode is used to carry data + * from peripheral to memory or negative direction. If user want + * use the dma easily, they can invoke this function. + * @param DMAx: Pointer to DMA peripheral + * @param src: Source data begin pointer + * @param dst: Destination data begin pointer + * @param size: The total number of DMA transfers that DMA cycle contains + * @param msel: Input source to DMA channel @ref dma_msel_t + * @param msigsel: Input signal to DMA channel @ref dma_msigsel_t + * @param channel: Channel index which will be used + * @param cbk: DMA complete callback function + * + * @retval None + * + */ +void ald_dma_config_basic_easy(void *src, void *dst, uint16_t size, ald_dma_msel_t msel, + ald_dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)) +{ + ald_dma_handle_t hperh; + + ald_dma_config_struct(&hperh.config); + + if (((uint32_t)src) >= 0x40000000) + hperh.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + + if (((uint32_t)dst) >= 0x40000000) + hperh.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + + hperh.config.src = src; + hperh.config.dst = dst; + hperh.config.size = size; + hperh.config.msel = msel; + hperh.config.msigsel = msigsel; + hperh.config.channel = channel; + + hperh.perh = DMA; + hperh.cplt_tc_cbk = cbk; + hperh.cplt_tc_arg = NULL; + hperh.cplt_ht_cbk = NULL; + + ald_dma_clear_flag_status(channel, ALD_DMA_IT_FLAG_TC); + ald_dma_clear_flag_status(channel, ALD_DMA_IT_FLAG_HT); + ald_dma_config_basic(&hperh); + + return; +} + +/** + * @brief Handle DMA interrupt + * @retval None + */ +void ald_dma_irq_handler(void) +{ + uint8_t i; + + for (i = 0; i < ALD_DMA_CH_COUNT; ++i) + { + if (READ_BIT(DMA->IFM, 1U << (2U * i))) + { + if (dma_cbk[i].cplt_tc_cbk != NULL) + dma_cbk[i].cplt_tc_cbk(dma_cbk[i].cplt_tc_arg); + + DMA->ICR = 1U << (2U * i); + } + + if (READ_BIT(DMA->IFM, 1U << (2U * i + 1U))) + { + if (dma_cbk[i].cplt_ht_cbk != NULL) + dma_cbk[i].cplt_ht_cbk(dma_cbk[i].cplt_ht_arg); + + DMA->ICR = 1U << (2U * i + 1U); + } + } + + return; +} +/** + * @}DMA_Private_Functions + */ + +/** @defgroup DMA_Public_Functions DMA Public Functions + * @{ + */ + +/** @defgroup DMA_Public_Functions_Group1 Initialization functions + * @brief Initialization functions + * + * @{ + */ + +/** + * @brief Reset the DMA register + * @param None + * @retval None + */ +void ald_dma_reset(void) +{ + uint32_t i; + + WRITE_REG(DMA->IDR, 0x3FFF); + WRITE_REG(DMA->ICR, 0x3FFF); + + for (i = 0; i < DMA_CHANNELS; ++i) + { + CLEAR_BIT(DMA->CHANNEL[i].CON, DMA_CON_CHEN_MSK); + WRITE_REG(DMA->CHANNEL[i].CON, 0x0); + WRITE_REG(DMA->CHANNEL[i].SAR, 0x0); + WRITE_REG(DMA->CHANNEL[i].DAR, 0x0); + WRITE_REG(DMA->CHANNEL[i].NDT, 0x0); + WRITE_REG(DMA_MUX->CH_SELCON[i], 0x0); + } + + return; +} + +/** + * @brief DMA module initialization, this function + * is invoked by ald_cmu_init(). + * @param None + * @retval None + */ +void ald_dma_init(void) +{ + memset(dma_cbk, 0x0, sizeof(dma_cbk)); + + ald_dma_reset(); + ald_mcu_irq_config(DMA_IRQn, 4, ENABLE); + + return; +} + +/** + * @brief Configure dma_config_t structure using default parameter. + * User can invoked this function, before configure dma_config_t + * @param config: Pointer to dma_config_t structure, see @ref dma_config_t + * @retval None + */ +void ald_dma_config_struct(ald_dma_config_t *config) +{ + config->size = 0; + config->src_data_width = ALD_DMA_DATA_SIZE_BYTE; + config->dst_data_width = ALD_DMA_DATA_SIZE_BYTE; + config->src_inc = ALD_DMA_DATA_INC_DISABLE; + config->dst_inc = ALD_DMA_DATA_INC_DISABLE; + config->R_power = ALD_DMA_R_POWER_1; + config->priority = ALD_DMA_LOW_PRIORITY; + config->mem_to_mem = DISABLE; + config->circle_mode = DISABLE; + config->msel = ALD_DMA_MSEL_NONE; + config->msigsel = ALD_DMA_MSIGSEL_NONE; + config->channel = ALD_DMA_CH_0; + + return; +} + +/** + * @}DMA_Public_Functions_Group1 + */ + +/** @defgroup DMA_Public_Functions_Group2 DMA Control functions + * @brief DMA control functions + * + * @verbatim + =================================================================== + + #### DMA control functions #### + + =================================================================== + [..] + This subsection provides some functions allowing to control DMA: + (+) ald_dma_channel_config(): Control DMA channel ENABLE/DISABLE. + (+) ald_dma_interrupt_config(): Control DMA channel interrupt ENABLE or + DISABLE. + (+) ald_dma_get_it_status(): Check whether the specified channel + interrupt is SET or RESET. + (+) ald_dma_get_flag_status(): Check whether the specified channel + flag is SET or RESET. + (+) ald_dma_clear_flag_status(): Clear the specified channel + pending flag + + @endverbatim + * @{ + */ + +/** + * @brief Configure channel enable or disable. It will unbind descriptor with + * channel, when channel has been disable. + * @param None + * @param channel: channel index + * @param state: status of channel: + * @arg ENABLE: Enable the channel + * @arg DISABLE: Disable the channel + * @retval None + */ +void ald_dma_channel_config(uint8_t channel, type_func_t state) +{ + assert_param(IS_DMA_CHANNEL(channel)); + assert_param(IS_FUNC_STATE(state)); + + if (state) + { + SET_BIT(DMA->CHANNEL[channel].CON, DMA_CON_CHEN_MSK); + } + else + { + CLEAR_BIT(DMA->CHANNEL[channel].CON, DMA_CON_CHEN_MSK); + WRITE_REG(DMA->CHANNEL[channel].CON, 0x0); + WRITE_REG(DMA->CHANNEL[channel].SAR, 0x0); + WRITE_REG(DMA->CHANNEL[channel].DAR, 0x0); + WRITE_REG(DMA->CHANNEL[channel].NDT, 0x0); + WRITE_REG(DMA_MUX->CH_SELCON[channel], 0x0); + } + + return; +} + +/** + * @brief Configure the interrupt enable or disable + * @param channel: Channel index. + * @arg 0~6: Channel index + * @param it: IT type. + * @arg DMA_IT_FLAG_TC + * @arg DMA_IT_FLAG_HT + * @param state: status of channel: + * @arg ENABLE: Enable the channel + * @arg DISABLE: Disable the channel + * + * @retval None + */ +void ald_dma_interrupt_config(uint8_t channel, ald_dma_it_flag_t it, type_func_t state) +{ + assert_param(IS_DMA_CHANNEL(channel)); + assert_param(IS_DMA_IT_TYPE(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state) + SET_BIT(DMA->IER, 1U << (channel * 2U + it)); + else + SET_BIT(DMA->IDR, 1U << (channel * 2U + it)); + + return; +} + +/** + * @brief Check whether the specified channel interrupt + * is set or reset + * @param it: IT type. + * @arg DMA_IT_FLAG_TC + * @arg DMA_IT_FLAG_HT + * @param channel: Channel index + * @arg 0~6: Channel index + * @retval Status: + * - SET: Channel interrupt is set + * - RESET: Channel interrupt is reset + */ +it_status_t ald_dma_get_it_status(uint8_t channel, ald_dma_it_flag_t it) +{ + assert_param(IS_DMA_CHANNEL(channel)); + assert_param(IS_DMA_IT_TYPE(it)); + + if (READ_BIT(DMA->IVS, 1 << (channel * 2U + it))) + return SET; + + return RESET; +} + +/** + * @brief Check whether the specified channel flag + * is set or reset + * @param channel: Channel index + * @arg 0~6: Channel index + * @param it: IT type. + * @arg DMA_IT_FLAG_TC + * @arg DMA_IT_FLAG_HT + * @retval Status: + * - SET: Channel flag is set + * - RESET: Channel flag is reset + */ +flag_status_t ald_dma_get_flag_status(uint8_t channel, ald_dma_it_flag_t it) +{ + assert_param(IS_DMA_CHANNEL(channel)); + assert_param(IS_DMA_IT_TYPE(it)); + + if (READ_BIT(DMA->IFM, 1 << (channel * 2U + it))) + return SET; + + return RESET; +} + +/** + * @brief Clear the specified channel pending flag + * @param channel: Channel index + * @arg 0~6: Channel index + * @param it: IT type. + * @arg DMA_IT_FLAG_TC + * @arg DMA_IT_FLAG_HT + * @retval None + */ +void ald_dma_clear_flag_status(uint8_t channel, ald_dma_it_flag_t it) +{ + assert_param(IS_DMA_CHANNEL(channel)); + assert_param(IS_DMA_IT_TYPE(it)); + + SET_BIT(DMA->ICR, 1U << (channel * 2U + it)); + return; +} + +/** + * @}DMA_Public_Functions_Group2 + */ + +/** + * @}DMA_Public_Functions + */ + +/** + * @}DMA + */ + +/** + * @}ES32VF2264_ALD + */ \ No newline at end of file diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_dma.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_dma.h new file mode 100644 index 0000000000..6e63f8d3f9 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_dma.h @@ -0,0 +1,367 @@ +/** + ********************************************************************************* + * + * @file ald_dma.h + * @brief DMA module Library. + * + * @version V1.0 + * @date 16 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 16 Feb. 2023 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_DMA_H__ +#define __ALD_DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_utils.h" + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Constants -------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** + * @defgroup DMA_Public_Macros DMA Public Macros + * @{ + */ +#define ALD_DMA_CH_COUNT 7U +/** + * @} + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** + * @defgroup DMA_Public_Types DMA Public Types + * @{ + */ + +/** + * @brief Input source to DMA channel + */ +typedef enum +{ + ALD_DMA_MSEL_NONE = 0x0U, /**< NONE */ + ALD_DMA_MSEL_GPIO = 0x1U, /**< GPIO */ + ALD_DMA_MSEL_ADC = 0x2U, /**< ADC */ + ALD_DMA_MSEL_CRC = 0x3U, /**< CRC */ + ALD_DMA_MSEL_EUART0 = 0x4U, /**< EUART0 */ + ALD_DMA_MSEL_EUART1 = 0x5U, /**< EUART1 */ + ALD_DMA_MSEL_CUART0 = 0x6U, /**< CUART0 */ + ALD_DMA_MSEL_CUART1 = 0x7U, /**< CUART1 */ + ALD_DMA_MSEL_CUART2 = 0x8U, /**< CUART2 */ + ALD_DMA_MSEL_SPI0 = 0x9U, /**< SPI0 */ + ALD_DMA_MSEL_SPI1 = 0xAU, /**< SPI1 */ + ALD_DMA_MSEL_I2C0 = 0xBU, /**< I2C0 */ + ALD_DMA_MSEL_I2C1 = 0xCU, /**< I2C1 */ + ALD_DMA_MSEL_AD16C4T = 0xDU, /**< AD16C4T */ + ALD_DMA_MSEL_GP16C4T0 = 0xEU, /**< GP16C4T0 */ + ALD_DMA_MSEL_GP16C4T1 = 0xFU, /**< GP16C4T1 */ + ALD_DMA_MSEL_GP16C4T2 = 0x10U, /**< GP16C4T2 */ + ALD_DMA_MSEL_PIS = 0x11U, /**< PIS */ + ALD_DMA_MSEL_BS16T = 0x12U, /**< BS16T */ +} ald_dma_msel_t; + +/** + * @brief Input signal to DMA channel + */ +typedef enum +{ + ALD_DMA_MSIGSEL_NONE = 0x0U, /**< NONE */ + ALD_DMA_MSIGSEL_EXTI_0 = 0x0U, /**< External interrupt 0 */ + ALD_DMA_MSIGSEL_EXTI_1 = 0x1U, /**< External interrupt 1 */ + ALD_DMA_MSIGSEL_EXTI_2 = 0x2U, /**< External interrupt 2 */ + ALD_DMA_MSIGSEL_EXTI_3 = 0x3U, /**< External interrupt 3 */ + ALD_DMA_MSIGSEL_EXTI_4 = 0x4U, /**< External interrupt 4 */ + ALD_DMA_MSIGSEL_EXTI_5 = 0x5U, /**< External interrupt 5 */ + ALD_DMA_MSIGSEL_EXTI_6 = 0x6U, /**< External interrupt 6 */ + ALD_DMA_MSIGSEL_EXTI_7 = 0x7U, /**< External interrupt 7 */ + ALD_DMA_MSIGSEL_EXTI_8 = 0x8U, /**< External interrupt 8 */ + ALD_DMA_MSIGSEL_EXTI_9 = 0x9U, /**< External interrupt 9 */ + ALD_DMA_MSIGSEL_EXTI_10 = 0xAU, /**< External interrupt 10 */ + ALD_DMA_MSIGSEL_EXTI_11 = 0xBU, /**< External interrupt 11 */ + ALD_DMA_MSIGSEL_EXTI_12 = 0xCU, /**< External interrupt 12 */ + ALD_DMA_MSIGSEL_EXTI_13 = 0xDU, /**< External interrupt 13 */ + ALD_DMA_MSIGSEL_EXTI_14 = 0xEU, /**< External interrupt 14 */ + ALD_DMA_MSIGSEL_EXTI_15 = 0xFU, /**< External interrupt 15 */ + ALD_DMA_MSIGSEL_ADC = 0x0U, /**< ADC mode */ + ALD_DMA_MSIGSEL_CRC = 0x0U, /**< CRC */ + ALD_DMA_MSIGSEL_UART_RNR = 0x0U, /**< UART reveive */ + ALD_DMA_MSIGSEL_UART_TXEMPTY = 0x1U, /**< UART transmit */ + ALD_DMA_MSIGSEL_SPI_RNR = 0x0U, /**< SPI receive */ + ALD_DMA_MSIGSEL_SPI_TXEMPTY = 0x1U, /**< SPI transmit */ + ALD_DMA_MSIGSEL_I2C_RNR = 0x0U, /**< I2C receive */ + ALD_DMA_MSIGSEL_I2C_TXEMPTY = 0x1U, /**< I2C transmit */ + ALD_DMA_MSIGSEL_TIMER_CH1 = 0x0U, /**< TIM channal 1 */ + ALD_DMA_MSIGSEL_TIMER_CH2 = 0x1U, /**< TIM channal 2 */ + ALD_DMA_MSIGSEL_TIMER_CH3 = 0x2U, /**< TIM channal 3 */ + ALD_DMA_MSIGSEL_TIMER_CH4 = 0x3U, /**< TIM channal 4 */ + ALD_DMA_MSIGSEL_TIMER_TRI = 0x4U, /**< TIM trigger */ + ALD_DMA_MSIGSEL_TIMER_COMP = 0x5U, /**< TIM compare */ + ALD_DMA_MSIGSEL_TIMER_UPDATE = 0x6U, /**< TIM update */ + ALD_DMA_MSIGSEL_PIS_CH0 = 0x0U, /**< PIS channal 0 */ + ALD_DMA_MSIGSEL_PIS_CH1 = 0x1U, /**< PIS channal 1 */ + ALD_DMA_MSIGSEL_PIS_CH2 = 0x2U, /**< PIS channal 2 */ + ALD_DMA_MSIGSEL_PIS_CH3 = 0x3U, /**< PIS channal 3 */ + ALD_DMA_MSIGSEL_PIS_CH4 = 0x4U, /**< PIS channal 4 */ + ALD_DMA_MSIGSEL_PIS_CH5 = 0x5U, /**< PIS channal 5 */ + ALD_DMA_MSIGSEL_PIS_CH6 = 0x6U, /**< PIS channal 6 */ + ALD_DMA_MSIGSEL_PIS_CH7 = 0x7U, /**< PIS channal 7 */ + ALD_DMA_MSIGSEL_BSTIM = 0x0U, /**< BSTIM */ +} ald_dma_msigsel_t; + +/** + * @brief Priority of DMA channel + */ +typedef enum +{ + ALD_DMA_LOW_PRIORITY = 0, + ALD_DMA_MEDIUM_PRIORITY = 1, + ALD_DMA_HIGH_PRIORUTY = 2, + ALD_DMA_HIGHEST_PRIORITY = 3 +} ald_dma_priority_t; + +/** + * @brief data increment + */ +typedef enum +{ + ALD_DMA_DATA_INC_DISABLE = 0x0U, + ALD_DMA_DATA_INC_ENABLE = 0x1U, +} ald_dma_data_inc_t; + +/** + * @brief Data size + */ +typedef enum +{ + ALD_DMA_DATA_SIZE_BYTE = 0x0U, /**< Byte */ + ALD_DMA_DATA_SIZE_HALFWORD = 0x1U, /**< Halfword */ + ALD_DMA_DATA_SIZE_WORD = 0x2U, /**< Word */ +} ald_dma_data_size_t; + +/** + * @brief Interrupt flag trigger mode + */ +typedef enum +{ + ALD_DMA_IT_FLAG_TC = 0x0U, /**< DMA transfer complete interrupt */ + ALD_DMA_IT_FLAG_HT = 0x1U, /**< DMA transfer half complete interrupt */ +} ald_dma_it_flag_t; + +/** + * @brief Control how many DMA transfers can occur + * before the controller re-arbitrates + */ +typedef enum +{ + ALD_DMA_R_POWER_1 = 0x0U, /**< Arbitrates after each DMA transfer */ + ALD_DMA_R_POWER_2 = 0x1U, /**< Arbitrates after 2 DMA transfer */ + ALD_DMA_R_POWER_4 = 0x2U, /**< Arbitrates after 4 DMA transfer */ + ALD_DMA_R_POWER_8 = 0x3U, /**< Arbitrates after 8 DMA transfer */ + ALD_DMA_R_POWER_16 = 0x4U, /**< Arbitrates after 16 DMA transfer */ + ALD_DMA_R_POWER_32 = 0x5U, /**< Arbitrates after 32 DMA transfer */ + ALD_DMA_R_POWER_64 = 0x6U, /**< Arbitrates after 64 DMA transfer */ + ALD_DMA_R_POWER_128 = 0x7U, /**< Arbitrates after 128 DMA transfer */ + ALD_DMA_R_POWER_256 = 0x8U, /**< Arbitrates after 256 DMA transfer */ + ALD_DMA_R_POWER_512 = 0x9U, /**< Arbitrates after 512 DMA transfer */ + ALD_DMA_R_POWER_1024 = 0xAU, /**< Arbitrates after 1024 DMA transfer */ +} ald_dma_arbiter_config_t; + +/* Exported Types ------------------------------------------------------------ */ + +/** + * @brief Callback function pointer and param + */ +typedef struct +{ + void (*cplt_tc_cbk)(void *arg); /**< DMA transfers complete callback */ + void (*cplt_ht_cbk)(void *arg); /**< DMA transfers half complete callback */ + void *cplt_tc_arg; /**< The parameter of cplt_tc_cbk() */ + void *cplt_ht_arg; /**< The parameter of cplt_ht_cbk() */ +} ald_dma_call_back_t; + +/** + * @brief DMA channal configure structure + */ +typedef struct +{ + void *src; /**< Source data begin pointer */ + void *dst; /**< Destination data begin pointer */ + uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */ + ald_dma_data_size_t src_data_width; /**< Source data width */ + ald_dma_data_size_t dst_data_width; /**< Dest data width */ + ald_dma_data_inc_t src_inc; /**< Source increment type */ + ald_dma_data_inc_t dst_inc; /**< Destination increment type */ + ald_dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates */ + ald_dma_priority_t priority; /**< High priority or default priority */ + TypeFunc mem_to_mem; /**< Enable/disable memory to memory mode */ + TypeFunc circle_mode; /**< Enable/disable circular mode */ + ald_dma_msel_t msel; /**< Input source to DMA channel */ + ald_dma_msigsel_t msigsel; /**< Input signal to DMA channel */ + uint8_t channel; /**< Channel index */ +} ald_dma_config_t; + +/* Exported Macros ----------------------------------------------------------- */ + +/** @defgroup ALD_DMA_Public_Constants DMA Public Constants + * @{ + */ +/** + * brief ALD_DMA_CHANNEL DMA channel + */ +#define ALD_DMA_CH_0 0x0U /**< Channel 0 */ +#define ALD_DMA_CH_1 0x1U /**< Channel 1 */ +#define ALD_DMA_CH_2 0x2U /**< Channel 2 */ +#define ALD_DMA_CH_3 0x3U /**< Channel 3 */ +#define ALD_DMA_CH_4 0x4U /**< Channel 4 */ +#define ALD_DMA_CH_5 0x5U /**< Channel 5 */ +#define ALD_DMA_CH_6 0x6U /**< Channel 6 */ +/** + * @} + */ + +/** + * @brief DMA handle structure definition + */ +typedef struct +{ + DMA_TypeDef *perh; /**< DMA registers base address */ + ald_dma_config_t config; /**< Channel configure structure. @ref dma_config_t */ + void (*cplt_tc_cbk)(void *arg); /**< DMA transfers complete callback */ + void (*cplt_ht_cbk)(void *arg); /**< DMA transfers half complete callback */ + void *cplt_tc_arg; /**< The parameter of cplt_tc_cbk() */ + void *cplt_ht_arg; /**< The parameter of cplt_ht_cbk() */ +} ald_dma_handle_t; + +/** + * @} + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** + * @defgroup DMA_Private_Macros DMA Private Macros + * @{ + */ +#define IS_DMA_MSEL_TYPE(x) ((x) <= ALD_DMA_MSEL_BS16T) +#define IS_DMA_MSIGSEL_TYPE(x) ((x) <= ALD_DMA_MSIGSEL_EXTI_15) +#define IS_DMA_DATAINC_TYPE(x) (((x) == ALD_DMA_DATA_INC_DISABLE) || \ + ((x) == ALD_DMA_DATA_INC_ENABLE)) +#define IS_DMA_DATASIZE_TYPE(x) (((x) == ALD_DMA_DATA_SIZE_BYTE) || \ + ((x) == ALD_DMA_DATA_SIZE_HALFWORD) || \ + ((x) == ALD_DMA_DATA_SIZE_WORD)) +#define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == ALD_DMA_R_POWER_1) || \ + ((x) == ALD_DMA_R_POWER_2) || \ + ((x) == ALD_DMA_R_POWER_4) || \ + ((x) == ALD_DMA_R_POWER_8) || \ + ((x) == ALD_DMA_R_POWER_16) || \ + ((x) == ALD_DMA_R_POWER_32) || \ + ((x) == ALD_DMA_R_POWER_64) || \ + ((x) == ALD_DMA_R_POWER_128) || \ + ((x) == ALD_DMA_R_POWER_256) || \ + ((x) == ALD_DMA_R_POWER_512) || \ + ((x) == ALD_DMA_R_POWER_1024)) +#define IS_DMA_PRIORITY_TYPE(x) (((x) == ALD_DMA_LOW_PRIORITY) || \ + ((x) == ALD_DMA_MEDIUM_PRIORITY) || \ + ((x) == ALD_DMA_HIGH_PRIORUTY) || \ + ((x) == ALD_DMA_HIGHEST_PRIORITY)) +#define IS_DMA_IT_TYPE(x) (((x) == ALD_DMA_IT_FLAG_TC) || \ + ((x) == ALD_DMA_IT_FLAG_HT)) +#define IS_DMA(x) ((x) == DMA) +#define IS_DMA_CHANNEL(x) ((x) <= ALD_DMA_CH_6) +#define IS_DMA_DATA_SIZE(x) ((x) <= 65535) +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** + * @addtogroup DMA_Public_Functions + * @{ + */ + +/** @addtogroup DMA_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +extern void ald_dma_config_base(ald_dma_config_t *config); +extern void ald_dma_config_basic(ald_dma_handle_t *hperh); +extern void ald_dma_config_basic_easy(void *src, void *dst, uint16_t size, ald_dma_msel_t msel, + ald_dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); +extern void ald_dma_irq_handler(void); +extern void ald_dma_reset(void); +extern void ald_dma_init(void); +extern void ald_dma_config_struct(ald_dma_config_t *p); +/** + * @} + */ + + +/** @addtogroup DMA_Public_Functions_Group2 + * @{ + */ +/* DMA control functions */ +extern void ald_dma_channel_config(uint8_t channel, type_func_t state); +void ald_dma_interrupt_config(uint8_t channel, ald_dma_it_flag_t it, type_func_t state); +extern it_status_t ald_dma_get_it_status(uint8_t channel, ald_dma_it_flag_t it); +extern flag_status_t ald_dma_get_flag_status(uint8_t channel, ald_dma_it_flag_t it); +extern void ald_dma_clear_flag_status(uint8_t channel, ald_dma_it_flag_t it); +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /*__ALD_DMA_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_gpio.c b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_gpio.c new file mode 100644 index 0000000000..cbf7a42925 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_gpio.c @@ -0,0 +1,681 @@ +/** + ********************************************************************************* + * + * @file ald_gpio.c + * @brief GPIO module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization functions + * + IO operation functions + * + Control functions + * + * @version V1.0 + * @date 30 Jan. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 30 Jan. 2023 Lisq The first version + * 1 Dec 2023 Zhuxf Improve the timing of md_gpio_clear_flag + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + * @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each + port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software + in several modes: + (+) Input mode + (+) Analog mode + (+) Output mode + (+) External interrupt/event lines + + [..] + During and just after reset, the external interrupt lines are not active and + the I/O ports are configured Analog mode. + + [..] + All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + [..] + In Output mode, each IO can be configured on open-drain or push-pull + type and the Output driver can be selected depending on ODRV register. + + [..] + In Input mode, each IO can select filter function. + + [..] + Each IO can select TTL or SMIT type. + + [..] + Each IO have up to eight functions, user can configure the functions depend + on the user's environment. + + [..] + Each IO can be locked. Once locked, uesr can only change the output data. + Only when the CPU reset to unlock the GPIO port. + + [..] + All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + [..] + Each input line can be independently configured to select the type (event or interrupt) and + the corresponding trigger event (rising or falling). Each line can also masked + independently. A pending register maintains the status line of the interrupt requests. + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO clock. + + (#) Configure the GPIO pin(s) using ald_gpio_init(). + (++) Configure the IO mode using "mode" member from gpio_init_t structure + (++) Activate Pull-up, Pull-down resistor using "pupd" member from gpio_init_t + structure. + (++) In Output mode, configured on open-drain or push-pull using "odos" + member from gpio_init_t structure. + (++) In Output mode, configured output driver using "odrv" member + from gpio_init_t structure. + (++) In Input mode, configured filter function using "flt" member + from gpio_init_t structure. + (++) Configured type using "type" member from gpio_init_t structure. + (++) Configured functions using "func" member from gpio_init_t structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + + (#) Configure the GPIO pin(s) using ald_gpio_init_default(). + (++) Configure GPIO pin using default param: + init.mode = ALD_GPIO_MODE_OUTPUT; + init.odos = ALD_GPIO_PUSH_PULL; + init.pupd = ALD_GPIO_PUSH_UP; + init.odrv = ALD_GPIO_OUT_DRIVE_NORMAL; + init.flt = ALD_GPIO_FILTER_DISABLE; + init.type = ALD_GPIO_TYPE_CMOS; + init.func = ALD_GPIO_FUNC_1; + + (#) In case of external interrupt/event mode selection, user need invoke + ald_gpio_exti_init() to configure some param. And then invoke + ald_gpio_exti_interrupt_config() to enable/disable external interrupt/event. + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using NVIC_SetPriority() and enable it using + NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use GPIO_read_pin(). + + (#) To set/reset the level of a pin configured in output mode use + ald_gpio_write_pin()/ald_gpio_toggle_pin(). + + (#) To lock pin configuration until next reset use ald_gpio_lock_pin(). + + (#) Configure external interrupt mode and enable/disable using + ald_gpio_exti_interrupt_config(). + + (#) Get external interrupt flag status using ald_gpio_exti_get_flag_status(). + + (#) Clear pending external interrupt flag status using + ald_gpio_exti_clear_flag_status(). + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_gpio.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO module driver + * @{ + */ + +/** @defgroup GPIO_Public_Functions GPIO Public Functions + * @{ + */ + +/** @defgroup GPIO_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the GPIOs or external + interrupt to be ready for use. + + @endverbatim + * @{ + */ + +/** + * @brief Initialize the GPIOx peripheral according to the specified + * parameters in the gpio_init_t. + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @param pin: The pin which need to initialize. + * @param init: Pointer to a gpio_init_t structure that can contains + * the configuration information for the specified parameters. + * @retval None + */ +void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, ald_gpio_init_t *init) +{ + uint32_t i, pos, mask, tmp; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_GPIO_MODE(init->mode)); + assert_param(IS_GPIO_OD(init->od)); + assert_param(IS_GPIO_PUPD(init->pupd)); + assert_param(IS_GPIO_ODRV(init->odrv)); + assert_param(IS_GPIO_FLT(init->flt)); + assert_param(IS_GPIO_TYPE(init->type)); + assert_param(IS_GPIO_FUNC(init->func)); + + for (i = 0; i < 16; ++i) + { + if (((pin >> i) & 0x1) == 0) + continue; + + /* Get position and 1-bit mask */ + pos = i; + mask = 0x1 << pos; + + /* Set PIN filter enable or disable */ + tmp = READ_REG(GPIOx->FLT); + tmp &= ~mask; + tmp |= (init->flt << pos); + WRITE_REG(GPIOx->FLT, tmp); + + /* Set PIN type ttl or smit */ + tmp = READ_REG(GPIOx->TYPE); + tmp &= ~mask; + tmp |= (init->type << pos); + WRITE_REG(GPIOx->TYPE, tmp); + + /* Configure PIN function */ + pos = i < 8 ? (i << 2) : ((i - 8) << 2); + mask = 0xF << pos; + tmp = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1); + tmp &= ~mask; + tmp |= (init->func << pos); + i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp); + + /* Get position and 2-bits mask */ + pos = i << 1; + mask = 0x3 << pos; + + /* Set PIN mode */ + tmp = READ_REG(GPIOx->MODE); + tmp &= ~mask; + tmp |= (init->mode << pos); + WRITE_REG(GPIOx->MODE, tmp); + + /* Set PIN open-drain or push-pull */ + tmp = READ_REG(GPIOx->OD); + tmp &= ~mask; + tmp |= (init->od << pos); + WRITE_REG(GPIOx->OD, tmp); + + /* Set PIN push-up or/and push-down */ + tmp = READ_REG(GPIOx->PUPD); + tmp &= ~mask; + tmp |= (init->pupd << pos); + WRITE_REG(GPIOx->PUPD, tmp); + + /* Set PIN output driver */ + tmp = READ_REG(GPIOx->ODRV); + tmp &= ~mask; + tmp |= (init->odrv << pos); + WRITE_REG(GPIOx->ODRV, tmp); + } + + return; +} + +/** + * @brief Initialize the GPIOx peripheral using the default parameters. + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @param pin: The pin which need to initialize. + * @retval None + */ +void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + ald_gpio_init_t init; + + /* Fill GPIO_init_t structure with default parameter */ + init.mode = ALD_GPIO_MODE_OUTPUT; + init.od = ALD_GPIO_PUSH_PULL; + init.pupd = ALD_GPIO_PUSH_UP; + init.odrv = ALD_GPIO_OUT_DRIVE_NORMAL; + init.flt = ALD_GPIO_FILTER_DISABLE; + init.type = ALD_GPIO_TYPE_CMOS; + init.func = ALD_GPIO_FUNC_1; + + ald_gpio_init(GPIOx, pin, &init); + + return; +} + +/** + * @brief Sets GPIO function to default(func0). + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @retval None + */ +void ald_gpio_func_default(GPIO_TypeDef *GPIOx) +{ + WRITE_REG(GPIOx->FUNC0, 0x00); + WRITE_REG(GPIOx->FUNC1, 0x00); + + return; +} + +/** + * @brief Initialize the external interrupt according to the specified + * parameters in the exti_init_t. + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @param pin: The pin which need to initialize. + * @param init: Pointer to a exti_init_t structure that can contains + * the configuration information for the specified parameters. + * @retval None + */ +void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, ald_exti_init_t *init) +{ + uint8_t i; + uint8_t port; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_FUNC_STATE(init->filter)); + + /* Get GPIO port */ + if (GPIOx == GPIOA) + port = 0x0; + else if (GPIOx == GPIOB) + port = 0x1; + else if (GPIOx == GPIOC) + port = 2; + else if (GPIOx == GPIOD) + port = 3; + else + port = 0; + + /* Get Pin index */ + for (i = 0; i < 16; ++i) + { + if (((pin >> i) & 0x1) == 0x1) + break; + } + + /* Select external interrupt line */ + if (i <= 7) + { + EXTI->EXTIPSR0 &= ~(0xFU << (i * 4)); + EXTI->EXTIPSR0 |= (port << (i * 4)); + } + else + { + i -= 8; + EXTI->EXTIPSR1 &= ~(0xFU << (i * 4)); + EXTI->EXTIPSR1 |= (port << (i * 4)); + } + + /* Configure filter parameter */ + if (init->filter == ENABLE) + { + SET_BIT(EXTI->EXTIFLTCR, pin); + MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTSEL_MSK, init->filter_time << GPIO_EXTIFLTCR_FLTSEL_POSS); + } + else + { + CLEAR_BIT(EXTI->EXTIFLTCR, pin); + } + + return; +} +/** + * @} + */ + +/** @defgroup GPIO_Public_Functions_Group2 IO operation functions + * @brief GPIO Read and Write + * + @verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the GPIOs. + + @endverbatim + * @{ + */ + +/** + * @brief Read the specified input port pin. + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @param pin: Specifies the pin to read. + * @retval The input pin value + */ +uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + if (READ_BIT(GPIOx->DIN, pin)) + return 1; + else + return 0; +} + +/** + * @brief Set or clear the select Pin data. + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @param pin: The specified pin to be written. + * @param val: The specifies value to be written. + * @retval None + */ +void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + if ((val & (0x01)) == 0x00) + GPIOx->BSRR = pin << 16U; + else + GPIOx->BSRR = pin; + + return; +} + +/** + * @brief Turn over the select data. + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @param pin: Specifies the pin to turn over. + * @retval None + */ +void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + WRITE_REG(GPIOx->BIR, pin); + return; +} + +/** + * @brief Turn over the direction. + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @param pin: Specifies the pin to turn over. + * @retval None + */ +void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + uint32_t i, pos, mask, tmp, value; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + for (i = 0; i < 16; ++i) + { + if (((pin >> i) & 0x1) == 0) + continue; + + /* Get position and 2-bits mask */ + pos = i << 1; + mask = 0x3 << pos; + + /* Get the new direction */ + tmp = READ_REG(GPIOx->MODE); + value = (tmp >> pos) & 0x3; + + if ((value == 2) || (value == 3)) + value = 1; + else if (value == 1) + { + value = 2; + } + else + { + continue; /* do nothing */ + } + + /* Set PIN mode */ + tmp &= ~mask; + tmp |= (value << pos); + WRITE_REG(GPIOx->MODE, tmp); + } + + return; +} + +/** + * @brief Lock the GPIO prot. Once locked, can + * only change the output data. Only when the CPU + * reset to unlock the GPIO port. + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @param pin: The specified Pin to be written. + * @retval None + */ +void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + MODIFY_REG(GPIOx->LOCK, GPIO_LOCK_KEY_MSK, ALD_UNLOCK_KEY << GPIO_LOCK_KEY_POSS); + WRITE_REG(GPIOx->LOCK, pin); + + return; +} + +/** + * @brief Read the specified input port pin. + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @retval The value; + */ +uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + + return READ_REG(GPIOx->DIN); +} + +/** + * @brief Set or clear the select Pin data. + * @param GPIOx: Where x can be (A--D) to select the GPIO peripheral. + * @param val: The specifies value to be written. + * @retval None + */ +void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + + WRITE_REG(GPIOx->DOUT, val); + return; +} +/** + * @} + */ + +/** @defgroup GPIO_Public_Functions_Group3 Control functions + * @brief EXTI Control functions + * + @verbatim + =============================================================================== + ##### Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to + control external interrupt. + + @endverbatim + * @{ + */ + +/** + * @brief Configure the interrupt according to the specified parameter. + * @param pin: The Pin which need to configure. + * @param style: External interrupt trigger style. + * @param status: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_gpio_exti_interrupt_config(uint16_t pin, ald_exti_trigger_style_t style, type_func_t status) +{ + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_TRIGGER_STYLE(style)); + assert_param(IS_FUNC_STATE(status)); + + if (status == ENABLE) + { + if (style == ALD_EXTI_TRIGGER_RISING_EDGE) + { + SET_BIT(EXTI->EXTIRER, pin); + } + else if (style == ALD_EXTI_TRIGGER_TRAILING_EDGE) + { + SET_BIT(EXTI->EXTIFER, pin); + } + else if (style == ALD_EXTI_TRIGGER_BOTH_EDGE) + { + SET_BIT(EXTI->EXTIRER, pin); + SET_BIT(EXTI->EXTIFER, pin); + } + else + { + ; /* do nothing */ + } + + WRITE_REG(EXTI->EXTICFR, 0xffff); + SET_BIT(EXTI->EXTIEN, pin); + } + else + { + if (style == ALD_EXTI_TRIGGER_RISING_EDGE) + { + CLEAR_BIT(EXTI->EXTIRER, pin); + } + else if (style == ALD_EXTI_TRIGGER_TRAILING_EDGE) + { + CLEAR_BIT(EXTI->EXTIFER, pin); + } + else if (style == ALD_EXTI_TRIGGER_BOTH_EDGE) + { + CLEAR_BIT(EXTI->EXTIRER, pin); + CLEAR_BIT(EXTI->EXTIFER, pin); + } + else + { + ; /* do nothing */ + } + + CLEAR_BIT(EXTI->EXTIEN, pin); + } + + return; +} + +/** + * @brief Get the IE status about external interrupt. + * @param pin: The pin which belong to external interrupt. + * @retval IE status + * - ENABLE + * - DISABLE + */ +type_func_t ald_gpio_exti_get_ie_status(uint16_t pin) +{ + assert_param(IS_GPIO_PIN(pin)); + + if (READ_BIT(EXTI->EXTIEN, pin)) + return ENABLE; + + return DISABLE; +} + +/** + * @brief Get the Flag about external interrupt. + * @param pin: The pin which belong to external interrupt. + * @retval Flag status + * - SET + * - RESET + */ +flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin) +{ + assert_param(IS_GPIO_PIN(pin)); + + if (READ_BIT(EXTI->EXTIFLAG, pin)) + return SET; + + return RESET; +} + +/** + * @brief Clear the external interrupt flag. + * @param pin: The pin which belong to external interrupt. + * @retval None + */ +void ald_gpio_exti_clear_flag_status(uint16_t pin) +{ + assert_param(IS_GPIO_PIN(pin)); + + if (READ_BIT(EXTI->EXTIFER, pin)) + { + CLEAR_BIT(EXTI->EXTIFER, pin); + SET_BIT(EXTI->EXTIFER, pin); + } + + if (READ_BIT(EXTI->EXTIRER, pin)) + { + CLEAR_BIT(EXTI->EXTIRER, pin); + SET_BIT(EXTI->EXTIRER, pin); + } + + WRITE_REG(EXTI->EXTICFR, pin); + return; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_gpio.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_gpio.h new file mode 100644 index 0000000000..8abeeb82a6 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_gpio.h @@ -0,0 +1,323 @@ +/** + ********************************************************************************* + * + * @file ald_gpio.h + * @brief Header file of GPIO module driver + * + * @version V1.0 + * @date 30 Jan. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 30 Jan. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_GPIO_H__ +#define __ALD_GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_utils.h" + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Constants -------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** + * @defgroup GPIO_Public_Macros GPIO Public Macros + * @{ + */ +#define ALD_GPIO_PIN_0 (0x1U) +#define ALD_GPIO_PIN_1 (0x2U) +#define ALD_GPIO_PIN_2 (0x4U) +#define ALD_GPIO_PIN_3 (0x8U) +#define ALD_GPIO_PIN_4 (0x10U) +#define ALD_GPIO_PIN_5 (0x20U) +#define ALD_GPIO_PIN_6 (0x40U) +#define ALD_GPIO_PIN_7 (0x80U) +#define ALD_GPIO_PIN_8 (0x100U) +#define ALD_GPIO_PIN_9 (0x200U) +#define ALD_GPIO_PIN_10 (0x400U) +#define ALD_GPIO_PIN_11 (0x800U) +#define ALD_GPIO_PIN_12 (0x1000U) +#define ALD_GPIO_PIN_13 (0x2000U) +#define ALD_GPIO_PIN_14 (0x4000U) +#define ALD_GPIO_PIN_15 (0x8000U) +#define ALD_GPIO_PIN_ALL (0xFFFF) + +/* Toggle IO */ +#define ALD_GPIOA_TOGGLE_PIN(x) (GPIOA->BIR = (x)) +#define ALD_GPIOB_TOGGLE_PIN(x) (GPIOB->BIR = (x)) +#define ALD_GPIOC_TOGGLE_PIN(x) (GPIOC->BIR = (x)) +#define ALD_GPIOD_TOGGLE_PIN(x) (GPIOD->BIR = (x)) + +/* Read IO level */ +#define ALD_GPIOA_READ_PIN(x) ((GPIOA->DIN & (x)) ? 1 : 0) +#define ALD_GPIOB_READ_PIN(x) ((GPIOB->DIN & (x)) ? 1 : 0) +#define ALD_GPIOC_READ_PIN(x) ((GPIOC->DIN & (x)) ? 1 : 0) +#define ALD_GPIOD_READ_PIN(x) ((GPIOD->DIN & (x)) ? 1 : 0) + +/* Set IO as high */ +#define ALD_GPIOA_SET_PIN(x) (GPIOA->BSRR = (x)) +#define ALD_GPIOB_SET_PIN(x) (GPIOB->BSRR = (x)) +#define ALD_GPIOC_SET_PIN(x) (GPIOC->BSRR = (x)) +#define ALD_GPIOD_SET_PIN(x) (GPIOD->BSRR = (x)) + +/* Set IO as low */ +#define ALD_GPIOA_RESET_PIN(x) (GPIOA->BSRR = ((x) << 16)) +#define ALD_GPIOB_RESET_PIN(x) (GPIOB->BSRR = ((x) << 16)) +#define ALD_GPIOC_RESET_PIN(x) (GPIOC->BSRR = ((x) << 16)) +#define ALD_GPIOD_RESET_PIN(x) (GPIOD->BSRR = ((x) << 16)) +/** + * @} + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** + * @defgroup GPIO_Public_Types GPIO Public Types + * @{ + */ + +/** + * @brief GPIO mode + */ +typedef enum +{ + ALD_GPIO_MODE_CLOSE = 0x0U, /**< Digital close Analog open */ + ALD_GPIO_MODE_INPUT = 0x1U, /**< Input */ + ALD_GPIO_MODE_OUTPUT = 0x2U, /**< Output */ +} ald_gpio_mode_t; + +/** + * @brief GPIO open-drain or push-pull + */ +typedef enum +{ + ALD_GPIO_PUSH_PULL = 0x0U, /**< Push-Pull */ + ALD_GPIO_OPEN_DRAIN = 0x2U, /**< Open-Drain. Can't output high level */ +} ald_gpio_od_t; + +/** + * @brief GPIO push-up or push-down + */ +typedef enum +{ + ALD_GPIO_FLOATING = 0x0U, /**< Floating */ + ALD_GPIO_PUSH_UP = 0x1U, /**< Push-Up */ + ALD_GPIO_PUSH_DOWN = 0x2U, /**< Push-Down */ + ALD_GPIO_PUSH_UP_DOWN = 0x3U, /**< Push-Up and Push-Down */ +} ald_gpio_push_t; + +/** + * @brief GPIO output drive + */ +typedef enum +{ + ALD_GPIO_OUT_DRIVE_NORMAL = 0x0U, /**< Normal current flow */ + ALD_GPIO_OUT_DRIVE_STRONG = 0x1U, /**< Strong current flow */ +} ald_gpio_out_drive_t; + +/** + * @brief GPIO filter + */ +typedef enum +{ + ALD_GPIO_FILTER_DISABLE = 0x0U, /**< Disable filter */ + ALD_GPIO_FILTER_ENABLE = 0x1U, /**< Enable filter */ +} ald_gpio_filter_t; + +/** + * @brief GPIO type + */ +typedef enum +{ + ALD_GPIO_TYPE_CMOS = 0x0U, /**< CMOS Type */ + ALD_GPIO_TYPE_TTL = 0x1U, /**< TTL Type */ +} ald_gpio_type_t; + +/** + * @brief GPIO functions + */ +typedef enum +{ + ALD_GPIO_FUNC_0 = 0U, /**< function #0 */ + ALD_GPIO_FUNC_1 = 1U, /**< function #1 */ + ALD_GPIO_FUNC_2 = 2U, /**< function #2 */ + ALD_GPIO_FUNC_3 = 3U, /**< function #3 */ + ALD_GPIO_FUNC_4 = 4U, /**< function #4 */ + ALD_GPIO_FUNC_5 = 5U, /**< function #5 */ + ALD_GPIO_FUNC_6 = 6U, /**< function #6 */ + ALD_GPIO_FUNC_7 = 7U, /**< function #7 */ +} ald_gpio_func_t; + +/** + * @brief GPIO Init Structure definition + */ +typedef struct +{ + ald_gpio_mode_t mode; /**< Specifies the operating mode for the selected pins. + This parameter can be any value of @ref gpio_mode_t */ + ald_gpio_od_t od; /**< Specifies the Open-Drain or Push-Pull for the selected pins. + This parameter can be a value of @ref gpio_od_t */ + ald_gpio_push_t pupd; /**< Specifies the Pull-up or Pull-Down for the selected pins. + This parameter can be a value of @ref gpio_push_t */ + ald_gpio_out_drive_t odrv; /**< Specifies the output MOS driver for the selected pins. + This parameter can be a value of @ref gpio_out_drive_t */ + ald_gpio_filter_t flt; /**< Specifies the input filter for the selected pins. + This parameter can be a value of @ref gpio_filter_t */ + ald_gpio_type_t type; /**< Specifies the type for the selected pins. + This parameter can be a value of @ref gpio_type_t */ + ald_gpio_func_t func; /**< Specifies the function for the selected pins. + This parameter can be a value of @ref gpio_func_t */ +} ald_gpio_init_t; + +/** + * @brief EXTI trigger style + */ +typedef enum +{ + ALD_EXTI_TRIGGER_RISING_EDGE = 0U, /**< Rising edge trigger */ + ALD_EXTI_TRIGGER_TRAILING_EDGE = 1U, /**< Trailing edge trigger */ + ALD_EXTI_TRIGGER_BOTH_EDGE = 2U, /**< Rising and trailing edge trigger */ +} ald_exti_trigger_style_t; + +/** + * @brief EXTI Init Structure definition + */ +typedef struct +{ + type_func_t filter; /**< Enable filter. */ + uint8_t filter_time; /**< Filter duration */ +} ald_exti_init_t; +/** + * @} + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** + * @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define ALD_PIN_MASK 0xFFFFU +#define ALD_UNLOCK_KEY 0x55AAU + +#define IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0)) +#define IS_GPIO_PORT(GPIOx) ((GPIOx == GPIOA) || \ + (GPIOx == GPIOB) || \ + (GPIOx == GPIOC) || \ + (GPIOx == GPIOD)) +#define IS_GPIO_MODE(x) (((x) == ALD_GPIO_MODE_CLOSE) || \ + ((x) == ALD_GPIO_MODE_INPUT) || \ + ((x) == ALD_GPIO_MODE_OUTPUT)) +#define IS_GPIO_OD(x) (((x) == ALD_GPIO_PUSH_PULL) || \ + ((x) == ALD_GPIO_OPEN_DRAIN)) +#define IS_GPIO_PUPD(x) (((x) == ALD_GPIO_FLOATING) || \ + ((x) == ALD_GPIO_PUSH_UP) || \ + ((x) == ALD_GPIO_PUSH_DOWN) || \ + ((x) == ALD_GPIO_PUSH_UP_DOWN)) +#define IS_GPIO_ODRV(x) (((x) == ALD_GPIO_OUT_DRIVE_NORMAL) || \ + ((x) == ALD_GPIO_OUT_DRIVE_STRONG)) +#define IS_GPIO_FLT(x) (((x) == ALD_GPIO_FILTER_DISABLE) || \ + ((x) == ALD_GPIO_FILTER_ENABLE)) +#define IS_GPIO_TYPE(x) (((x) == ALD_GPIO_TYPE_TTL) || \ + ((x) == ALD_GPIO_TYPE_CMOS)) +#define IS_TRIGGER_STYLE(x) (((x) == ALD_EXTI_TRIGGER_RISING_EDGE) || \ + ((x) == ALD_EXTI_TRIGGER_TRAILING_EDGE) || \ + ((x) == ALD_EXTI_TRIGGER_BOTH_EDGE)) +#define IS_GPIO_FUNC(x) ((x) <= 7) +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @addtogroup GPIO_Public_Functions + * @{ + */ + +/** @addtogroup GPIO_Public_Functions_Group1 + * @{ + */ +void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, ald_gpio_init_t *init); +void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_func_default(GPIO_TypeDef *GPIOx); +void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, ald_exti_init_t *init); +/** + * @} + */ + +/** @addtogroup GPIO_Public_Functions_Group2 + * @{ + */ +uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val); +void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx); +void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val); +/** + * @} + */ + +/** @addtogroup GPIO_Public_Functions_Group3 + * @{ + */ +void ald_gpio_exti_interrupt_config(uint16_t pin, ald_exti_trigger_style_t style, type_func_t status); +type_func_t ald_gpio_exti_get_ie_status(uint16_t pin); +flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin); +void ald_gpio_exti_clear_flag_status(uint16_t pin); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_GPIO_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_i2c.c b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_i2c.c new file mode 100644 index 0000000000..2f7bec2e45 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_i2c.c @@ -0,0 +1,3665 @@ +/** + ********************************************************************************* + * + * @file ald_i2c.c + * @brief I2C module driver. + * + * @version V1.0 + * @date 24 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 24 Feb. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The I2C driver can be used as follows: + + (#) Declare a i2c_handle_t handle structure, for example: + i2c_handle_t hperh; + + (#) Configure the Communication Speed, Addressing mode, Own Address1, + Dual Addressing mode, Own Address2, General call and Nostretch mode in the hperh init structure. + + (#) Initialize the I2C registers by calling the ald_i2c_init(). + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using ald_i2c_master_send() + (+) Receive in master mode an amount of data in blocking mode using ald_i2c_master_recv() + (+) Transmit in slave mode an amount of data in blocking mode using ald_i2c_slave_send() + (+) Receive in slave mode an amount of data in blocking mode using ald_i2c_slave_recv() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using ald_i2c_mem_write() + (+) Read an amount of data in blocking mode from a specific memory address using ald_i2c_mem_read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) The I2C interrupts should have the highest priority in the application in order + to make them uninterruptible. + (+) Transmit in master mode an amount of data in non-blocking mode using ald_i2c_master_send_by_it() + (+) At transmission end of transfer, hperh->master_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->master_tx_cplt_cbk() + (+) Receive in master mode an amount of data in non-blocking mode using ald_i2c_master_recv_by_it() + (+) At reception end of transfer, hperh->master_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->master_rx_cplt_cbk() + (+) Transmit in slave mode an amount of data in non-blocking mode using ald_i2c_slave_send_by_it() + (+) At transmission end of transfer, hperh->slave_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->slave_tx_cplt_cbk() + (+) Receive in slave mode an amount of data in non-blocking mode using ald_i2c_slave_recv_by_it() + (+) At reception end of transfer, hperh->slave_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->slave_rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_callback() function is executed and user can + add his own code by customization of function pointer hperh->error_callback() + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) The I2C interrupts should have the highest priority in the application in order + to make them uninterruptible. + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + ald_i2c_mem_write_by_it() + (+) At Memory end of write transfer, hperh->mem_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->mem_tx_cplt_cbk() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + ald_i2c_mem_read_by_it() + (+) At Memory end of read transfer, hperh->mem_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->mem_rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_callback() function is executed and user can + add his own code by customization of function pointer hperh->error_callback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + ald_i2c_master_send_by_dma() + (+) At transmission end of transfer, hperh->master_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->master_tx_cplt_cbk() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + ald_i2c_master_recv_by_dma() + (+) At reception end of transfer, hperh->master_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->master_rx_cplt_cbk() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + ald_i2c_slave_send_by_dma() + (+) At transmission end of transfer, hperh->slave_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->slave_tx_cplt_cbk() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + ald_i2c_slave_recv_by_dma() + (+) At reception end of transfer, hperh->slave_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->slave_rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_callback() function is executed and user can + add his own code by customization of function pointer hperh->error_callback() + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + ald_i2c_mem_write_by_dma() + (+) At Memory end of write transfer, hperh->mem_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->mem_tx_cplt_cbk() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + ald_i2c_mem_read_by_dma() + (+) At Memory end of read transfer, hperh->mem_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->mem_rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_callback() function is executed and user can + add his own code by customization of function pointer hperh->error_callback() + + + *** I2C ald_status_t driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C ald_status_t driver. + + (+) __I2C_ENABLE: Enable the I2C peripheral + (+) __I2C_DISABLE: Disable the I2C peripheral + (+) I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) I2C_DISABLE_IT: Disable the specified I2C interrupt + (@) You can refer to the I2C ald_status_t driver header file for more useful macros + + *** I2C Workarounds linked to Silicon Limitation *** + ==================================================== + [..] + Below the list of all silicon limitations implemented for library on our product. + (@) See ErrataSheet to know full silicon limitation list of your product. + + (#) Workarounds Implemented inside I2C library + (##) Wrong data read into data register (Polling and Interrupt mode) + (##) Start cannot be generated after a misplaced Stop + (##) Some software events must be managed before the current byte is being transferred: + Workaround: Use DMA in general, except when the Master is receiving a single byte. + For Interupt mode, I2C should have the highest priority in the application. + (##) Mismatch on the "Setup time for a repeated Start condition" timing parameter: + Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if + supported by the slave. + (##) Data valid time (tVD;DAT) violated without the OVR flag being set: + Workaround: If the slave device allows it, use the clock stretching mechanism + by programming no_stretch = I2C_NOSTRETCH_DISABLE in ald_i2c_init. + + @endverbatim + ********************************************************************************* + */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_i2c.h" + +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C module driver + * @{ + */ + +/* Private Macros ------------------------------------------------------------ */ + +/** @addtogroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +#define I2C_TIMEOUT_FLAG (10) +#define I2C_TIMEOUT_ADDR_SLAVE (10) +#define I2C_TIMEOUT_BUSY_FLAG (10) +#define I2C_MAX_DELAY 0xFFFFFFFF + +/** + * @} + */ + +/* Private function prototypes ----------------------------------------------- */ + +/** @addtogroup I2C_Private_Functions I2C Private Functions + * @{ + */ + +static void i2c_dma_master_send_cplt(void *argv); +static void i2c_dma_master_recv_cplt(void *argv); +static void i2c_dma_slave_send_cplt(void *argv); +static void i2c_dma_slave_recv_cplt(void *argv); +static void i2c_dma_mem_send_cplt(void *argv); +static void i2c_dma_mem_recv_cplt(void *argv); +static ald_status_t i2c_req_mem_read(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + uint16_t add_size, uint32_t timeout); + +static ald_status_t i2c_master_req_write(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout); +static ald_status_t i2c_master_req_read(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout); +static ald_status_t i2c_req_mem_write(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + uint16_t add_size, uint32_t timeout); +static ald_status_t i2c_wait_flag_change_to_timeout(ald_i2c_handle_t *hperh, uint32_t flag, + flag_status_t status, uint32_t timeout); +static ald_status_t i2c_wait_master_addr_to_timeout(ald_i2c_handle_t *hperh, uint32_t flag, uint32_t timeout); +static ald_status_t i2c_wait_txe_to_timeout(ald_i2c_handle_t *hperh, uint32_t timeout); +static ald_status_t i2c_wait_rxne_to_timeout(ald_i2c_handle_t *hperh, uint32_t timeout); +static ald_status_t i2c_master_send_tc(ald_i2c_handle_t *hperh); +static ald_status_t i2c_master_send_txe(ald_i2c_handle_t *hperh); +static ald_status_t i2c_master_recv_tc(ald_i2c_handle_t *hperh); +static ald_status_t i2c_master_recv_rxne(ald_i2c_handle_t *hperh); +static ald_status_t i2c_slave_send_txe(ald_i2c_handle_t *hperh); +static ald_status_t i2c_slave_recv_rxne(ald_i2c_handle_t *hperh); +static ald_status_t i2c_slave_stopf(ald_i2c_handle_t *hperh); + +/** + * @} + */ + +/* Private Function ---------------------------------------------------------- */ + +/** @defgroup I2C_Public_Functions I2C Public functions + * @{ + */ + +/** @defgroup I2C_Public_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialiaze the I2Cx peripheral: + + (+) Call the function ald_i2c_init() to configure the selected device with + the selected configuration: + (++) Communication Speed + (++) Addressing mode + (++) Own Address 1 + (++) Dual Addressing mode + (++) Own Address 2 + (++) General call mode + (++) Nostretch mode + + (+) Call the function ald_i2c_reset() to restore the default configuration + of the selected I2Cx periperal. + +@endverbatim + * @{ + */ + +/** + * @brief I2C Configuration Speed function. + * @param hperh: Pointer to a i2c_handle_t structure that contains. + * the configuration information for the I2C speed. + * @param clk: I2C Peripheral bus clock + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_speed_init(ald_i2c_handle_t *hperh, uint32_t clk) +{ + int32_t t_scl, t_pre, tmp; + uint8_t scll, sclh, sdadel, scldel; + + if (clk > 72000000) + return ALD_ERROR; + + if (hperh->init.module == ALD_I2C_MODULE_SLAVE) + { + hperh->init.clk_speed = 400000UL; + } + + if (hperh->init.clk_speed <= 100000UL) + { + tmp = clk / 4000000UL; + tmp = tmp >= 16UL ? 16UL : tmp; + clk = clk / tmp; + } + else if (hperh->init.clk_speed <= 500000UL) + { + if (clk < 8000000UL) + return ALD_ERROR; + + tmp = clk / 8000000UL; + clk = clk / tmp; + } + else + { + if (clk < 12000000UL) + return ALD_ERROR; + + tmp = clk / 12000000UL; + clk = clk / tmp; + } + + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_PRESC_MSK, (tmp - 1) << I2C_TIMINGR_PRESC_POSS); + + t_scl = 1000000000UL / hperh->init.clk_speed; + t_pre = 1000000000UL / clk; + + tmp = (t_scl << 4UL) / (t_pre << 1UL); + tmp = ((tmp + 8UL) >> 4UL); + tmp = tmp >= 255UL ? 255UL : tmp; + scll = tmp; + + if (scll < 4) + return ALD_ERROR; + + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLL_MSK, (scll - 1) << I2C_TIMINGR_SCLL_POSS); + scldel = ((scll << 1) / 3); + scldel = scldel > 16 ? 16 : scldel; + sdadel = (scll / 3) < (scll - scldel - 1) ? (scll / 3) : (scll - scldel - 1); + sdadel = sdadel > 3 ? 3 : sdadel; + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, (scldel - 1) << I2C_TIMINGR_SCLDEL_POSS); + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SDADEL_MSK, sdadel << I2C_TIMINGR_SDADEL_POSS); + + if (scll > 6) + sclh = scll - 3; + else if (scll > 4) + sclh = 3; + else + sclh = 2; + + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLH_MSK, (sclh - 1UL) << I2C_TIMINGR_SCLH_POSS); + return ALD_OK; +} +/** + * @brief Initializes the I2C according to the specified parameters + * in the i2c_init_t and initialize the associated handle. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_init(ald_i2c_handle_t *hperh) +{ + uint32_t freqrange = ald_cmu_get_pclk_clock(); + + if (hperh == NULL) + return ALD_ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_CLOCK_SPEED(hperh->init.clk_speed)); + assert_param(IS_I2C_ADDRESSING_MODE(hperh->init.addr_mode)); + assert_param(IS_I2C_GENERAL_CALL(hperh->init.general_call)); + assert_param(IS_I2C_NO_STRETCH(hperh->init.no_stretch)); + assert_param(IS_I2C_MODULE(hperh->init.module)); + + if (hperh->state == ALD_I2C_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = ALD_I2C_STATE_BUSY; + + ALD_I2C_DISABLE(hperh); + + if (ALD_OK != i2c_speed_init(hperh, freqrange)) + return ALD_ERROR; + + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NOSTRETCH_MSK, (hperh->init.no_stretch) << I2C_CON1_NOSTRETCH_POS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_GCEN_MSK, (hperh->init.general_call) << I2C_CON1_GCEN_POS); + + if (hperh->init.dual_addr == ALD_I2C_DUALADDR_ENABLE) + { + CLEAR_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK); + MODIFY_REG(hperh->perh->ADDR1, I2C_ADDR1_OA1_MSK, (hperh->init.own_addr1 & 0x3FF) << I2C_ADDR1_OA1_POSS); + SET_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK); + + CLEAR_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK); + MODIFY_REG(hperh->perh->ADDR2, I2C_ADDR2_OA2_MSK, (hperh->init.own_addr2 & 0x7F) << I2C_ADDR2_OA2_POSS); + SET_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK); + } + else + { + if (hperh->init.addr_mode == ALD_I2C_ADDR_10BIT) + { + CLEAR_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK); + SET_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1MODE_MSK); + MODIFY_REG(hperh->perh->ADDR1, I2C_ADDR1_OA1_MSK, (hperh->init.own_addr1 & 0x3FF) << I2C_ADDR1_OA1_POSS); + SET_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK); + } + else + { + CLEAR_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK); + MODIFY_REG(hperh->perh->ADDR2, I2C_ADDR2_OA2_MSK, (hperh->init.own_addr2 & 0x7F) << I2C_ADDR2_OA2_POSS); + SET_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK); + } + } + + ALD_I2C_ENABLE(hperh); + + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + + return ALD_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_reset(ald_i2c_handle_t *hperh) +{ + if (hperh == NULL) + return ALD_ERROR; + + ALD_I2C_DISABLE(hperh); + + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + + __UNLOCK(hperh); + + WRITE_REG(hperh->perh->CON1, 0); + WRITE_REG(hperh->perh->CON2, 0); + WRITE_REG(hperh->perh->ADDR1, 0); + WRITE_REG(hperh->perh->ADDR2, 0); + WRITE_REG(hperh->perh->TIMINGR, 0); + WRITE_REG(hperh->perh->TIMEOUTR, 0); + WRITE_REG(hperh->perh->IDR, ALD_I2C_FLAG_MASK); + WRITE_REG(hperh->perh->ICR, ALD_I2C_FLAG_MASK); + + ALD_I2C_ENABLE(hperh); + + return ALD_OK; +} +/** + * @} + */ + +/** @defgroup I2C_Public_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) ald_i2c_master_send() + (++) ald_i2c_master_recv() + (++) ald_i2c_slave_send() + (++) ald_i2c_slave_recv() + (++) ald_i2c_mem_write() + (++) ald_i2c_mem_read() + + (#) No-Blocking mode functions with Interrupt are : + (++) ald_i2c_master_send_by_it() + (++) ald_i2c_master_recv_by_it() + (++) ald_i2c_slave_send_by_it() + (++) ald_i2c_slave_recv_by_it() + (++) ald_i2c_mem_write_by_it() + (++) ald_i2c_mem_read_by_it() + + (#) No-Blocking mode functions with DMA are : + (++) ald_i2c_master_send_by_dma() + (++) ald_i2c_master_recv_by_dma() + (++) ald_i2c_slave_send_by_dma() + (++) ald_i2c_slave_recv_by_dma() + (++) ald_i2c_mem_write_by_dma() + (++) ald_i2c_mem_read_by_dma() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) hperh->mem_tx_cplt_cbk() + (++) hperh->mem_rx_cplt_cbk() + (++) hperh->master_tx_cplt_cbk() + (++) hperh->master_rx_cplt_cbk() + (++) hperh->slave_tx_cplt_cbk() + (++) hperh->slave_rx_cplt_cbk() + (++) hperh->error_callback() + +@endverbatim + * @{ + */ +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_send(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint32_t size, uint32_t timeout) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_MASTER; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + i2c_master_req_write(hperh, dev_addr, timeout); + + if (size <= 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + while (size > 0) + { + hperh->perh->TXDATA = (*buf++); + size--; + hperh->xfer_count++; + + if (i2c_wait_txe_to_timeout(hperh, timeout) != ALD_OK) + goto ERROR; + + if (((hperh->xfer_count % 0xFFFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) + { + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == ALD_OK) + { + if (size > 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + } + else + { + goto ERROR; + } + } + } + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK) == SET) + goto SUCCESS; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == ALD_OK) + { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + goto SUCCESS; + } + else + { + goto ERROR; + } + +ERROR: + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + +SUCCESS: + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t + */ +ald_status_t ald_i2c_master_recv(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint32_t size, uint32_t timeout) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_RX; + hperh->mode = ALD_I2C_MODE_MASTER; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + i2c_master_req_read(hperh, dev_addr, timeout); + + if (size <= 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + while (size > 0) + { + if (i2c_wait_rxne_to_timeout(hperh, timeout) != ALD_OK) + goto ERROR; + + (*buf++) = hperh->perh->RXDATA; + size--; + hperh->xfer_count++; + + if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) + { + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == ALD_OK) + { + if (size > 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + } + else + { + goto ERROR; + } + } + } + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK)) + goto SUCCESS; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + goto SUCCESS; + +ERROR: + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + +SUCCESS: + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_send(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_SLAVE; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + ALD_I2C_ENABLE(hperh); + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TXE, RESET, timeout) != ALD_OK) + goto ERROR; + + hperh->perh->TXDATA = (*buf++); + --size; + hperh->xfer_count++; + + if (i2c_wait_master_addr_to_timeout(hperh, ALD_I2C_IT_ADDR, timeout) == ALD_ERROR) + goto ERROR; + + while (size > 0) + { + if (i2c_wait_txe_to_timeout(hperh, timeout) == ALD_ERROR) + goto ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TXE, RESET, timeout) != ALD_OK) + goto ERROR; + + hperh->perh->TXDATA = (*buf++); + --size; + hperh->xfer_count++; + } + + goto SUCCESS; + +ERROR: + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + +SUCCESS: + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_recv(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_RX; + hperh->mode = ALD_I2C_MODE_SLAVE; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_count = 0; + hperh->xfer_size = size; + + if (i2c_wait_master_addr_to_timeout(hperh, ALD_I2C_IT_ADDR, timeout) == ALD_ERROR) + goto ERROR; + + while (size > 0) + { + if (i2c_wait_rxne_to_timeout(hperh, timeout) == ALD_ERROR) + goto ERROR; + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_HOLDACK_MSK)) + SET_BIT(hperh->perh->CON2, I2C_CON2_ACK_UPD_MSK); + + (*buf++) = hperh->perh->RXDATA; + --size; + hperh->xfer_count++; + } + + goto SUCCESS; + +ERROR: + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + +SUCCESS: + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_send_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_MASTER; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG); + + if (size <= 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TXE); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_NACK); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TC); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TCR); + + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + ALD_I2C_ENABLE_IT(hperh, ALD_I2C_IT_TXE | ALD_I2C_IT_NACK | ALD_I2C_IT_TC | ALD_I2C_IT_TCR); + + return ALD_OK; +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_recv_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_RX; + hperh->mode = ALD_I2C_MODE_MASTER; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) ; + + if (size <= 0xFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_RXNE); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TCR); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TC); + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + ALD_I2C_ENABLE_IT(hperh, ALD_I2C_IT_RXNE | ALD_I2C_IT_TCR | ALD_I2C_IT_TC); + + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + return ALD_OK; +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_send_by_it(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_SLAVE; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TXE); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_ADDR); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_NACK); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_STOP); + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + ALD_I2C_ENABLE_IT(hperh, ALD_I2C_IT_ADDR | ALD_I2C_IT_NACK | ALD_I2C_IT_STOP | ALD_I2C_IT_TXE); + + return ALD_OK; +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_recv_by_it(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_RX; + hperh->mode = ALD_I2C_MODE_SLAVE; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_RXNE); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_ADDR); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_STOP); + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + ALD_I2C_ENABLE_IT(hperh, ALD_I2C_IT_RXNE | ALD_I2C_IT_ADDR | ALD_I2C_IT_STOP); + + return ALD_OK; +} + +/** + * @brief Sequential Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param option: Options of Transfer + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_seq_send_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size, uint32_t option) +{ + uint32_t pre_state = 0U; + uint32_t it_flag = 0U; + + assert_param(IS_I2C_TRANSFER_OPTIONS(option)); + + if (hperh->state == ALD_I2C_STATE_READY) + { + if ((READ_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK) == I2C_CON2_STOP_MSK) || (option == ALD_I2C_FIRST_AND_LAST_FRAME) || (option == ALD_I2C_FIRST_FRAME)) + { + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + { + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + + __UNLOCK(hperh); + return ALD_BUSY; + } + } + + __LOCK(hperh); + + if ((READ_BIT(hperh->perh->CON1, I2C_CON1_PE_MSK) != I2C_CON1_PE_MSK)) + { + ALD_I2C_ENABLE(hperh); + } + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_MASTER; + hperh->error_code = ALD_I2C_ERROR_NONE; + + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + hperh->xfer_opt = option; + pre_state = hperh->pre_state; + + if (size <= 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + } + + if ((pre_state != ALD_I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS(option))) + { + i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG); + + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + } + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TXE); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_NACK); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TC); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TCR); + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + + it_flag = ALD_I2C_IT_TXE | ALD_I2C_IT_NACK | ALD_I2C_IT_TCR; + + if ((option == ALD_I2C_FIRST_AND_LAST_FRAME) || (option == ALD_I2C_LAST_FRAME) || (option == ALD_I2C_OTHER_AND_LAST_FRAME)) + { + it_flag |= ALD_I2C_IT_TC; + + if (size <= 0xFFFF) + { + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + it_flag &= ~ALD_I2C_IT_TCR; + } + } + + ALD_I2C_ENABLE_IT(hperh, it_flag); + + __UNLOCK(hperh); + } + else + { + return ALD_BUSY; + } + + return ALD_OK; +} + +/** + * @brief Sequential Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param option: Options of Transfer + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_seq_recv_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size, uint32_t option) +{ + uint32_t pre_state = 0U; + uint32_t it_flag = 0U; + + assert_param(IS_I2C_TRANSFER_OPTIONS(option)); + + if (hperh->state == ALD_I2C_STATE_READY) + { + if ((READ_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK) == I2C_CON2_STOP_MSK) || (option == ALD_I2C_FIRST_AND_LAST_FRAME) || (option == ALD_I2C_FIRST_FRAME)) + { + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + { + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + + __UNLOCK(hperh); + return ALD_BUSY; + } + } + + __LOCK(hperh); + + if ((READ_BIT(hperh->perh->CON1, I2C_CON1_PE_MSK) != I2C_CON1_PE_MSK)) + ALD_I2C_ENABLE(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_RX; + hperh->mode = ALD_I2C_MODE_MASTER; + hperh->error_code = ALD_I2C_ERROR_NONE; + + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + pre_state = hperh->pre_state; + + if (size <= 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + } + + if ((pre_state != ALD_I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS(option))) + { + i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG); + + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + } + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_RXNE); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TCR); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TC); + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + + it_flag = ALD_I2C_IT_RXNE | ALD_I2C_IT_TCR; + + if ((option == ALD_I2C_FIRST_AND_LAST_FRAME) || (option == ALD_I2C_LAST_FRAME) || (option == ALD_I2C_OTHER_AND_LAST_FRAME)) + it_flag |= ALD_I2C_IT_TC; + + ALD_I2C_ENABLE_IT(hperh, it_flag); + + __UNLOCK(hperh); + } + else + { + return ALD_BUSY; + } + + return ALD_OK; +} + +/** + * @brief Sequential Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param option: Options of Transfer + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_seq_send_by_it(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t option) +{ + assert_param(IS_I2C_TRANSFER_OPTIONS(option)); + + if (((hperh->state & ALD_I2C_STATE_LISTEN) == ALD_I2C_STATE_LISTEN) || (hperh->state == ALD_I2C_STATE_READY)) + { + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + __LOCK(hperh); + + if ((READ_BIT(hperh->perh->CON1, I2C_CON1_PE_MSK) != I2C_CON1_PE_MSK)) + { + ALD_I2C_ENABLE(hperh); + } + + hperh->state = ALD_I2C_STATE_BUSY_TX_LISTEN; + hperh->mode = ALD_I2C_MODE_SLAVE; + hperh->error_code = ALD_I2C_ERROR_NONE; + + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + hperh->xfer_opt = option; + + __UNLOCK(hperh); + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TXE); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_ADDR); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_NACK); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_STOP); + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + ALD_I2C_ENABLE_IT(hperh, ALD_I2C_IT_ADDR | ALD_I2C_IT_NACK | ALD_I2C_IT_STOP | ALD_I2C_IT_TXE); + } + else + { + return ALD_BUSY; + } + + return ALD_OK; +} + +/** + * @brief Sequential Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param option: Options of Transfer + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_seq_recv_by_it(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t option) +{ + assert_param(IS_I2C_TRANSFER_OPTIONS(option)); + + if (((hperh->state & ALD_I2C_STATE_LISTEN) == ALD_I2C_STATE_LISTEN) || (hperh->state == ALD_I2C_STATE_READY)) + { + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + __LOCK(hperh); + + if ((READ_BIT(hperh->perh->CON1, I2C_CON1_PE_MSK) != I2C_CON1_PE_MSK)) + { + ALD_I2C_ENABLE(hperh); + } + + hperh->state = ALD_I2C_STATE_BUSY_RX_LISTEN; + hperh->mode = ALD_I2C_MODE_SLAVE; + hperh->error_code = ALD_I2C_ERROR_NONE; + + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + hperh->xfer_opt = option; + + __UNLOCK(hperh); + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_RXNE); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_ADDR); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_STOP); + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + ALD_I2C_ENABLE_IT(hperh, ALD_I2C_IT_RXNE | ALD_I2C_IT_ADDR | ALD_I2C_IT_STOP); + } + else + { + return ALD_BUSY; + } + + return ALD_OK; +} + +/** + * @brief Enable the Address listen mode whit Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param addr: Devaddress Target device address + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_abort_it(ald_i2c_handle_t *hperh, uint16_t addr) +{ + UNUSED(addr); + + if ((READ_BIT(hperh->perh->STAT, I2C_STAT_BUSY_MSK) != RESET) && (hperh->mode == ALD_I2C_MODE_MASTER)) + { + __LOCK(hperh); + + hperh->pre_state = ALD_I2C_STATE_NONE; + hperh->state = ALD_I2C_STATE_ABORT; + + SET_BIT(hperh->perh->CON1, I2C_CON2_STOP_MSK); + hperh->xfer_size = 0; + hperh->xfer_count = 0; + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_FLAG_MASK); + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + + __UNLOCK(hperh); + return ALD_OK; + } + else + { + return ALD_ERROR; + } +} + +/** + * @brief Enable the Address listen mode whit Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_enablelisten_it(ald_i2c_handle_t *hperh) +{ + if (hperh->state == ALD_I2C_STATE_READY) + { + hperh->state = ALD_I2C_STATE_LISTEN; + + if ((READ_BIT(hperh->perh->CON1, I2C_CON1_PE_MSK) != I2C_CON1_PE_MSK)) + { + ALD_I2C_ENABLE(hperh); + } + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_ADDR); + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + ALD_I2C_ENABLE_IT(hperh, ALD_I2C_IT_ADDR); + + return ALD_OK; + } + else + { + return ALD_BUSY; + } +} + +/** + * @brief Disable the Address listen mode whit Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_disablelisten_it(ald_i2c_handle_t *hperh) +{ + if (hperh->state == ALD_I2C_STATE_LISTEN) + { + hperh->pre_state = ((hperh->state) & ALD_I2C_STATE_MSK) | (hperh->mode); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_ADDR); + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + + return ALD_OK; + } + else + { + return ALD_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @note The maximum amount of data to be sent is 0xFF. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent (maximum is 0xFF) + * @param channel: DMA channel as I2C transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_send_by_dma(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint16_t size, uint8_t channel) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + if (size >= 0xFFFF) + size = 0xFFFF; + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_MASTER; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA; + + hperh->hdmatx.cplt_tc_cbk = i2c_dma_master_send_cplt; + hperh->hdmatx.cplt_tc_arg = hperh; + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + + SET_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src = (void *)hperh->p_buff; + hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDATA; + hperh->hdmatx.config.src_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.dst_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmatx.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? ALD_DMA_MSEL_I2C0 : ALD_DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = ALD_DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmatx); + + i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG); + + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2C receive + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_recv_by_dma(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint16_t size, uint8_t channel) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + if (size >= 0xFFFF) + size = 0xFFFF; + + hperh->state = ALD_I2C_STATE_BUSY_RX; + hperh->mode = ALD_I2C_MODE_MASTER; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA; + + hperh->hdmarx.cplt_tc_cbk = i2c_dma_master_recv_cplt; + hperh->hdmarx.cplt_tc_arg = (void *)hperh; + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + + SET_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src = (void *)&hperh->perh->RXDATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmatx.config.src_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.dst_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmarx.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? ALD_DMA_MSEL_I2C0 : ALD_DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = ALD_DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmarx); + + i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG); + + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + return ALD_OK; +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2C Transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_send_by_dma(ald_i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_SLAVE; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + if (size >= 0xFFFF) + size = 0xFFFF; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA; + + hperh->hdmatx.cplt_tc_cbk = i2c_dma_slave_send_cplt; + hperh->hdmatx.cplt_tc_arg = hperh; + + SET_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.dst_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmatx.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? ALD_DMA_MSEL_I2C0 : ALD_DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = ALD_DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmatx); + + if (i2c_wait_master_addr_to_timeout(hperh, ALD_I2C_IT_ADDR, I2C_TIMEOUT_ADDR_SLAVE) == ALD_ERROR) + { + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + } + + return ALD_OK; +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2C receive + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_recv_by_dma(ald_i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_RX; + hperh->mode = ALD_I2C_MODE_SLAVE; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + if (size >= 0xFF) + size = 0xFF; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA; + + hperh->hdmarx.cplt_tc_cbk = i2c_dma_slave_recv_cplt; + hperh->hdmarx.cplt_tc_arg = (void *)hperh; + + SET_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->RXDATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmatx.config.src_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.dst_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmarx.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? ALD_DMA_MSEL_I2C0 : ALD_DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = ALD_DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmarx); + + if (i2c_wait_master_addr_to_timeout(hperh, ALD_I2C_IT_ADDR, I2C_TIMEOUT_ADDR_SLAVE) == ALD_ERROR) + { + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + } + + return ALD_OK; +} + +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_write(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + ald_i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t nbyte = 0U; + + assert_param(IS_I2C_MEMADD_size(add_size)); + + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_MEM; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + nbyte = (add_size == ALD_I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, timeout) != ALD_OK) + goto ERROR; + + if (size <= 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + while (size > 0) + { + hperh->perh->TXDATA = (*buf++); + --size; + hperh->xfer_count++; + + if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) + { + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == ALD_OK) + { + if (size > 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + } + else + { + goto ERROR; + } + } + + if (i2c_wait_txe_to_timeout(hperh, timeout) != ALD_OK) + goto ERROR; + } + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK)) + goto SUCCESS; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TC, RESET, timeout)) + goto ERROR; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + goto SUCCESS; + +ERROR: + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + +SUCCESS: + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_read(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, ald_i2c_addr_size_t add_size, + uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t nbyte = 0U; + + assert_param(IS_I2C_MEMADD_size(add_size)); + + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_RX; + hperh->mode = ALD_I2C_MODE_MEM; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->xfer_count = 0; + hperh->xfer_size = size; + + nbyte = (add_size == ALD_I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, timeout) != ALD_OK) + return ALD_ERROR; + + if (size <= 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + while (size > 0) + { + if (i2c_wait_rxne_to_timeout(hperh, timeout) != ALD_OK) + goto ERROR; + + (*buf++) = hperh->perh->RXDATA; + size--; + hperh->xfer_count++; + + if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) + { + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TCR, RESET, timeout) == ALD_OK) + { + if (size > 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + } + else + { + goto ERROR; + } + } + } + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK)) + goto SUCCESS; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + goto SUCCESS; + +ERROR: + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + +SUCCESS: + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_write_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + ald_i2c_addr_size_t add_size, uint8_t *buf, uint32_t size) +{ + uint32_t nbyte = 0U; + + assert_param(IS_I2C_MEMADD_size(add_size)); + + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_MEM; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + nbyte = (add_size == ALD_I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != ALD_OK) + { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + } + + if (size <= 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TXE); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_NACK); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TC); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TCR); + + hperh->perh->TXDATA = (*hperh->p_buff++); + hperh->xfer_count++; + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_FLAG_MASK); + ALD_I2C_ENABLE_IT(hperh, ALD_I2C_IT_TXE | ALD_I2C_IT_NACK | ALD_I2C_IT_TC | ALD_I2C_IT_TCR); + + return ALD_OK; +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_read_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + ald_i2c_addr_size_t add_size, uint8_t *buf, uint32_t size) +{ + uint32_t nbyte = 0U; + + assert_param(IS_I2C_MEMADD_size(add_size)); + + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_RX; + hperh->mode = ALD_I2C_MODE_MEM; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + nbyte = (add_size == ALD_I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != ALD_OK) + { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + } + + if (size <= 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_RXNE); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TC); + ALD_I2C_CLEAR_IT(hperh, ALD_I2C_IT_TCR); + + ALD_I2C_ENABLE_IT(hperh, ALD_I2C_IT_RXNE | ALD_I2C_IT_TC | ALD_I2C_IT_TCR); + + SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + return ALD_OK; +} + +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address(Maxsiz 0xFF) + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_write_by_dma(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, ald_i2c_addr_size_t add_size, + uint8_t *buf, uint16_t size, uint8_t channel) +{ + uint32_t nbyte = 0U; + + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_MEMADD_size(add_size)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_TX; + hperh->mode = ALD_I2C_MODE_MASTER; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + nbyte = (add_size == ALD_I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != ALD_OK) + { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + return ALD_ERROR; + } + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA; + + hperh->hdmatx.cplt_tc_cbk = i2c_dma_mem_send_cplt; + hperh->hdmatx.cplt_tc_arg = hperh; + + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)hperh->p_buff; + hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.dst_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmatx.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? ALD_DMA_MSEL_I2C0 : ALD_DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = ALD_DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmatx); + + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + + SET_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + return ALD_OK; +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be read + * @param channel: DMA channel + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_read_by_dma(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, ald_i2c_addr_size_t add_size, + uint8_t *buf, uint16_t size, uint8_t channel) +{ + uint32_t nbyte = 0U; + + if (hperh->state != ALD_I2C_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != ALD_OK) + return ALD_BUSY; + + assert_param(IS_I2C_MEMADD_size(add_size)); + __LOCK(hperh); + + hperh->state = ALD_I2C_STATE_BUSY_RX; + hperh->mode = ALD_I2C_MODE_MEM; + hperh->error_code = ALD_I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + nbyte = (add_size == ALD_I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != ALD_OK) + { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + } + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA; + + hperh->hdmarx.cplt_tc_cbk = i2c_dma_mem_recv_cplt; + hperh->hdmarx.cplt_tc_arg = (void *)hperh; + + SET_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->RXDATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.src_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.dst_data_width = ALD_DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmarx.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? ALD_DMA_MSEL_I2C0 : ALD_DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = ALD_DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmarx); + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @} + */ + +/** @defgroup I2C_Public_Functions_Group3 Peripheral state and Errors functions + * @brief Peripheral state and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral state and Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval ald_status_t state + */ +ald_i2c_state_t ald_i2c_get_state(ald_i2c_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Return the I2C error code. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t ald_i2c_get_error(ald_i2c_handle_t *hperh) +{ + return hperh->error_code; +} +/** + * @} + */ + +/** @defgroup I2C_Public_Functions_Group4 IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void ald_i2c_ev_irq_handler(ald_i2c_handle_t *hperh) +{ + uint32_t size = hperh->xfer_size - hperh->xfer_count; + + /**< Transmit empty interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TXE) == SET) + { + if ((hperh->mode == ALD_I2C_MODE_MASTER) || (hperh->mode == ALD_I2C_MODE_MEM)) + { + i2c_master_send_txe(hperh); + } + else if (hperh->mode == ALD_I2C_MODE_SLAVE) + { + i2c_slave_send_txe(hperh); + } + + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TXE); + } + + /**< Receive not empty interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_RXNE) == SET) + { + if ((hperh->mode == ALD_I2C_MODE_MASTER) || (hperh->mode == ALD_I2C_MODE_MEM)) + { + i2c_master_recv_rxne(hperh); + } + else if (hperh->mode == ALD_I2C_MODE_SLAVE) + { + i2c_slave_recv_rxne(hperh); + } + + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_RXNE); + } + + /**< Transmit completed interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TC) == SET) + { + if ((hperh->mode == ALD_I2C_MODE_MASTER) || (hperh->mode == ALD_I2C_MODE_MEM)) + { + if (ALD_I2C_MASTER_GET_DIR(hperh) == RESET) + { + i2c_master_send_tc(hperh); + } + else + { + i2c_master_recv_tc(hperh); + } + } + + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TC); + } + + /**< Transmit and reload completed interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TCR) == SET) + { + if (size > 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TCR); + } + + /**< Address matching interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_ADDR) == SET) + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_ADDR); + + /**< Stop detection interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_STOP) == SET) + { + i2c_slave_stopf(hperh); + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_STOP); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hperh: pointer to a i2c_handle_t structure that contains + * the configuration information for I2C module + * @retval NONE + */ +void ald_i2c_er_irq_handler(ald_i2c_handle_t *hperh) +{ + /**< Transmit overrun interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TXOV) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TXOV); + hperh->error_code |= ALD_I2C_ERROR_TOV; + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); + } + + /**< Transmit underrun */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TXUD) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TXUD); + hperh->error_code |= ALD_I2C_ERROR_TUD; + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); + } + + /**< Receive overrun interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_RXOV) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_RXOV); + hperh->error_code |= ALD_I2C_ERROR_ROV; + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); + } + + /**< Receive underrun interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_RXUD) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_RXUD); + hperh->error_code |= ALD_I2C_ERROR_RUD; + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); + } + + /**< NACK interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_NACK) == SET) + { + if (hperh->xfer_count != hperh->xfer_size) + { + hperh->state |= ALD_I2C_ERROR_AF; + } + else + { + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_TXE | ALD_I2C_IT_NACK); + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_NACK); + return; + } + + if ((hperh->mode == ALD_I2C_MODE_MASTER) || (hperh->mode == ALD_I2C_MODE_MEM)) + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_TXE | ALD_I2C_IT_NACK); + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_NACK); + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); + } + + /**< Bus error interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_BERR) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_BERR); + hperh->state |= ALD_I2C_ERROR_BERR; + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); + } + + /**< Arbitration loss interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_ARLO) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_ARLO); + hperh->state |= ALD_I2C_ERROR_ARLO; + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); + } + + /**< PEC error interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_PECE) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_PECE); + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); + } + + /**< Timeout interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TOUT) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TOUT); + hperh->state |= ALD_I2C_ERROR_TIMEOUT; + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); + } + + /**< SMBus Alert interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_ALERT) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_ALERT); + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); + } +} + +/** + * @brief This function handles I2C event interrupt request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void ald_i2c_seq_ev_irq_handler(ald_i2c_handle_t *hperh) +{ + uint32_t size = hperh->xfer_size - hperh->xfer_count; + ald_i2c_state_t current_state = hperh->state; + uint32_t current_opt = hperh->xfer_opt; + uint8_t tmp = 0U; + + /**< Address matching interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_ADDR) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_ADDR); + + if ((hperh->state & ALD_I2C_STATE_LISTEN) == ALD_I2C_STATE_LISTEN) + { + if (hperh->addr_cplt_cbk != NULL) + hperh->addr_cplt_cbk(hperh); + + if (hperh->state == ALD_I2C_STATE_BUSY_TX_LISTEN) + hperh->state = ALD_I2C_STATE_BUSY_TX; + + if (hperh->state == ALD_I2C_STATE_BUSY_RX_LISTEN) + hperh->state = ALD_I2C_STATE_BUSY_RX; + } + } + + /**< Transmit empty interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TXE) == SET) + { + if (hperh->mode == ALD_I2C_MODE_MASTER) + { + if ((hperh->xfer_size == 0) && (current_state == ALD_I2C_STATE_BUSY_TX)) + { + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_TXE | ALD_I2C_IT_NACK | ALD_I2C_IT_TC | ALD_I2C_IT_TCR); + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + + if ((current_opt != ALD_I2C_LAST_FRAME) && (current_opt != ALD_I2C_FIRST_AND_LAST_FRAME) && (current_opt != ALD_I2C_OTHER_AND_LAST_FRAME)) + { + hperh->pre_state = ALD_I2C_STATE_BUSY_TX; + __UNLOCK(hperh); + } + else + { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->pre_state = (uint32_t)ALD_I2C_STATE_NONE; + + __UNLOCK(hperh); + } + + if (hperh->master_tx_cplt_cbk != NULL) + hperh->master_tx_cplt_cbk(hperh); + } + + if (hperh->xfer_count != hperh->xfer_size) + { + hperh->perh->TXDATA = (*hperh->p_buff++); + hperh->xfer_count++; + } + } + else if (hperh->mode == ALD_I2C_MODE_SLAVE) + { + if (hperh->xfer_size > hperh->xfer_count) + { + while (hperh->perh->STAT & (0x1 << 1)); + + hperh->perh->TXDATA = (*hperh->p_buff++); + hperh->xfer_count++; + } + } + + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TXE); + } + + /**< Receive not empty interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_RXNE) == SET) + { + if ((hperh->state == ALD_I2C_STATE_BUSY_RX) || (hperh->state == ALD_I2C_STATE_BUSY_RX_LISTEN)) + { + if (hperh->xfer_size - hperh->xfer_count > 0) + { + (*hperh->p_buff++) = hperh->perh->RXDATA; + hperh->xfer_count++; + } + else + { + tmp = hperh->perh->RXDATA; + UNUSED(tmp); + } + } + + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_RXNE); + } + + /**< Transmit completed interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TC) == SET) + { + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_TC | ALD_I2C_IT_TCR); + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + + hperh->pre_state = ALD_I2C_STATE_NONE; + hperh->mode = ALD_I2C_MODE_NONE; + hperh->state = ALD_I2C_STATE_READY; + __UNLOCK(hperh); + + if (current_state == ALD_I2C_STATE_MASTER_BUSY_TX) + { + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_TXE | ALD_I2C_IT_NACK); + + if (hperh->master_tx_cplt_cbk != NULL) + hperh->master_tx_cplt_cbk(hperh); + } + else if (current_state == ALD_I2C_STATE_SLAVE_BUSY_TX) + { + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_TXE | ALD_I2C_IT_NACK); + + if (hperh->slave_tx_cplt_cbk != NULL) + hperh->slave_tx_cplt_cbk(hperh); + } + else if (current_state == ALD_I2C_STATE_MASTER_BUSY_RX) + { + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_RXNE); + + if (hperh->master_rx_cplt_cbk != NULL) + hperh->master_rx_cplt_cbk(hperh); + } + else if (current_state == ALD_I2C_STATE_SLAVE_BUSY_RX) + { + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_RXNE); + + if (hperh->slave_rx_cplt_cbk != NULL) + hperh->slave_rx_cplt_cbk(hperh); + } + + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TC); + } + + /**< Transmit and reload completed interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TCR) == SET) + { + if (size == 0) + { + if (current_state == ALD_I2C_STATE_BUSY_TX) + { + if (hperh->mode == ALD_I2C_MODE_MASTER) + hperh->pre_state = ALD_I2C_STATE_MASTER_BUSY_TX; + else + hperh->pre_state = ALD_I2C_STATE_SLAVE_BUSY_TX; + + hperh->mode = ALD_I2C_MODE_NONE; + hperh->state = ALD_I2C_STATE_READY; + __UNLOCK(hperh); + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_TXE | ALD_I2C_IT_NACK | ALD_I2C_IT_TCR); + + if (hperh->master_tx_cplt_cbk != NULL) + hperh->master_tx_cplt_cbk(hperh); + } + else if (current_state == ALD_I2C_STATE_BUSY_RX) + { + if (hperh->mode == ALD_I2C_MODE_MASTER) + hperh->pre_state = ALD_I2C_STATE_MASTER_BUSY_RX; + else + hperh->pre_state = ALD_I2C_STATE_SLAVE_BUSY_RX; + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_RXNE | ALD_I2C_IT_TCR); + + if (hperh->master_rx_cplt_cbk != NULL) + hperh->master_rx_cplt_cbk(hperh); + } + } + else + { + if (size > 0xFFFF) + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, 0xFF << I2C_CON1_NBYTES_POSS); + } + else + { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, (size & 0xFF) << I2C_CON2_NBYTES_POSS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NBYTES_MSK, (size >> 8) << I2C_CON1_NBYTES_POSS); + + if ((current_opt == ALD_I2C_FIRST_AND_LAST_FRAME) || (current_opt == ALD_I2C_LAST_FRAME) || (current_opt == ALD_I2C_OTHER_AND_LAST_FRAME)) + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + } + + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TCR); + } + + /**< Stop detection interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_STOP) == SET) + { + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_ADDR | ALD_I2C_IT_NACK | ALD_I2C_IT_RXNE | ALD_I2C_IT_TXE | ALD_I2C_IT_STOP); + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_STOP); + + if ((size == 0) && (hperh->error_code == ALD_I2C_ERROR_NONE)) + { + if (hperh->state == ALD_I2C_STATE_BUSY_TX_LISTEN) + { + hperh->pre_state = ALD_I2C_STATE_BUSY_TX_LISTEN; + hperh->state = ALD_I2C_STATE_LISTEN; + hperh->mode = ALD_I2C_MODE_NONE; + + if (hperh->slave_tx_cplt_cbk != NULL) + hperh->slave_tx_cplt_cbk(hperh); + } + + if (hperh->state == ALD_I2C_STATE_BUSY_RX_LISTEN) + { + hperh->pre_state = ALD_I2C_STATE_SLAVE_BUSY_RX; + hperh->state = ALD_I2C_STATE_LISTEN; + hperh->mode = ALD_I2C_MODE_NONE; + + if (hperh->slave_rx_cplt_cbk != NULL) + hperh->slave_rx_cplt_cbk(hperh); + } + + if (hperh->state == ALD_I2C_STATE_LISTEN) + { + hperh->xfer_opt = ALD_I2C_NO_OPTION_FRAME; + hperh->pre_state = ALD_I2C_STATE_NONE; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + + if (hperh->listen_cplt_cbk != NULL) + hperh->listen_cplt_cbk(hperh); + } + } + } +} + + +/** + * @brief This function handles I2C error interrupt request. + * @param hperh: pointer to a i2c_handle_t structure that contains + * the configuration information for I2C module + * @retval NONE + */ +void ald_i2c_seq_er_irq_handler(ald_i2c_handle_t *hperh) +{ + /**< Transmit overrun interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TXOV) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TXOV); + hperh->error_code |= ALD_I2C_ERROR_TOV; + } + + /**< Transmit underrun */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TXUD) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TXUD); + hperh->error_code |= ALD_I2C_ERROR_TUD; + } + + /**< Receive overrun interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_RXOV) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_RXOV); + hperh->error_code |= ALD_I2C_ERROR_ROV; + } + + /**< Receive underrun interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_RXUD) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_RXUD); + hperh->error_code |= ALD_I2C_ERROR_RUD; + } + + /**< NACK interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_NACK) == SET) + { + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_TXE | ALD_I2C_IT_NACK); + + if ((hperh->mode == ALD_I2C_MODE_SLAVE) && (hperh->xfer_count == hperh->xfer_size) && \ + ((hperh->state == ALD_I2C_STATE_BUSY_TX) || (hperh->state == ALD_I2C_STATE_BUSY_TX_LISTEN) || \ + ((hperh->state == ALD_I2C_STATE_LISTEN) && (hperh->pre_state == ALD_I2C_STATE_SLAVE_BUSY_TX)))) + { + if (((hperh->xfer_opt == ALD_I2C_FIRST_AND_LAST_FRAME) || (hperh->xfer_opt == ALD_I2C_LAST_FRAME)) && \ + (hperh->state == ALD_I2C_STATE_LISTEN)) + { + hperh->pre_state = ALD_I2C_STATE_NONE; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + + if (hperh->listen_cplt_cbk != NULL) + hperh->listen_cplt_cbk(hperh); + + } + else if (hperh->state == ALD_I2C_STATE_BUSY_TX) + { + hperh->xfer_opt = ALD_I2C_NO_OPTION_FRAME; + hperh->pre_state = ALD_I2C_STATE_SLAVE_BUSY_TX; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + + if (hperh->slave_tx_cplt_cbk != NULL) + hperh->slave_tx_cplt_cbk(hperh); + } + } + else + { + hperh->error_code |= ALD_I2C_ERROR_AF; + + if (hperh->mode == ALD_I2C_MODE_MASTER) + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + } + + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_NACK); + } + + /**< Bus error interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_BERR) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_BERR); + hperh->state |= ALD_I2C_ERROR_BERR; + } + + /**< Arbitration loss interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_ARLO) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_ARLO); + hperh->state |= ALD_I2C_ERROR_ARLO; + } + + /**< PEC error interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_PECE) == SET) + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_PECE); + + /**< Timeout interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_TOUT) == SET) + { + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TOUT); + hperh->state |= ALD_I2C_ERROR_TIMEOUT; + } + + /**< SMBus Alert interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, ALD_I2C_IT_ALERT) == SET) + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_ALERT); + + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); +} + +/** + * @brief Enable/disable the specified I2C interrupts. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param it: Specifies the i2c interrupt sources to be enabled or disabled. + * @param state: New state of the specified I2C interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_i2c_interrupt_config(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t it, type_func_t state) +{ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + hperh->perh->IER = it; + else + hperh->perh->IDR = it; + + return; +} + +/** + * @brief Get the status of I2C interrupt source. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param it: Specifies the I2C interrupt source. + * This parameter can be one of the @ref i2c_interrupt_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_i2c_get_it_status(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t it) +{ + it_status_t status = RESET; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT(it)); + + if (hperh->perh->IVS & it) + status = SET; + + return status; +} + +/** + * @brief Get the status of I2C interrupt flag. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param flag: Specifies the I2C interrupt flag. + * This parameter can be one of the @ref i2c_interrupt_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_i2c_get_flag_status(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t flag) +{ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + + +/** + * @brief Get the status of interrupt flag and interupt source. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param flag: Specifies the I2C interrupt flag. + * This parameter can be one of the @ref i2c_interrupt_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_i2c_get_mask_flag_status(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t flag) +{ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT(flag)); + + if (hperh->perh->IFM & flag) + return SET; + + return RESET; +} + +/** + * @brief Clear the I2C interrupt flag. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param flag: Specifies the I2C interrupt flag. + * @retval None + */ +void ald_i2c_clear_flag_status(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t flag) +{ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT(flag)); + + hperh->perh->ICR = flag; + return; +} + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Handle transmit complete flag for Master Transmit mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_send_tc(ald_i2c_handle_t *hperh) +{ + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_TXE | ALD_I2C_IT_NACK | ALD_I2C_IT_TC | ALD_I2C_IT_TCR); + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK) == RESET) + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + + __UNLOCK(hperh); + hperh->state = ALD_I2C_STATE_READY; + + if (hperh->mode == ALD_I2C_MODE_MEM) + { + if (hperh->mem_tx_cplt_cbk) + hperh->mem_tx_cplt_cbk(hperh); + } + else + { + if (hperh->master_tx_cplt_cbk) + hperh->master_tx_cplt_cbk(hperh); + } + + return ALD_OK; +} + +/** + * @brief Handle transmit empty flag for Master Transmit mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_send_txe(ald_i2c_handle_t *hperh) +{ + if (hperh->xfer_count != hperh->xfer_size) + { + hperh->perh->TXDATA = (*hperh->p_buff++); + hperh->xfer_count++; + } + + return ALD_OK; +} + +/** + * @brief Handle receive complete for Master Receive mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_recv_tc(ald_i2c_handle_t *hperh) +{ + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_RXNE | ALD_I2C_IT_TCR | ALD_I2C_IT_TC); + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK) == RESET) + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + + __UNLOCK(hperh); + hperh->state = ALD_I2C_STATE_READY; + + if (hperh->mode == ALD_I2C_MODE_MEM) + { + if (hperh->mem_rx_cplt_cbk) + hperh->mem_rx_cplt_cbk(hperh); + } + else + { + if (hperh->master_rx_cplt_cbk) + hperh->master_rx_cplt_cbk(hperh); + } + + return ALD_OK; +} + +/** + * @brief Handle receive not empty for Master Receive mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_recv_rxne(ald_i2c_handle_t *hperh) +{ + if (hperh->xfer_size - hperh->xfer_count > 0) + { + (*hperh->p_buff++) = hperh->perh->RXDATA; + hperh->xfer_count++; + } + else + { + return ALD_OK; + } + + return ALD_OK; +} + +/** + * @brief Handle TXE flag for Slave Transmit mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_slave_send_txe(ald_i2c_handle_t *hperh) +{ + if (hperh->xfer_size > hperh->xfer_count) + { + hperh->perh->TXDATA = (*hperh->p_buff++); + hperh->xfer_count++; + } + + return ALD_OK; +} + +/** + * @brief Handle RXNE flag for Slave Receive mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_slave_recv_rxne(ald_i2c_handle_t *hperh) +{ + if (hperh->xfer_size > hperh->xfer_count) + { + (*hperh->p_buff++) = hperh->perh->RXDATA; + hperh->xfer_count++; + } + else + { + return ALD_OK; + } + + return ALD_OK; +} + +/** + * @brief Handle STOPF flag for Slave mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_slave_stopf(ald_i2c_handle_t *hperh) +{ + ALD_I2C_DISABLE_IT(hperh, ALD_I2C_IT_ADDR | ALD_I2C_IT_NACK | ALD_I2C_IT_RXNE | ALD_I2C_IT_TXE | ALD_I2C_IT_STOP); + + hperh->mode = ALD_I2C_MODE_NONE; + hperh->error_code = ALD_I2C_ERROR_NONE; + __UNLOCK(hperh); + + if (hperh->state == ALD_I2C_STATE_BUSY_TX) + { + hperh->state = ALD_I2C_STATE_READY; + + if ((hperh->slave_tx_cplt_cbk) && (hperh->xfer_count != 0)) + hperh->slave_tx_cplt_cbk(hperh); + } + else if (hperh->state == ALD_I2C_STATE_BUSY_RX) + { + hperh->state = ALD_I2C_STATE_READY; + + if ((hperh->slave_rx_cplt_cbk) && (hperh->xfer_count != 0)) + hperh->slave_rx_cplt_cbk(hperh); + } + else + { + + } + + return ALD_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_req_write(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout) +{ + if (hperh->init.addr_mode == ALD_I2C_ADDR_7BIT) + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK); + else + SET_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK); + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_SADD_MSK, dev_addr << I2C_CON2_SADD_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + + return ALD_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_req_read(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout) +{ + if (hperh->init.addr_mode == ALD_I2C_ADDR_7BIT) + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK); + else + SET_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK); + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_SADD_MSK, dev_addr << I2C_CON2_SADD_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + + return ALD_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_req_mem_write(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout) +{ + uint32_t tmp = hperh->perh->CON2; + i2c_master_req_write(hperh, dev_addr, timeout); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + if (add_size == ALD_I2C_MEMADD_SIZE_8BIT) + { + hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr); + } + else + { + hperh->perh->TXDATA = I2C_MEM_ADD_MSB(mem_addr); + + if (i2c_wait_txe_to_timeout(hperh, timeout) != ALD_OK) + return ALD_ERROR; + + hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr); + } + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TCR, RESET, timeout) != ALD_OK) + { + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TCR); + return ALD_ERROR; + } + + ald_i2c_clear_flag_status(hperh, ALD_I2C_IT_TCR); + + if ((hperh->state == ALD_I2C_STATE_BUSY_RX) && (hperh->mode == ALD_I2C_MODE_MEM)) + { + tmp = hperh->perh->CON2; + tmp &= ~(I2C_CON2_RELOAD_MSK | I2C_CON2_NBYTES_MSK); + hperh->perh->CON2 = tmp; + + tmp = hperh->perh->CON1; + tmp &= ~I2C_CON1_NBYTES_MSK; + hperh->perh->CON1 = tmp; + } + + return ALD_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_req_mem_read(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout) +{ + uint32_t tim_count = 0U; + + if (i2c_master_req_write(hperh, dev_addr, timeout) != ALD_OK) + { + __UNLOCK(hperh); + return ALD_ERROR; + } + + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + if (add_size == ALD_I2C_MEMADD_SIZE_8BIT) + { + hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr); + } + else + { + hperh->perh->TXDATA = I2C_MEM_ADD_MSB(mem_addr); + + if (i2c_wait_txe_to_timeout(hperh, timeout) != ALD_OK) + { + if (hperh->error_code == ALD_I2C_ERROR_AF) + { + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + return ALD_ERROR; + } + else + { + return ALD_TIMEOUT; + } + } + + hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr); + } + + while (!ALD_I2C_GET_FLAG(hperh, ALD_I2C_STAT_TXE)) + { + tim_count++; + + if (tim_count > 0xFFFF) + return ALD_TIMEOUT; + } + + return ALD_OK; +} + +/** +* @brief DMA I2C master transmit process complete callback. +* @param argv: I2C handle +* @retval None +*/ +static void i2c_dma_master_send_cplt(void *argv) +{ + ald_i2c_handle_t *hperh = (ald_i2c_handle_t *)argv; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == ALD_ERROR) + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != ALD_I2C_ERROR_NONE) + { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else + { + if (hperh->master_tx_cplt_cbk) + hperh->master_tx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_slave_send_cplt(void *argv) +{ + ald_i2c_handle_t *hperh = (ald_i2c_handle_t *)argv; + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != ALD_I2C_ERROR_NONE) + { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else + { + if (hperh->slave_tx_cplt_cbk) + hperh->slave_tx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C master receive process complete callback + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_master_recv_cplt(void *argv) +{ + ald_i2c_handle_t *hperh = (ald_i2c_handle_t *)argv; + + if (i2c_wait_flag_change_to_timeout(hperh, ALD_I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == ALD_ERROR) + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != ALD_I2C_ERROR_NONE) + { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else + { + if (hperh->master_rx_cplt_cbk) + hperh->master_rx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C slave receive process complete callback. + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_slave_recv_cplt(void *argv) +{ + ald_i2c_handle_t *hperh = (ald_i2c_handle_t *)argv; + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != ALD_I2C_ERROR_NONE) + { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else + { + if (hperh->slave_rx_cplt_cbk) + hperh->slave_rx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C Memory Write process complete callback + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_mem_send_cplt(void *argv) +{ + uint32_t cnt = 0xFFFFFFU; + + ald_i2c_handle_t *hperh = (ald_i2c_handle_t *)argv; + + while (cnt--) + { + if ((hperh->perh->STAT & ALD_I2C_STAT_TC) != 0) + break; + } + + if (cnt == 0) + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != ALD_I2C_ERROR_NONE) + { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else + { + if (hperh->mem_tx_cplt_cbk) + hperh->mem_tx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C Memory Read process complete callback + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_mem_recv_cplt(void *argv) +{ + uint32_t cnt = 0xFFFFFU; + + ald_i2c_handle_t *hperh = (ald_i2c_handle_t *)argv; + + while (cnt--) + { + if ((hperh->perh->STAT & ALD_I2C_STAT_TC) != 0) + break; + } + + if (cnt == 0) + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = ALD_I2C_STATE_READY; + hperh->mode = ALD_I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != ALD_I2C_ERROR_NONE) + { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else + { + if (hperh->mem_rx_cplt_cbk) + hperh->mem_rx_cplt_cbk(hperh); + } +} + +/** + * @brief This function handles I2C Communication timeout. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param flag: specifies the I2C flag to check. + * @param status: The checked flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_flag_change_to_timeout(ald_i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tickstart = 0U; + + tickstart = ald_get_tick(); + + if (status == RESET) + { + while (ALD_I2C_GET_FLAG(hperh, flag) == RESET) + { + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) + { + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + return ALD_TIMEOUT; + } + } + } + else + { + while (ALD_I2C_GET_FLAG(hperh, flag) != RESET) + { + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) + { + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + return ALD_TIMEOUT; + } + } + } + + return ALD_OK; +} + +/** + * @brief This function handles I2C Communication timeout for Master addressing phase. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param flag: specifies the I2C flag to check. + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_master_addr_to_timeout(ald_i2c_handle_t *hperh, uint32_t flag, uint32_t timeout) +{ + uint32_t tickstart = ald_get_tick(); + + while (ALD_I2C_GET_IT_FLAG(hperh, flag) == RESET) + { + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) + { + hperh->error_code = ALD_I2C_ERROR_TIMEOUT; + + return ALD_ERROR; + } + } + + return ALD_OK; +} + +/** + * @brief This function handles I2C Communication timeout for specific usage of TXE flag. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_txe_to_timeout(ald_i2c_handle_t *hperh, uint32_t timeout) +{ + uint32_t tickstart = ald_get_tick(); + + while (ALD_I2C_GET_FLAG(hperh, ALD_I2C_STAT_TXE) == RESET) + { + if (ALD_I2C_GET_IT_FLAG(hperh, ALD_I2C_IT_ARLO)) + { + hperh->error_code |= ALD_I2C_ERROR_ARLO; + return ALD_ERROR; + } + + if (ALD_I2C_GET_IT_FLAG(hperh, ALD_I2C_IT_NACK) == SET) + { + hperh->error_code |= ALD_I2C_ERROR_AF; + return ALD_ERROR; + } + + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) + { + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + return ALD_ERROR; + } + } + + return ALD_OK; +} + +/** + * @brief This function handles I2C Communication timeout for specific usage of RXNE flag. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_rxne_to_timeout(ald_i2c_handle_t *hperh, uint32_t timeout) +{ + uint32_t tickstart = ald_get_tick(); + + while (ALD_I2C_GET_FLAG(hperh, ALD_I2C_STAT_RXNE) == RESET) + { + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) + { + hperh->error_code |= ALD_I2C_ERROR_TIMEOUT; + return ALD_ERROR; + } + } + + return ALD_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_i2c.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_i2c.h new file mode 100644 index 0000000000..9078d25e06 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_i2c.h @@ -0,0 +1,557 @@ +/** + ********************************************************************************* + * + * @file ald_i2c.h + * @brief Header file of I2C driver + * + * @version V1.0 + * @date 24 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 24 Feb. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_I2C_H__ +#define __ALD_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ + +#include +#include "ald_cmu.h" +#include "ald_dma.h" + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Constants -------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup I2C_Public_Types I2C Public Types + * @{ + */ +/** + * @brief I2C Error Code + */ +typedef enum +{ + ALD_I2C_ERROR_NONE = 0x0U, /**< No error */ + ALD_I2C_ERROR_BERR = 0x1U, /**< Berr error */ + ALD_I2C_ERROR_ARLO = 0x2U, /**< Arlo error */ + ALD_I2C_ERROR_RUD = 0x4U, /**< Rx underflow error */ + ALD_I2C_ERROR_AF = 0x8U, /**< Af error */ + ALD_I2C_ERROR_ROV = 0x10U, /**< Rx overflow error */ + ALD_I2C_ERROR_RF = 0x20U, /**< Rx full error */ + ALD_I2C_ERROR_TUD = 0x40U, /**< Tx underflow error */ + ALD_I2C_ERROR_TOV = 0x80U, /**< Tx overflow error */ + ALD_I2C_ERROR_TE = 0x100U, /**< Tx empty error */ + ALD_I2C_ERROR_DMA = 0x200U, /**< Dma error */ + ALD_I2C_ERROR_TIMEOUT = 0x400U, /**< Timeout error */ +} ald_i2c_error_t; + +/** + * @brief I2C state structure definition + */ +typedef enum +{ + ALD_I2C_STATE_RESET = 0x0U, /**< Peripheral is not yet Initialized */ + ALD_I2C_STATE_READY = 0x20U, /**< Peripheral Initialized and ready for use */ + ALD_I2C_STATE_BUSY = 0x24U, /**< An internal process is ongoing */ + ALD_I2C_STATE_BUSY_TX = 0x21U, /**< Data Transmission process is ongoing */ + ALD_I2C_STATE_BUSY_RX = 0x22U, /**< Data Reception process is ongoing */ + + ALD_I2C_STATE_LISTEN = 0x28U, /**< Address Listen */ + ALD_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /**< Address Listen and Data Transmission */ + ALD_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /**< Address Listen and Data Receive */ + + ALD_I2C_STATE_ABORT = 0x60U, /**< Abort user request */ + ALD_I2C_STATE_TIMEOUT = 0xA0U, /**< timeout state */ + ALD_I2C_STATE_ERROR = 0xE0U, /**< Error */ +} ald_i2c_state_t; + +/** + * @brief I2C Addressing Mode + */ +typedef enum +{ + ALD_I2C_ADDR_7BIT = 0x0U, /**< 7 bit address */ + ALD_I2C_ADDR_10BIT = 0x1U, /**< 10 bit address */ +} ald_i2c_addr_t; + +/** + * @brief I2C Dual Addressing Mode + */ +typedef enum +{ + ALD_I2C_DUALADDR_DISABLE = 0x0U, /**< dual address is disable */ + ALD_I2C_DUALADDR_ENABLE = 0x1U, /**< dual address is enable */ +} ald_i2c_dual_addr_t; + +/** + * @brief I2C General Call Addressing mode + */ +typedef enum +{ + ALD_I2C_GENERALCALL_DISABLE = 0x0U, /**< general call address is disable */ + ALD_I2C_GENERALCALL_ENABLE = 0x1U, /**< general call address is enable */ +} ald_i2c_general_addr_t; + +/** + * @brief I2C Nostretch Mode + */ +typedef enum +{ + ALD_I2C_NOSTRETCH_DISABLE = 0x0U, /**< Nostretch disable */ + ALD_I2C_NOSTRETCH_ENABLE = 0x1U, /**< Nostretch enable */ +} ald_i2c_nostretch_t; + +/** + * @brief I2C Memory Address Size + */ +typedef enum +{ + ALD_I2C_MEMADD_SIZE_8BIT = 0x8U, /**< 8 bit memory address size */ + ALD_I2C_MEMADD_SIZE_16BIT = 0x10U, /**< 10 bit memory address size */ +} ald_i2c_addr_size_t; + +/** + * @brief I2C mode structure definition + */ +typedef enum +{ + ALD_I2C_MODE_NONE = 0x0U, /**< No I2C communication on going */ + ALD_I2C_MODE_MASTER = 0x10U, /**< I2C communication is in Master mode */ + ALD_I2C_MODE_SLAVE = 0x20U, /**< I2C communication is in Slave mode */ + ALD_I2C_MODE_MEM = 0x40U, /**< I2C communication is in Memory mode */ +} ald_i2c_mode_t; + +/** + * @brief I2C Clock + */ +typedef enum +{ + ALD_I2C_STANDARD_MODE_MAX_CLK = 100000U, /**< Standard mode clock */ + ALD_I2C_FAST_MODE_MAX_CLK = 400000U, /**< Fast mode clock */ + ALD_I2C_EXTREME_FAST_MODE_MAX_CLK = 1000000U, /**< Extreme mode clock */ +} ald_i2c_clock_t; + +/** + * @brief I2C OAR2 Register + */ +typedef enum +{ + ALD_I2C_OAR2_ENDUAL = (1U << 0), /**< ENDUAL BIT */ + ALD_I2C_OAR2_ADD2 = (1U << 1) /**< ADD2 BIT */ +} ald_i2c_oar2_t; + +/** + * @brief I2C CON1 Register + */ +typedef enum +{ + ALD_I2C_CON1_PE = (1U << 0), /**< Peripheral enable BIT */ + ALD_I2C_CON1_TXDMA = (1U << 14), /**< Transmit DMA BIT */ + ALD_I2C_CON1_RXDMA = (1U << 15), /**< Receive DMA BIT */ + ALD_I2C_CON1_SBC = (1U << 16), /**< Receive DMA BIT */ + ALD_I2C_CON1_NOSTRETCH = (1U << 17), /**< Slave bytes control BIT */ + ALD_I2C_CON1_GCEN = (1U << 19), /**< General call BIT */ + ALD_I2C_CON1_SMBHEN = (1U << 20), /**< SMBus slave device enable BIT */ + ALD_I2C_CON1_SMBDEN = (1U << 21), /**< SMBus master device enable BIT */ + ALD_I2C_CON1_ALERTEN = (1U << 22), /**< SMBus alert device enable BIT */ + ALD_I2C_CON1_PECEN = (1U << 23), /**< PEC enable BIT */ +} ald_i2c_con1_t; + +/** + * @brief I2C CON2 Register + */ +typedef enum +{ + ALD_I2C_CON2_RD_WRN = (1U << 10), /**< Master R/W control BIT */ + ALD_I2C_CON2_ADD10 = (1U << 11), /**< 10bit address control BIT */ + ALD_I2C_CON2_HEAD10R = (1U << 12), /**< 10bit address master Receive control BIT */ + ALD_I2C_CON2_START = (1U << 13), /**< Master start singal control BIT */ + ALD_I2C_CON2_STOP = (1U << 14), /**< Master stop singal control BIT */ + ALD_I2C_CON2_NACK = (1U << 15), /**< Master Nack control BIT */ + ALD_I2C_CON2_RELOAD = (1U << 24), /**< Master communication reload control BIT */ + ALD_I2C_CON2_AUTOEND = (1U << 25), /**< Master Autoend control BIT */ + ALD_I2C_CON2_PECBYTE = (1U << 26), /**< PEC control BIT */ + ALD_I2C_CON2_HOLDACK = (1U << 28), /**< Hold ack control BIT */ +} ald_i2c_con2_t; + +/** + * @brief I2C ADDR1 Register + */ +typedef enum +{ + ALD_I2C_OA1MODE = (1U << 10), /**< Addr1 bits choose BIT */ + ALD_I2C_OA1EN = (1U << 15), /**< Addr1 enable BIT */ +} ald_i2c_addr1_t; + +/** + * @brief I2C ADDR2 Register + */ +typedef enum +{ + ALD_I2C_OA2EN = (1U << 15), /**< Addr2 enable BIT */ +} ald_i2c_addr2_t; + +/** + * @brief I2C TIMEOUTR Register + */ +typedef enum +{ + ALD_I2C_TIMEOUTR_TIDLE = (1U << 12), /**< SCL idle check enable BIT */ + ALD_I2C_TIMEOUTR_TIMEOUTEN = (1U << 15), /**< Timeout enable BIT */ +} ald_i2c_timoutr_t; + +/** + * @brief I2C peripherals module + */ +typedef enum +{ + ALD_I2C_MODULE_MASTER = (1U << 0), /**< Master module */ + ALD_I2C_MODULE_SLAVE = (1U << 1) /**< Slave module */ +} ald_i2c_module_t; + +/** + * @brief I2C STAT Register + */ +typedef enum +{ + ALD_I2C_STAT_TXE = (1U << 0), /**< Transmit empty flag */ + ALD_I2C_STAT_TXOV = (1U << 2), /**< Transmit overrun flag */ + ALD_I2C_STAT_TXUD = (1U << 3), /**< Transmit underrun flag */ + ALD_I2C_STAT_RXNE = (1U << 5), /**< Receive not empty flag */ + ALD_I2C_STAT_RXOV = (1U << 7), /**< Receive overrun flag */ + ALD_I2C_STAT_RXUD = (1U << 8), /**< Receive underrun flag */ + ALD_I2C_STAT_TC = (1U << 10), /**< Transmit completed flag */ + ALD_I2C_STAT_TCR = (1U << 11), /**< Transmit and reload completed flag */ + ALD_I2C_STAT_BUSY = (1U << 15), /**< Bus status busy flag */ + ALD_I2C_STAT_DIR = (1U << 16), /**< Slave R/W flag */ +} ald_i2c_stat_t; + +/** + * @brief Interrupt Configuration Definition + */ +typedef enum +{ + ALD_I2C_IT_TXE = (1U << 0), /**< Transmit empty interrupt */ + ALD_I2C_IT_TXOV = (1U << 2), /**< Transmit overrun interrupt */ + ALD_I2C_IT_TXUD = (1U << 3), /**< Transmit underrun interrupt */ + ALD_I2C_IT_RXNE = (1U << 5), /**< Receive not empty interrupt */ + ALD_I2C_IT_RXOV = (1U << 7), /**< Receive overrun interrupt */ + ALD_I2C_IT_RXUD = (1U << 8), /**< Receive underrun interrupt */ + ALD_I2C_IT_TC = (1U << 10), /**< Transmit completed interrupt */ + ALD_I2C_IT_TCR = (1U << 11), /**< Transmit and reload completed interrupt */ + ALD_I2C_IT_ADDR = (1U << 12), /**< Address matching interrupt */ + ALD_I2C_IT_NACK = (1U << 13), /**< NACK interrupt */ + ALD_I2C_IT_STOP = (1U << 14), /**< Stop detection interrupt */ + ALD_I2C_IT_BERR = (1U << 16), /**< Bus error interrupt */ + ALD_I2C_IT_ARLO = (1U << 17), /**< Arbitration loss interrupt */ + ALD_I2C_IT_PECE = (1U << 18), /**< PEC error interrupt */ + ALD_I2C_IT_TOUT = (1U << 19), /**< Timeout interrupt */ + ALD_I2C_IT_ALERT = (1U << 20), /**< SMBus Alert interrupt */ +} ald_i2c_interrupt_t; + +/** + * @brief I2C TRISE Register + */ +typedef enum +{ + ALD_I2C_TRISE_TRISE = 0x3FU, /**< TRISE BITS */ +} ald_i2c_trise_t; + +/** + * @brief I2C Configuration Structure definition + */ +typedef struct +{ + ald_i2c_module_t module; /**< Specifies the communication module */ + uint32_t clk_speed; /**< Specifies the clock frequency */ + uint32_t own_addr1; /**< Specifies the first device own address */ + ald_i2c_addr_t addr_mode; /**< Specifies addressing mode */ + ald_i2c_dual_addr_t dual_addr; /**< Specifies if dual addressing mode is selected */ + uint32_t own_addr2; /**< Specifies the second device own address */ + ald_i2c_general_addr_t general_call;/**< Specifies if general call mode is selected */ + ald_i2c_nostretch_t no_stretch; /**< Specifies if nostretch mode is selected */ +} ald_i2c_init_t; + +/** + * @brief I2C handle Structure definition + */ +typedef struct ald_i2c_handle_s +{ + I2C_TypeDef *perh; /**< I2C registers base address */ + ald_i2c_init_t init; /**< I2C communication parameters */ + uint8_t *p_buff; /**< Pointer to I2C transfer buffer */ + uint16_t xfer_size; /**< I2C transfer size */ + __IO uint16_t xfer_count; /**< I2C transfer counter */ + + __IO uint32_t xfer_opt; /**< I2C transfer options */ + __IO uint32_t pre_state; /**< I2C previous communication state */ + + ald_dma_handle_t hdmatx; /**< I2C Tx DMA handle parameters */ + ald_dma_handle_t hdmarx; /**< I2C Rx DMA handle parameters */ + + lock_state_t lock; /**< I2C locking object */ + __IO ald_i2c_state_t state; /**< I2C communication state */ + __IO ald_i2c_mode_t mode; /**< I2C communication mode */ + __IO uint32_t error_code; /**< I2C Error code */ + + void (*addr_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Call Slave Addr callback */ + void (*listen_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Listen callback */ + + void (*master_tx_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Master Tx completed callback */ + void (*master_rx_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Master Rx completed callback */ + void (*slave_tx_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Slave Tx completed callback */ + void (*slave_rx_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Slave Rx completed callback */ + void (*mem_tx_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Tx to Memory completed callback */ + void (*mem_rx_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Rx from Memory completed callback */ + void (*error_callback)(struct ald_i2c_handle_s *arg); /**< Error callback */ +} ald_i2c_handle_t; + +/** + * @} + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** @defgroup I2C_Public_Macro I2C Public Macros + * @{ + */ + +/** + * @brief I2C Direction Definition + */ +#define ALD_I2C_DIRECTION_RECEIVE (0x00000000U) +#define ALD_I2C_DIRECTION_TRANSMIT (0x00000001U) +/** + * @brief I2C Transfer Definition + */ +#define ALD_I2C_NO_OPTION_FRAME (0xFFFF0000U) + +#define ALD_I2C_FIRST_FRAME (0x00000001U) +#define ALD_I2C_FIRST_AND_NEXT_FRAME (0x00000002U) +#define ALD_I2C_NEXT_FRAME (0x00000004U) +#define ALD_I2C_FIRST_AND_LAST_FRAME (0x00000008U) +#define ALD_I2C_LAST_FRAME_NO_STOP (0x00000010U) +#define ALD_I2C_LAST_FRAME (0x00000020U) + +#define ALD_I2C_OTHER_FRAME (0x00550000U) +#define ALD_I2C_OTHER_AND_LAST_FRAME (0x55000000U) + +#define ALD_I2C_FLAG_MASK (0xFFFFFFFFU) +#define ALD_I2C_RESET_HANDLE_STATE(x) ((x)->state = ALD_I2C_STATE_RESET) +#define ALD_I2C_ENABLE_IT(x, y) (SET_BIT((x)->perh->IER, (y))) +#define ALD_I2C_DISABLE_IT(x, y) (SET_BIT((x)->perh->IDR, (y))) +#define ALD_I2C_CLEAR_IT(x, y) (SET_BIT((x)->perh->ICR, (y))) +#define ALD_I2C_GET_IT_FLAG(x, y) (READ_BIT((x)->perh->RIF, (y))) +#define ALD_I2C_GET_IT_SOURCE(x, y) ((((x)->perh->IFM & (y)) == (y)) ? SET : RESET) +#define ALD_I2C_GET_FLAG(x, y) ((((x)->perh->STAT) & ((y) & ALD_I2C_FLAG_MASK)) != RESET) +#define ALD_I2C_MASTER_GET_DIR(x) (READ_BIT(((x)->perh->CON2), I2C_CON2_RD_WRN_MSK)) +#define ALD_I2C_SLAVE_GET_DIR(x) (READ_BIT(((x)->perh->STAT), I2C_STAT_DIR_MSK)) +#define ALD_I2C_ENABLE(x) (SET_BIT((x)->perh->CON1, I2C_CON1_PE_MSK)) +#define ALD_I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PE_MSK)) +/** + * @} + */ + +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ +#define IS_I2C_TYPE(x) (((x) == I2C0) || ((x) == I2C1)) +#define IS_I2C_MODULE(x) (((x) == ALD_I2C_MODULE_MASTER) || ((x) == ALD_I2C_MODULE_SLAVE)) +#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == ALD_I2C_ADDR_7BIT) || \ + ((ADDRESS) == ALD_I2C_ADDR_10BIT)) +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == ALD_I2C_DUALADDR_DISABLE) || \ + ((ADDRESS) == ALD_I2C_DUALADDR_ENABLE)) +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == ALD_I2C_GENERALCALL_DISABLE) || \ + ((CALL) == ALD_I2C_GENERALCALL_ENABLE)) +#define IS_I2C_MEMADD_size(size) (((size) == ALD_I2C_MEMADD_SIZE_8BIT) || \ + ((size) == ALD_I2C_MEMADD_SIZE_16BIT)) +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == ALD_I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == ALD_I2C_NOSTRETCH_ENABLE)) +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= ALD_I2C_EXTREME_FAST_MODE_MAX_CLK) ) +#define I2C_FREQ_RANGE(__PCLK__) ((__PCLK__) / 1000000) +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) &\ + (uint16_t)(0xFF00))) >> 8))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) +#define IS_I2C_IT(x) (((x) == ALD_I2C_IT_TXE) || \ + ((x) == ALD_I2C_IT_TXOV) || \ + ((x) == ALD_I2C_IT_TXUD) || \ + ((x) == ALD_I2C_IT_RXNE) || \ + ((x) == ALD_I2C_IT_RXOV) || \ + ((x) == ALD_I2C_IT_RXUD) || \ + ((x) == ALD_I2C_IT_TC) || \ + ((x) == ALD_I2C_IT_TCR) || \ + ((x) == ALD_I2C_IT_ADDR) || \ + ((x) == ALD_I2C_IT_NACK) || \ + ((x) == ALD_I2C_IT_STOP) || \ + ((x) == ALD_I2C_IT_BERR) || \ + ((x) == ALD_I2C_IT_ARLO) || \ + ((x) == ALD_I2C_IT_PECE) || \ + ((x) == ALD_I2C_IT_TOUT) || \ + ((x) == ALD_I2C_IT_ALERT)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS(OPTION) (((OPTION) == ALD_I2C_OTHER_FRAME) || \ + ((OPTION) == ALD_I2C_OTHER_AND_LAST_FRAME)) + +#define IS_I2C_TRANSFER_OPTIONS(OPTION) (((OPTION) == ALD_I2C_FIRST_FRAME) || \ + ((OPTION) == ALD_I2C_FIRST_AND_NEXT_FRAME) || \ + ((OPTION) == ALD_I2C_NEXT_FRAME) || \ + ((OPTION) == ALD_I2C_FIRST_AND_LAST_FRAME) || \ + ((OPTION) == ALD_I2C_LAST_FRAME) || \ + ((OPTION) == ALD_I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS(OPTION)) + +#define ALD_I2C_STATE_MSK ((ALD_I2C_STATE_BUSY_TX | ALD_I2C_STATE_BUSY_RX) & (~(ALD_I2C_STATE_READY))) +#define ALD_I2C_STATE_NONE (ALD_I2C_MODE_NONE) +#define ALD_I2C_STATE_MASTER_BUSY_TX ((ALD_I2C_STATE_BUSY_TX | ALD_I2C_STATE_MSK) | (ALD_I2C_MODE_MASTER)) +#define ALD_I2C_STATE_MASTER_BUSY_RX ((ALD_I2C_STATE_BUSY_RX | ALD_I2C_STATE_MSK) | (ALD_I2C_MODE_MASTER)) +#define ALD_I2C_STATE_SLAVE_BUSY_TX ((ALD_I2C_STATE_BUSY_TX | ALD_I2C_STATE_MSK) | (ALD_I2C_MODE_SLAVE)) +#define ALD_I2C_STATE_SLAVE_BUSY_RX ((ALD_I2C_STATE_BUSY_RX | ALD_I2C_STATE_MSK) | (ALD_I2C_MODE_SLAVE)) + +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @addtogroup I2C_Public_Functions + * @{ + */ + +/** @addtogroup I2C_Public_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +ald_status_t ald_i2c_init(ald_i2c_handle_t *hperh); +ald_status_t ald_i2c_reset(ald_i2c_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group2 Input and Output operation functions + * @{ + */ +/** Blocking mode: Polling */ +ald_status_t ald_i2c_master_send(ald_i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2c_master_recv(ald_i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2c_slave_send(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2c_slave_recv(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2c_mem_write(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + ald_i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2c_mem_read(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + ald_i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout); + +/** Non-Blocking mode: Interrupt */ +ald_status_t ald_i2c_master_send_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size); +ald_status_t ald_i2c_master_recv_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size); +ald_status_t ald_i2c_slave_send_by_it(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size); +ald_status_t ald_i2c_slave_recv_by_it(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size); +ald_status_t ald_i2c_mem_write_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + ald_i2c_addr_size_t add_size, uint8_t *buf, uint32_t size); +ald_status_t ald_i2c_mem_read_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + ald_i2c_addr_size_t add_size, uint8_t *buf, uint32_t size); + + +/** Non-Blocking mode: DMA */ +ald_status_t ald_i2c_master_send_by_dma(ald_i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2c_master_recv_by_dma(ald_i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2c_slave_send_by_dma(ald_i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2c_slave_recv_by_dma(ald_i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2c_mem_write_by_dma(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, ald_i2c_addr_size_t add_size, + uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2c_mem_read_by_dma(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + ald_i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint8_t channel); + +/** Non-Blocking Sequence transmit mode */ + +ald_status_t ald_i2c_master_seq_send_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size, uint32_t option); +ald_status_t ald_i2c_master_seq_recv_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size, uint32_t option); +ald_status_t ald_i2c_slave_seq_send_by_it(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t option); +ald_status_t ald_i2c_slave_seq_recv_by_it(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t option); +ald_status_t ald_i2c_master_abort_it(ald_i2c_handle_t *hperh, uint16_t addr); +ald_status_t ald_i2c_enablelisten_it(ald_i2c_handle_t *hperh); +ald_status_t ald_i2c_disablelisten_it(ald_i2c_handle_t *hperh); + +void ald_i2c_seq_ev_irq_handler(ald_i2c_handle_t *hperh); +void ald_i2c_seq_er_irq_handler(ald_i2c_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group3 Peripheral state and Errors functions + * @{ + */ +ald_i2c_state_t ald_i2c_get_state(ald_i2c_handle_t *hperh); +uint32_t ald_i2c_get_error(ald_i2c_handle_t *hperh); +void ald_i2c_clear_flag_status(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t flag); +flag_status_t ald_i2c_get_mask_flag_status(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t flag); +flag_status_t ald_i2c_get_flag_status(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t flag); +it_status_t ald_i2c_get_it_status(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t it); +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group4 IRQ Handler and Callbacks + * @{ + */ +void ald_i2c_ev_irq_handler(ald_i2c_handle_t *hperh); +void ald_i2c_er_irq_handler(ald_i2c_handle_t *hperh); +void ald_i2c_interrupt_config(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t it, type_func_t state); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_I2C_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_i2s.c b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_i2s.c new file mode 100644 index 0000000000..a602d93613 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_i2s.c @@ -0,0 +1,1095 @@ +/** + ********************************************************************************* + * + * @file ald_I2S.c + * @brief I2S module driver. + * This file provides firmware functions to manage the following + * functionalities of I2S peripheral: + * + Initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + * @version V1.0 + * @date 09 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 09 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2S driver can be used as follows: + + (#) Declare a i2s_handle_t structure, for example: + i2s_handle_t hperh; + + (#) Initialize the I2S low level resources: + (##) Enable the I2Sx interface clock + (##) I2S pins configuration + (+++) Enable the clock for the I2S GPIOs + (+++) Configure these I2S pins as push-pull + (##) NVIC configuration if you need to use interrupt process + by implementing the ald_mcu_irq_config() API. + Invoked ald_i2s_irq_handler() function in I2S-IRQ function + (##) DMA Configuration if you need to use DMA process + (+++) Define ALD_DMA in ald_conf.h + (+++) Enable the DMAx clock + + (#) Program the Channel length, Data length, Polarity, Standard, Pcm frame, + external clock and Main clock output, Odd factor and Divide clock in the i2s_init_t structure. + + (#) Initialize the I2S module by invoking the ald_i2s_init() API. + + [..] + Circular mode restriction: + (#) When the I2S DMA Pause/Stop features are used, we must use the following APIs + the ald_i2s_dma_pause()/ ald_i2s_dma_stop(). + + * @endverbatim + */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_cmu.h" +#include "ald_i2s.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/* Private function prototypes ----------------------------------------------- */ + +/** @defgroup I2S I2S + * @brief I2S module driver + * @{ + */ +/** @addtogroup I2S_Private_Functions I2S Private Functions + * @{ + */ +static ald_status_t i2s_wait_status(ald_i2s_handle_t *hperh, ald_i2s_status_t state, flag_status_t status, uint32_t timeout); +static void __i2s_send_by_it(ald_i2s_handle_t *hperh); +static void __i2s_recv_by_it(ald_i2s_handle_t *hperh); +static void __i2s_tx_recv_by_it(ald_i2s_handle_t *hperh); + +static void i2s_dma_send_cplt(void *arg); +static void i2s_dma_recv_cplt(void *arg); + +/** + * @} + */ + +/* Private Function ---------------------------------------------------------- */ + +/** @defgroup I2S_Public_Functions I2S Public Functions + * @{ + */ + +/** @defgroup I2S_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * + * @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + reset the I2Sx peripheral: + + (+) User must configure all related peripherals resources + (CLOCK, GPIO, DMA, NVIC). + + (+) Call the function ald_i2s_init() to configure the selected device with + the selected configuration: + (++) Channel length + (++) Data length + (++) Polarity + (++) Standard + (++) Pcm frame + (++) External clock + (++) Main clock output function + (++) Odd factor + (++) Divide clock + + (+) Call the function ald_i2s_reset() to reset the selected I2Sx periperal. + + @endverbatim + * @{ + */ + +/** + * @brief Reset the I2S peripheral. + * @param hperh: Pointer to a i2s_handle_t structure that contains + * the configuration information for the specified I2S module. + * @retval None + */ +void ald_i2s_reset(ald_i2s_handle_t *hperh) +{ + hperh->perh->I2SCFG = 0x0; + hperh->perh->I2SPR = 0x0; + + ALD_I2S_RESET_HANDLE_STATE(hperh); + __UNLOCK(hperh); + + return; +} + +/** + * @brief Initializes the I2S mode according to the specified parameters in + * the i2s_init_t and create the associated handle. + * @param hperh: Pointer to a i2s_handle_t structure that contains + * the configuration information for the specified SPI module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_init(ald_i2s_handle_t *hperh) +{ + uint32_t tmp = 0U, clk, _div; + + if (hperh == NULL) + return ALD_ERROR; + + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_CH_LEN(hperh->init.ch_len)); + assert_param(IS_I2S_DATE_LEN(hperh->init.data_len)); + assert_param(IS_I2S_CPOL(hperh->init.polarity)); + assert_param(IS_I2S_STANDARD(hperh->init.standard)); + assert_param(IS_FUNC_STATE(hperh->init.ext_clk_en)); + assert_param(IS_FUNC_STATE(hperh->init.mck_en)); + assert_param(IS_I2S_PCMS(hperh->init.pcm_frame)); + + ald_i2s_reset(hperh); + + tmp |= (hperh->init.ext_clk_en << SPI_I2SPR_EXTCKEN_POS); + + /* Get I2S clock */ + if (hperh->init.ext_clk_en) + clk = hperh->init.ext_clk; + else + clk = ald_cmu_get_pclk_clock(); + + if (hperh->init.mck_en) + { + _div = ((clk / hperh->init.sampling) >> 8); + } + else + { + if (hperh->init.ch_len == ALD_I2S_WIDE_16) + _div = ((clk / hperh->init.sampling) >> 5); + else + _div = ((clk / hperh->init.sampling) >> 6); + } + + if (_div & 0x1) + { + SET_BIT(tmp, SPI_I2SPR_ODD_MSK); + --_div; + } + else + { + CLEAR_BIT(tmp, SPI_I2SPR_ODD_MSK); + } + + if (hperh->init.standard != ALD_I2S_STD_PCM) + MODIFY_REG(tmp, SPI_I2SPR_I2SDIV_MSK, (_div >> 1) << SPI_I2SPR_I2SDIV_POSS); + else + MODIFY_REG(tmp, SPI_I2SPR_I2SDIV_MSK, _div << SPI_I2SPR_I2SDIV_POSS); + + hperh->perh->I2SPR = tmp; + + tmp = hperh->perh->I2SCFG; + tmp |= ((hperh->init.ch_len << SPI_I2SCFG_CHLEN_POS) | (hperh->init.data_len << SPI_I2SCFG_DATLEN_POSS) | + (hperh->init.polarity << SPI_I2SCFG_CKPOL_POS) | (hperh->init.standard << SPI_I2SCFG_I2SSTD_POSS) | + (1 << SPI_I2SCFG_I2SMOD_POS)); + hperh->perh->I2SCFG = tmp; + + if (hperh->init.standard == ALD_I2S_STD_PCM) + hperh->perh->I2SCFG |= (hperh->init.pcm_frame << SPI_I2SCFG_PCMSYNC_POS); + + hperh->err_code = ALD_I2S_ERROR_NONE; + hperh->state = ALD_I2S_STATE_READY; + + return ALD_OK; +} +/** + * @} + */ + +/** @defgroup I2S_Public_Functions_Group2 IO operation functions + * @brief I2S Transmit and Receive functions + * + * @verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the I2S + data transfers. + + [..] The I2S supports master or slave mode: + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The ALD status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the ALD status. + The end of the data processing will be indicated through the + dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The hperh->err_cbk() user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA). + + * @endverbatim + * @{ + */ + +/** + * @brief Master mode transmit an amount of data in blocking mode. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_send(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != ALD_I2S_STATE_READY) + return ALD_BUSY; + + if (buf == NULL || size == 0) + return ALD_ERROR; + + hperh->state = ALD_I2S_STATE_BUSY_TX; + hperh->err_code = ALD_I2S_ERROR_NONE; + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, ALD_I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + ALD_I2S_ENABLE(hperh); + + while (size > 0) + { + if (i2s_wait_status(hperh, ALD_I2S_STATUS_TXE, SET, timeout) != ALD_OK) + { + ALD_I2S_DISABLE(hperh); + + hperh->state = ALD_I2S_STATE_READY; + return ALD_TIMEOUT; + } + + hperh->side = READ_BITS(hperh->perh->STAT, SPI_STAT_CHSIDE_MSK, SPI_STAT_CHSIDE_POS); + hperh->perh->DATA = *buf++; + --size; + } + + if ((i2s_wait_status(hperh, ALD_I2S_STATUS_TXE, SET, timeout) != ALD_OK) + || (i2s_wait_status(hperh, ALD_I2S_STATUS_BUSY, RESET, timeout) != ALD_OK)) + { + ALD_I2S_DISABLE(hperh); + hperh->state = ALD_I2S_STATE_READY; + return ALD_TIMEOUT; + } + + ALD_I2S_DISABLE(hperh); + hperh->state = ALD_I2S_STATE_READY; + + return ALD_OK; +} + +/** + * @brief Master mode receive an amount of data in blocking mode. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_recv(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != ALD_I2S_STATE_READY) + return ALD_BUSY; + + if (buf == NULL || size == 0) + return ALD_ERROR; + + hperh->state = ALD_I2S_STATE_BUSY_RX; + hperh->err_code = ALD_I2S_ERROR_NONE; + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, ALD_I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + ALD_I2S_ENABLE(hperh); + + while (size > 0) + { + hperh->perh->DATA = 0xffff; + + if (i2s_wait_status(hperh, ALD_I2S_STATUS_RXNE, SET, timeout) != ALD_OK) + { + ALD_I2S_DISABLE(hperh); + hperh->state = ALD_I2S_STATE_READY; + return ALD_TIMEOUT; + } + + *buf++ = hperh->perh->DATA; + --size; + } + + hperh->state = ALD_I2S_STATE_READY; + return ALD_OK; +} + +/** + * @brief Wraps up master mode transmission in non blocking mode. + * @param hperh: pointer to a i2s_handle_t structure. + * @param buf: Pointer to data transmitted buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_send_by_it(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != ALD_I2S_STATE_READY) + return ALD_BUSY; + + if (buf == NULL || size == 0) + return ALD_ERROR; + + hperh->state = ALD_I2S_STATE_BUSY_TX; + hperh->err_code = ALD_I2S_ERROR_NONE; + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + WRITE_REG(hperh->perh->ICR, 0xffffffff); + + ALD_I2S_DISABLE(hperh); + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, ALD_I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + ALD_I2S_ENABLE(hperh); + + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_TXE, ENABLE); + return ALD_OK; +} + +/** + * @brief Master mode receives an amount of data in non blocking mode + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_recv_by_it(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != ALD_I2S_STATE_READY) + return ALD_BUSY; + + if (buf == NULL || size == 0) + return ALD_ERROR; + + hperh->state = ALD_I2S_STATE_BUSY_TX_RX; + hperh->err_code = ALD_I2S_ERROR_NONE; + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = 0; + hperh->tx_size = size; + hperh->tx_count = size; + + WRITE_REG(hperh->perh->ICR, 0xffffffff); + + ALD_I2S_DISABLE(hperh); + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, ALD_I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + ALD_I2S_ENABLE(hperh); + + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_RXTH, ENABLE); + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_TXE, ENABLE); + + return ALD_OK; +} + +/** + * @brief Master mode transmit an amount of data used dma channel + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2S transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_send_by_dma(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t channel) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != ALD_I2S_STATE_READY) + return ALD_BUSY; + + if (buf == NULL || size == 0) + return ALD_ERROR; + + hperh->state = ALD_I2S_STATE_BUSY_TX; + hperh->err_code = ALD_I2S_ERROR_NONE; + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + WRITE_REG(hperh->perh->ICR, 0xffffffff); + + ALD_I2S_DISABLE(hperh); + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, ALD_I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + + hperh->hdmatx.cplt_tc_arg = (void *)hperh; + hperh->hdmatx.cplt_tc_cbk = i2s_dma_send_cplt; + + /* Configure I2S DMA transmit */ + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.perh = DMA; + hperh->hdmatx.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmatx.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.msel = ALD_DMA_MSEL_SPI0; + hperh->hdmatx.config.msigsel = ALD_DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&(hperh->hdmatx)); + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_TX, ENABLE); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + ALD_I2S_ENABLE(hperh); + + return ALD_OK; +} + +/** + * @brief Master mode receive an amount of data used dma channel + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param dma_ch: DMA channel for I2S receive + * @param _dma_ch: DMA channel for sending clock + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_recv_by_dma(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t dma_ch, uint8_t _dma_ch) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != ALD_I2S_STATE_READY) + return ALD_BUSY; + + if (buf == NULL || size == 0) + return ALD_ERROR; + + hperh->state = ALD_I2S_STATE_BUSY_RX; + hperh->err_code = ALD_I2S_ERROR_NONE; + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + buf[size - 1] = 0xFFFF; + + WRITE_REG(hperh->perh->ICR, 0xffffffff); + + ALD_I2S_DISABLE(hperh); + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, ALD_I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + + hperh->hdmatx.cplt_tc_arg = (void *)hperh; + hperh->hdmatx.cplt_tc_cbk = i2s_dma_send_cplt; + + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.perh = DMA; + hperh->hdmatx.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)&buf[size - 1]; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.msel = ALD_DMA_MSEL_SPI0; + hperh->hdmatx.config.msigsel = ALD_DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.channel = _dma_ch; + ald_dma_config_basic(&(hperh->hdmatx)); + ald_dma_interrupt_config(_dma_ch, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_TX, ENABLE); + + hperh->hdmarx.cplt_tc_arg = (void *)hperh; + hperh->hdmarx.cplt_tc_cbk = i2s_dma_recv_cplt; + + /* Configure DMA Receive */ + ald_dma_config_struct(&(hperh->hdmarx.config)); + hperh->hdmarx.perh = DMA; + hperh->hdmarx.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmarx.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmarx.config.msel = ALD_DMA_MSEL_SPI0; + hperh->hdmarx.config.msigsel = ALD_DMA_MSIGSEL_SPI_RNR; + hperh->hdmarx.config.channel = dma_ch; + ald_dma_config_basic(&(hperh->hdmarx)); + ald_dma_interrupt_config(dma_ch, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_RX, ENABLE); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + ALD_I2S_ENABLE(hperh); + + return ALD_OK; +} + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval Status + */ +ald_status_t ald_i2s_dma_pause(ald_i2s_handle_t *hperh) +{ + assert_param(IS_I2S(hperh->perh)); + + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_TX, DISABLE); + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_RX, DISABLE); + + return ALD_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval Status + */ +ald_status_t ald_i2s_dma_resume(ald_i2s_handle_t *hperh) +{ + assert_param(IS_I2S(hperh->perh)); + + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_TX, ENABLE); + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_RX, ENABLE); + + return ALD_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval Status + */ +ald_status_t ald_i2s_dma_stop(ald_i2s_handle_t *hperh) +{ + assert_param(IS_I2S(hperh->perh)); + + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_TX, DISABLE); + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_RX, DISABLE); + + hperh->state = ALD_I2S_STATE_READY; + return ALD_OK; +} + +/** + * @} + */ + +/** @defgroup I2S_Public_Functions_Group3 Control functions + * @brief I2S Control functions + * + * @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the I2S. + (+) Handle interrupt about I2S module. The ald_i2s_irq_handler() function must + be invoked by I2S-IRQ function. + (+) Configure the interrupt DISABLE/ENABLE. + (+) Configure the DMA request. + (+) Get interrupt source status. + (+) Get interrupt flag status. + (+) Clear interrupt flag + + @endverbatim + * @{ + */ + +/** + * @brief This function handles I2S interrupt request. + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval None + */ +void ald_i2s_irq_handler(ald_i2s_handle_t *hperh) +{ + if (ald_i2s_get_mask_flag_status(hperh, ALD_I2S_IF_RXTH) == SET) + { + ald_i2s_clear_flag_status(hperh, ALD_I2S_IF_RXTH); + + if ((hperh->state == ALD_I2S_STATE_BUSY_TX_RX) || (hperh->state == ALD_I2S_STATE_BUSY_RX)) + __i2s_recv_by_it(hperh); + } + + if (ald_i2s_get_mask_flag_status(hperh, ALD_I2S_IF_TXE) == SET) + { + ald_i2s_clear_flag_status(hperh, ALD_I2S_IF_TXE); + + if (hperh->state == ALD_I2S_STATE_BUSY_TX) + __i2s_send_by_it(hperh); + else if (hperh->state == ALD_I2S_STATE_BUSY_TX_RX) + __i2s_tx_recv_by_it(hperh); + else; + + } + + if (hperh->err_code != ALD_I2S_ERROR_NONE) + { + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_RXTH, DISABLE); + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_TXE, DISABLE); + hperh->state = ALD_I2S_STATE_READY; + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +/** + * @brief Enables or disables the specified I2S interrupts. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param it: Specifies the I2S interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref i2s_it_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_i2s_interrupt_config(ald_i2s_handle_t *hperh, ald_i2s_it_t it, type_func_t state) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + hperh->perh->IER = (uint32_t)it; + else + hperh->perh->IDR = (uint32_t)it; + + return; +} + +/** + * @brief Enables or disables the dma request. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param req: Specifies the I2S dma request sources to be enabled or disabled. + * This parameter can be one of the @ref i2s_dma_req_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_i2s_dma_req_config(ald_i2s_handle_t *hperh, ald_i2s_dma_req_t req, type_func_t state) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + { + if (req == ALD_I2S_DMA_REQ_TX) + SET_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + SET_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + else + { + if (req == ALD_I2S_DMA_REQ_TX) + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + + return; +} + +/** @brief Check whether the specified I2S flag is set or not. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param status: specifies the flag to check. + * This parameter can be one of the @ref i2s_status_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t ald_i2s_get_status(ald_i2s_handle_t *hperh, ald_i2s_status_t status) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_STATUS(status)); + + if (hperh->perh->STAT & status) + return SET; + + return RESET; +} + +/** + * @brief Checks whether the specified I2S interrupt has occurred or not. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param it: Specifies the I2S interrupt source to check. + * This parameter can be one of the @ref i2s_it_t. + * @retval Status + * - SET + * - RESET + */ +it_status_t ald_i2s_get_it_status(ald_i2s_handle_t *hperh, ald_i2s_it_t it) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_IT(it)); + + if (hperh->perh->IVS & it) + return SET; + + return RESET; +} + +/** @brief Check whether the specified I2S interrupt flag is set or not. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref i2s_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t ald_i2s_get_flag_status(ald_i2s_handle_t *hperh, ald_i2s_flag_t flag) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_IF(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + +/** @brief Check whether the specified I2S interrupt flag is set or not. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref i2s_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t ald_i2s_get_mask_flag_status(ald_i2s_handle_t *hperh, ald_i2s_flag_t flag) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_IF(flag)); + + if (hperh->perh->IFM & flag) + return SET; + + return RESET; +} + +/** @brief Clear the specified I2S interrupt flags. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref i2s_flag_t. + * @retval None + */ +void ald_i2s_clear_flag_status(ald_i2s_handle_t *hperh, ald_i2s_flag_t flag) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_IF(flag)); + + hperh->perh->ICR = flag; + return; +} +/** + * @} + */ + +/** @defgroup I2S_Public_Functions_Group4 Peripheral State and Errors functions + * @brief I2S State and Errors functions + * + * @verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the I2S. + (+) ald_i2s_get_state() API can check in run-time the state of the I2S peripheral + (+) ald_i2s_get_error() check in run-time Errors occurring during communication + + @endverbatim + * @{ + */ + +/** + * @brief Returns the I2S state. + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval Status, see @ref i2s_state_t. + */ +ald_i2s_state_t ald_i2s_get_state(ald_i2s_handle_t *hperh) +{ + assert_param(IS_I2S(hperh->perh)); + return hperh->state; +} + +/** + * @brief Return the I2S error code + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval I2S Error Code + */ +uint32_t ald_i2s_get_error(ald_i2s_handle_t *hperh) +{ + assert_param(IS_I2S(hperh->perh)); + return hperh->err_code; +} +/** + * @} + */ +/** + * @} + */ + +/** @defgroup I2S_Private_Functions I2S Private Functions + * @brief I2S Private functions + * @{ + */ +/** + * @brief This function wait I2S status until timeout. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param flag: specifies the I2S flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2s_wait_status(ald_i2s_handle_t *hperh, ald_i2s_status_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tick = ald_get_tick(); + + assert_param(timeout > 0); + + while ((ald_i2s_get_status(hperh, flag)) != status) + { + if (((ald_get_tick()) - tick) > timeout) + { + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_TXE, DISABLE); + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_RXTH, DISABLE); + return ALD_TIMEOUT; + } + } + + return ALD_OK; +} + +/** + * @brief handle program when an tx empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval None. + */ +static void __i2s_send_by_it(ald_i2s_handle_t *hperh) +{ + int cnt = 8000; + + if (hperh->tx_count == 0) + { + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_TXE, DISABLE); + hperh->state = ALD_I2S_STATE_READY; + + while ((hperh->perh->STAT & SPI_STAT_BUSY_MSK) && (--cnt)); + + if (cnt == 0) + { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_RXTH, DISABLE); + return; + } + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + + return; + } + + hperh->side = READ_BITS(hperh->perh->STAT, SPI_STAT_CHSIDE_MSK, SPI_STAT_CHSIDE_POS); + hperh->perh->DATA = *hperh->tx_buf++; + --hperh->tx_count; + + return; +} + +/** + * @brief handle program when an rx no empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval None. + */ +static void __i2s_recv_by_it(ald_i2s_handle_t *hperh) +{ + while (READ_BITS(hperh->perh->STAT, SPI_STAT_RXFLV_MSK, SPI_STAT_RXFLV_POSS)) + { + *(hperh->rx_buf++) = hperh->perh->DATA; + --hperh->rx_count; + } + + if (hperh->rx_count == 0) + { + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_RXTH, DISABLE); + hperh->state = ALD_I2S_STATE_READY; + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + return; +} + +/** + * @brief handle program when an rx no empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval None. + */ +static void __i2s_tx_recv_by_it(ald_i2s_handle_t *hperh) +{ + if (hperh->tx_count != 0) + { + ald_i2s_clear_flag_status(hperh, ALD_I2S_IF_TXE); + hperh->perh->DATA = 0xffff; + --hperh->tx_count; + + if (hperh->tx_count == 0) + ald_i2s_interrupt_config(hperh, ALD_I2S_IT_TXE, DISABLE); + } +} + +/** + * @brief DMA I2S transmit process complete callback. + * @param arg: Pointer to a void structure. + * @retval None + */ +static void i2s_dma_send_cplt(void *arg) +{ + int cnt = 8000; + ald_i2s_handle_t *hperh = (ald_i2s_handle_t *)arg; + + hperh->tx_count = 0; + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_TX, DISABLE); + hperh->state = ALD_I2S_STATE_READY; + + while ((hperh->perh->STAT & SPI_STAT_BUSY_MSK) && (--cnt)); + + if (cnt == 0) + hperh->err_code |= ALD_I2S_ERROR_FLAG; + + if (hperh->err_code == ALD_I2S_ERROR_NONE) + { + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + } + else + { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +/** + * @brief DMA I2S receive process complete callback. + * @param arg: Pointer to a void structure. + * @retval None + */ +static void i2s_dma_recv_cplt(void *arg) +{ + ald_i2s_handle_t *hperh = (ald_i2s_handle_t *)arg; + + hperh->rx_count = 0; + ald_i2s_dma_req_config(hperh, ALD_I2S_DMA_REQ_RX, DISABLE); + hperh->state = ALD_I2S_STATE_READY; + + if (hperh->err_code == ALD_I2S_ERROR_NONE) + { + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + else + { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_i2s.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_i2s.h new file mode 100644 index 0000000000..3f679dc7eb --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_i2s.h @@ -0,0 +1,427 @@ +/** + ********************************************************************************* + * + * @file ald_i2s.c + * @brief Header file of I2S module driver. + * + * @version V1.0 + * @date 09 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 09 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_I2S_H__ +#define __ALD_I2S_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_utils.h" +#include "ald_dma.h" + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Constants -------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup I2S + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup I2S_Public_Types I2S Public Types + * @{ + */ + +/** + * @brief Channel length + */ +typedef enum +{ + ALD_I2S_WIDE_16 = 0x0U, /**< Channel length is 16 */ + ALD_I2S_WIDE_32 = 0x1U, /**< Channel length is 32 */ +} ald_i2s_chlen_t; + +/** + * @brief Data length + */ +typedef enum +{ + ALD_I2S_LEN_16 = 0x0U, /**< Data length is 16 */ + ALD_I2S_LEN_24 = 0x1U, /**< Data length is 24 */ + ALD_I2S_LEN_32 = 0x2U, /**< Data length is 32 */ +} ald_i2s_datalen_t; + +/** + * @brief Inactive state clock polarity + */ +typedef enum +{ + ALD_I2S_INACTIVE_LOW = 0x0U, /**< Inactive state is low */ + ALD_I2S_INACTIVE_HIGH = 0x1U, /**< Inactive state is high */ +} ald_i2s_cpol_t; + +/** + * @brief I2s standard + */ +typedef enum +{ + ALD_I2S_STD_PHI = 0x0U, /**< Philips standard */ + ALD_I2S_STD_MSB = 0x1U, /**< MSB standard */ + ALD_I2S_STD_LSB = 0x2U, /**< LSB standard */ + ALD_I2S_STD_PCM = 0x3U, /**< PCM standard */ +} ald_i2s_standard_t; + +/** + * @brief I2s configuration mode + */ +typedef enum +{ + ALD_I2S_SLAVE_DUPLEX = 0x0U, /**< I2S slave full duplex mode */ + ALD_I2S_SLAVE_RECEIVE = 0x1U, /**< I2S slave receive mode */ + ALD_I2S_SLAVE_TRANSMIT = 0x2U, /**< I2S slave transmit mode */ + ALD_I2S_MASTER_DUPLEX = 0x4U, /**< I2S master full duplex mode */ + ALD_I2S_MASTER_TRANSMIT = 0x5U, /**< I2S master transmit mode */ + ALD_I2S_MASTER_RECEIVE = 0x6U, /**< I2S master receive mode */ +} ald_i2s_cfg_t; + +/** + * @brief Pcm frame synchronization + */ +typedef enum +{ + ALD_I2S_FRAME_SHORT = 0x0U, /**< I2S PCM short frame */ + ALD_I2S_FRAME_LONG = 0x1U, /**< I2S PCM long frame */ +} ald_i2s_pcms_t; + +/** + * @brief Channel side + */ +typedef enum +{ + ALD_I2S_SIDE_LEFT = 0U, /**< Sound channel is left */ + ALD_I2S_SIDE_RIGHT = 1U, /**< Sound channel is right */ +} ald_i2s_ch_side_t; + +/** + * @brief I2S error status + */ +typedef enum +{ + ALD_I2S_ERROR_NONE = 0x0U, /**< none */ + ALD_I2S_ERROR_MODF = 0x1U, /**< mode fault */ + ALD_I2S_ERROR_DMA = 0x2U, /**< crc error */ + ALD_I2S_ERROR_FRE = 0x4U, /**< frame error */ + ALD_I2S_ERROR_RXOV = 0x8U, /**< receive over error */ + ALD_I2S_ERROR_TXOV = 0x10U, /**< dma error */ + ALD_I2S_ERROR_FLAG = 0x20U, /**< interrupt flag error */ +} ald_i2s_error_t; + +/** + * @brief interrupt control + */ +typedef enum +{ + ALD_I2S_IT_TXE = (1U << 0), /**< Transmit fifo empty interrupt */ + ALD_I2S_IT_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt */ + ALD_I2S_IT_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt */ + ALD_I2S_IT_TXTH = (1U << 4), /**< Transmit fifo under threshold interrupt */ + ALD_I2S_IT_RXNE = (1U << 8), /**< Receive fifo not empty interrupt */ + ALD_I2S_IT_RXF = (1U << 9), /**< Receive fifo full interrupt */ + ALD_I2S_IT_RXOV = (1U << 10), /**< Receive fifo overflow interrupt */ + ALD_I2S_IT_RXUD = (1U << 11), /**< Receive fifo underflow interrupt */ + ALD_I2S_IT_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt */ + ALD_I2S_IT_CRCERR = (1U << 16), /**< Crc error interrupt */ + ALD_I2S_IT_MODF = (1U << 17), /**< Mode error interrupt */ + ALD_I2S_IT_FRE = (1U << 18), /**< Frame error interrupt */ +} ald_i2s_it_t; + +/** + * @brief I2S dma request definition + */ +typedef enum +{ + ALD_I2S_DMA_REQ_TX = 0U, /**< TX dma request */ + ALD_I2S_DMA_REQ_RX = 1U, /**< RX dma request */ +} ald_i2s_dma_req_t; + +/** + * @brief interrupt flag + */ +typedef enum +{ + ALD_I2S_IF_TXE = (1U << 0), /**< Transmit fifo empty interrupt flag */ + ALD_I2S_IF_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt flag */ + ALD_I2S_IF_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt flag */ + ALD_I2S_IF_TXTH = (1U << 4), /**< Transmit fifo under threshold interrupt flag */ + ALD_I2S_IF_RXNE = (1U << 8), /**< Receive fifo not empty interrupt flag */ + ALD_I2S_IF_RXF = (1U << 9), /**< Receive fifo full interrupt flag */ + ALD_I2S_IF_RXOV = (1U << 10), /**< Receive fifo overflow interrupt flag */ + ALD_I2S_IF_RXUD = (1U << 11), /**< Receive fifo underflow interrupt flag */ + ALD_I2S_IF_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt flag */ + ALD_I2S_IF_CRCERR = (1U << 16), /**< Crc error interrupt flag */ + ALD_I2S_IF_MODF = (1U << 17), /**< Mode error interrupt flag */ + ALD_I2S_IF_FRE = (1U << 18), /**< Frame error interrupt flag */ +} ald_i2s_flag_t; + +/** + * @brief I2S state structures definition + */ +typedef enum +{ + ALD_I2S_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + ALD_I2S_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + ALD_I2S_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + ALD_I2S_STATE_BUSY_TX = 0x11U, /**< transmit is ongoing */ + ALD_I2S_STATE_BUSY_RX = 0x21U, /**< receive is ongoing */ + ALD_I2S_STATE_BUSY_TX_RX = 0x31U, /**< transmit and receive are ongoing */ + ALD_I2S_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + ALD_I2S_STATE_ERROR = 0x04U, /**< Error */ +} ald_i2s_state_t; + +/** + * @brief I2S status definition + */ +typedef enum +{ + ALD_I2S_STATUS_TXE = (1U << 0), /**< Transmit fifo empty status */ + ALD_I2S_STATUS_TXF = (1U << 1), /**< Transmit fifo full status */ + ALD_I2S_STATUS_TXOV = (1U << 2), /**< Transmit fifo overflow status */ + ALD_I2S_STATUS_TXUD = (1U << 3), /**< Transmit fifo underflow status */ + ALD_I2S_STATUS_TXTH = (1U << 4), /**< Transmit fifo under threshold status */ + ALD_I2S_STATUS_RXNE = (1U << 8), /**< Receive fifo not empty status */ + ALD_I2S_STATUS_RXF = (1U << 9), /**< Receive fifo full status */ + ALD_I2S_STATUS_RXOV = (1U << 10), /**< Receive fifo overflow status */ + ALD_I2S_STATUS_RXUD = (1U << 11), /**< Receive fifo underflow status */ + ALD_I2S_STATUS_RXTH = (1U << 12), /**< Receive fifo over threshold status */ + ALD_I2S_STATUS_CHSIDE = (1U << 14), /**< Sound channel status */ + ALD_I2S_STATUS_BUSY = (1U << 15), /**< BUSY status */ +} ald_i2s_status_t; + +/** + * @brief I2S TXE/RXNE status definition + */ +typedef enum +{ + ALD_I2S_SR_TXE = 0U, /**< STAT TXE set */ + ALD_I2S_SR_RXNE = 1U, /**< STAT RXTH set */ + ALD_I2S_SR_TXE_RXNE = 2U, /**< STAT TXE and RXTH set */ +} ald_i2s_sr_status_t; + +/** + * @brief I2S init structure definition + */ +typedef struct +{ + ald_i2s_chlen_t ch_len; /**< Channel length choose */ + ald_i2s_datalen_t data_len; /**< Data length choose */ + ald_i2s_cpol_t polarity; /**< Inactive clock polarity */ + ald_i2s_standard_t standard; /**< Standard choose */ + ald_i2s_pcms_t pcm_frame; /**< PCM frame synchronization */ + type_func_t ext_clk_en; /**< Choose external clock or APB1 clock */ + uint32_t ext_clk; /**< External clock, unit is Hz */ + type_func_t mck_en; /**< Main clock output function */ + uint32_t sampling; /**< Sampling rate. eg. 192*1024-192KHz, 96*1024-96KHz */ +} ald_i2s_init_t; + +/** + * @brief I2S handle structure definition + */ +typedef struct ald_i2s_handle_s +{ + SPI_I2S_TypeDef *perh; /**< I2S registers base address */ + ald_i2s_init_t init; /**< I2S communication parameters */ + uint16_t *tx_buf; /**< Pointer to I2S Tx transfer buffer */ + uint32_t tx_size; /**< I2S Tx transfer size */ + uint32_t tx_count; /**< I2S Tx transfer counter */ + uint16_t *rx_buf; /**< Pointer to I2S Rx transfer buffer */ + uint32_t rx_size; /**< I2S Rx Transfer size */ + uint32_t rx_count; /**< I2S Rx Transfer Counter */ + + ald_dma_handle_t hdmatx; /**< I2S DMA handle parameters */ + ald_dma_handle_t hdmarx; /**< I2S DMA handle parameters */ + + lock_state_t lock; /**< Locking object */ + ald_i2s_state_t state; /**< I2S communication state */ + uint8_t side; /**< I2S channel side */ + uint32_t err_code; /**< I2S error code */ + + void (*tx_cplt_cbk)(struct ald_i2s_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct ald_i2s_handle_s *arg); /**< Rx completed callback */ + void (*err_cbk)(struct ald_i2s_handle_s *arg); /**< error callback */ +} ald_i2s_handle_t; +/** + * @} + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** @defgroup I2S_Public_Macros I2S Public Macros + * @{ + */ +#define ALD_I2S_RESET_HANDLE_STATE(x) ((x)->state = ALD_I2S_STATE_RESET) +#define ALD_I2S_ENABLE(x) (SET_BIT((x)->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK)) +#define ALD_I2S_DISABLE(x) (CLEAR_BIT((x)->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK)) +/** + * @} + */ + +/** @defgroup I2S_Private_Macros I2S Private Macros + * @{ + */ +#define IS_I2S(x) ((x) == I2S0) +#define IS_I2S_CH_LEN(x) (((x) == ALD_I2S_WIDE_16) || \ + ((x) == ALD_I2S_WIDE_32)) +#define IS_I2S_DATE_LEN(x) (((x) == ALD_I2S_LEN_16) || \ + ((x) == ALD_I2S_LEN_24) || \ + ((x) == ALD_I2S_LEN_32)) +#define IS_I2S_CPOL(x) (((x) == ALD_I2S_INACTIVE_LOW) || \ + ((x) == ALD_I2S_INACTIVE_HIGH)) +#define IS_I2S_STANDARD(x) (((x) == ALD_I2S_STD_PHI) || \ + ((x) == ALD_I2S_STD_MSB) || \ + ((x) == ALD_I2S_STD_LSB) || \ + ((x) == ALD_I2S_STD_PCM)) +#define IS_I2S_PCMS(x) (((x) == ALD_I2S_FRAME_SHORT) || \ + ((x) == ALD_I2S_FRAME_LONG)) +#define IS_I2S_IT(x) (((x) == ALD_I2S_IT_TXE) || \ + ((x) == ALD_I2S_IT_TXOV) || \ + ((x) == ALD_I2S_IT_TXUD) || \ + ((x) == ALD_I2S_IT_TXTH) || \ + ((x) == ALD_I2S_IT_RXNE) || \ + ((x) == ALD_I2S_IT_RXF) || \ + ((x) == ALD_I2S_IT_RXOV) || \ + ((x) == ALD_I2S_IT_RXUD) || \ + ((x) == ALD_I2S_IT_RXTH) || \ + ((x) == ALD_I2S_IT_CRCERR) || \ + ((x) == ALD_I2S_IT_MODF) || \ + ((x) == ALD_I2S_IT_FRE)) +#define IS_I2S_IF(x) (((x) == ALD_I2S_IF_TXE) || \ + ((x) == ALD_I2S_IF_TXOV) || \ + ((x) == ALD_I2S_IF_TXUD) || \ + ((x) == ALD_I2S_IF_TXTH) || \ + ((x) == ALD_I2S_IF_RXNE) || \ + ((x) == ALD_I2S_IF_RXF) || \ + ((x) == ALD_I2S_IF_RXOV) || \ + ((x) == ALD_I2S_IF_RXUD) || \ + ((x) == ALD_I2S_IF_RXTH) || \ + ((x) == ALD_I2S_IF_CRCERR) || \ + ((x) == ALD_I2S_IF_MODF) || \ + ((x) == ALD_I2S_IF_FRE)) +#define IS_I2S_STATUS(x) (((x) == ALD_I2S_STATUS_TXE) || \ + ((x) == ALD_I2S_STATUS_TXF) || \ + ((x) == ALD_I2S_STATUS_TXOV) || \ + ((x) == ALD_I2S_STATUS_TXUD) || \ + ((x) == ALD_I2S_STATUS_TXTH) || \ + ((x) == ALD_I2S_STATUS_RXNE) || \ + ((x) == ALD_I2S_STATUS_RXF) || \ + ((x) == ALD_I2S_STATUS_RXOV) || \ + ((x) == ALD_I2S_STATUS_RXUD) || \ + ((x) == ALD_I2S_STATUS_RXTH) || \ + ((x) == ALD_I2S_STATUS_CHSIDE) || \ + ((x) == ALD_I2S_STATUS_BUSY)) +#define IS_I2S_DMA_REQ(x) (((x) == ALD_I2S_DMA_REQ_TX) || \ + ((x) == ALD_I2S_DMA_REQ_RX)) +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @addtogroup I2S_Public_Functions + * @{ + */ + +/** @addtogroup I2S_Public_Functions_Group1 + * @{ + */ + +ald_status_t ald_i2s_init(ald_i2s_handle_t *hperh); +void ald_i2s_reset(ald_i2s_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup I2S_Public_Functions_Group2 + * @{ + */ +ald_status_t ald_i2s_master_send(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2s_master_recv(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2s_master_send_by_it(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size); +ald_status_t ald_i2s_master_recv_by_it(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size); + +ald_status_t ald_i2s_master_send_by_dma(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t channel); +ald_status_t ald_i2s_master_recv_by_dma(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t dma_ch, uint8_t _dma_ch); +ald_status_t ald_i2s_dma_pause(ald_i2s_handle_t *hperh); +ald_status_t ald_i2s_dma_resume(ald_i2s_handle_t *hperh); +ald_status_t ald_i2s_dma_stop(ald_i2s_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup I2S_Public_Functions_Group3 + * @{ + */ +void ald_i2s_irq_handler(ald_i2s_handle_t *hperh); +void ald_i2s_interrupt_config(ald_i2s_handle_t *hperh, ald_i2s_it_t it, type_func_t state); +void ald_i2s_dma_req_config(ald_i2s_handle_t *hperh, ald_i2s_dma_req_t req, type_func_t state); +flag_status_t ald_i2s_get_status(ald_i2s_handle_t *hperh, ald_i2s_status_t status); +it_status_t ald_i2s_get_it_status(ald_i2s_handle_t *hperh, ald_i2s_it_t it); +flag_status_t ald_i2s_get_flag_status(ald_i2s_handle_t *hperh, ald_i2s_flag_t flag); +flag_status_t ald_i2s_get_mask_flag_status(ald_i2s_handle_t *hperh, ald_i2s_flag_t flag); +void ald_i2s_clear_flag_status(ald_i2s_handle_t *hperh, ald_i2s_flag_t flag); +/** + * @} + */ + +/** @addtogroup I2S_Public_Functions_Group4 + * @{ + */ +ald_i2s_state_t ald_i2s_get_state(ald_i2s_handle_t *hperh); +uint32_t ald_i2s_get_error(ald_i2s_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALD_I2S_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_pis.c b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_pis.c new file mode 100644 index 0000000000..2812fb0092 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_pis.c @@ -0,0 +1,340 @@ +/** + ********************************************************************************* + * + * @file ald_pis.c + * @brief PIS module driver. + * + * @version V1.0 + * @date 03 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 03 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_pis.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup PIS PIS + * @brief PIS module driver + * @{ + */ +/** @defgroup PIS_Public_Functions PIS Public Functions + * @{ + */ + +/** @defgroup PIS_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Create the PIS mode according to the specified parameters in + * the pis_handle_t and create the associated handle. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_pis_create(ald_pis_handle_t *hperh) +{ + if (hperh == NULL) + return ALD_ERROR; + + assert_param(IS_PIS_SRC(hperh->init.producer_src)); + assert_param(IS_PIS_TRIG(hperh->init.consumer_trig)); + assert_param(IS_PIS_CLOCK(hperh->init.producer_clk)); + assert_param(IS_PIS_CLOCK(hperh->init.consumer_clk)); + assert_param(IS_PIS_EDGE(hperh->init.producer_edge)); + assert_param(IS_PIS_SIGNAL_MODE(hperh->init.producer_signal)); + + __LOCK(hperh); + hperh->perh = PIS; + + /* get location of consumer in channel and position of con0/con1 + * accord to comsumer_trig information */ + hperh->consumer_ch = (ald_pis_ch_t)(hperh->init.consumer_trig & 0x0F); + hperh->consumer_con = (ald_pis_con_t)((hperh->init.consumer_trig >> 4) & 0x0F); + hperh->consumer_pos = (1U << (uint32_t)((hperh->init.consumer_trig >> 8) & 0xFF)); + + if (hperh->perh->CH_CON[hperh->consumer_ch] != 0) + { + __UNLOCK(hperh); + return ALD_BUSY; + } + + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SRCS_MSK, ((hperh->init.producer_src) >> 4) << PIS_CH0_CON_SRCS_POSS); + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_MSIGS_MSK, ((hperh->init.producer_src) & 0xf) << PIS_CH0_CON_MSIGS_POSS); + + if (hperh->init.producer_clk == hperh->init.consumer_clk) + { + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, ALD_PIS_SYN_DIRECT << PIS_CH0_CON_SYNCSEL_POSS); + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_TSCKS_MSK, (hperh->init.consumer_clk) << PIS_CH0_CON_TSCKS_POSS); + } + else + { + if (hperh->init.producer_signal == ALD_PIS_OUT_LEVEL) + { + if (hperh->init.consumer_clk == ALD_PIS_CLK_PCLK) + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, ALD_PIS_SYN_LEVEL_ASY_APB << PIS_CH0_CON_SYNCSEL_POSS); + + if (hperh->init.consumer_clk == ALD_PIS_CLK_HCLK) + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, ALD_PIS_SYN_LEVEL_ASY_AHB << PIS_CH0_CON_SYNCSEL_POSS); + } + + if (hperh->init.producer_signal == ALD_PIS_OUT_PULSE) + { + if (hperh->init.consumer_clk == ALD_PIS_CLK_PCLK) + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, ALD_PIS_SYN_PULSE_ASY_APB << PIS_CH0_CON_SYNCSEL_POSS); + + if (hperh->init.consumer_clk == ALD_PIS_CLK_HCLK) + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, ALD_PIS_SYN_PULSE_ASY_AHB << PIS_CH0_CON_SYNCSEL_POSS); + } + } + + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_TSCKS_MSK, hperh->init.consumer_clk << PIS_CH0_CON_TSCKS_POSS); + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_EDGS_MSK, hperh->init.producer_edge << PIS_CH0_CON_EDGS_POSS); + hperh->check_info = hperh->perh->CH_CON[hperh->consumer_ch]; + + /* enable consumer bit, switch pin of consumer */ + if (hperh->init.input_chan == ALD_PIS_CHAN_INPUT) + { + switch (hperh->consumer_con) + { + case ALD_PIS_CON_0: + PIS->TAR_CON0 |= hperh->consumer_pos; + break; + + case ALD_PIS_CON_1: + PIS->TAR_CON1 |= hperh->consumer_pos; + break; + + default: + break; + } + } + + __UNLOCK(hperh); + return ALD_OK; +} + +/** + * @brief Destroy the PIS mode according to the specified parameters in + * the pis_init_t and create the associated handle. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_pis_destroy(ald_pis_handle_t *hperh) +{ + assert_param(IS_PIS(hperh->perh)); + + if (hperh->check_info != hperh->perh->CH_CON[hperh->consumer_ch]) + return ALD_ERROR; + + __LOCK(hperh); + + CLEAR_BIT(PIS->CH_OER, (1U << (uint32_t)hperh->consumer_ch)); + WRITE_REG(hperh->perh->CH_CON[hperh->consumer_ch], 0x0); + + switch (hperh->consumer_con) + { + case ALD_PIS_CON_0: + PIS->TAR_CON0 &= ~(hperh->consumer_pos); + break; + + case ALD_PIS_CON_1: + PIS->TAR_CON1 &= ~(hperh->consumer_pos); + break; + + default: + break; + } + + hperh->state = ALD_PIS_STATE_RESET; + __UNLOCK(hperh); + + return ALD_OK; +} +/** + * @} + */ + +/** @defgroup PIS_Public_Functions_Group2 Operation functions + * @brief PIS output enable or disable functions + * @{ + */ + +/** + * @brief Start the PIS output function. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @param ch: The PIS channel enable output + * This parameter can be one of the following values: + * @arg PIS_OUT_CH_0 + * @arg PIS_OUT_CH_1 + * @arg PIS_OUT_CH_2 + * @arg PIS_OUT_CH_3 + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_pis_output_start(ald_pis_handle_t *hperh, ald_pis_out_ch_t ch) +{ + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_OUPUT_CH(ch)); + __LOCK(hperh); + SET_BIT(PIS->CH_OER, (0x1UL << (uint32_t)ch)); + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Stop the PIS output function. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @param ch: The PIS channel disable output + * This parameter can be one of the following values: + * @arg PIS_OUT_CH_0 + * @arg PIS_OUT_CH_1 + * @arg PIS_OUT_CH_2 + * @arg PIS_OUT_CH_3 + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_pis_output_stop(ald_pis_handle_t *hperh, ald_pis_out_ch_t ch) +{ + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_OUPUT_CH(ch)); + __LOCK(hperh); + CLEAR_BIT(PIS->CH_OER, (0x1UL << (uint32_t)ch)); + __UNLOCK(hperh); + + return ALD_OK; +} +/** + * @} + */ + +/** @defgroup PIS_Public_Functions_Group3 Peripheral State and Errors functions + * @brief PIS State and Errors functions + * @{ + */ + +/** + * @brief Returns the PIS state. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @retval ALD state + */ +ald_pis_state_t ald_pis_get_state(ald_pis_handle_t *hperh) +{ + assert_param(IS_PIS(hperh->perh)); + return hperh->state; +} + +/** + * @} + */ + +/** @defgroup PIS_Public_Functions_Group4 modulate output functions + * @brief PIS modulate output signal functions + * @{ + */ + +/** + * @brief Config the PIS modulate signal function + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @param config: Pointer to a pis_modulate_config_t structure that + * contains the selected target (UART0,UART1,UART2,UART3 or + * LPUART0) how to modulate the target output signal. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_pis_modu_config(ald_pis_handle_t *hperh, ald_pis_modulate_config_t *config) +{ + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_MODU_TARGET(config->target)); + assert_param(IS_PIS_MODU_LEVEL(config->level)); + assert_param(IS_PIS_MODU_SRC(config->src)); + assert_param(IS_PIS_MODU_CHANNEL(config->channel)); + __LOCK(hperh); + + switch (config->target) + { + case ALD_PIS_UART0_TX: + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXMLVLS_MSK, config->level << PIS_UART0_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXMSS_MSK, config->src << PIS_UART0_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXSIGS_MSK, config->channel << PIS_UART0_TXMCR_TXSIGS_POSS); + break; + + case ALD_PIS_UART1_TX: + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXMLVLS_MSK, config->level << PIS_UART1_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXMSS_MSK, config->src << PIS_UART1_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXSIGS_MSK, config->channel << PIS_UART1_TXMCR_TXSIGS_POSS); + break; + + case ALD_PIS_UART2_TX: + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXMLVLS_MSK, config->level << PIS_UART2_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXMSS_MSK, config->src << PIS_UART2_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXSIGS_MSK, config->channel << PIS_UART2_TXMCR_TXSIGS_POSS); + break; + + case ALD_PIS_UART3_TX: + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXMLVLS_MSK, config->level << PIS_UART3_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXMSS_MSK, config->src << PIS_UART3_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXSIGS_MSK, config->channel << PIS_UART3_TXMCR_TXSIGS_POSS); + break; + + case ALD_PIS_UART4_TX: + MODIFY_REG(hperh->perh->UART4_TXMCR, PIS_UART4_TXMCR_TXMLVLS_MSK, config->level << PIS_UART4_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART4_TXMCR, PIS_UART4_TXMCR_TXMSS_MSK, config->src << PIS_UART4_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART4_TXMCR, PIS_UART4_TXMCR_TXSIGS_MSK, config->channel << PIS_UART4_TXMCR_TXSIGS_POSS); + break; + + default: + break; + } + + __UNLOCK(hperh); + return ALD_OK; +} +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_pis.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_pis.h new file mode 100644 index 0000000000..ff22fcd32e --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_pis.h @@ -0,0 +1,711 @@ +/** + ********************************************************************************* + * + * @file ald_pis.h + * @brief Header file of PIS driver. + * + * @version V1.0 + * @date 03 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 03 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_PIS_H__ +#define __ALD_PIS_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_utils.h" + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Constants -------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup PIS + * @{ + */ + +/** @defgroup PIS_Public_Types PIS Public Types + * @verbatim + In PIS module, for the convenience of code maintenance, + TIMERx is used to indicate the sequence of the timer peripheral. + Different product series TIMERx represent different meanings: + TIMER0 ----> AD16C4T + TIMER4 ----> BS16T + TIMER5 ----> GP16C4T0 + TIMER6 ----> GP16C4T1 + TIMER7 ----> GP16C4T2 + @endverbatim + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** + * @brief pis src enum brief description + */ +typedef enum +{ + ALD_PIS_NON = 0x0U, /**< No async */ + ALD_PIS_GPIO_PIN0 = 0x10U, /**< Pin0, level,support async */ + ALD_PIS_GPIO_PIN1 = 0x11U, /**< Pin1, level,support async */ + ALD_PIS_GPIO_PIN2 = 0x12U, /**< Pin2, level,support async */ + ALD_PIS_GPIO_PIN3 = 0x13U, /**< Pin3, level,support async */ + ALD_PIS_GPIO_PIN4 = 0x14U, /**< Pin4, level,support async */ + ALD_PIS_GPIO_PIN5 = 0x15U, /**< Pin5, level,support async */ + ALD_PIS_GPIO_PIN6 = 0x16U, /**< Pin6, level,support async */ + ALD_PIS_GPIO_PIN7 = 0x17U, /**< Pin7, level,support async */ + ALD_PIS_GPIO_PIN8 = 0x18U, /**< Pin8, level,support async */ + ALD_PIS_GPIO_PIN9 = 0x19U, /**< Pin9, level,support async */ + ALD_PIS_GPIO_PIN10 = 0x1aU, /**< Pin10, level,support async */ + ALD_PIS_GPIO_PIN11 = 0x1bU, /**< Pin11, level,support async */ + ALD_PIS_GPIO_PIN12 = 0x1cU, /**< Pin12, level,support async */ + ALD_PIS_GPIO_PIN13 = 0x1dU, /**< Pin13, level,support async */ + ALD_PIS_GPIO_PIN14 = 0x1eU, /**< Pin14, level,support async */ + ALD_PIS_GPIO_PIN15 = 0x1fU, /**< Pin15, level,support async */ + ALD_PIS_CLK_HSCO = 0x20U, /**< CLK: HSCO, level,support async */ + ALD_PIS_CLK_LSCO = 0x21U, /**< CLK: LSCO, level,support async */ + ALD_PIS_CLK_BUZ = 0x22U, /**< PCLK: BUZ, level,support async */ + ALD_PIS_ADC0_INSERT = 0x60U, /**< ADC0 insert, pclk2 pulse,support async */ + ALD_PIS_ADC0_NORMAL = 0x61U, /**< ADC0 normal, pclk2 pulse,support async */ + ALD_PIS_ADC0_AWDT = 0x62U, /**< ADC0 AWDT */ + ALD_PIS_LVD = 0x70U, /**< LVD, level,support async */ + ALD_PIS_UART0_RESERVE0 = 0x80U, /**< Uart0 reserve bit 0 */ + ALD_PIS_UART0_RESERVE1 = 0x81U, /**< Uart0 reserve bit 1 */ + ALD_PIS_UART0_RESERVE2 = 0x82U, /**< Uart0 reserve bit 2 */ + ALD_PIS_UART0_RTSOUT = 0x83U, /**< Uart0 rtsout, level */ + ALD_PIS_UART0_TXOUT = 0x84U, /**< Uart0 txout, level */ + ALD_PIS_UART0_SYN_SEND = 0x85U, /**< Uart0 syn send, pulse */ + ALD_PIS_UART0_SYN_RECV = 0x86U, /**< Uart0 syn recv, pulse */ + ALD_PIS_UART1_RESERVE0 = 0x90U, /**< Uart1 reserve bit 0 */ + ALD_PIS_UART1_RESERVE1 = 0x91U, /**< Uart1 reserve bit 1 */ + ALD_PIS_UART1_RESERVE2 = 0x92U, /**< Uart1 reserve bit 2 */ + ALD_PIS_UART1_RTSOUT = 0x93U, /**< Uart1 rtsout, level */ + ALD_PIS_UART1_TXOUT = 0x94U, /**< Uart1 txout, level */ + ALD_PIS_UART1_SYN_SEND = 0x95U, /**< Uart1 syn send, pulse */ + ALD_PIS_UART1_SYN_RECV = 0x96U, /**< Uart1 syn recv, pulse */ + ALD_PIS_UART2_RESERVE0 = 0xa0U, /**< Uart2 reserve bit 0 */ + ALD_PIS_UART2_RESERVE1 = 0xa1U, /**< Uart2 reserve bit 1 */ + ALD_PIS_UART2_RESERVE2 = 0xa2U, /**< Uart2 reserve bit 2 */ + ALD_PIS_UART2_RTSOUT = 0xa3U, /**< Uart2 rtsout, level */ + ALD_PIS_UART2_TXOUT = 0xa4U, /**< Uart2 txout, level */ + ALD_PIS_UART2_SYN_SEND = 0xa5U, /**< Uart2 syn send, pulse */ + ALD_PIS_UART2_SYN_RECV = 0xa6U, /**< Uart2 syn recv, pulse */ + ALD_PIS_UART3_RESERVE0 = 0xb0U, /**< Uart3 reserve bit 0 */ + ALD_PIS_UART3_RESERVE1 = 0xb1U, /**< Uart3 reserve bit 1 */ + ALD_PIS_UART3_RESERVE2 = 0xb2U, /**< Uart3 reserve bit 2 */ + ALD_PIS_UART3_RTSOUT = 0xb3U, /**< Uart3 rtsout, level */ + ALD_PIS_UART3_TXOUT = 0xb4U, /**< Uart3 txout, level */ + ALD_PIS_UART3_SYN_SEND = 0xb5U, /**< Uart3 syn send, pulse */ + ALD_PIS_UART3_SYN_RECV = 0xb6U, /**< Uart3 syn recv, pulse */ + ALD_PIS_UART4_RESERVE0 = 0xc0U, /**< Uart4 reserve bit 0 */ + ALD_PIS_UART4_RESERVE1 = 0xc1U, /**< Uart4 reserve bit 1 */ + ALD_PIS_UART4_RESERVE2 = 0xc2U, /**< Uart4 reserve bit 2 */ + ALD_PIS_UART4_RTSOUT = 0xc3U, /**< Uart4 rtsout, level */ + ALD_PIS_UART4_TXOUT = 0xc4U, /**< Uart4 txout, level */ + ALD_PIS_UART4_SYN_SEND = 0xc5U, /**< Uart4 syn send, pulse */ + ALD_PIS_UART4_SYN_RECV = 0xc6U, /**< Uart4 syn recv, pulse */ + ALD_PIS_SPI0_RECV = 0xe0U, /**< Spi0 recv, plck1 pulse */ + ALD_PIS_SPI0_SEND = 0xe1U, /**< Spi0 send, plck1 pulse */ + ALD_PIS_SPI0_NE = 0xe2U, /**< Spi0 ne, plck1 level */ + ALD_PIS_SPI1_RECV = 0xf0U, /**< Spi1 recv, plck1 pulse */ + ALD_PIS_SPI1_SEND = 0xf1U, /**< Spi1 send, plck1 pulse */ + ALD_PIS_SPI1_NE = 0xf2U, /**< Spi1 ne, plck1 level */ + ALD_PIS_I2C0_RECV = 0x100U, /**< I2c0 recv, plck1 level */ + ALD_PIS_I2C0_SEND = 0x101U, /**< I2c0 send, plck1 level */ + ALD_PIS_I2C1_RECV = 0x110U, /**< I2c1 recv, plck1 level */ + ALD_PIS_I2C1_SEND = 0x111U, /**< I2c1 send, plck1 level */ + ALD_PIS_TIMER0_UPDATA = 0x120U, /**< Timer0 updata, plck1 pulse */ + ALD_PIS_TIMER0_TRIG = 0x121U, /**< Timer0 trig, plck1 pulse */ + ALD_PIS_TIMER0_INPUT_1 = 0x122U, /**< Timer0 chan1 input catch, plck1 pulse */ + ALD_PIS_TIMER0_OUTPUT_1 = 0x122U, /**< Timer0 chan1 output compare, plck1 pulse */ + ALD_PIS_TIMER0_INPUT_2 = 0x124U, /**< Timer0 chan2 input catch, plck1 pulse */ + ALD_PIS_TIMER0_OUTPUT_2 = 0x124U, /**< Timer0 chan2 output compare, plck1 pulse */ + ALD_PIS_TIMER0_INPUT_3 = 0x126U, /**< Timer0 chan3 input catch, plck1 pulse */ + ALD_PIS_TIMER0_OUTPUT_3 = 0x126U, /**< Timer0 chan3 output compare, plck1 pulse */ + ALD_PIS_TIMER0_INPUT_4 = 0x128U, /**< Timer0 chan4 input catch, plck1 pulse */ + ALD_PIS_TIMER0_OUTPUT_4 = 0x128U, /**< Timer0 chan4 output compare, plck1 pulse */ + ALD_PIS_TIMER5_UPDATA = 0x1c0U, /**< Timer5 updata, plck1 pulse */ + ALD_PIS_TIMER5_TRIG = 0x1c1U, /**< Timer5 trig, plck1 pulse */ + ALD_PIS_TIMER5_INPUT_1 = 0x1c2U, /**< Timer5 chan1 input catch, plck1 pulse */ + ALD_PIS_TIMER5_OUTPUT_1 = 0x1c2U, /**< Timer5 chan1 output compare, plck1 pulse */ + ALD_PIS_TIMER5_INPUT_2 = 0x1c4U, /**< Timer5 chan2 input catch, plck1 pulse */ + ALD_PIS_TIMER5_OUTPUT_2 = 0x1c4U, /**< Timer5 chan2 output compare, plck1 pulse */ + ALD_PIS_TIMER5_INPUT_3 = 0x1c6U, /**< Timer5 chan3 input catch, plck1 pulse */ + ALD_PIS_TIMER5_OUTPUT_3 = 0x1c6U, /**< Timer5 chan3 output compare, plck1 pulse */ + ALD_PIS_TIMER5_INPUT_4 = 0x1c8U, /**< Timer5 chan4 input catch, plck1 pulse */ + ALD_PIS_TIMER5_OUTPUT_4 = 0x1c8U, /**< Timer5 chan4 output compare, plck1 pulse */ + ALD_PIS_TIMER6_UPDATA = 0x1d0U, /**< Timer6 updata, plck1 pulse */ + ALD_PIS_TIMER6_TRIG = 0x1d1U, /**< Timer6 trig, plck1 pulse */ + ALD_PIS_TIMER6_INPUT_1 = 0x1d2U, /**< Timer6 chan1 input catch, plck1 pulse */ + ALD_PIS_TIMER6_OUTPUT_1 = 0x1d2U, /**< Timer6 chan1 output compare, plck1 pulse */ + ALD_PIS_TIMER6_INPUT_2 = 0x1d4U, /**< Timer6 chan2 input catch, plck1 pulse */ + ALD_PIS_TIMER6_OUTPUT_2 = 0x1d4U, /**< Timer6 chan2 output compare, plck1 pulse */ + ALD_PIS_TIMER6_INPUT_3 = 0x1d6U, /**< Timer6 chan3 input catch, plck1 pulse */ + ALD_PIS_TIMER6_OUTPUT_3 = 0x1d6U, /**< Timer6 chan3 output compare, plck1 pulse */ + ALD_PIS_TIMER6_INPUT_4 = 0x1d8U, /**< Timer6 chan4 input catch, plck1 pulse */ + ALD_PIS_TIMER6_OUTPUT_4 = 0x1d8U, /**< Timer6 chan4 output compare, plck1 pulse */ + ALD_PIS_TIMER7_UPDATA = 0x1e0U, /**< Timer7 updata, plck1 pulse */ + ALD_PIS_TIMER7_TRIG = 0x1e1U, /**< Timer7 trig, plck1 pulse */ + ALD_PIS_TIMER7_INPUT_1 = 0x1e2U, /**< Timer7 chan1 input catch, plck1 pulse */ + ALD_PIS_TIMER7_OUTPUT_1 = 0x1e2U, /**< Timer7 chan1 output compare, plck1 pulse */ + ALD_PIS_TIMER7_INPUT_2 = 0x1e4U, /**< Timer7 chan2 input catch, plck1 pulse */ + ALD_PIS_TIMER7_OUTPUT_2 = 0x1e4U, /**< Timer7 chan2 output compare, plck1 pulse */ + ALD_PIS_TIMER7_INPUT_3 = 0x1e6U, /**< Timer7 chan3 input catch, plck1 pulse */ + ALD_PIS_TIMER7_OUTPUT_3 = 0x1e6U, /**< Timer7 chan3 output compare, plck1 pulse */ + ALD_PIS_TIMER7_INPUT_4 = 0x1e8U, /**< Timer7 chan4 input catch, plck1 pulse */ + ALD_PIS_TIMER7_OUTPUT_4 = 0x1e8U, /**< Timer7 chan4 output compare, plck1 pulse */ + ALD_PIS_TIMER4_UPDATA = 0x1b0U, /**< Timer4 updata, plck1 pulse */ + ALD_PIS_TIMER4_TRIG = 0x1b1U, /**< Timer4 trig, plck1 pulse */ + ALD_PIS_DMA_CH0 = 0x190U, /**< DMA CH0 complete, plck1 pulse, support async */ + ALD_PIS_DMA_CH1 = 0x191U, /**< DMA CH1 complete, plck1 pulse, support async */ + ALD_PIS_DMA_CH2 = 0x192U, /**< DMA CH2 complete, plck1 pulse, support async */ + ALD_PIS_DMA_CH3 = 0x193U, /**< DMA CH3 complete, plck1 pulse, support async */ + ALD_PIS_DMA_CH4 = 0x194U, /**< DMA CH4 complete, plck1 pulse, support async */ + ALD_PIS_DMA_CH5 = 0x195U, /**< DMA CH5 complete, plck1 pulse, support async */ + ALD_PIS_DMA_CH6 = 0x196U, /**< DMA CH6 complete, plck1 pulse, support async */ + ALD_PIS_DMA_ALL = 0x19fU, /**< DMA all channel complete, plck1 pulse, support async */ +} ald_pis_src_t; + +/** + * @brief pis trig enum brief description + */ + +typedef enum +{ + ALD_PIS_CH4_TIMER0_ITR0 = 0x0034U, /** Tim0 internal input chan0 */ + ALD_PIS_CH5_TIMER0_ITR1 = 0x0035U, /** Tim0 internal input chan1 */ + ALD_PIS_CH6_TIMER0_ITR2 = 0x0036U, /** Tim0 internal input chan2 */ + ALD_PIS_CH7_TIMER0_ITR3 = 0x0037U, /** Tim0 internal input chan3 */ + ALD_PIS_CH4_TIMER1_ITR0 = 0x0034U, /** Tim1 internal input chan0 */ + ALD_PIS_CH5_TIMER1_ITR1 = 0x0035U, /** Tim1 internal input chan1 */ + ALD_PIS_CH6_TIMER1_ITR2 = 0x0036U, /** Tim1 internal input chan2 */ + ALD_PIS_CH7_TIMER1_ITR3 = 0x0037U, /** Tim1 internal input chan3 */ + ALD_PIS_CH4_TIMER2_ITR0 = 0x0034U, /** Tim2 internal input chan0 */ + ALD_PIS_CH5_TIMER2_ITR1 = 0x0035U, /** Tim2 internal input chan1 */ + ALD_PIS_CH6_TIMER2_ITR2 = 0x0036U, /** Tim2 internal input chan2 */ + ALD_PIS_CH7_TIMER2_ITR3 = 0x0037U, /** Tim2 internal input chan3 */ + ALD_PIS_CH4_TIMER3_ITR0 = 0x0034U, /** Tim3 internal input chan0 */ + ALD_PIS_CH5_TIMER3_ITR1 = 0x0035U, /** Tim3 internal input chan1 */ + ALD_PIS_CH6_TIMER3_ITR2 = 0x0036U, /** Tim3 internal input chan2 */ + ALD_PIS_CH7_TIMER3_ITR3 = 0x0037U, /** Tim3 internal input chan3 */ + ALD_PIS_CH4_ADC0_NORMAL = 0x0034U, /** ADC0 normal transform */ + ALD_PIS_CH5_ADC0_INSERT = 0x0035U, /** ADC0 insert transform */ + ALD_PIS_CH7_DMA_REQUEST = 0x0037U, /** DMA request 7 */ + ALD_PIS_CH7_UART4_RXD = 0x0417U, /**< Uart4 Rx data */ + ALD_PIS_CH6_UART3_RXD = 0x0316U, /**< Uart3 Rx data */ + ALD_PIS_CH5_UART2_RXD = 0x0215U, /**< Uart2 Rx data */ + ALD_PIS_CH4_UART1_RXD = 0x0114U, /**< Uart1 Rx data */ + ALD_PIS_CH3_UART0_RXD = 0x0013U, /**< Uart0 Rx data */ + ALD_PIS_CH4_TIMER3_CH4IN = 0x1B04U, /**< Tim3 input chan4 */ + ALD_PIS_CH4_TIMER2_CH4IN = 0x1304U, /**< Tim2 input chan4 */ + ALD_PIS_CH3_SPI1_CLK = 0x0F13U, /**< Spi1 clk */ + ALD_PIS_CH7_TIMER3_CH3IN = 0x1A07U, /**< Tim3 input chan3 */ + ALD_PIS_CH7_TIMER2_CH3IN = 0x1207U, /**< Tim2 input chan3 */ + ALD_PIS_CH2_SPI1_RX = 0x0E12U, /**< Spi1 rx */ + ALD_PIS_CH6_TIMER3_CH2IN = 0x1906U, /**< Tim3 input chan2 */ + ALD_PIS_CH6_TIMER2_CH2IN = 0x1106U, /**< Tim2 input chan2 */ + ALD_PIS_CH1_SPI0_CLK = 0x0D11U, /**< SPI0 CLK */ + ALD_PIS_CH5_TIMER3_CH1IN = 0x1805U, /**< Tim3 input chan1 */ + ALD_PIS_CH5_TIMER2_CH1IN = 0x1005U, /**< Tim2 input chan1 */ + ALD_PIS_CH0_SPI0_RX = 0x0C10U, /**< SPI0 RX */ + ALD_PIS_CH4_TIMER1_CH4IN = 0x0B04U, /**< Tim1 input chan4 */ + ALD_PIS_CH4_TIMER0_CH4IN = 0x0304U, /**< Tim0 input chan4 */ + ALD_PIS_CH3_TIMER1_CH3IN = 0x0A03U, /**< Tim1 input chan3 */ + ALD_PIS_CH3_TIMER0_CH3IN = 0x0203U, /**< Tim0 input chan3 */ + ALD_PIS_CH2_TIMER1_CH2IN = 0x0902U, /**< Tim1 input chan2 */ + ALD_PIS_CH2_TIMER0_CH2IN = 0x0102U, /**< Tim0 input chan2 */ + ALD_PIS_CH1_TIMER1_CH1IN = 0x0801U, /**< Tim1 input chan1 */ + ALD_PIS_CH1_TIMER0_CH1IN = 0x0001U, /**< Tim0 input chan1 */ + ALD_PIS_CH0_TIMER0_BRKIN = 0x0400U, /**< Tim0 break in */ + ALD_PIS_TRIG_RESERVE = 0xFFFFU, /**< Other Consumer */ +} ald_pis_trig_t; + +/** + * @brief Clock select + */ +typedef enum +{ + ALD_PIS_CLK_PCLK = 0U, /**< APB peripherals clock */ + ALD_PIS_CLK_HCLK = 2U, /**< AHB peripherals clock */ + ALD_PIS_CLK_RESERVE = 3U, /**< reserve clock */ +} ald_pis_clock_t; + +/** + * @brief Level select + */ +typedef enum +{ + ALD_PIS_EDGE_NONE = 0U, /**< None edge */ + ALD_PIS_EDGE_UP = 1U, /**< Up edge */ + ALD_PIS_EDGE_DOWN = 2U, /**< Down edge */ + ALD_PIS_EDGE_UP_DOWN = 3U, /**< Up and down edge */ +} ald_pis_edge_t; + +/** + * @brief Output style + */ +typedef enum +{ + ALD_PIS_OUT_LEVEL = 0U, /**< Level */ + ALD_PIS_OUT_PULSE = 1U, /**< Pulse */ +} ald_pis_output_t; +/** + * @brief Sync select + */ +typedef enum +{ + ALD_PIS_SYN_DIRECT = 0U, /**< Direct */ + ALD_PIS_SYN_LEVEL_ASY_APB = 1U, /**< Producer level signal and Consumer in APB */ + ALD_PIS_SYN_LEVEL_ASY_AHB = 3U, /**< Producer level signal and Consumer in AHB */ + ALD_PIS_SYN_PULSE_ASY_APB = 4U, /**< Producer Pulse signal and Consumer in APB */ + ALD_PIS_SYN_PULSE_ASY_AHB = 6U, /**< Producer Pulse signal and Consumer in AHB */ +} ald_pis_syncsel_t; + +/** + * @brief Pis channel + */ +typedef enum +{ + ALD_PIS_CH_0 = 0U, /**< Channel 0 */ + ALD_PIS_CH_1 = 1U, /**< Channel 1 */ + ALD_PIS_CH_2 = 2U, /**< Channel 2 */ + ALD_PIS_CH_3 = 3U, /**< Channel 3 */ + ALD_PIS_CH_4 = 4U, /**< Channel 4 */ + ALD_PIS_CH_5 = 5U, /**< Channel 5 */ + ALD_PIS_CH_6 = 6U, /**< Channel 6 */ + ALD_PIS_CH_7 = 7U, /**< Channel 7 */ +} ald_pis_ch_t; + +/** + * @brief Pis output channel + */ +typedef enum +{ + ALD_PIS_OUT_CH_0 = 0U, /**< Channel 0 */ + ALD_PIS_OUT_CH_1 = 1U, /**< Channel 1 */ + ALD_PIS_OUT_CH_2 = 2U, /**< Channel 2 */ + ALD_PIS_OUT_CH_3 = 3U, /**< Channel 3 */ + ALD_PIS_OUT_CH_4 = 4U, /**< Channel 4 */ + ALD_PIS_OUT_CH_5 = 5U, /**< Channel 5 */ + ALD_PIS_OUT_CH_6 = 6U, /**< Channel 6 */ + ALD_PIS_OUT_CH_7 = 7U, /**< Channel 7 */ +} ald_pis_out_ch_t; + +/** + * @brief Indirect value,no care of it. + */ +typedef enum +{ + ALD_PIS_CON_0 = 0U, /**< Con 0 */ + ALD_PIS_CON_1 = 1U, /**< Con 1 */ + ALD_PIS_CON_NONE = 2U, /**< None */ +} ald_pis_con_t; + +/** + * @brief PIS state structures definition + */ +typedef enum +{ + ALD_PIS_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + ALD_PIS_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + ALD_PIS_STATE_BUSY = 0x02U, /**< An internal process is ongoing */ + ALD_PIS_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + ALD_PIS_STATE_ERROR = 0x04U, /**< Error */ +} ald_pis_state_t; + +/** + * @brief PIS modulate target + */ +typedef enum +{ + ALD_PIS_UART0_TX = 0U, /**< Modulate uart0 tx */ + ALD_PIS_UART1_TX = 1U, /**< Modulate uart1 tx */ + ALD_PIS_UART2_TX = 2U, /**< Modulate uart2 tx */ + ALD_PIS_UART3_TX = 3U, /**< Modulate uart3 tx */ + ALD_PIS_UART4_TX = 4U, /**< Modulate uart4 tx */ +} ald_pis_modu_targ_t; + +/** + * @brief PIS modulate level + */ +typedef enum +{ + ALD_PIS_LOW_LEVEL = 0U, /**< Modulate low level */ + ALD_PIS_HIGH_LEVEL = 1U, /**< Modulate high level */ +} ald_pis_modu_level_t; + +/** + * @brief PIS modulate source + */ +typedef enum +{ + ALD_PIS_SRC_NONE = 0U, /**< Stop modulate */ + ALD_PIS_SRC_TIMER0 = 1U, /**< Modulate source is TIMER0 */ + ALD_PIS_SRC_TIMER5 = 4U, /**< Modulate source is TIMER5 */ + ALD_PIS_SRC_TIMER6 = 5U, /**< Modulate source is TIMER6 */ + ALD_PIS_SRC_TIMER7 = 6U, /**< Modulate source is TIMER7 */ + ALD_PIS_SRC_BUZ = 8U, /**< Modulate source is buz */ +} ald_pis_modu_src_t; + +/** + * @brief PIS modulate channel + */ +typedef enum +{ + ALD_PIS_TIMER_CH1 = 0U, /**< Src is TIMERx and choose channel 1 */ + ALD_PIS_TIMER_CH2 = 1U, /**< Src is TIMERx and choose channel 2 */ + ALD_PIS_TIMER_CH3 = 2U, /**< Src is TIMERx and choose channel 3 */ + ALD_PIS_TIMER_CH4 = 3U, /**< Src is TIMERx and choose channel 4 */ +} ald_pis_modu_channel_t; + +/** + * @brief PIS input channel choose + */ +typedef enum +{ + ALD_PIS_NONE_INPUT = 0U, /**< Consumer input none */ + ALD_PIS_PORT_INPUT = 1U, /**< Consumer input choose external port */ + ALD_PIS_CHAN_INPUT = 2U, /**< Consumer input choose pis channel */ +} ald_pis_input_sel_t; + +/** + * @brief PIS init structure definition + */ +typedef struct +{ + ald_pis_src_t producer_src; /**< Producer entry */ + ald_pis_output_t producer_signal; /**< Producer signal mode */ + ald_pis_clock_t producer_clk; /**< Producer module clock */ + ald_pis_edge_t producer_edge; /**< Producer module pin output edge */ + ald_pis_trig_t consumer_trig; /**< Consumer entry */ + ald_pis_clock_t consumer_clk; /**< Consumer clock */ + ald_pis_input_sel_t input_chan; /**< Consumer input channel */ +} ald_pis_init_t; + +/** + * @brief PIS modulate config structure definition + */ +typedef struct +{ + ald_pis_modu_targ_t target; /**< Modulate target */ + ald_pis_modu_level_t level; /**< Modulate level */ + ald_pis_modu_src_t src; /**< Modulate src */ + ald_pis_modu_channel_t channel; /**< Modulate channel */ +} ald_pis_modulate_config_t; + +/** + * @brief PIS Handle Structure definition + */ +typedef struct ald_pis_handle_s +{ + PIS_TypeDef *perh; /**< Register base address */ + ald_pis_init_t init; /**< PIS required parameters */ + ald_pis_ch_t consumer_ch; /**< Indirect value, no care of it */ + ald_pis_con_t consumer_con; /**< Indirect value, no care of it */ + uint8_t consumer_pos; /**< Indirect value, no care of it */ + uint32_t check_info; /**< When destroy a handle ,user need check whether is right that ready to destroy */ + lock_state_t lock; /**< Locking object */ + ald_pis_state_t state; /**< PIS operation state */ +} ald_pis_handle_t; +/** + * @} + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** @defgroup PIS_Private_Macros PIS Private Macros + * @{ + */ +#define IS_PIS(x) (((x) == PIS)) +#define IS_PIS_SRC(x) (((x) == ALD_PIS_NON) || \ + ((x) == ALD_PIS_GPIO_PIN0) || \ + ((x) == ALD_PIS_GPIO_PIN1) || \ + ((x) == ALD_PIS_GPIO_PIN2) || \ + ((x) == ALD_PIS_GPIO_PIN3) || \ + ((x) == ALD_PIS_GPIO_PIN4) || \ + ((x) == ALD_PIS_GPIO_PIN5) || \ + ((x) == ALD_PIS_GPIO_PIN6) || \ + ((x) == ALD_PIS_GPIO_PIN7) || \ + ((x) == ALD_PIS_GPIO_PIN8) || \ + ((x) == ALD_PIS_GPIO_PIN9) || \ + ((x) == ALD_PIS_GPIO_PIN10) || \ + ((x) == ALD_PIS_GPIO_PIN11) || \ + ((x) == ALD_PIS_GPIO_PIN12) || \ + ((x) == ALD_PIS_GPIO_PIN13) || \ + ((x) == ALD_PIS_GPIO_PIN14) || \ + ((x) == ALD_PIS_GPIO_PIN15) || \ + ((x) == ALD_PIS_CLK_HSCO) || \ + ((x) == ALD_PIS_CLK_LSCO) || \ + ((x) == ALD_PIS_CLK_BUZ) || \ + ((x) == ALD_PIS_ADC0_INSERT) || \ + ((x) == ALD_PIS_ADC0_NORMAL) || \ + ((x) == ALD_PIS_ADC0_AWDT) || \ + ((x) == ALD_PIS_LVD) || \ + ((x) == ALD_PIS_UART0_RESERVE0) || \ + ((x) == ALD_PIS_UART0_RESERVE1) || \ + ((x) == ALD_PIS_UART0_RESERVE2) || \ + ((x) == ALD_PIS_UART0_RTSOUT) || \ + ((x) == ALD_PIS_UART0_TXOUT) || \ + ((x) == ALD_PIS_UART0_SYN_SEND) || \ + ((x) == ALD_PIS_UART0_SYN_RECV) || \ + ((x) == ALD_PIS_UART1_RESERVE0) || \ + ((x) == ALD_PIS_UART1_RESERVE1) || \ + ((x) == ALD_PIS_UART1_RESERVE2) || \ + ((x) == ALD_PIS_UART1_RTSOUT) || \ + ((x) == ALD_PIS_UART1_TXOUT) || \ + ((x) == ALD_PIS_UART1_SYN_SEND) || \ + ((x) == ALD_PIS_UART1_SYN_RECV) || \ + ((x) == ALD_PIS_UART2_RESERVE0) || \ + ((x) == ALD_PIS_UART2_RESERVE1) || \ + ((x) == ALD_PIS_UART2_RESERVE2) || \ + ((x) == ALD_PIS_UART2_RTSOUT) || \ + ((x) == ALD_PIS_UART2_TXOUT) || \ + ((x) == ALD_PIS_UART2_SYN_SEND) || \ + ((x) == ALD_PIS_UART2_SYN_RECV) || \ + ((x) == ALD_PIS_UART3_RESERVE0) || \ + ((x) == ALD_PIS_UART3_RESERVE1) || \ + ((x) == ALD_PIS_UART3_RESERVE2) || \ + ((x) == ALD_PIS_UART3_RTSOUT) || \ + ((x) == ALD_PIS_UART3_TXOUT) || \ + ((x) == ALD_PIS_UART3_SYN_SEND) || \ + ((x) == ALD_PIS_UART3_SYN_RECV) || \ + ((x) == ALD_PIS_UART4_RESERVE0) || \ + ((x) == ALD_PIS_UART4_RESERVE1) || \ + ((x) == ALD_PIS_UART4_RESERVE2) || \ + ((x) == ALD_PIS_UART4_RTSOUT) || \ + ((x) == ALD_PIS_UART4_TXOUT) || \ + ((x) == ALD_PIS_UART4_SYN_SEND) || \ + ((x) == ALD_PIS_UART4_SYN_RECV) || \ + ((x) == ALD_PIS_SPI0_RECV) || \ + ((x) == ALD_PIS_SPI0_SEND) || \ + ((x) == ALD_PIS_SPI0_NE) || \ + ((x) == ALD_PIS_SPI1_RECV) || \ + ((x) == ALD_PIS_SPI1_SEND) || \ + ((x) == ALD_PIS_SPI1_NE) || \ + ((x) == ALD_PIS_I2C0_RECV) || \ + ((x) == ALD_PIS_I2C0_SEND) || \ + ((x) == ALD_PIS_I2C1_RECV) || \ + ((x) == ALD_PIS_I2C1_SEND) || \ + ((x) == ALD_PIS_TIMER0_UPDATA) || \ + ((x) == ALD_PIS_TIMER0_TRIG) || \ + ((x) == ALD_PIS_TIMER0_INPUT_1) || \ + ((x) == ALD_PIS_TIMER0_OUTPUT_1) || \ + ((x) == ALD_PIS_TIMER0_INPUT_2) || \ + ((x) == ALD_PIS_TIMER0_OUTPUT_2) || \ + ((x) == ALD_PIS_TIMER0_INPUT_3) || \ + ((x) == ALD_PIS_TIMER0_OUTPUT_3) || \ + ((x) == ALD_PIS_TIMER0_INPUT_4) || \ + ((x) == ALD_PIS_TIMER0_OUTPUT_4) || \ + ((x) == ALD_PIS_TIMER5_UPDATA) || \ + ((x) == ALD_PIS_TIMER5_TRIG) || \ + ((x) == ALD_PIS_TIMER5_INPUT_1) || \ + ((x) == ALD_PIS_TIMER5_OUTPUT_1) || \ + ((x) == ALD_PIS_TIMER5_INPUT_2) || \ + ((x) == ALD_PIS_TIMER5_OUTPUT_2) || \ + ((x) == ALD_PIS_TIMER5_INPUT_3) || \ + ((x) == ALD_PIS_TIMER5_OUTPUT_3) || \ + ((x) == ALD_PIS_TIMER5_INPUT_4) || \ + ((x) == ALD_PIS_TIMER5_OUTPUT_4) || \ + ((x) == ALD_PIS_TIMER6_UPDATA) || \ + ((x) == ALD_PIS_TIMER6_TRIG) || \ + ((x) == ALD_PIS_TIMER6_INPUT_1) || \ + ((x) == ALD_PIS_TIMER6_OUTPUT_1) || \ + ((x) == ALD_PIS_TIMER6_INPUT_2) || \ + ((x) == ALD_PIS_TIMER6_OUTPUT_2) || \ + ((x) == ALD_PIS_TIMER6_INPUT_3) || \ + ((x) == ALD_PIS_TIMER6_OUTPUT_3) || \ + ((x) == ALD_PIS_TIMER6_INPUT_4) || \ + ((x) == ALD_PIS_TIMER6_OUTPUT_4) || \ + ((x) == ALD_PIS_TIMER7_UPDATA) || \ + ((x) == ALD_PIS_TIMER7_TRIG) || \ + ((x) == ALD_PIS_TIMER7_INPUT_1) || \ + ((x) == ALD_PIS_TIMER7_OUTPUT_1) || \ + ((x) == ALD_PIS_TIMER7_INPUT_2) || \ + ((x) == ALD_PIS_TIMER7_OUTPUT_2) || \ + ((x) == ALD_PIS_TIMER7_INPUT_3) || \ + ((x) == ALD_PIS_TIMER7_OUTPUT_3) || \ + ((x) == ALD_PIS_TIMER7_INPUT_4) || \ + ((x) == ALD_PIS_TIMER7_OUTPUT_4) || \ + ((x) == ALD_PIS_TIMER4_UPDATA) || \ + ((x) == ALD_PIS_TIMER4_TRIG) || \ + ((x) == ALD_PIS_DMA_CH0) || \ + ((x) == ALD_PIS_DMA_CH1) || \ + ((x) == ALD_PIS_DMA_CH2) || \ + ((x) == ALD_PIS_DMA_CH3) || \ + ((x) == ALD_PIS_DMA_CH4) || \ + ((x) == ALD_PIS_DMA_CH5) || \ + ((x) == ALD_PIS_DMA_CH6) || \ + ((x) == ALD_PIS_DMA_ALL)) +#define IS_PIS_TRIG(x) (((x) == ALD_PIS_CH4_TIMER0_ITR0) || \ + ((x) == ALD_PIS_CH5_TIMER0_ITR1) || \ + ((x) == ALD_PIS_CH6_TIMER0_ITR2) || \ + ((x) == ALD_PIS_CH7_TIMER0_ITR3) || \ + ((x) == ALD_PIS_CH4_TIMER1_ITR0) || \ + ((x) == ALD_PIS_CH5_TIMER1_ITR1) || \ + ((x) == ALD_PIS_CH6_TIMER1_ITR2) || \ + ((x) == ALD_PIS_CH7_TIMER1_ITR3) || \ + ((x) == ALD_PIS_CH4_TIMER2_ITR0) || \ + ((x) == ALD_PIS_CH5_TIMER2_ITR1) || \ + ((x) == ALD_PIS_CH6_TIMER2_ITR2) || \ + ((x) == ALD_PIS_CH7_TIMER2_ITR3) || \ + ((x) == ALD_PIS_CH4_TIMER3_ITR0) || \ + ((x) == ALD_PIS_CH5_TIMER3_ITR1) || \ + ((x) == ALD_PIS_CH6_TIMER3_ITR2) || \ + ((x) == ALD_PIS_CH7_TIMER3_ITR3) || \ + ((x) == ALD_PIS_CH4_ADC0_NORMAL ) || \ + ((x) == ALD_PIS_CH5_ADC0_INSERT) || \ + ((x) == ALD_PIS_CH7_DMA_REQUEST) || \ + ((x) == ALD_PIS_CH7_UART4_RXD) || \ + ((x) == ALD_PIS_CH6_UART3_RXD) || \ + ((x) == ALD_PIS_CH5_UART2_RXD) || \ + ((x) == ALD_PIS_CH4_UART1_RXD) || \ + ((x) == ALD_PIS_CH3_UART0_RXD) || \ + ((x) == ALD_PIS_CH4_TIMER3_CH4IN) || \ + ((x) == ALD_PIS_CH4_TIMER2_CH4IN) || \ + ((x) == ALD_PIS_CH3_SPI1_CLK) || \ + ((x) == ALD_PIS_CH7_TIMER3_CH3IN) || \ + ((x) == ALD_PIS_CH7_TIMER2_CH3IN) || \ + ((x) == ALD_PIS_CH2_SPI1_RX) || \ + ((x) == ALD_PIS_CH6_TIMER3_CH2IN) || \ + ((x) == ALD_PIS_CH6_TIMER2_CH2IN) || \ + ((x) == ALD_PIS_CH1_SPI0_CLK) || \ + ((x) == ALD_PIS_CH5_TIMER3_CH1IN) || \ + ((x) == ALD_PIS_CH5_TIMER2_CH1IN) || \ + ((x) == ALD_PIS_CH0_SPI0_RX) || \ + ((x) == ALD_PIS_CH4_TIMER1_CH4IN) || \ + ((x) == ALD_PIS_CH4_TIMER0_CH4IN) || \ + ((x) == ALD_PIS_CH3_TIMER1_CH3IN) || \ + ((x) == ALD_PIS_CH3_TIMER0_CH3IN) || \ + ((x) == ALD_PIS_CH2_TIMER1_CH2IN) || \ + ((x) == ALD_PIS_CH2_TIMER0_CH2IN) || \ + ((x) == ALD_PIS_CH1_TIMER1_CH1IN) || \ + ((x) == ALD_PIS_CH1_TIMER0_CH1IN) || \ + ((x) == ALD_PIS_CH0_TIMER0_BRKIN) || \ + ((x) == ALD_PIS_TRIG_RESERVE) || \ + ((x) <= 0x7U)) +#define IS_PIS_CLOCK(x) (((x) == ALD_PIS_CLK_PCLK) || \ + ((x) == ALD_PIS_CLK_HCLK) || \ + ((x) == ALD_PIS_CLK_RESERVE)) +#define IS_PIS_SIGNAL_MODE(x) (((x) == ALD_PIS_OUT_LEVEL) || \ + ((x) == ALD_PIS_OUT_PULSE)) +#define IS_PIS_EDGE(x) (((x) == ALD_PIS_EDGE_NONE) || \ + ((x) == ALD_PIS_EDGE_UP) || \ + ((x) == ALD_PIS_EDGE_DOWN) || \ + ((x) == ALD_PIS_EDGE_UP_DOWN)) +#define IS_PIS_OUTPUT(x) (((x) == ALD_PIS_OUT_LEVEL) || \ + ((x) == ALD_PIS_OUT_PULSE)) +#define IS_PIS_OUPUT_CH(x) (((x) == ALD_PIS_OUT_CH_0) || \ + ((x) == ALD_PIS_OUT_CH_1) || \ + ((x) == ALD_PIS_OUT_CH_2) || \ + ((x) == ALD_PIS_OUT_CH_3) || \ + ((x) == ALD_PIS_OUT_CH_4) || \ + ((x) == ALD_PIS_OUT_CH_5) || \ + ((x) == ALD_PIS_OUT_CH_6) || \ + ((x) == ALD_PIS_OUT_CH_7)) +#define IS_PIS_MODU_TARGET(x) (((x) == ALD_PIS_UART0_TX) || \ + ((x) == ALD_PIS_UART1_TX) || \ + ((x) == ALD_PIS_UART2_TX) || \ + ((x) == ALD_PIS_UART3_TX) || \ + ((x) == ALD_PIS_UART4_TX)) +#define IS_PIS_MODU_LEVEL(x) (((x) == ALD_PIS_LOW_LEVEL) || \ + ((x) == ALD_PIS_HIGH_LEVEL)) +#define IS_PIS_MODU_SRC(x) (((x) == ALD_PIS_SRC_NONE) || \ + ((x) == ALD_PIS_SRC_TIMER0) || \ + ((x) == ALD_PIS_SRC_TIMER5) || \ + ((x) == ALD_PIS_SRC_TIMER6) || \ + ((x) == ALD_PIS_SRC_TIMER7) || \ + ((x) == ALD_PIS_SRC_BUZ)) +#define IS_PIS_MODU_CHANNEL(x) (((x) == ALD_PIS_TIMER_CH1) || \ + ((x) == ALD_PIS_TIMER_CH2) || \ + ((x) == ALD_PIS_TIMER_CH3) || \ + ((x) == ALD_PIS_TIMER_CH4)) +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @addtogroup PIS_Public_Functions + * @{ + */ + +/** @addtogroup PIS_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_pis_create(ald_pis_handle_t *hperh); +ald_status_t ald_pis_destroy(ald_pis_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group2 + * @{ + */ +ald_status_t ald_pis_output_start(ald_pis_handle_t *hperh, ald_pis_out_ch_t ch); +ald_status_t ald_pis_output_stop(ald_pis_handle_t *hperh, ald_pis_out_ch_t ch); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group3 + * @{ + */ +ald_pis_state_t ald_pis_get_state(ald_pis_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group4 + * @{ + */ +ald_status_t ald_pis_modu_config(ald_pis_handle_t *hperh, ald_pis_modulate_config_t *config); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_PIS_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_pmu.c b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_pmu.c new file mode 100644 index 0000000000..7f8e7e0cfa --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_pmu.c @@ -0,0 +1,245 @@ +/** + ********************************************************************************* + * + * @file ald_pmu.c + * @brief PMU module driver. + * + * @version V1.0 + * @date 08 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 08 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_pmu.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup PMU PMU + * @brief PMU module driver + * @{ + */ + +/** @defgroup PMU_Private_Functions PMU Private Functions + * @{ + */ + +/** + * @brief PMU module interrupt handler + * @retval None + */ +void ald_lvd_irq_handler(void) +{ + ALD_SYSCFG_UNLOCK(); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + ALD_SYSCFG_LOCK(); + + return; +} +/** + * @}PMU_Private_Functions + */ + +/** @defgroup PMU_Public_Functions PMU Public Functions + * @{ + */ + +/** @addtogroup PMU_Public_Functions_Group1 Low Power Mode + * @brief Low power mode select functions + * + * @verbatim + ============================================================================== + ##### Low power mode select functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Get wakeup status. + (+) Clear wakeup status. + + @endverbatim + * @{ + */ + +/** + * @brief Get wakup status. + * @param sr: Status bit. + * @retval Status. + */ +flag_status_t ald_pmu_get_status(ald_pmu_status_t sr) +{ + assert_param(IS_PMU_STATUS(sr)); + + if (READ_BIT(PMU->SR, sr)) + return SET; + + return RESET; +} + +/** + * @brief Clear wakup status. + * @param sr: Status bit. + * @retval None + */ +void ald_pmu_clear_status(ald_pmu_status_t sr) +{ + assert_param(IS_PMU_STATUS(sr)); + ALD_SYSCFG_UNLOCK(); + + if (sr == ALD_PMU_SR_WUF) + SET_BIT(PMU->CR, PMU_CR_CWUF_MSK); + else + ;/* do nothing */ + + ALD_SYSCFG_LOCK(); + return; +} + +/** + * @brief Enter stop mode + * @retval None + */ +void ald_pmu_stop_enter(void) +{ + uint32_t clint_irq_en = 0U; + clint_irq_en = csi_vic_get_enabled_irq(CLINT_IRQn); + csi_vic_disable_sirq(CLINT_IRQn); + + ALD_SYSCFG_UNLOCK(); + MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, ALD_PMU_LP_STOP << PMU_CR_LPM_POSS); + CLEAR_BIT(PMU->CR, PMU_CR_VROSCEN_MSK); + MODIFY_REG(PMU->CR, PMU_CR_LPSTOP_MSK | PMU_CR_BGSTOP_MSK | \ + PMU_CR_STPRTNEN_MSK | PMU_CR_FSTOP_MSK, \ + 1 << PMU_CR_LPSTOP_POS | 1 << PMU_CR_BGSTOP_POS \ + | 1 << PMU_CR_STPRTNEN_POS | 1 << PMU_CR_FSTOP_POS); + /* WKEVNSEL is only for testing, and user should set it to be 0x10. */ + MODIFY_REG(PMU->CR, PMU_CR_WKEVNSEL_MSK, (0x10 << PMU_CR_WKEVNSEL_POSS)); + ALD_SYSCFG_LOCK(); + + csi_cpu_sleep_wfi(MEXSTATUS_SLEEP_DEEP); + + __WFI(); + + if(clint_irq_en) + csi_vic_enable_sirq(CLINT_IRQn); +} + +/** + * @brief Enter sleep mode + * @retval None + */ +void ald_pmu_sleep_enter(void) +{ + uint32_t clint_irq_en = 0U; + clint_irq_en = csi_vic_get_enabled_irq(CLINT_IRQn); + csi_vic_disable_sirq(CLINT_IRQn); + + ALD_SYSCFG_UNLOCK(); + MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, ALD_PMU_LP_STOP << PMU_CR_LPM_POSS); + /* WKEVNSEL is only for testing, and user should set it to be 0x10. */ + MODIFY_REG(PMU->CR, PMU_CR_WKEVNSEL_MSK, (0x10 << PMU_CR_WKEVNSEL_POSS)); + ALD_SYSCFG_LOCK(); + + csi_cpu_sleep_wfi(MEXSTATUS_SLEEP_LIGHT); + + __WFI(); + + if(clint_irq_en) + csi_vic_enable_sirq(CLINT_IRQn); +} + +/** + * @}PMU_Public_Functions_Group1 + */ + +/** @addtogroup PMU_Public_Functions_Group2 LVD Configure + * @brief LVD configure functions + * + * @verbatim + ============================================================================== + ##### LVD configure functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure lvd parameters. + + @endverbatim + * @{ + */ + +/** + * @brief Configure lvd using specified parameters. + * @param sel: LVD threshold voltage. + * @param mode: LVD trigger mode. + * @param state: New state, ENABLE/DISABLE; + * @retval None + */ +void ald_pmu_lvd_config(ald_pmu_lvd_voltage_sel_t sel, ald_pmu_lvd_trigger_mode_t mode, type_func_t state) +{ + assert_param(IS_FUNC_STATE(state)); + ALD_SYSCFG_UNLOCK(); + + if (state) + { + assert_param(IS_PMU_LVD_VOL_SEL(sel)); + assert_param(IS_PMU_LVD_TRIGGER_MODE(mode)); + + MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS); + MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDIFS_MSK, mode << PMU_LVDCR_LVDIFS_POSS); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); + } + else + { + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); + CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); + } + + ALD_SYSCFG_LOCK(); + return; +} +/** + * @}PMU_Public_Functions_Group2 + */ + +/** + * @}PMU_Public_Functions + */ + +/** + * @}PMU + */ + +/** + * @}ES32VF2264_ALD + */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_pmu.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_pmu.h new file mode 100644 index 0000000000..2cbba07006 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_pmu.h @@ -0,0 +1,245 @@ +/** + ********************************************************************************* + * + * @file ald_pmu.h + * @brief Header file of PMU module driver. + * + * @version V1.0 + * @date 08 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 08 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_PMU_H__ +#define __ALD_PMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_utils.h" +#include "ald_syscfg.h" + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Constants -------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup PMU + * @{ + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** @defgroup PMU_Public_Macros PMU Public Macros + * @{ + */ +#define ALD_PMU_LPSTOP_ENABLE() \ + do { \ + ALD_SYSCFG_UNLOCK(); \ + SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \ + ALD_SYSCFG_LOCK(); \ + } while (0) +#define ALD_PMU_LPSTOP_DISABLE() \ + do { \ + ALD_SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \ + ALD_SYSCFG_LOCK(); \ + } while (0) +#define ALD_PMU_FLASH_STOP_DISABLE() \ + do { \ + ALD_SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->CR, PMU_CR_FSTOP_MSK); \ + ALD_SYSCFG_LOCK(); \ + } while (0) +#define ALD_PMU_FLASH_STOP_ENABLE() \ + do { \ + ALD_SYSCFG_UNLOCK(); \ + SET_BIT(PMU->CR, PMU_CR_FSTOP_MSK); \ + ALD_SYSCFG_LOCK(); \ + } while (0) +#define ALD_PMU_BGSTOP_ENABLE() \ + do { \ + ALD_SYSCFG_UNLOCK(); \ + SET_BIT(PMU->CR, PMU_CR_BGSTOP_MSK); \ + ALD_SYSCFG_LOCK(); \ + } while (0) +#define ALD_PMU_BGSTOP_DISABLE() \ + do { \ + ALD_SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->CR, PMU_CR_BGSTOP_MSK); \ + ALD_SYSCFG_LOCK(); \ + } while (0) +#define ALD_PMU_VROSCEN_ENABLE() \ + do { \ + ALD_SYSCFG_UNLOCK(); \ + SET_BIT(PMU->CR, PMU_CR_VROSCEN_MSK); \ + ALD_SYSCFG_LOCK(); \ + } while (0) +#define ALD_PMU_VROSCEN_DISABLE() \ + do { \ + ALD_SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->CR, PMU_CR_VROSCEN_MSK); \ + ALD_SYSCFG_LOCK(); \ + } while (0) +#define ALD_PMU_STPRTNEN_ENABLE() \ + do { \ + ALD_SYSCFG_UNLOCK(); \ + SET_BIT(PMU->CR, PMU_CR_STPRTNEN_MSK); \ + ALD_SYSCFG_LOCK(); \ + } while (0) +#define ALD_PMU_STPRTNEN_DISABLE() \ + do { \ + ALD_SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->CR, PMU_CR_STPRTNEN_MSK); \ + ALD_SYSCFG_LOCK(); \ + } while (0) + +#define ALD_PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS)) +/** + * @}PMU_Public_Macros + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup PMU_Public_Types PMU Public Types + * @{ + */ +/** + * @brief Low power mode + */ +typedef enum +{ + ALD_PMU_LP_STOP = 0x0U, /**< Stop */ +} ald_pmu_lp_mode_t; + +typedef enum +{ + ALD_PMU_SR_WUF = (1U << 0), /**< WakeUp status */ +} ald_pmu_status_t; + +/** + * @brief LVD voltage select + */ +typedef enum +{ + ALD_PMU_LVD_VOL_SEL_2_2 = 0x0U, /**< 2.2V */ + ALD_PMU_LVD_VOL_SEL_2_4 = 0x1U, /**< 2.4V */ + ALD_PMU_LVD_VOL_SEL_2_6 = 0x2U, /**< 2.6V */ + ALD_PMU_LVD_VOL_SEL_2_8 = 0x3U, /**< 2.8V */ + ALD_PMU_LVD_VOL_SEL_3_0 = 0x4U, /**< 3.0V */ + ALD_PMU_LVD_VOL_SEL_3_6 = 0x5U, /**< 3.6V */ + ALD_PMU_LVD_VOL_SEL_4_0 = 0x6U, /**< 4.0V */ + ALD_PMU_LVD_VOL_SEL_4_6 = 0x7U, /**< 4.6V */ +} ald_pmu_lvd_voltage_sel_t; + +/** + * @brief LVD trigger mode + */ +typedef enum +{ + ALD_PMU_LVD_TRIGGER_RISING_EDGE = 0x0U, /**< Rising edge */ + ALD_PMU_LVD_TRIGGER_FALLING_EDGE = 0x1U, /**< Falling edge */ + ALD_PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2U, /**< High level */ + ALD_PMU_LVD_TRIGGER_LOW_LEVEL = 0x3U, /**< Low level */ + ALD_PMU_LVD_TRIGGER_RISING_FALLING = 0x4U, /**< Rising and falling edge */ +} ald_pmu_lvd_trigger_mode_t; + +/** + * @}PMU_Public_Types + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** + * @defgroup PMU_Private_Macros PMU Private Macros + * @{ + */ +#define IS_PMU_LP_MODE(x) (((x) == ALD_PMU_LP_STOP)) +#define IS_PMU_STATUS(x) (((x) == ALD_PMU_SR_WUF)) +#define IS_PMU_LVD_VOL_SEL(x) (((x) == ALD_PMU_LVD_VOL_SEL_2_2) || \ + ((x) == ALD_PMU_LVD_VOL_SEL_2_4) || \ + ((x) == ALD_PMU_LVD_VOL_SEL_2_6) || \ + ((x) == ALD_PMU_LVD_VOL_SEL_2_8) || \ + ((x) == ALD_PMU_LVD_VOL_SEL_3_0) || \ + ((x) == ALD_PMU_LVD_VOL_SEL_3_6) || \ + ((x) == ALD_PMU_LVD_VOL_SEL_4_0) || \ + ((x) == ALD_PMU_LVD_VOL_SEL_4_6)) +#define IS_PMU_LVD_TRIGGER_MODE(x) (((x) == ALD_PMU_LVD_TRIGGER_RISING_EDGE) || \ + ((x) == ALD_PMU_LVD_TRIGGER_FALLING_EDGE) || \ + ((x) == ALD_PMU_LVD_TRIGGER_HIGH_LEVEL) || \ + ((x) == ALD_PMU_LVD_TRIGGER_LOW_LEVEL) || \ + ((x) == ALD_PMU_LVD_TRIGGER_RISING_FALLING)) +/** + * @}PMU_Private_Macros + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @addtogroup PMU_Public_Functions + * @{ + */ + +/** @addtogroup PMU_Public_Functions_Group1 + * @{ + */ +flag_status_t ald_pmu_get_status(ald_pmu_status_t sr); +void ald_pmu_clear_status(ald_pmu_status_t sr); +void ald_pmu_sleep_enter(void); +void ald_pmu_stop_enter(void); +/** + * @}PMU_Public_Functions_Group1 + */ + +/** @addtogroup PMU_Public_Functions_Group2 + * @{ + */ +/* LVD configure */ +void ald_pmu_lvd_config(ald_pmu_lvd_voltage_sel_t sel, ald_pmu_lvd_trigger_mode_t mode, type_func_t state); +void ald_lvd_irq_handler(void); +/** + * @}PMU_Public_Functions_Group2 + */ + +/** + * @}PMU_Public_Functions + */ + +/** + * @}PMU + */ + +/** + * @}ES32VF2264_ALD + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_PMU_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_rmu.c b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_rmu.c new file mode 100644 index 0000000000..2acfaa58a8 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_rmu.c @@ -0,0 +1,194 @@ +/** + ********************************************************************************* + * + * @file ald_rmu.c + * @brief RMU module driver. + * + * @version V1.0 + * @date 09 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 09 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_syscfg.h" +#include "ald_rmu.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup RMU RMU + * @brief RMU module driver + * @{ + */ + +/** @defgroup RMU_Public_Functions RMU Public Functions + * @{ + */ + +/** + * @brief Configure BOR parameters. + * @param flt: filter time. + * @retval None + */ +void ald_rmu_bor_config(ald_rmu_bor_filter_t flt) +{ + assert_param(IS_RMU_BORFLT(flt)); + + ALD_SYSCFG_UNLOCK(); + MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, flt << RMU_CR_BORFLT_POSS); + ALD_SYSCFG_LOCK(); + + return; +} + +/** + * @brief Get specified reset status + * @param state: Speicifies the type of the reset, + * @retval The status. + */ +uint32_t ald_rmu_get_reset_status(ald_rmu_state_t state) +{ + assert_param(IS_RMU_STATE(state)); + + if (state == ALD_RMU_RST_ALL) + return RMU->RSTSR; + + if (READ_BIT(RMU->RSTSR, state)) + return SET; + + return RESET; +} + +/** + * @brief Clear the specified reset status + * @param state: Specifies the type of the reset, + * @retval None + */ +void ald_rmu_clear_reset_status(ald_rmu_state_t state) +{ + assert_param(IS_RMU_STATE_CLEAR(state)); + + ALD_SYSCFG_UNLOCK(); + WRITE_REG(RMU->CRSTSR, state); + ALD_SYSCFG_LOCK(); + + return; +} + +/** + * @brief Reset peripheral device + * @param perh: The peripheral device, + * @retval None + */ +void ald_rmu_reset_periperal(ald_rmu_peripheral_t perh) +{ + uint32_t idx, pos; + + assert_param(IS_RMU_PERH(perh)); + + idx = ((uint32_t)perh >> 27) & 0x7; + pos = perh & ~(0x7 << 27); + ALD_SYSCFG_UNLOCK(); + + switch (idx) + { + case 0: + WRITE_REG(RMU->AHB1RSTR, pos); + break; + + case 1: + WRITE_REG(RMU->AHB2RSTR, pos); + break; + + case 2: + WRITE_REG(RMU->APBRSTR, pos); + break; + + default: + break; + } + + ALD_SYSCFG_LOCK(); + return; +} + +/** + * @brief System reset request + * @param None + * @retval None + */ +void ald_rmu_reset_system(void) +{ + csi_cpu_reset(MEXSTATUS_RESET_CORE); + + return; +} + +/** + * @brief Chip reset request + * @param None + * @retval None + */ +void md_rmu_reset_chip(void) +{ + ALD_SYSCFG_UNLOCK(); + SET_BIT(RMU->AHB2RSTR, RMU_AHB2RSTR_CHIPRST_MSK); + ALD_SYSCFG_LOCK(); + + return; +} + +/** + * @brief CPU reset request + * @param None + * @retval None + */ +void md_rmu_reset_cpu(void) +{ + ALD_SYSCFG_UNLOCK(); + SET_BIT(RMU->AHB2RSTR, RMU_AHB2RSTR_CPURST_MSK); + ALD_SYSCFG_LOCK(); + + return; +} + +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_rmu.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_rmu.h new file mode 100644 index 0000000000..47cd12a6ab --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_rmu.h @@ -0,0 +1,228 @@ +/** + ********************************************************************************* + * + * @file ald_rmu.h + * @brief Header file of RMU module driver. + * + * @version V1.0 + * @date 09 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 09 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_RMU_H__ +#define __ALD_RMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_utils.h" + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Constants -------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup RMU + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup RMU_Public_Types RMU Public Types + * @{ + */ +/** + * @brief RMU BOR fliter + */ +typedef enum +{ + ALD_RMU_BORFLT_1 = 0x1U, /**< 1 cycle */ + ALD_RMU_BORFLT_2 = 0x2U, /**< 2 cycles */ + ALD_RMU_BORFLT_3 = 0x3U, /**< 3 cycles */ + ALD_RMU_BORFLT_4 = 0x4U, /**< 4 cycles */ + ALD_RMU_BORFLT_5 = 0x5U, /**< 5 cycles */ + ALD_RMU_BORFLT_6 = 0x6U, /**< 6 cycles */ + ALD_RMU_BORFLT_7 = 0x7U, /**< 7 cycles */ +} ald_rmu_bor_filter_t; + +/** + * @brief RMU reset status + */ +typedef enum +{ + ALD_RMU_RST_POR = (1U << 0), /**< POR */ + ALD_RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */ + ALD_RMU_RST_BOR = (1U << 2), /**< BOR */ + ALD_RMU_RST_NMRST = (1U << 3), /**< NMRST */ + ALD_RMU_RST_IWDT = (1U << 4), /**< IWDT */ + ALD_RMU_RST_WWDT = (1U << 5), /**< WWDT */ + ALD_RMU_RST_LOCKUP = (1U << 6), /**< LOCKUP */ + ALD_RMU_RST_CHIP = (1U << 7), /**< CHIP */ + ALD_RMU_RST_MCU = (1U << 8), /**< MCU */ + ALD_RMU_RST_CPU = (1U << 9), /**< CPU */ + ALD_RMU_RST_CFG = (1U << 10), /**< CFG */ + ALD_RMU_RST_CFGERR = (1U << 16), /**< CFG Error */ + ALD_RMU_RST_ALL = (0xFFFFFU), /**< ALL */ +} ald_rmu_state_t; + +/** + * @brief RMU periperal select bit + */ +typedef enum +{ + ALD_RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */ + ALD_RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */ + ALD_RMU_PERH_DMA = (1U << 2), /**< AHB1: DMA */ + ALD_RMU_PERH_PIS = (1U << 5), /**< AHB1: PIS */ + ALD_RMU_PERH_USB = (1U << 6), /**< AHB1: USB */ + ALD_RMU_PERH_CSU = (1U << 7), /**< AHB1: CSU */ + + ALD_RMU_PERH_CHIP = (1U << 0) | (1U << 27), /**< AHB2: CHIP */ + ALD_RMU_PERH_CPU = (1U << 1) | (1U << 27), /**< AHB2: CPU */ + + ALD_RMU_PERH_AD16C4T = (1U << 0) | (1U << 28), /**< APB: AD16C4T */ + ALD_RMU_PERH_BS16T0 = (1U << 1) | (1U << 28), /**< APB: BS16T0 */ + ALD_RMU_PERH_GP16C4T0 = (1U << 2) | (1U << 28), /**< APB: GP16C4T0 */ + ALD_RMU_PERH_GP16C4T1 = (1U << 3) | (1U << 28), /**< APB: GP16C4T1 */ + ALD_RMU_PERH_GP16C4T2 = (1U << 4) | (1U << 28), /**< APB: GP16C4T2 */ + ALD_RMU_PERH_EUART0 = (1U << 8) | (1U << 28), /**< APB: EUART0 */ + ALD_RMU_PERH_EUART1 = (1U << 9) | (1U << 28), /**< APB: EUART1 */ + ALD_RMU_PERH_CUART0 = (1U << 12) | (1U << 28), /**< APB: CUART0 */ + ALD_RMU_PERH_CUART1 = (1U << 13) | (1U << 28), /**< APB: CUART1 */ + ALD_RMU_PERH_CUART2 = (1U << 14) | (1U << 28), /**< APB: CUART2 */ + ALD_RMU_PERH_SPI0 = (1U << 16) | (1U << 28), /**< APB: SPI0 */ + ALD_RMU_PERH_SPI1 = (1U << 17) | (1U << 28), /**< APB: SPI1 */ + ALD_RMU_PERH_I2C0 = (1U << 20) | (1U << 28), /**< APB: I2C0 */ + ALD_RMU_PERH_I2C1 = (1U << 21) | (1U << 28), /**< APB: I2C1 */ + ALD_RMU_PERH_WWDT = (1U << 22) | (1U << 28), /**< APB: WWDT */ + ALD_RMU_PERH_IWDT = (1U << 23) | (1U << 28), /**< APB: IWDT */ + ALD_RMU_PERH_DBGCON = (1U << 24) | (1U << 28), /**< APB: DBGCON */ + ALD_RMU_PERH_ADC = (1U << 25) | (1U << 28), /**< APB: ADC */ +} ald_rmu_peripheral_t; +/** + * @} + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** + * @defgroup RMU_Private_Macros RMU Private Macros + * @{ + */ +#define IS_RMU_BORFLT(x) (((x) == ALD_RMU_BORFLT_1) || \ + ((x) == ALD_RMU_BORFLT_2) || \ + ((x) == ALD_RMU_BORFLT_3) || \ + ((x) == ALD_RMU_BORFLT_4) || \ + ((x) == ALD_RMU_BORFLT_5) || \ + ((x) == ALD_RMU_BORFLT_6) || \ + ((x) == ALD_RMU_BORFLT_7)) +#define IS_RMU_STATE(x) (((x) == ALD_RMU_RST_POR) || \ + ((x) == ALD_RMU_RST_WAKEUP) || \ + ((x) == ALD_RMU_RST_BOR) || \ + ((x) == ALD_RMU_RST_NMRST) || \ + ((x) == ALD_RMU_RST_IWDT) || \ + ((x) == ALD_RMU_RST_WWDT) || \ + ((x) == ALD_RMU_RST_LOCKUP) || \ + ((x) == ALD_RMU_RST_CHIP) || \ + ((x) == ALD_RMU_RST_MCU) || \ + ((x) == ALD_RMU_RST_CPU) || \ + ((x) == ALD_RMU_RST_CFG) || \ + ((x) == ALD_RMU_RST_CFGERR) || \ + ((x) == ALD_RMU_RST_ALL)) +#define IS_RMU_STATE_CLEAR(x) (((x) == ALD_RMU_RST_POR) || \ + ((x) == ALD_RMU_RST_WAKEUP) || \ + ((x) == ALD_RMU_RST_BOR) || \ + ((x) == ALD_RMU_RST_NMRST) || \ + ((x) == ALD_RMU_RST_IWDT) || \ + ((x) == ALD_RMU_RST_WWDT) || \ + ((x) == ALD_RMU_RST_LOCKUP) || \ + ((x) == ALD_RMU_RST_CHIP) || \ + ((x) == ALD_RMU_RST_MCU) || \ + ((x) == ALD_RMU_RST_CPU) || \ + ((x) == ALD_RMU_RST_CFG) || \ + ((x) == ALD_RMU_RST_ALL)) +#define IS_RMU_PERH(x) (((x) == ALD_RMU_PERH_GPIO) || \ + ((x) == ALD_RMU_PERH_CRC) || \ + ((x) == ALD_RMU_PERH_DMA) || \ + ((x) == ALD_RMU_PERH_PIS) || \ + ((x) == ALD_RMU_PERH_USB) || \ + ((x) == ALD_RMU_PERH_CSU) || \ + ((x) == ALD_RMU_PERH_CHIP) || \ + ((x) == ALD_RMU_PERH_CPU) || \ + ((x) == ALD_RMU_PERH_AD16C4T) || \ + ((x) == ALD_RMU_PERH_BS16T0) || \ + ((x) == ALD_RMU_PERH_GP16C4T0) || \ + ((x) == ALD_RMU_PERH_GP16C4T1) || \ + ((x) == ALD_RMU_PERH_GP16C4T2) || \ + ((x) == ALD_RMU_PERH_EUART0) || \ + ((x) == ALD_RMU_PERH_EUART1) || \ + ((x) == ALD_RMU_PERH_CUART0) || \ + ((x) == ALD_RMU_PERH_CUART1) || \ + ((x) == ALD_RMU_PERH_CUART2) || \ + ((x) == ALD_RMU_PERH_SPI0) || \ + ((x) == ALD_RMU_PERH_SPI1) || \ + ((x) == ALD_RMU_PERH_I2C0) || \ + ((x) == ALD_RMU_PERH_I2C1) || \ + ((x) == ALD_RMU_PERH_WWDT) || \ + ((x) == ALD_RMU_PERH_IWDT) || \ + ((x) == ALD_RMU_PERH_DBGCON) || \ + ((x) == ALD_RMU_PERH_ADC)) +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @addtogroup RMU_Public_Functions + * @{ + */ +void ald_rmu_bor_config(ald_rmu_bor_filter_t flt); +uint32_t ald_rmu_get_reset_status(ald_rmu_state_t state); +void ald_rmu_clear_reset_status(ald_rmu_state_t state); +void ald_rmu_reset_periperal(ald_rmu_peripheral_t perh); +void ald_rmu_reset_system(void); +void ald_rmu_reset_chip(void); +void ald_rmu_reset_cpu(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_RMU_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_spi.c b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_spi.c new file mode 100644 index 0000000000..50c19cc3dd --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_spi.c @@ -0,0 +1,2242 @@ +/** + ********************************************************************************* + * + * @file ald_spi.c + * @brief SPI module driver. + * This file provides firmware functions to manage the following + * functionalities of SPI peripheral: + * + Initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + * @version V1.0 + * @date 23 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Feb. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI driver can be used as follows: + + (#) Declare a spi_handle_t structure, for example: + spi_handle_t hperh; + + (#) Initialize the SPI low level resources: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as push-pull + (##) NVIC configuration if you need to use interrupt process + by implementing the ald_mcu_irq_config() API. + Invoked ald_spi_irq_handler() function in SPI-IRQ function + (##) DMA Configuration if you need to use DMA process + (+++) Define ALD_DMA in ald_conf.h + (+++) Enable the DMAx clock + + (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI module by invoking the ald_spi_init() API. + + [..] + Circular mode restriction: + (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + (##) Master 2Lines RxOnly + (##) Master 1Line Rx + (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + the ald_spi_dma_pause()/ ald_spi_dma_stop(). + + * @endverbatim + */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_spi.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/* Private function prototypes ----------------------------------------------- */ + +/** @defgroup SPI SPI + * @brief SPI module driver + * @{ + */ +/** @addtogroup SPI_Private_Functions SPI Private Functions + * @{ + */ + +static void __spi_send_by_it(ald_spi_handle_t *hperh); +static void __spi_recv_by_it(ald_spi_handle_t *hperh); +static void __spi_send_recv_by_it(ald_spi_handle_t *hperh, ald_spi_sr_status_t status); + +static ald_status_t spi_wait_flag_irq(ald_spi_handle_t *hperh, ald_spi_flag_t flag, flag_status_t status, uint32_t timeout); +static void spi_dma_send_cplt(void *arg); +static void spi_dma_recv_cplt(void *arg); +static void spi_dma_send_recv_cplt(void *arg); +/** + * @} + */ + +/* Private Function ---------------------------------------------------------- */ + +/** @defgroup SPI_Public_Functions SPI Public Functions + * @{ + */ + +/** @defgroup SPI_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * + * @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + reset the SPIx peripheral: + + (+) User must configure all related peripherals resources + (CLOCK, GPIO, DMA, NVIC). + + (+) Call the function ald_spi_init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + + (+) Call the function ald_spi_reset() to reset the selected SPIx periperal. + + @endverbatim + * @{ + */ + +/** + * @brief Reset the SPI peripheral. + * @param hperh: Pointer to a spi_handle_t structure that contains + * the configuration information for the specified SPI module. + * @retval None + */ +void ald_spi_reset(ald_spi_handle_t *hperh) +{ + ALD_SPI_DISABLE(hperh); + hperh->perh->CON1 = 0x0; + hperh->perh->CON2 = 0x0; + hperh->perh->CRCPOLY = 0x00000007; + + ALD_SPI_RESET_HANDLE_STATE(hperh); + __UNLOCK(hperh); + + return; +} + +/** + * @brief Initializes the SPI mode according to the specified parameters in + * the SPI_init_t and create the associated handle. + * @param hperh: Pointer to a spi_handle_t structure that contains + * the configuration information for the specified SPI module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_init(ald_spi_handle_t *hperh) +{ + uint32_t tmp = 0U; + + if (hperh == NULL) + return ALD_ERROR; + + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_MODE(hperh->init.mode)); + assert_param(IS_SPI_DIRECTION(hperh->init.dir)); + assert_param(IS_SPI_BAUD(hperh->init.baud)); + assert_param(IS_SPI_FIRBIT(hperh->init.first_bit)); + assert_param(IS_FUNC_STATE(hperh->init.ss_en)); + assert_param(IS_FUNC_STATE(hperh->init.crc_calc)); + assert_param(IS_SPI_DATASIZE(hperh->init.data_size)); + assert_param(IS_SPI_CPHA(hperh->init.phase)); + assert_param(IS_SPI_CPOL(hperh->init.polarity)); + assert_param(IS_SPI_FRAME(hperh->init.frame)); + + ald_spi_reset(hperh); + tmp = hperh->perh->CON1; + + if (hperh->init.mode == ALD_SPI_MODE_MASTER) + tmp |= 1 << SPI_CON1_SSOUT_POS; + + tmp |= ((hperh->init.phase << SPI_CON1_CPHA_POS) | (hperh->init.polarity << SPI_CON1_CPOL_POS) | + (hperh->init.baud << SPI_CON1_BAUD_POSS) | (hperh->init.data_size << SPI_CON1_FLEN_POS) | + (hperh->init.mode << SPI_CON1_MSTREN_POS) | (hperh->init.ss_en << SPI_CON1_SSEN_POS) | + (hperh->init.first_bit << SPI_CON1_LSBFST_POS)); + + hperh->perh->CON1 = tmp; + + MODIFY_REG(hperh->perh->CON2, SPI_CON2_FRF_MSK, hperh->init.frame << SPI_CON2_FRF_POS); + + if (hperh->init.dir == ALD_SPI_DIRECTION_2LINES) + { + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK); + } + else if (hperh->init.dir == ALD_SPI_DIRECTION_2LINES_RXONLY) + { + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + SET_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK); + } + else if (hperh->init.dir == ALD_SPI_DIRECTION_1LINE_RX) + { + SET_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDOEN_MSK); + } + else + { + SET_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + SET_BIT(hperh->perh->CON1, SPI_CON1_BIDOEN_MSK); + } + + /* configure CRC */ + hperh->perh->CON1 |= (hperh->init.crc_calc << SPI_CON1_CRCEN_POS); + hperh->perh->CRCPOLY = hperh->init.crc_poly; + + hperh->err_code = ALD_SPI_ERROR_NONE; + hperh->state = ALD_SPI_STATE_READY; + + ALD_SPI_ENABLE(hperh); + return ALD_OK; +} + +/** + * @brief Config the fifo threshold + * @param hperh: Pointer to a spi_handle_t structure that contains + * the configuration information for the specified SPI module. + * @param threshold: The threshold value of fifo. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t spi_fifo_threshold_config(ald_spi_handle_t *hperh, uint8_t threshold) +{ + assert_param(IS_SPI(hperh->perh)); + + MODIFY_REG(hperh->perh->CON2, SPI_CON2_RXFTH_MSK, threshold << SPI_CON2_RXFTH_POSS); + MODIFY_REG(hperh->perh->CON2, SPI_CON2_TXFTH_MSK, threshold << SPI_CON2_TXFTH_POSS); + + return ALD_OK; +} +/** + * @} + */ + +/** @defgroup SPI_Public_Functions_Group2 IO fast functions + * @brief SPI Transmit and Receive functions + * + * @verbatim + ============================================================================== + ##### IO fast functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the SPI + data transfers fast. + + * @endverbatim + * @{ + */ + +/** + * @brief Transmit one byte fast in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @param data: Data to be sent + * @retval status: + * - 0 Success + * - -1 Failed + */ +int32_t ald_spi_send_byte_fast(ald_spi_handle_t *hperh, uint8_t data) +{ + uint16_t cnt = 5000U, temp; + + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = data; + + while (((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt)); + + cnt = 5000; + + while (((hperh->perh->STAT & SPI_STAT_RXNE_MSK) != SPI_STAT_RXNE_MSK) && (--cnt)); + + temp = hperh->perh->DATA; + UNUSED(temp); + + return cnt == 0 ? -1 : 0; +} + +/** + * @brief Transmit one byte fast in blocking mode(1line). + * @param hperh: Pointer to a spi_handle_t structure. + * @param data: Data to be sent + * @retval status: + * - 0 Success + * - -1 Failed + */ +int32_t ald_spi_send_byte_fast_1line(ald_spi_handle_t *hperh, uint8_t data) +{ + uint16_t cnt = 5000U; + + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = data; + + while (((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt)); + + return cnt == 0 ? -1 : 0; +} + +/** + * @brief Receive one byte fast in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @param status: Status, success[0]/failed[-1] + * @retval Data. + */ +uint8_t ald_spi_recv_byte_fast(ald_spi_handle_t *hperh, int *status) +{ + uint16_t cnt = 5000U; + + if (hperh->init.mode == ALD_SPI_MODE_MASTER) + { + hperh->perh->DATA = 0xFF; + + while (((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt)); + } + + cnt = 5000; + + while (((hperh->perh->STAT & SPI_STAT_RXNE_MSK) != SPI_STAT_RXNE_MSK) && (--cnt)); + + *status = cnt == 0 ? - 1 : 0; + + return (uint8_t)hperh->perh->DATA; +} + +/** + * @brief Transmit some bytes fast in blocking mode. + * @note Bit width is 8-bits. Supports mode: Master/Slave. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be sent. + * @param size: Length of data. + * @param timeout: Timeout between two bytes. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_send_bytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t tick; + uint16_t i, n_fifo, tmp = 0U; + + while (size--) + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = *buf++; + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) + { + if (((ald_get_tick()) - tick) > timeout) + return ALD_TIMEOUT; + } + } + + if (hperh->perh == SPI0) + n_fifo = 16; + else if (hperh->perh == SPI1) + n_fifo = 4; + else + return ALD_ERROR; + + for (i = 0; i < n_fifo; ++i) + { + if ((hperh->perh->STAT & SPI_STAT_RXNE_MSK) != SPI_STAT_RXNE_MSK) + tmp = hperh->perh->DATA; + else + break; + } + + UNUSED(tmp); + return ALD_OK; +} + +/** + * @brief Receive some bytes fast in blocking mode. + * @note Bit width is 8-bits. Supports mode: Master. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be received. + * @param size: Length of data. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_master_recv_bytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + uint16_t cnt = 8000U; + + while (size--) + { + hperh->perh->DATA = 0xFF; + cnt = 8000; + + while (((hperh->perh->STAT & SPI_STAT_RXNE_MSK) != SPI_STAT_RXNE_MSK) && (--cnt)); + + if (cnt) + *buf++ = (uint8_t)hperh->perh->DATA; + else + return ALD_TIMEOUT; + } + + return ALD_OK; +} + +/** + * @brief Receive some bytes fast in blocking mode. + * @note Bit width is 8-bits. Supports mode: Slave. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be received. + * @param size: Length of data. + * @param timeout: Timeout between two bytes. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_slave_recv_bytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t tick; + + while (size--) + { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STAT_RXNE_MSK) != SPI_STAT_RXNE_MSK) + { + if (((ald_get_tick()) - tick) > timeout) + return ALD_TIMEOUT; + } + + *buf++ = (uint8_t)hperh->perh->DATA; + } + + return ALD_OK; +} + +/** + * @brief Transmit some double-bytes fast in blocking mode. + * @note Bit width is 16-bits. Supports mode: Master/Slave. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be sent. + * @param size: Length of data. Unit is double-bytes. + * @param timeout: Timeout between two dbytes. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_send_dbytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t tick; + uint16_t i, n_fifo, tmp = 0U; + + while (size--) + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = (*(uint16_t *)buf); + buf += 2; + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) + { + if (((ald_get_tick()) - tick) > timeout) + return ALD_TIMEOUT; + } + } + + if (hperh->perh == SPI0) + n_fifo = 16; + else if (hperh->perh == SPI1) + n_fifo = 4; + else + return ALD_ERROR; + + for (i = 0; i < n_fifo; ++i) + { + if ((hperh->perh->STAT & SPI_STAT_RXNE_MSK) != SPI_STAT_RXNE_MSK) + tmp = hperh->perh->DATA; + else + break; + } + + UNUSED(tmp); + return ALD_OK; +} + +/** + * @brief Receive some double-bytes fast in blocking mode. + * @note Bit width is 16-bits. Supports mode: Master. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be received. + * @param size: Length of data. Unit is double-bytes. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_master_recv_dbytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + uint16_t cnt = 8000U; + + while (size--) + { + hperh->perh->DATA = 0xFFFF; + cnt = 8000; + + while (((hperh->perh->STAT & SPI_STAT_RXNE_MSK) != SPI_STAT_RXNE_MSK) && (--cnt)); + + if (cnt) + { + *(uint16_t *)buf = (uint16_t)hperh->perh->DATA; + buf += 2; + } + else + { + return ALD_TIMEOUT; + } + } + + return ALD_OK; +} + +/** + * @brief Receive some double-bytes fast in blocking mode. + * @note Bit width is 16-bits. Supports mode: Slave. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be received. + * @param size: Length of data. Unit is double-bytes. + * @param timeout: Timeout between two dbytes. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_slave_recv_dbytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t tick; + + while (size--) + { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STAT_RXNE_MSK) != SPI_STAT_RXNE_MSK) + { + if (((ald_get_tick()) - tick) > timeout) + return ALD_TIMEOUT; + } + + *(uint16_t *)buf = (uint16_t)hperh->perh->DATA; + buf += 2; + } + + return ALD_OK; +} +/** + * @} + */ + +/** @defgroup SPI_Public_Functions_Group3 IO operation functions + * @brief SPI Transmit and Receive functions + * + * @verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master or slave mode: + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The ALD status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the ALD status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() and hperh->tx_rx_cplt_cbk() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The hperh->err_cbk() user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + + * @endverbatim + * @{ + */ +/** + * @brief Transmit an amount of data in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + uint32_t tick; + uint16_t temp; + + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != ALD_SPI_STATE_READY) + return ALD_BUSY; + + if (buf == NULL || size == 0) + return ALD_ERROR; + + hperh->state = ALD_SPI_STATE_BUSY_TX; + + if (hperh->init.crc_calc) + ALD_SPI_CRC_RESET(hperh); + + while (size > 1) + { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & ALD_SPI_STATUS_TXE) == RESET) + { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = *buf; + ++buf; + } + else + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = (*(uint16_t *)buf); + buf += 2; + } + + --size; + } + + tick = ald_get_tick(); + + while ((hperh->perh->STAT & ALD_SPI_STATUS_TXE) == RESET) + { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.crc_calc) + { + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = *buf; + } + else + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = (*(uint16_t *)buf); + } + + ALD_SPI_CRCNEXT_ENABLE(hperh); + } + else + { + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = *buf; + } + else + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = (*(uint16_t *)buf); + } + } + + while ((hperh->perh->STAT & ALD_SPI_STATUS_TXE) == RESET) + { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + while ((hperh->perh->STAT & ALD_SPI_STATUS_BUSY) != RESET) + { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + while ((spi_get_status(hperh, ALD_SPI_STATUS_RXNE)) != RESET) + { + temp = hperh->perh->DATA; + UNUSED(temp); + } + + hperh->state = ALD_SPI_STATE_READY; + return ALD_OK; +timeout: + + if (hperh->init.crc_calc) + ALD_SPI_CRC_RESET(hperh); + + hperh->state = ALD_SPI_STATE_READY; + return ALD_TIMEOUT; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_recv(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + uint32_t tick; + uint16_t temp; + + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != ALD_SPI_STATE_READY) + return ALD_BUSY; + + if (buf == NULL || size == 0) + return ALD_ERROR; + + if (hperh->init.mode == ALD_SPI_MODE_MASTER) + return ald_spi_send_recv(hperh, buf, buf, size, timeout); + + hperh->state = ALD_SPI_STATE_BUSY_RX; + hperh->err_code = ALD_SPI_ERROR_NONE; + + if (hperh->init.crc_calc) + ALD_SPI_CRC_RESET(hperh); + + while (size > 0) + { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & ALD_SPI_STATUS_RXNE) == RESET) + { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) + { + *buf = hperh->perh->DATA; + ++buf; + } + else + { + *(uint16_t *)buf = hperh->perh->DATA; + buf += 2; + } + + --size; + } + + if (hperh->init.crc_calc) + { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & ALD_SPI_STATUS_RXTH) != RESET) + { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + temp = hperh->perh->DATA; + UNUSED(temp); + + if ((hperh->perh->RIF & ALD_SPI_IF_CRCERR) != RESET) + { + hperh->err_code |= ALD_SPI_ERROR_CRC; + ALD_SPI_CRC_RESET(hperh); + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_CRCERR); + hperh->state = ALD_SPI_STATE_READY; + + return ALD_ERROR; + } + } + + hperh->state = ALD_SPI_STATE_READY; + return ALD_OK; + +timeout: + + if (hperh->init.crc_calc) + ALD_SPI_CRC_RESET(hperh); + + hperh->state = ALD_SPI_STATE_READY; + return ALD_TIMEOUT; +} + +/** + * @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). + * @param hperh: Pointer to a spi_handle_t structure. + * @param tx_buf: Pointer to data transmitted buffer + * @param rx_buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send_recv(ald_spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) +{ + uint32_t tick; + uint16_t temp; + + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != ALD_SPI_STATE_READY) + return ALD_BUSY; + + if (hperh->init.dir != ALD_SPI_DIRECTION_2LINES) + return ALD_ERROR; + + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ALD_ERROR; + + hperh->state = ALD_SPI_STATE_BUSY_TX_RX; + hperh->err_code = ALD_SPI_ERROR_NONE; + + if (hperh->init.crc_calc) + ALD_SPI_CRC_RESET(hperh); + + while (size > 1) + { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & ALD_SPI_STATUS_TXE) == RESET) + { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = *tx_buf; + ++tx_buf; + } + else + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = (*(uint16_t *)tx_buf); + tx_buf += 2; + } + + tick = ald_get_tick(); + + while ((hperh->perh->STAT & ALD_SPI_STATUS_RXNE) == RESET) + { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) + { + *rx_buf = (uint8_t)hperh->perh->DATA; + ++rx_buf; + } + else + { + (*(uint16_t *)rx_buf) = hperh->perh->DATA; + rx_buf += 2; + } + + --size; + } + + tick = ald_get_tick(); + + while ((hperh->perh->STAT & ALD_SPI_STATUS_TXE) == RESET) + { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) + { + if (hperh->init.crc_calc) + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = *tx_buf; + ALD_SPI_CRCNEXT_ENABLE(hperh); + } + else + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = *tx_buf; + } + } + else + { + if (hperh->init.crc_calc) + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = (*(uint16_t *)tx_buf); + ALD_SPI_CRCNEXT_ENABLE(hperh); + } + else + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = (*(uint16_t *)tx_buf); + } + } + + tick = ald_get_tick(); + + while ((hperh->perh->STAT & ALD_SPI_STATUS_RXNE) == RESET) + { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) + *rx_buf = (uint8_t)hperh->perh->DATA; + else + (*(uint16_t *)rx_buf) = hperh->perh->DATA; + + if (hperh->init.crc_calc) + { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & ALD_SPI_STATUS_TXE) == RESET) + { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + tick = ald_get_tick(); + + while ((hperh->perh->STAT & ALD_SPI_STATUS_RXNE) == RESET) + { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + temp = hperh->perh->DATA; + UNUSED(temp); + + if (ald_spi_get_flag_status(hperh, ALD_SPI_IF_CRCERR) != RESET) + { + hperh->err_code |= ALD_SPI_ERROR_CRC; + ALD_SPI_CRC_RESET(hperh); + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_CRCERR); + hperh->state = ALD_SPI_STATE_READY; + + return ALD_ERROR; + } + } + + while ((hperh->perh->STAT & ALD_SPI_STATUS_BUSY) != RESET) + { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + hperh->state = ALD_SPI_STATE_READY; + return ALD_OK; +timeout: + + if (hperh->init.crc_calc) + ALD_SPI_CRC_RESET(hperh); + + hperh->state = ALD_SPI_STATE_READY; + return ALD_TIMEOUT; +} + +/** + * @brief Wraps up transmission in non blocking mode. + * @param hperh: pointer to a spi_handle_t structure. + * @param buf: Pointer to data transmitted buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send_by_it(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != ALD_SPI_STATE_READY) + return ALD_BUSY; + + if (buf == NULL || size == 0) + return ALD_ERROR; + + __LOCK(hperh); + hperh->state = ALD_SPI_STATE_BUSY_TX; + hperh->err_code = ALD_SPI_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + __UNLOCK(hperh); + + if (hperh->init.crc_calc) + ALD_SPI_CRC_RESET(hperh); + + ald_spi_interrupt_config(hperh, ALD_SPI_IT_TXE, ENABLE); + + return ALD_OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_recv_by_it(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != ALD_SPI_STATE_READY) + return ALD_BUSY; + + if (buf == NULL || size == 0) + return ALD_ERROR; + + if ((hperh->init.dir == ALD_SPI_DIRECTION_2LINES) && (hperh->init.mode == ALD_SPI_MODE_MASTER)) + return ALD_ERROR; + + __LOCK(hperh); + hperh->state = ALD_SPI_STATE_BUSY_RX; + hperh->err_code = ALD_SPI_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + __UNLOCK(hperh); + + if (hperh->init.dir == ALD_SPI_DIRECTION_1LINE_RX) + ALD_SPI_1LINE_RX(hperh); + + if (hperh->init.crc_calc == ENABLE) + { + ALD_SPI_CRC_RESET(hperh); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_CRCERR, ENABLE); + } + + ald_spi_interrupt_config(hperh, ALD_SPI_IT_RXTH, ENABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_MODF, ENABLE); + + if (hperh->init.data_size <= ALD_SPI_DATA_SIZE_8) + { + *((uint8_t *) & (hperh->perh->DATA)) = 0xFF; + } + else + { + *((uint16_t *) & (hperh->perh->DATA)) = 0xFFFF; + } + + return ALD_OK; +} + +/** + * @brief Transmit and Receives an amount of data in non blocking mode + * @param hperh: Pointer to a spi_handle_t structure that contains + * the configuration information for the specified SPI module. + * @param tx_buf: Pointer to data transmitted buffer + * @param rx_buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send_recv_by_it(ald_spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != ALD_SPI_STATE_READY) + return ALD_BUSY; + + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ALD_ERROR; + + if (hperh->init.mode == ALD_SPI_MODE_SLAVER) + { + if ((spi_get_status(hperh, ALD_SPI_STATUS_TXE) == RESET) || (spi_get_status(hperh, ALD_SPI_STATUS_RXNE) != RESET)) + { + ALD_SYSCFG_UNLOCK(); + + if (hperh->perh == SPI0) + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_SPI0RST_MSK); + else if (hperh->perh == SPI1) + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_SPI1RST_MSK); + else + return ALD_ERROR; + + ALD_SYSCFG_LOCK(); + + ald_spi_reset(hperh); + ald_spi_init(hperh); + } + } + + __LOCK(hperh); + hperh->state = ALD_SPI_STATE_BUSY_TX_RX; + hperh->err_code = ALD_SPI_ERROR_NONE; + + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + __UNLOCK(hperh); + + if (hperh->init.crc_calc) + { + ALD_SPI_CRC_RESET(hperh); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_CRCERR, ENABLE); + } + + if ((hperh->init.dir == ALD_SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == ALD_SPI_DIRECTION_1LINE_RX)) + ALD_SPI_ENABLE(hperh); + + ald_spi_interrupt_config(hperh, ALD_SPI_IT_RXTH, ENABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_TXE, ENABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_MODF, ENABLE); + + return ALD_OK; +} + +/** + * @brief Transmit an amount of data used dma channel + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as SPI transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send_by_dma(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != ALD_SPI_STATE_READY) + return ALD_BUSY; + + if (buf == NULL || size == 0) + return ALD_ERROR; + + __LOCK(hperh); + hperh->state = ALD_SPI_STATE_BUSY_TX; + hperh->err_code = ALD_SPI_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + if (hperh->init.dir == ALD_SPI_DIRECTION_1LINE) + ALD_SPI_1LINE_TX(hperh); + + if (hperh->init.crc_calc) + ALD_SPI_CRC_RESET(hperh); + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA; + + hperh->hdmatx.cplt_tc_arg = (void *)hperh; + hperh->hdmatx.cplt_tc_cbk = spi_dma_send_cplt; + + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_TX, ENABLE); + + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + /* Configure SPI DMA transmit */ + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.config.src_data_width = hperh->init.data_size == ALD_SPI_DATA_SIZE_8 ? ALD_DMA_DATA_SIZE_BYTE : ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.dst_data_width = hperh->init.data_size == ALD_SPI_DATA_SIZE_8 ? ALD_DMA_DATA_SIZE_BYTE : ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmatx.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.msel = hperh->perh == SPI0 ? ALD_DMA_MSEL_SPI0 : ALD_DMA_MSEL_SPI1; + hperh->hdmatx.config.msigsel = ALD_DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&(hperh->hdmatx)); + + __UNLOCK(hperh); + + if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) + ALD_SPI_ENABLE(hperh); + + return ALD_OK; +} + +/** + * @brief Receive an amount of data used dma channel + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as SPI transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_recv_by_dma(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + uint16_t tmp_rx = 0xB1B2U; + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != ALD_SPI_STATE_READY) + return ALD_BUSY; + + if (buf == NULL || size == 0) + return ALD_ERROR; + + __LOCK(hperh); + hperh->state = ALD_SPI_STATE_BUSY_RX; + hperh->err_code = ALD_SPI_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + + if (hperh->init.dir == ALD_SPI_DIRECTION_1LINE_RX) + ALD_SPI_1LINE_RX(hperh); + + if ((hperh->init.dir == ALD_SPI_DIRECTION_2LINES) && (hperh->init.mode == ALD_SPI_MODE_MASTER)) + { + __UNLOCK(hperh); + return ALD_ERROR; + } + + if (hperh->init.crc_calc) + ALD_SPI_CRC_RESET(hperh); + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA; + + hperh->hdmarx.cplt_tc_arg = (void *)hperh; + hperh->hdmarx.cplt_tc_cbk = spi_dma_recv_cplt; + + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_RX, ENABLE); + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_TX, ENABLE); + + ald_dma_interrupt_config(ALD_DMA_CH_6, ALD_DMA_IT_FLAG_TC, ENABLE); + /* Configure SPI DMA transmit */ + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.config.src_data_width = hperh->init.data_size == ALD_SPI_DATA_SIZE_8 ? ALD_DMA_DATA_SIZE_BYTE : ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.dst_data_width = hperh->init.data_size == ALD_SPI_DATA_SIZE_8 ? ALD_DMA_DATA_SIZE_BYTE : ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)&tmp_rx; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.msel = hperh->perh == SPI0 ? ALD_DMA_MSEL_SPI0 : ALD_DMA_MSEL_SPI1; + hperh->hdmatx.config.msigsel = ALD_DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.channel = ALD_DMA_CH_6; + ald_dma_config_basic(&(hperh->hdmatx)); + + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + /* Configure DMA Receive */ + ald_dma_config_struct(&(hperh->hdmarx.config)); + hperh->hdmarx.config.src_data_width = hperh->init.data_size == ALD_SPI_DATA_SIZE_8 ? ALD_DMA_DATA_SIZE_BYTE : ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.dst_data_width = hperh->init.data_size == ALD_SPI_DATA_SIZE_8 ? ALD_DMA_DATA_SIZE_BYTE : ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmarx.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmarx.config.msel = hperh->perh == SPI0 ? ALD_DMA_MSEL_SPI0 : ALD_DMA_MSEL_SPI1; + hperh->hdmarx.config.msigsel = ALD_DMA_MSIGSEL_SPI_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&(hperh->hdmarx)); + + __UNLOCK(hperh); + + if ((hperh->init.dir == ALD_SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == ALD_SPI_DIRECTION_1LINE_RX)) + ALD_SPI_ENABLE(hperh); + + return ALD_OK; +} + +/** + * @brief Transmit and Receive an amount of data used dma channel + * @param hperh: Pointer to a spi_handle_t structure. + * @param tx_buf: Pointer to data buffer + * @param rx_buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param tx_channel: DMA channel as SPI transmit + * @param rx_channel: DMA channel as SPI receive + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send_recv_by_dma(ald_spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != ALD_SPI_STATE_READY && hperh->state != ALD_SPI_STATE_BUSY_RX) + return ALD_BUSY; + + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ALD_ERROR; + + __LOCK(hperh); + hperh->state = ALD_SPI_STATE_BUSY_RX; + hperh->err_code = ALD_SPI_ERROR_NONE; + + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA; + + hperh->hdmatx.cplt_tc_arg = NULL; + hperh->hdmatx.cplt_tc_cbk = NULL; + hperh->hdmarx.cplt_tc_arg = (void *)hperh; + hperh->hdmarx.cplt_tc_cbk = spi_dma_send_recv_cplt; + + if (hperh->init.crc_calc) + ALD_SPI_CRC_RESET(hperh); + + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_TX, ENABLE); + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_RX, ENABLE); + + ald_dma_interrupt_config(tx_channel, ALD_DMA_IT_FLAG_TC, ENABLE); + /* Configure SPI DMA transmit */ + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.config.src_data_width = hperh->init.data_size == ALD_SPI_DATA_SIZE_8 ? ALD_DMA_DATA_SIZE_BYTE : ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.dst_data_width = hperh->init.data_size == ALD_SPI_DATA_SIZE_8 ? ALD_DMA_DATA_SIZE_BYTE : ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)tx_buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmatx.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.msel = hperh->perh == SPI0 ? ALD_DMA_MSEL_SPI0 : ALD_DMA_MSEL_SPI1; + hperh->hdmatx.config.msigsel = ALD_DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.channel = tx_channel; + ald_dma_config_basic(&(hperh->hdmatx)); + + ald_dma_interrupt_config(rx_channel, ALD_DMA_IT_FLAG_TC, ENABLE); + /* Configure DMA Receive */ + ald_dma_config_struct(&(hperh->hdmarx.config)); + hperh->hdmarx.config.src_data_width = hperh->init.data_size == ALD_SPI_DATA_SIZE_8 ? ALD_DMA_DATA_SIZE_BYTE : ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.dst_data_width = hperh->init.data_size == ALD_SPI_DATA_SIZE_8 ? ALD_DMA_DATA_SIZE_BYTE : ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)rx_buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmarx.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmarx.config.msel = hperh->perh == SPI0 ? ALD_DMA_MSEL_SPI0 : ALD_DMA_MSEL_SPI1; + hperh->hdmarx.config.msigsel = ALD_DMA_MSIGSEL_SPI_RNR; + hperh->hdmarx.config.channel = rx_channel; + ald_dma_config_basic(&(hperh->hdmarx)); + + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status + */ +ald_status_t ald_spi_dma_pause(ald_spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + + __LOCK(hperh); + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_RX, DISABLE); + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status + */ +ald_status_t ald_spi_dma_resume(ald_spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + + __LOCK(hperh); + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_TX, ENABLE); + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_RX, ENABLE); + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status + */ +ald_status_t ald_spi_dma_stop(ald_spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + + __LOCK(hperh); + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_RX, DISABLE); + __UNLOCK(hperh); + + hperh->state = ALD_SPI_STATE_READY; + return ALD_OK; +} + +/** + * @} + */ + +/** @defgroup SPI_Public_Functions_Group4 Control functions + * @brief SPI Control functions + * + * @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) Handle interrupt about SPI module. The ald_spi_irq_handler() function must + be invoked by SPI-IRQ function. + (+) Configure the interrupt DISABLE/ENABLE. + (+) Configure the DMA request. + (+) Get interrupt source status. + (+) Get interrupt flag status. + (+) Clear interrupt flag + + @endverbatim + * @{ + */ + +/** + * @brief This function handles SPI interrupt request. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval None + */ +void ald_spi_irq_handler(ald_spi_handle_t *hperh) +{ + if ((hperh->state == ALD_SPI_STATE_BUSY_RX) || (hperh->state == ALD_SPI_STATE_BUSY_TX)) + { + if ((ald_spi_get_it_status(hperh, ALD_SPI_IT_RXTH) != RESET) && (ald_spi_get_flag_status(hperh, ALD_SPI_IF_RXTH) != RESET)) + __spi_recv_by_it(hperh); + + if ((ald_spi_get_it_status(hperh, ALD_SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, ALD_SPI_IF_TXE) != RESET)) + __spi_send_by_it(hperh); + } + else if (hperh->state == ALD_SPI_STATE_BUSY_TX_RX) + { + if (hperh->init.mode == ALD_SPI_MODE_SLAVER) + { + if ((ald_spi_get_it_status(hperh, ALD_SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, ALD_SPI_IF_TXE) != RESET)) + __spi_send_recv_by_it(hperh, ALD_SPI_SR_TXE); + + if ((ald_spi_get_it_status(hperh, ALD_SPI_IT_RXTH) != RESET) && (ald_spi_get_flag_status(hperh, ALD_SPI_IF_RXTH) != RESET)) + __spi_send_recv_by_it(hperh, ALD_SPI_SR_RXNE); + } + else + { + if (hperh->rx_size == hperh->tx_count) + { + if ((ald_spi_get_it_status(hperh, ALD_SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, ALD_SPI_IF_TXE) != RESET)) + __spi_send_recv_by_it(hperh, ALD_SPI_SR_TXE); + } + else + { + if ((ald_spi_get_it_status(hperh, ALD_SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, ALD_SPI_IF_TXE) != RESET) + && (ald_spi_get_it_status(hperh, ALD_SPI_IT_RXTH) != RESET) && (ald_spi_get_flag_status(hperh, ALD_SPI_IF_RXTH) != RESET)) + __spi_send_recv_by_it(hperh, ALD_SPI_SR_TXE_RXNE); + } + } + } + else + { + + } + + if (ald_spi_get_flag_status(hperh, ALD_SPI_IF_CRCERR) != RESET) + { + hperh->err_code |= ALD_SPI_ERROR_CRC; + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_CRCERR); + } + + if (ald_spi_get_flag_status(hperh, ALD_SPI_IF_MODF) != RESET) + { + hperh->err_code |= ALD_SPI_ERROR_MODF; + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_MODF); + } + + if (ald_spi_get_flag_status(hperh, ALD_SPI_IF_FRE) != RESET) + { + hperh->err_code |= ALD_SPI_ERROR_FRE; + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_FRE); + + } + + if (ald_spi_get_flag_status(hperh, ALD_SPI_IF_TXOV) != RESET) + { + if (hperh->state != ALD_SPI_STATE_BUSY_TX) + { + hperh->err_code |= ALD_SPI_ERROR_TXOV; + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_TXOV); + } + } + + if (ald_spi_get_flag_status(hperh, ALD_SPI_IF_RXOV) != RESET) + { + if (hperh->state != ALD_SPI_STATE_BUSY_RX) + { + hperh->err_code |= ALD_SPI_ERROR_RXOV; + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_RXOV); + } + } + + return; +} + +/** + * @brief Enables or disables the specified SPI interrupts. + * @param hperh: Pointer to a spi_handle_t structure. + * @param it: Specifies the SPI interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref spi_it_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_spi_interrupt_config(ald_spi_handle_t *hperh, ald_spi_it_t it, type_func_t state) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + hperh->perh->IER |= (uint32_t)it; + else + hperh->perh->IDR |= (uint32_t)it; + + return; +} + +/** + * @brief Configure the specified SPI speed. + * @param hperh: Pointer to a spi_handle_t structure. + * @param speed: Specifies the SPI speed. + * This parameter can be one of the @ref spi_baud_t. + * @retval None + */ +void ald_spi_speed_config(ald_spi_handle_t *hperh, ald_spi_baud_t speed) +{ + uint32_t tmp = 0U; + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_BAUD(speed)); + + tmp = hperh->perh->CON1; + tmp &= ~(0x7U << SPI_CON1_BAUD_POSS); + tmp |= (speed << SPI_CON1_BAUD_POSS); + hperh->perh->CON1 = tmp; + return; +} + +/** + * @brief Enables or disables the dma request. + * @param hperh: Pointer to a spi_handle_t structure. + * @param req: Specifies the SPI dma request sources to be enabled or disabled. + * This parameter can be one of the @ref spi_dma_req_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_spi_dma_req_config(ald_spi_handle_t *hperh, ald_spi_dma_req_t req, type_func_t state) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + { + if (req == ALD_SPI_DMA_REQ_TX) + SET_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + SET_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + else + { + if (req == ALD_SPI_DMA_REQ_TX) + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + + return; +} + +/** @brief Check whether the specified SPI state flag is set or not. + * @param hperh: Pointer to a spi_handle_t structure. + * @param status: specifies the flag to check. + * This parameter can be one of the @ref spi_status_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t spi_get_status(ald_spi_handle_t *hperh, ald_spi_status_t status) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_STATUS(status)); + + if (hperh->perh->STAT & status) + return SET; + + return RESET; +} + +/** + * @brief Checks whether the specified SPI interrupt has occurred or not. + * @param hperh: Pointer to a spi_handle_t structure. + * @param it: Specifies the SPI interrupt source to check. + * This parameter can be one of the @ref spi_it_t. + * @retval Status + * - SET + * - RESET + */ +it_status_t ald_spi_get_it_status(ald_spi_handle_t *hperh, ald_spi_it_t it) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IT(it)); + + if (hperh->perh->IVS & it) + return SET; + + return RESET; +} + +/** @brief Check whether the specified SPI flag is set or not. + * @param hperh: Pointer to a spi_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref spi_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t ald_spi_get_flag_status(ald_spi_handle_t *hperh, ald_spi_flag_t flag) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IF(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + +/** @brief Clear the specified SPI pending flags. + * @param hperh: Pointer to a spi_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref spi_flag_t. + * @retval None + */ +void ald_spi_clear_flag_status(ald_spi_handle_t *hperh, ald_spi_flag_t flag) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IF(flag)); + + hperh->perh->ICR |= flag; + return; +} + +/** + * @brief This function handles SPI communication timeout in interrupt function. + * @param hperh: Pointer to a spi_handle_t structure. + * @param flag: specifies the SPI flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t spi_wait_flag_irq(ald_spi_handle_t *hperh, ald_spi_flag_t flag, flag_status_t status, uint32_t timeout) +{ + assert_param(timeout > 0); + + while (((ald_spi_get_flag_status(hperh, flag)) != status) && (--timeout)); + + if (timeout) + return ALD_OK; + + ald_spi_interrupt_config(hperh, ALD_SPI_IT_TXE, DISABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_RXTH, DISABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_CRCERR, DISABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_MODF, DISABLE); + + return ALD_TIMEOUT; +} + +static ald_status_t spi_wait_bsy_flag(ald_spi_handle_t *hperh, flag_status_t status, uint32_t timeout) +{ + assert_param(timeout > 0); + + while ((READ_BIT(hperh->perh->STAT, SPI_STAT_BUSY_MSK)) && (--timeout)); + + if (timeout) + return ALD_OK; + + ald_spi_interrupt_config(hperh, ALD_SPI_IT_TXE, DISABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_RXTH, DISABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_CRCERR, DISABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_MODF, DISABLE); + + return ALD_TIMEOUT; +} + +/** + * @} + */ + +/** @defgroup SPI_Public_Functions_Group5 Peripheral State and Errors functions + * @brief SPI State and Errors functions + * + * @verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) ald_spi_get_state() API can check in run-time the state of the SPI peripheral + (+) ald_spi_get_error() check in run-time Errors occurring during communication + + @endverbatim + * @{ + */ + +/** + * @brief Returns the SPI state. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval ALD state + */ +ald_spi_state_t ald_spi_get_state(ald_spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + return hperh->state; +} + +/** + * @brief Return the SPI error code + * @param hperh: Pointer to a spi_handle_t structure. + * @retval SPI Error Code + */ +uint32_t ald_spi_get_error(ald_spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + return hperh->err_code; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Functions SPI Private Functions + * @brief SPI Private functions + * @{ + */ + +/** + * @brief handle program when an tx empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static void __spi_send_by_it(ald_spi_handle_t *hperh) +{ + uint16_t temp; + + if (hperh->tx_count == 0) + { + ald_spi_interrupt_config(hperh, ALD_SPI_IT_TXE, DISABLE); + hperh->state = ALD_SPI_STATE_READY; + + if (hperh->init.dir == ALD_SPI_DIRECTION_2LINES) + { + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_TXOV); + } + + if ((spi_wait_bsy_flag(hperh, RESET, 5000)) != ALD_OK) + { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + while ((spi_get_status(hperh, ALD_SPI_STATUS_RXNE)) != RESET) + { + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + + return; + } + + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_TXE); + + if (hperh->tx_count == 1) + { + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) + { + if (hperh->init.crc_calc) + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = *hperh->tx_buf; + ALD_SPI_CRCNEXT_ENABLE(hperh); + } + else + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = *hperh->tx_buf; + } + + ++hperh->tx_buf; + } + else + { + if (hperh->init.crc_calc) + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + ALD_SPI_CRCNEXT_ENABLE(hperh); + } + else + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + } + + hperh->tx_buf += 2; + } + } + else + { + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + } + else + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + hperh->tx_buf += 2; + } + } + + --hperh->tx_count; + return; +} + +/** + * @brief handle program when an rx no empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static void __spi_recv_by_it(ald_spi_handle_t *hperh) +{ + uint16_t temp; + + while (READ_BITS(hperh->perh->STAT, SPI_STAT_RXFLV_MSK, SPI_STAT_RXFLV_POSS)) + { + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) + { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + } + else + { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + } + + --hperh->rx_count; + } + + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_RXTH); + + if (hperh->rx_count == 0) + { + ald_spi_interrupt_config(hperh, ALD_SPI_IT_RXTH, DISABLE); + hperh->state = ALD_SPI_STATE_READY; + + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, ALD_SPI_IF_CRCERR) != RESET)) + { + hperh->err_code |= ALD_SPI_ERROR_CRC; + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_CRCERR); + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + if (hperh->init.crc_calc) + { + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + if (hperh->init.data_size <= ALD_SPI_DATA_SIZE_8) + { + hperh->perh->DATA = 0xff; + } + else + { + hperh->perh->DATA = 0xffff; + } + + return; +} + +/** + * @brief handle program when an rx no empty interrupt flag arrived in non block mode(2 lines) + * @param hperh: Pointer to a spi_handle_t structure. + * @param status: SR.TXE or SR.RXNE set. + * @retval Status, see @ref ald_status_t. + */ +static void __spi_send_recv_by_it(ald_spi_handle_t *hperh, ald_spi_sr_status_t status) +{ + if (hperh->rx_count != 0) + { + if ((status == ALD_SPI_SR_RXNE) || (status == ALD_SPI_SR_TXE_RXNE)) + { + while (spi_get_status(hperh, ALD_SPI_STATUS_RXTH) != RESET) + { + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) + { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + } + else + { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + } + + --hperh->rx_count; + } + + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_RXTH); + } + } + + if (hperh->tx_count != 0) + { + if ((status == ALD_SPI_SR_TXE) || (status == ALD_SPI_SR_TXE_RXNE)) + { + if (hperh->tx_count == 1) + { + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) + { + if (hperh->init.crc_calc) + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = *hperh->tx_buf; + ALD_SPI_CRCNEXT_ENABLE(hperh); + } + else + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = *hperh->tx_buf; + } + + ++hperh->tx_buf; + } + else + { + if (hperh->init.crc_calc) + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + ALD_SPI_CRCNEXT_ENABLE(hperh); + } + else + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + } + + hperh->tx_buf += 2; + } + + --hperh->tx_count; + } + else + { + if (hperh->init.data_size == ALD_SPI_DATA_SIZE_8) + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + } + else + { + while (hperh->perh->STAT & SPI_STAT_TXF_MSK); + + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + hperh->tx_buf += 2; + } + + --hperh->tx_count; + } + + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_TXE); + } + } + + if (hperh->rx_count == 0) + { + ald_spi_interrupt_config(hperh, ALD_SPI_IT_TXE, DISABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_RXTH, DISABLE); + ald_spi_interrupt_config(hperh, ALD_SPI_IT_MODF, DISABLE); + hperh->state = ALD_SPI_STATE_READY; + + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, ALD_SPI_IF_CRCERR) != RESET)) + { + hperh->err_code |= ALD_SPI_ERROR_CRC; + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_CRCERR); + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + if (hperh->tx_rx_cplt_cbk) + hperh->tx_rx_cplt_cbk(hperh); + } + + return; +} + +/** + * @brief DMA SPI transmit process complete callback. + * @param arg: Pointer to a spi_handle_t structure. + * @retval None + */ +static void spi_dma_send_cplt(void *arg) +{ + uint16_t delay, temp; + ald_spi_handle_t *hperh = (ald_spi_handle_t *)arg; + + hperh->tx_count = 0; + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_TX, DISABLE); + hperh->state = ALD_SPI_STATE_READY; + + while ((spi_get_status(hperh, ALD_SPI_STATUS_RXNE)) != RESET) + { + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if (hperh->init.dir == ALD_SPI_DIRECTION_2LINES) + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_TXOV); + + if ((spi_wait_bsy_flag(hperh, RESET, 5000)) != ALD_OK) + hperh->err_code |= ALD_SPI_ERROR_FLAG; + + for (delay = 0; delay < 3000; delay++); + + if (hperh->err_code == ALD_SPI_ERROR_NONE) + { + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + } + else + { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +/** + * @brief DMA SPI receive process complete callback. + * @param arg: Pointer to a spi_handle_t structure. + * @retval None + */ +static void spi_dma_recv_cplt(void *arg) +{ + uint32_t tmp; + ald_spi_handle_t *hperh = (ald_spi_handle_t *)arg; + + hperh->rx_count = 0; + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_RX, DISABLE); + hperh->state = ALD_SPI_STATE_READY; + + if (hperh->init.crc_calc) + { + if ((spi_wait_flag_irq(hperh, ALD_SPI_IF_RXTH, SET, 5000)) != ALD_OK) + hperh->err_code |= ALD_SPI_ERROR_FLAG; + + tmp = hperh->perh->DATA; + UNUSED(tmp); + + if (ald_spi_get_flag_status(hperh, ALD_SPI_IF_CRCERR) == SET) + { + SET_BIT(hperh->err_code, ALD_SPI_ERROR_CRC); + ALD_SPI_CRC_RESET(hperh); + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_CRCERR); + } + } + + if (hperh->err_code == ALD_SPI_ERROR_NONE) + { + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + else + { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +/** + * @brief DMA SPI transmit and receive process complete callback. + * @param arg: Pointer to a SPI_handle_t structure. + * @retval None + */ +static void spi_dma_send_recv_cplt(void *arg) +{ + uint32_t tmp; + uint16_t delay; + ald_spi_handle_t *hperh = (ald_spi_handle_t *)arg; + + if (hperh->init.crc_calc) + { + if ((spi_wait_flag_irq(hperh, ALD_SPI_IF_RXTH, SET, 5000)) != ALD_OK) + hperh->err_code |= ALD_SPI_ERROR_FLAG; + + tmp = hperh->perh->DATA; + UNUSED(tmp); + + if (ald_spi_get_flag_status(hperh, ALD_SPI_IF_CRCERR) == SET) + { + SET_BIT(hperh->err_code, ALD_SPI_ERROR_CRC); + ald_spi_clear_flag_status(hperh, ALD_SPI_IF_CRCERR); + } + } + + if ((spi_wait_bsy_flag(hperh, RESET, 5000)) != ALD_OK) + hperh->err_code |= ALD_SPI_ERROR_FLAG; + + for (delay = 0; delay < 3000; delay++); + + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, ALD_SPI_DMA_REQ_RX, DISABLE); + hperh->tx_count = 0; + hperh->rx_count = 0; + hperh->state = ALD_SPI_STATE_READY; + + if (hperh->err_code == ALD_SPI_ERROR_NONE) + { + if (hperh->tx_rx_cplt_cbk) + hperh->tx_rx_cplt_cbk(hperh); + } + else + { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_spi.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_spi.h new file mode 100644 index 0000000000..0a6583af7d --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_spi.h @@ -0,0 +1,482 @@ +/** + ********************************************************************************* + * + * @file ald_spi.c + * @brief Header file of SPI module driver. + * + * @version V1.0 + * @date 23 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Feb. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_SPI_H__ +#define __ALD_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_dma.h" +#include "ald_syscfg.h" + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Constants -------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup SPI_Public_Types SPI Public Types + * @{ + */ + +/** + * @brief clock phase + */ +typedef enum +{ + ALD_SPI_CPHA_FIRST = 0U, /**< Transiting data in the first edge */ + ALD_SPI_CPHA_SECOND = 1U, /**< Transiting data in the seconde edge */ +} ald_spi_cpha_t; + +/** + * @brief clock polarity + */ +typedef enum +{ + ALD_SPI_CPOL_LOW = 0U, /**< Polarity hold low when spi-bus is idle */ + ALD_SPI_CPOL_HIGH = 1U, /**< Polarity hold high when spi-bus is idle */ +} ald_spi_cpol_t; + +/** + * @brief master selection + */ +typedef enum +{ + ALD_SPI_MODE_SLAVER = 0U, /**< Slave mode */ + ALD_SPI_MODE_MASTER = 1U, /**< Master mode */ +} ald_spi_mode_t; + +/** + * @brief baud rate control + */ +typedef enum +{ + ALD_SPI_BAUD_2 = 0U, /**< fpclk/2 */ + ALD_SPI_BAUD_4 = 1U, /**< fpclk/4 */ + ALD_SPI_BAUD_8 = 2U, /**< fpclk/8 */ + ALD_SPI_BAUD_16 = 3U, /**< fpclk/16 */ + ALD_SPI_BAUD_32 = 4U, /**< fpclk/32 */ + ALD_SPI_BAUD_64 = 5U, /**< fpclk/64 */ + ALD_SPI_BAUD_128 = 6U, /**< fpclk/128 */ + ALD_SPI_BAUD_256 = 7U, /**< fpclk/256 */ +} ald_spi_baud_t; + +/** + * @brief frame format + */ +typedef enum +{ + ALD_SPI_FIRSTBIT_MSB = 0U, /**< MSB transmitted first */ + ALD_SPI_FIRSTBIT_LSB = 1U, /**< LSB transmitted first */ +} ald_spi_firstbit_t; + +/** + * @brief data frame format + */ +typedef enum +{ + ALD_SPI_DATA_SIZE_8 = 0U, /**< 8-bit data frame format is selected for transmission/reception */ + ALD_SPI_DATA_SIZE_16 = 1U, /**< 16-bit data frame format is selected for transmission/reception */ +} ald_spi_datasize_t; + +/** + * @brief SPI error status + */ +typedef enum +{ + ALD_SPI_ERROR_NONE = 0U, /**< none */ + ALD_SPI_ERROR_MODF = 1U, /**< mode fault */ + ALD_SPI_ERROR_CRC = 2U, /**< crc error */ + ALD_SPI_ERROR_FRE = 4U, /**< frame error */ + ALD_SPI_ERROR_RXOV = 8U, /**< receive over error */ + ALD_SPI_ERROR_TXOV = 0x10U, /**< dma error */ + ALD_SPI_ERROR_FLAG = 0x20U, /**< interrupt flag error */ +} ald_spi_error_t; + +/** + * @brief interrupt control + */ +typedef enum +{ + ALD_SPI_IT_TXE = (1U << 0), /**< Transmit fifo empty interrupt */ + ALD_SPI_IT_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt */ + ALD_SPI_IT_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt */ + ALD_SPI_IT_TXTH = (1U << 4), /**< Transmit fifo under threshold interrupt */ + ALD_SPI_IT_RXNE = (1U << 8), /**< Receive fifo not empty interrupt */ + ALD_SPI_IT_RXF = (1U << 9), /**< Receive fifo full interrupt */ + ALD_SPI_IT_RXOV = (1U << 10), /**< Receive fifo overflow interrupt */ + ALD_SPI_IT_RXUD = (1U << 11), /**< Receive fifo underflow interrupt */ + ALD_SPI_IT_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt */ + ALD_SPI_IT_CRCERR = (1U << 16), /**< Crc error interrupt */ + ALD_SPI_IT_MODF = (1U << 17), /**< Mode error interrupt */ + ALD_SPI_IT_FRE = (1U << 18), /**< Frame error interrupt */ +} ald_spi_it_t; + +/** + * @brief interrupt flag + */ +typedef enum +{ + ALD_SPI_IF_TXE = (1U << 0), /**< Transmit fifo empty interrupt flag */ + ALD_SPI_IF_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt flag */ + ALD_SPI_IF_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt flag */ + ALD_SPI_IF_TXTH = (1U << 4), /**< Transmit fifo under threshold interrupt flag */ + ALD_SPI_IF_RXNE = (1U << 8), /**< Receive fifo not empty interrupt flag */ + ALD_SPI_IF_RXF = (1U << 9), /**< Receive fifo full interrupt flag */ + ALD_SPI_IF_RXOV = (1U << 10), /**< Receive fifo overflow interrupt flag */ + ALD_SPI_IF_RXUD = (1U << 11), /**< Receive fifo underflow interrupt flag */ + ALD_SPI_IF_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt flag */ + ALD_SPI_IF_CRCERR = (1U << 16), /**< Crc error interrupt flag */ + ALD_SPI_IF_MODF = (1U << 17), /**< Mode error interrupt flag */ + ALD_SPI_IF_FRE = (1U << 18), /**< Frame error interrupt flag */ +} ald_spi_flag_t; + +/** + * @brief SPI state structures definition + */ +typedef enum +{ + ALD_SPI_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + ALD_SPI_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + ALD_SPI_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + ALD_SPI_STATE_BUSY_TX = 0x11U, /**< transmit is ongoing */ + ALD_SPI_STATE_BUSY_RX = 0x21U, /**< receive is ongoing */ + ALD_SPI_STATE_BUSY_TX_RX = 0x31U, /**< transmit and receive are ongoing */ + ALD_SPI_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + ALD_SPI_STATE_ERROR = 0x04U, /**< Error */ +} ald_spi_state_t; + +/** + * @brief SPI direction definition + */ +typedef enum +{ + ALD_SPI_DIRECTION_2LINES = 0U, /**< 2 lines */ + ALD_SPI_DIRECTION_2LINES_RXONLY = 1U, /**< 2 lines only rx */ + ALD_SPI_DIRECTION_1LINE = 2U, /**< 1 line */ + ALD_SPI_DIRECTION_1LINE_RX = 3U, /**< 1 line only rx */ +} ald_spi_direction_t; + +/** + * @brief SPI dma request definition + */ +typedef enum +{ + ALD_SPI_DMA_REQ_TX = 0U, /**< TX dma request */ + ALD_SPI_DMA_REQ_RX = 1U, /**< RX dma request */ +} ald_spi_dma_req_t; + +/** + * @brief SPI crc length definition + */ +typedef enum +{ + ALD_SPI_FRAME_MOTOROLA = 0U, /**< SPI motorola mode */ + ALD_SPI_FRAME_TI = 1U, /**< SPI TI mode */ +} ald_spi_frame_t; + +/** + * @brief SPI status definition + */ +typedef enum +{ + ALD_SPI_STATUS_TXE = (1U << 0), /**< Transmit fifo empty status */ + ALD_SPI_STATUS_TXF = (1U << 1), /**< Transmit fifo full status */ + ALD_SPI_STATUS_TXOV = (1U << 2), /**< Transmit fifo overflow status */ + ALD_SPI_STATUS_TXUD = (1U << 3), /**< Transmit fifo underflow status */ + ALD_SPI_STATUS_TXTH = (1U << 4), /**< Transmit fifo under threshold status */ + ALD_SPI_STATUS_RXNE = (1U << 8), /**< Receive fifo not empty status */ + ALD_SPI_STATUS_RXF = (1U << 9), /**< Receive fifo full status */ + ALD_SPI_STATUS_RXOV = (1U << 10), /**< Receive fifo overflow status */ + ALD_SPI_STATUS_RXUD = (1U << 11), /**< Receive fifo underflow status */ + ALD_SPI_STATUS_RXTH = (1U << 12), /**< Receive fifo under threshold status */ + ALD_SPI_STATUS_BUSY = (1U << 15), /**< BUSY status */ +} ald_spi_status_t; + +/** + * @brief SPI TXE/RXNE status definition + */ +typedef enum +{ + ALD_SPI_SR_TXE = 0U, /**< SR.TXE set */ + ALD_SPI_SR_RXNE = 1U, /**< SR.RXTH set */ + ALD_SPI_SR_TXE_RXNE = 2U, /**< SR.TXE and SR.RXNE set */ +} ald_spi_sr_status_t; + + +/** + * @brief SPI init structure definition + */ +typedef struct +{ + ald_spi_mode_t mode; /**< SPI mode */ + ald_spi_direction_t dir; /**< SPI direction */ + ald_spi_datasize_t data_size; /**< SPI data size */ + ald_spi_baud_t baud; /**< SPI baudrate prescaler */ + ald_spi_cpha_t phase; /**< SPI clock phase */ + ald_spi_cpol_t polarity; /**< SPI clock polarity */ + ald_spi_firstbit_t first_bit; /**< SPI first bit */ + type_func_t ss_en; /**< SPI ssm enable or disable */ + type_func_t crc_calc; /**< SPI crc calculation */ + ald_spi_frame_t frame; /**< SPI frame format */ + uint16_t crc_poly; /**< SPI crc polynomial */ +} ald_spi_init_t; + +/** + * @brief SPI handle structure definition + */ +typedef struct ald_spi_handle_s +{ + SPI_I2S_TypeDef *perh; /**< SPI registers base address */ + ald_spi_init_t init; /**< SPI communication parameters */ + uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */ + uint16_t tx_size; /**< SPI Tx transfer size */ + uint16_t tx_count; /**< SPI Tx transfer counter */ + uint8_t *rx_buf; /**< Pointer to SPI Rx transfer buffer */ + uint16_t rx_size; /**< SPI Rx Transfer size */ + uint16_t rx_count; /**< SPI Rx Transfer Counter */ + + ald_dma_handle_t hdmatx; /**< SPI Tx DMA handle parameters */ + ald_dma_handle_t hdmarx; /**< SPI Rx DMA handle parameters */ + + lock_state_t lock; /**< Locking object */ + ald_spi_state_t state; /**< SPI communication state */ + uint32_t err_code; /**< SPI error code */ + + void (*tx_cplt_cbk)(struct ald_spi_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct ald_spi_handle_s *arg); /**< Rx completed callback */ + void (*tx_rx_cplt_cbk)(struct ald_spi_handle_s *arg); /**< Tx & Rx completed callback */ + void (*err_cbk)(struct ald_spi_handle_s *arg); /**< error callback */ +} ald_spi_handle_t; +/** + * @} + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** @defgroup SPI_Public_Macros SPI Public Macros + * @{ + */ +#define ALD_SPI_RESET_HANDLE_STATE(x) ((x)->state = ALD_SPI_STATE_RESET) +#define ALD_SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS)) +#define ALD_SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS)) +#define ALD_SPI_CRC_RESET(x) \ + do { \ + CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ + SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ + } while (0) +#define ALD_SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) +#define ALD_SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) +#define ALD_SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) +#define ALD_SPI_RXONLY_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) +#define ALD_SPI_1LINE_TX(x) (SET_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK)) +#define ALD_SPI_1LINE_RX(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK)) +#define ALD_SPI_SSI_HIGH(x) (SET_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK)) +#define ALD_SPI_SSI_LOW(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK)) +#define ALD_SPI_SSOE_ENABLE(x) (SET_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK)) +#define ALD_SPI_SSOE_DISABLE(x) (CLEAR_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK)) +/** + * @} + */ + +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ +#define IS_SPI(x) (((x) == SPI0) || \ + ((x) == SPI1)) +#define IS_SPI_CPHA(x) (((x) == ALD_SPI_CPHA_FIRST) || \ + ((x) == ALD_SPI_CPHA_SECOND)) +#define IS_SPI_CPOL(x) (((x) == ALD_SPI_CPOL_LOW) || \ + ((x) == ALD_SPI_CPOL_HIGH)) +#define IS_SPI_MODE(x) (((x) == ALD_SPI_MODE_SLAVER) || \ + ((x) == ALD_SPI_MODE_MASTER)) +#define IS_SPI_FIRBIT(x) (((x) == ALD_SPI_FIRSTBIT_MSB) || \ + ((x) == ALD_SPI_FIRSTBIT_LSB)) +#define IS_SPI_BAUD(x) (((x) == ALD_SPI_BAUD_2) || \ + ((x) == ALD_SPI_BAUD_4) || \ + ((x) == ALD_SPI_BAUD_8) || \ + ((x) == ALD_SPI_BAUD_16) || \ + ((x) == ALD_SPI_BAUD_32) || \ + ((x) == ALD_SPI_BAUD_64) || \ + ((x) == ALD_SPI_BAUD_128) || \ + ((x) == ALD_SPI_BAUD_256)) +#define IS_SPI_DATASIZE(x) (((x) == ALD_SPI_DATA_SIZE_8) || \ + ((x) == ALD_SPI_DATA_SIZE_16)) +#define IS_SPI_BIDOE(x) (((x) == ALD_SPI_BID_RX) || \ + ((x) == ALD_SPI_BID_TX)) +#define IS_SPI_BIDMODE(x) (((x) == ALD_SPI_BIDMODE_DUAL) || \ + ((x) == ALD_SPI_BIDMODE_SOLE)) +#define IS_SPI_DIRECTION(x) (((x) == ALD_SPI_DIRECTION_2LINES) || \ + ((x) == ALD_SPI_DIRECTION_2LINES_RXONLY) || \ + ((x) == ALD_SPI_DIRECTION_1LINE) || \ + ((x) == ALD_SPI_DIRECTION_1LINE_RX)) +#define IS_SPI_DMA_REQ(x) (((x) == ALD_SPI_DMA_REQ_TX) || \ + ((x) == ALD_SPI_DMA_REQ_RX)) +#define IS_SPI_STATUS(x) (((x) == ALD_SPI_STATUS_TXE) || \ + ((x) == ALD_SPI_STATUS_TXF) || \ + ((x) == ALD_SPI_STATUS_TXOV) || \ + ((x) == ALD_SPI_STATUS_TXUD) || \ + ((x) == ALD_SPI_STATUS_TXTH) || \ + ((x) == ALD_SPI_STATUS_RXNE) || \ + ((x) == ALD_SPI_STATUS_RXF) || \ + ((x) == ALD_SPI_STATUS_RXOV) || \ + ((x) == ALD_SPI_STATUS_RXUD) || \ + ((x) == ALD_SPI_STATUS_RXTH) || \ + ((x) == ALD_SPI_STATUS_BUSY)) +#define IS_SPI_IT(x) (((x) == ALD_SPI_IT_TXE) || \ + ((x) == ALD_SPI_IT_TXOV) || \ + ((x) == ALD_SPI_IT_TXUD) || \ + ((x) == ALD_SPI_IT_TXTH) || \ + ((x) == ALD_SPI_IT_RXNE) || \ + ((x) == ALD_SPI_IT_RXF) || \ + ((x) == ALD_SPI_IT_RXOV) || \ + ((x) == ALD_SPI_IT_RXUD) || \ + ((x) == ALD_SPI_IT_RXTH) || \ + ((x) == ALD_SPI_IT_CRCERR) || \ + ((x) == ALD_SPI_IT_MODF) || \ + ((x) == ALD_SPI_IT_FRE)) +#define IS_SPI_IF(x) (((x) == ALD_SPI_IF_TXE) || \ + ((x) == ALD_SPI_IF_TXOV) || \ + ((x) == ALD_SPI_IF_TXUD) || \ + ((x) == ALD_SPI_IF_TXTH) || \ + ((x) == ALD_SPI_IF_RXNE) || \ + ((x) == ALD_SPI_IF_RXF) || \ + ((x) == ALD_SPI_IF_RXOV) || \ + ((x) == ALD_SPI_IF_RXUD) || \ + ((x) == ALD_SPI_IF_RXTH) || \ + ((x) == ALD_SPI_IF_CRCERR) || \ + ((x) == ALD_SPI_IF_MODF) || \ + ((x) == ALD_SPI_IF_FRE)) +#define IS_SPI_FRAME(x) (((x) == ALD_SPI_FRAME_MOTOROLA) || \ + ((x) == ALD_SPI_FRAME_TI) ) +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @addtogroup SPI_Public_Functions + * @{ + */ + +/** @addtogroup SPI_Public_Functions_Group1 + * @{ + */ + +ald_status_t ald_spi_init(ald_spi_handle_t *hperh); +void ald_spi_reset(ald_spi_handle_t *hperh); +/** + * @} + */ +/** @addtogroup SPI_Public_Functions_Group2 + * @{ + */ +int32_t ald_spi_send_byte_fast(ald_spi_handle_t *hperh, uint8_t data); +int32_t ald_spi_send_byte_fast_1line(ald_spi_handle_t *hperh, uint8_t data); +uint8_t ald_spi_recv_byte_fast(ald_spi_handle_t *hperh, int *status); +ald_status_t ald_spi_send_bytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_spi_master_recv_bytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size); +ald_status_t ald_spi_slave_recv_bytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_spi_send_dbytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_spi_master_recv_dbytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size); +ald_status_t ald_spi_slave_recv_dbytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +/** + * @} + */ +/** @addtogroup SPI_Public_Functions_Group3 + * @{ + */ +ald_status_t ald_spi_send(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_spi_recv(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_spi_send_recv(ald_spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout); +ald_status_t ald_spi_send_by_it(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_spi_recv_by_it(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_spi_send_recv_by_it(ald_spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size); + +ald_status_t ald_spi_send_by_dma(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_spi_recv_by_dma(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_spi_send_recv_by_dma(ald_spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); +ald_status_t ald_spi_dma_pause(ald_spi_handle_t *hperh); +ald_status_t ald_spi_dma_resume(ald_spi_handle_t *hperh); +ald_status_t ald_spi_dma_stop(ald_spi_handle_t *hperh); + +/** + * @} + */ +/** @addtogroup SPI_Public_Functions_Group4 + * @{ + */ +void ald_spi_irq_handler(ald_spi_handle_t *hperh); +void ald_spi_interrupt_config(ald_spi_handle_t *hperh, ald_spi_it_t it, type_func_t state); +void ald_spi_speed_config(ald_spi_handle_t *hperh, ald_spi_baud_t speed); +void ald_spi_dma_req_config(ald_spi_handle_t *hperh, ald_spi_dma_req_t req, type_func_t state); +it_status_t ald_spi_get_it_status(ald_spi_handle_t *hperh, ald_spi_it_t it); +flag_status_t spi_get_status(ald_spi_handle_t *hperh, ald_spi_status_t status); +flag_status_t ald_spi_get_flag_status(ald_spi_handle_t *hperh, ald_spi_flag_t flag); +void ald_spi_clear_flag_status(ald_spi_handle_t *hperh, ald_spi_flag_t flag); +/** + * @} + */ +/** @addtogroup SPI_Public_Functions_Group5 + * @{ + */ +ald_spi_state_t ald_spi_get_state(ald_spi_handle_t *hperh); +uint32_t ald_spi_get_error(ald_spi_handle_t *hperh); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_SPI_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_syscfg.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_syscfg.h new file mode 100644 index 0000000000..14200f812b --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_syscfg.h @@ -0,0 +1,95 @@ +/** + ********************************************************************************* + * + * @file ald_syscfg.h + * @brief SYSCFG module driver. + * + * @version V1.0 + * @date 31 Jan. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 31 Jan. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_SYSCFG_H__ +#define __ALD_SYSCFG_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_utils.h" + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Constants -------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup SYSCFG SYSCFG + * @brief SYSCFG module driver + * @{ + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** @defgroup SYSCFG_Public_Macros SYSCFG Public Macros + * @{ + */ +#define ALD_SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0U) +#define ALD_SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996U) +#define ALD_GET_SYSCFG_LOCK() READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK) + +/* Exported Types ------------------------------------------------------------ */ + +/** + * @brief PIS IO Select + */ +typedef enum +{ + ALD_SYSCFG_PISIOCFG_PA = 0x0U, + ALD_SYSCFG_PISIOCFG_PB = 0x1U, + ALD_SYSCFG_PISIOCFG_PC = 0x2U, + ALD_SYSCFG_PISIOCFG_PD = 0x3U, +} ald_syscfg_pisiocfg_t; +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALD_SYSCFG_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_timer.c b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_timer.c new file mode 100644 index 0000000000..786e3d3775 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_timer.c @@ -0,0 +1,3778 @@ +/** + ********************************************************************************* + * + * @file ald_timer.c + * @brief TIMER module driver. + * This is the common part of the TIMER initialization + * + * @version V1.0 + * @date 03 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 03 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ + +#include +#include "ald_timer.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup TIMER TIMER + * @brief TIMER module driver + * @{ + */ + +/* Private function prototypes ----------------------------------------------- */ + +/** @defgroup TIMER_Private_Functions TIMER Private Functions + * @{ + */ +static void timer_base_set_config(TIMER_TypeDef *TIMERx, ald_timer_base_init_t *init); +static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, ald_timer_oc_init_t *oc_config); +static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, ald_timer_oc_init_t *oc_config); +static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, ald_timer_oc_init_t *oc_config); +static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, ald_timer_oc_init_t *oc_config); +static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, ald_timer_channel_t ch, type_func_t state); +static void timer_ccxn_channel_cmd(TIMER_TypeDef *TIMERx, ald_timer_channel_t ch, type_func_t state); +static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, + ald_timer_ic_select_t sel, uint32_t filter); +static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, uint32_t filter); +static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, + ald_timer_ic_select_t sel, uint32_t filter); +static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, uint32_t filter); +static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, + ald_timer_ic_select_t sel, uint32_t filter); +static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, + ald_timer_ic_select_t sel, uint32_t filter); +static void timer_etr_set_config(TIMER_TypeDef *TIMERx, ald_timer_etr_psc_t psc, ald_timer_clock_polarity_t polarity, uint32_t filter); +static void timer_slave_set_config(ald_timer_handle_t *hperh, ald_timer_slave_config_t *config); + +static void timer_dma_oc_cplt(void *arg); +static void timer_dma_capture_cplt(void *arg); +static void timer_dma_period_elapse_cplt(void *arg); +static void timer_dma_msel(TIMER_TypeDef *hperh, ald_dma_config_t *config); + +/* Private Function ---------------------------------------------------------- */ + +/** + * @}TIMER_Private_Functions + */ + +/** @defgroup TIMER_Public_Functions TIMER Public Functions + * @{ + */ + +/** @defgroup TIMER_Public_Functions_Group1 TIMER Base functions + * @brief Time Base functions + * + * @verbatim + ============================================================================== + ##### Timer Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER base. + (+) Reset the TIMER base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Time base Unit according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER base handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_base_init(ald_timer_handle_t *hperh) +{ + if (hperh == NULL) + return ALD_ERROR; + + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + + if (hperh->state == ALD_TIMER_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = ALD_TIMER_STATE_BUSY; + timer_base_set_config(hperh->perh, &hperh->init); + hperh->state = ALD_TIMER_STATE_READY; + + return ALD_OK; +} + +/** + * @brief Reset the TIMER base peripheral + * @param hperh: TIMER base handle + * @retval Status, see @ref ald_status_t. + */ +void ald_timer_base_reset(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + hperh->state = ALD_TIMER_STATE_BUSY; + ALD_TIMER_DISABLE(hperh); + hperh->state = ALD_TIMER_STATE_RESET; + __UNLOCK(hperh); + + return; +} + +/** + * @brief Starts the TIMER Base generation. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_base_start(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + hperh->state = ALD_TIMER_STATE_BUSY; + ALD_TIMER_ENABLE(hperh); + hperh->state = ALD_TIMER_STATE_READY; + + return; +} + +/** + * @brief Stops the TIMER Base generation. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_base_stop(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + hperh->state = ALD_TIMER_STATE_BUSY; + ALD_TIMER_DISABLE(hperh); + hperh->state = ALD_TIMER_STATE_READY; + + return; +} + +/** + * @brief Starts the TIMER Base generation in interrupt mode. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_base_start_by_it(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_UPDATE, ENABLE); + ALD_TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER Base generation in interrupt mode. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_base_stop_by_it(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_UPDATE, DISABLE); + ALD_TIMER_DISABLE(hperh); + + return; +} + +/** + * @brief Starts the TIMER Base generation in DMA mode. + * @param hperh: TIMER handle + * @param buf: The source Buffer address. + * @param len: The length of buffer to be transferred from memory to TIMER peripheral + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. +*/ +ald_status_t ald_timer_base_start_by_dma(ald_timer_handle_t *hperh, + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + if ((hperh->state == ALD_TIMER_STATE_BUSY)) + return ALD_BUSY; + + if ((hperh->state == ALD_TIMER_STATE_READY)) + { + if (((uint32_t)buf == 0) || (len == 0)) + return ALD_ERROR; + } + + hperh->state = ALD_TIMER_STATE_BUSY; + + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA; + + hperh->hdma1.cplt_tc_cbk = timer_dma_period_elapse_cplt; + hperh->hdma1.cplt_tc_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.src = (void *)buf; + hperh->hdma1.config.dst = (void *)&hperh->perh->AR; + hperh->hdma1.config.size = len; + hperh->hdma1.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdma1.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_UPDATE; + hperh->hdma1.config.channel = dma_ch; + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + ald_dma_config_basic(&hperh->hdma1); + ald_dma_interrupt_config(dma_ch, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_UPDATE, ENABLE); + ALD_TIMER_ENABLE(hperh); + + return ALD_OK; +} + +/** + * @brief Stops the TIMER Base generation in DMA mode. + * @param hperh: TIMER handle + * @retval None +*/ +void ald_timer_base_stop_by_dma(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_UPDATE, DISABLE); + ALD_TIMER_DISABLE(hperh); + hperh->state = ALD_TIMER_STATE_READY; + + return; +} + +/** + * @}TIMER_Public_Functions_Group1 + */ + +/** @defgroup TIMER_Public_Functions_Group2 TIMER Output Compare functions + * @brief Time Output Compare functions + * + * @verbatim + ============================================================================== + ##### Time Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER Output Compare. + (+) Start the Time Output Compare. + (+) Stop the Time Output Compare. + (+) Start the Time Output Compare and enable interrupt. + (+) Stop the Time Output Compare and disable interrupt. + (+) Start the Time Output Compare and enable DMA transfer. + (+) Stop the Time Output Compare and disable DMA transfer. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Output Compare according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_oc_init(ald_timer_handle_t *hperh) +{ + return ald_timer_base_init(hperh); +} + +/** + * @brief Starts the TIMER Output Compare signal generation. + * @param hperh: TIMER handle + * @param ch : TIMER Channel to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_oc_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + ALD_TIMER_MOE_ENABLE(hperh); + + ALD_TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Output Compare signal generation. + * @param hperh: TIMER handle + * @param ch: TIMER Channel to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_oc_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + ALD_TIMER_MOE_DISABLE(hperh); + + ALD_TIMER_DISABLE(hperh); + hperh->state = ALD_TIMER_STATE_READY; + return; +} + +/** + * @brief Starts the TIMER Output Compare signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channel to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_oc_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, ENABLE); + break; + + case ALD_TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, ENABLE); + break; + + case ALD_TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC3, ENABLE); + break; + + case ALD_TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC4, ENABLE); + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + ALD_TIMER_MOE_ENABLE(hperh); + + ALD_TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Output Compare signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channel to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_oc_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, DISABLE); + break; + + case ALD_TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, DISABLE); + break; + + case ALD_TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC3, DISABLE); + break; + + case ALD_TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC4, DISABLE); + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + ALD_TIMER_MOE_DISABLE(hperh); + + ALD_TIMER_DISABLE(hperh); + hperh->state = ALD_TIMER_STATE_READY; + return; +} + +/** + * @brief Starts the TIMER Output Compare signal generation in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @param buf: The source Buffer address. + * @param len: The length of buffer to be transferred from memory to TIMER peripheral + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_oc_start_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch, + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + if ((hperh->state == ALD_TIMER_STATE_BUSY)) + return ALD_BUSY; + + if ((hperh->state == ALD_TIMER_STATE_READY)) + { + if (((uint32_t)buf == 0) || (len == 0)) + return ALD_ERROR; + } + + hperh->state = ALD_TIMER_STATE_BUSY; + + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA; + + hperh->hdma1.cplt_tc_cbk = timer_dma_oc_cplt; + hperh->hdma1.cplt_tc_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.src = (void *)buf; + hperh->hdma1.config.size = len; + hperh->hdma1.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdma1.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdma1.config.channel = dma_ch; + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_1; + break; + + case ALD_TIMER_CHANNEL_2: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC2, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_2; + break; + + case ALD_TIMER_CHANNEL_3: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL3; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC3, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_3; + break; + + case ALD_TIMER_CHANNEL_4: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL4; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH4; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC4, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_4; + break; + + default: + break; + } + + ald_dma_interrupt_config(dma_ch, ALD_DMA_IT_FLAG_TC, ENABLE); + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + ALD_TIMER_MOE_ENABLE(hperh); + + ALD_TIMER_ENABLE(hperh); + return ALD_OK; +} + +/** + * @brief Stops the TIMER Output Compare signal generation in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None +*/ +void ald_timer_oc_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, DISABLE); + break; + + case ALD_TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC2, DISABLE); + break; + + case ALD_TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC3, DISABLE); + break; + + case ALD_TIMER_CHANNEL_4: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC4, DISABLE); + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + ALD_TIMER_MOE_DISABLE(hperh); + + ALD_TIMER_DISABLE(hperh); + hperh->state = ALD_TIMER_STATE_READY; + return; +} + +/** + * @}TIMER_Public_Functions_Group2 + */ + +/** @defgroup TIMER_Public_Functions_Group3 TIMER PWM functions + * @brief TIMER PWM functions + * + * @verbatim + ============================================================================== + ##### Time PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER PWM. + (+) Start the Time PWM. + (+) Stop the Time PWM. + (+) Start the Time PWM and enable interrupt. + (+) Stop the Time PWM and disable interrupt. + (+) Start the Time PWM and enable DMA transfer. + (+) Stop the Time PWM and disable DMA transfer. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER PWM Time Base according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_pwm_init(ald_timer_handle_t *hperh) +{ + return ald_timer_base_init(hperh); +} + +/** + * @brief Starts the PWM signal generation. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_pwm_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_oc_start(hperh, ch); + return; +} + +/** + * @brief Stops the PWM signal generation. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_pwm_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_oc_stop(hperh, ch); + return; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channel to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_pwm_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_oc_start_by_it(hperh, ch); + return; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_pwm_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_oc_stop_by_it(hperh, ch); + return; +} + +/** + * @brief Starts the TIMER PWM signal generation in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @param buf: The source Buffer address. + * @param len: The length of buffer to be transferred from memory to TIMER peripheral + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_pwm_start_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch, + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + return ald_timer_oc_start_by_dma(hperh, ch, buf, len, dma_ch); +} + +/** + * @brief Stops the TIMER PWM signal generation in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_pwm_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_oc_stop_by_dma(hperh, ch); + return; +} + +/** + * @brief Set the PWM freq. + * @param hperh: TIMER handle + * @param freq: PWM freq to set + * @retval None + */ +void ald_timer_pwm_set_freq(ald_timer_handle_t *hperh, uint32_t freq) +{ + uint32_t _arr; + + if (freq == 0) + return; + + _arr = ald_cmu_get_pclk_clock() / (hperh->init.prescaler + 1) / freq - 1; + WRITE_REG(hperh->perh->AR, _arr); + hperh->init.period = _arr; +} + +/** + * @brief Set the PWM duty. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @param duty: PWM duty to set [0, 100] + * @retval None + */ +void ald_timer_pwm_set_duty(ald_timer_handle_t *hperh, ald_timer_channel_t ch, uint16_t duty) +{ + uint32_t tmp = (hperh->init.period + 1) * duty / 100; + + if (ch == ALD_TIMER_CHANNEL_1) + WRITE_REG(hperh->perh->CCVAL1, tmp); + else if (ch == ALD_TIMER_CHANNEL_2) + WRITE_REG(hperh->perh->CCVAL2, tmp); + else if (ch == ALD_TIMER_CHANNEL_3) + WRITE_REG(hperh->perh->CCVAL3, tmp); + else if (ch == ALD_TIMER_CHANNEL_4) + WRITE_REG(hperh->perh->CCVAL4, tmp); + else; +} + +/** + * @brief Set capture the PWM. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be captured the PWM + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_pwm_set_input(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_PWM_INPUT_INSTANCE(hperh->perh, ch)); + + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, ALD_TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, ALD_TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, ALD_TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, ALD_TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, ALD_TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, ALD_TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + break; + + case ALD_TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, ALD_TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, ALD_TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, ALD_TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, ALD_TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, ALD_TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, ALD_TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + break; + + default: + break; + } + + SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); + SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2EN_MSK); + + return; +} +/** + * @}TIMER_Public_Functions_Group3 + */ + +/** @defgroup TIMER_Public_Functions_Group4 TIMER Input Capture functions + * @brief Time Input Capture functions + * + * @verbatim + ============================================================================== + ##### Time Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER Input Capture. + (+) Start the Time Input Capture. + (+) Stop the Time Input Capture. + (+) Start the Time Input Capture and enable interrupt. + (+) Stop the Time Input Capture and disable interrupt. + (+) Start the Time Input Capture and enable DMA transfer. + (+) Stop the Time Input Capture and disable DMA transfer. + + * @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Input Capture Time base according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_ic_init(ald_timer_handle_t *hperh) +{ + return ald_timer_base_init(hperh); +} + +/** + * @brief Starts the TIMER Input Capture measurement. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_ic_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + ALD_TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Input Capture measurement. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_ic_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + ALD_TIMER_DISABLE(hperh); + return; +} + +/** + * @brief Starts the TIMER Input Capture measurement in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_ic_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, ENABLE); + break; + + case ALD_TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, ENABLE); + break; + + case ALD_TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC3, ENABLE); + break; + + case ALD_TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC4, ENABLE); + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + ALD_TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Input Capture measurement in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_ic_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, DISABLE); + break; + + case ALD_TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, DISABLE); + break; + + case ALD_TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC3, DISABLE); + break; + + case ALD_TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC4, DISABLE); + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + ALD_TIMER_DISABLE(hperh); + return; +} + +/** + * @brief Starts the TIMER Input Capture measurement in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @param buf: The destination Buffer address. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_ic_start_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch, + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + if ((hperh->state == ALD_TIMER_STATE_BUSY)) + return ALD_BUSY; + + if ((hperh->state == ALD_TIMER_STATE_READY)) + { + if (((uint32_t)buf == 0) || (len == 0)) + return ALD_ERROR; + } + + hperh->state = ALD_TIMER_STATE_BUSY; + + if (hperh->perh == NULL) + hperh->hdma1.perh = DMA; + + hperh->hdma1.cplt_tc_cbk = timer_dma_capture_cplt; + hperh->hdma1.cplt_tc_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.dst = (void *)buf; + hperh->hdma1.config.size = len; + hperh->hdma1.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdma1.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdma1.config.circle_mode = ENABLE; + hperh->hdma1.config.channel = dma_ch; + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_1; + break; + + case ALD_TIMER_CHANNEL_2: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC2, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_2; + break; + + case ALD_TIMER_CHANNEL_3: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL3; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC3, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_3; + break; + + case ALD_TIMER_CHANNEL_4: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL4; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH4; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC4, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_4; + break; + + default: + break; + } + + ald_dma_interrupt_config(dma_ch, ALD_DMA_IT_FLAG_TC, ENABLE); + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + ALD_TIMER_ENABLE(hperh); + return ALD_OK; +} + +/** + * @brief Stops the TIMER Input Capture measurement in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_ic_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, DISABLE); + break; + + case ALD_TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC2, DISABLE); + break; + + case ALD_TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC3, DISABLE); + break; + + case ALD_TIMER_CHANNEL_4: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC4, DISABLE); + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + ALD_TIMER_DISABLE(hperh); + hperh->state = ALD_TIMER_STATE_READY; + return; +} + +/** + * @}TIMER_Public_Functions_Group4 + */ + +/** @defgroup TIMER_Public_Functions_Group5 TIMER One Pulse functions + * @brief Time One Pulse functions + * + * @verbatim + ============================================================================== + ##### Time One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER One Pulse. + (+) Start the Time One Pulse. + (+) Stop the Time One Pulse. + (+) Start the Time One Pulse and enable interrupt. + (+) Stop the Time One Pulse and disable interrupt. + (+) Start the Time One Pulse and enable DMA transfer. + (+) Stop the Time One Pulse and disable DMA transfer. + + * @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER One Pulse Time Base according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER handle + * @param mode: Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIMER_OP_MODE_SINGLE: Only one pulse will be generated. + * @arg TIMER_OP_MODE_REPEAT: Repetitive pulses wil be generated. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_one_pulse_init(ald_timer_handle_t *hperh, ald_timer_op_mode_t mode) +{ + if (hperh == NULL) + return ALD_ERROR; + + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + assert_param(IS_TIMER_OP_MODE(mode)); + + if (hperh->state == ALD_TIMER_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = ALD_TIMER_STATE_BUSY; + timer_base_set_config(hperh->perh, &hperh->init); + MODIFY_REG(hperh->perh->CON1, TIMER_CON1_SPMEN_MSK, mode << TIMER_CON1_SPMEN_POS); + hperh->state = ALD_TIMER_STATE_READY; + + return ALD_OK; +} + +/** + * @brief Starts the TIMER One Pulse signal generation. + * @param hperh: TIMER One Pulse handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_start(ald_timer_handle_t *hperh, ald_timer_op_output_channel_t ch) +{ + /* Enable the Capture compare and the Input Capture channels + * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) + * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and + * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output + * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together + */ + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + ALD_TIMER_MOE_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER One Pulse signal generation. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_stop(ald_timer_handle_t *hperh, ald_timer_op_output_channel_t ch) +{ + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + ALD_TIMER_MOE_DISABLE(hperh); + + ALD_TIMER_DISABLE(hperh); + return; +} + +/** + * @brief Starts the TIMER One Pulse signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_start_by_it(ald_timer_handle_t *hperh, ald_timer_op_output_channel_t ch) +{ + /* Enable the Capture compare and the Input Capture channels + * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) + * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and + * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output + * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together + */ + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, ENABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + ALD_TIMER_MOE_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER One Pulse signal generation in interrupt mode. + * @param hperh : TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_stop_by_it(ald_timer_handle_t *hperh, ald_timer_op_output_channel_t ch) +{ + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, DISABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, DISABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + ALD_TIMER_MOE_DISABLE(hperh); + + ALD_TIMER_DISABLE(hperh); + return; +} +/** + * @}TIMER_Public_Functions_Group5 + */ + +/** @defgroup TIMER_Public_Functions_Group6 TIMER Encoder functions + * @brief TIMER Encoder functions + * + * @verbatim + ============================================================================== + ##### Time Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER Encoder. + (+) Start the Time Encoder. + (+) Stop the Time Encoder. + (+) Start the Time Encoder and enable interrupt. + (+) Stop the Time Encoder and disable interrupt. + (+) Start the Time Encoder and enable DMA transfer. + (+) Stop the Time Encoder and disable DMA transfer. + + * @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Encoder Interface and create the associated handle. + * @param hperh: TIMER handle + * @param config: TIMER Encoder Interface configuration structure + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_encoder_init(ald_timer_handle_t *hperh, ald_timer_encoder_init_t *config) +{ + if (hperh == NULL) + return ALD_ERROR; + + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_ENCODER_MODE(config->mode)); + assert_param(IS_TIMER_IC_POLARITY(config->ic1_polarity)); + assert_param(IS_TIMER_IC_POLARITY(config->ic2_polarity)); + assert_param(IS_TIMER_IC_SELECT(config->ic1_sel)); + assert_param(IS_TIMER_IC_SELECT(config->ic2_sel)); + assert_param(IS_TIMER_IC_PSC(config->ic1_psc)); + assert_param(IS_TIMER_IC_PSC(config->ic2_psc)); + assert_param(IS_TIMER_IC_FILTER(config->ic1_filter)); + assert_param(IS_TIMER_IC_FILTER(config->ic2_filter)); + + if (hperh->state == ALD_TIMER_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = ALD_TIMER_STATE_BUSY; + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + timer_base_set_config(hperh->perh, &hperh->init); + + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, config->ic1_sel << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, config->ic2_sel << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->ic1_psc << TIMER_CHMR1_IC1PRES_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->ic2_psc << TIMER_CHMR1_IC2PRES_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->ic1_filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I2FLT_MSK, config->ic2_filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, (config->ic1_polarity & 0x1) << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((config->ic1_polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, (config->ic2_polarity & 0x1) << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((config->ic2_polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS); + + hperh->state = ALD_TIMER_STATE_READY; + return ALD_OK; +} + +/** + * @brief Starts the TIMER Encoder Interface. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void ald_timer_encoder_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + break; + + case ALD_TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, ENABLE); + break; + + default: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, ENABLE); + break; + } + + ALD_TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Encoder Interface. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void ald_timer_encoder_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + break; + + case ALD_TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, DISABLE); + break; + + default: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, DISABLE); + break; + } + + ALD_TIMER_DISABLE(hperh); + return; +} + +/** + * @brief Starts the TIMER Encoder Interface in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void ald_timer_encoder_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, ENABLE); + break; + + case ALD_TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, ENABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, ENABLE); + break; + + default: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, ENABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, ENABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, ENABLE); + break; + } + + ALD_TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Encoder Interface in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void ald_timer_encoder_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, DISABLE); + break; + + case ALD_TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, DISABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, DISABLE); + break; + + default: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, DISABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, DISABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, DISABLE); + break; + } + + ALD_TIMER_DISABLE(hperh); + hperh->state = ALD_TIMER_STATE_READY; + return; +} + +/** + * @brief Starts the TIMER Encoder Interface in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @param buf1: The destination Buffer address. Reading data from CCR1. + * @param buf2: The destination Buffer address. Reading data from CCR2. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch1: Channel of DMA. + * @param dma_ch2: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_encoder_start_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch, + uint16_t *buf1, uint16_t *buf2, uint32_t len, + uint8_t dma_ch1, uint8_t dma_ch2) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + if ((hperh->state == ALD_TIMER_STATE_BUSY)) + return ALD_BUSY; + + if ((hperh->state == ALD_TIMER_STATE_READY)) + { + if (((uint32_t)buf1 == 0) || ((uint32_t)buf2 == 0) || (len == 0)) + return ALD_ERROR; + } + + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA; + + if (hperh->hdma2.perh == NULL) + hperh->hdma2.perh = DMA; + + hperh->state = ALD_TIMER_STATE_BUSY; + hperh->hdma1.cplt_tc_cbk = timer_dma_capture_cplt; + hperh->hdma1.cplt_tc_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.size = len; + hperh->hdma1.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdma1.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.dst = (void *)buf1; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH1; + hperh->hdma1.config.channel = dma_ch1; + ald_dma_config_basic(&hperh->hdma1); + ald_dma_interrupt_config(dma_ch1, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + ALD_TIMER_ENABLE(hperh); + break; + + case ALD_TIMER_CHANNEL_2: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.dst = (void *)buf2; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH2; + hperh->hdma1.config.channel = dma_ch2; + ald_dma_config_basic(&hperh->hdma1); + ald_dma_interrupt_config(dma_ch2, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC2, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, ENABLE); + ALD_TIMER_ENABLE(hperh); + break; + + default: + hperh->hdma2.cplt_tc_cbk = timer_dma_capture_cplt; + hperh->hdma2.cplt_tc_arg = (void *)hperh; + memcpy(&hperh->hdma2.config, &hperh->hdma1.config, sizeof(ald_dma_config_t)); + + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.dst = (void *)buf1; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH1; + hperh->hdma1.config.channel = dma_ch1; + ald_dma_config_basic(&hperh->hdma1); + ald_dma_interrupt_config(dma_ch1, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, ENABLE); + + hperh->hdma2.config.src = (void *)&hperh->perh->CCVAL2; + hperh->hdma2.config.dst = (void *)buf2; + hperh->hdma2.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH2; + hperh->hdma2.config.channel = dma_ch2; + ald_dma_config_basic(&hperh->hdma2); + ald_dma_interrupt_config(dma_ch2, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC2, ENABLE); + + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, ENABLE); + ALD_TIMER_ENABLE(hperh); + break; + } + + return ALD_OK; +} + +/** + * @brief Stops the TIMER Encoder Interface in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void ald_timer_encoder_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, DISABLE); + break; + + case ALD_TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, DISABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC2, DISABLE); + break; + + default: + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_2, DISABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, DISABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC2, DISABLE); + break; + } + + ALD_TIMER_DISABLE(hperh); + hperh->state = ALD_TIMER_STATE_READY; + return; +} + +/** + * @}TIMER_Public_Functions_Group6 + */ + +/** @defgroup TIMER_Public_Functions_Group7 TIMER Hall Sensor functions + * @brief TIMER Hall Sensor functions + * + * @verbatim + ============================================================================== + ##### Time Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER hall sensor. + (+) Start the hall sensor. + (+) Stop the hall sensor. + (+) Start the hall sensor and enable interrupt. + (+) Stop the hall sensor and disable interrupt. + (+) Start the hall sensor and enable DMA transfer. + (+) Stop the hal sensor and disable DMA transfer. + + * @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Encoder Interface and create the associated handle. + * @param hperh: TIMER handle + * @param config: TIMER Encoder Interface configuration structure + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_hall_sensor_init(ald_timer_handle_t *hperh, ald_timer_hall_sensor_init_t *config) +{ + ald_timer_oc_init_t oc; + + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + if (hperh->state == ALD_TIMER_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = ALD_TIMER_STATE_READY; + timer_base_set_config(hperh->perh, &hperh->init); + timer_ti1_set_config(hperh->perh, config->polarity, ALD_TIMER_IC_SEL_TRC, config->filter); + + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); + SET_BIT(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + + oc.oc_mode = ALD_TIMER_OC_MODE_PWM2; + oc.pulse = config->delay; + oc.oc_polarity = ALD_TIMER_OC_POLARITY_HIGH; + oc.ocn_polarity = ALD_TIMER_OCN_POLARITY_HIGH; + oc.oc_fast_en = DISABLE; + oc.oc_idle = ALD_TIMER_OC_IDLE_RESET; + oc.ocn_idle = ALD_TIMER_OCN_IDLE_RESET; + timer_oc2_set_config(hperh->perh, &oc); + + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_TRGO_OC2REF << TIMER_SMCON_SMODS_POSS); + return ALD_OK; +} +/** + * @brief Starts the TIMER hall sensor interface. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_hall_sensor_start(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + ALD_TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER hall sensor interface. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_hall_sensor_stop(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + ALD_TIMER_DISABLE(hperh); + + return; +} + +/** + * @brief Starts the TIMER hall sensor interface in interrupt mode. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_hall_sensor_start_by_it(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + ALD_TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER hall sensor interface in interrupt mode. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_hall_sensor_stop_by_it(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, DISABLE); + ALD_TIMER_DISABLE(hperh); + + return; +} + +/** + * @brief Starts the TIMER hall sensor interface in DMA mode. + * @param hperh: TIMER handle + * @param buf: The destination Buffer address. Reading data from CCR1. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_hall_sensor_start_by_dma(ald_timer_handle_t *hperh, + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + if ((hperh->state == ALD_TIMER_STATE_BUSY)) + return ALD_BUSY; + + if ((hperh->state == ALD_TIMER_STATE_READY)) + { + if (((uint32_t)buf == 0) || (len == 0)) + return ALD_ERROR; + } + + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA; + + hperh->state = ALD_TIMER_STATE_BUSY; + hperh->hdma1.cplt_tc_cbk = timer_dma_capture_cplt; + hperh->hdma1.cplt_tc_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.size = len; + hperh->hdma1.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdma1.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.dst = (void *)buf; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH1; + hperh->hdma1.config.channel = dma_ch; + ald_dma_config_basic(&hperh->hdma1); + ald_dma_interrupt_config(dma_ch, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, ENABLE); + ALD_TIMER_ENABLE(hperh); + + return ALD_OK; +} +/** + * @brief Stops the TIMER hall sensor interface in DMA mode. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_hall_sensor_stop_by_dma(ald_timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, ALD_TIMER_CHANNEL_1, DISABLE); + ALD_TIMER_DISABLE(hperh); + + return; +} + +/** + * @}TIMER_Public_Functions_Group7 + */ + +/** @defgroup TIMER_Public_Functions_Group8 TIMER complementary output compare functions + * @brief TIMER complementary output compare functions + * + * @verbatim + ============================================================================== + ##### Time complementary output compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary output compare. + (+) Stop the Time complementary output compare. + (+) Start the Time complementary output compare and enable interrupt. + (+) Stop the Time complementary output compare and disable interrupt. + (+) Start the Time complementary output compare and enable DMA transfer. + (+) Stop the Time complementary output compare and disable DMA transfer. + + * @endverbatim + * @{ + */ + +/** + * @brief Starts the TIMER output compare signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_ocn_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); + ALD_TIMER_MOE_ENABLE(hperh); + ALD_TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER output compare signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_ocn_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + ALD_TIMER_MOE_DISABLE(hperh); + ALD_TIMER_DISABLE(hperh); + + return; +} + +/** + * @brief Starts the TIMER output compare signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_ocn_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, ENABLE); + break; + + case ALD_TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, ENABLE); + break; + + case ALD_TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC3, ENABLE); + break; + + default: + break; + } + + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_BREAK, ENABLE); + timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); + ALD_TIMER_MOE_ENABLE(hperh); + ALD_TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER output compare signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_ocn_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC1, DISABLE); + break; + + case ALD_TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC2, DISABLE); + break; + + case ALD_TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_CC3, DISABLE); + break; + + default: + break; + } + + if ((!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1NE_MSK))) + && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2NE_MSK))) + && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC3NE_MSK)))) + { + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_BREAK, DISABLE); + } + + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + ALD_TIMER_MOE_DISABLE(hperh); + ALD_TIMER_DISABLE(hperh); + + return; +} + +/** + * @brief Starts the TIMER output compare signal generation on the complementary output. + * in DMA mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @param buf: The destination Buffer address. Reading data from CCRx. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch: Channel of DMA. + * @retval None + */ +ald_status_t ald_timer_ocn_start_by_dma(ald_timer_handle_t *hperh, + ald_timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + if ((hperh->state == ALD_TIMER_STATE_BUSY)) + return ALD_BUSY; + + if ((hperh->state == ALD_TIMER_STATE_READY)) + { + if (((uint32_t)buf == 0) || (len == 0)) + return ALD_ERROR; + } + + hperh->state = ALD_TIMER_STATE_BUSY; + + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA; + + hperh->hdma1.cplt_tc_cbk = timer_dma_oc_cplt; + hperh->hdma1.cplt_tc_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.src = (void *)buf; + hperh->hdma1.config.size = len; + hperh->hdma1.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdma1.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdma1.config.channel = dma_ch; + hperh->hdma1.config.msel = ALD_DMA_MSEL_AD16C4T; + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_1; + break; + + case ALD_TIMER_CHANNEL_2: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC2, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_2; + break; + + case ALD_TIMER_CHANNEL_3: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL3; + hperh->hdma1.config.msigsel = ALD_DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC3, ENABLE); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_3; + break; + + default: + break; + } + + ald_dma_interrupt_config(dma_ch, ALD_DMA_IT_FLAG_TC, ENABLE); + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + ALD_TIMER_MOE_ENABLE(hperh); + ALD_TIMER_ENABLE(hperh); + + return ALD_OK; +} + +/** + * @brief Starts the TIMER output compare signal generation on the complementary output. + * in DMA mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_ocn_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC1, DISABLE); + break; + + case ALD_TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC2, DISABLE); + break; + + case ALD_TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_CC3, DISABLE); + break; + + default: + break; + } + + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + ALD_TIMER_MOE_DISABLE(hperh); + ALD_TIMER_DISABLE(hperh); + + return; +} + +/** + * @}TIMER_Public_Functions_Group8 + */ + +/** @defgroup TIMER_Public_Functions_Group9 TIMER complementary PWM functions + * @brief TIMER complementary PWM functions + * + * @verbatim + ============================================================================== + ##### Time complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary PWM. + (+) Stop the Time complementary PWM. + (+) Start the Time complementary PWM and enable interrupt. + (+) Stop the Time complementary PWM and disable interrupt. + (+) Start the Time complementary PWM and enable DMA transfer. + (+) Stop the Time complementary PWM and disable DMA transfer. + + * @endverbatim + * @{ + */ + +/** + * @brief Starts the TIMER PWM signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_pwmn_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_ocn_start(hperh, ch); +} + +/** + * @brief Stops the TIMER PWM signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_pwmn_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_ocn_stop(hperh, ch); +} + +/** + * @brief Starts the TIMER PWM signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_pwmn_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_ocn_start_by_it(hperh, ch); +} + +/** + * @brief Stops the TIMER PWM signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_pwmn_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_ocn_stop_by_it(hperh, ch); +} + +/** + * @brief Starts the TIMER PWM signal generation on the complementary output. + * in DMA mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @param buf: The destination Buffer address. Reading data from CCRx. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch: Channel of DMA. + * @retval None + */ +ald_status_t ald_timer_pwmn_start_by_dma(ald_timer_handle_t *hperh, + ald_timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + return ald_timer_ocn_start_by_dma(hperh, ch, buf, len, dma_ch); +} + +/** + * @brief Starts the TIMER PWM signal generation on the complementary output. + * in DMA mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_pwmn_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_ocn_stop_by_dma(hperh, ch); +} + +/** + * @}TIMER_Public_Functions_Group9 + */ + +/** @defgroup TIMER_Public_Functions_Group10 TIMER complementary one pulse functions + * @brief TIMER complementary one pulse functions + * + * @verbatim + ============================================================================== + ##### Time complementary one pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary one pulse. + (+) Stop the Time complementary one pulse. + (+) Start the Time complementary one pulse and enable interrupt. + (+) Stop the Time complementary one pulse and disable interrupt. + + * @endverbatim + * @{ + */ + +/** + * @brief Starts the TIMER one pulse signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_n_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_ocn_start(hperh, ch); +} + +/** + * @brief Stops the TIMER one pulse signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_n_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_ocn_stop(hperh, ch); +} + +/** + * @brief Starts the TIMER one pulse signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_n_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_ocn_start_by_it(hperh, ch); +} + +/** + * @brief Stops the TIMER one pulse signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_n_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + ald_timer_ocn_stop_by_it(hperh, ch); +} +/** + * @}TIMER_Public_Functions_Group10 + */ + +/** @defgroup TIMER_Public_Functions_Group11 TIMER Peripheral Control functions + * @brief Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead timere. + (+) Configure Master and the Slave synchronization. + (+) Handle TIMER interrupt. + (+) Get TIMER compare register's vale. + (+) Configure TIMER interrupt ENABLE/DISABLE. + (+) Get TIMER interrupt source status. + (+) Get TIMER interrupt flag status. + (+) Clear TIMER interrupt flag. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Output Compare Channels according to the specified + * parameters in the timer_oc_init_t. + * @param hperh: TIMER handle + * @param config: TIMER Output Compare configuration structure + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_oc_config_channel(ald_timer_handle_t *hperh, ald_timer_oc_init_t *config, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_OC_MODE(config->oc_mode)); + assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity)); + + __LOCK(hperh); + hperh->state = ALD_TIMER_STATE_BUSY; + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + timer_oc1_set_config(hperh->perh, config); + break; + + case ALD_TIMER_CHANNEL_2: + timer_oc2_set_config(hperh->perh, config); + break; + + case ALD_TIMER_CHANNEL_3: + timer_oc3_set_config(hperh->perh, config); + break; + + case ALD_TIMER_CHANNEL_4: + timer_oc4_set_config(hperh->perh, config); + break; + + default: + break; + } + + hperh->state = ALD_TIMER_STATE_READY; + __UNLOCK(hperh); + return ALD_OK; +} + +/** + * @brief Initializes the TIMER Input Capture Channels according to the specified + * parameters in the timer_ic_init_t. + * @param hperh: TIMER handle + * @param config: TIMER Input Capture configuration structure + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_ic_config_channel(ald_timer_handle_t *hperh, ald_timer_ic_init_t *config, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_SELECT(config->sel)); + assert_param(IS_TIMER_IC_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = ALD_TIMER_STATE_BUSY; + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); + break; + + case ALD_TIMER_CHANNEL_2: + timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->psc << TIMER_CHMR1_IC2PRES_POSS); + break; + + case ALD_TIMER_CHANNEL_3: + timer_ti3_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC3PRES_MSK, config->psc << TIMER_CHMR2_IC3PRES_POSS); + break; + + case ALD_TIMER_CHANNEL_4: + timer_ti4_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC4PRES_MSK, config->psc << TIMER_CHMR2_IC4PRES_POSS); + break; + + default: + break; + } + + hperh->state = ALD_TIMER_STATE_READY; + __UNLOCK(hperh); + return ALD_OK; +} + +/** + * @brief Initializes the TIMER One Pulse Channels according to the specified + * parameters in the timer_one_pulse_init_t. + * @param hperh: TIMER handle + * @param config: TIMER One Pulse configuration structure + * @param ch_out: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @param ch_in: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_one_pulse_config_channel(ald_timer_handle_t *hperh, ald_timer_one_pulse_init_t *config, + ald_timer_channel_t ch_out, ald_timer_channel_t ch_in) +{ + ald_timer_oc_init_t tmp; + + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_OC_MODE(config->mode)); + assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity)); + assert_param(IS_TIMER_OCN_POLARITY(config->ocn_polarity)); + assert_param(IS_TIMER_OCIDLE_STATE(config->oc_idle)); + assert_param(IS_TIMER_OCNIDLE_STATE(config->ocn_idle)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_SELECT(config->sel)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + if (ch_out == ch_in) + return ALD_ERROR; + + __LOCK(hperh); + hperh->state = ALD_TIMER_STATE_BUSY; + + tmp.oc_mode = config->mode; + tmp.pulse = config->pulse; + tmp.oc_polarity = config->oc_polarity; + tmp.ocn_polarity = config->ocn_polarity; + tmp.oc_idle = config->oc_idle; + tmp.ocn_idle = config->ocn_idle; + + switch (ch_out) + { + case ALD_TIMER_CHANNEL_1: + timer_oc1_set_config(hperh->perh, &tmp); + break; + + case ALD_TIMER_CHANNEL_2: + timer_oc2_set_config(hperh->perh, &tmp); + break; + + default: + break; + } + + switch (ch_in) + { + case ALD_TIMER_CHANNEL_1: + timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); + CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); + break; + + case ALD_TIMER_CHANNEL_2: + timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); + CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); + break; + + default: + break; + } + + hperh->state = ALD_TIMER_STATE_READY; + __UNLOCK(hperh); + return ALD_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param hperh: TIMER handle + * @param config: pointer to a TIMER_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIMER peripheral. + * @param ch: specifies the TIMER Channel + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 + * @arg TIMER_CHANNEL_2: TIMER Channel 2 + * @arg TIMER_CHANNEL_3: TIMER Channel 3 + * @arg TIMER_CHANNEL_4: TIMER Channel 4 + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_config_oc_ref_clear(ald_timer_handle_t *hperh, ald_timer_clear_input_config_t *config, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->state)); + assert_param(IS_TIMER_CLEAR_INPUT_SOURCE(config->source)); + assert_param(IS_TIMER_CLEAR_INPUT_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_CHNREF_CLEAR(config->clrsel)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + if (config->source == ALD_TIMER_INPUT_NONE) + { + timer_etr_set_config(hperh->perh, ALD_TIMER_ETR_PSC_DIV1, ALD_TIMER_CLK_POLARITY_NO_INV, 0); + } + else + { + timer_etr_set_config(hperh->perh, config->psc, + (ald_timer_clock_polarity_t)config->polarity, config->filter); + } + + if (config->clrsel == ALD_TIMER_CHNREF_CLR_CMP_IN) + { + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_OCCS_MSK); + } + else + { + SET_BIT(hperh->perh->SMCON, TIMER_SMCON_OCCS_MSK); + } + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OCLREN_MSK, config->state << TIMER_CHMR1_CH1OCLREN_POS); + break; + + case ALD_TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OCLREN_MSK, config->state << TIMER_CHMR1_CH2OCLREN_POS); + break; + + case ALD_TIMER_CHANNEL_3: + assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OCLREN_MSK, config->state << TIMER_CHMR2_CH3OCLREN_POS); + break; + + case ALD_TIMER_CHANNEL_4: + assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OCLREN_MSK, config->state << TIMER_CHMR2_CH4OCLREN_POS); + break; + + default: + break; + } + + return ALD_OK; +} + +/** + * @brief Configures the clock source to be used + * @param hperh: TIMER handle + * @param config: pointer to a timer_clock_config_t structure that + * contains the clock source information for the TIMER peripheral. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_config_clock_source(ald_timer_handle_t *hperh, ald_timer_clock_config_t *config) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_CLOCK_SOURCE(config->source)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = ALD_TIMER_STATE_BUSY; + WRITE_REG(hperh->perh->SMCON, 0x0); + + switch (config->source) + { + case ALD_TIMER_SRC_INTER: + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + break; + + case ALD_TIMER_SRC_ETRMODE1: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_ETRF << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case ALD_TIMER_SRC_ETRMODE2: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + SET_BIT(hperh->perh->SMCON, TIMER_SMCON_ECM2EN_MSK); + break; + + case ALD_TIMER_SRC_TI1: + timer_ti1_set_config_stage(hperh->perh, (ald_timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case ALD_TIMER_SRC_TI2: + timer_ti2_set_config_stage(hperh->perh, (ald_timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case ALD_TIMER_SRC_TI1ED: + timer_ti1_set_config_stage(hperh->perh, (ald_timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case ALD_TIMER_SRC_ITR0: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_ITR0 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case ALD_TIMER_SRC_ITR1: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_ITR1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case ALD_TIMER_SRC_ITR2: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_ITR2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case ALD_TIMER_SRC_ITR3: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ALD_TIMER_TS_ITR3 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, ALD_TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + default: + break; + } + + hperh->state = ALD_TIMER_STATE_READY; + __UNLOCK(hperh); + return ALD_OK; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param hperh: TIMER handle. + * @param ti1_select: Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg 0: The TIMERx_CH1 pin is connected to TI1 input + * @arg 1: The TIMERx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_config_ti1_input(ald_timer_handle_t *hperh, uint32_t ti1_select) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK, ti1_select << TIMER_CON2_I1FSEL_POS); + return ALD_OK; +} + +/** + * @brief Configures the TIMER in Slave mode + * @param hperh: TIMER handle. + * @param config: pointer to a timer_slave_config_t structure that + * contains the selected trigger (internal trigger input, filtered + * timerer input or external trigger input) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_slave_config_sync(ald_timer_handle_t *hperh, ald_timer_slave_config_t *config) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_SLAVE_MODE(config->mode)); + assert_param(IS_TIMER_TS(config->input)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = ALD_TIMER_STATE_BUSY; + + timer_slave_set_config(hperh, config); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_TRIGGER, DISABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_TRIGGER, DISABLE); + + hperh->state = ALD_TIMER_STATE_READY; + __UNLOCK(hperh); + return ALD_OK; +} + +/** + * @brief Configures the TIMER in Slave mode in interrupt mode + * @param hperh: TIMER handle. + * @param config: pointer to a timer_slave_config_t structure that + * contains the selected trigger (internal trigger input, filtered + * timerer input or external trigger input) and the ) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_slave_config_sync_by_it(ald_timer_handle_t *hperh, ald_timer_slave_config_t *config) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_SLAVE_MODE(config->mode)); + assert_param(IS_TIMER_TS(config->input)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = ALD_TIMER_STATE_BUSY; + + timer_slave_set_config(hperh, config); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_TRIGGER, ENABLE); + ald_timer_dma_req_config(hperh, ALD_TIMER_DMA_TRIGGER, DISABLE); + + hperh->state = ALD_TIMER_STATE_READY; + __UNLOCK(hperh); + return ALD_OK; +} + +/** + * @brief Generate a software event + * @param hperh: TIMER handle + * @param event: specifies the event source. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_generate_event(ald_timer_handle_t *hperh, ald_timer_event_source_t event) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_EVENT_SOURCE(event)); + + __LOCK(hperh); + hperh->state = ALD_TIMER_STATE_BUSY; + WRITE_REG(hperh->perh->SGE, event); + hperh->state = ALD_TIMER_STATE_READY; + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param hperh: TIMER handle. + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1 : TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2 : TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3 : TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4 : TIMER Channel 4 selected + * @retval Captured value + */ +uint32_t ald_timer_read_capture_value(ald_timer_handle_t *hperh, ald_timer_channel_t ch) +{ + uint32_t tmp; + + __LOCK(hperh); + hperh->state = ALD_TIMER_STATE_BUSY; + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + tmp = hperh->perh->CCVAL1; + break; + + case ALD_TIMER_CHANNEL_2: + tmp = hperh->perh->CCVAL2; + break; + + case ALD_TIMER_CHANNEL_3: + tmp = hperh->perh->CCVAL3; + break; + + case ALD_TIMER_CHANNEL_4: + tmp = hperh->perh->CCVAL4; + break; + + default: + tmp = hperh->perh->CCVAL1; + break; + } + + hperh->state = ALD_TIMER_STATE_READY; + __UNLOCK(hperh); + return tmp; +} + +/** + * @brief Sets TIMER output mode. + * @param hperh: TIMER handle. + * @param mode: TIMER output mode. + * @param ch: TIMER Channels. + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1 : TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2 : TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3 : TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4 : TIMER Channel 4 selected + * @retval None + */ +void ald_timer_set_output_mode(ald_timer_handle_t *hperh, ald_timer_oc_mode_t mode, ald_timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_OC_MODE(mode)); + assert_param(IS_TIMER_CHANNELS(ch)); + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, mode << TIMER_CHMR1_CH1OMOD_POSS); + break; + + case ALD_TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, mode << TIMER_CHMR1_CH2OMOD_POSS); + break; + + case ALD_TIMER_CHANNEL_3: + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, mode << TIMER_CHMR2_CH3OMOD_POSS); + break; + + case ALD_TIMER_CHANNEL_4: + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, mode << TIMER_CHMR2_CH4OMOD_POSS); + break; + + default: + break; + } + + return; +} + +/** + * @brief Configure the channel in commutation event. + * @param hperh: TIMER handel + * @param config: Parameters of the channel. + * @retval None + */ +void ald_timer_com_change_config(ald_timer_handle_t *hperh, ald_timer_com_channel_config_t *config) +{ + uint32_t cm1, cm2, cce; + + assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->ch[0].en)); + assert_param(IS_FUNC_STATE(config->ch[0].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[0].mode)); + assert_param(IS_FUNC_STATE(config->ch[1].en)); + assert_param(IS_FUNC_STATE(config->ch[1].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[1].mode)); + assert_param(IS_FUNC_STATE(config->ch[2].en)); + assert_param(IS_FUNC_STATE(config->ch[2].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[2].mode)); + + ALD_TIMER_MOE_DISABLE(hperh); + ALD_TIMER_DISABLE(hperh); + + cm1 = hperh->perh->CHMR1; + cm2 = hperh->perh->CHMR2; + cce = hperh->perh->CCEP; + + MODIFY_REG(cm1, (0x7 << 4), (config->ch[0].mode << 4)); + MODIFY_REG(cm1, (0x7 << 12), (config->ch[1].mode << 12)); + MODIFY_REG(cm2, (0x7 << 4), (config->ch[2].mode << 4)); + MODIFY_REG(cce, (0x1 << 0), (config->ch[0].en << 0)); + MODIFY_REG(cce, (0x1 << 2), (config->ch[0].n_en << 2)); + MODIFY_REG(cce, (0x1 << 4), (config->ch[1].en << 4)); + MODIFY_REG(cce, (0x1 << 6), (config->ch[1].n_en << 6)); + MODIFY_REG(cce, (0x1 << 8), (config->ch[2].en << 8)); + MODIFY_REG(cce, (0x1 << 10), (config->ch[2].n_en << 10)); + + WRITE_REG(hperh->perh->CHMR1, cm1); + WRITE_REG(hperh->perh->CHMR2, cm2); + WRITE_REG(hperh->perh->CCEP, cce); + + ALD_TIMER_MOE_ENABLE(hperh); + ALD_TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Configure the TIMER commutation event sequence. + * @param hperh: TIMER handel + * @param ts: the internal trigger corresponding to the timerer interfacing + * with the hall sensor. + * This parameter can be one of the following values: + * @arg TIMER_TS_ITR0 + * @arg TIMER_TS_ITR1 + * @arg TIMER_TS_ITR2 + * @arg TIMER_TS_ITR3 + * @param trgi: the commutation event source. + * This parameter can be one of the following values: + * @arg ENABLE: Commutation event source is TRGI + * @arg DISABLE: Commutation event source is set by software using the COMG bit + * @retval None + */ +void ald_timer_com_event_config(ald_timer_handle_t *hperh, ald_timer_ts_t ts, type_func_t trgi) +{ + assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_TS(ts)); + assert_param(IS_FUNC_STATE(trgi)); + + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ts << TIMER_SMCON_TSSEL_POSS); + SET_BIT(hperh->perh->CON2, TIMER_CON2_CCPCEN_MSK); + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_CCUSEL_MSK, trgi << TIMER_CON2_CCUSEL_POS); + + return; +} + +/** + * @brief Configure the TIMER commutation event sequence with interrupt. + * @param hperh: TIMER handel + * @param ts: the internal trigger corresponding to the timerer interfacing + * with the hall sensor. + * This parameter can be one of the following values: + * @arg TIMER_TS_ITR0 + * @arg TIMER_TS_ITR1 + * @arg TIMER_TS_ITR2 + * @arg TIMER_TS_ITR3 + * @param trgi: the commutation event source. + * This parameter can be one of the following values: + * @arg ENABLE: Commutation event source is TRGI + * @arg DISABLE: Commutation event source is set by software using the COMG bit + * @retval None + */ +void ald_timer_com_event_config_it(ald_timer_handle_t *hperh, ald_timer_ts_t ts, type_func_t trgi) +{ + ald_timer_com_event_config(hperh, ts, trgi); + ald_timer_interrupt_config(hperh, ALD_TIMER_IT_COM, ENABLE); +} + +/** + * @brief Configure the break, dead timere, lock level state. + * @param hperh: TIMER handle + * @param config: Pointer to the timer_break_dead_timere_t structure. + * @retval None + */ +void ald_timer_break_dead_time_config(ald_timer_handle_t *hperh, ald_timer_break_dead_time_t *config) +{ + uint32_t tmp; + + assert_param(IS_TIMER_BREAK_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->off_run)); + assert_param(IS_FUNC_STATE(config->off_idle)); + assert_param(IS_TIMER_CLOCK_LEVEL(config->lock_level)); + assert_param(IS_TIMER_DEAD_TIMERE(config->dead_time)); + assert_param(IS_FUNC_STATE(config->break_state)); + assert_param(IS_TIMER_BREAK_POLARITY(config->polarity)); + assert_param(IS_FUNC_STATE(config->auto_out)); + + tmp = READ_REG(hperh->perh->BDCFG); + MODIFY_REG(tmp, TIMER_BDCFG_OFFSSR_MSK, config->off_run << TIMER_BDCFG_OFFSSR_POS); + MODIFY_REG(tmp, TIMER_BDCFG_OFFSSI_MSK, config->off_idle << TIMER_BDCFG_OFFSSI_POS); + MODIFY_REG(tmp, TIMER_BDCFG_LOCKLVL_MSK, config->lock_level << TIMER_BDCFG_LOCKLVL_POSS); + MODIFY_REG(tmp, TIMER_BDCFG_DT_MSK, config->dead_time << TIMER_BDCFG_DT_POSS); + MODIFY_REG(tmp, TIMER_BDCFG_BRKEN_MSK, config->break_state << TIMER_BDCFG_BRKEN_POS); + MODIFY_REG(tmp, TIMER_BDCFG_BRKP_MSK, config->polarity << TIMER_BDCFG_BRKP_POS); + MODIFY_REG(tmp, TIMER_BDCFG_AOEN_MSK, config->auto_out << TIMER_BDCFG_AOEN_POS); + WRITE_REG(hperh->perh->BDCFG, tmp); + + hperh->state = ALD_TIMER_STATE_READY; + return; +} + +/** + * @brief Configure the master mode + * @param hperh: TIMER handle + * @param config: Pointer to the timer_master_config_t structure. + * @retval None + */ +void ald_timer_master_sync_config(ald_timer_handle_t *hperh, ald_timer_master_config_t *config) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_MASTER_MODE_SEL(config->sel)); + assert_param(IS_FUNC_STATE(config->master_en)); + + hperh->state = ALD_TIMER_STATE_BUSY; + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_TRGOSEL_MSK, config->sel << TIMER_CON2_TRGOSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_MSCFG_MSK, config->master_en << TIMER_SMCON_MSCFG_POS); + hperh->state = ALD_TIMER_STATE_READY; + + return; +} + +/** + * @brief This function handles TIMER interrupts requests. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_irq_handler(ald_timer_handle_t *hperh) +{ + uint32_t reg = hperh->perh->IFM; + + /* Capture or compare 1 event */ + if (READ_BIT(reg, ALD_TIMER_FLAG_CC1)) + { + ald_timer_clear_flag_status(hperh, ALD_TIMER_FLAG_CC1); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK)) + { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else /* Output compare event */ + { + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_CLEARED; + } + + /* Capture or compare 2 event */ + if (READ_BIT(reg, ALD_TIMER_FLAG_CC2)) + { + ald_timer_clear_flag_status(hperh, ALD_TIMER_FLAG_CC2); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_2; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK)) + { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else /* Output compare event */ + { + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_CLEARED; + } + + /* Capture or compare 3 event */ + if (READ_BIT(reg, ALD_TIMER_FLAG_CC3)) + { + ald_timer_clear_flag_status(hperh, ALD_TIMER_FLAG_CC3); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_3; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC3SSEL_MSK)) + { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else /* Output compare event */ + { + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_CLEARED; + } + + /* Capture or compare 4 event */ + if (READ_BIT(reg, ALD_TIMER_FLAG_CC4)) + { + ald_timer_clear_flag_status(hperh, ALD_TIMER_FLAG_CC4); + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_4; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC4SSEL_MSK)) + { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else /* Output compare event */ + { + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_CLEARED; + } + + /* TIMER Update event */ + if (READ_BIT(reg, ALD_TIMER_FLAG_UPDATE)) + { + ald_timer_clear_flag_status(hperh, ALD_TIMER_FLAG_UPDATE); + + if (hperh->period_elapse_cbk) + hperh->period_elapse_cbk(hperh); + } + + /* TIMER Break input event */ + if (READ_BIT(reg, ALD_TIMER_FLAG_BREAK)) + { + ald_timer_clear_flag_status(hperh, ALD_TIMER_FLAG_BREAK); + + if (hperh->break_cbk) + hperh->break_cbk(hperh); + } + + /* TIMER Trigger detection event */ + if (READ_BIT(reg, ALD_TIMER_FLAG_TRIGGER)) + { + ald_timer_clear_flag_status(hperh, ALD_TIMER_FLAG_TRIGGER); + + if (hperh->trigger_cbk) + hperh->trigger_cbk(hperh); + } + + /* TIMER commutation event */ + if (READ_BIT(reg, ALD_TIMER_FLAG_COM)) + { + ald_timer_clear_flag_status(hperh, ALD_TIMER_FLAG_COM); + + if (hperh->com_cbk) + hperh->com_cbk(hperh); + } + + return; +} + +/** + * @brief Configure DMA request source. + * @param hperh: TIMER handle + * @param req: DMA request source. + * @param state: New state of the specified DMA request. + * @retval None + */ +void ald_timer_dma_req_config(ald_timer_handle_t *hperh, ald_timer_dma_req_t req, type_func_t state) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT(hperh->perh->DMAEN, req); + else + CLEAR_BIT(hperh->perh->DMAEN, req); + + return; +} + +/** + * @brief Enable/disable the specified TIMER interrupts. + * @param hperh: Pointer to a timer_handle_t structure. + * @param it: Specifies the timer interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref timer_it_t. + * @param state: New state of the specified TIMER interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_timer_interrupt_config(ald_timer_handle_t *hperh, ald_timer_it_t it, type_func_t state) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT(hperh->perh->IER, it); + else + SET_BIT(hperh->perh->IDR, it); + + return; +} + +/** + * @brief Get the status of TIMER interrupt source. + * @param hperh: Pointer to a timer_handle_t structure. + * @param it: Specifies the TIMER interrupt source. + * This parameter can be one of the @ref timer_it_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_timer_get_it_status(ald_timer_handle_t *hperh, ald_timer_it_t it) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IT(it)); + + if (hperh->perh->IVS & it) + return SET; + + return RESET; +} + +/** + * @brief Get the status of TIMER interrupt flag. + * @param hperh: Pointer to a timer_handle_t structure. + * @param flag: Specifies the TIMER interrupt flag. + * This parameter can be one of the @ref timer_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_timer_get_flag_status(ald_timer_handle_t *hperh, ald_timer_flag_t flag) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_FLAG(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + +/** + * @brief Clear the TIMER interrupt flag. + * @param hperh: Pointer to a timer_handle_t structure. + * @param flag: Specifies the TIMER interrupt flag. + * This parameter can be one of the @ref timer_flag_t. + * @retval None + */ +void ald_timer_clear_flag_status(ald_timer_handle_t *hperh, ald_timer_flag_t flag) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_FLAG(flag)); + + hperh->perh->ICR = flag; + return; +} +/** + * @}TIMER_Public_Functions_Group11 + */ + +/** @defgroup TIMER_Public_Functions_Group12 TIMER Peripheral State functions + * @brief Peripheral State functions + * + * @verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permit to get in run-timere the status of the peripheral + and the data flow. + + @endverbatim + * @{ + */ + +/** + * @brief Return the TIMER Base state + * @param hperh: TIMER handle + * @retval TIMER peripheral state + */ +ald_timer_state_t ald_timer_get_state(ald_timer_handle_t *hperh) +{ + return hperh->state; +} +/** + * @}TIMER_Public_Functions_Group12 + */ +/** + * @}TIMER_Public_Functions + */ + +/** @addtogroup TIMER_Private_Functions + * @{ + */ + +/** + * @brief TIMER DMA out compare complete callback. + * @param arg: pointer to TIMER handle. + * @retval None + */ +void timer_dma_oc_cplt(void *arg) +{ + ald_timer_handle_t *hperh = (ald_timer_handle_t *)arg; + + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_CLEARED; + return; +} + +/** + * @brief TIMER DMA Capture complete callback. + * @param arg: pointer to TIMER handle. + * @retval None + */ +void timer_dma_capture_cplt(void *arg) +{ + ald_timer_handle_t *hperh = (ald_timer_handle_t *)arg; + + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + + hperh->ch = ALD_TIMER_ACTIVE_CHANNEL_CLEARED; + return; +} + +/** + * @brief TIMER DMA Period Elapse complete callback. + * @param arg: pointer to TIMER handle. + * @retval None + */ +void timer_dma_period_elapse_cplt(void *arg) +{ + ald_timer_handle_t *hperh = (ald_timer_handle_t *)arg; + + if (hperh->period_elapse_cbk) + hperh->period_elapse_cbk(hperh); + + hperh->state = ALD_TIMER_STATE_READY; + return; +} + +/** + * @brief Time Base configuration + * @param TIMERx: TIMER periheral + * @param init: TIMER Base configuration structure + * @retval None + */ +static void timer_base_set_config(TIMER_TypeDef *TIMERx, ald_timer_base_init_t *init) +{ + assert_param(IS_TIMER_COUNTER_MODE(init->mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(init->clk_div)); + + if (init->mode == ALD_TIMER_CNT_MODE_UP || init->mode == ALD_TIMER_CNT_MODE_DOWN) + { + CLEAR_BIT(TIMERx->CON1, TIMER_CON1_CMSEL_MSK); + MODIFY_REG(TIMERx->CON1, TIMER_CON1_DIRSEL_MSK, init->mode << TIMER_CON1_DIRSEL_POS); + } + else + { + MODIFY_REG(TIMERx->CON1, TIMER_CON1_CMSEL_MSK, (init->mode - 1) << TIMER_CON1_CMSEL_POSS); + } + + if (IS_TIMER_CLOCK_DIVISION_INSTANCE(TIMERx)) + MODIFY_REG(TIMERx->CON1, TIMER_CON1_DFCKSEL_MSK, init->clk_div << TIMER_CON1_DFCKSEL_POSS); + + WRITE_REG(TIMERx->AR, init->period); + WRITE_REG(TIMERx->PRES, init->prescaler); + + if (IS_TIMER_REPETITION_COUNTER_INSTANCE(TIMERx)) + WRITE_REG(TIMERx->REPAR, init->re_cnt); + + return; +} + +/** + * @brief Time Ouput Compare 1 configuration + * @param TIMERx: Select the TIMER peripheral + * @param oc_config: The ouput configuration structure + * @retval None + */ +static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, ald_timer_oc_init_t *oc_config) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH1OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC1POL_POS); + + if (IS_TIMER_CCXN_INSTANCE(TIMERx, ALD_TIMER_CHANNEL_1)) + { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC1NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1NE_MSK); + } + + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) + { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1_MSK, oc_config->oc_idle << TIMER_CON2_OISS1_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS1N_POS); + } + + WRITE_REG(TIMERx->CCVAL1, oc_config->pulse); +} + +/** + * @brief Time Ouput Compare 2 configuration + * @param TIMERx: Select the TIMER peripheral + * @param oc_config: The ouput configuration structure + * @retval None + */ +static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, ald_timer_oc_init_t *oc_config) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH2OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC2POL_POS); + + if (IS_TIMER_CCXN_INSTANCE(TIMERx, ALD_TIMER_CHANNEL_2)) + { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC2NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2NE_MSK); + } + + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) + { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2_MSK, oc_config->oc_idle << TIMER_CON2_OISS2_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS2N_POS); + } + + WRITE_REG(TIMERx->CCVAL2, oc_config->pulse); +} + +/** + * @brief Time Ouput Compare 3 configuration + * @param TIMERx: Select the TIMER peripheral + * @param oc_config: The ouput configuration structure + * @retval None + */ +static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, ald_timer_oc_init_t *oc_config) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH3OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC3POL_POS); + + if (IS_TIMER_CCXN_INSTANCE(TIMERx, ALD_TIMER_CHANNEL_3)) + { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC3NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3NE_MSK); + } + + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) + { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3_MSK, oc_config->oc_idle << TIMER_CON2_OISS3_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS3N_POS); + } + + WRITE_REG(TIMERx->CCVAL3, oc_config->pulse); +} + +/** + * @brief Time Ouput Compare 4 configuration + * @param TIMERx: Select the TIMER peripheral + * @param oc_config: The ouput configuration structure + * @retval None + */ +static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, ald_timer_oc_init_t *oc_config) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH4OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC4POL_POS); + + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) + { + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS4_MSK, oc_config->oc_idle << TIMER_CON2_OISS4_POS); + } + + WRITE_REG(TIMERx->CCVAL4, oc_config->pulse); +} + +/** + * @brief Enables or disables the TIMER Capture Compare Channel x. + * @param TIMERx: Select the TIMER peripheral + * @param ch: specifies the TIMER Channel + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 + * @arg TIMER_CHANNEL_2: TIMER Channel 2 + * @arg TIMER_CHANNEL_3: TIMER Channel 3 + * @arg TIMER_CHANNEL_4: TIMER Channel 4 + * @param state: specifies the TIMER Channel CCxE bit new state. + * @retval None + */ +static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, ald_timer_channel_t ch, type_func_t state) +{ + assert_param(IS_TIMER_CC2_INSTANCE(TIMERx)); + assert_param(IS_TIMER_CHANNELS(ch)); + + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, state << TIMER_CCEP_CC1EN_POS); + break; + + case ALD_TIMER_CHANNEL_2: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, state << TIMER_CCEP_CC2EN_POS); + break; + + case ALD_TIMER_CHANNEL_3: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, state << TIMER_CCEP_CC3EN_POS); + break; + + case ALD_TIMER_CHANNEL_4: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, state << TIMER_CCEP_CC4EN_POS); + break; + + default: + break; + } +} +/** + * @brief Enables or disables the TIMER Capture Compare Channel xN. + * @param TIMERx: Select the TIMER peripheral + * @param ch: specifies the TIMER Channel + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 + * @arg TIMER_CHANNEL_2: TIMER Channel 2 + * @arg TIMER_CHANNEL_3: TIMER Channel 3 + * @param state: specifies the TIMER Channel CCxNE bit new state. + * @retval None + */ +static void timer_ccxn_channel_cmd(TIMER_TypeDef *TIMERx, ald_timer_channel_t ch, type_func_t state) +{ + switch (ch) + { + case ALD_TIMER_CHANNEL_1: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NE_MSK, state << TIMER_CCEP_CC1NE_POS); + break; + + case ALD_TIMER_CHANNEL_2: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NE_MSK, state << TIMER_CCEP_CC2NE_POS); + break; + + case ALD_TIMER_CHANNEL_3: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NE_MSK, state << TIMER_CCEP_CC3NE_POS); + break; + + default: + break; + } + +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param sel: specifies the input to be used. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, + ald_timer_ic_select_t sel, uint32_t filter) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, sel << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); + + return; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, uint32_t filter) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); + + return; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param sel: specifies the input to be used. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, + ald_timer_ic_select_t sel, uint32_t filter) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, sel << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); + + return; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, uint32_t filter) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); + return; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param sel: specifies the input to be used. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, + ald_timer_ic_select_t sel, uint32_t filter) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK, sel << TIMER_CHMR2_CC3SSEL_POSS); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I3FLT_MSK, filter << TIMER_CHMR2_I3FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, polarity << TIMER_CCEP_CC3POL_POS); + + return; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param sel: specifies the input to be used. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, ald_timer_ic_polarity_t polarity, + ald_timer_ic_select_t sel, uint32_t filter) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK, sel << TIMER_CHMR2_CC4SSEL_POSS); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I4FLT_MSK, filter << TIMER_CHMR2_I4FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, polarity << TIMER_CCEP_CC4POL_POS); + return; +} + +/** + * @brief Configures the TIMERx External Trigger (ETR). + * @param TIMERx: Select the TIMER peripheral + * @param psc: The external Trigger Prescaler. + * @param polarity: The external Trigger Polarity. + * @param filter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +static void timer_etr_set_config(TIMER_TypeDef *TIMERx, ald_timer_etr_psc_t psc, ald_timer_clock_polarity_t polarity, uint32_t filter) +{ + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETFLT_MSK, filter << TIMER_SMCON_ETFLT_POSS); + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPSEL_MSK, psc << TIMER_SMCON_ETPSEL_POSS); + CLEAR_BIT(TIMERx->SMCON, TIMER_SMCON_ECM2EN_MSK); + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPOL_MSK, polarity << TIMER_SMCON_ETPOL_POS); + return; +} + +/** + * @brief Time Slave configuration + * @param hperh: pointer to a timer_handle_t structure that contains + * the configuration information for TIMER module. + * @param config: The slave configuration structure + * @retval None + */ +static void timer_slave_set_config(ald_timer_handle_t *hperh, ald_timer_slave_config_t *config) +{ + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, config->input << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS); + + switch (config->input) + { + case ALD_TIMER_TS_ETRF: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + break; + + case ALD_TIMER_TS_TI1F_ED: + CLEAR_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->filter << TIMER_CHMR1_I1FLT_POSS); + break; + + case ALD_TIMER_TS_TI1FP1: + timer_ti1_set_config_stage(hperh->perh, (ald_timer_ic_polarity_t)config->polarity, config->filter); + break; + + case ALD_TIMER_TS_TI2FP2: + timer_ti2_set_config_stage(hperh->perh, (ald_timer_ic_polarity_t)config->polarity, config->filter); + break; + + default: + break; + } +} + +/** + * @brief Timer DMA msel signal configuration + * @param hperh: pointer to a timer_handle_t structure that contains + * the configuration information for TIMER module. + * @param config: DMA configuration structure + * @retval None + */ +static void timer_dma_msel(TIMER_TypeDef *hperh, ald_dma_config_t *config) +{ + if (hperh == AD16C4T) + config->msel = ALD_DMA_MSEL_AD16C4T; + + if (hperh == BS16T) + config->msel = ALD_DMA_MSEL_BS16T; + + if (hperh == GP16C4T0) + config->msel = ALD_DMA_MSEL_GP16C4T0; + + if (hperh == GP16C4T1) + config->msel = ALD_DMA_MSEL_GP16C4T1; + + if (hperh == GP16C4T2) + config->msel = ALD_DMA_MSEL_GP16C4T2; +} + +/** + * @}TIMER_Private_Functions + */ +/** + * @}TIMER + */ +/** + * @}ES32VF2264_ALD + */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_timer.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_timer.h new file mode 100644 index 0000000000..1a98ecc802 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_timer.h @@ -0,0 +1,1172 @@ +/** + ********************************************************************************* + * + * @file ald_timer.h + * @brief TIMER module driver. + * This is the common part of the TIMER initialization + * + * @version V1.0 + * @date 03 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 03 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_TIMER_H__ +#define __ALD_TIMER_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_utils.h" +#include "ald_cmu.h" +#include "ald_dma.h" + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Constants -------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup TIMER + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup TIMER_Public_Types TIMER Public Types + * @{ + */ + +/** + * @brief TIMER counter mode + */ +typedef enum +{ + ALD_TIMER_CNT_MODE_UP = 0U, /**< Counter mode up */ + ALD_TIMER_CNT_MODE_DOWN = 1U, /**< Counter mode down */ + ALD_TIMER_CNT_MODE_CENTER1 = 2U, /**< Counter mode center1 */ + ALD_TIMER_CNT_MODE_CENTER2 = 3U, /**< Counter mode center2 */ + ALD_TIMER_CNT_MODE_CENTER3 = 4U, /**< Counter mode center3 */ +} ald_timer_cnt_mode_t; + +/** + * @brief TIMER clock division + */ +typedef enum +{ + ALD_TIMER_CLOCK_DIV1 = 0U, /**< No prescaler is used */ + ALD_TIMER_CLOCK_DIV2 = 1U, /** Clock is divided by 2 */ + ALD_TIMER_CLOCK_DIV4 = 2U, /** Clock is divided by 4 */ +} ald_timer_clock_division_t; + +/** + * @brief TIMER output compare and PWM modes + */ +typedef enum +{ + ALD_TIMER_OC_MODE_TIMERING = 0U, /**< Output compare mode is timering */ + ALD_TIMER_OC_MODE_ACTIVE = 1U, /**< Output compare mode is active */ + ALD_TIMER_OC_MODE_INACTIVE = 2U, /**< Output compare mode is inactive */ + ALD_TIMER_OC_MODE_TOGGLE = 3U, /**< Output compare mode is toggle */ + ALD_TIMER_OC_MODE_FORCE_INACTIVE = 4U, /**< Output compare mode is force inactive */ + ALD_TIMER_OC_MODE_FORCE_ACTIVE = 5U, /**< Output compare mode is force active */ + ALD_TIMER_OC_MODE_PWM1 = 6U, /**< Output compare mode is pwm1 */ + ALD_TIMER_OC_MODE_PWM2 = 7U, /**< Output compare mode is pwm2 */ +} ald_timer_oc_mode_t; + +/** + * @brief TIMER output compare polarity + */ +typedef enum +{ + ALD_TIMER_OC_POLARITY_HIGH = 0U, /**< Output compare polarity is high */ + ALD_TIMER_OC_POLARITY_LOW = 1U, /**< Output compare polarity is low */ +} ald_timer_oc_polarity_t; + +/** + * @brief TIMER complementary output compare polarity + */ +typedef enum +{ + ALD_TIMER_OCN_POLARITY_HIGH = 0U, /**< Complementary output compare polarity is high */ + ALD_TIMER_OCN_POLARITY_LOW = 1U, /**< Complementary output compare polarity is low */ +} ald_timer_ocn_polarity_t; + +/** + * @brief TIMER output compare idle state + */ +typedef enum +{ + ALD_TIMER_OC_IDLE_RESET = 0U, /**< Output compare idle state is reset */ + ALD_TIMER_OC_IDLE_SET = 1U, /**< Output compare idle state is set */ +} ald_timer_oc_idle_t; + +/** + * @brief TIMER complementary output compare idle state + */ +typedef enum +{ + ALD_TIMER_OCN_IDLE_RESET = 0U, /**< Complementary output compare idle state is reset */ + ALD_TIMER_OCN_IDLE_SET = 1U, /**< Complementary output compare idle state is set */ +} ald_timer_ocn_idle_t; + +/** + * @brief TIMER channel + */ +typedef enum +{ + ALD_TIMER_CHANNEL_1 = 0U, /**< Channel 1 */ + ALD_TIMER_CHANNEL_2 = 1U, /**< Channel 2 */ + ALD_TIMER_CHANNEL_3 = 2U, /**< Channel 3 */ + ALD_TIMER_CHANNEL_4 = 3U, /**< Channel 4 */ + ALD_TIMER_CHANNEL_ALL = 0xFU, /**< All channel */ +} ald_timer_channel_t; + +/** + * @brief TIMER one pulse mode + */ +typedef enum +{ + ALD_TIMER_OP_MODE_REPEAT = 0U, /**< Repetitive */ + ALD_TIMER_OP_MODE_SINGLE = 1U, /**< single */ +} ald_timer_op_mode_t; + +/** + * @brief TIMER one pulse output channel + */ +typedef enum +{ + ALD_TIMER_OP_OUTPUT_CHANNEL_1 = 0U, /**< One pulse output channal 1 */ + ALD_TIMER_OP_OUTPUT_CHANNEL_2 = 1U, /**< One pulse output channal 2 */ +} ald_timer_op_output_channel_t; + +/** + * @brief TIMER time base configuration structure definition + */ +typedef struct +{ + uint32_t prescaler; /**< Specifies the prescaler value used to divide the TIMER clock. */ + ald_timer_cnt_mode_t mode; /**< Specifies the counter mode. */ + uint32_t period; /**< Specifies the period value to be loaded into ARR at the next update event. */ + ald_timer_clock_division_t clk_div; /**< Specifies the clock division.*/ + uint32_t re_cnt; /**< Specifies the repetition counter value. */ +} ald_timer_base_init_t; + +/** + * @brief TIMER output compare configuration structure definition + */ +typedef struct +{ + ald_timer_oc_mode_t oc_mode; /**< Specifies the TIMER mode. */ + uint32_t pulse; /**< Specifies the pulse value to be loaded into the Capture Compare Register. */ + ald_timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity. */ + ald_timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity. */ + type_func_t oc_fast_en; /**< Specifies the Fast mode state. */ + ald_timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ + ald_timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ +} ald_timer_oc_init_t; + +/** + * @brief State structures definition + */ +typedef enum +{ + ALD_TIMER_STATE_RESET = 0x00U, /**< Peripheral not yet initialized or disabled */ + ALD_TIMER_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + ALD_TIMER_STATE_BUSY = 0x02U, /**< An internal process is ongoing */ + ALD_TIMER_STATE_TIMEREOUT = 0x03U, /**< Timeout state */ + ALD_TIMER_STATE_ERROR = 0x04U, /**< Reception process is ongoing */ +} ald_timer_state_t; + +/** + * @brief Active channel structures definition + */ +typedef enum +{ + ALD_TIMER_ACTIVE_CHANNEL_1 = 0x01U, /**< The active channel is 1 */ + ALD_TIMER_ACTIVE_CHANNEL_2 = 0x02U, /**< The active channel is 2 */ + ALD_TIMER_ACTIVE_CHANNEL_3 = 0x04U, /**< The active channel is 3 */ + ALD_TIMER_ACTIVE_CHANNEL_4 = 0x08U, /**< The active channel is 4 */ + ALD_TIMER_ACTIVE_CHANNEL_CLEARED = 0x00U, /**< All active channels cleared */ +} ald_timer_active_channel_t; + +/** + * @brief TIMER time base handle structure definition + */ +typedef struct ald_timer_handle_s +{ + TIMER_TypeDef *perh; /**< Register base address */ + ald_timer_base_init_t init; /**< TIMER Time Base required parameters */ + ald_timer_active_channel_t ch; /**< Active channel */ + lock_state_t lock; /**< Locking object */ + ald_timer_state_t state; /**< TIMER operation state */ + + ald_dma_handle_t hdma1; /**< Timer DMA handle parameters */ + ald_dma_handle_t hdma2; + + void (*period_elapse_cbk)(struct ald_timer_handle_s *arg); /**< Period elapse callback */ + void (*delay_elapse_cbk)(struct ald_timer_handle_s *arg); /**< Delay_elapse callback */ + void (*capture_cbk)(struct ald_timer_handle_s *arg); /**< Capture callback */ + void (*pwm_pulse_finish_cbk)(struct ald_timer_handle_s *arg); /**< PWM_pulse_finish callback */ + void (*trigger_cbk)(struct ald_timer_handle_s *arg); /**< Trigger callback */ + void (*break_cbk)(struct ald_timer_handle_s *arg); /**< Break callback */ + void (*com_cbk)(struct ald_timer_handle_s *arg); /**< commutation callback */ + void (*error_cbk)(struct ald_timer_handle_s *arg); /**< Error callback */ +} ald_timer_handle_t; + + +/** + * @brief TIMER encoder mode + */ +typedef enum +{ + ALD_TIMER_ENC_MODE_TI1 = 1U, /**< encoder mode 1 */ + ALD_TIMER_ENC_MODE_TI2 = 2U, /**< encoder mode 2 */ + ALD_TIMER_ENC_MODE_TI12 = 3U, /**< encoder mode 3 */ +} ald_timer_encoder_mode_t; + +/** + * @brief TIMER input capture polarity + */ +typedef enum +{ + ALD_TIMER_IC_POLARITY_RISE = 0U, /**< Input capture polarity rising */ + ALD_TIMER_IC_POLARITY_FALL = 1U, /**< Input capture polarity falling */ +} ald_timer_ic_polarity_t; + +/** + *@brief TIMER input capture selection + */ +typedef enum +{ + ALD_TIMER_IC_SEL_DIRECT = 1U, /**< IC1 -- TI1 */ + ALD_TIMER_IC_SEL_INDIRECT = 2U, /**< IC1 -- TI2 */ + ALD_TIMER_IC_SEL_TRC = 3U, /**< IC1 -- TRC */ +} ald_timer_ic_select_t; + +/** + * @brief TIMER input capture prescaler + */ +typedef enum +{ + ALD_TIMER_IC_PSC_DIV1 = 0U, /**< Capture performed once every 1 events */ + ALD_TIMER_IC_PSC_DIV2 = 1U, /**< Capture performed once every 2 events */ + ALD_TIMER_IC_PSC_DIV4 = 2U, /**< Capture performed once every 4 events */ + ALD_TIMER_IC_PSC_DIV8 = 3U, /**< Capture performed once every 4 events */ +} ald_timer_ic_prescaler_t; + +/** + * @brief TIMER encoder configuration structure definition + */ +typedef struct +{ + ald_timer_encoder_mode_t mode; /**< Specifies the encoder mode */ + ald_timer_ic_polarity_t ic1_polarity; /**< Specifies the active edge of the input signal */ + ald_timer_ic_select_t ic1_sel; /**< Specifies the input */ + ald_timer_ic_prescaler_t ic1_psc; /**< Specifies the Input Capture Prescaler */ + uint32_t ic1_filter; /**< Specifies the input capture filter */ + ald_timer_ic_polarity_t ic2_polarity; /**< Specifies the active edge of the input signal */ + ald_timer_ic_select_t ic2_sel; /**< Specifies the input */ + ald_timer_ic_prescaler_t ic2_psc; /**< Specifies the Input Capture Prescaler */ + uint32_t ic2_filter; /**< Specifies the input capture filter */ +} ald_timer_encoder_init_t; + +/** + * @brief TIMER input capture configuration structure definition + */ +typedef struct +{ + ald_timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + ald_timer_ic_select_t sel; /**< Specifies the input */ + ald_timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ + uint32_t filter; /**< Specifies the input capture filter */ +} ald_timer_ic_init_t; + +/** + * @brief TIMER one pulse mode configuration structure definition + */ +typedef struct +{ + ald_timer_oc_mode_t mode; /**< Specifies the TIMER mode */ + uint16_t pulse; /**< Specifies the pulse value */ + ald_timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity */ + ald_timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity */ + ald_timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ + ald_timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ + ald_timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + ald_timer_ic_select_t sel; /**< Specifies the input */ + uint32_t filter; /**< Specifies the input capture filter */ +} ald_timer_one_pulse_init_t; + +/** @brief TIMER clear input source + */ +typedef enum +{ + ALD_TIMER_INPUT_NONE = 0U, /**< Clear input none */ + ALD_TIMER_INPUT_ETR = 1U, /**< Clear input etr */ +} ald_timer_clear_input_source_t; + +/** @brief TIMER clear input polarity + */ +typedef enum +{ + ALD_TIMER_POLARITY_NO_INV = 0U, /**< Polarity for ETRx pin */ + ALD_TIMER_POLARITY_INV = 1U, /**< Polarity for ETRx pin */ +} ald_timer_clear_input_polarity_t; + +/** @brief TIMER clear input polarity + */ +typedef enum +{ + ALD_TIMER_ETR_PSC_DIV1 = 0U, /**< No prescaler is used */ + ALD_TIMER_ETR_PSC_DIV2 = 1U, /**< ETR input source is divided by 2 */ + ALD_TIMER_ETR_PSC_DIV4 = 2U, /**< ETR input source is divided by 4 */ + ALD_TIMER_ETR_PSC_DIV8 = 3U, /**< ETR input source is divided by 8 */ +} ald_timer_etr_psc_t; + +/** @brief TIMER CHnREF Clear Select + */ +typedef enum +{ + ALD_TIMER_CHNREF_CLR_CMP_IN = 0U, /**< Comparator CMP_IN */ + ALD_TIMER_CHNREF_CLR_ETF = 1U, /**< External Trigger Signal ETF */ +} ald_timer_chnref_clr_sel_t; + +/** @brief TIMER clear input configuration handle structure definition + */ +typedef struct +{ + type_func_t state; /**< TIMER clear Input state */ + ald_timer_clear_input_source_t source; /**< TIMER clear Input sources */ + ald_timer_clear_input_polarity_t polarity; /**< TIMER Clear Input polarity */ + ald_timer_etr_psc_t psc; /**< TIMER Clear Input prescaler */ + ald_timer_chnref_clr_sel_t clrsel; /**state = TIMER_STATE_RESET) + +/** + * @brief Enable the TIMER peripheral. + */ +#define ALD_TIMER_ENABLE(hperh) (SET_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK)) + +/** + * @brief Enable the TIMER main output. + */ +#define ALD_TIMER_MOE_ENABLE(hperh) (SET_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK)) + +/** + * @brief Disable the TIMER peripheral. + */ +#define ALD_TIMER_DISABLE(hperh) \ + do { \ + if ((((hperh)->perh->CCEP & ALD_CCER_CCxE_MASK) == 0) \ + && (((hperh)->perh->CCEP & ALD_CCER_CCxNE_MASK) == 0)) \ + CLEAR_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK); \ + } while (0) + +/** + * @brief Disable the TIMER main output. + * @note The Main Output Enable of a timer instance is disabled only if + * all the CCx and CCxN channels have been disabled + */ +#define ALD_TIMER_MOE_DISABLE(hperh) \ + do { \ + if ((((hperh)->perh->CCEP & ALD_CCER_CCxE_MASK) == 0) \ + && (((hperh)->perh->CCEP & ALD_CCER_CCxNE_MASK) == 0)) \ + CLEAR_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK); \ + } while (0) + +/** + * @brief Sets the TIMER autoreload register value on runtime without calling + * another time any Init function. + */ +#define ALD_TIMER_SET_AUTORELOAD(handle, AUTORELOAD) \ + do { \ + (handle)->perh->AR = (AUTORELOAD); \ + (handle)->init.period = (AUTORELOAD); \ + } while (0) + +/** + * @brief Gets the TIMER autoreload register value on runtime + */ +#define ALD_TIMER_GET_AUTORELOAD(handle) ((handle)->perh->AR) + +/** + * @brief Gets the TIMER count register value on runtime + */ +#define ALD_TIMER_GET_CNT(handle) ((handle)->perh->COUNT) + +/** + * @brief Gets the TIMER count direction value on runtime + */ +#define ALD_TIMER_GET_DIR(handle) (READ_BITS((handle)->perh->CON1, TIMER_CON1_DIRSEL_MSK, TIMER_CON1_DIRSEL_POS)) + +/** + * @brief CCx DMA request sent when CCx event occurs + */ +#define ALD_TIMER_CCx_DMA_REQ_CCx(handle) (CLEAR_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) + +/** + * @brief CCx DMA request sent when update event occurs + */ +#define ALD_TIMER_CCx_DMA_REQ_UPDATE(handle) (SET_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) + +/** + * @brief Enable channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + * TIMER_CHANNEL_4 + */ +#define ALD_TIMER_CCx_ENABLE(handle, ch) (((ch) == ALD_TIMER_CHANNEL_4) ? \ + (SET_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4POL_MSK)) : (WRITE_REG(((handle)->perh->CCEP), (((handle)->perh->CCEP) | (1 << ((ch) << 2)))))) + +/** + * @brief Disable channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + * TIMER_CHANNEL_4 + */ +#define ALD_TIMER_CCx_DISABLE(handle, ch) (((ch) == ALD_TIMER_CHANNEL_4) ? \ + (CLEAR_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4EN_MSK)) : ((handle)->perh->CCEP &= ~(1 << ((ch) << 2)))) + +/** + * @brief Enable complementary channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + */ +#define ALD_TIMER_CCxN_ENABLE(handle, ch) ((handle)->perh->CCEP |= (1 << (((ch) << 2) + 2))) + +/** + * @brief Disable complementary channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + */ +#define ALD_TIMER_CCxN_DISABLE(handle, ch) ((handle)->perh->CCEP &= ~(1 << (((ch) << 2) + 2))) +/** + * @} + */ + +/** @defgroup TIMER_Private_Macros TIMER Private Macros + * @{ + */ + +#define IS_TIMER_INSTANCE(x) (((x) == AD16C4T) || \ + ((x) == BS16T) || \ + ((x) == GP16C4T0) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T2)) +#define IS_ADTIMER_INSTANCE(x) ((x) == AD16C4T) +#define IS_TIMER_XOR_INSTANCE(x) (((x) == AD16C4T) || \ + ((x) == GP16C4T2) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T0)) +#define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == AD16C4T) || \ + ((x) == GP16C4T2) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T0)) +#define IS_TIMER_CC2_INSTANCE(x) (((x) == AD16C4T) || \ + ((x) == GP16C4T0) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T2)) +#define IS_TIMER_CC4_INSTANCE(x) (((x) == AD16C4T) || \ + ((x) == GP16C4T0) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T2)) +#define IS_TIMER_BREAK_INSTANCE(x) ((x) == AD16C4T) +#define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == AD16C4T) && \ + (((y) == ALD_TIMER_CHANNEL_1) || \ + ((y) == ALD_TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T0) && \ + (((y) == ALD_TIMER_CHANNEL_1) || \ + ((y) == ALD_TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T1) && \ + (((y) == ALD_TIMER_CHANNEL_1) || \ + ((y) == ALD_TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T2) && \ + (((y) == ALD_TIMER_CHANNEL_1) || \ + ((y) == ALD_TIMER_CHANNEL_2)))) +#define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == AD16C4T) && \ + (((y) == ALD_TIMER_CHANNEL_1) || \ + ((y) == ALD_TIMER_CHANNEL_2) || \ + ((y) == ALD_TIMER_CHANNEL_3) || \ + ((y) == ALD_TIMER_CHANNEL_4))) || \ + (((x) == GP16C4T0) && \ + (((y) == ALD_TIMER_CHANNEL_1) || \ + ((y) == ALD_TIMER_CHANNEL_2) || \ + ((y) == ALD_TIMER_CHANNEL_3) || \ + ((y) == ALD_TIMER_CHANNEL_4))) || \ + (((x) == GP16C4T1) && \ + (((y) == ALD_TIMER_CHANNEL_1) || \ + ((y) == ALD_TIMER_CHANNEL_2) || \ + ((y) == ALD_TIMER_CHANNEL_3) || \ + ((y) == ALD_TIMER_CHANNEL_4))) || \ + (((x) == GP16C4T2) && \ + (((y) == ALD_TIMER_CHANNEL_1) || \ + ((y) == ALD_TIMER_CHANNEL_2) || \ + ((y) == ALD_TIMER_CHANNEL_3) || \ + ((y) == ALD_TIMER_CHANNEL_4)))) +#define IS_TIMER_CCXN_INSTANCE(x, y) (((x) == AD16C4T) && \ + (((y) == ALD_TIMER_CHANNEL_1) || \ + ((y) == ALD_TIMER_CHANNEL_2) || \ + ((y) == ALD_TIMER_CHANNEL_3) || \ + ((y) == ALD_TIMER_CHANNEL_4))) +#define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) ((x) == AD16C4T) +#define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) + +#define IS_TIMER_COUNTER_MODE(x) (((x) == ALD_TIMER_CNT_MODE_UP) || \ + ((x) == ALD_TIMER_CNT_MODE_DOWN) || \ + ((x) == ALD_TIMER_CNT_MODE_CENTER1) || \ + ((x) == ALD_TIMER_CNT_MODE_CENTER2) || \ + ((x) == ALD_TIMER_CNT_MODE_CENTER3)) +#define IS_TIMER_CLOCK_DIVISION(x) (((x) == ALD_TIMER_CLOCK_DIV1) || \ + ((x) == ALD_TIMER_CLOCK_DIV2) || \ + ((x) == ALD_TIMER_CLOCK_DIV4)) +#define IS_TIMER_PWM_MODE(x) (((x) == ALD_TIMER_OC_MODE_PWM1) || \ + ((x) == ALD_TIMER_OC_MODE_PWM2)) +#define IS_TIMER_OC_MODE(x) (((x) == ALD_TIMER_OC_MODE_TIMERING) || \ + ((x) == ALD_TIMER_OC_MODE_ACTIVE) || \ + ((x) == ALD_TIMER_OC_MODE_INACTIVE) || \ + ((x) == ALD_TIMER_OC_MODE_TOGGLE) || \ + ((x) == ALD_TIMER_OC_MODE_FORCE_ACTIVE) || \ + ((x) == ALD_TIMER_OC_MODE_FORCE_INACTIVE) || \ + ((x) == ALD_TIMER_OC_MODE_PWM1) || \ + ((x) == ALD_TIMER_OC_MODE_PWM2)) +#define IS_TIMER_OC_POLARITY(x) (((x) == ALD_TIMER_OC_POLARITY_HIGH) || \ + ((x) == ALD_TIMER_OC_POLARITY_LOW)) +#define IS_TIMER_OCN_POLARITY(x) (((x) == ALD_TIMER_OCN_POLARITY_HIGH) || \ + ((x) == ALD_TIMER_OCN_POLARITY_LOW)) +#define IS_TIMER_OCIDLE_STATE(x) (((x) == ALD_TIMER_OC_IDLE_RESET) || \ + ((x) == ALD_TIMER_OC_IDLE_SET)) +#define IS_TIMER_OCNIDLE_STATE(x) (((x) == ALD_TIMER_OCN_IDLE_RESET) || \ + ((x) == ALD_TIMER_OCN_IDLE_SET)) +#define IS_TIMER_CHANNELS(x) (((x) == ALD_TIMER_CHANNEL_1) || \ + ((x) == ALD_TIMER_CHANNEL_2) || \ + ((x) == ALD_TIMER_CHANNEL_3) || \ + ((x) == ALD_TIMER_CHANNEL_4) || \ + ((x) == ALD_TIMER_CHANNEL_ALL)) +#define IS_TIMER_OP_MODE(x) (((x) == ALD_TIMER_OP_MODE_REPEAT) || \ + ((x) == ALD_TIMER_OP_MODE_SINGLE)) +#define IS_TIMER_OP_OUTPUT_CH(x) (((x) == ALD_TIMER_OP_OUTPUT_CHANNEL_1) || \ + ((x) == ALD_TIMER_OP_OUTPUT_CHANNEL_2)) +#define IS_TIMER_ENCODER_MODE(x) (((x) == ALD_TIMER_ENC_MODE_TI1) || \ + ((x) == ALD_TIMER_ENC_MODE_TI2) || \ + ((x) == ALD_TIMER_ENC_MODE_TI12)) +#define IS_TIMER_IC_POLARITY(x) (((x) == ALD_TIMER_IC_POLARITY_RISE) || \ + ((x) == ALD_TIMER_IC_POLARITY_FALL)) +#define IS_TIMER_IC_SELECT(x) (((x) == ALD_TIMER_IC_SEL_DIRECT) || \ + ((x) == ALD_TIMER_IC_SEL_INDIRECT) || \ + ((x) == ALD_TIMER_IC_SEL_TRC)) +#define IS_TIMER_IC_PSC(x) (((x) == ALD_TIMER_IC_PSC_DIV1) || \ + ((x) == ALD_TIMER_IC_PSC_DIV2) || \ + ((x) == ALD_TIMER_IC_PSC_DIV4) || \ + ((x) == ALD_TIMER_IC_PSC_DIV8)) +#define IS_TIMER_IC_FILTER(x) ((x) <= 0xF) +#define IS_TIMER_DEAD_TIMERE(x) ((x) <= 0xFF) +#define IS_TIMER_CLEAR_INPUT_SOURCE(x) (((x) == ALD_TIMER_INPUT_NONE) || \ + ((x) == ALD_TIMER_INPUT_ETR)) +#define IS_TIMER_CLEAR_INPUT_POLARITY(x) (((x) == ALD_TIMER_POLARITY_NO_INV) || \ + ((x) == ALD_TIMER_POLARITY_INV)) +#define IS_TIMER_ETR_PSC(x) (((x) == ALD_TIMER_ETR_PSC_DIV1) || \ + ((x) == ALD_TIMER_ETR_PSC_DIV2) || \ + ((x) == ALD_TIMER_ETR_PSC_DIV4) || \ + ((x) == ALD_TIMER_ETR_PSC_DIV8)) +#define IS_TIMER_CHNREF_CLEAR(X) (((X) == ALD_TIMER_CHNREF_CLR_CMP_IN) || \ + ((X) == ALD_TIMER_CHNREF_CLR_ETF)) +#define IS_TIMER_CLOCK_SOURCE(x) (((x) == ALD_TIMER_SRC_ETRMODE2) || \ + ((x) == ALD_TIMER_SRC_INTER) || \ + ((x) == ALD_TIMER_SRC_ITR0) || \ + ((x) == ALD_TIMER_SRC_ITR1) || \ + ((x) == ALD_TIMER_SRC_ITR2) || \ + ((x) == ALD_TIMER_SRC_ITR3) || \ + ((x) == ALD_TIMER_SRC_TI1ED) || \ + ((x) == ALD_TIMER_SRC_TI1) || \ + ((x) == ALD_TIMER_SRC_TI2) || \ + ((x) == ALD_TIMER_SRC_ETRMODE1)) +#define IS_TIMER_CLOCK_POLARITY(x) (((x) == ALD_TIMER_CLK_POLARITY_INV) || \ + ((x) == ALD_TIMER_CLK_POLARITY_NO_INV) || \ + ((x) == ALD_TIMER_CLK_POLARITY_RISE) || \ + ((x) == ALD_TIMER_CLK_POLARITY_FALL) || \ + ((x) == ALD_TIMER_CLK_POLARITY_BOTH)) +#define IS_TIMER_SLAVE_MODE(x) (((x) == ALD_TIMER_MODE_DISABLE) || \ + ((x) == ALD_TIMER_MODE_ENC1) || \ + ((x) == ALD_TIMER_MODE_ENC2) || \ + ((x) == ALD_TIMER_MODE_ENC3) || \ + ((x) == ALD_TIMER_MODE_RESET) || \ + ((x) == ALD_TIMER_MODE_GATED) || \ + ((x) == ALD_TIMER_MODE_TRIG) || \ + ((x) == ALD_TIMER_MODE_EXTERNAL1)) +#define IS_TIMER_EVENT_SOURCE(x) (((x) == ALD_TIMER_SRC_UPDATE) || \ + ((x) == ALD_TIMER_SRC_CC1) || \ + ((x) == ALD_TIMER_SRC_CC2) || \ + ((x) == ALD_TIMER_SRC_CC3) || \ + ((x) == ALD_TIMER_SRC_CC4) || \ + ((x) == ALD_TIMER_SRC_COM) || \ + ((x) == ALD_TIMER_SRC_TRIG) || \ + ((x) == ALD_TIMER_SRC_BREAK)) +#define IS_TIMER_TS(x) (((x) == ALD_TIMER_TS_ITR0) || \ + ((x) == ALD_TIMER_TS_ITR1) || \ + ((x) == ALD_TIMER_TS_ITR2) || \ + ((x) == ALD_TIMER_TS_ITR3) || \ + ((x) == ALD_TIMER_TS_TI1F_ED) || \ + ((x) == ALD_TIMER_TS_TI1FP1) || \ + ((x) == ALD_TIMER_TS_TI2FP2) || \ + ((x) == ALD_TIMER_TS_ETRF)) +#define IS_TIMER_CLOCK_LEVEL(x) (((x) == ALD_TIMER_LOCK_LEVEL_OFF) || \ + ((x) == ALD_TIMER_LOCK_LEVEL_1) || \ + ((x) == ALD_TIMER_LOCK_LEVEL_2) || \ + ((x) == ALD_TIMER_LOCK_LEVEL_3)) +#define IS_TIMER_BREAK_POLARITY(x) (((x) == ALD_TIMER_BREAK_POLARITY_LOW) || \ + ((x) == ALD_TIMER_BREAK_POLARITY_HIGH)) +#define IS_TIMER_MASTER_MODE_SEL(x) (((x) == ALD_TIMER_TRGO_RESET) || \ + ((x) == ALD_TIMER_TRGO_ENABLE) || \ + ((x) == ALD_TIMER_TRGO_UPDATE) || \ + ((x) == ALD_TIMER_TRGO_OC1) || \ + ((x) == ALD_TIMER_TRGO_OC1REF) || \ + ((x) == ALD_TIMER_TRGO_OC2REF) || \ + ((x) == ALD_TIMER_TRGO_OC3REF) || \ + ((x) == ALD_TIMER_TRGO_OC4REF)) +#define IS_TIMER_IT(x) (((x) == ALD_TIMER_IT_UPDATE) || \ + ((x) == ALD_TIMER_IT_CC1) || \ + ((x) == ALD_TIMER_IT_CC2) || \ + ((x) == ALD_TIMER_IT_CC3) || \ + ((x) == ALD_TIMER_IT_CC4) || \ + ((x) == ALD_TIMER_IT_COM) || \ + ((x) == ALD_TIMER_IT_TRIGGER) || \ + ((x) == ALD_TIMER_IT_BREAK)) +#define IS_TIMER_DMA_REQ(x) (((x) == ALD_TIMER_DMA_UPDATE) || \ + ((x) == ALD_TIMER_DMA_CC1) || \ + ((x) == ALD_TIMER_DMA_CC2) || \ + ((x) == ALD_TIMER_DMA_CC3) || \ + ((x) == ALD_TIMER_DMA_CC4) || \ + ((x) == ALD_TIMER_DMA_COM) || \ + ((x) == ALD_TIMER_DMA_TRIGGER)) +#define IS_TIMER_FLAG(x) (((x) == ALD_TIMER_FLAG_UPDATE) || \ + ((x) == ALD_TIMER_FLAG_CC1) || \ + ((x) == ALD_TIMER_FLAG_CC2) || \ + ((x) == ALD_TIMER_FLAG_CC3) || \ + ((x) == ALD_TIMER_FLAG_CC4) || \ + ((x) == ALD_TIMER_FLAG_COM) || \ + ((x) == ALD_TIMER_FLAG_TRIGGER) || \ + ((x) == ALD_TIMER_FLAG_BREAK) || \ + ((x) == ALD_TIMER_FLAG_CC1OF) || \ + ((x) == ALD_TIMER_FLAG_CC2OF) || \ + ((x) == ALD_TIMER_FLAG_CC3OF) || \ + ((x) == ALD_TIMER_FLAG_CC4OF)) +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @addtogroup TIMER_Public_Functions + * @{ + */ +/** @addtogroup TIMER_Public_Functions_Group1 + * @{ + */ +/* Time Base functions */ +ald_status_t ald_timer_base_init(ald_timer_handle_t *hperh); +void ald_timer_base_reset(ald_timer_handle_t *hperh); +void ald_timer_base_start(ald_timer_handle_t *hperh); +void ald_timer_base_stop(ald_timer_handle_t *hperh); +void ald_timer_base_start_by_it(ald_timer_handle_t *hperh); +void ald_timer_base_stop_by_it(ald_timer_handle_t *hperh); + +ald_status_t ald_timer_base_start_by_dma(ald_timer_handle_t *hperh, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_base_stop_by_dma(ald_timer_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group2 + * @{ + */ +/* Timer Output Compare functions */ +ald_status_t ald_timer_oc_init(ald_timer_handle_t *hperh); +void ald_timer_oc_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_oc_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_oc_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_oc_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +ald_status_t ald_timer_oc_start_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_oc_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group3 + * @{ + */ +/* Timer PWM functions */ +ald_status_t ald_timer_pwm_init(ald_timer_handle_t *hperh); +void ald_timer_pwm_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_pwm_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_pwm_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_pwm_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_pwm_set_freq(ald_timer_handle_t *hperh, uint32_t freq); +void ald_timer_pwm_set_duty(ald_timer_handle_t *hperh, ald_timer_channel_t ch, uint16_t duty); +void ald_timer_pwm_set_input(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +ald_status_t ald_timer_pwm_start_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_pwm_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group4 + * @{ + */ +/* Timer Input Capture functions */ +ald_status_t ald_timer_ic_init(ald_timer_handle_t *hperh); +void ald_timer_ic_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_ic_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_ic_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_ic_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +ald_status_t ald_timer_ic_start_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_ic_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group5 + * @{ + */ +/* Timer One Pulse functions */ +ald_status_t ald_timer_one_pulse_init(ald_timer_handle_t *hperh, ald_timer_op_mode_t mode); +void ald_timer_one_pulse_start(ald_timer_handle_t *hperh, ald_timer_op_output_channel_t ch); +void ald_timer_one_pulse_stop(ald_timer_handle_t *hperh, ald_timer_op_output_channel_t ch); +void ald_timer_one_pulse_start_by_it(ald_timer_handle_t *hperh, ald_timer_op_output_channel_t ch); +void ald_timer_one_pulse_stop_by_it(ald_timer_handle_t *hperh, ald_timer_op_output_channel_t ch); +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group6 + * @{ + */ +/* Timer encoder functions */ +ald_status_t ald_timer_encoder_init(ald_timer_handle_t *hperh, ald_timer_encoder_init_t *config); +void ald_timer_encoder_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_encoder_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_encoder_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_encoder_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +ald_status_t ald_timer_encoder_start_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch, + uint16_t *buf1, uint16_t *buf2, uint32_t len, + uint8_t dma_ch1, uint8_t dma_ch2); +void ald_timer_encoder_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group7 + * @{ + */ +/* Timer hall sensor functions */ +ald_status_t ald_timer_hall_sensor_init(ald_timer_handle_t *hperh, ald_timer_hall_sensor_init_t *config); +void ald_timer_hall_sensor_start(ald_timer_handle_t *hperh); +void ald_timer_hall_sensor_stop(ald_timer_handle_t *hperh); +void ald_timer_hall_sensor_start_by_it(ald_timer_handle_t *hperh); +void ald_timer_hall_sensor_stop_by_it(ald_timer_handle_t *hperh); + +ald_status_t ald_timer_hall_sensor_start_by_dma(ald_timer_handle_t *hperh, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_hall_sensor_stop_by_dma(ald_timer_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group8 + * @{ + */ +/* Timer complementary output compare functions */ +void ald_timer_ocn_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_ocn_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_ocn_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_ocn_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +ald_status_t ald_timer_ocn_start_by_dma(ald_timer_handle_t *hperh, + ald_timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_ocn_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group9 + * @{ + */ +/* Timer complementary PWM functions */ +void ald_timer_pwmn_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_pwmn_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_pwmn_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_pwmn_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +ald_status_t ald_timer_pwmn_start_by_dma(ald_timer_handle_t *hperh, + ald_timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_pwmn_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group10 + * @{ + */ +/* Timer complementary one pulse functions */ +void ald_timer_one_pulse_n_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_one_pulse_n_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_one_pulse_n_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_one_pulse_n_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group11 + * @{ + */ +/* Control functions */ +ald_status_t ald_timer_oc_config_channel(ald_timer_handle_t *hperh, ald_timer_oc_init_t *config, ald_timer_channel_t ch); +ald_status_t ald_timer_ic_config_channel(ald_timer_handle_t *hperh, ald_timer_ic_init_t *config, ald_timer_channel_t ch); +ald_status_t ald_timer_one_pulse_config_channel(ald_timer_handle_t *hperh, ald_timer_one_pulse_init_t *config, ald_timer_channel_t ch_out, ald_timer_channel_t ch_in); +ald_status_t ald_timer_config_oc_ref_clear(ald_timer_handle_t *hperh, ald_timer_clear_input_config_t *config, ald_timer_channel_t ch); +ald_status_t ald_timer_config_clock_source(ald_timer_handle_t *hperh, ald_timer_clock_config_t *config); +ald_status_t ald_timer_config_ti1_input(ald_timer_handle_t *hperh, uint32_t ti1_select); +ald_status_t ald_timer_slave_config_sync(ald_timer_handle_t *hperh, ald_timer_slave_config_t *config); +ald_status_t ald_timer_slave_config_sync_by_it(ald_timer_handle_t *hperh, ald_timer_slave_config_t *config); +ald_status_t ald_timer_generate_event(ald_timer_handle_t *hperh, ald_timer_event_source_t event); +uint32_t ald_timer_read_capture_value(ald_timer_handle_t *hperh, ald_timer_channel_t ch); +void ald_timer_set_output_mode(ald_timer_handle_t *hperh, ald_timer_oc_mode_t mode, ald_timer_channel_t ch); +void ald_timer_com_change_config(ald_timer_handle_t *hperh, ald_timer_com_channel_config_t *config); +void ald_timer_com_event_config(ald_timer_handle_t *hperh, ald_timer_ts_t ts, type_func_t trgi); +void ald_timer_com_event_config_it(ald_timer_handle_t *hperh, ald_timer_ts_t ts, type_func_t trgi); +void ald_timer_break_dead_time_config(ald_timer_handle_t *hperh, ald_timer_break_dead_time_t *config); +void ald_timer_master_sync_config(ald_timer_handle_t *hperh, ald_timer_master_config_t *config); +void ald_timer_irq_handler(ald_timer_handle_t *hperh); +void ald_timer_dma_req_config(ald_timer_handle_t *hperh, ald_timer_dma_req_t req, type_func_t state); +void ald_timer_interrupt_config(ald_timer_handle_t *hperh, ald_timer_it_t it, type_func_t state); +it_status_t ald_timer_get_it_status(ald_timer_handle_t *hperh, ald_timer_it_t it); +flag_status_t ald_timer_get_flag_status(ald_timer_handle_t *hperh, ald_timer_flag_t flag); +void ald_timer_clear_flag_status(ald_timer_handle_t *hperh, ald_timer_flag_t flag); +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group12 + * @{ + */ +/* State functions */ +ald_timer_state_t ald_timer_get_state(ald_timer_handle_t *hperh); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_TIMER_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_uart.c b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_uart.c new file mode 100644 index 0000000000..58ae0127a6 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_uart.c @@ -0,0 +1,1556 @@ +/** + ********************************************************************************* + * + * @file ald_uart.c + * @brief UART module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + * + Initialization and Configuration functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + * @version V1.0 + * @date 23 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 23 Feb. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The UART driver can be used as follows: + + (#) Declare a uart_handle_t handle structure. + + (#) Initialize the UART low level resources: + (##) Enable the UARTx interface clock. + (##) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure the UART pins (TX as alternate function pull-up, RX as alternate function Input). + (##) NVIC configuration if you need to use interrupt process (ald_uart_send_by_it() + and ald_uart_recv_by_it() APIs): + (+++) Configure the uart interrupt priority. + (+++) Enable the NVIC UART IRQ handle. + (##) DMA Configuration if you need to use DMA process (ald_uart_send_by_dma() + and ald_uart_recv_by_dma() APIs): + (+++) Select the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) in the hperh Init structure. + + (#) Initialize the UART registers by calling the ald_uart_init() API. + + [..] + Three operation modes are available within this driver: + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using ald_uart_send() + (+) Receive an amount of data in blocking mode using ald_uart_recv() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using ald_uart_send_by_it() + (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->tx_cplt_cbk() + (+) Receive an amount of data in non blocking mode using ald_uart_recv_by_it() + (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_cbk() function is executed and user can + add his own code by customization of function pointer hperh->error_cbk() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using ald_uart_send_by_dma() + (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->tx_cplt_cbk() + (+) Receive an amount of data in non blocking mode (DMA) using ald_uart_recv_by_dma() + (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_cbk() function is executed and user can + add his own code by customization of function pointer hperh->error_cbk() + (+) Pause the DMA Transfer using ald_uart_dma_pause() + (+) Resume the DMA Transfer using ald_uart_dma_resume() + (+) Stop the DMA Transfer using ald_uart_dma_stop() + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_uart.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup UART UART + * @brief UART module driver + * @{ + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @brief UART Private functions + * @{ + */ + +/** + * @brief DMA uart transmit process complete callback. + * @param arg: Pointer to a uart_handle_t structure. + * @retval None + */ +static void uart_dma_send_cplt(void *arg) +{ + ald_uart_handle_t *hperh = (ald_uart_handle_t *)arg; + hperh->tx_count = hperh->tx_size; + + ald_uart_dma_req_config(hperh, ALD_UART_DMA_REQ_TX, DISABLE); + + /* wait last byte shifted out */ + ald_uart_interrupt_config(hperh, ALD_UART_IT_TBC, ENABLE); + + return; +} + +/** + * @brief DMA uart receive process complete callback. + * @param arg: Pointer to a uart_handle_t structure. + * @retval None + */ +static void uart_dma_recv_cplt(void *arg) +{ + uint32_t stat = 0U; + + ald_uart_handle_t *hperh = (ald_uart_handle_t *)arg; + hperh->rx_count = hperh->rx_size; + + ald_uart_dma_req_config(hperh, ALD_UART_DMA_REQ_RX, DISABLE); + hperh->rx_state = ALD_UART_STATE_READY; + stat = hperh->perh->STAT; + + /* Handle parity error */ + if ((READ_BIT(stat, ALD_UART_STATUS_PERR)) != RESET) + hperh->err_code |= ALD_UART_ERROR_PE; + + /* Handle frame error */ + if ((READ_BIT(stat, ALD_UART_STATUS_FERR)) != RESET) + hperh->err_code |= ALD_UART_ERROR_FE; + + /* Handle rx overflow error */ + if ((READ_BIT(stat, ALD_UART_STATUS_RFOERR)) != RESET) + { + hperh->err_code |= ALD_UART_ERROR_ORE; + } + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + + if (hperh->err_code != ALD_UART_ERROR_NONE) + { + if (hperh->error_cbk) + hperh->error_cbk(hperh); + } + + return; +} + +/** + * @brief This function handles uart Communication Timeout. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: specifies the uart flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t uart_wait_flag(ald_uart_handle_t *hperh, ald_uart_status_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tick; + + if (timeout == 0) + return ALD_ERROR; + + tick = ald_get_tick(); + + /* Waiting for flag */ + while ((ald_uart_get_status(hperh, flag)) != status) + { + if (((ald_get_tick()) - tick) > timeout) + return ALD_TIMEOUT; + } + + return ALD_OK; +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __uart_send_by_it(ald_uart_handle_t *hperh) +{ + uint32_t cnt = 0xFFFFFFU; + + if (hperh->state != ALD_UART_STATE_BUSY_TX) + return ALD_BUSY; + + hperh->perh->TXBUF = (uint8_t)(*hperh->tx_buf++ & 0x00FF); + hperh->tx_count++; + + if (hperh->tx_count >= hperh->tx_size) + { + ald_uart_interrupt_config(hperh, ALD_UART_IT_TFEMPTY, DISABLE); + + /* Wait TX empty */ + cnt = 0xFFFFFFU; + while (!(hperh->perh->STAT & (0x1 << 16)) && (cnt--)); + + ald_uart_interrupt_config(hperh, ALD_UART_IT_TBC, ENABLE); + } + + return ALD_OK; +} + +/** + * @brief Wraps up transmission in non blocking mode. + * @param hperh: pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __uart_end_send_by_it(ald_uart_handle_t *hperh) +{ + uint32_t cnt = 0xFFFFFFU; + + ald_uart_interrupt_config(hperh, ALD_UART_IT_TBC, DISABLE); + + while ((hperh->perh->STAT & ALD_UART_STATUS_TSBUSY) && (cnt--)); + + ald_uart_clear_flag_status(hperh, ALD_UART_IF_TBC); + hperh->state = ALD_UART_STATE_READY; + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + + return ALD_OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __uart_recv_by_it(ald_uart_handle_t *hperh) +{ + uint8_t tmp = 0; + + if (hperh->rx_state != ALD_UART_STATE_BUSY_RX) + { + return ALD_BUSY; + } + + if (hperh->rx_count < hperh->rx_size) + { + *hperh->rx_buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF); + hperh->rx_count++; + } + else + { + tmp = (uint8_t)(hperh->perh->RXBUF & 0xFF); + UNUSED(tmp); + } + + if (hperh->rx_count >= hperh->rx_size) + { + ald_uart_interrupt_config(hperh, ALD_UART_IT_RFNEMPTY, DISABLE); + hperh->rx_state = ALD_UART_STATE_READY; + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + return ALD_OK; +} +/** + * @} + */ +/** @defgroup UART_Public_Functions UART Public Functions + * @{ + */ +/** @defgroup UART_Public_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * + * @verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the UARTx + and configure UARTx param. + (+) For the UARTx only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity + (++) Hardware flow control + (+) For RS485 mode, user also need configure some parameters by + ald_uart_rs485_config(): + (++) Enable/disable normal point mode + (++) Enable/disable auto-direction + (++) Enable/disable address detection invert + (++) Enable/disable address for compare + + @endverbatim + * @{ + */ + +/** + * @brief Reset UART peripheral + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified uart module. + * @retval None + */ +void ald_uart_reset(ald_uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + WRITE_REG(hperh->perh->BRR, 0x0); + WRITE_REG(hperh->perh->LCON, 0x0); + WRITE_REG(hperh->perh->MCON, 0x0); + WRITE_REG(hperh->perh->RS485, 0x0); + WRITE_REG(hperh->perh->SCARD, 0x0); + WRITE_REG(hperh->perh->LIN, 0x0); + WRITE_REG(hperh->perh->RTOR, 0x0); + WRITE_REG(hperh->perh->IDR, 0xFFF); + hperh->err_code = ALD_UART_ERROR_NONE; + hperh->state = ALD_UART_STATE_RESET; + hperh->rx_state = ALD_UART_STATE_RESET; + + __UNLOCK(hperh); + + return; +} + +/** + * @brief Initializes the UARTx according to the specified + * parameters in the uart_handle_t. + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +void ald_uart_init(ald_uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_BAUDRATE(hperh->init.baud)); + assert_param(IS_UART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_UART_STOPBITS(hperh->init.stop_bits)); + assert_param(IS_UART_PARITY(hperh->init.parity)); + assert_param(IS_UART_MODE(hperh->init.mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); + + ald_uart_reset(hperh); + + MODIFY_REG(hperh->perh->LCON, UART_LCON_DLS_MSK, hperh->init.word_length << UART_LCON_DLS_POSS); + MODIFY_REG(hperh->perh->LCON, UART_LCON_STOP_MSK, hperh->init.stop_bits << UART_LCON_STOP_POS); + + if ((hperh->init.parity) != ALD_UART_PARITY_NONE) + { + SET_BIT(hperh->perh->LCON, UART_LCON_PE_MSK); + + if ((hperh->init.parity) == ALD_UART_PARITY_ODD) + CLEAR_BIT(hperh->perh->LCON, UART_LCON_PS_MSK); + + if ((hperh->init.parity) == ALD_UART_PARITY_EVEN) + SET_BIT(hperh->perh->LCON, UART_LCON_PS_MSK); + } + + MODIFY_REG(hperh->perh->MCON, UART_MCON_AFCEN_MSK, hperh->init.fctl << UART_MCON_AFCEN_POS); + hperh->perh->BRR = (ald_cmu_get_pclk_clock() + (hperh->init.baud >> 1)) / hperh->init.baud; + + if (hperh->init.mode == ALD_UART_MODE_LIN) + SET_BIT(hperh->perh->LIN, UART_LIN_LINEN_MSK); + else if (hperh->init.mode == ALD_UART_MODE_IrDA) + SET_BIT(hperh->perh->MCON, UART_MCON_IREN_MSK); + else if (hperh->init.mode == ALD_UART_MODE_RS485) + SET_BIT(hperh->perh->RS485, UART_RS485_AADEN_MSK); + else if (hperh->init.mode == ALD_UART_MODE_HDSEL) + SET_BIT(hperh->perh->MCON, UART_MCON_HDEN_MSK); + else if (hperh->init.mode == ALD_UART_MODE_SCARD) + SET_BIT(hperh->perh->SCARD, UART_SCARD_SCEN_MSK); + else + ; /* do nothing */ + + SET_BIT(hperh->perh->LCON, UART_LCON_RXEN_MSK); + SET_BIT(hperh->perh->LCON, UART_LCON_TXEN_MSK); + + hperh->state = ALD_UART_STATE_READY; + hperh->rx_state = ALD_UART_STATE_READY; + hperh->err_code = ALD_UART_ERROR_NONE; + return; +} + +/** + * @brief Configure the RS485 mode according to the specified + * parameters in the uart_rs485_config_t. + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified UART module. + * @param config: Specifies the RS485 parameters. + * @retval None + */ +void ald_uart_rs485_config(ald_uart_handle_t *hperh, ald_uart_rs485_config_t *config) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_FUNC_STATE(config->normal)); + assert_param(IS_FUNC_STATE(config->dir)); + assert_param(IS_FUNC_STATE(config->invert)); + + MODIFY_REG(hperh->perh->RS485, UART_RS485_AADNEN_MSK, config->normal << UART_RS485_AADNEN_POS); + MODIFY_REG(hperh->perh->RS485, UART_RS485_AADACEN_MSK, config->dir << UART_RS485_AADACEN_POS); + MODIFY_REG(hperh->perh->RS485, UART_RS485_AADINV_MSK, config->invert << UART_RS485_AADINV_POS); + MODIFY_REG(hperh->perh->RS485, UART_RS485_ADDR_MSK, config->addr << UART_RS485_ADDR_POSS); + + return; +} + +/** + * @brief Configure the smart card mode according to the specified + * parameters in the uart_scard_config_t. + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified UART module. + * @param config: Specifies the scard parameters. + * @retval None + */ +void ald_uart_scard_config(ald_uart_handle_t *hperh, ald_uart_scard_config_t *config) +{ + assert_param(IS_UART_ENHANCE(hperh->perh)); + assert_param(IS_UART_SCARD_CLK(config->clk_div)); + + MODIFY_REG(hperh->perh->SCARD, UART_SCARD_BLEN_MSK, config->block_len << UART_SCARD_BLEN_POSS); + MODIFY_REG(hperh->perh->SCARD, UART_SCARD_GT_MSK, config->pt << UART_SCARD_GT_POSS); + MODIFY_REG(hperh->perh->SCARD, UART_SCARD_SCCNT_MSK, config->retry << UART_SCARD_SCCNT_POSS); + MODIFY_REG(hperh->perh->SCARD, UART_SCARD_PSC_MSK, config->clk_div << UART_SCARD_PSC_POSS); + MODIFY_REG(hperh->perh->SCARD, UART_SCARD_SCLKEN_MSK, config->clk_out << UART_SCARD_SCLKEN_POS); + + return; +} +/** + * @} + */ + +/** @defgroup UART_Public_Functions_Group2 IO operation functions + * @brief UART Transmit and Receive functions + * @verbatim + ============================================================================== + # IO operation functions # + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the UART data transfers. + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The Status of all data processing is returned by the same function + after finishing transfer. + (++) Non blocking mode: The communication is performed using Interrupts + or DMA, these APIs return the Status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() user callbacks + will be executed respectively at the end of the transmit or receive process. + The hperh->error_cbk() user callback will be executed when + a communication error is detected. + + (#) Blocking mode APIs are: + (++) ald_uart_send() + (++) ald_uart_recv() + + (#) Non Blocking mode APIs with Interrupt are: + (++) ald_uart_send_by_it() + (++) ald_uart_recv_by_it() + (++) ald_uart_irq_handler() + + (#) Non Blocking mode functions with DMA are: + (++) ald_uart_send_by_dma() + (++) ald_uart_recv_by_dma() + (++) ald_uart_dma_pause() + (++) ald_uart_dma_resume() + (++) ald_uart_dma_stop() + + (#) A set of transfer complete callbacks are provided in non blocking mode: + (++) hperh->tx_cplt_cbk() + (++) hperh->rx_cplt_cbk() + (++) hperh->error_cbk() + + @endverbatim + * @{ + */ + +/** + * @brief Sends an amount of data in blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_send(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if (hperh->state != ALD_UART_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + __LOCK(hperh); + hperh->err_code = ALD_UART_ERROR_NONE; + hperh->state = ALD_UART_STATE_BUSY_TX; + + hperh->tx_size = size; + hperh->tx_count = 0; + + while (size-- > 0) + { + if (uart_wait_flag(hperh, ALD_UART_STATUS_TFEMPTY, SET, timeout) != ALD_OK) + { + __UNLOCK(hperh); + hperh->state = ALD_UART_STATE_READY; + return ALD_TIMEOUT; + } + + hperh->perh->TXBUF = (*buf++ & 0xFF); + hperh->tx_count++; + } + + if (uart_wait_flag(hperh, ALD_UART_STATUS_TSBUSY, RESET, timeout) != ALD_OK) + { + __UNLOCK(hperh); + hperh->state = ALD_UART_STATE_READY; + return ALD_TIMEOUT; + } + + hperh->state = ALD_UART_STATE_READY; + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Receives an amount of data in blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_recv(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + uint32_t stat = 0U; + uint32_t err = 0U; + uint32_t tick = 0U; + + assert_param(IS_UART_ALL(hperh->perh)); + + if (hperh->rx_state != ALD_UART_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0) || (timeout == 0)) + return ALD_ERROR; + + __LOCK(hperh); + hperh->err_code = ALD_UART_ERROR_NONE; + hperh->rx_state = ALD_UART_STATE_BUSY_RX; + + hperh->rx_size = size; + hperh->rx_count = 0; + + err = (ALD_UART_STATUS_PERR | ALD_UART_STATUS_FERR | ALD_UART_STATUS_RFOERR); + + while (size-- > 0) + { + tick = ald_get_tick(); + + /* Waiting for flag */ + while (1) + { + stat = hperh->perh->STAT; + + if (READ_BIT(stat, ALD_UART_STATUS_RFNEMPTY) != RESET) + break; + + if (((ald_get_tick()) - tick) > timeout) + { + __UNLOCK(hperh); + hperh->rx_state = ALD_UART_STATE_READY; + return ALD_TIMEOUT; + } + } + + if ((stat & err) == RESET) + { + *buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF); + hperh->rx_count++; + } + else + { + /* Handle parity error */ + if ((READ_BIT(stat, ALD_UART_STATUS_PERR)) != RESET) + hperh->err_code |= ALD_UART_ERROR_PE; + + /* Handle frame error */ + if ((READ_BIT(stat, ALD_UART_STATUS_FERR)) != RESET) + hperh->err_code |= ALD_UART_ERROR_FE; + + /* Handle rx overflow error */ + if ((READ_BIT(stat, ALD_UART_STATUS_RFOERR)) != RESET) + hperh->err_code |= ALD_UART_ERROR_ORE; + + hperh->rx_state = ALD_UART_STATE_READY; + __UNLOCK(hperh); + + return ALD_ERROR; + } + } + + hperh->rx_state = ALD_UART_STATE_READY; + __UNLOCK(hperh); + + return ALD_OK; +} + +/** + * @brief Sends an amount of data in blocking mode. + Don't care about device lock. This is for RTOS. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_send_n_lock(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if (hperh->state != ALD_UART_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + hperh->err_code = ALD_UART_ERROR_NONE; + hperh->state = ALD_UART_STATE_BUSY_TX; + + hperh->tx_size = size; + hperh->tx_count = 0; + + while (size-- > 0) + { + if (uart_wait_flag(hperh, ALD_UART_STATUS_TFEMPTY, SET, timeout) != ALD_OK) + { + hperh->state = ALD_UART_STATE_READY; + return ALD_TIMEOUT; + } + + hperh->perh->TXBUF = (*buf++ & 0xFF); + hperh->tx_count++; + } + + if (uart_wait_flag(hperh, ALD_UART_STATUS_TSBUSY, RESET, timeout) != ALD_OK) + { + hperh->state = ALD_UART_STATE_READY; + return ALD_TIMEOUT; + } + + hperh->state = ALD_UART_STATE_READY; + return ALD_OK; +} + +/** + * @brief Receives an amount of data in blocking mode. + Don't care about device lock. This is for RTOS. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_recv_n_lock(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if (hperh->rx_state != ALD_UART_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + hperh->err_code = ALD_UART_ERROR_NONE; + hperh->rx_state = ALD_UART_STATE_BUSY_RX; + + hperh->rx_size = size; + hperh->rx_count = 0; + + while (size-- > 0) + { + if (uart_wait_flag(hperh, ALD_UART_STATUS_RFNEMPTY, SET, timeout) != ALD_OK) + { + hperh->rx_state = ALD_UART_STATE_READY; + return ALD_TIMEOUT; + } + + *buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF); + hperh->rx_count++; + } + + hperh->rx_state = ALD_UART_STATE_READY; + + return ALD_OK; +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_send_by_it(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if (hperh->state != ALD_UART_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + __LOCK(hperh); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = 0; + hperh->err_code = ALD_UART_ERROR_NONE; + hperh->state = ALD_UART_STATE_BUSY_TX; + + __UNLOCK(hperh); + SET_BIT(hperh->perh->ICR, UART_ICR_TFEMPTY_MSK); + ald_uart_interrupt_config(hperh, ALD_UART_IT_TFEMPTY, ENABLE); + + return ALD_OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_recv_by_it(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if (hperh->rx_state != ALD_UART_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + __LOCK(hperh); + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = 0; + hperh->err_code = ALD_UART_ERROR_NONE; + hperh->rx_state = ALD_UART_STATE_BUSY_RX; + + __UNLOCK(hperh); + SET_BIT(hperh->perh->ICR, UART_ICR_RFNEMPTY_MSK); + ald_uart_interrupt_config(hperh, ALD_UART_IT_RFNEMPTY, ENABLE); + + return ALD_OK; +} + +/** + * @brief Receives an frame of data in non blocking mode + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Max length of frame. + * @param t_out: Timeout duration. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_recv_frame_by_it(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t t_out) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if (hperh->rx_state != ALD_UART_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (t_out == 0) || (t_out > 0xFFFFFF) || (size == 0)) + return ALD_ERROR; + + __LOCK(hperh); + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = 0; + hperh->err_code = ALD_UART_ERROR_NONE; + hperh->rx_state = ALD_UART_STATE_BUSY_RX; + + __UNLOCK(hperh); + SET_BIT(hperh->perh->ICR, UART_ICR_RFNEMPTY_MSK); + SET_BIT(hperh->perh->RTOR, UART_RTOR_RTOEN_MSK); + MODIFY_REG(hperh->perh->RTOR, UART_RTOR_RTO_MSK, t_out << UART_RTOR_RTO_POSS); + ald_uart_interrupt_config(hperh, ALD_UART_IT_RFNEMPTY, ENABLE); + ald_uart_interrupt_config(hperh, ALD_UART_IT_RXTO, ENABLE); + + return ALD_OK; +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as UART transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_send_by_dma(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if (hperh->state != ALD_UART_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + __LOCK(hperh); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = 0; + hperh->err_code = ALD_UART_ERROR_NONE; + hperh->state = ALD_UART_STATE_BUSY_TX; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA; + + /* Set the dma parameters */ + hperh->hdmatx.cplt_tc_cbk = uart_dma_send_cplt; + hperh->hdmatx.cplt_tc_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->TXBUF; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmatx.config.dst_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmatx.config.msigsel = ALD_DMA_MSIGSEL_UART_TXEMPTY; + hperh->hdmatx.config.channel = channel; + + if (hperh->init.mode == ALD_UART_MODE_RS485) + { + hperh->hdmatx.config.src_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + } + + if (hperh->perh == CUART0) + hperh->hdmatx.config.msel = ALD_DMA_MSEL_CUART0; + else if (hperh->perh == CUART1) + hperh->hdmatx.config.msel = ALD_DMA_MSEL_CUART1; + else if (hperh->perh == CUART2) + hperh->hdmatx.config.msel = ALD_DMA_MSEL_CUART2; + else if (hperh->perh == EUART0) + hperh->hdmatx.config.msel = ALD_DMA_MSEL_EUART0; + else if (hperh->perh == EUART1) + hperh->hdmatx.config.msel = ALD_DMA_MSEL_EUART1; + else + ; /* do nothing */ + + ald_dma_config_basic(&hperh->hdmatx); + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + + __UNLOCK(hperh); + ald_uart_clear_flag_status(hperh, ALD_UART_IF_TBC); + ald_uart_dma_req_config(hperh, ALD_UART_DMA_REQ_TX, ENABLE); + + return ALD_OK; +} + +/** + * @brief Receives an amount of data in non blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param channel: DMA channel as UART receive + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_recv_by_dma(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if (hperh->rx_state != ALD_UART_STATE_READY) + return ALD_BUSY; + + if ((buf == NULL) || (size == 0)) + return ALD_ERROR; + + __LOCK(hperh); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->err_code = ALD_UART_ERROR_NONE; + hperh->rx_state = ALD_UART_STATE_BUSY_RX; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA; + + /* Set the dma parameters */ + hperh->hdmarx.cplt_tc_cbk = uart_dma_recv_cplt; + hperh->hdmarx.cplt_tc_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->RXBUF; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = ALD_DMA_DATA_INC_DISABLE; + hperh->hdmarx.config.dst_inc = ALD_DMA_DATA_INC_ENABLE; + hperh->hdmarx.config.msigsel = ALD_DMA_MSIGSEL_UART_RNR; + hperh->hdmarx.config.channel = channel; + + if (hperh->init.mode == ALD_UART_MODE_RS485) + { + hperh->hdmarx.config.dst_data_width = ALD_DMA_DATA_SIZE_HALFWORD; + } + + if (hperh->perh == CUART0) + hperh->hdmarx.config.msel = ALD_DMA_MSEL_CUART0; + else if (hperh->perh == CUART1) + hperh->hdmarx.config.msel = ALD_DMA_MSEL_CUART1; + else if (hperh->perh == CUART2) + hperh->hdmarx.config.msel = ALD_DMA_MSEL_CUART2; + else if (hperh->perh == EUART0) + hperh->hdmarx.config.msel = ALD_DMA_MSEL_EUART0; + else if (hperh->perh == EUART1) + hperh->hdmarx.config.msel = ALD_DMA_MSEL_EUART1; + else + ; + + __UNLOCK(hperh); + ald_dma_config_basic(&hperh->hdmarx); + ald_dma_interrupt_config(channel, ALD_DMA_IT_FLAG_TC, ENABLE); + ald_uart_dma_req_config(hperh, ALD_UART_DMA_REQ_RX, ENABLE); + + return ALD_OK; +} + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_dma_pause(ald_uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + ald_uart_dma_req_config(hperh, ALD_UART_DMA_REQ_TX, DISABLE); + ald_uart_dma_req_config(hperh, ALD_UART_DMA_REQ_RX, DISABLE); + return ALD_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_dma_resume(ald_uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + ald_uart_dma_req_config(hperh, ALD_UART_DMA_REQ_TX, ENABLE); + ald_uart_dma_req_config(hperh, ALD_UART_DMA_REQ_RX, ENABLE); + return ALD_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_dma_stop(ald_uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + ald_uart_dma_req_config(hperh, ALD_UART_DMA_REQ_TX, DISABLE); + ald_uart_dma_req_config(hperh, ALD_UART_DMA_REQ_RX, DISABLE); + + hperh->state = ALD_UART_STATE_READY; + hperh->rx_state = ALD_UART_STATE_READY; + + return ALD_OK; +} + +/** + * @brief This function handles UART interrupt request. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval None + */ +void ald_uart_irq_handler(ald_uart_handle_t *hperh) +{ + uint32_t stat = 0U; + + assert_param(IS_UART_ALL(hperh->perh)); + + stat = hperh->perh->STAT; + + /* Handle parity error */ + if ((READ_BIT(stat, ALD_UART_STATUS_PERR)) != RESET) + hperh->err_code |= ALD_UART_ERROR_PE; + + /* Handle frame error */ + if ((READ_BIT(stat, ALD_UART_STATUS_FERR)) != RESET) + hperh->err_code |= ALD_UART_ERROR_FE; + + /* Handle rx overflow error */ + if ((READ_BIT(stat, ALD_UART_STATUS_RFOERR)) != RESET) + { + hperh->err_code |= ALD_UART_ERROR_ORE; + hperh->perh->ICR = ALD_UART_IF_RFOERR; + } + + /* Handle tx overflow error */ + if ((READ_BIT(stat, ALD_UART_STATUS_TFOERR)) != RESET) + { + hperh->err_code |= ALD_UART_ERROR_ORE; + hperh->perh->ICR = ALD_UART_IF_TFOVER; + } + + /* Receive */ + if ((ald_uart_get_mask_flag_status(hperh, ALD_UART_IF_RFNEMPTY)) != RESET) + { + __uart_recv_by_it(hperh); + ald_uart_clear_flag_status(hperh, ALD_UART_IF_RFNEMPTY); + } + + /* Transmit */ + if ((ald_uart_get_mask_flag_status(hperh, ALD_UART_IF_TFEMPTY)) != RESET) + { + __uart_send_by_it(hperh); + ald_uart_clear_flag_status(hperh, ALD_UART_IF_TFEMPTY); + } + + /* End Transmit */ + if ((ald_uart_get_mask_flag_status(hperh, ALD_UART_IF_TBC)) != RESET) + { + __uart_end_send_by_it(hperh); + ald_uart_clear_flag_status(hperh, ALD_UART_IF_TBC); + } + + /* Receive frame timeout*/ + if ((ald_uart_get_mask_flag_status(hperh, ALD_UART_IF_RXTO)) != RESET) + { + ald_uart_clear_flag_status(hperh, ALD_UART_IF_RFNEMPTY); + ald_uart_clear_flag_status(hperh, ALD_UART_IF_RXTO); + + ald_uart_interrupt_config(hperh, ALD_UART_IT_RFNEMPTY, DISABLE); + ald_uart_interrupt_config(hperh, ALD_UART_IT_RXTO, DISABLE); + + hperh->rx_state = ALD_UART_STATE_READY; + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + /* Handle error state */ + if (hperh->err_code != ALD_UART_ERROR_NONE) + { + if (hperh->error_cbk) + hperh->error_cbk(hperh); + } +} + +/** + * @brief This function handles UART interrupt request. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval None + */ +void ald_uart_irq_handler_fast(ald_uart_handle_t *hperh) +{ + volatile uint32_t tmp = hperh->perh->IFM; + uint32_t tmp_reg = 0; + uint32_t err = 0; + uint32_t stat = 0; + uint32_t cnt = 0xFFFFFF; + + /* Transmit */ + if (tmp & 0x10000) + { + hperh->perh->ICR = 0x10000; + hperh->perh->TXBUF = *hperh->tx_buf++; + ++hperh->tx_count; + + if (hperh->tx_count >= hperh->tx_size) + { + hperh->perh->IDR = 0x10000; + + /* Wait for fifo empty */ + while (!(hperh->perh->STAT & 0x10000U) && (cnt--)); + + /* Enable TBC interrupt */ + hperh->perh->IER = 0x4000; + hperh->state = ALD_UART_STATE_READY; + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + } + } + + /* End Transmit */ + if (tmp & 0x4000) + { + hperh->perh->IDR = 0x4000; + + cnt = 0xFFFFFFU; + while ((hperh->perh->STAT & ALD_UART_STATUS_TSBUSY) && (cnt--)); + + /* Clear TBC flag */ + hperh->perh->ICR = 0x4000; + hperh->state = ALD_UART_STATE_READY; + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + } + + /* Receive*/ + if (tmp & 0x400) + { + /* Read FIFO */ + if (hperh->rx_count < hperh->rx_size) + { + *hperh->rx_buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF); + ++hperh->rx_count; + } + else + { + tmp_reg = (uint8_t)(hperh->perh->RXBUF & 0xFF); + UNUSED(tmp_reg); + } + + hperh->perh->ICR = 0x400; + + if (hperh->rx_count >= hperh->rx_size) + { + hperh->perh->IDR = 0x400; + hperh->rx_state = ALD_UART_STATE_READY; + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + } + + /* Receive frame */ + if (tmp & 0x10) + { + hperh->perh->ICR = 0x10U; + hperh->perh->ICR = 0x400U; + + hperh->perh->IDR = 0x10U; + hperh->perh->IDR = 0x400U; + hperh->rx_state = ALD_UART_STATE_READY; + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + /* Handle error state */ + err = (ALD_UART_STATUS_PERR | ALD_UART_STATUS_FERR | ALD_UART_STATUS_RFOERR); + stat = hperh->perh->STAT; + + if ((stat & err) != RESET) + { + if (hperh->error_cbk) + hperh->error_cbk(hperh); + } + + return; +} +/** + * @} + */ + +/** @defgroup UART_Public_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART: + (+) ald_uart_interrupt_config() API can be helpful to configure UART interrupt source. + (+) ald_uart_dma_req_config() API can be helpful to configure UART DMA request. + (+) ald_uart_tx_fifo_config() API can be helpful to configure UART TX FIFO paramters. + (+) ald_uart_rx_fifo_config() API can be helpful to configure UART RX FIFO paramters. + (+) ald_uart_lin_send_break() API can send a frame of break in LIN mode. + (+) ald_uart_lin_detect_break_len_config() API can be helpful to configure the length of break frame. + (+) ald_uart_auto_baud_config() API can be helpful to configure detection data mode. + (+) ald_uart_get_it_status() API can get the status of interrupt source. + (+) ald_uart_get_status() API can get the status of UART_SR register. + (+) ald_uart_get_flag_status() API can get the status of UART flag. + (+) ald_uart_get_mask_flag_status() API can get status os flag and interrupt source. + (+) ald_uart_clear_flag_status() API can clear UART flag. + + @endverbatim + * @{ + */ + +/** + * @brief Enable/disable the specified UART interrupts. + * @param hperh: Pointer to a uart_handle_t structure. + * @param it: Specifies the UART interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref uart_it_t. + * @param state: New state of the specified UART interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_uart_interrupt_config(ald_uart_handle_t *hperh, ald_uart_it_t it, type_func_t state) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + hperh->perh->IER = it; + else + hperh->perh->IDR = it; + + return; +} + +/** + * @brief Configure UART DMA request. + * @param hperh: Pointer to a uart_handle_t structure. + * @param req: The type of DMA request. + * @param state: New state of the specified DMA request. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_uart_dma_req_config(ald_uart_handle_t *hperh, ald_uart_dma_req_t req, type_func_t state) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (req == ALD_UART_DMA_REQ_TX) + { + if (state == ENABLE) + SET_BIT(hperh->perh->MCON, UART_MCON_TXDMAEN_MSK); + else + CLEAR_BIT(hperh->perh->MCON, UART_MCON_TXDMAEN_MSK); + } + else + { + if (state == ENABLE) + SET_BIT(hperh->perh->MCON, UART_MCON_RXDMAEN_MSK); + else + CLEAR_BIT(hperh->perh->MCON, UART_MCON_RXDMAEN_MSK); + } + + return; +} + +/** + * @brief Enable/Disable break signal detect interrup. + * @param hperh: Pointer to a uart_handle_t structure. + * @param status: The new status. + * @retval None + */ +void uart_lin_break_detect_irq(ald_uart_handle_t *hperh, type_func_t status) +{ + assert_param(IS_UART_ENHANCE(hperh->perh)); + + if (status == ENABLE) + { + SET_BIT(hperh->perh->IER, UART_IER_LINBK_MSK); + } + else + { + CLEAR_BIT(hperh->perh->IER, UART_IER_LINBK_MSK); + } + + return; +} + +/** + * @brief request to send a frame of break. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval None + */ +void ald_uart_lin_send_break(ald_uart_handle_t *hperh) +{ + assert_param(IS_UART_ENHANCE(hperh->perh)); + + SET_BIT(hperh->perh->LIN, UART_LIN_LINBKREQ_MSK); + hperh->perh->TXBUF = 0x55; + + return; +} + +/** + * @brief Configure the length of break frame to be detect. + * @param hperh: Pointer to a uart_handle_t structure. + * @param len: Length of break frame. + * @arg LIN_BREAK_LEN_10B + * @arg LIN_BREAK_LEN_11B + * @retval None + */ +void ald_uart_lin_detect_break_len_config(ald_uart_handle_t *hperh, ald_uart_lin_break_len_t len) +{ + assert_param(IS_UART_ENHANCE(hperh->perh)); + assert_param(IS_UART_LIN_BREAK_LEN(len)); + + MODIFY_REG(hperh->perh->LIN, UART_LIN_LINBDL_MSK, len << UART_LIN_LINBDL_POS); + + return; +} + +/** + * @brief Configure the mode of auto-baud-rate detect. + * @param hperh: Pointer to a uart_handle_t structure. + * @param mode: The mode of auto-baud-rate detect. + * @arg UART_ABRMOD_1_TO_0 + * @arg UART_ABRMOD_1 + * @arg UART_ABRMOD_0_TO_1 + * @retval None + */ +void ald_uart_auto_baud_config(ald_uart_handle_t *hperh, ald_uart_auto_baud_mode_t mode) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_AUTO_BAUD_MODE(mode)); + + MODIFY_REG(hperh->perh->MCON, UART_MCON_ABRMOD_MSK, mode << UART_MCON_ABRMOD_POSS); + + return; +} + +/** + * @brief Send address in RS485 mode. + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified UART module. + * @param addr: the address of RS485 device. + * @param timeout: Timeout duration + * @retval The ALD status. + */ +ald_status_t ald_uart_rs485_send_addr(ald_uart_handle_t *hperh, uint16_t addr, uint32_t timeout) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if (hperh->state != ALD_UART_STATE_READY) + return ALD_BUSY; + + hperh->state = ALD_UART_STATE_BUSY_TX; + + if (uart_wait_flag(hperh, ALD_UART_STATUS_TFEMPTY, SET, timeout) != ALD_OK) + { + hperh->state = ALD_UART_STATE_READY; + return ALD_TIMEOUT; + } + + WRITE_REG(hperh->perh->TXBUF, (addr | 0x100)); + + if (uart_wait_flag(hperh, ALD_UART_STATUS_TFEMPTY, SET, timeout) != ALD_OK) + { + hperh->state = ALD_UART_STATE_READY; + return ALD_TIMEOUT; + } + + hperh->state = ALD_UART_STATE_READY; + + return ALD_OK; +} + +/** + * @brief Get the status of UART interrupt source. + * @param hperh: Pointer to a uart_handle_t structure. + * @param it: Specifies the UART interrupt source. + * This parameter can be one of the @ref uart_it_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_uart_get_it_status(ald_uart_handle_t *hperh, ald_uart_it_t it) +{ + it_status_t status = RESET; + + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IT(it)); + + if (hperh->perh->IVS & it) + status = SET; + + return status; +} + +/** + * @brief Get the status of UART_SR register. + * @param hperh: Pointer to a uart_handle_t structure. + * @param status: Specifies the UART status type. + * This parameter can be one of the @ref uart_status_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_uart_get_status(ald_uart_handle_t *hperh, ald_uart_status_t status) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_STATUS(status)); + + if (hperh->perh->STAT & status) + return SET; + + return RESET; +} + + +/** + * @brief Get the status of UART interrupt flag. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: Specifies the UART interrupt flag. + * This parameter can be one of the @ref uart_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_uart_get_flag_status(ald_uart_handle_t *hperh, ald_uart_flag_t flag) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + +/** + * @brief Get the status of interrupt flag and interupt source. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: Specifies the UART interrupt flag. + * This parameter can be one of the @ref uart_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_uart_get_mask_flag_status(ald_uart_handle_t *hperh, ald_uart_flag_t flag) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); + + if (hperh->perh->IFM & flag) + return SET; + + return RESET; +} + +/** + * @brief Clear the UART interrupt flag. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: Specifies the UART interrupt flag. + * This parameter can be one of the @ref uart_flag_t. + * @retval None + */ +void ald_uart_clear_flag_status(ald_uart_handle_t *hperh, ald_uart_flag_t flag) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); + + hperh->perh->ICR = flag; + return; +} +/** + * @} + */ + +/** @defgroup UART_Public_Functions_Group4 Peripheral State and Errors functions + * @brief UART State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of + UART communication process, return Peripheral Errors occurred during communication + process + (+) ald_uart_get_state() API can be helpful to check in run-time the state of the UART peripheral. + (+) ald_uart_get_error() check in run-time errors that could be occurred during communication. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the UART state. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval ALD state + */ +ald_uart_state_t ald_uart_get_state(ald_uart_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Return the UART error code + * @param hperh: Pointer to a uart_handle_t structure. + * @retval UART Error Code + */ +uint32_t ald_uart_get_error(ald_uart_handle_t *hperh) +{ + return hperh->err_code; +} + +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_uart.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_uart.h new file mode 100644 index 0000000000..a13325858a --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_uart.h @@ -0,0 +1,535 @@ +/** + ********************************************************************************* + * + * @file ald_uart.h + * @brief Header file of UART module library. + * + * @version V1.0 + * @date 22 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 22 Feb. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_UART_H__ +#define __ALD_UART_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_cmu.h" +#include "ald_dma.h" + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Constants -------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** + * @defgroup UART_Public_Macros UART Public Macros + * @{ + */ +#define ALD_UART_RX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK)) +#define ALD_UART_RX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK)) +#define ALD_UART_TX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK)) +#define ALD_UART_TX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK)) +#define ALD_UART_RX_TIMEOUT_ENABLE(hperh) (SET_BIT((hperh)->perh->RTOR, UART_RTOR_RTOEN_MSK)) +#define ALD_UART_RX_TIMEOUT_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->RTOR, UART_RTOR_RTOEN_MSK)) +#define ALD_UART_MSB_FIRST_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK)) +#define ALD_UART_MSB_FIRST_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK)) +#define ALD_UART_DATA_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK)) +#define ALD_UART_DATA_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK)) +#define ALD_UART_RX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_RXINV_MSK)) +#define ALD_UART_RX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXINV_MSK)) +#define ALD_UART_TX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_TXINV_MSK)) +#define ALD_UART_TX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXINV_MSK)) +#define ALD_UART_TX_RX_SWAP_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_SWAP_MSK)) +#define ALD_UART_TX_RX_SWAP_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_SWAP_MSK)) +#define ALD_UART_HDSEL_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK)) +#define ALD_UART_HDSEL_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK)) +#define ALD_UART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_LPBKEN_MSK)) +#define ALD_UART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_LPBKEN_MSK)) +#define ALD_UART_AUTOBR_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK)) +#define ALD_UART_AUTOBR_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK)) +#define ALD_UART_AUTOBR_REPT(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_ABRREPT_MSK)) +#define ALD_UART_GET_BRR_VALUE(hperh) (READ_REG((hperh)->perh->BRR)) +#define ALD_UART_SET_TIMEOUT_VALUE(x, y) (MODIFY_REG((x)->perh->RTOR, UART_RTOR_RTO_MSK, (y) << UART_RTOR_RTO_POSS)) +#define ALD_UART_ENABLE_SCARD_CLK(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCLKEN_MSK)) +#define ALD_UART_DISABLE_SCARD_CLK(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCLKEN_MSK)) +#define ALD_UART_ENABLE_SCARD_NACK(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCNACK_MSK)) +#define ALD_UART_DISABLE_SCARD_NACK(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCNACK_MSK)) +#define ALD_UART_SCARD_ENABLE(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCEN_MSK)) +#define ALD_UART_SCARD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCEN_MSK)) +/** + * @} + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup UART_Public_Types UART Public Types + * @{ + */ +/** + * @brief UART word length + */ +typedef enum +{ + ALD_UART_WORD_LENGTH_8B = 0x0U, /**< 8-bits */ + ALD_UART_WORD_LENGTH_7B = 0x1U, /**< 7-bits */ + ALD_UART_WORD_LENGTH_6B = 0x2U, /**< 6-bits */ + ALD_UART_WORD_LENGTH_5B = 0x3U, /**< 5-bits */ +} ald_uart_word_length_t; + +/** + * @brief UART stop bits + */ +typedef enum +{ + ALD_UART_STOP_BITS_1 = 0x0U, /**< 1-bits */ + ALD_UART_STOP_BITS_2 = 0x1U, /**< 2-bits */ + ALD_UART_STOP_BITS_0_5 = 0x0U, /**< 0.5-bits, using smartcard mode */ + ALD_UART_STOP_BITS_1_5 = 0x1U, /**< 1.5-bits, using smartcard mode */ +} ald_uart_stop_bits_t; + +/** + * @brief UART parity + */ +typedef enum +{ + ALD_UART_PARITY_NONE = 0x0U, /**< Not parity */ + ALD_UART_PARITY_ODD = 0x1U, /**< Odd parity */ + ALD_UART_PARITY_EVEN = 0x3U, /**< Even parity */ +} ald_uart_parity_t; + +/** + * @brief UART mode + */ +typedef enum +{ + ALD_UART_MODE_UART = 0x0U, /**< UART */ + ALD_UART_MODE_LIN = 0x1U, /**< LIN */ + ALD_UART_MODE_IrDA = 0x2U, /**< IrDA */ + ALD_UART_MODE_RS485 = 0x3U, /**< RS485 */ + ALD_UART_MODE_HDSEL = 0x4U, /**< Single-wire half-duplex */ + ALD_UART_MODE_SCARD = 0x5U, /**< Smart card */ +} ald_uart_mode_t; + +/** + * @brief UART hardware flow control + */ +typedef enum +{ + ALD_UART_HW_FLOW_CTL_DISABLE = 0x0U, /**< Auto-flow-control disable */ + ALD_UART_HW_FLOW_CTL_ENABLE = 0x1U, /**< Auto-flow-control enable */ +} ald_uart_hw_flow_ctl_t; + +/** + * @brief ALD UART state + */ +typedef enum +{ + ALD_UART_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + ALD_UART_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + ALD_UART_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + ALD_UART_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */ + ALD_UART_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */ + ALD_UART_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission Reception process is ongoing */ + ALD_UART_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + ALD_UART_STATE_ERROR = 0x04U, /**< Error */ + ALD_UART_STATE_TX_MASK = 0x10U, /**< TX_MASK */ + ALD_UART_STATE_RX_MASK = 0x20U, /**< RX_MASK */ +} ald_uart_state_t; + +/** + * @brief UART error codes + */ +typedef enum +{ + ALD_UART_ERROR_NONE = ((uint32_t)0x00U), /**< No error */ + ALD_UART_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */ + ALD_UART_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */ + ALD_UART_ERROR_FE = ((uint32_t)0x04U), /**< frame error */ + ALD_UART_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */ + ALD_UART_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */ +} ald_uart_error_t; + +/** + * @brief UART init structure definition + */ +typedef struct +{ + uint32_t baud; /**< Specifies the uart communication baud rate */ + ald_uart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */ + ald_uart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */ + ald_uart_parity_t parity; /**< Specifies the parity mode */ + ald_uart_mode_t mode; /**< Specifies uart mode */ + ald_uart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */ +} ald_uart_init_t; + +/** + * @brief UART handle structure definition + */ +typedef struct ald_uart_handle_s +{ + UART_TypeDef *perh; /**< UART registers base address */ + ald_uart_init_t init; /**< UART communication parameters */ + uint8_t *tx_buf; /**< Pointer to UART Tx transfer Buffer */ + uint16_t tx_size; /**< UART Tx Transfer size */ + uint16_t tx_count; /**< UART Tx Transfer Counter */ + uint8_t *rx_buf; /**< Pointer to UART Rx transfer Buffer */ + uint16_t rx_size; /**< UART Rx Transfer size */ + uint16_t rx_count; /**< UART Rx Transfer Counter */ + + ald_dma_handle_t hdmatx; /**< UART Tx DMA Handle parameters */ + ald_dma_handle_t hdmarx; /**< UART Rx DMA Handle parameters */ + + lock_state_t lock; /**< Locking object */ + ald_uart_state_t state; /**< UART communication state */ + ald_uart_state_t rx_state; /**< UART receive state */ + ald_uart_error_t err_code; /**< UART Error code */ + + void (*tx_cplt_cbk)(struct ald_uart_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct ald_uart_handle_s *arg); /**< Rx completed callback */ + void (*error_cbk)(struct ald_uart_handle_s *arg); /**< error callback */ +} ald_uart_handle_t; + +/** + * @brief UART RS485 configure structure definition + */ +typedef struct +{ + type_func_t normal; /**< Normal mode */ + type_func_t dir; /**< Auto-direction mode */ + type_func_t invert; /**< Address detection invert */ + uint8_t addr; /**< Address for compare */ +} ald_uart_rs485_config_t; + +/** + * @brief Smart_card Rx/Tx handle retry time + */ +typedef enum +{ + ALD_SCARD_RETRY_CNT0 = 0x0U, /**< retry time 0 */ + ALD_SCARD_RETRY_CNT1 = 0x1U, /**< retry time 1 */ + ALD_SCARD_RETRY_CNT2 = 0x2U, /**< retry time 2 */ + ALD_SCARD_RETRY_CNT3 = 0x3U, /**< retry time 3 */ + ALD_SCARD_RETRY_CNT4 = 0x4U, /**< retry time 4 */ + ALD_SCARD_RETRY_CNT5 = 0x5U, /**< retry time 5 */ + ALD_SCARD_RETRY_CNT6 = 0x6U, /**< retry time 6 */ + ALD_SCARD_RETRY_CNT7 = 0x7U, /**< retry time 7 */ +} ald_scard_retry_t; + +/** + * @brief UART Smart card configure structure definition + */ +typedef struct +{ + uint8_t block_len; /**< Specifies the data block length.*/ + uint8_t pt; /**< Specifies the protect time*/ + ald_scard_retry_t retry; /**< Specifies retry time.*/ + uint8_t clk_div; /**< Specifies the clock division.*/ + type_func_t clk_out; /**< Specifies the clock out */ +} ald_uart_scard_config_t; + +/** + * @brief LIN detection break length + */ +typedef enum +{ + ALD_LIN_BREAK_LEN_10B = 0x0U, /**< 10-bit break */ + ALD_LIN_BREAK_LEN_11B = 0x1U, /**< 11-bit break */ +} ald_uart_lin_break_len_t; + +/** + * @brief UART auto-baud mode + */ +typedef enum +{ + ALD_UART_ABRMOD_1_TO_0 = 0x0U, /**< Detect bit0:1, bit1:0 */ + ALD_UART_ABRMOD_1 = 0x1U, /**< Detect bit0:1 */ + ALD_UART_ABRMOD_0_TO_1 = 0x2U, /**< Detect bit0:0, bit1:1 */ +} ald_uart_auto_baud_mode_t; + +/** + * @brief UART DMA Requests + */ +typedef enum +{ + ALD_UART_DMA_REQ_TX = 0x0U, /**< TX dma */ + ALD_UART_DMA_REQ_RX = 0x1U, /**< RX dma */ +} ald_uart_dma_req_t; + +/** + * @brief UART status types + */ +typedef enum +{ + ALD_UART_STATUS_PERR = (1U << 0), /**< Parity error */ + ALD_UART_STATUS_FERR = (1U << 1), /**< Framing error */ + ALD_UART_STATUS_BKERR = (1U << 2), /**< Break error */ + ALD_UART_STATUS_CTSSTA = (1U << 3), /**< Clear to send status */ + ALD_UART_STATUS_RSBUSY = (1U << 8), /**< Receive shif register busy */ + ALD_UART_STATUS_RFNEMPTY = (1U << 10), /**< Receive FIFO not empty */ + ALD_UART_STATUS_RFOERR = (1U << 12), /**< Reveive FIFO overrun error */ + ALD_UART_STATUS_RFUERR = (1U << 13), /**< Receive FIFO underrun error */ + ALD_UART_STATUS_TSBUSY = (1U << 14), /**< Transmit shit register busy */ + ALD_UART_STATUS_TFEMPTY = (1U << 16), /**< Transmit FIFO empty */ + ALD_UART_STATUS_TFOERR = (1U << 18), /**< Transmit FIFO overrun error */ +} ald_uart_status_t; + +/** + * @brief UART interrupt types + */ +typedef enum +{ + ALD_UART_IT_RXBERR = (1U << 0), /**< Receiver byte error */ + ALD_UART_IT_ABEND = (1U << 1), /**< Auto-Baud rate detection end */ + ALD_UART_IT_ABTO = (1U << 2), /**< Auto-Baud rate detection timeout */ + ALD_UART_IT_DCTS = (1U << 3), /**< Delta CTS status */ + ALD_UART_IT_RXTO = (1U << 4), /**< Receiver timeout */ + ALD_UART_IT_ADDRM = (1U << 5), /**< Addredd match */ + ALD_UART_IT_LINBK = (1U << 6), /**< Lin break detection */ + ALD_UART_IT_EOB = (1U << 7), /**< End of block */ + ALD_UART_IT_NOISE = (1U << 8), /**< Start bit noise detection */ + ALD_UART_IT_RFNEMPTY = (1U << 10), /**< Receive FIFO not empty */ + ALD_UART_IT_RFFULL = (1U << 11), /**< Receive FIFO full */ + ALD_UART_IT_RFOERR = (1U << 12), /**< Receive FIFO overrun */ + ALD_UART_IT_RFUERR = (1U << 13), /**< Reveive FIFO underrun */ + ALD_UART_IT_TBC = (1U << 14), /**< Transmit shift register empty */ + ALD_UART_IT_TFEMPTY = (1U << 16), /**< Transmit FIFO empty */ + ALD_UART_IT_TFOERR = (1U << 18), /**< Transmit FIFO overrun error */ +} ald_uart_it_t; + +/** + * @brief UART flags types + */ +typedef enum +{ + ALD_UART_IF_RXBERR = (1U << 0), /**< Receiver byte error */ + ALD_UART_IF_ABEND = (1U << 1), /**< Auto-Baud rate detection end */ + ALD_UART_IF_ABTO = (1U << 2), /**< Auto-Baud rate detection timeout */ + ALD_UART_IF_DCTS = (1U << 3), /**< Delta CTS status */ + ALD_UART_IF_RXTO = (1U << 4), /**< Receiver timeout */ + ALD_UART_IF_ADDRM = (1U << 5), /**< Addredd match */ + ALD_UART_IF_LINBK = (1U << 6), /**< Lin break detection */ + ALD_UART_IF_EOB = (1U << 7), /**< End of block */ + ALD_UART_IF_NOISE = (1U << 8), /**< Start bit noise detection */ + ALD_UART_IF_RFNEMPTY = (1U << 10), /**< Receive FIFO not empty */ + ALD_UART_IF_RFFULL = (1U << 11), /**< Receive FIFO full */ + ALD_UART_IF_RFOERR = (1U << 12), /**< Receive FIFO overrun */ + ALD_UART_IF_RFUERR = (1U << 13), /**< Reveive FIFO underrun */ + ALD_UART_IF_TBC = (1U << 14), /**< Transmit shift register empty */ + ALD_UART_IF_TFEMPTY = (1U << 16), /**< Transmit FIFO empty */ + ALD_UART_IF_TFOVER = (1U << 18), /**< Transmit FIFO overrun */ +} ald_uart_flag_t; +/** + * @} + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +#define IS_UART_ENHANCE(x)(((x) == EUART0) || \ + ((x) == EUART1)) +#define IS_UART_ALL(x) (((x) == EUART0) || \ + ((x) == EUART1) || \ + ((x) == CUART0) || \ + ((x) == CUART1) || \ + ((x) == CUART2)) +#define IS_UART_WORD_LENGTH(x) (((x) == ALD_UART_WORD_LENGTH_5B) || \ + ((x) == ALD_UART_WORD_LENGTH_6B) || \ + ((x) == ALD_UART_WORD_LENGTH_7B) || \ + ((x) == ALD_UART_WORD_LENGTH_8B)) +#define IS_UART_STOPBITS(x) (((x) == ALD_UART_STOP_BITS_1) || \ + ((x) == ALD_UART_STOP_BITS_2) || \ + ((x) == ALD_UART_STOP_BITS_0_5) || \ + ((x) == ALD_UART_STOP_BITS_1_5)) +#define IS_UART_PARITY(x) (((x) == ALD_UART_PARITY_NONE) || \ + ((x) == ALD_UART_PARITY_ODD) || \ + ((x) == ALD_UART_PARITY_EVEN)) +#define IS_UART_MODE(x) (((x) == ALD_UART_MODE_UART) || \ + ((x) == ALD_UART_MODE_LIN) || \ + ((x) == ALD_UART_MODE_IrDA) || \ + ((x) == ALD_UART_MODE_HDSEL) || \ + ((x) == ALD_UART_MODE_SCARD) || \ + ((x) == ALD_UART_MODE_RS485)) +#define IS_UART_HARDWARE_FLOW_CONTROL(x) \ + (((x) == ALD_UART_HW_FLOW_CTL_DISABLE) || \ + ((x) == ALD_UART_HW_FLOW_CTL_ENABLE)) +#define IS_UART_LIN_BREAK_LEN(x) (((x) == ALD_LIN_BREAK_LEN_10B) || \ + ((x) == ALD_LIN_BREAK_LEN_11B)) +#define IS_UART_AUTO_BAUD_MODE(x) (((x) == ALD_UART_ABRMOD_1_TO_0) || \ + ((x) == ALD_UART_ABRMOD_1) || \ + ((x) == ALD_UART_ABRMOD_0_TO_1)) +#define IS_UART_DMA_REQ(x) (((x) == ALD_UART_DMA_REQ_TX) || \ + ((x) == ALD_UART_DMA_REQ_RX)) +#define IS_UART_STATUS(x) (((x) == ALD_UART_STATUS_PERR) || \ + ((x) == ALD_UART_STATUS_FERR) || \ + ((x) == ALD_UART_STATUS_BKERR) || \ + ((x) == ALD_UART_STATUS_CTSSTA) || \ + ((x) == ALD_UART_STATUS_RSBUSY) || \ + ((x) == ALD_UART_STATUS_RFNEMPTY) || \ + ((x) == ALD_UART_STATUS_RFOERR) || \ + ((x) == ALD_UART_STATUS_RFUERR) || \ + ((x) == ALD_UART_STATUS_TSBUSY) || \ + ((x) == ALD_UART_STATUS_TFEMPTY) || \ + ((x) == ALD_UART_STATUS_TFOERR)) +#define IS_UART_IT(x) (((x) == ALD_UART_IT_RXBERR) || \ + ((x) == ALD_UART_IT_ABEND) || \ + ((x) == ALD_UART_IT_ABTO) || \ + ((x) == ALD_UART_IT_DCTS) || \ + ((x) == ALD_UART_IT_RXTO) || \ + ((x) == ALD_UART_IT_ADDRM) || \ + ((x) == ALD_UART_IT_LINBK) || \ + ((x) == ALD_UART_IT_EOB) || \ + ((x) == ALD_UART_IT_NOISE) || \ + ((x) == ALD_UART_IT_RFNEMPTY) || \ + ((x) == ALD_UART_IT_RFOERR) || \ + ((x) == ALD_UART_IT_RFUERR) || \ + ((x) == ALD_UART_IT_TBC) || \ + ((x) == ALD_UART_IT_TFEMPTY) || \ + ((x) == ALD_UART_IT_TFOERR)) +#define IS_UART_IF(x) (((x) == ALD_UART_IF_RXBERR) || \ + ((x) == ALD_UART_IF_ABEND) || \ + ((x) == ALD_UART_IF_ABTO) || \ + ((x) == ALD_UART_IF_DCTS) || \ + ((x) == ALD_UART_IF_RXTO) || \ + ((x) == ALD_UART_IF_ADDRM) || \ + ((x) == ALD_UART_IF_LINBK) || \ + ((x) == ALD_UART_IF_EOB) || \ + ((x) == ALD_UART_IF_NOISE) || \ + ((x) == ALD_UART_IF_RFNEMPTY) || \ + ((x) == ALD_UART_IF_RFOERR) || \ + ((x) == ALD_UART_IF_RFUERR) || \ + ((x) == ALD_UART_IF_TBC) || \ + ((x) == ALD_UART_IF_TFEMPTY) || \ + ((x) == ALD_UART_IF_TFOVER)) +#define IS_UART_SCARD_CLK(x) (((x) <= 0x1F)) +#define IS_UART_BAUDRATE(x) (((x) > 0) && ((x) < 0x44AA21)) +#define IS_UART_DATA(x) ((x) <= 0x1FF) +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @addtogroup UART_Public_Functions + * @{ + */ + +/** @addtogroup UART_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +void ald_uart_init(ald_uart_handle_t *hperh); +void ald_uart_reset(ald_uart_handle_t *hperh); +void ald_uart_rs485_config(ald_uart_handle_t *hperh, ald_uart_rs485_config_t *config); +void ald_uart_scard_config(ald_uart_handle_t *hperh, ald_uart_scard_config_t *config); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group2 + * @{ + */ +/* IO operation functions */ +ald_status_t ald_uart_send(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_uart_recv(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_uart_send_n_lock(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_uart_recv_n_lock(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_uart_send_by_it(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_uart_recv_by_it(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_uart_recv_frame_by_it(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t t_out); + +ald_status_t ald_uart_send_by_dma(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_uart_recv_by_dma(ald_uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_uart_dma_pause(ald_uart_handle_t *hperh); +ald_status_t ald_uart_dma_resume(ald_uart_handle_t *hperh); +ald_status_t ald_uart_dma_stop(ald_uart_handle_t *hperh); + +void ald_uart_irq_handler(ald_uart_handle_t *hperh); +void ald_uart_irq_handler_fast(ald_uart_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group3 + * @{ + */ +/* Peripheral Control functions */ +void ald_uart_interrupt_config(ald_uart_handle_t *hperh, ald_uart_it_t it, type_func_t state); +void ald_uart_dma_req_config(ald_uart_handle_t *hperh, ald_uart_dma_req_t req, type_func_t state); +void uart_lin_break_detect_irq(ald_uart_handle_t *hperh, type_func_t status); +void ald_uart_lin_send_break(ald_uart_handle_t *hperh); +void ald_uart_lin_detect_break_len_config(ald_uart_handle_t *hperh, ald_uart_lin_break_len_t len); +void ald_uart_auto_baud_config(ald_uart_handle_t *hperh, ald_uart_auto_baud_mode_t mode); +ald_status_t ald_uart_rs485_send_addr(ald_uart_handle_t *hperh, uint16_t addr, uint32_t timeout); +it_status_t ald_uart_get_it_status(ald_uart_handle_t *hperh, ald_uart_it_t it); +flag_status_t ald_uart_get_status(ald_uart_handle_t *hperh, ald_uart_status_t status); +flag_status_t ald_uart_get_flag_status(ald_uart_handle_t *hperh, ald_uart_flag_t flag); +flag_status_t ald_uart_get_mask_flag_status(ald_uart_handle_t *hperh, ald_uart_flag_t flag); +void ald_uart_clear_flag_status(ald_uart_handle_t *hperh, ald_uart_flag_t flag); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group4 + * @{ + */ +/* Peripheral State and Errors functions */ +ald_uart_state_t ald_uart_get_state(ald_uart_handle_t *hperh); +uint32_t ald_uart_get_error(ald_uart_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_UART_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_usb.c b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_usb.c new file mode 100644 index 0000000000..f7220c8b02 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_usb.c @@ -0,0 +1,1727 @@ +/** + ********************************************************************************* + * + * @file ald_usb.c + * @brief USB module driver. + * + * @version V1.0 + * @date 25 Feb 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 25 Feb 2022 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ +#include "ald_conf.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup USB USB + * @brief USB module driver + * @{ + */ +#ifdef ALD_USB +/** + * @defgroup USB_Public_Functions USB Public Function + * @{ + */ +/** @defgroup USB_Public_Functions_Group1 USB Base functions + * @brief USB Base functions + * @{ + */ + +/** + * @brief Gets the number of current frame. + * @retval Number of the frame. + */ +uint32_t ald_usb_frame_number_get(void) +{ + uint8_t framel = (uint8_t)USB->FRAME1; + uint8_t frameh = (uint8_t)USB->FRAME2; + return ((uint32_t)(framel & 0xFF) + ((uint32_t)(frameh & 0xFF) << 8)); +} + +/** + * @brief Request the session. + * @param start: true/false. + * @retval None + */ +void ald_usb_otg_session_request(bool start) +{ + if (start) + USB->DEVCON |= (uint8_t)ALD_USB_DEVCON_SESSION; + else + USB->DEVCON &= (uint8_t)(~(ALD_USB_DEVCON_SESSION)); + + return; +} + +/** + * @brief Gets the mode. + * @retval Mode + */ +uint32_t ald_usb_mode_get(void) +{ + return (USB->DEVCON & ((uint8_t)(ALD_USB_DEVCON_HOST | ALD_USB_DEVCON_SESSION))); +} + +/** + * @brief Start host require. + * @retval Mode + */ +uint32_t ald_usb_mode_host_req(void) +{ + USB->DEVCON |= (uint8_t)ALD_USB_DEVCON_HOSTREQ; + return 0; +} + +/** + * @brief Clear host require. + * @retval Mode + */ +uint32_t ald_usb_mode_host_req_clear(void) +{ + USB->DEVCON &= (uint8_t)(~ALD_USB_DEVCON_HOSTREQ); + return 0; +} + +/** + * @brief Enable/Disable the high mode. + * @param enable: ENABLE/DISABLE. + * @retval None + */ +void ald_usb_high_speed_enable(bool enable) +{ + assert_param(enable == DISABLE); + + return; +} + +/** + * @brief Gets the speed of the device. + * @retval Type of the speed. + */ +uint32_t ald_usb_device_speed_get(void) +{ + return ALD_USB_FULL_SPEED; +} + +/** + * @brief Gets the number of the endpoint. + * @retval Number of the endpoint. + */ +uint32_t ald_usb_num_ep_get(void) +{ + return ALD_NUM_USB_EP; +} + +/** + * @brief Reset USB Control. + * @retval None + */ +void ald_usb_control_reset(void) +{ + /*ALD_RCU_USB_RESET_ENABLE();*/ + + return; +} + +/** + * @brief Output USB clock, not support. + * @retval None + */ +void ald_usb_clock_output(void) +{ + return; +} + +/** + * @brief Starts eye diagram for high-speed host, not support. + * @param buf: Buffer for eye diagram. + * @param len: Length of the buffer. + * @retval Status, 0 means success, other values means failure. + */ +int ald_usb_eye_diagram_start(uint8_t *buf, uint16_t len) +{ + return 0; +} + +/** + * @brief Pull up or pull down USB dp line. + * @param pupd: USB_DPDM_FLOATING/USB_DPDM_PUSH_UP/USB_DPDM_PUSH_DOWN. + * @retval None + */ +void ald_usb_dppud_set(ald_dpdm_push_t pupd) +{ + USB->DPDMCON &= (uint8_t)(~USB_DPDMCON_DPPUD_MSK); + USB->DPDMCON |= (uint8_t)(pupd << USB_DPDMCON_DPPUD_POSS); + return; +} + +/** + * @brief Pull up or pull down USB dm line. + * @param pupd: USB_DPDM_FLOATING/USB_DPDM_PUSH_UP/USB_DPDM_PUSH_DOWN. + * @retval None + */ +void ald_usb_dmpud_set(ald_dpdm_push_t pupd) +{ + USB->DPDMCON &= (uint8_t)(~USB_DPDMCON_DMPUD_MSK); + USB->DPDMCON |= (uint8_t)(pupd << USB_DPDMCON_DMPUD_POSS); + return; +} + +/** + * @brief Switch the control method of CID. + * @param cid: 0, indicates that use the hardware control + cid: 1, indicates that use the software control. + * @retval None + */ +void ald_usb_swcid_cidctrl(uint8_t cid) +{ + if (cid) + USB->SWCID |= (uint8_t)(ALD_USB_SWCID_CIDCTRL); + else + USB->SWCID &= (uint8_t)(~ALD_USB_SWCID_CIDCTRL); + + return; +} + +/** + * @brief Switch usb mode by software. + * @param host: 0, indicates that software force to host + host: 1, indicates that software force to device. + * @retval None + */ +void ald_usb_swcid_host(uint8_t host) +{ + if (host) + USB->SWCID |= (uint8_t)(USB_SWCID_HOST_MSK); + else + USB->SWCID &= (uint8_t)(~USB_SWCID_HOST_MSK); + + return; +} + +/** + * @}USB_Public_Functions_Group1 + */ + +/** @defgroup USB_Public_Functions_Group2 USB Device functions + * @brief USB Device functions + * @{ + */ + +/** + * @brief Gets the address. + * @retval Address. + */ +uint8_t ald_usb_dev_get_addr(void) +{ + return (USB->FADDR); +} + +/** + * @brief Sets the address. + * @param addr: The address which will be set. + * @retval None + */ +void ald_usb_dev_set_addr(uint8_t addr) +{ + USB->FADDR = addr; + return; +} + +/** + * @brief Enable connection. + * @retval None + */ +void ald_usb_dev_connect(void) +{ + USB->DPDMCON |= (uint8_t)(ALD_USB_DPDMCON_PHYPWREN); + return; +} + +/** + * @brief Disable connection. + * @retval None + */ +void ald_usb_dev_disconnect(void) +{ + USB->DPDMCON &= (uint8_t)(~(ALD_USB_DPDMCON_PHYPWREN)); + return; +} + +/** + * @brief Enable the devices suspend. + * @retval None + */ +void ald_usb_dev_suspend_enable(void) +{ + USB->POWER |= (uint8_t)USB_POWER_SUSPENDEN_MSK; + return; +} + +/** + * @brief Configure the endpoint in device mode. + * @param ep_idx: Index of the endpoint + * @param p_max: Size of the maximum package. + * @param flags: Flags of the endpoint. + * @retval None + */ +void ald_usb_dev_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t flags) +{ + uint32_t tmp = 0U; + + USB->INDEX = (uint8_t)ep_idx; + + if (flags & ALD_USB_EP_DEV_IN) + { + USB->TXMAXP = (uint8_t)(p_max); + + if (flags & ALD_USB_EP_AUTO_SET) + tmp |= USB_TXCSRH_AUTOSET_MSK; + + if ((flags & ALD_USB_EP_MODE_MASK) == ALD_USB_EP_MODE_ISOC) + tmp |= USB_TXCSRH_ISO_MSK; + + USB->CSR0H_TXCSRH |= (uint8_t)tmp; + USB->CSR0L_TXCSRL |= (uint8_t)USB_TXCSRL_CLRDT_MSK; + } + else + { + USB->RXMAXP = (uint8_t)(p_max); + + if (flags & ALD_USB_EP_AUTO_CLEAR) + tmp |= USB_RXCSRH_AUTOCLR_MSK; + + if ((flags & ALD_USB_EP_MODE_MASK) == ALD_USB_EP_MODE_ISOC) + tmp |= USB_TXCSRH_ISO_MSK; + + USB->RXCSRH |= (uint8_t)tmp; + USB->RXCSRL |= (uint8_t)USB_RXCSRL_CLRDT_MSK; + } + + return; +} + +/** + * @brief Gets the parameters of the endpoint. + * @param ep_idx: Index of the endpoint + * @param p_max: Size of the maximum package. + * @param flags: Flags of the endpoint. + * @retval None + */ +void ald_usb_dev_ep_get_config(uint32_t ep_idx, uint32_t *p_max, uint32_t *flags) +{ + uint32_t tmp; + + USB->INDEX = (uint8_t)ep_idx; + + if (*flags & ALD_USB_EP_DEV_IN) + { + *flags = ALD_USB_EP_DEV_IN; + *p_max = (uint32_t)USB->TXMAXP; + tmp = (uint32_t)USB->CSR0H_TXCSRH; + + if (tmp & USB_TXCSRH_AUTOSET_MSK) + *flags |= ALD_USB_EP_AUTO_SET; + + if (tmp & USB_TXCSRH_ISO_MSK) + *flags |= ALD_USB_EP_MODE_ISOC; + else + *flags |= ALD_USB_EP_MODE_BULK; + } + else + { + *flags = ALD_USB_EP_DEV_OUT; + *p_max = (uint32_t)USB->RXMAXP; + tmp = (uint32_t)USB->RXCSRH; + + if (tmp & USB_RXCSRH_AUTOCLR_MSK) + *flags |= ALD_USB_EP_AUTO_CLEAR; + + if (tmp & USB_RXCSRH_ISO_MSK) + *flags |= ALD_USB_EP_MODE_ISOC; + else + *flags |= ALD_USB_EP_MODE_BULK; + } + + return; +} + +/** + * @brief Acknowledge the data from host. + * @param ep_idx: Index of the endpoint + * @param last: true/false + * @retval None + */ +void ald_usb_dev_ep_data_ack(uint32_t ep_idx, bool last) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + USB->CSR0L_TXCSRL |= (uint8_t)(USB_CSR0L_RXRDYC_MSK | (last ? USB_CSR0L_DATAEND_MSK : 0)); + else + USB->RXCSRL &= (uint8_t)(~USB_RXCSRL_RXRDY_MSK); + + return; +} + +/** + * @brief Stall the endpoint. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_dev_ep_stall(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + USB->CSR0L_TXCSRL |= (uint8_t)(USB_CSR0L_RXRDYC_MSK | USB_CSR0L_STALL_MSK); + else if (flags == ALD_USB_EP_DEV_IN) + USB->CSR0L_TXCSRL |= (uint8_t)USB_TXCSRL_STALL_MSK; + else + USB->RXCSRL |= (uint8_t)USB_RXCSRL_STALL_MSK; + + return; +} + +/** + * @brief Cancel the stall status. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_dev_ep_stall_clear(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + USB->CSR0L_TXCSRL &= (uint8_t)(~USB_CSR0L_STALLED_MSK); + else if (flags == ALD_USB_EP_DEV_IN) + { + USB->CSR0L_TXCSRL &= (uint8_t)(~(USB_TXCSRL_STALL_MSK | USB_TXCSRL_STALLED_MSK)); + USB->CSR0L_TXCSRL |= (uint8_t)USB_TXCSRL_CLRDT_MSK; + } + else + { + USB->RXCSRL &= (uint8_t)(~(USB_RXCSRL_STALL_MSK | USB_RXCSRL_STALLED_MSK)); + USB->RXCSRL |= (uint8_t)USB_RXCSRL_CLRDT_MSK; + } + + return; +} + +/** + * @brief Clear the status of the endpoint. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_dev_ep_status_clear(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + { + if (flags & ALD_USB_DEV_EP0_OUT_PKTRDY) + USB->CSR0L_TXCSRL |= (uint8_t)USB_CSR0L_RXRDYC_MSK; + + if (flags & ALD_USB_DEV_EP0_SETUP_END) + USB->CSR0L_TXCSRL |= (uint8_t)USB_CSR0L_SETENDC_MSK; + + if (flags & ALD_USB_DEV_EP0_SENT_STALL) + USB->CSR0L_TXCSRL &= (uint8_t)(~USB_CSR0L_STALLED_MSK); + } + else + { + USB->CSR0L_TXCSRL &= (uint8_t)(~(flags & (ALD_USB_DEV_TX_SENT_STALL | ALD_USB_DEV_TX_UNDERRUN))); + USB->RXCSRL &= (uint8_t)(~((flags & (ALD_USB_DEV_RX_SENT_STALL | ALD_USB_DEV_RX_DATA_ERROR + | ALD_USB_DEV_RX_OVERRUN)) >> ALD_USB_RX_EPSTATUS_SHIFT)); + } + + return; +} + +/** + * @}USB_Public_Functions_Group2 + */ + +/** @defgroup USB_Public_Functions_Group3 USB Host functions + * @brief USB Host functions + * @{ + */ +/** + * @brief Gets the device's address. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval Address + */ +uint32_t ald_usb_host_addr_get(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + return (USB->FADDR); +} + +/** + * @brief Sets the device's address. + * @param ep_idx: Index of the endpoint. + * @param addr: The device's address. + * @param flags: Flags. + * @retval None + */ +void ald_usb_host_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + USB->FADDR = (uint8_t)addr; + + return; +} + +/** + * @brief Configure the endpoint in host mode. + * @param ep_idx: Index of the endpoint. + * @param p_max: Size of the maximum package. + * @param nak_val: Value of the nack. + * @param t_ep: Target endpoint. + * @param flags: Flags. + * @retval None + */ +void ald_usb_host_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t nak_val, uint32_t t_ep, uint32_t flags) +{ + uint32_t tmp = 0U; + + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + { + USB->NAKLIMIT0_TXINTERVAL = (uint8_t)nak_val; + + if (flags & ALD_USB_EP_SPEED_HIGH) + ; + else if (flags & ALD_USB_EP_SPEED_FULL) + ; + else + ; + } + else + { + tmp = t_ep; + + if (flags & ALD_USB_EP_SPEED_HIGH) + ; + else if (flags & ALD_USB_EP_SPEED_FULL) + ; + else + ; + + switch (flags & ALD_USB_EP_MODE_MASK) + { + case ALD_USB_EP_MODE_BULK: + tmp |= ALD_USB_TXTYPE1_PROTO_BULK; + break; + + case ALD_USB_EP_MODE_ISOC: + tmp |= ALD_USB_TXTYPE1_PROTO_ISOC; + break; + + case ALD_USB_EP_MODE_INT: + tmp |= ALD_USB_TXTYPE1_PROTO_INT; + break; + + case ALD_USB_EP_MODE_CTRL: + tmp |= ALD_USB_TXTYPE1_PROTO_CTRL; + break; + + default: + break; + } + + if (flags & ALD_USB_EP_HOST_OUT) + { + USB->TXTYPE = (uint8_t)tmp; + USB->NAKLIMIT0_TXINTERVAL = (uint8_t)nak_val; + USB->TXMAXP = (uint8_t)p_max; + + tmp = 0; + + if (flags & ALD_USB_EP_AUTO_SET) + tmp = (uint8_t)ALD_USB_TXCSRH_AUTOSET; + + USB->CSR0H_TXCSRH |= (uint8_t)tmp; + } + else + { + USB->RXTYPE = (uint8_t)tmp; + USB->RXINTERVAL = (uint8_t)nak_val; + USB->RXMAXP = (uint8_t)p_max; + + tmp = 0; + + if (flags & ALD_USB_EP_AUTO_CLEAR) + tmp |= (uint8_t)USB_RXCSRH_AUTOCLR_MSK; + + if (flags & ALD_USB_EP_AUTO_REQUEST) + tmp |= (uint8_t)USB_RXCSRH_AUTOREQ_MSK; + + USB->RXCSRH |= (uint8_t)tmp; + } + } + + return; +} + +/** + * @brief Acknowledge the data in host mode. + * @param ep_idx: Index of the endpoint. + * @retval None + */ +void ald_usb_host_ep_data_ack(uint32_t ep_idx) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + USB->CSR0L_TXCSRL &= (uint8_t)(~(USB_CSR0L_RXRDY_MSK)); + else + USB->RXCSRL &= (uint8_t)(~(USB_RXCSRL_RXRDY_MSK)); + + return; +} + +/** + * @brief Toggle the data in host mode. + * The function is used to force the state of the data toggle in host mode. + * If the value passed in the bDataToggle parameter is false, then the data + * toggle is set to the DATA0 state, and if it is true it is set to the DATA1 + * state. + * @param ep_idx: Index of the endpoint. + * @param toggle: true/false. + * @param flags: can be USB_EP_HOST_IN or USB_EP_HOST_OUT. + * @retval None + */ +void ald_usb_host_ep_data_toggle(uint32_t ep_idx, bool toggle, uint32_t flags) +{ + /* not supported by es32f0271. */ + return; +} + +/** + * @brief Clear the status of endpoint in host mode. + * @param ep_idx: Index of the endpoint. + * @param flags: Flags. + * @retval None + */ +void ald_usb_host_ep_status_clear(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + { + USB->CSR0L_TXCSRL &= (uint8_t)(~flags & 0xFF); + } + else + { + USB->CSR0L_TXCSRL &= (uint8_t)(~flags & 0xFF); + USB->RXCSRL &= (uint8_t)(~(flags >> 16) & 0xFF); + } + + return; +} + +/** + * @brief Gets the HUB's address. + * @param ep_idx: Index of the endpoint. + * @param flags: Flags. + * @retval Address + */ +uint32_t ald_usb_host_hub_addr_get(uint32_t ep_idx, uint32_t flags) +{ + /* not supported by es32f0271. */ + return 0; +} + +/** + * @brief Sets the HUB's address. + * @param ep_idx: Index of the endpoint. + * @param addr: HUB's address which will be set. + * @param flags: Flags. + * @retval Address + */ +void ald_usb_host_hub_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags) +{ + /* not supported by es32f0271. */ + return; +} + +/** + * @brief Disable power. + * @retval None + */ +void ald_usb_host_pwr_disable(void) +{ + USB->DPDMCON &= (uint8_t)(~(ALD_USB_DPDMCON_PHYPWREN)); + return; +} + +/** + * @brief Enable power. + * @retval None + */ +void ald_usb_host_pwr_enable(void) +{ + USB->DPDMCON |= (uint8_t)(ALD_USB_DPDMCON_PHYPWREN); + return; +} + +/** + * @brief Configure power in host mode. + * @param flags: Flags + * @retval None + */ +void ald_usb_host_pwr_config(uint32_t flags) +{ + return; +} + +/** + * @brief Disable the fault parameters of the power. + * @retval None + */ +void ald_usb_host_pwr_fault_disable(void) +{ + return; +} + +/** + * @brief Enable the fault parameters of the power. + * @retval None + */ +void ald_usb_host_pwr_fault_enable(void) +{ + return; +} + +/** + * @brief Request data IN(from device to host) + * @param ep_idx: Index of the endpoint. + * @retval None + */ +void ald_usb_host_request_in(uint32_t ep_idx) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + USB->CSR0L_TXCSRL |= (uint8_t)USB_CSR0L_REQPKT_MSK; + else + USB->RXCSRL |= (uint8_t)USB_RXCSRL_REQPKT_MSK; + + return; +} + +/** + * @brief Clear the status of request IN. + * @param ep_idx: Index of the endpoint. + * @retval None + */ +void ald_usb_host_request_in_clear(uint32_t ep_idx) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + USB->CSR0L_TXCSRL &= (uint8_t)(~USB_CSR0L_REQPKT_MSK); + else + USB->RXCSRL &= (uint8_t)(~USB_RXCSRL_REQPKT_MSK); + + return; +} + +/** + * @brief Set the request for a status IN transaction. + * @retval None + */ +void ald_usb_host_request_status(void) +{ + USB->CSR0L_TXCSRL |= (uint8_t)(ALD_USB_CSR0L_REQPKT | ALD_USB_CSR0L_STATUSPKT); + + return; +} + +/** + * @brief Reset the USB's bus. + * @param start: true/false. + * @retval None + */ +void ald_usb_host_reset(bool start) +{ + if (start) + USB->POWER |= ALD_USB_POWER_RESET; + else + USB->POWER &= ~(ALD_USB_POWER_RESET); + + return; +} + +/** + * @brief Resume the devices. + * @param start: true/false. + * @retval None + */ +void ald_usb_host_resume(bool start) +{ + if (start) + USB->POWER |= (uint8_t)USB_POWER_RESUME_MSK; + else + USB->POWER &= (uint8_t)(~(ALD_USB_POWER_RESUME)); + + return; +} + +/** + * @brief Suspend the devices. + * @retval None + */ +void ald_usb_host_suspend(void) +{ + USB->POWER |= (uint8_t)USB_POWER_SUSPEND_MSK; + return; +} + +/** + * @brief Gets the device's speed. + * @retval Type of the speed. + */ +uint32_t ald_usb_host_speed_get(void) +{ + if (USB->DEVCON & ALD_USB_DEVCON_FSDEV) + return ALD_USB_FULL_SPEED; + + if (USB->DEVCON & ALD_USB_DEVCON_LSDEV) + return ALD_USB_LOW_SPEED; + + return ALD_USB_UNDEF_SPEED; +} + +/** + * @brief Sets the endpoint speed. + * @param ep_idx: Index of the endpoint. + * @param flags: Type of the speed. + * @retval None + */ +void ald_usb_host_ep_speed_set(uint32_t ep_idx, uint32_t flags) +{ + /* not support in F0271 */ + return; +} + +/** + * @brief Ping the endpoint. + * @param ep_idx: Index of the endpoint. + * @param enable: ENABLE/DISABLE. + * @retval None + */ +void ald_usb_host_ep_ping(uint32_t ep_idx, bool enable) +{ + /* not support in F0271 */ + return; +} + +/** + * @}USB_Public_Functions_Group3 + */ + +/** @defgroup USB_Public_Functions_Group4 USB Endpoint functions + * @brief USB Endpoint functions + * @{ + */ +/** + * @brief Gets the size of the available data. + * @param ep_idx: Index of the endpoint + * @retval Size in bytes. + */ +uint32_t ald_usb_ep_data_avail(uint32_t ep_idx) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + { + if ((USB->CSR0L_TXCSRL & ALD_USB_CSR0L_RXRDY) == 0) + { + return 0; + } + + return USB->COUNT0_RX1; + } + else + { + if ((USB->RXCSRL & ALD_USB_CSR0L_RXRDY) == 0) + { + return 0; + } + + return (USB->COUNT0_RX1 + (((uint32_t)USB->RXCOUNT2) << 8)); + } +} + +/** + * @brief Gets the data from FIFO. + * @param ep_idx: Index of the endpoint + * @param data: Pointer to the buffer. + * @param size: Size of the data. + * @retval Status. + */ +int32_t ald_usb_ep_data_get(uint32_t ep_idx, uint8_t *data, uint32_t *size) +{ + uint32_t i, rx_fifo_addr; + + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + { + if ((USB->CSR0L_TXCSRL & ALD_USB_CSR0L_RXRDY) == 0) + { + *size = 0; + return -1; + } + + i = USB->COUNT0_RX1; + } + else + { + if ((USB->RXCSRL & ALD_USB_CSR0L_RXRDY) == 0) + { + *size = 0; + return -1; + } + + i = USB->COUNT0_RX1 + (((uint32_t)USB->RXCOUNT2) << 8); + } + + i = (i < *size) ? i : *size; + *size = i; + + rx_fifo_addr = (uint32_t)(&USB->EP0FIFO) + 4 * ep_idx; + + for (; i > 0; i--) + *data++ = *(volatile uint8_t *)(rx_fifo_addr); + + return 0; +} + +/** + * @brief Puts data to the FIFO. + * @param ep_idx: Index of the endpoint + * @param data: Pointer to the data. + * @param size: Size of the data. + * @retval Status. + */ +int32_t ald_usb_ep_data_put(uint32_t ep_idx, uint8_t *data, uint32_t size) +{ + uint32_t tx_fifo_addr; + + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + { + if (USB->CSR0L_TXCSRL & ALD_USB_CSR0L_TXRDY) + return -1; + } + else + { + if (USB->CSR0L_TXCSRL & ALD_USB_TXCSRL_TXRDY) + return -1; + } + + tx_fifo_addr = (uint32_t)(&USB->EP0FIFO) + 4 * ep_idx; + + for (; size > 0; size--) + *(volatile uint8_t *)tx_fifo_addr = *data++; + + return 0; +} + +/** + * @brief Send data. + * @param ep_idx: Index of the endpoint + * @param tx_type: Type. + * @retval Status. + */ +int32_t ald_usb_ep_data_send(uint32_t ep_idx, uint32_t tx_type) +{ + uint32_t tmp; + + USB->INDEX = (uint8_t)ep_idx; + + if (ep_idx == ALD_USB_EP_0) + { + if (USB->CSR0L_TXCSRL & ALD_USB_CSR0L_TXRDY) + return -1; + + tmp = tx_type & 0xFF; + } + else + { + if (USB->CSR0L_TXCSRL & ALD_USB_TXCSRL_TXRDY) + return -1; + + tmp = (tx_type >> 8) & 0xff; + } + + USB->CSR0L_TXCSRL = tmp; + + return 0; +} + +/** + * @brief Clear the status of the toggle. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_ep_data_toggle_clear(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = (uint8_t)ep_idx; + + if (flags & (ALD_USB_EP_HOST_OUT | ALD_USB_EP_DEV_IN)) + USB->CSR0L_TXCSRL |= (uint8_t)ALD_USB_TXCSRL_CLRDT; + else + USB->RXCSRL |= (uint8_t)ALD_USB_RXCSRL_CLRDT; + + return; +} + +/** + * @brief Sets the size of request data IN + * @param ep_idx: Index of the endpoint + * @param count: Size of request data IN. + * @retval None + */ +void ald_usb_ep_req_packet_count(uint32_t ep_idx, uint32_t count) +{ + /* not support in f0271 */ + return; +} + +/** + * @brief Gets the status of the endpoint. + * @param ep_idx: Index of the endpoint + * @retval Status. + */ +uint32_t ald_usb_ep_status(uint32_t ep_idx) +{ + uint32_t status; + + USB->INDEX = (uint8_t)ep_idx; + + status = (ep_idx == ALD_USB_EP_0) ? (USB->CSR0L_TXCSRL) : (USB->CSR0L_TXCSRL | (USB->RXCSRL << 16)); + + return status; +} + +/** + * @brief Configure the endpoint in DMA mode. + * @param ep_idx: Index of the endpoint + * @param flag: Flags. + * @param en: ENABLE/DISABLE. + * @retval None + */ +void ald_usb_ep_dma_config(uint32_t ep_idx, uint32_t flag, type_func_t en) +{ + /* Not supported in F0271 */ + + return; +} +/** + * @}USB_Public_Functions_Group4 + */ + +/** @defgroup USB_Public_Functions_Group5 USB FIFO functions + * @brief USB FIFO functions + * @{ + */ +/** + * @brief Gets the address of the FIFO. + * @param ep_idx: Index of the endpoint + * @retval Address + */ +uint32_t ald_usb_fifo_addr_get(uint32_t ep_idx) +{ + /* Not supported in F0271 */ + + return 0; +} + +/** + * @brief Gets the parameters of the FIFO. + * @param ep_idx: Index of the endpoint + * @param addr: Address. + * @param size: Size of FIFO. + * @param flags: Flags. + * @retval None + */ +void ald_usb_fifo_config_get(uint32_t ep_idx, uint32_t *addr, uint32_t *size, uint32_t flags) +{ + USB->INDEX = ep_idx; + + if (flags & (ALD_USB_EP_HOST_OUT | ALD_USB_EP_DEV_IN)) + { + *addr = ((uint32_t)USB->TXFIFO1 | ((uint32_t)USB->TXFIFO2 & 0x03)) << 3; + *size = ((USB->TXFIFO2 & ALD_USB_TXFIFO2_DPB) == 0x00) ? (USB->TXFIFO2 & ALD_USB_TXFIFO2_MAXPKTSIZE_1024) : (2 * (USB->TXFIFO2 & ALD_USB_TXFIFO2_MAXPKTSIZE_1024)); + } + else + { + *addr = ((uint32_t)USB->RXFIFO1 | ((uint32_t)USB->RXFIFO2 & 0x03)) << 3; + *size = ((USB->RXFIFO2 & ALD_USB_RXFIFO2_DPB) == 0x00) ? (USB->RXFIFO2 & ALD_USB_RXFIFO2_MAXPKTSIZE_1024) : (2 * (USB->RXFIFO2 & ALD_USB_RXFIFO2_MAXPKTSIZE_1024)); + } + + return; +} + +/** + * @brief Sets the parameters of the FIFO. + * @param ep_idx: Index of the endpoint + * @param addr: Address. + * @param size: Size of FIFO, valid parameter has defined in usb_lowlayer_api.h. + * @param flags: Flags. + * @retval None + */ +void ald_usb_fifo_config_set(uint32_t ep_idx, uint32_t addr, uint32_t size, uint32_t flags) +{ + USB->INDEX = ep_idx; + + if (flags & (ALD_USB_EP_HOST_OUT | ALD_USB_EP_DEV_IN)) + { + USB->TXFIFO1 = (uint8_t)((addr >> 3) & 0xFF); + USB->TXFIFO2 |= (uint8_t)(((addr >> 3) >> 8) & 0x0F); + + USB->TXFIFO2 |= (uint8_t)(size << USB_TXFIFO2_MAXPKTSIZE_POSS); + + USB->CSR0L_TXCSRL |= (uint8_t)ALD_USB_TXCSRL_FLUSH; + } + else + { + USB->RXFIFO1 = (uint8_t)((addr >> 3) & 0xFF); + USB->RXFIFO2 |= (uint8_t)(((addr >> 3) >> 8) & 0x0F); + + USB->RXFIFO2 |= (uint8_t)(size << USB_RXFIFO2_MAXPKTSIZE_POSS); + + USB->RXCSRL |= (uint8_t)ALD_USB_RXCSRL_FLUSH; + } + + return; +} + +/** + * @brief Flush the FIFO + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_fifo_flush(uint32_t ep_idx, uint32_t flags) +{ + USB->INDEX = ep_idx; + + if (ep_idx == ALD_USB_EP_0) + { + if ((USB->CSR0L_TXCSRL & (ALD_USB_CSR0L_RXRDY | ALD_USB_CSR0L_TXRDY)) != 0) + USB->CSR0H_TXCSRH |= ALD_USB_CSR0H_FLUSH; + } + else + { + if (flags & (ALD_USB_EP_HOST_OUT | ALD_USB_EP_DEV_IN)) + { + if (USB->CSR0L_TXCSRL & ALD_USB_TXCSRL_TXRDY) + USB->CSR0L_TXCSRL |= ALD_USB_TXCSRL_FLUSH; + } + else + { + if (USB->RXCSRL & ALD_USB_RXCSRL_RXRDY) + USB->RXCSRL |= ALD_USB_RXCSRL_FLUSH; + } + } + + return; +} + +/** + * @}USB_Public_Functions_Group5 + */ + +/** @defgroup USB_Public_Functions_Group6 USB Interrupt functions + * @brief USB Interrupt functions + * @{ + */ +/** + * @brief Disable interrupt. + * @param flags: Type of the interrupt. + * @retval None + */ +void ald_usb_int_disable(uint32_t flags) +{ + if (flags & ALD_USB_IDR_STATUS) + USB->IDR |= (uint8_t)(flags & ALD_USB_IDR_STATUS); + + return; +} + +/** + * @brief Enable interrupt. + * @param flags: Type of the interrupt. + * @retval None + */ +void ald_usb_int_enable(uint32_t flags) +{ + if (flags & ALD_USB_IER_STATUS) + USB->IER |= (uint8_t)(flags & ALD_USB_IER_STATUS); + + return; +} + +/** + * @brief Gets the status of the interrupt. + * @retval Status. + */ +uint32_t ald_usb_int_status_get(void) +{ + uint32_t Status; + + Status = USB->IFM & 0x7F; + USB->ICR |= Status; + + return Status; +} + +/** + * @brief Disable interrupt of the endpoint. + * @param flags: Type of the interrupt. + * @retval None + */ +void ald_usb_int_disable_ep(uint32_t flags) +{ + USB->TXIDR |= (uint8_t)(flags & (ALD_USB_INTEP_HOST_OUT | ALD_USB_INTEP_DEV_IN | ALD_USB_INTEP_0)); + USB->RXIDR |= (uint8_t)((flags & (ALD_USB_INTEP_HOST_IN | ALD_USB_INTEP_DEV_OUT)) >> ALD_USB_INTEP_RX_SHIFT); + return; +} + +/** + * @brief Enable interrupt of the endpoint. + * @param flags: Type of the interrupt. + * @retval None + */ +void ald_usb_int_enable_ep(uint32_t flags) +{ + USB->TXIER |= (uint8_t)(flags & (ALD_USB_INTEP_HOST_OUT | ALD_USB_INTEP_DEV_IN | ALD_USB_INTEP_0)); + USB->RXIER |= (uint8_t)((flags & (ALD_USB_INTEP_HOST_IN | ALD_USB_INTEP_DEV_OUT)) >> ALD_USB_INTEP_RX_SHIFT); + return; +} + +/** + * @brief Gets the ststus of the endpoint interrupt. + * @retval Status. + */ +uint32_t ald_usb_int_status_ep_get(void) +{ + uint32_t status; + + status = USB->TXIFM; + status |= (USB->RXIFM << ALD_USB_INTEP_RX_SHIFT); + + USB->TXICR |= (uint8_t)(status & 0xFF); + USB->RXICR |= (uint8_t)((status >> ALD_USB_INTEP_RX_SHIFT) & 0xFF); + + return status; +} + +/** + * @brief Register USB's interrupt. + * @retval None + */ +void ald_usb_int_register(void) +{ + /*ald_mcu_irq_config(USB_IRQn, 2, ENABLE);*/ + csi_vic_set_prio(USB_IRQn, 0); + csi_vic_enable_sirq(USB_IRQn); + return; +} + +/** + * @brief Unregister USB's interrupt. + * @retval None + */ +void ald_usb_int_unregister(void) +{ + /*ald_mcu_irq_config(USB_IRQn, 2, DISABLE);*/ + csi_vic_disable_sirq(USB_IRQn); + return; +} + +/** + * @brief Get USB's interrupt number. + * @retval None + */ +uint32_t ald_usb_int_num_get(void) +{ + return USB_IRQn; +} +/** + * @}USB_Public_Functions_Group6 + */ + +/** @defgroup USB_Public_Functions_Group7 USB DMA functions + * @brief USB DMA functions + * @{ + */ +#if defined(__ALD_MDA_H__) +/** + * @brief Configure DMA's channel. + * @param ch: Channel. + * @param addr: Address. + * @param count: Size of the data to be moved. + * @param ctrl: Parameters of the DMA's controler + * @retval None + */ +void ald_usb_dma_channel_config(uint8_t ch, uint32_t addr, uint32_t count, uint32_t ctrl) +{ + return; +} + +/** + * @brief Start multiple receive. + * @param ep_idx: Index of the endpoint + * @retval None + */ +void ald_usb_dma_mult_recv_start(uint32_t ep_idx) +{ + return; +} + +/** + * @brief Start DMA's machine. + * @param ch: Channel. + * @retval None + */ +void ald_usb_dma_channel_start(uint8_t ch) +{ + return; +} + +/** + * @brief Stop DMA's machine. + * @param ch: Channel. + * @retval None + */ +void ald_usb_dma_channel_stop(uint8_t ch) +{ + return; +} + +/** + * @brief Gets flags of the interrupt. + * @retval Flags of the interrupt. + */ +uint32_t ald_usb_dma_get_interrupt_flag(void) +{ + return; +} + +/** + * @brief Gets the status of the error. + * @param ch: Channel. + * @retval Status. + */ +uint32_t ald_usb_dma_get_channel_error(uint8_t ch) +{ + return 0; +} + +/** + * @brief Clear the status of the error. + * @param ch: Channel. + * @retval None + */ +void ald_usb_dma_clear_channel_error(uint8_t ch) +{ + return; +} + +#endif/*defined(__ALD_MDA_H__)*/ +/** + * @}USB_Public_Functions_Group7 + */ + +/** @defgroup USB_Public_Functions_Group8 USB LPM functions + * @brief USB LPM functions + * @{ + */ +/** + * @brief Gets status of remote wakeup. + * @retval Status. + */ +uint32_t ald_usb_lpm_remote_wake_is_enable(void) +{ + return 1; +} + +/** + * @brief Gets the link status + * @retval Status + */ +uint32_t ald_usb_lpm_link_status_get(void) +{ + return 0; +} + +/** + * @brief Gets the index of the endpoint. + * @retval Index of the endpoint. + */ +uint32_t ald_usb_lpm_ep_get(void) +{ + return 0; +} + +/** + * @brief Gets the status of the interrupt. + * @retval Status. + */ +uint32_t ald_usb_lpm_int_status_get(void) +{ + return 0; +} + +/** + * @brief Disable the LPM interrupt. + * @retval None + */ +void ald_usb_lpm_int_disable(uint32_t ints) +{ + return; +} + +/** + * @brief Enable the LPM interrupt. + * @retval None + */ +void ald_usb_lpm_int_enable(uint32_t ints) +{ + return; +} + +/** + * @brief Transmit a LPM transaction in host mode. + * @param addr: Address. + * @param ep_idx: Index of the endpoint. + * @retval None + */ +void ald_usb_host_lpm_send(uint32_t addr, uint32_t ep_idx) +{ + return; +} + +/** + * @brief Configure the LPM parameters in host mode. + * @param resume_time: Resume time. + * @param config: Parameters + * @retval None + */ +void ald_usb_host_lpm_config(uint32_t resume_time, uint32_t config) +{ + return; +} + +/** + * @brief Initiate a RESUME from the L1 state in host mode. + * @retval None + */ +void ald_usb_host_lpm_resume(void) +{ + return; +} + +/** + * @brief Enable remote wakeup in device mode. + * @retval None + */ +void ald_usb_dev_lpm_remote_wake(void) +{ + return; +} + +/** + * @brief Enable remote wakeup in device mode. + * @retval None + */ +void ald_usb_dev_lpm_config(uint32_t config) +{ + return; +} + +/** + * @brief Enable LPM in device mode. + * @retval None + */ +void ald_usb_dev_lpm_enable(void) +{ + return; +} + +/** + * @brief Disable LPM in device mode. + * @retval None + */ +void ald_usb_dev_lpm_disable(void) +{ + return; +} + +/** + * @}USB_Public_Functions_Group8 + */ + +/** @defgroup USB_Public_Functions_Group9 USB SWVBUS control functions + * @brief USB SWVBUS control functions + * @{ + */ +/** + * @brief Selet the control mode of VBUS. + * @param sigctl: 0, indicates that use the hardware control + * sigctl: 1, indicates that use the software control. + * @retval Status. + */ +void ald_usb_swvbus_sigctl_set(uint8_t sigctl) +{ + if (sigctl == 1) + { + USB->SWVBUS |= 0x01 << 0; + } + else + { + USB->SWVBUS &= ~(0x01 << 0); + } + + return; +} + +/** + * @brief Selet the control mode of VBUS. + * @param None. + * @retval Status: 0, indicates that use the hardware control + * Status: 1, indicates that use the software control. + */ +uint8_t ald_usb_swvbus_sigctl_get(void) +{ + return (USB->SWVBUS & (0x01 << 0)); +} + +/** + * @brief Set session end threshold. + * @param thd: 0, indicates that lower than the session end threshold + * thd: 1, indicates that higher than the session end threshold. + * @retval Status. + */ +void ald_usb_swvbus_sesendth_set(uint8_t thd) +{ + if (thd == 1) + { + USB->SWVBUS |= 0x01 << 1; + } + else + { + USB->SWVBUS &= ~(0x01 << 1); + } + + return; +} + +/** + * @brief Set session end threshold. + * @param None. + * @retval Status: 0, indicates that lower than the session end threshold + * Status: 1, indicates that higher than the session end threshold. + */ +uint8_t ald_usb_swvbus_sesendth_get(void) +{ + return (USB->SWVBUS & (0x01 << 1)); +} + +/** + * @brief Set session valid threshold. + * @param thd: 0, indicates that lower than the session valid threshold + thd: 1, indicates that higher than the session valid threshold. + * @retval Status. + */ +void ald_usb_swvbus_sesvalth_set(uint8_t thd) +{ + if (thd == 1) + { + USB->SWVBUS |= 0x01 << 2; + } + else + { + USB->SWVBUS &= ~(0x01 << 2); + } + + return; +} + +/** + * @brief Set session valid threshold. + * @param None. + * @retval Status: 0, indicates that lower than the session valid threshold + Status: 1, indicates that higher than the session valid threshold. + */ +uint8_t ald_usb_swvbus_sesvalth_get(void) +{ + return (USB->SWVBUS & (0x01 << 2)); +} + +/** + * @brief Set VBUS valid threshold. + * @param thd: 0, indicates that lower than the vbus valid threshold + thd: 1, indicates that higher than the vbus valid threshold. + * @retval Status. + */ +void ald_usb_swvbus_valth_set(uint8_t thd) +{ + if (thd == 1) + { + USB->SWVBUS |= 0x01 << 3; + } + else + { + USB->SWVBUS &= ~(0x01 << 3); + } + + return; +} + +/** + * @brief Set VBUS valid threshold. + * @param None. + * @retval Status: 0, indicates that lower than the vbus valid threshold + Status:thd: 1, indicates that higher than the vbus valid threshold. + */ +uint8_t ald_usb_swvbus_valth_get(void) +{ + return (USB->SWVBUS & (0x01 << 3)); +} + +/** + * @}USB_Public_Functions_Group9 + */ + +/** @defgroup USB_Public_Functions_Group10 USB components initialization functions + * @brief USB components initialization functions + * @{ + */ +/** + * @brief Initialize usb host components. + * @retval None + */ +void ald_usb_host_components_init(void) +{ + WRITE_REG(SYSCFG->PROT, 0x55AA6996U); + RMU->AHB1RSTR |= 0x40; + RMU->AHB1RSTR &= 0xFFFFFFBF; + WRITE_REG(SYSCFG->PROT, 0x0); + + /* Config EP0 */ + ald_usb_host_ep_config(ALD_USB_EP_0, 64, 0, 0, (ALD_USB_EP_MODE_CTRL | ALD_USB_EP_SPEED_FULL | ALD_USB_EP_HOST_OUT)); + + /* Clear interrupts */ + + /* Enable PHY power */ + ald_usb_host_pwr_enable(); + /* clear hnp session */ + ald_usb_otg_session_request(false); + + /* set vbus control mode and threshold value */ + ald_usb_swvbus_sigctl_set(1); + ald_usb_swvbus_sesendth_set(1); + ald_usb_swvbus_sesvalth_set(1); + ald_usb_swvbus_valth_set(1); + /* Pull down DP and DM */ + ald_usb_dppud_set(ALD_USB_DPDM_PUSH_DOWN); + ald_usb_dmpud_set(ALD_USB_DPDM_PUSH_DOWN); + /* software control CID */ + ald_usb_swcid_cidctrl(1); + /* force to host mode */ + ald_usb_swcid_host(0); + /* start host request */ + ald_usb_mode_host_req(); + /* Start hnp */ + ald_usb_otg_session_request(true); + + /* Clear interrupts */ + ald_usb_int_status_get(); + /* Init interrupts */ + ald_usb_int_enable(ALD_USB_INTCTRL_SESSION | ALD_USB_INTCTRL_DISCONNECT | ALD_USB_INTCTRL_CONNECT | ALD_USB_INTCTRL_SOF | + ALD_USB_INTCTRL_BABBLE | ALD_USB_INTCTRL_RESUME); + ald_usb_int_enable_ep(ALD_USB_INTEP_ALL); + ald_usb_int_register(); + + return; +} + +/** + * @brief Initialize usb device components. + * @retval None + */ +void ald_usb_device_components_init(void) +{ + ald_usb_otg_session_request(true); + ald_usb_dppud_set(ALD_USB_DPDM_PUSH_UP); + /* software control CID */ + ald_usb_swcid_cidctrl(1); + /* force to dev mode */ + ald_usb_swcid_host(1); + ald_usb_dev_suspend_enable(); + + return; +} + +/** + * @}USB_Public_Functions_Group10 + */ + +/** + * @}USB_Public_Functions + */ +#endif /* ALD_USB */ +/** + * @}USB + */ + +/** + * @}ES32VF2264_ALD + */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_usb.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_usb.h new file mode 100644 index 0000000000..f67914d28b --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_usb.h @@ -0,0 +1,835 @@ +/** + ********************************************************************************* + * + * @file ald_usb.h + * @brief Header file of USB module driver. + * + * @version V1.0 + * @date 25 Feb. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 25 Feb. 2022 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_USB_H__ +#define __ALD_USB_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ +#include +#include "ald_utils.h" +#include "ald_dma.h" + +/* Exported Macros ----------------------------------------------------------- */ +/* Exported Types ------------------------------------------------------------ */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup USB + * @{ + */ + +/** @defgroup USB_Public_Macros USB Public Macros + * @{ + */ +/* Power */ +#define ALD_USB_POWER_RESET 0x00000008U +#define ALD_USB_POWER_RESUME 0x00000004U +#define ALD_USB_POWER_SUSPEND 0x00000002U +#define ALD_USB_POWER_ISOUDT 0x00000080U +#define ALD_USB_POWER_SUSPENDEN 0x00000001U + +/* DPDMCON */ +#define ALD_USB_DPDMCON_DPPUD 0x00000018U +#define ALD_USB_DPDMCON_DPPUD_FLOAT 0x00000000U +#define ALD_USB_DPDMCON_DPPUD_UP 0x00000008U +#define ALD_USB_DPDMCON_DPPUD_DOWN 0x00000010U +#define ALD_USB_DPDMCON_DMPUD 0x00000006U +#define ALD_USB_DPDMCON_DMPUD_FLOAT 0x00000000U +#define ALD_USB_DPDMCON_DMPUD_UP 0x00000002U +#define ALD_USB_DPDMCON_DMPUD_DOWN 0x00000004U +#define ALD_USB_DPDMCON_PHYPWREN 0x00000001U + +/* SWCID */ +#define ALD_USB_SWCID_HOST 0x00000002U +#define ALD_USB_SWCID_CIDCTRL 0x00000001U + +/* SWVBUS */ +#define ALD_USB_SWVBUS_VALTH 0x00000008U +#define ALD_USB_SWVBUS_SESVALTH 0x00000004U +#define ALD_USB_SWVBUS_SESENDTH 0x00000002U +#define ALD_USB_SWVBUS_SIGCTRL 0x00000001U + +/* SWTMODE */ +#define ALD_USB_SWTMODE_EN 0x00000001U + +/* DEVCON */ +#define ALD_USB_DEVCON_FSDEV 0x00000040U +#define ALD_USB_DEVCON_LSDEV 0x00000020U +#define ALD_USB_DEVCON_HOST 0x00000004U +#define ALD_USB_DEVCON_HOSTREQ 0x00000002U +#define ALD_USB_DEVCON_SESSION 0x00000001U + +/* CSR0L_TXCSRL */ +#define ALD_USB_CSR0L_NAKTO 0x00000080U +#define ALD_USB_CSR0L_STATUSPKT 0x00000040U +#define ALD_USB_CSR0L_REQPKT 0x00000020U +#define ALD_USB_CSR0L_ERROR 0x00000010U +#define ALD_USB_CSR0L_SETUPPKT 0x00000008U +#define ALD_USB_CSR0L_STALLED 0x00000004U +#define ALD_USB_CSR0L_TXRDY 0x00000002U +#define ALD_USB_CSR0L_RXRDY 0x00000001U + +#define ALD_USB_CSR0L_SETENDC 0x00000080U +#define ALD_USB_CSR0L_RXRDYC 0x00000040U +#define ALD_USB_CSR0L_STALL 0x00000020U +#define ALD_USB_CSR0L_SETEND 0x00000010U +#define ALD_USB_CSR0L_DATAEND 0x00000008U + +#define ALD_USB_TXCSRL_NAKTO 0x00000080U +#define ALD_USB_TXCSRL_CLRDT 0x00000040U +#define ALD_USB_TXCSRL_STALLED 0x00000020U +#define ALD_USB_TXCSRL_FLUSH 0x00000008U +#define ALD_USB_TXCSRL_ERROR 0x00000004U +#define ALD_USB_TXCSRL_FIFONE 0x00000002U +#define ALD_USB_TXCSRL_TXRDY 0x00000001U + +#define ALD_USB_TXCSRL_STALL 0x00000010U +#define ALD_USB_TXCSRL_UNDRUN 0x00000004U + +/* CSR0H_TXCSRH */ +#define ALD_USB_CSR0H_FLUSH 0x00000001U + +#define ALD_USB_TXCSRH_AUTOSET 0x00000080U +#define ALD_USB_TXCSRH_ISO 0x00000040U +#define ALD_USB_TXCSRH_MODE 0x00000020U +#define ALD_USB_TXCSRH_FDT 0x00000008U + +/* RXCSRL */ +#define ALD_USB_RXCSRL_CLRDT 0x00000080U +#define ALD_USB_RXCSRL_STALLED 0x00000040U +#define ALD_USB_RXCSRL_REQPKT 0x00000020U +#define ALD_USB_RXCSRL_FLUSH 0x00000010U +#define ALD_USB_RXCSRL_DATAERR_NAKTO 0x00000008U +#define ALD_USB_RXCSRL_ERROR 0x00000004U +#define ALD_USB_RXCSRL_FULL 0x00000002U +#define ALD_USB_RXCSRL_RXRDY 0x00000001U + +#define ALD_USB_RXCSRL_STALL 0x00000020U +#define ALD_USB_RXCSRL_DATAERR 0x00000008U +#define ALD_USB_RXCSRL_OVERRUN 0x00000004U + +/* RXCSRH */ +#define ALD_USB_RXCSRL_AUTOCLR 0x00000080U +#define ALD_USB_RXCSRL_AUTOREQ 0x00000040U + +#define ALD_USB_RXCSRL_ISO 0x00000040U + +/* TXTYPE */ +#define ALD_USB_TXTYPE_PROTOCOL 0x00000030U +#define ALD_USB_TXTYPE1_PROTOCOL_CTRL 0x00000000U +#define ALD_USB_TXTYPE_PROTOCOL_ISO 0x00000010U +#define ALD_USB_TXTYPE_PROTOCOL_BULK 0x00000020U +#define ALD_USB_TXTYPE_PROTOCOL_INT 0x00000030U +#define ALD_USB_TXTYPE_TEPN_1 0x00000001U +#define ALD_USB_TXTYPE_TEPN_2 0x00000002U +#define ALD_USB_TXTYPE_TEPN_3 0x00000003U +#define ALD_USB_TXTYPE_TEPN_4 0x00000004U +#define ALD_USB_TXTYPE_TEPN_5 0x00000005U +#define ALD_USB_TXTYPE_TEPN_6 0x00000006U + +/* RXTYPE */ +#define ALD_USB_RXTYPE_PROTOCOL_ISO 0x00000010U +#define ALD_USB_RXTYPE_PROTOCOL_BULK 0x00000020U +#define ALD_USB_RXTYPE_PROTOCOL_INT 0x00000030U +#define ALD_USB_RXTYPE_TEPN_1 0x00000001U +#define ALD_USB_RXTYPE_TEPN_2 0x00000002U +#define ALD_USB_RXTYPE_TEPN_3 0x00000003U +#define ALD_USB_RXTYPE_TEPN_4 0x00000004U +#define ALD_USB_RXTYPE_TEPN_5 0x00000005U +#define ALD_USB_RXTYPE_TEPN_6 0x00000006U + +/* TXFIFO2 */ +#define ALD_USB_TXFIFO2_MAXPKTSIZE_1024 0x000000E0U +#define ALD_USB_TXFIFO2_MAXPKTSIZE_512 0x000000C0U +#define ALD_USB_TXFIFO2_MAXPKTSIZE_256 0x000000A0U +#define ALD_USB_TXFIFO2_MAXPKTSIZE_128 0x00000080U +#define ALD_USB_TXFIFO2_MAXPKTSIZE_64 0x00000060U +#define ALD_USB_TXFIFO2_MAXPKTSIZE_32 0x00000040U +#define ALD_USB_TXFIFO2_MAXPKTSIZE_16 0x00000020U +#define ALD_USB_TXFIFO2_DPB 0x00000010U +#define ALD_USB_TXFIFO2_ADDRH 0x00000007U + +/* RXFIFO2 */ +#define ALD_USB_RXFIFO2_MAXPKTSIZE_1024 0x000000E0U +#define ALD_USB_RXFIFO2_MAXPKTSIZE_512 0x000000C0U +#define ALD_USB_RXFIFO2_MAXPKTSIZE_256 0x000000A0U +#define ALD_USB_RXFIFO2_MAXPKTSIZE_128 0x00000080U +#define ALD_USB_RXFIFO2_MAXPKTSIZE_64 0x00000060U +#define ALD_USB_RXFIFO2_MAXPKTSIZE_32 0x00000040U +#define ALD_USB_RXFIFO2_MAXPKTSIZE_16 0x00000020U +#define ALD_USB_RXFIFO2_DPB 0x00000010U + +/* TXIER */ +#define ALD_USB_TXIER_EP6IE 0x00000040U +#define ALD_USB_TXIER_EP5IE 0x00000020U +#define ALD_USB_TXIER_EP4IE 0x00000010U +#define ALD_USB_TXIER_EP3IE 0x00000008U +#define ALD_USB_TXIER_EP2IE 0x00000004U +#define ALD_USB_TXIER_EP1IE 0x00000002U +#define ALD_USB_TXIER_EP0IE 0x00000001U + +/* RXIER */ +#define ALD_USB_RXIER_EP6IE 0x00000040U +#define ALD_USB_RXIER_EP5IE 0x00000020U +#define ALD_USB_RXIER_EP4IE 0x00000010U +#define ALD_USB_RXIER_EP3IE 0x00000008U +#define ALD_USB_RXIER_EP2IE 0x00000004U +#define ALD_USB_RXIER_EP1IE 0x00000002U + +/* TXIDR */ +#define ALD_USB_TXIDR_EP6ID 0x00000040U +#define ALD_USB_TXIDR_EP5ID 0x00000020U +#define ALD_USB_TXIDR_EP4ID 0x00000010U +#define ALD_USB_TXIDR_EP3ID 0x00000008U +#define ALD_USB_TXIDR_EP2ID 0x00000004U +#define ALD_USB_TXIDR_EP1ID 0x00000002U +#define ALD_USB_TXIDR_EP0ID 0x00000001U + +/* RXIDR */ +#define ALD_USB_RXIDR_EP6ID 0x00000040U +#define ALD_USB_RXIDR_EP5ID 0x00000020U +#define ALD_USB_RXIDR_EP4ID 0x00000010U +#define ALD_USB_RXIDR_EP3ID 0x00000008U +#define ALD_USB_RXIDR_EP2ID 0x00000004U +#define ALD_USB_RXIDR_EP1ID 0x00000002U + +/* TXIVS */ +#define ALD_USB_TXIVS_EP6IVS 0x00000040U +#define ALD_USB_TXIVS_EP5IVS 0x00000020U +#define ALD_USB_TXIVS_EP4IVS 0x00000010U +#define ALD_USB_TXIVS_EP3IVS 0x00000008U +#define ALD_USB_TXIVS_EP2IVS 0x00000004U +#define ALD_USB_TXIVS_EP1IVS 0x00000002U +#define ALD_USB_TXIVS_EP0IVS 0x00000001U + +/* RXIVS */ +#define ALD_USB_RXIVS_EP6IVS 0x00000040U +#define ALD_USB_RXIVS_EP5IVS 0x00000020U +#define ALD_USB_RXIVS_EP4IVS 0x00000010U +#define ALD_USB_RXIVS_EP3IVS 0x00000008U +#define ALD_USB_RXIVS_EP2IVS 0x00000004U +#define ALD_USB_RXIVS_EP1IVS 0x00000002U + +/* TXRIF */ +#define ALD_USB_TXRIF_EP6RIF 0x00000040U +#define ALD_USB_TXRIF_EP5RIF 0x00000020U +#define ALD_USB_TXRIF_EP4RIF 0x00000010U +#define ALD_USB_TXRIF_EP3RIF 0x00000008U +#define ALD_USB_TXRIF_EP2RIF 0x00000004U +#define ALD_USB_TXRIF_EP1RIF 0x00000002U +#define ALD_USB_TXRIF_EP0RIF 0x00000001U + +/* RXRIF */ +#define ALD_USB_RXRIF_EP6RIF 0x00000040U +#define ALD_USB_RXRIF_EP5RIF 0x00000020U +#define ALD_USB_RXRIF_EP4RIF 0x00000010U +#define ALD_USB_RXRIF_EP3RIF 0x00000008U +#define ALD_USB_RXRIF_EP2RIF 0x00000004U +#define ALD_USB_RXRIF_EP1RIF 0x00000002U + +/* TXIFM */ +#define ALD_USB_TXIFM_EP6IFM 0x00000040U +#define ALD_USB_TXIFM_EP5IFM 0x00000020U +#define ALD_USB_TXIFM_EP4IFM 0x00000010U +#define ALD_USB_TXIFM_EP3IFM 0x00000008U +#define ALD_USB_TXIFM_EP2IFM 0x00000004U +#define ALD_USB_TXIFM_EP1IFM 0x00000002U +#define ALD_USB_TXIFM_EP0IFM 0x00000001U + +/* RXIFM */ +#define ALD_USB_RXIFM_EP6IFM 0x00000040U +#define ALD_USB_RXIFM_EP5IFM 0x00000020U +#define ALD_USB_RXIFM_EP4IFM 0x00000010U +#define ALD_USB_RXIFM_EP3IFM 0x00000008U +#define ALD_USB_RXIFM_EP2IFM 0x00000004U +#define ALD_USB_RXIFM_EP1IFM 0x00000002U + +/* TXICR */ +#define ALD_USB_TXICR_EP6ICR 0x00000040U +#define ALD_USB_TXICR_EP5ICR 0x00000020U +#define ALD_USB_TXICR_EP4ICR 0x00000010U +#define ALD_USB_TXICR_EP3ICR 0x00000008U +#define ALD_USB_TXICR_EP2ICR 0x00000004U +#define ALD_USB_TXICR_EP1ICR 0x00000002U +#define ALD_USB_TXICR_EP0ICR 0x00000001U + +/* RXICR */ +#define ALD_USB_RXICR_EP6ICR 0x00000040U +#define ALD_USB_RXICR_EP5ICR 0x00000020U +#define ALD_USB_RXICR_EP4ICR 0x00000010U +#define ALD_USB_RXICR_EP3ICR 0x00000008U +#define ALD_USB_RXICR_EP2ICR 0x00000004U +#define ALD_USB_RXICR_EP1ICR 0x00000002U + +/* IER */ +#define ALD_USB_IER_STATUS 0x000000FFU +#define ALD_USB_IER_SESREQIE 0x00000040U +#define ALD_USB_IER_DISCONIE 0x00000020U +#define ALD_USB_IER_CONIE 0x00000010U +#define ALD_USB_IER_SOFIE 0x00000008U +#define ALD_USB_IER_BABIE 0x00000004U +#define ALD_USB_IER_RESIE 0x00000002U +#define ALD_USB_IER_SUSPDIE 0x00000001U + +/* IDR */ +#define ALD_USB_IDR_STATUS 0x000000FFU +#define ALD_USB_IDR_SESREQID 0x00000040U +#define ALD_USB_IDR_DISCONID 0x00000020U +#define ALD_USB_IDR_CONID 0x00000010U +#define ALD_USB_IDR_SOFID 0x00000008U +#define ALD_USB_IDR_BABID 0x00000004U +#define ALD_USB_IDR_RESID 0x00000002U +#define ALD_USB_IDR_SUSPDID 0x00000001U + +/* IVS */ +#define ALD_USB_IVS_SESREQIVS 0x00000040U +#define ALD_USB_IVS_DISCONIVS 0x00000020U +#define ALD_USB_IVS_CONIVS 0x00000010U +#define ALD_USB_IVS_SOFIVS 0x00000008U +#define ALD_USB_IVS_BABIVS 0x00000004U +#define ALD_USB_IVS_RESIVS 0x00000002U +#define ALD_USB_IVS_SUSPDIVS 0x00000001U + +/* RIF */ +#define ALD_USB_RIF_SESREQRIF 0x00000040U +#define ALD_USB_RIF_DISCONRIF 0x00000020U +#define ALD_USB_RIF_CONRIF 0x00000010U +#define ALD_USB_RIF_SOFRIF 0x00000008U +#define ALD_USB_RIF_BABRIF 0x00000004U +#define ALD_USB_RIF_RESRIF 0x00000002U +#define ALD_USB_RIF_SUSPDRIF 0x00000001U + +/* IFM */ +#define ALD_USB_IFM_SESREQIFM 0x00000040U +#define ALD_USB_IFM_DISCONIFM 0x00000020U +#define ALD_USB_IFM_CONIFM 0x00000010U +#define ALD_USB_IFM_SOFIFM 0x00000008U +#define ALD_USB_IFM_BABIFM 0x00000004U +#define ALD_USB_IFM_RESIFM 0x00000002U +#define ALD_USB_IFM_SUSPDIFM 0x00000001U + +/* ICR */ +#define ALD_USB_ICR_SESREQICR 0x00000040U +#define ALD_USB_ICR_DISCONICR 0x00000020U +#define ALD_USB_ICR_CONICR 0x00000010U +#define ALD_USB_ICR_SOFICR 0x00000008U +#define ALD_USB_ICR_BABICR 0x00000004U +#define ALD_USB_ICR_RESICR 0x00000002U +#define ALD_USB_ICR_SUSPDICR 0x00000001U + +#define ALD_MAX_NAK_LIMIT 255U +#define ALD_DISABLE_NAK_LIMIT 0U + +#define ALD_USB_RX_EPSTATUS_SHIFT 16U +#define ALD_USB_INTEP_RX_SHIFT 16U + +#define ALD_MAX_PACKET_SIZE_EP0 64U + +#define ALD_USB_TXTYPE1_PROTO_M 0x00000030U +#define ALD_USB_TXTYPE1_PROTO_CTRL 0x00000000U +#define ALD_USB_TXTYPE1_PROTO_ISOC 0x00000010U +#define ALD_USB_TXTYPE1_PROTO_BULK 0x00000020U +#define ALD_USB_TXTYPE1_PROTO_INT 0x00000030U + +#define ALD_USB_FIFO_SZ_8 0x00000000U +#define ALD_USB_FIFO_SZ_16 0x00000001U +#define ALD_USB_FIFO_SZ_32 0x00000002U +#define ALD_USB_FIFO_SZ_64 0x00000003U +#define ALD_USB_FIFO_SZ_128 0x00000004U +#define ALD_USB_FIFO_SZ_256 0x00000005U +#define ALD_USB_FIFO_SZ_512 0x00000006U +#define ALD_USB_FIFO_SZ_1024 0x00000007U +#define ALD_USB_FIFO_SZ_2048 0x00000008U +#define ALD_USBFIFO_SIZE_TO_BYTES(X) (8 << (X)) + +#define ALD_USB_TRANS_OUT 0x00000102U +#define ALD_USB_TRANS_IN 0x00000102U +#define ALD_USB_TRANS_IN_LAST 0x0000010aU +#define ALD_USB_TRANS_SETUP 0x0000110aU +#define ALD_USB_TRANS_STATUS 0x00000142U + +#define ALD_USB_RX_EPSTATUS_SHIFT 16U +#define ALD_USB_INTEP_RX_SHIFT 16U + +#define ALD_USB_UNDEF_SPEED 0x80000000U +#define ALD_USB_HIGH_SPEED 0x00000002U +#define ALD_USB_FULL_SPEED 0x00000001U +#define ALD_USB_LOW_SPEED 0x00000000U + +#define ALD_USB_EP_AUTO_SET 0x00000001 +#define ALD_USB_EP_AUTO_REQUEST 0x00000002 +#define ALD_USB_EP_AUTO_CLEAR 0x00000004 +#define ALD_USB_EP_DUAL_BUFFERING 0x00000008 +#define ALD_USB_EP_DMA_MODE_0 0x00000008 +#define ALD_USB_EP_DMA_MODE_1 0x00000010 +#define ALD_USB_EP_DIS_NYET 0x00000020 + +#define ALD_USB_EP_MODE_ISOC 0x00000000 /* Isochronous endpoint*/ +#define ALD_USB_EP_MODE_BULK 0x00000100 /* Bulk endpoint*/ +#define ALD_USB_EP_MODE_INT 0x00000200 /* Interrupt endpoint*/ +#define ALD_USB_EP_MODE_CTRL 0x00000300 /* Control endpoint*/ +#define ALD_USB_EP_MODE_MASK 0x00000300 /* Mode Mask*/ +#define ALD_USB_EP_SPEED_LOW 0x00000000 /* Low Speed*/ +#define ALD_USB_EP_SPEED_FULL 0x00001000 /* Full Speed*/ +#define ALD_USB_EP_SPEED_HIGH 0x00004000 /* High Speed*/ +#define ALD_USB_EP_HOST_IN 0x00000000 /* Host IN endpoint*/ +#define ALD_USB_EP_HOST_OUT 0x00002000 /* Host OUT endpoint*/ +#define ALD_USB_EP_DEV_IN 0x00002000 /* Device IN endpoint*/ +#define ALD_USB_EP_DEV_OUT 0x00000000 /* Device OUT endpoint*/ + +#define ALD_USB_INTCTRL_ALL 0x000003FFU +#define ALD_USB_INTCTRL_STATUS 0x000000FFU +#define ALD_USB_INTCTRL_VBUS_ERR 0x00000080U +#define ALD_USB_INTCTRL_SESSION 0x00000040U +#define ALD_USB_INTCTRL_SESSION_END 0x00000040U +#define ALD_USB_INTCTRL_DISCONNECT 0x00000020U +#define ALD_USB_INTCTRL_CONNECT 0x00000010U +#define ALD_USB_INTCTRL_SOF 0x00000008U +#define ALD_USB_INTCTRL_BABBLE 0x00000004U +#define ALD_USB_INTCTRL_RESET 0x00000004U +#define ALD_USB_INTCTRL_RESUME 0x00000002U +#define ALD_USB_INTCTRL_SUSPEND 0x00000001U +#define ALD_USB_INTCTRL_MODE_DETECT 0x00000200U +#define ALD_USB_INTCTRL_POWER_FAULT 0x00000100U + + +#define ALD_USB_INTEP_ALL 0xFFFFFFFFU +#define ALD_USB_INTEP_HOST_IN 0x001E0000U +#define ALD_USB_INTEP_HOST_IN_15 0x80000000U +#define ALD_USB_INTEP_HOST_IN_14 0x40000000U +#define ALD_USB_INTEP_HOST_IN_13 0x20000000U +#define ALD_USB_INTEP_HOST_IN_12 0x10000000U +#define ALD_USB_INTEP_HOST_IN_11 0x08000000U +#define ALD_USB_INTEP_HOST_IN_10 0x04000000U +#define ALD_USB_INTEP_HOST_IN_9 0x02000000U +#define ALD_USB_INTEP_HOST_IN_8 0x01000000U +#define ALD_USB_INTEP_HOST_IN_7 0x00800000U +#define ALD_USB_INTEP_HOST_IN_6 0x00400000U +#define ALD_USB_INTEP_HOST_IN_5 0x00200000U +#define ALD_USB_INTEP_HOST_IN_4 0x00100000U +#define ALD_USB_INTEP_HOST_IN_3 0x00080000U +#define ALD_USB_INTEP_HOST_IN_2 0x00040000U +#define ALD_USB_INTEP_HOST_IN_1 0x00020000U +#define ALD_USB_INTEP_DEV_OUT 0x001E0000U +#define ALD_USB_INTEP_DEV_OUT_15 0x80000000U +#define ALD_USB_INTEP_DEV_OUT_14 0x40000000U +#define ALD_USB_INTEP_DEV_OUT_13 0x20000000U +#define ALD_USB_INTEP_DEV_OUT_12 0x10000000U +#define ALD_USB_INTEP_DEV_OUT_11 0x08000000U +#define ALD_USB_INTEP_DEV_OUT_10 0x04000000U +#define ALD_USB_INTEP_DEV_OUT_9 0x02000000U +#define ALD_USB_INTEP_DEV_OUT_8 0x01000000U +#define ALD_USB_INTEP_DEV_OUT_7 0x00800000U +#define ALD_USB_INTEP_DEV_OUT_6 0x00400000U +#define ALD_USB_INTEP_DEV_OUT_5 0x00200000U +#define ALD_USB_INTEP_DEV_OUT_4 0x00100000U +#define ALD_USB_INTEP_DEV_OUT_3 0x00080000U +#define ALD_USB_INTEP_DEV_OUT_2 0x00040000U +#define ALD_USB_INTEP_DEV_OUT_1 0x00020000U +#define ALD_USB_INTEP_HOST_OUT 0x0000001EU +#define ALD_USB_INTEP_HOST_OUT_15 0x00008000U +#define ALD_USB_INTEP_HOST_OUT_14 0x00004000U +#define ALD_USB_INTEP_HOST_OUT_13 0x00002000U +#define ALD_USB_INTEP_HOST_OUT_12 0x00001000U +#define ALD_USB_INTEP_HOST_OUT_11 0x00000800U +#define ALD_USB_INTEP_HOST_OUT_10 0x00000400U +#define ALD_USB_INTEP_HOST_OUT_9 0x00000200U +#define ALD_USB_INTEP_HOST_OUT_8 0x00000100U +#define ALD_USB_INTEP_HOST_OUT_7 0x00000080U +#define ALD_USB_INTEP_HOST_OUT_6 0x00000040U +#define ALD_USB_INTEP_HOST_OUT_5 0x00000020U +#define ALD_USB_INTEP_HOST_OUT_4 0x00000010U +#define ALD_USB_INTEP_HOST_OUT_3 0x00000008U +#define ALD_USB_INTEP_HOST_OUT_2 0x00000004U +#define ALD_USB_INTEP_HOST_OUT_1 0x00000002U +#define ALD_USB_INTEP_DEV_IN 0x0000001EU +#define ALD_USB_INTEP_DEV_IN_15 0x00008000U +#define ALD_USB_INTEP_DEV_IN_14 0x00004000U +#define ALD_USB_INTEP_DEV_IN_13 0x00002000U +#define ALD_USB_INTEP_DEV_IN_12 0x00001000U +#define ALD_USB_INTEP_DEV_IN_11 0x00000800U +#define ALD_USB_INTEP_DEV_IN_10 0x00000400U +#define ALD_USB_INTEP_DEV_IN_9 0x00000200U +#define ALD_USB_INTEP_DEV_IN_8 0x00000100U +#define ALD_USB_INTEP_DEV_IN_7 0x00000080U +#define ALD_USB_INTEP_DEV_IN_6 0x00000040U +#define ALD_USB_INTEP_DEV_IN_5 0x00000020U +#define ALD_USB_INTEP_DEV_IN_4 0x00000010U +#define ALD_USB_INTEP_DEV_IN_3 0x00000008U +#define ALD_USB_INTEP_DEV_IN_2 0x00000004U +#define ALD_USB_INTEP_DEV_IN_1 0x00000002U +#define ALD_USB_INTEP_0 0x00000001U + + +#define ALD_USB_UNDEF_SPEED 0x80000000U +#define ALD_USB_HIGH_SPEED 0x00000002U +#define ALD_USB_FULL_SPEED 0x00000001U +#define ALD_USB_LOW_SPEED 0x00000000U + +#define ALD_USB_HOST_IN_STATUS 0x114F0000U +#define ALD_USB_HOST_IN_PID_ERROR 0x10000000U +#define ALD_USB_HOST_IN_NOT_COMP 0x01000000U +#define ALD_USB_HOST_IN_STALL 0x00400000U +#define ALD_USB_HOST_IN_DATA_ERROR 0x00080000U +#define ALD_USB_HOST_IN_NAK_TO 0x00080000U +#define ALD_USB_HOST_IN_ERROR 0x00040000U +#define ALD_USB_HOST_IN_FIFO_FULL 0x00020000U +#define ALD_USB_HOST_IN_PKTRDY 0x00010000U +#define ALD_USB_HOST_OUT_STATUS 0x000000A7U +#define ALD_USB_HOST_OUT_NAK_TO 0x00000080U +#define ALD_USB_HOST_OUT_NOT_COMP 0x00000080U +#define ALD_USB_HOST_OUT_STALL 0x00000020U +#define ALD_USB_HOST_OUT_ERROR 0x00000004U +#define ALD_USB_HOST_OUT_FIFO_NE 0x00000002U +#define ALD_USB_HOST_OUT_PKTPEND 0x00000001U +#define ALD_USB_HOST_EP0_NAK_TO 0x00000080U +#define ALD_USB_HOST_EP0_STATUS 0x00000040U +#define ALD_USB_HOST_EP0_ERROR 0x00000010U +#define ALD_USB_HOST_EP0_RX_STALL 0x00000004U +#define ALD_USB_HOST_EP0_RXPKTRDY 0x00000001U +#define ALD_USB_DEV_RX_PID_ERROR 0x01000000U +#define ALD_USB_DEV_RX_SENT_STALL 0x00400000U +#define ALD_USB_DEV_RX_DATA_ERROR 0x00080000U +#define ALD_USB_DEV_RX_OVERRUN 0x00040000U +#define ALD_USB_DEV_RX_FIFO_FULL 0x00020000U +#define ALD_USB_DEV_RX_PKT_RDY 0x00010000U +#define ALD_USB_DEV_TX_NOT_COMP 0x00000080U +#define ALD_USB_DEV_TX_SENT_STALL 0x00000020U +#define ALD_USB_DEV_TX_UNDERRUN 0x00000004U +#define ALD_USB_DEV_TX_FIFO_NE 0x00000002U +#define ALD_USB_DEV_TX_TXPKTRDY 0x00000001U +#define ALD_USB_DEV_EP0_SETUP_END 0x00000010U +#define ALD_USB_DEV_EP0_SENT_STALL 0x00000004U +#define ALD_USB_DEV_EP0_IN_PKTPEND 0x00000002U +#define ALD_USB_DEV_EP0_OUT_PKTRDY 0x00000001U + + +#define ALD_USB_EP_0 0x00000000U +#define ALD_USB_EP_1 0x00000001U +#define ALD_USB_EP_2 0x00000002U +#define ALD_USB_EP_3 0x00000003U +#define ALD_USB_EP_4 0x00000004U +#define ALD_USB_EP_5 0x00000005U +#define ALD_USB_EP_6 0x00000006U +#define ALD_USB_EP_7 0x00000007U +#define ALD_NUM_USB_EP 8U + +#define ALD_USB_FIFO_SZ_8 0x00000000U +#define ALD_USB_FIFO_SZ_16 0x00000001U +#define ALD_USB_FIFO_SZ_32 0x00000002U +#define ALD_USB_FIFO_SZ_64 0x00000003U +#define ALD_USB_FIFO_SZ_128 0x00000004U +#define ALD_USB_FIFO_SZ_256 0x00000005U +#define ALD_USB_FIFO_SZ_512 0x00000006U +#define ALD_USB_FIFO_SZ_1024 0x00000007U +#define ALD_USB_FIFO_SZ_2048 0x00000008U + +#define ALD_USB_TRANS_OUT 0x00000102U +#define ALD_USB_TRANS_IN 0x00000102U +#define ALD_USB_TRANS_IN_LAST 0x0000010aU +#define ALD_USB_TRANS_SETUP 0x0000110aU +#define ALD_USB_TRANS_STATUS 0x00000142U +#define ALD_USB_DMA_EP_CFG_TX 0x00000001U +#define ALD_USB_DMA_EP_CFG_RX_DEV 0x00000002U +#define ALD_USB_DMA_EP_CFG_RX_HOST 0x00000004U +#define ALD_USB_DMA_EP_TX_MSK 0x94U +#define ALD_USB_DMA_EP_RX_DEV_MSK 0xA8U +#define ALD_USB_DMA_EP_RX_HOST_MSK 0xE8U + +#define ALD_USB_INTLPM_ERROR 0x00000020U +#define ALD_USB_INTLPM_RESUME 0x00000010U +#define ALD_USB_INTLPM_INCOMPLETE 0x00000008U +#define ALD_USB_INTLPM_ACK 0x00000004U +#define ALD_USB_INTLPM_NYET 0x00000002U +#define ALD_USB_INTLPM_STALL 0x00000001U + + +#define ALD_USB_DEV_LPM_NAK 0x00000010U +#define ALD_USB_DEV_LPM_NONE 0x00000000U +#define ALD_USB_DEV_LPM_EN 0x0000000cU +#define ALD_USB_DEV_LPM_EXTONLY 0x00000004U + +#define ALD_USB_HOST_LPM_RMTWAKE 0x00000100U +#define ALD_USB_HOST_LPM_L1 0x00000001U + +#define ALD_USB_DEV_LPM_LS_RMTWAKE 0x00000100U +#define ALD_USB_DEV_LPM_LS_L1 0x00000001U + +#define ALD_USB_HOST_PWRFLT_LOW 0x00000010U +#define ALD_USB_HOST_PWRFLT_HIGH 0x00000030U +#define ALD_USB_HOST_PWRFLT_EP_NONE 0x00000000U +#define ALD_USB_HOST_PWRFLT_EP_TRI 0x00000140U +#define ALD_USB_HOST_PWRFLT_EP_LOW 0x00000240U +#define ALD_USB_HOST_PWRFLT_EP_HIGH 0x00000340U +#define ALD_USB_HOST_PWREN_MAN_LOW 0x00000000U +#define ALD_USB_HOST_PWREN_MAN_HIGH 0x00000001U +#define ALD_USB_HOST_PWREN_AUTOLOW 0x00000002U +#define ALD_USB_HOST_PWREN_AUTOHIGH 0x00000003U +#define ALD_USB_HOST_PWREN_FILTER 0x00010000U + + +/** + * @} + */ + + +/** + * @defgroup USB_Public_Types USB Public Types + * @{ + */ + +/** + * @brief USB DP/DM line push-up or push-down + */ +typedef enum +{ + ALD_USB_DPDM_FLOATING = 0x0U, /**< Floating */ + ALD_USB_DPDM_PUSH_UP = 0x1U, /**< Push-Up */ + ALD_USB_DPDM_PUSH_DOWN = 0x2U, /**< Push-Down */ +} ald_dpdm_push_t; + + +/** + * @} + */ + +/** @addtogroup USB_Public_Functions + * @{ + */ + +/** @addtogroup USB_Public_Functions_Group1 USB Base functions + * @{ + */ +/* Base functions */ +extern uint32_t ald_usb_frame_number_get(void); +extern void ald_usb_otg_session_request(bool start); +extern uint32_t ald_usb_mode_get(void); +extern uint32_t ald_usb_mode_host_req(void); +extern uint32_t ald_usb_mode_host_req_clear(void); +extern void ald_usb_high_speed_enable(bool enable); +extern uint32_t ald_usb_device_speed_get(void); +extern uint32_t ald_usb_num_ep_get(void); +extern void ald_usb_control_reset(void); +void ald_usb_dppud_set(ald_dpdm_push_t pupd); +void ald_usb_dmpud_set(ald_dpdm_push_t pupd); +void ald_usb_swcid_cidctrl(uint8_t cid); +void ald_usb_swcid_host(uint8_t host); + +/** + * @}USB_Public_Functions_Group1 + */ + +/** @addtogroup USB_Public_Functions_Group2 USB Device functions + * @{ + */ +/* Device functions */ +extern uint8_t ald_usb_dev_get_addr(void); +extern void ald_usb_dev_set_addr(uint8_t addr); +extern void ald_usb_dev_connect(void); +extern void ald_usb_dev_disconnect(void); +extern void ald_usb_dev_suspend_enable(void); +extern void ald_usb_dev_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t flags); +extern void ald_usb_dev_ep_get_config(uint32_t ep_idx, uint32_t *p_max, uint32_t *flags); +extern void ald_usb_dev_ep_data_ack(uint32_t ep_idx, bool last); +extern void ald_usb_dev_ep_stall(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_dev_ep_stall_clear(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_dev_ep_status_clear(uint32_t ep_idx, uint32_t flags); + +/** + * @}USB_Public_Functions_Group2 + */ + +/** @addtogroup USB_Public_Functions_Group3 USB Host functions + * @{ + */ +/* Host functions */ +extern uint32_t ald_usb_host_addr_get(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_host_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags); +extern void ald_usb_host_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t nak_val, uint32_t t_ep, uint32_t flags); +extern void ald_usb_host_ep_data_ack(uint32_t ep_idx); +extern void ald_usb_host_ep_data_toggle(uint32_t ep_idx, bool toggle, uint32_t flags); +extern void ald_usb_host_ep_status_clear(uint32_t ep_idx, uint32_t flags); +extern uint32_t ald_usb_host_hub_addr_get(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_host_hub_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags); +extern void ald_usb_host_pwr_disable(void); +extern void ald_usb_host_pwr_enable(void); +extern void ald_usb_host_pwr_config(uint32_t flags); +extern void ald_usb_host_pwr_fault_disable(void); +extern void ald_usb_host_pwr_fault_enable(void); +extern void ald_usb_host_request_in(uint32_t ep_idx); +extern void ald_usb_host_request_in_clear(uint32_t ep_idx); +extern void ald_usb_host_request_status(void); +extern void ald_usb_host_reset(bool start); +extern void ald_usb_host_resume(bool start); +extern void ald_usb_host_suspend(void); +extern uint32_t ald_usb_host_speed_get(void); +extern void ald_usb_host_ep_speed_set(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_host_ep_ping(uint32_t ep_idx, bool enable); +/** + * @}USB_Public_Functions_Group3 + */ + +/** @addtogroup USB_Public_Functions_Group4 USB Endpoint functions + * @{ + */ +/* Endpoint functions */ +extern uint32_t ald_usb_ep_data_avail(uint32_t ep_idx); +extern int32_t ald_usb_ep_data_get(uint32_t ep_idx, uint8_t *data, uint32_t *size); +extern int32_t ald_usb_ep_data_put(uint32_t ep_idx, uint8_t *data, uint32_t size); +extern int32_t ald_usb_ep_data_send(uint32_t ep_idx, uint32_t tx_type); +extern void ald_usb_ep_data_toggle_clear(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_ep_req_packet_count(uint32_t ep_idx, uint32_t count); +extern uint32_t ald_usb_ep_status(uint32_t ep_idx); +extern void ald_usb_ep_dma_config(uint32_t ep_idx, uint32_t flag, type_func_t en); + +/** + * @}USB_Public_Functions_Group4 + */ + +/** @addtogroup USB_Public_Functions_Group5 USB FIFO functions + * @{ + */ +/* FIFO functions */ +extern uint32_t ald_usb_fifo_addr_get(uint32_t ep_idx); +extern void ald_usb_fifo_config_get(uint32_t ep_idx, uint32_t *addr, uint32_t *size, uint32_t flags); +extern void ald_usb_fifo_config_set(uint32_t ep_idx, uint32_t addr, uint32_t size, uint32_t flags); +extern void ald_usb_fifo_flush(uint32_t ep_idx, uint32_t flags); +/** + * @}USB_Public_Functions_Group5 + */ + +/** @addtogroup USB_Public_Functions_Group6 USB Interrupt functions + * @{ + */ +/* Interrupt functions */ +extern void ald_usb_int_disable(uint32_t flags); +extern void ald_usb_int_enable(uint32_t flags); +extern uint32_t ald_usb_int_status_get(void); +extern void ald_usb_int_disable_ep(uint32_t flags); +extern void ald_usb_int_enable_ep(uint32_t flags); +extern uint32_t ald_usb_int_status_ep_get(void); +extern void ald_usb_int_register(void); +extern void ald_usb_int_unregister(void); +extern uint32_t ald_usb_int_num_get(void); +/** + * @}USB_Public_Functions_Group6 + */ + +/** @addtogroup USB_Public_Functions_Group7 USB DMA functions + * @{ + */ +/* DMA functions */ +extern void ald_usb_dma_channel_config(uint8_t ch, uint32_t addr, uint32_t count, uint32_t ctrl); +extern void ald_usb_dma_mult_recv_start(uint32_t ep_idx); +extern void ald_usb_dma_channel_start(uint8_t ch); +extern void ald_usb_dma_channel_stop(uint8_t ch); +extern uint32_t ald_usb_dma_get_interrupt_flag(void); +extern uint32_t ald_usb_dma_get_channel_error(uint8_t ch); +extern void ald_usb_dma_clear_channel_error(uint8_t ch); +/** + * @}USB_Public_Functions_Group7 + */ + +/** @addtogroup USB_Public_Functions_Group8 USB LPM functions + * @{ + */ +/* LPM functions */ +extern uint32_t ald_usb_lpm_remote_wake_is_enable(void); +extern uint32_t ald_usb_lpm_link_status_get(void); +extern uint32_t ald_usb_lpm_ep_get(void); +extern uint32_t ald_usb_lpm_int_status_get(void); +extern void ald_usb_lpm_int_disable(uint32_t ints); +extern void ald_usb_lpm_int_enable(uint32_t ints); +extern void ald_usb_host_lpm_send(uint32_t addr, uint32_t ep_idx); +extern void ald_usb_host_lpm_config(uint32_t resume_time, uint32_t config); +extern void ald_usb_host_lpm_resume(void); +extern void ald_usb_dev_lpm_remote_wake(void); +extern void ald_usb_dev_lpm_config(uint32_t config); +extern void ald_usb_dev_lpm_enable(void); +extern void ald_usb_dev_lpm_disable(void); + +/** + * @}USB_Public_Functions_Group8 + */ + +/** @addtogroup USB_Public_Functions_Group9 USB SWVBUS control functions + * @{ + */ +/* usb swvbus control functions */ +extern void ald_usb_swvbus_sigctl_set(uint8_t sigctl); +extern uint8_t ald_usb_swvbus_sigctl_get(void); +extern void ald_usb_swvbus_sesendth_set(uint8_t thd); +extern uint8_t ald_usb_swvbus_sesendth_get(void); +extern void ald_usb_swvbus_sesvalth_set(uint8_t thd); +extern uint8_t ald_usb_swvbus_sesvalth_get(void); +extern void ald_usb_swvbus_valth_set(uint8_t thd); +extern uint8_t ald_usb_swvbus_valth_get(void); + +/** + * @}USB_Public_Functions_Group9 + */ + +/** @addtogroup USB_Public_Functions_Group10 USB components initialization functions + * @{ + */ +/* usb init functions */ +extern void ald_usb_host_components_init(void); +extern void ald_usb_device_components_init(void); + +/** + * @}USB_Public_Functions_Group10 + */ +/** + * @}USB_Public_Functions + */ + +/** + * @}USB + */ + +/** + * @}ES32VF2264_ALD + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALD_USB_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_utils.c b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_utils.c new file mode 100644 index 0000000000..87582e790b --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_utils.c @@ -0,0 +1,437 @@ +/** + ********************************************************************************* + * + * @file ald_utils.c + * @brief This file contains the Utilities functions/types for the driver. + * + * @version V1.0 + * @date 8 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 8 Feb. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ + +#include +#include "ald_conf.h" + +/* Public Variables ---------------------------------------------------------- */ + +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @brief Shanghai Eastsoft Microelectronics E902 Chip Abstraction Layer Driver(ALD) + * @{ + */ + +/** @defgroup UTILS Utils + * @brief Utils module driver + * @{ + */ + +/** @defgroup ALD_Private_Constants Private Constants + * @brief ALD Private Constants + * @{ + */ + +/* Private Macros ------------------------------------------------------------ */ + +/** + * @brief ALD version number + */ +#define __ALD_VERSION_MAIN (0x01) /**< [31:24] main version */ +#define __ALD_VERSION_SUB1 (0x00) /**< [23:16] sub1 version */ +#define __ALD_VERSION_SUB2 (0x00) /**< [15:8] sub2 version */ +#define __ALD_VERSION_RC (0x00) /**< [7:0] release candidate */ +#define __ALD_VERSION ((__ALD_VERSION_MAIN << 24) | \ + (__ALD_VERSION_SUB1 << 16) | \ + (__ALD_VERSION_SUB2 << 8 ) | \ + (__ALD_VERSION_RC)) +/** + * @} + */ + +/* Private Variables --------------------------------------------------------- */ + +/** @defgroup ALD_Private_Variables Private Variables + * @{ + */ + +/** @brief lib_tick: Increase by one millisecond + */ +__IO uint32_t lib_tick; +uint32_t __systick_interval = ALD_SYSTICK_INTERVAL_1MS; + +/** + * @}ALD_Private_Variables + */ + +/** @defgroup ALD_Public_Functions Public Functions + * @{ + */ + +/** @defgroup ALD_Public_Functions_Group1 Initialization Function + * @brief Initialization functions + * + * @verbatim + =============================================================================== + ##### Initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes interface, the NVIC allocation and initial clock + configuration. It initializes the source of time base also when timeout + is needed and the backup domain when enabled. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) Systick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms. + (++) Time base configuration function (ald_tick_init()) is called automatically + at the beginning of the program after reset by ald_cmu_init() or at + any time when clock is configured. + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if ald_delay_ms() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. + (+) Configure the interval of Systick interrupt. + + @endverbatim + * @{ + */ + +/* Private Function ---------------------------------------------------------- */ + +/** + * @brief This function Configures time base source, CLINT and DMA. + * @note This function is called at the beginning of program after reset and before + * the clock configuration. + * @note The time base configuration is based on MSI clock when exiting from Reset. + * Once done, time base tick start incrementing. + * In the default implementation, Systick is used as source of time base. + * The tick variable is incremented each 1ms in its ISR. + * @retval None + */ +void ald_cmu_init(void) +{ + ald_cmu_clock_config_default(); + ald_tick_init(TICK_INT_PRIORITY); +#ifdef ALD_DMA + ald_cmu_perh_clock_config(ALD_CMU_PERH_DMA, ENABLE); + ald_dma_init(); +#endif /* ALD_DMA */ + return; +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if ald_delay_ms() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param prio: Tick interrupt priority. + * @retval None + */ +__weak void ald_tick_init(uint32_t prio) +{ + /* Configure the SysTick IRQ */ + csi_coret_config(ald_cmu_get_sys_clock() / ALD_SYSTICK_INTERVAL_1MS, CLINT_IRQn); + csi_vic_set_prio(CLINT_IRQn, prio); + csi_vic_enable_sirq(CLINT_IRQn); + + return; +} + +/** + * @brief Selects the interval of systick interrupt. + * @param value: The value of interval: + * @arg @ref SYSTICK_INTERVAL_1MS 1 millisecond + * @arg @ref SYSTICK_INTERVAL_10MS 10 milliseconds + * @arg @ref SYSTICK_INTERVAL_100MS 100 milliseconds + * @arg @ref SYSTICK_INTERVAL_1000MS 1 second + * @retval None + */ +void ald_systick_interval_select(ald_systick_interval_t value) +{ + assert_param(IS_SYSTICK_INTERVAL(value)); + + if (value == 0) + return; + + csi_coret_config(ald_cmu_get_sys_clock() / value, CLINT_IRQn); + __systick_interval = value; + + csi_vic_set_prio(CLINT_IRQn, TICK_INT_PRIORITY); + + return; +} +/** + * @} + */ + +/** @defgroup ALD_Public_Functions_Group2 Control functions + * @brief Control functions + * + * @verbatim + =============================================================================== + ##### Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the ALD version + (+) Waiting for flag + (+) Configure the interrupt + (+) Provide system tick value + (+) Initialize core timestamp + (+) Get core timestamp + (+) Get CPU ID + (+) Get UID + (+) Get CHIPID + + @endverbatim + * @{ + */ + +/** + * @brief This function invoked by Systick ISR. + * @note This function is declared as __weak to be overwritten in case of + * other implementations in user file. + * @retval None + */ +__weak void ald_systick_irq_cbk(void) +{ + /* do nothing */ + return; +} + +/** + * @brief This function is called to increment a global variable "lib_tick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in Systick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void ald_inc_tick(void) +{ + ++lib_tick; + ald_systick_irq_cbk(); +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t ald_get_tick(void) +{ + return lib_tick; +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where lib_tick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param delay: specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void ald_delay_1ms(__IO uint32_t delay) +{ + uint32_t tick, __delay; + + switch (__systick_interval) + { + case ALD_SYSTICK_INTERVAL_1MS: + __delay = delay; + break; + + case ALD_SYSTICK_INTERVAL_10MS: + __delay = delay / 10; + break; + + case ALD_SYSTICK_INTERVAL_100MS: + __delay = delay / 100; + break; + + case ALD_SYSTICK_INTERVAL_1000MS: + __delay = delay / 1000; + break; + + default: + __delay = delay; + break; + } + + tick = ald_get_tick(); + __delay = __delay == 0 ? 1 : __delay; + + while ((ald_get_tick() - tick) < __delay) + ; +} + +/** + * @brief This function provides accurate delay (in microseconds) based + * on variable incremented. + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where lib_tick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param delay: specifies the delay time length, in microseconds(us). + * @retval None + */ +__weak void ald_delay_1us(__IO uint32_t delay) +{ + uint32_t start, now, delta, us_tick; + start = CORET->MTIME; + us_tick = ald_cmu_get_sys_clock() / 1000000UL; + + do + { + now = CORET->MTIME; + delta = now - start; + } + while (delta < (us_tick * delay)); +} + +/** + * @brief This method returns the ALD revision + * @retval version: 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t ald_get_ald_version(void) +{ + return __ALD_VERSION; +} + +/** + * @brief Configure the flash wait period. + * @param cycle: The period. + * @retval None + */ +void ald_flash_wait_config(uint8_t cycle) +{ + uint32_t tmp; + + tmp = MSC->MEMWAIT; + MODIFY_REG(tmp, MSC_MEMWAIT_FLASH_W_MSK, (0x30U | cycle) << MSC_MEMWAIT_FLASH_W_POSS); + MSC->MEMWAIT = tmp; + + return; +} + +/** + * @brief Waiting the specified bit in the register change to SET/RESET. + * @param reg: The register address. + * @param bit: The specified bit. + * @param status: The status for waiting. + * @param timeout: Timeout duration. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout) +{ + uint32_t tick = ald_get_tick(); + + assert_param(timeout > 0); + + if (status == SET) + { + while (!(IS_BIT_SET(*reg, bit))) + { + if (((ald_get_tick()) - tick) > timeout) + return ALD_TIMEOUT; + } + } + else + { + while ((IS_BIT_SET(*reg, bit))) + { + if (((ald_get_tick()) - tick) > timeout) + return ALD_TIMEOUT; + } + } + + return ALD_OK; +} + +/** + * @brief Configure interrupt. + * @param irq: Interrunpt type. + * @param prio: preempt priority(0-7). The larger the prio value, the higher the priority. + * @param status: Status. + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status) +{ + assert_param(IS_FUNC_STATE(status)); + + if (status == ENABLE) + { + csi_vic_set_prio(irq, prio); + csi_vic_enable_sirq(irq); + + if (irq == ADC_IRQn) + CLIC->CLICINT[irq].ATTR |= (CLIC_INTATTR_SHV_Msk | (0x1UL << CLIC_INTATTR_TRIG_Pos)); + } + else + { + csi_vic_disable_sirq(irq); + } + + return; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_utils.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_utils.h new file mode 100644 index 0000000000..c650c1b115 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_utils.h @@ -0,0 +1,229 @@ +/** + ********************************************************************************* + * + * @file ald_utils.h + * @brief This file contains the Utilities functions/types for the driver. + * + * @version V1.0 + * @date 8 Feb. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 8 Feb. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_UTILS_H__ +#define __ALD_UTILS_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ + +#include +#include "es32vf2264.h" +#include "type.h" + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Constants -------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup UTILS Utils + * @{ + */ + +/* Exported Variables -------------------------------------------------------- */ + +/** @addtogroup ALD_Private_Variables Private Variables + * @{ + */ + +/** + * @brief SysTick interval + */ +extern uint32_t __systick_interval; + +/** + * @}ALD_Private_Variables + */ + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup ALD_Public_Types Public Types + * @{ + */ + +/** + * @brief ALD Status structures definition + */ +typedef enum +{ + ALD_OK = 0x0U, /**< OK */ + ALD_ERROR = 0x1U, /**< ERROR */ + ALD_BUSY = 0x2U, /**< BUSY */ + ALD_TIMEOUT = 0x3U, /**< TIMEOUT */ +} ald_status_t; + +/** + * @brief SysTick interval definition + */ +typedef enum +{ + ALD_SYSTICK_INTERVAL_1MS = 1000U, /**< Interval is 1ms */ + ALD_SYSTICK_INTERVAL_10MS = 100U, /**< Interval is 10ms */ + ALD_SYSTICK_INTERVAL_100MS = 10U, /**< Interval is 100ms */ + ALD_SYSTICK_INTERVAL_1000MS = 1U, /**< Interval is 1s */ +} ald_systick_interval_t; +/** + * @}ALD_Public_Types + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** + * @brief Nested IRQ start : Save CSR and enable global interrupt. + */ +#ifdef NEST_INT_ENABLE + #define ALD_NEST_INT_START(); \ + uint32_t val_mcause, val_mepc, val_mstatus; \ + __ASM volatile("csrr %0, mcause" : "=r"(val_mcause)); \ + __ASM volatile("csrr %0, mepc" : "=r"(val_mepc)); \ + __ASM volatile("csrr %0, mstatus" : "=r"(val_mstatus)); \ + __enable_irq(); +#else + #define ALD_NEST_INT_START(); +#endif /* NEST_INT_ENABLE */ + +/** + * @brief Nested IRQ end : Restore CSR and disable global interrupt. + */ +#ifdef NEST_INT_ENABLE + #define ALD_NEST_INT_END(); \ + __disable_irq(); \ + __ASM volatile("csrw mstatus, %0" : : "r"(val_mstatus)); \ + __ASM volatile("csrw mepc, %0" : : "r"(val_mepc)); \ + __ASM volatile("csrw mcause, %0" : : "r"(val_mcause)); +#else + #define ALD_NEST_INT_END(); +#endif /* NEST_INT_ENABLE */ + +/** @defgroup ALD_Public_Macros Public Macros + * @{ + */ +#define ALD_MAX_DELAY 0xFFFFFFFFU +#define IS_BIT_SET(reg, bit) (((reg) & (bit)) != RESET) +#define IS_BIT_CLR(reg, bit) (((reg) & (bit)) == RESET) +#define ALD_RESET_HANDLE_STATE(x) ((x)->state = 0) +#define __LOCK(x) \ + do { \ + if ((x)->lock == LOCK) { \ + return ALD_BUSY; \ + } \ + else { \ + (x)->lock = LOCK; \ + } \ + } while (0) +#define __UNLOCK(x) \ + do { \ + (x)->lock = UNLOCK; \ + } while (0) +#define ALD_PANIC() \ + do { \ + while (1) \ + ; \ + } while (0) + + +/** + * @}ALD_Public_Macros + */ + +/** @defgroup ALD_Private_Macros Private Macros + * @{ + */ +#define IS_SYSTICK_INTERVAL(x) (((x) == ALD_SYSTICK_INTERVAL_1MS) || \ + ((x) == ALD_SYSTICK_INTERVAL_10MS) || \ + ((x) == ALD_SYSTICK_INTERVAL_100MS) || \ + ((x) == ALD_SYSTICK_INTERVAL_1000MS)) +/** + * @}ALD_Private_Macros + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @addtogroup ALD_Public_Functions + * @{ + */ + +/** @addtogroup ALD_Public_Functions_Group1 Initialization Function + * @{ + */ + +/* Initialization functions */ +void ald_cmu_init(void); +void ald_tick_init(uint32_t prio); +void ald_systick_interval_select(ald_systick_interval_t value); + +/** + * @}ALD_Public_Functions_Group1 + */ + +/** @addtogroup ALD_Public_Functions_Group2 Control functions + * @{ + */ +/* Peripheral Control functions */ +void ald_inc_tick(void); +void ald_systick_irq_cbk(void); +void ald_delay_1ms(__IO uint32_t delay); +void ald_delay_1us(__IO uint32_t delay); +uint32_t ald_get_tick(void); +uint32_t ald_get_ald_version(void); +void ald_flash_wait_config(uint8_t cycle); +ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout); +void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status); +/** + * @}ALD_Public_Functions_Group2 + */ + +/** + * @}ALD_Public_Functions + */ + +/** + * @}UTILS + */ + +/** + * @}ES32VF2264_ALD + */ + +#ifdef __cplusplus + } +#endif /* __cplusplus */ + +#endif /* __ALD_UTILS_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_wdt.c b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_wdt.c new file mode 100644 index 0000000000..98c5296042 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_wdt.c @@ -0,0 +1,286 @@ +/** + ********************************************************************************* + * + * @file ald_wdt.c + * @brief WDT module driver. + * + * @version V1.0 + * @date 07 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_wdt.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @defgroup WDT WDT + * @brief WDT module driver + * @{ + */ +/** @defgroup WWDT_Public_Functions WWDT Public Functions + * @brief Init and configure WWDT function + * @{ + */ +/** + * @brief Initializes the WWDT according to the specified parameters. + * @param load: Specifies the free-running downcounter value. + * @param win: specifics the no dog windows, + * the parameter can be one of the following values: + * @arg @ref WWDT_WIN_25 No dog window size: 25% + * @arg @ref WWDT_WIN_50 No dog window size: 50% + * @arg @ref WWDT_WIN_75 No dog window size: 75% + * @arg @ref WWDT_WIN_00 No dog window size: 0% + * @param interrupt: Enable or disable interrupt. + * @retval None + */ +void ald_wwdt_init(uint32_t load, ald_wwdt_win_t win, type_func_t interrupt) +{ + assert_param(IS_WWDT_WIN_TYPE(win)); + assert_param(IS_FUNC_STATE(interrupt)); + + ALD_WWDT_UNLOCK(); + WRITE_REG(WWDT->LOAD, load); + MODIFY_REG(WWDT->CON, WWDT_CON_WWDTWIN_MSK, win << WWDT_CON_WWDTWIN_POSS); + SET_BIT(WWDT->CON, WWDT_CON_CLKS_MSK); + SET_BIT(WWDT->CON, WWDT_CON_RSTEN_MSK); + MODIFY_REG(WWDT->CON, WWDT_CON_IE_MSK, interrupt << WWDT_CON_IE_POS); + ALD_WWDT_LOCK(); + + return; +} + +/** + * @brief Initializes the WWDT without reset according to the specified parameters. + * @param load: Specifies the free-running downcounter value. + * @param win: specifics the no dog windows, + * the parameter can be one of the following values: + * @arg @ref WWDT_WIN_25 No dog window size: 25% + * @arg @ref WWDT_WIN_50 No dog window size: 50% + * @arg @ref WWDT_WIN_75 No dog window size: 75% + * @arg @ref WWDT_WIN_00 No dog window size: 0% + * @param interrupt: Enable or disable interrupt. + * @retval None + */ +void ald_wwdt_init_no_reset(uint32_t load, ald_wwdt_win_t win, type_func_t interrupt) +{ + assert_param(IS_WWDT_WIN_TYPE(win)); + assert_param(IS_FUNC_STATE(interrupt)); + + ALD_WWDT_UNLOCK(); + WRITE_REG(WWDT->LOAD, load); + MODIFY_REG(WWDT->CON, WWDT_CON_WWDTWIN_MSK, win << WWDT_CON_WWDTWIN_POSS); + SET_BIT(WWDT->CON, WWDT_CON_CLKS_MSK); + CLEAR_BIT(WWDT->CON, WWDT_CON_RSTEN_MSK); + MODIFY_REG(WWDT->CON, WWDT_CON_IE_MSK, interrupt << WWDT_CON_IE_POS); + ALD_WWDT_LOCK(); + + return; +} + +/** + * @brief Start the WWDT + * @retval None + */ +void ald_wwdt_start(void) +{ + ALD_WWDT_UNLOCK(); + SET_BIT(WWDT->CON, WWDT_CON_EN_MSK); + ALD_WWDT_LOCK(); + + return; +} + +/** + * @brief Get the free-running downcounter value + * @retval Value + */ +uint32_t ald_wwdt_get_value(void) +{ + return WWDT->VALUE; +} + +/** + * @brief Get interrupt state + * @retval Value + */ +it_status_t ald_wwdt_get_flag_status(void) +{ + if (READ_BIT(WWDT->RIS, WWDT_RIS_WWDTIF_MSK)) + return SET; + + return RESET; +} + +/** + * @brief Clear interrupt state + * @retval None + */ +void ald_wwdt_clear_flag_status(void) +{ + ALD_WWDT_UNLOCK(); + WRITE_REG(WWDT->INTCLR, 0x55AA); + ALD_WWDT_LOCK(); + + return; +} + +/** + * @brief Refreshes the WWDT + * @retval None + */ +void ald_wwdt_feed_dog(void) +{ + ALD_WWDT_UNLOCK(); + WRITE_REG(WWDT->INTCLR, 0xFFFFFFFF); + ALD_WWDT_LOCK(); + + return; +} +/** + * @} + */ + +/** @defgroup IWDT_Public_Functions IWDT Public Functions + * @brief Init and configure IWDT function + * @{ + */ +/** + * @brief Initializes the IWDG according to the specified parameters. + * @param load: Specifies the free-running downcounter value. + * @param interrupt: Enable or disable interrupt. + * @retval None + */ +void ald_iwdt_init(uint32_t load, type_func_t interrupt) +{ + assert_param(IS_FUNC_STATE(interrupt)); + + ALD_IWDT_UNLOCK(); + WRITE_REG(IWDT->LOAD, load); + SET_BIT(IWDT->CON, IWDT_CON_CLKS_MSK); + SET_BIT(IWDT->CON, IWDT_CON_RSTEN_MSK); + MODIFY_REG(IWDT->CON, IWDT_CON_IE_MSK, interrupt << IWDT_CON_IE_POS); + ALD_IWDT_LOCK(); + + return; +} + +/** + * @brief Initializes the IWDG without reset according to the specified parameters. + * @param load: Specifies the free-running downcounter value. + * @param interrupt: Enable or disable interrupt. + * @retval None + */ +void ald_iwdt_init_no_reset(uint32_t load, type_func_t interrupt) +{ + assert_param(IS_FUNC_STATE(interrupt)); + + ALD_IWDT_UNLOCK(); + WRITE_REG(IWDT->LOAD, load); + SET_BIT(IWDT->CON, IWDT_CON_CLKS_MSK); + CLEAR_BIT(IWDT->CON, IWDT_CON_RSTEN_MSK); + MODIFY_REG(IWDT->CON, IWDT_CON_IE_MSK, interrupt << IWDT_CON_IE_POS); + ALD_IWDT_LOCK(); + + return; +} + +/** + * @brief Start the IWDT + * @retval None + */ +void ald_iwdt_start(void) +{ + ALD_IWDT_UNLOCK(); + SET_BIT(IWDT->CON, IWDT_CON_EN_MSK); + ALD_IWDT_LOCK(); + + return; +} + +/** + * @brief Get the free-running downcounter value + * @retval Value + */ +uint32_t ald_iwdt_get_value(void) +{ + return IWDT->VALUE; +} + +/** + * @brief Get interrupt state + * @retval Value + */ +it_status_t ald_iwdt_get_flag_status(void) +{ + if (READ_BIT(IWDT->RIS, IWDT_RIS_WDTIF_MSK)) + return SET; + + return RESET; +} + +/** + * @brief Clear interrupt state + * @retval None + */ +void ald_iwdt_clear_flag_status(void) +{ + ALD_IWDT_UNLOCK(); + WRITE_REG(IWDT->INTCLR, 0x55AA); + ALD_IWDT_LOCK(); + return; +} + +/** + * @brief Refreshes the WWDT + * @retval None + */ +void ald_iwdt_feed_dog(void) +{ + ALD_IWDT_UNLOCK(); + WRITE_REG(IWDT->INTCLR, 0xFFFFFFFF); + ALD_IWDT_LOCK(); + + return; +} +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_wdt.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_wdt.h new file mode 100644 index 0000000000..8c34934d5c --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_wdt.h @@ -0,0 +1,147 @@ +/** + ********************************************************************************* + * + * @file ald_wdt.h + * @brief Header file of WDT module driver. + * + * @version V1.0 + * @date 07 Mar. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 Mar. 2023 Lisq The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_WDT_H__ +#define __ALD_WDT_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ + +#include "ald_utils.h" + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Constants -------------------------------------------------------- */ + +/** @addtogroup ES32VF2264_ALD + * @{ + */ + +/** @addtogroup WDT + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup WDT_Public_Types WDT Public Types + * @{ + */ + +/** + * @brief Wwdt no dog window + */ +typedef enum +{ + ALD_WWDT_WIN_25 = 0x0U, /**< No dog window size: 25% */ + ALD_WWDT_WIN_50 = 0x1U, /**< No dog window size: 50% */ + ALD_WWDT_WIN_75 = 0x2U, /**< No dog window size: 75% */ + ALD_WWDT_WIN_00 = 0x3U, /**< No dog window size: 0% */ +} ald_wwdt_win_t; + +/** + * @} + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** + * @defgroup WDT_Private_Macros WDT Private Macros + * @{ + */ +#define ALD_WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551U);} +#define ALD_WWDT_LOCK() {WRITE_REG(WWDT->LOCK, 0xFFFFFFFFU);} +#define ALD_IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551U);} +#define ALD_IWDT_LOCK() {WRITE_REG(IWDT->LOCK, 0xFFFFFFFFU);} + +/** + * @} + */ + +/** + * @addtogroup WDT_Private_Macros WDT Private Macros + * @{ + */ +#define IS_WWDT_WIN_TYPE(x) ((x == ALD_WWDT_WIN_25) || \ + (x == ALD_WWDT_WIN_50) || \ + (x == ALD_WWDT_WIN_75) || \ + (x == ALD_WWDT_WIN_00)) +#define IS_FUNC_STATE(x) (((x) == DISABLE) || \ + ((x) == ENABLE)) +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @addtogroup WWDT_Public_Functions + * @{ + */ +void ald_wwdt_init(uint32_t load, ald_wwdt_win_t win, type_func_t interrupt); +void ald_wwdt_init_no_reset(uint32_t load, ald_wwdt_win_t win, type_func_t interrupt); +void ald_wwdt_start(void); +uint32_t ald_wwdt_get_value(void); +it_status_t ald_wwdt_get_flag_status(void); +void ald_wwdt_clear_flag_status(void); +void ald_wwdt_feed_dog(void); +/** + * @} + */ + +/** @addtogroup IWDT_Public_Functions + * @{ + */ +void ald_iwdt_init(uint32_t load, type_func_t interrupt); +void ald_iwdt_init_no_reset(uint32_t load, type_func_t interrupt); +void ald_iwdt_start(void); +uint32_t ald_iwdt_get_value(void); +it_status_t ald_iwdt_get_flag_status(void); +void ald_iwdt_clear_flag_status(void); +void ald_iwdt_feed_dog(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALD_WDT_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/ald/type.h b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/type.h new file mode 100644 index 0000000000..f69eb8e2fe --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/ald/type.h @@ -0,0 +1,155 @@ +/********************************************************************************** + * + * @file type.h + * @brief define type + * + * @date 30 Jan. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 30 Jan. 2023 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __TYPE_H__ +#define __TYPE_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ +#include + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Macros ----------------------------------------------------------- */ + +#if defined (__CC_ARM) +#define __INLINE__ __inline +#define __STATIC_INLINE__ static __inline +#else +#define __INLINE__ inline +#define __STATIC_INLINE__ static inline +#endif /* __CC_ARM */ + +#define __isr__ + +/* Exported Types ------------------------------------------------------------ */ + +typedef enum +{ + RESET = 0x0U, + SET = 0x1U, +} flag_status_t, it_status_t; + +typedef enum +{ + BIT_RESET = 0x0U, + BIT_SET = 0x1U, +} bit_status_t; + +typedef enum +{ + DISABLE = 0x0U, + ENABLE = 0x1U, +} type_func_t, TypeFunc; + +typedef enum +{ + FALSE = 0x0U, + TRUE = 0x1U, +} type_bool_t; + +typedef enum +{ + UNLOCK = 0x0U, + LOCK = 0x1U, +} lock_state_t; + +/* Exported Macros ----------------------------------------------------------- */ + +#define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK)) +#define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE)) + +#define BIT(x) ((1U << (x))) +#define BITS(s, e) ((0xffffffffU << (s)) & (0xffffffffU >> (31 - (e)))) +#define SET_BIT(reg, bit) ((reg) |= (bit)) +#define CLEAR_BIT(reg, bit) ((reg) &= ~(bit)) +#define READ_BIT(reg, bit) ((reg) & (bit)) +#define READ_BITS(reg, msk, s) (((reg) & (msk)) >> (s)) +#define CLEAR_REG(reg) ((reg) = (0x0)) +#define WRITE_REG(reg, val) ((reg) = (val)) +#define READ_REG(reg) ((reg)) +#define MODIFY_REG(reg, clearmask, setmask) \ + WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask))) +#define UNUSED(x) ((void)(x)) + +#ifdef USE_ASSERT +#define assert_param(x) \ + do { \ + if (!(x)) { \ + __disable_irq(); \ + while (1) \ + ; \ + } \ + } while (0) +#else +#define assert_param(x) +#endif /* USE_ASSERT */ + +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /* PER base address */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /* RAM base address */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /* Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /* SRAM Address Space bit-band area */ + +/* Exported Functions -------------------------------------------------------- */ + +__STATIC_INLINE__ void BITBAND_PER(volatile uint32_t *addr, uint32_t bit, uint32_t val) +{ + uint32_t tmp = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) << 5) + (bit << 2); + *((volatile uint32_t *)tmp) = (uint32_t)val; +} + +__STATIC_INLINE__ void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val) +{ + uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) << 5) + (bit << 2); + *((volatile uint32_t *)tmp) = (uint32_t)val; +} + +#if defined ( __GNUC__ ) +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __GNUC__ */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __TYPE_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/core_rv32.h b/os/common/ext/CMSIS/ES32/ES32VF2264/core_rv32.h new file mode 100644 index 0000000000..7127d79348 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/core_rv32.h @@ -0,0 +1,1537 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + */ + + +/****************************************************************************** + * @file core_rv32.h + * @brief CSI RV32 Core Peripheral Access Layer Header File + * @version V1.0 + * @date 01. Sep 2018 + ******************************************************************************/ + +#ifndef __CORE_RV32_H_GENERIC +#define __CORE_RV32_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * CSI definitions + ******************************************************************************/ +/** + \ingroup RV32 + @{ + */ + +#ifndef __RV32 +#define __RV32 (0x01U) +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_RV32_H_GENERIC */ + +#ifndef __CSI_GENERIC + +#ifndef __CORE_RV32_H_DEPENDANT +#define __CORE_RV32_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#ifndef __RV32_REV +#define __RV32_REV 0x0000U +#endif + +#ifndef __VIC_PRIO_BITS +#define __VIC_PRIO_BITS 2U +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 1U +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 1U +#endif + +#ifndef __ICACHE_PRESENT +#define __ICACHE_PRESENT 1U +#endif + +#ifndef __DCACHE_PRESENT +#define __DCACHE_PRESENT 1U +#endif + +#include + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CSI_glob_defs CSI Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group CK802 */ + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core CLIC Register + ******************************************************************************/ +/** + \defgroup CSI_core_register Defines and Type Definitions + \brief Type definitions and defines for CK80X processor based devices. +*/ + +/** + \ingroup CSI_core_register + \defgroup CSI_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \ingroup CSI_core_register + \defgroup CSI_CLIC Core-Local Interrupt Controller (CLIC) + \brief Type definitions for the CLIC Registers + @{ + */ + +/** + \brief Access to the structure of a vector interrupt controller. + */ +typedef struct { + __IOM uint8_t IP; /*!< Offset: 0x000 (R/W) Interrupt set pending register */ + __IOM uint8_t IE; /*!< Offset: 0x004 (R/W) Interrupt set enable register */ + __IOM uint8_t ATTR; /*!< Offset: 0x008 (R/W) Interrupt set attribute register */ + __IOM uint8_t CTL; /*!< Offset: 0x00C (R/W) Interrupt control register */ +} CLIC_INT_Control; + +typedef struct { + __IOM uint32_t CLICCFG:8; /*!< Offset: 0x000 (R/W) CLIC configure register */ + __IM uint32_t CLICINFO; + __IOM uint32_t MINTTHRESH; + uint32_t RESERVED[1021]; + CLIC_INT_Control CLICINT[4096]; +} ES_CLIC_Type; + +#define CLIC_INFO_CLICINTCTLBITS_Pos 21U +#define CLIC_INFO_CLICINTCTLBITS_Msk (0xFUL << CLIC_INFO_CLICINTCTLBITS_Pos) + +#define CLIC_INTIP_IP_Pos 0U /*!< CLIC INTIP: IP Position */ +#define CLIC_INTIP_IP_Msk (0x1UL << CLIC_INTIP_IP_Pos) /*!< CLIC INTIP: IP Mask */ + +#define CLIC_INTIE_IE_Pos 0U /*!< CLIC INTIE: IE Position */ +#define CLIC_INTIE_IE_Msk (0x1UL << CLIC_INTIE_IE_Pos) /*!< CLIC INTIE: IE Mask */ + +#define CLIC_INTIE_T_Pos 7U /*!< CLIC INTIE: T Position */ +#define CLIC_INTIE_T_Msk (0x1UL << CLIC_INTIE_T_Pos) /*!< CLIC INTIE: T Mask */ + +#define CLIC_INTATTR_TRIG_Pos 1U /*!< CLIC INTATTR: TRIG Position */ +#define CLIC_INTATTR_TRIG_Msk (0x3UL << CLIC_INTATTR_TRIG_Pos) /*!< CLIC INTATTR: TRIG Mask */ + +#define CLIC_INTATTR_SHV_Pos 0U /*!< CLIC INTATTR: SHV Position */ +#define CLIC_INTATTR_SHV_Msk (0x1UL << CLIC_INTATTR_SHV_Pos) /*!< CLIC INTATTR: SHV Mask */ + +#define CLIC_INTCFG_NVBIT_Pos 5U /*!< CLIC INTCFG: NVBIT Position */ +#define CLIC_INTCFG_NVBIT_Msk (0x1UL << CLIC_INTCFG_NVBIT_Pos) /*!< CLIC INTCFG: NVBIT Mask */ + +#define CLIC_INTCFG_PRIO_Pos 5U /*!< CLIC INTCFG: INTCFG Position */ +#define CLIC_INTCFG_PRIO_Msk (0x7UL << CLIC_INTCFG_PRIO_Pos) /*!< CLIC INTCFG: INTCFG Mask */ + +#define CLIC_CLICCFG_NVBIT_Pos 0U /*!< CLIC CLICCFG: NVBIT Position */ +#define CLIC_CLICCFG_NVBIT_Msk (0x1UL << CLIC_CLICCFG_NVBIT_Pos) /*!< CLIC CLICCFG: NVBIT Mask */ + +#define CLIC_CLICCFG_NLBIT_Pos 1U /*!< CLIC CLICCFG: NLBIT Position */ +#define CLIC_CLICCFG_NLBIT_Msk (0xFUL << CLIC_CLICCFG_NLBIT_Pos) /*!< CLIC CLICCFG: NLBIT Mask */ + +#define CLIC_CLICCFG_NMBIT_Pos 5U /*!< CLIC CLICCFG: NMBIT Position */ +#define CLIC_CLICCFG_NMBIT_Msk (0x3UL << CLIC_CLICCFG_NMBIT_Pos) /*!< CLIC CLICCFG: NMBIT Mask */ + +/*@} end of group CSI_CLIC */ + +/** + \ingroup CSI_core_register + \defgroup CSI_PMP Physical Memory Protection (PMP) + \brief Type definitions for the PMP Registers + @{ + */ + +#define PMP_PMPCFG_R_Pos 0U /*!< PMP PMPCFG: R Position */ +#define PMP_PMPCFG_R_Msk (0x1UL << PMP_PMPCFG_R_Pos) /*!< PMP PMPCFG: R Mask */ + +#define PMP_PMPCFG_W_Pos 1U /*!< PMP PMPCFG: W Position */ +#define PMP_PMPCFG_W_Msk (0x1UL << PMP_PMPCFG_W_Pos) /*!< PMP PMPCFG: W Mask */ + +#define PMP_PMPCFG_X_Pos 2U /*!< PMP PMPCFG: X Position */ +#define PMP_PMPCFG_X_Msk (0x1UL << PMP_PMPCFG_X_Pos) /*!< PMP PMPCFG: X Mask */ + +#define PMP_PMPCFG_A_Pos 3U /*!< PMP PMPCFG: A Position */ +#define PMP_PMPCFG_A_Msk (0x3UL << PMP_PMPCFG_A_Pos) /*!< PMP PMPCFG: A Mask */ + +#define PMP_PMPCFG_L_Pos 7U /*!< PMP PMPCFG: L Position */ +#define PMP_PMPCFG_L_Msk (0x1UL << PMP_PMPCFG_L_Pos) /*!< PMP PMPCFG: L Mask */ + +typedef enum { + REGION_SIZE_4B = -1, + REGION_SIZE_8B = 0, + REGION_SIZE_16B = 1, + REGION_SIZE_32B = 2, + REGION_SIZE_64B = 3, + REGION_SIZE_128B = 4, + REGION_SIZE_256B = 5, + REGION_SIZE_512B = 6, + REGION_SIZE_1KB = 7, + REGION_SIZE_2KB = 8, + REGION_SIZE_4KB = 9, + REGION_SIZE_8KB = 10, + REGION_SIZE_16KB = 11, + REGION_SIZE_32KB = 12, + REGION_SIZE_64KB = 13, + REGION_SIZE_128KB = 14, + REGION_SIZE_256KB = 15, + REGION_SIZE_512KB = 16, + REGION_SIZE_1MB = 17, + REGION_SIZE_2MB = 18, + REGION_SIZE_4MB = 19, + REGION_SIZE_8MB = 20, + REGION_SIZE_16MB = 21, + REGION_SIZE_32MB = 22, + REGION_SIZE_64MB = 23, + REGION_SIZE_128MB = 24, + REGION_SIZE_256MB = 25, + REGION_SIZE_512MB = 26, + REGION_SIZE_1GB = 27, + REGION_SIZE_2GB = 28, + REGION_SIZE_4GB = 29, + REGION_SIZE_8GB = 30, + REGION_SIZE_16GB = 31 +} region_size_e; + +typedef enum { + ADDRESS_MATCHING_NONE = 0, + ADDRESS_MATCHING_TOR = 1, + ADDRESS_MATCHING_NA4 = 2, + ADDRESS_MATCHING_NAPOT = 3 +} address_matching_e; + +typedef struct { + uint32_t r: 1; /* readable enable */ + uint32_t w: 1; /* writeable enable */ + uint32_t x: 1; /* execable enable */ + address_matching_e a: 2; /* address matching mode */ + uint32_t reserved: 2; /* reserved */ + uint32_t l: 1; /* lock enable */ +} mpu_region_attr_t; + +/*@} end of group CSI_PMP */ + +/* CACHE Register Definitions */ +#define CACHE_MHCR_L0BTB_Pos 12U /*!< CACHE MHCR: L0BTB Position */ +#define CACHE_MHCR_L0BTB_Msk (0x1UL << CACHE_MHCR_L0BTB_Pos) /*!< CACHE MHCR: WA Mask */ + +#define CACHE_MHCR_BPE_Pos 5U /*!< CACHE MHCR: BPE Position */ +#define CACHE_MHCR_BPE_Msk (0x1UL << CACHE_MHCR_BPE_Pos) /*!< CACHE MHCR: BPE Mask */ + +#define CACHE_MHCR_RS_Pos 4U /*!< CACHE MHCR: RS Position */ +#define CACHE_MHCR_RS_Msk (0x1UL << CACHE_MHCR_RS_Pos) /*!< CACHE MHCR: RS Mask */ + +#define CACHE_MHCR_WA_Pos 3U /*!< CACHE MHCR: WA Position */ +#define CACHE_MHCR_WA_Msk (0x1UL << CACHE_MHCR_WA_Pos) /*!< CACHE MHCR: WA Mask */ + +#define CACHE_MHCR_WB_Pos 2U /*!< CACHE MHCR: WB Position */ +#define CACHE_MHCR_WB_Msk (0x1UL << CACHE_MHCR_WB_Pos) /*!< CACHE MHCR: WB Mask */ + +#define CACHE_MHCR_DE_Pos 1U /*!< CACHE MHCR: DE Position */ +#define CACHE_MHCR_DE_Msk (0x1UL << CACHE_MHCR_DE_Pos) /*!< CACHE MHCR: DE Mask */ + +#define CACHE_MHCR_IE_Pos 0U /*!< CACHE MHCR: IE Position */ +#define CACHE_MHCR_IE_Msk (0x1UL << CACHE_MHCR_IE_Pos) /*!< CACHE MHCR: IE Mask */ + +#define CACHE_INV_ADDR_Pos 5U +#define CACHE_INV_ADDR_Msk (0xFFFFFFFFUL << CACHE_INV_ADDR_Pos) + +/*@} end of group CSI_CACHE */ + +/** + \ingroup CSI_core_register + \defgroup CSI_SYSMAP system map (SYSMAP) + \brief Type definitions for the SYSMAP Registers + @{ + */ + +#define SYSMAP_SYSMAPCFG_B_Pos 0U /*!< SYSMAP SYSMAPCFG: B Position */ +#define SYSMAP_SYSMAPCFG_B_Msk (0x1UL << SYSMAP_SYSMAPCFG_B_Pos) /*!< SYSMAP SYSMAPCFG: B Mask */ + +#define SYSMAP_SYSMAPCFG_C_Pos 1U /*!< SYSMAP SYSMAPCFG: C Position */ +#define SYSMAP_SYSMAPCFG_C_Msk (0x1UL << SYSMAP_SYSMAPCFG_C_Pos) /*!< SYSMAP SYSMAPCFG: C Mask */ + +#define SYSMAP_SYSMAPCFG_SO_Pos 2U /*!< SYSMAP SYSMAPCFG: SO Position */ +#define SYSMAP_SYSMAPCFG_SO_Msk (0x1UL << SYSMAP_SYSMAPCFG_SO_Pos) /*!< SYSMAP SYSMAPCFG: SO Mask */ + +/** + \ingroup CSI_core_register + \defgroup CSI_SYSMAP system map (SYSMAP) + \brief Type definitions for the SYSMAP Registers + @{ + */ +typedef struct { + __IOM uint32_t SYSMAPADDR0; /*!< Offset: 0x000 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPCFG0; /*!< Offset: 0x004 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPADDR1; /*!< Offset: 0x008 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPCFG1; /*!< Offset: 0x00c (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPADDR2; /*!< Offset: 0x010 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPCFG2; /*!< Offset: 0x014 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPADDR3; /*!< Offset: 0x018 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPCFG3; /*!< Offset: 0x01c (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPADDR4; /*!< Offset: 0x020 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPCFG4; /*!< Offset: 0x024 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPADDR5; /*!< Offset: 0x028 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPCFG5; /*!< Offset: 0x02c (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPADDR6; /*!< Offset: 0x030 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPCFG6; /*!< Offset: 0x034 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPADDR7; /*!< Offset: 0x038 (R/W) SYSMAP configure register */ + __IOM uint32_t SYSMAPCFG7; /*!< Offset: 0x03c (R/W) SYSMAP configure register */ +} SYSMAP_Type; + + +/*@} end of group CSI_SYSMAP */ + + +/** + \ingroup CSI_core_register + \defgroup CSI_SysTick System Tick Timer (CORET) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief The data structure of the access system timer. + */ +typedef struct { + __IOM unsigned long long MTIMECMP; /*!< Offset: 0x000 (R/W) Timer compare register */ + uint32_t RESERVED[8187]; + __IM unsigned long long MTIME; /*!< Offset: 0x7FFC (R) Timer current register */ +} CORET_Type; + +/*@} end of group CSI_SysTick */ + +/** + \ingroup CSI_core_register + \defgroup CSI_DCC + \brief Type definitions for the DCC. + @{ + */ + +/** + \brief Access to the data structure of DCC. + */ +typedef struct { + uint32_t RESERVED0[13U]; + __IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */ + __IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */ + uint32_t RESERVED1[6U]; + union { + __IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/ + __OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/ + }; + +} DCC_Type; + +#define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */ +#define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */ + +#define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */ +#define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */ + +#define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */ +#define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */ + +#define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */ +#define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */ + +/*@} end of group CSI_DCC */ + + +/** + \ingroup CSI_core_register + \defgroup CSI_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD_(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL_(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CSI_core_bitfield */ + +/** + \ingroup CSI_core_register + \defgroup CSI_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of CK802 Hardware */ +#define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */ +#define CORET_BASE (0xE0004000UL) /*!< CORET Base Address */ +#define CLIC_BASE (0xE0800000UL) /*!< CLIC Base Address */ +#define SYSMAP_BASE (0xEFFFF000UL) /*!< SYSMAP Base Address */ +#define DCC_BASE (0xE4010000UL) /*!< DCC Base Address */ +#define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */ + +#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */ +#define CLIC ((ES_CLIC_Type *) CLIC_BASE ) /*!< CLIC configuration struct */ +#define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */ +#define SYSMAP ((SYSMAP_Type *) SYSMAP_BASE ) /*!< SYSMAP configuration struct */ +#define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */ + +/*@} */ + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core VIC Functions + - Core CORET Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CSI_Core_FunctionInterface Functions and Instructions Reference +*/ + +/* ########################## VIC functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_VICFunctions VIC Functions + \brief Functions that manage interrupts and exceptions via the VIC. + @{ + */ + +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) ) +#define _IP2_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +/** + \brief Enable External Interrupt + \details Enable a device-specific interrupt in the VIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IE |= CLIC_INTIE_IE_Msk; +} + +/** + \brief Disable External Interrupt + \details Disable a device-specific interrupt in the VIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IE &= ~CLIC_INTIE_IE_Msk; +} + +/** + \brief Enable External Secure Interrupt + \details Enable a secure device-specific interrupt in the VIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IE |= (CLIC_INTIE_IE_Msk | CLIC_INTIE_T_Msk); + CLIC->CLICINT[IRQn].ATTR |= CLIC_INTATTR_SHV_Msk; +} + +/** + \brief Disable External Secure Interrupt + \details Disable a secure device-specific interrupt in the VIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IE &= ~(CLIC_INTIE_IE_Msk | CLIC_INTIE_T_Msk); +} + +/** + \brief Check Interrupt is Enabled or not + \details Read the enabled register in the VIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not enabled. + \return 1 Interrupt status is enabled. + */ +__STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn) +{ + return (uint32_t)(CLIC->CLICINT[IRQn].IE & CLIC_INTIE_IE_Msk); +} + +/** + \brief Check Interrupt is Pending or not + \details Read the pending register in the VIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn) +{ + return (uint32_t)(CLIC->CLICINT[IRQn].IP & CLIC_INTIP_IP_Msk); +} + +/** + \brief Set Pending Interrupt + \details Set the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IP |= CLIC_INTIP_IP_Msk; +} + +/** + \brief Clear Pending Interrupt + \details Clear the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn) +{ + CLIC->CLICINT[IRQn].IP &= ~CLIC_INTIP_IP_Msk; +} + +/** + \brief Set Interrupt Priority + \details Set the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority) +{ + CLIC->CLICCFG |= 0x6; /* NLBITS = 3 */ + uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos; + CLIC->CLICINT[IRQn].CTL = (CLIC->CLICINT[IRQn].CTL & (~CLIC_INTCFG_PRIO_Msk)) | (priority << (8 - nlbits)); +} + +/** + \brief Get Interrupt Priority + \details Read the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn) +{ + uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos; + return CLIC->CLICINT[IRQn].CTL >> (8 - nlbits); +} + +/** + \brief Get Interrupt thresh + \details Read the thresh of interrupt + Only the interrupt priority is greater than the value of thresh, the interrupt can be responded to + \return Interrupt thresh value(0~255). + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t csi_vic_get_thresh(void) +{ + return CLIC->MINTTHRESH >> 24; +} + +/** + \brief Set Interrupt thresh + \details Write the thresh of interrupt + Only the interrupt priority is greater than the value of thresh, the interrupt can be responded to + \param [in] Interrupt thresh value(0~255). + */ +__STATIC_INLINE uint32_t csi_vic_set_thresh(uint32_t thresh) +{ + uint32_t temp = CLIC->MINTTHRESH; + uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos; + + if(!nlbits) + CLIC->MINTTHRESH = 0xff << 24; + + CLIC->MINTTHRESH = thresh << 24; + return temp; +} + +/** + \brief Set interrupt handler + \details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors. + \param [in] IRQn Interrupt number. + \param [in] handler Interrupt handler. + */ +__STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler) +{ + if (IRQn >= 0 && IRQn < 1024) { + uint32_t *vectors = (uint32_t *)__get_MTVT(); + vectors[IRQn] = handler; + } +} + +/** + \brief Get interrupt handler + \details Get the address of interrupt handler function. + \param [in] IRQn Interrupt number. + */ +__STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn) +{ + if (IRQn >= 0 && IRQn < 1024) { + uint32_t *vectors = (uint32_t *)__get_MTVT(); + return (uint32_t)vectors[IRQn]; + } + + return 0; +} + +/*@} end of CSI_Core_VICFunctions */ + +/* ########################## PMP functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_PMPFunctions PMP Functions + \brief Functions that manage interrupts and exceptions via the VIC. + @{ + */ + +/** + \brief configure memory protected region. + \details + \param [in] idx memory protected region (0, 1, 2, ..., 15). + \param [in] base_addr base address must be aligned with page size. + \param [in] size \ref region_size_e. memory protected region size. + \param [in] attr \ref region_size_t. memory protected region attribute. + \param [in] enable enable or disable memory protected region. + */ +__STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size, + mpu_region_attr_t attr, uint32_t enable) +{ + uint8_t pmpxcfg = 0; + uint32_t addr = 0; + + if (idx > 15) { + return; + } + + if (!enable) { + attr.a = ADDRESS_MATCHING_NONE; + } + + if (attr.a == ADDRESS_MATCHING_TOR) { + addr = base_addr >> 2; + } else { + if (size == REGION_SIZE_4B) { + addr = base_addr >> 2; + attr.a = ADDRESS_MATCHING_NA4; + } else { + addr = ((base_addr >> 2) & (0xFFFFFFFFU - ((1 << (size + 1)) - 1))) | ((1 << size) - 1); + } + } + + __es_set_PMPADDRx(idx, addr); + + pmpxcfg |= (attr.r << PMP_PMPCFG_R_Pos) | (attr.w << PMP_PMPCFG_W_Pos) | + (attr.x << PMP_PMPCFG_X_Pos) | (attr.a << PMP_PMPCFG_A_Pos) | + (attr.l << PMP_PMPCFG_L_Pos); + + __es_set_PMPxCFG(idx, pmpxcfg); +} + +/** + \brief disable mpu region by idx. + \details + \param [in] idx memory protected region (0, 1, 2, ..., 15). + */ +__STATIC_INLINE void csi_mpu_disable_region(uint32_t idx) +{ + __es_set_PMPxCFG(idx, __es_get_PMPxCFG(idx) & (~PMP_PMPCFG_A_Msk)); +} + +/*@} end of CSI_Core_PMPFunctions */ + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + + +/** + \brief CORE timer Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \param [in] IRQn core timer Interrupt number. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn) +{ + if (CORET->MTIMECMP) + CORET->MTIMECMP = CORET->MTIMECMP + ticks; + else + CORET->MTIMECMP = CORET->MTIME + ticks; + + return (0UL); +} + +__STATIC_INLINE uint32_t csi_coret_clr(uint32_t ticks, int32_t IRQn) +{ + CORET->MTIMECMP = CORET->MTIME + ticks; + + return (0UL); +} + +/** + \brief get CORE timer reload value + \return CORE timer counter value. + */ +__STATIC_INLINE uint32_t csi_coret_get_load(void) +{ + return CORET->MTIMECMP & 0xFFFFFFFF; +} + +/** + \brief get CORE timer reload high value + \return CORE timer counter value. + */ +__STATIC_INLINE uint32_t csi_coret_get_loadh(void) +{ + return (CORET->MTIMECMP >> 32) & 0xFFFFFFFF; +} + +/** + \brief get CORE timer counter value + \return CORE timer counter value. + */ +__STATIC_INLINE uint32_t csi_coret_get_value(void) +{ + return CORET->MTIME & 0xFFFFFFFF; +} + +/** + \brief get CORE timer counter high value + \return CORE timer counter value. + */ +__STATIC_INLINE uint32_t csi_coret_get_valueh(void) +{ + return (CORET->MTIME >> 32) & 0xFFFFFFFF; +} + +/*@} end of CSI_Core_SysTickFunctions */ + +/* ########################## SYSMAP functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_SYSMAPFunctions SYSMAP Functions + \brief Functions that manage system map attribute + @{ + */ + +/** + \brief Get SYSMAPCFGx Register by index + \details Returns the content of the SYSMAPxCFG Register. + \param [in] idx SYSMAP region index + \return SYSMAPxCFG Register value + */ +__STATIC_INLINE uint8_t __get_SYSMAPCFGx(uint32_t idx) +{ + switch (idx) { + case 0: return SYSMAP->SYSMAPCFG0; + case 1: return SYSMAP->SYSMAPCFG1; + case 2: return SYSMAP->SYSMAPCFG2; + case 3: return SYSMAP->SYSMAPCFG3; + case 4: return SYSMAP->SYSMAPCFG4; + case 5: return SYSMAP->SYSMAPCFG5; + case 6: return SYSMAP->SYSMAPCFG6; + case 7: return SYSMAP->SYSMAPCFG7; + default: return 0; + } +} + +/** + \brief Set SYSMAPCFGx by index + \details Writes the given value to the SYSMAPxCFG Register. + \param [in] idx SYSMAPx region index + \param [in] sysmapxcfg SYSMAPxCFG Register value to set + */ +__STATIC_INLINE void __set_SYSMAPCFGx(uint32_t idx, uint32_t sysmapxcfg) +{ + switch (idx) { + case 0: SYSMAP->SYSMAPCFG0 = sysmapxcfg; break; + case 1: SYSMAP->SYSMAPCFG1 = sysmapxcfg; break; + case 2: SYSMAP->SYSMAPCFG2 = sysmapxcfg; break; + case 3: SYSMAP->SYSMAPCFG3 = sysmapxcfg; break; + case 4: SYSMAP->SYSMAPCFG4 = sysmapxcfg; break; + case 5: SYSMAP->SYSMAPCFG5 = sysmapxcfg; break; + case 6: SYSMAP->SYSMAPCFG6 = sysmapxcfg; break; + case 7: SYSMAP->SYSMAPCFG7 = sysmapxcfg; break; + default: return; + } +} + +/** + \brief Get SYSMAPADDRx Register by index + \details Returns the content of the SYSMAPADDRx Register. + \param [in] idx SYSMAP region index + \return SYSMAPADDRx Register value + */ +__STATIC_INLINE uint32_t __get_SYSMAPADDRx(uint32_t idx) +{ + switch(idx){ + case 0: return SYSMAP->SYSMAPADDR0; + case 1: return SYSMAP->SYSMAPADDR1; + case 2: return SYSMAP->SYSMAPADDR2; + case 3: return SYSMAP->SYSMAPADDR3; + case 4: return SYSMAP->SYSMAPADDR4; + case 5: return SYSMAP->SYSMAPADDR5; + case 6: return SYSMAP->SYSMAPADDR6; + case 7: return SYSMAP->SYSMAPADDR7; + default: return 0; + } +} + +/** + \brief Set SYSMAPADDRx by index + \details Writes the given value to the SYSMAPADDRx Register. + \param [in] idx SYSMAP region index + \param [in] sysmapaddr SYSMAPADDRx Register value to set + */ +__STATIC_INLINE void __set_SYSMAPADDRx(uint32_t idx, uint32_t sysmapxaddr) +{ + switch (idx) { + case 0: SYSMAP->SYSMAPADDR0 = sysmapxaddr; break; + case 1: SYSMAP->SYSMAPADDR1 = sysmapxaddr; break; + case 2: SYSMAP->SYSMAPADDR2 = sysmapxaddr; break; + case 3: SYSMAP->SYSMAPADDR3 = sysmapxaddr; break; + case 4: SYSMAP->SYSMAPADDR4 = sysmapxaddr; break; + case 5: SYSMAP->SYSMAPADDR5 = sysmapxaddr; break; + case 6: SYSMAP->SYSMAPADDR6 = sysmapxaddr; break; + case 7: SYSMAP->SYSMAPADDR7 = sysmapxaddr; break; + default: return; + } +} + +/** + \brief configure system map attribute. + \details + \param [in] idx system map region (0, 1, 2, ..., 7). + \param [in] base_addr base address must be aligned with page size. + \param [in] enable enable or disable memory protected region. + */ +__STATIC_INLINE void csi_sysmap_config_region(uint32_t idx, uint32_t base_addr, uint32_t attr) +{ + uint32_t addr = 0; + + if (idx > 7) { + return; + } + + addr = base_addr >> 12; + attr = attr << 2; + + __set_SYSMAPADDRx(idx, addr); + __set_SYSMAPCFGx(idx, attr); +} + +/*@} end of CSI_Core_SYSMAPFunctions */ + + +/* ##################################### DCC function ########################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_core_DebugFunctions HAD Functions + \brief Functions that access the HAD debug interface. + @{ + */ + +/** + \brief HAD Send Character + \details Transmits a character via the HAD channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch) +{ + DCC->DERJR = (uint8_t)ch; + + return (ch); +} + + +/** + \brief HAD Receive Character + \details Inputs a character via the external variable \ref HAD_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t csi_had_receive_char(void) +{ + int32_t ch = -1; /* no character available */ + + if (_FLD2VAL_(DCC_EHSR_JW, DCC->EHSR)) { + ch = DCC->DERJW; + } + + return (ch); +} + + +/** + \brief HAD Check Character + \details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t csi_had_check_char(void) +{ + return _FLD2VAL_(DCC_EHSR_JW, DCC->EHSR); /* no character available */ +} + +/*@} end of CSI_core_DebugFunctions */ + + +/* ########################## sleep and Reset functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_SleepAndResetFunctions Sleep and Reset Functions + \brief Functions that configure Sleep and Reset. + @{ + */ + + +/* MEXSTATUS Register Definitions */ +#define MEXSTATUS_RESET_Pos 0U +#define MEXSTATUS_RESET_Msk (0x3UL << MEXSTATUS_RESET_Pos) /*!< MEXSTATUS: RESET Position */ +#define MEXSTATUS_SLEEP_Pos 2U +#define MEXSTATUS_SLEEP_Msk (0x3UL << MEXSTATUS_SLEEP_Pos) /*!< MEXSTATUS: RESET Position */ +#define MEXSTATUS_WFE_Pos 4U +#define MEXSTATUS_WFE_Msk (0x1UL << MEXSTATUS_WFE_Pos) + +typedef enum { + MEXSTATUS_RESET_CORE = 1, /* Reset CPU Core, But Not Reset Debug System */ + MEXSTATUS_RESET_CPUSYS = 2 /* Reset CPU Core and Reset Debug System */ +} mexstatus_reset_e; + +typedef enum { + MEXSTATUS_SLEEP_LIGHT = 1, + MEXSTATUS_SLEEP_DEEP = 0 +} mexstatus_sleep_e; + + +/*@} end of group CSI_MEXSTATUS */ + +/** + \brief CPU Reset + \details Triggle CPU Reset + */ +__STATIC_INLINE uint32_t csi_cpu_get_reset_addr (void) +{ + uint32_t result; + result = __get_MRADDR(); + + return result; +} + +/** + \brief CPU Reset + \details Triggle CPU Reset + */ +__STATIC_INLINE void csi_cpu_reset (mexstatus_reset_e reset_mode) +{ + uint32_t mexstatus; + mexstatus = __get_MEXSTATUS(); + mexstatus &= (~(MEXSTATUS_RESET_Msk)); + mexstatus |= (uint32_t)(reset_mode << MEXSTATUS_RESET_Pos); + __set_MEXSTATUS(mexstatus); +} + +/** + \brief CPU Sleep WFI mode + \details Triggle CPU Sleep + */ +__STATIC_INLINE void csi_cpu_sleep_wfi (mexstatus_sleep_e sleep_mode) +{ + uint32_t mexstatus; + mexstatus = __get_MEXSTATUS(); + mexstatus &= (~(MEXSTATUS_SLEEP_Msk)); + mexstatus &= (~(MEXSTATUS_WFE_Msk)); /* WFI mode */ + mexstatus |= (uint32_t)(sleep_mode << MEXSTATUS_SLEEP_Pos); + __set_MEXSTATUS(mexstatus); +} + +/** + \brief CPU Sleep WFE mode + \details Triggle CPU Sleep + */ +__STATIC_INLINE void csi_cpu_sleep_wfe (mexstatus_sleep_e sleep_mode) +{ + uint32_t mexstatus; + mexstatus = __get_MEXSTATUS(); + mexstatus &= (~(MEXSTATUS_SLEEP_Msk)); + mexstatus |= MEXSTATUS_WFE_Msk; /* WFE mode */ + mexstatus |= (uint32_t)(sleep_mode << MEXSTATUS_SLEEP_Pos); + __set_MEXSTATUS(mexstatus); +} + +/** + \brief Get CPU Sleep Status + \details Get CPU Sleep Status + */ +__STATIC_INLINE uint32_t csi_cpu_get_sleep_status (void) +{ + uint32_t mexstatus; + mexstatus = __get_MEXSTATUS(); + mexstatus = (mexstatus_sleep_e)((mexstatus & MEXSTATUS_SLEEP_Msk) >> MEXSTATUS_SLEEP_Pos); + return mexstatus; +} + +/* ########################## Cache functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void csi_icache_enable (void) +{ +#if (__ICACHE_PRESENT == 1U) + uint32_t cache; + __DSB(); + __ISB(); + __ICACHE_IALL(); + cache = __get_MHCR(); + cache |= CACHE_MHCR_IE_Msk; + __set_MHCR(cache); + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void csi_icache_disable (void) +{ +#if (__ICACHE_PRESENT == 1U) + uint32_t cache; + __DSB(); + __ISB(); + cache = __get_MHCR(); + cache &= ~CACHE_MHCR_IE_Msk; /* disable icache */ + __set_MHCR(cache); + __ICACHE_IALL(); /* invalidate all icache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void csi_icache_invalid (void) +{ +#if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + __ICACHE_IALL(); /* invalidate all icache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + \note I-Cache also turns on. + */ +__STATIC_INLINE void csi_dcache_enable (void) +{ +#if (__DCACHE_PRESENT == 1U) + uint32_t cache; + __DSB(); + __ISB(); + __DCACHE_IALL(); /* invalidate all dcache */ + cache = __get_MHCR(); + cache |= (CACHE_MHCR_DE_Msk | CACHE_MHCR_WB_Msk | CACHE_MHCR_WA_Msk | CACHE_MHCR_RS_Msk | CACHE_MHCR_BPE_Msk | CACHE_MHCR_L0BTB_Msk); /* enable all Cache */ + __set_MHCR(cache); + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + \note I-Cache also turns off. + */ +__STATIC_INLINE void csi_dcache_disable (void) +{ +#if (__DCACHE_PRESENT == 1U) + uint32_t cache; + __DSB(); + __ISB(); + cache = __get_MHCR(); + cache &= ~(uint32_t)CACHE_MHCR_DE_Msk; /* disable all Cache */ + __set_MHCR(cache); + __DCACHE_IALL(); /* invalidate all Cache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + \note I-Cache also invalid + */ +__STATIC_INLINE void csi_dcache_invalid (void) +{ +#if (__DCACHE_PRESENT == 1U) + __DSB(); + __ISB(); + __DCACHE_IALL(); /* invalidate all Cache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + \note I-Cache also cleans + */ +__STATIC_INLINE void csi_dcache_clean (void) +{ +#if (__DCACHE_PRESENT == 1U) + __DSB(); + __ISB(); + __DCACHE_CALL(); /* clean all Cache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + \note I-Cache also flush. + */ +__STATIC_INLINE void csi_dcache_clean_invalid (void) +{ +#if (__DCACHE_PRESENT == 1U) + __DSB(); + __ISB(); + __DCACHE_CIALL(); /* clean and inv all Cache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize) +{ +#if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize + (uint32_t)addr % 32; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; + + __DSB(); + + while (op_size > 0) { + __DCACHE_IPA(op_addr); + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize) +{ + +#if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize + (uint32_t)addr % 32; + uint32_t op_addr = (uint32_t) addr & CACHE_INV_ADDR_Msk; + int32_t linesize = 32; + + __DSB(); + + while (op_size > 0) { + __DCACHE_CPA(op_addr); + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#endif + +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 16-byte boundary) + \param[in] dsize size of memory block (aligned to 16-byte boundary) +*/ +__STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize) +{ +#if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize + (uint32_t)addr % 32; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; + + __DSB(); + + while (op_size > 0) { + __DCACHE_CIPA(op_addr); + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#endif +} + +/** + \brief setup cacheable range Cache + \details setup Cache range + */ +__STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable) +{ + ; +} + +/** + \brief Enable cache profile + \details Turns on Cache profile + */ +__STATIC_INLINE void csi_cache_enable_profile (void) +{ + ; +} + +/** + \brief Disable cache profile + \details Turns off Cache profile + */ +__STATIC_INLINE void csi_cache_disable_profile (void) +{ + ; +} + +/** + \brief Reset cache profile + \details Reset Cache profile + */ +__STATIC_INLINE void csi_cache_reset_profile (void) +{ + ; +} + +/** + \brief cache access times + \details Cache access times + \note every 256 access add 1. + \return cache access times, actual times should be multiplied by 256 + */ +__STATIC_INLINE uint32_t csi_cache_get_access_time (void) +{ + return 0; +} + +/** + \brief cache miss times + \details Cache miss times + \note every 256 miss add 1. + \return cache miss times, actual times should be multiplied by 256 + */ +__STATIC_INLINE uint32_t csi_cache_get_miss_time (void) +{ + return 0; +} + +/*@} end of CSI_Core_CacheFunctions */ + +/** + \ingroup CSI_tcm_register + \defgroup CSI_TCM + \brief Type definitions for the tcm Registers + @{ + */ + +/** + \brief Consortium definition for accessing protection area selection register(MITCMCR, csr<0x7f9>). + */ +typedef union { + struct { + uint32_t EN: 1; /*!< bit: 0 Instruction Tightly-Coupled Memory enable */ + uint32_t _reserved0: 1; /*!< bit: 1 Reserved */ + uint32_t _reserved1: 1; /*!< bit: 2 Reserved */ + uint32_t _reserved2: 1; /*!< bit: 3 Reserved */ + uint32_t Size: 4; /*!< bit: 4..7 Size of ITCM */ + uint32_t _reserved4: 4; /*!< bit: 8..11 Reserved */ + uint32_t Base_Address: 20; /*!< bit: 12..31 Base address of ITCM */ + } b; /*!< Structure Access by bit */ + uint32_t w; /*!< Type Access by whole register */ +} MITCMCR_Type; + +#define MITCMCR_Base_Address_Pos 12U /*!< MITCMCR: Base_Address Position */ +#define MITCMCR_Base_Address_Msk (0xfffffUL << MITCMCR_Base_Address_Pos) /*!< MITCMCR: Base_Address Mask */ + +#define MITCMCR_Size_Pos 4U /*!< MITCMCR: Size Position */ +#define MITCMCR_Size_Msk (0xfUL << MITCMCR_Size_Pos) /*!< MITCMCR: Size Mask */ + +#define MITCMCR_EN_Pos 0U /*!< MITCMCR: EN Position */ +#define MITCMCR_EN_Msk (0x1UL << MITCMCR_EN_Pos) /*!< MITCMCR: EN Mask */ + +/** + \brief Consortium definition for accessing protection area selection register(MDTCMCR, csr<0x7f8>). + */ +typedef union { + struct { + uint32_t EN: 1; /*!< bit: 0 Instruction Tightly-Coupled Memory enable */ + uint32_t _reserved0: 1; /*!< bit: 1 Reserved */ + uint32_t _reserved1: 1; /*!< bit: 2 Reserved */ + uint32_t _reserved2: 1; /*!< bit: 3 Reserved */ + uint32_t Size: 4; /*!< bit: 4..7 Size of DTCM */ + uint32_t _reserved4: 4; /*!< bit: 8..11 Reserved */ + uint32_t Base_Address: 20; /*!< bit: 12..31 Base address of DTCM */ + } b; /*!< Structure Access by bit */ + uint32_t w; /*!< Type Access by whole register */ +} MDTCMCR_Type; + +#define MDTCMCR_Base_Address_Pos 12U /*!< MDTCMCR: Base_Address Position */ +#define MDTCMCR_Base_Address_Msk (0xfffffUL << MDTCMCR_Base_Address_Pos) /*!< MDTCMCR: Base_Address Mask */ + +#define MDTCMCR_Size_Pos 4U /*!< MDTCMCR: Size Position */ +#define MDTCMCR_Size_Msk (0xfUL << MDTCMCR_Size_Pos) /*!< MDTCMCR: Size Mask */ + +#define MDTCMCR_EN_Pos 0U /*!< MDTCMCR: EN Position */ +#define MDTCMCR_EN_Msk (0x1UL << MDTCMCR_EN_Pos) /*!< MDTCMCR: EN Mask */ +/*@} end of group CSI_TCM_bitfield */ + +/* ########################## TCM functions #################################### */ +/** + \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_TCMFunctions TCM Functions + \brief Functions that configure TCM. + @{ + */ + +/** + \brief Enable ITCM + \details Turns on ITCM + */ +__STATIC_INLINE void csi_itcm_enable (void) +{ + __set_MITCMCR(__get_MITCMCR() | MITCMCR_EN_Msk); +} + +/** + \brief Enable DTCM + \details Turns on DTCM + */ +__STATIC_INLINE void csi_dtcm_enable (void) +{ + __set_MDTCMCR(__get_MDTCMCR() | MDTCMCR_EN_Msk); +} + +/** + \brief Enable ITCM + \details Turns on ITCM + */ +__STATIC_INLINE void csi_itcm_disable (void) +{ + __set_MITCMCR(__get_MITCMCR() & (~MITCMCR_EN_Msk)); +} + +/** + \brief Enable DTCM + \details Turns on DTCM + */ +__STATIC_INLINE void csi_dtcm_disable (void) +{ + __set_MDTCMCR(__get_MDTCMCR() & (~MDTCMCR_EN_Msk)); +} + +/** + \brief Get ITCM Size + \details Get ITCM Size + \return ITCM size (bytes). + */ +__STATIC_INLINE uint32_t csi_itcm_get_size(void) +{ + MITCMCR_Type sizemask; + uint32_t ret; + + sizemask.w = __get_MITCMCR(); + ret = sizemask.b.Size; + + return (1 << ret) << 9; +} + +/** + \brief Get DTCM Size + \details Get DTCM Size + \return DTCM size (bytes). + */ +__STATIC_INLINE uint32_t csi_dtcm_get_size(void) +{ + MDTCMCR_Type sizemask; + uint32_t ret; + + sizemask.w = __get_MDTCMCR(); + ret = sizemask.b.Size; + + return (1 << ret) << 9; +} + +/** + \brief Set ITCM Base Address + \details Set ITCM Base Address + \param [in] base_addr itcm base address. + */ +__STATIC_INLINE void csi_itcm_set_base_addr(uint32_t base_addr) +{ + __set_MITCMCR((__get_MITCMCR() & (~MITCMCR_Base_Address_Msk)) | (base_addr & MITCMCR_Base_Address_Msk)); +} + +/** + \brief Set DTCM Base Address + \details Set DTCM Base Address + \param [in] base_addr dtcm base address. + */ +__STATIC_INLINE void csi_dtcm_set_base_addr(uint32_t base_addr) +{ + __set_MDTCMCR((__get_MDTCMCR() & (~MDTCMCR_Base_Address_Msk)) | (base_addr & MDTCMCR_Base_Address_Msk)); +} + +/*@} end of CSI_Core_TCMFunctions */ + + +/*@} end of CSI_core_DebugFunctions */ + +/* ################################## IRQ Functions ############################################ */ + +/** + \brief Save the Irq context + \details save the psr result before disable irq. + */ +__STATIC_INLINE uint32_t csi_irq_save(void) +{ + uint32_t result; + result = __get_MSTATUS(); + __disable_irq_(); + return(result); +} + +/** + \brief Restore the Irq context + \details restore saved primask state. + \param [in] irq_state psr irq state. + */ +__STATIC_INLINE void csi_irq_restore(uint32_t irq_state) +{ + __set_MSTATUS(irq_state); +} + +/*@} end of IRQ Functions */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_RV32_H_DEPENDANT */ + +#endif /* __CSI_GENERIC */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/csi_core.h b/os/common/ext/CMSIS/ES32/ES32VF2264/csi_core.h new file mode 100644 index 0000000000..d8e95b8cc5 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/csi_core.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + */ + + +/****************************************************************************** + * @file csi_core.h + * @brief CSI Core Layer Header File + * @version V1.0 + * @date 02. June 2017 + ******************************************************************************/ + +#ifndef _CORE_H_ +#define _CORE_H_ + +#include + +#if defined(__CK801__) || defined(__E801__) +#include +#elif defined(__CK802__) || defined(__E802__) || defined(__E802T__) || defined(__S802__) || defined(__S802T__) +#include +#elif defined(__CK804__) || defined(__E804D__) || defined(__E804DT__) || defined(__E804F__) || defined(__E804FT__) || defined (__E804DF__) || defined(__E804DFT__) +#include +#elif defined(__CK803__) || defined(__E803__) || defined(__E803T__) || defined(__S803__) || defined(__S803T__) +#include +#elif defined(__CK805__) || defined(__I805__) || defined(__I805F__) +#include +#elif defined(__CK610__) +#include +#elif defined(__CK810__) || defined(__C810__) || defined(__C810T__) || defined(__C810V__) || defined(__C810VT__) +#include +#elif defined(__CK807__) || defined(__C807__) || defined(__C807F__) || defined(__C807FV__) || defined(__R807__) +#include +#elif defined(__riscv) && defined(CONFIG_CSKY_CORETIM) +#include +#elif defined(__riscv) +#include +#endif + +#ifdef __riscv +#include +#else +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _CORE_H_ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/csi_rv32_gcc.h b/os/common/ext/CMSIS/ES32/ES32VF2264/csi_rv32_gcc.h new file mode 100644 index 0000000000..5bee6c5d9e --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/csi_rv32_gcc.h @@ -0,0 +1,2928 @@ +/* + * Copyright (C) 2017-2019 Alibaba Group Holding Limited + */ + + +/****************************************************************************** + * @file csi_rv32_gcc.h + * @brief CSI Header File for GCC. + * @version V1.0 + * @date 01. Sep 2018 + ******************************************************************************/ + +#ifndef _CSI_RV32_GCC_H_ +#define _CSI_RV32_GCC_H_ + +#include + +#ifndef __ASM +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#endif + +#ifndef __INLINE +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#endif + +#ifndef __ALWAYS_STATIC_INLINE +#define __ALWAYS_STATIC_INLINE __attribute__((always_inline)) static inline +#endif + +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CSI_Core_FunctionInterface + \defgroup CSI_Core_RegAccFunctions CSI Core Register Access Functions + @{ + */ +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by setting the IE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __enable_irq_(void) +{ + __ASM volatile("csrs mstatus, 8"); +} + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by clearing the IE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __disable_irq_(void) +{ + __ASM volatile("csrc mstatus, 8"); +} + +/** + \brief Get MXSTATUS + \details Returns the content of the MXSTATUS Register. + \return MXSTATUS Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MXSTATUS(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mxstatus" : "=r"(result)); + return (result); +} + +/** + \brief Set MXSTATUS + \details Writes the given value to the MXSTATUS Register. + \param [in] mxstatus MXSTATUS Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MXSTATUS(uint32_t mxstatus) +{ + __ASM volatile("csrw mxstatus, %0" : : "r"(mxstatus)); +} + +/** + \brief Get MEXSTATUS + \details Returns the content of the MEXSTATUS Register. + \return MEXSTATUS Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MEXSTATUS(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mexstatus" : "=r"(result)); + return (result); +} + +/** + \brief Set MEXSTATUS + \details Writes the given value to the MSTATUS Register. + \param [in] MEXSTATUS Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MEXSTATUS(uint32_t mexstatus) +{ + __ASM volatile("csrw mexstatus, %0" : : "r"(mexstatus)); +} + + +/** + \brief Get MRADDR + \details Returns the content of the MRADDR Register. + \return MRADDR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MRADDR(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mraddr" : "=r"(result)); + return (result); +} + +/** + \brief Get FXCR + \details Returns the content of the FXCR Register. + \return FXCR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_FXCR(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, fxcr" : "=r"(result)); + return (result); +} + + +/** + \brief Set FXCR + \details Writes the given value to the FXCR Register. + \param [in] FXCR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_FXCR(uint32_t fxcr) +{ + __ASM volatile("csrw fxcr, %0" : : "r"(fxcr)); +} + +/** + \brief Get MSTATUS + \details Returns the content of the MSTATUS Register. + \return MSTATUS Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MSTATUS(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mstatus" : "=r"(result)); + return (result); +} + +/** + \brief Set MSTATUS + \details Writes the given value to the MSTATUS Register. + \param [in] mstatus MSTATUS Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MSTATUS(uint32_t mstatus) +{ + __ASM volatile("csrw mstatus, %0" : : "r"(mstatus)); +} + +/** + \brief Get MHCR + \details Returns the content of the MHCR Register. + \return MHCR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MHCR(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mhcr" : "=r"(result)); + return (result); +} + +/** + \brief Set MHCR + \details Writes the given value to the MHCR Register. + \param [in] MHCR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MHCR(uint32_t mhcr) +{ + __ASM volatile("csrw mhcr, %0" : : "r"(mhcr)); +} + +/** + \brief Get MHINT + \details Returns the content of the MHINT Register. + \return MHINT Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MHINT(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mhint" : "=r"(result)); + return (result); +} + +/** + \brief Set MHINT + \details Writes the given value to the MHINT Register. + \param [in] MHINT Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MHINT(uint32_t mhint) +{ + __ASM volatile("csrw mhint, %0" : : "r"(mhint)); +} + +/** + \brief Get MISA Register + \details Returns the content of the MISA Register. + \return MISA Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MISA(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, misa" : "=r"(result)); + return (result); +} + +/** + \brief Set MISA + \details Writes the given value to the MISA Register. + \param [in] misa MISA Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MISA(uint32_t misa) +{ + __ASM volatile("csrw misa, %0" : : "r"(misa)); +} + +/** + \brief Get MIE Register + \details Returns the content of the MIE Register. + \return MIE Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MIE(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mie" : "=r"(result)); + return (result); +} + +/** + \brief Set MIE + \details Writes the given value to the MIE Register. + \param [in] mie MIE Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MIE(uint32_t mie) +{ + __ASM volatile("csrw mie, %0" : : "r"(mie)); +} + +/** + \brief Get MTVEC Register + \details Returns the content of the MTVEC Register. + \return MTVEC Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MTVEC(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mtvec" : "=r"(result)); + return (result); +} + +/** + \brief Set MTVEC + \details Writes the given value to the MTVEC Register. + \param [in] mtvec MTVEC Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MTVEC(uint32_t mtvec) +{ + __ASM volatile("csrw mtvec, %0" : : "r"(mtvec)); +} + +/** + \brief Set MTVT + \details Writes the given value to the MTVT Register. + \param [in] mtvt MTVT Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MTVT(uint32_t mtvt) +{ + __ASM volatile("csrw mtvt, %0" : : "r"(mtvt)); +} + +/** + \brief Get MTVT Register + \details Returns the content of the MTVT Register. + \return MTVT Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MTVT(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mtvt" : "=r"(result)); + return (result); +} + +/** + \brief Get SP + \details Returns the content of the SP Register. + \return SP Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_SP(void) +{ + uint32_t result; + + __ASM volatile("mv %0, sp" : "=r"(result)); + return (result); +} + +/** + \brief Set SP + \details Writes the given value to the SP Register. + \param [in] sp SP Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_SP(uint32_t sp) +{ + __ASM volatile("mv sp, %0" : : "r"(sp): "sp"); +} + +/** + \brief Get MSCRATCH Register + \details Returns the content of the MSCRATCH Register. + \return MSCRATCH Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mscratch" : "=r"(result)); + return (result); +} + +/** + \brief Set MSCRATCH + \details Writes the given value to the MSCRATCH Register. + \param [in] mscratch MSCRATCH Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MSCRATCH(uint32_t mscratch) +{ + __ASM volatile("csrw mscratch, %0" : : "r"(mscratch)); +} + +/** + \brief Get MEPC Register + \details Returns the content of the MEPC Register. + \return MEPC Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MEPC(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mepc" : "=r"(result)); + return (result); +} + +/** + \brief Set MEPC + \details Writes the given value to the MEPC Register. + \param [in] mepc MEPC Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MEPC(uint32_t mepc) +{ + __ASM volatile("csrw mepc, %0" : : "r"(mepc)); +} + +/** + \brief Get MCAUSE Register + \details Returns the content of the MCAUSE Register. + \return MCAUSE Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MCAUSE(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mcause" : "=r"(result)); + return (result); +} + +/** + \brief Get MNXTI Register + \details Returns the content of the MNXTI Register. + \return MNXTI Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MNXTI(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mnxti" : "=r"(result)); + return (result); +} + +/** + \brief Set MNXTI + \details Writes the given value to the MNXTI Register. + \param [in] mnxti MNXTI Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MNXTI(uint32_t mnxti) +{ + __ASM volatile("csrw mnxti, %0" : : "r"(mnxti)); +} + +/** + \brief Get MINTSTATUS Register + \details Returns the content of the MINTSTATUS Register. + \return MINTSTATUS Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MINTSTATUS(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mintstatus" : "=r"(result)); + return (result); +} + +/** + \brief Get MTVAL Register + \details Returns the content of the MTVAL Register. + \return MTVAL Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MTVAL(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mtval" : "=r"(result)); + return (result); +} + +/** + \brief Get MIP Register + \details Returns the content of the MIP Register. + \return MIP Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MIP(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mip" : "=r"(result)); + return (result); +} + +/** + \brief Set MIP + \details Writes the given value to the MIP Register. + \param [in] mip MIP Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MIP(uint32_t mip) +{ + __ASM volatile("csrw mip, %0" : : "r"(mip)); +} + +/** + \brief Get MCYCLEL Register + \details Returns the content of the MCYCLEL Register. + \return MCYCLE Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MCYCLE(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mcycle" : "=r"(result)); + return (result); +} + +/** + \brief Get MCYCLEH Register + \details Returns the content of the MCYCLEH Register. + \return MCYCLEH Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MCYCLEH(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mcycleh" : "=r"(result)); + return (result); +} + +/** + \brief Get MINSTRET Register + \details Returns the content of the MINSTRET Register. + \return MINSTRET Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MINSTRET(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, minstret" : "=r"(result)); + return (result); +} + +/** + \brief Get MINSTRETH Register + \details Returns the content of the MINSTRETH Register. + \return MINSTRETH Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MINSTRETH(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, minstreth" : "=r"(result)); + return (result); +} + +/** + \brief Get MITCMCR + \details Returns the content of the MITCMCR Register. + \return MITCMCR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MITCMCR(void) +{ + uint32_t result; + __ASM volatile("csrr %0, mitcmcr" : "=r"(result)); + + return (result); +} + +/** + \brief Set MITCMCR + \details Writes the given value to the MITCMCR Register. + \param [in] itcmcr MITCMCR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MITCMCR(uint32_t mitcmcr) +{ + __ASM volatile("csrw mitcmcr, %0" : : "r"(mitcmcr)); +} + +/** + \brief Get MDTCMCR + \details Returns the content of the MDTCMCR Register. + \return MDTCMCR Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MDTCMCR(void) +{ + uint32_t result; + __ASM volatile("csrr %0, mdtcmcr" : "=r"(result)); + return (result); +} + +/** + \brief Set MDTCMCR + \details Writes the given value to the MDTCMCR Register. + \param [in] dtcmcr MDTCMCR Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_MDTCMCR(uint32_t mdtcmcr) +{ + __ASM volatile("csrw mdtcmcr, %0" : : "r"(mdtcmcr)); +} + + +/** + \brief Get MVENDORID Register + \details Returns the content of the MVENDROID Register. + \return MVENDORID Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MVENDORID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mvendorid" : "=r"(result)); + return (result); +} + +/** + \brief Get MARCHID Register + \details Returns the content of the MARCHID Register. + \return MARCHID Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MARCHID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, marchid" : "=r"(result)); + return (result); +} + +/** + \brief Get MIMPID Register + \details Returns the content of the MIMPID Register. + \return MIMPID Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MIMPID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mimpid" : "=r"(result)); + return (result); +} + +/** + \brief Get MHARTID Register + \details Returns the content of the MHARTID Register. + \return MHARTID Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_MHARTID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, mhartid" : "=r"(result)); + return (result); +} + +/** + \brief Get PMPCFGx Register + \details Returns the content of the PMPCFGx Register. + \return PMPCFGx Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG0(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpcfg0" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG1(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpcfg1" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG2(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpcfg2" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPCFG3(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpcfg3" : "=r"(result)); + return (result); +} + +/** + \brief Get PMPxCFG Register by index + \details Returns the content of the PMPxCFG Register. + \param [in] idx PMP region index + \return PMPxCFG Register value + */ +__STATIC_INLINE uint8_t __es_get_PMPxCFG(uint32_t idx) +{ + uint32_t pmpcfgx = 0; + + if (idx < 4) { + pmpcfgx = __get_PMPCFG0(); + } else if (idx >=4 && idx < 8) { + idx -= 4; + pmpcfgx = __get_PMPCFG1(); + } else if (idx >=8 && idx < 12) { + idx -= 8; + pmpcfgx = __get_PMPCFG2(); + } else if (idx >=12 && idx < 16) { + idx -= 12; + pmpcfgx = __get_PMPCFG3(); + } else { + return 0; + } + + return (uint8_t)((pmpcfgx & (0xFF << (idx << 3))) >> (idx << 3)); +} + +/** + \brief Set PMPCFGx + \details Writes the given value to the PMPCFGx Register. + \param [in] pmpcfg PMPCFGx Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_PMPCFG0(uint32_t pmpcfg) +{ + __ASM volatile("csrw pmpcfg0, %0" : : "r"(pmpcfg)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPCFG1(uint32_t pmpcfg) +{ + __ASM volatile("csrw pmpcfg1, %0" : : "r"(pmpcfg)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPCFG2(uint32_t pmpcfg) +{ + __ASM volatile("csrw pmpcfg2, %0" : : "r"(pmpcfg)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPCFG3(uint32_t pmpcfg) +{ + __ASM volatile("csrw pmpcfg3, %0" : : "r"(pmpcfg)); +} + +/** + \brief Set PMPxCFG by index + \details Writes the given value to the PMPxCFG Register. + \param [in] idx PMPx region index + \param [in] pmpxcfg PMPxCFG Register value to set + */ +__STATIC_INLINE void __es_set_PMPxCFG(uint32_t idx, uint8_t pmpxcfg) +{ + uint32_t pmpcfgx = 0; + + if (idx < 4) { + pmpcfgx = __get_PMPCFG0(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3)); + __set_PMPCFG0(pmpcfgx); + } else if (idx >=4 && idx < 8) { + idx -= 4; + pmpcfgx = __get_PMPCFG1(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3)); + __set_PMPCFG1(pmpcfgx); + } else if (idx >=8 && idx < 12) { + idx -= 8; + pmpcfgx = __get_PMPCFG2(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3)); + __set_PMPCFG2(pmpcfgx); + } else if (idx >=12 && idx < 16) { + idx -= 12; + pmpcfgx = __get_PMPCFG3(); + pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3)); + __set_PMPCFG3(pmpcfgx); + } else { + return; + } +} + +/** + \brief Get PMPADDRx Register + \details Returns the content of the PMPADDRx Register. + \return PMPADDRx Register value + */ +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR0(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr0" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR1(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr1" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR2(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr2" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR3(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr3" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR4(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr4" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR5(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr5" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR6(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr6" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR7(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr7" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR8(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr8" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR9(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr9" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR10(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr10" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR11(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr11" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR12(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr12" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR13(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr13" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR14(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr14" : "=r"(result)); + return (result); +} + +__ALWAYS_STATIC_INLINE uint32_t __get_PMPADDR15(void) +{ + uint32_t result; + + __ASM volatile("csrr %0, pmpaddr15" : "=r"(result)); + return (result); +} + +/** + \brief Get PMPADDRx Register by index + \details Returns the content of the PMPADDRx Register. + \param [in] idx PMP region index + \return PMPADDRx Register value + */ +__STATIC_INLINE uint32_t __es_get_PMPADDRx(uint32_t idx) +{ + switch (idx) { + case 0: return __get_PMPADDR0(); + case 1: return __get_PMPADDR1(); + case 2: return __get_PMPADDR2(); + case 3: return __get_PMPADDR3(); + case 4: return __get_PMPADDR4(); + case 5: return __get_PMPADDR5(); + case 6: return __get_PMPADDR6(); + case 7: return __get_PMPADDR7(); + case 8: return __get_PMPADDR8(); + case 9: return __get_PMPADDR9(); + case 10: return __get_PMPADDR10(); + case 11: return __get_PMPADDR11(); + case 12: return __get_PMPADDR12(); + case 13: return __get_PMPADDR13(); + case 14: return __get_PMPADDR14(); + case 15: return __get_PMPADDR15(); + default: return 0; + } +} + +/** + \brief Set PMPADDRx + \details Writes the given value to the PMPADDRx Register. + \param [in] pmpaddr PMPADDRx Register value to set + */ +__ALWAYS_STATIC_INLINE void __set_PMPADDR0(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr0, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR1(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr1, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR2(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr2, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR3(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr3, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR4(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr4, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR5(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr5, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR6(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr6, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR7(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr7, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR8(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr8, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR9(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr9, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR10(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr10, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR11(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr11, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR12(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr12, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR13(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr13, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR14(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr14, %0" : : "r"(pmpaddr)); +} + +__ALWAYS_STATIC_INLINE void __set_PMPADDR15(uint32_t pmpaddr) +{ + __ASM volatile("csrw pmpaddr15, %0" : : "r"(pmpaddr)); +} + +/** + \brief Set PMPADDRx by index + \details Writes the given value to the PMPADDRx Register. + \param [in] idx PMP region index + \param [in] pmpaddr PMPADDRx Register value to set + */ +__STATIC_INLINE void __es_set_PMPADDRx(uint32_t idx, uint32_t pmpaddr) +{ + switch (idx) { + case 0: __set_PMPADDR0(pmpaddr); break; + case 1: __set_PMPADDR1(pmpaddr); break; + case 2: __set_PMPADDR2(pmpaddr); break; + case 3: __set_PMPADDR3(pmpaddr); break; + case 4: __set_PMPADDR4(pmpaddr); break; + case 5: __set_PMPADDR5(pmpaddr); break; + case 6: __set_PMPADDR6(pmpaddr); break; + case 7: __set_PMPADDR7(pmpaddr); break; + case 8: __set_PMPADDR8(pmpaddr); break; + case 9: __set_PMPADDR9(pmpaddr); break; + case 10: __set_PMPADDR10(pmpaddr); break; + case 11: __set_PMPADDR11(pmpaddr); break; + case 12: __set_PMPADDR12(pmpaddr); break; + case 13: __set_PMPADDR13(pmpaddr); break; + case 14: __set_PMPADDR14(pmpaddr); break; + case 15: __set_PMPADDR15(pmpaddr); break; + default: return; + } +} + +/** + \brief Enable interrupts and exceptions + \details Enables interrupts and exceptions by setting the IE-bit and EE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __enable_excp_irq(void) +{ + __ASM volatile("csrs mstatus, 8");//__enable_irq(); +} + +/** + \brief Disable interrupts and exceptions + \details Disables interrupts and exceptions by clearing the IE-bit and EE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __disable_excp_irq(void) +{ + __ASM volatile("csrc mstatus, 8");//__disable_irq(); +} + +#define __CSI_GCC_OUT_REG(r) "=r" (r) +#define __CSI_GCC_USE_REG(r) "r" (r) + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__ALWAYS_STATIC_INLINE void __NOP_(void) +{ + __ASM volatile("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__ALWAYS_STATIC_INLINE void __WFI_(void) +{ + __ASM volatile("wfi"); +} + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one interrupt occurs. + */ +__ALWAYS_STATIC_INLINE void __WAIT(void) +{ + __ASM volatile("wfi"); +} + +/** + \brief Doze For Interrupt + \details Doze For Interrupt is a hint instruction that suspends execution until one interrupt occurs. + */ +__ALWAYS_STATIC_INLINE void __DOZE(void) +{ + __ASM volatile("wfi"); +} + +/** + \brief Stop For Interrupt + \details Stop For Interrupt is a hint instruction that suspends execution until one interrupt occurs. + */ +__ALWAYS_STATIC_INLINE void __STOP(void) +{ + __ASM volatile("wfi"); +} + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__ALWAYS_STATIC_INLINE void __ISB(void) +{ + __ASM volatile("fence.i"); + __ASM volatile("fence r, r"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__ALWAYS_STATIC_INLINE void __DSB(void) +{ + __ASM volatile("fence iorw, iorw"); +#ifndef __riscv_xtheadse + __ASM volatile("sync"); +#endif +} + +/** + \brief Invalid all icache + \details invalid all icache. + */ +__ALWAYS_STATIC_INLINE void __ICACHE_IALL(void) +{ + __ASM volatile("icache.iall"); +} + +/** + \brief Invalid Icache by addr + \details Invalid Icache by addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __ICACHE_IPA(uint32_t addr) +{ + __ASM volatile("icache.ipa %0" : : "r"(addr)); +} + +/** + \brief Invalid all dcache + \details invalid all dcache. + */ +__ALWAYS_STATIC_INLINE void __DCACHE_IALL(void) +{ + __ASM volatile("dcache.iall"); +} + +/** + \brief Clear all dcache + \details clear all dcache. + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CALL(void) +{ + __ASM volatile("dcache.call"); +} + +/** + \brief Clear&invalid all dcache + \details clear & invalid all dcache. + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CIALL(void) +{ + __ASM volatile("dcache.ciall"); +} + +/** + \brief Invalid Dcache by addr + \details Invalid Dcache by addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_IPA(uint32_t addr) +{ + __ASM volatile("dcache.ipa %0" : : "r"(addr)); +} + +/** + \brief Clear Dcache by addr + \details Clear Dcache by addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CPA(uint32_t addr) +{ + __ASM volatile("dcache.cpa %0" : : "r"(addr)); +} + +/** + \brief Clear & Invalid Dcache by addr + \details Clear & Invalid Dcache by addr. + \param [in] addr operate addr + */ +__ALWAYS_STATIC_INLINE void __DCACHE_CIPA(uint32_t addr) +{ + __ASM volatile("dcache.cipa %0" : : "r"(addr)); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__ALWAYS_STATIC_INLINE void __DMB(void) +{ + __ASM volatile("fence rw, rw"); +} + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE uint32_t __REV_(uint32_t value) +{ + return __builtin_bswap32(value); +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE uint32_t __REV16_(uint32_t value) +{ + uint32_t result; + + result = ((value & 0xFF000000) >> 8) | ((value & 0x00FF0000) << 8) | + ((value & 0x0000FF00) >> 8) | ((value & 0x000000FF) << 8); + + return (result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE int32_t __REVSH_(int32_t value) +{ + return (short)(((value & 0xFF00) >> 8) | ((value & 0x00FF) << 8)); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__ALWAYS_STATIC_INLINE uint32_t __ROR_(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + */ +__ALWAYS_STATIC_INLINE void __BKPT(void) +{ + __ASM volatile("ebreak"); +} + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__ALWAYS_STATIC_INLINE uint32_t __RBIT_(uint32_t value) +{ + uint32_t result; + + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + + for (value >>= 1U; value; value >>= 1U) { + result <<= 1U; + result |= value & 1U; + s--; + } + + result <<= s; /* shift when v's highest bits are zero */ + + return (result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ_ __builtin_clz +/** + \details This function saturates a signed value. + \param [in] x Value to be saturated + \param [in] y Bit position to saturate to [1..32] + \return Saturated value. + */ +__ALWAYS_STATIC_INLINE int32_t __SSAT_(int32_t x, uint32_t y) +{ + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + + for (i = 0; i < (y - 1); i++) { + posMax = posMax * 2; + } + + if (x > 0) { + posMax = (posMax - 1); + + if (x > posMax) { + x = posMax; + } + +// x &= (posMax * 2 + 1); + } else { + negMin = -posMax; + + if (x < negMin) { + x = negMin; + } + +// x &= (posMax * 2 - 1); + } + + return (x); +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__ALWAYS_STATIC_INLINE uint32_t __USAT_(uint32_t value, uint32_t sat) +{ + uint32_t result; + + if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) { + result = 0xFFFFFFFF >> (32 - sat); + } else { + result = value; + } + + return (result); +} + +/** + \brief Unsigned Saturate for internal use + \details Saturates an unsigned value, should not call directly. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__ALWAYS_STATIC_INLINE uint32_t __IUSAT(uint32_t value, uint32_t sat) +{ + uint32_t result; + + if (value & 0x80000000) { /* only overflow set bit-31 */ + result = 0; + } else if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) { + result = 0xFFFFFFFF >> (32 - sat); + } else { + result = value; + } + + return (result); +} + +/** + \brief Rotate Right with Extend + \details This function moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \note carry input will always 0. + \param [in] op1 Value to rotate + \return Rotated value + */ +__ALWAYS_STATIC_INLINE uint32_t __RRX(uint32_t op1) +{ + return 0; +} + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] addr Pointer to location + \return value of type uint8_t at (*ptr) + */ +__ALWAYS_STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile("lb %0, 0(%1)" : "=r"(result) : "r"(addr)); + + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] addr Pointer to location + \return value of type uint16_t at (*ptr) + */ +__ALWAYS_STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile("lh %0, 0(%1)" : "=r"(result) : "r"(addr)); + + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] addr Pointer to location + \return value of type uint32_t at (*ptr) + */ +__ALWAYS_STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile("lw %0, 0(%1)" : "=r"(result) : "r"(addr)); + + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] addr Pointer to location + */ +__ALWAYS_STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile("sb %1, 0(%0)" :: "r"(addr), "r"((uint32_t)value) : "memory"); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] addr Pointer to location + */ +__ALWAYS_STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile("sh %1, 0(%0)" :: "r"(addr), "r"((uint32_t)value) : "memory"); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] addr Pointer to location + */ +__ALWAYS_STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile("sw %1, 0(%0)" :: "r"(addr), "r"(value) : "memory"); +} + +/*@}*/ /* end of group CSI_Core_InstructionInterface */ + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CSI_SIMD_intrinsics CSI SIMD Intrinsics + Access to dedicated SIMD instructions \n + Single Instruction Multiple Data (SIMD) extensions are provided to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used. + + @{ +*/ + +/** + \brief Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] + of val2 levitated with the val3. + \details Combine a halfword from one register with a halfword from another register. + The second argument can be left-shifted before extraction of the halfword. + \param [in] val1 first 16-bit operands + \param [in] val2 second 16-bit operands + \param [in] val3 value for left-shifting val2. Value range [0..31]. + \return the combination of halfwords. + \remark + res[15:0] = val1[15:0] \n + res[31:16] = val2[31:16] << val3 + */ +__ALWAYS_STATIC_INLINE uint32_t __PKHBT(uint32_t val1, uint32_t val2, uint32_t val3) +{ + return ((((int32_t)(val1) << 0) & (int32_t)0x0000FFFF) | (((int32_t)(val2) << val3) & (int32_t)0xFFFF0000)); +} + +/** + \brief Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] + of val2 right-shifted with the val3. + \details Combine a halfword from one register with a halfword from another register. + The second argument can be right-shifted before extraction of the halfword. + \param [in] val1 first 16-bit operands + \param [in] val2 second 16-bit operands + \param [in] val3 value for right-shifting val2. Value range [1..32]. + \return the combination of halfwords. + \remark + res[15:0] = val2[15:0] >> val3 \n + res[31:16] = val1[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __PKHTB(uint32_t val1, uint32_t val2, uint32_t val3) +{ + return ((((int32_t)(val1) << 0) & (int32_t)0xFFFF0000) | (((int32_t)(val2) >> val3) & (int32_t)0x0000FFFF)); +} + +/** + \brief Dual 16-bit signed saturate. + \details This function saturates a signed value. + \param [in] x two signed 16-bit values to be saturated. + \param [in] y bit position for saturation, an integral constant expression in the range 1 to 16. + \return the sum of the absolute differences of the following bytes, added to the accumulation value:\n + the signed saturation of the low halfword in val1, saturated to the bit position specified in + val2 and returned in the low halfword of the return value.\n + the signed saturation of the high halfword in val1, saturated to the bit position specified in + val2 and returned in the high halfword of the return value. + */ +__ALWAYS_STATIC_INLINE uint32_t __SSAT16(int32_t x, const uint32_t y) +{ + int32_t r = 0, s = 0; + + r = __SSAT_((((int32_t)x << 16) >> 16), y) & (int32_t)0x0000FFFF; + s = __SSAT_((((int32_t)x) >> 16), y) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturate. + \details This function enables you to saturate two signed 16-bit values to a selected unsigned range. + \param [in] x two signed 16-bit values to be saturated. + \param [in] y bit position for saturation, an integral constant expression in the range 1 to 16. + \return the saturation of the two signed 16-bit values, as non-negative values: + the saturation of the low halfword in val1, saturated to the bit position specified in + val2 and returned in the low halfword of the return value.\n + the saturation of the high halfword in val1, saturated to the bit position specified in + val2 and returned in the high halfword of the return value. + */ +__ALWAYS_STATIC_INLINE uint32_t __USAT16(uint32_t x, const uint32_t y) +{ + int32_t r = 0, s = 0; + + r = __IUSAT(((x << 16) >> 16), y) & 0x0000FFFF; + s = __IUSAT(((x) >> 16), y) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Quad 8-bit saturating addition. + \details This function enables you to perform four 8-bit integer additions, + saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the saturated addition of the first byte of each operand in the first byte of the return value.\n + the saturated addition of the second byte of each operand in the second byte of the return value.\n + the saturated addition of the third byte of each operand in the third byte of the return value.\n + the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __QADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = __SSAT_(((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT_(((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT_(((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT_(((((int32_t)x) >> 24) + (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned saturating addition. + \details This function enables you to perform four unsigned 8-bit integer additions, + saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the saturated addition of the first byte of each operand in the first byte of the return value.\n + the saturated addition of the second byte of each operand in the second byte of the return value.\n + the saturated addition of the third byte of each operand in the third byte of the return value.\n + the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit signed integer range 0 <= x <= 2^8 - 1. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = __IUSAT((((x << 24) >> 24) + ((y << 24) >> 24)), 8) & 0x000000FF; + s = __IUSAT((((x << 16) >> 24) + ((y << 16) >> 24)), 8) & 0x000000FF; + t = __IUSAT((((x << 8) >> 24) + ((y << 8) >> 24)), 8) & 0x000000FF; + u = __IUSAT((((x) >> 24) + ((y) >> 24)), 8) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Quad 8-bit signed addition. + \details This function performs four 8-bit signed integer additions. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the addition of the first bytes from each operand, in the first byte of the return value.\n + the addition of the second bytes of each operand, in the second byte of the return value.\n + the addition of the third bytes of each operand, in the third byte of the return value.\n + the addition of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __SADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = ((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF; + s = ((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF; + t = ((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF; + u = ((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned addition. + \details This function performs four unsigned 8-bit integer additions. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the addition of the first bytes from each operand, in the first byte of the return value.\n + the addition of the second bytes of each operand, in the second byte of the return value.\n + the addition of the third bytes of each operand, in the third byte of the return value.\n + the addition of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] + val2[7:0] \n + res[15:8] = val1[15:8] + val2[15:8] \n + res[23:16] = val1[23:16] + val2[23:16] \n + res[31:24] = val1[31:24] + val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __UADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((x << 24) >> 24) + ((y << 24) >> 24)) & 0x000000FF; + s = (((x << 16) >> 24) + ((y << 16) >> 24)) & 0x000000FF; + t = (((x << 8) >> 24) + ((y << 8) >> 24)) & 0x000000FF; + u = (((x) >> 24) + ((y) >> 24)) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Quad 8-bit saturating subtract. + \details This function enables you to perform four 8-bit integer subtractions, + saturating the results to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the subtraction of the first byte of each operand in the first byte of the return value.\n + the subtraction of the second byte of each operand in the second byte of the return value.\n + the subtraction of the third byte of each operand in the third byte of the return value.\n + the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit signed integer range -2^7 <= x <= 2^7 - 1. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __QSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = __SSAT_(((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT_(((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT_(((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT_(((((int32_t)x) >> 24) - (((int32_t)y) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned saturating subtraction. + \details This function enables you to perform four unsigned 8-bit integer subtractions, + saturating the results to the 8-bit unsigned integer range 0 < x < 2^8 - 1. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the subtraction of the first byte of each operand in the first byte of the return value.\n + the subtraction of the second byte of each operand in the second byte of the return value.\n + the subtraction of the third byte of each operand in the third byte of the return value.\n + the subtraction of the fourth byte of each operand in the fourth byte of the return value.\n + The returned results are saturated to the 8-bit unsigned integer range 0 <= x <= 2^8 - 1. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = __IUSAT((((x << 24) >> 24) - ((y << 24) >> 24)), 8) & 0x000000FF; + s = __IUSAT((((x << 16) >> 24) - ((y << 16) >> 24)), 8) & 0x000000FF; + t = __IUSAT((((x << 8) >> 24) - ((y << 8) >> 24)), 8) & 0x000000FF; + u = __IUSAT((((x) >> 24) - ((y) >> 24)), 8) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Quad 8-bit signed subtraction. + \details This function enables you to perform four 8-bit signed integer subtractions. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __SSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = ((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) & (int32_t)0x000000FF; + s = ((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) & (int32_t)0x000000FF; + t = ((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) & (int32_t)0x000000FF; + u = ((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned subtract. + \details This function enables you to perform four 8-bit unsigned integer subtractions. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + res[7:0] = val1[7:0] - val2[7:0] \n + res[15:8] = val1[15:8] - val2[15:8] \n + res[23:16] = val1[23:16] - val2[23:16] \n + res[31:24] = val1[31:24] - val2[31:24] + */ +__ALWAYS_STATIC_INLINE uint32_t __USUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF; + s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF; + t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF; + u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Unsigned sum of quad 8-bit unsigned absolute difference. + \details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values + of the differences together, returning the result as a single unsigned integer. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \return the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value.\n + The sum is returned as a single unsigned integer. + \remark + absdiff1 = val1[7:0] - val2[7:0] \n + absdiff2 = val1[15:8] - val2[15:8] \n + absdiff3 = val1[23:16] - val2[23:16] \n + absdiff4 = val1[31:24] - val2[31:24] \n + res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4 + */ +__ALWAYS_STATIC_INLINE uint32_t __USAD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((x << 24) >> 24) - ((y << 24) >> 24)) & 0x000000FF; + s = (((x << 16) >> 24) - ((y << 16) >> 24)) & 0x000000FF; + t = (((x << 8) >> 24) - ((y << 8) >> 24)) & 0x000000FF; + u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF; + + return (u + t + s + r); +} + +/** + \brief Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate. + \details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values + of the differences to a 32-bit accumulate operand. + \param [in] x first four 8-bit operands of each subtraction. + \param [in] y second four 8-bit operands of each subtraction. + \param [in] sum accumulation value. + \return the sum of the absolute differences of the following bytes, added to the accumulation value: + the subtraction of the first bytes from each operand, in the first byte of the return value.\n + the subtraction of the second bytes of each operand, in the second byte of the return value.\n + the subtraction of the third bytes of each operand, in the third byte of the return value.\n + the subtraction of the fourth bytes of each operand, in the fourth byte of the return value. + \remark + absdiff1 = val1[7:0] - val2[7:0] \n + absdiff2 = val1[15:8] - val2[15:8] \n + absdiff3 = val1[23:16] - val2[23:16] \n + absdiff4 = val1[31:24] - val2[31:24] \n + sum = absdiff1 + absdiff2 + absdiff3 + absdiff4 \n + res[31:0] = sum[31:0] + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __USADA8(uint32_t x, uint32_t y, uint32_t sum) +{ + int32_t r, s, t, u; + +#ifdef __cplusplus + r = (abs((long long)((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF; + s = (abs((long long)((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF; + t = (abs((long long)((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF; + u = (abs((long long)((x) >> 24) - ((y) >> 24))) & 0x000000FF; +#else + r = (abs(((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF; + s = (abs(((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF; + t = (abs(((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF; + u = (abs(((x) >> 24) - ((y) >> 24))) & 0x000000FF; +#endif + return (u + t + s + r + sum); +} + +/** + \brief Dual 16-bit saturating addition. + \details This function enables you to perform two 16-bit integer arithmetic additions in parallel, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the saturated addition of the low halfwords, in the low halfword of the return value.\n + the saturated addition of the high halfwords, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __QADD16(uint32_t x, uint32_t y) +{ + int32_t r = 0, s = 0; + + r = __SSAT_(((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT_(((((int32_t)x) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating addition. + \details This function enables you to perform two unsigned 16-bit integer additions, saturating + the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the saturated addition of the low halfwords, in the low halfword of the return value.\n + the saturated addition of the high halfwords, in the high halfword of the return value.\n + The results are saturated to the 16-bit unsigned integer range 0 < x < 2^16 - 1. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQADD16(uint32_t x, uint32_t y) +{ + int32_t r = 0, s = 0; + + r = __IUSAT((((x << 16) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed addition. + \details This function enables you to perform two 16-bit signed integer additions. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the addition of the low halfwords in the low halfword of the return value.\n + the addition of the high halfwords in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __SADD16(uint32_t x, uint32_t y) +{ + int32_t r = 0, s = 0; + + r = ((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition + \details This function enables you to perform two 16-bit unsigned integer additions. + \param [in] x first two 16-bit summands for each addition. + \param [in] y second two 16-bit summands for each addition. + \return the addition of the low halfwords in the low halfword of the return value.\n + the addition of the high halfwords in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] + val2[15:0] \n + res[31:16] = val1[31:16] + val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __UADD16(uint32_t x, uint32_t y) +{ + int32_t r = 0, s = 0; + + r = (((x << 16) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) + ((y) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + + +/** + \brief Dual 16-bit signed addition with halved results. + \details This function enables you to perform two signed 16-bit integer additions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved addition of the low halfwords, in the low halfword of the return value.\n + the halved addition of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] + val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHADD16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition with halved results. + \details This function enables you to perform two unsigned 16-bit integer additions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved addition of the low halfwords, in the low halfword of the return value.\n + the halved addition of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] + val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHADD16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Quad 8-bit signed addition with halved results. + \details This function enables you to perform four signed 8-bit integer additions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved addition of the first bytes from each operand, in the first byte of the return value.\n + the halved addition of the second bytes from each operand, in the second byte of the return value.\n + the halved addition of the third bytes from each operand, in the third byte of the return value.\n + the halved addition of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] + val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((((int32_t)x << 24) >> 24) + (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF; + s = (((((int32_t)x << 16) >> 24) + (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF; + t = (((((int32_t)x << 8) >> 24) + (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF; + u = (((((int32_t)x) >> 24) + (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned addition with halved results. + \details This function enables you to perform four unsigned 8-bit integer additions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved addition of the first bytes from each operand, in the first byte of the return value.\n + the halved addition of the second bytes from each operand, in the second byte of the return value.\n + the halved addition of the third bytes from each operand, in the third byte of the return value.\n + the halved addition of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] + val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] + val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] + val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] + val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHADD8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = ((((x << 24) >> 24) + ((y << 24) >> 24)) >> 1) & 0x000000FF; + s = ((((x << 16) >> 24) + ((y << 16) >> 24)) >> 1) & 0x000000FF; + t = ((((x << 8) >> 24) + ((y << 8) >> 24)) >> 1) & 0x000000FF; + u = ((((x) >> 24) + ((y) >> 24)) >> 1) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Dual 16-bit saturating subtract. + \details This function enables you to perform two 16-bit integer subtractions in parallel, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n + the saturated subtraction of the high halfwords, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __QSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __SSAT_(((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT_(((((int32_t)x) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating subtraction. + \details This function enables you to perform two unsigned 16-bit integer subtractions, + saturating the results to the 16-bit unsigned integer range 0 < x < 2^16 - 1. + \param [in] x first two 16-bit operands for each subtraction. + \param [in] y second two 16-bit operands for each subtraction. + \return the saturated subtraction of the low halfwords, in the low halfword of the return value.\n + the saturated subtraction of the high halfwords, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __IUSAT((((x << 16) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed subtraction. + \details This function enables you to perform two 16-bit signed integer subtractions. + \param [in] x first two 16-bit operands of each subtraction. + \param [in] y second two 16-bit operands of each subtraction. + \return the subtraction of the low halfword in the second operand from the low + halfword in the first operand, in the low halfword of the return value. \n + the subtraction of the high halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __SSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned subtract. + \details This function enables you to perform two 16-bit unsigned integer subtractions. + \param [in] x first two 16-bit operands of each subtraction. + \param [in] y second two 16-bit operands of each subtraction. + \return the subtraction of the low halfword in the second operand from the low + halfword in the first operand, in the low halfword of the return value. \n + the subtraction of the high halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[15:0] \n + res[31:16] = val1[31:16] - val2[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __USUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((x << 16) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) - ((y) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed subtraction with halved results. + \details This function enables you to perform two signed 16-bit integer subtractions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved subtraction of the low halfwords, in the low halfword of the return value.\n + the halved subtraction of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] - val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned subtraction with halved results. + \details This function enables you to perform two unsigned 16-bit integer subtractions, halving the results. + \param [in] x first two 16-bit summands. + \param [in] y second two 16-bit summands. + \return the halved subtraction of the low halfwords, in the low halfword of the return value.\n + the halved subtraction of the high halfwords, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[15:0]) >> 1 \n + res[31:16] = (val1[31:16] - val2[31:16]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHSUB16(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Quad 8-bit signed addition with halved results. + \details This function enables you to perform four signed 8-bit integer subtractions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n + the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n + the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n + the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] - val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = (((((int32_t)x << 24) >> 24) - (((int32_t)y << 24) >> 24)) >> 1) & (int32_t)0x000000FF; + s = (((((int32_t)x << 16) >> 24) - (((int32_t)y << 16) >> 24)) >> 1) & (int32_t)0x000000FF; + t = (((((int32_t)x << 8) >> 24) - (((int32_t)y << 8) >> 24)) >> 1) & (int32_t)0x000000FF; + u = (((((int32_t)x) >> 24) - (((int32_t)y) >> 24)) >> 1) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + +/** + \brief Quad 8-bit unsigned subtraction with halved results. + \details This function enables you to perform four unsigned 8-bit integer subtractions, halving the results. + \param [in] x first four 8-bit summands. + \param [in] y second four 8-bit summands. + \return the halved subtraction of the first bytes from each operand, in the first byte of the return value.\n + the halved subtraction of the second bytes from each operand, in the second byte of the return value.\n + the halved subtraction of the third bytes from each operand, in the third byte of the return value.\n + the halved subtraction of the fourth bytes from each operand, in the fourth byte of the return value. + \remark + res[7:0] = (val1[7:0] - val2[7:0] ) >> 1 \n + res[15:8] = (val1[15:8] - val2[15:8] ) >> 1 \n + res[23:16] = (val1[23:16] - val2[23:16]) >> 1 \n + res[31:24] = (val1[31:24] - val2[31:24]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHSUB8(uint32_t x, uint32_t y) +{ + int32_t r, s, t, u; + + r = ((((x << 24) >> 24) - ((y << 24) >> 24)) >> 1) & 0x000000FF; + s = ((((x << 16) >> 24) - ((y << 16) >> 24)) >> 1) & 0x000000FF; + t = ((((x << 8) >> 24) - ((y << 8) >> 24)) >> 1) & 0x000000FF; + u = ((((x) >> 24) - ((y) >> 24)) >> 1) & 0x000000FF; + + return ((u << 24) | (t << 16) | (s << 8) | (r)); +} + +/** + \brief Dual 16-bit add and subtract with exchange. + \details This function enables you to exchange the halfwords of the one operand, + then add the high halfwords and subtract the low halfwords, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the saturated subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the saturated addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __QASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __SSAT_(((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT_(((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating addition and subtraction with exchange. + \details This function enables you to exchange the halfwords of the second operand and + perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, + saturating the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the saturated subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the saturated addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __IUSAT((((x << 16) >> 16) - ((y) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) + ((y << 16) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit addition and subtraction with exchange. + \details It enables you to exchange the halfwords of the second operand, add the high halfwords + and subtract the low halfwords. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition and subtraction with exchange. + \details This function enables you to exchange the two halfwords of the second operand, + add the high halfwords and subtract the low halfwords. + \param [in] x first operand for the subtraction in the low halfword, + and the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, + and the second operand for the addition in the low halfword. + \return the subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the addition of the high halfword in the first operand and the + low halfword in the second operand, in the high halfword of the return value. + \remark + res[15:0] = val1[15:0] - val2[31:16] \n + res[31:16] = val1[31:16] + val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __UASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((x << 16) >> 16) - ((y) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) + ((y << 16) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed addition and subtraction with halved results. + \details This function enables you to exchange the two halfwords of one operand, perform one + signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results. + \param [in] x first 16-bit operands. + \param [in] y second 16-bit operands. + \return the halved subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the halved addition of the low halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] + val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) - (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) + (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned addition and subtraction with halved results and exchange. + \details This function enables you to exchange the halfwords of the second operand, + add the high halfwords and subtract the low halfwords, halving the results. + \param [in] x first operand for the subtraction in the low halfword, and + the first operand for the addition in the high halfword. + \param [in] y second operand for the subtraction in the high halfword, and + the second operand for the addition in the low halfword. + \return the halved subtraction of the high halfword in the second operand from the + low halfword in the first operand, in the low halfword of the return value.\n + the halved addition of the low halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] - val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] + val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHASX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) - ((y) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) + ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit subtract and add with exchange. + \details This function enables you to exchange the halfwords of one operand, + then subtract the high halfwords and add the low halfwords, + saturating the results to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \param [in] x first operand for the addition in the low halfword, + and the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, + and the second operand for the subtraction in the low halfword. + \return the saturated addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the saturated subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit signed integer range -2^15 <= x <= 2^15 - 1. + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __QSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __SSAT_(((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT_(((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned saturating subtraction and addition with exchange. + \details This function enables you to exchange the halfwords of the second operand and perform + one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating + the results to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \param [in] x first operand for the addition in the low halfword, + and the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, + and the second operand for the subtraction in the low halfword. + \return the saturated addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the saturated subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + The returned results are saturated to the 16-bit unsigned integer range 0 <= x <= 2^16 - 1. + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __UQSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = __IUSAT((((x << 16) >> 16) + ((y) >> 16)), 16) & 0x0000FFFF; + s = __IUSAT((((x) >> 16) - ((y << 16) >> 16)), 16) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit unsigned subtract and add with exchange. + \details This function enables you to exchange the halfwords of the second operand, + subtract the high halfwords and add the low halfwords. + \param [in] x first operand for the addition in the low halfword, + and the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, + and the second operand for the subtraction in the low halfword. + \return the addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __USAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((x << 16) >> 16) + ((y) >> 16)) & 0x0000FFFF; + s = (((x) >> 16) - ((y << 16) >> 16)) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed subtraction and addition with exchange. + \details This function enables you to exchange the two halfwords of one operand and perform one + 16-bit integer subtraction and one 16-bit addition. + \param [in] x first operand for the addition in the low halfword, and the first operand + for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, and the second + operand for the subtraction in the low halfword. + \return the addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.\n + the subtraction of the low halfword of the second operand from the + high halfword of the first operand, in the high halfword of the return value.\n + \remark + res[15:0] = val1[15:0] + val2[31:16] \n + res[31:16] = val1[31:16] - val2[15:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) & (int32_t)0x0000FFFF; + s = ((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + + +/** + \brief Dual 16-bit signed subtraction and addition with halved results. + \details This function enables you to exchange the two halfwords of one operand, perform one signed + 16-bit integer subtraction and one signed 16-bit addition, and halve the results. + \param [in] x first 16-bit operands. + \param [in] y second 16-bit operands. + \return the halved addition of the low halfword in the first operand and the + high halfword in the second operand, in the low halfword of the return value.\n + the halved subtraction of the low halfword in the second operand from the + high halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] - val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __SHSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = (((((int32_t)x << 16) >> 16) + (((int32_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((int32_t)x) >> 16) - (((int32_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + +/** + \brief Dual 16-bit unsigned subtraction and addition with halved results and exchange. + \details This function enables you to exchange the halfwords of the second operand, + subtract the high halfwords and add the low halfwords, halving the results. + \param [in] x first operand for the addition in the low halfword, and + the first operand for the subtraction in the high halfword. + \param [in] y second operand for the addition in the high halfword, and + the second operand for the subtraction in the low halfword. + \return the halved addition of the low halfword in the first operand and the + high halfword in the second operand, in the low halfword of the return value.\n + the halved subtraction of the low halfword in the second operand from the + high halfword in the first operand, in the high halfword of the return value. + \remark + res[15:0] = (val1[15:0] + val2[31:16]) >> 1 \n + res[31:16] = (val1[31:16] - val2[15:0]) >> 1 + */ +__ALWAYS_STATIC_INLINE uint32_t __UHSAX(uint32_t x, uint32_t y) +{ + int32_t r, s; + + r = ((((x << 16) >> 16) + ((y) >> 16)) >> 1) & 0x0000FFFF; + s = ((((x) >> 16) - ((y << 16) >> 16)) >> 1) & 0x0000FFFF; + + return ((s << 16) | (r)); +} + +/** + \brief Dual 16-bit signed multiply with exchange returning difference. + \details This function enables you to perform two 16-bit signed multiplications, subtracting + one of the products from the other. The halfwords of the second operand are exchanged + before performing the arithmetic. This produces top * bottom and bottom * top multiplication. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the difference of the products of the two 16-bit signed multiplications. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 - p2 + */ +__ALWAYS_STATIC_INLINE uint32_t __SMUSDX(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)))); +} + +/** + \brief Sum of dual 16-bit signed multiply with exchange. + \details This function enables you to perform two 16-bit signed multiplications with exchanged + halfwords of the second operand, adding the products together. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 + p2 + */ +__ALWAYS_STATIC_INLINE uint32_t __SMUADX(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)))); +} + + +/** + \brief Saturating add. + \details This function enables you to obtain the saturating add of two integers. + \param [in] x first summand of the saturating add operation. + \param [in] y second summand of the saturating add operation. + \return the saturating addition of val1 and val2. + \remark + res[31:0] = SAT(val1 + SAT(val2)) + */ +__ALWAYS_STATIC_INLINE int32_t __QADD(int32_t x, int32_t y) +{ + int32_t result; + + if (y >= 0) { + if ((int32_t)((uint32_t)x + (uint32_t)y) >= x) { + result = x + y; + } else { + result = 0x7FFFFFFF; + } + } else { + if ((int32_t)((uint32_t)x + (uint32_t)y) < x) { + result = x + y; + } else { + result = 0x80000000; + } + } + + return result; +} + +/** + \brief Saturating subtract. + \details This function enables you to obtain the saturating add of two integers. + \param [in] x first summand of the saturating add operation. + \param [in] y second summand of the saturating add operation. + \return the saturating addition of val1 and val2. + \remark + res[31:0] = SAT(val1 - SAT(val2)) + */ +__ALWAYS_STATIC_INLINE int32_t __QSUB(int32_t x, int32_t y) +{ + int64_t tmp; + int32_t result; + + tmp = (int64_t)x - (int64_t)y; + + if (tmp > 0x7fffffff) { + tmp = 0x7fffffff; + } else if (tmp < (-2147483647 - 1)) { + tmp = -2147483647 - 1; + } + + result = tmp; + return result; +} + +/** + \brief Dual 16-bit signed multiply with single 32-bit accumulator. + \details This function enables you to perform two signed 16-bit multiplications, + adding both results to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication added to the accumulate value, as a 32-bit integer. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 + p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMLAD(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator. + \details This function enables you to perform two signed 16-bit multiplications with exchanged + halfwords of the second operand, adding both results to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication with exchanged halfwords of the second + operand added to the accumulate value, as a 32-bit integer. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 + p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMLADX(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. + \details This function enables you to perform two 16-bit signed multiplications, take the + difference of the products, subtracting the high halfword product from the low + halfword product, and add the difference to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 - p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMLSD(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. + \details This function enables you to exchange the halfwords in the second operand, then perform two 16-bit + signed multiplications. The difference of the products is added to a 32-bit accumulate operand. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[31:0] = p1 - p2 + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMLSDX(uint32_t x, uint32_t y, uint32_t sum) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((int32_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with single 64-bit accumulator. + \details This function enables you to perform two signed 16-bit multiplications, adding both results + to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. + This overflow is not detected if it occurs. Instead, the result wraps around modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication added to the accumulate value. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + sum = p1 + p2 + val3[63:32][31:0] \n + res[63:32] = sum[63:32] \n + res[31:0] = sum[31:0] + */ +__ALWAYS_STATIC_INLINE uint64_t __SMLALD(uint32_t x, uint32_t y, uint64_t sum) +{ + return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((uint64_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange with single 64-bit accumulator. + \details This function enables you to exchange the halfwords of the second operand, and perform two + signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow + is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. + Instead, the result wraps around modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the product of each multiplication added to the accumulate value. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + sum = p1 + p2 + val3[63:32][31:0] \n + res[63:32] = sum[63:32] \n + res[31:0] = sum[31:0] + */ +__ALWAYS_STATIC_INLINE uint64_t __SMLALDX(uint32_t x, uint32_t y, uint64_t sum) +{ + return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((uint64_t)sum)))); +} + +/** + \brief dual 16-bit signed multiply subtract with 64-bit accumulate. + \details This function It enables you to perform two 16-bit signed multiplications, take the difference + of the products, subtracting the high halfword product from the low halfword product, and add the + difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the + subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not + detected. Instead, the result wraps round to modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[63:32][31:0] = p1 - p2 + val3[63:32][31:0] + */ +__ALWAYS_STATIC_INLINE uint64_t __SMLSLD(uint32_t x, uint32_t y, uint64_t sum) +{ + return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)) + + (((uint64_t)sum)))); +} + +/** + \brief Dual 16-bit signed multiply with exchange subtract with 64-bit accumulate. + \details This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications, + adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the + multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow + is not detected. Instead, the result wraps round to modulo2^64. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \param [in] sum accumulate value. + \return the difference of the product of each multiplication, added to the accumulate value. + \remark + p1 = val1[15:0] * val2[31:16] \n + p2 = val1[31:16] * val2[15:0] \n + res[63:32][31:0] = p1 - p2 + val3[63:32][31:0] + */ +__ALWAYS_STATIC_INLINE uint64_t __SMLSLDX(uint32_t x, uint32_t y, uint64_t sum) +{ + return ((uint64_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y << 16) >> 16)) + + (((uint64_t)sum)))); +} + +/** + \brief 32-bit signed multiply with 32-bit truncated accumulator. + \details This function enables you to perform a signed 32-bit multiplications, adding the most + significant 32 bits of the 64-bit result to a 32-bit accumulate operand. + \param [in] x first operand for multiplication. + \param [in] y second operand for multiplication. + \param [in] sum accumulate value. + \return the product of multiplication (most significant 32 bits) is added to the accumulate value, as a 32-bit integer. + \remark + p = val1 * val2 \n + res[31:0] = p[63:32] + val3[31:0] + */ +__ALWAYS_STATIC_INLINE uint32_t __SMMLA(int32_t x, int32_t y, int32_t sum) +{ + return (uint32_t)((int32_t)((int64_t)((int64_t)x * (int64_t)y) >> 32) + sum); +} + +/** + \brief Sum of dual 16-bit signed multiply. + \details This function enables you to perform two 16-bit signed multiplications, adding the products together. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the sum of the products of the two 16-bit signed multiplications. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 + p2 + */ +__ALWAYS_STATIC_INLINE uint32_t __SMUAD(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) + + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)))); +} + +/** + \brief Dual 16-bit signed multiply returning difference. + \details This function enables you to perform two 16-bit signed multiplications, taking the difference + of the products by subtracting the high halfword product from the low halfword product. + \param [in] x first 16-bit operands for each multiplication. + \param [in] y second 16-bit operands for each multiplication. + \return the difference of the products of the two 16-bit signed multiplications. + \remark + p1 = val1[15:0] * val2[15:0] \n + p2 = val1[31:16] * val2[31:16] \n + res[31:0] = p1 - p2 + */ +__ALWAYS_STATIC_INLINE uint32_t __SMUSD(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((int32_t)x << 16) >> 16) * (((int32_t)y << 16) >> 16)) - + ((((int32_t)x) >> 16) * (((int32_t)y) >> 16)))); +} + +/** + \brief Dual extracted 8-bit to 16-bit signed addition. + \details This function enables you to extract two 8-bit values from the second operand (at bit positions + [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand. + \param [in] x values added to the sign-extended to 16-bit values. + \param [in] y two 8-bit values to be extracted and sign-extended. + \return the addition of val1 and val2, where the 8-bit values in val2[7:0] and + val2[23:16] have been extracted and sign-extended prior to the addition. + \remark + res[15:0] = val1[15:0] + SignExtended(val2[7:0]) \n + res[31:16] = val1[31:16] + SignExtended(val2[23:16]) + */ +__ALWAYS_STATIC_INLINE uint32_t __SXTAB16(uint32_t x, uint32_t y) +{ + return ((uint32_t)((((((int32_t)y << 24) >> 24) + (((int32_t)x << 16) >> 16)) & (int32_t)0x0000FFFF) | + (((((int32_t)y << 8) >> 8) + (((int32_t)x >> 16) << 16)) & (int32_t)0xFFFF0000))); +} + +/** + \brief Extracted 16-bit to 32-bit unsigned addition. + \details This function enables you to extract two 8-bit values from one operand, zero-extend + them to 16 bits each, and add the results to two 16-bit values from another operand. + \param [in] x values added to the zero-extended to 16-bit values. + \param [in] y two 8-bit values to be extracted and zero-extended. + \return the addition of val1 and val2, where the 8-bit values in val2[7:0] and + val2[23:16] have been extracted and zero-extended prior to the addition. + \remark + res[15:0] = ZeroExt(val2[7:0] to 16 bits) + val1[15:0] \n + res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16] + */ +__ALWAYS_STATIC_INLINE uint32_t __UXTAB16(uint32_t x, uint32_t y) +{ + return ((uint32_t)(((((y << 24) >> 24) + ((x << 16) >> 16)) & 0x0000FFFF) | + ((((y << 8) >> 8) + ((x >> 16) << 16)) & 0xFFFF0000))); +} + +/** + \brief Dual extract 8-bits and sign extend each to 16-bits. + \details This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each. + \param [in] x two 8-bit values in val[7:0] and val[23:16] to be sign-extended. + \return the 8-bit values sign-extended to 16-bit values.\n + sign-extended value of val[7:0] in the low halfword of the return value.\n + sign-extended value of val[23:16] in the high halfword of the return value. + \remark + res[15:0] = SignExtended(val[7:0]) \n + res[31:16] = SignExtended(val[23:16]) + */ +__ALWAYS_STATIC_INLINE uint32_t __SXTB16(uint32_t x) +{ + return ((uint32_t)(((((int32_t)x << 24) >> 24) & (int32_t)0x0000FFFF) | + ((((int32_t)x << 8) >> 8) & (int32_t)0xFFFF0000))); +} + +/** + \brief Dual extract 8-bits and zero-extend to 16-bits. + \details This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each. + \param [in] x two 8-bit values in val[7:0] and val[23:16] to be zero-extended. + \return the 8-bit values sign-extended to 16-bit values.\n + sign-extended value of val[7:0] in the low halfword of the return value.\n + sign-extended value of val[23:16] in the high halfword of the return value. + \remark + res[15:0] = SignExtended(val[7:0]) \n + res[31:16] = SignExtended(val[23:16]) + */ +__ALWAYS_STATIC_INLINE uint32_t __UXTB16(uint32_t x) +{ + return ((uint32_t)((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000))); +} + +//#define __disable_irq __disable_irq_ +//#define __enable_irq __enable_irq_ + +//#include "core_feature_base.h" + +#endif /* _CSI_RV32_GCC_H_ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/es32vf2264.h b/os/common/ext/CMSIS/ES32/ES32VF2264/es32vf2264.h new file mode 100644 index 0000000000..45ed8a81d8 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/es32vf2264.h @@ -0,0 +1,234 @@ +/********************************************************************************** + * + * @file es32vf2264.h + * @brief ES32VF2264 Head File + * + * @date 13 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 13 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __ES32VF2264_H__ +#define __ES32VF2264_H__ + +#define ES32VF2264 + +/* ToDo: set the defines according your Device */ +/* ToDo: define the correct core revision */ +#define __NUCLEI_N_REV 0x0100 /*!< Core Revision r1p0 */ + +/* ToDo: define the correct core features for the nuclei_soc */ +#define __ECLIC_PRESENT 1 /*!< Set to 1 if ECLIC is present */ +#define __ECLIC_BASEADDR 0xD2000000UL /*!< Set to ECLIC baseaddr of your device */ + +#define __ECLIC_INTCTLBITS 4 /*!< Set to 1 - 8, the number of hardware bits are actually implemented in the clicintctl registers. */ +#define __ECLIC_INTNUM 86 /*!< Set to 1 - 1005, the external interrupt number of ECLIC Unit */ +#define __SYSTIMER_PRESENT 1 /*!< Set to 1 if System Timer is present */ +#define __SYSTIMER_BASEADDR 0xD1000000UL /*!< Set to SysTimer baseaddr of your device */ + +/*!< Set to 0, 1, or 2, 0 not present, 1 single floating point unit present, 2 double floating point unit present */ +#define __FPU_PRESENT 0 + +#define __DSP_PRESENT 0 /*!< Set to 1 if DSP is present */ +#define __PMP_PRESENT 1 /*!< Set to 1 if PMP is present */ +#define __PMP_ENTRY_NUM 8 /*!< Set to 8 or 16, the number of PMP entries */ +#define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */ +#define __DCACHE_PRESENT 0 /*!< Set to 1 if D-Cache is present */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __Vendor_EXCEPTION 0 /*!< Set to 1 if vendor exception hander is present */ + +#include +#include "core_rv32.h" +#include "nmsis_compiler.h" + +/** @} */ /* End of group Configuration_of_CMSIS */ + +//#include "core_feature_eclic.h" +//#include "core_feature_timer.h" + +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ + +/* Exported Macros ----------------------------------------------------------- */ +#define CC_WEAK __attribute__((weak)) +#define CPU_CLOCK (72000000) + +#define SYSCFG_LOCK() (WRITE_REG(SYSCFG->PROT, 0x0U)) +#define SYSCFG_UNLOCK() (WRITE_REG(SYSCFG->PROT, 0x55AA6996U)) +#define GET_SYSCFG_LOCK() (READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK)) + +#ifdef __cplusplus + #define __I volatile /* defines 'read only' permissions */ +#else + #define __I volatile const /* defines 'read only' permissions */ +#endif /* __cplusplus */ +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +/* Exported Types ------------------------------------------------------------ */ + +typedef enum IRQn +{ + /* ES32VF2264 specific Interrupt Numbers */ + MACHINE_MODE_SOFT_IRQn = 3, /* 12 */ + CLINT_IRQn = 7, /* 28 */ + MACHINE_MODE_EXTERNAL_IRQn = 11, /* 44 */ + WWDT_IRQn = 16, /* 0 64 */ + IWDT_IRQn = 17, /* 1 68 */ + LVD_IRQn = 18, /* 2 72 */ + CSU_IRQn = 19, /* 3 */ + CMU_IRQn = 20, /* 4 80 */ + EXTI0_3_IRQn = 21, /* 5 84 */ + EXTI4_7_IRQn = 22, /* 6 88 */ + EXTI8_11_IRQn = 23, /* 7 92 */ + EXTI12_15_IRQn = 24, /* 8 96 */ + DMA_IRQn = 25, /* 9 100*/ + USB_IRQn = 27, /* 11 108*/ + ADC_IRQn = 28, /* 12 112*/ + AD16C4T_UP_TRIG_COM_IRQn = 29, /* 13 116*/ + AD16C4T_CC_IRQn = 30, /* 14 120*/ + BSTIM0_IRQn = 31, /* 15 124*/ + GPTIMB0_IRQn = 33, /* 17 132*/ + GPTIMB1_IRQn = 34, /* 18 136*/ + GPTIMB2_IRQn = 35, /* 19 140*/ + AD16C4T_IRQn = 37, /* 21 148*/ + I2C0_IRQn = 39, /* 23 156*/ + I2C1_IRQn = 40, /* 24 */ + SPI0_I2S0_IRQn = 41, /* 25 164*/ + SPI1_I2S1_IRQn = 42, /* 26 */ + EUART0_IRQn = 43, /* 27 */ + EUART1_IRQn = 44, /* 28 */ + CUART0_IRQn = 45, /* 29 180*/ + CUART1_IRQn = 46, /* 30 184*/ + CUART2_IRQn = 47, /* 31 188*/ +} IRQn_Type; + +#define SysTimer_IRQn CLINT_IRQn + +/* Includes ------------------------------------------------------------------ */ + +#include "./ES32VF2264/reg_adc.h" +#include "./ES32VF2264/reg_cmu.h" +#include "./ES32VF2264/reg_crc.h" +#include "./ES32VF2264/reg_csu.h" +#include "./ES32VF2264/reg_dbg.h" +#include "./ES32VF2264/reg_dma.h" +#include "./ES32VF2264/reg_gpio.h" +#include "./ES32VF2264/reg_i2c.h" +#include "./ES32VF2264/reg_iwdt.h" +#include "./ES32VF2264/reg_msc.h" +#include "./ES32VF2264/reg_pis.h" +#include "./ES32VF2264/reg_pmu.h" +#include "./ES32VF2264/reg_rmu.h" +#include "./ES32VF2264/reg_spi.h" +#include "./ES32VF2264/reg_syscfg.h" +#include "./ES32VF2264/reg_timer.h" +#include "./ES32VF2264/reg_uart.h" +#include "./ES32VF2264/reg_wwdt.h" +#include "./ES32VF2264/reg_usb.h" + +/* Exported Macros ----------------------------------------------------------- */ + +#define SRAM_BASE (0x20000000UL) +#define APB_BASE (0x40000000UL) +#define AHB_BASE (0x40080000UL) + +#define SYSCFG_BASE (AHB_BASE + 0x0000) +#define CMU_BASE (AHB_BASE + 0x0400) +#define RMU_BASE (AHB_BASE + 0x0800) +#define PMU_BASE (AHB_BASE + 0x0C00) +#define MSC_BASE (AHB_BASE + 0x1000) +#define GPIOA_BASE (AHB_BASE + 0x4000) +#define GPIOB_BASE (AHB_BASE + 0x4040) +#define GPIOC_BASE (AHB_BASE + 0x4080) +#define GPIOD_BASE (AHB_BASE + 0x40C0) +#define EXTI_BASE (AHB_BASE + 0x4300) +#define CRC_BASE (AHB_BASE + 0x5000) +#define DMA_BASE (AHB_BASE + 0x5400) +#define CSU_BASE (AHB_BASE + 0x5C00) +#define PIS_BASE (AHB_BASE + 0x6000) +#define USB_BASE (AHB_BASE + 0x6400) + +#define AD16C4T_BASE (APB_BASE + 0x0000) +#define BS16T_BASE (APB_BASE + 0x0400) +#define GP16C4T0_BASE (APB_BASE + 0x0800) +#define GP16C4T1_BASE (APB_BASE + 0x0C00) +#define GP16C4T2_BASE (APB_BASE + 0x1000) +#define EUART0_BASE (APB_BASE + 0x4000) +#define EUART1_BASE (APB_BASE + 0x4400) +#define CUART0_BASE (APB_BASE + 0x5000) +#define CUART1_BASE (APB_BASE + 0x5400) +#define CUART2_BASE (APB_BASE + 0x5800) +#define SPI0_I2S0_BASE (APB_BASE + 0x6000) +#define SPI1_I2S1_BASE (APB_BASE + 0x6400) +#define I2C0_BASE (APB_BASE + 0x8000) +#define I2C1_BASE (APB_BASE + 0x8400) +#define WWDT_BASE (APB_BASE + 0x8800) +#define IWDT_BASE (APB_BASE + 0x8C00) +#define DBGC_BASE (APB_BASE + 0x9000) +#define ADC_BASE (APB_BASE + 0x9400) +#define DMA_MUX_BASE (APB_BASE + 0xD000) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define CMU ((CMU_TypeDef *) CMU_BASE) +#define RMU ((RMU_TypeDef *) RMU_BASE) +#define PMU ((PMU_TypeDef *) PMU_BASE) +#define MSC ((MSC_TypeDef *) MSC_BASE ) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define PIS ((PIS_TypeDef *) PIS_BASE) +#define AD16C4T ((TIMER_TypeDef *) AD16C4T_BASE) +#define BS16T ((TIMER_TypeDef *) BS16T_BASE) +#define GP16C4T0 ((TIMER_TypeDef *) GP16C4T0_BASE) +#define GP16C4T1 ((TIMER_TypeDef *) GP16C4T1_BASE) +#define GP16C4T2 ((TIMER_TypeDef *) GP16C4T2_BASE) +#define EUART0 ((UART_TypeDef *) EUART0_BASE) +#define EUART1 ((UART_TypeDef *) EUART1_BASE) +#define CUART0 ((UART_TypeDef *) CUART0_BASE) +#define CUART1 ((UART_TypeDef *) CUART1_BASE) +#define CUART2 ((UART_TypeDef *) CUART2_BASE) +#define SPI0 ((SPI_I2S_TypeDef *) SPI0_I2S0_BASE) +#define SPI1 ((SPI_I2S_TypeDef *) SPI1_I2S1_BASE) +#define I2S0 ((SPI_I2S_TypeDef *) SPI0_I2S0_BASE) +#define I2S1 ((SPI_I2S_TypeDef *) SPI1_I2S1_BASE) +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define WWDT ((WWDT_TypeDef *) WWDT_BASE) +#define IWDT ((IWDT_TypeDef *) IWDT_BASE) +#define DBGC ((DBGC_TypeDef *) DBGC_BASE) +#define ADC ((ADC_TypeDef *) ADC_BASE) +#define DMA ((DMA_TypeDef *) DMA_BASE) +#define DMA_MUX ((DMA_MUX_Typedef *) DMA_MUX_BASE) +#define CSU ((CSU_TypeDef *) CSU_BASE) +#define USB ((USB_TypeDef *) USB_BASE) + +#define ES_USB_PERH_EP_MAX_INDEX (4U) + +#endif /* __ES32VF2264_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_adc.c b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_adc.c new file mode 100644 index 0000000000..5711f8305d --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_adc.c @@ -0,0 +1,291 @@ +/********************************************************************************** + * + * @file md_adc.c + * @brief ADC module driver. + * + * @date 26 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 26 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_adc.h" +#include "md_cmu.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ + +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @addtogroup MD_ADC + * @{ + */ + +/** @addtogroup MD_ADC_Public_Functions + * @{ + */ +/** @addtogroup MD_ADC_Public_Functions_Group1 + * @{ + */ +/** + * @brief Initializes the ADC peripheral according to + * parameters specified in structure ADC_TypeDef. + * @param ADCx: adc peripheral + * @param init: Pointer to a md_adc_init_t structure that contains + * the configuration information for the specified ADC module. + * @retval md_status_t, see @ref md_status_t. + */ +md_status_t md_adc_init(ADC_TypeDef *ADCx, md_adc_init_t *init) +{ + MD_ADC_DISABLE(ADCx); + MODIFY_REG(ADCx->CON1, ADC_CON1_ALIGN_MSK, init->align << ADC_CON1_ALIGN_POS); + MODIFY_REG(ADCx->CON0, ADC_CON0_RSEL_MSK, init->data_bit << ADC_CON0_RSEL_POSS); + + /* Enable discontinuous mode only if continuous mode is disable */ + if (init->disc == MD_ADC_NCH_DISC_EN) + { + init->scan = ENABLE; + init->cont = DISABLE; + SET_BIT(ADCx->CON0, ADC_CON0_NCHDCEN_MSK); + MODIFY_REG(ADCx->CON0, ADC_CON0_ETRGN_MSK, init->disc_nr << ADC_CON0_ETRGN_POSS); + } + else if (init->disc == MD_ADC_ICH_DISC_EN) + { + init->scan = ENABLE; + init->cont = DISABLE; + SET_BIT(ADCx->CON0, ADC_CON0_ICHDCEN_MSK); + MODIFY_REG(ADCx->CON0, ADC_CON0_ETRGN_MSK, init->disc_nr << ADC_CON0_ETRGN_POSS); + } + else + { + CLEAR_BIT(ADCx->CON0, ADC_CON0_NCHDCEN_MSK); + CLEAR_BIT(ADCx->CON0, ADC_CON0_ICHDCEN_MSK); + } + + if ((init->scan == ENABLE) || (init->disc == MD_ADC_NCH_DISC_EN)) + MODIFY_REG(ADCx->CHSL, ADC_CHSL_NSL_MSK, init->nch_nr << ADC_CHSL_NSL_POSS); + + MODIFY_REG(ADCx->CON1, ADC_CON1_CM_MSK, init->cont << ADC_CON1_CM_POS); + MODIFY_REG(ADCx->CON0, ADC_CON0_SCANEN_MSK, init->scan << ADC_CON0_SCANEN_POS); + + /* if the ADC clock less than 1MHz,PWRMOD should be disable*/ + MODIFY_REG(ADCx->CCR, ADC_CCR_PWRMODSEL_MSK, DISABLE << ADC_CCR_PWRMODSEL_POS); + MODIFY_REG(ADCx->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS); + MODIFY_REG(ADCx->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS); + MODIFY_REG(ADCx->CCR, ADC_CCR_POSDIV_MSK, init->div << ADC_CCR_POSDIV_POSS); + MODIFY_REG(ADCx->CCR, ADC_CCR_VRNSEL_MSK, init->n_ref << ADC_CCR_VRNSEL_POS); + MODIFY_REG(ADCx->CCR, ADC_CCR_VRPSEL_MSK, init->p_ref << ADC_CCR_VRPSEL_POS); + MODIFY_REG(ADCx->CON1, ADC_CON1_NCHESEL_MSK, init->nche_sel << ADC_CON1_NCHESEL_POS); + + MD_ADC_ENABLE(ADCx); + + return MD_OK; +} + +/** + * @brief Set each @ref md_adc_init_t field to default value. + * @param init: Pointer to a @ref md_adc_init_t structure + * whose fields will be set to default values. + * @retval None + */ +void md_adc_struct_init(md_adc_init_t *init) +{ + init->align = MD_ADC_DATAALIGN_RIGHT; + init->scan = DISABLE; + init->cont = DISABLE; + init->nch_nr = MD_ADC_NCH_NR_1; + init->disc = MD_ADC_ALL_DISABLE; + init->disc_nr = MD_ADC_DISC_NR_1; + init->data_bit = MD_ADC_CONV_BIT_12; + init->div = MD_ADC_POSDIV_128; + init->nche_sel = MD_ADC_NCHESEL_MODE_ALL; + init->n_ref = MD_ADC_NEG_REF_VSS; + init->p_ref = MD_ADC_POS_REF_VDD; + + return; +} + +/** + * @brief Initializes the ADC peripheral and normal group according to + * parameters specified in structure ADC_TypeDef. + * @param ADCx: adc peripheral + * @param config: Pointer to a md_adc_nch_conf_t structure that contains + * the configuration information for the specified ADC module. + * @retval md_status_t, see @ref md_status_t. + */ +md_status_t md_adc_normal_channel_config(ADC_TypeDef *ADCx, md_adc_nch_conf_t *config) +{ + if (config->idx <= MD_ADC_NCH_IDX_4) + { + ADCx->NCHS1 &= ~(0x1f << (uint32_t)((config->idx - 1) << 3)); + ADCx->NCHS1 |= (config->ch << (uint32_t)((config->idx - 1) << 3)); + } + else if (config->idx <= MD_ADC_NCH_IDX_8) + { + ADCx->NCHS2 &= ~(0x1f << (uint32_t)((config->idx - 5) << 3)); + ADCx->NCHS2 |= (config->ch << (uint32_t)((config->idx - 5) << 3)); + } + else if (config->idx <= MD_ADC_NCH_IDX_12) + { + ADCx->NCHS3 &= ~(0x1f << (uint32_t)((config->idx - 9) << 3)); + ADCx->NCHS3 |= (config->ch << (uint32_t)((config->idx - 9) << 3)); + } + else + { + ADCx->NCHS4 &= ~(0x1f << (uint32_t)((config->idx - 13) << 3)); + ADCx->NCHS4 |= (config->ch << (uint32_t)((config->idx - 13) << 3)); + } + + if (config->ch < 8) + { + ADCx->SMPT1 &= ~(0x0f << (uint32_t)(config->ch << 2)); + ADCx->SMPT1 |= config->samp << (uint32_t)(config->ch << 2); + } + else if (config->ch < 16) + { + ADCx->SMPT2 &= ~(0x0f << (uint32_t)((config->ch - 8) << 2)); + ADCx->SMPT2 |= config->samp << (uint32_t)((config->ch - 8) << 2); + } + else + { + ADCx->SMPT3 &= ~(0x0f << (uint32_t)((config->ch - 16) << 2)); + ADCx->SMPT3 |= config->samp << (uint32_t)((config->ch - 16) << 2); + } + + return MD_OK; +} + +/** + * @brief Set each @ref md_adc_nch_conf_t field to default value. + * @param config: Pointer to a @ref md_adc_nch_conf_t structure + * whose fields will be set to default values. + * @retval None + */ +void md_adc_normal_struct_init(md_adc_nch_conf_t *config) +{ + config->ch = MD_ADC_CHANNEL_0; + config->idx = MD_ADC_NCH_IDX_1; + config->samp = MD_ADC_SAMPLETIME_4; + + return; +} + +/** + * @brief Initializes the ADC insert group according to + * parameters specified in structure ADC_TypeDef. + * @param ADCx: adc peripheral + * @param config: Pointer to a md_adc_ich_conf_t structure that contains + * the configuration information for the specified ADC module. + * @retval md_status_t, see @ref md_status_t. + */ +md_status_t md_adc_insert_channel_config(ADC_TypeDef *ADCx, md_adc_ich_conf_t *config) +{ + MODIFY_REG(ADCx->CHSL, ADC_CHSL_ISL_MSK, config->nr << ADC_CHSL_ISL_POSS); + ADCx->ICHS &= ~(0x1f << (uint32_t)((config->idx - 1) << 3)); + ADCx->ICHS |= config->ch << (uint32_t)((config->idx - 1) << 3); + + if (config->auto_m == ENABLE) + SET_BIT(ADCx->CON0, ADC_CON0_IAUTO_MSK); + else + CLEAR_BIT(ADCx->CON0, ADC_CON0_IAUTO_MSK); + + if (config->ch < 8) + { + ADCx->SMPT1 &= ~(0x0f << (uint32_t)(config->ch << 2)); + ADCx->SMPT1 |= config->samp << (uint32_t)(config->ch << 2); + } + else if (config->ch < 16) + { + ADCx->SMPT2 &= ~(0x0f << (uint32_t)((config->ch - 8) << 2)); + ADCx->SMPT2 |= config->samp << (uint32_t)((config->ch - 8) << 2); + } + else + { + ADCx->SMPT3 &= ~(0x0f << (uint32_t)((config->ch - 16) << 2)); + ADCx->SMPT3 |= config->samp << (uint32_t)((config->ch - 16) << 2); + } + + switch (config->idx) + { + case MD_ADC_ICH_IDX_1: + ADCx->ICHOFF1 = config->offset; + break; + + case MD_ADC_ICH_IDX_2: + ADCx->ICHOFF2 = config->offset; + break; + + case MD_ADC_ICH_IDX_3: + ADCx->ICHOFF3 = config->offset; + break; + + case MD_ADC_ICH_IDX_4: + ADCx->ICHOFF4 = config->offset; + break; + + default: + break; + } + + return MD_OK; +} + +/** + * @brief Set each @ref md_adc_ich_conf_t field to default value. + * @param config: Pointer to a @ref md_adc_ich_conf_t structure + * whose fields will be set to default values. + * @retval None + */ +void md_adc_insert_struct_init(md_adc_ich_conf_t *config) +{ + config->ch = MD_ADC_CHANNEL_2; + config->idx = MD_ADC_ICH_IDX_1; + config->samp = MD_ADC_SAMPLETIME_4; + config->offset = 0; + config->nr = MD_ADC_ICH_NR_1; + config->auto_m = DISABLE; + + return; +} +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_adc.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_adc.h new file mode 100644 index 0000000000..c0449b668d --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_adc.h @@ -0,0 +1,2327 @@ +/********************************************************************************** + * + * @file md_adc.h + * @brief Header file of ADC module driver. + * + * @date 26 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 26 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __MD_ADC_H__ +#define __MD_ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif /*__cplusplus */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_utils.h" + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Constants -------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_ADC ADC + * @brief ADC micro driver + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup MD_ADC_Pubulic_Types ADC Pubulic Types + * @{ + */ + +/** + *@brief ADC data alignment + */ +typedef enum +{ + MD_ADC_DATAALIGN_RIGHT = 0x0U, /**< ADC data alignment right */ + MD_ADC_DATAALIGN_LEFT = 0x1U, /**< ADC data alignment left */ +} md_adc_align_t; + +/** + *@brief ADC config hannal trigger the EOC IT mode + */ +typedef enum +{ + MD_ADC_NCHESEL_MODE_ALL = 0x0U, /**< ADC set RCHE after convert sequence finish */ + MD_ADC_NCHESEL_MODE_ONE = 0x1U, /**< ADC set RCHE after one convert finish */ +} md_adc_nchesel_t; + +/** + *@brief ADC channels + */ +typedef enum +{ + MD_ADC_CHANNEL_0 = 0x0U, /**< ADC channel 0 */ + MD_ADC_CHANNEL_1 = 0x1U, /**< ADC channel 1 */ + MD_ADC_CHANNEL_2 = 0x2U, /**< ADC channel 2 */ + MD_ADC_CHANNEL_3 = 0x3U, /**< ADC channel 3 */ + MD_ADC_CHANNEL_4 = 0x4U, /**< ADC channel 4 */ + MD_ADC_CHANNEL_5 = 0x5U, /**< ADC channel 5 */ + MD_ADC_CHANNEL_6 = 0x6U, /**< ADC channel 6 */ + MD_ADC_CHANNEL_7 = 0x7U, /**< ADC channel 7 */ + MD_ADC_CHANNEL_8 = 0x8U, /**< ADC channel 8 */ + MD_ADC_CHANNEL_9 = 0x9U, /**< ADC channel 9 */ + MD_ADC_CHANNEL_10 = 0xAU, /**< ADC channel 10 */ + MD_ADC_CHANNEL_11 = 0xBU, /**< ADC channel 11 */ + MD_ADC_CHANNEL_12 = 0xCU, /**< ADC channel 12 */ + MD_ADC_CHANNEL_13 = 0xDU, /**< ADC channel 13 */ + MD_ADC_CHANNEL_14 = 0xEU, /**< ADC channel 14 */ + MD_ADC_CHANNEL_15 = 0xFU, /**< ADC channel 15 */ + MD_ADC_CHANNEL_16 = 0x10U, /**< ADC channel 16 */ + MD_ADC_CHANNEL_17 = 0x11U, /**< ADC channel 17 */ + MD_ADC_CHANNEL_18 = 0x12U, /**< ADC channel 18 */ + MD_ADC_CHANNEL_19 = 0x13U, /**< ADC channel 19 */ +} md_adc_channel_t; + +/** + * @brief ADC sampletime + */ +typedef enum +{ + MD_ADC_SAMPLETIME_4 = 0x0U, /**< ADC sampling times 4 clk */ + MD_ADC_SAMPLETIME_6 = 0x1U, /**< ADC sampling times 6 clk */ + MD_ADC_SAMPLETIME_10 = 0x2U, /**< ADC sampling times 10 clk */ + MD_ADC_SAMPLETIME_18 = 0x3U, /**< ADC sampling times 18 clk */ +} md_adc_samp_t; + +/** + *@brief ADC index channel in normal group + */ +typedef enum +{ + MD_ADC_NCH_IDX_1 = 0x1U, /**< ADC normal channel index 1 */ + MD_ADC_NCH_IDX_2 = 0x2U, /**< ADC normal channel index 2 */ + MD_ADC_NCH_IDX_3 = 0x3U, /**< ADC normal channel index 3 */ + MD_ADC_NCH_IDX_4 = 0x4U, /**< ADC normal channel index 4 */ + MD_ADC_NCH_IDX_5 = 0x5U, /**< ADC normal channel index 5 */ + MD_ADC_NCH_IDX_6 = 0x6U, /**< ADC normal channel index 6 */ + MD_ADC_NCH_IDX_7 = 0x7U, /**< ADC normal channel index 7 */ + MD_ADC_NCH_IDX_8 = 0x8U, /**< ADC normal channel index 8 */ + MD_ADC_NCH_IDX_9 = 0x9U, /**< ADC normal channel index 9 */ + MD_ADC_NCH_IDX_10 = 0xAU, /**< ADC normal channel index 10 */ + MD_ADC_NCH_IDX_11 = 0xBU, /**< ADC normal channel index 11 */ + MD_ADC_NCH_IDX_12 = 0xCU, /**< ADC normal channel index 12 */ + MD_ADC_NCH_IDX_13 = 0xDU, /**< ADC normal channel index 13 */ + MD_ADC_NCH_IDX_14 = 0xEU, /**< ADC normal channel index 14 */ + MD_ADC_NCH_IDX_15 = 0xFU, /**< ADC normal channel index 15 */ + MD_ADC_NCH_IDX_16 = 0x10U, /**< ADC normal channel index 16 */ +} md_adc_nch_idx_t; + +/** + * @brief ADC index channel in insert group + */ +typedef enum +{ + MD_ADC_ICH_IDX_1 = 0x1U, /**< ADC insert channel index 1 */ + MD_ADC_ICH_IDX_2 = 0x2U, /**< ADC insert channel index 2 */ + MD_ADC_ICH_IDX_3 = 0x3U, /**< ADC insert channel index 3 */ + MD_ADC_ICH_IDX_4 = 0x4U, /**< ADC insert channel index 4 */ +} md_adc_ich_idx_t; + +/** + * @brief ADC analog watchdog mode + */ +typedef enum +{ + MD_ADC_ANAWTD_NONE = 0x0U, /**< No watch dog */ + MD_ADC_ANAWTD_SING_NM = 0x800200U, /**< One normal channel watch dog */ + MD_ADC_ANAWTD_SING_IST = 0x400200U, /**< One insert channel Injec watch dog */ + MD_ADC_ANAWTD_SING_NMIST = 0xC00200U, /**< One normal and insert channel watch dog */ + MD_ADC_ANAWTD_ALL_NM = 0x800000U, /**< All normal channel watch dog */ + MD_ADC_ANAWTD_ALL_IST = 0x400000U, /**< All insert channel watch dog */ + MD_ADC_ANAWTD_ALL_NMIST = 0xC00000U, /**< All normal and insert channel watch dog */ +} md_adc_ana_wdg_t; + +/** + * @brief ADC Event type + */ +typedef enum +{ + MD_ADC_AWD_EVENT = (1U << 0), /**< ADC analog watch dog event */ +} md_adc_event_type_t; + +/** + * @brief ADC CLK POST DIV definition + */ +typedef enum +{ + MD_ADC_POSDIV_2 = 0x0U, /**< ADC CLK POST DIV 2 */ + MD_ADC_POSDIV_4 = 0x1U, /**< ADC CLK POST DIV 4 */ + MD_ADC_POSDIV_8 = 0x2U, /**< ADC CLK POST DIV 8 */ + MD_ADC_POSDIV_16 = 0x3U, /**< ADC CLK POST DIV 16 */ + MD_ADC_POSDIV_32 = 0x4U, /**< ADC CLK POST DIV 32 */ + MD_ADC_POSDIV_64 = 0x5U, /**< ADC CLK POST DIV 64 */ + MD_ADC_POSDIV_128 = 0x6U, /**< ADC CLK POST DIV 128 */ + MD_ADC_POSDIV_256 = 0x7U, /**< ADC CLK POST DIV 256 */ +} md_adc_clk_div_t; + +/** + * @brief ADC negative reference voltage definition + */ +typedef enum +{ + MD_ADC_NEG_REF_VSS = 0x1U, /**< ADC negative regerence voltage VSS */ + MD_ADC_NEG_REF_VREFN = 0x0U, /**< ADC negative regerence voltage VREFN */ +} md_adc_neg_ref_t; + +/** + * @brief ADC positive reference voltage definition + */ +typedef enum +{ + MD_ADC_POS_REF_VDD = 0x0U, /**< ADC posotove reference is VDD */ + MD_ADC_POS_REF_VREEFP = 0x1U, /**< ADC posotove reference is VREEFP */ +} md_adc_pos_ref_t; + +/** + * @brief ADC numbers of normal conversion channals + */ +typedef enum +{ + MD_ADC_NCH_NR_1 = 0x0U, /**< ADC number of normal conversion 1 */ + MD_ADC_NCH_NR_2 = 0x1U, /**< ADC number of normal conversion 2 */ + MD_ADC_NCH_NR_3 = 0x2U, /**< ADC number of normal conversion 3 */ + MD_ADC_NCH_NR_4 = 0x3U, /**< ADC number of normal conversion 4 */ + MD_ADC_NCH_NR_5 = 0x4U, /**< ADC number of normal conversion 5 */ + MD_ADC_NCH_NR_6 = 0x5U, /**< ADC number of normal conversion 6 */ + MD_ADC_NCH_NR_7 = 0x6U, /**< ADC number of normal conversion 7 */ + MD_ADC_NCH_NR_8 = 0x7U, /**< ADC number of normal conversion 8 */ + MD_ADC_NCH_NR_9 = 0x8U, /**< ADC number of normal conversion 9 */ + MD_ADC_NCH_NR_10 = 0x9U, /**< ADC number of normal conversion 10 */ + MD_ADC_NCH_NR_11 = 0xAU, /**< ADC number of normal conversion 11 */ + MD_ADC_NCH_NR_12 = 0xBU, /**< ADC number of normal conversion 12 */ + MD_ADC_NCH_NR_13 = 0xCU, /**< ADC number of normal conversion 13 */ + MD_ADC_NCH_NR_14 = 0xDU, /**< ADC number of normal conversion 14 */ + MD_ADC_NCH_NR_15 = 0xEU, /**< ADC number of normal conversion 15 */ + MD_ADC_NCH_NR_16 = 0xFU, /**< ADC number of normal conversion 16 */ +} md_adc_nch_nr_t; + +/** + * @brief ADC numbers of insert conversion channals + */ +typedef enum +{ + MD_ADC_ICH_NR_1 = 0x0U, /**< ADC number of insert conversion 1 */ + MD_ADC_ICH_NR_2 = 0x1U, /**< ADC number of insert conversion 2 */ + MD_ADC_ICH_NR_3 = 0x2U, /**< ADC number of insert conversion 3 */ + MD_ADC_ICH_NR_4 = 0x3U, /**< ADC number of insert conversion 4 */ +} md_adc_ich_nr_t; + +/** + * @brief ADC discontinuous mode choose + */ +typedef enum +{ + MD_ADC_ALL_DISABLE = 0x0U, /**< ADC discontinuous mode all disable */ + MD_ADC_NCH_DISC_EN = 0x1U, /**< ADC normal channel discontinuous mode enable */ + MD_ADC_ICH_DISC_EN = 0x2U, /**< ADC insert channel discontinuous mode enable */ +} md_adc_disc_mode_t; + +/** + * @brief ADC numbers of channals in discontinuous conversion mode + */ +typedef enum +{ + MD_ADC_DISC_NR_1 = 0x0U, /**< ADC number of discontinuous conversion 1 */ + MD_ADC_DISC_NR_2 = 0x1U, /**< ADC number of discontinuous conversion 2 */ + MD_ADC_DISC_NR_3 = 0x2U, /**< ADC number of discontinuous conversion 3 */ + MD_ADC_DISC_NR_4 = 0x3U, /**< ADC number of discontinuous conversion 4 */ + MD_ADC_DISC_NR_5 = 0x4U, /**< ADC number of discontinuous conversion 5 */ + MD_ADC_DISC_NR_6 = 0x5U, /**< ADC number of discontinuous conversion 6 */ + MD_ADC_DISC_NR_7 = 0x6U, /**< ADC number of discontinuous conversion 7 */ + MD_ADC_DISC_NR_8 = 0x7U, /**< ADC number of discontinuous conversion 8 */ +} md_adc_disc_nr_t; + +/** + * @brief ADC resolution of conversion + */ +typedef enum +{ + MD_ADC_CONV_BIT_6 = 0x0U, /**< ADC resolution of conversion 6 */ + MD_ADC_CONV_BIT_8 = 0x1U, /**< ADC resolution of conversion 8 */ + MD_ADC_CONV_BIT_10 = 0x2U, /**< ADC resolution of conversion 10 */ + MD_ADC_CONV_BIT_12 = 0x3U, /**< ADC resolution of conversion 12 */ +} md_adc_conv_bit_t; + +/** + * @brief ADC external trigger mode choose + */ +typedef enum +{ + MD_ADC_ETS_DISABLE = 0x0U, /**< ADC external trigger function disable */ + MD_ADC_ETS_RISE = 0x1U, /**< rise edge trigger ADC */ + MD_ADC_ETS_FALL = 0x2U, /**< fall edge trigger ADC */ + MD_ADC_ETS_RISE_FALL = 0x3U, /**< both rise and fall edge trigger ADC */ +} md_adc_ets_t; + +/** + * @brief Structure definition of ADC common initialization + */ +typedef struct +{ + md_adc_align_t align; /**< Specifies ADC data alignment */ + type_func_t scan; /**< Choose scan mode enable or not */ + type_func_t cont; /**< Choose continuous mode enable or not */ + md_adc_nch_nr_t nch_nr; /**< Length of normal ranks will be converted */ + md_adc_disc_mode_t disc; /**< Discontinuous mode enable or not */ + md_adc_disc_nr_t disc_nr; /**< Number of discontinuous conversions channel */ + md_adc_conv_bit_t data_bit; /**< The precision of conversion */ + md_adc_clk_div_t div; /**< ADCCLK divider */ + md_adc_nchesel_t nche_sel; /**< Trigger the NCHE FALG mode */ + md_adc_neg_ref_t n_ref; /**< The negative reference voltage*/ + md_adc_pos_ref_t p_ref; /**< The positive reference voltage*/ +} md_adc_init_t; + +/** + * @brief Structure definition of ADC channel for normal group + */ +typedef struct +{ + md_adc_channel_t ch; /**< The channel to configure into ADC normal group */ + md_adc_nch_idx_t idx; /**< The rank in the normal group sequencer */ + md_adc_samp_t samp; /**< Sampling time value to be set */ +} md_adc_nch_conf_t; + +/** + * @brief ADC Configuration insert Channel structure definition + */ +typedef struct +{ + md_adc_channel_t ch; /**< Selection of ADC channel to configure */ + md_adc_ich_idx_t idx; /**< Rank in the insert group sequencer */ + md_adc_samp_t samp; /**< Sampling time value for selected channel */ + uint32_t offset; /**< The offset about converted data */ + md_adc_ich_nr_t nr; /**< The number of insert ranks */ + type_func_t auto_m; /**< insert sequence's auto function */ +} md_adc_ich_conf_t; +/** + * @} + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** @defgroup MD_ADC_Public_Macros ADC Public Macros + * @{ + */ +#define MD_ADC_ENABLE(x) (SET_BIT((x)->CON1, ADC_CON1_ADCEN_MSK)) +#define MD_ADC_DISABLE(x) (CLEAR_BIT((x)->CON1, ADC_CON1_ADCEN_MSK)) +#define MD_ADC_NH_TRIG_BY_SOFT(x) (SET_BIT((x)->CON1, ADC_CON1_NCHTRG_MSK)) +#define MD_ADC_IH_TRIG_BY_SOFT(x) (SET_BIT((x)->CON1, ADC_CON1_ICHTRG_MSK)) +#define MD_ADC_VREF_OUT_ENABLE(x) (SET_BIT((x)->CCR, ADC_CCR_VREFOEN_MSK)) +#define MD_ADC_VREF_OUT_DISABLE(x) (CLEAR_BIT((x)->CCR, ADC_CCR_VREFOEN_MSK)) +#define MD_ADC_NETS_ENABLE(x, mode) (MODIFY_REG((x)->CON1, ADC_CON1_NETS_MSK, (mode) << ADC_CON1_NETS_POSS)) +#define MD_ADC_IETS_ENABLE(x, mode) (MODIFY_REG((x)->CON1, ADC_CON1_IETS_MSK, (mode) << ADC_CON1_IETS_POSS)) +#define MD_ADC_NETS_DISABLE(x) (MODIFY_REG((x)->CON1, ADC_CON1_NETS_MSK, 0 << ADC_CON1_NETS_POSS)) +#define MD_ADC_IETS_DISABLE(x) (MODIFY_REG((x)->CON1, ADC_CON1_IETS_MSK, 0 << ADC_CON1_IETS_POSS)) +#define MD_ADC_SPEED_HIGH_ENABLE(x) (CLEAR_BIT((x)->CCR, ADC_CCR_PWRMODSEL_MSK)) +#define MD_ADC_SPEED_HIGH_DISABLE(x) (SET_BIT((x)->CCR, ADC_CCR_PWRMODSEL_MSK)) +#define MD_ADC_CALIBRATE_ENABLE(x) (SET_BIT((x)->CCR, ADC_CCR_TRMEN_MSK)) +#define MD_ADC_CALIBRATE_DISABLE(x) (CLEAR_BIT((x)->CCR, ADC_CCR_TRMEN_MSK)) +#define MD_ADC_CALZERO_ENABLE(x) (SET_BIT((x)->CCR, ADC_CCR_CALZERO_MSK)) +#define MD_ADC_CALZERO_DISABLE(x) (CLEAR_BIT((x)->CCR, ADC_CCR_CALZERO_MSK)) +#define MD_ADC_TEMP_SENSE_ENABLE(x) (SET_BIT((x)->CCR, ADC_CCR_TSEN_MSK)) +#define MD_ADC_TEMP_SENSE_DISABLE(x) (CLEAR_BIT((x)->CCR, ADC_CCR_TSEN_MSK)) +#define MD_ADC_PREDIV_ENABLE(x) (SET_BIT((x)->CCR, ADC_CCR_PREDIV_MSK)) +#define MD_ADC_PREDIV_DISABLE(x) (CLEAR_BIT((x)->CCR, ADC_CCR_PREDIV_MSK)) + +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @defgroup MD_ADC_Public_Functions ADC Public Functions + * @{ + */ +/** @defgroup MD_ADC_Public_Functions_Group2 STAT + * @{ + */ + +/** + * @brief Get Status of AWDF. + * @param ADCx ADC Instance + * @retval Status: + * - 0: NO HAPPEN + * - 1: HAPPEN + */ +__STATIC_INLINE uint32_t md_adc_get_stat_awdf(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->STAT, ADC_STAT_AWDF_MSK, ADC_STAT_AWDF_POS); +} + +/** + * @brief Get Status of nche. + * @param ADCx ADC Instance + * @retval Status: + * - 0: no completed + * - 1: completed + */ +__STATIC_INLINE uint32_t md_adc_get_stat_nche(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->STAT, ADC_STAT_NCHE_MSK, ADC_STAT_NCHE_POS); +} + +/** + * @brief Get Status of iche. + * @param ADCx ADC Instance + * @retval Status: + * - 0: no completed + * - 1: completed + */ +__STATIC_INLINE uint32_t md_adc_get_stat_iche(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->STAT, ADC_STAT_ICHE_MSK, ADC_STAT_ICHE_POS); +} + +/** + * @brief Get Status of ovr. + * @param ADCx ADC Instance + * @retval Status: + * - 0: no happen + * - 1: happen + */ +__STATIC_INLINE uint32_t md_adc_get_stat_ovr(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->STAT, ADC_STAT_OVR_MSK, ADC_STAT_OVR_POS); +} + +/** + * @brief Get Status of nchs. + * @param ADCx ADC Instance + * @retval Status: + * - 0: no happen + * - 1: standard switch + */ +__STATIC_INLINE uint32_t md_adc_get_stat_nchs(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->STAT, ADC_STAT_NCHS_MSK, ADC_STAT_NCHS_POS); +} + +/** + * @brief Get Status of ichs. + * @param ADCx ADC Instance + * @retval Status: + * - 0: no happen + * - 1: insert swith + */ +__STATIC_INLINE uint32_t md_adc_get_stat_ichs(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->STAT, ADC_STAT_ICHS_MSK, ADC_STAT_ICHS_POS); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group3 CLR + * @{ + */ +/** + * @brief Clear AWDF flag . + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_clr_awdf(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CLR, ADC_CLR_AWDF_MSK); +} + +/** + * @brief Clear NCHE flag . + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_clr_nche(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CLR, ADC_CLR_NCHE_MSK); +} + +/** + * @brief Clear ICHE flag + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_clr_iche(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CLR, ADC_CLR_ICHE_MSK); +} + +/** + * @brief Clear OVR flag + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_clr_ovr(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CLR, ADC_CLR_OVR_MSK); +} + +/** + * @brief Clear NCHS flag + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_clr_nchs(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CLR, ADC_CLR_NCHS_MSK); +} + +/** + * @brief Clear ICHS flag + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_clr_ichs(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CLR, ADC_CLR_ICHS_MSK); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group4 CON0 + * @{ + */ +/** + * @brief Set analog watchdog channel selection + * @param ADCx ADC Instance + * @param sel Value of the following: + * - 0x0: ADC analog input Channel0 + * - 0x1: ADC analog input Channel1 + * ...... + * - 0x12: ADC analog input Channel18 + * @retval None + */ +__STATIC_INLINE void md_adc_set_channel_awdch(ADC_TypeDef *ADCx, uint32_t sel) +{ + MODIFY_REG(ADCx->CON0, ADC_CON0_AWDCH_MSK, sel << ADC_CON0_AWDCH_POSS); +} + +/** + * @brief Get analog watchdog channel selection + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: ADC analog input Channel0 + * - 0x1: ADC analog input Channel1 + * ...... + * - 0x12: ADC analog input Channel18 + */ +__STATIC_INLINE uint32_t md_adc_get_channel_awdch(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON0, ADC_CON0_AWDCH_MSK, ADC_CON0_AWDCH_POSS); +} + +/** + * @brief Interrupt enable for end of conversion + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_conv_end_interrupt_enable_ncheie(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CON0, ADC_CON0_NCHEIE_MSK); +} + +/** + * @brief Interrupt disable for end of conversion + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_conv_end_interrupt_disable_ncheie(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CON0, ADC_CON0_NCHEIE_MSK); +} + +/** + * @brief Check if interrupt enable for end of conversion + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: Disable + * - 0x1: Enable + */ +__STATIC_INLINE uint32_t md_adc_is_conv_end_interrupt_enable(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON0, ADC_CON0_NCHEIE_MSK, ADC_CON0_NCHEIE_POS); +} + +/** + * @brief Analog watchdog interrupt enable + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_analog_wdt_interrupt_enable_awdie(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CON0, ADC_CON0_AWDIE_MSK); +} + +/** + * @brief Analog watchdog interrupt disable + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_analog_wdt_interrupt_disable_awdie(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CON0, ADC_CON0_AWDIE_MSK); +} + +/** + * @brief Check if interrupt enable for analog watchdog + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: Disable + * - 0x1: Enable + */ +__STATIC_INLINE uint32_t md_adc_is_analog_wdt_enable(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON0, ADC_CON0_AWDIE_MSK, ADC_CON0_AWDIE_POS); +} + +/** + * @brief Interrupt enable for inserted channels + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_inserted_channel_interrupt_enable_icheie(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CON0, ADC_CON0_ICHEIE_MSK); +} + +/** + * @brief Interrupt disable for inserted channels + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_inserted_channel_interrupt_disable_icheie(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CON0, ADC_CON0_ICHEIE_MSK); +} + +/** + * @brief Check if interrupt enable for inserted channels + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: Disable + * - 0x1: Enable + */ +__STATIC_INLINE uint32_t md_adc_is_inserted_channel_interrupt_enable(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON0, ADC_CON0_ICHEIE_MSK, ADC_CON0_ICHEIE_POS); +} + +/** + * @brief Scan mode enable + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_scan_mode_enable_scanen(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CON0, ADC_CON0_SCANEN_MSK); +} + +/** + * @brief Scan mode disable + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_scan_mode_disable_scanen(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CON0, ADC_CON0_SCANEN_MSK); +} + +/** + * @brief Check if interrupt enable for scan mode + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: Disable + * - 0x1: Enable + */ +__STATIC_INLINE uint32_t md_adc_is_scan_mode_enable(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON0, ADC_CON0_SCANEN_MSK, ADC_CON0_SCANEN_POS); +} + +/** + * @brief Enable the watchdog on a single channel in scan mode + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_wdt_single_channel_scan_mode_enable_awdsgl(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CON0, ADC_CON0_AWDSGL_MSK); +} + +/** + * @brief Enable the watchdog on a single channel in scan mode + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_wdt_single_channel_scan_mode_disable_awdsgl(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CON0, ADC_CON0_AWDSGL_MSK); +} + +/** + * @brief Check if interrupt enable for watchdog on a single channel in scan mode + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: Disable + * - 0x1: Enable + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_awdsgl(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON0, ADC_CON0_AWDSGL_MSK, ADC_CON0_AWDSGL_POS); +} + +/** + * @brief Automatic inserted group conversion enable + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_auto_inserted_conversion_enable_iauto(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CON0, ADC_CON0_IAUTO_MSK); +} + +/** + * @brief Automatic inserted group conversion disable + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_auto_inserted_conversion_disable_iauto(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CON0, ADC_CON0_IAUTO_MSK); +} + +/** + * @brief Check if interrupt enable for automatic inserted group conversion + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: Disable + * - 0x1: Enable + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_iauto(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON0, ADC_CON0_IAUTO_MSK, ADC_CON0_IAUTO_POS); +} + +/** + * @brief Discontinuous mode on normal channels enable + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_normal_channel_discon_mode_enable_nchdcen(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CON0, ADC_CON0_NCHDCEN_MSK); +} + +/** + * @brief Discontinuous mode on normal channels disable + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_normal_channel_discon_mode_disable_nchdcen(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CON0, ADC_CON0_NCHDCEN_MSK); +} + +/** + * @brief Check if interrupt enable for discontinuous mode on normal channels + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: Disable + * - 0x1: Enable + */ +__STATIC_INLINE uint32_t md_adc_is_normal_channel_discon_mode_enable(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON0, ADC_CON0_NCHDCEN_MSK, ADC_CON0_NCHDCEN_POS); +} + +/** + * @brief Discontinuous mode on inserted channels enable + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_inserted_channel_discon_mode_enable_ichdcen(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CON0, ADC_CON0_ICHDCEN_MSK); +} + +/** + * @brief Discontinuous mode on inserted channels enable + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_inserted_channel_discon_mode_disable_ichdcen(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CON0, ADC_CON0_ICHDCEN_MSK); +} + +/** + * @brief Check if interrupt enable for discontinuous mode on inserted channels + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: Disable + * - 0x1: Enable + */ +__STATIC_INLINE uint32_t md_adc_is_inserted_channel_discon_mode_enable(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON0, ADC_CON0_ICHDCEN_MSK, ADC_CON0_ICHDCEN_POS); +} + +/** + * @brief External trigger enable for discontinuous channels + * @param ADCx ADC Instance + * @param sel: Value of the following: + * - 0x0: 0 channels + * - 0x1: 1 channels + * - 0x2: 2 channels + * - 0x3: 3 channels + * - 0x4: 4 channels + * - 0x5: 5 channels + * - 0x6: 6 channels + * - 0x7: 7 channels + * - 0x8: 8 channels + * @retval None + */ +__STATIC_INLINE void md_adc_set_ex_trigger_discon_etrgn(ADC_TypeDef *ADCx, uint32_t sel) +{ + MODIFY_REG(ADCx->CON0, ADC_CON0_ETRGN_MSK, sel << ADC_CON0_ETRGN_POSS); +} +/** + * @brief gets channel of extrigger noncontinuous. + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: 0 channels + * - 0x1: 1 channels + * - 0x2: 2 channels + * - 0x3: 3 channels + * - 0x4: 4 channels + * - 0x5: 5 channels + * - 0x6: 6 channels + * - 0x7: 7 channels + * - 0x8: 8 channels + */ +__STATIC_INLINE uint32_t md_adc_get_ex_trigger_discon_etrgn(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON0, ADC_CON0_ETRGN_MSK, ADC_CON0_ETRGN_POSS); +} + +/** + * @brief + * @param ADCx ADC Instance + * @param sel: Value of the following: + * - 0x0: 0 + * - 0x1: 1 clk + * - 0x2: 2 clk + * - 0x3: 3 clk + * - 0x4: 4 clk + * - 0x5: 5 clk + * - 0x6: 6 clk + * - 0x7: 7 clk + * @retval None + */ +__STATIC_INLINE void md_adc_set_channel_switch_time_cntw(ADC_TypeDef *ADCx, uint32_t val) +{ + MODIFY_REG(ADCx->CON0, ADC_CON0_CNTW_MSK, val << ADC_CON0_CNTW_POSS); +} +/** + * @brief + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: 0 + * - 0x1: 1 clk + * - 0x2: 2 clk + * - 0x3: 3 clk + * - 0x4: 4 clk + * - 0x5: 5 clk + * - 0x6: 6 clk + * - 0x7: 7 clk + */ +__STATIC_INLINE uint32_t md_adc_get_channel_switch_time_cntw(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON0, ADC_CON0_CNTW_MSK, ADC_CON0_CNTW_POSS); +} + +/** + * @brief Analog watchdog enable on inserted channels + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_wdt_inserted_channel_enable_ichwdten(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CON0, ADC_CON0_ICHWDTEN_MSK); +} + +/** + * @brief Analog watchdog disable on inserted channels + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_wdt_inserted_channel_disable_ichwdten(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CON0, ADC_CON0_ICHWDTEN_MSK); +} + +/** + * @brief Check if interrupt enable for analog watchdog on inserted channels + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: Disable + * - 0x1: Enable + */ +__STATIC_INLINE uint32_t md_adc_is_wdt_inserted_channel_enable(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON0, ADC_CON0_ICHWDTEN_MSK, ADC_CON0_ICHWDTEN_POS); +} + +/** + * @brief Analog watchdog enable on normal channels + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_wdt_normal_channel_enable_nchwden(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CON0, ADC_CON0_NCHWDEN_MSK); +} + +/** + * @brief Analog watchdog disable on normal channels + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_wdt_normal_channel_disable_nchwden(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CON0, ADC_CON0_NCHWDEN_MSK); +} + +/** + * @brief Check if interrupt enable for analog watchdog on normal channels + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: Disable + * - 0x1: Enable + */ +__STATIC_INLINE uint32_t md_adc_is_wdt_normal_channel_enable_nchwden(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON0, ADC_CON0_NCHWDEN_MSK, ADC_CON0_NCHWDEN_POS); +} + +/** + * @brief Sets Resolution + * @param ADCx ADC Instance + * @param rsel: Value of the following: + * - 0x0: 6 bits + * - 0x1: 8 bits + * - 0x2: 10 bits + * - 0x3: 12 bits + * @retval NONE + */ +__STATIC_INLINE void md_adc_set_resolution_rsel(ADC_TypeDef *ADCx, uint32_t rsel) +{ + MODIFY_REG(ADCx->CON0, ADC_CON0_RSEL_MSK, rsel << ADC_CON0_RSEL_POSS); +} + +/** + * @brief Gets resolution + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: 6 bits + * - 0x1: 8 bits + * - 0x2: 10 bits + * - 0x3: 12 bits + */ +__STATIC_INLINE uint32_t md_adc_get_resolution_rsel(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON0, ADC_CON0_RSEL_MSK, ADC_CON0_RSEL_POSS); +} + +/** + * @brief Overrun interrupt enable + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_overrun_interrupt_enable_ovrie(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CON0, ADC_CON0_OVRIE_MSK); +} + +/** + * @brief Overrun interrupt disable + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_overrun_interrupt_disable_ovrie(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CON0, ADC_CON0_OVRIE_MSK); +} + +/** + * @brief Check if interrupt enable for overrun + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: Disable + * - 0x1: Enable + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ovrie(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON0, ADC_CON0_OVRIE_MSK, ADC_CON0_OVRIE_POS); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group5 CON1 + * @{ + */ +/** + * @brief A/D converter enable + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_converter_enable_adcen(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CON1, ADC_CON1_ADCEN_MSK); +} + +/** + * @brief A/D converter disable + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_converter_disable_adcen(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CON1, ADC_CON1_ADCEN_MSK); +} + +/** + * @brief Check if converter enable + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: Disable + * - 0x1: Enable + */ +__STATIC_INLINE uint32_t md_adc_is_converter_enable(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON1, ADC_CON1_ADCEN_MSK, ADC_CON1_ADCEN_POS); +} + +/** + * @brief Continuous conversion enable + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_continuous_conversion_enable_cm(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CON1, ADC_CON1_CM_MSK); +} + +/** + * @brief Continuous conversion disable + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_continuous_conversion_disable_cm(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CON1, ADC_CON1_CM_MSK); +} + +/** + * @brief Check if continuous conversion enable + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: Disable + * - 0x1: Enable + */ +__STATIC_INLINE uint32_t md_adc_is_continuous_conversion_enable(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON1, ADC_CON1_CM_MSK, ADC_CON1_CM_POS); +} + +/** + * @brief Enable DMA request + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_dma_enable(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CON1, ADC_CON1_DMA_MSK); +} + +/** + * @brief Disable DMA request + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_dma_disable(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CON1, ADC_CON1_DMA_MSK); +} + +/** + * @brief Get dma function state + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: disable + * - 0x1: enable + */ +__STATIC_INLINE uint32_t md_adc_get_dma_status(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON1, ADC_CON1_DMA_MSK, ADC_CON1_DMA_POS); +} + +/** + * @brief Set dma function + * @param ADCx ADC Instance + * @param sel Value of the following: + * - 0x0: disable + * - 0x1: enable + * @retval None + */ +__STATIC_INLINE void md_adc_set_overflow_detection_state_ovrdis(ADC_TypeDef *ADCx, uint32_t sel) +{ + MODIFY_REG(ADCx->CON1, ADC_CON1_DMA_MSK, sel << ADC_CON1_DMA_POS); +} + +/** + * @brief Get dma function state + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: disable + * - 0x1: enable + */ +__STATIC_INLINE uint32_t md_adc_get_overflow_detection_state_ovrdis(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON1, ADC_CON1_DMA_MSK, ADC_CON1_DMA_POS); +} + +/** + * @brief Set end of conversion selection + * @param ADCx ADC Instance + * @param sel Value of the following: + * - 0x0: The EOC bit is set at the end of each sequence of normal conversions + * - 0x1: The EOC bit is set at the end of each normal conversion + * @retval None + */ +__STATIC_INLINE void md_adc_set_eoc_selection_nchesel(ADC_TypeDef *ADCx, uint32_t sel) +{ + MODIFY_REG(ADCx->CON1, ADC_CON1_NCHESEL_MSK, sel << ADC_CON1_NCHESEL_POS); +} + +/** + * @brief Get end of conversion selection + * @param ADCx ADC Instance + * @retval sel Value of the following: + * - 0x0: The EOC bit is set at the end of each sequence of normal conversions + * - 0x1: The EOC bit is set at the end of each normal conversion + */ +__STATIC_INLINE uint32_t md_adc_get_eoc_selection_nchesel(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON1, ADC_CON1_NCHESEL_MSK, ADC_CON1_NCHESEL_POS); +} + +/** + * @brief Set data alignment + * @param ADCx ADC Instance + * @param sel Value of the following: + * - 0x0: Right alignment + * - 0x1: Left alignment + * @retval None + */ +__STATIC_INLINE void md_adc_set_data_alignment_align(ADC_TypeDef *ADCx, uint32_t sel) +{ + MODIFY_REG(ADCx->CON1, ADC_CON1_ALIGN_MSK, sel << ADC_CON1_ALIGN_POS); +} + +/** + * @brief Get data alignment + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: Right alignment + * - 0x1: Left alignment + */ +__STATIC_INLINE uint32_t md_adc_get_data_alignment_align(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON1, ADC_CON1_ALIGN_MSK, ADC_CON1_ALIGN_POS); +} + +/** + * @brief Set extern trigger polarity of insert channel + * @param ADCx ADC Instance + * @param polarity External trigger polarity + * @retval None + */ +__STATIC_INLINE void md_adc_set_insert_conv_extern_polarity(ADC_TypeDef *ADCx, md_adc_ets_t polarity) +{ + MODIFY_REG(ADCx->CON1, ADC_CON1_IETS_MSK, polarity << ADC_CON1_IETS_POSS); +} + +/** + * @brief Get extern trigger polarity of insert channel + * @param ADCx ADC Instance + * @retval External trigger polarity + */ +__STATIC_INLINE uint32_t md_adc_get_insert_conv_extern_polarity(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON1, ADC_CON1_IETS_MSK, ADC_CON1_IETS_POSS); +} + +/** + * @brief Start conversion of inserted channels + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_inserted_channel_conv_start_ichtrg(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CON1, ADC_CON1_ICHTRG_MSK); +} + +/** + * @brief Set extern trigger polarity of normal channel + * @param ADCx ADC Instance + * @param polarity External trigger polarity + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_conv_extern_polarity(ADC_TypeDef *ADCx, md_adc_ets_t polarity) +{ + MODIFY_REG(ADCx->CON1, ADC_CON1_NETS_MSK, polarity << ADC_CON1_NETS_POSS); +} + +/** + * @brief Get extern trigger polarity of normal channel + * @param ADCx ADC Instance + * @retval External trigger polarity + */ +__STATIC_INLINE uint32_t md_adc_get_normal_conv_extern_polarity(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CON1, ADC_CON1_NETS_MSK, ADC_CON1_NETS_POSS); +} + +/** + * @brief Start conversion of normal channels + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_channel_conv_start_nchtrg(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CON1, ADC_CON1_NCHTRG_MSK); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group6 SMPT1 + * @{ + */ +/** + * @brief Set channel sampling time configuration + * @param ADCx ADC Instance + * @param is1 ADC channel,see @ref md_adc_channel_t + * @param val Sampling time of each channels[0 ~ 7] ,see @ref md_adc_samp_t + * @retval None + */ +__STATIC_INLINE void md_adc_set_smpt1_cht(ADC_TypeDef *ADCx, uint32_t val, uint32_t is1) +{ + MODIFY_REG(ADCx->SMPT1, 0xf << (4 * is1), val << (4 * is1)); +} + +/** + * @brief Get channel sampling time configuration + * @param ADCx ADC Instance + * @param is1 ADC channel,see @ref md_adc_channel_t + * @retval Sampling time of each channels[0 ~ 7],see @ref md_adc_samp_t + */ +__STATIC_INLINE uint32_t md_adc_get_smpt1_cht(ADC_TypeDef *ADCx, uint32_t is1) +{ + return READ_BITS(ADCx->SMPT1, (0xf << (4 * is1)), (4 * is1)); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group7 SMPT2 + * @{ + */ +/** + * @brief Set channel sampling time configuration + * @param ADCx ADC Instance + * @param is1 ADC channel,see @ref md_adc_channel_t + * @param val Sampling time of each channels[8 ~ 15],see @ref md_adc_samp_t + * @retval None + */ +__STATIC_INLINE void md_adc_set_smpt2_cht(ADC_TypeDef *ADCx, uint32_t val, uint32_t is1) +{ + MODIFY_REG(ADCx->SMPT2, (0xf << (4 * (is1 - 8))), val << (4 * (is1 - 8))); +} + +/** + * @brief Get channel sampling time configuration + * @param ADCx ADC Instance + * @param is1 ADC channel,see @ref md_adc_channel_t + * @retval Sampling time of each channels[8 ~ 15],see @ref md_adc_samp_t + */ +__STATIC_INLINE uint32_t md_adc_get_smpt2_cht(ADC_TypeDef *ADCx, uint32_t is1) +{ + return READ_BITS(ADCx->SMPT2, (0xf << (4 * (is1 - 8))), (4 * (is1 - 8))); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group8 SMPT3 + * @{ + */ +/** + * @brief Set channel sampling time configuration + * @param ADCx ADC Instance + * @param is1 ADC channel,see @ref md_adc_channel_t + * @param val Sampling time of each channels[16 ~ 19] + * @retval None + */ +__STATIC_INLINE void md_adc_set_smpt3_cht(ADC_TypeDef *ADCx, uint32_t val, uint32_t is1) +{ + MODIFY_REG(ADCx->SMPT3, (0xf << (4 * (is1 - 16))), val << (4 * (is1 - 16))); +} + +/** + * @brief Get channel sampling time configuration + * @param ADCx ADC Instance + * @param is1 ADC channel,see @ref md_adc_channel_t + * @retval Sampling time of each channels[16 ~ 19],see @ref md_adc_samp_t + */ +__STATIC_INLINE uint32_t md_adc_get_smpt3_cht(ADC_TypeDef *ADCx, uint32_t is1) +{ + return READ_BITS(ADCx->SMPT3, 0xf << (4 * (is1 - 16)), (4 * (is1 - 16))); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group9 NCHOFF + * @{ + */ +/** + * @brief Set nch data offset + * @param ADCx ADC Instance + * @param val nch data offset[0 ~ 4095] + * @retval None + */ +__STATIC_INLINE void md_adc_set_nch_data_offset_noff(ADC_TypeDef *ADCx, uint32_t val) +{ + WRITE_REG(ADCx->NCHOFF, val); +} + +/** + * @brief Get channel sampling time configuration + * @param ADCx ADC Instance + * @retval nch data offset[0 ~ 4095] + */ +__STATIC_INLINE uint32_t md_adc_get_nch_data_offset_noff(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->NCHOFF) & 0xfff; +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group10 ICHOFF1 + * @{ + */ +/** + * @brief Set data offset for inserted channel(ADC_ICHDR1) + * @param ADCx ADC Instance + * @param val Offset data + * @retval None + */ +__STATIC_INLINE void md_adc_set_joffset_ichoff1_ioff(ADC_TypeDef *ADCx, uint32_t val) +{ + WRITE_REG(ADCx->ICHOFF1, val); +} + +/** + * @brief Get data offset for inserted channel(ADC_ICHDR1) + * @param ADCx ADC Instance + * @retval Offset data + */ +__STATIC_INLINE uint32_t md_adc_get_joffset_ichoff1_ioff(ADC_TypeDef *ADCx) +{ + return (READ_REG(ADCx->ICHOFF1) & 0xfff); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group11 ICHOFF2 + * @{ + */ +/** + * @brief Set data offset for inserted channel(ADC_ICHDR2) + * @param ADCx ADC Instance + * @param val Offset data + * @retval None + */ +__STATIC_INLINE void md_adc_set_joffset_ichoff2_ioff(ADC_TypeDef *ADCx, uint32_t val) +{ + WRITE_REG(ADCx->ICHOFF2, val); +} + +/** + * @brief Get data offset for inserted channel(ADC_ICHDR2) + * @param ADCx ADC Instance + * @retval Offset data + */ +__STATIC_INLINE uint32_t md_adc_get_joffset_ichoff2_ioff(ADC_TypeDef *ADCx) +{ + return (READ_REG(ADCx->ICHOFF2) & 0xfff); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group12 ICHOFF3 + * @{ + */ +/** + * @brief Set data offset for inserted channel(ADC_ICHDR3) + * @param ADCx ADC Instance + * @param val Offset data + * @retval None + */ +__STATIC_INLINE void md_adc_set_joffset_ichoff3_ioff(ADC_TypeDef *ADCx, uint32_t val) +{ + WRITE_REG(ADCx->ICHOFF3, val); +} + +/** + * @brief Get data offset for inserted channel(ADC_ICHDR3) + * @param ADCx ADC Instance + * @retval Offset data + */ +__STATIC_INLINE uint32_t md_adc_get_joffset_ichoff3_ioff(ADC_TypeDef *ADCx) +{ + return (READ_REG(ADCx->ICHOFF3) & 0xfff) ; +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group13 ICHOFF4 + * @{ + */ +/** + * @brief Set data offset for inserted channel(ADC_ICHDR4) + * @param ADCx ADC Instance + * @param val Offset data + * @retval None + */ +__STATIC_INLINE void md_adc_set_joffset_ichoff4_ioff(ADC_TypeDef *ADCx, uint32_t val) +{ + WRITE_REG(ADCx->ICHOFF4, val); +} + +/** + * @brief Get data offset for inserted channel(ADC_ICHDR4) + * @param ADCx ADC Instance + * @retval Offset data + */ +__STATIC_INLINE uint32_t md_adc_get_joffset_ichoff4_ioff(ADC_TypeDef *ADCx) +{ + return (READ_REG(ADCx->ICHOFF4) & 0xfff) ; +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group14 NCHS1 + * @{ + */ +/** + * @brief Set 1st conversion in normal sequence + * @param ADCx ADC Instance + * @param ns1 Channel number[0 ~ 18] + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_1st_conv_ns1(ADC_TypeDef *ADCx, uint32_t ns1) +{ + MODIFY_REG(ADCx->NCHS1, ADC_NCHS1_NS1_MSK, ns1 << ADC_NCHS1_NS1_POSS); +} + +/** + * @brief Get 1st conversion in normal sequence + * @param ADCx ADC Instance + * @retval Channel number[0 ~ 18] + */ +__STATIC_INLINE uint32_t md_adc_get_normal_1st_conv_ns1(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->NCHS1, ADC_NCHS1_NS1_MSK, ADC_NCHS1_NS1_POSS); +} + +/** + * @brief Set 2st conversion in normal sequence + * @param ADCx ADC Instance + * @param ns2 Channel number[0 ~ 18] + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_2st_conv_ns2(ADC_TypeDef *ADCx, uint32_t ns2) +{ + MODIFY_REG(ADCx->NCHS1, ADC_NCHS1_NS2_MSK, ns2 << ADC_NCHS1_NS2_POSS); +} + +/** + * @brief Get 2st conversion in normal sequence + * @param ADCx ADC Instance + * @retval Channel number[0 ~ 18] + */ +__STATIC_INLINE uint32_t md_adc_get_normal_2st_conv_ns2(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->NCHS1, ADC_NCHS1_NS2_MSK, ADC_NCHS1_NS2_POSS); +} + +/** + * @brief Set 3st conversion in normal sequence + * @param ADCx ADC Instance + * @param ns3 Channel number[0 ~ 18] + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_3st_conv_ns3(ADC_TypeDef *ADCx, uint32_t ns3) +{ + MODIFY_REG(ADCx->NCHS1, ADC_NCHS1_NS3_MSK, ns3 << ADC_NCHS1_NS3_POSS); +} + +/** + * @brief Get 3st conversion in normal sequence + * @param ADCx ADC Instance + * @retval Channel number[0 ~ 18] + */ +__STATIC_INLINE uint32_t md_adc_get_normal_3st_conv_ns3(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->NCHS1, ADC_NCHS1_NS3_MSK, ADC_NCHS1_NS3_POSS); +} + +/** + * @brief Set 4st conversion in normal sequence + * @param ADCx ADC Instance + * @param ns4 Channel number[0 ~ 18] + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_4st_conv_ns4(ADC_TypeDef *ADCx, uint32_t ns4) +{ + MODIFY_REG(ADCx->NCHS1, ADC_NCHS1_NS4_MSK, ns4 << ADC_NCHS1_NS4_POSS); +} + +/** + * @brief Get 4st conversion in normal sequence + * @param ADCx ADC Instance + * @retval Channel number[0 ~ 18] + */ +__STATIC_INLINE uint32_t md_adc_get_normal_4st_conv_ns4(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->NCHS1, ADC_NCHS1_NS4_MSK, ADC_NCHS1_NS4_POSS); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group15 NCHS2 + * @{ + */ +/** + * @brief Set 5st conversion in normal sequence + * @param ADCx ADC Instance + * @param ns5 Channel number[0 ~ 18] + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_5st_conv_ns5(ADC_TypeDef *ADCx, uint32_t ns5) +{ + MODIFY_REG(ADCx->NCHS2, ADC_NCHS2_NS5_MSK, ns5 << ADC_NCHS2_NS5_POSS); +} + +/** + * @brief Get 5st conversion in normal sequence + * @param ADCx ADC Instance + * @retval Channel number[0 ~ 18] + */ +__STATIC_INLINE uint32_t md_adc_get_normal_5st_conv_ns5(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->NCHS2, ADC_NCHS2_NS5_MSK, ADC_NCHS2_NS5_POSS); +} + +/** + * @brief Set 6st conversion in normal sequence + * @param ADCx ADC Instance + * @param ns6 Channel number[0 ~ 18] + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_6st_conv_ns6(ADC_TypeDef *ADCx, uint32_t ns6) +{ + MODIFY_REG(ADCx->NCHS2, ADC_NCHS2_NS6_MSK, ns6 << ADC_NCHS2_NS6_POSS); +} + +/** + * @brief Get 6st conversion in normal sequence + * @param ADCx ADC Instance + * @retval Channel number[0 ~ 18] + */ +__STATIC_INLINE uint32_t md_adc_get_normal_6st_conv_ns6(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->NCHS2, ADC_NCHS2_NS6_MSK, ADC_NCHS2_NS6_POSS); +} + +/** + * @brief Set 7st conversion in normal sequence + * @param ADCx ADC Instance + * @param ns7 Channel number[0 ~ 18] + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_7st_conv_ns7(ADC_TypeDef *ADCx, uint32_t ns7) +{ + MODIFY_REG(ADCx->NCHS2, ADC_NCHS2_NS7_MSK, ns7 << ADC_NCHS2_NS7_POSS); +} + +/** + * @brief Get 7st conversion in normal sequence + * @param ADCx ADC Instance + * @retval Channel number[0 ~ 18] + */ +__STATIC_INLINE uint32_t md_adc_get_normal_7st_conv_ns7(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->NCHS2, ADC_NCHS2_NS7_MSK, ADC_NCHS2_NS7_POSS); +} + +/** + * @brief Set 8st conversion in normal sequence + * @param ADCx ADC Instance + * @param ns8 Channel number[0 ~ 18] + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_8st_conv_ns8(ADC_TypeDef *ADCx, uint32_t ns8) +{ + MODIFY_REG(ADCx->NCHS2, ADC_NCHS2_NS8_MSK, ns8 << ADC_NCHS2_NS8_POSS); +} + +/** + * @brief Get 8st conversion in normal sequence + * @param ADCx ADC Instance + * @retval Channel number[0 ~ 18] + */ +__STATIC_INLINE uint32_t md_adc_get_normal_8st_conv_ns8(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->NCHS2, ADC_NCHS2_NS8_MSK, ADC_NCHS2_NS8_POSS); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group16 NCHS3 + * @{ + */ +/** + * @brief Set 9st conversion in normal sequence + * @param ADCx ADC Instance + * @param ns9 Channel number[0 ~ 18] + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_9st_conv_ns9(ADC_TypeDef *ADCx, uint32_t ns9) +{ + MODIFY_REG(ADCx->NCHS3, ADC_NCHS3_NS9_MSK, ns9 << ADC_NCHS3_NS9_POSS); +} + +/** + * @brief Get 9st conversion in normal sequence + * @param ADCx ADC Instance + * @retval Channel number[0 ~ 18] + */ +__STATIC_INLINE uint32_t md_adc_get_normal_9st_conv_ns9(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->NCHS3, ADC_NCHS3_NS9_MSK, ADC_NCHS3_NS9_POSS); +} + +/** + * @brief Set 10st conversion in normal sequence + * @param ADCx ADC Instance + * @param ns10 Channel number[0 ~ 18] + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_10st_conv_ns10(ADC_TypeDef *ADCx, uint32_t ns10) +{ + MODIFY_REG(ADCx->NCHS3, ADC_NCHS3_NS10_MSK, ns10 << ADC_NCHS3_NS10_POSS); +} + +/** + * @brief Get 10st conversion in normal sequence + * @param ADCx ADC Instance + * @retval Channel number[0 ~ 18] + */ +__STATIC_INLINE uint32_t md_adc_get_normal_10st_conv_ns10(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->NCHS3, ADC_NCHS3_NS10_MSK, ADC_NCHS3_NS10_POSS); +} + +/** + * @brief Set 11st conversion in normal sequence + * @param ADCx ADC Instance + * @param ns11 Channel number[0 ~ 18] + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_11st_conv_ns11(ADC_TypeDef *ADCx, uint32_t ns11) +{ + MODIFY_REG(ADCx->NCHS3, ADC_NCHS3_NS11_MSK, ns11 << ADC_NCHS3_NS11_POSS); +} + +/** + * @brief Get 11st conversion in normal sequence + * @param ADCx ADC Instance + * @retval Channel number[0 ~ 18] + */ +__STATIC_INLINE uint32_t md_adc_get_normal_11st_conv_ns11(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->NCHS3, ADC_NCHS3_NS11_MSK, ADC_NCHS3_NS11_POSS); +} + +/** + * @brief Set 12st conversion in normal sequence + * @param ADCx ADC Instance + * @param ns12 Channel number[0 ~ 18] + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_12st_conv_ns12(ADC_TypeDef *ADCx, uint32_t ns12) +{ + MODIFY_REG(ADCx->NCHS3, ADC_NCHS3_NS12_MSK, ns12 << ADC_NCHS3_NS12_POSS); +} + +/** + * @brief Get 12st conversion in normal sequence + * @param ADCx ADC Instance + * @retval Channel number[0 ~ 18] + */ +__STATIC_INLINE uint32_t md_adc_get_normal_12st_conv_ns12(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->NCHS3, ADC_NCHS3_NS12_MSK, ADC_NCHS3_NS12_POSS); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group17 NCHS4 + * @{ + */ +/** + * @brief Set 13st conversion in normal sequence + * @param ADCx ADC Instance + * @param ns13 Channel number[0 ~ 18] + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_13st_conv_ns13(ADC_TypeDef *ADCx, uint32_t ns13) +{ + MODIFY_REG(ADCx->NCHS4, ADC_NCHS4_NS13_MSK, ns13 << ADC_NCHS4_NS13_POSS); +} + +/** + * @brief Get 13st conversion in normal sequence + * @param ADCx ADC Instance + * @retval Channel number[0 ~ 18] + */ +__STATIC_INLINE uint32_t md_adc_get_normal_13st_conv_ns13(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->NCHS4, ADC_NCHS4_NS13_MSK, ADC_NCHS4_NS13_POSS); +} + +/** + * @brief Set 14st conversion in normal sequence + * @param ADCx ADC Instance + * @param ns14 Channel number[0 ~ 18] + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_14st_conv_ns14(ADC_TypeDef *ADCx, uint32_t ns14) +{ + MODIFY_REG(ADCx->NCHS4, ADC_NCHS4_NS14_MSK, ns14 << ADC_NCHS4_NS14_POSS); +} + +/** + * @brief Get 14st conversion in normal sequence + * @param ADCx ADC Instance + * @retval Channel number[0 ~ 18] + */ +__STATIC_INLINE uint32_t md_adc_get_normal_14st_conv_ns14(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->NCHS4, ADC_NCHS4_NS14_MSK, ADC_NCHS4_NS14_POSS); +} + +/** + * @brief Set 15st conversion in normal sequence + * @param ADCx ADC Instance + * @param ns15 Channel number[0 ~ 18] + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_15st_conv_ns15(ADC_TypeDef *ADCx, uint32_t ns15) +{ + MODIFY_REG(ADCx->NCHS4, ADC_NCHS4_NS15_MSK, ns15 << ADC_NCHS4_NS15_POSS); +} + +/** + * @brief Get 15st conversion in normal sequence + * @param ADCx ADC Instance + * @retval Channel number[0 ~ 18] + */ +__STATIC_INLINE uint32_t md_adc_get_normal_15st_conv_ns15(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->NCHS4, ADC_NCHS4_NS15_MSK, ADC_NCHS4_NS15_POSS); +} + +/** + * @brief Set 16st conversion in normal sequence + * @param ADCx ADC Instance + * @param ns16 Channel number[0 ~ 18] + * @retval None + */ +__STATIC_INLINE void md_adc_set_normal_16st_conv_ns16(ADC_TypeDef *ADCx, uint32_t ns16) +{ + MODIFY_REG(ADCx->NCHS4, ADC_NCHS4_NS16_MSK, ns16 << ADC_NCHS4_NS16_POSS); +} + +/** + * @brief Get 16st conversion in normal sequence + * @param ADCx ADC Instance + * @retval Channel number[0 ~ 18] + */ +__STATIC_INLINE uint32_t md_adc_get_normal_16st_conv_ns16(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->NCHS4, ADC_NCHS4_NS16_MSK, ADC_NCHS4_NS16_POSS); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group18 ICHS + * @{ + */ +/** + * @brief Set 1st conversion in inserted sequence + * @param ADCx ADC Instance + * @param is1 Channel number[0 ~ 18] + * @retval None + */ +__STATIC_INLINE void md_adc_set_insert_1st_conv_is1(ADC_TypeDef *ADCx, uint32_t is1) +{ + MODIFY_REG(ADCx->ICHS, ADC_ICHS_IS1_MSK, is1 << ADC_ICHS_IS1_POSS); +} + +/** + * @brief Get 1st conversion in inserted sequence + * @param ADCx ADC Instance + * @retval Channel number[0 ~ 18] + */ +__STATIC_INLINE uint32_t md_adc_get_insert_1st_conv_is1(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->ICHS, ADC_ICHS_IS1_MSK, ADC_ICHS_IS1_POSS); +} + +/** + * @brief Set 2st conversion in inserted sequence + * @param ADCx ADC Instance + * @param is2 Channel number[0 ~ 18] + * @retval None + */ +__STATIC_INLINE void md_adc_set_insert_2st_conv_is2(ADC_TypeDef *ADCx, uint32_t is2) +{ + MODIFY_REG(ADCx->ICHS, ADC_ICHS_IS2_MSK, is2 << ADC_ICHS_IS2_POSS); +} + +/** + * @brief Get 2st conversion in inserted sequence + * @param ADCx ADC Instance + * @retval Channel number[0 ~ 18] + */ +__STATIC_INLINE uint32_t md_adc_get_insert_2st_conv_is2(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->ICHS, ADC_ICHS_IS2_MSK, ADC_ICHS_IS2_POSS); +} + +/** + * @brief Set 3st conversion in inserted sequence + * @param ADCx ADC Instance + * @param is3 Channel number[0 ~ 18] + * @retval None + */ +__STATIC_INLINE void md_adc_set_insert_3st_conv_is3(ADC_TypeDef *ADCx, uint32_t is3) +{ + MODIFY_REG(ADCx->ICHS, ADC_ICHS_IS3_MSK, is3 << ADC_ICHS_IS3_POSS); +} + +/** + * @brief Get 3st conversion in inserted sequence + * @param ADCx ADC Instance + * @retval Channel number[0 ~ 18] + */ +__STATIC_INLINE uint32_t md_adc_get_insert_3st_conv_is3(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->ICHS, ADC_ICHS_IS3_MSK, ADC_ICHS_IS3_POSS); +} + +/** + * @brief Set 4st conversion in inserted sequence + * @param ADCx ADC Instance + * @param is4 Channel number[0 ~ 18] + * @retval None + */ +__STATIC_INLINE void md_adc_set_insert_4st_conv_is4(ADC_TypeDef *ADCx, uint32_t is4) +{ + MODIFY_REG(ADCx->ICHS, ADC_ICHS_IS4_MSK, is4 << ADC_ICHS_IS4_POSS); +} + +/** + * @brief Get 4st conversion in inserted sequence + * @param ADCx ADC Instance + * @retval Channel number[0 ~ 18] + */ +__STATIC_INLINE uint32_t md_adc_get_insert_4st_conv_is4(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->ICHS, ADC_ICHS_IS4_MSK, ADC_ICHS_IS4_POSS); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group19 CHSL + * @{ + */ +/** + * @brief Set normal channel sequence length + * @param ADCx ADC Instance + * @param sel Value of the following: + * - 0x0: 1 conversions + * - 0x1: 2 conversions + * - 0x2: 3 conversions + * - 0x3: 4 conversions + * - 0x4: 5 conversions + * - 0x5: 6 conversions + * - 0x6: 7 conversions + * - 0x7: 8 conversions + * - 0x8: 9 conversions + * - 0x9: 10 conversions + * - 0x10: 11 conversions + * - 0x11: 12 conversions + * - 0x12: 13 conversions + * - 0x13: 14 conversions + * - 0x14: 15 conversions + * - 0x15: 16 conversions + * @retval NONE + */ +__STATIC_INLINE void md_adc_set_normal_channel_length_nsl(ADC_TypeDef *ADCx, uint32_t sel) +{ + MODIFY_REG(ADCx->CHSL, ADC_CHSL_NSL_MSK, sel << ADC_CHSL_NSL_POSS); +} + +/** + * @brief Get normal channel sequence length + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: 1 conversions + * - 0x1: 2 conversions + * - 0x2: 3 conversions + * - 0x3: 4 conversions + * - 0x4: 5 conversions + * - 0x5: 6 conversions + * - 0x6: 7 conversions + * - 0x7: 8 conversions + * - 0x8: 9 conversions + * - 0x9: 10 conversions + * - 0x10: 11 conversions + * - 0x11: 12 conversions + * - 0x12: 13 conversions + * - 0x13: 14 conversions + * - 0x14: 15 conversions + * - 0x15: 16 conversions + */ +__STATIC_INLINE uint32_t md_adc_get_normal_channel_length_nsl(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CHSL, ADC_CHSL_NSL_MSK, ADC_CHSL_NSL_POSS); +} + +/** + * @brief Set insert channel sequence length + * @param ADCx ADC Instance + * @param sel Value of the following: + * - 0x0: 1 conversions + * - 0x1: 2 conversions + * - 0x2: 3 conversions + * - 0x3: 4 conversions + * @retval NONE + */ +__STATIC_INLINE void md_adc_set_insert_channel_length_isl(ADC_TypeDef *ADCx, uint32_t sel) +{ + MODIFY_REG(ADCx->CHSL, ADC_CHSL_ISL_MSK, sel << ADC_CHSL_ISL_POSS); +} + + +/** + * @brief Get insert channel sequence length + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: 1 conversions + * - 0x1: 2 conversions + * - 0x2: 3 conversions + * - 0x3: 4 conversions + */ +__STATIC_INLINE uint32_t md_adc_get_insert_channel_length_isl(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CHSL, ADC_CHSL_ISL_MSK, ADC_CHSL_ISL_POSS); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group20 WDTH + * @{ + */ +/** + * @brief Set analog watchdog higher threshold + * @param ADCx ADC Instance + * @param val Higher threshold value + * @retval None + */ +__STATIC_INLINE void md_adc_set_higher_threshold_ht(ADC_TypeDef *ADCx, uint32_t val) +{ + MODIFY_REG(ADCx->WDTH, ADC_WDTH_HT_MSK, val << ADC_WDTH_HT_POSS); +} + +/** + * @brief Get analog watchdog higher threshold + * @param ADCx ADC Instance + * @retval Higher threshold value + */ +__STATIC_INLINE uint32_t md_adc_get_higher_threshold_ht(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->WDTH, ADC_WDTH_HT_MSK, ADC_WDTH_HT_POSS); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group21 WDTL + * @{ + */ +/** + * @brief Set analog watchdog lower threshold + * @param ADCx ADC Instance + * @param lt Lower threshold value + * @retval None + */ +__STATIC_INLINE void md_adc_set_lower_threshold_lt(ADC_TypeDef *ADCx, uint32_t lt) +{ + MODIFY_REG(ADCx->WDTL, ADC_WDTL_LT_MSK, lt << ADC_WDTL_LT_POSS); +} + +/** + * @brief Get analog watchdog lower threshold + * @param ADCx ADC Instance + * @retval Lower threshold value + */ +__STATIC_INLINE uint32_t md_adc_get_lower_threshold_lt(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->WDTL, ADC_WDTL_LT_MSK, ADC_WDTL_LT_POSS); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group22 ICHDR1 + * @{ + */ +/** + * @brief Get the conversion result from inserted channel 1 + * @param ADCx ADC Instance + * @retval Injected data + */ +__STATIC_INLINE uint32_t md_adc_get_insert_channel1_val(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->ICHDR1, ADC_ICHDR1_VAL_MSK, ADC_ICHDR1_VAL_POSS); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group23 ICHDR2 + * @{ + */ +/** + * @brief Get the conversion result from inserted channel 2 + * @param ADCx ADC Instance + * @retval Injected data + */ +__STATIC_INLINE uint32_t md_adc_get_insert_channel2_val(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->ICHDR2, ADC_ICHDR2_VAL_MSK, ADC_ICHDR2_VAL_POSS); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group24 ICHDR3 + * @{ + */ +/** + * @brief Get the conversion result from inserted channel 3 + * @param ADCx ADC Instance + * @retval Injected data + */ +__STATIC_INLINE uint32_t md_adc_get_insert_channel3_val(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->ICHDR3, ADC_ICHDR3_VAL_MSK, ADC_ICHDR3_VAL_POSS); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group25 ICHDR4 + * @{ + */ +/** + * @brief Get the conversion result from inserted channel 4 + * @param ADCx ADC Instance + * @retval Injected data + */ +__STATIC_INLINE uint32_t md_adc_get_insert_channel4_val(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->ICHDR4, ADC_ICHDR4_VAL_MSK, ADC_ICHDR4_VAL_POSS); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group26 NCHDR + * @{ + */ +/** + * @brief Get the conversion result from normal channel + * @param ADCx ADC Instance + * @retval Injected data + */ +__STATIC_INLINE uint32_t md_adc_get_normal_channel_val(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->NCHDR, ADC_NCHDR_VAL_MSK, ADC_NCHDR_VAL_POSS); +} +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group27 CCR + * @{ + */ +/** + * @brief Set ADC clock post divider value + * @param ADCx ADC Instance + * @param sel Value of the following: + * - 0x0: frequency divided by 2 + * - 0x1: frequency divided by 4 + * - 0x2: frequency divided by 8 + * - 0x3: frequency divided by 16 + * - 0x4: frequency divided by 32 + * - 0x5: frequency divided by 64 + * - 0x6: frequency divided by 128 + * - 0x7: frequency divided by 256 + * @retval NONE + */ +__STATIC_INLINE void md_adc_set_clock_post_divide_val_posdiv(ADC_TypeDef *ADCx, uint32_t sel) +{ + MODIFY_REG(ADCx->CCR, ADC_CCR_POSDIV_MSK, sel << ADC_CCR_POSDIV_POSS); +} + +/** + * @brief Get ADC clock post divider value + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: frequency divided by 2 + * - 0x1: frequency divided by 4 + * - 0x2: frequency divided by 8 + * - 0x3: frequency divided by 16 + * - 0x4: frequency divided by 32 + * - 0x5: frequency divided by 64 + * - 0x6: frequency divided by 128 + * - 0x7: frequency divided by 256 + */ +__STATIC_INLINE uint32_t md_adc_get_clock_post_divide_val_ckdiv(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CCR, ADC_CCR_POSDIV_MSK, ADC_CCR_POSDIV_POSS); +} + +/** + * @brief Set internal reference voltage enable + * @param ADCx ADC Instance + * @param sel Value of the following: + * - 0x0: Disable + * - 0x1: Enable + * @retval None + */ +__STATIC_INLINE void md_adc_set_internal_ref_voltage_vrefen(ADC_TypeDef *ADCx, uint32_t sel) +{ + MODIFY_REG(ADCx->CCR, ADC_CCR_VREFEN_MSK, sel << ADC_CCR_VREFEN_POS); +} + +/** + * @brief Check if internal reference voltage enable + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: Disable + * - 0x1: Enable + */ +__STATIC_INLINE uint32_t md_adc_is_internal_ref_voltage_enable(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CCR, ADC_CCR_VREFEN_MSK, ADC_CCR_VREFEN_POS); +} + +/** + * @brief Set buffer reference current enable + * @param ADCx ADC Instance + * @param sel Value of the following: + * - 0x0: Disable + * - 0x1: Enable + * @retval None + */ +__STATIC_INLINE void md_adc_set_buffer_reference_current_vrefen(ADC_TypeDef *ADCx, uint32_t sel) +{ + MODIFY_REG(ADCx->CCR, ADC_CCR_IREFEN_MSK, sel << ADC_CCR_IREFEN_POS); +} + +/** + * @brief Check if buffer reference current enable + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: Disable + * - 0x1: Enable + */ +__STATIC_INLINE uint32_t md_adc_get_buffer_reference_current_vrefen(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CCR, ADC_CCR_IREFEN_MSK, ADC_CCR_IREFEN_POS); +} + +/** + * @brief Set VREF mode enable + * @param ADCx ADC Instance + * @param sel Value of the following: + * - 0x0: high speed (while ADC clock more than 1M) + * - 0x1: low speed (while ADC clock less than 1M) + * @retval None + */ +__STATIC_INLINE void md_adc_set_vref_mode_pwrmodsel(ADC_TypeDef *ADCx, uint32_t sel) +{ + MODIFY_REG(ADCx->CCR, ADC_CCR_PWRMODSEL_MSK, sel << ADC_CCR_PWRMODSEL_POS); +} + +/** + * @brief Get VREF mode enable + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: high speed + * - 0x1: low speed + */ +__STATIC_INLINE uint32_t md_adc_get_vref_mode_pwrmodsel(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CCR, ADC_CCR_PWRMODSEL_MSK, ADC_CCR_PWRMODSEL_POS); +} +/** + * @brief Set forward reference voltage + * @param ADCx ADC Instance + * @param sel Value of the following: + * - 0x0: VDD + * - 0x1: VREFP + * @retval None + */ +__STATIC_INLINE void md_adc_set_forward_ref_voltage_vrpsel(ADC_TypeDef *ADCx, uint32_t sel) +{ + MODIFY_REG(ADCx->CCR, ADC_CCR_VRPSEL_MSK, sel << ADC_CCR_VRPSEL_POS); +} + +/** + * @brief Get forward reference voltage + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: VDD + * - 0x1: VREFP + */ +__STATIC_INLINE uint32_t md_adc_get_forward_ref_voltage_vrpsel(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CCR, ADC_CCR_VRPSEL_MSK, ADC_CCR_VRPSEL_POS); +} +/** + * @brief Set backward reference voltage + * @param ADCx ADC Instance + * @param sel Value of the following: + * - 0x0: VSS + * - 0x1: VREFN + * @retval None + */ +__STATIC_INLINE void md_adc_set_backward_ref_voltage_vrnsel(ADC_TypeDef *ADCx, uint32_t sel) +{ + MODIFY_REG(ADCx->CCR, ADC_CCR_VRNSEL_MSK, sel << ADC_CCR_VRNSEL_POS); +} + +/** + * @brief Get backward reference voltage + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: VSS + * - 0x1: VREFN + */ +__STATIC_INLINE uint32_t md_adc_get_backward_ref_voltage_vrnsel(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CCR, ADC_CCR_VRNSEL_MSK, ADC_CCR_VRNSEL_POS); +} + +/** + * @brief Set A/D data modified + * @param ADCx ADC Instance + * @param sel Value of the following: + * - 0x0: Disable + * - 0x1: Enable + * @retval None + */ +__STATIC_INLINE void md_adc_set_data_modified_trmen(ADC_TypeDef *ADCx, uint32_t sel) +{ + MODIFY_REG(ADCx->CCR, ADC_CCR_TRMEN_MSK, sel << ADC_CCR_TRMEN_POS); +} + +/** + * @brief Check if A/D data modified enable + * @param ADCx ADC Instance + * @retval Value of the following: + * - 0x0: Disable + * - 0x1: Enable + */ +__STATIC_INLINE uint32_t md_adc_is_data_modified_enable(ADC_TypeDef *ADCx) +{ + return READ_BITS(ADCx->CCR, ADC_CCR_TRMEN_MSK, ADC_CCR_TRMEN_POS); +} + +/** + * @} + */ +/** @defgroup MD_ADC_Public_Functions_Group1 Initialization + * @{ + */ +extern md_status_t md_adc_init(ADC_TypeDef *ADCx, md_adc_init_t *init); +extern void md_adc_struct_init(md_adc_init_t *init); +extern md_status_t md_adc_normal_channel_config(ADC_TypeDef *ADCx, md_adc_nch_conf_t *config); +extern void md_adc_normal_struct_init(md_adc_nch_conf_t *config); +extern md_status_t md_adc_insert_channel_config(ADC_TypeDef *ADCx, md_adc_ich_conf_t *config); +extern void md_adc_insert_struct_init(md_adc_ich_conf_t *config); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __MD_ADC_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_cmu.c b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_cmu.c new file mode 100644 index 0000000000..c4e7e95868 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_cmu.c @@ -0,0 +1,463 @@ +/********************************************************************************** + * + * @file md_cmu.c + * @brief CMU module driver. + * + * @date 15 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 15 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_cmu.h" +#include "md_msc.h" + +/* Private Macros ------------------------------------------------------------ */ + +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @addtogroup MD_CMU + * @{ + */ + +/* Private Variables --------------------------------------------------------- */ + +/** + * @defgroup MD_CMU_Private_Variables CMU Private Variables + * @{ + */ +uint32_t md_system_clock = 48000000U; +/** + * @} + */ + +/* Private Function ---------------------------------------------------------- */ + +/** @defgroup MD_CMU_Private_Functions CMU Private Functions + * @{ + */ + +/** + * @brief Update the current system clock. This function + * will be invoked, when system clock has changed. + * @param clock: The new clock. + * @retval None + */ + +static void md_cmu_clock_update(uint32_t clock) +{ + md_system_clock = clock; +} +/** + * @} + */ +/** @addtogroup MD_CMU_Public_Functions + * @{ + */ +/** @addtogroup MD_CMU_Public_Functions_Group1 + * @{ + */ +/** + * @brief Configure system clock using default. + * Select MD_CMU_CLOCK_HRC(48MHz) as system clock and + * enable MD_CMU_CLOCK_LRC(32000Hz). + * @retval The status of MD. + */ +md_status_t md_cmu_clock_config_default(void) +{ + uint32_t cnt = 4000U, tmp; + + md_msc_set_flash_read_wait_cycle(2); + + MD_SYSCFG_UNLOCK(); + + WRITE_REG(CMU->CFGR, 0x0); + + tmp = READ_REG(CMU->CLKENR); + /* Enable HRC48M */ + SET_BIT(tmp, CMU_CLKENR_HRC48MEN_MSK); + WRITE_REG(CMU->CLKENR, tmp); + + for (cnt = 4000; cnt; --cnt); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC48MACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC48MRDY_MSK))) && (--cnt)); + + /* Select HRC48M */ + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, MD_CMU_CLOCK_HRC48M << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != MD_CMU_CLOCK_HRC48M) + { + MD_SYSCFG_LOCK(); + return MD_ERROR; + } + + md_cmu_clock_update(48000000); + + MD_SYSCFG_LOCK(); + + return MD_OK; +} + +/** + * @brief Configure system clock using specified parameters + * @param clk: The parameter can be one of the following: + * @arg @ref MD_CMU_CLOCK_HRC 4MHz or 48MHz + * @arg @ref MD_CMU_CLOCK_LRC 32kHz + * @arg @ref MD_CMU_CLOCK_PLL 48MHz, 64MHz, 72MHz + * @arg @ref MD_CMU_CLOCK_HOSC 4MHz, 8MHz, 12MHz + * @param clock: The clock which will be set. the value depends + * on the parameter of clk. + * @retval The status of MD. + */ +md_status_t md_cmu_clock_config(md_cmu_clock_t clk, uint32_t clock) +{ + uint32_t cnt = 8000U; + + md_msc_set_flash_read_wait_cycle(2); + + MD_SYSCFG_UNLOCK(); + MODIFY_REG(CMU->CFGR, 0xFFFFFFU, 0); + + switch (clk) + { + case MD_CMU_CLOCK_HRC48M: + assert_param(clock == 48000000); + + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC48MEN_MSK); + + for (cnt = 4000; cnt; --cnt); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC48MACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC48MRDY_MSK))) && (--cnt)); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, MD_CMU_CLOCK_HRC48M << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != MD_CMU_CLOCK_HRC48M) + { + MD_SYSCFG_LOCK(); + return MD_ERROR; + } + + md_cmu_clock_update(clock); + + break; + + case MD_CMU_CLOCK_LRC: + assert_param(clock == 32000); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCRDY_MSK))) && (--cnt)); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, MD_CMU_CLOCK_LRC << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != MD_CMU_CLOCK_LRC) + { + MD_SYSCFG_LOCK(); + return MD_ERROR; + } + + md_cmu_clock_update(clock); + + break; + + case MD_CMU_CLOCK_HOSC: + assert_param(clock == 4000000 || clock == 8000000 || clock == 12000000); + + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); + + MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 4000000 - 1); + + for (cnt = 8000; cnt; --cnt); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt)); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, MD_CMU_CLOCK_HOSC << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != MD_CMU_CLOCK_HOSC) + { + MD_SYSCFG_LOCK(); + return MD_ERROR; + } + + md_cmu_clock_update(clock); + + break; + + case MD_CMU_CLOCK_PLL: + assert_param(clock == 72000000 || clock == 64000000 || clock == 48000000); + + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLLEN_MSK); + + for (cnt = 4000; cnt; --cnt); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLLACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLLRDY_MSK))) && (--cnt)); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, MD_CMU_CLOCK_PLL << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != MD_CMU_CLOCK_PLL) + { + MD_SYSCFG_LOCK(); + return MD_ERROR; + } + + md_cmu_clock_update(clock); + + break; + + case MD_CMU_CLOCK_HRC4M: + assert_param(clock == 4000000); + + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC4MEN_MSK); + + for (cnt = 4000; cnt; --cnt); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC4MACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC4MRDY_MSK))) && (--cnt)); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, MD_CMU_CLOCK_HRC4M << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != MD_CMU_CLOCK_HRC4M) + { + MD_SYSCFG_LOCK(); + return MD_ERROR; + } + + md_cmu_clock_update(clock); + + break; + + default: + break; + } + + MD_SYSCFG_LOCK(); + return MD_OK; +} + +/** + * @brief Configure PLL using specified parameters. + * @param input: The input clock type. + * @param output: The output clock which can be 48MHz/64MHz/72MHz. + * @retval None + */ +void md_cmu_pll_config(md_cmu_pll_input_t input, md_cmu_pll_output_t output) +{ + uint32_t cnt = 4000U; + + MD_SYSCFG_UNLOCK(); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == MD_CMU_CLOCK_PLL) + { + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC48MEN_MSK); + + for (cnt = 4000; cnt; --cnt); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC48MACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRC48MRDY_MSK))) && (--cnt)); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, MD_CMU_CLOCK_HRC48M << CMU_CSR_SYS_CMD_POSS); + + cnt = 4000; + + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + } + + if (input == MD_CMU_PLL_INPUT_HRC4M) + { + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC4MEN_MSK); + } + else + { + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); + + if (input == MD_CMU_PLL_INPUT_HOSC4M) + { + MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, 0); + } + else if (input == MD_CMU_PLL_INPUT_HOSC8M) + { + MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, 1); + } + else + { + + } + + cnt = 20000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt)); + } + + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLLEN_MSK); + + MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_REFS_MSK, input << CMU_PLLCFG_REFS_POSS); + MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_CLKOS_MSK, output << CMU_PLLCFG_CLKOS_POSS); + + SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); + MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 0x2 << CMU_PULMCR_MODE_POSS); + + MD_SYSCFG_LOCK(); + return; +} + +/** + * @brief Configure the bus division. + * @param bus: The type of bus: + * @arg CMU_SYS + * @arg CMU_PCLK + * @param clk_div: The value of divider. + * @retval None + */ +void md_cmu_div_config(md_cmu_bus_t bus, md_cmu_div_t clk_div) +{ + MD_SYSCFG_UNLOCK(); + + switch (bus) + { + case MD_CMU_SYS: + MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, clk_div << CMU_CFGR_SYSDIV_POSS); + break; + + case MD_CMU_PCLK: + MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLKDIV_MSK, clk_div << CMU_CFGR_PCLKDIV_POSS); + break; + + default: + break; + } + + MD_SYSCFG_LOCK(); + + return; +} + +/** + * @brief Get SYS clock + * @retval The value of SYS clock + */ +uint32_t md_cmu_get_sys_clock(void) +{ + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + + return md_system_clock >> sys_div; +} + +/** + * @brief Get APB clock. + * @retval The value of APB clock. + */ +uint32_t md_cmu_get_pclk_clock(void) +{ + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t apb_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLKDIV_MSK, CMU_CFGR_PCLKDIV_POSS); + + return (md_system_clock >> sys_div) >> apb_div; +} + +/** + * @brief Gets current system clock. + * @retval The value of system clock. + */ +uint32_t md_cmu_get_clock(void) +{ + return md_system_clock; +} +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_cmu.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_cmu.h new file mode 100644 index 0000000000..343c55757d --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_cmu.h @@ -0,0 +1,2315 @@ +/********************************************************************************** + * + * @file md_cmu.h + * @brief Header file of CMU module driver. + * + * @date 14 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 14 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + + +#ifndef __MD_CMU_H__ +#define __MD_CMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_utils.h" +#include "md_syscfg.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_CMU CMU + * @brief CMU micro driver + + * @{ + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup MD_CMU_MD_Public_Types CMU Public Types + * @{ + */ +/** + * @brief CMU state structure definition + */ +typedef enum +{ + MD_CMU_CLOCK_HRC48M = 0x1U, /**< HRC48M */ + MD_CMU_CLOCK_LRC = 0x2U, /**< LRC */ + MD_CMU_CLOCK_HOSC = 0x3U, /**< HOSC */ + MD_CMU_CLOCK_PLL = 0x4U, /**< PLL */ + MD_CMU_CLOCK_HRC4M = 0x5U, /**< HRC4M */ +} md_cmu_clock_t; + +/** + * @brief PLL output clock + */ +typedef enum +{ + MD_CMU_PLL_OUTPUT_72M = 0x0U, /**< 72MHz */ + MD_CMU_PLL_OUTPUT_64M = 0x2U, /**< 64MHz */ + MD_CMU_PLL_OUTPUT_48M = 0x3U, /**< 48MHz */ +} md_cmu_pll_output_t; + +/** + * @brief PLL referance clock + */ +typedef enum +{ + MD_CMU_PLL_INPUT_HRC4M = 0x0U, /**< HRC4M */ + MD_CMU_PLL_INPUT_HOSC4M = 0x1U, /**< HOSC4M */ + MD_CMU_PLL_INPUT_HOSC8M = 0x2U, /**< HOSC8M */ +} md_cmu_pll_input_t; + +/** + * @brief Frequency division select bit + */ +typedef enum +{ + MD_CMU_DIV_1 = 0x0U, /**< Division by 1 */ + MD_CMU_DIV_2 = 0x1U, /**< Division by 2 */ + MD_CMU_DIV_4 = 0x2U, /**< Division by 4 */ + MD_CMU_DIV_8 = 0x3U, /**< Division by 8 */ + MD_CMU_DIV_16 = 0x4U, /**< Division by 16 */ + MD_CMU_DIV_32 = 0x5U, /**< Division by 32 */ + MD_CMU_DIV_64 = 0x6U, /**< Division by 64 */ + MD_CMU_DIV_128 = 0x7U, /**< Division by 128 */ + MD_CMU_DIV_256 = 0x8U, /**< Division by 256 */ + MD_CMU_DIV_512 = 0x9U, /**< Division by 512 */ + MD_CMU_DIV_1024 = 0xAU, /**< Division by 1024 */ + MD_CMU_DIV_2048 = 0xBU, /**< Division by 2048 */ + MD_CMU_DIV_4096 = 0xCU, /**< Division by 4096 */ +} md_cmu_div_t; + +/** + * @brief Bus type + */ +typedef enum +{ + MD_CMU_SYS = 0x1U, /**< SYS bus */ + MD_CMU_PCLK = 0x2U, /**< APB bus */ +} md_cmu_bus_t; +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @defgroup MD_CMU_Public_Functions CMU Public Functions + * @{ + */ +/** @defgroup MD_CMU_Public_Functions_Group2 CSR + * @{ + */ +/** + * @brief Configure system clock. + * @param clk: Clock parameter. can be one of the following values: + * @arg @ref MD_CMU_CLOCK_HRC48M + * @arg @ref MD_CMU_CLOCK_LRC + * @arg @ref MD_CMU_CLOCK_HOSC + * @arg @ref MD_CMU_CLOCK_PLL + * @arg @ref MD_CMU_CLOCK_HRC4M + * @retval NONE + */ +__STATIC_INLINE void md_cmu_config_clock(md_cmu_clock_t clk) +{ + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, clk); +} + +/** + * @brief Get system clock. + * @retval Current system clock. Can be one of the following values: + * @arg @ref MD_CMU_CLOCK_HRC48M + * @arg @ref MD_CMU_CLOCK_LRC + * @arg @ref MD_CMU_CLOCK_HOSC + * @arg @ref MD_CMU_CLOCK_PLL + * @arg @ref MD_CMU_CLOCK_HRC4M + */ +__STATIC_INLINE uint32_t md_cmu_get_current_clock(void) +{ + return READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS); +} + +/** + * @brief Get Status of switch clock. + * @retval Status: + * - 0: Ready + * - 1: Busy + */ +__STATIC_INLINE uint32_t md_cmu_get_sys_rdyn(void) +{ + return READ_BITS(CMU->CSR, CMU_CSR_SYS_RDYN_MSK, CMU_CSR_SYS_RDYN_POS); +} + +/** + * @brief Configure system clock filter. + * @param cft: Value of the following: + * - 0x55: Select system clock filter + * - 0xAA: Bypass system clock filter + * @retval NONE + */ +__STATIC_INLINE void md_cmu_config_cft(uint32_t cft) +{ + MODIFY_REG(CMU->CSR, CMU_CSR_CFT_CMD_MSK, cft << CMU_CSR_CFT_CMD_POSS); +} + +/** + * @brief Get system clock. + * @retval Current filter clock: + * - 0: Select system clock filter + * - 1: Bypass system clock filter + */ +__STATIC_INLINE uint32_t md_cmu_get_active_filter(void) +{ + return READ_BITS(CMU->CSR, CMU_CSR_CFT_STU_MSK, CMU_CSR_CFT_STU_POS); +} + +/** + * @brief Get Status of switch filter clock. + * @retval Status: + * - 0: Ready + * - 1: Busy + */ +__STATIC_INLINE uint32_t md_cmu_get_cft_rdyn(void) +{ + return READ_BITS(CMU->CSR, CMU_CSR_CFT_RDYN_MSK, CMU_CSR_CFT_RDYN_POS); +} +/** + * @} + */ +/** @defgroup MD_CMU_Public_Functions_Group3 CFGR + * @{ + */ + +/** + * @brief Select PLLCLK to be I2S clock source + * @retval NONE + */ +__STATIC_INLINE void md_cmu_sel_i2sclk_pll(void) +{ + SET_BIT(CMU->CFGR, CMU_CFGR_I2SSW_MSK); +} + +/** + * @brief Select HOSCCLK to be I2S clock source + * @retval NONE + */ +__STATIC_INLINE void md_cmu_sel_i2sclk_hosc(void) +{ + CLEAR_BIT(CMU->CFGR, CMU_CFGR_I2SSW_MSK); +} + +/** + * @brief Gets I2S clock source + * @retval Value: + * - 0: HOSCCLK + * - 1: PLLCLK + */ +__STATIC_INLINE uint32_t md_cmu_get_i2sclk(void) +{ + return READ_BITS(CMU->CFGR, CMU_CFGR_I2SSW_MSK, CMU_CFGR_I2SSW_POS); +} + +/** + * @brief Select PLLCLK to be USB clock source + * @retval NONE + */ +__STATIC_INLINE void md_cmu_sel_usbclk_pll(void) +{ + SET_BIT(CMU->CFGR, CMU_CFGR_USBSW_MSK); +} + +/** + * @brief Select HRC48CLK to be USB clock source + * @retval NONE + */ +__STATIC_INLINE void md_cmu_sel_usbclk_hrc48(void) +{ + CLEAR_BIT(CMU->CFGR, CMU_CFGR_USBSW_MSK); +} + +/** + * @brief Gets USB clock source + * @retval Value: + * - 0: HRC48CLK + * - 1: PLLCLK + */ +__STATIC_INLINE uint32_t md_cmu_get_usbclk(void) +{ + return READ_BITS(CMU->CFGR, CMU_CFGR_USBSW_MSK, CMU_CFGR_USBSW_POS); +} + +/** + * @brief Sets SYSCLK divider. + * @param div: Value of the following: + * - 0x0: Fclk / 1 + * - 0x1: Fclk / 2 + * - 0x2: Fclk / 4 + * - 0x3: Fclk / 8 + * - 0x4: Fclk / 16 + * - 0x5: Fclk / 32 + * - 0x6: Fclk / 64 + * - 0x7: Fclk / 128 + * - 0x8: Fclk / 256 + * - 0x9: Fclk / 512 + * - 0xA: Fclk / 1024 + * - 0xB: Fclk / 2048 + * - 0xC: Fclk / 4096 + * @retval NONE + */ +__STATIC_INLINE void md_cmu_set_sysclk_div(uint32_t div) +{ + MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS); +} + +/** + * @brief Gets SYSCLK divider. + * @retval divider: Value of the following: + * - 0x0: Fclk / 1 + * - 0x1: Fclk / 2 + * - 0x2: Fclk / 4 + * - 0x3: Fclk / 8 + * - 0x4: Fclk / 16 + * - 0x5: Fclk / 32 + * - 0x6: Fclk / 64 + * - 0x7: Fclk / 128 + * - 0x8: Fclk / 256 + * - 0x9: Fclk / 512 + * - 0xA: Fclk / 1024 + * - 0xB: Fclk / 2048 + * - 0xC: Fclk / 4096 + */ +__STATIC_INLINE uint32_t md_cmu_get_sysclk_div(void) +{ + return READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); +} + +/** + * @brief Sets PCLK divider. + * @param div: Value of the following: + * - 0x0: Fclk / 1 + * - 0x1: Fclk / 2 + * - 0x2: Fclk / 4 + * - 0x3: Fclk / 8 + * - 0x4: Fclk / 16 + * - 0x5: Fclk / 32 + * - 0x6: Fclk / 64 + * - 0x7: Fclk / 128 + * - 0x8: Fclk / 256 + * - 0x9: Fclk / 512 + * - 0xA: Fclk / 1024 + * - 0xB: Fclk / 2048 + * - 0xC: Fclk / 4096 + * @retval NONE + */ +__STATIC_INLINE void md_cmu_set_pclk_div(uint32_t div) +{ + MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLKDIV_MSK, div << CMU_CFGR_PCLKDIV_POSS); +} + +/** + * @brief Gets PCLK divider. + * @retval divider: Value of the following: + * - 0x0: Fclk / 1 + * - 0x1: Fclk / 2 + * - 0x2: Fclk / 4 + * - 0x3: Fclk / 8 + * - 0x4: Fclk / 16 + * - 0x5: Fclk / 32 + * - 0x6: Fclk / 64 + * - 0x7: Fclk / 128 + * - 0x8: Fclk / 256 + * - 0x9: Fclk / 512 + * - 0xA: Fclk / 1024 + * - 0xB: Fclk / 2048 + * - 0xC: Fclk / 4096 + */ +__STATIC_INLINE uint32_t md_cmu_get_pclk_div(void) +{ + return READ_BITS(CMU->CFGR, CMU_CFGR_PCLKDIV_MSK, CMU_CFGR_PCLKDIV_POSS); +} + +/** + * @} + */ +/** @defgroup MD_CMU_Public_Functions_Group4 CLKENR + * @{ + */ +/** + * @brief Enable HOSC + * @retval NONE + */ +__STATIC_INLINE void md_cmu_enable_hosc(void) +{ + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); +} + +/** + * @brief Disable HOSC + * @retval NONE + */ +__STATIC_INLINE void md_cmu_disable_hosc(void) +{ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); +} + +/** + * @brief Gets HOSC status + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_hosc(void) +{ + return READ_BITS(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK, CMU_CLKENR_HOSCEN_POS); +} + +/** + * @brief Enable HRC48M + * @retval NONE + */ +__STATIC_INLINE void md_cmu_enable_hrc48m(void) +{ + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC48MEN_MSK); +} + +/** + * @brief Disable HRC48M + * @retval NONE + */ +__STATIC_INLINE void md_cmu_disable_hrc48m(void) +{ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HRC48MEN_MSK); +} + +/** + * @brief Gets HRC48M status + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_hrc48m(void) +{ + return READ_BITS(CMU->CLKENR, CMU_CLKENR_HRC48MEN_MSK, CMU_CLKENR_HRC48MEN_POS); +} + +/** + * @brief Enable HRC4M + * @retval NONE + */ +__STATIC_INLINE void md_cmu_enable_hrc4m(void) +{ + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC4MEN_MSK); +} + +/** + * @brief Disable HRC4M + * @retval NONE + */ +__STATIC_INLINE void md_cmu_disable_hrc4m(void) +{ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HRC4MEN_MSK); +} + +/** + * @brief Gets HRC4M status + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_hrc4m(void) +{ + return READ_BITS(CMU->CLKENR, CMU_CLKENR_HRC4MEN_MSK, CMU_CLKENR_HRC4MEN_POS); +} + +/** + * @brief Enable PLL + * @retval NONE + */ +__STATIC_INLINE void md_cmu_enable_pll(void) +{ + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLLEN_MSK); +} + +/** + * @brief Disable PLL + * @retval NONE + */ +__STATIC_INLINE void md_cmu_disable_pll(void) +{ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLLEN_MSK); +} + +/** + * @brief Gets PLL status + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_pll(void) +{ + return READ_BITS(CMU->CLKENR, CMU_CLKENR_PLLEN_MSK, CMU_CLKENR_PLLEN_POS); +} + +/** + * @brief Enable HRC48M Bypass Filter + * @retval NONE + */ +__STATIC_INLINE void md_cmu_enable_hrc48mflybps(void) +{ + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC48MFLYBPS_MSK); +} + +/** + * @brief Disable HRC48M Bypass Filter + * @retval NONE + */ +__STATIC_INLINE void md_cmu_disable_hrc48mflybps(void) +{ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HRC48MFLYBPS_MSK); +} + +/** + * @brief Gets HRC48M Bypass Filter status + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_hrc48mflybps(void) +{ + return READ_BITS(CMU->CLKENR, CMU_CLKENR_HRC48MFLYBPS_MSK, CMU_CLKENR_HRC48MFLYBPS_POS); +} + +/** + * @brief Enable I2SCK + * @retval NONE + */ +__STATIC_INLINE void md_cmu_enable_i2sck(void) +{ + SET_BIT(CMU->CLKENR, CMU_CLKENR_I2SCKEN_MSK); +} + +/** + * @brief Disable I2SCK + * @retval NONE + */ +__STATIC_INLINE void md_cmu_disable_i2sck(void) +{ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_I2SCKEN_MSK); +} + +/** + * @brief Gets I2SCK status + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_i2sck(void) +{ + return READ_BITS(CMU->CLKENR, CMU_CLKENR_I2SCKEN_MSK, CMU_CLKENR_I2SCKEN_POS); +} + +/** + * @brief Enable USBCK 48M + * @retval NONE + */ +__STATIC_INLINE void md_cmu_enable_usbck48(void) +{ + SET_BIT(CMU->CLKENR, CMU_CLKENR_USBCKEN_MSK); +} + +/** + * @brief Disable USBCK 48M + * @retval NONE + */ +__STATIC_INLINE void md_cmu_disable_usbck48(void) +{ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_USBCKEN_MSK); +} + +/** + * @brief Gets USBCK 48M status + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_usbck48(void) +{ + return READ_BITS(CMU->CLKENR, CMU_CLKENR_USBCKEN_MSK, CMU_CLKENR_USBCKEN_POS); +} + +/** + * @brief Enable HOSC32K + * @retval NONE + */ +__STATIC_INLINE void md_cmu_enable_hosc32k(void) +{ + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSC32K_MSK); +} + +/** + * @brief Disable HOSC32K + * @retval NONE + */ +__STATIC_INLINE void md_cmu_disable_hosc32k(void) +{ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HOSC32K_MSK); +} + +/** + * @brief Gets HOSC32K status + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_hosc32k(void) +{ + return READ_BITS(CMU->CLKENR, CMU_CLKENR_HOSC32K_MSK, CMU_CLKENR_HOSC32K_POS); +} + +/** + * @brief Enable HOSCBPS + * @retval NONE + */ +__STATIC_INLINE void md_cmu_enable_hoscbps(void) +{ + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCBPS_MSK); +} + +/** + * @brief Disable HOSCBPS + * @retval NONE + */ +__STATIC_INLINE void md_cmu_disable_hoscbps(void) +{ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HOSCBPS_MSK); +} + +/** + * @brief Gets HOSCBPS status + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_hoscbps(void) +{ + return READ_BITS(CMU->CLKENR, CMU_CLKENR_HOSCBPS_MSK, CMU_CLKENR_HOSCBPS_POS); +} + +/** + * @brief Enable HOSCFLYBPS + * @retval NONE + */ +__STATIC_INLINE void md_cmu_enable_hoscflybps(void) +{ + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCFLYBPS_MSK); +} + +/** + * @brief Disable HOSCFLYBPS + * @retval NONE + */ +__STATIC_INLINE void md_cmu_disable_hoscflybps(void) +{ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HOSCFLYBPS_MSK); +} + +/** + * @brief Gets HOSCFLYBPS status + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_hoscflybps(void) +{ + return READ_BITS(CMU->CLKENR, CMU_CLKENR_HOSCFLYBPS_MSK, CMU_CLKENR_HOSCFLYBPS_POS); +} + +/** + * @} + */ +/** @defgroup MD_CMU_Public_Functions_Group5 CLKSR + * @{ + */ +/** + * @brief Check the HOSC is active. + * @retval Status: + * - 0: Not active + * - 1: Active + */ +__STATIC_INLINE uint32_t md_cmu_is_active_state_hosc(void) +{ + return READ_BITS(CMU->CLKSR, CMU_CLKSR_HOSCACT_MSK, CMU_CLKSR_HOSCACT_POS); +} + +/** + * @brief Check the PLL is active. + * @retval Status: + * - 0: Not active + * - 1: Active + */ +__STATIC_INLINE uint32_t md_cmu_is_active_state_pll(void) +{ + return READ_BITS(CMU->CLKSR, CMU_CLKSR_PLLACT_MSK, CMU_CLKSR_PLLACT_POS); +} + +/** + * @brief Check the HRC4M is active. + * @retval Status: + * - 0: Not active + * - 1: Active + */ +__STATIC_INLINE uint32_t md_cmu_is_active_state_hrc4m(void) +{ + return READ_BITS(CMU->CLKSR, CMU_CLKSR_HRC4MACT_MSK, CMU_CLKSR_HRC4MACT_POS); +} + +/** + * @brief Check the HRC48M is active. + * @retval Status: + * - 0: Not active + * - 1: Active + */ +__STATIC_INLINE uint32_t md_cmu_is_active_state_hrc48m(void) +{ + return READ_BITS(CMU->CLKSR, CMU_CLKSR_HRC48MACT_MSK, CMU_CLKSR_HRC48MACT_POS); +} + +/** + * @brief Check the HOSC is stable. + * @retval Status: + * - 0: Not stable + * - 1: Stable + */ +__STATIC_INLINE uint32_t md_cmu_is_stable_state_hosc(void) +{ + return READ_BITS(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK, CMU_CLKSR_HOSCRDY_POS); +} + +/** + * @brief Check the HRC4MRDY is stable. + * @retval Status: + * - 0: Not stable + * - 1: Stable + */ +__STATIC_INLINE uint32_t md_cmu_is_stable_state_hrc4mrdy(void) +{ + return READ_BITS(CMU->CLKSR, CMU_CLKSR_HRC4MRDY_MSK, CMU_CLKSR_HRC4MRDY_POS); +} + +/** + * @brief Check the HRC48MRDY is stable. + * @retval Status: + * - 0: Not stable + * - 1: Stable + */ +__STATIC_INLINE uint32_t md_cmu_is_stable_state_hrc48mrdy(void) +{ + return READ_BITS(CMU->CLKSR, CMU_CLKSR_HRC48MRDY_MSK, CMU_CLKSR_HRC48MRDY_POS); +} + +/** + * @brief Check the LRCRDY is stable. + * @retval Status: + * - 0: Not stable + * - 1: Stable + */ +__STATIC_INLINE uint32_t md_cmu_is_stable_state_lrcrdy(void) +{ + return READ_BITS(CMU->CLKSR, CMU_CLKSR_LRCRDY_MSK, CMU_CLKSR_LRCRDY_POS); +} + +/** + * @brief Check the PLLRDY is stable. + * @retval Status: + * - 0: Not stable + * - 1: Stable + */ +__STATIC_INLINE uint32_t md_cmu_is_stable_state_pllrdy(void) +{ + return READ_BITS(CMU->CLKSR, CMU_CLKSR_PLLRDY_MSK, CMU_CLKSR_PLLRDY_POS); +} + +/** + * @} + */ +/** @defgroup MD_CMU_Public_Functions_Group6 HOSCCFG + * @{ + */ +/** + * @brief Sets HOSC frequence. + * @param clk: The value of following: + * - 0x0: 4MHz + * - 0x1: 8MHz + * - 0x2: 12MHz + * - 0x3: 16MHz + * - 0x4: 20MHz + * - 0x5: 24MHz + * @retval None + */ +__STATIC_INLINE void md_cmu_set_hosc_freq(uint32_t clk) +{ + MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clk << CMU_HOSCCFG_FREQ_POSS); +} + +/** + * @brief Gets HOSC frequence. + * @retval clk: The value of following: + * - 0x0: 4MHz + * - 0x1: 8MHz + * - 0x2: 12MHz + * - 0x3: 16MHz + * - 0x4: 20MHz + * - 0x5: 24MHz + */ +__STATIC_INLINE uint32_t md_cmu_get_hosc_freq(void) +{ + return READ_BITS(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, CMU_HOSCCFG_FREQ_POSS); +} +/** + * @} + */ +/** @defgroup MD_CMU_Public_Functions_Group7 HOSMCR + * @{ + */ +/** + * @brief Enable HOSC safe. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_hosc_safe(void) +{ + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); +} + +/** + * @brief Disable HOSC safe. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_hosc_safe(void) +{ + CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); +} + +/** + * @brief Check HOSC safe is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_hosc_safe(void) +{ + return READ_BITS(CMU->HOSMCR, CMU_HOSMCR_EN_MSK, CMU_HOSMCR_EN_POS); +} + +/** + * @brief Gets HOSC stop state. + * @retval Status: + * - 0: HOSC run + * - 1: HOSC stop + */ +__STATIC_INLINE uint32_t md_cmu_get_hosc_stop_state(void) +{ + return READ_BITS(CMU->HOSMCR, CMU_HOSMCR_FLAG_MSK, CMU_HOSMCR_FLAG_POS); +} + +/** + * @brief Sets HOSC frequence region + * @param clk: The value of following: + * - 0: 1-2MHz + * - 1: 2-4MHz + * - 2: 4-8MHz + * - 3: 8-16MHz + * - 4: 16-24MHz + * @retval None + */ +__STATIC_INLINE void md_cmu_set_hosc_freq_region(uint32_t clk) +{ + MODIFY_REG(CMU->HOSMCR, CMU_HOSMCR_FRQS_MSK, clk << CMU_HOSMCR_FRQS_POSS); +} + +/** + * @brief Gets HOSC frequence region + * @retval The value of following: + * - 0: 1-2MHz + * - 1: 2-4MHz + * - 2: 4-8MHz + * - 3: 8-16MHz + * - 4: 16-24MHz + */ +__STATIC_INLINE uint32_t md_cmu_get_hosc_freq_region(void) +{ + return READ_BITS(CMU->HOSMCR, CMU_HOSMCR_FRQS_MSK, CMU_HOSMCR_FRQS_POSS); +} + +/** + * @brief Enable STR interrupt + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_hosc_str_interrupt(void) +{ + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIE_MSK); +} + +/** + * @brief Disable STR interrupt + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_hosc_str_interrupt(void) +{ + CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIE_MSK); +} + +/** + * @brief Check STR interrupt is enable. + * @retval Status. + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_hosc_str_interrupt(void) +{ + return READ_BITS(CMU->HOSMCR, CMU_HOSMCR_STRIE_MSK, CMU_HOSMCR_STRIE_POS); +} + +/** + * @brief Enable STP interrupt + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_hosc_stp_interrupt(void) +{ + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); +} + +/** + * @brief Disable STP interrupt + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_hosc_stp_interrupt(void) +{ + CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); +} + +/** + * @brief Check STP interrupt is enable. + * @retval Status. + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_hosc_stp_interrupt(void) +{ + return READ_BITS(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK, CMU_HOSMCR_STPIE_POS); +} + +/** + * @brief Gets STR flag state + * @retval State + */ +__STATIC_INLINE uint32_t md_cmu_is_active_flag_hosc_str(void) +{ + return READ_BITS(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK, CMU_HOSMCR_STRIF_POS); +} + +/** + * @brief Clear STR flag + * @retval None + */ +__STATIC_INLINE void md_cmu_clear_flag_hosc_str(void) +{ + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK); +} + +/** + * @brief Gets STP flag state + * @retval State + */ +__STATIC_INLINE uint32_t md_cmu_is_active_flag_hosc_stp(void) +{ + return READ_BITS(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK, CMU_HOSMCR_STPIF_POS); +} + +/** + * @brief Clear STP flag + * @retval None + */ +__STATIC_INLINE void md_cmu_clear_flag_hosc_stp(void) +{ + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); +} + +/** + * @brief Enable HOSC NMI interrupt + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_hosc_nmi_interrupt(void) +{ + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_NMIE_MSK); +} + +/** + * @brief Disable HOSC NMI interrupt + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_hosc_nmi_interrupt(void) +{ + CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_NMIE_MSK); +} + +/** + * @brief Check HOSC NMI interrupt is enable. + * @retval Status. + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_hosc_nmi_interrupt(void) +{ + return READ_BITS(CMU->HOSMCR, CMU_HOSMCR_NMIE_MSK, CMU_HOSMCR_NMIE_POS); +} + +/** + * @} + */ +/** @defgroup MD_CMU_Public_Functions_Group8 PULMCR + * @{ + */ +/** + * @brief Enable PLL unlock management. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_pll_unlock_manage(void) +{ + SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); +} + +/** + * @brief Disable PLL unlock management. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_pll_unlock_manage(void) +{ + CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); +} + +/** + * @brief Check PLL unlock management is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_pll_unlock_manage(void) +{ + return READ_BITS(CMU->PULMCR, CMU_PULMCR_EN_MSK, CMU_PULMCR_EN_POS); +} + +/** + * @brief Gets current selected clock. + * @retval Status: + * - 0: PLL + * - 1: HRC + */ +__STATIC_INLINE uint32_t md_cmu_get_current_sel_clock(void) +{ + return READ_BITS(CMU->PULMCR, CMU_PULMCR_CLKS_MSK, CMU_PULMCR_CLKS_POS); +} + +/** + * @brief Select mode after PLL unlock + * @param sel : Value of following: + * - 0: No operation + * - 1: Switch to HRC + * - 2: Switch to HRC, and switch back to PLL when PLL re-lock + * @retval None + */ +__STATIC_INLINE void md_cmu_set_pll_unlock_mode(uint32_t sel) +{ + MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, sel << CMU_PULMCR_MODE_POSS); +} + +/** + * @brief Gets high clock output type + * @retval Value of following: + * - 0: No operation + * - 1: Switch to HRC + * - 2: Switch to HRC, and switch back to PLL when PLL re-lock + */ +__STATIC_INLINE uint32_t md_cmu_get_pll_unlock_mode(void) +{ + return READ_BITS(CMU->PULMCR, CMU_PULMCR_MODE_MSK, CMU_PULMCR_MODE_POSS); +} + +/** + * @brief Enable PLL lock interrupt. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_pll_lock_interrupt(void) +{ + SET_BIT(CMU->PULMCR, CMU_PULMCR_LCKIE_MSK); +} + +/** + * @brief Disable PLL lock interrupt. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_pll_lock_interrupt(void) +{ + CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_LCKIE_MSK); +} + +/** + * @brief Check PLL lock interrupt is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_pll_lock_interrupt(void) +{ + return READ_BITS(CMU->PULMCR, CMU_PULMCR_LCKIE_MSK, CMU_PULMCR_LCKIE_POS); +} + +/** + * @brief Enable PLL unlock interrupt. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_pll_unlock_interrupt(void) +{ + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); +} + +/** + * @brief Disable PLL unlock interrupt. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_pll_unlock_interrupt(void) +{ + CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); +} + +/** + * @brief Check PLL unlock interrupt is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_pll_unlock_interrupt(void) +{ + return READ_BITS(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK, CMU_PULMCR_ULKIE_POS); +} + +/** + * @brief Clear PLL lock flag. + * @retval None + */ +__STATIC_INLINE void md_cmu_clear_flag_pll_lock(void) +{ + SET_BIT(CMU->PULMCR, CMU_PULMCR_LCKIF_MSK); +} + +/** + * @brief Get PLL lock flag. + * @retval Status: + * - 0: Flag is clear + * - 1: PLL lock + */ +__STATIC_INLINE uint32_t md_cmu_is_active_flag_pll_lock(void) +{ + return READ_BITS(CMU->PULMCR, CMU_PULMCR_LCKIF_MSK, CMU_PULMCR_LCKIF_POS); +} + +/** + * @brief Clear PLL unlock flag. + * @retval None + */ +__STATIC_INLINE void md_cmu_clear_flag_pll_unlock(void) +{ + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); +} + +/** + * @brief Get PLL unlock flag. + * @retval Status: + * - 0: Flag is clear + * - 1: PLL unlock + */ +__STATIC_INLINE uint32_t md_cmu_is_active_flag_pll_unlock(void) +{ + return READ_BITS(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK, CMU_PULMCR_ULKIF_POS); +} + +/** + * @brief Enable PLL NMI interrupt + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_pll_nmi_interrupt(void) +{ + SET_BIT(CMU->PULMCR, CMU_PULMCR_NMIE_MSK); +} + +/** + * @brief Disable PLL NMI interrupt + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_pll_nmi_it(void) +{ + CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_NMIE_MSK); +} + +/** + * @brief Check PLL NMI interrupt is enable. + * @retval Status. + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_pll_nmi_it(void) +{ + return READ_BITS(CMU->PULMCR, CMU_PULMCR_NMIE_MSK, CMU_PULMCR_NMIE_POS); +} + +/** + * @} + */ +/** @defgroup MD_CMU_Public_Functions_Group9 CLKOCR + * @{ + */ +/** + * @brief Enable HSC output. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_hsco(void) +{ + SET_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); +} + +/** + * @brief Disable HSC output. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_hsco(void) +{ + CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); +} + +/** + * @brief Check HSC output is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_hsco(void) +{ + return READ_BITS(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK, CMU_CLKOCR_HSCOEN_POS); +} + +/** + * @brief Sets high clock output type + * @param sel : Value of following: + * - 0: HOSC + * - 1: HOSM + * - 2: HRC4M + * - 3: LRC + * - 4: SYSCLK + * - 5: HOSC32K + * - 6: HRC48M + * - 7: PLL + * @retval None + */ +__STATIC_INLINE void md_cmu_set_hsco_type(uint32_t sel) +{ + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCOS_MSK, sel << CMU_CLKOCR_HSCOS_POSS); +} + +/** + * @brief Gets high clock output type + * @retval Value of following: + * - 0: HOSC + * - 1: HOSM + * - 2: HRC4M + * - 3: LRC + * - 4: SYSCLK + * - 5: HOSC32K + * - 6: HRC48M + * - 7: PLL + */ +__STATIC_INLINE uint32_t md_cmu_get_hsco_type(void) +{ + return READ_BITS(CMU->CLKOCR, CMU_CLKOCR_HSCOS_MSK, CMU_CLKOCR_HSCOS_POSS); +} + +/** + * @brief Sets high clock output divider + * @param div: Value of following: + * - 0: HSC / 1 + * - 1: HSC / 2 + * - 2: HSC / 4 + * - 3: HSC / 8 + * - 4: HSC / 16 + * - 5: HSC / 32 + * - 6: HSC / 64 + * - 7: HSC / 128 + * @retval None + */ +__STATIC_INLINE void md_cmu_set_hsco_div(uint32_t div) +{ + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCODIV_MSK, div << CMU_CLKOCR_HSCODIV_POSS); +} + +/** + * @brief Gets high clock output divider + * @retval Value of following: + * - 0: HSC / 1 + * - 1: HSC / 2 + * - 2: HSC / 4 + * - 3: HSC / 8 + * - 4: HSC / 16 + * - 5: HSC / 32 + * - 6: HSC / 64 + * - 7: HSC / 128 + */ +__STATIC_INLINE uint32_t md_cmu_get_hsco_div(void) +{ + return READ_BITS(CMU->CLKOCR, CMU_CLKOCR_HSCODIV_MSK, CMU_CLKOCR_HSCODIV_POSS); +} + +/** + * @brief Enable LSC output. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_lsco(void) +{ + SET_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); +} + +/** + * @brief Disable LSC output. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_lsco(void) +{ + CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); +} + +/** + * @brief Check LSC output is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_lsco(void) +{ + return READ_BITS(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK, CMU_CLKOCR_LSCOEN_POS); +} + +/** + * @brief Sets low clock output type + * @param sel : Value of following: + * - 0: BUZZ + * - 1: LRC + * @retval None + */ +__STATIC_INLINE void md_cmu_set_lsco_type(uint32_t sel) +{ + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_LSCOS_MSK, sel << CMU_CLKOCR_LSCOS_POSS); +} + +/** + * @brief Gets low clock output type + * @retval Value of following: + * - 0: BUZZ + * - 1: LRC + */ +__STATIC_INLINE uint32_t md_cmu_get_lsco_type(void) +{ + return READ_BITS(CMU->CLKOCR, CMU_CLKOCR_LSCOS_MSK, CMU_CLKOCR_LSCOS_POSS); +} +/** + * @} + */ +/** @defgroup MD_CMU_Public_Functions_Group10 BUZZCR + * @{ + */ +/** + * @brief Enable BUZZ output. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_buzz(void) +{ + SET_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); +} + +/** + * @brief Disable BUZZ output. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_buzz(void) +{ + CLEAR_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); +} + +/** + * @brief Check BUZZ output is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_buzz(void) +{ + return READ_BITS(CMU->BUZZCR, CMU_BUZZCR_EN_MSK, CMU_BUZZCR_EN_POS); +} + +/** + * @brief Sets BUZZ divider + * @param div: Value of following: + * - 0: Freq / 2 + * - 1: Freq / 4 + * - 2: Freq / 8 + * - 3: Freq / 16 + * - 4: Freq / 32 + * - 5: Freq / 64 + * - 6: Freq / 128 + * - 7: Freq / 256 + * @retval None + */ +__STATIC_INLINE void md_cmu_set_buzz_div(uint32_t div) +{ + MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DIV_MSK, div << CMU_BUZZCR_DIV_POSS); +} + +/** + * @brief Gets BUZZ divider + * @retval Value of following: + * - 0: Freq / 2 + * - 1: Freq / 4 + * - 2: Freq / 8 + * - 3: Freq / 16 + * - 4: Freq / 32 + * - 5: Freq / 64 + * - 6: Freq / 128 + * - 7: Freq / 256 + */ +__STATIC_INLINE uint32_t md_cmu_get_buzz_div(void) +{ + return READ_BITS(CMU->BUZZCR, CMU_BUZZCR_DIV_MSK, CMU_BUZZCR_DIV_POSS); +} + +/** + * @brief Sets BUZZ data + * @param data: Region is from 0x00 to 0xFFFF + * @retval None + */ +__STATIC_INLINE void md_cmu_set_buzz_data(uint32_t data) +{ + MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DAT_MSK, data << CMU_BUZZCR_DAT_POSS); +} + +/** + * @brief Gets BUZZ data + * @retval BUZZ data + */ +__STATIC_INLINE uint32_t md_cmu_get_buzz_data(uint32_t data) +{ + return READ_BITS(CMU->BUZZCR, CMU_BUZZCR_DAT_MSK, CMU_BUZZCR_DAT_POSS); +} +/** + * @} + */ +/** @defgroup MD_CMU_Public_Functions_Group11 AHBENR + * @{ + */ +/** + * @brief Enable GPIO peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_gpio(void) +{ + SET_BIT(CMU->AHBENR, CMU_AHBENR_GPIOEN_MSK); +} + +/** + * @brief Disable GPIO peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_gpio(void) +{ + CLEAR_BIT(CMU->AHBENR, CMU_AHBENR_GPIOEN_MSK); +} + +/** + * @brief Check GPIO peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_gpio(void) +{ + return READ_BITS(CMU->AHBENR, CMU_AHBENR_GPIOEN_MSK, CMU_AHBENR_GPIOEN_POS); +} + +/** + * @brief Enable CRC peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_crc(void) +{ + SET_BIT(CMU->AHBENR, CMU_AHBENR_CRCEN_MSK); +} + +/** + * @brief Disable CRC peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_crc(void) +{ + CLEAR_BIT(CMU->AHBENR, CMU_AHBENR_CRCEN_MSK); +} + +/** + * @brief Check CRC peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_crc(void) +{ + return READ_BITS(CMU->AHBENR, CMU_AHBENR_CRCEN_MSK, CMU_AHBENR_CRCEN_POS); +} + +/** + * @brief Enable DMA peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_dma(void) +{ + SET_BIT(CMU->AHBENR, CMU_AHBENR_DMAEN_MSK); +} + +/** + * @brief Disable DMA peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_dma(void) +{ + CLEAR_BIT(CMU->AHBENR, CMU_AHBENR_DMAEN_MSK); +} + +/** + * @brief Check DMA peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_dma(void) +{ + return READ_BITS(CMU->AHBENR, CMU_AHBENR_DMAEN_MSK, CMU_AHBENR_DMAEN_POS); +} + +/** + * @brief Enable PIS peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_pis(void) +{ + SET_BIT(CMU->AHBENR, CMU_AHBENR_PISEN_MSK); +} + +/** + * @brief Disable PIS peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_pis(void) +{ + CLEAR_BIT(CMU->AHBENR, CMU_AHBENR_PISEN_MSK); +} + +/** + * @brief Check PIS peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_pis(void) +{ + return READ_BITS(CMU->AHBENR, CMU_AHBENR_PISEN_MSK, CMU_AHBENR_PISEN_POS); +} + +/** + * @brief Enable USB peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_usb(void) +{ + SET_BIT(CMU->AHBENR, CMU_AHBENR_USBEN_MSK); +} + +/** + * @brief Disable USB peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_usb(void) +{ + CLEAR_BIT(CMU->AHBENR, CMU_AHBENR_USBEN_MSK); +} + +/** + * @brief Check USB peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_usb(void) +{ + return READ_BITS(CMU->AHBENR, CMU_AHBENR_USBEN_MSK, CMU_AHBENR_USBEN_POS); +} + +/** + * @brief Enable CSU peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_csu(void) +{ + SET_BIT(CMU->AHBENR, CMU_AHBENR_CSUEN_MSK); +} + +/** + * @brief Disable CSU peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_csu(void) +{ + CLEAR_BIT(CMU->AHBENR, CMU_AHBENR_CSUEN_MSK); +} + +/** + * @brief Check CSU peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_csu(void) +{ + return READ_BITS(CMU->AHBENR, CMU_AHBENR_CSUEN_MSK, CMU_AHBENR_CSUEN_POS); +} + +/** + * @} + */ +/** @defgroup MD_CMU_Public_Functions_Group12 APBENR + * @{ + */ +/** + * @brief Enable AD16C4T0 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_ad16c4t0(void) +{ + SET_BIT(CMU->APBENR, CMU_APBENR_AD16C4T0EN_MSK); +} + +/** + * @brief Disable AD16C4T0 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_ad16c4t0(void) +{ + CLEAR_BIT(CMU->APBENR, CMU_APBENR_AD16C4T0EN_MSK); +} + +/** + * @brief Check AD16C4T0 peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_ad16c4t0(void) +{ + return READ_BITS(CMU->APBENR, CMU_APBENR_AD16C4T0EN_MSK, CMU_APBENR_AD16C4T0EN_POS); +} + +/** + * @brief Enable BS16T0 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_bs16t0(void) +{ + SET_BIT(CMU->APBENR, CMU_APBENR_BS16T0EN_MSK); +} + +/** + * @brief Disable BS16T0 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_bs16t0(void) +{ + CLEAR_BIT(CMU->APBENR, CMU_APBENR_BS16T0EN_MSK); +} + +/** + * @brief Check BS16T0 peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_bs16t0(void) +{ + return READ_BITS(CMU->APBENR, CMU_APBENR_BS16T0EN_MSK, CMU_APBENR_BS16T0EN_POS); +} + +/** + * @brief Enable GP16C4T0 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_gp16c4t0(void) +{ + SET_BIT(CMU->APBENR, CMU_APBENR_GP16C4T0EN_MSK); +} + +/** + * @brief Disable GP16C4T0 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_gp16c4t0(void) +{ + CLEAR_BIT(CMU->APBENR, CMU_APBENR_GP16C4T0EN_MSK); +} + +/** + * @brief Check GP16C4T0 peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_gp16c4t0(void) +{ + return READ_BITS(CMU->APBENR, CMU_APBENR_GP16C4T0EN_MSK, CMU_APBENR_GP16C4T0EN_POS); +} + +/** + * @brief Enable GP16C4T1 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_gp16c4t1(void) +{ + SET_BIT(CMU->APBENR, CMU_APBENR_GP16C4T1EN_MSK); +} + +/** + * @brief Disable GP16C4T1 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_gp16c4t1(void) +{ + CLEAR_BIT(CMU->APBENR, CMU_APBENR_GP16C4T1EN_MSK); +} + +/** + * @brief Check GP16C4T1 peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_gp16c4t1(void) +{ + return READ_BITS(CMU->APBENR, CMU_APBENR_GP16C4T1EN_MSK, CMU_APBENR_GP16C4T1EN_POS); +} + +/** + * @brief Enable GP16C4T2 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_gp16c4t2(void) +{ + SET_BIT(CMU->APBENR, CMU_APBENR_GP16C4T2EN_MSK); +} + +/** + * @brief Disable GP16C4T2 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_gp16c4t2(void) +{ + CLEAR_BIT(CMU->APBENR, CMU_APBENR_GP16C4T2EN_MSK); +} + +/** + * @brief Check GP16C4T2 peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_gp16c4t2(void) +{ + return READ_BITS(CMU->APBENR, CMU_APBENR_GP16C4T2EN_MSK, CMU_APBENR_GP16C4T2EN_POS); +} + +/** + * @brief Enable EUART0 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_euart0(void) +{ + SET_BIT(CMU->APBENR, CMU_APBENR_EUART0EN_MSK); +} + +/** + * @brief Disable EUART0 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_euart0(void) +{ + CLEAR_BIT(CMU->APBENR, CMU_APBENR_EUART0EN_MSK); +} + +/** + * @brief Check EUART0 peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_euart0(void) +{ + return READ_BITS(CMU->APBENR, CMU_APBENR_EUART0EN_MSK, CMU_APBENR_EUART0EN_POS); +} + +/** + * @brief Enable EUART1 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_euart1(void) +{ + SET_BIT(CMU->APBENR, CMU_APBENR_EUART1EN_MSK); +} + +/** + * @brief Disable EUART1 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_euart1(void) +{ + CLEAR_BIT(CMU->APBENR, CMU_APBENR_EUART1EN_MSK); +} + +/** + * @brief Check EUART1 peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_euart1(void) +{ + return READ_BITS(CMU->APBENR, CMU_APBENR_EUART1EN_MSK, CMU_APBENR_EUART1EN_POS); +} + +/** + * @brief Enable CUART0 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_cuart0(void) +{ + SET_BIT(CMU->APBENR, CMU_APBENR_CUART0EN_MSK); +} + +/** + * @brief Disable CUART0 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_cuart0(void) +{ + CLEAR_BIT(CMU->APBENR, CMU_APBENR_CUART0EN_MSK); +} + +/** + * @brief Check CUART0 peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_cuart0(void) +{ + return READ_BITS(CMU->APBENR, CMU_APBENR_CUART0EN_MSK, CMU_APBENR_CUART0EN_POS); +} + +/** + * @brief Enable CUART1 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_cuart1(void) +{ + SET_BIT(CMU->APBENR, CMU_APBENR_CUART1EN_MSK); +} + +/** + * @brief Disable CUART1 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_cuart1(void) +{ + CLEAR_BIT(CMU->APBENR, CMU_APBENR_CUART1EN_MSK); +} + +/** + * @brief Check CUART1 peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_cuart1(void) +{ + return READ_BITS(CMU->APBENR, CMU_APBENR_CUART1EN_MSK, CMU_APBENR_CUART1EN_POS); +} + +/** + * @brief Enable CUART2 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_cuart2(void) +{ + SET_BIT(CMU->APBENR, CMU_APBENR_CUART2EN_MSK); +} + +/** + * @brief Disable CUART2 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_cuart2(void) +{ + CLEAR_BIT(CMU->APBENR, CMU_APBENR_CUART2EN_MSK); +} + +/** + * @brief Check CUART2 peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_cuart2(void) +{ + return READ_BITS(CMU->APBENR, CMU_APBENR_CUART2EN_MSK, CMU_APBENR_CUART2EN_POS); +} + +/** + * @brief Enable SPI0 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_spi0(void) +{ + SET_BIT(CMU->APBENR, CMU_APBENR_SPI0EN_MSK); +} + +/** + * @brief Disable SPI0 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_spi0(void) +{ + CLEAR_BIT(CMU->APBENR, CMU_APBENR_SPI0EN_MSK); +} + +/** + * @brief Check SPI0 peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_spi0(void) +{ + return READ_BITS(CMU->APBENR, CMU_APBENR_SPI0EN_MSK, CMU_APBENR_SPI0EN_POS); +} + +/** + * @brief Enable SPI1 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_spi1(void) +{ + SET_BIT(CMU->APBENR, CMU_APBENR_SPI1EN_MSK); +} + +/** + * @brief Disable SPI1 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_spi1(void) +{ + CLEAR_BIT(CMU->APBENR, CMU_APBENR_SPI1EN_MSK); +} + +/** + * @brief Check SPI1 peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_spi1(void) +{ + return READ_BITS(CMU->APBENR, CMU_APBENR_SPI1EN_MSK, CMU_APBENR_SPI1EN_POS); +} + +/** + * @brief Enable I2C0 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_i2c0(void) +{ + SET_BIT(CMU->APBENR, CMU_APBENR_I2C0EN_MSK); +} + +/** + * @brief Disable I2C0 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_i2c0(void) +{ + CLEAR_BIT(CMU->APBENR, CMU_APBENR_I2C0EN_MSK); +} + +/** + * @brief Check I2C0 peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_i2c0(void) +{ + return READ_BITS(CMU->APBENR, CMU_APBENR_I2C0EN_MSK, CMU_APBENR_I2C0EN_POS); +} + +/** + * @brief Enable I2C1 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_i2c1(void) +{ + SET_BIT(CMU->APBENR, CMU_APBENR_I2C1EN_MSK); +} + +/** + * @brief Disable I2C1 peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_i2c1(void) +{ + CLEAR_BIT(CMU->APBENR, CMU_APBENR_I2C1EN_MSK); +} + +/** + * @brief Check I2C1 peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_i2c1(void) +{ + return READ_BITS(CMU->APBENR, CMU_APBENR_I2C1EN_MSK, CMU_APBENR_I2C1EN_POS); +} + +/** + * @brief Enable WWDT peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_wwdt(void) +{ + SET_BIT(CMU->APBENR, CMU_APBENR_WWDTEN_MSK); +} + +/** + * @brief Disable WWDT peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_wwdt(void) +{ + CLEAR_BIT(CMU->APBENR, CMU_APBENR_WWDTEN_MSK); +} + +/** + * @brief Check WWDT peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_wwdt(void) +{ + return READ_BITS(CMU->APBENR, CMU_APBENR_WWDTEN_MSK, CMU_APBENR_WWDTEN_POS); +} + +/** + * @brief Enable IWDT peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_iwdt(void) +{ + SET_BIT(CMU->APBENR, CMU_APBENR_IWDTEN_MSK); +} + +/** + * @brief Disable IWDT peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_iwdt(void) +{ + CLEAR_BIT(CMU->APBENR, CMU_APBENR_IWDTEN_MSK); +} + +/** + * @brief Check IWDT peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_iwdt(void) +{ + return READ_BITS(CMU->APBENR, CMU_APBENR_IWDTEN_MSK, CMU_APBENR_IWDTEN_POS); +} + +/** + * @brief Enable DBGC peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_dbgc(void) +{ + SET_BIT(CMU->APBENR, CMU_APBENR_DBGCEN_MSK); +} + +/** + * @brief Disable DBGC peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_dbgc(void) +{ + CLEAR_BIT(CMU->APBENR, CMU_APBENR_DBGCEN_MSK); +} + +/** + * @brief Check DBGC peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_dbgc(void) +{ + return READ_BITS(CMU->APBENR, CMU_APBENR_DBGCEN_MSK, CMU_APBENR_DBGCEN_POS); +} + +/** + * @brief Enable ADC peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_adc(void) +{ + SET_BIT(CMU->APBENR, CMU_APBENR_ADCEN_MSK); +} + +/** + * @brief Disable ADC peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_adc(void) +{ + CLEAR_BIT(CMU->APBENR, CMU_APBENR_ADCEN_MSK); +} + +/** + * @brief Check ADC peripheral is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_perh_adc(void) +{ + return READ_BITS(CMU->APBENR, CMU_APBENR_ADCEN_MSK, CMU_APBENR_ADCEN_POS); +} + +/** + * @brief Enable ALL peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_perh_all(void) +{ + WRITE_REG(CMU->AHBENR, 0xFFFFFFFF); + WRITE_REG(CMU->APBENR, 0xFFFFFFFF); +} + +/** + * @brief Disable ALL peripheral. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_perh_all(void) +{ + WRITE_REG(CMU->AHBENR, 0x0); + WRITE_REG(CMU->APBENR, 0x0); +} +/** + * @} + */ +/** @defgroup MD_CMU_Public_Functions_Group13 LPENR + * @{ + */ + +/** + * @brief Enable PLL low power mode. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_lp_pll(void) +{ + SET_BIT(CMU->LPENR, CMU_LPENR_PLLEN_MSK); +} + +/** + * @brief Disable PLL low power mode. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_lp_pll(void) +{ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_PLLEN_MSK); +} + +/** + * @brief Check PLL low power mode is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_lp_pll(void) +{ + return READ_BITS(CMU->LPENR, CMU_LPENR_PLLEN_MSK, CMU_LPENR_PLLEN_POS); +} + +/** + * @brief Enable HRC4M low power mode. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_lp_hrc4m(void) +{ + SET_BIT(CMU->LPENR, CMU_LPENR_HRC4MEN_MSK); +} + +/** + * @brief Disable HRC4M low power mode. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_lp_hrc4m(void) +{ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRC4MEN_MSK); +} + +/** + * @brief Check HRC4M low power mode is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_lp_hrc4m(void) +{ + return READ_BITS(CMU->LPENR, CMU_LPENR_HRC4MEN_MSK, CMU_LPENR_HRC4MEN_POS); +} + +/** + * @brief Enable HRC48M low power mode. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_lp_hrc48m(void) +{ + SET_BIT(CMU->LPENR, CMU_LPENR_HRC48MEN_MSK); +} + +/** + * @brief Disable HRC48M low power mode. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_lp_hrc48m(void) +{ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRC48MEN_MSK); +} + +/** + * @brief Check HRC48M low power mode is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_lp_hrc48m(void) +{ + return READ_BITS(CMU->LPENR, CMU_LPENR_HRC48MEN_MSK, CMU_LPENR_HRC48MEN_POS); +} + +/** + * @brief Enable HOSC low power mode. + * @retval None + */ +__STATIC_INLINE void md_cmu_enable_lp_hosc(void) +{ + SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); +} + +/** + * @brief Disable HOSC low power mode. + * @retval None + */ +__STATIC_INLINE void md_cmu_disable_lp_hosc(void) +{ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); +} + +/** + * @brief Check HOSC low power mode is enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_cmu_is_enabled_lp_hosc(void) +{ + return READ_BITS(CMU->LPENR, CMU_LPENR_HOSCEN_MSK, CMU_LPENR_HOSCEN_POS); +} + +/** + * @} + */ +/** @defgroup MD_CMU_Public_Functions_Group1 Initialization and Get BUS Clock value + * @{ + */ +extern md_status_t md_cmu_clock_config_default(void); +extern md_status_t md_cmu_clock_config(md_cmu_clock_t clk, uint32_t clock); +extern void md_cmu_pll_config(md_cmu_pll_input_t input, md_cmu_pll_output_t output); +extern void md_cmu_div_config(md_cmu_bus_t bus, md_cmu_div_t clk_div); +extern uint32_t md_cmu_get_sys_clock(void); +extern uint32_t md_cmu_get_pclk_clock(void); +extern uint32_t md_cmu_get_clock(void); +/** + * @} + */ + +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __MD_CMU_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_conf.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_conf.h new file mode 100644 index 0000000000..e07fd1a5b2 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_conf.h @@ -0,0 +1,143 @@ +/********************************************************************************** + * + * @file md_conf.h + * @brief Enable/Disable the peripheral module. + * + * @date + * @author + * @note + * Change Logs: + * Date Author Notes + * + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ +#ifndef __MD_CONF_H__ +#define __MD_CONF_H__ + +/* Includes ------------------------------------------------------------------ */ + +#define MD_I2C +#define MD_GPIO +#define MD_TIMER +#define MD_ADC +#define MD_DMA +#define MD_SPI +#define MD_IWDT +#define MD_WWDT +#define MD_CRC +#define MD_UART +#define MD_CMU +#define MD_DBGC +#define MD_MSC +#define MD_PIS +#define MD_PMU +#define MD_RMU +#define MD_SYSCFG +#define MD_TYPE +#define MD_UTILS + +#include "md_csu.h" + +#ifdef MD_I2C + #include "md_i2c.h" +#endif /* MD_I2C */ + +#ifdef MD_GPIO + #include "md_gpio.h" +#endif /* MD_GPIO */ + +#ifdef MD_TIMER + #include "md_timer.h" +#endif /* MD_TIMER */ + +#ifdef MD_ADC + #include "md_adc.h" +#endif /* MD_ADC */ + +#ifdef MD_DMA + #include "md_dma.h" +#endif /* MD_DMA */ + +#ifdef MD_SPI + #include "md_spi.h" +#endif /* MD_SPI */ + +#ifdef MD_IWDT + #include "md_iwdt.h" +#endif /* MD_IWDT */ + +#ifdef MD_WWDT + #include "md_wwdt.h" +#endif /* MD_WWDT */ + +#ifdef MD_CRC + #include "md_crc.h" +#endif /* MD_CRC */ + +#ifdef MD_UART + #include "md_uart.h" +#endif /* MD_UART */ + +#ifdef MD_CMU + #include "md_cmu.h" +#endif /* MD_CMU */ + +#ifdef MD_DBGC + +#endif /* MD_DBGC */ + +#ifdef MD_MSC + #include "md_msc.h" +#endif /* MD_MSC */ + +#ifdef MD_PIS + #include "md_pis.h" +#endif /* MD_PIS */ + +#ifdef MD_PMU + #include "md_pmu.h" +#endif /* MD_PMU */ + +#ifdef MD_RMU + #include "md_rmu.h" +#endif /* MD_RMU */ + +#ifdef MD_SYSCFG + #include "md_syscfg.h" +#endif /* MD_SYSCFG */ + +#ifdef MD_UTILS + #include "md_utils.h" +#endif /* MD_UTILS */ + +#ifdef MD_TYPE + #include "type.h" +#endif /* MD_TYPE */ + +/* Exported Types ------------------------------------------------------------ */ +/* Exported Macros ----------------------------------------------------------- */ +/* Exported Variables -------------------------------------------------------- */ +/* Exported Constants -------------------------------------------------------- */ +/* Exported Functions -------------------------------------------------------- */ + +#endif /*__MD_CONF_H__*/ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ + diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_crc.c b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_crc.c new file mode 100644 index 0000000000..f0f86e2d84 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_crc.c @@ -0,0 +1,121 @@ +/********************************************************************************** + * + * @file md_crc.c + * @brief CRC module driver. + * + * @date 20 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 20 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_crc.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ + +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ +/** @addtogroup MD_CRC + * @{ + */ +/** @addtogroup MD_CRC_Public_Functions + * @{ + */ +/** @defgroup MD_CRC_Public_Functions_Group1 Initialization + * @{ + */ +/** + * @brief Reset the CRC peripheral. + * @retval None + */ +void md_crc_reset_reg(void) +{ + CRC->DATA = 0x0; + CRC->CR = 0x2; + CRC->SEED = 0xFFFFFFFF; +} + +/** + * @brief Initializes the CRC mode according to the specified parameters in + * the md_crc_init_t. + * @param init: Pointer to a md_crc_init_t structure that contains + * the configuration information for the specified CRC module. + * @retval None + */ +void md_crc_init(md_crc_init_t *init) +{ + uint32_t tmp = 0U; + + md_crc_reset_reg(); + tmp |= ((init->chs_rev << CRC_CR_CHSREV_POS) | (init->data_inv << CRC_CR_DATINV_POS) | + (init->chs_inv << CRC_CR_CHSINV_POS) | (init->mode << CRC_CR_MODE_POSS) | + (init->len << CRC_CR_DATLEN_POSS) | (init->data_rev << CRC_CR_DATREV_POS) | + (init->order << CRC_CR_BYTORD_POS)); + WRITE_REG(CRC->CR, tmp); + WRITE_REG(CRC->SEED, init->seed); + MD_CRC_RESET(); + MD_CRC_ENABLE(); + + return; +} + +/** + * @brief Initialize the CRC peripheral using the default parameters. + * @param init: Pointer to a md_crc_init_t structure + * @retval None + */ +void md_crc_init_struct(md_crc_init_t *init) +{ + init->mode = MD_CRC_MODE_CCITT; + init->len = MD_CRC_DATASIZE_8; + init->order = MD_CRC_BYTORD_LOW; + init->data_rev = DISABLE; + init->data_inv = DISABLE; + init->chs_rev = DISABLE; + init->chs_inv = DISABLE; + init->seed = 0x0; + + return; +} +/** + * @} MD_CRC_Public_Functions_Group1 + */ +/** + * @} MD_CRC_Public_Functions + */ +/** + * @} MD_CRC + */ +/** + * @} Micro_Driver + */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_crc.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_crc.h new file mode 100644 index 0000000000..191151d48e --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_crc.h @@ -0,0 +1,524 @@ +/********************************************************************************** + * + * @file md_crc.h + * @brief Header file of CRC module driver. + * + * @date 20 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 20 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + + +#ifndef __MD_CRC_H__ +#define __MD_CRC_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_utils.h" + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @addtogroup Micro_Driver + * @{ + */ +/** @defgroup MD_CRC CRC + * @brief CRC micro driver + * @{ + */ +/** + * @defgroup MD_CRC_Public_Macros CRC Public Macros + * @{ + */ +/** + * @brief CRC check byte order select + */ +typedef enum +{ + MD_CRC_BYTORD_LOW = 0x0U, /**< LSB first */ + MD_CRC_BYTORD_HIGH = 0x1U, /**< MSB first */ +} md_crc_bytord_t; + +/** + * @brief CRC data length select + */ +typedef enum +{ + MD_CRC_LEN_AUTO = 0x0U, /**< Auto */ + MD_CRC_DATASIZE_8 = 0x1U, /**< Byte */ + MD_CRC_DATASIZE_16 = 0x2U, /**< Half word */ + MD_CRC_DATASIZE_32 = 0x3U, /**< Word */ +} md_crc_data_bits_t; +/** + * @brief CRC Mode + */ +typedef enum +{ + MD_CRC_MODE_CCITT = 0x0U, /**< CRC-CCITT */ + MD_CRC_MODE_8 = 0x1U, /**< CRC-8 */ + MD_CRC_MODE_16 = 0x2U, /**< CRC-16 */ + MD_CRC_MODE_32 = 0x3U, /**< CRC-32 */ +} md_crc_mode_t; +/** + * @} + */ +/** + * @defgroup MD_CRC_Public_Types CRC Public Types + * @{ + */ +/** + * @brief CRC init structure definition + */ +typedef struct +{ + md_crc_mode_t mode; /**< CRC mode */ + md_crc_data_bits_t len; /**< Data length */ + md_crc_bytord_t order; /**< Byte order for checking */ + type_func_t data_rev; /**< CRC data reverse or no */ + type_func_t data_inv; /**< CRC data inverse or no */ + type_func_t chs_rev; /**< CRC check sum reverse or no */ + type_func_t chs_inv; /**< CRC check sum inverse or no */ + uint32_t seed; /**< CRC seed */ +} md_crc_init_t; +/** + * @} + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** @defgroup MD_CRC_Public_Macros CRC Public Macros + * @{ + */ +#define MD_CRC_ENABLE() (SET_BIT(CRC->CR, CRC_CR_EN_MSK)) +#define MD_CRC_DISABLE() (CLEAR_BIT(CRC->CR, CRC_CR_EN_MSK)) +#define MD_CRC_RESET() (SET_BIT(CRC->CR, CRC_CR_RST_MSK)) +#define MD_CRC_DMA_ENABLE() (SET_BIT(CRC->CR, CRC_CR_DMAEN_MSK)) +#define MD_CRC_DMA_DISABLE() (CLEAR_BIT(CRC->CR, CRC_CR_DMAEN_MSK)) +#define MD_CRC_CLEAR_ERROR_FLAG() (SET_BIT(CRC->CR, CRC_CR_WERR_MSK)) +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @defgroup MD_CRC_Public_Functions CRC Public Functions + * @{ + */ +/** @defgroup MD_CRC_Public_Functions_Group2 CR + * @{ + */ +/** + * @brief CRC Enable + * @param CRCx: CRC Peripheral + * @retval NONE + */ +__STATIC_INLINE void md_crc_enable(CRC_TypeDef *CRCx) +{ + SET_BIT(CRCx->CR, CRC_CR_EN_MSK); +} + +/** + * @brief CRC Disable + * @param CRCx: CRC Peripheral + * @retval NONE + */ +__STATIC_INLINE void md_crc_disable(CRC_TypeDef *CRCx) +{ + CLEAR_BIT(CRCx->CR, CRC_CR_EN_MSK); +} + +/** + * @brief Indicate if CRC is enabled + * @param CRCx: CRC Peripheral + * @retval State. + */ +__STATIC_INLINE uint32_t md_crc_is_enabled(CRC_TypeDef *CRCx) +{ + return (READ_BIT(CRCx->CR, CRC_CR_EN_MSK) == (CRC_CR_EN_MSK)); +} + +/** + * @brief Reset CRC + * @param CRCx: CRC Peripheral + * @retval NONE + */ +__STATIC_INLINE void md_crc_reset(CRC_TypeDef *CRCx) +{ + SET_BIT(CRCx->CR, CRC_CR_RST_MSK); +} + +/** + * @brief Indicate if the CRC write data error flag is set or not + * @param CRCx: CRC Peripheral + * @retval State. + */ +__STATIC_INLINE uint32_t md_crc_get_flag_error(CRC_TypeDef *CRCx) +{ + return (READ_BIT(CRCx->CR, CRC_CR_WERR_MSK) == (CRC_CR_WERR_MSK)); +} + +/** + * @brief Clear CRC write data error flag + * @param CRCx: CRC Peripheral + * @retval NONE + */ +__STATIC_INLINE void md_crc_clear_flag_error(CRC_TypeDef *CRCx) +{ + SET_BIT(CRCx->CR, CRC_CR_CWERR_MSK); +} + +/** + * @brief CRC DMA Enable + * @param CRCx: CRC Peripheral + * @retval NONE + */ +__STATIC_INLINE void md_crc_enable_dma(CRC_TypeDef *CRCx) +{ + SET_BIT(CRCx->CR, CRC_CR_DMAEN_MSK); +} + +/** + * @brief CRC DMA Disable + * @param CRCx: CRC Peripheral + * @retval NONE + */ +__STATIC_INLINE void md_crc_disable_dma(CRC_TypeDef *CRCx) +{ + CLEAR_BIT(CRCx->CR, CRC_CR_DMAEN_MSK); +} + +/** + * @brief Indicate if CRC DMA is enabled + * @param CRCx: CRC Peripheral + * @retval State. + */ +__STATIC_INLINE uint32_t md_crc_is_enabled_dma(CRC_TypeDef *CRCx) +{ + return (READ_BIT(CRCx->CR, CRC_CR_DMAEN_MSK) == (CRC_CR_DMAEN_MSK)); +} + +/** + * @brief CRC write data reverse Enable + * @param CRCx: CRC Peripheral + * @retval NONE + */ +__STATIC_INLINE void md_crc_enable_data_reverse(CRC_TypeDef *CRCx) +{ + SET_BIT(CRCx->CR, CRC_CR_DATREV_MSK); +} + +/** + * @brief CRC write data reverse Disable + * @param CRCx: CRC Peripheral + * @retval NONE + */ +__STATIC_INLINE void md_crc_disable_data_reverse(CRC_TypeDef *CRCx) +{ + CLEAR_BIT(CRCx->CR, CRC_CR_DATREV_MSK); +} + +/** + * @brief Indicate if CRC write data reverse is enabled + * @param CRCx: CRC Peripheral + * @retval State. + */ +__STATIC_INLINE uint32_t md_crc_is_enabled_data_reverse_(CRC_TypeDef *CRCx) +{ + return (READ_BIT(CRCx->CR, CRC_CR_DATREV_MSK) == (CRC_CR_DATREV_MSK)); +} + +/** + * @brief CRC checksum reverse Enable + * @param CRCx: CRC Peripheral + * @retval NONE + */ +__STATIC_INLINE void md_crc_enable_result_reverse(CRC_TypeDef *CRCx) +{ + SET_BIT(CRCx->CR, CRC_CR_CHSREV_MSK); +} + +/** + * @brief CRC checksum reverse Disable + * @param CRCx: CRC Peripheral + * @retval NONE + */ +__STATIC_INLINE void md_crc_disable_result_reverse(CRC_TypeDef *CRCx) +{ + CLEAR_BIT(CRCx->CR, CRC_CR_CHSREV_MSK); +} + +/** + * @brief Indicate if CRC checksum reverse is enabled + * @param CRCx: CRC Peripheral + * @retval State. + */ +__STATIC_INLINE uint32_t md_crc_is_enabled_result_reverse(CRC_TypeDef *CRCx) +{ + return (READ_BIT(CRCx->CR, CRC_CR_CHSREV_MSK) == (CRC_CR_CHSREV_MSK)); +} + +/** + * @brief CRC write data invert Enable + * @param CRCx: CRC Peripheral + * @retval NONE + */ +__STATIC_INLINE void md_crc_enable_data_invert(CRC_TypeDef *CRCx) +{ + SET_BIT(CRCx->CR, CRC_CR_DATINV_MSK); +} + +/** + * @brief CRC data invert Disable + * @param CRCx: CRC Peripheral + * @retval NONE + */ +__STATIC_INLINE void md_crc_disable_data_invert(CRC_TypeDef *CRCx) +{ + CLEAR_BIT(CRCx->CR, CRC_CR_DATINV_MSK); +} + +/** + * @brief Indicate if CRC data invert is enabled + * @param CRCx: CRC Peripheral + * @retval State. + */ +__STATIC_INLINE uint32_t md_crc_is_enabled_data_invert(CRC_TypeDef *CRCx) +{ + return (READ_BIT(CRCx->CR, CRC_CR_DATINV_MSK) == (CRC_CR_DATINV_MSK)); +} + +/** + * @brief CRC checksum invert Enable + * @param CRCx: CRC Peripheral + * @retval NONE + */ +__STATIC_INLINE void md_crc_enable_result_invert(CRC_TypeDef *CRCx) +{ + SET_BIT(CRCx->CR, CRC_CR_CHSINV_MSK); +} + +/** + * @brief CRC checksum invert Disable + * @param CRCx: CRC Peripheral + * @retval NONE + */ +__STATIC_INLINE void md_crc_disable_result_invert(CRC_TypeDef *CRCx) +{ + CLEAR_BIT(CRCx->CR, CRC_CR_CHSINV_MSK); +} + +/** + * @brief Indicate if CRC checksum invert is enabled + * @param CRCx: CRC Peripheral + * @retval State. + */ +__STATIC_INLINE uint32_t md_crc_is_enabled_result_invert(CRC_TypeDef *CRCx) +{ + return (READ_BIT(CRCx->CR, CRC_CR_CHSINV_MSK) == (CRC_CR_CHSINV_MSK)); +} + +/** + * @brief Set the mode of CRC + * @param CRCx: CRC Peripheral + * @param mode This parameter can be one of the following values: + * @arg @ref MD_CRC_MODE_CCITT + * @arg @ref MD_CRC_MODE_8 + * @arg @ref MD_CRC_MODE_16 + * @arg @ref MD_CRC_MODE_32 + * @retval NONE + */ +__STATIC_INLINE void md_crc_set_mode(CRC_TypeDef *CRCx, uint32_t mode) +{ + MODIFY_REG(CRCx->CR, CRC_CR_MODE_MSK, mode << CRC_CR_MODE_POSS); +} + +/** + * @brief Get the mode of CRC + * @param CRCx: CRC Peripheral + * @retval Returned value can be one of the following values: + * @arg @ref MD_CRC_MODE_CCITT + * @arg @ref MD_CRC_MODE_8 + * @arg @ref MD_CRC_MODE_16 + * @arg @ref MD_CRC_MODE_32 + */ +__STATIC_INLINE uint32_t md_crc_get_mode(CRC_TypeDef *CRCx) +{ + return (READ_BITS(CRCx->CR, CRC_CR_MODE_MSK, CRC_CR_MODE_POSS)); +} + +/** + * @brief Set the data length of CRC + * @param CRCx: CRC Peripheral + * @param data_bits This parameter can be one of the following values: + * @arg @ref MD_CRC_LEN_AUTO + * @arg @ref MD_CRC_DATASIZE_8 + * @arg @ref MD_CRC_DATASIZE_16 + * @arg @ref MD_CRC_DATASIZE_32 + * @retval NONE + */ +__STATIC_INLINE void md_crc_set_data_bits(CRC_TypeDef *CRCx, uint32_t data_bits) +{ + MODIFY_REG(CRCx->CR, CRC_CR_DATLEN_MSK, data_bits << CRC_CR_DATLEN_POSS); +} + +/** + * @brief Get the data length of CRC + * @param CRCx: CRC Peripheral + * @retval Returned value can be one of the following values: + * @arg @ref MD_CRC_LEN_AUTO + * @arg @ref MD_CRC_DATASIZE_8 + * @arg @ref MD_CRC_DATASIZE_16 + * @arg @ref MD_CRC_DATASIZE_32 + */ +__STATIC_INLINE uint32_t md_crc_get_data_bits(CRC_TypeDef *CRCx) +{ + return (READ_BITS(CRCx->CR, CRC_CR_DATLEN_MSK, CRC_CR_DATLEN_POSS)); +} + +/** + * @brief Set the check byte order of CRC + * @param CRCx: CRC Peripheral + * @param order This parameter can be one of the following values: + * @arg @ref MD_CRC_BYTORD_LOW + * @arg @ref MD_CRC_BYTORD_HIGH + * @retval NONE + */ +__STATIC_INLINE void md_crc_set_check_order(CRC_TypeDef *CRCx, uint32_t order) +{ + MODIFY_REG(CRCx->CR, CRC_CR_BYTORD_MSK, order << CRC_CR_BYTORD_POS); +} + +/** + * @brief Get the checksum byte order of CRC + * @param CRCx: CRC Peripheral + * @retval Returned value can be one of the following values: + * @arg @ref MD_CRC_BYTORD_LOW + * @arg @ref MD_CRC_BYTORD_HIGH + */ +__STATIC_INLINE uint32_t md_crc_get_check_order(CRC_TypeDef *CRCx) +{ + return (READ_BITS(CRCx->CR, CRC_CR_BYTORD_MSK, CRC_CR_BYTORD_POS)); +} +/** + * @} + */ +/** @defgroup MD_CRC_Public_Functions_Group3 DATA + * @{ + */ +/** + * @brief write data of CRC + * @param CRCx: CRC Peripheral + * @param data: Original data + * @retval NONE + */ +__STATIC_INLINE void md_crc_write_data(CRC_TypeDef *CRCx, uint32_t data) +{ + WRITE_REG(CRCx->DATA, data); +} + +/** + * @brief Get the original data of CRC + * @param CRCx: CRC Peripheral + * @retval writed data + */ +__STATIC_INLINE uint32_t md_crc_get_original_data(CRC_TypeDef *CRCx) +{ + return READ_REG(CRCx->DATA); +} +/** + * @} + */ +/** @defgroup MD_CRC_Public_Functions_Group4 SEED + * @{ + */ +/** + * @brief Set the seed of CRC + * @param CRCx: CRC Peripheral + * @param seed: This parameter can be 0~0xFFFFFFFF + * @retval NONE + */ +__STATIC_INLINE void md_crc_set_seed(CRC_TypeDef *CRCx, uint32_t seed) +{ + WRITE_REG(CRCx->SEED, seed); +} + +/** + * @brief Get the seed of CRC + * @param CRCx: CRC Peripheral + * @retval seed + */ +__STATIC_INLINE uint32_t md_crc_get_seed(CRC_TypeDef *CRCx) +{ + return READ_REG(CRCx->SEED); +} +/** + * @} + */ +/** @defgroup MD_CRC_Public_Functions_Group5 CHECKSUM + * @{ + */ +/** + * @brief Get the CRC check result + * @param CRCx: CRC Peripheral + * @retval CRC check result + */ +__STATIC_INLINE uint32_t md_crc_get_check_result(CRC_TypeDef *CRCx) +{ + return READ_REG(CRCx->CHECKSUM); +} +/** + * @} + */ +/** @addtogroup MD_CRC_Public_Functions_Group1 + * @{ + */ + +extern void md_crc_reset_reg(void); +extern void md_crc_init(md_crc_init_t *init); +extern void md_crc_init_struct(md_crc_init_t *init); + +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __MD_CRC_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_csu.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_csu.h new file mode 100644 index 0000000000..fc5efd04a1 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_csu.h @@ -0,0 +1,131 @@ +/********************************************************************************** + * + * @file md_cmu.h + * @brief Header file of CSU module driver. + * + * @date 2023.02.13 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 2023.02.13 liuhy the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __MD_CSU_H__ +#define __MD_CSU_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_utils.h" +#include "md_syscfg.h" + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Types ------------------------------------------------------------ */ + +/* Exported Macros ----------------------------------------------------------- */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_CSU CSU + * @brief CSU micro driver + + * @{ + */ + + +/** @defgroup MD_CSU_Public_Functions CSU Public Functions + * @{ + */ +/** @defgroup MD_CSU_Public_Functions_Group2 CON + * @{ + */ + +/** + * @brief Enable CSU_CON_AUTOEN + * @retval NONE + */ +__STATIC_INLINE void md_csu_enable_auto(void) +{ + SET_BIT(CSU->CON, CSU_CON_AUTOEN_MSK); +} + +/** + * @brief Disable CSU_CON_AUTOEN + * @retval NONE + */ +__STATIC_INLINE void md_csu_disable_auto(void) +{ + CLEAR_BIT(CSU->CON, CSU_CON_AUTOEN_MSK); +} + +/** + * @brief Enable CSU_CON_CNTEN + * @retval NONE + */ +__STATIC_INLINE void md_csu_enable_cnt(void) +{ + SET_BIT(CSU->CON, CSU_CON_CNTEN_MSK); +} + +/** + * @brief Disable CSU_CON_CNTEN + * @retval NONE + */ +__STATIC_INLINE void md_csu_disable_cnt(void) +{ + CLEAR_BIT(CSU->CON, CSU_CON_CNTEN_MSK); +} + +/** + * @} + */ +/** @defgroup MD_CSU_Public_Functions_Group1 Initialization and Get BUS Clock value + * @{ + */ +/** + * @} + */ + +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __MD_CSU_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_dma.c b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_dma.c new file mode 100644 index 0000000000..8a9522912a --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_dma.c @@ -0,0 +1,127 @@ +/********************************************************************************** + * + * @file md_dma.c + * @brief DMA module driver. + * + * @date 19 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 19 July 2022 Shiwa the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_dma.h" + +/* Private Macros ------------------------------------------------------------ */ +#define IS_PERH_ADDR(x) (((uint32_t)(x))>=0x40000000) +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ + +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @addtogroup MD_DMA + * @{ + */ + +/** @addtogroup MD_DMA_Public_Functions + * @{ + */ +/** @addtogroup MD_DMA_Public_Functions_Group1 + * @{ + */ +/** + * @brief Reset the DMA register + * @param DMAx: Pointer to DMA peripheral + * @retval None + */ +void md_dma_reset(void) +{ + uint32_t i; + + WRITE_REG(DMA->IDR, 0x3FFF); + WRITE_REG(DMA->ICR, 0x3FFF); + + for (i = 0; i < DMA_CHANNELS; ++i) + { + md_dma_disable_channel(i); + WRITE_REG(DMA->CHANNEL[i].CON, 0x0); + WRITE_REG(DMA->CHANNEL[i].SAR, 0x0); + WRITE_REG(DMA->CHANNEL[i].DAR, 0x0); + WRITE_REG(DMA->CHANNEL[i].NDT, 0x0); + WRITE_REG(DMA_MUX->CH_SELCON[i], 0x0); + } + + return; +} + +/** + * @brief DMA init + * @param ch: DMA channel + * @param config: DMA config + * @retval None + */ +void md_dma_init(uint32_t ch, md_dma_config_t *config) +{ + md_dma_set_source_addr(ch, config->src); + md_dma_set_source_width(ch, config->src_data_width); + md_dma_set_source_inc(ch, config->src_inc); + md_dma_set_dest_addr(ch, config->dst); + md_dma_set_dest_width(ch, config->dst_data_width); + md_dma_set_dest_inc(ch, config->dst_inc); + md_dma_set_circle_mode(ch, config->circle_mode); + md_dma_set_mem_to_mem(ch, config->mem_to_mem); + md_dma_set_priority(ch, config->priority); + md_dma_set_r_power(ch, config->R_power); + md_dma_set_transfer_size(ch, config->size); + md_dma_set_channel_msel(ch, config->msel); + md_dma_set_channel_msigsel(ch, config->msigsel); + + if (IS_PERH_ADDR(config->dst)&&!IS_PERH_ADDR(config->src)) + { + md_dma_set_data_dir(ch, ENABLE); + } + else + { + md_dma_set_data_dir(ch, DISABLE); + } +} +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_dma.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_dma.h new file mode 100644 index 0000000000..375ce018e7 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_dma.h @@ -0,0 +1,939 @@ +/********************************************************************************** + * + * @file md_dma.h + * @brief Header file of DMA module driver. + * + * @date 19 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 19 July 2022 Shiwa the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + + +#ifndef __MD_DMA_H__ +#define __MD_DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_utils.h" +/** @addtogroup Micro_Driver + * @{ + */ +/** @defgroup MD_DMA DMA + * @brief DMA micro driver + * @{ + */ + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup MD_DMA_Public_Types DMA Public Types + * @{ + */ +/** + * @brief Input source to DMA channel + */ +typedef enum +{ + MD_DMA_MSEL_NONE = 0x0U, /**< NONE */ + MD_DMA_MSEL_GPIO = 0x1U, /**< GPIO */ + MD_DMA_MSEL_ADC = 0x2U, /**< ADC */ + MD_DMA_MSEL_CRC = 0x3U, /**< CRC */ + MD_DMA_MSEL_EUART0 = 0x4U, /**< EUART0 */ + MD_DMA_MSEL_EUART1 = 0x5U, /**< EUART1 */ + MD_DMA_MSEL_CUART0 = 0x6U, /**< CUART0 */ + MD_DMA_MSEL_CUART1 = 0x7U, /**< CUART1 */ + MD_DMA_MSEL_CUART2 = 0x8U, /**< CUART2 */ + MD_DMA_MSEL_SPI0 = 0x9U, /**< SPI */ + MD_DMA_MSEL_SPI1 = 0xAU, /**< SPI */ + MD_DMA_MSEL_I2C0 = 0xBU, /**< I2C0 */ + MD_DMA_MSEL_I2C1 = 0xCU, /**< I2C1 */ + MD_DMA_MSEL_AD16C4T = 0xDU, /**< AD16C4T */ + MD_DMA_MSEL_GP16C2T0 = 0xEU, /**< GP16C2T0 */ + MD_DMA_MSEL_GP16C2T1 = 0xFU, /**< GP16C2T1 */ + MD_DMA_MSEL_GP16C2T2 = 0x10U, /**< GP16C2T2 */ + MD_DMA_MSEL_PIS = 0x11U,/**< PIS */ + MD_DMA_MSEL_BSTIM0 = 0x12U,/**< BSTIM0 */ +} md_dma_msel_t; + +/** + * @brief Input signal to DMA channel + */ +typedef enum +{ + MD_DMA_MSIGSEL_NONE = 0x0U, /**< NONE */ + MD_DMA_MSIGSEL_EXTI_0 = 0x0U, /**< External interrupt 0 */ + MD_DMA_MSIGSEL_EXTI_1 = 0x1U, /**< External interrupt 1 */ + MD_DMA_MSIGSEL_EXTI_2 = 0x2U, /**< External interrupt 2 */ + MD_DMA_MSIGSEL_EXTI_3 = 0x3U, /**< External interrupt 3 */ + MD_DMA_MSIGSEL_EXTI_4 = 0x4U, /**< External interrupt 4 */ + MD_DMA_MSIGSEL_EXTI_5 = 0x5U, /**< External interrupt 5 */ + MD_DMA_MSIGSEL_EXTI_6 = 0x6U, /**< External interrupt 6 */ + MD_DMA_MSIGSEL_EXTI_7 = 0x7U, /**< External interrupt 7 */ + MD_DMA_MSIGSEL_EXTI_8 = 0x8U, /**< External interrupt 8 */ + MD_DMA_MSIGSEL_EXTI_9 = 0x9U, /**< External interrupt 9 */ + MD_DMA_MSIGSEL_EXTI_10 = 0xAU, /**< External interrupt 10 */ + MD_DMA_MSIGSEL_EXTI_11 = 0xBU, /**< External interrupt 11 */ + MD_DMA_MSIGSEL_EXTI_12 = 0xCU, /**< External interrupt 12 */ + MD_DMA_MSIGSEL_EXTI_13 = 0xDU, /**< External interrupt 13 */ + MD_DMA_MSIGSEL_EXTI_14 = 0xEU, /**< External interrupt 14 */ + MD_DMA_MSIGSEL_EXTI_15 = 0xFU, /**< External interrupt 15 */ + MD_DMA_MSIGSEL_ADC = 0x0U, /**< ADC mode */ + MD_DMA_MSIGSEL_CRC = 0x0U, /**< CRC */ + MD_DMA_MSIGSEL_UART_RNR = 0x0U, /**< UART reveive */ + MD_DMA_MSIGSEL_UART_TXEMPTY = 0x1U, /**< UART transmit */ + MD_DMA_MSIGSEL_SPI_RNR = 0x0U, /**< SPI receive */ + MD_DMA_MSIGSEL_SPI_TXEMPTY = 0x1U, /**< SPI transmit */ + MD_DMA_MSIGSEL_I2C_RNR = 0x0U, /**< I2C receive */ + MD_DMA_MSIGSEL_I2C_TXEMPTY = 0x1U, /**< I2C transmit */ + MD_DMA_MSIGSEL_TIMER_CH1 = 0x0U, /**< TIM channal 1 */ + MD_DMA_MSIGSEL_TIMER_CH2 = 0x1U, /**< TIM channal 2 */ + MD_DMA_MSIGSEL_TIMER_CH3 = 0x2U, /**< TIM channal 3 */ + MD_DMA_MSIGSEL_TIMER_CH4 = 0x3U, /**< TIM channal 4 */ + MD_DMA_MSIGSEL_TIMER_TRI = 0x4U, /**< TIM trigger */ + MD_DMA_MSIGSEL_TIMER_COMP = 0x5U, /**< TIM compare */ + MD_DMA_MSIGSEL_TIMER_UPDATE = 0x6U, /**< TIM update */ + MD_DMA_MSIGSEL_BSTIM0 = 0x0U, /**< BSTIM0 */ + MD_DMA_MSIGSEL_PIS_CH0 = 0x0U, /**< PIS channal 0 */ + MD_DMA_MSIGSEL_PIS_CH1 = 0x1U, /**< PIS channal 1 */ + MD_DMA_MSIGSEL_PIS_CH2 = 0x2U, /**< PIS channal 2 */ + MD_DMA_MSIGSEL_PIS_CH3 = 0x3U, /**< PIS channal 3 */ + MD_DMA_MSIGSEL_PIS_CH4 = 0x4U, /**< PIS channal 4 */ + MD_DMA_MSIGSEL_PIS_CH5 = 0x5U, /**< PIS channal 5 */ + MD_DMA_MSIGSEL_PIS_CH6 = 0x6U, /**< PIS channal 6 */ + MD_DMA_MSIGSEL_PIS_CH7 = 0x7U, /**< PIS channal 7 */ +} md_dma_msigsel_t; +/** + * @brief Priority of DMA channel + */ +typedef enum +{ + MD_DMA_LOW_PRIORITY = 0, + MD_DMA_MEDIUM_PRIORITY = 1, + MD_DMA_HIGH_PRIORUTY = 2, + MD_DMA_HIGHEST_PRIORITY = 3 +} md_dma_priority_t; + +/** + * @brief data increment + */ +typedef enum +{ + MD_DMA_DATA_INC_DISABLE = 0x0U, + MD_DMA_DATA_INC_ENABLE = 0x1U, +} md_dma_data_inc_t; + +/** + * @brief Data size + */ +typedef enum +{ + MD_DMA_DATA_SIZE_BYTE = 0x0U, /**< Byte */ + MD_DMA_DATA_SIZE_HALFWORD = 0x1U, /**< Halfword */ + MD_DMA_DATA_SIZE_WORD = 0x2U, /**< Word */ +} md_dma_data_size_t; + +/** + * @brief Control how many DMA transfers can occur + * before the controller re-arbitrates + */ +typedef enum +{ + MD_DMA_R_POWER_1 = 0x0U, /**< Arbitrates after each DMA transfer */ + MD_DMA_R_POWER_2 = 0x1U, /**< Arbitrates after 2 DMA transfer */ + MD_DMA_R_POWER_4 = 0x2U, /**< Arbitrates after 4 DMA transfer */ + MD_DMA_R_POWER_8 = 0x3U, /**< Arbitrates after 8 DMA transfer */ + MD_DMA_R_POWER_16 = 0x4U, /**< Arbitrates after 16 DMA transfer */ + MD_DMA_R_POWER_32 = 0x5U, /**< Arbitrates after 32 DMA transfer */ + MD_DMA_R_POWER_64 = 0x6U, /**< Arbitrates after 64 DMA transfer */ + MD_DMA_R_POWER_128 = 0x7U, /**< Arbitrates after 128 DMA transfer */ + MD_DMA_R_POWER_256 = 0x8U, /**< Arbitrates after 256 DMA transfer */ + MD_DMA_R_POWER_512 = 0x9U, /**< Arbitrates after 512 DMA transfer */ + MD_DMA_R_POWER_1024 = 0xAU, /**< Arbitrates after 1024 DMA transfer */ +} md_dma_arbiter_config_t; + +/** + * @brief DMA channal configure structure + */ +typedef struct +{ + void *src; /**< Source data begin pointer */ + void *dst; /**< Destination data begin pointer */ + uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */ + md_dma_data_size_t src_data_width; /**< Source data width */ + md_dma_data_size_t dst_data_width; /**< Dest data width */ + TypeFunc src_inc; /**< Source increment type */ + TypeFunc dst_inc; /**< Destination increment type */ + md_dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates */ + md_dma_priority_t priority; /**< High priority or default priority */ + TypeFunc mem_to_mem; /**< Enable/disable memory to memory mode */ + TypeFunc circle_mode; /**< Enable/disable circular mode */ + md_dma_msel_t msel; /**< Input source to DMA channel */ + md_dma_msigsel_t msigsel; /**< Input signal to DMA channel */ + uint8_t channel; /**< Channel index */ +} md_dma_config_t; +/** + * @} + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** @defgroup MD_DMA_Public_Macros DMA Public Macros + * @{ + */ +/** + * brief MD_DMA_CHANNEL DMA channel + */ +#define MD_DMA_CH_0 0x0U /**< Channel 0 */ +#define MD_DMA_CH_1 0x1U /**< Channel 1 */ +#define MD_DMA_CH_2 0x2U /**< Channel 2 */ +#define MD_DMA_CH_3 0x3U /**< Channel 3 */ +#define MD_DMA_CH_4 0x4U /**< Channel 4 */ +#define MD_DMA_CH_5 0x5U /**< Channel 5 */ +#define MD_DMA_CH_6 0x6U /**< Channel 6 */ + +/** + * @brief DMA interrupt flag + */ +#define MD_DMA_CH0_TC DMA_CH0_TC_MSK /**< interrupt mask 1 */ +#define MD_DMA_CH0_HT DMA_CH0_HT_MSK /**< interrupt mask 2 */ +#define MD_DMA_CH1_TC DMA_CH1_TC_MSK /**< interrupt mask 3 */ +#define MD_DMA_CH1_HT DMA_CH1_HT_MSK /**< interrupt mask 4 */ +#define MD_DMA_CH2_TC DMA_CH2_TC_MSK /**< interrupt mask 5 */ +#define MD_DMA_CH2_HT DMA_CH2_HT_MSK /**< interrupt mask 6 */ +#define MD_DMA_CH3_TC DMA_CH3_TC_MSK /**< interrupt mask 7 */ +#define MD_DMA_CH3_HT DMA_CH3_HT_MSK /**< interrupt mask 8 */ +#define MD_DMA_CH4_TC DMA_CH4_TC_MSK /**< interrupt mask 9 */ +#define MD_DMA_CH4_HT DMA_CH4_HT_MSK /**< interrupt mask 10 */ +#define MD_DMA_CH5_TC DMA_CH5_TC_MSK /**< interrupt mask 11 */ +#define MD_DMA_CH5_HT DMA_CH5_HT_MSK /**< interrupt mask 12 */ +#define MD_DMA_CH6_TC DMA_CH6_TC_MSK /**< interrupt mask 13 */ +#define MD_DMA_CH6_HT DMA_CH6_HT_MSK /**< interrupt mask 14 */ +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @defgroup MD_DMA_Public_Functions DMA Public Functions + * @{ + */ +/** @defgroup MD_DMA_Public_Functions_Group2 STATUS + * @{ + */ + +/** + * @brief Check if DMA peripheral is enabled + * @param ch: DMA channel (0-6) + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ + +/** + * @brief Check if DMA peripheral is enabled + * @param ch: DMA channel (0-6) + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_dma_is_enabled(uint32_t ch) +{ + return READ_BIT(DMA->CHANNEL[ch].CON, DMA_CON_CHEN_POS); +} +/** + * @} + */ +/** @defgroup MD_DMA_Public_Functions_Group3 Enable/Disable + * @{ + */ +/** + * @brief Enable DMA peripheral + * @param ch: DMA channel(0-6) + * @retval None + */ +__STATIC_INLINE void md_dma_enable_channel(uint32_t ch) +{ + SET_BIT(DMA->CHANNEL[ch].CON, DMA_CON_CHEN_MSK); +} + +/** + * @brief Disable DMA peripheral + * @param ch: DMA channel(0-6) + * @retval None + */ +__STATIC_INLINE void md_dma_disable_channel(uint32_t ch) +{ + CLEAR_BIT(DMA->CHANNEL[ch].CON, DMA_CON_CHEN_MSK); +} + +/** + * @} + */ + +/** @defgroup MD_DMA_Public_Functions_Group4 SAR + * @{ + */ +/** + * @brief Set DMA source data address + * @param ch: DMA channel + * @param addr: Source data address + * @retval None + */ +__STATIC_INLINE void md_dma_set_source_addr(uint32_t ch, void *addr) +{ + WRITE_REG(DMA->CHANNEL[ch].SAR, (uint32_t)addr); +} + +/** + * @brief Get DMA source data address + * @param ch: DMA channel + * @retval DMA source data address + */ +__STATIC_INLINE void *md_dma_get_source_addr(uint32_t ch) +{ + return (void *)DMA->CHANNEL[ch].SAR; +} +/** + * @} + */ + +/** @defgroup MD_DMA_Public_Functions_Group5 DAR + * @{ + */ + +/** + * @brief Set DMA destination data address + * @param ch: DMA channel + * @param addr: DMA destination data address + * @retval None + */ +__STATIC_INLINE void md_dma_set_dest_addr(uint32_t ch, void *addr) +{ + WRITE_REG(DMA->CHANNEL[ch].DAR, (uint32_t)addr); +} + +/** + * @brief Get DMA destination data address + * @param ch: DMA channel + * @retval The destination data address + */ +__STATIC_INLINE void *md_dma_get_dest_addr(uint32_t ch) +{ + return (void *)DMA->CHANNEL[ch].DAR; +} + +/** + * @} + */ + +/** @defgroup MD_DMA_Public_Functions_Group6 CON + * @{ + */ + +/** + * @brief Sets DMA source data width + * @param ch: DMA channel + * @param data_width: This parameter can be one of the @ref md_dma_data_size_t + * @retval None + */ +__STATIC_INLINE void md_dma_set_source_width(uint32_t ch, uint32_t data_width) +{ + MODIFY_REG(DMA->CHANNEL[ch].CON, DMA_CON_SDWSEL_MSK, data_width << DMA_CON_SDWSEL_POSS); +} + +/** + * @brief Gets DMA source data width + * @param ch: DMA channel + * @retval The return data width, see @ref md_dma_data_size_t + */ +__STATIC_INLINE uint32_t md_dma_get_source_width(uint32_t ch) +{ + return READ_BITS(DMA->CHANNEL[ch].CON, DMA_CON_SDWSEL_MSK, DMA_CON_SDWSEL_POSS); +} + +/** + * @brief Set DMA source data increment + * @param ch: DMA channel + * @param src_inc: ENABLE(1) or DISABLE(0) + * @retval None + */ +__STATIC_INLINE void md_dma_set_source_inc(uint32_t ch, uint32_t src_inc) +{ + MODIFY_REG(DMA->CHANNEL[ch].CON, DMA_CON_SINC_MSK, src_inc << DMA_CON_SINC_POS); +} + +/** + * @brief Get DMA source data increment + * @param ch: DMA channel + * @retval ENABLE(1) or DISABLE(0) + */ +__STATIC_INLINE uint32_t md_dma_get_source_inc(uint32_t ch) +{ + return READ_BIT(DMA->CHANNEL[ch].CON, DMA_CON_SINC_POS); +} + +/** + * @brief Sets DMA dest data width + * @param ch: DMA channel + * @param data_width: This parameter can be one of the @ref md_dma_data_size_t + * @retval None + */ +__STATIC_INLINE void md_dma_set_dest_width(uint32_t ch, uint32_t data_width) +{ + MODIFY_REG(DMA->CHANNEL[ch].CON, DMA_CON_DDWSEL_MSK, data_width << DMA_CON_DDWSEL_POSS); +} + +/** + * @brief Gets DMA dest data width + * @param ch: DMA channel + * @retval The return data width, see @ref md_dma_data_size_t + */ +__STATIC_INLINE uint32_t md_dma_get_dest_width(uint32_t ch) +{ + return READ_BITS(DMA->CHANNEL[ch].CON, DMA_CON_DDWSEL_MSK, DMA_CON_DDWSEL_POSS); +} +/** + * @brief Set DMA destination data increment + * @param ch: DMA channel + * @param dst_inc This parameter can be one of the @ref md_dma_data_inc_t + * @retval None + */ +__STATIC_INLINE void md_dma_set_dest_inc(uint32_t ch, uint32_t dst_inc) +{ + MODIFY_REG(DMA->CHANNEL[ch].CON, DMA_CON_DINC_MSK, dst_inc << DMA_CON_DINC_POS); +} + +/** + * @brief Get DMA destination data increment + * @param ch: DMA channel + * @retval The return destination data increment, see @ref md_dma_data_inc_t + */ +__STATIC_INLINE uint32_t md_dma_get_dest_inc(uint32_t ch) +{ + return READ_BIT(DMA->CHANNEL[ch].CON, DMA_CON_SINC_POS); +} + +/** + * @brief Set how many DMA transfers can occur before the controller rearbitrates + * @param ch: DMA channel + * @param r_power: The r_power value, see @ref md_dma_arbiter_config_t + * @retval None + */ +__STATIC_INLINE void md_dma_set_r_power(uint32_t ch, uint32_t r_power) +{ + MODIFY_REG(DMA->CHANNEL[ch].CON, DMA_CON_MAX_BURST_MSK, r_power << DMA_CON_MAX_BURST_POSS); +} + +/** + * @brief Get how many DMA transfers can occur before the controller rearbitrates + * @param ch: DMA channel + * @retval The r_power value, see @ref md_dma_arbiter_config_t + */ +__STATIC_INLINE uint32_t md_dma_get_r_power(uint32_t ch) +{ + return READ_BITS(DMA->CHANNEL[ch].CON, DMA_CON_MAX_BURST_MSK, DMA_CON_MAX_BURST_POSS); +} + +/** + * @brief Enable or disable DMA memory to memory transfer mode + * @param ch: DMA channel + * @param enable: 1-Enable,0-Disable + * @retval None + */ +__STATIC_INLINE void md_dma_set_mem_to_mem(uint32_t ch, uint32_t enable) +{ + MODIFY_REG(DMA->CHANNEL[ch].CON, DMA_CON_M2M_MSK, enable << DMA_CON_M2M_POS); +} +/** + * @brief Get whether DMA memory to memory transfer is enabled + * @param ch: DMA channel + * @retval 1-Enable,0-Disable + */ +__STATIC_INLINE uint32_t md_dma_get_mem_to_mem(uint32_t ch) +{ + return (READ_BIT(DMA->CHANNEL[ch].CON, DMA_CON_M2M_MSK) == DMA_CON_M2M_MSK); +} + +/** + * @brief Set DMA data transfer direction (However,NO actual effect) + * @param ch: DMA channel + * @param dir: 0-peri->mem,1-mem->peri + * @retval None + */ +__STATIC_INLINE void md_dma_set_data_dir(uint32_t ch, uint32_t dir) +{ + MODIFY_REG(DMA->CHANNEL[ch].CON, DMA_CON_DIR_MSK, dir << DMA_CON_DIR_POS); +} +/** + * @brief Get DMA data transfer direction (However,NO actual effect) + * @param ch: DMA channel + * @retval 0-peri->mem,1-mem->peri + */ +__STATIC_INLINE uint32_t md_dma_get_data_dir(uint32_t ch) +{ + return (READ_BIT(DMA->CHANNEL[ch].CON, DMA_CON_DIR_MSK) == DMA_CON_DIR_MSK); +} + +/** + * @brief Set DMA data transfer direction + * @param ch: DMA channel + * @param enable: 1-Enable,0-Disable + * @retval None + */ +__STATIC_INLINE void md_dma_set_circle_mode(uint32_t ch, uint32_t enable) +{ + MODIFY_REG(DMA->CHANNEL[ch].CON, DMA_CON_CIRC_MSK, enable << DMA_CON_CIRC_POS); +} +/** + * @brief Get whether DMA mem to mem transfer is enabled + * @param ch: DMA channel + * @retval 1-Enable,0-Disable + */ +__STATIC_INLINE uint32_t md_dma_get_circle_mode(uint32_t ch) +{ + return (READ_BIT(DMA->CHANNEL[ch].CON, DMA_CON_CIRC_MSK) == DMA_CON_CIRC_MSK); +} +/** + * @brief Set channel priority + * @param ch: DMA channel + * @param priority: Priority of DMA channel see @ref md_dma_priority_t + * @retval None + */ +__STATIC_INLINE void md_dma_set_priority(uint32_t ch, uint32_t priority) +{ + MODIFY_REG(DMA->CHANNEL[ch].CON, DMA_CON_CHPRI_MSK, priority << DMA_CON_CHPRI_POSS); +} +/** + * @brief Get channel priority + * @param ch: DMA channel + * @retval Priority of DMA channel see @ref md_dma_priority_t + */ +__STATIC_INLINE uint32_t md_dma_get_priority(uint32_t ch) +{ + return READ_BITS(DMA->CHANNEL[ch].CON, DMA_CON_CHPRI_MSK, DMA_CON_CHPRI_POSS); +} +/** + * @} + */ +/** @defgroup MD_DMA_Public_Functions_Group7 NDT + * @{ + */ +/** + * @brief Set the total numbers of DMA transfers + * @param ch: DMA channel + * @param n: The size of DMA transfers + * @retval None + */ +__STATIC_INLINE void md_dma_set_transfer_size(uint32_t ch, uint16_t n) +{ + MODIFY_REG(DMA->CHANNEL[ch].NDT, DMA_NDT_TNDT_MSK, n << DMA_NDT_TNDT_POSS); +} + +/** + * @brief Get the total numbers of DMA transfers + * @param ch: DMA channel + * @retval The size + */ +__STATIC_INLINE uint32_t md_dma_get_transfer_size(uint32_t ch) +{ + return READ_BITS(DMA->CHANNEL[ch].NDT, DMA_NDT_TNDT_MSK, DMA_NDT_TNDT_POSS); +} +/** + * @brief Get the total numbers of DMA remaining data transfers + * @param ch: DMA channel + * @retval The size + */ +__STATIC_INLINE uint32_t md_dma_get_remaining_size(uint32_t ch) +{ + return READ_BITS(DMA->CHANNEL[ch].NDT, DMA_NDT_NRDT_MSK, DMA_NDT_NRDT_POSS); +} +/** + * @} + */ + +/** @defgroup MD_DMA_Public_Functions_Group8 IFM + * @{ + */ +/** + * @brief Get DMA flag + * @param ch_flag: This parameter can be one or combined of the following values: + * @arg @ref MD_DMA_CH0_TC + * @arg @ref MD_DMA_CH0_HT + * @arg @ref MD_DMA_CH1_TC + * @arg @ref MD_DMA_CH1_HT + * @arg @ref MD_DMA_CH2_TC + * @arg @ref MD_DMA_CH2_HT + * @arg @ref MD_DMA_CH3_TC + * @arg @ref MD_DMA_CH3_HT + * @arg @ref MD_DMA_CH4_TC + * @arg @ref MD_DMA_CH4_HT + * @arg @ref MD_DMA_CH5_TC + * @arg @ref MD_DMA_CH5_HT + * @arg @ref MD_DMA_CH6_TC + * @arg @ref MD_DMA_CH6_HT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_is_active_flag(uint32_t ch_flag) +{ + return (READ_BIT(DMA->IFM, ch_flag) == ch_flag); +} +/** + * @brief Get DMA transfer complete flag + * @param ch: DMA channel + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_is_active_flag_tc(uint32_t ch) +{ + return md_dma_is_active_flag(MD_DMA_CH0_TC << (ch * 2)); +} +/** + * @brief Get DMA half transfer flag + * @param ch: DMA channel + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_is_active_flag_ht(uint32_t ch) +{ + return md_dma_is_active_flag(MD_DMA_CH0_HT << (ch * 2)); +} +/** + * @} + */ +/** @defgroup MD_DMA_Public_Functions_Group9 ICR + * @{ + */ +/** + * @brief Clear DMA flag + * @param ch_flag: This parameter can be one or combined of the following values: + * @arg @ref MD_DMA_CH0_TC + * @arg @ref MD_DMA_CH0_HT + * @arg @ref MD_DMA_CH1_TC + * @arg @ref MD_DMA_CH1_HT + * @arg @ref MD_DMA_CH2_TC + * @arg @ref MD_DMA_CH2_HT + * @arg @ref MD_DMA_CH3_TC + * @arg @ref MD_DMA_CH3_HT + * @arg @ref MD_DMA_CH4_TC + * @arg @ref MD_DMA_CH4_HT + * @arg @ref MD_DMA_CH5_TC + * @arg @ref MD_DMA_CH5_HT + * @arg @ref MD_DMA_CH6_TC + * @arg @ref MD_DMA_CH6_HT + * @retval None + */ +__STATIC_INLINE void md_dma_clear_flag(uint32_t ch_flag) +{ + SET_BIT(DMA->ICR, ch_flag); +} +/** + * @brief Clear DMA transfer complete flag + * @param ch: DMA channel + * @retval None + */ +__STATIC_INLINE void md_dma_clear_flag_tc(uint32_t ch) +{ + md_dma_clear_flag(MD_DMA_CH0_TC << (ch * 2)); +} +/** + * @brief Clear DMA half transfer flag + * @param ch: DMA channel + * @retval None + */ +__STATIC_INLINE void md_dma_clear_flag_ht(uint32_t ch) +{ + md_dma_clear_flag(MD_DMA_CH0_HT << (ch * 2)); +} + +/** + * @} + */ +/** @defgroup MD_DMA_Public_Functions_Group10 IER + * @{ + */ +/** + * @brief Enable DMA CHx interrupt + * @param ch_flag: This parameter can be one or combined of the following values: + * @arg @ref MD_DMA_CH0_TC + * @arg @ref MD_DMA_CH0_HT + * @arg @ref MD_DMA_CH1_TC + * @arg @ref MD_DMA_CH1_HT + * @arg @ref MD_DMA_CH2_TC + * @arg @ref MD_DMA_CH2_HT + * @arg @ref MD_DMA_CH3_TC + * @arg @ref MD_DMA_CH3_HT + * @arg @ref MD_DMA_CH4_TC + * @arg @ref MD_DMA_CH4_HT + * @arg @ref MD_DMA_CH5_TC + * @arg @ref MD_DMA_CH5_HT + * @arg @ref MD_DMA_CH6_TC + * @arg @ref MD_DMA_CH6_HT + * @retval None + */ +__STATIC_INLINE void md_dma_enable_it(uint32_t ch_flag) +{ + SET_BIT(DMA->IER, ch_flag); +} +/** + * @brief Enable DMA transfer complete interrupt + * @param ch: DMA channel + * @retval None + */ +__STATIC_INLINE void md_dma_enable_it_tc(uint32_t ch) +{ + md_dma_enable_it(MD_DMA_CH0_TC << (ch * 2)); +} +/** + * @brief Enable DMA half transfer interrupt + * @param ch: DMA channel + * @retval None + */ +__STATIC_INLINE void md_dma_enable_it_ht(uint32_t ch) +{ + md_dma_enable_it(MD_DMA_CH0_HT << (ch * 2)); +} +/** + * @} + */ +/** @defgroup MD_DMA_Public_Functions_Group11 IDR + * @{ + */ +/** + * @brief Disable DMA CHx interrupt + * @param ch_flag: This parameter can be one or combined of the following values: + * @arg @ref MD_DMA_CH0_TC + * @arg @ref MD_DMA_CH0_HT + * @arg @ref MD_DMA_CH1_TC + * @arg @ref MD_DMA_CH1_HT + * @arg @ref MD_DMA_CH2_TC + * @arg @ref MD_DMA_CH2_HT + * @arg @ref MD_DMA_CH3_TC + * @arg @ref MD_DMA_CH3_HT + * @arg @ref MD_DMA_CH4_TC + * @arg @ref MD_DMA_CH4_HT + * @arg @ref MD_DMA_CH5_TC + * @arg @ref MD_DMA_CH5_HT + * @arg @ref MD_DMA_CH6_TC + * @arg @ref MD_DMA_CH6_HT + * @retval None + */ +__STATIC_INLINE void md_dma_disable_it(uint32_t ch_flag) +{ + SET_BIT(DMA->IDR, ch_flag); +} +/** + * @brief Disable DMA transfer complete interrupt + * @param ch: DMA channel + * @retval None + */ +__STATIC_INLINE void md_dma_disable_it_tc(uint32_t ch) +{ + md_dma_disable_it(MD_DMA_CH0_TC << (ch * 2)); +} +/** + * @brief Disable DMA half transfer interrupt + * @param ch: DMA channel + * @retval None + */ +__STATIC_INLINE void md_dma_disable_it_ht(uint32_t ch) +{ + md_dma_disable_it(MD_DMA_CH0_HT << (ch * 2)); +} +/** + * @} + */ +/** @defgroup MD_DMA_Public_Functions_Group12 IVS + * @{ + */ +/** + * @brief Check if DMA CHx interrupt is enabled + * @param ch_flag: This parameter can be one or combined of the following values: + * @arg @ref MD_DMA_CH0_TC + * @arg @ref MD_DMA_CH0_HT + * @arg @ref MD_DMA_CH1_TC + * @arg @ref MD_DMA_CH1_HT + * @arg @ref MD_DMA_CH2_TC + * @arg @ref MD_DMA_CH2_HT + * @arg @ref MD_DMA_CH3_TC + * @arg @ref MD_DMA_CH3_HT + * @arg @ref MD_DMA_CH4_TC + * @arg @ref MD_DMA_CH4_HT + * @arg @ref MD_DMA_CH5_TC + * @arg @ref MD_DMA_CH5_HT + * @arg @ref MD_DMA_CH6_TC + * @arg @ref MD_DMA_CH6_HT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_is_enabled_it(uint32_t ch_flag) +{ + return (READ_BIT(DMA->IVS, ch_flag) == ch_flag); +} +/** + * @brief Check if DMA transfer complete interrupt is enabled + * @param ch: DMA channel + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_is_enabled_it_tc(uint32_t ch) +{ + return md_dma_is_enabled_it(MD_DMA_CH0_TC << (ch * 2)); +} +/** + * @brief Check if DMA half transfer interrupt is enabled + * @param ch: DMA channel + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_is_enabled_it_ht(uint32_t ch) +{ + return md_dma_is_enabled_it(MD_DMA_CH0_HT << (ch * 2)); +} +/** + * @} + */ +/** @defgroup MD_DMA_Public_Functions_Group13 RIF + * @{ + */ +/** + * @brief Check if DMA CHx interrupt is enabled + * @param ch_flag: This parameter can be one or combined of the following values: + * @arg @ref MD_DMA_CH0_TC + * @arg @ref MD_DMA_CH0_HT + * @arg @ref MD_DMA_CH1_TC + * @arg @ref MD_DMA_CH1_HT + * @arg @ref MD_DMA_CH2_TC + * @arg @ref MD_DMA_CH2_HT + * @arg @ref MD_DMA_CH3_TC + * @arg @ref MD_DMA_CH3_HT + * @arg @ref MD_DMA_CH4_TC + * @arg @ref MD_DMA_CH4_HT + * @arg @ref MD_DMA_CH5_TC + * @arg @ref MD_DMA_CH5_HT + * @arg @ref MD_DMA_CH6_TC + * @arg @ref MD_DMA_CH6_HT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_is_active_rif(uint32_t ch_flag) +{ + return (READ_BIT(DMA->RIF, ch_flag) == ch_flag); +} +/** + * @brief Check if DMA transfer complete interrupt is enabled + * @param ch: DMA channel + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_is_active_rif_tc(uint32_t ch) +{ + return md_dma_is_active_rif(MD_DMA_CH0_TC << (ch * 2)); +} +/** + * @brief Check if DMA half transfer interrupt is enabled + * @param ch: DMA channel + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_is_active_rif_ht(uint32_t ch) +{ + return md_dma_is_active_rif(MD_DMA_CH0_HT << (ch * 2)); +} +/** + * @} + */ +/** @defgroup MD_DMA_Public_Functions_Group14 DMA_CH_SELCON + * @{ + */ +/** + * @brief Set channel msel + * @param ch: DMA channel + * @param msel: This parameter can be one of the @ref md_dma_msel_t + * @retval None + */ +__STATIC_INLINE void md_dma_set_channel_msel(uint32_t ch, uint32_t msel) +{ + MODIFY_REG(DMA_MUX->CH_SELCON[ch], DMA_SELCON_MSEL_MSK, msel << DMA_SELCON_MSEL_POSS); +} + +/** + * @brief get channel msel + * @param ch: DMA channel + * @retval The msel, see @ref md_dma_msel_t + */ +__STATIC_INLINE uint32_t md_dma_get_channel_msel(uint32_t ch) +{ + return READ_BITS(DMA_MUX->CH_SELCON[ch], DMA_SELCON_MSEL_MSK, DMA_SELCON_MSEL_POSS); +} + +/** + * @brief Set channel msigsel + * @param ch: DMA channel + * @param msigsel: This parameter can be one of the @ref md_dma_msigsel_t + * @retval None + */ +__STATIC_INLINE void md_dma_set_channel_msigsel(uint32_t ch, uint32_t msigsel) +{ + MODIFY_REG(DMA_MUX->CH_SELCON[ch], DMA_SELCON_MSIGSEL_MSK, msigsel << DMA_SELCON_MSIGSEL_POSS); +} + +/** + * @brief get channel msigsel + * @param ch: DMA channel + * @retval The msigsel, see @ref md_dma_msigsel_t + */ +__STATIC_INLINE uint32_t md_dma_get_channel_msigsel(uint32_t ch) +{ + return READ_BITS(DMA_MUX->CH_SELCON[ch], DMA_SELCON_MSIGSEL_MSK, DMA_SELCON_MSIGSEL_POSS); +} +/** + * @} + */ +/** @defgroup MD_DMA_Public_Functions_Group1 Initialization + * @{ + */ +void md_dma_reset(void); +void md_dma_init(uint32_t ch, md_dma_config_t *config); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __MD_DMA_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_gpio.c b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_gpio.c new file mode 100644 index 0000000000..a6aeda6bc3 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_gpio.c @@ -0,0 +1,180 @@ +/********************************************************************************** + * + * @file md_gpio.c + * @brief GPIO module driver. + * + * @date 13 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 13 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_gpio.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ + +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @addtogroup MD_GPIO + * @{ + */ + +/** @addtogroup MD_GPIO_Public_Functions + * @{ + */ +/** @addtogroup MD_GPIO_Public_Functions_Group1 + * @{ + */ +/** + * @brief Initialize the GPIOx peripheral according to the specified + * parameters in the gpio_init_t. + * @param GPIOx: Where x can be (A--B) to select the GPIO peripheral. + * @param pin: The pin which need to initialize. + * @param init: Pointer to a md_gpio_init_t structure that can contains + * the configuration information for the specified parameters. + * @retval None + */ +void md_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, md_gpio_init_t *init) +{ + uint32_t i, pos, mask, tmp; + + for (i = 0; i < 16; ++i) + { + if (((pin >> i) & 0x1) == 0) + continue; + + /* Get position and 1-bit mask */ + pos = i; + mask = 0x1 << pos; + + /* Set PIN filter enable or disable */ + tmp = READ_REG(GPIOx->FLT); + tmp &= ~mask; + tmp |= (init->flt << pos); + WRITE_REG(GPIOx->FLT, tmp); + + /* Set PIN type ttl or smit */ + tmp = READ_REG(GPIOx->TYPE); + tmp &= ~mask; + tmp |= (init->type << pos); + WRITE_REG(GPIOx->TYPE, tmp); + + /* Configure PIN function */ + pos = i < 8 ? (i << 2) : ((i - 8) << 2); + mask = 0xF << pos; + tmp = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1); + tmp &= ~mask; + tmp |= (init->func << pos); + i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp); + + /* Get position and 2-bits mask */ + pos = i << 1; + mask = 0x3 << pos; + + /* Set PIN mode */ + tmp = READ_REG(GPIOx->MODE); + tmp &= ~mask; + tmp |= (init->mode << pos); + WRITE_REG(GPIOx->MODE, tmp); + + /* Set PIN open-drain or push-pull */ + tmp = READ_REG(GPIOx->OD); + tmp &= ~mask; + tmp |= (init->odos << pos); + WRITE_REG(GPIOx->OD, tmp); + + /* Set PIN push-up or/and push-down */ + tmp = READ_REG(GPIOx->PUPD); + tmp &= ~mask; + tmp |= (init->pupd << pos); + WRITE_REG(GPIOx->PUPD, tmp); + + /* Set PIN output P-MOS driver */ + tmp = READ_REG(GPIOx->ODRV); + tmp &= ~mask; + tmp |= (init->odrv << pos); + WRITE_REG(GPIOx->ODRV, tmp); + } + + return; +} + +/** + * @brief Initialize the GPIOx peripheral using the default parameters. + * @param init: Pointer to a md_gpio_init_t structure + * @retval None + */ +void md_gpio_init_struct(md_gpio_init_t *init) +{ + /* Fill md_gpio_init_t structure with default parameter */ + init->mode = MD_GPIO_MODE_OUTPUT; + init->odos = MD_GPIO_PUSH_PULL; + init->pupd = MD_GPIO_PUSH_UP; + init->odrv = MD_GPIO_OUT_DRIVE_NORMAL; + init->flt = MD_GPIO_FILTER_DISABLE; + init->type = MD_GPIO_TYPE_CMOS; + init->func = MD_GPIO_FUNC_1; + + return; +} + +/** + * @brief Set or clear the select Pin data. + * @param GPIOx: Where x can be (A--B) to select the GPIO peripheral. + * @param pin: The specified pin to be written. + * @param val: The specifies value to be written. + * @retval None + */ +void md_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val) +{ + if ((val & (0x01)) == 0x00) + GPIOx->BSRR = pin << 16U; + else + GPIOx->BSRR = pin; + + return; +} + +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_gpio.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_gpio.h new file mode 100644 index 0000000000..7ed04e164d --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_gpio.h @@ -0,0 +1,1704 @@ +/********************************************************************************** + * + * @file md_gpio.h + * @brief Header file of GPIO module driver. + * + * @date 08 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 08 July 2022 Lisq the first version + * 1 Dec 2023 Zhuxf Improve the timing of md_gpio_clear_flag + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + + +#ifndef __MD_GPIO_H__ +#define __MD_GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_utils.h" + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Variables -------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_GPIO GPIO + * @brief GPIO micro driver + * @{ + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** + * @defgroup MD_GPIO_Public_Macros GPIO Public Macros + * @{ + */ +#define MD_GPIO_PIN_0 0x0001U +#define MD_GPIO_PIN_1 0x0002U +#define MD_GPIO_PIN_2 0x0004U +#define MD_GPIO_PIN_3 0x0008U +#define MD_GPIO_PIN_4 0x0010U +#define MD_GPIO_PIN_5 0x0020U +#define MD_GPIO_PIN_6 0x0040U +#define MD_GPIO_PIN_7 0x0080U +#define MD_GPIO_PIN_8 0x0100U +#define MD_GPIO_PIN_9 0x0200U +#define MD_GPIO_PIN_10 0x0400U +#define MD_GPIO_PIN_11 0x0800U +#define MD_GPIO_PIN_12 0x1000U +#define MD_GPIO_PIN_13 0x2000U +#define MD_GPIO_PIN_14 0x4000U +#define MD_GPIO_PIN_15 0x8000U + +#define MD_GPIO_PIN_MUL(pin) ((pin) * (pin)) +#define MD_GPIO_PIN_TWO_0_MSK(pin) (MD_GPIO_PIN_MUL(pin)) +#define MD_GPIO_PIN_TWO_1_MSK(pin) (MD_GPIO_PIN_MUL(pin) << 1) +#define MD_GPIO_PIN_TWO_MSK(pin) ((MD_GPIO_PIN_TWO_0_MSK(pin)) | (MD_GPIO_PIN_TWO_1_MSK(pin))) +/** + * @} + */ +/** + * @defgroup GPIO_MD_Public_Types GPIO Public Types + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** + * @brief GPIO mode + */ +typedef enum +{ + MD_GPIO_MODE_CLOSE = 0x0U, /**< Digital close Analog open */ + MD_GPIO_MODE_INPUT = 0x1U, /**< Input */ + MD_GPIO_MODE_OUTPUT = 0x2U, /**< Output */ +} md_gpio_mode_t; + +/** + * @brief GPIO open-drain or push-pull + */ +typedef enum +{ + MD_GPIO_PUSH_PULL = 0x0U, /**< Push-Pull */ + MD_GPIO_OPEN_DRAIN = 0x2U, /**< Open-Drain. Can't output high level */ +} md_gpio_odos_t; + +/** + * @brief GPIO push-up or push-down + */ +typedef enum +{ + MD_GPIO_FLOATING = 0x0U, /**< Floating */ + MD_GPIO_PUSH_UP = 0x1U, /**< Push-Up */ + MD_GPIO_PUSH_DOWN = 0x2U, /**< Push-Down */ + MD_GPIO_PUSH_UP_DOWN = 0x3U, /**< Push-Up and Push-Down */ +} md_gpio_push_t; + +/** + * @brief GPIO output drive + */ +typedef enum +{ + MD_GPIO_OUT_DRIVE_NORMAL = 0x0U, /**< Normal current flow */ + MD_GPIO_OUT_DRIVE_STRONG = 0x1U, /**< Strong current flow */ +} md_gpio_out_drive_t; + +/** + * @brief GPIO filter + */ +typedef enum +{ + MD_GPIO_FILTER_DISABLE = 0x0U, /**< Disable filter */ + MD_GPIO_FILTER_ENABLE = 0x1U, /**< Enable filter */ +} md_gpio_filter_t; + +/** + * @brief GPIO type + */ +typedef enum +{ + MD_GPIO_TYPE_CMOS = 0x0U, /**< CMOS Type */ + MD_GPIO_TYPE_TTL = 0x1U, /**< TTL Type */ +} md_gpio_type_t; + +/** + * @brief GPIO functions + */ +typedef enum +{ + MD_GPIO_FUNC_0 = 0U, /**< function #0 */ + MD_GPIO_FUNC_1 = 1U, /**< function #1 */ + MD_GPIO_FUNC_2 = 2U, /**< function #2 */ + MD_GPIO_FUNC_3 = 3U, /**< function #3 */ + MD_GPIO_FUNC_4 = 4U, /**< function #4 */ + MD_GPIO_FUNC_5 = 5U, /**< function #5 */ + MD_GPIO_FUNC_6 = 6U, /**< function #6 */ + MD_GPIO_FUNC_7 = 7U, /**< function #7 */ +} md_gpio_func_t; + + +/** + * @brief GPIO Init Structure definition + */ +typedef struct +{ + md_gpio_mode_t mode; /**< Specifies the operating mode for the selected pins. + This parameter can be any value of @ref md_gpio_mode_t */ + md_gpio_odos_t odos; /**< Specifies the Open-Drain or Push-Pull for the selected pins. + This parameter can be a value of @ref md_gpio_odos_t */ + md_gpio_push_t pupd; /**< Specifies the Pull-up or Pull-Down for the selected pins. + This parameter can be a value of @ref md_gpio_push_t */ + md_gpio_out_drive_t odrv; /**< Specifies the output P-MOS driver for the selected pins. + This parameter can be a value of @ref md_gpio_out_drive_t */ + md_gpio_filter_t flt; /**< Specifies the input filter for the selected pins. + This parameter can be a value of @ref md_gpio_filter_t */ + md_gpio_type_t type; /**< Specifies the type for the selected pins. + This parameter can be a value of @ref md_gpio_type_t */ + md_gpio_func_t func; /**< Specifies the function for the selected pins. + This parameter can be a value of @ref md_gpio_func_t */ +} md_gpio_init_t; +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @defgroup MD_GPIO_Public_Functions GPIO Public Functions + * @{ + */ +/** @defgroup MD_GPIO_Public_Functions_Group2 DIN + * @{ + */ +/** + * @brief Gets data of the pin when it's mode is input. + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Input data: + * - 0: Low level + * - 1: High level + */ +__STATIC_INLINE uint8_t md_gpio_get_input_data(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + return (READ_BIT(GPIOx->DIN, pin) == pin); +} +/** + * @} + */ +/** @defgroup MD_GPIO_Public_Functions_Group3 DOUT + * @{ + */ +/** + * @brief Output high level + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_high(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + GPIOx->BSRR = pin; +} + +/** + * @brief Output low level + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_low(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + GPIOx->BSRR = pin << 16U; +} + +/** + * @brief Gets output level + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Output level: + * - 0: Low level + * - 1: High level + */ +__STATIC_INLINE uint8_t md_gpio_get_pin_output_level(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + return (READ_BIT(GPIOx->DOUT, pin) == pin); +} +/** + * @} + */ +/** @defgroup MD_GPIO_Public_Functions_Group4 BIR + * @{ + */ +/** + * @brief Toggle output level + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_toggle_pin_output(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + GPIOx->BIR = pin; +} +/** + * @} + */ +/** @defgroup MD_GPIO_Public_Functions_Group5 MODE + * @{ + */ +/** + * @brief Sets input mode of the pin + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_mode_input(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + CLEAR_BIT(GPIOx->MODE, MD_GPIO_PIN_TWO_1_MSK(pin)); + SET_BIT(GPIOx->MODE, MD_GPIO_PIN_TWO_0_MSK(pin)); +} + +/** + * @brief Sets output mode of the pin + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_mode_output(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + SET_BIT(GPIOx->MODE, MD_GPIO_PIN_TWO_1_MSK(pin)); +} + +/** + * @brief Gets input/output mode of the pin + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Input/output mode, see @ref md_gpio_mode_t + */ +__STATIC_INLINE uint8_t md_gpio_get_pin_mode(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + if (READ_BIT(GPIOx->MODE, MD_GPIO_PIN_TWO_1_MSK(pin))) + return MD_GPIO_MODE_OUTPUT; + + if (READ_BIT(GPIOx->MODE, MD_GPIO_PIN_TWO_0_MSK(pin))) + return MD_GPIO_MODE_INPUT; + + return MD_GPIO_MODE_CLOSE; +} +/** + * @} + */ +/** @defgroup MD_GPIO_Public_Functions_Group6 OD + * @{ + */ +/** + * @brief Sets Push-Pull of the pin + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_push_pull(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + CLEAR_BIT(GPIOx->OD, MD_GPIO_PIN_TWO_1_MSK(pin)); +} + +/** + * @brief Sets Open-Drain of the pin + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_open_drain(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + SET_BIT(GPIOx->OD, MD_GPIO_PIN_TWO_1_MSK(pin)); + CLEAR_BIT(GPIOx->OD, MD_GPIO_PIN_TWO_0_MSK(pin)); +} + +/** + * @brief Sets Open-Source of the pin + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_open_source(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + SET_BIT(GPIOx->OD, MD_GPIO_PIN_TWO_MSK(pin)); +} + +/** + * @brief Gets ODOS status of the pin + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval ODOS status, see @ref md_gpio_odos_t + */ +__STATIC_INLINE uint8_t md_gpio_get_pin_odos(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + if (!(READ_BIT(GPIOx->OD, MD_GPIO_PIN_TWO_1_MSK(pin)))) + return MD_GPIO_PUSH_PULL; + + return MD_GPIO_OPEN_DRAIN; +} +/** + * @} + */ +/** @defgroup MD_GPIO_Public_Functions_Group7 PUPD + * @{ + */ +/** + * @brief Sets Floating of the pin + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_floating(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + CLEAR_BIT(GPIOx->PUPD, MD_GPIO_PIN_TWO_MSK(pin)); +} + +/** + * @brief Sets Push-Up of the pin + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_push_up(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + SET_BIT(GPIOx->PUPD, MD_GPIO_PIN_TWO_0_MSK(pin)); + CLEAR_BIT(GPIOx->PUPD, MD_GPIO_PIN_TWO_1_MSK(pin)); +} + +/** + * @brief Sets Push-Down of the pin + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_push_down(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + SET_BIT(GPIOx->PUPD, MD_GPIO_PIN_TWO_1_MSK(pin)); + CLEAR_BIT(GPIOx->PUPD, MD_GPIO_PIN_TWO_0_MSK(pin)); +} + +/** + * @brief Sets Push-Up and Push-Down of the pin + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_push_up_down(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + SET_BIT(GPIOx->PUPD, MD_GPIO_PIN_TWO_MSK(pin)); +} + +/** + * @brief Gets PUPD status of the pin + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval PUPD status, see @ref md_gpio_push_t + */ +__STATIC_INLINE uint8_t md_gpio_get_pin_pupd(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + if ((!(READ_BIT(GPIOx->PUPD, MD_GPIO_PIN_TWO_1_MSK(pin)))) + && (!(READ_BIT(GPIOx->PUPD, MD_GPIO_PIN_TWO_0_MSK(pin))))) + return MD_GPIO_FLOATING; + + if ((!(READ_BIT(GPIOx->PUPD, MD_GPIO_PIN_TWO_1_MSK(pin)))) + && (READ_BIT(GPIOx->PUPD, MD_GPIO_PIN_TWO_0_MSK(pin)))) + return MD_GPIO_PUSH_UP; + + if ((READ_BIT(GPIOx->PUPD, MD_GPIO_PIN_TWO_1_MSK(pin))) + && (!(READ_BIT(GPIOx->PUPD, MD_GPIO_PIN_TWO_0_MSK(pin))))) + return MD_GPIO_PUSH_DOWN; + + return MD_GPIO_PUSH_UP_DOWN; +} +/** + * @} + */ +/** @defgroup MD_GPIO_Public_Functions_Group9 ODRV + * @{ + */ +/** + * @brief Sets Normal-Drive of the pin + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_drive_normal(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + CLEAR_BIT(GPIOx->ODRV, MD_GPIO_PIN_TWO_MSK(pin)); +} + +/** + * @brief Sets Strong-Drive of the pin + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_drive_strong(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + CLEAR_BIT(GPIOx->ODRV, MD_GPIO_PIN_TWO_1_MSK(pin)); + SET_BIT(GPIOx->ODRV, MD_GPIO_PIN_TWO_0_MSK(pin)); +} + +/** + * @brief Gets ODRV status of the pin + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval ODRV status, see @ref md_gpio_out_drive_t + */ +__STATIC_INLINE uint8_t md_gpio_get_pin_odrv(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + if ((!(READ_BIT(GPIOx->ODRV, MD_GPIO_PIN_TWO_1_MSK(pin)))) + && (!(READ_BIT(GPIOx->ODRV, MD_GPIO_PIN_TWO_0_MSK(pin))))) + return MD_GPIO_OUT_DRIVE_NORMAL; + + if ((!(READ_BIT(GPIOx->ODRV, MD_GPIO_PIN_TWO_1_MSK(pin)))) + && (READ_BIT(GPIOx->ODRV, MD_GPIO_PIN_TWO_0_MSK(pin)))) + return MD_GPIO_OUT_DRIVE_STRONG; + + return MD_GPIO_OUT_DRIVE_NORMAL; +} +/** + * @} + */ +/** @defgroup MD_GPIO_Public_Functions_Group10 FLT + * @{ + */ +/** + * @brief Enable filter + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_enable_pin_filter(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + SET_BIT(GPIOx->FLT, pin); +} + +/** + * @brief Disable filter + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_disable_pin_filter(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + CLEAR_BIT(GPIOx->FLT, pin); +} + +/** + * @brief Check if the filter is enabled + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval ENABLE/DISABLE + */ +__STATIC_INLINE uint8_t md_gpio_is_enabled_pin_filter(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + if (READ_BIT(GPIOx->FLT, pin) == pin) + return ENABLE; + + return DISABLE; +} +/** + * @} + */ +/** @defgroup MD_GPIO_Public_Functions_Group11 TYPE + * @{ + */ +/** + * @brief Sets CMOS type + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_type_cmos(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + CLEAR_BIT(GPIOx->TYPE, pin); +} + +/** + * @brief Sets TTL type + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_type_ttl(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + SET_BIT(GPIOx->TYPE, pin); +} + +/** + * @brief Gets type of the pin + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval ODRV status, see @ref md_gpio_type_t + */ +__STATIC_INLINE uint8_t md_gpio_get_pin_type(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + if (READ_BIT(GPIOx->TYPE, pin) == pin) + return MD_GPIO_TYPE_TTL; + + return MD_GPIO_TYPE_CMOS; +} +/** + * @} + */ +/** @defgroup MD_GPIO_Public_Functions_Group12 FUNC + * @{ + */ +/** + * @brief Sets function of the pin + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @param func: Function of the pin, see @ref md_gpio_func_t. + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_function(GPIO_TypeDef *GPIOx, uint32_t pin, md_gpio_func_t func) +{ + uint32_t i, pos, mask, tmp; + + for (i = 0; i < 16; ++i) + { + if (((pin >> i) & 0x1) == 1) + break; + } + + if (i == 16) + return; + + pos = i < 8 ? (i << 2) : ((i - 8) << 2); + mask = 0xF << pos; + tmp = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1); + tmp &= ~mask; + tmp |= (func << pos); + i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp); +} + +/** + * @brief Gets Function of the pin + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Function, see @ref md_gpio_func_t + */ +__STATIC_INLINE uint8_t md_gpio_get_pin_function(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + uint32_t i, pos, mask; + + for (i = 0; i < 16; ++i) + { + if (((pin >> i) & 0x1) == 1) + break; + } + + pos = i < 8 ? (i << 2) : ((i - 8) << 2); + pos = pos > 28 ? 28 : pos; + mask = (uint32_t)(0xF << pos); + + if (i < 8) + return READ_BITS(GPIOx->FUNC0, mask, pos); + else + return READ_BITS(GPIOx->FUNC1, mask, pos); +} +/** + * @} + */ +/** @defgroup MD_GPIO_Public_Functions_Group13 LOCK + * @{ + */ +/** + * @brief Lock the pin + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + MODIFY_REG(GPIOx->LOCK, GPIO_LOCK_KEY_MSK, 0x55AA << GPIO_LOCK_KEY_POSS); + SET_BIT(GPIOx->LOCK, pin); +} + +/** + * @brief Gets Lock status the pin + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Lock status: + * - 0: Unlock + * - 1: Lock + */ +__STATIC_INLINE uint8_t md_gpio_get_lock(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + if (READ_BIT(GPIOx->LOCK, pin) == pin) + return 1; + + return 0; +} +/** + * @} + */ +/** @defgroup MD_GPIO_Public_Functions_Group14 EXTIRER + * @{ + */ +/** + * @brief Enable trigger rising edge + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_enable_riging_edge_trigger(uint32_t pin) +{ + SET_BIT(EXTI->EXTIRER, pin); +} + +/** + * @brief Disable trigger rising edge + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_disable_riging_edge_trigger(uint32_t pin) +{ + CLEAR_BIT(EXTI->EXTIRER, pin); +} + +/** + * @brief Check if rising edge trigger is enabled + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval ENABLE/DISABLE + */ +__STATIC_INLINE uint8_t md_gpio_is_enabled_riging_edge_trigger(uint32_t pin) +{ + if (READ_BIT(EXTI->EXTIRER, pin) == pin) + return ENABLE; + + return DISABLE; +} +/** + * @} + */ +/** @defgroup MD_GPIO_Public_Functions_Group15 EXTIFER + * @{ + */ +/** + * @brief Enable trigger trailing edge + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_enable_trailing_edge_trigger(uint32_t pin) +{ + SET_BIT(EXTI->EXTIFER, pin); +} + +/** + * @brief Disable trigger trailing edge + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_disable_trailing_edge_trigger(uint32_t pin) +{ + CLEAR_BIT(EXTI->EXTIFER, pin); +} + +/** + * @brief Check if trailing edge trigger is enabled + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval ENABLE/DISABLE + */ +__STATIC_INLINE uint8_t md_gpio_is_enabled_trailing_edge_trigger(uint32_t pin) +{ + if (READ_BIT(EXTI->EXTIFER, pin) == pin) + return ENABLE; + + return DISABLE; +} +/** + * @} + */ +/** @defgroup MD_GPIO_Public_Functions_Group16 EXTIEN + * @{ + */ +/** + * @brief Enable external interrupt + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_enable_external_interrupt(uint32_t pin) +{ + SET_BIT(EXTI->EXTIEN, pin); +} + +/** + * @brief Disable external interrupt + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_disable_external_interrupt(uint32_t pin) +{ + CLEAR_BIT(EXTI->EXTIEN, pin); +} + +/** + * @brief Check if external interrupt is enabled + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval ENABLE/DISABLE + */ +__STATIC_INLINE uint8_t md_gpio_is_enabled_external_interrupt(uint32_t pin) +{ + if (READ_BIT(EXTI->EXTIEN, pin) == pin) + return ENABLE; + + return DISABLE; +} +/** + * @} + */ +/** @defgroup MD_GPIO_Public_Functions_Group17 EXTIFLAG + * @{ + */ +/** + * @brief Gets status of flag + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Status. + */ +__STATIC_INLINE uint8_t md_gpio_get_flag(uint32_t pin) +{ + if (READ_BIT(EXTI->EXTIFLAG, pin) == pin) + return 1; + + return 0; +} +/** + * @} + */ +/** @defgroup MD_GPIO_Public_Functions_Group18 EXTICFR + * @{ + */ +/** + * @brief Clear status of flag + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Status. + */ +__STATIC_INLINE void md_gpio_clear_flag(uint32_t pin) +{ + if (READ_BIT(EXTI->EXTIFER, pin)) + { + CLEAR_BIT(EXTI->EXTIFER, pin); + SET_BIT(EXTI->EXTIFER, pin); + } + + if (READ_BIT(EXTI->EXTIRER, pin)) + { + CLEAR_BIT(EXTI->EXTIRER, pin); + SET_BIT(EXTI->EXTIRER, pin); + } + + WRITE_REG(EXTI->EXTICFR, pin); +} +/** + * @} + */ +/** @defgroup MD_GPIO_Public_Functions_Group19 EXTIPSR + * @{ + */ +/** + * @brief Sets port of the interrup + * @param GPIOx: GPIO Port + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_interrupt_port(GPIO_TypeDef *GPIOx, uint32_t pin) +{ + uint8_t i, port; + + if (GPIOx == GPIOA) + port = 0; + else if (GPIOx == GPIOB) + port = 1; + else if (GPIOx == GPIOC) + port = 2; + else if (GPIOx == GPIOD) + port = 3; + else + port = 0; + + /* Get Pin index */ + for (i = 0; i < 16; ++i) + { + if (((pin >> i) & 0x1) == 0x1) + break; + } + + if (i <= 7) + { + EXTI->EXTIPSR0 &= ~(0xfU << (i * 4)); + EXTI->EXTIPSR0 |= (port << (i * 4)); + } + else + { + i -= 8; + EXTI->EXTIPSR1 &= ~(0xfU << (i * 4)); + EXTI->EXTIPSR1 |= (port << (i * 4)); + } +} + +/** + * @brief Gets port of the interrup + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval GPIO port: + * - 0x0: GPIOA + * - 0X1: GPIOB + * - 0x2: GPIOC + * - 0X3: GPIOD + * - 0x4: GPIOE + * - 0X5: GPIOF + * - 0x6: GPIOG + * - 0X7: GPIOH + */ +__STATIC_INLINE uint8_t md_gpio_get_interrupt_port(uint32_t pin) +{ + uint8_t i, port; + + /* Get Pin index */ + for (i = 0; i < 16; ++i) + { + if (((pin >> i) & 0x1) == 0x1) + break; + } + + if (i <= 7) + { + port = READ_BITS(EXTI->EXTIPSR0, (0xf << (i * 4)), (i * 4)); + } + else + { + i -= 8; + port = READ_BITS(EXTI->EXTIPSR1, (0xf << (i * 4)), (i * 4)); + } + + return port; +} +/** + * @} + */ +/** @defgroup MD_GPIO_Public_Functions_Group20 EXTIFLTCR + * @{ + */ +/** + * @brief Enable filter + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_interrupt_filter_enable(uint32_t pin) +{ + SET_BIT(EXTI->EXTIFLTCR, pin); +} + +/** + * @brief Disable filter + * @param pin: This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval None + */ +__STATIC_INLINE void md_gpio_interrupt_filter_disable(uint32_t pin) +{ + CLEAR_BIT(EXTI->EXTIFLTCR, pin); +} + +/** + * @brief Check if filter is enabled or disabled. + * @retval Status: + * - 0: Disable + * - NOT_0: Enable + */ +__STATIC_INLINE uint32_t md_gpio_interrupt_filter_is_enable(uint32_t pin) +{ + return (READ_BIT(EXTI->EXTIFLTCR, pin) == pin); +} + +/** + * @brief Set filter time + * @param time: Filter time, ((time + 1) * 2)CLOCK + * @retval None + */ +__STATIC_INLINE void md_gpio_interrupt_filter_time_set(uint8_t time) +{ + MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTSEL_MSK, time << GPIO_EXTIFLTCR_FLTSEL_POSS); +} + +/** + * @brief Get filter time + * @retval Filter time + */ +__STATIC_INLINE uint32_t md_gpio_interrupt_filter_time_get(void) +{ + return READ_BITS(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTSEL_MSK, GPIO_EXTIFLTCR_FLTSEL_POSS); +} + +/** + * @} + */ +/** @defgroup MD_GPIO_Public_Functions_Group1 Initialization + * @{ + */ +extern void md_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, md_gpio_init_t *init); +extern void md_gpio_init_struct(md_gpio_init_t *init); +extern void md_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __MD_GPIO_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_i2c.c b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_i2c.c new file mode 100644 index 0000000000..31173c144b --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_i2c.c @@ -0,0 +1,216 @@ +/********************************************************************************** + * + * @file md_i2c.c + * @brief I2C module driver. + * + * @date 13 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 13 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ +#include +#include "md_i2c.h" +#include "md_cmu.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ + +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ +/** @defgroup MD_I2C I2C + * @{ + */ + +/** @addtogroup MD_I2C_Public_Functions + * @{ + */ + +/** @addtogroup MD_I2C_Public_Functions_Group1 + * @{ + */ +/** + * @brief I2C Configuration Speed function. + * @param I2Cx: I2C instance. + * @param init: Pointer to a i2c_init_t structure that contains + * the configuration information for the specified I2C. + * @param clk: I2C Peripheral bus clock + * @retval Status, see @ref md_status_t. + */ +static void _i2c_speed_init(I2C_TypeDef *I2Cx, md_i2c_init_t *init, uint32_t clk) +{ + int32_t t_scl, t_pre, tmp; + + if (init->module == MD_I2C_MODULE_SLAVE) + { + init->clk_speed = 450000UL; + } + + if (init->clk_speed <= 100000UL) + { + tmp = clk / 4000000UL; + clk = (tmp >= 16UL) ? (clk >> 4UL) : 4000000UL; + } + else + { + tmp = clk / 8000000UL; + clk = (tmp >= 16UL) ? (clk >> 4UL) : 8000000UL; + } + + tmp = tmp >= 16UL ? 15UL : tmp; + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_PRESC_MSK, tmp << I2C_TIMINGR_PRESC_POSS); + + t_scl = 1000000000 / init->clk_speed; + t_pre = 1000000000 / clk; + + tmp = (t_scl * 10) / (t_pre << 1UL); + tmp = (tmp % 10) >= 5 ? (tmp / 10 + 1) : tmp / 10; + tmp = tmp >= 255UL ? 255UL : tmp; + + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SCLL_MSK, (tmp - 1UL) << I2C_TIMINGR_SCLL_POSS); + + if (init->clk_speed > 100000UL) + { + if ((tmp - 1UL) > 3UL) + { + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, ((tmp - 1UL) / 3UL) << I2C_TIMINGR_SCLDEL_POSS); + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL_MSK, ((((tmp - 1UL) / 3UL) >= 3) ? 3 : (((tmp - 1UL) / 3UL) % 3)) << I2C_TIMINGR_SDADEL_POSS); + } + else + { + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, 1UL << I2C_TIMINGR_SCLDEL_POSS); + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL_MSK, 1UL << I2C_TIMINGR_SDADEL_POSS); + } + } + else + { + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL_MSK, 2UL << I2C_TIMINGR_SDADEL_POSS); + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, 4UL << I2C_TIMINGR_SCLDEL_POSS); + } + + tmp = t_scl - (tmp + READ_BITS(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, I2C_TIMINGR_SCLDEL_POSS) + \ + READ_BITS(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL_MSK, I2C_TIMINGR_SDADEL_POSS) + 1UL) * t_pre; + + tmp = (tmp * 10) / t_pre; + tmp = (tmp % 10) >= 5 ? (tmp / 10 + 1) : tmp / 10; + tmp = tmp >= 255UL ? 255UL : tmp; + /* tscll >= 3*tsclh */ + tmp = (tmp - 1) <= (READ_BITS(I2Cx->TIMINGR, I2C_TIMINGR_SCLL_MSK, I2C_TIMINGR_SCLL_POSS) / 3) ? (READ_BITS(I2Cx->TIMINGR, I2C_TIMINGR_SCLL_MSK, I2C_TIMINGR_SCLL_POSS) / 3) + 1 : tmp; + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SCLH_MSK, (tmp - 1UL) << I2C_TIMINGR_SCLH_POSS); + +} + +/** + * @brief Initializes the I2C according to the specified parameters + * in the i2c_init_t and initialize the associated handle. + * @param I2Cx: I2C instance. + * @param init: Pointer to a i2c_init_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref md_status_t. + */ +md_status_t md_i2c_init(I2C_TypeDef *I2Cx, md_i2c_init_t *init) +{ + uint32_t freq; + + if ((I2Cx == NULL) || (init == NULL)) + return MD_ERROR; + + freq = md_cmu_get_pclk_clock(); + MD_I2C_DISABLE(I2Cx); + + _i2c_speed_init(I2Cx, init, freq); + MODIFY_REG(I2Cx->CON1, I2C_CON1_NOSTRETCH_MSK, (init->no_stretch) << I2C_CON1_NOSTRETCH_POS); + MODIFY_REG(I2Cx->CON1, I2C_CON1_GCEN_MSK, (init->general_call) << I2C_CON1_GCEN_POS); + + if (init->dual_addr == MD_I2C_DUALADDR_ENABLE) + { + CLEAR_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1EN_MSK); + MODIFY_REG(I2Cx->ADDR1, I2C_ADDR1_OA1_MSK, (init->own_addr1 & 0x3FF) << I2C_ADDR1_OA1_POSS); + SET_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1EN_MSK); + + CLEAR_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2EN_MSK); + MODIFY_REG(I2Cx->ADDR2, I2C_ADDR2_OA2_MSK, (init->own_addr2 & 0x7F) << I2C_ADDR2_OA2_POSS); + SET_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2EN_MSK); + } + else + { + if (init->addr_mode == MD_I2C_ADDR_10BIT) + { + CLEAR_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1EN_MSK); + SET_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1MODE_MSK); + MODIFY_REG(I2Cx->ADDR1, I2C_ADDR1_OA1_MSK, (init->own_addr1 & 0x3FF) << I2C_ADDR1_OA1_POSS); + SET_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1EN_MSK); + } + else + { + CLEAR_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2EN_MSK); + MODIFY_REG(I2Cx->ADDR2, I2C_ADDR2_OA2_MSK, (init->own_addr2 & 0x7F) << I2C_ADDR2_OA2_POSS); + SET_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2EN_MSK); + } + } + + MD_I2C_ENABLE(I2Cx); + return MD_OK; +} + +/** + * @brief Set each @ref md_i2c_init_t field to default value. + * @param init Pointer to a @ref md_i2c_init_t structure. + * @retval None + */ +void md_i2c_struct_init(md_i2c_init_t *init) +{ + init->module = MD_I2C_MODULE_MASTER; + init->clk_speed = MD_I2C_STANDARD_MODE_MAX_CLK; + init->own_addr1 = 0xA0; + init->addr_mode = MD_I2C_ADDR_7BIT; + init->dual_addr = MD_I2C_DUALADDR_DISABLE; + init->own_addr2 = 0x0; + init->general_call = MD_I2C_GENERALCALL_DISABLE; + init->no_stretch = MD_I2C_NOSTRETCH_ENABLE; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_i2c.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_i2c.h new file mode 100644 index 0000000000..da0ccf1b4e --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_i2c.h @@ -0,0 +1,2454 @@ +/********************************************************************************** + * + * @file md_i2c.h + * @brief Header file of I2C module driver. + * + * @date 13 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 13 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __MD_I2C_H__ +#define __MD_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_utils.h" + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Variables -------------------------------------------------------- */ + +/** + * @addtogroup Micro_Driver + * @{ + */ +/** + * @defgroup MD_I2C I2C + * @brief I2C micro driver + * @{ + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** + * @defgroup MD_I2C_Public_Macros I2C Public Macros + * @{ + */ +#define MD_I2C_ENABLE(x) (SET_BIT((x)->CON1, I2C_CON1_PE_MSK)) +#define MD_I2C_DISABLE(x) (CLEAR_BIT((x)->CON1, I2C_CON1_PE_MSK)) +/** + * @} + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup MD_I2C_Public_Types I2C Public Types + * @{ + */ +/** + * @brief I2C Addressing Mode + */ +typedef enum +{ + MD_I2C_ADDR_7BIT = 0x0U, /**< 7 bit address */ + MD_I2C_ADDR_10BIT = 0x1U, /**< 10 bit address */ +} md_i2c_addr_t; + +/** + * @brief I2C Dual Addressing Mode + */ +typedef enum +{ + MD_I2C_DUALADDR_DISABLE = 0x0U, /**< dual address is disable */ + MD_I2C_DUALADDR_ENABLE = 0x1U, /**< dual address is enable */ +} md_i2c_dual_addr_t; + +/** + * @brief I2C General Call Addressing mode + */ +typedef enum +{ + MD_I2C_GENERALCALL_DISABLE = 0x0U, /**< feneral call address is disable */ + MD_I2C_GENERALCALL_ENABLE = 0x1U, /**< feneral call address is enable */ +} md_i2c_general_addr_t; + +/** + * @brief I2C Nostretch Mode + */ +typedef enum +{ + MD_I2C_NOSTRETCH_DISABLE = 0x0U, /**< Nostretch disable */ + MD_I2C_NOSTRETCH_ENABLE = 0x1U, /**< Nostretch enable */ +} md_i2c_nostretch_t; + +/** + * @brief I2C Memory Address Size + */ +typedef enum +{ + MD_I2C_MEMADD_SIZE_8BIT = 0x8U, /**< 8 bit memory address size */ + MD_I2C_MEMADD_SIZE_16BIT = 0x10U, /**< 10 bit memory address size */ +} md_i2c_addr_size_t; + +/** + * @brief I2C mode structure definition + */ +typedef enum +{ + MD_I2C_MODE_NONE = 0x0U, /**< No I2C communication on going */ + MD_I2C_MODE_MASTER = 0x10U, /**< I2C communication is in Master mode */ + MD_I2C_MODE_SLAVE = 0x20U, /**< I2C communication is in Slave mode */ + MD_I2C_MODE_MEM = 0x40U, /**< I2C communication is in Memory mode */ +} md_i2c_mode_t; + +/** + * @brief I2C Clock + */ +typedef enum +{ + MD_I2C_STANDARD_MODE_MAX_CLK = 100000U, /**< Standard mode clock */ + MD_I2C_FAST_MODE_MAX_CLK = 400000U, /**< Fast mode clock */ + MD_I2C_EXTREME_FAST_MODE_MAX_CLK = 1000000U, /**< Extreme mode clock */ +} md_i2c_clock_t; + +/** + * @brief I2C OAR2 Register + */ +typedef enum +{ + MD_I2C_OAR2_ENDUAL = (1U << 0), /**< ENDUAL BIT */ + MD_I2C_OAR2_ADD2 = (1U << 1), /**< ADD2 BIT */ +} md_i2c_oar2_t; + +/** + * @brief I2C peripherals module + */ +typedef enum +{ + MD_I2C_MODULE_MASTER = (1U << 0), /**< Master module */ + MD_I2C_MODULE_SLAVE = (1U << 1), /**< Slave module */ +} md_i2c_module_t; + + +/** + * @brief I2C Configuration Structure definition + */ +typedef struct +{ + md_i2c_module_t module; /**< Specifies the communication module */ + uint32_t clk_speed; /**< Specifies the clock frequency */ + uint32_t own_addr1; /**< Specifies the first device own address */ + md_i2c_addr_t addr_mode; /**< Specifies addressing mode */ + md_i2c_dual_addr_t dual_addr; /**< Specifies if dual addressing mode is selected */ + uint32_t own_addr2; /**< Specifies the second device own address */ + md_i2c_general_addr_t general_call; /**< Specifies if general call mode is selected */ + md_i2c_nostretch_t no_stretch; /**< Specifies if nostretch mode is selected */ +} md_i2c_init_t; +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @defgroup MD_I2C_Public_Functions I2C Public Functions + * @{ + */ +/** @defgroup MD_I2C_Public_Functions_Group2 CON1 + * @{ + */ +/** + * @brief Enable SMBus Packet Error Calculation (PEC). + * @param I2Cx: I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_smbus_pec(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_PECEN_MSK); +} + +/** + * @brief Disable SMBus Packet Error Calculation (PEC). + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_smbus_pec(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_PECEN_MSK); +} + +/** + * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_smbus_pec(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON1, I2C_CON1_PECEN_MSK) == (I2C_CON1_PECEN_MSK)); +} + +/** + * @brief Enable SMBus alert (Host or Device mode) + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_smbus_alert(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_ALERTEN_MSK); +} + +/** + * @brief Disable SMBus alert (Host or Device mode) + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_smbus_alert(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_ALERTEN_MSK); +} + +/** + * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_smbus_alert(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON1, I2C_CON1_ALERTEN_MSK) == (I2C_CON1_ALERTEN_MSK)); +} + +/** + * @brief Enable SMBus device slave address. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_smbus_slave_addr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_SMBDEN_MSK); +} + +/** + * @brief Disable SMBus device slave address. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_smbus_slave_addr(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_SMBDEN_MSK); +} + +/** + * @brief Check if SMBus device slave address is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_smbus_slave_addr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON1, I2C_CON1_SMBDEN_MSK) == (I2C_CON1_SMBDEN_MSK)); +} + +/** + * @brief Enable SMBus host device address. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_smbus_host_addr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_SMBHEN_MSK); +} + +/** + * @brief Disable SMBus host device address. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_smbus_host_addr(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_SMBHEN_MSK); +} + +/** + * @brief Check if SMBus host device address is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_smbus_host_addr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON1, I2C_CON1_SMBHEN_MSK) == (I2C_CON1_SMBHEN_MSK)); +} + +/** + * @brief Enable General Call. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_general_call(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_GCEN_MSK); +} + +/** + * @brief Disable General Call. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_general_call(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_GCEN_MSK); +} + +/** + * @brief Check if General Call is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_general_call(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON1, I2C_CON1_GCEN_MSK) == (I2C_CON1_GCEN_MSK)); +} + +/** + * @brief Enable I2C slave device scl stretch function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_scl_stretch(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_NOSTRETCH_MSK); +} + +/** + * @brief Disable I2C slave device scl stretch function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_scl_stretch(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_NOSTRETCH_MSK); +} + +/** + * @brief Check if is enabled I2C slave device scl stretch function. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_scl_stretch(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON1, I2C_CON1_NOSTRETCH_MSK) != (I2C_CON1_NOSTRETCH_MSK)); +} + +/** + * @brief Enable I2C slave byte control function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_slave_byte_control(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_SBC_MSK); +} + +/** + * @brief Disable I2C slave byte control function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_slave_byte_control(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_SBC_MSK); +} + +/** + * @brief Check if is enabled I2C slave device byte control function. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_slave_byte_control(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON1, I2C_CON1_SBC_MSK) != (I2C_CON1_SBC_MSK)); +} + +/** + * @brief Enable DMA receive function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_dma_receive(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_RXDMAEN_MSK); +} + +/** + * @brief Disable DMA receive function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_dma_receive(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_RXDMAEN_MSK); +} + +/** + * @brief Check if is enable DMA receive function. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_dma_receive(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON1, I2C_CON1_RXDMAEN_MSK) == (I2C_CON1_RXDMAEN_MSK)); +} + +/** + * @brief Enable DMA transmit function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_dma_transmit(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_TXDMAEN_MSK); +} + +/** + * @brief Disable DMA transmit function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_dma_transmit(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_TXDMAEN_MSK); +} + +/** + * @brief Check if is enable DMA transmit function. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_dma_transmit(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON1, I2C_CON1_TXDMAEN_MSK) == (I2C_CON1_TXDMAEN_MSK)); +} + +/** + * @brief Set I2C digit filter timer. + * @param I2Cx I2C Instance. + * @param timer filter timer. + * @retval None + */ +__STATIC_INLINE void md_i2c_set_digit_filter(I2C_TypeDef *I2Cx, uint8_t timer) +{ + MODIFY_REG(I2Cx->CON1, I2C_CON1_DNF_MSK, timer << I2C_CON1_DNF_POSS); +} + +/** + * @brief Get I2C digit filter timer. + * @param I2Cx I2C Instance. + * @retval timer filter timer. + */ +__STATIC_INLINE uint32_t md_i2c_get_digit_filter(I2C_TypeDef *I2Cx) +{ + return (READ_BITS(I2Cx->CON1, I2C_CON1_DNF_MSK, I2C_CON1_DNF_POSS)); +} + +/** + * @brief Enable I2C module. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_pe(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_PE_MSK); +} + +/** + * @brief Disable I2C module. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_pe(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_PE_MSK); +} + +/** + * @brief Check if i2c is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_pe(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON1, I2C_CON1_PE_MSK) == (I2C_CON1_PE_MSK)); +} +/** + * @} + */ +/** @defgroup MD_I2C_Public_Functions_Group3 CON2 + * @{ + */ +/** + * @brief Get I2C acknowledge updata flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_ack_updata(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_ACK_UPD_MSK)); +} + +/** + * @brief Clear I2C acknowledge updata flag. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_ack_updata(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_ACK_UPD_MSK); +} + +/** + * @brief Enable I2C wait acknowledge function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_holdack(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_HOLDACK_MSK); +} + +/** + * @brief Disable I2C wait acknowledge function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_holdack(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON2, I2C_CON2_HOLDACK_MSK); +} + +/** + * @brief Check if the I2C wait acknowledge is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_holdack(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_HOLDACK_MSK) == (I2C_CON2_HOLDACK_MSK)); +} + +/** + * @brief Enable SMBus PEC transfer requests function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_pec_byte(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_PECBYTE_MSK); +} + +/** + * @brief Disable SMBus PEC transfer requests function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_pec_byte(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON2, I2C_CON2_PECBYTE_MSK); +} + +/** + * @brief Check if SMBus PEC transfer requests function is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_pec_byte(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_PECBYTE_MSK) == (I2C_CON2_PECBYTE_MSK)); +} + +/** + * @brief Enable I2C auto end function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_auto_end(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_AUTOEND_MSK); +} + +/** + * @brief Disable I2C auto end function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_auto_end(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON2, I2C_CON2_AUTOEND_MSK); +} + +/** + * @brief Check if I2C auto end function is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_auto_end(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_AUTOEND_MSK) == (I2C_CON2_AUTOEND_MSK)); +} + +/** + * @brief Enable I2C reload fuctions. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_reload(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_RELOAD_MSK); +} + +/** + * @brief Disable I2C reload fuctions. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_reload(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON2, I2C_CON2_RELOAD_MSK); +} + +/** + * @brief Check if I2C reload fuctions is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_reload(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_RELOAD_MSK) == (I2C_CON2_RELOAD_MSK)); +} + +/** + * @brief Set I2C transmit data length. + * @param I2Cx I2C Instance. + * @param length of transmit data. + * @retval None + */ +__STATIC_INLINE void md_i2c_set_transmit_length(I2C_TypeDef *I2Cx, uint32_t length) +{ + MODIFY_REG(I2Cx->CON1, I2C_CON1_NBYTES_MSK, (length >> 8) << I2C_CON1_NBYTES_POSS); + MODIFY_REG(I2Cx->CON2, I2C_CON2_NBYTES_MSK, (length & 0xFF) << I2C_CON2_NBYTES_POSS); +} + +/** + * @brief Get I2C transmit data length. + * @param I2Cx I2C Instance. + * @retval length of transmit data. + */ +__STATIC_INLINE uint32_t md_i2c_get_transmit_length(I2C_TypeDef *I2Cx) +{ + uint32_t nbytes_h, nbytes_l, nbytes; + nbytes_h = READ_BITS(I2Cx->CON1, I2C_CON1_NBYTES_MSK, I2C_CON1_NBYTES_POSS); + nbytes_l = READ_BITS(I2Cx->CON2, I2C_CON2_NBYTES_MSK, I2C_CON2_NBYTES_POSS); + nbytes = (nbytes_h << 8) | nbytes_l; + + return nbytes; +} + +/** + * @brief Set I2C send NACK. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_set_nack(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_NACK_MSK); +} + +/** + * @brief Get I2C NACK flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_nack(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_NACK_MSK)); +} + +/** + * @brief Set I2C send stop flag. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_set_stop(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_STOP_MSK); +} + +/** + * @brief Get I2C stop flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_stop(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_STOP_MSK)); +} + +/** + * @brief Set I2C send start flag. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_set_start(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_START_MSK); +} + +/** + * @brief Get I2C start flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_start(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_START_MSK)); +} + +/** + * @brief Enable i2c send 10-bit standard address header. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_standard_10_bit_header(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_HEAD10R_MSK); +} + +/** + * @brief Disable i2c send 10-bit standard address header. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_standard_10_bit_header(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON2, I2C_CON2_HEAD10R_MSK); +} + +/** + * @brief Check if is enabled send 10-bit standard address header. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_standard_10_bit_header(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_HEAD10R_MSK) == (I2C_CON2_HEAD10R_MSK)); +} + +/** + * @brief Enable 10-bit address mode. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_addr_10_bit(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_ADD10_MSK); +} + +/** + * @brief Enable 7-bit address mode. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_addr_7_bit(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON2, I2C_CON2_ADD10_MSK); +} + +/** + * @brief Check if is enabled 10-bit address mode. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_addr_10_bit(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_ADD10_MSK) == (I2C_CON2_ADD10_MSK)); +} + +/** + * @brief Enable i2c master read. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_master_read(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_RD_WRN_MSK); +} + +/** + * @brief Enable i2c master write. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_master_write(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON2, I2C_CON2_RD_WRN_MSK); +} + +/** + * @brief Check if is enabled master read. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_master_read(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_RD_WRN_MSK) == (I2C_CON2_RD_WRN_MSK)); +} + +/** + * @brief Set address 0:9 bit value. + * @param I2Cx I2C Instance. + * @param addr: address 0:9 bit value. + * @retval None + */ +__STATIC_INLINE void md_i2c_set_slave_addr(I2C_TypeDef *I2Cx, uint32_t addr) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_SADD_MSK, (addr << I2C_CON2_SADD_POSS)); +} + +/** + * @brief Get address 0:9 bit value. + * @param I2Cx I2C Instance. + * @retval address 0:9 bit value. + */ +__STATIC_INLINE uint32_t md_i2c_get_slave_addr(I2C_TypeDef *I2Cx) +{ + return (READ_BITS(I2Cx->CON2, I2C_CON2_SADD_MSK, I2C_CON2_SADD_POSS)); +} +/** + * @} + */ +/** @defgroup MD_I2C_Public_Functions_Group4 ADDR1 + * @{ + */ +/** + * @brief Enable i2c own1 address. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_own1_address(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1EN_MSK); +} + +/** + * @brief Disable i2c own1 address. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_own1_address(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1EN_MSK); +} + +/** + * @brief Check if is enabled i2c own1 address. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_own1_address(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1EN_MSK) == (I2C_ADDR1_OA1EN_MSK)); +} + +/** + * @brief Enable i2c own1 10_bit address. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_own1_10_bit_addr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1MODE_MSK); +} + +/** + * @brief Enable i2c own1 7_bit address. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_own1_7_bit_addr(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1MODE_MSK); +} + +/** + * @brief Check if is enabled i2c own1 10_bit address. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_own1_10_bit_address(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1MODE_MSK) == (I2C_ADDR1_OA1MODE_MSK)); +} + +/** + * @brief Set own1 address. + * @param I2Cx I2C Instance. + * @param addr of own1. + * @retval None + */ +__STATIC_INLINE void md_i2c_set_own1_addr(I2C_TypeDef *I2Cx, uint32_t addr) +{ + MODIFY_REG(I2Cx->ADDR1, I2C_ADDR1_OA1_MSK, (addr << I2C_ADDR1_OA1_POSS)); +} + +/** + * @brief Get own1 address. + * @param I2Cx I2C Instance. + * @retval addr of own1. + */ +__STATIC_INLINE uint32_t md_i2c_get_own1_addr(I2C_TypeDef *I2Cx) +{ + return (READ_BITS(I2Cx->ADDR1, I2C_ADDR1_OA1_MSK, I2C_ADDR1_OA1_POSS)); +} +/** + * @} + */ +/** @defgroup MD_I2C_Public_Functions_Group5 ADDR2 + * @{ + */ +/** + * @brief Enable i2c own2 address. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_own2_address(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2EN_MSK); +} + +/** + * @brief Disable i2c own2 address. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_own2_address(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2EN_MSK); +} + +/** + * @brief Check if is enabled i2c own2 address. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_own2_address(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2EN_MSK) == (I2C_ADDR2_OA2EN_MSK)); +} + +/** + * @brief Set the own2 mask Address. + * @param I2Cx I2C Instance. + * @param own2mask mask value. + * @retval None + */ +__STATIC_INLINE void md_i2c_set_own2_mask_address(I2C_TypeDef *I2Cx, uint32_t own2mask) +{ + MODIFY_REG(I2Cx->ADDR2, I2C_ADDR2_OA2MSK_MSK, (own2mask << I2C_ADDR2_OA2MSK_POSS)); +} + +/** + * @brief Get the own2 mask Address. + * @param I2Cx I2C Instance. + * @retval Own2 mask value. + */ +__STATIC_INLINE uint32_t md_i2c_get_own2_mask_address(I2C_TypeDef *I2Cx) +{ + return (READ_BITS(I2Cx->ADDR2, I2C_ADDR2_OA2MSK_MSK, I2C_ADDR2_OA2MSK_POSS)); +} + +/** + * @brief Set the own2 Address. + * @param I2Cx I2C Instance. + * @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F. + * @retval None + */ +__STATIC_INLINE void md_i2c_set_own2_address(I2C_TypeDef *I2Cx, uint32_t OwnAddress2) +{ + MODIFY_REG(I2Cx->ADDR2, I2C_ADDR2_OA2_MSK, (OwnAddress2 << I2C_ADDR2_OA2_POSS)); +} + +/** + * @brief Get the 7bits Own Address2 value. + * @param I2Cx I2C Instance. + * @retval Own Address2 value. + */ +__STATIC_INLINE uint32_t md_i2c_get_own2_address(I2C_TypeDef *I2Cx) +{ + return (READ_BITS(I2Cx->ADDR2, I2C_ADDR2_OA2_MSK, I2C_ADDR2_OA2_POSS)); +} +/** + * @} + */ +/** @defgroup MD_I2C_Public_Functions_Group6 TIMINGR + * @{ + */ +/** + * @brief Set i2c clock prescaler value. + * @param I2Cx I2C Instance. + * @param pres prescaler value. + * @retval None + */ +__STATIC_INLINE void md_i2c_set_clock_prescaler(I2C_TypeDef *I2Cx, uint32_t pres) +{ + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_PRESC_MSK, pres << I2C_TIMINGR_PRESC_POSS); +} + +/** + * @brief Get i2c clock prescaler value. + * @param I2Cx I2C Instance. + * @retval clock prescaler value. + */ +__STATIC_INLINE uint32_t md_i2c_get_clock_prescaler(I2C_TypeDef *I2Cx) +{ + return (READ_BITS(I2Cx->TIMINGR, I2C_TIMINGR_PRESC_MSK, I2C_TIMINGR_PRESC_POSS)); +} + +/** + * @brief Set i2c clock delay time. + * @param I2Cx I2C Instance. + * @param time delay time. + * @retval None + */ +__STATIC_INLINE void md_i2c_set_clock_delay(I2C_TypeDef *I2Cx, uint32_t time) +{ + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, time << I2C_TIMINGR_SCLDEL_POSS); +} + +/** + * @brief Get i2c clock delay time. + * @param I2Cx I2C Instance. + * @retval clock delay value. + */ +__STATIC_INLINE uint32_t md_i2c_get_clock_delay(I2C_TypeDef *I2Cx) +{ + return (READ_BITS(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, I2C_TIMINGR_SCLDEL_POSS)); +} + +/** + * @brief Set i2c data delay time. + * @param I2Cx I2C Instance. + * @param time delay time. + * @retval None + */ +__STATIC_INLINE void md_i2c_set_data_delay(I2C_TypeDef *I2Cx, uint32_t time) +{ + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL_MSK, time << I2C_TIMINGR_SDADEL_POSS); +} + +/** + * @brief Get i2c clock delay time. + * @param I2Cx I2C Instance. + * @retval data delay value. + */ +__STATIC_INLINE uint32_t md_i2c_get_data_delay(I2C_TypeDef *I2Cx) +{ + return (READ_BITS(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL_MSK, I2C_TIMINGR_SDADEL_POSS)); +} + +/** + * @brief Set i2c clock high level time. + * @param I2Cx I2C Instance. + * @param time high level time. + * @retval None + */ +__STATIC_INLINE void md_i2c_set_clock_high_time(I2C_TypeDef *I2Cx, uint32_t time) +{ + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SCLH_MSK, time << I2C_TIMINGR_SCLH_POSS); +} + +/** + * @brief Get i2c clock high level time. + * @param I2Cx I2C Instance. + * @retval scl high level time. + */ +__STATIC_INLINE uint32_t md_i2c_get_clock_high_time(I2C_TypeDef *I2Cx) +{ + return (READ_BITS(I2Cx->TIMINGR, I2C_TIMINGR_SCLH_MSK, I2C_TIMINGR_SCLH_POSS)); +} + +/** + * @brief Set i2c clock low level time. + * @param I2Cx I2C Instance. + * @param time low level time. + * @retval None + */ +__STATIC_INLINE void md_i2c_set_clock_low_time(I2C_TypeDef *I2Cx, uint32_t time) +{ + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SCLL_MSK, time << I2C_TIMINGR_SCLL_POSS); +} + +/** + * @brief Get i2c clock low level time. + * @param I2Cx I2C Instance. + * @retval scl low level time. + */ +__STATIC_INLINE uint32_t md_i2c_get_clock_low_time(I2C_TypeDef *I2Cx) +{ + return (READ_BITS(I2Cx->TIMINGR, I2C_TIMINGR_SCLL_MSK, I2C_TIMINGR_SCLL_POSS)); +} +/** + * @} + */ +/** @defgroup MD_I2C_Public_Functions_Group7 TIMEOUTR + * @{ + */ +/** + * @brief Enable i2c clock stretch cumulation timeout function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_texten(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TEXTEN_MSK); +} + +/** + * @brief Disable i2c clock stretch cumulation timeout function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_texten(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TEXTEN_MSK); +} + +/** + * @brief Check if is enabled i2c clock stretch cumulation timeout function. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_texten(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TEXTEN_MSK) == (I2C_TIMEOUTR_TEXTEN_MSK)); +} + +/** + * @brief Set i2c bus timeout time. + * @param I2Cx I2C Instance. + * @param time timeout time. + * @retval None + */ +__STATIC_INLINE void md_i2c_set_bus_timeoutB_time(I2C_TypeDef *I2Cx, uint8_t time) +{ + MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB_MSK, (time << I2C_TIMEOUTR_TIMEOUTB_POSS)); +} + +/** + * @brief Get i2c bus timeout time. + * @param I2Cx I2C Instance. + * @retval timeout time. + */ +__STATIC_INLINE uint32_t md_i2c_get_bus_timeoutB_time(I2C_TypeDef *I2Cx) +{ + return (READ_BITS(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB_MSK, I2C_TIMEOUTR_TIMEOUTB_POSS)); +} + +/** + * @brief Enable i2c timeout function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_timeouten(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTEN_MSK); +} + +/** + * @brief Disable i2c timeout function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_timeouten(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTEN_MSK); +} + +/** + * @brief Check if is enabled i2c timeout function. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_timeouten(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTEN_MSK) == (I2C_TIMEOUTR_TIMEOUTEN_MSK)); +} + +/** + * @brief Enable i2c idle state timeout detect function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_idle_timeout(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE_MSK); +} + +/** + * @brief Enable i2c scl low state detect function. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_scl_low_timeout(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE_MSK); +} + +/** + * @brief Check if is enabled i2c idle state timeout detect function + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_idle_timeout(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE_MSK) == (I2C_TIMEOUTR_TIDLE_MSK)); +} + +/** + * @brief Set i2c bus timeout time. + * @param I2Cx I2C Instance. + * @param time timeout time. + * @retval None + */ +__STATIC_INLINE void md_i2c_set_bus_timeoutA_time(I2C_TypeDef *I2Cx, uint8_t time) +{ + MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA_MSK, (time << I2C_TIMEOUTR_TIMEOUTA_POSS)); +} + +/** + * @brief Get i2c bus timeout time. + * @param I2Cx I2C Instance. + * @retval timeout time. + */ +__STATIC_INLINE uint32_t md_i2c_get_bus_timeoutA_time(I2C_TypeDef *I2Cx) +{ + return (READ_BITS(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA_MSK, I2C_TIMEOUTR_TIMEOUTA_POSS)); +} +/** + * @} + */ +/** @defgroup MD_I2C_Public_Functions_Group8 STAT + * @{ + */ +/** + * @brief Get slave module matched address. + * @param I2Cx I2C Instance. + * @retval matched address. + */ +__STATIC_INLINE uint32_t md_i2c_get_addr_match(I2C_TypeDef *I2Cx) +{ + return (READ_BITS(I2Cx->STAT, I2C_STAT_ADDCODE_MSK, I2C_STAT_ADDCODE_POSS)); +} + +/** + * @brief Get slave module write. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_write(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_DIR_MSK) != (I2C_STAT_DIR_MSK)); +} + +/** + * @brief Get slave module read. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_read(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_DIR_MSK) == (I2C_STAT_DIR_MSK)); +} + +/** + * @brief Get bus busy flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_busy(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_BUSY_MSK) == (I2C_STAT_BUSY_MSK)); +} + +/** + * @brief Get transmit and reload complete flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_tcr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_TCR_MSK) == (I2C_STAT_TCR_MSK)); +} + +/** + * @brief Get transmit complete flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_tc(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_TC_MSK) == (I2C_STAT_TC_MSK)); +} + +/** + * @brief Get receive fifo underflow flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rxud(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_RXUD_MSK) == (I2C_STAT_RXUD_MSK)); +} + +/** + * @brief Get receive fifo overflow flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rxov(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_RXOV_MSK) == (I2C_STAT_RXOV_MSK)); +} + +/** + * @brief Get receive fifo not empty flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rxne(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_RXNE_MSK) == (I2C_STAT_RXNE_MSK)); +} + +/** + * @brief Get transmit fifo underflow flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_txud(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_TXUD_MSK) == (I2C_STAT_TXUD_MSK)); +} + +/** + * @brief Get transmit fifo overflow flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_txov(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_TXOV_MSK) == (I2C_STAT_TXOV_MSK)); +} + +/** + * @brief Get transmit fifo empty flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_txe(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_TXE_MSK) == (I2C_STAT_TXE_MSK)); +} + +/** + * @} + */ +/** @defgroup MD_I2C_Public_Functions_Group10 PECR + * @{ + */ +/** + * @brief Get receive pec register value. + * @param I2Cx I2C Instance. + * @retval receive data. + */ +__STATIC_INLINE uint32_t md_i2c_get_rx_reg_pec(I2C_TypeDef *I2Cx) +{ + return (READ_BITS(I2Cx->PECR, I2C_PECR_PEC_MSK, I2C_PECR_PEC_POSS)); +} +/** + * @} + */ +/** @defgroup MD_I2C_Public_Functions_Group11 RXDATA + * @{ + */ +/** + * @brief Get receive register value. + * @param I2Cx I2C Instance. + * @retval receive data. + */ +__STATIC_INLINE uint32_t md_i2c_get_rx_reg_data(I2C_TypeDef *I2Cx) +{ + return (READ_BITS(I2Cx->RXDATA, I2C_RXDATA_RXDATA_MSK, I2C_RXDATA_RXDATA_POSS)); +} +/** + * @} + */ +/** @defgroup MD_I2C_Public_Functions_Group12 TXDATA + * @{ + */ +/** + * @brief Set transmit register value. + * @param I2Cx I2C Instance. + * @param data transmit value. + * @retval None + */ +__STATIC_INLINE void md_i2c_set_tx_reg_data(I2C_TypeDef *I2Cx, uint8_t data) +{ + MODIFY_REG(I2Cx->TXDATA, I2C_TXDATA_TXDATA_MSK, data << I2C_TXDATA_TXDATA_POSS); +} +/** + * @} + */ +/** @defgroup MD_I2C_Public_Functions_Group13 IER + * @{ + */ +/** + * @brief Enable TX fifo empty interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_txe(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TXE_MSK); +} + +/** + * @brief Enable TX fifo overflow interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_txov(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TXOV_MSK); +} + +/** + * @brief Enable TX fifo underflow interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_txud(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TXUD_MSK); +} + +/** + * @brief Enable rx not empty interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_rxne(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_RXNE_MSK); +} + +/** + * @brief Enable rx fifo overflow interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_rxov(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_RXOV_MSK); +} + +/** + * @brief Enable rx fifo underflow interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_rxud(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_RXUD_MSK); +} + +/** + * @brief Enable i2c transmit complete interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_tc(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TC_MSK); +} + +/** + * @brief Enable i2c transmit and reload complete interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_tcr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TCR_MSK); +} + +/** + * @brief Enable i2c addr matched interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_addr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_ADDR_MSK); +} + +/** + * @brief Enable i2c nack interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_nack(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_NACK_MSK); +} + +/** + * @brief Enable i2c stop interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_stop(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_STOP_MSK); +} + +/** + * @brief Enable i2c bus error interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_berr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_BERR_MSK); +} + +/** + * @brief Enable i2c lost arbitration interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_arlo(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_ARLO_MSK); +} + +/** + * @brief Enable i2c pec error interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_pece(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_PECE_MSK); +} + +/** + * @brief Enable i2c timeout interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_tout(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TOUT_MSK); +} + +/** + * @brief Enable i2c SMBus alert interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_it_alert(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_ALERT_MSK); +} + +/** + * @} + */ +/** @defgroup MD_I2C_Public_Functions_Group14 IDR + * @{ + */ +/** + * @brief Disable TX fifo empty interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_txe(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_TXE_MSK); +} + +/** + * @brief Disable TX fifo overflow interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_txov(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_TXOV_MSK); +} + +/** + * @brief Disable TX fifo underflow interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_txud(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_TXUD_MSK); +} + +/** + * @brief Disable rx not empty interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_rxne(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_RXNE_MSK); +} + +/** + * @brief Disable rx fifo overflow interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_rxov(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_RXOV_MSK); +} + +/** + * @brief Disable rx fifo underflow interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_rxud(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_RXUD_MSK); +} + +/** + * @brief Disable i2c transmit complete interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_tc(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_TC_MSK); +} + +/** + * @brief Disable i2c transmit and reload complete interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_tcr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_TCR_MSK); +} + +/** + * @brief Disable i2c addr matched interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_addr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_ADDR_MSK); +} + +/** + * @brief Disable i2c nack interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_nack(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_NACK_MSK); +} + +/** + * @brief Disable i2c stop interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_stop(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_STOP_MSK); +} + +/** + * @brief Disable i2c bus error interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_berr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_BERR_MSK); +} + +/** + * @brief Disable i2c lost arbitration interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_arlo(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_ARLO_MSK); +} + +/** + * @brief Disable i2c pec error interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_pece(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_PECE_MSK); +} + +/** + * @brief Disable i2c timeout interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_tout(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_TOUT_MSK); +} + +/** + * @brief Disable i2c SMBus alert interrupt. + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_it_alert(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IDR, I2C_IDR_ALERT_MSK); +} + +/** + * @} + */ +/** @defgroup MD_I2C_Public_Functions_Group15 IVS + * @{ + */ +/** + * @brief Check if the TX fifo empty interrupt is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_it_txe(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TXE_MSK) == (I2C_IVS_TXE_MSK)); +} + +/** + * @brief Check if the TX fifo overflow interrupt is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_it_txov(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TXOV_MSK) == (I2C_IVS_TXOV_MSK)); +} + +/** + * @brief Check if the TX fifo underflow interrupt is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_it_txud(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TXUD_MSK) == (I2C_IVS_TXUD_MSK)); +} + +/** + * @brief Check if the rx not empty interrupt is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_it_rxne(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_RXNE_MSK) == (I2C_IVS_RXNE_MSK)); +} + +/** + * @brief Check if the rx fifo overflow interrupt is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_it_rxov(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_RXOV_MSK) == (I2C_IVS_RXOV_MSK)); +} + +/** + * @brief Check if the rx fifo underflow interrupt is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_it_rxud(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_RXUD_MSK) == (I2C_IVS_RXUD_MSK)); +} + +/** + * @brief Check if the transmit complete interrupt is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_it_tc(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TC_MSK) == (I2C_IVS_TC_MSK)); +} + +/** + * @brief Check if the transmit and reload complete interrupt is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_it_tcr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TCR_MSK) == (I2C_IVS_TCR_MSK)); +} + +/** + * @brief Check if the addr matched interrupt is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_it_addr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_ADDR_MSK) == (I2C_IVS_ADDR_MSK)); +} + +/** + * @brief Check if the nack interrupt is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_it_nack(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_NACK_MSK) == (I2C_IVS_NACK_MSK)); +} + +/** + * @brief Check if the stop interrupt is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_it_stop(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_STOP_MSK) == (I2C_IVS_STOP_MSK)); +} + +/** + * @brief Check if the bus error interrupt is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_it_berr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_BERR_MSK) == (I2C_IVS_BERR_MSK)); +} + +/** + * @brief Check if the lost arbitration interrupt is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_it_arlo(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_ARLO_MSK) == (I2C_IVS_ARLO_MSK)); +} + +/** + * @brief Check if the pec error interrupt is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_it_pece(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_PECE_MSK) == (I2C_IVS_PECE_MSK)); +} + +/** + * @brief Check if the timeout interrupt is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_it_tout(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TOUT_MSK) == (I2C_IVS_TOUT_MSK)); +} + +/** + * @brief Check if the SMBus alert interrupt is enabled or disabled. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enable_it_alert(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_ALERT_MSK) == (I2C_IVS_ALERT_MSK)); +} + +/** + * @} + */ +/** @defgroup MD_I2C_Public_Functions_Group16 RIF + * @{ + */ +/** + * @brief Get tx fifo empty interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_txe(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TXE_MSK) == (I2C_RIF_TXE_MSK)); +} + +/** + * @brief Get TX fifo overflow interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_txov(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TXOV_MSK) == (I2C_RIF_TXOV_MSK)); +} + +/** + * @brief Get TX fifo underflow interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_txud(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TXUD_MSK) == (I2C_RIF_TXUD_MSK)); +} + +/** + * @brief Get rx not empty interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_rxne(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_RXNE_MSK) == (I2C_RIF_RXNE_MSK)); +} + +/** + * @brief Get rx fifo overflow interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_rxov(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_RXOV_MSK) == (I2C_RIF_RXOV_MSK)); +} + +/** + * @brief Get rx fifo underflow interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_rxud(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_RXUD_MSK) == (I2C_RIF_RXUD_MSK)); +} + +/** + * @brief Get transmit complete interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_tc(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TC_MSK) == (I2C_RIF_TC_MSK)); +} + +/** + * @brief Get transmit and reload complete interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_tcr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TCR_MSK) == (I2C_RIF_TCR_MSK)); +} + + +/** + * @brief Get addr matched interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_addr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_ADDR_MSK) == (I2C_RIF_ADDR_MSK)); +} + +/** + * @brief Get nack interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_nack(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_NACK_MSK) == (I2C_RIF_NACK_MSK)); +} + +/** + * @brief Get stop interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_stop(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_STOP_MSK) == (I2C_RIF_STOP_MSK)); +} + +/** + * @brief Get bus error interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_berr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_BERR_MSK) == (I2C_RIF_BERR_MSK)); +} + +/** + * @brief Get lost arbitration interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_arlo(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_ARLO_MSK) == (I2C_RIF_ARLO_MSK)); +} + +/** + * @brief Get pec error interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_pece(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_PECE_MSK) == (I2C_RIF_PECE_MSK)); +} + +/** + * @brief Get timeout interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_tout(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TOUT_MSK) == (I2C_RIF_TOUT_MSK)); +} + +/** + * @brief Get SMBus alert interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_flag_alert(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_ALERT_MSK) == (I2C_RIF_ALERT_MSK)); +} +/** + * @} + */ +/** @defgroup MD_I2C_Public_Functions_Group17 IFM + * @{ + */ +/** + * @brief Mask tx fifo empty interrupt. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_mask_it_txe(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TXE_MSK) == I2C_IFM_TXE_MSK); +} + +/** + * @brief Mask TX fifo overflow interrupt. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_mask_it_txov(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TXOV_MSK) == I2C_IFM_TXOV_MSK); +} + +/** + * @brief Mask TX fifo underflow interrupt. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_mask_it_txud(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TXUD_MSK) == I2C_IFM_TXUD_MSK); +} + +/** + * @brief Mask rx not empty interrupt. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_mask_it_rxne(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_RXNE_MSK) == I2C_IFM_RXNE_MSK); +} + +/** + * @brief Mask rx fifo overflow interrupt. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_mask_it_rxov(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_RXOV_MSK) == I2C_IFM_RXOV_MSK); +} + +/** + * @brief Mask rx fifo underflow interrupt. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_mask_it_rxud(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_RXUD_MSK) == I2C_IFM_RXUD_MSK); +} + +/** + * @brief Mask transmit complete interrupt. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_mask_it_tc(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TC_MSK) == I2C_IFM_TC_MSK); +} + +/** + * @brief Mask transmit and reload complete interrupt. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_mask_it_tcr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TCR_MSK) == I2C_IFM_TCR_MSK); +} + +/** + * @brief Mask addr matched interrupt. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_mask_it_addr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_ADDR_MSK) == I2C_IFM_ADDR_MSK); +} + +/** + * @brief Mask nack interrupt. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_mask_it_nack(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_NACK_MSK) == I2C_IFM_NACK_MSK); +} + +/** + * @brief Mask stop interrupt. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_mask_it_stop(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_STOP_MSK) == I2C_IFM_STOP_MSK); +} + +/** + * @brief Mask bus error interrupt. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_mask_it_berr(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_BERR_MSK) == I2C_IFM_BERR_MSK); +} + +/** + * @brief Mask lost arbitration interrupt. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_mask_it_arlo(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_ARLO_MSK) == I2C_IFM_ARLO_MSK); +} + +/** + * @brief Mask pec error interrupt. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_mask_it_pece(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_PECE_MSK) == I2C_IFM_PECE_MSK); +} + +/** + * @brief Mask timeout interrupt. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_mask_it_tout(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TOUT_MSK) == I2C_IFM_TOUT_MSK); +} + +/** + * @brief Mask SMBus alert interrupt. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_mask_it_alert(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_ALERT_MSK) == I2C_IFM_ALERT_MSK); +} + +/** + * @} + */ +/** @defgroup MD_I2C_Public_Functions_Group18 ICR + * @{ + */ +/** + * @brief Clear tx fifo empty interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2c_clear_flag_txe(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TXE_MSK); +} + +/** + * @brief Clear TX fifo overflow interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2c_clear_flag_txov(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TXOV_MSK); +} + +/** + * @brief Clear TX fifo underflow interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2c_clear_flag_txud(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TXUD_MSK); +} + +/** + * @brief Clear rx not empty interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2c_clear_flag_rxne(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_RXNE_MSK); +} + +/** + * @brief Clear rx fifo overflow interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2c_clear_flag_rxov(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_RXOV_MSK); +} + +/** + * @brief Clear rx fifo underflow interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2c_clear_flag_rxud(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_RXUD_MSK); +} + +/** + * @brief Clear transmit complete interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2c_clear_flag_tc(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TC_MSK); +} + +/** + * @brief Clear transmit and reload complete interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2c_clear_flag_tcr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TCR_MSK); +} + +/** + * @brief Clear addr matched interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2c_clear_flag_addr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ADDR_MSK); +} + +/** + * @brief Clear nack interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2c_clear_flag_nack(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_NACK_MSK); +} + +/** + * @brief Clear stop interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2c_clear_flag_stop(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_STOP_MSK); +} + +/** + * @brief Clear bus error interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2c_clear_flag_berr(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_BERR_MSK); +} + +/** + * @brief Clear lost arbitration interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2c_clear_flag_arlo(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ARLO_MSK); +} + +/** + * @brief Clear pec error interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2c_clear_flag_pece(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_PECE_MSK); +} + +/** + * @brief Clear timeout interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2c_clear_flag_tout(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TOUT_MSK); +} + +/** + * @brief Clear SMBus alert interrupt flag. + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2c_clear_flag_alert(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ALERT_MSK); +} +/** + * @} + */ +/** @defgroup MD_I2C_Public_Functions_Group1 Initialization + * @{ + */ +extern md_status_t md_i2c_init(I2C_TypeDef *I2Cx, md_i2c_init_t *init); +void md_i2c_struct_init(md_i2c_init_t *init); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __MD_I2C_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_i2s.c b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_i2s.c new file mode 100644 index 0000000000..dd73c8a4cb --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_i2s.c @@ -0,0 +1,168 @@ +/** + ********************************************************************************* + * + * @file md_i2s.c + * @brief I2S module driver. + * + * @version V1.0 + * @date 9 Jan. 2023 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 9 Jan. 2023 Shiwa The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ + +#include "md_cmu.h" +#include "md_i2s.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ + +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ +/** @addtogroup MD_I2S + * @{ + */ + +/** @addtogroup MD_I2S_Public_Functions + * @{ + */ +/** @addtogroup MD_I2S_Public_Functions_Group1 + * @{ + */ +/** + * @brief Reset the I2S specificed. + * @param I2Sx: I2S Instance. + * @retval None + */ +void md_i2s_reset(SPI_I2S_TypeDef *I2Sx) +{ + I2Sx->I2SCFG = 0x0; + I2Sx->I2SPR = 0x0; + + return; +} + +/** + * @brief Initialize the I2S registers according to the specified parameters in init. + * @param I2Sx: I2S Instance. + * @param init pointer to a @ref md_i2s_init_t structure + * @retval An ErrorStatus enumeration value. + */ +md_status_t md_i2s_init(SPI_I2S_TypeDef *I2Sx, md_i2s_init_t *init) +{ + uint32_t tmp = 0U, clk, _div; + + if ((I2Sx == NULL) || (init == NULL)) + return MD_ERROR; + + md_i2s_reset(I2Sx); + + tmp |= (init->ext_clk_en << SPI_I2SPR_EXTCKEN_POS); + + /* Get I2S clock */ + if (init->ext_clk_en) + clk = init->ext_clk; + else + clk = md_cmu_get_pclk_clock(); + + if (init->mck_en) + { + _div = (clk + ((init->sampling) << 7)) / ((init->sampling) << 8); + tmp |= SPI_I2SPR_MCKOE_MSK; + } + else + { + if (init->ch_len == MD_I2S_WIDE_16) + _div = ((clk / init->sampling) >> 5); + else + _div = ((clk / init->sampling) >> 6); + } + + if (_div & 0x1) + { + SET_BIT(tmp, SPI_I2SPR_ODD_MSK); + --_div; + } + else + { + CLEAR_BIT(tmp, SPI_I2SPR_ODD_MSK); + } + + if (init->standard != MD_I2S_STD_PCM) + MODIFY_REG(tmp, SPI_I2SPR_I2SDIV_MSK, (_div >> 1) << SPI_I2SPR_I2SDIV_POSS); + else + MODIFY_REG(tmp, SPI_I2SPR_I2SDIV_MSK, _div << SPI_I2SPR_I2SDIV_POSS); + + I2Sx->I2SPR = tmp; + + tmp = I2Sx->I2SCFG; + tmp |= ((init->ch_len << SPI_I2SCFG_CHLEN_POS) | (init->data_len << SPI_I2SCFG_DATLEN_POSS) | + (init->polarity << SPI_I2SCFG_CKPOL_POS) | (init->standard << SPI_I2SCFG_I2SSTD_POSS) | + (1 << SPI_I2SCFG_I2SMOD_POS)); + I2Sx->I2SCFG = tmp; + + if (init->standard == MD_I2S_STD_PCM) + I2Sx->I2SCFG |= (init->pcm_frame << SPI_I2SCFG_PCMSYNC_POS); + + return MD_OK; +} + +/** + * @brief Set each @ref md_i2s_init_t field to default value. + * @param init pointer to a @ref md_i2s_init_t structure + * whose fields will be set to default values. + * @retval None + */ +void md_i2s_struct_init(md_i2s_init_t *init) +{ + init->ch_len = MD_I2S_WIDE_16; + init->data_len = MD_I2S_LEN_16; + init->polarity = MD_I2S_INACTIVE_LOW; + init->standard = MD_I2S_STD_PHI; + init->pcm_frame = MD_I2S_FRAME_SHORT; + init->ext_clk_en = DISABLE; + init->ext_clk = 0x0; + init->mck_en = DISABLE; + init->sampling = 96 * 1024; + + return; +} +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_i2s.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_i2s.h new file mode 100644 index 0000000000..8099becbe5 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_i2s.h @@ -0,0 +1,1358 @@ +/** + ********************************************************************************* + * + * @file md_i2s.h + * @brief Header file of I2S module driver. + * + * @version V1.0 + * @date 02 Aug 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 02 Aug 2022 shiwa The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __MD_I2S_H__ +#define __MD_I2S_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ + +#include "md_utils.h" + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_I2S I2S + * @brief I2S micro driver + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup MD_I2S_Public_Types I2S Public Types + * @{ + */ +/** + * @brief Channel length + */ +typedef enum +{ + MD_I2S_WIDE_16 = 0x0U, /**< Channel length is 16 */ + MD_I2S_WIDE_32 = 0x1U, /**< Channel length is 32 */ +} md_i2s_chlen_t; + +/** + * @brief Data length + */ +typedef enum +{ + MD_I2S_LEN_16 = 0x0U, /**< Data length is 16 */ + MD_I2S_LEN_24 = 0x1U, /**< Data length is 24 */ + MD_I2S_LEN_32 = 0x2U, /**< Data length is 32 */ +} md_i2s_datalen_t; + +/** + * @brief Inactive state clock polarity + */ +typedef enum +{ + MD_I2S_INACTIVE_LOW = 0x0U, /**< Inactive state is low */ + MD_I2S_INACTIVE_HIGH = 0x1U, /**< Inactive state is high */ +} md_i2s_cpol_t; + +/** + * @brief I2s standard + */ +typedef enum +{ + MD_I2S_STD_PHI = 0x0U, /**< Philips standard */ + MD_I2S_STD_MSB = 0x1U, /**< MSB standard */ + MD_I2S_STD_LSB = 0x2U, /**< LSB standard */ + MD_I2S_STD_PCM = 0x3U, /**< PCM standard */ +} md_i2s_standard_t; + +/** + * @brief I2s configuration mode + */ +typedef enum +{ + MD_I2S_SLAVE_DUPLEX = 0x0U, /**< I2S slave full duplex mode */ + MD_I2S_SLAVE_RECEIVE = 0x1U, /**< I2S slave receive mode */ + MD_I2S_SLAVE_TRANSMIT = 0x2U, /**< I2S slave transmit mode */ + MD_I2S_MASTER_DUPLEX = 0x4U, /**< I2S master full duplex mode */ + MD_I2S_MASTER_TRANSMIT = 0x5U, /**< I2S master transmit mode */ + MD_I2S_MASTER_RECEIVE = 0x6U, /**< I2S master receive mode */ +} md_i2s_cfg_t; + +/** + * @brief Pcm frame synchronization + */ +typedef enum +{ + MD_I2S_FRAME_SHORT = 0x0U, /**< I2S PCM short frame */ + MD_I2S_FRAME_LONG = 0x1U, /**< I2S PCM long frame */ +} md_i2s_pcms_t; + +/** + * @brief Channel side + */ +typedef enum +{ + MD_I2S_SIDE_LEFT = 0U, /**< Sound channel is left */ + MD_I2S_SIDE_RIGHT = 1U, /**< Sound channel is right */ +} md_i2s_ch_side_t; + + +/** + * @brief I2S init structure definition + */ +typedef struct +{ + md_i2s_chlen_t ch_len; /**< Channel length choose */ + md_i2s_datalen_t data_len; /**< Data length choose */ + md_i2s_cpol_t polarity; /**< Inactive clock polarity */ + md_i2s_standard_t standard; /**< Standard choose */ + md_i2s_pcms_t pcm_frame; /**< PCM frame synchronization */ + type_func_t ext_clk_en; /**< Choose external clock or APB1 clock */ + uint32_t ext_clk; /**< External clock, unit is Hz */ + type_func_t mck_en; /**< Main clock output function */ + uint32_t sampling; /**< Sampling rate. eg. 192KHz/96KHz/48KHz */ +} md_i2s_init_t; +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @defgroup MD_I2S_Public_Functions I2S Public Functions + * @{ + */ +/** @defgroup MD_I2S_Public_Functions_Group2 CON2 + * @{ + */ +/** + * @brief Set I2S receive fifo threshold. + * @param I2Sx: I2S Instance. + * @param rxth: rx fifo threshold(1, 4, 8, 11) + * - 0: 1 char + * - 1: 4 chars + * - 2: 8 chars + * - 3: 14 chars + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_rxfifo_threshold(SPI_I2S_TypeDef *I2Sx, uint8_t rxth) +{ + MODIFY_REG(I2Sx->CON2, SPI_CON2_RXFTH_MSK, (rxth << SPI_CON2_RXFTH_POSS)); +} + +/** + * @brief Get I2S receive fifo threshold. + * @param I2Sx: I2S Instance. + * @retval RX fifo threshold. + * - 0: 1 char + * - 1: 4 chars + * - 2: 8 chars + * - 3: 14 chars + */ +__STATIC_INLINE uint8_t md_i2s_get_rxfifo_threshold(SPI_I2S_TypeDef *I2Sx) +{ + return READ_BITS(I2Sx->CON2, SPI_CON2_RXFTH_MSK, SPI_CON2_RXFTH_POSS); +} + +/** + * @brief Set I2S transmit fifo threshold. + * @param I2Sx: I2S Instance. + * @param txth: RX fifo threshold(1, 4, 8, 11) + * - 0: 1 char + * - 1: 4 chars + * - 2: 8 chars + * - 3: 14 chars + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_txfifo_threshold(SPI_I2S_TypeDef *I2Sx, uint8_t txth) +{ + MODIFY_REG(I2Sx->CON2, SPI_CON2_TXFTH_MSK, (txth << SPI_CON2_TXFTH_POSS)); +} + +/** + * @brief Get spi transmit fifo threshold. + * @param I2Sx: SPI Instance. + * @retval TX fifo threshold. + * - 0: 1 char + * - 1: 4 chars + * - 2: 8 chars + * - 3: 14 chars + */ +__STATIC_INLINE uint8_t md_i2s_get_txfifo_threshold(SPI_I2S_TypeDef *I2Sx) +{ + return READ_BITS(I2Sx->CON2, SPI_CON2_TXFTH_MSK, SPI_CON2_TXFTH_POSS); +} + +/** + * @brief Enable I2S tx_dma function. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_enable_txdma(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->CON2, SPI_CON2_TXDMA_MSK); +} + +/** + * @brief Disable I2S error interrupt. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_disable_txdma(SPI_I2S_TypeDef *I2Sx) +{ + CLEAR_BIT(I2Sx->CON2, SPI_CON2_TXDMA_MSK); +} + +/** + * @brief Check if I2S is enable txdma. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enable_txdma(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->CON2, SPI_CON2_TXDMA_MSK) == SPI_CON2_TXDMA_MSK); +} + +/** + * @brief Enable I2S rx_dma function. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_enable_rxdma(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->CON2, SPI_CON2_RXDMA_MSK); +} + +/** + * @brief Disable I2S rx_dma function. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_disable_rxdma(SPI_I2S_TypeDef *I2Sx) +{ + CLEAR_BIT(I2Sx->CON2, SPI_CON2_RXDMA_MSK); +} + +/** + * @brief Check if I2S is enable rxdma. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enable_rxdma(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->CON2, SPI_CON2_RXDMA_MSK) == SPI_CON2_RXDMA_MSK); +} +/** + * @} + */ +/** @defgroup MD_I2S_Public_Functions_Group3 STAT + * @{ + */ +/** + * @brief Get I2S rxfifo value. + * @param I2Sx: I2S Instance. + * @retval rxfifo threshold. + */ +__STATIC_INLINE uint32_t md_i2s_get_rxfifo_value(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BITS(I2Sx->STAT, SPI_STAT_RXFLV_MSK, SPI_STAT_RXFLV_POSS)); +} + +/** + * @brief Get I2S txfifo value. + * @param I2Sx: I2S Instance. + * @retval txfifo threshold. + */ +__STATIC_INLINE uint32_t md_i2s_get_txfifo_value(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BITS(I2Sx->STAT, SPI_STAT_TXFLV_MSK, SPI_STAT_TXFLV_POSS)); +} + +/** + * @brief Get I2S busy flag. + * @param I2Sx: I2S Instance. + * @retval State I2S bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_busy(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->STAT, SPI_STAT_BUSY_MSK) == SPI_STAT_BUSY_MSK); +} + +/** + * @brief Get I2S channel side flag. + * @param I2Sx: I2S Instance. + * @retval channel flag (0: left or 1: right). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_chside(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->STAT, SPI_STAT_CHSIDE_MSK) == SPI_STAT_CHSIDE_MSK); +} + +/** + * @brief Get I2S rx threshold flag. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_rxth(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->STAT, SPI_STAT_RXTH_MSK) == SPI_STAT_RXTH_MSK); +} + +/** + * @brief Get I2S rx under flow flag. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_get_flag_rxud(SPI_I2S_TypeDef *I2Sx) +{ + return ((I2Sx->STAT, SPI_STAT_RXUD_MSK) == SPI_STAT_RXUD_MSK); +} + +/** + * @brief Get I2S rx over flow flag. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_get_flag_rxov(SPI_I2S_TypeDef *I2Sx) +{ + return ((I2Sx->STAT, SPI_STAT_RXOV_MSK) == SPI_STAT_RXOV_MSK); +} + +/** + * @brief Get I2S rx buffer full flag. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_rxf(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->STAT, SPI_STAT_RXF_MSK) == SPI_STAT_RXF_MSK); +} + +/** + * @brief Get I2S rx buffer empty flag. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_rxne(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->STAT, SPI_STAT_RXNE_MSK) == SPI_STAT_RXNE_MSK); +} + +/** + * @brief Get I2S tx threshold flag. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_txth(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->STAT, SPI_STAT_TXTH_MSK) == SPI_STAT_TXTH_MSK); +} + +/** + * @brief Get I2S tx under flow flag. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_get_flag_txud(SPI_I2S_TypeDef *I2Sx) +{ + return ((I2Sx->STAT, SPI_STAT_TXUD_MSK) == SPI_STAT_TXUD_MSK); +} + +/** + * @brief Get I2S tx over flow flag. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_get_flag_txov(SPI_I2S_TypeDef *I2Sx) +{ + return ((I2Sx->STAT, SPI_STAT_TXOV_MSK) == SPI_STAT_TXOV_MSK); +} + +/** + * @brief Get I2S tx buffer full flag. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_txf(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->STAT, SPI_STAT_TXF_MSK) == SPI_STAT_TXF_MSK); +} + +/** + * @brief Get I2S tx buffer empty flag. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_txe(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->STAT, SPI_STAT_TXE_MSK) == SPI_STAT_TXE_MSK); +} +/** + * @} + */ +/** @defgroup MD_I2S_Public_Functions_Group4 DATA + * @{ + */ +/** + * @brief Set I2S data register value. + * @param I2Sx: I2S Instance. + * @param data: tx data. + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_data_reg(SPI_I2S_TypeDef *I2Sx, uint32_t data) +{ + WRITE_REG(I2Sx->DATA, data); +} + +/** + * @brief Get I2S data register value. + * @param I2Sx: I2S Instance. + * @retval data: value for data register. + */ +__STATIC_INLINE uint32_t md_i2s_get_data_reg_value(SPI_I2S_TypeDef *I2Sx) +{ + return READ_REG(I2Sx->DATA); +} +/** + * @} + */ +/** @defgroup MD_I2S_Public_Functions_Group5 I2SCFG + * @{ + */ +/** + * @brief Set I2S mode. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_chose_i2s(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->I2SCFG, SPI_I2SCFG_I2SMOD_MSK); +} + +/** + * @brief Check is set I2S mode. + * @param I2Sx: I2S Instance. + * @retval State of bit (0:SPI or 1:I2S). + */ +__STATIC_INLINE uint32_t md_i2s_is_set_i2s_mode(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->I2SCFG, SPI_I2SCFG_I2SMOD_MSK) == SPI_I2SCFG_I2SMOD_MSK); +} + +/** + * @brief Enable I2S module. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_enable(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->I2SCFG, SPI_I2SCFG_I2SE_MSK); +} + +/** + * @brief Disable I2S module. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_disable(SPI_I2S_TypeDef *I2Sx) +{ + CLEAR_BIT(I2Sx->I2SCFG, SPI_I2SCFG_I2SE_MSK); +} + +/** + * @brief Check if I2S is enable. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enable(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->I2SCFG, SPI_I2SCFG_I2SE_MSK) == SPI_I2SCFG_I2SE_MSK); +} + +/** + * @brief Set TX/RX mode. + * @param I2Sx: I2S Instance. + * @param mode: 0x2 - TX, 0x3 - RX. + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_mode(SPI_I2S_TypeDef *I2Sx, uint32_t mode) +{ + MODIFY_REG(I2Sx->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, mode << SPI_I2SCFG_I2SCFG_POSS); +} + +/** + * @brief Get TX/RX mode. + * @param I2Sx: I2S Instance. + * @retval Mode: + * - 0x2: TX + * - 0x3: RX + */ +__STATIC_INLINE uint32_t md_i2s_get_mode(SPI_I2S_TypeDef *I2Sx) +{ + return READ_BITS(I2Sx->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, SPI_I2SCFG_I2SCFG_POSS); +} + +/** + * @brief Set PCM short frame. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_short_frame(SPI_I2S_TypeDef *I2Sx) +{ + CLEAR_BIT(I2Sx->I2SCFG, SPI_I2SCFG_PCMSYNC_MSK); +} + +/** + * @brief Set PCM long frame. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_long_frame(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->I2SCFG, SPI_I2SCFG_PCMSYNC_MSK); +} + +/** + * @brief Get PCM frame mode. + * @param I2Sx: I2S Instance. + * @retval PCM frame mode: + * -0: Short frame + * -1: Long frame + */ +__STATIC_INLINE uint32_t md_i2s_get_frame_mode(SPI_I2S_TypeDef *I2Sx) +{ + return READ_BITS(I2Sx->I2SCFG, SPI_I2SCFG_PCMSYNC_MSK, SPI_I2SCFG_PCMSYNC_POS); +} + +/** + * @brief Set I2S standard. + * @param I2Sx: I2S Instance. + * @param std: I2S standard, @ref md_i2s_standard_t + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_standard(SPI_I2S_TypeDef *I2Sx, md_i2s_standard_t std) +{ + MODIFY_REG(I2Sx->I2SCFG, SPI_I2SCFG_I2SSTD_MSK, std << SPI_I2SCFG_I2SSTD_POSS); +} + +/** + * @brief Get I2S standard. + * @param I2Sx: I2S Instance. + * @retval I2S standard, @ref md_i2s_standard_t + */ +__STATIC_INLINE md_i2s_standard_t md_i2s_get_standard(SPI_I2S_TypeDef *I2Sx) +{ + return (md_i2s_standard_t)READ_BITS(I2Sx->I2SCFG, SPI_I2SCFG_I2SSTD_MSK, SPI_I2SCFG_I2SSTD_POSS); +} + +/** + * @brief Set I2S clock polarity. + * @param I2Sx: I2S Instance. + * @param pol: 0 - low, 1 - high. + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_inactive_polarity(SPI_I2S_TypeDef *I2Sx, uint32_t pol) +{ + MODIFY_REG(I2Sx->I2SCFG, SPI_I2SCFG_CKPOL_MSK, pol << SPI_I2SCFG_CKPOL_POS); +} + +/** + * @brief Get I2S clock polarity. + * @param I2Sx: I2S Instance. + * @retval I2S polarity: + * - 0: low + * - 1: high + */ +__STATIC_INLINE uint32_t md_i2s_get_inactive_polarity(SPI_I2S_TypeDef *I2Sx) +{ + return READ_BITS(I2Sx->I2SCFG, SPI_I2SCFG_CKPOL_MSK, SPI_I2SCFG_CKPOL_POS); +} + +/** + * @brief Set I2S data length. + * @param I2Sx: I2S Instance. + * @param length: + * - 0: 16-bits + * - 1: 24-bits + * - 2: 32-bits + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_data_length(SPI_I2S_TypeDef *I2Sx, uint32_t length) +{ + MODIFY_REG(I2Sx->I2SCFG, SPI_I2SCFG_DATLEN_MSK, length << SPI_I2SCFG_DATLEN_POSS); +} + +/** + * @brief Get I2S data length. + * @param I2Sx: I2S Instance. + * @retval Data length: + * - 0: 16-bits + * - 1: 24-bits + * - 2: 32-bits + */ +__STATIC_INLINE uint32_t md_i2s_get_data_length(SPI_I2S_TypeDef *I2Sx) +{ + return READ_BITS(I2Sx->I2SCFG, SPI_I2SCFG_DATLEN_MSK, SPI_I2SCFG_DATLEN_POSS); +} + +/** + * @brief Set I2S channel length. + * @param I2Sx: I2S Instance. + * @param length: + * - 0: 16-bits + * - 1: 32-bits + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_channel_length(SPI_I2S_TypeDef *I2Sx, uint32_t length) +{ + MODIFY_REG(I2Sx->I2SCFG, SPI_I2SCFG_CHLEN_MSK, length << SPI_I2SCFG_CHLEN_POS); +} + +/** + * @brief Get I2S channel length. + * @param I2Sx: I2S Instance. + * @retval Channel length: + * - 0: 16-bits + * - 1: 32-bits + */ +__STATIC_INLINE uint32_t md_i2s_get_channel_length(SPI_I2S_TypeDef *I2Sx) +{ + return READ_BITS(I2Sx->I2SCFG, SPI_I2SCFG_CHLEN_MSK, SPI_I2SCFG_CHLEN_POS); +} +/** + * @} + */ +/** @defgroup MD_I2S_Public_Functions_Group6 I2SPR + * @{ + */ +/** + * @brief Set I2S clock source. + * @param I2Sx: I2S Instance. + * @param clk: Clock source + * - 0: APB1 + * - 1: Extend clock + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_clock_cource(SPI_I2S_TypeDef *I2Sx, uint32_t clk) +{ + MODIFY_REG(I2Sx->I2SPR, SPI_I2SPR_EXTCKEN_MSK, clk << SPI_I2SPR_EXTCKEN_POS); +} + +/** + * @brief Get I2S clock source. + * @param I2Sx: I2S Instance. + * @retval Clock source: + * - 0: APB1 + * - 1: Extend clock + */ +__STATIC_INLINE uint32_t md_i2s_get_clock_cource(SPI_I2S_TypeDef *I2Sx) +{ + return READ_BITS(I2Sx->I2SPR, SPI_I2SPR_EXTCKEN_MSK, SPI_I2SPR_EXTCKEN_POS); +} + +/** + * @brief Enable I2S main clock output. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_enable_mclock(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->I2SPR, SPI_I2SPR_MCKOE_MSK); +} + +/** + * @brief Disable I2S main clock output. + * @param I2Sx: I2S Instance. + * @retval None. + */ +__STATIC_INLINE void md_i2s_disable_mclock(SPI_I2S_TypeDef *I2Sx) +{ + CLEAR_BIT(I2Sx->I2SPR, SPI_I2SPR_MCKOE_MSK); +} + +/** + * @brief Check if main clock output is enable. + * @param I2Sx: I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enable_mclock(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->I2SPR, SPI_I2SPR_MCKOE_MSK) == SPI_I2SPR_MCKOE_MSK); +} + +/** + * @brief Set I2S odd coefficient. + * @param I2Sx: I2S Instance. + * @param odd: Odd coefficient + * - 0: Frequency division = I2SDIV * 2 + * - 1: Frequency division = (I2SDIV * 2) + 1 + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_div_odd(SPI_I2S_TypeDef *I2Sx, uint32_t odd) +{ + MODIFY_REG(I2Sx->I2SPR, SPI_I2SPR_ODD_MSK, odd << SPI_I2SPR_ODD_POS); +} + +/** + * @brief Get I2S odd coefficient. + * @param I2Sx: I2S Instance. + * @retval Odd coefficient: + * - 0: Frequency division = I2SDIV * 2 + * - 1: Frequency division = (I2SDIV * 2) + 1 + */ +__STATIC_INLINE uint32_t md_i2s_get_div_odd(SPI_I2S_TypeDef *I2Sx) +{ + return READ_BITS(I2Sx->I2SPR, SPI_I2SPR_ODD_MSK, SPI_I2SPR_ODD_POS); +} + +/** + * @brief Set I2S division + * @param I2Sx: I2S Instance. + * @param div: Frequency division. + * @retval None. + */ +__STATIC_INLINE void md_i2s_set_div(SPI_I2S_TypeDef *I2Sx, uint32_t div) +{ + MODIFY_REG(I2Sx->I2SPR, SPI_I2SPR_I2SDIV_MSK, div << SPI_I2SPR_I2SDIV_POSS); +} + +/** + * @brief Get I2S division. + * @param I2Sx: I2S Instance. + * @retval Frequency division. + */ +__STATIC_INLINE uint32_t md_i2s_get_div(SPI_I2S_TypeDef *I2Sx) +{ + return READ_BITS(I2Sx->I2SPR, SPI_I2SPR_I2SDIV_MSK, SPI_I2SPR_I2SDIV_POSS); +} +/** + * @} + */ +/** @defgroup MD_I2S_Public_Functions_Group7 IER + * @{ + */ +/** + * @brief Enable I2S frame error interrupt. + * @param I2Sx I2S Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_enable_it_fre(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->IER, SPI_IER_FRE_MSK); +} + +/** + * @brief Enable I2S rx threshold interrupt. + * @param I2Sx I2S Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_enable_it_rxth(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->IER, SPI_IER_RXTH_MSK); +} + +/** + * @brief Enable I2S rx under flow interrupt. + * @param I2Sx I2S Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_enable_it_rxud(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->IER, SPI_IER_RXUD_MSK); +} + + +/** + * @brief Enable I2S rx over flow interrupt. + * @param I2Sx I2S Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_enable_it_rxov(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->IER, SPI_IER_RXOV_MSK); +} + +/** + * @brief Enable I2S rx full interrupt. + * @param I2Sx I2S Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_enable_it_rxf(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->IER, SPI_IER_RXF_MSK); +} + +/** + * @brief Enable I2S tx threshold interrupt. + * @param I2Sx I2S Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_enable_it_txth(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->IER, SPI_IER_TXTH_MSK); +} + +/** + * @brief Enable I2S tx under flow interrupt. + * @param I2Sx I2S Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_enable_it_txud(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->IER, SPI_IER_TXUD_MSK); +} + +/** + * @brief Enable I2S tx over flow interrupt. + * @param I2Sx I2S Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_enable_it_txov(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->IER, SPI_IER_TXOV_MSK); +} + +/** + * @brief Enable I2S tx empty interrupt. + * @param I2Sx I2S Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_enable_it_txe(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->IER, SPI_IER_TXE_MSK); +} +/** + * @} + */ +/** @defgroup MD_I2S_Public_Functions_Group8 IDR + * @{ + */ +/** + * @brief Disable I2S frame error interrupt. + * @param I2Sx I2S Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_disable_it_fre(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->IDR, SPI_IDR_FRE_MSK); +} + +/** + * @brief Disable I2S rx threshold interrupt. + * @param I2Sx I2S Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_disable_it_rxth(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->IDR, SPI_IDR_RXTH_MSK); +} + +/** + * @brief Disable I2S rx under flow interrupt. + * @param I2Sx I2S Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_disable_it_rxud(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->IDR, SPI_IDR_RXUD_MSK); +} + +/** + * @brief Disable I2S rx over flow interrupt. + * @param I2Sx I2S Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_disable_it_rxov(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->IDR, SPI_IDR_RXOV_MSK); +} + +/** + * @brief Disable I2S rx full interrupt. + * @param I2Sx I2S Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_disable_it_rxf(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->IDR, SPI_IDR_RXF_MSK); +} + +/** + * @brief Disable I2S tx threshold interrupt. + * @param I2Sx I2S Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_disable_it_txth(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->IDR, SPI_IDR_TXTH_MSK); +} + +/** + * @brief Disable I2S tx under flow interrupt. + * @param I2Sx I2S Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_disable_it_txud(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->IDR, SPI_IDR_TXUD_MSK); +} + +/** + * @brief Disable I2S tx over flow interrupt. + * @param I2Sx I2S Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_disable_it_txov(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->IDR, SPI_IDR_TXOV_MSK); +} + +/** + * @brief Disable I2S tx empty interrupt. + * @param I2Sx I2S Instance. + * @retval None + */ +__STATIC_INLINE void md_i2s_disable_it_txe(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->IDR, SPI_IDR_TXE_MSK); +} +/** + * @} + */ +/** @defgroup MD_I2S_Public_Functions_Group9 IVS + * @{ + */ +/** + * @brief Check if the frame error interrupt is enabled or disabled. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enable_it_fre(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->IVS, SPI_IVS_FRE_MSK) == (SPI_IVS_FRE_MSK)); +} + +/** + * @brief Check if the rx threshold interrupt is enabled or disabled. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enable_it_rxth(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->IVS, SPI_IVS_RXTH_MSK) == (SPI_IVS_RXTH_MSK)); +} + +/** + * @brief Check if the rx under flow interrupt is enabled or disabled. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enable_it_rxud(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->IVS, SPI_IVS_RXUD_MSK) == (SPI_IVS_RXUD_MSK)); +} + +/** + * @brief Check if the rx over flow interrupt is enabled or disabled. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enable_it_rxov(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->IVS, SPI_IVS_RXOV_MSK) == (SPI_IVS_RXOV_MSK)); +} + +/** + * @brief Check if the rx full interrupt is enabled or disabled. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enable_it_rxf(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->IVS, SPI_IVS_RXF_MSK) == (SPI_IVS_RXF_MSK)); +} + +/** + * @brief Check if the tx threshold interrupt is enabled or disabled. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enable_it_txth(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->IVS, SPI_IVS_TXTH_MSK) == (SPI_IVS_TXTH_MSK)); +} + +/** + * @brief Check if the tx under flow interrupt is enabled or disabled. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enable_it_txud(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->IVS, SPI_IVS_TXUD_MSK) == (SPI_IVS_TXUD_MSK)); +} + +/** + * @brief Check if the tx over flow interrupt is enabled or disabled. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enable_it_txov(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->IVS, SPI_IVS_TXOV_MSK) == (SPI_IVS_TXOV_MSK)); +} + +/** + * @brief Check if the tx empty interrupt is enabled or disabled. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_enable_it_txe(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->IVS, SPI_IVS_TXE_MSK) == (SPI_IVS_TXE_MSK)); +} +/** + * @} + */ +/** @defgroup MD_I2S_Public_Functions_Group10 RIF + * @{ + */ +/** + * @brief Get frame error interrupt flag. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_flag_fre(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->RIF, SPI_RIF_FRE_MSK) == (SPI_RIF_FRE_MSK)); +} + +/** + * @brief Get rx threshold interrupt flag. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_it_rxth(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->RIF, SPI_RIF_RXTH_MSK) == (SPI_RIF_RXTH_MSK)); +} + +/** + * @brief Get rx under flow interrupt flag. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_it_rxud(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->RIF, SPI_RIF_RXUD_MSK) == (SPI_RIF_RXUD_MSK)); +} + +/** + * @brief Get rx over flow interrupt flag. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_it_rxov(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->RIF, SPI_RIF_RXOV_MSK) == (SPI_RIF_RXOV_MSK)); +} + +/** + * @brief Get rx full interrupt flag. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_it_rxf(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->RIF, SPI_RIF_RXF_MSK) == (SPI_RIF_RXF_MSK)); +} + +/** + * @brief Get tx threshold interrupt flag. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_it_txth(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->RIF, SPI_RIF_TXTH_MSK) == (SPI_RIF_TXTH_MSK)); +} + +/** + * @brief Get tx under flow interrupt flag. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_it_txud(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->RIF, SPI_RIF_TXUD_MSK) == (SPI_RIF_TXUD_MSK)); +} + +/** + * @brief Get tx over flow interrupt flag. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_it_txov(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->RIF, SPI_RIF_TXOV_MSK) == (SPI_RIF_TXOV_MSK)); +} + +/** + * @brief Get tx empty interrupt flag. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_is_active_it_txe(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->RIF, SPI_RIF_TXE_MSK) == (SPI_RIF_TXE_MSK)); +} +/** + * @} + */ +/** @defgroup MD_I2S_Public_Functions_Group11 IFM + * @{ + */ +/** + * @brief Mask frame error interrupt. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_mask_it_fre(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->IFM, SPI_IFM_FRE_MSK) == SPI_IFM_FRE_MSK); +} + +/** + * @brief Mask rx threshold interrupt. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_mask_it_rxth(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->IFM, SPI_IFM_RXTH_MSK) == SPI_IFM_RXTH_MSK); +} + +/** + * @brief Mask rx under flow interrupt. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_mask_it_rxud(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->IFM, SPI_IFM_RXUD_MSK) == SPI_IFM_RXUD_MSK); +} + +/** + * @brief Mask rx over flow interrupt. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_mask_it_rxov(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->IFM, SPI_IFM_RXOV_MSK) == SPI_IFM_RXOV_MSK); +} + +/** + * @brief Mask rx full interrupt. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_mask_it_rxf(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->IFM, SPI_IFM_RXF_MSK) == SPI_IFM_RXF_MSK); +} + +/** + * @brief Mask tx threshold interrupt. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_mask_it_txth(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->IFM, SPI_IFM_TXTH_MSK) == SPI_IFM_TXTH_MSK); +} + +/** + * @brief Mask tx under flow interrupt. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_mask_it_txud(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->IFM, SPI_IFM_TXUD_MSK) == SPI_IFM_TXUD_MSK); +} + +/** + * @brief Mask tx over flow interrupt. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_mask_it_txov(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->IFM, SPI_IFM_TXOV_MSK) == SPI_IFM_TXOV_MSK); +} + +/** + * @brief Mask tx empty interrupt. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2s_mask_it_txe(SPI_I2S_TypeDef *I2Sx) +{ + return (READ_BIT(I2Sx->IFM, SPI_IFM_TXE_MSK) == SPI_IFM_TXE_MSK); +} +/** + * @} + */ +/** @defgroup MD_I2S_Public_Functions_Group12 ICR + * @{ + */ +/** + * @brief Clear frame error interrupt flag. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2s_clear_flag_fre(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->ICR, SPI_ICR_FRE_MSK); +} + +/** + * @brief Clear rx under flow interrupt flag. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2s_clear_flag_rxth(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->ICR, SPI_ICR_RXTH_MSK); +} + +/** + * @brief Clear rx under flow interrupt flag. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2s_clear_flag_rxud(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->ICR, SPI_ICR_RXUD_MSK); +} + +/** + * @brief Clear rx over flow interrupt flag. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2s_clear_flag_rxov(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->ICR, SPI_ICR_RXOV_MSK); +} + +/** + * @brief Clear rx full interrupt flag. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2s_clear_flag_rxf(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->ICR, SPI_ICR_RXF_MSK); +} + +/** + * @brief Clear tx under flow interrupt flag. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2s_clear_flag_txth(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->ICR, SPI_ICR_TXTH_MSK); +} + +/** + * @brief Clear tx under flow interrupt flag. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2s_clear_flag_txud(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->ICR, SPI_ICR_TXUD_MSK); +} + +/** + * @brief Clear tx over flow interrupt flag. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2s_clear_flag_txov(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->ICR, SPI_ICR_TXOV_MSK); +} + +/** + * @brief Clear tx empty interrupt flag. + * @param I2Sx I2S Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_i2s_clear_flag_txe(SPI_I2S_TypeDef *I2Sx) +{ + SET_BIT(I2Sx->ICR, SPI_ICR_TXE_MSK); +} +/** + * @} + */ +/** @defgroup MD_I2S_Public_Functions_Group1 Initialization + * @{ + */ +extern void md_i2s_reset(SPI_I2S_TypeDef *I2Sx); +extern md_status_t md_i2s_init(SPI_I2S_TypeDef *I2Sx, md_i2s_init_t *init); +extern void md_i2s_struct_init(md_i2s_init_t *init); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __MD_I2S_H__ */ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_iwdt.c b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_iwdt.c new file mode 100644 index 0000000000..e9c8edc9a9 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_iwdt.c @@ -0,0 +1,130 @@ +/********************************************************************************** + * + * @file md_iwdt.c + * @brief IWDT module driver. + * + * @date 20 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 20 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_iwdt.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ + +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_IWDT IWDT + * @{ + */ +/** @addtogroup MD_IWDT_Public_Functions + * @{ + */ + +/** @addtogroup MD_IWDT_Public_Functions_Group1 + * @{ + */ +/** + * @brief Initializes the IWDT according to the specified parameters. + * @param load: Specifies the free-running downcounter value. + * @param interrupt: Enable or disable interrupt. + * @retval None + */ +void md_iwdt_init(uint32_t load, type_func_t interrupt) +{ + assert_param(IS_FUNC_STATE(interrupt)); + + IWDT_UNLOCK(); + md_iwdt_set_count_overload(load); + md_iwdt_set_count_clock2(); + md_iwdt_enable_reset(); + + if (interrupt == ENABLE) + { + md_iwdt_enable_interrupt(); + } + else + { + md_iwdt_disable_interrupt(); + } + + IWDT_LOCK(); + + return; +} + +/** + * @brief Initializes the IWDT without reset according to the specified parameters. + * @param load: Specifies the free-running downcounter value. + * @param interrupt: Enable or disable interrupt. + * @retval None + */ +void md_iwdt_init_no_reset(uint32_t load, type_func_t interrupt) +{ + assert_param(IS_FUNC_STATE(interrupt)); + + IWDT_UNLOCK(); + md_iwdt_set_count_overload(load); + md_iwdt_set_count_clock2(); + md_iwdt_disable_reset(); + + if (interrupt == ENABLE) + { + md_iwdt_enable_interrupt(); + } + else + { + md_iwdt_disable_interrupt(); + } + + IWDT_LOCK(); + + return; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_iwdt.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_iwdt.h new file mode 100644 index 0000000000..e5b514a8bc --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_iwdt.h @@ -0,0 +1,298 @@ +/********************************************************************************** + * + * @file md_iwdt.h + * @brief Header file of IWDT module driver. + * + * @date 20 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 20 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __MD_IWDT_H__ +#define __MD_IWDT_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_utils.h" + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_IWDT IWDT + * @{ + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** + * @defgroup MD_IWDT_Private_Macros IWDT Private Macros + * @{ + */ +#define IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551U);} +#define IWDT_LOCK() {WRITE_REG(IWDT->LOCK, 0xFFFFFFFFU);} + +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @defgroup MD_IWDT_Public_Functions IWDT Public Functions + * @{ + */ +/** @defgroup MD_IWDT_Public_Functions_Group2 LOAD + * @{ + */ +/** +* @brief Set iwdt count overload value. +* @param cnt: iwdt overload value. +* @retval None +*/ +__STATIC_INLINE void md_iwdt_set_count_overload(uint32_t cnt) +{ + MODIFY_REG(IWDT->LOAD_, IWDT_LOAD_LOAD_MSK, cnt << IWDT_LOAD_LOAD_POSS); +} +/** + * @} + */ +/** @defgroup MD_IWDT_Public_Functions_Group3 VALUE + * @{ + */ +/** + * @brief Get iwdt current count value. + * @retval Value for count value + */ +__STATIC_INLINE uint32_t md_iwdt_get_count_value(void) +{ + return READ_BITS(IWDT->VALUE, IWDT_VALUE_VALUE_MSK, IWDT_VALUE_VALUE_POSS); +} +/** + * @} + */ +/** @defgroup MD_IWDT_Public_Functions_Group4 CON + * @{ + */ +/** + * @brief Set iwdt count clock 1. + * @retval None + */ +__STATIC_INLINE void md_iwdt_set_count_clock1(void) +{ + CLEAR_BIT(IWDT->CON, IWDT_CON_CLKS_MSK); +} + +/** + * @brief Set iwdt count clock 2. + * @retval None + */ +__STATIC_INLINE void md_iwdt_set_count_clock2(void) +{ + SET_BIT(IWDT->CON, IWDT_CON_CLKS_MSK); +} + +/** + * @brief Check if iwdt count clock is clock1 source. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint8_t md_iwdt_is_enable_count_clock1(void) +{ + return (READ_BIT(IWDT->CON, IWDT_CON_CLKS_MSK) != IWDT_CON_CLKS_MSK); +} + +/** + * @brief Check if iwdt count clock is clock2 source. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint8_t md_iwdt_is_enable_count_clock2(void) +{ + return (READ_BIT(IWDT->CON, IWDT_CON_CLKS_MSK) == IWDT_CON_CLKS_MSK); +} + +/** + * @brief Enable iwdt reset bit. + * @retval None + */ +__STATIC_INLINE void md_iwdt_enable_reset(void) +{ + SET_BIT(IWDT->CON, IWDT_CON_RSTEN_MSK); +} + +/** + * @brief Disable iwdt reset bit. + * @retval None + */ +__STATIC_INLINE void md_iwdt_disable_reset(void) +{ + CLEAR_BIT(IWDT->CON, IWDT_CON_RSTEN_MSK); +} + +/** + * @brief Check if is enable reset bit. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint8_t md_iwdt_is_enable_reset(void) +{ + return (READ_BIT(IWDT->CON, IWDT_CON_RSTEN_MSK) == IWDT_CON_RSTEN_MSK); +} + +/** + * @brief Enable iwdt interrupt. + * @retval None + */ +__STATIC_INLINE void md_iwdt_enable_interrupt(void) +{ + SET_BIT(IWDT->CON, IWDT_CON_IE_MSK); +} + +/** + * @brief Disable iwdt interrupt. + * @retval None + */ +__STATIC_INLINE void md_iwdt_disable_interrupt(void) +{ + CLEAR_BIT(IWDT->CON, IWDT_CON_IE_MSK); +} + +/** + * @brief Check if is enable interrupt. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint8_t md_iwdt_is_enable_interrupt(void) +{ + return (READ_BIT(IWDT->CON, IWDT_CON_IE_MSK) == IWDT_CON_IE_MSK); +} + +/** + * @brief Enable iwdt module. + * @retval None + */ +__STATIC_INLINE void md_iwdt_enable(void) +{ + SET_BIT(IWDT->CON, IWDT_CON_EN_MSK); +} + +/** + * @brief Disable iwdt interrupt. + * @retval None + */ +__STATIC_INLINE void md_iwdt_disable(void) +{ + CLEAR_BIT(IWDT->CON, IWDT_CON_EN_MSK); +} + +/** + * @brief Check if is enable interrupt. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint8_t md_iwdt_is_enable(void) +{ + return (READ_BIT(IWDT->CON, IWDT_CON_EN_MSK) == IWDT_CON_EN_MSK); +} +/** + * @} + */ +/** @defgroup MD_IWDT_Public_Functions_Group5 INTCLR + * @{ + */ +/** + * @brief Clear iwdt Interrupt flag. + * @retval None + */ +__STATIC_INLINE void md_iwdt_clear_flag_interrupt(void) +{ + WRITE_REG(IWDT->INTCLR, 0x55AAU); +} +/** + * @brief feed iwdt. + * @retval None + */ +__STATIC_INLINE void md_iwdt_feed_iwdt(void) +{ + WRITE_REG(IWDT->INTCLR, 0xFFFFFFFFU); +} +/** + * @} + */ +/** @defgroup MD_IWDT_Public_Functions_Group6 RIS + * @{ + */ +/** + * @brief Get iwdt interrupt flag. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint8_t md_iwdt_is_active_flag_interrupt(void) +{ + return (READ_BIT(IWDT->RIS, IWDT_RIS_WDTIF_MSK) == IWDT_RIS_WDTIF_MSK); +} +/** + * @} + */ +/** @defgroup MD_IWDT_Public_Functions_Group7 LOCK + * @{ + */ +/** + * @brief Get iwdt project register status. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint8_t md_iwdt_is_active_flag_lock(void) +{ + return (READ_BIT(IWDT->LOCK, IWDT_LOCK_LOCK_MSK) == IWDT_LOCK_LOCK_MSK); +} + +/** + * @} + */ +/** @defgroup MD_IWDT_Public_Functions_Group1 Initialization + * @{ + */ +extern void md_iwdt_init(uint32_t load, type_func_t interrupt); +extern void md_iwdt_init_no_reset(uint32_t load, type_func_t interrupt); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __MD_IWDT_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_msc.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_msc.h new file mode 100644 index 0000000000..ebeaa34513 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_msc.h @@ -0,0 +1,335 @@ +/********************************************************************************** + * + * @file md_msc.h + * @brief Header file of MSC module driver. + * + * @date 15 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 15 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __MD_MSC_H__ +#define __MD_MSC_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_utils.h" + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Variables -------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** @defgroup MD_MSC MSC + * @brief MSC module driver + * @{ + */ +/** + * @defgroup MD_MSC_Public_Macros MSC Public Macros + * @{ + */ +#define FLASH_REG_UNLOCK() \ + do { \ + WRITE_REG(MSC->FLASHKEY, 0x8ACE0246); \ + WRITE_REG(MSC->FLASHKEY, 0x9BDF1357); \ + } while (0) + +#define FLASH_REG_LOCK() \ + do { \ + WRITE_REG(MSC->FLASHKEY, 0x0); \ + WRITE_REG(MSC->FLASHKEY, 0x0); \ + } while (0) + + +#define MD_MSC_CODE_WSP_ADDR 0x10000000U +#define MD_MSC_CODE_PE_ADDR 0x10000004U +#define MD_MSC_CODE_WP_ADDR 0x10000008U + +#define MD_MSC_DATA_WSP_ADDR 0x10000010U +#define MD_MSC_DATA_PE_ADDR 0x10000014U +#define MD_MSC_DATA_WP_ADDR 0x10000018U +/** + * @} + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup MD_MSC_Private_Types MSC Private Types + * @{ + */ +typedef uint32_t (*MD_MSC_PE)(uint32_t adr, uint32_t adri, uint32_t sect); +typedef uint32_t (*MD_MSC_WP)(uint32_t adr, uint32_t adri, uint32_t data); +typedef uint32_t (*MD_MSC_WSP)(uint32_t adr, uint32_t adri, uint8_t *buf, uint32_t sz, uint32_t epif); + +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @defgroup IAP_Public_Functions MSC Public Functions + * @{ + */ +/** @defgroup IAP_Public_Functions_Group1 FLASH Operation Functions + * @{ + */ +/** + * @brief Erases a specified page. + * @param adr: The beginning address of the page to be erased. + * @param adri:Inverse code of adr + * @param sect:erase section + * @retval The result: + * - 0: SUCCESS + * - 1: MD_ERROR + */ +__STATIC_INLINE__ uint32_t md_msc_code_erase_page(uint32_t adr, uint32_t adri, uint32_t sect) +{ + uint32_t status; + + MD_MSC_PE pe = (MD_MSC_PE)(*(uint32_t *)MD_MSC_CODE_PE_ADDR); + FLASH_REG_UNLOCK(); + __disable_irq_(); + status = (*pe)(adr, adri, sect); + __enable_irq_(); + FLASH_REG_LOCK(); + + return !status; +} + +/** + * @brief Programs a word at a specified address. + * @param adr: Specifies the address to be programmed. + * Bit0-1 must be zero. + * @param adri:Inverse code of adr + * @param data: Specifies the data to be programmed. + * @retval The result: + * - 0: SUCCESS + * - 1: MD_ERROR + */ +__STATIC_INLINE__ uint32_t md_msc_code_program_word(uint32_t adr, uint32_t adri, uint32_t data) +{ + uint32_t status; + + MD_MSC_WP wp = (MD_MSC_WP)(*(uint32_t *)MD_MSC_CODE_WP_ADDR); + + if (adr & 0x3) + return 1; + + FLASH_REG_UNLOCK(); + __disable_irq_(); + status = (*wp)(adr, adri, data); + __enable_irq_(); + FLASH_REG_LOCK(); + + return !status; +} + + +/** + * @brief Programs datas at a specified address. + * @param adr: Specifies the address to be programmed. + * Bit0-1 must be zero. + * @param adri:Inverse code of adr + * @param buf: Specifies the data to be programmed. + * @param sz: Specifies the data length to be programmed. + * Bit0-1 must be zero. + * @param epif: Erase page flag before programming. + * @retval The result: + * - 0: SUCCESS + * - 1: MD_ERROR + */ +__STATIC_INLINE__ uint32_t md_msc_code_program_words(uint32_t adr, uint32_t adri, uint8_t *buf, uint32_t sz, uint32_t epif) +{ + uint32_t status; + + MD_MSC_WSP wsp = (MD_MSC_WSP)(*(uint32_t *)MD_MSC_CODE_WSP_ADDR); + + if ((adr & 0x3) || (sz & 0x3)) + return 1; + + FLASH_REG_UNLOCK(); + __disable_irq_(); + status = (*wsp)(adr, adri, buf, sz, epif); + __enable_irq_(); + FLASH_REG_LOCK(); + + return !status; +} + +/** + * @brief Erases a specified page. + * @param adr: The beginning address of the page to be erased. + * @param adri:Inverse code of adr + * @param sect:erase section + * @retval The result: + * - 0: SUCCESS + * - 1: MD_ERROR + */ +__STATIC_INLINE__ uint32_t md_msc_data_erase_page(uint32_t adr, uint32_t adri, uint32_t sect) +{ + uint32_t status; + + MD_MSC_PE pe = (MD_MSC_PE)(*(uint32_t *)MD_MSC_DATA_PE_ADDR); + FLASH_REG_UNLOCK(); + __disable_irq_(); + status = (*pe)(adr, adri, sect); + __enable_irq_(); + FLASH_REG_LOCK(); + + return !status; +} + +/** + * @brief Programs a word at a specified address. + * @param adr: Specifies the address to be programmed. + * Bit0-1 must be zero. + * @param adri:Inverse code of adr + * @param data: Specifies the data to be programmed. + * @retval The result: + * - 0: SUCCESS + * - 1: MD_ERROR + */ +__STATIC_INLINE__ uint32_t md_msc_data_program_word(uint32_t adr, uint32_t adri, uint32_t data) +{ + uint32_t status; + + MD_MSC_WP wp = (MD_MSC_WP)(*(uint32_t *)MD_MSC_DATA_WP_ADDR); + + if (adr & 0x3) + return 1; + + FLASH_REG_UNLOCK(); + __disable_irq_(); + status = (*wp)(adr, adri, data); + __enable_irq_(); + FLASH_REG_LOCK(); + + return !status; +} + + +/** + * @brief Programs datas at a specified address. + * @param adr: Specifies the address to be programmed. + * Bit0-1 must be zero. + * @param adri:Inverse code of adr + * @param buf: Specifies the data to be programmed. + * @param sz: Specifies the data length to be programmed. + * Bit0-1 must be zero. + * @param epif: Erase page flag before programming. + * @retval The result: + * - 0: SUCCESS + * - 1: MD_ERROR + */ +__STATIC_INLINE__ uint32_t md_msc_data_program_words(uint32_t adr, uint32_t adri, uint8_t *buf, uint32_t sz, uint32_t epif) +{ + uint32_t status; + + MD_MSC_WSP wsp = (MD_MSC_WSP)(*(uint32_t *)MD_MSC_DATA_WSP_ADDR); + + if ((adr & 0x3) || (sz & 0x3)) + return 1; + + FLASH_REG_UNLOCK(); + __disable_irq_(); + status = (*wsp)(adr, adri, buf, sz, epif); + __enable_irq_(); + FLASH_REG_LOCK(); + + return !status; +} +/** + * @} + */ +/** @defgroup IAP_Public_Functions_Group2 MSC Control Functions + * @{ + */ +/** + * @brief Set flash read wait cycle + * @param cycle: Wait cycle, [0-3] sysclock + * @retval None + */ +__STATIC_INLINE__ void md_msc_set_flash_read_wait_cycle(uint8_t cycle) +{ + uint32_t tmp; + + tmp = MSC->MEMWAIT; + MODIFY_REG(tmp, MSC_MEMWAIT_FLASH_W_MSK, (0x30U | cycle) << MSC_MEMWAIT_FLASH_W_POSS); + MSC->MEMWAIT = tmp; +} + +/** + * @brief Get flash read wait cycle + * @retval Wait cycle, [0-3] sysclock + */ +__STATIC_INLINE__ uint32_t md_msc_get_flash_read_wait_cycle(void) +{ + return READ_BITS(MSC->MEMWAIT, MSC_MEMWAIT_FLASH_W_MSK, MSC_MEMWAIT_FLASH_W_POSS); +} + +/** + * @brief Set sram read wait cycle + * @param cycle: Wait cycle, [0-3] sysclock + * @retval None + */ +__STATIC_INLINE__ void md_msc_set_flash_sram_wait_cycle(uint8_t cycle) +{ + MODIFY_REG(MSC->MEMWAIT, MSC_MEMWAIT_SRAM_W_MSK, (cycle | 0x30) << MSC_MEMWAIT_SRAM_W_POSS); +} + +/** + * @brief Get sram read wait cycle + * @retval Wait cycle, [0-3] sysclock + */ +__STATIC_INLINE__ uint32_t md_msc_get_sram_read_wait_cycle(void) +{ + return READ_BITS(MSC->MEMWAIT, MSC_MEMWAIT_SRAM_W_MSK, MSC_MEMWAIT_SRAM_W_POSS); +} +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __MD_MSC_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_pis.c b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_pis.c new file mode 100644 index 0000000000..eb61a3f781 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_pis.c @@ -0,0 +1,164 @@ +/********************************************************************************** + * + * @file md_pis.c + * @brief PIS module driver. + * + * @date 19 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 19 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_pis.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ + +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @addtogroup MD_PIS + * @{ + */ + +/** @addtogroup MD_PIS_Public_Functions + * @{ + */ +/** @addtogroup MD_PIS_Public_Functions_Group1 + * @{ + */ +/** + * @brief Reset the PIS register + * @retval None + */ +void md_pis_reset(void) +{ + uint32_t i; + + for (i = 0; i < 8; ++i) + WRITE_REG(PIS->CH_CON[i], 0x0); + + WRITE_REG(PIS->CH_OER, 0x0); + WRITE_REG(PIS->TAR_CON0, 0x0); + WRITE_REG(PIS->TAR_CON1, 0x0); + WRITE_REG(PIS->UART0_TXMCR, 0x0); + WRITE_REG(PIS->UART1_TXMCR, 0x0); + WRITE_REG(PIS->UART2_TXMCR, 0x0); + WRITE_REG(PIS->UART3_TXMCR, 0x0); + WRITE_REG(PIS->UART4_TXMCR, 0x0); + + return; +} + +/** + * @brief Initializes the PIS mode according to the specified parameters in + * the md_pis_init_t. + * @param init: Pointer to a md_pis_init_t structure that contains + * the configuration information for the specified PIS module. + * @retval Status, see @ref md_status_t. + */ +md_status_t md_pis_init(md_pis_init_t *init) +{ + uint8_t ch, c_idx, shift; + + if (init == NULL) + return MD_ERROR; + + ch = init->c_trig & 0xF; + c_idx = (init->c_trig >> 4) & 0xF; + shift = (init->c_trig >> 8) & 0xFF; + + MODIFY_REG(PIS->CH_CON[ch], PIS_CH0_CON_SRCS_MSK, ((init->p_src) >> 4) << PIS_CH0_CON_SRCS_POSS); + MODIFY_REG(PIS->CH_CON[ch], PIS_CH0_CON_MSIGS_MSK, ((init->p_src) & 0xF) << PIS_CH0_CON_MSIGS_POSS); + + if (init->p_clk == init->c_clk) + { + MODIFY_REG(PIS->CH_CON[ch], PIS_CH0_CON_SYNCSEL_MSK, MD_PIS_SYN_DIRECT << PIS_CH0_CON_SYNCSEL_POSS); + } + else + { + if (init->p_output == MD_PIS_OUT_LEVEL) + { + if (init->c_clk == MD_PIS_CLK_PCLK) + MODIFY_REG(PIS->CH_CON[ch], PIS_CH0_CON_SYNCSEL_MSK, MD_PIS_SYN_LEVEL_ASY_APB << PIS_CH0_CON_SYNCSEL_POSS); + + if (init->c_clk == MD_PIS_CLK_PCLK) + MODIFY_REG(PIS->CH_CON[ch], PIS_CH0_CON_SYNCSEL_MSK, MD_PIS_SYN_LEVEL_ASY_APB << PIS_CH0_CON_SYNCSEL_POSS); + + if (init->c_clk == MD_PIS_CLK_HCLK) + MODIFY_REG(PIS->CH_CON[ch], PIS_CH0_CON_SYNCSEL_MSK, MD_PIS_SYN_LEVEL_ASY_AHB << PIS_CH0_CON_SYNCSEL_POSS); + } + + if (init->p_output == MD_PIS_OUT_PULSE) + { + if (init->c_clk == MD_PIS_CLK_PCLK) + MODIFY_REG(PIS->CH_CON[ch], PIS_CH0_CON_SYNCSEL_MSK, MD_PIS_SYN_PULSE_ASY_APB << PIS_CH0_CON_SYNCSEL_POSS); + + if (init->c_clk == MD_PIS_CLK_PCLK) + MODIFY_REG(PIS->CH_CON[ch], PIS_CH0_CON_SYNCSEL_MSK, MD_PIS_SYN_PULSE_ASY_APB << PIS_CH0_CON_SYNCSEL_POSS); + + if (init->c_clk == MD_PIS_CLK_HCLK) + MODIFY_REG(PIS->CH_CON[ch], PIS_CH0_CON_SYNCSEL_MSK, MD_PIS_SYN_PULSE_ASY_AHB << PIS_CH0_CON_SYNCSEL_POSS); + } + } + + MODIFY_REG(PIS->CH_CON[ch], PIS_CH0_CON_TSCKS_MSK, (init->c_clk) << PIS_CH0_CON_TSCKS_POSS); + MODIFY_REG(PIS->CH_CON[ch], PIS_CH0_CON_EDGS_MSK, init->p_edge << PIS_CH0_CON_EDGS_POSS); + + switch (c_idx) + { + case 0: + PIS->TAR_CON0 |= (1 << shift); + break; + + case 1: + PIS->TAR_CON1 |= (1 << shift); + break; + + default: + break; + } + + return MD_OK; +} +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_pis.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_pis.h new file mode 100644 index 0000000000..5de574999f --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_pis.h @@ -0,0 +1,2502 @@ +/********************************************************************************** + * + * @file md_pis.h + * @brief Header file of PIS module driver. + * + * @date 19 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 19 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __MD_PIS_H__ +#define __MD_PIS_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ +/* Includes ------------------------------------------------------------------ */ +#include "md_utils.h" + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** + * @addtogroup Micro_Driver + * @{ + */ + +/** + * @defgroup MD_PIS PIS + * @brief PIS micro driver + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup MD_PIS_Public_Types PIS Public Types + * @{ + */ + +/** + * @brief Producer entry + */ +typedef enum +{ + MD_PIS_NON = 0x0U, /**< No async */ + MD_PIS_GPIO_PIN0 = 0x10U, /**< Pin0, level,support async */ + MD_PIS_GPIO_PIN1 = 0x11U, /**< Pin1, level,support async */ + MD_PIS_GPIO_PIN2 = 0x12U, /**< Pin2, level,support async */ + MD_PIS_GPIO_PIN3 = 0x13U, /**< Pin3, level,support async */ + MD_PIS_GPIO_PIN4 = 0x14U, /**< Pin4, level,support async */ + MD_PIS_GPIO_PIN5 = 0x15U, /**< Pin5, level,support async */ + MD_PIS_GPIO_PIN6 = 0x16U, /**< Pin6, level,support async */ + MD_PIS_GPIO_PIN7 = 0x17U, /**< Pin7, level,support async */ + MD_PIS_GPIO_PIN8 = 0x18U, /**< Pin8, level,support async */ + MD_PIS_GPIO_PIN9 = 0x19U, /**< Pin9, level,support async */ + MD_PIS_GPIO_PIN10 = 0x1aU, /**< Pin10, level,support async */ + MD_PIS_GPIO_PIN11 = 0x1bU, /**< Pin11, level,support async */ + MD_PIS_GPIO_PIN12 = 0x1cU, /**< Pin12, level,support async */ + MD_PIS_GPIO_PIN13 = 0x1dU, /**< Pin13, level,support async */ + MD_PIS_GPIO_PIN14 = 0x1eU, /**< Pin14, level,support async */ + MD_PIS_GPIO_PIN15 = 0x1fU, /**< Pin15, level,support async */ + MD_PIS_CLK_HSCO = 0x20U, /**< CLK: HSCO, level,support async */ + MD_PIS_CLK_LSCO = 0x21U, /**< CLK: LSCO, level,support async */ + MD_PIS_CLK_BUZ = 0x22U, /**< PCLK: BUZ, level,support async */ + MD_PIS_ADC0_INSERT = 0x60U, /**< ADC0 insert, pclk2 pulse,support async */ + MD_PIS_ADC0_NORMAL = 0x61U, /**< ADC0 normal, pclk2 pulse,support async */ + MD_PIS_ADC0_AWDT = 0x62U, /**< ADC0 AWDT */ + MD_PIS_LVD = 0x70U, /**< LVD, level,support async */ + MD_PIS_UART0_RESERVE0 = 0x80U, /**< Uart0 reserve bit 0 */ + MD_PIS_UART0_RESERVE1 = 0x81U, /**< Uart0 reserve bit 1 */ + MD_PIS_UART0_RESERVE2 = 0x82U, /**< Uart0 reserve bit 2 */ + MD_PIS_UART0_RTSOUT = 0x83U, /**< Uart0 rtsout, level */ + MD_PIS_UART0_TXOUT = 0x84U, /**< Uart0 txout, level */ + MD_PIS_UART0_SYN_SEND = 0x85U, /**< Uart0 syn send, pulse */ + MD_PIS_UART0_SYN_RECV = 0x86U, /**< Uart0 syn recv, pulse */ + MD_PIS_UART1_RESERVE0 = 0x90U, /**< Uart1 reserve bit 0 */ + MD_PIS_UART1_RESERVE1 = 0x91U, /**< Uart1 reserve bit 1 */ + MD_PIS_UART1_RESERVE2 = 0x92U, /**< Uart1 reserve bit 2 */ + MD_PIS_UART1_RTSOUT = 0x93U, /**< Uart1 rtsout, level */ + MD_PIS_UART1_TXOUT = 0x94U, /**< Uart1 txout, level */ + MD_PIS_UART1_SYN_SEND = 0x95U, /**< Uart1 syn send, pulse */ + MD_PIS_UART1_SYN_RECV = 0x96U, /**< Uart1 syn recv, pulse */ + MD_PIS_UART2_RESERVE0 = 0xa0U, /**< Uart2 reserve bit 0 */ + MD_PIS_UART2_RESERVE1 = 0xa1U, /**< Uart2 reserve bit 1 */ + MD_PIS_UART2_RESERVE2 = 0xa2U, /**< Uart2 reserve bit 2 */ + MD_PIS_UART2_RTSOUT = 0xa3U, /**< Uart2 rtsout, level */ + MD_PIS_UART2_TXOUT = 0xa4U, /**< Uart2 txout, level */ + MD_PIS_UART2_SYN_SEND = 0xa5U, /**< Uart2 syn send, pulse */ + MD_PIS_UART2_SYN_RECV = 0xa6U, /**< Uart2 syn recv, pulse */ + MD_PIS_UART3_RESERVE0 = 0xb0U, /**< Uart3 reserve bit 0 */ + MD_PIS_UART3_RESERVE1 = 0xb1U, /**< Uart3 reserve bit 1 */ + MD_PIS_UART3_RESERVE2 = 0xb2U, /**< Uart3 reserve bit 2 */ + MD_PIS_UART3_RTSOUT = 0xb3U, /**< Uart3 rtsout, level */ + MD_PIS_UART3_TXOUT = 0xb4U, /**< Uart3 txout, level */ + MD_PIS_UART3_SYN_SEND = 0xb5U, /**< Uart3 syn send, pulse */ + MD_PIS_UART3_SYN_RECV = 0xb6U, /**< Uart3 syn recv, pulse */ + MD_PIS_UART4_RESERVE0 = 0xc0U, /**< Uart4 reserve bit 0 */ + MD_PIS_UART4_RESERVE1 = 0xc1U, /**< Uart4 reserve bit 1 */ + MD_PIS_UART4_RESERVE2 = 0xc2U, /**< Uart4 reserve bit 2 */ + MD_PIS_UART4_RTSOUT = 0xc3U, /**< Uart4 rtsout, level */ + MD_PIS_UART4_TXOUT = 0xc4U, /**< Uart4 txout, level */ + MD_PIS_UART4_SYN_SEND = 0xc5U, /**< Uart4 syn send, pulse */ + MD_PIS_UART4_SYN_RECV = 0xc6U, /**< Uart4 syn recv, pulse */ + MD_PIS_SPI0_RECV = 0xe0U, /**< Spi0 recv, plck1 pulse */ + MD_PIS_SPI0_SEND = 0xe1U, /**< Spi0 send, plck1 pulse */ + MD_PIS_SPI0_NE = 0xe2U, /**< Spi0 ne, plck1 level */ + MD_PIS_SPI1_RECV = 0xf0U, /**< Spi1 recv, plck1 pulse */ + MD_PIS_SPI1_SEND = 0xf1U, /**< Spi1 send, plck1 pulse */ + MD_PIS_SPI1_NE = 0xf2U, /**< Spi1 ne, plck1 level */ + MD_PIS_I2C0_RECV = 0x100U, /**< I2c0 recv, plck1 level */ + MD_PIS_I2C0_SEND = 0x101U, /**< I2c0 send, plck1 level */ + MD_PIS_I2C1_RECV = 0x110U, /**< I2c1 recv, plck1 level */ + MD_PIS_I2C1_SEND = 0x111U, /**< I2c1 send, plck1 level */ + MD_PIS_TIMER0_UPDATA = 0x120U, /**< Timer0 updata, plck1 pulse */ + MD_PIS_TIMER0_TRIG = 0x121U, /**< Timer0 trig, plck1 pulse */ + MD_PIS_TIMER0_INPUT_1 = 0x122U, /**< Timer0 chan1 input catch, plck1 pulse */ + MD_PIS_TIMER0_OUTPUT_1 = 0x122U, /**< Timer0 chan1 output compare, plck1 pulse */ + MD_PIS_TIMER0_INPUT_2 = 0x124U, /**< Timer0 chan2 input catch, plck1 pulse */ + MD_PIS_TIMER0_OUTPUT_2 = 0x124U, /**< Timer0 chan2 output compare, plck1 pulse */ + MD_PIS_TIMER0_INPUT_3 = 0x126U, /**< Timer0 chan3 input catch, plck1 pulse */ + MD_PIS_TIMER0_OUTPUT_3 = 0x126U, /**< Timer0 chan3 output compare, plck1 pulse */ + MD_PIS_TIMER0_INPUT_4 = 0x128U, /**< Timer0 chan4 input catch, plck1 pulse */ + MD_PIS_TIMER0_OUTPUT_4 = 0x128U, /**< Timer0 chan4 output compare, plck1 pulse */ + MD_PIS_TIMER5_UPDATA = 0x1c0U, /**< Timer5 updata, plck1 pulse */ + MD_PIS_TIMER5_TRIG = 0x1c1U, /**< Timer5 trig, plck1 pulse */ + MD_PIS_TIMER5_INPUT_1 = 0x1c2U, /**< Timer5 chan1 input catch, plck1 pulse */ + MD_PIS_TIMER5_OUTPUT_1 = 0x1c2U, /**< Timer5 chan1 output compare, plck1 pulse */ + MD_PIS_TIMER5_INPUT_2 = 0x1c4U, /**< Timer5 chan2 input catch, plck1 pulse */ + MD_PIS_TIMER5_OUTPUT_2 = 0x1c4U, /**< Timer5 chan2 output compare, plck1 pulse */ + MD_PIS_TIMER5_INPUT_3 = 0x1c6U, /**< Timer5 chan3 input catch, plck1 pulse */ + MD_PIS_TIMER5_OUTPUT_3 = 0x1c6U, /**< Timer5 chan3 output compare, plck1 pulse */ + MD_PIS_TIMER5_INPUT_4 = 0x1c8U, /**< Timer5 chan4 input catch, plck1 pulse */ + MD_PIS_TIMER5_OUTPUT_4 = 0x1c8U, /**< Timer5 chan4 output compare, plck1 pulse */ + MD_PIS_TIMER6_UPDATA = 0x1d0U, /**< Timer6 updata, plck1 pulse */ + MD_PIS_TIMER6_TRIG = 0x1d1U, /**< Timer6 trig, plck1 pulse */ + MD_PIS_TIMER6_INPUT_1 = 0x1d2U, /**< Timer6 chan1 input catch, plck1 pulse */ + MD_PIS_TIMER6_OUTPUT_1 = 0x1d2U, /**< Timer6 chan1 output compare, plck1 pulse */ + MD_PIS_TIMER6_INPUT_2 = 0x1d4U, /**< Timer6 chan2 input catch, plck1 pulse */ + MD_PIS_TIMER6_OUTPUT_2 = 0x1d4U, /**< Timer6 chan2 output compare, plck1 pulse */ + MD_PIS_TIMER6_INPUT_3 = 0x1d6U, /**< Timer6 chan3 input catch, plck1 pulse */ + MD_PIS_TIMER6_OUTPUT_3 = 0x1d6U, /**< Timer6 chan3 output compare, plck1 pulse */ + MD_PIS_TIMER6_INPUT_4 = 0x1d8U, /**< Timer6 chan4 input catch, plck1 pulse */ + MD_PIS_TIMER6_OUTPUT_4 = 0x1d8U, /**< Timer6 chan4 output compare, plck1 pulse */ + MD_PIS_TIMER7_UPDATA = 0x1e0U, /**< Timer7 updata, plck1 pulse */ + MD_PIS_TIMER7_TRIG = 0x1e1U, /**< Timer7 trig, plck1 pulse */ + MD_PIS_TIMER7_INPUT_1 = 0x1e2U, /**< Timer7 chan1 input catch, plck1 pulse */ + MD_PIS_TIMER7_OUTPUT_1 = 0x1e2U, /**< Timer7 chan1 output compare, plck1 pulse */ + MD_PIS_TIMER7_INPUT_2 = 0x1e4U, /**< Timer7 chan2 input catch, plck1 pulse */ + MD_PIS_TIMER7_OUTPUT_2 = 0x1e4U, /**< Timer7 chan2 output compare, plck1 pulse */ + MD_PIS_TIMER7_INPUT_3 = 0x1e6U, /**< Timer7 chan3 input catch, plck1 pulse */ + MD_PIS_TIMER7_OUTPUT_3 = 0x1e6U, /**< Timer7 chan3 output compare, plck1 pulse */ + MD_PIS_TIMER7_INPUT_4 = 0x1e8U, /**< Timer7 chan4 input catch, plck1 pulse */ + MD_PIS_TIMER7_OUTPUT_4 = 0x1e8U, /**< Timer7 chan4 output compare, plck1 pulse */ + MD_PIS_TIMER4_UPDATA = 0x1b0U, /**< Timer4 updata, plck1 pulse */ + MD_PIS_TIMER4_TRIG = 0x1b1U, /**< Timer4 trig, plck1 pulse */ + MD_PIS_DMA_CH0 = 0x190U, /**< DMA CH0 complete, plck1 pulse, support async */ + MD_PIS_DMA_CH1 = 0x191U, /**< DMA CH1 complete, plck1 pulse, support async */ + MD_PIS_DMA_CH2 = 0x192U, /**< DMA CH2 complete, plck1 pulse, support async */ + MD_PIS_DMA_CH3 = 0x193U, /**< DMA CH3 complete, plck1 pulse, support async */ + MD_PIS_DMA_CH4 = 0x194U, /**< DMA CH4 complete, plck1 pulse, support async */ + MD_PIS_DMA_CH5 = 0x195U, /**< DMA CH5 complete, plck1 pulse, support async */ + MD_PIS_DMA_CH6 = 0x196U, /**< DMA CH6 complete, plck1 pulse, support async */ + MD_PIS_DMA_ALL = 0x19fU, /**< DMA all channel complete, plck1 pulse, support async */ +} md_pis_src_t; + +/** + * @brief Consumer entry + */ +typedef enum +{ + MD_PIS_CH4_TIMER0_ITR0 = 0x0034U, /** Tim0 internal input chan0 */ + MD_PIS_CH5_TIMER0_ITR1 = 0x0035U, /** Tim0 internal input chan1 */ + MD_PIS_CH6_TIMER0_ITR2 = 0x0036U, /** Tim0 internal input chan2 */ + MD_PIS_CH7_TIMER0_ITR3 = 0x0037U, /** Tim0 internal input chan3 */ + MD_PIS_CH4_TIMER1_ITR0 = 0x0034U, /** Tim1 internal input chan0 */ + MD_PIS_CH5_TIMER1_ITR1 = 0x0035U, /** Tim1 internal input chan1 */ + MD_PIS_CH6_TIMER1_ITR2 = 0x0036U, /** Tim1 internal input chan2 */ + MD_PIS_CH7_TIMER1_ITR3 = 0x0037U, /** Tim1 internal input chan3 */ + MD_PIS_CH4_TIMER2_ITR0 = 0x0034U, /** Tim2 internal input chan0 */ + MD_PIS_CH5_TIMER2_ITR1 = 0x0035U, /** Tim2 internal input chan1 */ + MD_PIS_CH6_TIMER2_ITR2 = 0x0036U, /** Tim2 internal input chan2 */ + MD_PIS_CH7_TIMER2_ITR3 = 0x0037U, /** Tim2 internal input chan3 */ + MD_PIS_CH4_TIMER3_ITR0 = 0x0034U, /** Tim3 internal input chan0 */ + MD_PIS_CH5_TIMER3_ITR1 = 0x0035U, /** Tim3 internal input chan1 */ + MD_PIS_CH6_TIMER3_ITR2 = 0x0036U, /** Tim3 internal input chan2 */ + MD_PIS_CH7_TIMER3_ITR3 = 0x0037U, /** Tim3 internal input chan3 */ + MD_PIS_CH4_ADC0_NORMAL = 0x0034U, /** ADC0 normal transform */ + MD_PIS_CH5_ADC0_INSERT = 0x0035U, /** ADC0 insert transform */ + MD_PIS_CH7_DMA_REQUEST = 0x0037U, /** DMA request 7 */ + MD_PIS_CH7_UART4_RXD = 0x0417U, /**< Uart4 Rx data */ + MD_PIS_CH6_UART3_RXD = 0x0316U, /**< Uart3 Rx data */ + MD_PIS_CH5_UART2_RXD = 0x0215U, /**< Uart2 Rx data */ + MD_PIS_CH4_UART1_RXD = 0x0114U, /**< Uart1 Rx data */ + MD_PIS_CH3_UART0_RXD = 0x0013U, /**< Uart0 Rx data */ + MD_PIS_CH4_TIMER3_CH4IN = 0x1B04U, /**< Tim3 input chan4 */ + MD_PIS_CH4_TIMER2_CH4IN = 0x1304U, /**< Tim2 input chan4 */ + MD_PIS_CH3_SPI1_CLK = 0x0F13U, /**< Spi1 clk */ + MD_PIS_CH7_TIMER3_CH3IN = 0x1A07U, /**< Tim3 input chan3 */ + MD_PIS_CH7_TIMER2_CH3IN = 0x1207U, /**< Tim2 input chan3 */ + MD_PIS_CH2_SPI1_RX = 0x0E12U, /**< Spi1 rx */ + MD_PIS_CH6_TIMER3_CH2IN = 0x1906U, /**< Tim3 input chan2 */ + MD_PIS_CH6_TIMER2_CH2IN = 0x1106U, /**< Tim2 input chan2 */ + MD_PIS_CH1_SPI0_CLK = 0x0D11U, /**< SPI0 CLK */ + MD_PIS_CH5_TIMER3_CH1IN = 0x1805U, /**< Tim3 input chan1 */ + MD_PIS_CH5_TIMER2_CH1IN = 0x1005U, /**< Tim2 input chan1 */ + MD_PIS_CH0_SPI0_RX = 0x0C10U, /**< SPI0 RX */ + MD_PIS_CH4_TIMER1_CH4IN = 0x0B04U, /**< Tim1 input chan4 */ + MD_PIS_CH4_TIMER0_CH4IN = 0x0304U, /**< Tim0 input chan4 */ + MD_PIS_CH3_TIMER1_CH3IN = 0x0A03U, /**< Tim1 input chan3 */ + MD_PIS_CH3_TIMER0_CH3IN = 0x0203U, /**< Tim0 input chan3 */ + MD_PIS_CH2_TIMER1_CH2IN = 0x0902U, /**< Tim1 input chan2 */ + MD_PIS_CH2_TIMER0_CH2IN = 0x0102U, /**< Tim0 input chan2 */ + MD_PIS_CH1_TIMER1_CH1IN = 0x0801U, /**< Tim1 input chan1 */ + MD_PIS_CH1_TIMER0_CH1IN = 0x0001U, /**< Tim0 input chan1 */ + MD_PIS_CH0_TIMER0_BRKIN = 0x0400U, /**< Tim0 break in */ + MD_PIS_TRIG_RESERVE = 0xFFFFU, /**< Other Consumer */ +} md_pis_trig_t; + +/** + * @brief input source + */ +typedef enum +{ + MD_SRC_NONE = 0x00U, /**< None input source */ + MD_SRC_GPIO = 0x01U, /**< gpio source */ + MD_SRC_CLK = 0x02U, /**< reserve source */ + MD_SRC_ADC0 = 0x06U, /**< adc0 source */ + MD_SRC_LVD = 0x07U, /**< lvd source */ + MD_SRC_UART0 = 0x08U, /**< uart0 source */ + MD_SRC_UART1 = 0x09U, /**< uart1 source */ + MD_SRC_UART2 = 0x0AU, /**< uart2 source */ + MD_SRC_UART3 = 0x0BU, /**< uart3 source */ + MD_SRC_UART4 = 0x0CU, /**< uart4 source */ + MD_SRC_SPI0 = 0x0EU, /**< spi0 source */ + MD_SRC_SPI1 = 0x0FU, /**< spi1 source */ + MD_SRC_I2C0 = 0x10U, /**< i2c0 source */ + MD_SRC_I2C1 = 0x11U, /**< i2c1 source */ + MD_SRC_TIM0 = 0x12U, /**< tim0 source */ + MD_SRC_DMA = 0x19U, /**< dma source */ + MD_SRC_TIM4 = 0x1BU, /**< tim4 source */ + MD_SRC_TIM5 = 0x1CU, /**< tim5 source */ + MD_SRC_TIM6 = 0x1DU, /**< tim6 source */ + MD_SRC_TIM7 = 0x1EU, /**< tim7 source */ +} md_pis_input_src_t; + +/** + * @brief Clock select + */ +typedef enum +{ + MD_PIS_CLK_PCLK = 0U, /**< APB peripherals clock */ + MD_PIS_CLK_HCLK = 2U, /**< AHB peripherals clock */ + MD_PIS_CLK_RESERVE = 3U, /**< reserve clock */ +} md_pis_clock_t; + +/** + * @brief Level select + */ +typedef enum +{ + MD_PIS_EDGE_NONE = 0U, /**< None edge */ + MD_PIS_EDGE_UP = 1U, /**< Up edge */ + MD_PIS_EDGE_DOWN = 2U, /**< Down edge */ + MD_PIS_EDGE_UP_DOWN = 3U, /**< Up and down edge */ +} md_pis_edge_t; + +/** + * @brief Output style + */ +typedef enum +{ + MD_PIS_OUT_LEVEL = 0U, /**< Level */ + MD_PIS_OUT_PULSE = 1U, /**< Pulse */ +} md_pis_output_t; +/** + * @brief Sync select + */ +typedef enum +{ + MD_PIS_SYN_DIRECT = 0U, /**< Direct */ + MD_PIS_SYN_LEVEL_ASY_APB = 1U, /**< Producer level signal and Consumer in APB */ + MD_PIS_SYN_LEVEL_ASY_AHB = 3U, /**< Producer level signal and Consumer in AHB */ + MD_PIS_SYN_PULSE_ASY_APB = 4U, /**< Producer Pulse signal and Consumer in APB */ + MD_PIS_SYN_PULSE_ASY_AHB = 6U, /**< Producer Pulse signal and Consumer in AHB */ +} md_pis_syncsel_t; + +/** + * @brief Pis channel + */ +typedef enum +{ + MD_PIS_CH_0 = 0U, /**< Channel 0 */ + MD_PIS_CH_1 = 1U, /**< Channel 1 */ + MD_PIS_CH_2 = 2U, /**< Channel 2 */ + MD_PIS_CH_3 = 3U, /**< Channel 3 */ + MD_PIS_CH_4 = 4U, /**< Channel 4 */ + MD_PIS_CH_5 = 5U, /**< Channel 5 */ + MD_PIS_CH_6 = 6U, /**< Channel 6 */ + MD_PIS_CH_7 = 7U, /**< Channel 7 */ +} md_pis_ch_t; + +/** + * @brief PIS init structure definition + */ +typedef struct +{ + md_pis_src_t p_src; /**< Producer entry */ + md_pis_output_t p_output; /**< Producer signal mode */ + md_pis_clock_t p_clk; /**< Producer module clock */ + md_pis_edge_t p_edge; /**< Producer module pin output edge */ + md_pis_trig_t c_trig; /**< Consumer entry */ + md_pis_clock_t c_clk; /**< Consumer clock */ +} md_pis_init_t; + +/** + * @brief PIS state structures definition + */ +typedef enum +{ + MD_PIS_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + MD_PIS_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + MD_PIS_STATE_BUSY = 0x02U, /**< An internal process is ongoing */ + MD_PIS_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + MD_PIS_STATE_ERROR = 0x04U, /**< Error */ +} md_pis_state_t; + +/** + * @brief PIS modulate target + */ +typedef enum +{ + MD_PIS_UART0_TX = 0U, /**< Modulate uart0 tx */ + MD_PIS_UART1_TX = 1U, /**< Modulate uart1 tx */ + MD_PIS_UART2_TX = 2U, /**< Modulate uart2 tx */ + MD_PIS_UART3_TX = 3U, /**< Modulate uart3 tx */ + MD_PIS_UART4_TX = 4U, /**< Modulate uart4 tx */ +} md_pis_modu_targ_t; + +/** + * @brief PIS modulate level + */ +typedef enum +{ + MD_PIS_LOW_LEVEL = 0U, /**< Modulate low level */ + MD_PIS_HIGH_LEVEL = 1U, /**< Modulate high level */ +} md_pis_modu_level_t; + +/** + * @brief PIS modulate source + */ +typedef enum +{ + MD_PIS_SRC_NONE = 0U, /**< Stop modulate */ + MD_PIS_SRC_TIMER0 = 1U, /**< Modulate source is TIMER0 */ + MD_PIS_SRC_TIMER5 = 4U, /**< Modulate source is TIMER5 */ + MD_PIS_SRC_TIMER6 = 5U, /**< Modulate source is TIMER6 */ + MD_PIS_SRC_TIMER7 = 6U, /**< Modulate source is TIMER7 */ + MD_PIS_SRC_BUZ = 8U, /**< Modulate source is buz */ +} md_pis_modu_src_t; + +/** + * @brief PIS modulate channel + */ +typedef enum +{ + MD_PIS_TIMER_CH1 = 0U, /**< Src is TIMERx and choose channel 1 */ + MD_PIS_TIMER_CH2 = 1U, /**< Src is TIMERx and choose channel 2 */ + MD_PIS_TIMER_CH3 = 2U, /**< Src is TIMERx and choose channel 3 */ + MD_PIS_TIMER_CH4 = 3U, /**< Src is TIMERx and choose channel 4 */ +} md_pis_modu_channel_t; +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @defgroup MD_PIS_Public_Functions PIS Public Functions + * @{ + */ +/** @defgroup MD_PIS_Public_Functions_Group2 CH_CON + * @{ + */ +/** + * @brief output pis level. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_level_output(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + SET_BIT(PISx->CH_CON[channel], PIS_CH0_CON_LEVEL_MSK); +} + +/** + * @brief clear pis level. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_level_clear(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + CLEAR_BIT(PISx->CH_CON[channel], PIS_CH0_CON_LEVEL_MSK); +} + +/** + * @brief output pis pulse. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_pulse_output(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + SET_BIT(PISx->CH_CON[channel], PIS_CH0_CON_PULSE_MSK); +} + +/** + * @brief Set pis signal synchronization type. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param signal PIS signal. + * @retval None + */ +__STATIC_INLINE void md_pis_set_signal_syn_type(PIS_TypeDef *PISx, md_pis_ch_t channel, md_pis_syncsel_t signal) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_SYNCSEL_MSK, signal << PIS_CH0_CON_SYNCSEL_POSS); +} + +/** + * @brief Get pis signal synchronization type. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis channel signal synchronization type @ref md_pis_syncsel_t + */ +__STATIC_INLINE uint32_t md_pis_get_signal_syn_type(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_SYNCSEL_MSK, PIS_CH0_CON_SYNCSEL_POSS); +} + +/** + * @brief Set pis edge sampling clock. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param clock PIS sample clock. + * @retval None + */ +__STATIC_INLINE void md_pis_set_edge_sample_clock(PIS_TypeDef *PISx, md_pis_ch_t channel, md_pis_clock_t clock) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_TSCKS_MSK, clock << PIS_CH0_CON_TSCKS_POSS); +} + +/** + * @brief Get pis edge sampling clock. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis edge sampling clock @ref md_pis_clock_t + */ +__STATIC_INLINE uint32_t md_pis_get_edge_sample_clock(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_TSCKS_MSK, PIS_CH0_CON_TSCKS_POSS); +} + +/** + * @brief Set pis sample edge. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param edge PIS sample edge. + * @retval None + */ +__STATIC_INLINE void md_pis_set_sample_edge(PIS_TypeDef *PISx, md_pis_ch_t channel, md_pis_edge_t edge) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_EDGS_MSK, edge << PIS_CH0_CON_EDGS_POSS); +} + +/** + * @brief Get pis sample edge. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis edge sampling clock @ref md_pis_edge_t + */ +__STATIC_INLINE uint32_t md_pis_get_sample_edge(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_EDGS_MSK, PIS_CH0_CON_EDGS_POSS); +} + +/** + * @brief Set pis input source. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param src PIS input source. + * @retval None + */ +__STATIC_INLINE void md_pis_set_input_src(PIS_TypeDef *PISx, md_pis_ch_t channel, md_pis_input_src_t src) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_SRCS_MSK, src << PIS_CH0_CON_SRCS_POSS); +} + +/** + * @brief Get pis input source. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis input source @ref md_pis_input_src_t + */ +__STATIC_INLINE uint32_t md_pis_get_input_src(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_SRCS_MSK, PIS_CH0_CON_SRCS_POSS); +} + +/** + * @brief Set pis input source gpiob. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param pin PIS input source gpiob. + * @retval None + */ +__STATIC_INLINE void md_pis_set_src_gpiob(PIS_TypeDef *PISx, md_pis_ch_t channel, uint8_t pin) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, pin << PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Get pis input source gpiob. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis input source gpiob. + */ +__STATIC_INLINE uint32_t md_pis_get_src_gpiob(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Set pis input source clk. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param clk PIS input source clk. + * @retval None + */ +__STATIC_INLINE void md_pis_set_src_clk(PIS_TypeDef *PISx, md_pis_ch_t channel, uint8_t clk) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, clk << PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Get pis input source clk. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis input source clk. + */ +__STATIC_INLINE uint32_t md_pis_get_src_clk(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Set pis input source adc0. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param adc0 PIS input source adc0. + * @retval None + */ +__STATIC_INLINE void md_pis_set_src_adc0(PIS_TypeDef *PISx, md_pis_ch_t channel, uint32_t adc0) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, adc0 << PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Get pis input source adc0. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis input source adc0. + */ +__STATIC_INLINE uint32_t md_pis_get_src_adc0(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Set pis input source lvd. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param lvd PIS input source lvd. + * @retval None + */ +__STATIC_INLINE void md_pis_set_src_lvd(PIS_TypeDef *PISx, md_pis_ch_t channel, uint32_t lvd) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, lvd << PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Get pis input source lvd. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis input source lvd. + */ +__STATIC_INLINE uint32_t md_pis_get_src_lvd(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Set pis input source uart0. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param uart0 PIS input source uart0. + * @retval None + */ +__STATIC_INLINE void md_pis_set_src_uart0(PIS_TypeDef *PISx, md_pis_ch_t channel, uint32_t uart0) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, uart0 << PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Get pis input source uart0. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis input source uart0. + */ +__STATIC_INLINE uint32_t md_pis_get_src_uart0(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Set pis input source uart1. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param uart1 PIS input source uart1. + * @retval None + */ +__STATIC_INLINE void md_pis_set_src_uart1(PIS_TypeDef *PISx, md_pis_ch_t channel, uint32_t uart1) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, uart1 << PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Get pis input source uart1. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis input source uart1. + */ +__STATIC_INLINE uint32_t md_pis_get_src_uart1(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Set pis input source uart2. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param uart2 PIS input source uart2. + * @retval None + */ +__STATIC_INLINE void md_pis_set_src_uart2(PIS_TypeDef *PISx, md_pis_ch_t channel, uint32_t uart2) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, uart2 << PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Get pis input source uart2. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis input source uart2. + */ +__STATIC_INLINE uint32_t md_pis_get_src_uart2(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Set pis input source uart3. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param uart3 PIS input source uart3. + * @retval None + */ +__STATIC_INLINE void md_pis_set_src_uart3(PIS_TypeDef *PISx, md_pis_ch_t channel, uint32_t uart3) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, uart3 << PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Get pis input source uart3. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis input source uart3. + */ +__STATIC_INLINE uint32_t md_pis_get_src_uart3(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Set pis input source uart4. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param uart4 PIS input source uart4. + * @retval None + */ +__STATIC_INLINE void md_pis_set_src_uart4(PIS_TypeDef *PISx, md_pis_ch_t channel, uint32_t uart4) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, uart4 << PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Get pis input source uart4. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis input source uart4. + */ +__STATIC_INLINE uint32_t md_pis_get_src_uart4(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Set pis input source spi0. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param spi0 PIS input source spi0. + * @retval None + */ +__STATIC_INLINE void md_pis_set_src_spi0(PIS_TypeDef *PISx, md_pis_ch_t channel, uint32_t spi0) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, spi0 << PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Get pis input source spi0. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis input source spi0. + */ +__STATIC_INLINE uint32_t md_pis_get_src_spi0(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Set pis input source spi1. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param spi1 PIS input source spi1. + * @retval None + */ +__STATIC_INLINE void md_pis_set_src_spi1(PIS_TypeDef *PISx, md_pis_ch_t channel, uint32_t spi1) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, spi1 << PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Get pis input source spi1. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis input source spi1. + */ +__STATIC_INLINE uint32_t md_pis_get_src_spi1(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Set pis input source i2c0. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param i2c0 PIS input source i2c0. + * @retval None + */ +__STATIC_INLINE void md_pis_set_src_i2c0(PIS_TypeDef *PISx, md_pis_ch_t channel, uint32_t i2c0) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, i2c0 << PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Get pis input source i2c0. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis input source i2c0. + */ +__STATIC_INLINE uint32_t md_pis_get_src_i2c0(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Set pis input source i2c1. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param i2c1 PIS input source i2c1. + * @retval None + */ +__STATIC_INLINE void md_pis_set_src_i2c1(PIS_TypeDef *PISx, md_pis_ch_t channel, uint32_t i2c1) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, i2c1 << PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Get pis input source i2c1. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis input source i2c1 + */ +__STATIC_INLINE uint32_t md_pis_get_src_i2c1(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Set pis input source tim0. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param tim0 PIS input source tim0. + * @retval None + */ +__STATIC_INLINE void md_pis_set_src_tim0(PIS_TypeDef *PISx, md_pis_ch_t channel, uint32_t tim0) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, tim0 << PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Get pis input source tim0. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis input source tim0 + */ +__STATIC_INLINE uint32_t md_pis_get_src_tim0(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Set pis input source tim4. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param tim0 PIS input source tim4. + * @retval None + */ +__STATIC_INLINE void md_pis_set_src_tim4(PIS_TypeDef *PISx, md_pis_ch_t channel, uint32_t tim4) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, tim4 << PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Get pis input source tim4. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis input source tim4 + */ +__STATIC_INLINE uint32_t md_pis_get_src_tim4(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Set pis input source tim5. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param tim0 PIS input source tim5. + * @retval None + */ +__STATIC_INLINE void md_pis_set_src_tim5(PIS_TypeDef *PISx, md_pis_ch_t channel, uint32_t tim5) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, tim5 << PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Get pis input source tim5. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis input source tim5 + */ +__STATIC_INLINE uint32_t md_pis_get_src_tim5(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Set pis input source tim6. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param tim0 PIS input source tim6. + * @retval None + */ +__STATIC_INLINE void md_pis_set_src_tim6(PIS_TypeDef *PISx, md_pis_ch_t channel, uint32_t tim6) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, tim6 << PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Get pis input source tim6. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis input source tim6 + */ +__STATIC_INLINE uint32_t md_pis_get_src_tim6(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Set pis input source tim7. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param tim0 PIS input source tim7. + * @retval None + */ +__STATIC_INLINE void md_pis_set_src_tim7(PIS_TypeDef *PISx, md_pis_ch_t channel, uint32_t tim7) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, tim7 << PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Get pis input source tim7. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis input source tim7 + */ +__STATIC_INLINE uint32_t md_pis_get_src_tim7(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Set pis input source dma. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @param dma PIS input source dma. + * @retval None + */ +__STATIC_INLINE void md_pis_set_src_dma(PIS_TypeDef *PISx, md_pis_ch_t channel, uint32_t dma) +{ + MODIFY_REG(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, dma << PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @brief Get pis input source dma. + * @param PISx PIS Instance. + * @param channel PIS channel. + * @retval pis input source dma. + */ +__STATIC_INLINE uint32_t md_pis_get_src_dma(PIS_TypeDef *PISx, md_pis_ch_t channel) +{ + return READ_BITS(PISx->CH_CON[channel], PIS_CH0_CON_MSIGS_MSK, PIS_CH0_CON_MSIGS_POSS); +} + +/** + * @} + */ +/** @defgroup MD_PIS_Public_Functions_Group3 CH_OER + * @{ + */ +/** + * @brief Disable pis channel 7 output to port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_ch7_output(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->CH_OER, PIS_CH_OER_CH7OE_MSK); +} + +/** + * @brief Enable pis channel 7 output to port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_disable_ch7_output(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->CH_OER, PIS_CH_OER_CH7OE_MSK); +} + +/** + * @brief Indicate if pis channel 7 output to port is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_ch7_output(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->CH_OER, PIS_CH_OER_CH7OE_MSK) == (PIS_CH_OER_CH7OE_MSK)); +} + +/** + * @brief Disable pis channel 6 output to port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_ch6_output(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->CH_OER, PIS_CH_OER_CH6OE_MSK); +} + +/** + * @brief Enable pis channel 6 output to port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_disable_ch6_output(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->CH_OER, PIS_CH_OER_CH6OE_MSK); +} + +/** + * @brief Indicate if pis channel 6 output to port is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_ch6_output(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->CH_OER, PIS_CH_OER_CH6OE_MSK) == (PIS_CH_OER_CH6OE_MSK)); +} + +/** + * @brief Disable pis channel 5 output to port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_ch5_output(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->CH_OER, PIS_CH_OER_CH5OE_MSK); +} + +/** + * @brief Enable pis channel 5 output to port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_disable_ch5_output(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->CH_OER, PIS_CH_OER_CH5OE_MSK); +} + +/** + * @brief Indicate if pis channel 5 output to port is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_ch5_output(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->CH_OER, PIS_CH_OER_CH5OE_MSK) == (PIS_CH_OER_CH5OE_MSK)); +} + +/** + * @brief Disable pis channel 4 output to port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_ch4_output(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->CH_OER, PIS_CH_OER_CH4OE_MSK); +} + +/** + * @brief Enable pis channel 4 output to port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_disable_ch4_output(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->CH_OER, PIS_CH_OER_CH4OE_MSK); +} + +/** + * @brief Indicate if pis channel 4 output to port is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_ch4_output(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->CH_OER, PIS_CH_OER_CH4OE_MSK) == (PIS_CH_OER_CH4OE_MSK)); +} + +/** + * @brief Disable pis channel 3 output to port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_ch3_output(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->CH_OER, PIS_CH_OER_CH3OE_MSK); +} + +/** + * @brief Enable pis channel 3 output to port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_disable_ch3_output(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->CH_OER, PIS_CH_OER_CH3OE_MSK); +} + +/** + * @brief Indicate if pis channel 3 output to port is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_ch3_output(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->CH_OER, PIS_CH_OER_CH3OE_MSK) == (PIS_CH_OER_CH3OE_MSK)); +} + +/** + * @brief Disable pis channel 2 output to port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_ch2_output(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->CH_OER, PIS_CH_OER_CH2OE_MSK); +} + +/** + * @brief Enable pis channel 2 output to port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_disable_ch2_output(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->CH_OER, PIS_CH_OER_CH2OE_MSK); +} + +/** + * @brief Indicate if pis channel 2 output to port is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_ch2_output(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->CH_OER, PIS_CH_OER_CH2OE_MSK) == (PIS_CH_OER_CH2OE_MSK)); +} + +/** + * @brief Disable pis channel 1 output to port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_ch1_output(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->CH_OER, PIS_CH_OER_CH1OE_MSK); +} + +/** + * @brief Enable pis channel 1 output to port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_disable_ch1_output(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->CH_OER, PIS_CH_OER_CH1OE_MSK); +} + +/** + * @brief Indicate if pis channel 1 output to port is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_ch1_output(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->CH_OER, PIS_CH_OER_CH1OE_MSK) == (PIS_CH_OER_CH1OE_MSK)); +} + +/** + * @brief Disable pis channel 0 output to port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_ch0_output(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->CH_OER, PIS_CH_OER_CH0OE_MSK); +} + +/** + * @brief Enable pis channel 0 output to port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_disable_ch0_output(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->CH_OER, PIS_CH_OER_CH0OE_MSK); +} + +/** + * @brief Indicate if pis channel 0 output to port is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_ch0_output(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->CH_OER, PIS_CH_OER_CH0OE_MSK) == (PIS_CH_OER_CH0OE_MSK)); +} +/** + * @} + */ +/** @defgroup MD_PIS_Public_Functions_Group4 TAR_CON0 + * @{ + */ +/** + * @brief Set pis tim3 input etr chose ch6. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim3_etrin_ch6(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM3_ETRIN_SEL_MSK); +} + +/** + * @brief Set pis tim3 input etr chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim3_etrin_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM3_ETRIN_SEL_MSK); +} + +/** + * @brief Indicate if pis tim3 input etr chose ch6 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_tim3_etr_ch6(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM3_ETRIN_SEL_MSK) == (PIS_TAR_CON0_TIM3_ETRIN_SEL_MSK)); +} + +/** + * @brief Set pis tim3 input capture ch4 chose ch0. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim3_ch4in_ch0(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM3_CH4IN_SEL_MSK); +} + +/** + * @brief Set pis tim3 input capture ch4 chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim3_ch4in_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM3_CH4IN_SEL_MSK); +} + +/** + * @brief Indicate if pis tim3 input capture ch4 chose ch0 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_tim3_ch4in_ch0(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM3_CH4IN_SEL_MSK) == (PIS_TAR_CON0_TIM3_CH4IN_SEL_MSK)); +} + +/** + * @brief Set pis tim3 input capture ch3 chose ch7. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim3_ch3in_ch7(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM3_CH3IN_SEL_MSK); +} + +/** + * @brief Set pis tim3 input capture ch3 chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim3_ch3in_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM3_CH3IN_SEL_MSK); +} + +/** + * @brief Indicate if pis tim3 input capture ch3 chose ch7 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_tim3_ch3in_ch7(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM3_CH3IN_SEL_MSK) == (PIS_TAR_CON0_TIM3_CH3IN_SEL_MSK)); +} + +/** + * @brief Set pis tim3 input capture ch2 chose ch6. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim3_ch2in_ch6(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM3_CH2IN_SEL_MSK); +} + +/** + * @brief Set pis tim3 input capture ch2 chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim3_ch2in_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM3_CH2IN_SEL_MSK); +} + +/** + * @brief Indicate if pis tim3 input capture ch2 chose ch6 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_tim3_ch2in_ch6(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM3_CH2IN_SEL_MSK) == (PIS_TAR_CON0_TIM3_CH2IN_SEL_MSK)); +} + +/** + * @brief Set pis tim3 input capture ch1 chose ch5. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim3_ch1in_ch5(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM3_CH1IN_SEL_MSK); +} + +/** + * @brief Set pis tim3 input capture ch1 chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim3_ch1in_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM3_CH1IN_SEL_MSK); +} + +/** + * @brief Indicate if pis tim3 input capture ch1 chose ch5 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_tim3_ch1in_ch5(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM3_CH1IN_SEL_MSK) == (PIS_TAR_CON0_TIM3_CH1IN_SEL_MSK)); +} + +/** + * @brief Set pis tim2 input etr chose ch6. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim2_etrin_ch6(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM2_ETRIN_SEL_MSK); +} + +/** + * @brief Set pis tim2 input etr chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim2_etrin_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM2_ETRIN_SEL_MSK); +} + +/** + * @brief Indicate if pis tim2 input etr chose ch6 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_tim2_etr_ch6(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM2_ETRIN_SEL_MSK) == (PIS_TAR_CON0_TIM2_ETRIN_SEL_MSK)); +} + +/** + * @brief Set pis tim2 input capture ch4 chose ch4. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim2_ch4in_ch4(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM2_CH4IN_SEL_MSK); +} + +/** + * @brief Set pis tim2 input capture ch4 chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim2_ch4in_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM2_CH4IN_SEL_MSK); +} + +/** + * @brief Indicate if pis tim2 input capture ch4 chose ch4 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_tim2_ch4in_ch4(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM2_CH4IN_SEL_MSK) == (PIS_TAR_CON0_TIM2_CH4IN_SEL_MSK)); +} + +/** + * @brief Set pis tim2 input capture ch3 chose ch3. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim2_ch3in_ch3(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM2_CH3IN_SEL_MSK); +} + +/** + * @brief Set pis tim2 input capture ch3 chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim2_ch3in_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM2_CH3IN_SEL_MSK); +} + +/** + * @brief Indicate if pis tim2 input capture ch3 chose ch7 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_tim2_ch3in_ch3(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM2_CH3IN_SEL_MSK) == (PIS_TAR_CON0_TIM2_CH3IN_SEL_MSK)); +} + +/** + * @brief Set pis tim2 input capture ch2 chose ch2. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim2_ch2in_ch2(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM2_CH2IN_SEL_MSK); +} + +/** + * @brief Set pis tim2 input capture ch2 chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim2_ch2in_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM2_CH2IN_SEL_MSK); +} + +/** + * @brief Indicate if pis tim2 input capture ch2 chose ch2 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_tim2_ch2in_ch2(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM2_CH2IN_SEL_MSK) == (PIS_TAR_CON0_TIM2_CH2IN_SEL_MSK)); +} + +/** + * @brief Set pis tim2 input capture ch1 chose ch1. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim2_ch1in_ch1(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM2_CH1IN_SEL_MSK); +} + +/** + * @brief Set pis tim2 input capture ch1 chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim2_ch1in_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM2_CH1IN_SEL_MSK); +} + +/** + * @brief Indicate if pis tim2 input capture ch1 chose ch1 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_tim2_ch1in_ch1(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM2_CH1IN_SEL_MSK) == (PIS_TAR_CON0_TIM2_CH1IN_SEL_MSK)); +} + +/** + * @brief Set pis tim1 input etr chose ch6. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim1_etrin_ch6(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM1_ETRIN_SEL_MSK); +} + +/** + * @brief Set pis tim1 input etr chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim1_etrin_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM1_ETRIN_SEL_MSK); +} + +/** + * @brief Indicate if pis tim1 input etr chose ch6 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_tim1_etr_ch6(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM1_ETRIN_SEL_MSK) == (PIS_TAR_CON0_TIM1_ETRIN_SEL_MSK)); +} + +/** + * @brief Set pis tim1 input capture ch4 chose ch4. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim1_ch4in_ch4(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM1_CH4IN_SEL_MSK); +} + +/** + * @brief Set pis tim1 input capture ch4 chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim1_ch4in_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM1_CH4IN_SEL_MSK); +} + +/** + * @brief Indicate if pis tim1 input capture ch4 chose ch4 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_tim1_ch4in_ch4(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM1_CH4IN_SEL_MSK) == (PIS_TAR_CON0_TIM1_CH4IN_SEL_MSK)); +} + +/** + * @brief Set pis tim1 input capture ch3 chose ch3. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim1_ch3in_ch3(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM1_CH3IN_SEL_MSK); +} + +/** + * @brief Set pis tim1 input capture ch3 chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim1_ch3in_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM1_CH3IN_SEL_MSK); +} + +/** + * @brief Indicate if pis tim1 input capture ch3 chose ch3 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_tim1_ch3in_ch3(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM1_CH3IN_SEL_MSK) == (PIS_TAR_CON0_TIM1_CH3IN_SEL_MSK)); +} + +/** + * @brief Set pis tim1 input capture ch2 chose ch2. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim1_ch2in_ch2(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM1_CH2IN_SEL_MSK); +} + +/** + * @brief Set pis tim1 input capture ch2 chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim1_ch2in_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM1_CH2IN_SEL_MSK); +} + +/** + * @brief Indicate if pis tim1 input capture ch2 chose ch2 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_tim1_ch2in_ch2(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM1_CH2IN_SEL_MSK) == (PIS_TAR_CON0_TIM1_CH2IN_SEL_MSK)); +} + +/** + * @brief Set pis tim1 input capture ch1 chose ch1. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim1_ch1in_ch1(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM1_CH1IN_SEL_MSK); +} + +/** + * @brief Set pis tim1 input capture ch1 chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim1_ch1in_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM1_CH1IN_SEL_MSK); +} + +/** + * @brief Indicate if pis tim1 input capture ch1 chose ch1 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_tim1_ch1in_ch1(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM1_CH1IN_SEL_MSK) == (PIS_TAR_CON0_TIM1_CH1IN_SEL_MSK)); +} + +/** + * @brief Set pis tim0 input etr chose ch5. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim0_etrin_ch5(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM0_ETRIN_SEL_MSK); +} + +/** + * @brief Set pis tim0 input etr chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim0_etrin_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM0_ETRIN_SEL_MSK); +} + +/** + * @brief Indicate if pis tim1 input etr chose ch5 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_tim0_etr_ch5(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM0_ETRIN_SEL_MSK) == (PIS_TAR_CON0_TIM0_ETRIN_SEL_MSK)); +} + +/** + * @brief Set pis tim0 input capture ch4 chose ch4. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim0_ch4in_ch4(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM0_CH4IN_SEL_MSK); +} + +/** + * @brief Set pis tim0 input capture ch4 chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim0_ch4in_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM0_CH4IN_SEL_MSK); +} + +/** + * @brief Indicate if pis tim0 input capture ch4 chose ch4 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_tim0_ch4in_ch4(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM0_CH4IN_SEL_MSK) == (PIS_TAR_CON0_TIM0_CH4IN_SEL_MSK)); +} + +/** + * @brief Set pis tim0 input capture ch3 chose ch3. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim0_ch3in_ch3(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM0_CH3IN_SEL_MSK); +} + +/** + * @brief Set pis tim0 input capture ch3 chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim0_ch3in_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM0_CH3IN_SEL_MSK); +} + +/** + * @brief Indicate if pis tim0 input capture ch3 chose ch3 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_tim0_ch3in_ch3(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM0_CH3IN_SEL_MSK) == (PIS_TAR_CON0_TIM0_CH3IN_SEL_MSK)); +} + +/** + * @brief Set pis tim0 input capture ch2 chose ch2. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim0_ch2in_ch2(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM0_CH2IN_SEL_MSK); +} + +/** + * @brief Set pis tim0 input capture ch2 chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim0_ch2in_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM0_CH2IN_SEL_MSK); +} + +/** + * @brief Indicate if pis tim0 input capture ch2 chose ch2 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_tim0_ch2in_ch2(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM0_CH2IN_SEL_MSK) == (PIS_TAR_CON0_TIM0_CH2IN_SEL_MSK)); +} + +/** + * @brief Set pis tim0 input capture ch1 chose ch1. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim0_ch1in_ch1(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM0_CH1IN_SEL_MSK); +} + +/** + * @brief Set pis tim0 input capture ch1 chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_tim0_ch1in_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM0_CH1IN_SEL_MSK); +} + +/** + * @brief Indicate if pis tim0 input capture ch1 chose ch1 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_tim0_ch1in_ch1(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON0, PIS_TAR_CON0_TIM0_CH1IN_SEL_MSK) == (PIS_TAR_CON0_TIM0_CH1IN_SEL_MSK)); +} +/** + * @} + */ +/** @defgroup MD_PIS_Public_Functions_Group5 TAR_CON1 + * @{ + */ +/** + * @brief Set pis spi1 clk input chose ch3. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_spi1_clk_ch3(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON1, PIS_TAR_CON1_SPI1_CLK_SEL_MSK); +} + +/** + * @brief Set pis spi1 clk input chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_spi1_clk_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON1, PIS_TAR_CON1_SPI1_CLK_SEL_MSK); +} + +/** + * @brief Indicate if pis spi1 clk input chose ch3 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_spi1_clk_ch3(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON1, PIS_TAR_CON1_SPI1_CLK_SEL_MSK) == (PIS_TAR_CON1_SPI1_CLK_SEL_MSK)); +} + +/** + * @brief Set pis spi1 rx input chose ch2. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_spi1_rx_ch2(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON1, PIS_TAR_CON1_SPI1_RX_SEL_MSK); +} + +/** + * @brief Set pis spi1 rx input chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_spi1_rx_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON1, PIS_TAR_CON1_SPI1_RX_SEL_MSK); +} + +/** + * @brief Indicate if pis spi1 rx input chose ch2 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_spi1_rx_ch2(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON1, PIS_TAR_CON1_SPI1_RX_SEL_MSK) == (PIS_TAR_CON1_SPI1_RX_SEL_MSK)); +} + +/** + * @brief Set pis spi0 clk input chose ch1. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_spi0_clk_ch1(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON1, PIS_TAR_CON1_SPI0_CLK_SEL_MSK); +} + +/** + * @brief Set pis spi0 clk input chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_spi0_clk_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON1, PIS_TAR_CON1_SPI0_CLK_SEL_MSK); +} + +/** + * @brief Indicate if pis spi0 clk input chose ch1 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_spi0_clk_ch1(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON1, PIS_TAR_CON1_SPI0_CLK_SEL_MSK) == (PIS_TAR_CON1_SPI0_CLK_SEL_MSK)); +} + +/** + * @brief Set pis spi0 rx input chose ch0. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_spi0_rx_ch0(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON1, PIS_TAR_CON1_SPI0_RX_SEL_MSK); +} + +/** + * @brief Set pis spi0 rx input chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_spi0_rx_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON1, PIS_TAR_CON1_SPI0_RX_SEL_MSK); +} + +/** + * @brief Indicate if pis spi0 rx input chose ch0 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_spi0_rx_ch0(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON1, PIS_TAR_CON1_SPI0_RX_SEL_MSK) == (PIS_TAR_CON1_SPI0_RX_SEL_MSK)); +} + +/** + * @brief Set pis uart4 rx input chose ch7. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_uart4_rx_ch7(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON1, PIS_TAR_CON1_UART4_RXD_SEL_MSK); +} + +/** + * @brief Set pis uart4 rx input chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_uart4_rx_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON1, PIS_TAR_CON1_UART4_RXD_SEL_MSK); +} + +/** + * @brief Indicate if pis uart4 rx input chose ch7 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_uart4_rx_ch7(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON1, PIS_TAR_CON1_UART4_RXD_SEL_MSK) == (PIS_TAR_CON1_UART4_RXD_SEL_MSK)); +} + +/** + * @brief Set pis uart3 rx input chose ch6. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_uart3_rx_ch6(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON1, PIS_TAR_CON1_UART3_RXD_SEL_MSK); +} + +/** + * @brief Set pis uart3 rx input chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_uart3_rx_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON1, PIS_TAR_CON1_UART3_RXD_SEL_MSK); +} + +/** + * @brief Indicate if pis uart3 rx input chose ch6 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_uart3_rx_ch6(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON1, PIS_TAR_CON1_UART3_RXD_SEL_MSK) == (PIS_TAR_CON1_UART3_RXD_SEL_MSK)); +} + +/** + * @brief Set pis uart2 rx input chose ch5. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_uart2_rx_ch5(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON1, PIS_TAR_CON1_UART2_RXD_SEL_MSK); +} + +/** + * @brief Set pis uart2 rx input chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_uart2_rx_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON1, PIS_TAR_CON1_UART2_RXD_SEL_MSK); +} + +/** + * @brief Indicate if pis uart2 rx input chose ch5 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_uart2_rx_ch5(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON1, PIS_TAR_CON1_UART2_RXD_SEL_MSK) == (PIS_TAR_CON1_UART2_RXD_SEL_MSK)); +} + +/** + * @brief Set pis uart1 rx input chose ch4. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_uart1_rx_ch4(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON1, PIS_TAR_CON1_UART1_RXD_SEL_MSK); +} + +/** + * @brief Set pis uart1 rx input chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_uart1_rx_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON1, PIS_TAR_CON1_UART1_RXD_SEL_MSK); +} + +/** + * @brief Indicate if pis uart1 rx input chose ch4 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_uart1_rx_ch4(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON1, PIS_TAR_CON1_UART1_RXD_SEL_MSK) == (PIS_TAR_CON1_UART1_RXD_SEL_MSK)); +} + +/** + * @brief Set pis uart0 rx input chose ch3. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_uart0_rx_ch3(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->TAR_CON1, PIS_TAR_CON1_UART0_RXD_SEL_MSK); +} + +/** + * @brief Set pis uart0 rx input chose port. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_enable_uart0_rx_port(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->TAR_CON1, PIS_TAR_CON1_UART0_RXD_SEL_MSK); +} + +/** + * @brief Indicate if pis uart0 rx input chose ch3 is enabled + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_enabled_uart0_rx_ch3(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->TAR_CON1, PIS_TAR_CON1_UART0_RXD_SEL_MSK) == (PIS_TAR_CON1_UART0_RXD_SEL_MSK)); +} +/** + * @} + */ +/** @defgroup MD_PIS_Public_Functions_Group6 UART0_TXMCR + * @{ + */ +/** + * @brief Set pis uart0 tx modulation level high. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_set_uart0_tx_mod_high(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->UART0_TXMCR, PIS_UART0_TXMCR_TXMLVLS_MSK); +} + +/** + * @brief Set pis uart0 tx modulation level low. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_set_uart0_tx_mod_low(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->UART0_TXMCR, PIS_UART0_TXMCR_TXMLVLS_MSK); +} + +/** + * @brief Indicate if pis uart0 tx modulation level high is set + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_set_uart0_tx_mod_high(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->UART0_TXMCR, PIS_UART0_TXMCR_TXMLVLS_MSK) == (PIS_UART0_TXMCR_TXMLVLS_MSK)); +} + +/** + * @brief Set pis uart0 modulation source. + * @param PISx PIS Instance. + * @param src PIS uart0 modulation source. + * @retval None + */ +__STATIC_INLINE void md_pis_set_uart0_mod_src(PIS_TypeDef *PISx, md_pis_modu_src_t src) +{ + MODIFY_REG(PISx->UART0_TXMCR, PIS_UART0_TXMCR_TXMSS_MSK, src << PIS_UART0_TXMCR_TXMSS_POSS); +} + +/** + * @brief Get pis uart0 modulation source. + * @param PISx PIS Instance. + * @retval uart0 modulation source @ref md_pis_modu_src_t + */ +__STATIC_INLINE uint32_t md_pis_get_uart0_mod_src(PIS_TypeDef *PISx) +{ + return READ_BITS(PISx->UART0_TXMCR, PIS_UART0_TXMCR_TXMSS_MSK, PIS_UART0_TXMCR_TXMSS_POSS); +} + +/** + * @brief Set pis uart0 modulation timx channel. + * @param PISx PIS Instance. + * @param channel PIS timx modulation channel. + * @retval None + */ +__STATIC_INLINE void md_pis_set_uart0_mod_tim_channel(PIS_TypeDef *PISx, md_pis_modu_channel_t channel) +{ + MODIFY_REG(PISx->UART0_TXMCR, PIS_UART0_TXMCR_TXSIGS_MSK, channel << PIS_UART0_TXMCR_TXSIGS_POSS); +} + +/** + * @brief Get pis uart0 timx modulation channel. + * @param PISx PIS Instance. + * @retval uart0 timx modulation channel @ref md_pis_modu_channel_t + */ +__STATIC_INLINE uint32_t md_pis_get_uart0_mod_tim_channel(PIS_TypeDef *PISx) +{ + return READ_BITS(PISx->UART0_TXMCR, PIS_UART0_TXMCR_TXSIGS_MSK, PIS_UART0_TXMCR_TXSIGS_POSS); +} +/** + * @} + */ +/** @defgroup MD_PIS_Public_Functions_Group7 UART1_TXMCR + * @{ + */ +/** + * @brief Set pis uart1 tx modulation level high. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_set_uart1_tx_mod_high(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->UART1_TXMCR, PIS_UART1_TXMCR_TXMLVLS_MSK); +} + +/** + * @brief Set pis uart1 tx modulation level low. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_set_uart1_tx_mod_low(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->UART1_TXMCR, PIS_UART1_TXMCR_TXMLVLS_MSK); +} + +/** + * @brief Indicate if pis uart1 tx modulation level high is set + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_set_uart1_tx_mod_high(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->UART1_TXMCR, PIS_UART1_TXMCR_TXMLVLS_MSK) == (PIS_UART1_TXMCR_TXMLVLS_MSK)); +} + +/** + * @brief Set pis uart1 modulation source. + * @param PISx PIS Instance. + * @param src PIS uart1 modulation source. + * @retval None + */ +__STATIC_INLINE void md_pis_set_uart1_mod_src(PIS_TypeDef *PISx, md_pis_modu_src_t src) +{ + MODIFY_REG(PISx->UART1_TXMCR, PIS_UART1_TXMCR_TXMSS_MSK, src << PIS_UART1_TXMCR_TXMSS_POSS); +} + +/** + * @brief Get pis uart1 modulation source. + * @param PISx PIS Instance. + * @retval uart1 modulation source @ref md_pis_modu_src_t + */ +__STATIC_INLINE uint32_t md_pis_get_uart1_mod_src(PIS_TypeDef *PISx) +{ + return READ_BITS(PISx->UART1_TXMCR, PIS_UART1_TXMCR_TXMSS_MSK, PIS_UART1_TXMCR_TXMSS_POSS); +} + +/** + * @brief Set pis uart1 modulation timx channel. + * @param PISx PIS Instance. + * @param channel PIS timx modulation channel. + * @retval None + */ +__STATIC_INLINE void md_pis_set_uart1_mod_tim_channel(PIS_TypeDef *PISx, md_pis_modu_channel_t channel) +{ + MODIFY_REG(PISx->UART1_TXMCR, PIS_UART1_TXMCR_TXSIGS_MSK, channel << PIS_UART1_TXMCR_TXSIGS_POSS); +} + +/** + * @brief Get pis uart1 timx modulation channel. + * @param PISx PIS Instance. + * @retval uart1 timx modulation channel @ref md_pis_modu_channel_t + */ +__STATIC_INLINE uint32_t md_pis_get_uart1_mod_tim_channel(PIS_TypeDef *PISx) +{ + return READ_BITS(PISx->UART1_TXMCR, PIS_UART1_TXMCR_TXSIGS_MSK, PIS_UART1_TXMCR_TXSIGS_POSS); +} +/** + * @} + */ +/** @defgroup MD_PIS_Public_Functions_Group8 UART2_TXMCR + * @{ + */ +/** + * @brief Set pis uart2 tx modulation level high. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_set_uart2_tx_mod_high(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->UART2_TXMCR, PIS_UART2_TXMCR_TXMLVLS_MSK); +} + +/** + * @brief Set pis uart2 tx modulation level low. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_set_uart2_tx_mod_low(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->UART2_TXMCR, PIS_UART2_TXMCR_TXMLVLS_MSK); +} + +/** + * @brief Indicate if pis uart2 tx modulation level high is set + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_set_uart2_tx_mod_high(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->UART2_TXMCR, PIS_UART2_TXMCR_TXMLVLS_MSK) == (PIS_UART2_TXMCR_TXMLVLS_MSK)); +} + +/** + * @brief Set pis uart2 modulation source. + * @param PISx PIS Instance. + * @param src PIS uart2 modulation source. + * @retval None + */ +__STATIC_INLINE void md_pis_set_uart2_mod_src(PIS_TypeDef *PISx, md_pis_modu_src_t src) +{ + MODIFY_REG(PISx->UART2_TXMCR, PIS_UART2_TXMCR_TXMSS_MSK, src << PIS_UART2_TXMCR_TXMSS_POSS); +} + +/** + * @brief Get pis uart2 modulation source. + * @param PISx PIS Instance. + * @retval uart2 modulation source @ref md_pis_modu_src_t + */ +__STATIC_INLINE uint32_t md_pis_get_uart2_mod_src(PIS_TypeDef *PISx) +{ + return READ_BITS(PISx->UART2_TXMCR, PIS_UART2_TXMCR_TXMSS_MSK, PIS_UART2_TXMCR_TXMSS_POSS); +} + +/** + * @brief Set pis uart2 modulation timx channel. + * @param PISx PIS Instance. + * @param channel PIS timx modulation channel. + * @retval None + */ +__STATIC_INLINE void md_pis_set_uart2_mod_tim_channel(PIS_TypeDef *PISx, md_pis_modu_channel_t channel) +{ + MODIFY_REG(PISx->UART2_TXMCR, PIS_UART2_TXMCR_TXSIGS_MSK, channel << PIS_UART2_TXMCR_TXSIGS_POSS); +} + +/** + * @brief Get pis uart2 timx modulation channel. + * @param PISx PIS Instance. + * @retval uart2 timx modulation channel @ref md_pis_modu_channel_t + */ +__STATIC_INLINE uint32_t md_pis_get_uart2_mod_tim_channel(PIS_TypeDef *PISx) +{ + return READ_BITS(PISx->UART2_TXMCR, PIS_UART2_TXMCR_TXSIGS_MSK, PIS_UART2_TXMCR_TXSIGS_POSS); +} +/** + * @} + */ +/** @defgroup MD_PIS_Public_Functions_Group9 UART3_TXMCR + * @{ + */ +/** + * @brief Set pis uart3 tx modulation level high. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_set_uart3_tx_mod_high(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->UART3_TXMCR, PIS_UART3_TXMCR_TXMLVLS_MSK); +} + +/** + * @brief Set pis uart3 tx modulation level low. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_set_uart3_tx_mod_low(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->UART3_TXMCR, PIS_UART3_TXMCR_TXMLVLS_MSK); +} + +/** + * @brief Indicate if pis uart3 tx modulation level high is set + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_set_uart3_tx_mod_high(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->UART3_TXMCR, PIS_UART3_TXMCR_TXMLVLS_MSK) == (PIS_UART3_TXMCR_TXMLVLS_MSK)); +} + +/** + * @brief Set pis uart3 modulation source. + * @param PISx PIS Instance. + * @param src PIS uart3 modulation source. + * @retval None + */ +__STATIC_INLINE void md_pis_set_uart3_mod_src(PIS_TypeDef *PISx, md_pis_modu_src_t src) +{ + MODIFY_REG(PISx->UART3_TXMCR, PIS_UART3_TXMCR_TXMSS_MSK, src << PIS_UART3_TXMCR_TXMSS_POSS); +} + +/** + * @brief Get pis uart3 modulation source. + * @param PISx PIS Instance. + * @retval uart3 modulation source @ref md_pis_modu_src_t + */ +__STATIC_INLINE uint32_t md_pis_get_uart3_mod_src(PIS_TypeDef *PISx) +{ + return READ_BITS(PISx->UART3_TXMCR, PIS_UART3_TXMCR_TXMSS_MSK, PIS_UART3_TXMCR_TXMSS_POSS); +} + +/** + * @brief Set pis uart3 modulation timx channel. + * @param PISx PIS Instance. + * @param channel PIS timx modulation channel. + * @retval None + */ +__STATIC_INLINE void md_pis_set_uart3_mod_tim_channel(PIS_TypeDef *PISx, md_pis_modu_channel_t channel) +{ + MODIFY_REG(PISx->UART3_TXMCR, PIS_UART3_TXMCR_TXSIGS_MSK, channel << PIS_UART3_TXMCR_TXSIGS_POSS); +} + +/** + * @brief Get pis uart3 timx modulation channel. + * @param PISx PIS Instance. + * @retval uart3 timx modulation channel @ref md_pis_modu_channel_t + */ +__STATIC_INLINE uint32_t md_pis_get_uart3_mod_tim_channel(PIS_TypeDef *PISx) +{ + return READ_BITS(PISx->UART3_TXMCR, PIS_UART3_TXMCR_TXSIGS_MSK, PIS_UART3_TXMCR_TXSIGS_POSS); +} +/** + * @} + */ +/** @defgroup MD_PIS_Public_Functions_Group10 UART4_TXMCR + * @{ + */ +/** + * @brief Set pis uart4 tx modulation level high. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_set_uart4_tx_mod_high(PIS_TypeDef *PISx) +{ + SET_BIT(PISx->UART4_TXMCR, PIS_UART4_TXMCR_TXMLVLS_MSK); +} + +/** + * @brief Set pis uart4 tx modulation level low. + * @param PISx PIS Instance. + * @retval None + */ +__STATIC_INLINE void md_pis_set_uart4_tx_mod_low(PIS_TypeDef *PISx) +{ + CLEAR_BIT(PISx->UART4_TXMCR, PIS_UART4_TXMCR_TXMLVLS_MSK); +} + +/** + * @brief Indicate if pis uart4 tx modulation level high is set + * @param PISx PIS Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pis_is_set_uart4_tx_mod_high(PIS_TypeDef *PISx) +{ + return (uint32_t)(READ_BIT(PISx->UART4_TXMCR, PIS_UART4_TXMCR_TXMLVLS_MSK) == (PIS_UART4_TXMCR_TXMLVLS_MSK)); +} + +/** + * @brief Set pis uart4 modulation source. + * @param PISx PIS Instance. + * @param src PIS uart4 modulation source. + * @retval None + */ +__STATIC_INLINE void md_pis_set_uart4_mod_src(PIS_TypeDef *PISx, md_pis_modu_src_t src) +{ + MODIFY_REG(PISx->UART4_TXMCR, PIS_UART4_TXMCR_TXMSS_MSK, src << PIS_UART4_TXMCR_TXMSS_POSS); +} + +/** + * @brief Get pis uart4 modulation source. + * @param PISx PIS Instance. + * @retval uart4 modulation source @ref md_pis_modu_src_t + */ +__STATIC_INLINE uint32_t md_pis_get_uart4_mod_src(PIS_TypeDef *PISx) +{ + return READ_BITS(PISx->UART4_TXMCR, PIS_UART4_TXMCR_TXMSS_MSK, PIS_UART4_TXMCR_TXMSS_POSS); +} + +/** + * @brief Set pis uart4 modulation timx channel. + * @param PISx PIS Instance. + * @param channel PIS timx modulation channel. + * @retval None + */ +__STATIC_INLINE void md_pis_set_uart4_mod_tim_channel(PIS_TypeDef *PISx, md_pis_modu_channel_t channel) +{ + MODIFY_REG(PISx->UART4_TXMCR, PIS_UART4_TXMCR_TXSIGS_MSK, channel << PIS_UART4_TXMCR_TXSIGS_POSS); +} + +/** + * @brief Get pis uart4 timx modulation channel. + * @param PISx PIS Instance. + * @retval uart4 timx modulation channel @ref md_pis_modu_channel_t + */ +__STATIC_INLINE uint32_t md_pis_get_uart4_mod_tim_channel(PIS_TypeDef *PISx) +{ + return READ_BITS(PISx->UART4_TXMCR, PIS_UART4_TXMCR_TXSIGS_MSK, PIS_UART4_TXMCR_TXSIGS_POSS); +} +/** + * @} + */ +/** @defgroup MD_PIS_Public_Functions_Group1 Initialization + * @{ + */ +extern void md_pis_reset(void); +extern md_status_t md_pis_init(md_pis_init_t *init); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __MD_PIS_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_pmu.c b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_pmu.c new file mode 100644 index 0000000000..44ed407244 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_pmu.c @@ -0,0 +1,166 @@ +/********************************************************************************** + * + * @file md_pmu.c + * @brief Power management unit driver. + * + * @date 16 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 16 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_pmu.h" +#include "md_syscfg.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ + +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @addtogroup MD_PMU + * @{ + */ + +/** @addtogroup MD_PMU_Public_Functions + * @{ + */ +/** @addtogroup MD_PMU_Public_Functions_Group1 + * @{ + */ +/** + * @brief Reset the PMU register + * @retval None + */ +void md_pmu_reset(void) +{ + MD_SYSCFG_UNLOCK(); + WRITE_REG(PMU->CR, 0x1C000080); + WRITE_REG(PMU->LVDCR, 0x0); + MD_SYSCFG_LOCK(); + return; +} + +/** + * @brief Enter stop mode + * @retval None + */ +void md_pmu_stop_enter(void) +{ + uint32_t clint_irq_en = 0U; + clint_irq_en = csi_vic_get_enabled_irq(CLINT_IRQn); + csi_vic_disable_sirq(CLINT_IRQn); + + MD_SYSCFG_UNLOCK(); + CLEAR_BIT(PMU->CR, PMU_CR_VROSCEN_MSK); + MODIFY_REG(PMU->CR, PMU_CR_LPSTOP_MSK | PMU_CR_BGSTOP_MSK | \ + PMU_CR_STPRTNEN_MSK | PMU_CR_FSTOP_MSK, \ + 1 << PMU_CR_LPSTOP_POS | 1 << PMU_CR_BGSTOP_POS \ + | 1 << PMU_CR_STPRTNEN_POS | 1 << PMU_CR_FSTOP_POS); + /* WKEVNSEL is only for testing, and user should set it to be 0x10. */ + MODIFY_REG(PMU->CR, PMU_CR_WKEVNSEL_MSK, (0x10 << PMU_CR_WKEVNSEL_POSS)); + MD_SYSCFG_LOCK(); + + csi_cpu_sleep_wfi(MEXSTATUS_SLEEP_DEEP); + + __WFI_(); + + if(clint_irq_en) + csi_vic_enable_sirq(CLINT_IRQn); +} + +/** + * @brief Enter sleep mode + * @retval None + */ +void md_pmu_sleep_enter(void) +{ + uint32_t clint_irq_en = 0U; + clint_irq_en = csi_vic_get_enabled_irq(CLINT_IRQn); + csi_vic_disable_sirq(CLINT_IRQn); + + MD_SYSCFG_UNLOCK(); + /* WKEVNSEL is only for testing, and user should set it to be 0x10. */ + MODIFY_REG(PMU->CR, PMU_CR_WKEVNSEL_MSK, (0x10 << PMU_CR_WKEVNSEL_POSS)); + MD_SYSCFG_LOCK(); + + csi_cpu_sleep_wfi(MEXSTATUS_SLEEP_LIGHT); + + __WFI_(); + + if(clint_irq_en) + csi_vic_enable_sirq(CLINT_IRQn); +} + +/** + * @brief Configure lvd using specified parameters. + * @param sel: LVD threshold voltage. + * @param mode: LVD trigger mode. + * @param state: New state, ENABLE/DISABLE; + * @retval None + */ +void md_pmu_lvd_config(md_pmu_lvd_voltage_sel_t sel, md_pmu_lvd_trigger_mode_t mode, type_func_t state) +{ + MD_SYSCFG_UNLOCK(); + + if (state) + { + MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS); + MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDIFS_MSK, mode << PMU_LVDCR_LVDIFS_POSS); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); + } + else + { + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); + CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); + } + + MD_SYSCFG_LOCK(); + + return; +} +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_pmu.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_pmu.h new file mode 100644 index 0000000000..ff3e7d3630 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_pmu.h @@ -0,0 +1,583 @@ +/********************************************************************************** + * + * @file md_pmu.h + * @brief Header file of PMU module driver. + * + * @date 16 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 16 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __MD_PMU_H__ +#define __MD_PMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_utils.h" + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_PMU PMU + * @brief PMU micro driver + * @{ + */ + +/** @defgroup MD_PMU_Public_Types PMU Public Types + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** + * @brief Low power mode + */ +typedef enum +{ + MD_PMU_LP_STOP = 0x0U /**< stop */ +} md_pmu_lp_mode_t; + +/** + * @brief LVD voltage select + */ +typedef enum +{ + MD_PMU_LVD_VOL_SEL_2_2 = 0x0U, /**< 2.2V */ + MD_PMU_LVD_VOL_SEL_2_4 = 0x1U, /**< 2.4V */ + MD_PMU_LVD_VOL_SEL_2_6 = 0x2U, /**< 2.6V */ + MD_PMU_LVD_VOL_SEL_2_8 = 0x3U, /**< 2.8V */ + MD_PMU_LVD_VOL_SEL_3_0 = 0x4U, /**< 3.0V */ + MD_PMU_LVD_VOL_SEL_3_6 = 0x5U, /**< 3.6V */ + MD_PMU_LVD_VOL_SEL_4_0 = 0x6U, /**< 4.0V */ + MD_PMU_LVD_VOL_SEL_4_6 = 0x7U, /**< 4.6V */ +} md_pmu_lvd_voltage_sel_t; + +/** + * @brief LVD trigger mode + */ +typedef enum +{ + MD_PMU_LVD_TRIGGER_RISING_EDGE = 0x0U, /**< Rising edge */ + MD_PMU_LVD_TRIGGER_FALLING_EDGE = 0x1U, /**< Falling edge */ + MD_PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2U, /**< High level */ + MD_PMU_LVD_TRIGGER_LOW_LEVEL = 0x3U, /**< Low level */ + MD_PMU_LVD_TRIGGER_RISING_FALLING = 0x4U, /**< Rising and falling edge */ +} md_pmu_lvd_trigger_mode_t; + +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @defgroup MD_PMU_Public_Functions PMU Public Functions + * @{ + */ +/** @defgroup MD_PMU_Public_Functions_Group1 CR + * @{ + */ + +/** + * @brief Set pmu low power mode. + * @param mode: low power mode @see md_pmu_lp_mode_t + * @retval None + */ +__STATIC_INLINE void md_pmu_set_low_power_mode(md_pmu_lp_mode_t mode) +{ + MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, mode << PMU_CR_LPM_POSS); +} + +/** + * @brief Get pmu low power mode. + * @retval low power mode @see md_pmu_lp_mode_t + */ +__STATIC_INLINE uint32_t md_pmu_get_low_power_mode(void) +{ + return READ_BITS(PMU->CR, PMU_CR_LPM_MSK, PMU_CR_LPM_POSS); +} + +/** + * @brief Clear wuf flag. + * @retval None + */ +__STATIC_INLINE void md_pmu_clear_flag_cwuf(void) +{ + SET_BIT(PMU->CR, PMU_CR_CWUF_MSK); +} + +/** + * @brief Set STOP2 SRAM retention enable. + * @retval None + */ +__STATIC_INLINE void md_pmu_set_stop2_sram_retention_enable(void) +{ + SET_BIT(PMU->CR, PMU_CR_STPRTNEN_MSK); +} +/** + * @brief Set STOP2 SRAM retention disable. + * @retval None + */ +__STATIC_INLINE void md_pmu_set_stop2_sram_retention_disable(void) +{ + CLEAR_BIT(PMU->CR, PMU_CR_STPRTNEN_MSK); +} +/** + * @brief check if STOP2 SRAM retention enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_pmu_is_enable_stop2_sram_retention(void) +{ + return (READ_BIT(PMU->CR, PMU_CR_STPRTNEN_MSK) == PMU_CR_STPRTNEN_MSK); +} + +/** + * @brief Set normal mode SRAM retention enable. + * @retval None + */ +__STATIC_INLINE void md_pmu_set_normal_sram_retention_enable(void) +{ + SET_BIT(PMU->CR, PMU_CR_NORRTNEN_MSK); +} +/** + * @brief Set normal mode SRAM retention disable. + * @retval None + */ +__STATIC_INLINE void md_pmu_set_normal_sram_retention_disable(void) +{ + CLEAR_BIT(PMU->CR, PMU_CR_NORRTNEN_MSK); +} +/** + * @brief check if normal mode SRAM retention enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_pmu_is_enable_normal_sram_retention(void) +{ + return (READ_BIT(PMU->CR, PMU_CR_NORRTNEN_MSK) == PMU_CR_NORRTNEN_MSK); +} + +/** + * @brief Set VR clock enable. + * @retval None + */ +__STATIC_INLINE void md_pmu_set_vr_clk_enable_vroscen(void) +{ + SET_BIT(PMU->CR, PMU_CR_VROSCEN_MSK); +} +/** + * @brief Set VR clock disable. + * @retval None + */ +__STATIC_INLINE void md_pmu_set_vr_clk_disable_vroscen(void) +{ + CLEAR_BIT(PMU->CR, PMU_CR_VROSCEN_MSK); +} +/** + * @brief check if VR clock enable. + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_pmu_is_enable_vr_clk(void) +{ + return (READ_BIT(PMU->CR, PMU_CR_VROSCEN_MSK) == PMU_CR_VROSCEN_MSK); +} + +/** + * @brief Set the ldo voltage in lowpower mode. + * @param voltage: + * 0x0 - 1.3V + * 0x1 - 1.4V + * 0x2 - 1.5V + * 0x3 - 1.6V + * @retval None + */ +__STATIC_INLINE void md_pmu_set_ldo_mode(uint32_t voltage) +{ + MODIFY_REG(PMU->CR, PMU_CR_LPVS_MSK, (voltage << PMU_CR_LPVS_POSS)); +} +/** + * @brief Get ldo voltage in lowpower mode. + * @retval ldo voltage in lowpower mode. + */ +__STATIC_INLINE uint32_t md_pmu_get_ldo(void) +{ + return (READ_BITS(PMU->CR, PMU_CR_LPVS_MSK, PMU_CR_LPVS_POSS)); +} + +/** + * @brief Enable LDO low power mode. + * @retval None + */ +__STATIC_INLINE void md_pmu_enable_ldo_lp(void) +{ + SET_BIT(PMU->CR, PMU_CR_LPRUN_MSK); +} +/** + * @brief Disable LDO low power mode. + * @retval None + */ +__STATIC_INLINE void md_pmu_disable_ldo_lp(void) +{ + CLEAR_BIT(PMU->CR, PMU_CR_LPRUN_MSK); +} +/** + * @brief Get if LDO low power mode is enable. + * @retval Status: + * - 0: Disable + * - 1: Enable + */ +__STATIC_INLINE uint32_t md_pmu_get_if_ldo_lp_is_enable(void) +{ + return (READ_BIT(PMU->CR, PMU_CR_LPRUN_MSK) == PMU_CR_LPRUN_MSK); +} + +/** + * @brief Enable STOP2 LDO low power mode. + * @retval None + */ +__STATIC_INLINE void md_pmu_enable_stop2_ldo_lp(void) +{ + SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); +} +/** + * @brief Disable STOP2 LDO low power mode. + * @retval None + */ +__STATIC_INLINE void md_pmu_disable_stop2_ldo_lp(void) +{ + CLEAR_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); +} +/** + * @brief Get if STOP2 LDO low power mode is enable. + * @retval Status: + * - 0: Disable + * - 1: Enable + */ +__STATIC_INLINE uint32_t md_pmu_get_if_stop2_ldo_lp_is_enable(void) +{ + return (READ_BIT(PMU->CR, PMU_CR_LPSTOP_MSK) == PMU_CR_LPSTOP_MSK); +} + +/** + * @brief Enable STOP2 BG low power mode. + * @retval None + */ +__STATIC_INLINE void md_pmu_enable_stop2_bg_lp(void) +{ + SET_BIT(PMU->CR, PMU_CR_BGSTOP_MSK); +} +/** + * @brief Disable STOP2 BG low power mode. + * @retval None + */ +__STATIC_INLINE void md_pmu_disable_stop2_bg_lp(void) +{ + CLEAR_BIT(PMU->CR, PMU_CR_BGSTOP_MSK); +} +/** + * @brief Get if STOP2 BG low power mode is enable. + * @retval Status: + * - 0: Disable + * - 1: Enable + */ +__STATIC_INLINE uint32_t md_pmu_get_if_stop2_bg_lp_is_enable(void) +{ + return (READ_BIT(PMU->CR, PMU_CR_BGSTOP_MSK) == PMU_CR_BGSTOP_MSK); +} + +/** + * @brief Enable STOP2 Flash stop. + * @retval None + */ +__STATIC_INLINE void md_pmu_enable_stop2_flash_stop(void) +{ + SET_BIT(PMU->CR, PMU_CR_FSTOP_MSK); +} +/** + * @brief Disable STOP2 Flash stop. + * @retval None + */ +__STATIC_INLINE void md_pmu_disable_stop2_flash_stop(void) +{ + CLEAR_BIT(PMU->CR, PMU_CR_FSTOP_MSK); +} +/** + * @brief Get if STOP2 Flash stop is enable. + * @retval Status: + * - 0: Disable + * - 1: Enable + */ +__STATIC_INLINE uint32_t md_pmu_get_if_stop2_flash_stop_is_enable(void) +{ + return (READ_BIT(PMU->CR, PMU_CR_FSTOP_MSK) == PMU_CR_FSTOP_MSK); +} +/** + * @brief Set the WFE wakeup event. + * @param event: irq table + * @retval None + */ +__STATIC_INLINE void md_pmu_set_wfe_wakeup_event(uint32_t event) +{ + MODIFY_REG(PMU->CR, PMU_CR_WKEVNSEL_MSK, (event << PMU_CR_WKEVNSEL_POSS)); +} +/** + * @brief Get WFE wakeup event. + * @retval WFE wakeup event. + */ +__STATIC_INLINE uint32_t md_pmu_get_wfe_wakeup_event(void) +{ + return (READ_BITS(PMU->CR, PMU_CR_WKEVNSEL_MSK, PMU_CR_WKEVNSEL_POSS)); +} + +/** + * @} + */ + +/** @defgroup MD_PMU_Public_Functions_Group2 SR + * @{ + */ + +/** + * @brief Get Wakeup flag . + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pmu_is_active_flag_wakeup(void) +{ + return (READ_BIT(PMU->SR, PMU_SR_WUF_MSK) == PMU_SR_WUF_MSK); +} + +/** + * @} + */ +/** @defgroup MD_PMU_Public_Functions_Group3 LVDCR + * @{ + */ +/** + * @brief Get LVD Status flag . + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pmu_is_active_flag_lvdo(void) +{ + return (READ_BIT(PMU->LVDCR, PMU_LVDCR_LVDO_MSK) == PMU_LVDCR_LVDO_MSK); +} + +/** + * @brief Enable the LVD filter . + * @retval None + */ +__STATIC_INLINE void md_pmu_enable_lvd_filter(void) +{ + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK); +} + +/** + * @brief Disable the LVD filter . + * @retval None + */ +__STATIC_INLINE void md_pmu_disable_lvd_filter(void) +{ + CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK); +} + +/** + * @brief Check if the LVD filter is enable or disable. + * @retval State for bit (1 or 0) + */ +__STATIC_INLINE uint32_t md_pmu_is_enable_lvd_filter(void) +{ + return (READ_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK) == PMU_LVDCR_LVDFLT_MSK); +} + +/** + * @brief Set LVD Interrupt mode. + * @param mode: lvd interrupt mode @see md_pmu_lvd_trigger_mode_t. + * @retval None. + */ +__STATIC_INLINE void md_pmu_set_lvd_it_mode(md_pmu_lvd_trigger_mode_t mode) +{ + MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDIFS_MSK, mode << PMU_LVDCR_LVDIFS_POSS); +} + +/** + * @brief Get LVD Interrupt mode. + * @retval value for lvd it mode. + */ +__STATIC_INLINE uint32_t md_pmu_get_lvd_it_mode(void) +{ + return READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDIFS_MSK, PMU_LVDCR_LVDIFS_POSS); +} + +/** + * @brief Set LVD voltage threshold value. + * @param value: threshold value @see md_pmu_lvd_voltage_sel_t. + * @retval None. + */ +__STATIC_INLINE void md_pmu_set_lvd_vol_threshold(md_pmu_lvd_voltage_sel_t value) +{ + MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, value << PMU_LVDCR_LVDS_POSS); +} + +/** + * @brief Get LVD voltage threshold value. + * @retval value for lvd voltage threshold @see pmu_lvd_voltage_sel_t. + */ +__STATIC_INLINE uint32_t md_pmu_get_lvd_vol_threshold(void) +{ + return (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, PMU_LVDCR_LVDS_POSS)); +} + +/** + * @brief Set LVD interrupt flag clear bit. + * @retval None. + */ +__STATIC_INLINE void md_pmu_set_lvd_it_flag(void) +{ + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); +} + +/** + * @brief Get LVD interrupt flag. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pmu_is_active_flag_lvd_it(void) +{ + return (READ_BIT(PMU->LVDCR, PMU_LVDCR_LVDIF_MSK) == PMU_LVDCR_LVDIF_MSK); +} + +/** + * @brief Enable LVD interrupt. + * @retval None. + */ +__STATIC_INLINE void md_pmu_enable_lvd_it(void) +{ + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); +} + +/** + * @brief Disable LVD interrupt. + * @retval None. + */ +__STATIC_INLINE void md_pmu_disable_lvd_it(void) +{ + CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); +} + +/** + * @brief Check if LVD interrupt is enable or disable. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pmu_is_enable_lvd_it(void) +{ + return (READ_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK) == PMU_LVDCR_LVDIE_MSK); +} + +/** + * @brief Enable LVD. + * @retval None. + */ +__STATIC_INLINE void md_pmu_enable_lvd(void) +{ + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); +} + +/** + * @brief Disable LVD interrupt. + * @retval None. + */ +__STATIC_INLINE void md_pmu_disable_lvd(void) +{ + CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); +} + +/** + * @brief Check if LVD is enable or disable. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_pmu_lvd_is_enable(void) +{ + return (READ_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK) == PMU_LVDCR_LVDEN_MSK); +} +/** + * @} + */ + +/** @defgroup MD_PMU_Public_Functions_Group4 Initialization + * @{ + */ +/** + * @brief Set LVD TWUR value. + * @param value: TWUR value. + * @retval None. + */ +__STATIC_INLINE__ void md_pmu_set_twur_value(uint32_t value) +{ + WRITE_REG(PMU->TWUR, value); +} + +/** + * @brief Get LVD TWUR value. + * @retval value of TWUR + */ +__STATIC_INLINE uint32_t md_pmu_get_twur_value(void) +{ + return (READ_BITS(PMU->TWUR, PMU_TWUR_TWU_MSK, PMU_TWUR_TWU_POSS)); +} + +extern void md_pmu_reset(void); +extern void md_pmu_sleep_enter(void); +extern void md_pmu_stop_enter(void); +extern void md_pmu_lvd_config(md_pmu_lvd_voltage_sel_t sel, md_pmu_lvd_trigger_mode_t mode, type_func_t state); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __MD_PMU_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_rmu.c b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_rmu.c new file mode 100644 index 0000000000..a3f427d8f0 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_rmu.c @@ -0,0 +1,208 @@ +/********************************************************************************** + * + * @file md_rmu.c + * @brief Reset management unit driver. + * + * @date 26 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 26 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_rmu.h" +#include "md_syscfg.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ + +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @addtogroup MD_RMU + * @{ + */ + +/** @addtogroup MD_RMU_Public_Functions + * @{ + */ +/** @addtogroup MD_RMU_Public_Functions_Group1 + * @{ + */ +/** + * @brief Reset the RMU register + * @retval None + */ +void md_rmu_reset(void) +{ + MD_SYSCFG_UNLOCK(); + WRITE_REG(RMU->CR, 0x0); + WRITE_REG(RMU->CRSTSR, 0xFFFF); + WRITE_REG(RMU->AHB1RSTR, 0x0); + WRITE_REG(RMU->AHB2RSTR, 0x0); + WRITE_REG(RMU->APBRSTR, 0x0); + MD_SYSCFG_LOCK(); + + return; +} + +/** + * @brief Configure BOR parameters. + * @param flt: filter time. + * @retval None + */ +void md_rmu_bor_config(md_rmu_bor_filter_t flt) +{ + MD_SYSCFG_UNLOCK(); + MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, flt << RMU_CR_BORFLT_POSS); + MD_SYSCFG_LOCK(); + + return; +} + +/** + * @brief Get specified reset status + * @param state: Speicifies the type of the reset, + * @retval The status. + */ +uint32_t md_rmu_get_reset_status(md_rmu_state_t state) +{ + if (state == MD_RMU_RST_ALL) + return RMU->RSTSR; + + if (READ_BIT(RMU->RSTSR, state)) + return SET; + + return RESET; +} + +/** + * @brief Clear the specified reset status + * @param state: Specifies the type of the reset, + * @retval None + */ +void md_rmu_clear_reset_status(md_rmu_state_t state) +{ + MD_SYSCFG_UNLOCK(); + WRITE_REG(RMU->CRSTSR, state); + MD_SYSCFG_LOCK(); + + return; +} + +/** + * @brief Reset peripheral device + * @param perh: The peripheral device, + * @retval None + */ +void md_rmu_reset_periperal(md_rmu_peripheral_t perh) +{ + uint32_t idx, pos; + + idx = ((uint32_t)perh >> 27) & 0x7; + pos = perh & ~(0x7 << 27); + MD_SYSCFG_UNLOCK(); + + switch (idx) + { + case 0: + WRITE_REG(RMU->AHB1RSTR, pos); + break; + + case 1: + WRITE_REG(RMU->AHB2RSTR, pos); + break; + + case 2: + WRITE_REG(RMU->APBRSTR, pos); + break; + + default: + break; + } + + MD_SYSCFG_LOCK(); + return; +} + +/** + * @brief System reset request + * @param None + * @retval None + */ +void md_rmu_reset_system(void) +{ + csi_cpu_reset(MEXSTATUS_RESET_CORE); + + return; +} + +/** + * @brief Chip reset request + * @param None + * @retval None + */ +void md_rmu_reset_chip(void) +{ + MD_SYSCFG_UNLOCK(); + SET_BIT(RMU->AHB2RSTR, RMU_AHB2RSTR_CHIPRST_MSK); + MD_SYSCFG_LOCK(); + + return; +} + +/** + * @brief CPU reset request + * @param None + * @retval None + */ +void md_rmu_reset_cpu(void) +{ + MD_SYSCFG_UNLOCK(); + SET_BIT(RMU->AHB2RSTR, RMU_AHB2RSTR_CPURST_MSK); + MD_SYSCFG_LOCK(); + + return; +} + +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_rmu.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_rmu.h new file mode 100644 index 0000000000..804ea75680 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_rmu.h @@ -0,0 +1,652 @@ +/********************************************************************************** + * + * @file md_rmu.h + * @brief Header file of RMU module driver. + * + * @date 16 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 16 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + + +#ifndef __MD_RMU_H__ +#define __MD_RMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_utils.h" + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_RMU RMU + * @brief RMU micro driver + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup MD_RMU_Public_Types RMU Public Types + * @{ + */ + +/** + * @brief Standby wakeup port select + */ +typedef enum +{ + MD_RMU_BORFLT_1 = 0x1U, /**< 1 cycle */ + MD_RMU_BORFLT_2 = 0x2U, /**< 2 cycles */ + MD_RMU_BORFLT_3 = 0x3U, /**< 3 cycles */ + MD_RMU_BORFLT_4 = 0x4U, /**< 4 cycles */ + MD_RMU_BORFLT_5 = 0x5U, /**< 5 cycles */ + MD_RMU_BORFLT_6 = 0x6U, /**< 6 cycles */ + MD_RMU_BORFLT_7 = 0x7U, /**< 7 cycles */ +} md_rmu_bor_filter_t; + +/** + * @brief RMU reset status + */ +typedef enum +{ + MD_RMU_RST_POR = (1U << 0), /**< POR */ + MD_RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */ + MD_RMU_RST_BOR = (1U << 2), /**< BOR */ + MD_RMU_RST_NMRST = (1U << 3), /**< NMRST */ + MD_RMU_RST_IWDT = (1U << 4), /**< IWDT */ + MD_RMU_RST_WWDT = (1U << 5), /**< WWDT */ + MD_RMU_RST_LOCKUP = (1U << 6), /**< LOCKUP */ + MD_RMU_RST_CHIP = (1U << 7), /**< CHIP */ + MD_RMU_RST_MCU = (1U << 8), /**< MCU */ + MD_RMU_RST_CPU = (1U << 9), /**< CPU */ + MD_RMU_RST_CFG = (1U << 10), /**< CFG */ + MD_RMU_RST_CFGERR = (1U << 16), /**< CFG Error */ + MD_RMU_RST_ALL = (0xFFFFFU), /**< ALL */ +} md_rmu_state_t; + +/** + * @brief RMU periperal select bit + */ +typedef enum +{ + MD_RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */ + MD_RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */ + MD_RMU_PERH_DMA = (1U << 2), /**< AHB1: DMA */ + MD_RMU_PERH_PIS = (1U << 5), /**< AHB1: PIS */ + MD_RMU_PERH_USB = (1U << 6), /**< AHB1: USB */ + MD_RMU_PERH_CSU = (1U << 7), /**< AHB1: CSU */ + + MD_RMU_PERH_CHIP = (1U << 0) | (1U << 27), /**< AHB2: CHIP */ + MD_RMU_PERH_CPU = (1U << 1) | (1U << 27), /**< AHB2: CPU */ + + MD_RMU_PERH_AD16C4T = (1U << 0) | (1U << 28), /**< APB: AD16C4T */ + MD_RMU_PERH_BS16T0 = (1U << 1) | (1U << 28), /**< APB: BS16T0 */ + MD_RMU_PERH_GP16C4T0 = (1U << 2) | (1U << 28), /**< APB: GP16C4T0 */ + MD_RMU_PERH_GP16C4T1 = (1U << 3) | (1U << 28), /**< APB: GP16C4T1 */ + MD_RMU_PERH_GP16C4T2 = (1U << 4) | (1U << 28), /**< APB: GP16C4T2 */ + MD_RMU_PERH_EUART0 = (1U << 8) | (1U << 28), /**< APB: EUART0 */ + MD_RMU_PERH_EUART1 = (1U << 9) | (1U << 28), /**< APB: EUART1 */ + MD_RMU_PERH_CUART0 = (1U << 12) | (1U << 28), /**< APB: CUART0 */ + MD_RMU_PERH_CUART1 = (1U << 13) | (1U << 28), /**< APB: CUART1 */ + MD_RMU_PERH_CUART2 = (1U << 14) | (1U << 28), /**< APB: CUART2 */ + MD_RMU_PERH_SPI0 = (1U << 16) | (1U << 28), /**< APB: SPI0 */ + MD_RMU_PERH_SPI1 = (1U << 17) | (1U << 28), /**< APB: SPI1 */ + MD_RMU_PERH_I2C0 = (1U << 20) | (1U << 28), /**< APB: I2C0 */ + MD_RMU_PERH_I2C1 = (1U << 21) | (1U << 28), /**< APB: I2C1 */ + MD_RMU_PERH_WWDT = (1U << 22) | (1U << 28), /**< APB: WWDT */ + MD_RMU_PERH_IWDT = (1U << 23) | (1U << 28), /**< APB: IWDT */ + MD_RMU_PERH_DBGCON = (1U << 24) | (1U << 28), /**< APB: DBGCON */ + MD_RMU_PERH_ADC = (1U << 25) | (1U << 28), /**< APB: ADC */ +} md_rmu_peripheral_t; +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @defgroup MD_RMU_Public_Functions RMU Public Functions + * @{ + */ +/** @defgroup MD_RMU_Public_Functions_Group2 CR + * @{ + */ +/** + * @brief Set period for BOR filter. + * @param period for BOR filter. + * @retval None. + */ +__STATIC_INLINE void md_rmu_set_bor_filter_period(md_rmu_bor_filter_t period) +{ + MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, period << RMU_CR_BORFLT_POSS); +} + +/** + * @brief Get period for BOR filter. + * @retval period for BOR filter. + */ +__STATIC_INLINE uint32_t md_rmu_get_bor_filter_period(void) +{ + return READ_BITS(RMU->CR, RMU_CR_BORFLT_MSK, RMU_CR_BORFLT_POSS); +} + +/** + * @} + */ +/** @defgroup MD_RMU_Public_Functions_Group3 RSTSR + * @{ + */ +/** + * @brief Get rmu configuration byte flag. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rmu_is_active_flag_cfgerr(void) +{ + return (READ_BIT(RMU->RSTSR, RMU_RSTSR_CFGERR_MSK) == (RMU_RSTSR_CFGERR_MSK)); +} + +/** + * @brief Get rmu configuration byte reset flag. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rmu_is_active_flag_cfg(void) +{ + return (READ_BIT(RMU->RSTSR, RMU_RSTSR_CFG_MSK) == (RMU_RSTSR_CFG_MSK)); +} + +/** + * @brief Get rmu cpu reset by soft flag. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rmu_is_active_flag_cpu(void) +{ + return (READ_BIT(RMU->RSTSR, RMU_RSTSR_CPU_MSK) == (RMU_RSTSR_CPU_MSK)); +} + +/** + * @brief Get rmu mcu reset by soft flag. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rmu_is_active_flag_mcu(void) +{ + return (READ_BIT(RMU->RSTSR, RMU_RSTSR_MCU_MSK) == (RMU_RSTSR_MCU_MSK)); +} + +/** + * @brief Get rmu chip reset by soft flag. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rmu_is_active_flag_rmu(void) +{ + return (READ_BIT(RMU->RSTSR, RMU_RSTSR_CHIP_MSK) == (RMU_RSTSR_CHIP_MSK)); +} + +/** + * @brief Get rmu lockup reset flag. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rmu_is_active_flag_lockup(void) +{ + return (READ_BIT(RMU->RSTSR, RMU_RSTSR_LOCKUP_MSK) == (RMU_RSTSR_LOCKUP_MSK)); +} + +/** + * @brief Get rmu wwdt reset flag. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rmu_is_active_flag_wwdt(void) +{ + return (READ_BIT(RMU->RSTSR, RMU_RSTSR_WWDT_MSK) == (RMU_RSTSR_WWDT_MSK)); +} + +/** + * @brief Get rmu iwdt reset flag. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rmu_is_active_flag_iwdt(void) +{ + return (READ_BIT(RMU->RSTSR, RMU_RSTSR_IWDT_MSK) == (RMU_RSTSR_IWDT_MSK)); +} + +/** + * @brief Get rmu nmrst reset flag. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rmu_is_active_flag_nmrst(void) +{ + return (READ_BIT(RMU->RSTSR, RMU_RSTSR_NMRST_MSK) == (RMU_RSTSR_NMRST_MSK)); +} + +/** + * @brief Get rmu bor reset flag. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rmu_is_active_flag_bor(void) +{ + return (READ_BIT(RMU->RSTSR, RMU_RSTSR_BOR_MSK) == (RMU_RSTSR_BOR_MSK)); +} + +/** + * @brief Get rmu wake up reset flag. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rmu_is_active_flag_wakeup(void) +{ + return (READ_BIT(RMU->RSTSR, RMU_RSTSR_WAKEUP_MSK) == (RMU_RSTSR_WAKEUP_MSK)); +} + +/** + * @brief Get rmu por reset flag. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rmu_is_active_flag_por(void) +{ + return (READ_BIT(RMU->RSTSR, RMU_RSTSR_POR_MSK) == (RMU_RSTSR_POR_MSK)); +} +/** + * @} + */ +/** @defgroup MD_RMU_Public_Functions_Group4 CRSTSR + * @{ + */ +/** + * @brief Clear rmu configuration byte reset flag. + * @retval None. + */ +__STATIC_INLINE void md_rmu_clear_flag_cfg(void) +{ + SET_BIT(RMU->CRSTSR, RMU_CRSTSR_CFG_MSK); +} + +/** + * @brief Clear rmu cpu reset by soft flag. + * @retval None. + */ +__STATIC_INLINE void md_rmu_clear_flag_cpu(void) +{ + SET_BIT(RMU->CRSTSR, RMU_CRSTSR_CPU_MSK); +} + +/** + * @brief Clear rmu mcu reset by soft flag. + * @retval None. + */ +__STATIC_INLINE void md_rmu_clear_flag_mcu(void) +{ + SET_BIT(RMU->CRSTSR, RMU_CRSTSR_MCU_MSK); +} + +/** + * @brief Clear rmu chip reset by soft flag. + * @retval None. + */ +__STATIC_INLINE void md_rmu_clear_flag_chip(void) +{ + SET_BIT(RMU->CRSTSR, RMU_CRSTSR_CHIP_MSK); +} + +/** + * @brief Clear rmu lockup reset by soft flag. + * @retval None. + */ +__STATIC_INLINE void md_rmu_clear_flag_lockup(void) +{ + SET_BIT(RMU->CRSTSR, RMU_CRSTSR_LOCKUP_MSK); +} + +/** + * @brief Clear rmu wwdt reset by soft flag. + * @retval None. + */ +__STATIC_INLINE void md_rmu_clear_flag_wwdt(void) +{ + SET_BIT(RMU->CRSTSR, RMU_CRSTSR_WWDT_MSK); +} + +/** + * @brief Clear rmu iwdt reset by soft flag. + * @retval None. + */ +__STATIC_INLINE void md_rmu_clear_flag_iwdt(void) +{ + SET_BIT(RMU->CRSTSR, RMU_CRSTSR_IWDT_MSK); +} + +/** + * @brief Clear rmu nmrst reset by soft flag. + * @retval None. + */ +__STATIC_INLINE void md_rmu_clear_flag_nmrst(void) +{ + SET_BIT(RMU->CRSTSR, RMU_CRSTSR_NMRST_MSK); +} + +/** + * @brief Clear rmu bor reset by soft flag. + * @retval None. + */ +__STATIC_INLINE void md_rmu_clear_flag_bor(void) +{ + SET_BIT(RMU->CRSTSR, RMU_CRSTSR_BOR_MSK); +} + +/** + * @brief Clear rmu por reset flag. + * @retval None. + */ +__STATIC_INLINE void md_rmu_clear_flag_por(void) +{ + SET_BIT(RMU->CRSTSR, RMU_CRSTSR_POR_MSK); +} +/** + * @} + */ +/** @defgroup MD_RMU_Public_Functions_Group5 AHB1RSTR + * @{ + */ +/** + * @brief Reset CSU periperal which depend on AHB1 bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_csu_reset(void) +{ + SET_BIT(RMU->AHB1RSTR, RMU_AHB1RSTR_CSURST_MSK); +} + +/** + * @brief Reset USB periperal which depend on AHB1 bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_usb_reset(void) +{ + SET_BIT(RMU->AHB1RSTR, RMU_AHB1RSTR_USBRST_MSK); +} + +/** + * @brief Reset pis periperal which depend on AHB1 bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_pis_reset(void) +{ + SET_BIT(RMU->AHB1RSTR, RMU_AHB1RSTR_PISRST_MSK); +} + +/** + * @brief Reset DMA periperal which depend on AHB1 bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_dma_reset(void) +{ + SET_BIT(RMU->AHB1RSTR, RMU_AHB1RSTR_DMARST_MSK); +} + +/** + * @brief Reset crc periperal which depend on AHB1 bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_crc_reset(void) +{ + SET_BIT(RMU->AHB1RSTR, RMU_AHB1RSTR_CRCRST_MSK); +} + +/** + * @brief Reset gpio periperal which depend on AHB1 bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_gpio_reset(void) +{ + SET_BIT(RMU->AHB1RSTR, RMU_AHB1RSTR_GPIORST_MSK); +} +/** + * @} + */ +/** @defgroup MD_RMU_Public_Functions_Group6 AHB2RSTR + * @{ + */ +/** + * @brief Reset kernel processor which depend on AHB2 bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_cpu_reset(void) +{ + SET_BIT(RMU->AHB2RSTR, RMU_AHB2RSTR_CPURST_MSK); +} + +/** + * @brief Reset full chip . + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_chip_reset(void) +{ + SET_BIT(RMU->AHB2RSTR, RMU_AHB2RSTR_CHIPRST_MSK); +} +/** + * @} + */ +/** @defgroup MD_RMU_Public_Functions_Group7 APBRSTR + * @{ + */ +/** + * @brief Reset adc periperal which depend on APB bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_adc_reset(void) +{ + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_ADCRST_MSK); +} + +/** + * @brief Reset dbgcon periperal which depend on APB bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_dbgcon_reset(void) +{ + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_DBGCONRST_MSK); +} + +/** + * @brief Reset iwdt periperal which depend on APB bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_iwdt_reset(void) +{ + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_IWDTRST_MSK); +} + +/** + * @brief Reset wwdt periperal which depend on APB bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_wwdt_reset(void) +{ + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_WWDTRST_MSK); +} + +/** + * @brief Reset i2c1 periperal which depend on APB bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_i2c1_reset(void) +{ + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_I2C1RST_MSK); +} + +/** + * @brief Reset i2c0 periperal which depend on APB bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_i2c0_reset(void) +{ + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_I2C0RST_MSK); +} + +/** + * @brief Reset spi1 periperal which depend on APB bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_spi1_reset(void) +{ + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_SPI1RST_MSK); +} + +/** + * @brief Reset spi0 periperal which depend on APB bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_spi0_reset(void) +{ + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_SPI0RST_MSK); +} + +/** + * @brief Reset cuart2 periperal which depend on APB bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_cuart2_reset(void) +{ + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_CUART2RST_MSK); +} + +/** + * @brief Reset cuart1 periperal which depend on APB bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_cuart1_reset(void) +{ + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_CUART1RST_MSK); +} + +/** + * @brief Reset cuart0 periperal which depend on APB bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_cuart0_reset(void) +{ + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_CUART0RST_MSK); +} + +/** + * @brief Reset euart1 periperal which depend on APB bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_euart1_reset(void) +{ + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_EUART1RST_MSK); +} + +/** + * @brief Reset euart0 periperal which depend on APB bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_euart0_reset(void) +{ + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_EUART0RST_MSK); +} + +/** + * @brief Reset gp16c4t2 periperal which depend on APB bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_gp16c4t2_reset(void) +{ + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_GP16C4T2RST_MSK); +} + +/** + * @brief Reset gp16c4t1 periperal which depend on APB bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_gp16c4t1_reset(void) +{ + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_GP16C4T1RST_MSK); +} + +/** + * @brief Reset gp16c4t0 periperal which depend on APB bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_gp16c4t0_reset(void) +{ + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_GP16C4T0RST_MSK); +} + +/** + * @brief Reset bs16t0 periperal which depend on APB bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_bs16t0_reset(void) +{ + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_BS16T0RST_MSK); +} + +/** + * @brief Reset ad16c4t0 periperal which depend on APB bus. + * @retval None. + */ +__STATIC_INLINE void md_rmu_enable_ad16c4t0_reset(void) +{ + SET_BIT(RMU->APBRSTR, RMU_APBRSTR_AD16C4T0RST_MSK); +} +/** + * @} + */ +/** @defgroup MD_RMU_Public_Functions_Group1 Initialization + * @{ + */ +extern void md_rmu_reset(void); +extern void md_rmu_bor_config(md_rmu_bor_filter_t flt); +extern uint32_t md_rmu_get_reset_status(md_rmu_state_t state); +extern void md_rmu_clear_reset_status(md_rmu_state_t state); +extern void md_rmu_reset_periperal(md_rmu_peripheral_t perh); +extern void md_rmu_reset_system(void); +extern void md_rmu_reset_chip(void); +extern void md_rmu_reset_cpu(void); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __MD_RMU_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_spi.c b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_spi.c new file mode 100644 index 0000000000..9e2778f3d3 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_spi.c @@ -0,0 +1,215 @@ +/********************************************************************************** + * + * @file md_spi.c + * @brief SPI module driver. + * + * @date 28 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 28 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_spi.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ + +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @addtogroup MD_SPI + * @{ + */ + +/** @addtogroup MD_SPI_Public_Functions + * @{ + */ +/** @addtogroup MD_SPI_Public_Functions_Group1 + * @{ + */ +/** + * @brief Reset the SPI specificed. + * @param SPIx: SPI Instance. + * @retval None + */ +void md_spi_reset(SPI_I2S_TypeDef *SPIx) +{ + SPIx->CON1 = 0x0; + SPIx->CON2 = 0x0; + SPIx->CRCPOLY = 0x00000007; + + return; +} + +/** + * @brief Initialize the SPI registers according to the specified parameters in init. + * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CON1_SPIEN bit =0), + * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @param init pointer to a @ref md_spi_init_t structure + * @retval An ErrorStatus enumeration value. + */ +md_status_t md_spi_init(md_spi_init_t *init) +{ + uint32_t tmp = 0U; + + md_spi_reset(init->SPIx); + tmp = init->SPIx->CON1; + + if ((init->mode) == MD_SPI_MODE_MASTER) + tmp |= 1 << SPI_CON1_SSOUT_POS; + + tmp |= ((init->phase << SPI_CON1_CPHA_POS) | (init->polarity << SPI_CON1_CPOL_POS) | + (init->baud << SPI_CON1_BAUD_POSS) | (init->data_size << SPI_CON1_FLEN_POS) | + (init->mode << SPI_CON1_MSTREN_POS) | (init->ss_en << SPI_CON1_SSEN_POS) | + (init->first_bit << SPI_CON1_LSBFST_POS)); + + init->SPIx->CON1 = tmp; + + MODIFY_REG(init->SPIx->CON2, SPI_CON2_FRF_MSK, init->frame << SPI_CON2_FRF_POS); + + if (init->dir == MD_SPI_DIRECTION_2LINES) + { + md_spi_set_duplex_line_simplex(init->SPIx); + md_spi_disable_recv_only(init->SPIx); + } + else if (init->dir == MD_SPI_DIRECTION_2LINES_RXONLY) + { + md_spi_set_duplex_line_simplex(init->SPIx); + md_spi_enable_recv_only(init->SPIx); + } + else if (init->dir == MD_SPI_DIRECTION_1LINE_RX) + { + md_spi_set_simplex_line_duplex(init->SPIx); + md_spi_enable_simplex_line_rx(init->SPIx); + } + else + { + md_spi_set_simplex_line_duplex(init->SPIx); + md_spi_enable_simplex_line_tx(init->SPIx); + } + + /* configure CRC */ + init->SPIx->CON1 |= (init->crc_calc << SPI_CON1_CRCEN_POS); + init->SPIx->CRCPOLY = init->crc_poly; + + if (init->dir == MD_SPI_DIRECTION_2LINES) + md_spi_enable(init->SPIx); + + return MD_OK; +} + +/** + * @brief Set each @ref md_spi_init_t field to default value. + * @param init pointer to a @ref md_spi_init_t structure + * whose fields will be set to default values. + * @retval None + */ +void md_spi_struct_init(md_spi_init_t *init) +{ + init->SPIx = SPI1; + init->mode = MD_SPI_MODE_MASTER; + init->dir = MD_SPI_DIRECTION_2LINES; + init->data_size = MD_SPI_DATA_SIZE_8; + init->baud = MD_SPI_BAUD_64; + init->phase = MD_SPI_CPHA_FIRST; + init->polarity = MD_SPI_CPOL_HIGH; + init->first_bit = MD_SPI_FIRSTBIT_MSB; + init->ss_en = DISABLE; + init->crc_calc = DISABLE; + init->crc_poly = 0; +} + +/** + * @brief transmit one byte fast in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @param data: Data to be sent + * @retval status: + * - 0 Success + * - -1 Failed + */ +int32_t md_spi_send_byte_fast(md_spi_init_t *hperh, uint8_t data) +{ + uint16_t cnt = 5000U, temp; + + hperh->SPIx->DATA = data; + + while (((hperh->SPIx->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt)); + + cnt = 5000; + + while (((hperh->SPIx->STAT & SPI_STAT_RXNE_MSK) != SPI_STAT_RXNE_MSK) && (--cnt)); + + temp = hperh->SPIx->DATA; + UNUSED(temp); + + return cnt == 0 ? -1 : 0; +} + +/** + * @brief Receive one byte fast in blocking mode. + * @param hperh Pointer to a spi_handle_t structure. + * @param status: + * - 0 Success + * - -1 Failed + * @retval Data. + */ +uint8_t md_spi_recv_byte_fast(md_spi_init_t *hperh, int *status) +{ + uint16_t cnt = 4000U; + + if (hperh->mode == MD_SPI_MODE_MASTER) + { + hperh->SPIx->DATA = 0xFF; + + while (((hperh->SPIx->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt)); + } + + cnt = 4000; + + while (((hperh->SPIx->STAT & SPI_STAT_RXNE_MSK) != SPI_STAT_RXNE_MSK) && (--cnt)); + + *status = cnt == 0 ? -1 : 0; + + return (uint8_t)hperh->SPIx->DATA; +} +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_spi.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_spi.h new file mode 100644 index 0000000000..3a28faf441 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_spi.h @@ -0,0 +1,1830 @@ +/********************************************************************************** + * + * @file md_spi.h + * @brief Header file of SPI module driver. + * + * @date 28 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 28 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __MD_SPI_H__ +#define __MD_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_utils.h" + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_SPI SPI + * @brief SPI micro driver + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup MD_SPI_Public_Types SPI Public Types + * @{ + */ +/** + * @brief clock phase + */ +typedef enum +{ + MD_SPI_CPHA_FIRST = 0U, /**< Transiting data in the first edge */ + MD_SPI_CPHA_SECOND = 1U, /**< Transiting data in the seconde edge */ +} md_spi_cpha_t; + +/** + * @brief clock polarity + */ +typedef enum +{ + MD_SPI_CPOL_LOW = 0U, /**< Polarity hold low when spi-bus is idle */ + MD_SPI_CPOL_HIGH = 1U, /**< Polarity hold high when spi-bus is idle */ +} md_spi_cpol_t; + +/** + * @brief master selection + */ +typedef enum +{ + MD_SPI_MODE_SLAVER = 0U, /**< Slave mode */ + MD_SPI_MODE_MASTER = 1U, /**< Master mode */ +} md_spi_mode_t; + +/** + * @brief baud rate control + */ +typedef enum +{ + MD_SPI_BAUD_2 = 0U, /**< fpclk/2 */ + MD_SPI_BAUD_4 = 1U, /**< fpclk/4 */ + MD_SPI_BAUD_8 = 2U, /**< fpclk/8 */ + MD_SPI_BAUD_16 = 3U, /**< fpclk/16 */ + MD_SPI_BAUD_32 = 4U, /**< fpclk/32 */ + MD_SPI_BAUD_64 = 5U, /**< fpclk/64 */ + MD_SPI_BAUD_128 = 6U, /**< fpclk/128 */ + MD_SPI_BAUD_256 = 7U, /**< fpclk/256 */ +} md_md_spi_baud_t; + +/** + * @brief frame format + */ +typedef enum +{ + MD_SPI_FIRSTBIT_MSB = 0U, /**< MSB transmitted first */ + MD_SPI_FIRSTBIT_LSB = 1U, /**< LSB transmitted first */ +} md_spi_firstbit_t; + +/** + * @brief data frame format + */ +typedef enum +{ + MD_SPI_DATA_SIZE_8 = 0U, /**< 8-bit data frame format is selected for transmission/reception */ + MD_SPI_DATA_SIZE_16 = 1U, /**< 16-bit data frame format is selected for transmission/reception */ +} md_spi_datasize_t; + +/** + * @brief SPI direction definition + */ +typedef enum +{ + MD_SPI_DIRECTION_2LINES = 0U, /**< 2 lines */ + MD_SPI_DIRECTION_2LINES_RXONLY = 1U, /**< 2 lines only rx */ + MD_SPI_DIRECTION_1LINE = 2U, /**< 1 line */ + MD_SPI_DIRECTION_1LINE_RX = 3U, /**< 1 line only rx */ +} md_spi_direction_t; + +/** + * @brief SPI crc length definition + */ +typedef enum +{ + MD_SPI_FRAME_MOTOROLA = 0U, /**< SPI motorola mode */ + MD_SPI_FRAME_TI = 1U, /**< SPI TI mode */ +} md_spi_frame_t; + +/** + * @brief SPI init structure definition + */ +typedef struct +{ + SPI_I2S_TypeDef *SPIx; /**< SPI peripheral */ + md_spi_mode_t mode; /**< SPI mode */ + md_spi_direction_t dir; /**< SPI direction */ + md_spi_datasize_t data_size; /**< SPI data size */ + md_md_spi_baud_t baud; /**< SPI baudrate prescaler */ + md_spi_cpha_t phase; /**< SPI clock phase */ + md_spi_cpol_t polarity; /**< SPI clock polarity */ + md_spi_firstbit_t first_bit; /**< SPI first bit */ + type_func_t ss_en; /**< SPI ssm enable or disable */ + type_func_t crc_calc; /**< SPI crc calculation */ + md_spi_frame_t frame; /**< SPI frame format */ + uint16_t crc_poly; /**< SPI crc polynomial */ +} md_spi_init_t; +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @defgroup MD_SPI_Public_Functions SPI Public Functions + * @{ + */ +/** @defgroup MD_SPI_Public_Functions_Group2 CON1 + * @{ + */ +/** + * @brief Set spi duplex line simplex direction commumication. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_set_duplex_line_simplex(SPI_I2S_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_BIDEN_MSK); +} + +/** + * @brief Set spi simplex line duplex direction commumication. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_set_simplex_line_duplex(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_BIDEN_MSK); +} + +/** + * @brief Check if spi is Enable duplex line simplex direction commumication. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t md_spi_is_enable_duplex_line_simplex(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_BIDEN_MSK) != SPI_CON1_BIDEN_MSK); +} + +/** + * @brief Check if spi is Enable simplex line duplex direction commumication + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t md_spi_is_enable_simplex_line_duplex(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_BIDEN_MSK) == SPI_CON1_BIDEN_MSK); +} + +/** + * @brief Enable spi duplex line mode data transmit. + * @param SPIx: SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_simplex_line_tx(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_BIDOEN_MSK); +} + +/** + * @brief Enable spi duplex line mode data receive. + * @param SPIx: SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_simplex_line_rx(SPI_I2S_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_BIDOEN_MSK); +} + +/** + * @brief Check if spi is enable duplex line mode data transmit. + * @param SPIx: SPI Instance. + * @retval State: + * - 1: transmit + * - 0: receive + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_simplex_line_tx(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_BIDOEN_MSK) == SPI_CON1_BIDOEN_MSK); +} + +/** + * @brief Enable spi crc by hardware. + * @param SPIx: SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_crc_hardware(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_CRCEN_MSK); +} + +/** + * @brief Disable spi crc by hardware. + * @param SPIx: SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_crc_hardware(SPI_I2S_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_CRCEN_MSK); +} + +/** + * @brief Check if spi is enable crc by hardware. + * @param SPIx: SPI Instance. + * @retval State for 1 or 0. + */ +__STATIC_INLINE uint32_t md_spi_is_enable_crc_hardware(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_CRCEN_MSK) == SPI_CON1_CRCEN_MSK); +} + +/** + * @brief Enable spi next time transmit is crc. + * @param SPIx: SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_next_crc_transmit(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_NXTCRC_MSK); +} + +/** + * @brief Disable spi next time transmit is crc. + * @param SPIx: SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_next_crc_transmit(SPI_I2S_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_NXTCRC_MSK); +} + +/** + * @brief Check if spi is enable next time transmit is crc. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_next_crc_transmit(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_NXTCRC_MSK) == SPI_CON1_NXTCRC_MSK); +} + +/** + * @brief Enable spi 16 bytes commumication data . + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_16_byte_commumication(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_FLEN_MSK); +} + +/** + * @brief Enable spi 8 bytes commumication data . + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_8_byte_commumication(SPI_I2S_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_FLEN_MSK); +} + +/** + * @brief Check if spi is enable 16 bytes commumication data. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_16_byte_commumication(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_FLEN_MSK) == SPI_CON1_FLEN_MSK); +} + +/** + * @brief Check if spi is enable 8 bytes commumication data. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_8_byte_commumication(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_FLEN_MSK) != SPI_CON1_FLEN_MSK); +} + +/** + * @brief Enable spi only receive mode. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_recv_only(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_RXO_MSK); +} + +/** + * @brief Disable spi only receive mode. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_disable_recv_only(SPI_I2S_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_RXO_MSK); +} + +/** + * @brief Check if spi is enable only receive mode. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint8_t md_spi_is_enable_recv_only(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_RXO_MSK) == SPI_CON1_RXO_MSK); +} + +/** + * @brief Enable spi control slave device by software. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_control_slave(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_SSEN_MSK); +} + +/** + * @brief Disable spi control slave device by software. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_disable_control_slave(SPI_I2S_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_SSEN_MSK); +} + +/** + * @brief Check if spi is enable control slave device by software. + * @param SPIx: SPI Instance. + * @retval State for bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_control_slave(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_SSEN_MSK) == SPI_CON1_SSEN_MSK); +} + +/** + * @brief Enable spi chip select output high. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_ss_output_high(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_SSOUT_MSK); +} + +/** + * @brief Enable spi chip select output low. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_ss_output_low(SPI_I2S_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_SSOUT_MSK); +} + +/** + * @brief Check if spi is enable chip select output high. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_ss_output_high(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_SSOUT_MSK) == SPI_CON1_SSOUT_MSK); +} + +/** + * @brief Enable spi data first transmit MSB. + * @param SPIx: SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_first_transmit_msb(SPI_I2S_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_LSBFST_MSK); +} + +/** + * @brief Enable spi data first transmit LSB. + * @param SPIx: SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_first_transmit_lsb(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_LSBFST_MSK); +} + +/** + * @brief Check if spi is enable data first transmit MSB. + * @param SPIx: SPI Instance. + * @retval State: + * - 1: LSB first + * - 0: MSB first + */ +__STATIC_INLINE uint32_t md_spi_is_enable_first_transmit_msb(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_LSBFST_MSK) != SPI_CON1_LSBFST_MSK); +} + +/** + * @brief Enable SPI module. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_SPIEN_MSK); +} + +/** + * @brief Disable SPI module. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_disable(SPI_I2S_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_SPIEN_MSK); +} + +/** + * @brief Check if is enable spi. + * @param SPIx: SPI Instance. + * @retval State for bit (1 or 0) + */ +__STATIC_INLINE uint32_t md_spi_is_enable(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_SPIEN_MSK) == SPI_CON1_SPIEN_MSK); +} + +/** + * @brief Set spi commumication baudrate. + * @param SPIx: SPI Instance. + * @param baud: specific commumication rate @see md_spi_baud_t. + * @retval None. + */ +__STATIC_INLINE void md_spi_set_commumication_baud(SPI_I2S_TypeDef *SPIx, md_md_spi_baud_t baud) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_BAUD_MSK, baud << SPI_CON1_BAUD_POSS); +} + +/** + * @brief Get spi commumication baudrate. + * @param SPIx: SPI Instance. + * @retval specific commumication rate @see md_spi_baud_t. + */ +__STATIC_INLINE uint32_t md_spi_get_commumication_baud(SPI_I2S_TypeDef *SPIx) +{ + return READ_BITS(SPIx->CON1, SPI_CON1_BAUD_MSK, SPI_CON1_BAUD_POSS); +} + +/** + * @brief Enable spi master mode. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_master_mode(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_MSTREN_MSK); +} + +/** + * @brief Enable spi slave mode. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_slave_mode(SPI_I2S_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_MSTREN_MSK); +} +/** + * @brief Check if spi is enable master mode. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_master_mode(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_MSTREN_MSK) == SPI_CON1_MSTREN_MSK); +} + +/** + * @brief Enable spi sck bus keep high polarity in idle mode. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_sck_high_idle(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_CPOL_MSK); +} + +/** + * @brief Enable spi sck bus keep low polarity in idle mode. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_sck_low_idle(SPI_I2S_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_CPOL_MSK); +} + +/** + * @brief Check if spi is enable sck keep high in idle. + * @param SPIx: SPI Instance. + * @retval State: + * - 1: SCK high in idle + * - 0: SCK low in idle + */ +__STATIC_INLINE uint32_t md_spi_is_enable_sck_high_idle(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_CPOL_MSK) == SPI_CON1_CPOL_MSK); +} + +/** + * @brief Enable spi sample data in seconde time edge. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_sample_sec_edge(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_CPHA_MSK); +} + +/** + * @param SPIx: SPI Instance. + * @brief Enable spi sample data in first time edge. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_sample_first_edge(SPI_I2S_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_CPHA_MSK); +} + +/** + * @brief Check is spi is enable sample data in seconde time edge. + * @param SPIx: SPI Instance. + * @retval State: + * - 1: Sample in second edge + * - 0: Sample in first edge + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_sample_sec_edge(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_CPHA_MSK) == SPI_CON1_CPHA_MSK); +} +/** + * @} + */ +/** @defgroup MD_SPI_Public_Functions_Group3 CON2 + * @{ + */ +/** + * @brief Set spi receive fifo threshold. + * @param SPIx: SPI Instance. + * @param rxth: rx fifo threshold(1, 4, 8, 11) + * @retval None. + */ +__STATIC_INLINE void md_spi_set_rxfifo_threshold(SPI_I2S_TypeDef *SPIx, uint8_t rxth) +{ + MODIFY_REG(SPIx->CON2, SPI_CON2_RXFTH_MSK, (rxth << SPI_CON2_RXFTH_POSS)); +} + +/** + * @brief Get spi receive fifo threshold. + * @param SPIx: SPI Instance. + * @retval Rx fifo threshold. + */ +__STATIC_INLINE uint8_t md_spi_get_rxfifo_threshold(SPI_I2S_TypeDef *SPIx) +{ + return READ_BITS(SPIx->CON2, SPI_CON2_RXFTH_MSK, SPI_CON2_RXFTH_POSS); +} + +/** + * @brief Set spi transmit fifo threshold. + * @param SPIx: SPI Instance. + * @param rxth: rx fifo threshold(1, 4, 8, 11) + * @retval None. + */ +__STATIC_INLINE void md_spi_set_txfifo_threshold(SPI_I2S_TypeDef *SPIx, uint8_t rxth) +{ + MODIFY_REG(SPIx->CON2, SPI_CON2_TXFTH_MSK, (rxth << SPI_CON2_TXFTH_POSS)); +} + +/** + * @brief Get spi transmit fifo threshold. + * @param SPIx: SPI Instance. + * @retval TX fifo threshold. + */ +__STATIC_INLINE uint8_t md_spi_get_txfifo_threshold(SPI_I2S_TypeDef *SPIx) +{ + return READ_BITS(SPIx->CON2, SPI_CON2_TXFTH_MSK, SPI_CON2_TXFTH_POSS); +} + +/** + * @brief Set MOTO TI mode. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_set_moto_mode(SPI_I2S_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON2, SPI_CON2_FRF_MSK); +} + +/** + * @brief Set MOTO SPI mode. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_set_ti_mode(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON2, SPI_CON2_FRF_MSK); +} + +/** + * @brief Get spi mode. + * @param SPIx: SPI Instance. + * @retval SPI mode(0: MOTO 1: TI). + */ +__STATIC_INLINE uint8_t md_spi_get_mode(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON2, SPI_CON2_FRF_MSK) == SPI_CON2_FRF_MSK); +} + +/** + * @brief Produce spi clock(master mode). + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_nss_pulse(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON2, SPI_CON2_NSSP_MSK); +} + +/** + * @brief Stop spi clock(master mode). + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_disable_nss_pulse(SPI_I2S_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON2, SPI_CON2_NSSP_MSK); +} + +/** + * @brief Get spi clock(master mode). + * @param SPIx: SPI Instance. + * @retval SPI mode(0: CLK Disable 1: CLK Enable). + */ +__STATIC_INLINE uint8_t md_spi_is_enabled_nss_pulse(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON2, SPI_CON2_NSSP_MSK) == SPI_CON2_NSSP_MSK); +} + +/** + * @brief Enable nss output clock function. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_nss_output(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON2, SPI_CON2_NSSOE_MSK); +} + +/** + * @brief Disable nss output clock function. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_disable_nss_output(SPI_I2S_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON2, SPI_CON2_NSSOE_MSK); +} + +/** + * @brief Get nss output clock function.. + * @param SPIx: SPI Instance. + * @retval nss mode(0: Output Disable 1: Output Enable). + */ +__STATIC_INLINE uint8_t md_spi_is_enabled_nss_output(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON2, SPI_CON2_NSSOE_MSK) == SPI_CON2_NSSOE_MSK); +} + +/** + * @brief Enable spi tx_dma function. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_txdma(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON2, SPI_CON2_TXDMA_MSK); +} + +/** + * @brief Disable spi error interrupt. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_disable_txdma(SPI_I2S_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON2, SPI_CON2_TXDMA_MSK); +} + +/** + * @brief Check if spi is enable txdma. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_txdma(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON2, SPI_CON2_TXDMA_MSK) == SPI_CON2_TXDMA_MSK); +} + +/** + * @brief Enable spi rx_dma function. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_enable_rxdma(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON2, SPI_CON2_RXDMA_MSK); +} + +/** + * @brief Disable spi rx_dma function. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_disable_rxdma(SPI_I2S_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON2, SPI_CON2_RXDMA_MSK); +} + +/** + * @brief Check if spi is enable rxdma. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_rxdma(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON2, SPI_CON2_RXDMA_MSK) == SPI_CON2_RXDMA_MSK); +} +/** + * @} + */ +/** @defgroup MD_SPI_Public_Functions_Group4 STAT + * @{ + */ +/** + * @brief Get spi rxfifo value. + * @param SPIx: SPI Instance. + * @retval rxfifo threshold. + */ +__STATIC_INLINE uint32_t md_spi_get_rxfifo_value(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BITS(SPIx->STAT, SPI_STAT_RXFLV_MSK, SPI_STAT_RXFLV_POSS)); +} + +/** + * @brief Get spi txfifo value. + * @param SPIx: SPI Instance. + * @retval txfifo threshold. + */ +__STATIC_INLINE uint32_t md_spi_get_txfifo_value(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BITS(SPIx->STAT, SPI_STAT_TXFLV_MSK, SPI_STAT_TXFLV_POSS)); +} + +/** + * @brief Get spi busy flag. + * @param SPIx: SPI Instance. + * @retval State for bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_busy(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_BUSY_MSK) == SPI_STAT_BUSY_MSK); +} + +/** + * @brief Get spi rx threshold flag. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rxth(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_RXTH_MSK) == SPI_STAT_RXTH_MSK); +} + +/** + * @brief Get spi rx under flow flag. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_get_flag_rxud(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_RXUD_MSK) == SPI_STAT_RXUD_MSK); +} + +/** + * @brief Get spi rx over flow flag. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_get_flag_rxov(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_RXOV_MSK) == SPI_STAT_RXOV_MSK); +} + +/** + * @brief Get spi rx buffer full flag. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rxf(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_RXF_MSK) == SPI_STAT_RXF_MSK); +} + +/** + * @brief Get spi rx buffer not empty flag. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rxne(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_RXNE_MSK) == SPI_STAT_RXNE_MSK); +} + +/** + * @brief Get spi tx threshold flag. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_txth(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_TXTH_MSK) == SPI_STAT_TXTH_MSK); +} + +/** + * @brief Get spi tx under flow flag. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_get_flag_txud(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_TXUD_MSK) == SPI_STAT_TXUD_MSK); +} + +/** + * @brief Get spi tx over flow flag. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_get_flag_txov(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_TXOV_MSK) == SPI_STAT_TXOV_MSK); +} + +/** + * @brief Get spi tx buffer full flag. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_txf(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_TXF_MSK) == SPI_STAT_TXF_MSK); +} + +/** + * @brief Get spi tx buffer empty flag. + * @param SPIx: SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_txe(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->STAT, SPI_STAT_TXE_MSK) == SPI_STAT_TXE_MSK); +} +/** + * @} + */ +/** @defgroup MD_SPI_Public_Functions_Group5 DATA + * @{ + */ +/** + * @brief Set spi data register value. + * @param SPIx: SPI Instance. + * @param data: tx data. + * @retval None. + */ +__STATIC_INLINE void md_spi_set_data_reg(SPI_I2S_TypeDef *SPIx, uint32_t data) +{ + WRITE_REG(SPIx->DATA, data); +} + +/** + * @brief Get spi data register value. + * @param SPIx: SPI Instance. + * @retval data: value for data register. + */ +__STATIC_INLINE uint32_t md_spi_get_data_reg_value(SPI_I2S_TypeDef *SPIx) +{ + return READ_REG(SPIx->DATA); +} +/** + * @} + */ +/** @defgroup MD_SPI_Public_Functions_Group6 CRCPOLY + * @{ + */ +/** + * @brief Set spi crc register value. + * @param SPIx: SPI Instance. + * @param data: crc data. + * @retval None. + */ +__STATIC_INLINE void md_spi_set_crc_reg_value(SPI_I2S_TypeDef *SPIx, uint32_t data) +{ + WRITE_REG(SPIx->CRCPOLY, data); +} + +/** + * @brief Get spi crc register value. + * @param SPIx: SPI Instance. + * @retval data: value for crc register. + */ +__STATIC_INLINE uint32_t md_spi_get_crc_reg_value(SPI_I2S_TypeDef *SPIx) +{ + return READ_REG(SPIx->CRCPOLY); +} +/** + * @} + */ +/** @defgroup MD_SPI_Public_Functions_Group7 RXCRC + * @{ + */ +/** + * @brief Get spi receive data crc value. + * @param SPIx: SPI Instance. + * @retval data: value for receive crc. + */ +__STATIC_INLINE uint32_t md_spi_get_rx_data_crc(SPI_I2S_TypeDef *SPIx) +{ + return READ_REG(SPIx->RXCRC); +} +/** + * @} + */ +/** @defgroup MD_SPI_Public_Functions_Group8 TXCRC + * @{ + */ +/** + * @brief Get spi transmit data crc value. + * @param SPIx: SPI Instance. + * @retval data: value for transmit crc. + */ +__STATIC_INLINE uint32_t md_spi_get_tx_data_crc(SPI_I2S_TypeDef *SPIx) +{ + return READ_REG(SPIx->TXCRC); +} +/** + * @} + */ +/** @defgroup MD_SPI_Public_Functions_Group9 I2SCFG + * @{ + */ +/** + * @brief Set spi mode. + * @param SPIx: SPI Instance. + * @retval None. + */ +__STATIC_INLINE void md_spi_chose_spi(SPI_I2S_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SMOD_MSK); +} + +/** + * @brief Check is set spi mode. + * @param SPIx: SPI Instance. + * @retval State: + * - 1: SPI mode + * - 0: I2S mode + */ +__STATIC_INLINE uint32_t md_spi_is_set_spi_mode(SPI_I2S_TypeDef *SPIx) +{ + return !(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SMOD_MSK) == SPI_I2SCFG_I2SMOD_MSK); +} +/** + * @} + */ +/** @defgroup MD_SPI_Public_Functions_Group10 IER + * @{ + */ +/** + * @brief Enable spi frame error interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_fre(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_FRE_MSK); +} + +/** + * @brief Enable spi mode fail interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_modf(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_MODF_MSK); +} + +/** + * @brief Enable spi crc error interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_crcerr(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_CRCERR_MSK); +} + +/** + * @brief Enable spi rx threshold interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_rxth(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXTH_MSK); +} + +/** + * @brief Enable spi rx under flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_rxud(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXUD_MSK); +} + + +/** + * @brief Enable spi rx over flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_rxov(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXOV_MSK); +} + +/** + * @brief Enable spi rx full interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_rxf(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXF_MSK); +} + +/** + * @brief Enable spi rx not empty interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_rxne(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXNE_MSK); +} + +/** + * @brief Enable spi tx threshold interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_txth(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXTH_MSK); +} + +/** + * @brief Enable spi tx under flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_txud(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXUD_MSK); +} + +/** + * @brief Enable spi tx over flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_txov(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXOV_MSK); +} + +/** + * @brief Enable spi tx empty interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_enable_it_txe(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXE_MSK); +} +/** + * @} + */ +/** @defgroup MD_SPI_Public_Functions_Group11 IDR + * @{ + */ +/** + * @brief Disable spi frame error interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_fre(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_FRE_MSK); +} + +/** + * @brief Disable spi mode fail interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_modf(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_MODF_MSK); +} + +/** + * @brief Disable spi crc error interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_crcerr(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_CRCERR_MSK); +} + +/** + * @brief Disable spi rx threshold interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_rxth(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_RXTH_MSK); +} + +/** + * @brief Disable spi rx under flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_rxud(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_RXUD_MSK); +} + +/** + * @brief Disable spi rx over flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_rxov(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_RXOV_MSK); +} + +/** + * @brief Disable spi rx full interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_rxf(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_RXF_MSK); +} + +/** + * @brief Disable spi rx not empty interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_rxne(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_RXNE_MSK); +} + +/** + * @brief Disable spi tx threshold interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_txth(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_TXTH_MSK); +} + +/** + * @brief Disable spi tx under flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_txud(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_TXUD_MSK); +} + +/** + * @brief Disable spi tx over flow interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_txov(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_TXOV_MSK); +} + +/** + * @brief Disable spi tx empty interrupt. + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void md_spi_disable_it_txe(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_TXE_MSK); +} +/** + * @} + */ +/** @defgroup MD_SPI_Public_Functions_Group12 IVS + * @{ + */ +/** + * @brief Check if the frame error interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_it_fre(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_FRE_MSK) == (SPI_IVS_FRE_MSK)); +} + +/** + * @brief Check if the mode fail interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_it_modf(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_MODF_MSK) == (SPI_IVS_MODF_MSK)); +} + +/** + * @brief Check if the crc error interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_it_crcerr(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_CRCERR_MSK) == (SPI_IVS_CRCERR_MSK)); +} + +/** + * @brief Check if the rx threshold interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_it_rxth(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_RXTH_MSK) == (SPI_IVS_RXTH_MSK)); +} + +/** + * @brief Check if the rx under flow interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_it_rxud(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_RXUD_MSK) == (SPI_IVS_RXUD_MSK)); +} + +/** + * @brief Check if the rx over flow interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_it_rxov(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_RXOV_MSK) == (SPI_IVS_RXOV_MSK)); +} + +/** + * @brief Check if the rx full interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_it_rxf(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_RXF_MSK) == (SPI_IVS_RXF_MSK)); +} + +/** + * @brief Check if the rx not empty interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_it_rxne(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_RXNE_MSK) == (SPI_IVS_RXNE_MSK)); +} + +/** + * @brief Check if the tx threshold interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_it_txth(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_TXTH_MSK) == (SPI_IVS_TXTH_MSK)); +} + +/** + * @brief Check if the tx under flow interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_it_txud(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_TXUD_MSK) == (SPI_IVS_TXUD_MSK)); +} + +/** + * @brief Check if the tx over flow interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_it_txov(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_TXOV_MSK) == (SPI_IVS_TXOV_MSK)); +} + +/** + * @brief Check if the tx empty interrupt is enabled or disabled. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_it_txe(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_TXE_MSK) == (SPI_IVS_TXE_MSK)); +} +/** + * @} + */ +/** @defgroup MD_SPI_Public_Functions_Group13 RIF + * @{ + */ +/** + * @brief Get frame error interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_fre(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_FRE_MSK) == (SPI_RIF_FRE_MSK)); +} + +/** + * @brief Get mode fail interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_modf(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_MODF_MSK) == (SPI_RIF_MODF_MSK)); +} + +/** + * @brief Get crc error interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_crcerr(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_CRCERR_MSK) == (SPI_RIF_CRCERR_MSK)); +} + +/** + * @brief Get rx threshold interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_rxth(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_RXTH_MSK) == (SPI_RIF_RXTH_MSK)); +} + +/** + * @brief Get rx under flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_rxud(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_RXUD_MSK) == (SPI_RIF_RXUD_MSK)); +} + +/** + * @brief Get rx over flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_rxov(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_RXOV_MSK) == (SPI_RIF_RXOV_MSK)); +} + +/** + * @brief Get rx full interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_rxf(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_RXF_MSK) == (SPI_RIF_RXF_MSK)); +} + +/** + * @brief Get rx not empty interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_rxne(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_RXNE_MSK) == (SPI_RIF_RXNE_MSK)); +} + +/** + * @brief Get tx threshold interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_txth(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_TXTH_MSK) == (SPI_RIF_TXTH_MSK)); +} + +/** + * @brief Get tx under flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_txud(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_TXUD_MSK) == (SPI_RIF_TXUD_MSK)); +} + +/** + * @brief Get tx over flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_txov(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_TXOV_MSK) == (SPI_RIF_TXOV_MSK)); +} + +/** + * @brief Get tx empty interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_active_it_txe(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->RIF, SPI_RIF_TXE_MSK) == (SPI_RIF_TXE_MSK)); +} +/** + * @} + */ +/** @defgroup MD_SPI_Public_Functions_Group14 IFM + * @{ + */ +/** + * @brief Mask frame error interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_mask_it_fre(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_FRE_MSK) == SPI_IFM_FRE_MSK); +} + +/** + * @brief Mask mode fail interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_mask_it_modf(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_MODF_MSK) == SPI_IFM_MODF_MSK); +} + +/** + * @brief Mask crc error interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_mask_it_crcerr(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_CRCERR_MSK) == SPI_IFM_CRCERR_MSK); +} + +/** + * @brief Mask rx threshold interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_mask_it_rxth(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_RXTH_MSK) == SPI_IFM_RXTH_MSK); +} + +/** + * @brief Mask rx under flow interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_mask_it_rxud(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_RXUD_MSK) == SPI_IFM_RXUD_MSK); +} + +/** + * @brief Mask rx over flow interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_mask_it_rxov(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_RXOV_MSK) == SPI_IFM_RXOV_MSK); +} + +/** + * @brief Mask rx full interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_mask_it_rxf(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_RXF_MSK) == SPI_IFM_RXF_MSK); +} + +/** + * @brief Mask rx not empty interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_mask_it_rxne(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_RXNE_MSK) == SPI_IFM_RXNE_MSK); +} + +/** + * @brief Mask tx threshold interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_mask_it_txth(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_TXTH_MSK) == SPI_IFM_TXTH_MSK); +} + +/** + * @brief Mask tx under flow interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_mask_it_txud(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_TXUD_MSK) == SPI_IFM_TXUD_MSK); +} + +/** + * @brief Mask tx over flow interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_mask_it_txov(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_TXOV_MSK) == SPI_IFM_TXOV_MSK); +} + +/** + * @brief Mask tx empty interrupt. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_mask_it_txe(SPI_I2S_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IFM, SPI_IFM_TXE_MSK) == SPI_IFM_TXE_MSK); +} +/** + * @} + */ +/** @defgroup MD_SPI_Public_Functions_Group15 ICR + * @{ + */ +/** + * @brief Clear frame error interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_flag_fre(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_FRE_MSK); +} + +/** + * @brief Clear mode fail interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_flag_modf(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_MODF_MSK); +} + +/** + * @brief Clear crc error interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_flag_crcerr(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_CRCERR_MSK); +} + +/** + * @brief Clear rx under flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_flag_rxth(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_RXTH_MSK); +} + +/** + * @brief Clear rx under flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_flag_rxud(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_RXUD_MSK); +} + +/** + * @brief Clear rx over flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_flag_rxov(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_RXOV_MSK); +} + +/** + * @brief Clear rx full interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_flag_rxf(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_RXF_MSK); +} + +/** + * @brief Clear rx not empty interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_flag_rxne(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_RXNE_MSK); +} + +/** + * @brief Clear tx under flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_flag_txth(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_TXTH_MSK); +} + +/** + * @brief Clear tx under flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_flag_txud(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_TXUD_MSK); +} + +/** + * @brief Clear tx over flow interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_flag_txov(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_TXOV_MSK); +} + +/** + * @brief Clear tx empty interrupt flag. + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_flag_txe(SPI_I2S_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_TXE_MSK); +} +/** + * @} + */ + +/** @defgroup MD_SPI_Public_Functions_Group1 Initialization + * @{ + */ +extern void md_spi_reset(SPI_I2S_TypeDef *SPIx); +extern md_status_t md_spi_init(md_spi_init_t *init); +extern void md_spi_struct_init(md_spi_init_t *init); +extern int32_t md_spi_send_byte_fast(md_spi_init_t *hperh, uint8_t data); +extern uint8_t md_spi_recv_byte_fast(md_spi_init_t *hperh, int *status); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __MD_SPI_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_syscfg.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_syscfg.h new file mode 100644 index 0000000000..3c67b35ef1 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_syscfg.h @@ -0,0 +1,706 @@ +/********************************************************************************** + * + * @file md_syscfg.h + * @brief SYSCFG module driver. + * + * @date 13 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 13 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __MD_SYSCFG_H__ +#define __MD_SYSCFG_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_utils.h" + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Variables -------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_SYSCFG SYSCFG + * @brief SYSCFG module driver + * @{ + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** @defgroup MD_SYSCFG_Public_Macros SYSCFG Public Macros + * @{ + */ +#define MD_SYSCFG_LOCK() (WRITE_REG(SYSCFG->PROT, 0x0U)) +#define MD_SYSCFG_UNLOCK() (WRITE_REG(SYSCFG->PROT, 0x55AA6996U)) +#define MD_GET_SYSCFG_LOCK() (READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK)) + +/* Exported Types ------------------------------------------------------------ */ + +/** + * @brief PIS IO Select + */ +typedef enum +{ + MD_SYSCFG_PISIOCFG_PA = 0x0U, + MD_SYSCFG_PISIOCFG_PB = 0x1U, + MD_SYSCFG_PISIOCFG_PC = 0x2U, + MD_SYSCFG_PISIOCFG_PD = 0x3U, +} md_syscfg_pisiocfg_t; + +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @defgroup MD_SYSCFG_Public_Functions SYSCFG Public Functions + * @{ + */ +/** @defgroup MD_SYSCFG_Public_Functions_Group2 BTADDR + * @{ + */ +/** + * @brief Set cpu boot address + * @param addr: cpu boot address + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_cpu_boot_addr(uint32_t addr) +{ + WRITE_REG(SYSCFG->BTADDR, addr); +} + +/** + * @} + */ + +/** @defgroup MD_SYSCFG_Public_Functions_Group3 TBKCFG + * @{ + */ +/** + * @brief Enable clock safety event as the timer brake source + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_cssbke(void) +{ + SET_BIT(SYSCFG->TBKCFG, SYSCFG_TBKCFG_CCSBKE_MSK); +} + +/** + * @brief Disable clock safety event as the timer brake source + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_cssbke(void) +{ + CLEAR_BIT(SYSCFG->TBKCFG, SYSCFG_TBKCFG_CCSBKE_MSK); +} + +/** + * @brief Whether clock safety event is the timer brake source + * @retval 1-enable, 0-disable + */ +__STATIC_INLINE uint32_t md_syscfg_is_enable_cssbke(void) +{ + return READ_BITS(SYSCFG->TBKCFG, SYSCFG_TBKCFG_CCSBKE_MSK, SYSCFG_TBKCFG_CCSBKE_POS); +} + +/** + * @brief Enable LVD event as the timer brake source + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_lvdbke(void) +{ + SET_BIT(SYSCFG->TBKCFG, SYSCFG_TBKCFG_LVDBKE_MSK); +} + +/** + * @brief Disable LVD event as the timer brake source + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_lvdbke(void) +{ + CLEAR_BIT(SYSCFG->TBKCFG, SYSCFG_TBKCFG_LVDBKE_MSK); +} + +/** + * @brief Whether LVD event is the timer brake source + * @retval 1-enable, 0-disable + */ +__STATIC_INLINE uint32_t md_syscfg_is_enable_lvdbke(void) +{ + return READ_BITS(SYSCFG->TBKCFG, SYSCFG_TBKCFG_LVDBKE_MSK, SYSCFG_TBKCFG_LVDBKE_POS); +} + +/** + * @brief Enable CPU lock event as the timer brake source + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_clubke(void) +{ + SET_BIT(SYSCFG->TBKCFG, SYSCFG_TBKCFG_CLUBKE_MSK); +} + +/** + * @brief Disable CPU lock as the timer brake source + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_clubke(void) +{ + CLEAR_BIT(SYSCFG->TBKCFG, SYSCFG_TBKCFG_CLUBKE_MSK); +} + +/** + * @brief Whether CPU lock is the timer brake source + * @retval 1-enable, 0-disable + */ +__STATIC_INLINE uint32_t md_syscfg_is_enable_clubke(void) +{ + return READ_BITS(SYSCFG->TBKCFG, SYSCFG_TBKCFG_CLUBKE_MSK, SYSCFG_TBKCFG_CLUBKE_POS); +} + +/** + * @brief Select PIS producer IO15 + * @note + * @param SYSCFGx: SYSCFG Instance + * @param io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + * @retval None + */ +__STATIC_INLINE void md_syscfg_pisiocfg_io15sel(SYSCFG_TypeDef *SYSCFGx, md_syscfg_pisiocfg_t io) +{ + MODIFY_REG(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO15SEL_MSK, io << SYSCFG_PISIOCFG_IO15SEL_POSS); +} + +/** + * @brief Get PIS producer IO15 + * @note + * @param SYSCFGx: SYSCFG Instance + * @retval io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + */ +__STATIC_INLINE uint32_t md_syscfg_get_pisiocfg_io15sel(SYSCFG_TypeDef *SYSCFGx) +{ + return (READ_BIT(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO15SEL_MSK)); +} + +/** + * @brief Select PIS producer IO14 + * @note + * @param SYSCFGx: SYSCFG Instance + * @param io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + * @retval None + */ +__STATIC_INLINE void md_syscfg_pisiocfg_io14sel(SYSCFG_TypeDef *SYSCFGx, md_syscfg_pisiocfg_t io) +{ + MODIFY_REG(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO14SEL_MSK, io << SYSCFG_PISIOCFG_IO14SEL_POSS); +} + +/** + * @brief Get PIS producer IO14 + * @note + * @param SYSCFGx: SYSCFG Instance + * @retval io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + */ +__STATIC_INLINE uint32_t md_syscfg_get_pisiocfg_io14sel(SYSCFG_TypeDef *SYSCFGx) +{ + return (READ_BIT(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO14SEL_MSK)); +} + +/** + * @brief Select PIS producer IO13 + * @note + * @param SYSCFGx: SYSCFG Instance + * @param io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + * @retval None + */ +__STATIC_INLINE void md_syscfg_pisiocfg_io13sel(SYSCFG_TypeDef *SYSCFGx, md_syscfg_pisiocfg_t io) +{ + MODIFY_REG(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO13SEL_MSK, io << SYSCFG_PISIOCFG_IO13SEL_POSS); +} + +/** + * @brief Get PIS producer IO13 + * @note + * @param SYSCFGx: SYSCFG Instance + * @retval io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + */ +__STATIC_INLINE uint32_t md_syscfg_get_pisiocfg_io13sel(SYSCFG_TypeDef *SYSCFGx) +{ + return (READ_BIT(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO13SEL_MSK)); +} + +/** + * @brief Select PIS producer IO12 + * @note + * @param SYSCFGx: SYSCFG Instance + * @param io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + * @retval None + */ +__STATIC_INLINE void md_syscfg_pisiocfg_io12sel(SYSCFG_TypeDef *SYSCFGx, md_syscfg_pisiocfg_t io) +{ + MODIFY_REG(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO12SEL_MSK, io << SYSCFG_PISIOCFG_IO12SEL_POSS); +} + +/** + * @brief Get PIS producer IO12 + * @note + * @param SYSCFGx: SYSCFG Instance + * @retval io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + */ +__STATIC_INLINE uint32_t md_syscfg_get_pisiocfg_io12sel(SYSCFG_TypeDef *SYSCFGx) +{ + return (READ_BIT(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO12SEL_MSK)); +} + +/** + * @brief Select PIS producer IO11 + * @note + * @param SYSCFGx: SYSCFG Instance + * @param io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + * @retval None + */ +__STATIC_INLINE void md_syscfg_pisiocfg_io11sel(SYSCFG_TypeDef *SYSCFGx, md_syscfg_pisiocfg_t io) +{ + MODIFY_REG(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO11SEL_MSK, io << SYSCFG_PISIOCFG_IO11SEL_POSS); +} + +/** + * @brief Get PIS producer IO11 + * @note + * @param SYSCFGx: SYSCFG Instance + * @retval io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + */ +__STATIC_INLINE uint32_t md_syscfg_get_pisiocfg_io11sel(SYSCFG_TypeDef *SYSCFGx) +{ + return (READ_BIT(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO11SEL_MSK)); +} + +/** + * @brief Select PIS producer IO10 + * @note + * @param SYSCFGx: SYSCFG Instance + * @param io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + * @retval None + */ +__STATIC_INLINE void md_syscfg_pisiocfg_io10sel(SYSCFG_TypeDef *SYSCFGx, md_syscfg_pisiocfg_t io) +{ + MODIFY_REG(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO10SEL_MSK, io << SYSCFG_PISIOCFG_IO10SEL_POSS); +} + +/** + * @brief Get PIS producer IO10 + * @note + * @param SYSCFGx: SYSCFG Instance + * @retval io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + */ +__STATIC_INLINE uint32_t md_syscfg_get_pisiocfg_io10sel(SYSCFG_TypeDef *SYSCFGx) +{ + return (READ_BIT(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO10SEL_MSK)); +} + +/** + * @brief Select PIS producer IO9 + * @note + * @param SYSCFGx: SYSCFG Instance + * @param io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + * @retval None + */ +__STATIC_INLINE void md_syscfg_pisiocfg_io9sel(SYSCFG_TypeDef *SYSCFGx, md_syscfg_pisiocfg_t io) +{ + MODIFY_REG(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO9SEL_MSK, io << SYSCFG_PISIOCFG_IO9SEL_POSS); +} + +/** + * @brief Get PIS producer IO9 + * @note + * @param SYSCFGx: SYSCFG Instance + * @retval io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + */ +__STATIC_INLINE uint32_t md_syscfg_get_pisiocfg_io9sel(SYSCFG_TypeDef *SYSCFGx) +{ + return (READ_BIT(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO9SEL_MSK)); +} + +/** + * @brief Select PIS producer IO8 + * @note + * @param SYSCFGx: SYSCFG Instance + * @param io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + * @retval None + */ +__STATIC_INLINE void md_syscfg_pisiocfg_io8sel(SYSCFG_TypeDef *SYSCFGx, md_syscfg_pisiocfg_t io) +{ + MODIFY_REG(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO8SEL_MSK, io << SYSCFG_PISIOCFG_IO8SEL_POSS); +} + +/** + * @brief Get PIS producer IO8 + * @note + * @param SYSCFGx: SYSCFG Instance + * @retval io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + */ +__STATIC_INLINE uint32_t md_syscfg_get_pisiocfg_io8sel(SYSCFG_TypeDef *SYSCFGx) +{ + return (READ_BIT(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO8SEL_MSK)); +} + +/** + * @brief Select PIS producer IO7 + * @note + * @param SYSCFGx: SYSCFG Instance + * @param io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + * @retval None + */ +__STATIC_INLINE void md_syscfg_pisiocfg_io7sel(SYSCFG_TypeDef *SYSCFGx, md_syscfg_pisiocfg_t io) +{ + MODIFY_REG(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO7SEL_MSK, io << SYSCFG_PISIOCFG_IO7SEL_POSS); +} + +/** + * @brief Get PIS producer IO7 + * @note + * @param SYSCFGx: SYSCFG Instance + * @retval io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + */ +__STATIC_INLINE uint32_t md_syscfg_get_pisiocfg_io7sel(SYSCFG_TypeDef *SYSCFGx) +{ + return (READ_BIT(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO7SEL_MSK)); +} + +/** + * @brief Select PIS producer IO6 + * @note + * @param SYSCFGx: SYSCFG Instance + * @param io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + * @retval None + */ +__STATIC_INLINE void md_syscfg_pisiocfg_io6sel(SYSCFG_TypeDef *SYSCFGx, md_syscfg_pisiocfg_t io) +{ + MODIFY_REG(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO6SEL_MSK, io << SYSCFG_PISIOCFG_IO6SEL_POSS); +} + +/** + * @brief Get PIS producer IO6 + * @note + * @param SYSCFGx: SYSCFG Instance + * @retval io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + */ +__STATIC_INLINE uint32_t md_syscfg_get_pisiocfg_io6sel(SYSCFG_TypeDef *SYSCFGx) +{ + return (READ_BIT(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO6SEL_MSK)); +} + +/** + * @brief Select PIS producer IO5 + * @note + * @param SYSCFGx: SYSCFG Instance + * @param io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + * @retval None + */ +__STATIC_INLINE void md_syscfg_pisiocfg_io5sel(SYSCFG_TypeDef *SYSCFGx, md_syscfg_pisiocfg_t io) +{ + MODIFY_REG(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO5SEL_MSK, io << SYSCFG_PISIOCFG_IO5SEL_POSS); +} + +/** + * @brief Get PIS producer IO5 + * @note + * @param SYSCFGx: SYSCFG Instance + * @retval io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + */ +__STATIC_INLINE uint32_t md_syscfg_get_pisiocfg_io5sel(SYSCFG_TypeDef *SYSCFGx) +{ + return (READ_BIT(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO5SEL_MSK)); +} + +/** + * @brief Select PIS producer IO4 + * @note + * @param SYSCFGx: SYSCFG Instance + * @param io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + * @retval None + */ +__STATIC_INLINE void md_syscfg_pisiocfg_io4sel(SYSCFG_TypeDef *SYSCFGx, md_syscfg_pisiocfg_t io) +{ + MODIFY_REG(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO4SEL_MSK, io << SYSCFG_PISIOCFG_IO4SEL_POSS); +} + +/** + * @brief Get PIS producer IO4 + * @note + * @param SYSCFGx: SYSCFG Instance + * @retval io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + */ +__STATIC_INLINE uint32_t md_syscfg_get_pisiocfg_io4sel(SYSCFG_TypeDef *SYSCFGx) +{ + return (READ_BIT(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO4SEL_MSK)); +} + +/** + * @brief Select PIS producer IO3 + * @note + * @param SYSCFGx: SYSCFG Instance + * @param io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + * @retval None + */ +__STATIC_INLINE void md_syscfg_pisiocfg_io3sel(SYSCFG_TypeDef *SYSCFGx, md_syscfg_pisiocfg_t io) +{ + MODIFY_REG(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO3SEL_MSK, io << SYSCFG_PISIOCFG_IO3SEL_POSS); +} + +/** + * @brief Get PIS producer IO3 + * @note + * @param SYSCFGx: SYSCFG Instance + * @retval io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + */ +__STATIC_INLINE uint32_t md_syscfg_get_pisiocfg_io3sel(SYSCFG_TypeDef *SYSCFGx) +{ + return (READ_BIT(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO3SEL_MSK)); +} + +/** + * @brief Select PIS producer IO2 + * @note + * @param SYSCFGx: SYSCFG Instance + * @param io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + * @retval None + */ +__STATIC_INLINE void md_syscfg_pisiocfg_io2sel(SYSCFG_TypeDef *SYSCFGx, md_syscfg_pisiocfg_t io) +{ + MODIFY_REG(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO2SEL_MSK, io << SYSCFG_PISIOCFG_IO2SEL_POSS); +} + +/** + * @brief Get PIS producer IO2 + * @note + * @param SYSCFGx: SYSCFG Instance + * @retval io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + */ +__STATIC_INLINE uint32_t md_syscfg_get_pisiocfg_io2sel(SYSCFG_TypeDef *SYSCFGx) +{ + return (READ_BIT(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO2SEL_MSK)); +} + +/** + * @brief Select PIS producer IO1 + * @note + * @param SYSCFGx: SYSCFG Instance + * @param io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + * @retval None + */ +__STATIC_INLINE void md_syscfg_pisiocfg_io1sel(SYSCFG_TypeDef *SYSCFGx, md_syscfg_pisiocfg_t io) +{ + MODIFY_REG(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO1SEL_MSK, io << SYSCFG_PISIOCFG_IO1SEL_POSS); +} + +/** + * @brief Get PIS producer IO1 + * @note + * @param SYSCFGx: SYSCFG Instance + * @retval io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + */ +__STATIC_INLINE uint32_t md_syscfg_get_pisiocfg_io1sel(SYSCFG_TypeDef *SYSCFGx) +{ + return (READ_BIT(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO1SEL_MSK)); +} + +/** + * @brief Select PIS producer IO0 + * @note + * @param SYSCFGx: SYSCFG Instance + * @param io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + * @retval None + */ +__STATIC_INLINE void md_syscfg_pisiocfg_io0sel(SYSCFG_TypeDef *SYSCFGx, md_syscfg_pisiocfg_t io) +{ + MODIFY_REG(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO0SEL_MSK, io << SYSCFG_PISIOCFG_IO0SEL_POSS); +} + +/** + * @brief Get PIS producer IO0 + * @note + * @param SYSCFGx: SYSCFG Instance + * @retval io: This parameter can be one of the following values: + * @arg @ref PA + * @arg @ref PB + * @arg @ref PC + * @arg @ref PD + */ +__STATIC_INLINE uint32_t md_syscfg_get_pisiocfg_io0sel(SYSCFG_TypeDef *SYSCFGx) +{ + return (READ_BIT(SYSCFGx->PISIOCFG, SYSCFG_PISIOCFG_IO0SEL_MSK)); +} +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __MD_SYSCFG_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_timer.c b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_timer.c new file mode 100644 index 0000000000..aca9266685 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_timer.c @@ -0,0 +1,814 @@ +/********************************************************************************** + * + * @file md_timer.c + * @brief TIMER module driver. + * + * @date 08 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 08 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_timer.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ + +/* Private function prototypes ----------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @addtogroup MD_TIMER + * @{ + */ + +/** @addtogroup MD_TIMER_Private_Functions + * @{ + */ +static md_status_t oc1_config(TIMER_TypeDef *TIMERx, md_timer_oc_init_t *init); +static md_status_t oc2_config(TIMER_TypeDef *TIMERx, md_timer_oc_init_t *init); +static md_status_t oc3_config(TIMER_TypeDef *TIMERx, md_timer_oc_init_t *init); +static md_status_t oc4_config(TIMER_TypeDef *TIMERx, md_timer_oc_init_t *init); +static md_status_t ic1_config(TIMER_TypeDef *TIMERx, md_timer_ic_init_t *init); +static md_status_t ic2_config(TIMER_TypeDef *TIMERx, md_timer_ic_init_t *init); +static md_status_t ic3_config(TIMER_TypeDef *TIMERx, md_timer_ic_init_t *init); +static md_status_t ic4_config(TIMER_TypeDef *TIMERx, md_timer_ic_init_t *init); +/** + * @} + */ + +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup MD_TIMER_Public_Functions + * @{ + */ +/** @addtogroup MD_TIMER_Public_Functions_Group1 + * @{ + */ +/** + * @brief Timer Base configuration + * @param TIMERx: TIMER periherl + * @param init: TIMER Base configuration structure + * @retval None + */ +void md_timer_base_set_config(TIMER_TypeDef *TIMERx, md_timer_base_init_t *init) +{ + if (init->mode == MD_TIMER_CNT_MODE_UP || init->mode == MD_TIMER_CNT_MODE_DOWN) + { + CLEAR_BIT(TIMERx->CON1, TIMER_CON1_CMSEL_MSK); + MODIFY_REG(TIMERx->CON1, TIMER_CON1_DIRSEL_MSK, init->mode << TIMER_CON1_DIRSEL_POS); + } + else + { + MODIFY_REG(TIMERx->CON1, TIMER_CON1_CMSEL_MSK, (init->mode - 1) << TIMER_CON1_CMSEL_POSS); + } + + if (MD_IS_TIMER_CLOCK_DIVISION_INSTANCE(TIMERx)) + MODIFY_REG(TIMERx->CON1, TIMER_CON1_DFCKSEL_MSK, init->clk_div << TIMER_CON1_DFCKSEL_POSS); + + md_timer_set_auto_reload_value_arrv(TIMERx, init->period); + md_timer_set_prescaler_value_pscv(TIMERx, init->prescaler); + + if (MD_IS_TIMER_REPETITION_COUNTER_INSTANCE(TIMERx)) + md_timer_set_repetition_counter_value_repv(TIMERx, init->re_cnt); + + /* Generate an update event to reload the pareameters */ + md_timer_enable_update_disue(TIMERx); + return; +} + +/** + * @brief Set the fields of the time base unit configuration data structure + * to their default values. + * @param init pointer to a @ref md_timer_base_init_t structure + * @retval None + */ +void md_timer_base_struct_init(md_timer_base_init_t *init) +{ + /* Set the default configuration */ + init->prescaler = (uint16_t)0x0000; + init->mode = MD_TIMER_CNT_MODE_UP; + init->period = 0xFFFFFFFFU; + init->clk_div = MD_TIMER_CLOCK_DIV1; + init->re_cnt = (uint8_t)0x00; +} + +/** + * @brief Set the fields of the TIMERx output channel configuration data + * structure to their default values. + * @param init pointer to a @ref md_timer_oc_init_t structure + * @retval None + */ +void md_timer_oc_struct_init(md_timer_oc_init_t *init) +{ + /* Set the default configuration */ + init->ocstate = MD_TIMER_OCSTATE_DISABLE; + init->ocnstate = MD_TIMER_OCSTATE_DISABLE; + init->oc_mode = MD_TIMER_OC_MODE_TIMERING; + init->pulse = 0x00000000; + init->oc_polarity = MD_TIMER_OC_POLARITY_HIGH; + init->ocn_polarity = MD_TIMER_OCN_POLARITY_HIGH; + init->oc_idle = MD_TIMER_OC_IDLE_RESET; + init->ocn_idle = MD_TIMER_OCN_IDLE_RESET; +} + +/** + * @brief Configure the TIMERx output channel. + * @param TIMERx Timer Instance + * @param channel This parameter can be one of @ref md_timer_channel_t + * @param init pointer to a @ref md_timer_oc_init_t structure + * @retval An md_status_t enumeration value: + * - MD_OK: TIMERx output channel is initialized + * - MD_ERROR: TIMERx output channel is not initialized + */ +md_status_t md_timer_oc_init(TIMER_TypeDef *TIMERx, md_timer_channel_t channel, md_timer_oc_init_t *init) +{ + md_status_t result = MD_ERROR; + + switch (channel) + { + case MD_TIMER_CHANNEL_1: + result = oc1_config(TIMERx, init); + break; + + case MD_TIMER_CHANNEL_2: + result = oc2_config(TIMERx, init); + break; + + case MD_TIMER_CHANNEL_3: + result = oc3_config(TIMERx, init); + break; + + case MD_TIMER_CHANNEL_4: + result = oc4_config(TIMERx, init); + break; + + default: + break; + } + + return result; +} + +/** + * @brief Set the fields of the TIMERx input channel configuration data + * structure to their default values. + * @param init pointer to a @ref md_timer_ic_init_t structure + * @retval None + */ +void md_timer_ic_struct_init(md_timer_ic_init_t *init) +{ + /* Set the default configuration */ + init->polarity = MD_TIMER_IC_POLARITY_RISE; + init->sel = MD_TIMER_IC_SEL_DIRECT; + init->psc = MD_TIMER_IC_PSC_DIV1; + init->filter = 0; +} + +/** + * @brief Configure the TIMERx input channel. + * @param TIMERx Timer Instance + * @param Channel This parameter can be one of @ref md_timer_channel_t + * @param init pointer to a @ref md_timer_ic_init_t structure + * @retval An md_status_t enumeration value: + * - MD_OK: TIMERx output channel is initialized + * - MD_ERROR: TIMERx output channel is not initialized + */ +md_status_t md_timer_ic_init(TIMER_TypeDef *TIMERx, md_timer_channel_t Channel, md_timer_ic_init_t *init) +{ + md_status_t result = MD_ERROR; + + switch (Channel) + { + case MD_TIMER_CHANNEL_1: + result = ic1_config(TIMERx, init); + break; + + case MD_TIMER_CHANNEL_2: + result = ic2_config(TIMERx, init); + break; + + case MD_TIMER_CHANNEL_3: + result = ic3_config(TIMERx, init); + break; + + case MD_TIMER_CHANNEL_4: + result = ic4_config(TIMERx, init); + break; + + default: + break; + } + + return result; +} + +/** + * @brief Fills each timer_encoder_init_struct field with its default value + * @param init pointer to a @ref md_timer_encoder_init_t structure + * @retval None + */ +void timer_encoder_struct_init(md_timer_encoder_init_t *init) +{ + /* Set the default configuration */ + init->mode = MD_TIMER_ENC_MODE_TI1; + init->ic1_polarity = MD_TIMER_IC_POLARITY_RISE; + init->ic1_sel = MD_TIMER_IC_SEL_DIRECT; + init->ic1_psc = MD_TIMER_IC_PSC_DIV1; + init->ic1_filter = 0; + init->ic2_polarity = MD_TIMER_IC_POLARITY_RISE; + init->ic2_sel = MD_TIMER_IC_SEL_DIRECT; + init->ic2_psc = MD_TIMER_IC_PSC_DIV1; + init->ic2_filter = 0; +} + +/** + * @brief Configure the encoder interface of the timer instance. + * @param TIMERx Timer Instance + * @param init pointer to a @ref md_timer_encoder_init_t structure + * @retval An md_status_t enumeration value: + * - MD_OK: TIMERx registers are de-initialized + * - MD_ERROR: not applicable + */ +md_status_t timer_encoder_init(TIMER_TypeDef *TIMERx, md_timer_encoder_init_t *init) +{ + uint32_t tmpchmr1 = 0U; + uint32_t tmpccep = 0U; + + /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ + TIMERx->CCEP &= (uint32_t)~(TIMER_CCEP_CC1EN_MSK | TIMER_CCEP_CC2EN_MSK); + + /* Get the TIMERx CCMR1 register value */ + tmpchmr1 = READ_REG(TIMERx->CHMR1); + + /* Get the TIMERx CCER register value */ + tmpccep = READ_REG(TIMERx->CCEP); + + /* Configure TI1 */ + tmpchmr1 &= (uint32_t)~(TIMER_CHMR1_CC1SSEL_MSK | TIMER_CHMR1_I1FLT_MSK | TIMER_CHMR1_IC1PRES_MSK); + tmpchmr1 |= (uint32_t)(init->ic1_sel << 0U); + tmpchmr1 |= (uint32_t)(init->ic1_filter << 4U); + tmpchmr1 |= (uint32_t)(init->ic1_psc << 2U); + + /* Configure TI2 */ + tmpchmr1 &= (uint32_t)~(TIMER_CHMR1_CC2SSEL_MSK | TIMER_CHMR1_I2FLT_MSK | TIMER_CHMR1_IC2PRES_MSK); + tmpchmr1 |= (uint32_t)(init->ic2_sel << 8U); + tmpchmr1 |= (uint32_t)(init->ic2_filter << 12U); + tmpchmr1 |= (uint32_t)(init->ic2_psc << 10U); + + /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ + tmpccep &= (uint32_t)~(TIMER_CCEP_CC1POL_MSK | TIMER_CCEP_CC1NPOL_MSK | TIMER_CCEP_CC2POL_MSK | TIMER_CCEP_CC2NPOL_MSK); + tmpccep |= (uint32_t)(init->ic1_polarity << 1U); + tmpccep |= (uint32_t)(init->ic2_polarity << 5U); + tmpccep |= (uint32_t)(TIMER_CCEP_CC1EN_MSK | TIMER_CCEP_CC2EN_MSK); + + /* Set encoder mode */ + md_timer_set_slave_mode_smods(TIMERx, init->mode); + + /* Write to TIMERx CCMR1 */ + WRITE_REG(TIMERx->CHMR1, tmpchmr1); + + /* Write to TIMERx CCER */ + WRITE_REG(TIMERx->CCEP, tmpccep); + + return MD_OK; +} + +/** + * @brief Set the fields of the TIMERx Hall sensor interface configuration data + * structure to their default values. + * @param init pointer to a @ref md_timer_hall_sensor_init_t structure + * @retval None + */ +void timer_hallsensor_struct_init(md_timer_hall_sensor_init_t *init) +{ + /* Set the default configuration */ + init->polarity = MD_TIMER_IC_POLARITY_RISE; + init->psc = MD_TIMER_IC_PSC_DIV1; + init->filter = 0U; + init->delay = 0U; +} + +/** + * @brief Configure the Hall sensor interface of the timer instance. + * @note TIMERx CH1, CH2 and CH3 inputs connected through a XOR + * to the TI1 input channel + * @param TIMERx Timer Instance + * @param init pointer to a @ref md_timer_hall_sensor_init_t structure + * @retval An md_status_t enumeration value: + * - MD_OK: TIMERx registers are de-initialized + * - MD_ERROR: not applicable + */ +md_status_t timer_hallsensor_init(TIMER_TypeDef *TIMERx, md_timer_hall_sensor_init_t *init) +{ + uint32_t tmpcon2 = 0U; + uint32_t tmpchmr1 = 0U; + uint32_t tmpccep = 0U; + uint32_t tmpsmcon = 0U; + + /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ + TIMERx->CCEP &= (uint32_t)~(TIMER_CCEP_CC1EN_MSK | TIMER_CCEP_CC2EN_MSK); + + /* Get the TIMERx CON2 register value */ + tmpcon2 = READ_REG(TIMERx->CON2); + + /* Get the TIMERx CHMR1 register value */ + tmpchmr1 = READ_REG(TIMERx->CHMR1); + + /* Get the TIMERx CCER register value */ + tmpccep = READ_REG(TIMERx->CCEP); + + /* Get the TIMERx SMCON register value */ + tmpsmcon = READ_REG(TIMERx->SMCON); + + /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */ + tmpcon2 |= TIMER_CON2_I1FSEL_MSK; + + /* OC2REF signal is used as trigger output (TRGO) */ + tmpcon2 |= (0x4U << TIMER_CON2_TRGOSEL_POSS) | (0x1U << TIMER_CON2_TRGOSEL_POSS); + + /* Configure the slave mode controller */ + tmpsmcon &= (uint32_t)~(TIMER_SMCON_TSSEL_MSK | TIMER_SMCON_SMODS_MSK); + tmpsmcon |= (0x4U << TIMER_SMCON_TSSEL_POSS); + tmpsmcon |= (0x4U << TIMER_SMCON_SMODS_POSS); + + /* Configure input channel 1 */ + tmpchmr1 &= (uint32_t)~(TIMER_CHMR1_CC1SSEL_POSS | TIMER_CHMR1_I1FLT_MSK | TIMER_CHMR1_IC1PRES_MSK); + tmpchmr1 |= (uint32_t)(TIMER_CHMR1_CC1SSEL_MSK); + tmpchmr1 |= (uint32_t)(init->filter << TIMER_CHMR1_I1FLT_POSS); + tmpchmr1 |= (uint32_t)(init->psc << TIMER_CHMR1_IC1PRES_POSS); + + /* Configure input channel 2 */ + tmpchmr1 &= (uint32_t)~(TIMER_CHMR1_CH2OMOD_MSK | TIMER_CHMR1_CH2OFEN_MSK | TIMER_CHMR1_CH2OPEN_MSK | TIMER_CHMR1_CH2OCLREN_MSK); + tmpchmr1 |= (uint32_t)(0x7U << TIMER_CHMR1_CH1OMOD_POSS); + + /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ + tmpccep &= (uint32_t)~(TIMER_CCEP_CC1POL_MSK | TIMER_CCEP_CC1NPOL_MSK | TIMER_CCEP_CC2POL_MSK | TIMER_CCEP_CC2NPOL_MSK); + tmpccep |= (uint32_t)(init->polarity << TIMER_CCEP_CC1POL_POS); + tmpccep |= (uint32_t)(TIMER_CCEP_CC1EN_MSK | TIMER_CCEP_CC2EN_MSK); + + /* Write to TIMERx CON2 */ + WRITE_REG(TIMERx->CON2, tmpcon2); + + /* Write to TIMERx SMCON */ + WRITE_REG(TIMERx->SMCON, tmpsmcon); + + /* Write to TIMERx CHMR1 */ + WRITE_REG(TIMERx->CHMR1, tmpchmr1); + + /* Write to TIMERx CCEP */ + WRITE_REG(TIMERx->CCEP, tmpccep); + + /* Write to TIMERx CCR2 */ + md_timer_set_capture_compare2_value_ccrv2(TIMERx, init->delay); + + return MD_OK; +} + +/** + * @brief Set the fields of the Break and Dead Time configuration data structure + * to their default values. + * @param init pointer to a @ref md_timer_break_dead_time_t structure (Break and Dead Time configuration data structure) + * @retval None + */ +void timer_bdtr_struct_init(md_timer_break_dead_time_t *init) +{ + /* Set the default configuration */ + init->off_run = DISABLE; + init->off_idle = DISABLE; + init->lock_level = MD_TIMER_LOCK_LEVEL_OFF; + init->dead_time = (uint8_t)0x00; + init->break_state = DISABLE; + init->polarity = MD_TIMER_BREAK_POLARITY_LOW; + init->auto_out = DISABLE; +} + +/** + * @brief Configure the Break and Dead Time feature of the timer instance. + * @param TIMERx Timer Instance + * @param init pointer to a @ref md_timer_break_dead_time_t structure + * @retval An md_status_t enumeration value: + * - MD_OK: Break and Dead Time is initialized + * - MD_ERROR: not applicable + */ +md_status_t timer_bdtr_init(TIMER_TypeDef *TIMERx, md_timer_break_dead_time_t *init) +{ + uint32_t tmpbdcfg = 0U; + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdcfg, TIMER_BDCFG_DT_MSK, (init->dead_time << TIMER_BDCFG_DT_POSS)); + MODIFY_REG(tmpbdcfg, TIMER_BDCFG_LOCKLVL_MSK, (init->lock_level << TIMER_BDCFG_LOCKLVL_POSS)); + MODIFY_REG(tmpbdcfg, TIMER_BDCFG_OFFSSI_MSK, (init->off_idle << TIMER_BDCFG_OFFSSI_POS)); + MODIFY_REG(tmpbdcfg, TIMER_BDCFG_OFFSSR_MSK, (init->off_run << TIMER_BDCFG_OFFSSR_POS)); + MODIFY_REG(tmpbdcfg, TIMER_BDCFG_BRKEN_MSK, (init->break_state << TIMER_BDCFG_BRKEN_POS)); + MODIFY_REG(tmpbdcfg, TIMER_BDCFG_BRKP_MSK, (init->polarity << TIMER_BDCFG_BRKP_POS)); + MODIFY_REG(tmpbdcfg, TIMER_BDCFG_AOEN_MSK, (init->auto_out << TIMER_BDCFG_AOEN_POS)); + MODIFY_REG(tmpbdcfg, TIMER_BDCFG_GOEN_MSK, (init->auto_out << TIMER_BDCFG_GOEN_POS)); + + /* Set TIMx_BDTR */ + WRITE_REG(TIMERx->BDCFG, tmpbdcfg); + return MD_OK; +} +/** + * @} + */ +/** + * @} + */ +/** @defgroup MD_TIMER_Private_Functions TIMER Private Functions + * @{ + */ +/** + * @brief Configure the TIMERx input channel 1. + * @param TIMERx Timer Instance + * @param init pointer to the the TIMERx input channel 1 configuration data structure + * @retval An md_status_t enumeration value: + * - MD_OK: TIMERx registers are de-initialized + * - MD_ERROR: not applicable + */ +static md_status_t ic1_config(TIMER_TypeDef *TIMERx, md_timer_ic_init_t *init) +{ + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMERx->CCEP &= (uint32_t)~TIMER_CCEP_CC1EN_MSK; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMERx->CHMR1, + (TIMER_CHMR1_CC1SSEL_MSK | TIMER_CHMR1_I1FLT_MSK | TIMER_CHMR1_IC1PRES_MSK), + (init->sel << 0U) | (init->filter << 4U) | (init->psc << 2U)); + + /* Select the Polarity and set the CC1E Bit */ + MODIFY_REG(TIMERx->CCEP, + (TIMER_CCEP_CC1POL_MSK | TIMER_CCEP_CC1NPOL_MSK), + (init->polarity << 1U) | (TIMER_CCEP_CC1EN_MSK)); + + return MD_OK; +} + +/** + * @brief Configure the TIMERx input channel 2. + * @param TIMERx Timer Instance + * @param init pointer to the the TIMERx input channel 2 configuration data structure + * @retval An md_status_t enumeration value: + * - MD_OK: TIMERx registers are de-initialized + * - MD_ERROR: not applicable + */ +static md_status_t ic2_config(TIMER_TypeDef *TIMERx, md_timer_ic_init_t *init) +{ + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMERx->CCEP &= (uint32_t)~TIMER_CCEP_CC2EN_MSK; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMERx->CHMR1, + (TIMER_CHMR1_CC2SSEL_MSK | TIMER_CHMR1_I2FLT_MSK | TIMER_CHMR1_IC2PRES_MSK), + (init->sel << 8U) | (init->filter << 12U) | (init->psc << 10U)); + + /* Select the Polarity and set the CC2E Bit */ + MODIFY_REG(TIMERx->CCEP, + (TIMER_CCEP_CC2POL_MSK | TIMER_CCEP_CC2NPOL_MSK), + (init->polarity << 5U) | (TIMER_CCEP_CC2EN_MSK)); + + return MD_OK; +} + +/** + * @brief Configure the TIMERx input channel 3. + * @param TIMERx Timer Instance + * @param init pointer to the the TIMERx input channel 3 configuration data structure + * @retval An md_status_t enumeration value: + * - MD_OK: TIMERx registers are de-initialized + * - MD_ERROR: not applicable + */ +static md_status_t ic3_config(TIMER_TypeDef *TIMERx, md_timer_ic_init_t *init) +{ + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMERx->CCEP &= (uint32_t)~TIMER_CCEP_CC3EN_MSK; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMERx->CHMR2, + (TIMER_CHMR2_CC3SSEL_MSK | TIMER_CHMR2_I3FLT_MSK | TIMER_CHMR2_IC3PRES_MSK), + (init->sel << 0U) | (init->filter << 4U) | (init->psc << 2U)); + + /* Select the Polarity and set the CC3E Bit */ + MODIFY_REG(TIMERx->CCEP, + (TIMER_CCEP_CC3POL_MSK | TIMER_CCEP_CC3NPOL_MSK), + (init->polarity << 9U) | (TIMER_CCEP_CC3EN_MSK)); + + return MD_OK; +} + +/** + * @brief Configure the TIMERx input channel 4. + * @param TIMERx Timer Instance + * @param init pointer to the the TIMERx input channel 4 configuration data structure + * @retval An md_status_t enumeration value: + * - MD_OK: TIMERx registers are de-initialized + * - MD_ERROR: not applicable + */ +static md_status_t ic4_config(TIMER_TypeDef *TIMERx, md_timer_ic_init_t *init) +{ + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMERx->CCEP &= (uint32_t)~TIMER_CCEP_CC4EN_MSK; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMERx->CHMR2, + (TIMER_CHMR2_CC4SSEL_MSK | TIMER_CHMR2_I4FLT_MSK | TIMER_CHMR2_IC4PRES_MSK), + (init->sel << 8U) | (init->filter << 12U) | (init->psc << 10U)); + + /* Select the Polarity and set the CC4E Bit */ + MODIFY_REG(TIMERx->CCEP, + TIMER_CCEP_CC4POL_MSK, + (init->polarity << 13U) | (TIMER_CCEP_CC4EN_MSK)); + + return MD_OK; +} + +/** + * @brief Configure the TIMERx output channel 1. + * @param TIMERx Timer Instance + * @param init pointer to the the TIMERx output channel 1 configuration data structure + * @retval An md_status_t enumeration value: + * - MD_OK: TIMERx registers are de-initialized + * - MD_ERROR: not applicable + */ +static md_status_t oc1_config(TIMER_TypeDef *TIMERx, md_timer_oc_init_t *init) +{ + uint32_t tmpchmr1 = 0U; + uint32_t tmpccep = 0U; + uint32_t tmpcon2 = 0U; + + /* Disable the Channel 1: Reset the CC1E Bit */ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); + + /* Get the TIMERx CCEP register value */ + tmpccep = READ_REG(TIMERx->CCEP); + + /* Get the TIMERx CON2 register value */ + tmpcon2 = READ_REG(TIMERx->CON2); + + /* Get the TIMERx CHMR1 register value */ + tmpchmr1 = READ_REG(TIMERx->CHMR1); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpchmr1, TIMER_CHMR1_CC1SSEL_MSK); + + /* Set the Output Compare Mode */ + MODIFY_REG(tmpchmr1, TIMER_CHMR1_CH1OMOD_MSK, init->oc_mode << 4U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccep, TIMER_CCEP_CC1POL_MSK, init->oc_polarity << 1U); + + /* Set the Output State */ + MODIFY_REG(tmpccep, TIMER_CCEP_CC1EN_MSK, init->ocstate); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccep, TIMER_CCEP_CC1NPOL_MSK, init->ocn_polarity << 3U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccep, TIMER_CCEP_CC1NE_MSK, init->ocnstate << 2U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcon2, TIMER_CON2_OISS1_MSK, init->oc_idle << 8U); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcon2, TIMER_CON2_OISS1N_MSK, init->ocn_idle << 9U); + + /* Write to TIMERx CON2 */ + WRITE_REG(TIMERx->CON2, tmpcon2); + + /* Write to TIMERx CHMR1 */ + WRITE_REG(TIMERx->CHMR1, tmpchmr1); + + /* Set the Capture Compare Register value */ + md_timer_set_capture_compare1_value_ccrv1(TIMERx, init->pulse); + + /* Write to TIMERx CCEP */ + WRITE_REG(TIMERx->CCEP, tmpccep); + + return MD_OK; +} + +/** + * @brief Configure the TIMERx output channel 1. + * @param TIMERx Timer Instance + * @param init pointer to the the TIMERx output channel 1 configuration data structure + * @retval An md_status_t enumeration value: + * - MD_OK: TIMERx registers are de-initialized + * - MD_ERROR: not applicable + */ +static md_status_t oc2_config(TIMER_TypeDef *TIMERx, md_timer_oc_init_t *init) +{ + uint32_t tmpchmr1 = 0U; + uint32_t tmpccep = 0U; + uint32_t tmpcon2 = 0U; + + /* Disable the Channel 2: Reset the CC2E Bit */ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); + + /* Get the TIMERx CCEP register value */ + tmpccep = READ_REG(TIMERx->CCEP); + + /* Get the TIMERx CON2 register value */ + tmpcon2 = READ_REG(TIMERx->CON2); + + /* Get the TIMERx CHMR1 register value */ + tmpchmr1 = READ_REG(TIMERx->CHMR1); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpchmr1, TIMER_CHMR1_CC2SSEL_MSK); + + /* Set the Output Compare Mode */ + MODIFY_REG(tmpchmr1, TIMER_CHMR1_CH2OMOD_MSK, init->oc_mode << 12U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccep, TIMER_CCEP_CC2POL_MSK, init->oc_polarity << 5U); + + /* Set the Output State */ + MODIFY_REG(tmpccep, TIMER_CCEP_CC2EN_MSK, init->ocstate << 4U); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccep, TIMER_CCEP_CC2NPOL_MSK, init->ocn_polarity << 7U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccep, TIMER_CCEP_CC2NE_MSK, init->ocnstate << 6U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcon2, TIMER_CON2_OISS2_MSK, init->oc_idle << 10U); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcon2, TIMER_CON2_OISS2N_MSK, init->ocn_idle << 11U); + + /* Write to TIMERx CON2 */ + WRITE_REG(TIMERx->CON2, tmpcon2); + + /* Write to TIMERx CHMR1 */ + WRITE_REG(TIMERx->CHMR1, tmpchmr1); + + /* Set the Capture Compare Register value */ + md_timer_set_capture_compare2_value_ccrv2(TIMERx, init->pulse); + + /* Write to TIMERx CCEP */ + WRITE_REG(TIMERx->CCEP, tmpccep); + + return MD_OK; +} + +/** + * @brief Configure the TIMERx output channel 1. + * @param TIMERx Timer Instance + * @param init pointer to the the TIMERx output channel 1 configuration data structure + * @retval An md_status_t enumeration value: + * - MD_OK: TIMERx registers are de-initialized + * - MD_ERROR: not applicable + */ +static md_status_t oc3_config(TIMER_TypeDef *TIMERx, md_timer_oc_init_t *init) +{ + uint32_t tmpchmr2 = 0U; + uint32_t tmpccep = 0U; + uint32_t tmpcon2 = 0U; + + /* Disable the Channel 3: Reset the CC3E Bit */ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); + + /* Get the TIMERx CCEP register value */ + tmpccep = READ_REG(TIMERx->CCEP); + + /* Get the TIMERx CON2 register value */ + tmpcon2 = READ_REG(TIMERx->CON2); + + /* Get the TIMERx CHMR2 register value */ + tmpchmr2 = READ_REG(TIMERx->CHMR2); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpchmr2, TIMER_CHMR2_CC3SSEL_MSK); + + /* Set the Output Compare Mode */ + MODIFY_REG(tmpchmr2, TIMER_CHMR2_CH3OMOD_MSK, init->oc_mode << 4U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccep, TIMER_CCEP_CC3POL_MSK, init->oc_polarity << 9U); + + /* Set the Output State */ + MODIFY_REG(tmpccep, TIMER_CCEP_CC3EN_MSK, init->ocstate << 8U); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccep, TIMER_CCEP_CC3NPOL_MSK, init->ocn_polarity << 11U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccep, TIMER_CCEP_CC3NE_MSK, init->ocnstate << 10U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcon2, TIMER_CON2_OISS3_MSK, init->oc_idle << 12U); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcon2, TIMER_CON2_OISS3N_MSK, init->ocn_idle << 13U); + + /* Write to TIMERx CON2 */ + WRITE_REG(TIMERx->CON2, tmpcon2); + + /* Write to TIMERx CHMR1 */ + WRITE_REG(TIMERx->CHMR2, tmpchmr2); + + /* Set the Capture Compare Register value */ + md_timer_set_capture_compare3_value_ccrv3(TIMERx, init->pulse); + + /* Write to TIMERx CCEP */ + WRITE_REG(TIMERx->CCEP, tmpccep); + + return MD_OK; +} + +/** + * @brief Configure the TIMERx output channel 1. + * @param TIMERx Timer Instance + * @param init pointer to the the TIMERx output channel 1 configuration data structure + * @retval An md_status_t enumeration value: + * - MD_OK: TIMERx registers are de-initialized + * - MD_ERROR: not applicable + */ +static md_status_t oc4_config(TIMER_TypeDef *TIMERx, md_timer_oc_init_t *init) +{ + uint32_t tmpchmr2 = 0U; + uint32_t tmpccep = 0U; + uint32_t tmpcon2 = 0U; + + /* Disable the Channel 4: Reset the CC4E Bit */ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); + + /* Get the TIMERx CCEP register value */ + tmpccep = READ_REG(TIMERx->CCEP); + + /* Get the TIMERx CON2 register value */ + tmpcon2 = READ_REG(TIMERx->CON2); + + /* Get the TIMERx CHMR2 register value */ + tmpchmr2 = READ_REG(TIMERx->CHMR2); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpchmr2, TIMER_CHMR2_CC4SSEL_MSK); + + /* Set the Output Compare Mode */ + MODIFY_REG(tmpchmr2, TIMER_CHMR2_CH4OMOD_MSK, init->oc_mode << 12U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccep, TIMER_CCEP_CC4POL_MSK, init->oc_polarity << 13U); + + /* Set the Output State */ + MODIFY_REG(tmpccep, TIMER_CCEP_CC4EN_MSK, init->ocstate << 12U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcon2, TIMER_CON2_OISS4_MSK, init->oc_idle << 14U); + + /* Write to TIMERx CON2 */ + WRITE_REG(TIMERx->CON2, tmpcon2); + + /* Write to TIMERx CHMR1 */ + WRITE_REG(TIMERx->CHMR2, tmpchmr2); + + /* Set the Capture Compare Register value */ + md_timer_set_capture_compare4_value_ccrv4(TIMERx, init->pulse); + + /* Write to TIMERx CCEP */ + WRITE_REG(TIMERx->CCEP, tmpccep); + + return MD_OK; +} +/** + * @} + */ + +/** + * @} MD_TIMER + */ +/** + * @} Micro_Driver + */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_timer.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_timer.h new file mode 100644 index 0000000000..484b8e88e6 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_timer.h @@ -0,0 +1,3899 @@ +/********************************************************************************** + * + * @file md_timer.h + * @brief Header file of TIMER module driver. + * + * @date 28 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 28 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __MD_TIMER_H__ +#define __MD_TIMER_H__ + +/* Includes ------------------------------------------------------------------ */ +#include "md_utils.h" + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Variables -------------------------------------------------------- */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Micro_Driver + * @{ + */ +/** @defgroup MD_TIMER TIMER + * @brief TIMER micro driver + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup MD_TIMER_Public_Types TIMER Public Types + * @{ + */ +/** + * @brief TIMER counter mode + */ +typedef enum +{ + MD_TIMER_CNT_MODE_UP = 0U, /**< Counter mode up */ + MD_TIMER_CNT_MODE_DOWN = 1U, /**< Counter mode down */ + MD_TIMER_CNT_MODE_CENTER1 = 2U, /**< Counter mode center1 */ + MD_TIMER_CNT_MODE_CENTER2 = 3U, /**< Counter mode center2 */ + MD_TIMER_CNT_MODE_CENTER3 = 4U, /**< Counter mode center3 */ +} md_timer_cnt_mode_t; + +/** + * @brief TIMER clock division + */ +typedef enum +{ + MD_TIMER_CLOCK_DIV1 = 0U, /**< No prescaler is used */ + MD_TIMER_CLOCK_DIV2 = 1U, /** Clock is divided by 2 */ + MD_TIMER_CLOCK_DIV4 = 2U, /** Clock is divided by 4 */ +} md_timer_clock_division_t; + +/** + * @brief TIMER output compare and PWM modes + */ +typedef enum +{ + MD_TIMER_OC_MODE_TIMERING = 0U, /**< Output compare mode is timering */ + MD_TIMER_OC_MODE_ACTIVE = 1U, /**< Output compare mode is active */ + MD_TIMER_OC_MODE_INACTIVE = 2U, /**< Output compare mode is inactive */ + MD_TIMER_OC_MODE_TOGGLE = 3U, /**< Output compare mode is toggle */ + MD_TIMER_OC_MODE_FORCE_INACTIVE = 4U, /**< Output compare mode is force inactive */ + MD_TIMER_OC_MODE_FORCE_ACTIVE = 5U, /**< Output compare mode is force active */ + MD_TIMER_OC_MODE_PWM1 = 6U, /**< Output compare mode is pwm1 */ + MD_TIMER_OC_MODE_PWM2 = 7U, /**< Output compare mode is pwm2 */ +} md_timer_oc_mode_t; + +/** + * @brief TIMER output compare polarity + */ +typedef enum +{ + MD_TIMER_OC_POLARITY_HIGH = 0U, /**< Output compare polarity is high */ + MD_TIMER_OC_POLARITY_LOW = 1U, /**< Output compare polarity is low */ +} md_timer_oc_polarity_t; + +/** + * @brief TIMER channel + */ +typedef enum +{ + MD_TIMER_CHANNEL_1 = 0U, /**< Channel 1 */ + MD_TIMER_CHANNEL_2 = 1U, /**< Channel 2 */ + MD_TIMER_CHANNEL_3 = 2U, /**< Channel 3 */ + MD_TIMER_CHANNEL_4 = 4U, /**< Channel 4 */ + MD_TIMER_CHANNEL_ALL = 0xFU, /**< All channel */ +} md_timer_channel_t; + +/** + * @brief TIMER complementary output compare polarity + */ +typedef enum +{ + MD_TIMER_OCN_POLARITY_HIGH = 0U, /**< Complementary output compare polarity is high */ + MD_TIMER_OCN_POLARITY_LOW = 1U, /**< Complementary output compare polarity is low */ +} md_timer_ocn_polarity_t; + +/** + * @brief TIMER output compare idle state + */ +typedef enum +{ + MD_TIMER_OC_IDLE_RESET = 0U, /**< Output compare idle state is reset */ + MD_TIMER_OC_IDLE_SET = 1U, /**< Output compare idle state is set */ +} md_timer_oc_idle_t; + +/** + * @brief TIMER complementary output compare idle state + */ +typedef enum +{ + MD_TIMER_OCN_IDLE_RESET = 0U, /**< Complementary output compare idle state is reset */ + MD_TIMER_OCN_IDLE_SET = 1U, /**< Complementary output compare idle state is set */ +} md_timer_ocn_idle_t; + +/** + * @brief TIMER output compare state + */ +typedef enum +{ + MD_TIMER_OCSTATE_DISABLE = 0U, /**< OCx is not active */ + MD_TIMER_OCSTATE_ENABLE = 1U, /**< OCx signal is output on the corresponding output pin */ +} md_timer_oc_state_t; + +/** + * @brief TIMER time base configuration structure definition + */ +typedef struct +{ + uint32_t prescaler; /**< Specifies the prescaler value used to divide the TIMER clock. */ + md_timer_cnt_mode_t mode; /**< Specifies the counter mode. */ + uint32_t period; /**< Specifies the period value to be loaded into ARR at the next update event. */ + md_timer_clock_division_t clk_div; /**< Specifies the clock division.*/ + uint32_t re_cnt; /**< Specifies the repetition counter value. */ +} md_timer_base_init_t; + +/** + * @brief TIMER output compare configuration structure definition + */ +typedef struct +{ + md_timer_oc_state_t ocstate; + md_timer_oc_state_t ocnstate; + md_timer_oc_mode_t oc_mode; /**< Specifies the TIMER mode. */ + uint32_t pulse; /**< Specifies the pulse value to be loaded into the Capture Compare Register. */ + md_timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity. */ + md_timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity. */ + type_func_t oc_fast_en; /**< Specifies the Fast mode state. */ + md_timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ + md_timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ +} md_timer_oc_init_t; + +/** + * @brief TIMER encoder mode + */ +typedef enum +{ + MD_TIMER_ENC_MODE_TI1 = 1U, /**< encoder mode 1 */ + MD_TIMER_ENC_MODE_TI2 = 2U, /**< encoder mode 2 */ + MD_TIMER_ENC_MODE_TI12 = 3U, /**< encoder mode 3 */ +} md_timer_encoder_mode_t; + +/** + * @brief TIMER input capture polarity + */ +typedef enum +{ + MD_TIMER_IC_POLARITY_RISE = 0U, /**< Input capture polarity rising */ + MD_TIMER_IC_POLARITY_FALL = 1U, /**< Input capture polarity falling */ + MD_TIMER_IC_POLARITY_BOTH = 5U, /**< Input capture polarity rising and falling */ +} md_timer_ic_polarity_t; + +/** + *@brief TIMER input capture selection + */ +typedef enum +{ + MD_TIMER_IC_SEL_DIRECT = 1U, /**< IC1 -- TI1 */ + MD_TIMER_IC_SEL_INDIRECT = 2U, /**< IC1 -- TI2 */ + MD_TIMER_IC_SEL_TRC = 3U, /**< IC1 -- TRC */ +} md_timer_ic_select_t; + +/** + * @brief TIMER input capture prescaler + */ +typedef enum +{ + MD_TIMER_IC_PSC_DIV1 = 0U, /**< Capture performed once every 1 events */ + MD_TIMER_IC_PSC_DIV2 = 1U, /**< Capture performed once every 2 events */ + MD_TIMER_IC_PSC_DIV4 = 2U, /**< Capture performed once every 4 events */ + MD_TIMER_IC_PSC_DIV8 = 3U, /**< Capture performed once every 4 events */ +} md_timer_ic_prescaler_t; + +/** + * @brief TIMER encoder configuration structure definition + */ +typedef struct +{ + md_timer_encoder_mode_t mode; /**< Specifies the encoder mode */ + md_timer_ic_polarity_t ic1_polarity; /**< Specifies the active edge of the input signal */ + md_timer_ic_select_t ic1_sel; /**< Specifies the input */ + md_timer_ic_prescaler_t ic1_psc; /**< Specifies the Input Capture Prescaler */ + uint32_t ic1_filter; /**< Specifies the input capture filter */ + md_timer_ic_polarity_t ic2_polarity; /**< Specifies the active edge of the input signal */ + md_timer_ic_select_t ic2_sel; /**< Specifies the input */ + md_timer_ic_prescaler_t ic2_psc; /**< Specifies the Input Capture Prescaler */ + uint32_t ic2_filter; /**< Specifies the input capture filter */ +} md_timer_encoder_init_t; + +/** + * @brief TIMER input capture configuration structure definition + */ +typedef struct +{ + md_timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + md_timer_ic_select_t sel; /**< Specifies the input */ + md_timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ + uint32_t filter; /**< Specifies the input capture filter */ +} md_timer_ic_init_t; + +/** + * @brief TIMER hall sensor configuretion structure definition + */ +typedef struct +{ + md_timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + md_timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ + uint32_t filter; /**< Specifies the input capture filter [0x0, 0xF] */ + uint32_t delay; /**< Specifies the pulse value to be loaded into the register [0x0, 0xFFFF] */ +} md_timer_hall_sensor_init_t; + +/** + * @brief TIMER lock level + */ +typedef enum +{ + MD_TIMER_LOCK_LEVEL_OFF = 0U, /**< Lock off */ + MD_TIMER_LOCK_LEVEL_1 = 1U, /**< Lock level 1 */ + MD_TIMER_LOCK_LEVEL_2 = 2U, /**< Lock level 2 */ + MD_TIMER_LOCK_LEVEL_3 = 3U, /**< Lock level 3 */ +} md_timer_lock_level_t; + +/** + * @brief TIMER break polarity + */ +typedef enum +{ + MD_TIMER_BREAK_POLARITY_LOW = 0U, /**< LOW */ + MD_TIMER_BREAK_POLARITY_HIGH = 1U, /**< HIGH */ +} md_timer_break_polarity_t; + +/** + * @brief TIMER break and dead time configuretion structure definition + */ +typedef struct +{ + type_func_t off_run; /**< Enalbe/Disable off state in run mode */ + type_func_t off_idle; /**< Enalbe/Disable off state in idle mode */ + md_timer_lock_level_t lock_level; /**< Lock level */ + uint32_t dead_time; /**< Dead time, [0x0, 0xFF] */ + type_func_t break_state; /**< Break state */ + md_timer_break_polarity_t polarity; /**< Break input polarity */ + type_func_t auto_out; /**< Enalbe/Disable automatic output */ +} md_timer_break_dead_time_t; + +/** + * @} + */ + +/** @defgroup MD_TIMER_Private_Macros TIMER Private Macros + * @{ + */ + +/* Exported Macros ----------------------------------------------------------- */ + +#if defined(__ES32VF2264_H__) + +#define MD_IS_TIMER_CC2_INSTANCE(x) (((x) == AD16C4T) || \ + ((x) == GP16C4T0) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T2)) +#define MD_IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == AD16C4T) ) +#define MD_IS_TIMER_CLOCK_DIVISION_INSTANCE(x) (MD_IS_TIMER_CC2_INSTANCE(x)) + +#endif /* __ES32VF2264_H__ */ + +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @defgroup MD_TIMER_Public_Functions TIMER Public Functions + * @{ + */ +/** @defgroup MD_TIMER_Public_Functions_Group2 CON1 + * @{ + */ +/** + * @brief TIMER Counter enable + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_counter_cnten(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->CON1, TIMER_CON1_CNTEN_MSK); +} + +/** + * @brief TIMER Counter disable + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_counter_cnten(TIMER_TypeDef *TIMERx) +{ + CLEAR_BIT(TIMERx->CON1, TIMER_CON1_CNTEN_MSK); +} + +/** + * @brief TIMER Check if counter enable + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_timer_is_counter_enable(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CON1, TIMER_CON1_CNTEN_MSK, TIMER_CON1_CNTEN_POS); +} + +/** + * @brief TIMER Update enable + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_update_disue(TIMER_TypeDef *TIMERx) +{ + CLEAR_BIT(TIMERx->CON1, TIMER_CON1_DISUE_MSK); +} + +/** + * @brief TIMER Update disable + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_update_disue(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->CON1, TIMER_CON1_DISUE_MSK); +} + +/** + * @brief TIMER Set update request source + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: Counter overflow/underflow Setting the UG bit + Update generation through the slave mode controller + * - 0x1: Only counter overflow/underflow generates an update + interrupt or DMA request if enabled + * @retval None + */ +__STATIC_INLINE void md_timer_set_update_source(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CON1, TIMER_CON1_UERSEL_MSK, sel << TIMER_CON1_UERSEL_POS); +} + +/** + * @brief TIMER Update request source + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Counter overflow/underflow + Setting the UG bit + Update generation through the slave mode controller + * - 0x1: Only counter overflow/underflow generates an update + interrupt or DMA request if enabled + */ +__STATIC_INLINE uint32_t md_timer_get_update_source(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CON1, TIMER_CON1_UERSEL_MSK, TIMER_CON1_UERSEL_POS); +} + +/** + * @brief TIMER Enable one pulse mode + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_onepulse_spmen(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->CON1, TIMER_CON1_SPMEN_MSK); +} + +/** + * @brief TIMER Disable one pulse mode + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_onepulse_spmen(TIMER_TypeDef *TIMERx) +{ + CLEAR_BIT(TIMERx->CON1, TIMER_CON1_SPMEN_MSK); +} + +/** + * @brief TIMER Check if one pulse mode enable + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_timer_is_onepulse_enable(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CON1, TIMER_CON1_SPMEN_MSK, TIMER_CON1_SPMEN_POS); +} + +/** + * @brief TIMER Set counter direction + * @param TIMERx TIMER Instance + * @param dir: The value of following: + * - 0x0: Counter used as upcounter + * - 0x1: Counter used as downcounter + * @retval None + */ +__STATIC_INLINE void md_timer_set_counter_direction_dirsel(TIMER_TypeDef *TIMERx, uint32_t dir) +{ + MODIFY_REG(TIMERx->CON1, TIMER_CON1_DIRSEL_MSK, dir << TIMER_CON1_DIRSEL_POS); +} + +/** + * @brief TIMER Get counter direction + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Counter used as upcounter + * - 0x1: Counter used as downcounter + */ +__STATIC_INLINE uint32_t md_timer_get_counter_direction_dirsel(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CON1, TIMER_CON1_DIRSEL_MSK, TIMER_CON1_DIRSEL_POS); +} + +/** + * @brief TIMER Set counter aligned mode + * @param TIMERx TIMER Instance + * @param mode: The value of following: + * - 0x0: Edge-aligned mode + * - 0x1: Center-aligned mode 1 + * - 0x2: Center-aligned mode 2 + * - 0x3: Center-aligned mode 3 + * @retval None + */ +__STATIC_INLINE void md_timer_set_counter_aligned_mode_cmsel(TIMER_TypeDef *TIMERx, uint32_t mode) +{ + MODIFY_REG(TIMERx->CON1, TIMER_CON1_CMSEL_MSK, mode << TIMER_CON1_CMSEL_POSS); +} + +/** + * @brief TIMER Get counter aligned mode + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Edge-aligned mode + * - 0x1: Center-aligned mode 1 + * - 0x2: Center-aligned mode 2 + * - 0x3: Center-aligned mode 3 + */ +__STATIC_INLINE uint32_t md_timer_get_counter_aligned_mode_cmsel(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CON1, TIMER_CON1_CMSEL_MSK, TIMER_CON1_CMSEL_POSS); +} + +/** + * @brief TIMER Auto-reload preload enable + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_autoreload_preload_arpen(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->CON1, TIMER_CON1_ARPEN_MSK); +} + +/** + * @brief TIMER Auto-reload preload disable + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_autoreload_preload_arpen(TIMER_TypeDef *TIMERx) +{ + CLEAR_BIT(TIMERx->CON1, TIMER_CON1_ARPEN_MSK); +} + +/** + * @brief TIMER Check if auto-reload preload enable + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_timer_is_autoreload_preload_enable(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CON1, TIMER_CON1_ARPEN_MSK, TIMER_CON1_ARPEN_POS); +} + +/** + * @brief TIMER Set clock division + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: tDTS=tCK_INT + * - 0x1: tDTS=2*tCK_INT + * - 0x2: tDTS=4*tCK_INT + * - 0x3: Reserved, do not program this value + * @retval None + */ +__STATIC_INLINE void md_timer_set_df_clock_dfcksel(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CON1, TIMER_CON1_DFCKSEL_MSK, sel << TIMER_CON1_DFCKSEL_POSS); +} + +/** + * @brief TIMER Get clock division + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: tDTS=tCK_INT + * - 0x1: tDTS=2*tCK_INT + * - 0x2: tDTS=4*tCK_INT + * - 0x3: Reserved, do not program this value + */ +__STATIC_INLINE uint32_t md_timer_get_df_clock_dfcksel(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CON1, TIMER_CON1_DFCKSEL_MSK, TIMER_CON1_DFCKSEL_POSS); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group3 CON2 + * @{ + */ +/** + * @brief TIMER Set capture/compare preloaded control + * @param TIMERx TIMER Instance + * @param cfg The value of following: + * - 0x0: CCnEN, CCnNEn and OCnOCM bits are not preloaded + * - 0x1: CCnEN, CCnNEn and OCnOCM bits are preloaded + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc_preload_ccpcen(TIMER_TypeDef *TIMERx, uint32_t cfg) +{ + MODIFY_REG(TIMERx->CON2, TIMER_CON2_CCPCEN_MSK, cfg << TIMER_CON2_CCPCEN_POS); +} + +/** + * @brief TIMER Get capture/compare preloaded control + * @param TIMERx TIMER Instance + * @retval cfg The value of following: + * - 0x0: CCnEN, CCnNEn and OCnOCM bits are not preloaded + * - 0x1: CCnEN, CCnNEn and OCnOCM bits are preloaded + */ +__STATIC_INLINE uint32_t md_timer_get_cc_preload_ccpcen(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CON2, TIMER_CON2_CCPCEN_MSK, TIMER_CON2_CCPCEN_POS); +} + +/** + * @brief TIMER Set capture/compare control update selection + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: if CCPCEN = 1,updated by setting the SGCOMG bit only + * - 0x1: if CCPCEN = 1,updated by setting the COMG bit or when an rising edge occurs on TI + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc_update_select_ccusel(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CON2, TIMER_CON2_CCPCEN_MSK, sel << TIMER_CON2_CCPCEN_POS); +} + +/** + * @brief TIMER Get capture/compare control update selection + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: if CCPCEN = 1,updated by setting the SGCOMG bit only + * - 0x1: if CCPCEN = 1,updated by setting the COMG bit or when an rising edge occurs on TI + */ +__STATIC_INLINE uint32_t md_timer_get_cc_update_select_ccusel(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CON2, TIMER_CON2_CCPCEN_MSK, TIMER_CON2_CCPCEN_POS); +} + +/** + * @brief TIMER Set capture/compare DMA selection + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CCn DMA request sent when CCx event occurs + * - 0x1: CCn DMA requests sent when update event occurs + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc_dma_select_ccdmasel(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CON2, TIMER_CON2_CCDMASEL_MSK, sel << TIMER_CON2_CCDMASEL_POS); +} + +/** + * @brief TIMER Get capture/compare DMA selection + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CCn DMA request sent when CCx event occurs + * - 0x1: CCn DMA requests sent when update event occurs + */ +__STATIC_INLINE uint32_t md_timer_get_cc_dma_select_ccdmasel(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CON2, TIMER_CON2_CCDMASEL_MSK, TIMER_CON2_CCDMASEL_POS); +} + +/** + * @brief TIMER I1 function selection + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: The TIMERn_CH1 pin is connected to I1 input + * - 0x1: The TIMERn_CH1, CH2 and CH3 pins are connected to the I1 input (XOR combination) + * @retval None + */ +__STATIC_INLINE void md_timer_set_i1_func_select_i1fsel(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CON2, TIMER_CON2_I1FSEL_MSK, sel << TIMER_CON2_I1FSEL_POS); +} + +/** + * @brief TIMER I1 function selection + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: The TIMERn_CH1 pin is connected to I1 input + * - 0x1: The TIMERn_CH1, CH2 and CH3 pins are connected to the I1 input (XOR combination) + */ +__STATIC_INLINE uint32_t md_timer_get_i1_func_select_i1fsel(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CON2, TIMER_CON2_I1FSEL_MSK, TIMER_CON2_I1FSEL_POS); +} + +/** + * @brief TIMER Output Idle state 1 (CH1O output) + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CH1O=0 (after a dead-time if CH1ON is implemented) when GOEN=0 + * - 0x1: CH1O=1 (after a dead-time if CH1ON is implemented) when GOEN=0 + * @retval None + */ +__STATIC_INLINE void md_timer_set_ch1o_idle_select_oiss1(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1_MSK, sel << TIMER_CON2_OISS1_POS); +} + +/** + * @brief TIMER Output Idle state 1 (CH1O output) + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CH1O=0 (after a dead-time if CH1ON is implemented) when GOEN=0 + * - 0x1: CH1O=1 (after a dead-time if CH1ON is implemented) when GOEN=0 + */ +__STATIC_INLINE uint32_t md_timer_get_ch1o_idle_select_oiss1(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CON2, TIMER_CON2_OISS1_MSK, TIMER_CON2_OISS1_POS); +} + +/** + * @brief TIMER Output Idle state 1 (CH1ON output) + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CH1ON=0 after a dead-time when GOEN=0 + * - 0x1: CH1ON=1 after a dead-time when GOEN=0 + * @retval None + */ +__STATIC_INLINE void md_timer_set_ch1on_idle_select_oiss1n(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1N_MSK, sel << TIMER_CON2_OISS1N_POS); +} + +/** + * @brief TIMER Output Idle state 1 (CH1ON output) + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CH1ON=0 after a dead-time when GOEN=0 + * - 0x1: CH1ON=1 after a dead-time when GOEN=0 + */ +__STATIC_INLINE uint32_t md_timer_get_ch1on_idle_select_oiss1n(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CON2, TIMER_CON2_OISS1N_MSK, TIMER_CON2_OISS1N_POS); +} + +/** + * @brief TIMER Output Idle state 1 (CH2O output) + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CH2O=0 (after a dead-time if CH2ON is implemented) when GOEN=0 + * - 0x1: CH2O=1 (after a dead-time if CH2ON is implemented) when GOEN=0 + * @retval None + */ +__STATIC_INLINE void md_timer_set_ch2o_idle_select_oiss2(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2_MSK, sel << TIMER_CON2_OISS2_POS); +} + +/** + * @brief TIMER Output Idle state 1 (CH2O output) + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CH2O=0 (after a dead-time if CH2ON is implemented) when GOEN=0 + * - 0x1: CH2O=1 (after a dead-time if CH2ON is implemented) when GOEN=0 + */ +__STATIC_INLINE uint32_t md_timer_get_ch2o_idle_select_oiss2(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CON2, TIMER_CON2_OISS2_MSK, TIMER_CON2_OISS2_POS); +} + +/** + * @brief TIMER Output Idle state 1 (CH2ON output) + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CH2ON=0 after a dead-time when GOEN=0 + * - 0x1: CH2ON=1 after a dead-time when GOEN=0 + * @retval None + */ +__STATIC_INLINE void md_timer_set_ch2on_idle_select_oiss2n(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2N_MSK, sel << TIMER_CON2_OISS2N_POS); +} + +/** + * @brief TIMER Output Idle state 1 (CH2ON output) + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CH2ON=0 after a dead-time when GOEN=0 + * - 0x1: CH2ON=1 after a dead-time when GOEN=0 + */ +__STATIC_INLINE uint32_t md_timer_get_ch2on_idle_select_oiss2n(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CON2, TIMER_CON2_OISS2N_MSK, TIMER_CON2_OISS2N_POS); +} + +/** + * @brief TIMER Output Idle state 1 (CH3O output) + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CH3O=0 (after a dead-time if CH3ON is implemented) when GOEN=0 + * - 0x1: CH3O=1 (after a dead-time if CH3ON is implemented) when GOEN=0 + * @retval None + */ +__STATIC_INLINE void md_timer_set_ch3o_idle_select_oiss3(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3_MSK, sel << TIMER_CON2_OISS3_POS); +} + +/** + * @brief TIMER Output Idle state 1 (CH3O output) + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CH3O=0 (after a dead-time if CH3ON is implemented) when GOEN=0 + * - 0x1: CH3O=1 (after a dead-time if CH3ON is implemented) when GOEN=0 + */ +__STATIC_INLINE uint32_t md_timer_get_ch3o_idle_select_oiss3(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CON2, TIMER_CON2_OISS3_MSK, TIMER_CON2_OISS3_POS); +} + +/** + * @brief TIMER Output Idle state 1 (CH3ON output) + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CH3ON=0 after a dead-time when GOEN=0 + * - 0x1: CH3ON=1 after a dead-time when GOEN=0 + * @retval None + */ +__STATIC_INLINE void md_timer_set_ch3on_idle_select_oiss3n(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3N_MSK, sel << TIMER_CON2_OISS3N_POS); +} + +/** + * @brief TIMER Output Idle state 1 (CH3ON output) + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CH3ON=0 after a dead-time when GOEN=0 + * - 0x1: CH3ON=1 after a dead-time when GOEN=0 + */ +__STATIC_INLINE uint32_t md_timer_get_ch3on_idle_select_oiss3n(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CON2, TIMER_CON2_OISS3N_MSK, TIMER_CON2_OISS3N_POS); +} + +/** + * @brief TIMER Output Idle state 1 (CH4O output) + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CH4O=0 when GOEN=0 + * - 0x1: CH4O=1 when GOEN=0 + * @retval None + */ +__STATIC_INLINE void md_timer_set_ch4o_idle_select_oiss4(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS4_MSK, sel << TIMER_CON2_OISS4_POS); +} + +/** + * @brief TIMER Output Idle state 1 (CH4O output) + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CH4O=0 when GOEN=0 + * - 0x1: CH4O=1 when GOEN=0 + */ +__STATIC_INLINE uint32_t md_timer_get_ch4o_idle_select_oiss4(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CON2, TIMER_CON2_OISS4_MSK, TIMER_CON2_OISS4_POS); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group4 SMCON + * @{ + */ +/** + * @brief TIMER Set slave mode selection + * @param TIMERx TIMER Instance + * @param sel: The value of following: + * - 0x0: Slave mode disabled + * - 0x1: Encoder mode 1 + * - 0x2: Encoder mode 2 + * - 0x3: Encoder mode 3 + * - 0x4: Reset Mode + * - 0x5: Gated Mode + * - 0x6: Trigger Mode + * - 0x6: External Clock Mode 1 + * @retval None + */ +__STATIC_INLINE void md_timer_set_slave_mode_smods(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_SMODS_MSK, sel << TIMER_SMCON_SMODS_POSS); +} + +/** + * @brief TIMER Set slave mode selection + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Slave mode disabled + * - 0x1: Encoder mode 1 + * - 0x2: Encoder mode 2 + * - 0x3: Encoder mode 3 + * - 0x4: Reset Mode + * - 0x5: Gated Mode + * - 0x6: Trigger Mode + * - 0x6: External Clock Mode 1 + */ +__STATIC_INLINE uint32_t md_timer_get_slave_mode_smods(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_SMCON_SMODS_POSS); +} + +/** + * @brief TIMER output channel clear OCCISS + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_output_channel_clear_occiss(TIMER_TypeDef *TIMERx) +{ + CLEAR_BIT(TIMERx->SMCON, TIMER_SMCON_OCCS_MSK); +} + +/** + * @brief TIMER output channel clear ETFP + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_output_channel_clear_etfp(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->SMCON, TIMER_SMCON_OCCS_MSK); +} + +/** + * @brief TIMER Check output channel clear is occiss or etfp + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: occiss + * - 0x1: etfp + */ +__STATIC_INLINE uint32_t md_timer_output_channel_clear_is_occiss_or_etfp(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->SMCON, TIMER_SMCON_OCCS_MSK, TIMER_SMCON_OCCS_POS); +} + +/** + * @brief TIMER Trigger selection + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: Internal Trigger 0 + * - 0x1: Internal Trigger 1 + * - 0x2: Internal Trigger 2 + * - 0x3: Internal Trigger 3 + * - 0x4: I1 Edge Detector + * - 0x5: Filtered Timer Input 1 + * - 0x6: Filtered Timer Input 2 + * - 0x7: External Trigger input + * @retval None + */ +__STATIC_INLINE void md_timer_set_slave_trigger_tssel(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_TSSEL_MSK, sel << TIMER_SMCON_TSSEL_POSS); +} + +/** + * @brief TIMER Trigger selection + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Internal Trigger 0 + * - 0x1: Internal Trigger 1 + * - 0x2: Internal Trigger 2 + * - 0x3: Internal Trigger 3 + * - 0x4: I1 Edge Detector + * - 0x5: Filtered Timer Input 1 + * - 0x6: Filtered Timer Input 2 + * - 0x7: External Trigger input + */ +__STATIC_INLINE uint32_t md_timer_get_slave_trigger_tssel(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_SMCON_TSSEL_POSS); +} + +/** + * @brief TIMER Set master/slave mode + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: No action + * - 0x1: The effect of an event on the trigger input is delayed to allow a perfect + * synchronization between the current timer and its slaves. + * @retval None + */ +__STATIC_INLINE void md_timer_set_master_slave_mode_mscfg(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_MSCFG_MSK, sel << TIMER_SMCON_MSCFG_POS); +} + +/** + * @brief TIMER Get master/slave mode + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: No action + * - 0x1: The effect of an event on the trigger input is delayed to allow a perfect + * synchronization between the current timer and its slaves. + */ +__STATIC_INLINE uint32_t md_timer_get_master_slave_mode_mscfg(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->SMCON, TIMER_SMCON_MSCFG_MSK, TIMER_SMCON_MSCFG_POS); +} + +/** + * @brief TIMER Set slave mode selection + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0:No filter, sampling is done at fDTS + * - 0x1:fSAMPLING = fINT_CLK, N = 2 + * - 0x2:fSAMPLING = fINT_CLK, N = 4 + * - 0x3:fSAMPLING = fINT_CLK, N = 8 + * - 0x4:fSAMPLING = fDTS / 2, N = 6 + * - 0x5:fSAMPLING = fDTS / 2, N = 8 + * - 0x6:fSAMPLING = fDTS / 4, N = 6 + * - 0x7:fSAMPLING = fDTS / 4, N = 8 + * - 0x8:fSAMPLING = fDTS / 8, N = 6 + * - 0x9:fSAMPLING = fDTS / 8, N = 8 + * - 0x10:fSAMPLING = fDTS / 16, N = 5 + * - 0x11:fSAMPLING = fDTS / 16, N = 6 + * - 0x12:fSAMPLING = fDTS / 16, N = 8 + * - 0x13:fSAMPLING = fDTS / 32, N = 5 + * - 0x14:fSAMPLING = fDTS / 32, N = 6 + * - 0x15:fSAMPLING = fDTS / 32, N = 8 + * @retval None + */ +__STATIC_INLINE void md_timer_set_external_trigger_filter_etflt(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETFLT_MSK, sel << TIMER_SMCON_ETFLT_POSS); +} + +/** + * @brief TIMER Trigger selection + * @param TIMERx TIMER Instance + * @retval sel The value of following: + * - 0x0:No filter, sampling is done at fDTS + * - 0x1:fSAMPLING = fINT_CLK, N = 2 + * - 0x2:fSAMPLING = fINT_CLK, N = 4 + * - 0x3:fSAMPLING = fINT_CLK, N = 8 + * - 0x4:fSAMPLING = fDTS / 2, N = 6 + * - 0x5:fSAMPLING = fDTS / 2, N = 8 + * - 0x6:fSAMPLING = fDTS / 4, N = 6 + * - 0x7:fSAMPLING = fDTS / 4, N = 8 + * - 0x8:fSAMPLING = fDTS / 8, N = 6 + * - 0x9:fSAMPLING = fDTS / 8, N = 8 + * - 0x10:fSAMPLING = fDTS / 16, N = 5 + * - 0x11:fSAMPLING = fDTS / 16, N = 6 + * - 0x12:fSAMPLING = fDTS / 16, N = 8 + * - 0x13:fSAMPLING = fDTS / 32, N = 5 + * - 0x14:fSAMPLING = fDTS / 32, N = 6 + * - 0x15:fSAMPLING = fDTS / 32, N = 8 + */ +__STATIC_INLINE uint32_t md_timer_get_external_trigger_filter_etflt(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->SMCON, TIMER_SMCON_MSCFG_MSK, TIMER_SMCON_MSCFG_POS); +} + +/** + * @brief TIMER Set external trigger prescaler + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: Prescaler OFF + * - 0x1: ETRP frequency divided by 2 + * - 0x2: ETRP frequency divided by 4 + * - 0x3: ETRP frequency divided by 8 + * @retval None + */ +__STATIC_INLINE void md_timer_set_external_trigger_prescaler_etpsel(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPSEL_MSK, sel << TIMER_SMCON_ETPSEL_POSS); +} + +/** + * @brief TIMER Get external trigger prescaler + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Prescaler OFF + * - 0x1: ETRP frequency divided by 2 + * - 0x2: ETRP frequency divided by 4 + * - 0x3: ETRP frequency divided by 8 + */ +__STATIC_INLINE uint32_t md_timer_get_external_trigger_prescaler_etpsel(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->SMCON, TIMER_SMCON_ETPSEL_MSK, TIMER_SMCON_ETPSEL_POSS); +} + +/** + * @brief TIMER Enable external clock mode 2 + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_external_clk2mode_ecm2en(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->SMCON, TIMER_SMCON_ECM2EN_MSK); +} + +/** + * @brief TIMER Disable external clock mode 2 + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_external_clk2mode_ecm2en(TIMER_TypeDef *TIMERx) +{ + CLEAR_BIT(TIMERx->SMCON, TIMER_SMCON_ECM2EN_MSK); +} + +/** + * @brief TIMER Check if external clock mode 2 enabled + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: External clock mode 2 disabled + * - 0x1: External clock mode 2 enabled + */ +__STATIC_INLINE uint32_t md_timer_is_external_clk2mode_enable(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->SMCON, TIMER_SMCON_ECM2EN_MSK, TIMER_SMCON_ECM2EN_POS); +} + +/** + * @brief TIMER Set external trigger polarity + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: ETR is non-inverted, active at high level or rising edge. + * - 0x1: ETR is inverted, active at low level or falling edge. + * @retval None + */ +__STATIC_INLINE void md_timer_set_external_trigger_polarity_etpol(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPOL_MSK, sel << TIMER_SMCON_ETPOL_POS); +} + +/** + * @brief TIMER Get external trigger polarity + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: ETR is non-inverted, active at high level or rising edge. + * - 0x1: ETR is inverted, active at low level or falling edge. + */ +__STATIC_INLINE uint32_t md_timer_get_external_trigger_polarity_etpol(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->SMCON, TIMER_SMCON_ETPOL_MSK, TIMER_SMCON_ETPOL_POS); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group5 IER + * @{ + */ +/** + * @brief TIMER Enable update interrupt + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_uit_interrupt(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->IER, TIMER_IER_UIT_MSK); +} + +/** + * @brief TIMER Enable cc1 interrupt + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_cc1it_interrupt(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->IER, TIMER_IER_CC1IT_MSK); +} + +/** + * @brief TIMER Enable cc2 interrupt + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_cc2it_interrupt(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->IER, TIMER_IER_CC2IT_MSK); +} + +/** + * @brief TIMER Enable cc3 interrupt + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_cc3it_interrupt(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->IER, TIMER_IER_CC3IT_MSK); +} + +/** + * @brief TIMER Enable cc4 interrupt + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_cc4it_interrupt(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->IER, TIMER_IER_CC4IT_MSK); +} + +/** + * @brief TIMER Enable COM interrupt + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_comit_interrupt(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->IER, TIMER_IER_COMIT_MSK); +} + +/** + * @brief TIMER Enable trigger interrupt + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_trgit_interrupt(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->IER, TIMER_IER_TRGIT_MSK); +} + +/** + * @brief TIMER Enable break interrupt + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_brkit_interrupt(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->IER, TIMER_IER_BRKIT_MSK); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group6 IDR + * @{ + */ +/** + * @brief TIMER Disable update interrupt + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_ui_interrupt(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->IDR, TIMER_IDR_UI_MSK); +} + +/** + * @brief TIMER Disable cc1i interrupt + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_cc1i_interrupt(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->IDR, TIMER_IDR_CC1I_MSK); +} + +/** + * @brief TIMER Disable cc2i interrupt + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_cc2i_interrupt(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->IDR, TIMER_IDR_CC3I_MSK); +} + +/** + * @brief TIMER Disable cc3i interrupt + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_cc3i_interrupt(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->IDR, TIMER_IDR_CC3I_MSK); +} + +/** + * @brief TIMER Disable cc4 interrupt + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_cc4i_interrupt(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->IDR, TIMER_IDR_CC4I_MSK); +} + +/** + * @brief TIMER Disable COM interrupt + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_comi_interrupt(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->IDR, TIMER_IDR_COMI_MSK); +} + +/** + * @brief TIMER Disable trigger interrupt + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_trgi_interrupt(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->IDR, TIMER_IDR_TRGI_MSK); +} + +/** + * @brief TIMER Disable break interrupt + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_brki_interrupt(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->IDR, TIMER_IDR_BRKI_MSK); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group7 IVS + * @{ + */ +/** + * @brief TIMER Get update event interrupt state + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_timer_get_update_interrupt_state_uei(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->IVS, TIMER_IVS_UEI_MSK, TIMER_IVS_UEI_POS); +} + +/** + * @brief TIMER Get capture/compare 1 interrupt state + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_timer_get_cc1_interrupt_state_cc1i(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->IVS, TIMER_IVS_CC1I_MSK, TIMER_IVS_CC1I_POS); +} + +/** + * @brief TIMER Get capture/compare 2 interrupt state + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_timer_get_cc2_interrupt_state_cc2i(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->IVS, TIMER_IVS_CC2I_MSK, TIMER_IVS_CC2I_POS); +} + +/** + * @brief TIMER Get capture/compare 3 interrupt state + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_timer_get_cc3_interrupt_state_cc3i(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->IVS, TIMER_IVS_CC3I_MSK, TIMER_IVS_CC3I_POS); +} + +/** + * @brief TIMER Get capture/compare 4 interrupt state + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_timer_get_cc4_interrupt_state_cc4i(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->IVS, TIMER_IVS_CC4I_MSK, TIMER_IVS_CC4I_POS); +} + +/** + * @brief TIMER Get COM interrupt state + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_timer_get_com_interrupt_state_comi(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->IVS, TIMER_IVS_COMI_MSK, TIMER_IVS_COMI_POS); +} + +/** + * @brief TIMER Get trig interrupt state + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_timer_get_trigger_interrupt_state_trgi(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->IVS, TIMER_IVS_TRGI_MSK, TIMER_IVS_TRGI_POS); +} + +/** + * @brief TIMER Get break interrupt state + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_timer_get_break_interrupt_state_bki(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->IVS, TIMER_IVS_BKI_MSK, TIMER_IVS_BKI_POS); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group8 RIF + * @{ + */ +/** + * @brief TIMER Get update interrupt flag + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: RESET + * - 1: SET + */ +__STATIC_INLINE uint32_t md_timer_get_update_interrupt_flag_uevtif(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->RIF, TIMER_RIF_UEVTIF_MSK, TIMER_RIF_UEVTIF_POS); +} + +/** + * @brief TIMER Get capture/compare 1 interrupt flag + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: RESET + * - 1: SET + */ +__STATIC_INLINE uint32_t md_timer_get_cc1_interrupt_flag_ch1if(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->RIF, TIMER_RIF_CH1IF_MSK, TIMER_RIF_CH1IF_POS); +} + +/** + * @brief TIMER Get capture/compare 2 interrupt flag + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: RESET + * - 1: SET + */ +__STATIC_INLINE uint32_t md_timer_get_cc2_interrupt_flag_ch2if(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->RIF, TIMER_RIF_CH2IF_MSK, TIMER_RIF_CH2IF_POS); +} + +/** + * @brief TIMER Get capture/compare 3 interrupt flag + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: RESET + * - 1: SET + */ +__STATIC_INLINE uint32_t md_timer_get_cc3_interrupt_flag_ch3if(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->RIF, TIMER_RIF_CH3IF_MSK, TIMER_RIF_CH3IF_POS); +} + +/** + * @brief TIMER Get capture/compare 4 interrupt flag + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: RESET + * - 1: SET + */ +__STATIC_INLINE uint32_t md_timer_get_cc4_interrupt_flag_ch4if(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->RIF, TIMER_RIF_CH4IF_MSK, TIMER_RIF_CH4IF_POS); +} + +/** + * @brief TIMER Get com interrupt flag + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: RESET + * - 1: SET + */ +__STATIC_INLINE uint32_t md_timer_get_com_interrupt_flag_comif(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->RIF, TIMER_RIF_COMIF_MSK, TIMER_RIF_COMIF_POS); +} + +/** + * @brief TIMER Get trigger interrupt flag + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: RESET + * - 1: SET + */ +__STATIC_INLINE uint32_t md_timer_get_trigger_interrupt_flag_trgif(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->RIF, TIMER_RIF_TRGIF_MSK, TIMER_RIF_TRGIF_POS); +} + +/** + * @brief TIMER Get break interrupt flag + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: RESET + * - 1: SET + */ +__STATIC_INLINE uint32_t md_timer_get_break_interrupt_flag_brkif(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->RIF, TIMER_RIF_BRKIF_MSK, TIMER_RIF_BRKIF_POS); +} + +/** + * @brief TIMER Get capture/compare 1 overflow interrupt flag + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: RESET + * - 1: SET + */ +__STATIC_INLINE uint32_t md_timer_get_cc1_overflow_interrupt_flag_ch1ovif(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->RIF, TIMER_RIF_CH1OVIF_MSK, TIMER_RIF_CH1OVIF_POS); +} + +/** + * @brief TIMER Get capture/compare 2 overflow interrupt flag + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: RESET + * - 1: SET + */ +__STATIC_INLINE uint32_t md_timer_get_cc2_overflow_interrupt_flag_ch2ovif(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->RIF, TIMER_RIF_CH2OVIF_MSK, TIMER_RIF_CH2OVIF_POS); +} + +/** + * @brief TIMER Get capture/compare 3 overflow interrupt flag + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: RESET + * - 1: SET + */ +__STATIC_INLINE uint32_t md_timer_get_cc3_overflow_interrupt_flag_ch3ovif(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->RIF, TIMER_RIF_CH3OVIF_MSK, TIMER_RIF_CH3OVIF_POS); +} + +/** + * @brief TIMER Get capture/compare 4 overflow interrupt flag + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: RESET + * - 1: SET + */ +__STATIC_INLINE uint32_t md_timer_get_cc4_overflow_interrupt_flag_ch4ovif(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->RIF, TIMER_RIF_CH4OVIF_MSK, TIMER_RIF_CH4OVIF_POS); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group9 IFM + * @{ + */ +/** + * @brief TIMER Get update valid interrupt flag + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: RESET + * - 1: SET + */ +__STATIC_INLINE uint32_t md_timer_get_update_valid_interrupt_flag_uei(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->IFM, TIMER_IFM_UEI_MSK, TIMER_IFM_UEI_POS); +} + +/** + * @brief TIMER Get capture/compare 1 valid interrupt flag + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: RESET + * - 1: SET + */ +__STATIC_INLINE uint32_t md_timer_get_cc1_valid_interrupt_flag_ch1cci(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->IFM, TIMER_IFM_CH1CCI_MSK, TIMER_IFM_CH1CCI_POS); +} + +/** + * @brief TIMER Get capture/compare 2 valid interrupt flag + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: RESET + * - 1: SET + */ +__STATIC_INLINE uint32_t md_timer_get_cc2_valid_interrupt_flag_ch2cci(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->IFM, TIMER_IFM_CH2CCI_MSK, TIMER_IFM_CH2CCI_POS); +} + +/** + * @brief TIMER Get capture/compare 3 valid interrupt flag + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: RESET + * - 1: SET + */ +__STATIC_INLINE uint32_t md_timer_get_cc3_valid_interrupt_flag_ch3cci(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->IFM, TIMER_IFM_CH3CCI_MSK, TIMER_IFM_CH3CCI_POS); +} + +/** + * @brief TIMER Get capture/compare 4 valid interrupt flag + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: RESET + * - 1: SET + */ +__STATIC_INLINE uint32_t md_timer_get_cc4_valid_interrupt_flag_ch4cci(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->IFM, TIMER_IFM_CH4CCI_MSK, TIMER_IFM_CH4CCI_POS); +} + +/** + * @brief TIMER Get com valid interrupt flag + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: RESET + * - 1: SET + */ +__STATIC_INLINE uint32_t md_timer_get_com_valid_interrupt_flag_comi(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->IFM, TIMER_IFM_COMI_MSK, TIMER_IFM_COMI_POS); +} + +/** + * @brief TIMER Get trigger valid interrupt flag + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: RESET + * - 1: SET + */ +__STATIC_INLINE uint32_t md_timer_get_trigger_valid_interrupt_flag_trgi(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->IFM, TIMER_IFM_TRGI_MSK, TIMER_IFM_TRGI_POS); +} + +/** + * @brief TIMER Get break valid interrupt flag + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: RESET + * - 1: SET + */ +__STATIC_INLINE uint32_t md_timer_get_break_valid_interrupt_flag_brkim(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->IFM, TIMER_IFM_BRKIM_MSK, TIMER_IFM_BRKIM_POS); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group10 ICR + * @{ + */ +/** + * @brief TIMER Clear update interrupt flag + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_clear_update_interrupt_flag_ueic(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->ICR, TIMER_ICR_UEIC_MSK); +} + +/** + * @brief TIMER Clear capture/compare 1 interrupt flag + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_clear_cc1_interrupt_flag_ch1ccic(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->ICR, TIMER_ICR_CH1CCIC_MSK); +} + +/** + * @brief TIMER Clear capture/compare 2 interrupt flag + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_clear_cc2_interrupt_flag_ch2ccic(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->ICR, TIMER_ICR_CH2CCIC_MSK); +} + +/** + * @brief TIMER Clear capture/compare 3 interrupt flag + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_clear_cc3_interrupt_flag_ch3ccic(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->ICR, TIMER_ICR_CH3CCIC_MSK); +} + +/** + * @brief TIMER Clear capture/compare 4 interrupt flag + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_clear_cc4_interrupt_flag_ch4ccic(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->ICR, TIMER_ICR_CH4CCIC_MSK); +} + +/** + * @brief TIMER Clear com interrupt flag + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_clear_com_interrupt_flag_comic(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->ICR, TIMER_ICR_COMIC_MSK); +} + +/** + * @brief TIMER Clear trigger interrupt flag + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_clear_trigger_interrupt_flag_trgic(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->ICR, TIMER_ICR_TRGIC_MSK); +} + +/** + * @brief TIMER Clear break interrupt flag + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_clear_break_interrupt_flag_brkic(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->ICR, TIMER_ICR_BRKIC_MSK); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group11 SGE + * @{ + */ +/** + * @brief TIMER Set software to generate update event + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: No action + * - 0x1: Reinitialize the counter and generates an update of the registers + * @retval None + */ +__STATIC_INLINE void md_timer_set_uev_software_sgu(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->SGE, TIMER_SGE_SGU_MSK, sel << TIMER_SGE_SGU_POS); +} + +/** + * @brief TIMER Set software to generate capture/compare 1 event + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: No action + * - 0x1: A capture/compare event is generated on channel 1 + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc1ev_software_sgcc1e(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->SGE, TIMER_SGE_SGCC1E_MSK, sel << TIMER_SGE_SGCC1E_POS); +} + +/** + * @brief TIMER Set software to generate capture/compare 2 event + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: No action + * - 0x1: A capture/compare event is generated on channel 2 + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc2ev_software_sgcc2e(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->SGE, TIMER_SGE_SGCC2E_MSK, sel << TIMER_SGE_SGCC2E_POS); +} + +/** + * @brief TIMER Set software to generate capture/compare 3 event + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: No action + * - 0x1: A capture/compare event is generated on channel 3 + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc3ev_software_sgcc3e(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->SGE, TIMER_SGE_SGCC3E_MSK, sel << TIMER_SGE_SGCC3E_POS); +} + +/** + * @brief TIMER Set software to generate capture/compare 4 event + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: No action + * - 0x1: A capture/compare event is generated on channel 4 + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc4ev_software_sgcc4e(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->SGE, TIMER_SGE_SGCC4E_MSK, sel << TIMER_SGE_SGCC4E_POS); +} + +/** + * @brief TIMER Set software to generate capture/compare control update event + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: No action + * - 0x1: When CCPCEN bit is set, it allows to update CCnEN, CCnNEN and CHnOCM bits + * @retval None + */ +__STATIC_INLINE void md_timer_set_comev_software_sgcom(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->SGE, TIMER_SGE_SGCOM_MSK, sel << TIMER_SGE_SGCOM_POS); +} + +/** + * @brief TIMER Set software to generate trigger event + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: No action + * - 0x1: The TRGIF flag is set in TIMERn_RIF register. Related interrupt or DMA transfer + can occur if enabled + * @retval None + */ +__STATIC_INLINE void md_timer_set_trigev_software_sgtrg(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->SGE, TIMER_SGE_SGTRG_MSK, sel << TIMER_SGE_SGTRG_POS); +} + +/** + * @brief TIMER Set software to generate break event + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: No action + * - 0x1: The TRGIF flag is set in TIMERn_RIF register. Related interrupt or DMA transfer + * can occur if enabled + * @retval None + */ +__STATIC_INLINE void md_timer_set_breakev_software_sgbrk(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->SGE, TIMER_SGE_SGBRK_MSK, sel << TIMER_SGE_SGBRK_POS); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group12 CHMR1 + * @{ + */ +/** + * @brief TIMER Set capture/compare 1 channel function selection + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CC1 channel is configured as output + * - 0x1: CC1 channel is configured as input, mapped on I1 + * - 0x2: CC1 channel is configured as input, mapped on I2 + * - 0x3: CC1 channel is configured as input, mapped on ITn or both edge of I1 + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc1_func_cc1ssel(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, sel << TIMER_CHMR1_CC1SSEL_POSS); +} + +/** + * @brief TIMER Get capture/compare 1 channel function selection + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CC1 channel is configured as output + * - 0x1: CC1 channel is configured as input, mapped on I1 + * - 0x2: CC1 channel is configured as input, mapped on I2 + * - 0x3: CC1 channel is configured as input, mapped on ITn or both edge of I1 + */ +__STATIC_INLINE uint32_t md_timer_get_cc1_func_cc1ssel(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_CHMR1_CC1SSEL_POSS); +} + +/** + * @brief TIMER Set output Compare 1 fast enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CCVAL1 behaves normally depending on counter and CCRV1 values even when the trigger is ON + * - 0x1: An active edge on the trigger input acts like a compare match on CCVAL1 output. + * @retval None + */ +__STATIC_INLINE void md_timer_set_output_compare1_fast_enable_ch1ohsen(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH1OHSEN_MSK, sel << TIMER_CHMR1_CH1OHSEN_POS); +} + +/** + * @brief TIMER Get output Compare 1 fast enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CCVAL1 behaves normally depending on counter and CCRV1 values even when the trigger is ON + * - 0x1: An active edge on the trigger input acts like a compare match on CCVAL1 output. + */ +__STATIC_INLINE uint32_t md_timer_is_output_compare1_fast_enable_ch1ohsen(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR1, TIMER_CHMR1_CH1OHSEN_MSK, TIMER_CHMR1_CH1OHSEN_POS); +} + +/** + * @brief TIMER Set output Compare 1 preload enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: Preload register on TIMERn_CCVAL1 disabled + * - 0x1: Preload register on TIMERn_CCVAL1 enabled + * @retval None + */ +__STATIC_INLINE void md_timer_set_output_compare1_preload_enable_ch1opren(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH1OPREN_MSK, sel << TIMER_CHMR1_CH1OPREN_POS); +} + +/** + * @brief TIMER Get output Compare 1 preload enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Preload register on TIMERn_CCVAL1 disabled + * - 0x1: Preload register on TIMERn_CCVAL1 enabled + */ +__STATIC_INLINE uint32_t md_timer_is_output_compare1_preload_enable_ch1opren(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR1, TIMER_CHMR1_CH1OPREN_MSK, TIMER_CHMR1_CH1OPREN_POS); +} + +/** + * @brief TIMER Set Output Compare 1 mode + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: Frozen + * - 0x1: Set channel 1 to active level on match + * - 0x2: Set channel 1 to inactive level on match + * - 0x3: Toggle + * - 0x4: Force inactive level + * - 0x5: Force active level + * - 0x6: PWM mode 1 + * - 0x7: PWM mode 2 + * @retval None + */ +__STATIC_INLINE void md_timer_set_output_compare1_mode_ch1omod(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, sel << TIMER_CHMR1_CH1OMOD_POSS); +} + +/** + * @brief TIMER Set Output Compare 1 mode + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Frozen + * - 0x1: Set channel 1 to active level on match + * - 0x2: Set channel 1 to inactive level on match + * - 0x3: Toggle + * - 0x4: Force inactive level + * - 0x5: Force active level + * - 0x6: PWM mode 1 + * - 0x7: PWM mode 2 + */ +__STATIC_INLINE uint32_t md_timer_get_output_compare1_mode_ch1omod(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, TIMER_CHMR1_CH1OMOD_POSS); +} + +/** + * @brief TIMER Set output compare 1 clear enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CH1O is not affected by the ETRF Input + * - 0x1: CH1O is cleared as soon as a High level is detected on ETRF input + * @retval None + */ +__STATIC_INLINE void md_timer_set_output_compare1_clear_enable_ch1oclren(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH1OCLREN_MSK, sel << TIMER_CHMR1_CH1OCLREN_POS); +} + +/** + * @brief TIMER Get output compare 1 clear enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CH1O is not affected by the ETRF Input + * - 0x1: CH1O is cleared as soon as a High level is detected on ETRF input + */ +__STATIC_INLINE uint32_t md_timer_is_output_compare1_clear_enable_ch1oclren(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR1, TIMER_CHMR1_CH1OCLREN_MSK, TIMER_CHMR1_CH1OCLREN_POS); +} + +/** + * @brief TIMER Set capture/compare 2 channel function selection + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CC2 channel is configured as output + * - 0x1: CC2 channel is configured as input, mapped on I1 + * - 0x2: CC2 channel is configured as input, mapped on I2 + * - 0x3: CC2 channel is configured as input, mapped on ITn or both edge of I1 + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc2_func_cc2ssel(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, sel << TIMER_CHMR1_CC2SSEL_POSS); +} + +/** + * @brief TIMER Get capture/compare 2 channel function selection + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CC2 channel is configured as output + * - 0x1: CC2 channel is configured as input, mapped on I1 + * - 0x2: CC2 channel is configured as input, mapped on I2 + * - 0x3: CC2 channel is configured as input, mapped on ITn or both edge of I1 + */ +__STATIC_INLINE uint32_t md_timer_get_cc2_func_cc2ssel(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_CHMR1_CC2SSEL_POSS); +} + +/** + * @brief TIMER Set output Compare 2 fast enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CCVAL2 behaves normally depending on counter and CCRV2 values even when the trigger is ON + * - 0x1: An active edge on the trigger input acts like a compare match on CCVAL2 output. + * @retval None + */ +__STATIC_INLINE void md_timer_set_output_compare2_fast_enable_ch2ohsen(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH2OFEN_MSK, sel << TIMER_CHMR1_CH2OFEN_POS); +} + +/** + * @brief TIMER Get output Compare 2 fast enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CCVAL2 behaves normally depending on counter and CCRV2 values even when the trigger is ON + * - 0x1: An active edge on the trigger input acts like a compare match on CCVAL2 output. + */ +__STATIC_INLINE uint32_t md_timer_is_output_compare2_fast_enable_ch2ohsen(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR1, TIMER_CHMR1_CH2OFEN_MSK, TIMER_CHMR1_CH2OFEN_POS); +} + +/** + * @brief TIMER Set output Compare 2 preload enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: Preload register on TIMERn_CCVAL2 disabled + * - 0x1: Preload register on TIMERn_CCVAL2 enabled + * @retval None + */ +__STATIC_INLINE void md_timer_set_output_compare2_preload_enable_ch2opren(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH2OPEN_MSK, sel << TIMER_CHMR1_CH2OPEN_POS); +} + +/** + * @brief TIMER Get output Compare 2 preload enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Preload register on TIMERn_CCVAL2 disabled + * - 0x1: Preload register on TIMERn_CCVAL2 enabled + */ +__STATIC_INLINE uint32_t md_timer_is_output_compare2_preload_enable_ch2opren(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR1, TIMER_CHMR1_CH2OPEN_MSK, TIMER_CHMR1_CH2OPEN_POS); +} + +/** + * @brief TIMER Set Output Compare 2 mode + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: Frozen + * - 0x1: Set channel 2 to active level on match + * - 0x2: Set channel 2 to inactive level on match + * - 0x3: Toggle + * - 0x4: Force inactive level + * - 0x5: Force active level + * - 0x6: PWM mode 1 + * - 0x7: PWM mode 2 + * @retval None + */ +__STATIC_INLINE void md_timer_set_output_compare2_mode_ch2omod(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, sel << TIMER_CHMR1_CH2OMOD_POSS); +} + +/** + * @brief TIMER Set Output Compare 2 mode + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Frozen + * - 0x1: Set channel 2 to active level on match + * - 0x2: Set channel 2 to inactive level on match + * - 0x3: Toggle + * - 0x4: Force inactive level + * - 0x5: Force active level + * - 0x6: PWM mode 1 + * - 0x7: PWM mode 2 + */ +__STATIC_INLINE uint32_t md_timer_get_output_compare2_mode_ch2omod(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, TIMER_CHMR1_CH2OMOD_POSS); +} + +/** + * @brief TIMER Set output compare 2 clear enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CH2O is not affected by the ETRF Input + * - 0x1: CH2O is cleared as soon as a High level is detected on ETRF input + * @retval None + */ +__STATIC_INLINE void md_timer_set_output_compare2_clear_enable_ch2oclren(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH2OCLREN_MSK, sel << TIMER_CHMR1_CH2OCLREN_POS); +} + +/** + * @brief TIMER Get output compare 2 clear enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CH2O is not affected by the ETRF Input + * - 0x1: CH2O is cleared as soon as a High level is detected on ETRF input + */ +__STATIC_INLINE uint32_t md_timer_is_output_compare2_clear_ch2oclren(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR1, TIMER_CHMR1_CH2OCLREN_MSK, TIMER_CHMR1_CH2OCLREN_POS); +} + +/** + * @brief TIMER Set input capture 1 prescaler + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: no prescaler + * - 0x1: capture is done once every 2 events + * - 0x2: capture is done once every 4 events + * - 0x3: capture is done once every 8 events + * @retval None + */ +__STATIC_INLINE void md_timer_set_input_capture1_prescaler_ic1pres(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_IC1PRES_MSK, sel << TIMER_CHMR1_IC1PRES_POSS); +} + +/** + * @brief TIMER Get input capture 1 prescaler + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: no prescaler + * - 0x1: capture is done once every 2 events + * - 0x2: capture is done once every 4 events + * - 0x3: capture is done once every 8 events + */ +__STATIC_INLINE uint32_t md_timer_get_input_capture1_prescaler_ic1pres(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR1, TIMER_CHMR1_IC1PRES_MSK, TIMER_CHMR1_IC1PRES_POSS); +} + +/** + * @brief TIMER Set input capture 1 filter + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: No filter, sampling is done at fDTS + * - 0x1: fSAMPLING=fCK_INT, N=2 + * - 0x2: fSAMPLING=fCK_INT, N=4 + * - 0x3: fSAMPLING=fCK_INT, N=8 + * - 0x4: fSAMPLING=fDTS/2, N=6 + * - 0x5: fSAMPLING=fDTS/2, N=8 + * - 0x6: fSAMPLING=fDTS/4, N=6 + * - 0x7: fSAMPLING=fDTS/4, N=8 + * - 0x8: fSAMPLING=fDTS/8, N=6 + * - 0x9: fSAMPLING=fDTS/8, N=8 + * - 0xa: fSAMPLING=fDTS/16, N=5 + * - 0xb: fSAMPLING=fDTS/16, N=6 + * - 0xc: fSAMPLING=fDTS/16, N=8 + * - 0xd: fSAMPLING=fDTS/32, N=5 + * - 0xe: fSAMPLING=fDTS/32, N=6 + * - 0xf: fSAMPLING=fDTS/32, N=8 + * @retval None + */ +__STATIC_INLINE void md_timer_set_input_capture1_filter_i1flt(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, sel << TIMER_CHMR1_I1FLT_POSS); +} + +/** + * @brief TIMER Set input capture 1 filter + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: No filter, sampling is done at fDTS + * - 0x1: fSAMPLING=fCK_INT, N=2 + * - 0x2: fSAMPLING=fCK_INT, N=4 + * - 0x3: fSAMPLING=fCK_INT, N=8 + * - 0x4: fSAMPLING=fDTS/2, N=6 + * - 0x5: fSAMPLING=fDTS/2, N=8 + * - 0x6: fSAMPLING=fDTS/4, N=6 + * - 0x7: fSAMPLING=fDTS/4, N=8 + * - 0x8: fSAMPLING=fDTS/8, N=6 + * - 0x9: fSAMPLING=fDTS/8, N=8 + * - 0xa: fSAMPLING=fDTS/16, N=5 + * - 0xb: fSAMPLING=fDTS/16, N=6 + * - 0xc: fSAMPLING=fDTS/16, N=8 + * - 0xd: fSAMPLING=fDTS/32, N=5 + * - 0xe: fSAMPLING=fDTS/32, N=6 + * - 0xf: fSAMPLING=fDTS/32, N=8 + */ +__STATIC_INLINE uint32_t md_timer_get_input_capture1_filter_i1flt(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, TIMER_CHMR1_I1FLT_POSS); +} + +/** + * @brief TIMER Set input capture 2 prescaler + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: no prescaler + * - 0x1: capture is done once every 2 events + * - 0x2: capture is done once every 4 events + * - 0x3: capture is done once every 8 events + * @retval None + */ +__STATIC_INLINE void md_timer_set_input_capture2_prescaler_ic2pres(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_IC2PRES_MSK, sel << TIMER_CHMR1_IC2PRES_POSS); +} + +/** + * @brief TIMER Get input capture 2 prescaler + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: no prescaler + * - 0x1: capture is done once every 2 events + * - 0x2: capture is done once every 4 events + * - 0x3: capture is done once every 8 events + */ +__STATIC_INLINE uint32_t md_timer_get_input_capture2_prescaler_ic2pres(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR1, TIMER_CHMR1_IC2PRES_MSK, TIMER_CHMR1_IC2PRES_POSS); +} + +/** + * @brief TIMER Set input capture 2 filter + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: No filter, sampling is done at fDTS + * - 0x1: fSAMPLING=fCK_INT, N=2 + * - 0x2: fSAMPLING=fCK_INT, N=4 + * - 0x3: fSAMPLING=fCK_INT, N=8 + * - 0x4: fSAMPLING=fDTS/2, N=6 + * - 0x5: fSAMPLING=fDTS/2, N=8 + * - 0x6: fSAMPLING=fDTS/4, N=6 + * - 0x7: fSAMPLING=fDTS/4, N=8 + * - 0x8: fSAMPLING=fDTS/8, N=6 + * - 0x9: fSAMPLING=fDTS/8, N=8 + * - 0xa: fSAMPLING=fDTS/16, N=5 + * - 0xb: fSAMPLING=fDTS/16, N=6 + * - 0xc: fSAMPLING=fDTS/16, N=8 + * - 0xd: fSAMPLING=fDTS/32, N=5 + * - 0xe: fSAMPLING=fDTS/32, N=6 + * - 0xf: fSAMPLING=fDTS/32, N=8 + * @retval None + */ +__STATIC_INLINE void md_timer_set_input_capture2_filter_i2flt(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, sel << TIMER_CHMR1_I2FLT_POSS); +} + +/** + * @brief TIMER Set input capture 2 filter + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: No filter, sampling is done at fDTS + * - 0x1: fSAMPLING=fCK_INT, N=2 + * - 0x2: fSAMPLING=fCK_INT, N=4 + * - 0x3: fSAMPLING=fCK_INT, N=8 + * - 0x4: fSAMPLING=fDTS/2, N=6 + * - 0x5: fSAMPLING=fDTS/2, N=8 + * - 0x6: fSAMPLING=fDTS/4, N=6 + * - 0x7: fSAMPLING=fDTS/4, N=8 + * - 0x8: fSAMPLING=fDTS/8, N=6 + * - 0x9: fSAMPLING=fDTS/8, N=8 + * - 0xa: fSAMPLING=fDTS/16, N=5 + * - 0xb: fSAMPLING=fDTS/16, N=6 + * - 0xc: fSAMPLING=fDTS/16, N=8 + * - 0xd: fSAMPLING=fDTS/32, N=5 + * - 0xe: fSAMPLING=fDTS/32, N=6 + * - 0xf: fSAMPLING=fDTS/32, N=8 + */ +__STATIC_INLINE uint32_t md_timer_get_input_capture2_filter_i2flt(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, TIMER_CHMR1_I2FLT_POSS); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group13 CHMR2 + * @{ + */ +/** + * @brief TIMER Set capture/compare 3 channel function selection + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CC1 channel is configured as output + * - 0x1: CC1 channel is configured as input, mapped on I3 + * - 0x2: CC1 channel is configured as input, mapped on I4 + * - 0x3: CC1 channel is configured as input, mapped on ITn or both edge of I1 + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc3_func_cc3ssel(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK, sel << TIMER_CHMR2_CC3SSEL_POSS); +} + +/** + * @brief TIMER Get capture/compare 3 channel function selection + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CC1 channel is configured as output + * - 0x1: CC1 channel is configured as input, mapped on I3 + * - 0x2: CC1 channel is configured as input, mapped on I4 + * - 0x3: CC1 channel is configured as input, mapped on ITn or both edge of I1 + */ +__STATIC_INLINE uint32_t md_timer_get_cc3_func_cc3ssel(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK, TIMER_CHMR2_CC3SSEL_POSS); +} + +/** + * @brief TIMER Set output Compare 3 fast enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CCVAL3 behaves normally depending on counter and CCRV3 values even when the trigger is ON + * - 0x1: An active edge on the trigger input acts like a compare match on CCVAL3 output. + * @retval None + */ +__STATIC_INLINE void md_timer_set_output_compare3_fast_enable_ch3ofen(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH3OFEN_MSK, sel << TIMER_CHMR2_CH3OFEN_POS); +} + +/** + * @brief TIMER Get output Compare 3 fast enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CCVAL3 behaves normally depending on counter and CCRV3 values even when the trigger is ON + * - 0x1: An active edge on the trigger input acts like a compare match on CCVAL3 output. + */ +__STATIC_INLINE uint32_t md_timer_is_output_compare3_fast_enable_ch3ofen(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR2, TIMER_CHMR2_CH3OFEN_MSK, TIMER_CHMR2_CH3OFEN_POS); +} + +/** + * @brief TIMER Set output Compare 3 preload enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: Preload register on TIMERn_CCVAL3 disabled + * - 0x1: Preload register on TIMERn_CCVAL3 enabled + * @retval None + */ +__STATIC_INLINE void md_timer_set_output_compare3_preload_enable_ch3open(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH3OPEN_MSK, sel << TIMER_CHMR2_CH3OPEN_POS); +} + +/** + * @brief TIMER Get output Compare 3 preload enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Preload register on TIMERn_CCVAL3 disabled + * - 0x1: Preload register on TIMERn_CCVAL3 enabled + */ +__STATIC_INLINE uint32_t md_timer_is_output_compare3_preload_enable_ch3open(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR2, TIMER_CHMR2_CH3OPEN_MSK, TIMER_CHMR2_CH3OPEN_POS); +} + +/** + * @brief TIMER Set Output Compare 3 mode + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: Frozen + * - 0x1: Set channel 3 to active level on match + * - 0x2: Set channel 3 to inactive level on match + * - 0x3: Toggle + * - 0x4: Force inactive level + * - 0x5: Force active level + * - 0x6: PWM mode 1 + * - 0x7: PWM mode 2 + * @retval None + */ +__STATIC_INLINE void md_timer_set_output_compare3_mode_ch3omod(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, sel << TIMER_CHMR2_CH3OMOD_POSS); +} + +/** + * @brief TIMER Set Output Compare 3 mode + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Frozen + * - 0x1: Set channel 3 to active level on match + * - 0x2: Set channel 3 to inactive level on match + * - 0x3: Toggle + * - 0x4: Force inactive level + * - 0x5: Force active level + * - 0x6: PWM mode 1 + * - 0x7: PWM mode 2 + */ +__STATIC_INLINE uint32_t md_timer_get_output_compare3_mode_ch3omod(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, TIMER_CHMR2_CH3OMOD_POSS); +} + +/** + * @brief TIMER Set output compare 3 clear enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CH3O is not affected by the ETRF Input + * - 0x1: CH3O is cleared as soon as a High level is detected on ETRF input + * @retval None + */ +__STATIC_INLINE void md_timer_set_output_compare3_clear_enable_ch3oclren(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH3OCLREN_MSK, sel << TIMER_CHMR2_CH3OCLREN_POS); +} + +/** + * @brief TIMER Get output compare 3 clear enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CH3O is not affected by the ETRF Input + * - 0x1: CH3O is cleared as soon as a High level is detected on ETRF input + */ +__STATIC_INLINE uint32_t md_timer_is_output_compare3_clear_enable_ch3oclren(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR2, TIMER_CHMR2_CH3OCLREN_MSK, TIMER_CHMR2_CH3OCLREN_POS); +} + +/** + * @brief TIMER Set capture/compare 4 channel function selection + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CC4 channel is configured as output + * - 0x1: CC4 channel is configured as input, mapped on I3 + * - 0x2: CC4 channel is configured as input, mapped on I4 + * - 0x3: CC4 channel is configured as input, mapped on ITn or both edge of I1 + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc4_func_cc4ssel(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK, sel << TIMER_CHMR2_CC4SSEL_POSS); +} + +/** + * @brief TIMER Get capture/compare 4 channel function selection + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CC4 channel is configured as output + * - 0x1: CC4 channel is configured as input, mapped on I3 + * - 0x2: CC4 channel is configured as input, mapped on I4 + * - 0x3: CC4 channel is configured as input, mapped on ITn or both edge of I1 + */ +__STATIC_INLINE uint32_t md_timer_get_cc4_func_cc4ssel(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK, TIMER_CHMR2_CC4SSEL_POSS); +} + +/** + * @brief TIMER Set output Compare 4 fast enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CCVAL4 behaves normally depending on counter and CCRV4 values even when the trigger is ON + * - 0x1: An active edge on the trigger input acts like a compare match on CCVAL4 output. + * @retval None + */ +__STATIC_INLINE void md_timer_set_output_compare4_fast_enable_ch4ohsen(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH4OHSEN_MSK, sel << TIMER_CHMR2_CH4OHSEN_POS); +} + +/** + * @brief TIMER Get output Compare 4 fast enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CCVAL4 behaves normally depending on counter and CCRV4 values even when the trigger is ON + * - 0x1: An active edge on the trigger input acts like a compare match on CCVAL4 output. + */ +__STATIC_INLINE uint32_t md_timer_is_output_compare4_fast_enable_ch4ohsen(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR2, TIMER_CHMR2_CH4OHSEN_MSK, TIMER_CHMR2_CH4OHSEN_POS); +} + +/** + * @brief TIMER Set output Compare 4 preload enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: Preload register on TIMERn_CCVAL4 disabled + * - 0x1: Preload register on TIMERn_CCVAL4 enabled + * @retval None + */ +__STATIC_INLINE void md_timer_set_output_compare4_preload_enable_ch4open(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH4OPEN_MSK, sel << TIMER_CHMR2_CH4OPEN_POS); +} + +/** + * @brief TIMER Get output Compare 4 preload enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Preload register on TIMERn_CCVAL4 disabled + * - 0x1: Preload register on TIMERn_CCVAL4 enabled + */ +__STATIC_INLINE uint32_t md_timer_is_output_compare4_preload_enable_ch4open(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR2, TIMER_CHMR2_CH4OPEN_MSK, TIMER_CHMR2_CH4OPEN_POS); +} + +/** + * @brief TIMER Set Output Compare 4 mode + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: Frozen + * - 0x1: Set channel 4 to active level on match + * - 0x2: Set channel 4 to inactive level on match + * - 0x3: Toggle + * - 0x4: Force inactive level + * - 0x5: Force active level + * - 0x6: PWM mode 1 + * - 0x7: PWM mode 2 + * @retval None + */ +__STATIC_INLINE void md_timer_set_output_compare4_mode_ch4omod(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, sel << TIMER_CHMR2_CH4OMOD_POSS); +} + +/** + * @brief TIMER Set Output Compare 4 mode + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Frozen + * - 0x1: Set channel 4 to active level on match + * - 0x2: Set channel 4 to inactive level on match + * - 0x3: Toggle + * - 0x4: Force inactive level + * - 0x5: Force active level + * - 0x6: PWM mode 1 + * - 0x7: PWM mode 2 + */ +__STATIC_INLINE uint32_t md_timer_get_output_compare4_mode_ch4omod(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, TIMER_CHMR2_CH4OMOD_POSS); +} + +/** + * @brief TIMER Set output compare 4 clear enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CH4O is not affected by the ETRF Input + * - 0x1: CH4O is cleared as soon as a High level is detected on ETRF input + * @retval None + */ +__STATIC_INLINE void md_timer_set_output_compare4_clear_enable_ch4oclren(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH4OCLREN_MSK, sel << TIMER_CHMR2_CH4OCLREN_POS); +} + +/** + * @brief TIMER Get output compare 4 clear enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CH4O is not affected by the ETRF Input + * - 0x1: CH4O is cleared as soon as a High level is detected on ETRF input + */ +__STATIC_INLINE uint32_t md_timer_is_output_compare4_clear_enable_ch4oclren(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR2, TIMER_CHMR2_CH4OCLREN_MSK, TIMER_CHMR2_CH4OCLREN_POS); +} + +/** + * @brief TIMER Set input capture 3 prescaler + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: no prescaler + * - 0x1: capture is done once every 2 events + * - 0x2: capture is done once every 4 events + * - 0x3: capture is done once every 8 events + * @retval None + */ +__STATIC_INLINE void md_timer_set_input_capture3_prescaler_ic3pres(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_IC3PRES_MSK, sel << TIMER_CHMR2_IC3PRES_POSS); +} + +/** + * @brief TIMER Get input capture 3 prescaler + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: no prescaler + * - 0x1: capture is done once every 2 events + * - 0x2: capture is done once every 4 events + * - 0x3: capture is done once every 8 events + */ +__STATIC_INLINE uint32_t md_timer_get_input_capture3_prescaler_ic3pres(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR2, TIMER_CHMR2_IC3PRES_MSK, TIMER_CHMR2_IC3PRES_POSS); +} + +/** + * @brief TIMER Set input capture 3 filter + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: No filter, sampling is done at fDTS + * - 0x1: fSAMPLING=fCK_INT, N=2 + * - 0x2: fSAMPLING=fCK_INT, N=4 + * - 0x3: fSAMPLING=fCK_INT, N=8 + * - 0x4: fSAMPLING=fDTS/2, N=6 + * - 0x5: fSAMPLING=fDTS/2, N=8 + * - 0x6: fSAMPLING=fDTS/4, N=6 + * - 0x7: fSAMPLING=fDTS/4, N=8 + * - 0x8: fSAMPLING=fDTS/8, N=6 + * - 0x9: fSAMPLING=fDTS/8, N=8 + * - 0xa: fSAMPLING=fDTS/16, N=5 + * - 0xb: fSAMPLING=fDTS/16, N=6 + * - 0xc: fSAMPLING=fDTS/16, N=8 + * - 0xd: fSAMPLING=fDTS/32, N=5 + * - 0xe: fSAMPLING=fDTS/32, N=6 + * - 0xf: fSAMPLING=fDTS/32, N=8 + * @retval None + */ +__STATIC_INLINE void md_timer_set_input_capture3_filter_i3flt(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I3FLT_MSK, sel << TIMER_CHMR2_I3FLT_POSS); +} + +/** + * @brief TIMER Get input capture 3 filter + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: No filter, sampling is done at fDTS + * - 0x1: fSAMPLING=fCK_INT, N=2 + * - 0x2: fSAMPLING=fCK_INT, N=4 + * - 0x3: fSAMPLING=fCK_INT, N=8 + * - 0x4: fSAMPLING=fDTS/2, N=6 + * - 0x5: fSAMPLING=fDTS/2, N=8 + * - 0x6: fSAMPLING=fDTS/4, N=6 + * - 0x7: fSAMPLING=fDTS/4, N=8 + * - 0x8: fSAMPLING=fDTS/8, N=6 + * - 0x9: fSAMPLING=fDTS/8, N=8 + * - 0xa: fSAMPLING=fDTS/16, N=5 + * - 0xb: fSAMPLING=fDTS/16, N=6 + * - 0xc: fSAMPLING=fDTS/16, N=8 + * - 0xd: fSAMPLING=fDTS/32, N=5 + * - 0xe: fSAMPLING=fDTS/32, N=6 + * - 0xf: fSAMPLING=fDTS/32, N=8 + */ +__STATIC_INLINE uint32_t md_timer_get_input_capture3_filter_i3flt(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR2, TIMER_CHMR2_I3FLT_MSK, TIMER_CHMR2_I3FLT_POSS); +} + +/** + * @brief TIMER Set input capture 4 prescaler + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: no prescaler + * - 0x1: capture is done once every 2 events + * - 0x2: capture is done once every 4 events + * - 0x3: capture is done once every 8 events + * @retval None + */ +__STATIC_INLINE void md_timer_set_input_capture4_prescaler_ic4pres(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_IC4PRES_MSK, sel << TIMER_CHMR2_IC4PRES_POSS); +} + +/** + * @brief TIMER Get input capture 4 prescaler + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: no prescaler + * - 0x1: capture is done once every 2 events + * - 0x2: capture is done once every 4 events + * - 0x3: capture is done once every 8 events + */ +__STATIC_INLINE uint32_t md_timer_get_input_capture4_prescaler_ic4pres(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR2, TIMER_CHMR2_IC4PRES_MSK, TIMER_CHMR2_IC4PRES_POSS); +} + +/** + * @brief TIMER Set input capture 4 filter + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: No filter, sampling is done at fDTS + * - 0x1: fSAMPLING=fCK_INT, N=2 + * - 0x2: fSAMPLING=fCK_INT, N=4 + * - 0x3: fSAMPLING=fCK_INT, N=8 + * - 0x4: fSAMPLING=fDTS/2, N=6 + * - 0x5: fSAMPLING=fDTS/2, N=8 + * - 0x6: fSAMPLING=fDTS/4, N=6 + * - 0x7: fSAMPLING=fDTS/4, N=8 + * - 0x8: fSAMPLING=fDTS/8, N=6 + * - 0x9: fSAMPLING=fDTS/8, N=8 + * - 0xa: fSAMPLING=fDTS/16, N=5 + * - 0xb: fSAMPLING=fDTS/16, N=6 + * - 0xc: fSAMPLING=fDTS/16, N=8 + * - 0xd: fSAMPLING=fDTS/32, N=5 + * - 0xe: fSAMPLING=fDTS/32, N=6 + * - 0xf: fSAMPLING=fDTS/32, N=8 + * @retval None + */ +__STATIC_INLINE void md_timer_set_input_capture4_filter_i4flt(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I4FLT_MSK, sel << TIMER_CHMR2_I4FLT_POSS); +} + +/** + * @brief TIMER Set input capture 4 filter + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: No filter, sampling is done at fDTS + * - 0x1: fSAMPLING=fCK_INT, N=2 + * - 0x2: fSAMPLING=fCK_INT, N=4 + * - 0x3: fSAMPLING=fCK_INT, N=8 + * - 0x4: fSAMPLING=fDTS/2, N=6 + * - 0x5: fSAMPLING=fDTS/2, N=8 + * - 0x6: fSAMPLING=fDTS/4, N=6 + * - 0x7: fSAMPLING=fDTS/4, N=8 + * - 0x8: fSAMPLING=fDTS/8, N=6 + * - 0x9: fSAMPLING=fDTS/8, N=8 + * - 0xa: fSAMPLING=fDTS/16, N=5 + * - 0xb: fSAMPLING=fDTS/16, N=6 + * - 0xc: fSAMPLING=fDTS/16, N=8 + * - 0xd: fSAMPLING=fDTS/32, N=5 + * - 0xe: fSAMPLING=fDTS/32, N=6 + * - 0xf: fSAMPLING=fDTS/32, N=8 + */ +__STATIC_INLINE uint32_t md_timer_get_input_capture4_filter_i4flt(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CHMR2, TIMER_CHMR2_I4FLT_MSK, TIMER_CHMR2_I4FLT_POSS); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group14 CCEP + * @{ + */ +/** + * @brief TIMER Set capture/compare 1 output enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: Off - CH1O is not active + * - 0x1: On - CH1O signal is output on the corresponding output pin depending on GOEN, OFFSSI, + * OFFSSR, OISS1, OISS1N and CC1EN bits. + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc1_output_enable_cc1en(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, sel << TIMER_CCEP_CC1EN_POS); +} + +/** + * @brief TIMER Get capture/compare 1 output enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Off - CH1O is not active + * - 0x1: On - CH1O signal is output on the corresponding output pin depending on GOEN, OFFSSI, + * OFFSSR, OISS1, OISS1N and CC1EN bits. + */ +__STATIC_INLINE uint32_t md_timer_is_cc1_output_enable_cc1en(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, TIMER_CCEP_CC1EN_POS); +} + +/** + * @brief TIMER Set capture/compare 1 input enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: capture disabled + * - 0x1: capture enabled + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc1_input_enable_cc1en(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, sel << TIMER_CCEP_CC1EN_POS); +} + +/** + * @brief TIMER Get capture/compare 1 output enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Off - CH1O is not active + * - 0x1: On - CH1O signal is output on the corresponding output pin depending on GOEN, OFFSSI, + * OFFSSR, OISS1, OISS1N and CC1EN bits. + */ +__STATIC_INLINE uint32_t md_timer_is_cc1_input_enable_cc1en(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, TIMER_CCEP_CC1EN_POS); +} + +/** + * @brief TIMER Set capture/compare 1 output polarity + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: OC1 active high + * - 0x1: OC1 active low + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc1_output_polarity_cc1pol(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, sel << TIMER_CCEP_CC1POL_POS); +} + +/** + * @brief TIMER Get capture/compare 1 output polarity + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: OC1 active high + * - 0x1: OC1 active low + */ +__STATIC_INLINE uint32_t md_timer_get_cc1_output_polarity_cc1pol(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_CCEP_CC1POL_POS); +} + +/** + * @brief TIMER Set capture/compare 1 input edge + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: non-inverted: capture is done on a rising edge of I1 + * - 0x1: inverted: capture is done on a falling edge of I1 + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc1_input_edge_cc1pol(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, sel << TIMER_CCEP_CC1POL_POS); +} + +/** + * @brief TIMER Get capture/compare 1 input edge + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: non-inverted: capture is done on a rising edge of I1 + * - 0x1: inverted: capture is done on a falling edge of I1 + */ +__STATIC_INLINE uint32_t md_timer_get_cc1_input_edge_cc1pol(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_CCEP_CC1POL_POS); +} + +/** + * @brief TIMER Set capture/compare 1 complementary output enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: Off-CH1ON is not active + * - 0x1: On-OC1N signal is output on the corresponding output pin depending on GOEN, OFFSSI, + * OFFSSR, OISS1, OISS1N and CC1EN bits. + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc1_complementary_enable_cc1nen(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NE_MSK, sel << TIMER_CCEP_CC1NE_POS); +} + +/** + * @brief TIMER Set capture/compare 1 complementary output enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Off-CH1ON is not active + * - 0x1: On-OC1N signal is output on the corresponding output pin depending on GOEN, OFFSSI, + * OFFSSR, OISS1, OISS1N and CC1EN bits. + */ +__STATIC_INLINE uint32_t md_timer_get_cc1_complementary_enable_cc1nen(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC1NE_MSK, TIMER_CCEP_CC1NE_POS); +} + +/** + * @brief TIMER Set capture/compare 1 complementary output polarity + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CH1ON active high + * - 0x1: CH1ON active low + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc1_complementary_polarity_cc1npol(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NE_MSK, sel << TIMER_CCEP_CC1NE_POS); +} + +/** + * @brief TIMER Set capture/compare 1 complementary output enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CH1ON active high + * - 0x1: CH1ON active low + */ +__STATIC_INLINE uint32_t md_timer_get_cc1_complementary_polarity_cc1npol(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC1NE_MSK, TIMER_CCEP_CC1NE_POS); +} + +/** + * @brief TIMER Set capture/compare 2 output enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: Off - CH2O is not active + * - 0x1: On - CH2O signal is output on the corresponding output pin depending on GOEN, OFFSSI, + * OFFSSR, OISS2, OISS2N and CC2EN bits. + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc2_output_enable_cc2en(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, sel << TIMER_CCEP_CC2EN_POS); +} + +/** + * @brief TIMER Get capture/compare 2 output enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Off - CH1O is not active + * - 0x1: On - CH1O signal is output on the corresponding output pin depending on GOEN, OFFSSI, + * OFFSSR, OISS2, OISS2N and CC2EN bits. + */ +__STATIC_INLINE uint32_t md_timer_is_cc2_output_enable_cc2en(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, TIMER_CCEP_CC2EN_POS); +} + +/** + * @brief TIMER Set capture/compare 2 input enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: capture disabled + * - 0x1: capture enabled + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc2_input_enable_cc2en(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, sel << TIMER_CCEP_CC2EN_POS); +} + +/** + * @brief TIMER Get capture/compare 2 output enable + * @param TIMERx TIMER Instance + * @retval sel The value of following: + * - 0x0: Off - CH1O is not active + * - 0x1: On - CH1O signal is output on the corresponding output pin depending on GOEN, OFFSSI, + * OFFSSR, OISS2, OISS2N and CC2EN bits. + */ +__STATIC_INLINE uint32_t md_timer_is_cc2_input_enable_cc2en(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, TIMER_CCEP_CC2EN_POS); +} + +/** + * @brief TIMER Set capture/compare 2 output polarity + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CHO2 active high + * - 0x1: CHO2 active low + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc2_output_polarity_cc2pol(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, sel << TIMER_CCEP_CC2POL_POS); +} + +/** + * @brief TIMER Get capture/compare 2 output polarity + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CHO2 active high + * - 0x1: CHO2 active low + */ +__STATIC_INLINE uint32_t md_timer_get_cc2_output_polarity_cc2pol(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_CCEP_CC2POL_POS); +} + +/** + * @brief TIMER Set capture/compare 2 input edge + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: non-inverted: capture is done on a rising edge of I2 + * - 0x1: inverted: capture is done on a falling edge of I2 + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc2_input_edge_cc2pol(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, sel << TIMER_CCEP_CC2POL_POS); +} + +/** + * @brief TIMER Get capture/compare 2 input edge + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: non-inverted: capture is done on a rising edge of I2 + * - 0x1: inverted: capture is done on a falling edge of I2 + */ +__STATIC_INLINE uint32_t md_timer_get_cc2_input_edge_cc2pol(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_CCEP_CC2POL_POS); +} + +/** + * @brief TIMER Set capture/compare 2 complementary output enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: Off-CH2ON is not active + * - 0x1: On-CH2ON signal is output on the corresponding output pin depending on GOEN, OFFSSI, + * OFFSSR, OISS2, OISS2N and CC2EN bits. + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc2_complementary_enable_cc2nen(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NE_MSK, sel << TIMER_CCEP_CC2NE_POS); +} + +/** + * @brief TIMER Set capture/compare 2 complementary output enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Off-CH2ON is not active + * - 0x1: On-CH2ON signal is output on the corresponding output pin depending on GOEN, OFFSSI, + * OFFSSR, OISS2, OISS2N and CC2EN bits. + */ +__STATIC_INLINE uint32_t md_timer_get_cc2_complementary_enable_cc2nen(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC2NE_MSK, TIMER_CCEP_CC2NE_POS); +} + +/** + * @brief TIMER Set capture/compare 2 complementary output polarity + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0:CH2ON active high + * - 0x1:CH2ON active low + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc2_complementary_polarity_cc2npol(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NE_MSK, sel << TIMER_CCEP_CC2NE_POS); +} + +/** + * @brief TIMER Set capture/compare 2 complementary output enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0:CH2ON active high + * - 0x1:CH2ON active low + */ +__STATIC_INLINE uint32_t md_timer_get_cc2_complementary_polarity_cc2npol(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC2NE_MSK, TIMER_CCEP_CC2NE_POS); +} +/** + * @brief TIMER Set capture/compare 3 output enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: Off - CH3O is not active + * - 0x1: On - CH3O signal is output on the corresponding output pin depending on GOEN, OFFSSI, + * OFFSSR, OISS3, OISS3N and CC3EN bits. + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc3_output_enable_cc3en(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, sel << TIMER_CCEP_CC3EN_POS); +} + +/** + * @brief TIMER Get capture/compare 3 output enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Off - CH3O is not active + * - 0x1: On - CH3O signal is output on the corresponding output pin depending on GOEN, OFFSSI, + * OFFSSR, OISS3, OISS3N and CC3EN bits. + */ +__STATIC_INLINE uint32_t md_timer_is_cc3_output_enable_cc3en(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, TIMER_CCEP_CC3EN_POS); +} + +/** + * @brief TIMER Set capture/compare 3 input enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: capture disabled + * - 0x1: capture enabled + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc3_input_enable_cc3en(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, sel << TIMER_CCEP_CC3EN_POS); +} + +/** + * @brief TIMER Get capture/compare 3 output enable + * @param TIMERx TIMER Instance + * @retval sel The value of following: + * - 0x0: Off - CH1O is not active + * - 0x1: On - CH1O signal is output on the corresponding output pin depending on GOEN, OFFSSI, + * OFFSSR, OISS3, OISS3N and CC3EN bits. + */ +__STATIC_INLINE uint32_t md_timer_is_cc3_input_enable_cc3en(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, TIMER_CCEP_CC3EN_POS); +} + +/** + * @brief TIMER Set capture/compare 3 output polarity + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CHO3 active high + * - 0x1: CHO3 active low + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc3_output_polarity_cc3pol(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, sel << TIMER_CCEP_CC3POL_POS); +} + +/** + * @brief TIMER Get capture/compare 3 output polarity + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CHO3 active high + * - 0x1: CHO3 active low + */ +__STATIC_INLINE uint32_t md_timer_get_cc3_output_polarity_cc3pol(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, TIMER_CCEP_CC3POL_POS); +} + +/** + * @brief TIMER Set capture/compare 3 input edge + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: non-inverted: capture is done on a rising edge of I3 + * - 0x1: inverted: capture is done on a falling edge of I3 + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc3_input_edge_cc3pol(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, sel << TIMER_CCEP_CC3POL_POS); +} + +/** + * @brief TIMER Get capture/compare 3 input edge + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: non-inverted: capture is done on a rising edge of I3 + * - 0x1: inverted: capture is done on a falling edge of I3 + */ +__STATIC_INLINE uint32_t md_timer_get_cc3_input_edge_cc3pol(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, TIMER_CCEP_CC3POL_POS); +} + +/** + * @brief TIMER Set capture/compare 3 complementary output enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: Off-CH3ON is not active + * - 0x1: On-CH3ON signal is output on the corresponding output pin depending on GOEN, OFFSSI, + * OFFSSR, OISS3, OISS3N and CC3EN bits. + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc3_complementary_enable_cc3nen(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NE_MSK, sel << TIMER_CCEP_CC3NE_POS); +} + +/** + * @brief TIMER Set capture/compare 3 complementary output enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Off-CH3ON is not active + * - 0x1: On-CH3ON signal is output on the corresponding output pin depending on GOEN, OFFSSI, + * OFFSSR, OISS3, OISS3N and CC3EN bits. + */ +__STATIC_INLINE uint32_t md_timer_get_cc3_complementary_enable_cc3nen(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC3NE_MSK, TIMER_CCEP_CC3NE_POS); +} + +/** + * @brief TIMER Set capture/compare 3 complementary output polarity + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0:CH3ON active high + * - 0x1:CH3ON active low + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc3_complementary_polarity_cc3npol(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NE_MSK, sel << TIMER_CCEP_CC3NE_POS); +} + +/** + * @brief TIMER Set capture/compare 3 complementary output enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0:CH3ON active high + * - 0x1:CH3ON active low + */ +__STATIC_INLINE uint32_t md_timer_get_cc3_complementary_polarity_cc3npol(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC3NE_MSK, TIMER_CCEP_CC3NE_POS); +} + +/** + * @brief TIMER Set capture/compare 4 output enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: Off - CH4O is not active + * - 0x1: On - CH4O signal is output on the corresponding output pin depending on GOEN, OFFSSI, + * OFFSSR, OISS4, OISS4N and CC4EN bits. + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc4_output_enable_cc4en(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, sel << TIMER_CCEP_CC4EN_POS); +} + +/** + * @brief TIMER Get capture/compare 4 output enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Off - CH4O is not active + * - 0x1: On - CH4O signal is output on the corresponding output pin depending on GOEN, OFFSSI, + * OFFSSR, OISS4, OISS4N and CC3EN bits. + */ +__STATIC_INLINE uint32_t md_timer_is_cc4_output_enable_cc4en(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, TIMER_CCEP_CC4EN_POS); +} + +/** + * @brief TIMER Set capture/compare 4 input enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: capture disabled + * - 0x1: capture enabled + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc4_input_enable_cc4en(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, sel << TIMER_CCEP_CC4EN_POS); +} + +/** + * @brief TIMER Get capture/compare 4 output enable + * @param TIMERx TIMER Instance + * @retval sel The value of following: + * - 0x0: Off - CH1O is not active + * - 0x1: On - CH1O signal is output on the corresponding output pin depending on GOEN, OFFSSI, + * OFFSSR, OISS4, OISS4N and CC4EN bits. + */ +__STATIC_INLINE uint32_t md_timer_is_cc4_input_enable_cc4en(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, TIMER_CCEP_CC4EN_POS); +} + +/** + * @brief TIMER Set capture/compare 4 output polarity + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CHO4 active high + * - 0x1: CHO4 active low + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc4_output_polarity_cc4pol(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, sel << TIMER_CCEP_CC4POL_POS); +} + +/** + * @brief TIMER Get capture/compare 4 output polarity + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CHO4 active high + * - 0x1: CHO4 active low + */ +__STATIC_INLINE uint32_t md_timer_get_cc4_output_polarity_cc4pol(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, TIMER_CCEP_CC4POL_POS); +} + +/** + * @brief TIMER Set capture/compare 4 input edge + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: non-inverted: capture is done on a rising edge of I4 + * - 0x1: inverted: capture is done on a falling edge of I4 + * @retval None + */ +__STATIC_INLINE void md_timer_set_cc4_input_edge_cc4pol(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, sel << TIMER_CCEP_CC4POL_POS); +} + +/** + * @brief TIMER Get capture/compare 4 input edge + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: non-inverted: capture is done on a rising edge of I4 + * - 0x1: inverted: capture is done on a falling edge of I4 + */ +__STATIC_INLINE uint32_t md_timer_get_cc4_input_edge_cc4pol(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, TIMER_CCEP_CC3POL_POS); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group15 COUNT + * @{ + */ +/** + * @brief TIMER Set counter value + * @param TIMERx TIMER Instance + * @param val Counter value + * @retval None + */ +__STATIC_INLINE void md_timer_set_counter_value_cntv(TIMER_TypeDef *TIMERx, uint32_t val) +{ + MODIFY_REG(TIMERx->COUNT, TIMER_COUNT_CNTV_MSK, val << TIMER_COUNT_CNTV_POSS); +} + +/** + * @brief TIMER Get counter value + * @param TIMERx TIMER Instance + * @retval counter value + */ +__STATIC_INLINE uint32_t md_timer_get_counter_value_cntv(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->COUNT, TIMER_COUNT_CNTV_MSK, TIMER_COUNT_CNTV_POSS); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group16 PRES + * @{ + */ +/** + * @brief TIMER Set Prescaler value + * @param TIMERx TIMER Instance + * @param val Prescaler value + * @retval None + */ +__STATIC_INLINE void md_timer_set_prescaler_value_pscv(TIMER_TypeDef *TIMERx, uint32_t val) +{ + MODIFY_REG(TIMERx->PRES, TIMER_PRES_PSCV_MSK, val << TIMER_PRES_PSCV_POSS); +} + +/** + * @brief TIMER Get counter value + * @param TIMERx TIMER Instance + * @retval prescaler value + */ +__STATIC_INLINE uint32_t md_timer_get_prescaler_value_pscv(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->PRES, TIMER_PRES_PSCV_MSK, TIMER_PRES_PSCV_POSS); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group17 AR + * @{ + */ +/** + * @brief TIMER Set auto-reload value + * @param TIMERx TIMER Instance + * @param val Auto-reload value + * @retval None + */ +__STATIC_INLINE void md_timer_set_auto_reload_value_arrv(TIMER_TypeDef *TIMERx, uint32_t val) +{ + MODIFY_REG(TIMERx->AR, TIMER_AR_ARRV_MSK, val << TIMER_AR_ARRV_POSS); +} + +/** + * @brief TIMER Get auto-reload value + * @param TIMERx TIMER Instance + * @retval auto-reload value + */ +__STATIC_INLINE uint32_t md_timer_get_auto_reload_value_arrv(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->AR, TIMER_AR_ARRV_MSK, TIMER_AR_ARRV_POSS); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group18 REPAR + * @{ + */ +/** + * @brief TIMER Set repetition counter value + * @param TIMERx TIMER Instance + * @param val Repetition counter value + * @retval None + */ +__STATIC_INLINE void md_timer_set_repetition_counter_value_repv(TIMER_TypeDef *TIMERx, uint32_t val) +{ + MODIFY_REG(TIMERx->REPAR, TIMER_REPAR_REPV_MSK, val << TIMER_REPAR_REPV_POSS); +} + +/** + * @brief TIMER Get repetition counter value + * @param TIMERx TIMER Instance + * @retval repetition counter value + */ +__STATIC_INLINE uint32_t md_timer_get_repetition_counter_value_repv(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->REPAR, TIMER_REPAR_REPV_MSK, TIMER_REPAR_REPV_POSS); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group19 CCVAL1 + * @{ + */ +/** + * @brief TIMER Set capture/compare 1 value + * @param TIMERx TIMER Instance + * @param val Value + * @retval None + */ +__STATIC_INLINE void md_timer_set_capture_compare1_value_ccrv1(TIMER_TypeDef *TIMERx, uint32_t val) +{ + MODIFY_REG(TIMERx->CCVAL1, TIMER_CCVAL1_CCRV1_MSK, val << TIMER_CCVAL1_CCRV1_POSS); +} + +/** + * @brief TIMER Get capture/compare 1 value + * @param TIMERx TIMER Instance + * @retval value + */ +__STATIC_INLINE uint32_t md_timer_get_capture_compare1_value_ccrv1(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCVAL1, TIMER_CCVAL1_CCRV1_MSK, TIMER_CCVAL1_CCRV1_POSS); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group20 CCVAL2 + * @{ + */ +/** + * @brief TIMER Set capture/compare 2 value + * @param TIMERx TIMER Instance + * @param val Value + * @retval None + */ +__STATIC_INLINE void md_timer_set_capture_compare2_value_ccrv2(TIMER_TypeDef *TIMERx, uint32_t val) +{ + MODIFY_REG(TIMERx->CCVAL2, TIMER_CCVAL2_CCRV2_MSK, val << TIMER_CCVAL2_CCRV2_POSS); +} +/** + * @brief TIMER Get capture/compare 2 value + * @param TIMERx TIMER Instance + * @retval value + */ +__STATIC_INLINE uint32_t md_timer_get_capture_compare2_value_ccrv2(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCVAL2, TIMER_CCVAL2_CCRV2_MSK, TIMER_CCVAL2_CCRV2_POSS); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group21 CCVAL3 + * @{ + */ +/** + * @brief TIMER Set capture/compare 3 value + * @param TIMERx TIMER Instance + * @param val Value + * @retval None + */ +__STATIC_INLINE void md_timer_set_capture_compare3_value_ccrv3(TIMER_TypeDef *TIMERx, uint32_t val) +{ + MODIFY_REG(TIMERx->CCVAL3, TIMER_CCVAL3_CCRV3_MSK, val << TIMER_CCVAL3_CCRV3_POSS); +} +/** + * @brief TIMER Get capture/compare 3 value + * @param TIMERx TIMER Instance + * @retval value + */ +__STATIC_INLINE uint32_t md_timer_get_capture_compare3_value_ccrv3(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCVAL3, TIMER_CCVAL3_CCRV3_MSK, TIMER_CCVAL3_CCRV3_POSS); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group22 CCVAL4 + * @{ + */ +/** + * @brief TIMER Set capture/compare 4 value + * @param TIMERx TIMER Instance + * @param val Value + * @retval None + */ +__STATIC_INLINE void md_timer_set_capture_compare4_value_ccrv4(TIMER_TypeDef *TIMERx, uint32_t val) +{ + MODIFY_REG(TIMERx->CCVAL4, TIMER_CCVAL4_CCRV4_MSK, val << TIMER_CCVAL4_CCRV4_POSS); +} +/** + * @brief TIMER Get capture/compare 4 value + * @param TIMERx TIMER Instance + * @retval value + */ +__STATIC_INLINE uint32_t md_timer_get_capture_compare4_value_ccrv4(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->CCVAL4, TIMER_CCVAL4_CCRV4_MSK, TIMER_CCVAL4_CCRV4_POSS); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group23 BDCFG + * @{ + */ +/** + * @brief TIMER Set dead-time generator setup + * @param TIMERx TIMER Instance + * @param val Value + * @retval None + */ +__STATIC_INLINE void md_timer_set_dead_time_duration_dt(TIMER_TypeDef *TIMERx, uint32_t val) +{ + MODIFY_REG(TIMERx->BDCFG, TIMER_BDCFG_DT_MSK, val << TIMER_BDCFG_DT_POSS); +} +/** + * @brief TIMER Set dead-time generator setup + * @param TIMERx TIMER Instance + * @retval value + */ +__STATIC_INLINE uint32_t md_timer_get_dead_time_duration_dt(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->BDCFG, TIMER_BDCFG_DT_MSK, TIMER_BDCFG_DT_POSS); +} + +/** + * @brief TIMER Set lock configuration + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: LOCK OFF + * - 0x1: LOCK Level 1 + * - 0x2: LOCK Level 2 + * - 0x3: LOCK Level 3 + * @retval None + */ +__STATIC_INLINE void md_timer_set_lock_config_locklvl(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->BDCFG, TIMER_BDCFG_LOCKLVL_MSK, sel << TIMER_BDCFG_LOCKLVL_POSS); +} + +/** + * @brief TIMER Get lock configuration + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: LOCK OFF + * - 0x1: LOCK Level 1 + * - 0x2: LOCK Level 2 + * - 0x3: LOCK Level 3 + */ +__STATIC_INLINE uint32_t md_timer_get_lock_config_locklvl(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->BDCFG, TIMER_BDCFG_LOCKLVL_MSK, TIMER_BDCFG_LOCKLVL_POSS); +} + +/** + * @brief TIMER Set Off-state selection for Idle mode + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: When inactive, OC/OCN outputs are disabled + * - 0x1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCnEN=1 or + * CCnNEN=1. OC/OCN enable output signal=1) + * @retval None + */ +__STATIC_INLINE void md_timer_set_offstate_idle_selection_offssi(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->BDCFG, TIMER_BDCFG_OFFSSI_MSK, sel << TIMER_BDCFG_OFFSSI_POS); +} + +/** + * @brief TIMER Get Off-state selection for Idle mode + * @param TIMERx TIMER Instance + * @retval sel The value of following: + * - 0x0: When inactive, OC/OCN outputs are disabled + * - 0x1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCnEN=1 or + * CCnNEN=1. CHO/CHON enable output signal=1) + */ +__STATIC_INLINE uint32_t md_timer_get_offstate_idle_selection_offssi(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->BDCFG, TIMER_BDCFG_OFFSSI_MSK, TIMER_BDCFG_OFFSSI_POS); +} + +/** + * @brief TIMER SetOff-state selection for Run mode + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: When inactive, OC/OCN outputs are disabled + * - 0x1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCnEN=1 + * or CCnNEN=1. Then, OC/OCN enable output signal=1 + * @retval None + */ +__STATIC_INLINE void md_timer_set_offstate_run_selection_offssr(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->BDCFG, TIMER_BDCFG_OFFSSR_MSK, sel << TIMER_BDCFG_OFFSSR_POS); +} + +/** + * @brief TIMER SetOff-state selection for Run mode + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: When inactive, OC/OCN outputs are disabled + * - 0x1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCnEN=1 + * or CCnNEN=1. Then, OC/OCN enable output signal=1 + */ +__STATIC_INLINE uint32_t md_timer_get_offstate_run_selection_offssr(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->BDCFG, TIMER_BDCFG_OFFSSR_MSK, TIMER_BDCFG_OFFSSR_POS); +} + +/** + * @brief TIMER Enable break + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_break_brken(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->BDCFG, TIMER_BDCFG_BRKEN_MSK); +} + +/** + * @brief TIMER Disable break + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_break_brken(TIMER_TypeDef *TIMERx) +{ + CLEAR_BIT(TIMERx->BDCFG, TIMER_BDCFG_BRKEN_MSK); +} + +/** + * @brief TIMER Check if break enable + * @param TIMERx TIMER Instance + * @retval Status: + * - 0: DISABLE + * - 1: ENABLE + */ +__STATIC_INLINE uint32_t md_timer_is_break_enable_brken(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->BDCFG, TIMER_BDCFG_BRKEN_MSK, TIMER_BDCFG_BRKEN_POS); +} + +/** + * @brief TIMER Set break polarity + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: Break input BRK is active low + * - 0x1: Break input BRK is active high + * @retval None + */ +__STATIC_INLINE void md_timer_set_break_polarity_brkp(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->BDCFG, TIMER_BDCFG_BRKP_MSK, sel << TIMER_BDCFG_BRKP_POS); +} + +/** + * @brief TIMER Get break polarity + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: Break input BRK is active low + * - 0x1: Break input BRK is active high + */ +__STATIC_INLINE uint32_t md_timer_get_break_polarity_brkp(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->BDCFG, TIMER_BDCFG_BRKP_MSK, TIMER_BDCFG_BRKP_POS); +} + +/** + * @brief TIMER Set automatic output enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: GOEN can be set only by software + * - 0x1: GOEN can be set by software or automatically at the next update event + * @retval None + */ +__STATIC_INLINE void md_timer_set_auto_output_enable(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->BDCFG, TIMER_BDCFG_AOEN_MSK, sel << TIMER_BDCFG_AOEN_POS); +} + +/** + * @brief TIMER Get automatic output enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: GOEN can be set only by software + * - 0x1: GOEN can be set by software or automatically at the next update event + */ +__STATIC_INLINE uint32_t md_timer_get_auto_output_enable(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->BDCFG, TIMER_BDCFG_AOEN_MSK, TIMER_BDCFG_AOEN_POS); +} + +/** + * @brief TIMER Set main output enable + * @param TIMERx TIMER Instance + * @param sel The value of following: + * - 0x0: CHO and CHON outputs are disabled or forced to idle state. + * - 0x1: CHO and CHON outputs are enabled if their respective enable bits are set + * @retval None + */ +__STATIC_INLINE void md_timer_set_main_output_enable(TIMER_TypeDef *TIMERx, uint32_t sel) +{ + MODIFY_REG(TIMERx->BDCFG, TIMER_BDCFG_GOEN_MSK, sel << TIMER_BDCFG_GOEN_POS); +} + +/** + * @brief TIMER Get main output enable + * @param TIMERx TIMER Instance + * @retval The value of following: + * - 0x0: CHO and CHON outputs are disabled or forced to idle state. + * - 0x1: CHO and CHON outputs are enabled if their respective enable bits are set + */ +__STATIC_INLINE uint32_t md_timer_get_main_output_enable(TIMER_TypeDef *TIMERx) +{ + return READ_BITS(TIMERx->BDCFG, TIMER_BDCFG_GOEN_MSK, TIMER_BDCFG_GOEN_POS); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group24 DMAEN + * @{ + */ +/** + * @brief TIMER Enable update DMA request enable + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_udma(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->DMAEN, TIMER_DMAEN_UDS_MSK); +} + +/** + * @brief TIMER Enable capture/compare 1 DMA request + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_cc1dma(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->DMAEN, TIMER_DMAEN_CC1DS_MSK); +} + +/** + * @brief TIMER Enable capture/compare 2 DMA request + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_cc2dma(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->DMAEN, TIMER_DMAEN_CC2DS_MSK); +} + +/** + * @brief TIMER Enable capture/compare 3 DMA request + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_cc3dma(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->DMAEN, TIMER_DMAEN_CC3DS_MSK); +} + +/** + * @brief TIMER Enable capture/compare 4 DMA request + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_cc4dma(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->DMAEN, TIMER_DMAEN_CC4DS_MSK); +} + +/** + * @brief TIMER Enable COM DMA request + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_comdma(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->DMAEN, TIMER_DMAEN_COMDS_MSK); +} + +/** + * @brief TIMER Enable trigger DMA request + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_enable_trgdma(TIMER_TypeDef *TIMERx) +{ + SET_BIT(TIMERx->DMAEN, TIMER_DMAEN_TDS_MSK); +} + +/** + * @brief TIMER Disable update DMA request + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_udma(TIMER_TypeDef *TIMERx) +{ + CLEAR_BIT(TIMERx->DMAEN, TIMER_DMAEN_UDS_MSK); +} + +/** + * @brief TIMER Disable capture/compare 1 DMA request + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_cc1dma(TIMER_TypeDef *TIMERx) +{ + CLEAR_BIT(TIMERx->DMAEN, TIMER_DMAEN_CC1DS_MSK); +} + +/** + * @brief TIMER Disable capture/compare 2 DMA request + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_cc2dma(TIMER_TypeDef *TIMERx) +{ + CLEAR_BIT(TIMERx->DMAEN, TIMER_DMAEN_CC2DS_MSK); +} + +/** + * @brief TIMER Disable capture/compare 3 DMA request + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_cc3dma(TIMER_TypeDef *TIMERx) +{ + CLEAR_BIT(TIMERx->DMAEN, TIMER_DMAEN_CC3DS_MSK); +} + +/** + * @brief TIMER Disable capture/compare 4 DMA request + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_cc4dma(TIMER_TypeDef *TIMERx) +{ + CLEAR_BIT(TIMERx->DMAEN, TIMER_DMAEN_CC4DS_MSK); +} + +/** + * @brief TIMER Disable COM DMA request + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_comdma(TIMER_TypeDef *TIMERx) +{ + CLEAR_BIT(TIMERx->DMAEN, TIMER_DMAEN_COMDS_MSK); +} + +/** + * @brief TIMER Disable trigger DMA request + * @param TIMERx TIMER Instance + * @retval None + */ +__STATIC_INLINE void md_timer_disable_trgdma(TIMER_TypeDef *TIMERx) +{ + CLEAR_BIT(TIMERx->DMAEN, TIMER_DMAEN_TDS_MSK); +} +/** + * @} + */ +/** @defgroup MD_TIMER_Public_Functions_Group1 Initialization + * @{ + */ + +void md_timer_base_struct_init(md_timer_base_init_t *timer_init_struct); +void md_timer_base_set_config(TIMER_TypeDef *TIMERx, md_timer_base_init_t *init); +void md_timer_ic_struct_init(md_timer_ic_init_t *init); +md_status_t md_timer_ic_init(TIMER_TypeDef *TIMERx, md_timer_channel_t Channel, md_timer_ic_init_t *init); +void md_timer_oc_struct_init(md_timer_oc_init_t *timer_oc_init_struct); +md_status_t md_timer_oc_init(TIMER_TypeDef *TIMERx, md_timer_channel_t channel, md_timer_oc_init_t *timer_oc_init_struct); +void timer_encoder_struct_init(md_timer_encoder_init_t *init); +md_status_t timer_encoder_init(TIMER_TypeDef *TIMERx, md_timer_encoder_init_t *init); +void timer_hallsensor_struct_init(md_timer_hall_sensor_init_t *init); +md_status_t timer_hallsensor_init(TIMER_TypeDef *TIMERx, md_timer_hall_sensor_init_t *init); +void timer_bdtr_struct_init(md_timer_break_dead_time_t *init); +md_status_t timer_bdtr_init(TIMER_TypeDef *TIMERx, md_timer_break_dead_time_t *init); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __MD_TIMER_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_uart.c b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_uart.c new file mode 100644 index 0000000000..ab92915e14 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_uart.c @@ -0,0 +1,153 @@ +/********************************************************************************** + * + * @file md_uart.c + * @brief UART module driver. + * + * @date 12 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 12 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_uart.h" +#include "md_cmu.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ + +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @addtogroup MD_UART + * @{ + */ +/** @addtogroup MD_UART_Public_Functions + * @{ + */ +/** @addtogroup MD_UART_Public_Functions_Group1 + * @{ + */ +/** + * @brief Reset UART peripheral + * @param UARTx: UART peripheral + * @retval None + */ +void md_uart_reset(UART_TypeDef *UARTx) +{ + WRITE_REG(UARTx->BRR, 0x0); + WRITE_REG(UARTx->LCON, 0x0); + WRITE_REG(UARTx->MCON, 0x0); + WRITE_REG(UARTx->RS485, 0x0); + WRITE_REG(UARTx->SCARD, 0x0); + WRITE_REG(UARTx->LIN, 0x0); + WRITE_REG(UARTx->RTOR, 0x0); + WRITE_REG(UARTx->IDR, 0xFFF); +} + +/** + * @brief Initializes the UARTx according to the specified + * parameters in the uart_init_t. + * @param UARTx: UART peripheral + * @param init: Pointer to a md_uart_init_t structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +void md_uart_init(UART_TypeDef *UARTx, md_uart_init_t *init) +{ + uint32_t brr = 0U; + brr = md_cmu_get_pclk_clock(); + brr = (brr + (init->baud >> 1)) / init->baud; + + md_uart_reset(UARTx); + + md_uart_set_datawidth(UARTx, init->word_length); + md_uart_set_stop(UARTx, init->stop_bits); + + md_uart_set_parity(UARTx, init->parity); + + if (init->fctl) + { + md_uart_enable_auto_flow(UARTx); + } + else + { + md_uart_disable_auto_flow(UARTx); + } + + md_uart_set_baudrate(UARTx, brr); + + if (init->mode == MD_UART_MODE_LIN) + md_uart_enable_lin_mode(UARTx); + else if (init->mode == MD_UART_MODE_IRDA) + md_uart_enable_irda(UARTx); + else if (init->mode == MD_UART_MODE_RS485) + md_uart_enable_aaden(UARTx); + else if (init->mode == MD_UART_MODE_HDSEL) + md_uart_enable_half_duplex(UARTx); + else + ; /* do nothing */ + + md_uart_enable_tx(UARTx); + md_uart_enable_rx(UARTx); + + return; +} + +/** + * @brief Initialize the UARTx peripheral using the default parameters. + * @param init: Pointer to a md_uart_init_t structure + * @retval None + */ +void md_uart_init_struct(md_uart_init_t *init) +{ + init->baud = 115200; + init->word_length = MD_UART_WORD_LENGTH_8B; + init->stop_bits = MD_UART_STOP_BITS_1; + init->parity = MD_UART_PARITY_NONE; + init->fctl = MD_UART_FLOW_CTL_DISABLE; + init->mode = MD_UART_MODE; + + return; +} +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_uart.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_uart.h new file mode 100644 index 0000000000..4f0237043c --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_uart.h @@ -0,0 +1,2658 @@ +/********************************************************************************** + * + * @file md_usart.h + * @brief Header file of USART module driver. + * + * @date 12 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 12 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + + +#ifndef __MD_UART_H__ +#define __MD_UART_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_utils.h" + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Variables -------------------------------------------------------- */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ +/** @defgroup MD_UART UART + * @brief UART micro driver + * @{ + */ +/** + * @defgroup MD_UART_Public_Macros UART Public Macros + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** + * @brief UART mode + */ +typedef enum +{ + MD_UART_MODE = 0x0U, /**< UART */ + MD_UART_MODE_IRDA = 0x1U, /**< IrDA */ + MD_UART_MODE_LIN = 0x2U, /**< LIN */ + MD_UART_MODE_RS485 = 0x3U, /**< RS485 */ + MD_UART_MODE_HDSEL = 0x4U, /**< Single-wire half-duplex */ + MD_UART_MODE_SCARD = 0x5U, /**< Smart card */ +} md_uart_mode_t; + +/** + * @brief UART word length + */ +typedef enum +{ + MD_UART_WORD_LENGTH_5B = 0x3U, /**< 5-bits */ + MD_UART_WORD_LENGTH_6B = 0x2U, /**< 6-bits */ + MD_UART_WORD_LENGTH_7B = 0x1U, /**< 7-bits */ + MD_UART_WORD_LENGTH_8B = 0x0U, /**< 8-bits */ +} md_uart_word_length_t; + +/** + * @brief UART stop bits + */ +typedef enum +{ + MD_UART_STOP_BITS_1 = 0x0U, /**< 1-bits */ + MD_UART_STOP_BITS_2 = 0x4U, /**< 2-bits */ + MD_UART_STOP_BITS_0_5 = 0x0U, /**< 0.5-bits, using smartcard mode */ + MD_UART_STOP_BITS_1_5 = 0x4U, /**< 1.5-bits, using smartcard mode */ +} md_uart_stop_bits_t; + +/** + * @brief UART parity + */ +typedef enum +{ + MD_UART_PARITY_NONE = 0x0U, /**< Not parity */ + MD_UART_PARITY_ODD = 0x8U, /**< Odd parity */ + MD_UART_PARITY_EVEN = 0x18U, /**< Even parity */ +} md_uart_parity_t; + +/** + * @brief UART hardware flow control + */ +typedef enum +{ + MD_UART_FLOW_CTL_DISABLE = 0x0U, /**< Auto-flow-control disable */ + MD_UART_FLOW_CTL_ENABLE = 0x4U, /**< Auto-flow-control enable */ +} md_uart_flow_ctl_t; + +/** + * @brief Smart_card clock division + */ +typedef enum +{ + MD_SCARD_CLOCK_DIV1 = 0x0U, /**< No prescaler is used */ + MD_SCARD_CLOCK_DIV2 = 0x1U, /** Clock is divided by 2 */ + MD_SCARD_CLOCK_DIV4 = 0x2U, /** Clock is divided by 4 */ + MD_SCARD_CLOCK_DIV6 = 0x3U, /** Clock is divided by 6 */ +} md_scard_clk_div_t; + +/** + * @brief Smart_card Rx/Tx handle retry time + */ +typedef enum +{ + MD_SCARD_RETRY_CNT0 = 0x0U, /**< retry time 0 */ + MD_SCARD_RETRY_CNT1 = 0x1U, /**< retry time 1 */ + MD_SCARD_RETRY_CNT2 = 0x2U, /**< retry time 2 */ + MD_SCARD_RETRY_CNT3 = 0x3U, /**< retry time 3 */ + MD_SCARD_RETRY_CNT4 = 0x4U, /**< retry time 4 */ + MD_SCARD_RETRY_CNT5 = 0x5U, /**< retry time 5 */ + MD_SCARD_RETRY_CNT6 = 0x6U, /**< retry time 6 */ + MD_SCARD_RETRY_CNT7 = 0x7U, /**< retry time 7 */ +} md_scard_retry_t; + +/** + * @brief LIN detection break length + */ +typedef enum +{ + MD_LIN_BREAK_LEN_10B = 0x0U, /**< 10-bit break */ + MD_LIN_BREAK_LEN_11B = 0x1U, /**< 11-bit break */ +} md_uart_lin_break_len_t; + +/** + * @brief UART TXFIFO size + */ +typedef enum +{ + MD_UART_TXFIFO_EMPTY = 0x0U, /**< Empty */ + MD_UART_TXFIFO_2BYTE = 0x1U, /**< 2-Bytes */ + MD_UART_TXFIFO_4BYTE = 0x2U, /**< 4-Bytes */ + MD_UART_TXFIFO_8BYTE = 0x3U, /**< 8-Bytes */ +} md_uart_txfifo_t; + +/** + * @brief UART RXFIFO size + */ +typedef enum +{ + MD_UART_RXFIFO_1BYTE = 0x0U, /**< 1-Byte */ + MD_UART_RXFIFO_4BYTE = 0x1U, /**< 4-Bytes */ + MD_UART_RXFIFO_8BYTE = 0x2U, /**< 8-Bytes */ + MD_UART_RXFIFO_14BYTE = 0x3U, /**< 14-Bytes */ +} md_uart_rxfifo_t; + +/** + * @brief UART auto-baud mode + */ +typedef enum +{ + MD_UART_ABRMOD_1_TO_0 = 0x0U, /**< Detect bit0:1, bit1:0 */ + MD_UART_ABRMOD_1 = 0x1U, /**< Detect bit0:1 */ + MD_UART_ABRMOD_0_TO_1 = 0x2U, /**< Detect bit0:0, bit1:1 */ +} md_uart_auto_baud_mode_t; + +/** + * @brief UART DMA Requests + */ +typedef enum +{ + MD_UART_DMA_REQ_TX = 0x0U, /**< TX dma */ + MD_UART_DMA_REQ_RX = 0x1U, /**< RX dma */ +} md_uart_dma_req_t; + +/** + * @brief UART status types + */ +typedef enum +{ + MD_UART_STATUS_PERR = (1U << 0), /**< Parity error */ + MD_UART_STATUS_FERR = (1U << 1), /**< Framing error */ + MD_UART_STATUS_BKERR = (1U << 2), /**< Break error */ + MD_UART_STATUS_CTSSTA = (1U << 3), /**< Clear to send status */ + MD_UART_STATUS_RSBUSY = (1U << 8), /**< Receive shif register busy */ + MD_UART_STATUS_RFTH = (1U << 9), /**< Receive FIFO trigger threshold */ + MD_UART_STATUS_RFEMPTY = (1U << 10), /**< Receive FIFO empty */ + MD_UART_STATUS_RFFULL = (1U << 11), /**< Receive FIFO full */ + MD_UART_STATUS_RFOERR = (1U << 12), /**< Reveive FIFO overrun error */ + MD_UART_STATUS_RFUERR = (1U << 13), /**< Receive FIFO underrun error */ + MD_UART_STATUS_TSBUSY = (1U << 14), /**< Transmit shit register busy */ + MD_UART_STATUS_TFTH = (1U << 15), /**< Transmit FIFO trigger threshold */ + MD_UART_STATUS_TFEMPTY = (1U << 16), /**< Transmit FIFO empty */ + MD_UART_STATUS_TFFULL = (1U << 17), /**< Transmit FIFO full */ + MD_UART_STATUS_TFOERR = (1U << 18), /**< Transmit FIFO overrun error */ +} md_uart_status_t; + +/** + * @brief UART interrupt types + */ +typedef enum +{ + MD_UART_IT_RXBERR = (1U << 0), /**< Receiver byte error */ + MD_UART_IT_ABEND = (1U << 1), /**< Auto-Baud rate detection end */ + MD_UART_IT_ABTO = (1U << 2), /**< Auto-Baud rate detection timeout */ + MD_UART_IT_DCTS = (1U << 3), /**< Delta CTS status */ + MD_UART_IT_RXTO = (1U << 4), /**< Receiver timeout */ + MD_UART_IT_ADDRM = (1U << 5), /**< Addredd match */ + MD_UART_IT_LINBK = (1U << 6), /**< Lin break detection */ + MD_UART_IT_EOB = (1U << 7), /**< End of block */ + MD_UART_IT_NOISE = (1U << 8), /**< Start bit noise detection */ + MD_UART_IT_RFTH = (1U << 9), /**< Receive FIFO trigger threshold */ + MD_UART_IT_RFFULL = (1U << 11), /**< Receive FIFO full */ + MD_UART_IT_RFOERR = (1U << 12), /**< Receive FIFO overrun */ + MD_UART_IT_RFUERR = (1U << 13), /**< Reveive FIFO underrun */ + MD_UART_IT_TSEMPTY = (1U << 14), /**< Transmit shift register empty */ + MD_UART_IT_TFTH = (1U << 15), /**< Transmit FIFO trigger threshold */ + MD_UART_IT_TFEMPTY = (1U << 16), /**< Transmit FIFO empty */ + MD_UART_IT_TFOVER = (1U << 18), /**< Transmit FIFO overrun */ +} md_uart_it_t; + +/** + * @brief UART flags types + */ +typedef enum +{ + MD_UART_IF_RXBERR = (1U << 0), /**< Receiver byte error */ + MD_UART_IF_ABEND = (1U << 1), /**< Auto-Baud rate detection end */ + MD_UART_IF_ABTO = (1U << 2), /**< Auto-Baud rate detection timeout */ + MD_UART_IF_DCTS = (1U << 3), /**< Delta CTS status */ + MD_UART_IF_RXTO = (1U << 4), /**< Receiver timeout */ + MD_UART_IF_ADDRM = (1U << 5), /**< Addredd match */ + MD_UART_IF_LINBK = (1U << 6), /**< Lin break detection */ + MD_UART_IF_EOB = (1U << 7), /**< End of block */ + MD_UART_IF_NOISE = (1U << 8), /**< Start bit noise detection */ + MD_UART_IF_RFTH = (1U << 9), /**< Receive FIFO trigger threshold */ + MD_UART_IF_RFFULL = (1U << 11), /**< Receive FIFO full */ + MD_UART_IF_RFOERR = (1U << 12), /**< Receive FIFO overrun */ + MD_UART_IF_RFUERR = (1U << 13), /**< Reveive FIFO underrun */ + MD_UART_IF_TBC = (1U << 14), /**< Transmit shift register empty */ + MD_UART_IF_TFTH = (1U << 15), /**< Transmit FIFO trigger threshold */ + MD_UART_IF_TFEMPTY = (1U << 16), /**< Transmit FIFO empty */ + MD_UART_IF_TFOVER = (1U << 18), /**< Transmit FIFO overrun */ +} md_uart_flag_t; +/** + * @} + */ +/** + * @defgroup MD_UART_Public_Types UART Public Types + * @{ + */ +/** + * @brief UART init structure definition + */ +typedef struct +{ + uint32_t baud; /**< Specifies the uart communication baud rate */ + md_uart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */ + md_uart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */ + md_uart_parity_t parity; /**< Specifies the parity mode */ + md_uart_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */ + md_uart_mode_t mode; /**< Specifies the uart mode */ +} md_uart_init_t; +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @defgroup MD_UART_Public_Functions UART Public Functions + * @{ + */ +/** @defgroup MD_UART_Public_Functions_Group2 RXBUF + * @{ + */ +/** + * @brief Read 8-Bits in the data register + * @param UARTx UART Instance + * @retval Data Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t md_uart_recv_data8(UART_TypeDef *UARTx) +{ + return (uint8_t)(READ_REG(UARTx->RXBUF)); +} + +/** + * @brief Read 9-Bits in the data register + * @param UARTx UART Instance + * @retval Data Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t md_uart_recv_data9(UART_TypeDef *UARTx) +{ + return (uint16_t)(READ_REG(UARTx->RXBUF)); +} +/** + * @} + */ +/** @defgroup MD_UART_Public_Functions_Group3 TXBUF + * @{ + */ +/** + * @brief Write data in the data register + * @param UARTx UART Instance + * @param data Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void md_uart_set_send_data9(UART_TypeDef *UARTx, uint16_t data) +{ + WRITE_REG(UARTx->TXBUF, data); +} + +/** + * @brief Write data in the data register + * @param UARTx UART Instance + * @param data Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void md_uart_set_send_data8(UART_TypeDef *UARTx, uint8_t data) +{ + WRITE_REG(UARTx->TXBUF, data); +} + +/** + * @brief Read 8-Bits in the tx data register + * @param UARTx UART Instance + * @retval Data Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t md_uart_get_send_data8(UART_TypeDef *UARTx) +{ + return (uint8_t)(READ_REG(UARTx->TXBUF)); +} + +/** + * @brief Read 9-Bits in the tx data register + * @param UARTx UART Instance + * @retval Data Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t md_uart_get_send_data9(UART_TypeDef *UARTx) +{ + return (uint16_t)(READ_REG(UARTx->TXBUF)); +} +/** + * @} + */ +/** @defgroup MD_UART_Public_Functions_Group4 BRR + * @{ + */ +/** + * @brief Set UART baud rate + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @param buadrate UART buad rate value + * @retval None + */ +__STATIC_INLINE void md_uart_set_baudrate(UART_TypeDef *UARTx, uint32_t buadrate) +{ + WRITE_REG(UARTx->BRR, buadrate); +} + +/** + * @brief Get UART baud rate + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @retval buadrate UART buad rate value + */ +__STATIC_INLINE uint32_t md_uart_get_baudrate(UART_TypeDef *UARTx) +{ + return (READ_REG(UARTx->BRR)); +} +/** + * @} + */ +/** @defgroup MD_UART_Public_Functions_Group5 LCON + * @{ + */ +/** + * @brief UART Tx Enable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_tx(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_TXEN_MSK); +} + +/** + * @brief UART Tx Disable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_tx(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_TXEN_MSK); +} + +/** + * @brief Indicate if UART Tx is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_tx(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->LCON, UART_LCON_TXEN_MSK) == (UART_LCON_TXEN_MSK)); +} + +/** + * @brief UART Rx Enable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_rx(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_RXEN_MSK); +} + +/** + * @brief UART Rx Disable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_rx(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_RXEN_MSK); +} + +/** + * @brief Indicate if UART Rx is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_rx(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->LCON, UART_LCON_RXEN_MSK) == (UART_LCON_RXEN_MSK)); +} + +/** + * @brief UART Rx filter Enable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_dbcen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_DBCEN_MSK); +} + +/** + * @brief UART Rx filter Disable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_dbcen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_DBCEN_MSK); +} + +/** + * @brief Indicate if UART Rx filter is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_dbcen(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->LCON, UART_LCON_DBCEN_MSK) == (UART_LCON_DBCEN_MSK)); +} + +/** + * @brief UART Break Enable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_break(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_BREAK_MSK); +} + +/** + * @brief UART Break Disable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_break(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_BREAK_MSK); +} + +/** + * @brief Indicate if UART break is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_break(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->LCON, UART_LCON_BREAK_MSK) == (UART_LCON_BREAK_MSK)); +} + +/** + * @brief Enable UART swap TX/RX pins + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_swap(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_SWAP_MSK); +} + +/** + * @brief Disable UART swap TX/RX pins + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_swap(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_SWAP_MSK); +} + +/** + * @brief Indicate if UART TX/RX pins is swaped + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_swap(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->LCON, UART_LCON_SWAP_MSK) == (UART_LCON_SWAP_MSK)); +} + +/** + * @brief Enable UART TX pin active level inversion + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_txinv(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_TXINV_MSK); +} + +/** + * @brief Disable UART TX pin active level inversion + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_txinv(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_TXINV_MSK); +} + +/** + * @brief Indicate if UART TX pin active level is invered + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_txinv(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_TXINV_MSK) == (UART_LCON_TXINV_MSK)); +} + +/** + * @brief Enable UART RX pin active level inversion + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_rxinv(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_RXINV_MSK); +} + +/** + * @brief Disable UART RX pin active level inversion + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_rxinv(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_RXINV_MSK); +} + +/** + * @brief Indicate if UART RX pin active level is invered + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_rxinv(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_RXINV_MSK) == (UART_LCON_RXINV_MSK)); +} + +/** + * @brief Enable UART Binary data inversion + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_datainv(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_DATAINV_MSK); +} + +/** + * @brief Disable UART Binary data inversion + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_datainv(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_DATAINV_MSK); +} + +/** + * @brief Indicate if UART Binary data is invered + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_datainv(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_DATAINV_MSK) == (UART_LCON_DATAINV_MSK)); +} + +/** + * @brief Set UART Binary data bit order LSB first + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_set_bitorder_lsb(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_MSB_MSK); +} + +/** + * @brief Set UART Binary data bit order MSB first + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_set_bitorder_msb(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_MSB_MSK); +} + +/** + * @brief Get UART Binary data bit order + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @retval The retval: + * - 0: LSB first + * - 0: MSB first + */ +__STATIC_INLINE uint32_t md_uart_get_bitorder(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->LCON, UART_LCON_MSB_MSK) == (UART_LCON_MSB_MSK)); +} + +/** + * @brief Set UART data parity + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @param parity This parameter can be one of the following values: + * @arg @ref MD_UART_PARITY_NONE + * @arg @ref MD_UART_PARITY_ODD + * @arg @ref MD_UART_PARITY_EVEN + * @retval None + */ +__STATIC_INLINE void md_uart_set_parity(UART_TypeDef *UARTx, uint32_t parity) +{ + MODIFY_REG(UARTx->LCON, UART_LCON_PE_MSK | UART_LCON_PS_MSK, parity); +} + +/** + * @brief Get UART data parity + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_UART_PARITY_NONE + * @arg @ref MD_UART_PARITY_ODD + * @arg @ref MD_UART_PARITY_EVEN + */ +__STATIC_INLINE uint32_t md_uart_get_parity(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->LCON, UART_LCON_PE_MSK | UART_LCON_PS_MSK)); +} + +/** + * @brief Set UART data stop bit + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @param stop This parameter can be one of the following values: + * @arg @ref MD_UART_STOP_BITS_1 + * @arg @ref MD_UART_STOP_BITS_2 + * @retval None + */ +__STATIC_INLINE void md_uart_set_stop(UART_TypeDef *UARTx, uint32_t stop) +{ + MODIFY_REG(UARTx->LCON, UART_LCON_STOP_MSK, stop); +} + +/** + * @brief Get UART data stop bit + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_UART_STOP_BITS_1 + * @arg @ref MD_UART_STOP_BITS_2 + */ +__STATIC_INLINE uint32_t md_uart_get_stop(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->LCON, UART_LCON_STOP_MSK)); +} + + +/** + * @brief Set UART data width + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @param width This parameter can be one of the following values: + * @arg @ref MD_UART_WORD_LENGTH_5B + * @arg @ref MD_UART_WORD_LENGTH_6B + * @arg @ref MD_UART_WORD_LENGTH_7B + * @arg @ref MD_UART_WORD_LENGTH_8B + * @retval None + */ +__STATIC_INLINE void md_uart_set_datawidth(UART_TypeDef *UARTx, uint32_t width) +{ + MODIFY_REG(UARTx->LCON, UART_LCON_DLS_MSK, width); +} + +/** + * @brief Get UART data width + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_UART_WORD_LENGTH_5B + * @arg @ref MD_UART_WORD_LENGTH_6B + * @arg @ref MD_UART_WORD_LENGTH_7B + * @arg @ref MD_UART_WORD_LENGTH_8B + */ +__STATIC_INLINE uint32_t md_uart_get_datawidth(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->LCON, UART_LCON_DLS_MSK)); +} +/** + * @} + */ +/** @defgroup MD_UART_Public_Functions_Group6 MCON + * @{ + */ + +/** + * @brief Enable TXFLOAT + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_txfloat(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_TXFLOAT_MSK); +} + +/** + * @brief Disable TXFLOAT + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_txfloat(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_TXFLOAT_MSK); +} + +/** + * @brief Check if TXFLOAT is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_txfloat(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->MCON, UART_MCON_TXFLOAT_MSK) == (UART_MCON_TXFLOAT_MSK)); +} + +/** + * @brief Enable TXDMA request + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_txdma(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_TXDMAEN_MSK); +} + +/** + * @brief Disable TXDMA request + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_txdma(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_TXDMAEN_MSK); +} + +/** + * @brief Check if TXDMA request is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_txdma(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->MCON, UART_MCON_TXDMAEN_MSK) == (UART_MCON_TXDMAEN_MSK)); +} + +/** + * @brief Enable RXDMA request + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_rxdma(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_RXDMAEN_MSK); +} + +/** + * @brief Disable RXDMA request + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_rxdma(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_RXDMAEN_MSK); +} + +/** + * @brief Check if RXDMA request is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_rxdma(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->MCON, UART_MCON_RXDMAEN_MSK) == (UART_MCON_RXDMAEN_MSK)); +} + +/** + * @brief UART auto baud rate detection repeat Enable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_abrrept(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_ABRREPT_MSK); +} + +/** + * @brief UART auto baud rate detection repeat Disable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_abrrept(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_ABRREPT_MSK); +} + +/** + * @brief Indicate if UART auto baud rate detection repeat is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_abrrept(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_ABRREPT_MSK) == (UART_MCON_ABRREPT_MSK)); +} + +/** + * @brief Set UART auto baud-rate mode + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @param mode This parameter can be one of the following values: + * - 0: MODE0 + * - 1: MODE1 + * - 2: MODE2 + * @retval None + */ +__STATIC_INLINE void md_uart_set_abrmod(UART_TypeDef *UARTx, uint32_t mode) +{ + MODIFY_REG(UARTx->MCON, UART_MCON_ABRMOD_MSK, mode << UART_MCON_ABRMOD_POSS); +} + +/** + * @brief Get UART auto baud-rate mode + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance + * @retval The retval can be one of the following values: + * - 0: MODE0 + * - 1: MODE1 + * - 2: MODE2 + */ +__STATIC_INLINE uint32_t md_uart_get_abrmod(UART_TypeDef *UARTx) +{ + return READ_BITS(UARTx->MCON, UART_MCON_ABRMOD_MSK, UART_MCON_ABRMOD_POSS); +} + +/** + * @brief Enable auto-baud + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_abr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_ABREN_MSK); +} + +/** + * @brief Disable auto-baud + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_abr(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_ABREN_MSK); +} + +/** + * @brief Indicate if auto-baud is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_abr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->MCON, UART_MCON_ABREN_MSK) == (UART_MCON_ABREN_MSK)); +} + +/** + * @brief Send UART LIN mode break request + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_trigger_break_request(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_BKREQ_MSK); +} + +/** + * @brief UART half-duplex Enable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_half_duplex(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_HDEN_MSK); +} + +/** + * @brief UART half-duplex Disable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_half_duplex(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_HDEN_MSK); +} + +/** + * @brief Indicate if UART half-duplex is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_half_duplex(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_HDEN_MSK) == (UART_MCON_HDEN_MSK)); +} + +/** + * @brief UART Irda Enable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_irda(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_IREN_MSK); +} + +/** + * @brief UART Irda Disable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_irda(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_IREN_MSK); +} + +/** + * @brief Indicate if UART Irda is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_irda(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_IREN_MSK) == (UART_MCON_IREN_MSK)); +} + +/** + * @brief UART auto flow control Enable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_auto_flow(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_AFCEN_MSK); +} + +/** + * @brief UART auto flow control Disable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_auto_flow(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_AFCEN_MSK); +} + +/** + * @brief Indicate if UART auto flow control is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_auto_flow(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_AFCEN_MSK) == (UART_MCON_AFCEN_MSK)); +} + +/** + * @brief Set UART RTSn pin level + * @note This bit is set and cleared by software when auto flow disabled + * @param UARTx UART Instance + * @param level This parameter can be one of the following values: + * - 1: Low level + * - 0: High level + * @retval None + */ +__STATIC_INLINE void md_uart_set_rtsset(UART_TypeDef *UARTx, uint32_t level) +{ + MODIFY_REG(UARTx->MCON, UART_MCON_RTSSET_MSK, level << UART_MCON_RTSSET_POS); +} + +/** + * @brief Get UART RTSn pin level + * @param UARTx UART Instance + * @retval The retval can be one of the following values: + * - 0: Low level + * - 1: High level + */ +__STATIC_INLINE uint32_t md_uart_get_rtsset(UART_TypeDef *UARTx) +{ + return READ_BITS(UARTx->MCON, UART_MCON_RTSSET_MSK, UART_MCON_RTSSET_POS); +} + +/** + * @brief UART loopback mode Enable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_loopback(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_LPBKEN_MSK); +} + +/** + * @brief UART loopback mode Disable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_loopback(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_LPBKEN_MSK); +} + +/** + * @brief Indicate if UART loopback mode is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_loopback(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_LPBKEN_MSK) == (UART_MCON_LPBKEN_MSK)); +} +/** + * @} + */ +/** @defgroup MD_UART_Public_Functions_Group7 RS485 + * @{ + */ +/** + * @brief Set UART direction control RTSn delay value + * @param UARTx UART Instance + * @param delay UART direction control RTSn delay value + * @retval None + */ +__STATIC_INLINE void md_uart_set_rs485_dly(UART_TypeDef *UARTx, uint32_t delay) +{ + MODIFY_REG(UARTx->RS485, UART_RS485_DLY_MSK, delay << UART_RS485_DLY_POSS); +} + +/** + * @brief Get UART direction control RTSn delay value + * @param UARTx UART Instance + * @retval UART delay value + */ +__STATIC_INLINE uint32_t md_uart_get_rs485_dly(UART_TypeDef *UARTx) +{ + return READ_BITS(UARTx->RS485, UART_RS485_DLY_MSK, UART_RS485_DLY_POSS); +} + +/** + * @brief Set UART RS485 address value + * @param UARTx UART Instance + * @param address UART match address value + * @retval None + */ +__STATIC_INLINE void md_uart_set_rs485_addr(UART_TypeDef *UARTx, uint32_t address) +{ + MODIFY_REG(UARTx->RS485, UART_RS485_ADDR_MSK, address << UART_RS485_ADDR_POSS); +} + +/** + * @brief Get UART RS485 address value + * @param UARTx UART Instance + * @retval UART match address value + */ +__STATIC_INLINE uint32_t md_uart_get_rs485_addr(UART_TypeDef *UARTx) +{ + return (READ_BITS(UARTx->RS485, UART_RS485_ADDR_MSK, UART_RS485_ADDR_POSS)); +} + +/** + * @brief Set UART RS485 automatic address detection invertion + * @param UARTx UART Instance + * @param aadinv can be one of the following value: + * - 0: Low + * - 0: High + * @retval None + */ +__STATIC_INLINE void md_uart_set_rs485_auto_addr_invert(UART_TypeDef *UARTx, uint32_t aadinv) +{ + MODIFY_REG(UARTx->RS485, UART_RS485_AADINV_MSK, aadinv << UART_RS485_AADINV_POS); +} + +/** + * @brief Get UART RS485 automatic address detection invertion + * @param UARTx UART Instance + * @retval The status. + */ +__STATIC_INLINE uint32_t md_uart_get_rs485_auto_addr_invert(UART_TypeDef *UARTx) +{ + return READ_BITS(UARTx->RS485, UART_RS485_AADINV_MSK, UART_RS485_AADINV_POS); +} + +/** + * @brief UART auto direction mode Enable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_auto_dir_mode(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->RS485, UART_RS485_AADACEN_MSK); +} + +/** + * @brief UART auto direction mode Disable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_auto_dir_mode(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->RS485, UART_RS485_AADACEN_MSK); +} + +/** + * @brief Indicate if auto direction mode is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_auto_dir_mode(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->RS485, UART_RS485_AADACEN_MSK) == (UART_RS485_AADACEN_MSK)); +} + +/** + * @brief UART auto address detection normal mode Enable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_autoaddr_normal_mode(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->RS485, UART_RS485_AADNEN_MSK); +} + +/** + * @brief UART auto address detection normal mode Disable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_autoaddr_normal_mode(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->RS485, UART_RS485_AADNEN_MSK); +} + +/** + * @brief Indicate if auto address detection normal mode is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_autoaddr_normal_mode(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->RS485, UART_RS485_AADNEN_MSK) == (UART_RS485_AADNEN_MSK)); +} + +/** + * @brief UART auto bit_addr detect Enable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_aaden(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->RS485, UART_RS485_AADEN_MSK); +} + +/** + * @brief UART auto bit_addr detect Disable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_aaden(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->RS485, UART_RS485_AADEN_MSK); +} + +/** + * @brief Indicate if auto bit_addr detect is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_aaden(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->RS485, UART_RS485_AADEN_MSK) == (UART_RS485_AADEN_MSK)); +} +/** + * @} + */ +/** @defgroup MD_UART_Public_Functions_Group8 SCARD + * @{ + */ +/** + * @brief Set UART receive data block length. + * @param UARTx UART Instance + * @param len length of data block + * @retval None + */ +__STATIC_INLINE void md_uart_set_rx_data_block_length(UART_TypeDef *UARTx, uint32_t len) +{ + MODIFY_REG(UARTx->SCARD, UART_SCARD_BLEN_MSK, len << UART_SCARD_BLEN_POSS); +} + +/** + * @brief Get UART receive data block length. + * @param UARTx UART Instance + * @retval length of receive data block + */ +__STATIC_INLINE uint32_t md_uart_get_rx_data_block_length(UART_TypeDef *UARTx) +{ + return READ_BITS(UARTx->SCARD, UART_SCARD_BLEN_MSK, UART_SCARD_BLEN_POSS); +} + +/** + * @brief Set UART Smartcard protect time. + * @param UARTx UART Instance + * @param tim time of Smartcard protect time. + * @retval None + */ +__STATIC_INLINE void md_uart_set_scard_gt(UART_TypeDef *UARTx, uint32_t tim) +{ + MODIFY_REG(UARTx->SCARD, UART_SCARD_GT_MSK, tim << UART_SCARD_GT_POSS); +} + +/** + * @brief Get UART Smartcard protect time. + * @param UARTx UART Instance + * @retval Smartcard protect time + */ +__STATIC_INLINE uint32_t md_uart_get_scard_gt(UART_TypeDef *UARTx) +{ + return READ_BITS(UARTx->SCARD, UART_SCARD_GT_MSK, UART_SCARD_GT_POSS); +} + +/** + * @brief Set UART Smartcard prescaler clock. + * @param UARTx UART Instance + * @param pre prescaler clock value. + * @retval None + */ +__STATIC_INLINE void md_uart_set_scard_psc(UART_TypeDef *UARTx, uint32_t pre) +{ + MODIFY_REG(UARTx->SCARD, UART_SCARD_PSC_MSK, pre << UART_SCARD_PSC_POSS); +} + +/** + * @brief Get UART Smartcard protect time. + * @param UARTx UART Instance + * @retval Smartcard protect time + */ +__STATIC_INLINE uint32_t md_uart_get_scard_sccnt(UART_TypeDef *UARTx) +{ + return READ_BITS(UARTx->SCARD, UART_SCARD_PSC_MSK, UART_SCARD_PSC_POSS); +} + +/** + * @brief Set UART Smartcard repetition transmit frequency. + * @param UARTx UART Instance + * @param num repetition frequency. + * @retval None + */ +__STATIC_INLINE void md_uart_set_scard_sccnt(UART_TypeDef *UARTx, uint32_t num) +{ + MODIFY_REG(UARTx->SCARD, UART_SCARD_SCCNT_MSK, num << UART_SCARD_SCCNT_POSS); +} + +/** + * @brief Get UART Smartcard repetition transmit frequency. + * @param UARTx UART Instance + * @retval Smartcard repetition transmit frequency. + */ +__STATIC_INLINE uint32_t md_uart_get_scard_psc(UART_TypeDef *UARTx) +{ + return READ_BITS(UARTx->SCARD, UART_SCARD_SCCNT_MSK, UART_SCARD_SCCNT_POSS); +} + +/** + * @brief Enable UART Smartcard clock. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_scard_sclken(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->SCARD, UART_SCARD_SCLKEN_MSK); +} + +/** + * @brief Disable UART Smartcard clock. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_scard_sclken(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->SCARD, UART_SCARD_SCLKEN_MSK); +} + +/** + * @brief Indicate if Smartcard clock is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_scard_sclken(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->SCARD, UART_SCARD_SCLKEN_MSK) == (UART_SCARD_SCLKEN_MSK)); +} + +/** + * @brief Enable UART Smartcard nack. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_scard_nack(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->SCARD, UART_SCARD_SCNACK_MSK); +} + +/** + * @brief Disable UART Smartcard nack. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_scard_nack(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->SCARD, UART_SCARD_SCNACK_MSK); +} + +/** + * @brief Indicate if Smartcard nack is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_scard_nack(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->SCARD, UART_SCARD_SCNACK_MSK) == (UART_SCARD_SCNACK_MSK)); +} + +/** + * @brief Enable UART Smartcard mode. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_scard_mode(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->SCARD, UART_SCARD_SCEN_MSK); +} + +/** + * @brief Disable UART Smartcard mode. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_scard_mode(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->SCARD, UART_SCARD_SCEN_MSK); +} + +/** + * @brief Indicate if Smartcard mode is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_scard_mode(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->SCARD, UART_SCARD_SCEN_MSK) == (UART_SCARD_SCEN_MSK)); +} +/** + * @} + */ +/** @defgroup MD_UART_Public_Functions_Group9 LIN + * @{ + */ +/** + * @brief Enable UART LIN break request. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_lin_bkreq(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LIN, UART_LIN_LINBKREQ_MSK); +} + +/** + * @brief Disable UART LIN break request. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_lin_bkreq(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LIN, UART_LIN_LINBKREQ_MSK); +} + +/** + * @brief Set UART LIN break 11 bit length. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_set_lin_bk11(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LIN, UART_LIN_LINBDL_MSK); +} + +/** + * @brief Set UART LIN break 10 bit length. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_set_lin_bk10(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LIN, UART_LIN_LINBDL_MSK); +} + +/** + * @brief Indicate the length of LIN break + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + * - 0: 10bit + * - 1: 11bit + */ +__STATIC_INLINE uint32_t md_uart_get_lin_break_length(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LIN, UART_LIN_LINBDL_MSK)); +} + +/** + * @brief Enable UART LIN mode. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_lin_mode(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LIN, UART_LIN_LINEN_MSK); +} + +/** + * @brief Disable UART LIN mode. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_lin_mode(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LIN, UART_LIN_LINEN_MSK); +} + +/** + * @brief Indicate if UART LIN mode is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lin_mode(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LIN, UART_LIN_LINEN_MSK) == (UART_LIN_LINEN_MSK)); +} +/** + * @} + */ +/** @defgroup MD_UART_Public_Functions_Group10 RTOR + * @{ + */ +/** + * @brief Enable UART rx timeout. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_rtoen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->RTOR, UART_RTOR_RTOEN_MSK); +} + +/** + * @brief Disable UART rx timeout. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_rtoen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->RTOR, UART_RTOR_RTOEN_MSK); +} + +/** + * @brief Indicate if rx timeout is enabled + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_rtoen(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->RTOR, UART_RTOR_RTOEN_MSK) == (UART_RTOR_RTOEN_MSK)); +} + +/** + * @brief Set UART receiver timeout value and enable receiver timeout + * @param UARTx UART Instance + * @param timeout UART timeout value + * @retval None + */ +__STATIC_INLINE void md_uart_set_rec_timeout(UART_TypeDef *UARTx, uint32_t timeout) +{ + MODIFY_REG(UARTx->RTOR, UART_RTOR_RTO_MSK, timeout); +} + +/** + * @brief Get UART receiver timeout value + * @param UARTx UART Instance + * @retval UART timeout value + */ +__STATIC_INLINE uint32_t md_uart_get_rec_timeout(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RTOR, UART_RTOR_RTO_MSK)); +} + +/** + * @} + */ +/** @defgroup MD_UART_Public_Functions_Group12 STAT + * @{ + */ +/** + * @brief Get UART Tx FIFO overflow state + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_tfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_TFOERR_MSK) == (UART_STAT_TFOERR_MSK)); +} + +/** + * @brief Get UART Tx FIFO empty state + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_tfempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_TFEMPTY_MSK) == (UART_STAT_TFEMPTY_MSK)); +} + +/** + * @brief Get UART Tx shifting register busy state + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_tsbusy(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_TSBUSY_MSK) == (UART_STAT_TSBUSY_MSK)); +} + +/** + * @brief Get UART Rx underflow error state + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rfuerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_RFUERR_MSK) == (UART_STAT_RFUERR_MSK)); +} + +/** + * @brief Get UART Rx overflow error state + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_RFOERR_MSK) == (UART_STAT_RFOERR_MSK)); +} + +/** + * @brief Get UART Rx fifo not empty state + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rfnempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_RFNEMPTY_MSK) == (UART_STAT_RFNEMPTY_MSK)); +} + +/** + * @brief Get UART Rx shifting register busy state + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rsbusy(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_RSBUSY_MSK) == (UART_STAT_RSBUSY_MSK)); +} + +/** + * @brief Get UART CTSn state + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ctssta(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_CTSSTA_MSK) == (UART_STAT_CTSSTA_MSK)); +} + +/** + * @brief Get UART break error state + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_bkerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_BKERR_MSK) == (UART_STAT_BKERR_MSK)); +} + +/** + * @brief Get UART frame error state + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ferr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_FERR_MSK) == (UART_STAT_FERR_MSK)); +} + +/** + * @brief Get UART verify error state + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_perr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_PERR_MSK) == (UART_STAT_PERR_MSK)); +} +/** + * @} + */ +/** @defgroup MD_UART_Public_Functions_Group13 IER + * @{ + */ +/** + * @brief Enable UART tx fifo overflow interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_tfoerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_TFOERR_MSK); +} + +/** + * @brief Enable UART tx fifo empty interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_tfempty(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_TFEMPTY_MSK); +} + +/** + * @brief Enable UART tx fifo transmit complete interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_tbc(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_TBC_MSK); +} + +/** + * @brief Enable UART rx fifo underflow interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_rfuerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RFUERR_MSK); +} + +/** + * @brief Enable UART rx fifo overflow interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_rfoerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RFOERR_MSK); +} + +/** + * @brief Enable UART rx not empty interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_rfnempty(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RFNEMPTY_MSK); +} + +/** + * @brief Enable UART noise interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_noise(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_NOISE_MSK); +} + +/** + * @brief Enable UART block end interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_eob(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_EOB_MSK); +} + +/** + * @brief Enable UART link break interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_linbk(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_LINBK_MSK); +} + +/** + * @brief Enable UART address match interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_addrm(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_ADDRM_MSK); +} + +/** + * @brief Enable UART receive timeout interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_rxto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RXTO_MSK); +} + +/** + * @brief Enable UART CTSn change interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_dcts(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_DCTS_MSK); +} + +/** + * @brief Enable UART auto-baud detection timeout interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_abto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_ABTO_MSK); +} + +/** + * @brief Enable UART auto-baud detection end interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_abend(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_ABEND_MSK); +} + +/** + * @brief Enable UART rx format error interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_it_rxberr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RXBERR_MSK); +} +/** + * @} + */ +/** @defgroup MD_UART_Public_Functions_Group14 IDR + * @{ + */ +/** + * @brief Disable UART tx fifo overflow interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_tfover(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_TFOVER_MSK); +} + +/** + * @brief Disable UART tx fifo empty interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_tfempty(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_TFEMPTY_MSK); +} + +/** + * @brief Disable UART tx fifo transmit complete interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_tbc(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_TBC_MSK); +} + +/** + * @brief Disable UART rx fifo underflow interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_rfuerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RFUERR_MSK); +} + +/** + * @brief Disable UART rx fifo overflow interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_rfoerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RFOERR_MSK); +} + +/** + * @brief Disable UART rx not empty interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_rfnempty(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RFNEMPTY_MSK); +} + +/** + * @brief Disable UART rx fifo noise interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_noise(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_NOISE_MSK); +} + +/** + * @brief Disable UART block end interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_eob(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_EOB_MSK); +} + +/** + * @brief Disable UART link break interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_linbk(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_LINBK_MSK); +} + +/** + * @brief Disable UART address match interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_addrm(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_ADDRM_MSK); +} + +/** + * @brief Disable UART receive timeout interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_rxto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RXTO_MSK); +} + +/** + * @brief Disable UART CTSn change interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_dcts(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_DCTS_MSK); +} + +/** + * @brief Disable UART auto-baud detection timeout interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_abto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_ABTO_MSK); +} + +/** + * @brief Disable UART auto-baud detection end interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_abend(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_ABEND_MSK); +} + +/** + * @brief Disable UART rx format error interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_it_rxberr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RXBERR_MSK); +} +/** + * @} + */ +/** @defgroup MD_UART_Public_Functions_Group15 IVS + * @{ + */ +/** + * @brief Check if is enable tx fifo overflow interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enable_it_tfover(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_TFOVER_MSK) == (UART_IVS_TFOVER_MSK)); +} + +/** + * @brief Check if is enable tx fifo empty interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enable_it_tfempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_TFEMPTY_MSK) == (UART_IVS_TFEMPTY_MSK)); +} + +/** + * @brief Check if is enable tx fifo transmit complete interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enable_it_tbc(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_TBC_MSK) == (UART_IVS_TBC_MSK)); +} + +/** + * @brief Check if is enable rx fifo underflow interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enable_it_rfuerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RFUERR_MSK) == (UART_IVS_RFUERR_MSK)); +} + +/** + * @brief Check if is enable rx fifo overflow interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enable_it_rfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RFOERR_MSK) == (UART_IVS_RFOERR_MSK)); +} + +/** + * @brief Check if is enable rx not empty interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enable_it_rfnempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RFNEMPTY_MSK) == (UART_IVS_RFNEMPTY_MSK)); +} + +/** + * @brief Check if is enable rx noise threshold interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enable_it_noise(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_NOISE_MSK) == (UART_IVS_NOISE_MSK)); +} + +/** + * @brief Check if is enable block end interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enable_it_eob(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_EOB_MSK) == (UART_IVS_EOB_MSK)); +} + +/** + * @brief Check if is enable link break interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enable_it_linbk(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_LINBK_MSK) == (UART_IVS_LINBK_MSK)); +} + +/** + * @brief Check if is enable address match interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enable_it_addrm(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_ADDRM_MSK) == (UART_IVS_ADDRM_MSK)); +} + +/** + * @brief Check if is enable receive timeout interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enable_it_rxto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RXTO_MSK) == (UART_IVS_RXTO_MSK)); +} + +/** + * @brief Check if is enable CTSn change interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enable_it_dcts(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_DCTS_MSK) == (UART_IVS_DCTS_MSK)); +} + +/** + * @brief Check if is enable auto-baud detection timeout interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enable_it_abto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_ABTO_MSK) == (UART_IVS_ABTO_MSK)); +} + +/** + * @brief Check if is enable auto-baud detection end interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enable_it_abend(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_ABEND_MSK) == (UART_IVS_ABEND_MSK)); +} + +/** + * @brief Check if is enable rx format error interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enable_it_rxberr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RXBERR_MSK) == (UART_IVS_RXBERR_MSK)); +} +/** + * @} + */ +/** @defgroup MD_UART_Public_Functions_Group16 RIF + * @{ + */ +/** + * @brief Check if is active tx fifo overflow interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_tfover(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_TFOVER_MSK) == (UART_RIF_TFOVER_MSK)); +} + +/** + * @brief Check if is active tx fifo empty interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_tfempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_TFEMPTY_MSK) == (UART_RIF_TFEMPTY_MSK)); +} + +/** + * @brief Check if is active tx fifo transmit complete interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_tbc(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_TBC_MSK) == (UART_RIF_TBC_MSK)); +} + +/** + * @brief Check if is active rx fifo underflow interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_rfuerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RFUERR_MSK) == (UART_RIF_RFUERR_MSK)); +} + +/** + * @brief Check if is active rx fifo overflow interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_rfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RFOERR_MSK) == (UART_RIF_RFOERR_MSK)); +} + +/** + * @brief Check if is active rx not empty interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_it_rfnempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RFNEMPTY_MSK) == (UART_RIF_RFNEMPTY_MSK)); +} + +/** + * @brief Check if is active rx noise threshold interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_noise(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_NOISE_MSK) == (UART_RIF_NOISE_MSK)); +} + +/** + * @brief Check if is active block end interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_eob(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_EOB_MSK) == (UART_RIF_EOB_MSK)); +} + +/** + * @brief Check if is active link break interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_linbk(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_LINBK_MSK) == (UART_RIF_LINBK_MSK)); +} + +/** + * @brief Check if is active address match interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_addrm(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_ADDRM_MSK) == (UART_RIF_ADDRM_MSK)); +} + +/** + * @brief Check if is active receive timeout interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rxto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RXTO_MSK) == (UART_RIF_RXTO_MSK)); +} + +/** + * @brief Check if is active CTSn change interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_dcts(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_DCTS_MSK) == (UART_RIF_DCTS_MSK)); +} + +/** + * @brief Check if is active auto-baud detection timeout interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_abto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_ABTO_MSK) == (UART_RIF_ABTO_MSK)); +} + +/** + * @brief Check if is active auto-baud detection end interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_abend(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_ABEND_MSK) == (UART_RIF_ABEND_MSK)); +} + +/** + * @brief Check if is active rx format error interrupt. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rxberr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RXBERR_MSK) == (UART_RIF_RXBERR_MSK)); +} +/** + * @} + */ +/** @defgroup MD_UART_Public_Functions_Group17 IFM + * @{ + */ +/** + * @brief Mask tx fifo overflow interrupt. + * @param UARTx UART Instance + * @retval Interrupt Mask. + */ +__STATIC_INLINE uint32_t md_uart_mask_it_tfover(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_TFOVER_MSK) == UART_IFM_TFOVER_MSK); +} + +/** + * @brief Mask tx fifo empty interrupt. + * @param UARTx UART Instance + * @retval Interrupt Mask. + */ +__STATIC_INLINE uint32_t md_uart_mask_it_tfempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_TFEMPTY_MSK) == UART_IFM_TFEMPTY_MSK); +} + +/** + * @brief Mask tx fifo transmit complete interrupt. + * @param UARTx UART Instance + * @retval Interrupt Mask. + */ +__STATIC_INLINE uint32_t md_uart_mask_it_tbc(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_TBC_MSK) == UART_IFM_TBC_MSK); +} + +/** + * @brief Mask rx fifo underflow interrupt. + * @param UARTx UART Instance + * @retval Interrupt Mask. + */ +__STATIC_INLINE uint32_t md_uart_mask_it_rfuerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_RFUERR_MSK) == UART_IFM_RFUERR_MSK); +} + +/** + * @brief Mask rx fifo overflow interrupt. + * @param UARTx UART Instance + * @retval Interrupt Mask. + */ +__STATIC_INLINE uint32_t md_uart_mask_it_rfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_RFOERR_MSK) == UART_IFM_RFOERR_MSK); +} + +/** + * @brief Mask rx not empty interrupt. + * @param UARTx UART Instance + * @retval Interrupt Mask. + */ +__STATIC_INLINE uint32_t md_uart_mask_it_rfnempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_RFNEMPTY_MSK) == UART_IFM_RFNEMPTY_MSK); +} + +/** + * @brief Mask rx fifo noise interrupt. + * @param UARTx UART Instance + * @retval Interrupt Mask. + */ +__STATIC_INLINE uint32_t md_uart_mask_it_noise(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_NOISE_MSK) == UART_IFM_NOISE_MSK); +} + +/** + * @brief Mask block end interrupt. + * @param UARTx UART Instance + * @retval Interrupt Mask. + */ +__STATIC_INLINE uint32_t md_uart_mask_it_eob(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_EOB_MSK) == UART_IFM_EOB_MSK); +} + +/** + * @brief Mask link break interrupt. + * @param UARTx UART Instance + * @retval Interrupt Mask. + */ +__STATIC_INLINE uint32_t md_uart_mask_it_linbk(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_LINBK_MSK) == UART_IFM_LINBK_MSK); +} + +/** + * @brief Mask address match interrupt. + * @param UARTx UART Instance + * @retval Interrupt Mask. + */ +__STATIC_INLINE uint32_t md_uart_mask_it_addrm(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_ADDRM_MSK) == UART_IFM_ADDRM_MSK); +} + +/** + * @brief Mask receive timeout interrupt. + * @param UARTx UART Instance + * @retval Interrupt Mask. + */ +__STATIC_INLINE uint32_t md_uart_mask_it_rxto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_RXTO_MSK) == UART_IFM_RXTO_MSK); +} + +/** + * @brief Mask CTSn change interrupt. + * @param UARTx UART Instance + * @retval Interrupt Mask. + */ +__STATIC_INLINE uint32_t md_uart_mask_it_dcts(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_DCTS_MSK) == UART_IFM_DCTS_MSK); +} + +/** + * @brief Mask auto-baud detection timeout interrupt. + * @param UARTx UART Instance + * @retval Interrupt Mask. + */ +__STATIC_INLINE uint32_t md_uart_mask_it_abto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_ABTO_MSK) == UART_IFM_ABTO_MSK); +} + +/** + * @brief Mask auto-baud detection end interrupt. + * @param UARTx UART Instance + * @retval Interrupt Mask. + */ +__STATIC_INLINE uint32_t md_uart_mask_it_abend(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_ABEND_MSK) == UART_IFM_ABEND_MSK); +} + +/** + * @brief Read Mask rx format error interrupt. + * @param UARTx UART Instance + * @retval Interrupt Mask. + */ +__STATIC_INLINE uint32_t md_uart_mask_it_rxberr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_IFM_RXBERR_MSK) == UART_IFM_RXBERR_MSK); +} +/** + * @} + */ +/** @defgroup MD_UART_Public_Functions_Group18 ICR + * @{ + */ +/** + * @brief Clear tx fifo overflow interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_it_tfover(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_TFOVER_MSK); +} + +/** + * @brief Clear tx fifo empty interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_it_tfempty(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_TFEMPTY_MSK); +} + +/** + * @brief Clear tx fifo transmit complete interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_it_tbc(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_TBC_MSK); +} + +/** + * @brief Clear rx fifo underflow interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_rfuerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RFUERC_W1_MSK); +} + +/** + * @brief Clear rx fifo overflow interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_rfoerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RFOERC_W1_MSK); +} + +/** + * @brief Clear rx not empty interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_rfnempty(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RFNEMPTY_MSK); +} + +/** + * @brief Clear rx fifo noise interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_noise(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_NOISE_MSK); +} + +/** + * @brief Clear block end interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_eob(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_EOB_MSK); +} + +/** + * @brief Clear LIN break interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_linbk(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_LINBK_MSK); +} + +/** + * @brief Clear address match interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_addrm(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_ADDRM_MSK); +} + +/** + * @brief Clear receive timeout interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_rxto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RXTO_MSK); +} + +/** + * @brief Clear CTSn change interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_dcts(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_DCTS_MSK); +} + +/** + * @brief Clear auto-baud detection timeout interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_abto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_ABTO_MSK); +} + +/** + * @brief Clear auto-baud detection end interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_it_abend(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_ABEND_MSK); +} + +/** + * @brief Clear rx format error interrupt. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_rxberr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RXBERR_MSK); +} +/** + * @} + */ +/** @defgroup MD_UART_Public_Functions_Group1 Initialization + * @{ + */ +extern void md_uart_reset(UART_TypeDef *UARTx); +extern void md_uart_init(UART_TypeDef *UARTx, md_uart_init_t *init); +extern void md_uart_init_struct(md_uart_init_t *init); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __MD_UART_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_utils.c b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_utils.c new file mode 100644 index 0000000000..8d1afda8e5 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_utils.c @@ -0,0 +1,185 @@ +/********************************************************************************** + * + * @file md_utils.c + * @brief UTILS module driver. + * + * @date 27 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 27 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ +#include +#include "md_utils.h" +#include "md_cmu.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Public Variables ---------------------------------------------------------- */ + +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ + +/** @defgroup Micro_Driver EASTSOFT Micro Driver + * @{ + */ + +/* Private Variables --------------------------------------------------------- */ + +/** @defgroup MD_UTILS Utils + * @brief Utils module driver + * @{ + */ +/** @defgroup MD_UTILS_Private_Variables Utils Private Variables + * @{ + */ +static __IO uint32_t __md_tick = 0; +/** + * @} + */ + +/* Private Function ---------------------------------------------------------- */ + +/** @defgroup MD_UTILS_Public_Functions Utils Public Functions + * @{ + */ +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @retval None + */ +void md_init_1ms_tick(void) +{ + /* Configure the SysTick IRQ */ + csi_coret_config(md_cmu_get_clock() / 1000, CLINT_IRQn); + csi_vic_set_prio(CLINT_IRQn, 0); + csi_vic_enable_sirq(CLINT_IRQn); + + return; +} + +/** + * @brief This function invoked by Systick ISR. + * @note This function is declared as __weak to be overwritten in case of + * other implementations in user file. + * @retval None + */ +__weak void md_systick_irq_cbk(void) +{ + /* do nothing */ + return; +} + +/** + * @brief This function invoked by Systick ISR each 1ms. + * @retval None + */ +__isr__ void md_inc_tick(void) +{ + ++__md_tick; + md_systick_irq_cbk(); + return; +} + +/** + * @brief Provides a tick value in millisecond. + * @retval tick value + */ +uint32_t md_get_tick(void) +{ + return __md_tick; +} + +/** + * @brief This function provides accurate delay (in microsecond) based + * on variable incremented. + * @param delay: specifies the delay time length, in microsecond. + * @retval None + */ +void md_delay_1us(__IO uint32_t delay) +{ + unsigned int start, now, delta, ticks; + start = CORET->MTIME; + ticks = (md_cmu_get_clock() / 1000000UL) * delay; + + do + { + now = CORET->MTIME; + delta = now - start; + } + while (delta < ticks); +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on variable incremented. + * @param delay: specifies the delay time length, in milliseconds. + * @retval None + */ +void md_delay_1ms(__IO uint32_t delay) +{ + md_delay_1us(delay * 1000); +} + +/** + * @brief Configure interrupt. + * @param irq: Interrunpt type. + * @param prio: preempt priority(0-7). The larger the prio value, the higher the priority. + * @param status: Status. + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void md_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status) +{ + if (status == ENABLE) + { + csi_vic_set_prio(irq, prio); + csi_vic_enable_sirq(irq); + + if (irq == ADC_IRQn) + CLIC->CLICINT[irq].ATTR |= (CLIC_INTATTR_SHV_Msk | (0x1UL << CLIC_INTATTR_TRIG_Pos)); + } + else + { + csi_vic_disable_sirq(irq); + } + + return; +} + +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_utils.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_utils.h new file mode 100644 index 0000000000..6ff031af05 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_utils.h @@ -0,0 +1,140 @@ +/********************************************************************************** + * + * @file md_utils.h + * @brief Header file of UTILS module driver. + * + * @date 13 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 13 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __MD_UTILS_H__ +#define __MD_UTILS_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ +#include +#include "es32vf2264.h" +#include "type.h" + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Variables -------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @addtogroup MD_UTILS + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ +/** @defgroup MD_UTILS_Public_Types Utils Public Types + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** + * @brief MD Status structures definition + */ +typedef enum +{ + MD_OK = 0x0U, /**< Status: OK */ + MD_ERROR = 0x1U, /**< Status: ERROR */ + MD_BUSY = 0x2U, /**< Status: BUSY */ + MD_TIMEOUT = 0x3U, /**< Status: TIMEOUT */ +} md_status_t; + +/** + * @} + */ + +/** @defgroup MD_UTILS_Public_Macros Utils Public Macros + * @{ + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** + * @brief Nested IRQ start : Save CSR and enable global interrupt. + */ +#ifdef NEST_INT_ENABLE + #define MD_NEST_INT_START(); \ + uint32_t val_mcause, val_mepc, val_mstatus; \ + __ASM volatile("csrr %0, mcause" : "=r"(val_mcause)); \ + __ASM volatile("csrr %0, mepc" : "=r"(val_mepc)); \ + __ASM volatile("csrr %0, mstatus" : "=r"(val_mstatus)); \ + __enable_irq(); +#else + #define MD_NEST_INT_START(); +#endif /* NEST_INT_ENABLE */ + +/** + * @brief Nested IRQ end : Restore CSR and disable global interrupt. + */ +#ifdef NEST_INT_ENABLE + #define MD_NEST_INT_END(); \ + __disable_irq(); \ + __ASM volatile("csrw mstatus, %0" : : "r"(val_mstatus)); \ + __ASM volatile("csrw mepc, %0" : : "r"(val_mepc)); \ + __ASM volatile("csrw mcause, %0" : : "r"(val_mcause)); +#else + #define MD_NEST_INT_END(); +#endif /* NEST_INT_ENABLE */ + +/** + * @} + */ +/* Exported Functions -------------------------------------------------------- */ + +/** @addtogroup MD_UTILS_Public_Functions + * @{ + */ +extern void md_init_1ms_tick(void); +extern void md_inc_tick(void); +extern __weak void md_systick_irq_cbk(void); +extern uint32_t md_get_tick(void); +extern void md_delay_1ms(__IO uint32_t delay); +extern void md_delay_1us(__IO uint32_t delay); +extern void md_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus + } +#endif /* __cplusplus */ +#endif /* __MD_UTILS_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_wwdt.c b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_wwdt.c new file mode 100644 index 0000000000..2019a29f74 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_wwdt.c @@ -0,0 +1,139 @@ +/********************************************************************************** + * + * @file md_wwdt.c + * @brief WWDT module driver. + * + * @date 20 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 20 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_wwdt.h" + +/* Private Macros ------------------------------------------------------------ */ +/* Private Variables --------------------------------------------------------- */ +/* Public Variables ---------------------------------------------------------- */ +/* Private Constants --------------------------------------------------------- */ +/* Private function prototypes ----------------------------------------------- */ + +/* Private Function ---------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup MD_WWDT WWDT + * @{ + */ +/** @defgroup MD_WWDT_Public_Functions WWDT Public Functions + * @{ + */ +/** @defgroup MD_WWDT_Public_Functions_Group1 Initialization + * @{ + */ + +/** + * @brief Initializes the WWDT according to the specified parameters. + * @param load: Specifies the free-running downcounter value. + * @param win: specifics the no dog windows, + * the parameter can be one of the following values: + * @arg @ref MD_WWDT_WIN_25 No dog window size: 25% + * @arg @ref MD_WWDT_WIN_50 No dog window size: 50% + * @arg @ref MD_WWDT_WIN_75 No dog window size: 75% + * @arg @ref MD_WWDT_WIN_00 No dog window size: 0% + * @param interrupt: Enable or disable interrupt. + * @retval None + */ +void md_wwdt_init(uint32_t load, md_wwdt_win_t win, type_func_t interrupt) +{ + WWDT_UNLOCK(); + md_wwdt_set_count_overload(load); + md_wwdt_set_forbid_feed_time(win); + md_wwdt_set_count_lrc(); + md_wwdt_enable_reset(); + + if (interrupt == ENABLE) + { + md_wwdt_enable_interrupt(); + } + else + { + md_wwdt_disable_interrupt(); + } + + WWDT_LOCK(); + + return; +} + +/** + * @brief Initializes the WWDT without reset according to the specified parameters. + * @param load: Specifies the free-running downcounter value. + * @param win: specifics the no dog windows, + * the parameter can be one of the following values: + * @arg @ref MD_WWDT_WIN_25 No dog window size: 25% + * @arg @ref MD_WWDT_WIN_50 No dog window size: 50% + * @arg @ref MD_WWDT_WIN_75 No dog window size: 75% + * @arg @ref MD_WWDT_WIN_00 No dog window size: 0% + * @param interrupt: Enable or disable interrupt. + * @retval None + */ +void md_wwdt_init_no_reset(uint32_t load, md_wwdt_win_t win, type_func_t interrupt) +{ + WWDT_UNLOCK(); + md_wwdt_set_count_overload(load); + md_wwdt_set_forbid_feed_time(win); + md_wwdt_set_count_lrc(); + md_wwdt_disable_reset(); + + if (interrupt == ENABLE) + { + md_wwdt_enable_interrupt(); + } + else + { + md_wwdt_disable_interrupt(); + } + + WWDT_LOCK(); + + return; +} + +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_wwdt.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_wwdt.h new file mode 100644 index 0000000000..c361d25df9 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_wwdt.h @@ -0,0 +1,333 @@ +/********************************************************************************** + * + * @file md_wwdt.h + * @brief Header file of WWDT module driver. + * + * @date 20 July 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 20 July 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __MD_WWDT_H__ +#define __MD_WWDT_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ +#include "md_utils.h" + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Variables -------------------------------------------------------- */ + +/** @addtogroup Micro_Driver + * @{ + */ +/** @addtogroup MD_WWDT WWDT + * @{ + */ + +/* Exported Types ------------------------------------------------------------ */ + +/** @defgroup MD_WWDT_Public_Types WWDT Public Types + * @{ + */ +/** + * @brief wwdt no dog window + */ +typedef enum +{ + MD_WWDT_WIN_25 = 0x0U, /**< No dog window size: 25% */ + MD_WWDT_WIN_50 = 0x1U, /**< No dog window size: 50% */ + MD_WWDT_WIN_75 = 0x2U, /**< No dog window size: 75% */ + MD_WWDT_WIN_00 = 0x3U, /**< No dog window size: 0% */ +} md_wwdt_win_t; +/** + * @} + */ + +/* Exported Macros ----------------------------------------------------------- */ + +/** + * @defgroup MD_WWDT_Private_Macros WWDT Private Macros + * @{ + */ +#define WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551U);} +#define WWDT_LOCK() {WRITE_REG(WWDT->LOCK, 0xFFFFFFFFU);} +/** + * @} + */ + +/* Exported Functions -------------------------------------------------------- */ + +/** @addtogroup MD_WWDT_Public_Functions WWDT Public Functions + * @{ + */ +/** @defgroup MD_WWDT_Public_Functions_Group2 LOAD + * @{ + */ +/** + * @brief Set wwdt count overload value. + * @param cnt: Value for overload value. + * @retval None + */ +__STATIC_INLINE void md_wwdt_set_count_overload(uint32_t cnt) +{ + MODIFY_REG(WWDT->LOAD_, WWDT_LOAD_LOAD_MSK, cnt << WWDT_LOAD_LOAD_POSS); +} +/** + * @} + */ +/** @defgroup MD_WWDT_Public_Functions_Group3 VALUE + * @{ + */ +/** + * @brief Get wwdt current count value. + * @retval Value for count value. + */ +__STATIC_INLINE uint32_t md_wwdt_get_count_value(void) +{ + return READ_BITS(WWDT->VALUE, WWDT_VALUE_VALUE_MSK, WWDT_VALUE_VALUE_POSS); +} +/** + * @} + */ +/** @defgroup MD_WWDT_Public_Functions_Group4 CON + * @{ + */ +/** + * @brief Set wwdt forbid feed dog time. + * @param time: forbid feed dog time @see wwdt_win_t. + * @retval None + */ +__STATIC_INLINE void md_wwdt_set_forbid_feed_time(md_wwdt_win_t time) +{ + MODIFY_REG(WWDT->CON, WWDT_CON_WWDTWIN_MSK, time << WWDT_CON_WWDTWIN_POSS); +} + +/** + * @brief Read wwdt forbid feed dog time. + * @retval Time for forbid feed dog. + */ +__STATIC_INLINE uint32_t md_wwdt_get_forbid_feed_time(void) +{ + return READ_BITS(WWDT->CON, WWDT_CON_WWDTWIN_MSK, WWDT_CON_WWDTWIN_POSS); +} + +/** + * @brief Set wwdt count by pclk. + * @retval None + */ +__STATIC_INLINE void md_wwdt_set_count_pclk(void) +{ + CLEAR_BIT(WWDT->CON, WWDT_CON_CLKS_MSK); +} + +/** + * @brief Set wwdt count by lrc. + * @retval None + */ +__STATIC_INLINE void md_wwdt_set_count_lrc(void) +{ + SET_BIT(WWDT->CON, WWDT_CON_CLKS_MSK); +} + +/** + * @brief Check if wwdt count clock is pclk source. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint8_t md_wwdt_is_enable_count_pclk(void) +{ + return (READ_BIT(WWDT->CON, WWDT_CON_CLKS_MSK) != WWDT_CON_CLKS_MSK); +} + +/** + * @brief Check if wwdt count clock is lrc source. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint8_t md_wwdt_is_enable_count_lrc(void) +{ + return (READ_BIT(WWDT->CON, WWDT_CON_CLKS_MSK) == WWDT_CON_CLKS_MSK); +} + +/** + * @brief Enable wwdt reset bit. + * @retval None + */ +__STATIC_INLINE void md_wwdt_enable_reset(void) +{ + SET_BIT(WWDT->CON, WWDT_CON_RSTEN_MSK); +} + +/** + * @brief Disable wwdt reset bit. + * @retval None + */ +__STATIC_INLINE void md_wwdt_disable_reset(void) +{ + CLEAR_BIT(WWDT->CON, WWDT_CON_RSTEN_MSK); +} + +/** + * @brief Check if is enable reset bit. + * @retval State for 1 or 0 + */ +__STATIC_INLINE uint8_t md_wwdt_is_enable_reset(void) +{ + return (READ_BIT(WWDT->CON, WWDT_CON_RSTEN_MSK) == WWDT_CON_RSTEN_MSK); +} + +/** + * @brief Enable wwdt interrupt. + * @retval None + */ +__STATIC_INLINE void md_wwdt_enable_interrupt(void) +{ + SET_BIT(WWDT->CON, WWDT_CON_IE_MSK); +} + +/** + * @brief Disable wwdt interrupt. + * @retval None + */ +__STATIC_INLINE void md_wwdt_disable_interrupt(void) +{ + CLEAR_BIT(WWDT->CON, WWDT_CON_IE_MSK); +} + +/** + * @brief Check if is enable interrupt. + * @retval State for 1 or 0 + */ +__STATIC_INLINE uint8_t md_wwdt_is_enable_interrupt(void) +{ + return (READ_BIT(WWDT->CON, WWDT_CON_IE_MSK) == WWDT_CON_IE_MSK); +} + +/** + * @brief Enable wwdt module. + * @retval None + */ +__STATIC_INLINE void md_wwdt_enable(void) +{ + SET_BIT(WWDT->CON, WWDT_CON_EN_MSK); +} + +/** + * @brief Disable wwdt interrupt. + * @retval None + */ +__STATIC_INLINE void md_wwdt_disable(void) +{ + CLEAR_BIT(WWDT->CON, WWDT_CON_EN_MSK); +} + +/** + * @brief Check if is enable interrupt. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint8_t md_wwdt_is_enable(void) +{ + return (READ_BIT(WWDT->CON, WWDT_CON_EN_MSK) == WWDT_CON_EN_MSK); +} +/** + * @} + */ +/** @defgroup MD_WWDT_Public_Functions_Group5 INTCLR + * @{ + */ +/** + * @brief Clear wwdt Interrupt flag. + * @retval None + */ +__STATIC_INLINE void md_wwdt_clear_interrupt(void) +{ + WRITE_REG(WWDT->INTCLR, 0x55AA); +} +/** + * @brief feed wwdt. + * @retval None + */ +__STATIC_INLINE void md_wwdt_feed_wwdt(void) +{ + WRITE_REG(WWDT->INTCLR, 0xFFFFFFFF); +} +/** + * @} + */ +/** @defgroup MD_WWDT_Public_Functions_Group6 RIS + * @{ + */ +/** + * @brief Read wwdt interrupt flag. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint8_t md_wwdt_read_interrupt(void) +{ + return (READ_BIT(WWDT->RIS, WWDT_RIS_WWDTIF_MSK) == WWDT_RIS_WWDTIF_MSK); +} +/** + * @} + */ +/** @defgroup MD_WWDT_Public_Functions_Group7 LOCK + * @{ + */ +/** + * @brief Read wwdt project register status. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint8_t md_wwdt_lock_status(void) +{ + return (READ_BIT(WWDT->LOCK, WWDT_LOCK_LOCK_MSK) == WWDT_LOCK_LOCK_MSK); +} + +/** + * @} + */ +/** @addtogroup MD_WWDT_Public_Functions_Group1 Initialization + * @{ + */ +extern void md_wwdt_init(uint32_t load, md_wwdt_win_t win, type_func_t interrupt); +extern void md_wwdt_init_no_reset(uint32_t load, md_wwdt_win_t win, type_func_t interrupt); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __MD_WWDT_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/md/type.h b/os/common/ext/CMSIS/ES32/ES32VF2264/md/type.h new file mode 100644 index 0000000000..b59931f89c --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/md/type.h @@ -0,0 +1,159 @@ +/********************************************************************************** + * + * @file type.h + * @brief define type + * + * @date 15 Dec. 2022 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 15 Dec. 2022 Lisq the first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ********************************************************************************** + */ + +#ifndef __TYPE_H__ +#define __TYPE_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------ */ +#include + +/* Exported Constants -------------------------------------------------------- */ + +/* Exported Variables -------------------------------------------------------- */ + +#if defined (__CC_ARM) +#define __INLINE__ __inline +#define __STATIC_INLINE__ static __inline +#else +#define __INLINE__ inline +#define __STATIC_INLINE__ static inline +#endif /* __CC_ARM */ + +#define __isr__ + +/* Exported Types ------------------------------------------------------------ */ + +typedef enum +{ + RESET = 0x0U, + SET = 0x1U, +} flag_status_t, it_status_t; + +typedef enum +{ + BIT_RESET = 0x0U, + BIT_SET = 0x1U, +} bit_status_t; + +typedef enum +{ + MD_DISABLE = 0x0U, + MD_ENABLE = 0x1U, +} type_func_t, TypeFunc; +#define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE)) + +#define DISABLE 0 +#define ENABLE 1 + +typedef enum +{ + MD_FALSE = 0x0U, + MD_TRUE = 0x1U, +} type_bool_t; + +#define FALSE 0 +#define TRUE 1 + +typedef enum +{ + UNLOCK = 0x0U, + LOCK = 0x1U, +} lock_state_t; + +/* Exported Macros ----------------------------------------------------------- */ + +#define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK)) + +#define BIT(x) ((1U << (x))) +#define BITS(s, e) ((0xffffffffU << (s)) & (0xffffffffU >> (31 - (e)))) +#define SET_BIT(reg, bit) ((*(volatile uint32_t *)(0x00080000)) = ((reg) |= (bit))) +#define CLEAR_BIT(reg, bit) ((*(volatile uint32_t *)(0x00080000)) = ((reg) &= ~(bit))) +#define READ_BIT(reg, bit) (((reg) | (*(volatile uint32_t *)(0x00080000))) & (bit)) +#define READ_BITS(reg, msk, s) ((((reg) | (*(volatile uint32_t *)(0x00080000))) & (msk)) >> (s)) +#define CLEAR_REG(reg) ((*(volatile uint32_t *)(0x00080000)) = ((reg) = (0x0))) +#define WRITE_REG(reg, val) ((*(volatile uint32_t *)(0x00080000)) = ((reg) = (val))) +#define READ_REG(reg) ((reg) | (*(volatile uint32_t *)(0x00080000))) +#define MODIFY_REG(reg, clearmask, setmask) \ + WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask))) +#define UNUSED(x) ((void)(x)) + +#ifdef USE_ASSERT +#define assert_param(x) \ + do { \ + if (!(x)) { \ + __disable_irq(); \ + while (1) \ + ; \ + } \ + } while (0) +#else +#define assert_param(x) +#endif /* USE_ASSERT */ + +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /* PER base address */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /* RAM base address */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /* Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /* SRAM Address Space bit-band area */ + +/* Exported Functions -------------------------------------------------------- */ + +__INLINE__ void BITBAND_PER(volatile uint32_t *addr, uint32_t bit, uint32_t val) +{ + uint32_t tmp = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) << 5) + (bit << 2); + *((volatile uint32_t *)tmp) = (uint32_t)val; +} + +__INLINE__ void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val) +{ + uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) << 5) + (bit << 2); + *((volatile uint32_t *)tmp) = (uint32_t)val; +} + +#if defined ( __GNUC__ ) +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __GNUC__ */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __TYPE_H__ */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/startup_es32vf2264.s b/os/common/ext/CMSIS/ES32/ES32VF2264/startup_es32vf2264.s new file mode 100644 index 0000000000..25952b79dd --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/startup_es32vf2264.s @@ -0,0 +1,517 @@ +/********************************************************************************* + * file : startup_es32vf2264.S + * description: es32vf2264 Device Startup File + * author : AE Team + * data : 01 Dec. 2022 + * note + * Change Logs: + * Date Author Notes + * 01 Dec. 2022 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************* + */ + +# define LREG lw +# define SREG sw +# define REGBYTES 4 + +// <<< Use Configuration Wizard in Context Menu >>> + +#define MSTATUS_PRV1 0x1880 + +.global __initial_sp + +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:4> +// Config the stack size for the application +#define StackSize 0x400 + + +.section .app_stack,"aw",@nobits +.align 2 +Stack_Mem: +.space StackSize +__initial_sp: + + +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Config the heap size for the application +#define HeapSize 0x200 + +.global __heap_start +.global __heap_end +.section .bss,"aw",@nobits +.align 2 +Heap_Mem: +__heap_start: +.space HeapSize +__heap_end: + + +.section .vectors, "aw", @progbits + .align 6 + .globl __Vectors + .type __Vectors, @object +__Vectors: //#totally 0~63 entries + .rept 3 // + .long 0 // + .endr // + .long MACHINE_MODE_SOFT_Handler // ##3 + .rept 3 // + .long 0 // + .endr // + .long CLINT_Handler // ##7 + .rept 3 // + .long 0 // + .endr // + .long MACHINE_MODE_EXTERNAL_Handler // ##11 no used + .rept 4 // ##12~15 reserved + .long 0 // + .endr // + +/* External interrupts */ +//##------------------------------------------------------------ + .long WWDT_Handler // ##16 0 + .long IWDT_Handler // ##17 1 + .long LVD_Handler // ##18 2 + .long CSU_Handler // ##19 3 + .long CMU_Handler // ##20 4 + .long EXTI0_3_Handler // ##21 5 + .long EXTI4_7_Handler // ##22 6 + .long EXTI8_11_Handler // ##23 7 + .long EXTI12_15_Handler // ##24 8 + .long DMA_Handler // ##25 9 + .long 0 // ##26 10 + .long USB_Handler // ##27 11 + .long ADC_Handler // ##28 12 + .long AD16C4T_UP_TRIG_COM_Handler // ##29 13 + .long AD16C4T_CC_Handler // ##30 14 + .long BSTIM0_Handler // ##31 15 + .long 0 // ## 16 + .long GPTIMB0_Handler // ##33 17 + .long GPTIMB1_Handler // ##34 18 + .long GPTIMB2_Handler // ##35 19 + .long 0 // ## 20 + .long AD16C4T_Handler // ##37 21 + .long 0 // ## 22 + .long I2C0_Handler // ##39 23 + .long I2C1_Handler // ##40 24 + .long SPI0_I2S0_Handler // ##41 25 + .long SPI1_I2S1_Handler // ##42 26 + .long EUART0_Handler // ##43 27 + .long EUART1_Handler // ##44 28 + .long CUART0_Handler // ##45 29 + .long CUART1_Handler // ##46 30 + .long CUART2_Handler // ##47 31 +//##--------------------------------------------------- + +/* + * For importing variable or functions from other c or assemble files. + */ +.global CFG_Check +.global __main +.global handle_trap + + .section ".text.init" + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +.option push +.option norelax + la gp, __global_pointer$ +.option pop + + la a0, Default_Handler + ori a0, a0, 3 + csrw mtvec, a0 + + la a0, __Vectors + csrw mtvt, a0 + + la sp, g_top_irqstack + + /* Load data section */ + la a0, __erodata + la a1, __data_start__ + la a2, __data_end__ + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b +2: + + /* Clear bss section */ + la a0, __bss_start__ + la a1, __bss_end__ + bgeu a0, a1, 2f +1: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, 1b +2: + jal CFG_Check + + jal main + + .size Reset_Handler, . - Reset_Handler + +/* Configure word checking */ + .section .text.CFG_Check_Handler + .weak CFG_Check + .type CFG_Check, %function +CFG_Check: + sw ra, -4(sp) + sw sp, -8(sp) + +LABLE_CHECK_CFG_WORD0: + li a1, 0x00000000 + li a2, 0x00000000 + li a0, 0x00040000 /* CFG_WORD0 address */ + lhu a1, (a0) + li a0, 0x00040002 /* CFG_WORD0_N address */ + lhu a2, (a0) + xor a1, a1, a2 + li a2, 0x0000FFFF + beq a1, a2, LABLE_CHECK_CFG_PASS + j __exit + +LABLE_CHECK_CFG_PASS: + lw ra, -4(sp) + lw sp, -8(sp) + jr ra + +.size CFG_Check, .-CFG_Check + + .align 6 + .weak Default_Handler +#ifdef __GCC__ /* GCC Compiler */ + .global Default_Handler +#else +#endif /* __GCC__ */ + .type Default_Handler, %function +Default_Handler: + addi sp, sp, -272 + + SREG x1, 1*REGBYTES(sp) + SREG x2, 2*REGBYTES(sp) + SREG x3, 3*REGBYTES(sp) + SREG x4, 4*REGBYTES(sp) + SREG x5, 5*REGBYTES(sp) + SREG x6, 6*REGBYTES(sp) + SREG x7, 7*REGBYTES(sp) + SREG x8, 8*REGBYTES(sp) + SREG x9, 9*REGBYTES(sp) + SREG x10, 10*REGBYTES(sp) + SREG x11, 11*REGBYTES(sp) + SREG x12, 12*REGBYTES(sp) + SREG x13, 13*REGBYTES(sp) + SREG x14, 14*REGBYTES(sp) + SREG x15, 15*REGBYTES(sp) + + csrr a0, mcause + csrr a1, mepc + mv a2, sp + jal handle_trap + csrw mepc, a0 + + # Remain in M-mode after eret + li t0, MSTATUS_PRV1 + csrs mstatus, t0 + + LREG x1, 1*REGBYTES(sp) + LREG x2, 2*REGBYTES(sp) + LREG x3, 3*REGBYTES(sp) + LREG x4, 4*REGBYTES(sp) + LREG x5, 5*REGBYTES(sp) + LREG x6, 6*REGBYTES(sp) + LREG x7, 7*REGBYTES(sp) + LREG x8, 8*REGBYTES(sp) + LREG x9, 9*REGBYTES(sp) + LREG x10, 10*REGBYTES(sp) + LREG x11, 11*REGBYTES(sp) + LREG x12, 12*REGBYTES(sp) + LREG x13, 13*REGBYTES(sp) + LREG x14, 14*REGBYTES(sp) + LREG x15, 15*REGBYTES(sp) + + addi sp, sp, 272 + mret + + .weak MACHINE_MODE_SOFT_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl MACHINE_MODE_SOFT_Handler +#else +#endif /* __GCC__ */ + .type MACHINE_MODE_SOFT_Handler, %function +MACHINE_MODE_SOFT_Handler: + + .weak CLINT_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl CLINT_Handler +#else +#endif /* __GCC__ */ + .type CLINT_Handler, %function +CLINT_Handler: + + .weak MACHINE_MODE_EXTERNAL_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl MACHINE_MODE_EXTERNAL_Handler +#else +#endif /* __GCC__ */ + .type MACHINE_MODE_EXTERNAL_Handler, %function +MACHINE_MODE_EXTERNAL_Handler: + + .weak WWDT_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl WWDT_Handler +#else +#endif /* __GCC__ */ + .type WWDT_Handler, %function +WWDT_Handler: + + .weak IWDT_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl IWDT_Handler +#else +#endif /* __GCC__ */ + .type IWDT_Handler, %function +IWDT_Handler: + + .weak LVD_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl LVD_Handler +#else +#endif /* __GCC__ */ + .type LVD_Handler, %function +LVD_Handler: + + .weak CSU_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl CSU_Handler +#else +#endif /* __GCC__ */ + .type CSU_Handler, %function +CSU_Handler: + + .weak CMU_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl CMU_Handler +#else +#endif /* __GCC__ */ + .type CMU_Handler, %function +CMU_Handler: + + .weak EXTI0_3_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl EXTI0_3_Handler +#else +#endif /* __GCC__ */ + .type EXTI0_3_Handler, %function +EXTI0_3_Handler: + + .weak EXTI4_7_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl EXTI4_7_Handler +#else +#endif /* __GCC__ */ + .type EXTI4_7_Handler, %function +EXTI4_7_Handler: + + .weak EXTI8_11_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl EXTI8_11_Handler +#else +#endif /* __GCC__ */ + .type EXTI8_11_Handler, %function +EXTI8_11_Handler: + + .weak EXTI12_15_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl EXTI12_15_Handler +#else +#endif /* __GCC__ */ + .type EXTI12_15_Handler, %function +EXTI12_15_Handler: + + .weak DMA_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl DMA_Handler +#else +#endif /* __GCC__ */ + .type DMA_Handler, %function +DMA_Handler: + + .weak USB_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl USB_Handler +#else +#endif /* __GCC__ */ + .type USB_Handler, %function +USB_Handler: + + .weak ADC_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl ADC_Handler +#else +#endif /* __GCC__ */ + .type ADC_Handler, %function +ADC_Handler: + + .weak AD16C4T_UP_TRIG_COM_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl AD16C4T_UP_TRIG_COM_Handler +#else +#endif /* __GCC__ */ + .type AD16C4T_UP_TRIG_COM_Handler, %function +AD16C4T_UP_TRIG_COM_Handler: + + .weak AD16C4T_CC_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl AD16C4T_CC_Handler +#else +#endif /* __GCC__ */ + .type AD16C4T_CC_Handler, %function +AD16C4T_CC_Handler: + + .weak BSTIM0_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl BSTIM0_Handler +#else +#endif /* __GCC__ */ + .type BSTIM0_Handler, %function +BSTIM0_Handler: + + .weak GPTIMB0_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl GPTIMB0_Handler +#else +#endif /* __GCC__ */ + .type GPTIMB0_Handler, %function +GPTIMB0_Handler: + + .weak GPTIMB1_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl GPTIMB1_Handler +#else +#endif /* __GCC__ */ + .type GPTIMB1_Handler, %function +GPTIMB1_Handler: + + .weak GPTIMB2_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl GPTIMB2_Handler +#else +#endif /* __GCC__ */ + .type GPTIMB2_Handler, %function +GPTIMB2_Handler: + + .weak AD16C4T_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl AD16C4T_Handler +#else +#endif /* __GCC__ */ + .type AD16C4T_Handler, %function +AD16C4T_Handler: + + .weak I2C0_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl I2C0_Handler +#else +#endif /* __GCC__ */ + .type I2C0_Handler, %function +I2C0_Handler: + + .weak I2C1_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl I2C1_Handler +#else +#endif /* __GCC__ */ + .type I2C1_Handler, %function +I2C1_Handler: + + .weak SPI0_I2S0_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl SPI0_I2S0_Handler +#else +#endif /* __GCC__ */ + .type SPI0_I2S0_Handler, %function +SPI0_I2S0_Handler: + + .weak SPI1_I2S1_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl SPI1_I2S1_Handler +#else +#endif /* __GCC__ */ + .type SPI1_I2S1_Handler, %function +SPI1_I2S1_Handler: + + .weak EUART0_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl EUART0_Handler +#else +#endif /* __GCC__ */ + .type EUART0_Handler, %function +EUART0_Handler: + + .weak EUART1_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl EUART1_Handler +#else +#endif /* __GCC__ */ + .type EUART1_Handler, %function +EUART1_Handler: + + .weak CUART0_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl CUART0_Handler +#else +#endif /* __GCC__ */ + .type CUART0_Handler, %function +CUART0_Handler: + + .weak CUART1_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl CUART1_Handler +#else +#endif /* __GCC__ */ + .type CUART1_Handler, %function +CUART1_Handler: + + .weak CUART2_Handler +#ifdef __GCC__ /* GCC Compiler */ + .globl CUART2_Handler +#else +#endif /* __GCC__ */ + .type CUART2_Handler, %function +CUART2_Handler: + +__exit: + j __exit + +//##--------------------------------------------------- +.section .bss + + .align 3 + .global g_base_irqstack + .global g_top_irqstack +g_base_irqstack: + .space StackSize //CONFIG_ARCH_INTERRUPTSTACK +g_top_irqstack: diff --git a/os/common/ext/CMSIS/ES32/ES32VF2264/system_es32vf2264.c b/os/common/ext/CMSIS/ES32/ES32VF2264/system_es32vf2264.c new file mode 100644 index 0000000000..71d846aa03 --- /dev/null +++ b/os/common/ext/CMSIS/ES32/ES32VF2264/system_es32vf2264.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2022 C-SKY Microsystems Co., Ltd. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file system.c + * @brief CSI Device System Source File + * @version V1.0 + * @date June 27 2022 + ******************************************************************************/ + +#include + +void board_init(void) +{ + + return; + +} + +int fputc(int ch, FILE *stream) +{ + (void)stream; + + return 0; +} + + +void SystemInit(void) +{ + return; +} diff --git a/os/common/ext/CMSIS/ES32/FS026/fs026.h b/os/common/ext/CMSIS/ES32/FS026/fs026.h index bd85a72f73..7272e25bc4 100644 --- a/os/common/ext/CMSIS/ES32/FS026/fs026.h +++ b/os/common/ext/CMSIS/ES32/FS026/fs026.h @@ -298,6 +298,9 @@ typedef enum IRQn #define END_SIM *MSG_END #define SIM_FAIL 0xFFFFAAAA #define SIM_PASS 0xFFFF5555 + +#define ES_USB_PERH_EP_MAX_INDEX (6U) + /******************************************************************************/ /* macros */ /******************************************************************************/ diff --git a/os/common/ports/RISCV-CLIC/chcore.c b/os/common/ports/RISCV-CLIC/chcore.c new file mode 100644 index 0000000000..2989589e7b --- /dev/null +++ b/os/common/ports/RISCV-CLIC/chcore.c @@ -0,0 +1,77 @@ +/* + ChibiOS - Copyright (C) 2021 Stefan Kerkmann. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chcore.c + * @brief Port related template code. + * + * @addtogroup port_core + * @details Non portable code templates. + * @{ + */ + +#include "ch.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +volatile uint32_t rt_interrupt_from_thread; +volatile uint32_t rt_interrupt_to_thread; +volatile uint32_t rt_thread_switch_interrupt_flag = 0; + +volatile thread_t * last_ntp; +volatile thread_t * last_otp; + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void switch_thread_by_handler(thread_t *ntp, thread_t *otp) +{ + last_ntp = ntp; + last_otp = otp; + + rt_interrupt_from_thread = (uint32_t)(&(otp->ctx.sp)); + rt_interrupt_to_thread = (uint32_t)(&(ntp->ctx.sp)); + rt_thread_switch_interrupt_flag = 1; + + *((uint8_t*)0xE080100C) = 0x1;//trig MACHINE_MODE_SOFT_Handler + + __enable_irq(); + __disable_irq(); +} + +/** @} */ diff --git a/os/common/ports/RISCV-CLIC/chcore.h b/os/common/ports/RISCV-CLIC/chcore.h new file mode 100644 index 0000000000..bdec63d5a3 --- /dev/null +++ b/os/common/ports/RISCV-CLIC/chcore.h @@ -0,0 +1,512 @@ +/* + ChibiOS - Copyright (C) 2021 Stefan Kerkmann. + ChibiOS - Copyright (C) 2020 Patrick Seidel. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file RISCV/chcore.h + * @brief Port related template macros and structures. + * + * @addtogroup port_core + * @{ + */ + +#ifndef CHCORE_H +#define CHCORE_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/** + * @name Port Capabilities and Constants + * @{ + */ +/** + * @brief This port supports a realtime counter. + */ +#define PORT_SUPPORTS_RT TRUE + +/** + * @brief Natural alignment constant. + * @note It is the minimum alignment for pointer-size variables. + */ +#define PORT_NATURAL_ALIGN sizeof(void *) + +/** + * @brief Stack alignment constant. + * @note It is the alignment required for the stack pointer. + */ +#define PORT_STACK_ALIGN sizeof(stkalign_t) + +/** + * @brief Working Areas alignment constant. + * @note It is the alignment to be enforced for thread working areas. + */ +#define PORT_WORKING_AREA_ALIGN sizeof(stkalign_t) +/** @} */ + +/** + * @name Architecture and Compiler + * @{ + */ +/** + * @brief Macro defining a RISCV architecture. + */ +#define PORT_ARCHITECTURE_RISCV + +/** + * @brief Macro defining the specific RISCV architecture. + */ +#define PORT_ARCHITECTURE_RISCV_YYY + +/** + * @brief Name of the implemented architecture. + */ +#define PORT_ARCHITECTURE_NAME "RISC-V" + +/** + * @brief Name of the architecture variant. + */ +#define PORT_CORE_VARIANT_NAME "RV32EMC" + +/** + * @brief Compiler name and version. + */ +#if defined(__GNUC__) || defined(__DOXYGEN__) +#define PORT_COMPILER_NAME "GCC " __VERSION__ + +#else +#error "unsupported compiler" +#endif + +/** + * @brief Port-specific information string. + */ +#define PORT_INFO "RV32EMC - CLIC" +/** @} */ + +/* Inclusion of the RISC-V implementation specific parameters.*/ +#if !defined(_FROM_ASM_) + +#include "eclic_parameters.h" +#include "nmsis_core.h" + +#endif + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + */ +#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__) +#define PORT_IDLE_THREAD_STACK_SIZE 64 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + */ +#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__) +#define PORT_INT_REQUIRED_STACK 256 +#endif + +/** + * @brief Enables an alternative timer implementation. + * @details Usually the port uses a timer interface defined in the file + * @p chcore_timer.h, if this option is enabled then the file + * @p chcore_timer_alt.h is included instead. + */ +#if !defined(PORT_USE_ALT_TIMER) || defined(__DOXYGEN__) +#define PORT_USE_ALT_TIMER FALSE +#endif + +/** + * @brief Enables a "wait for interrupt" instruction in the idle loop. + */ +#if !defined(PORT_RISCV_WFI_SLEEP_IDLE) || defined(__DOXYGEN__) +#define PORT_RISCV_ENABLE_WFI_IDLE FALSE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +/** + * @brief Type of stack and memory alignment enforcement. + * @note In this architecture the stack alignment is enforced to 128 bits. + */ +typedef struct { + uint8_t padding[16]; +} stkalign_t ALIGNED_VAR(16); + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + * @note GP is not saved because it is assumed to be immutable + * during the system life cycle. + */ +struct port_extctx { + uint32_t ra; + uint32_t tp; + uint32_t t0; + uint32_t t1; + uint32_t t2; + uint32_t a0; + uint32_t a1; + uint32_t a2; + uint32_t a3; + uint32_t a4; + uint32_t a5; + uint32_t mepc; + uint32_t mcause; + uint32_t msubm; +#if !defined(__riscv_32e) + uint32_t a6; + uint32_t a7; + uint32_t t3; + uint32_t t4; + uint32_t t5; + uint32_t t6; +#endif +}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching. + * @note GP and TP are not saved because those are assumed to be immutable + * during the system life cycle. + */ +struct port_intctx { + uint32_t epc; /* epc - epc - program counter */ + uint32_t ra; /* x1 - ra - return address for jumps */ + uint32_t mstatus; /* - machine status register */ + uint32_t gp; /* x3 - gp - global pointer */ + uint32_t tp; /* x4 - tp - thread pointer */ + uint32_t t0; /* x5 - t0 - temporary register 0 */ + uint32_t t1; /* x6 - t1 - temporary register 1 */ + uint32_t t2; /* x7 - t2 - temporary register 2 */ + uint32_t s0; /* x8 - s0/fp - saved register 0 or frame pointer */ + uint32_t s1; /* x9 - s1 - saved register 1 */ + uint32_t a0; /* x10 - a0 - return value or function argument 0 */ + uint32_t a1; /* x11 - a1 - return value or function argument 1 */ + uint32_t a2; /* x12 - a2 - function argument 2 */ + uint32_t a3; /* x13 - a3 - function argument 3 */ + uint32_t a4; /* x14 - a4 - function argument 4 */ + uint32_t a5; /* x15 - a5 - function argument 5 */ +}; + +/** + * @brief Platform dependent part of the @p thread_t structure. + * @details This structure usually contains just the saved stack pointer + * defined as a pointer to a @p port_intctx structure. + */ +struct port_context { + struct port_intctx *sp; +}; + +#endif /* !defined(_FROM_ASM_) */ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p port_intctx structure. + */ +#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) \ + { \ + (tp)->ctx.sp = (struct port_intctx *)((uint8_t *)(wtop) - \ + sizeof(struct port_intctx)); \ + (tp)->ctx.sp->epc = (uint32_t)_port_thread_start; \ + (tp)->ctx.sp->ra = (uint32_t)_port_thread_start; \ + (tp)->ctx.sp->s0 = (uint32_t)(pf); \ + (tp)->ctx.sp->s1 = (uint32_t)(arg); \ + } + + +/** + * @brief Computes the thread working area global size. + * @note There is no need to perform alignments in this macro. + */ +#define PORT_WA_SIZE(n) \ + (sizeof(struct port_intctx) + sizeof(struct port_extctx) + ((size_t)(n)) + \ + ((size_t)(PORT_INT_REQUIRED_STACK))) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + * + * @param[in] s the name to be assigned to the stack array + * @param[in] n the stack size to be assigned to the thread + */ +#define PORT_WORKING_AREA(s, n) \ + stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof(stkalign_t)] + +/** + * @brief Priority level verification macro. + */ +#define PORT_IRQ_IS_VALID_PRIORITY(n) true + +/** + * @brief Priority level verification macro. + */ +#define PORT_IRQ_IS_VALID_KERNEL_PRIORITY(n) true + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#ifdef __cplusplus +#define PORT_IRQ_HANDLER(id) \ + extern "C" __attribute__((interrupt)) void id(void) +#else +#define PORT_IRQ_HANDLER(id) __attribute__((interrupt)) void id(void) +#endif + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#ifdef __cplusplus +#define PORT_FAST_IRQ_HANDLER(id) \ + extern "C" __attribute__((interrupt)) void id(void) +#else +#define PORT_FAST_IRQ_HANDLER(id) __attribute__((interrupt)) void id(void) +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#define port_switch(ntp, otp) switch_thread_by_handler(ntp, otp) + +/** + * @brief Returns a word representing a critical section status. + * + * @return The critical section status. + */ +#define port_get_lock_status() port_get_irq_status() + +/** + * @brief Determines if in a critical section. + * + * @param[in] sts status word returned by @p port_get_lock_status() + * @return The current status. + * @retval false if running outside a critical section. + * @retval true if running within a critical section. + */ +#define port_is_locked(sts) !port_irq_enabled(sts) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +#ifdef __cplusplus +extern "C" { +#endif +void _port_switch(thread_t *ntp, thread_t *otp); +void _port_switch_after_isr(void); +void _port_switch_from_isr(void); +void _port_exit_from_isr(void); +void _port_thread_start(void); +bool _port_irq_epilogue(void); + void switch_thread_by_handler(thread_t *ntp, thread_t *otp); +#ifdef __cplusplus +} +#endif + +#endif /* !defined(_FROM_ASM_) */ + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +/** + * @brief Port-related initialization code. + */ +static inline void port_init(os_instance_t *oip){} + +/** + * @brief Returns a word encoding the current interrupts status. + * + * @return The interrupts status. + */ +static inline syssts_t port_get_irq_status(void) { + return (syssts_t)__RV_CSR_READ(CSR_MSTATUS); +} + +/** + * @brief Checks the interrupt status. + * + * @param[in] sts the interrupt status word + * + * @return The interrupt status. + * @retval false the word specified a disabled interrupts status. + * @retval true the word specified an enabled interrupts status. + */ +static inline bool port_irq_enabled(syssts_t sts) { return sts & MSTATUS_MIE; } + +/** + * @brief Determines the current execution context. + * + * @return The execution context. + * @retval false not running in ISR mode. + * @retval true running in ISR mode. + */ +static inline bool port_is_isr_context(void) { + /* msubm.typ == 1 is interrupt handling mode. */ + return false;//change context in special isr, always reutrn false. //__RV_CSR_READ(CSR_MSUBM) & (0x1 << 6); +} + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform more + * actions. + */ +static inline void port_lock(void) { __disable_irq(); } + +/** + * @brief Kernel-unlock action. + * @details Usually this function just enables interrupts but may perform more + * actions. + */ +static inline void port_unlock(void) { __enable_irq(); } + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + */ +static inline void port_lock_from_isr(void) { port_lock(); } + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + */ +static inline void port_unlock_from_isr(void) { port_unlock(); } + +/** + * @brief Disables all the interrupt sources. + * @note Of course non-maskable interrupt sources are not included. + */ +static inline void port_disable(void) { __disable_irq(); } + +/** + * @brief Disables the interrupt sources below kernel-level priority. + * @note Interrupt sources above kernel level remains enabled. + */ +static inline void port_suspend(void) { __disable_irq(); } + +/** + * @brief Enables all the interrupt sources. + */ +static inline void port_enable(void) { __enable_irq(); } + +/** + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + */ +static inline void port_wait_for_interrupt(void) { +#if PORT_RISCV_ENABLE_WFI_IDLE + __WFI(); +#endif +} + +/** + * @brief Returns the current value of the realtime counter. + * + * @return The realtime counter value. + */ +static inline rtcnt_t port_rt_get_counter_value(void) { + return (rtcnt_t)__get_rv_cycle(); +} + +#endif /* !defined(_FROM_ASM_) */ + +/*===========================================================================*/ +/* Module late inclusions. */ +/*===========================================================================*/ + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +#if CH_CFG_ST_TIMEDELTA > 0 +#include "chcore_timer.h" +#endif /* CH_CFG_ST_TIMEDELTA > 0 */ + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* CHCORE_H */ + +/** @} */ diff --git a/os/common/ports/RISCV-CLIC/chcore_timer.h b/os/common/ports/RISCV-CLIC/chcore_timer.h new file mode 100644 index 0000000000..0361b2ee03 --- /dev/null +++ b/os/common/ports/RISCV-CLIC/chcore_timer.h @@ -0,0 +1,121 @@ +/* + ChibiOS - Copyright (C) 2020 Patrick Seidel. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file chcore_timer.h + * @brief System timer header file. + * + * @addtogroup RISCV_TIMER + * @{ + */ + +#ifndef CHCORE_TIMER_H +#define CHCORE_TIMER_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +void stStartAlarm(systime_t time); +void stStopAlarm(void); +void stSetAlarm(systime_t time); +systime_t stGetCounter(void); +systime_t stGetAlarm(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +/** + * @brief Starts the alarm. + * @note Makes sure that no spurious alarms are triggered after + * this call. + * + * @param[in] time the time to be set for the first alarm + * + * @notapi + */ +static inline void port_timer_start_alarm(systime_t time) { + + stStartAlarm(time); +} + +/** + * @brief Stops the alarm interrupt. + * + * @notapi + */ +static inline void port_timer_stop_alarm(void) { stStopAlarm(); } + +/** + * @brief Sets the alarm time. + * + * @param[in] time the time to be set for the next alarm + * + * @notapi + */ +static inline void port_timer_set_alarm(systime_t time) { stSetAlarm(time); } + +/** + * @brief Returns the system time. + * + * @return The system time. + * + * @notapi + */ +static inline systime_t port_timer_get_time(void) { return stGetCounter(); } + +/** + * @brief Returns the current alarm time. + * + * @return The currently set alarm time. + * + * @notapi + */ +static inline systime_t port_timer_get_alarm(void) { return stGetAlarm(); } + +#endif /* CHCORE_TIMER_H */ + +/** @} */ diff --git a/os/common/ports/RISCV-CLIC/chtypes.h b/os/common/ports/RISCV-CLIC/chtypes.h new file mode 100644 index 0000000000..f2fd95a5b5 --- /dev/null +++ b/os/common/ports/RISCV-CLIC/chtypes.h @@ -0,0 +1,101 @@ +/* + ChibiOS - Copyright (C) 2020 Patrick Seidel. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chtypes.h + * @brief System types template. + * + * @addtogroup port_types + * @details The types defined in this file may change depending on the target + * architecture. You may also try to optimize the size of the various + * types in order to privilege size or performance, be careful in + * doing so. + * @{ + */ + +#ifndef CHTYPES_H +#define CHTYPES_H + +#include +#include +#include + +/** + * @name Kernel types + * @{ + */ +typedef uint64_t rtcnt_t; /**< Realtime counter. */ +typedef uint64_t rttime_t; /**< Realtime accumulator. */ +typedef uint32_t syssts_t; /**< System status word. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint8_t tslices_t; /**< Thread time slices counter.*/ +typedef uint32_t tprio_t; /**< Thread priority. */ +typedef int32_t msg_t; /**< Inter-thread message. */ +typedef int32_t eventid_t; /**< Numeric event identifier. */ +typedef uint32_t eventmask_t; /**< Mask of event identifiers. */ +typedef uint32_t eventflags_t; /**< Mask of event flags. */ +typedef int32_t cnt_t; /**< Generic signed counter. */ +typedef uint32_t ucnt_t; /**< Generic unsigned counter. */ +/** @} */ + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Makes functions not inlineable. + * @note If the compiler does not support such attribute then the + * realtime counter precision could be degraded. + */ +#define NOINLINE __attribute__((noinline)) + +/** + * @brief Optimized thread function declaration macro. + */ +#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg) + +/** + * @brief Packed variable specifier. + */ +#define PACKED_VAR __attribute__((packed)) + +/** + * @brief Memory alignment enforcement for variables. + */ +#define ALIGNED_VAR(n) __attribute__((aligned(n))) + +/** + * @brief Size of a pointer. + * @note To be used where the sizeof operator cannot be used, preprocessor + * expressions for example. + */ +#define SIZEOF_PTR 4 + +/** + * @brief True if alignment is low-high in current architecture. + */ +#define REVERSE_ORDER 1 + +#endif /* CHTYPES_H */ + +/** @} */ diff --git a/os/common/ports/RISCV-CLIC/compilers/GCC/chcoreasm.S b/os/common/ports/RISCV-CLIC/compilers/GCC/chcoreasm.S new file mode 100644 index 0000000000..ee272ebfd7 --- /dev/null +++ b/os/common/ports/RISCV-CLIC/compilers/GCC/chcoreasm.S @@ -0,0 +1,456 @@ +/* + ChibiOS - Copyright (C) 2021 Stefan Kerkmann. + ChibiOS - Copyright (C) 2020 Patrick Seidel. + + This file is part of ChibiOS. + + ChibiOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file compilers/GCC/chcoreasm.S + * @brief RISC-V ECLIC architecture port low level code. + * + * @addtogroup RISCV_ECLIC_GCC_CORE + * @{ + */ + +#if !defined(FALSE) || defined(__DOXYGEN__) +#define FALSE 0 +#endif + +#if !defined(TRUE) || defined(__DOXYGEN__) +#define TRUE 1 +#endif + +#define _FROM_ASM_ +#include "chlicense.h" +#include "chconf.h" +#include "chcore.h" +#include "riscv_encoding.h" + +#if !defined(__DOXYGEN__) + + +# -------------------------------------------------------------------------- +# RTOS-specific context offset. +# -------------------------------------------------------------------------- +#if defined(_CHIBIOS_RT_CONF_) +#define CONTEXT_OFFSET 12 +#elif defined(_CHIBIOS_NIL_CONF_) +#define CONTEXT_OFFSET 0 +#else +#error "invalid chconf.h" +#endif + +# Disable Interrupts globally. +.macro DISABLE_MIE + csrc CSR_MSTATUS, MSTATUS_MIE +.endm + +# Enable Interrupts globally. +.macro ENABLE_MIE + csrs CSR_MSTATUS, MSTATUS_MIE +.endm + +# -------------------------------------------------------------------------- +# Interrupt context save macro. Saves all caller save registers +# and status csr registers on the stack. +# -------------------------------------------------------------------------- +.macro SAVE_CONTEXT + # Allocate stack space for context saving +#if !defined(__riscv_32e) + addi sp, sp, -20*REGBYTES +#else + addi sp, sp, -14*REGBYTES +#endif /* __riscv_32e */ + + # Store CSR mepc to stack using pushmepc + csrrwi zero, CSR_PUSHMEPC, 11 + # Store CSR mcause to stack using pushmcause + csrrwi zero, CSR_PUSHMCAUSE, 12 + # Store CSR msubm to stack using pushmsub + csrrwi zero, CSR_PUSHMSUBM, 13 + + STORE ra, 0*REGBYTES(sp) + STORE tp, 1*REGBYTES(sp) + STORE t0, 2*REGBYTES(sp) + STORE t1, 3*REGBYTES(sp) + STORE t2, 4*REGBYTES(sp) + STORE a0, 5*REGBYTES(sp) + STORE a1, 6*REGBYTES(sp) + STORE a2, 7*REGBYTES(sp) + STORE a3, 8*REGBYTES(sp) + STORE a4, 9*REGBYTES(sp) + STORE a5, 10*REGBYTES(sp) +#if !defined(__riscv_32e) + STORE a6, 14*REGBYTES(sp) + STORE a7, 15*REGBYTES(sp) + STORE t3, 16*REGBYTES(sp) + STORE t4, 17*REGBYTES(sp) + STORE t5, 18*REGBYTES(sp) + STORE t6, 19*REGBYTES(sp) +#endif +.endm + +# -------------------------------------------------------------------------- +# Interrupt context restore macro. Restores all caller save +# registers and status csr registers from stack. +# -------------------------------------------------------------------------- +.macro RESTORE_CONTEXT + LOAD t0, 11*REGBYTES(sp) + csrw CSR_MEPC, t0 + LOAD t0, 12*REGBYTES(sp) + csrw CSR_MCAUSE, t0 + LOAD t0, 13*REGBYTES(sp) + csrw CSR_MSUBM, t0 + + LOAD ra, 0*REGBYTES(sp) + LOAD tp, 1*REGBYTES(sp) + LOAD t0, 2*REGBYTES(sp) + LOAD t1, 3*REGBYTES(sp) + LOAD t2, 4*REGBYTES(sp) + LOAD a0, 5*REGBYTES(sp) + LOAD a1, 6*REGBYTES(sp) + LOAD a2, 7*REGBYTES(sp) + LOAD a3, 8*REGBYTES(sp) + LOAD a4, 9*REGBYTES(sp) + LOAD a5, 10*REGBYTES(sp) +#if !defined(__riscv_32e) + LOAD a6, 14*REGBYTES(sp) + LOAD a7, 15*REGBYTES(sp) + LOAD t3, 16*REGBYTES(sp) + LOAD t4, 17*REGBYTES(sp) + LOAD t5, 18*REGBYTES(sp) + LOAD t6, 19*REGBYTES(sp) + + # De-allocate the stack space + addi sp, sp, 20*REGBYTES +#else + addi sp, sp, 14*REGBYTES +#endif /* __riscv_32e */ +.endm + +# -------------------------------------------------------------------------- +# Trap entry point (_start_trap) +# -------------------------------------------------------------------------- +.section .trap, "ax" +.option push +.option norelax +.align 6 +.globl _start_trap + _start_trap: + # Save the caller saving registers (context) + SAVE_CONTEXT + + # Set the function argument + csrr a0, mcause + mv a1, sp + csrr a2, CSR_MDCAUSE + csrr a3, CSR_MSUBM + + # Call the function + call handle_trap + + # Restore the caller saving registers (context) + RESTORE_CONTEXT + + # Return to regular code + mret +.option pop + +# -------------------------------------------------------------------------- +# Start a thread by invoking its work function. +# +# Threads execution starts here, the code leaves the system critical zone +# and then jumps into the thread function passed in register S0. The +# register S1 contains the thread parameter. The function chThdExit() is +# called on thread function return. +# -------------------------------------------------------------------------- +.globl _port_thread_start +_port_thread_start: +#if CH_DBG_SYSTEM_STATE_CHECK + jal ra, _dbg_check_unlock +#endif +#if CH_DBG_STATISTICS + jal ra, _stats_stop_measure_crit_thd +#endif + ENABLE_MIE + mv a0, s1 + jalr ra, s0 + li a0, 0 # MSG_OK + jal ra, chThdExit + +_zombies: + j _zombies + +# -------------------------------------------------------------------------- +# Performs a context switch between two threads. +# a0 = ntp, a1 = otp +# -------------------------------------------------------------------------- +.option push +.option norelax +.align 4 +.globl _port_switch +.type _port_switch,@function +_port_switch: + # OLD THREAD CONTEXT SAVE BEGIN + # Allocate space for port_intctx structure on the threading stack. + # The stackpointer is 16 byte aligned to be compliant with risc-v abi. +#if !defined(__riscv_32e) + addi sp, sp, -16*REGBYTES +#else + addi sp, sp, -4*REGBYTES +#endif + + # Store callee save registers + STORE ra, 0*REGBYTES(sp) + STORE s0, 1*REGBYTES(sp) + STORE s1, 2*REGBYTES(sp) +#if !defined(__riscv_32e) + STORE s2, 3*REGBYTES(sp) + STORE s3, 4*REGBYTES(sp) + STORE s4, 5*REGBYTES(sp) + STORE s5, 6*REGBYTES(sp) + STORE s6, 7*REGBYTES(sp) + STORE s7, 8*REGBYTES(sp) + STORE s8, 9*REGBYTES(sp) + STORE s9, 10*REGBYTES(sp) + STORE s10, 11*REGBYTES(sp) + STORE s11, 12*REGBYTES(sp) +#endif + + # Store stackpointer in otp->ctx + STORE sp, CONTEXT_OFFSET(a1) + # OLD THREAD CONTEXT SAVE END + + # NEW THREAD CONTEXT RESTORE BEGIN + # Load stackpointer from ntp->ctx + LOAD sp, CONTEXT_OFFSET(a0) + + LOAD ra, 0*REGBYTES(sp) + LOAD s0, 1*REGBYTES(sp) + LOAD s1, 2*REGBYTES(sp) +#if !defined(__riscv_32e) + LOAD s2, 3*REGBYTES(sp) + LOAD s3, 4*REGBYTES(sp) + LOAD s4, 5*REGBYTES(sp) + LOAD s5, 6*REGBYTES(sp) + LOAD s6, 7*REGBYTES(sp) + LOAD s7, 8*REGBYTES(sp) + LOAD s8, 9*REGBYTES(sp) + LOAD s9, 10*REGBYTES(sp) + LOAD s10, 11*REGBYTES(sp) + LOAD s11, 12*REGBYTES(sp) + + # De-allocate space on the threading stack + addi sp, sp, 16*REGBYTES +#else + addi sp, sp, 4*REGBYTES +#endif + # NEW THREAD CONTEXT RESTORE END + + # Jump to return address loaded into ra + ret +.option pop + +# -------------------------------------------------------------------------- +# IRQ entry point +# -------------------------------------------------------------------------- +.section .text +.option push +.option norelax +.align 2 +.globl _irq_handler +_irq_handler: + # Save all caller registers and csr registers on the thread stack + SAVE_CONTEXT + + # The special CSR read/write operation, which is actually Claim the CLIC to + # find its pending highest ID, if the ID is not 0, then automatically enable + # the mstatus.MIE, and jump to its vector-entry-label, and update the link register. + csrrw ra, CSR_JALMNXTI, ra + + # Critical Section Disable Interrupts Globaly + DISABLE_MIE + + # No reschedule is necessary, just restore irq context and exit machine mode. + beq a0, zero, _port_exit_from_isr + + # Context switch is necessary, load switching routine into mepc + la a0, _port_switch_from_isr + csrw mepc, a0 + + # Interrupt handling and context restoring is handled differently in nucleisys cores. + # mstatus.mpie and mstatus.mpp are mirror fields of mcause.mpie and mcause.mpp. + # Therefore we directly set the bits in mcause and not mstatus. + # See https://doc.nucleisys.com/nuclei_spec/isa/core_csr.html#mcause + + # Context switch is a critical section, so disable interrupts on return. + # Clear mcause.mpie. + li a0, 0x8000000 + csrc mcause, a0 + + # Set previous privelege mode to machine mode to enforce it on return. + # Set mcause.mpp to 0x3 (== machine mode). + li a0, 0x30000000 + csrs mcause, a0 + + mret + +.option pop + +.globl handle_trap +.weak handle_trap +handle_trap: + j handle_trap # jump to handle_trap + +# -------------------------------------------------------------------------- +# Post-IRQ switch code. +# +# Exception handlers return here for context switching. +# -------------------------------------------------------------------------- +.section .text +.option push +.option norelax +.align 4 +.globl _port_switch_from_isr +_port_switch_from_isr: +#if CH_DBG_STATISTICS + jal ra, _stats_start_measure_crit_thd +#endif +#if CH_DBG_SYSTEM_STATE_CHECK + jal ra, _dbg_check_lock +#endif + # Calls _port_switch at the end of the function + jal ra, chSchDoPreemption +#if CH_DBG_SYSTEM_STATE_CHECK + jal ra, _dbg_check_unlock +#endif +#if CH_DBG_STATISTICS + jal ra, _stats_stop_measure_crit_thd +#endif + +.globl _port_exit_from_isr +_port_exit_from_isr: + # Restore caller registers and csr registers from the thread stack + RESTORE_CONTEXT + + # Leave interrupt handling and return to address stored in mepc. + mret + +.option pop + + +# -------------------------------------------------------------------------- +# IRQ switch code. +# +# Use SW_handler to switch thread. +# -------------------------------------------------------------------------- +.section .text +.option push +.option norelax +.align 4 + +// .global SW_handler +//SW_handler: + .global vector3 +vector3: + li t0, 0x08 + csrc mstatus, t0 + + /* save all from thread context */ + addi sp, sp, -16 * REGBYTES + + STORE x5, 5 * REGBYTES(sp) + STORE x1, 1 * REGBYTES(sp) + /* Mandatory set the MPIE of mstatus */ + li t0, 0x80 + STORE t0, 2 * REGBYTES(sp) + STORE x4, 4 * REGBYTES(sp) + STORE x6, 6 * REGBYTES(sp) + STORE x7, 7 * REGBYTES(sp) + STORE x8, 8 * REGBYTES(sp) + STORE x9, 9 * REGBYTES(sp) + STORE x10, 10 * REGBYTES(sp) + STORE x11, 11 * REGBYTES(sp) + STORE x12, 12 * REGBYTES(sp) + STORE x13, 13 * REGBYTES(sp) + STORE x14, 14 * REGBYTES(sp) + STORE x15, 15 * REGBYTES(sp) + + /* switch to interrupt stack */ +// csrrw sp,mscratch,sp + /* interrupt handle */ +// call rt_interrupt_enter + /* Do the work after saving the above */ +// jal rt_hw_do_after_save_above + +// call rt_interrupt_leave + /* switch to from thread stack */ +// csrrw sp,mscratch,sp + + /* Determine whether to trigger scheduling at the interrupt function */ + la t0, rt_thread_switch_interrupt_flag + lw t2, 0(t0) + beqz t2, 1f + /* clear the flag of rt_thread_switch_interrupt_flag */ + sw zero, 0(t0) + + csrr a0, mepc + STORE a0, 0 * REGBYTES(sp) + + la t0, rt_interrupt_from_thread + LOAD t1, 0(t0) + STORE sp, 0(t1) + + la t0, rt_interrupt_to_thread + LOAD t1, 0(t0) + LOAD sp, 0(t1) + + LOAD a0, 0 * REGBYTES(sp) + csrw mepc, a0 +1: + LOAD x1, 1 * REGBYTES(sp) + + /* Set the mode after MRET */ + li t0, 0x1800 + csrs mstatus, t0 + LOAD t0, 2 * REGBYTES(sp) + csrs mstatus, t0 + + LOAD x4, 4 * REGBYTES(sp) + LOAD x5, 5 * REGBYTES(sp) + LOAD x6, 6 * REGBYTES(sp) + LOAD x7, 7 * REGBYTES(sp) + LOAD x8, 8 * REGBYTES(sp) + LOAD x9, 9 * REGBYTES(sp) + LOAD x10, 10 * REGBYTES(sp) + LOAD x11, 11 * REGBYTES(sp) + LOAD x12, 12 * REGBYTES(sp) + LOAD x13, 13 * REGBYTES(sp) + LOAD x14, 14 * REGBYTES(sp) + LOAD x15, 15 * REGBYTES(sp) + + addi sp, sp, 16 * REGBYTES + + mret + + + +.option pop + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/common/ports/RISCV-CLIC/compilers/GCC/mk/port.mk b/os/common/ports/RISCV-CLIC/compilers/GCC/mk/port.mk new file mode 100644 index 0000000000..d882e6daa7 --- /dev/null +++ b/os/common/ports/RISCV-CLIC/compilers/GCC/mk/port.mk @@ -0,0 +1,12 @@ +# List of the ChibiOS/RT RISCV generic port files. +PORTSRC = $(CHIBIOS_CONTRIB)/os/common/ports/RISCV-CLIC/chcore.c + +PORTASM = $(CHIBIOS_CONTRIB)/os/common/ports/RISCV-CLIC/compilers/GCC/chcoreasm.S + +PORTINC = $(CHIBIOS_CONTRIB)/os/common/ports/RISCV-CLIC \ + $(CHIBIOS)/os/common/ports/RISCV-CLIC/compilers/GCC + +# Shared variables +ALLXASMSRC += $(PORTASM) +ALLCSRC += $(PORTSRC) +ALLINC += $(PORTINC) diff --git a/os/common/startup/RISCV-CLIC/compilers/GCC/crt0.S b/os/common/startup/RISCV-CLIC/compilers/GCC/crt0.S new file mode 100644 index 0000000000..326988e38d --- /dev/null +++ b/os/common/startup/RISCV-CLIC/compilers/GCC/crt0.S @@ -0,0 +1,277 @@ +/* + ChibiOS - Copyright (C) 2020 Patrick Seidel + ChibiOS - Copyright (C) 2021 Stefan Kerkmann + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file crt0.S + * @brief RISC-V ECLIC startup file for ChibiOS. + * + * @addtogroup RISCV_ECLIC_STARTUP + * @{ + */ + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#if !defined(FALSE) || defined(__DOXYGEN__) +#define FALSE 0 +#endif + +#if !defined(TRUE) || defined(__DOXYGEN__) +#define TRUE 1 +#endif + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Core initialization switch. + */ +#if !defined(CRT0_INIT_CORE) || defined(__DOXYGEN__) +#define CRT0_INIT_CORE TRUE +#endif + +/** + * @brief Stack segments initialization switch. + */ +#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__) +#define CRT0_STACKS_FILL_PATTERN 0x55555555 +#endif + +/** + * @brief Stack segments initialization switch. + */ +#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__) +#define CRT0_INIT_STACKS TRUE +#endif + +/** + * @brief DATA segment initialization switch. + */ +#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__) +#define CRT0_INIT_DATA TRUE +#endif + +/** + * @brief BSS segment initialization switch. + */ +#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__) +#define CRT0_INIT_BSS TRUE +#endif + +/** + * @brief RAM areas initialization switch. + */ +#if !defined(CRT0_INIT_RAM_AREAS) || defined(__DOXYGEN__) +#define CRT0_INIT_RAM_AREAS TRUE +#endif + +/** + * @brief Constructors invocation switch. + */ +#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__) +#define CRT0_CALL_CONSTRUCTORS TRUE +#endif + +/** + * @brief Destructors invocation switch. + */ +#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__) +#define CRT0_CALL_DESTRUCTORS TRUE +#endif + +/*===========================================================================*/ +/* Code section. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) + +#include "riscv_encoding.h" + +.section .crt0, "ax" +.global _start +.type _start, @function +_start: + /* Disable interrupts globaly */ + csrc CSR_MSTATUS, MSTATUS_MIE + + /* Jump to logical address first to ensure correct operation of RAM region */ +// la a0, _start +// li a1, 1 +// slli a1, a1, 29 +// bleu a1, a0, _crt0_entry +// srli a1, a1, 2 +// bleu a1, a0, _crt0_entry + la a0, _crt0_entry +// add a0, a0, a1 + jr a0 + +/* + * CRT0 entry point. + */ +.global _crt0_entry +.type _crt0_entry, @function +_crt0_entry: + /* Disable interrupts globaly */ + csrc CSR_MSTATUS, MSTATUS_MIE + + /* Initialize global pointer gp for linker relaxation.*/ + .option push + .option norelax + la gp, __global_pointer$ + .option pop + + /* Initialize stack pointer sp */ + la sp, __process_stack_end__ + + /* + * Set the the NMI base mnvec to share + * with mtvec by setting CSR_MMISC_CTL + * bit 9 NMI_CAUSE_FFF to 1 + */ +// li t0, MMISC_CTL_NMI_CAUSE_FFF +// csrs CSR_MMISC_CTL, t0 + + /* + * Intialize ECLIC vector interrupt + * base address mtvt to vector_base + */ + la t0, vector_base + csrw CSR_MTVT, t0 + + /* + * Set ECLIC non-vector entry to be controlled + * by mtvt2 CSR register. + * Intialize ECLIC non-vector interrupt + * base address mtvt2 to _irq_handler. + */ +// la t0, _irq_handler +// csrw CSR_MTVT2, t0 +// csrs CSR_MTVT2, 0x1 + + /* + * Set Exception Entry MTVEC to _start_trap + * Due to settings above, Exception and NMI + * will share common entry. + */ + la t0, _start_trap + csrw CSR_MTVEC, t0 + + /* Set the interrupt processing mode to ECLIC mode */ + li t0, 0x3f + csrc CSR_MTVEC, t0 + csrs CSR_MTVEC, 0x3 + + /* Enable mcycle and minstret counters */ +// csrci CSR_MCOUNTINHIBIT, 0x5 + +#if CRT0_INIT_CORE == TRUE + /* Core initialization.*/ + jal ra, __core_init +#endif + + /* Early initialization..*/ + jal ra, __early_init + +#if CRT0_INIT_STACKS == TRUE + li a0, CRT0_STACKS_FILL_PATTERN + /* Main Stack initialization. Note, it assumes that the + stack size is a multiple of 4 so the linker file must + ensure this.*/ + la a1, __process_stack_base__ + la a2, __process_stack_end__ +psloop: + bge a1, a2, endpsloop + sw a0, 0(a1) + addi a1, a1, 4 + j psloop +endpsloop: +#endif + +#if CRT0_INIT_DATA == TRUE + /* Data initialization. Note, it assumes that the DATA size + is a multiple of 4 so the linker file must ensure this.*/ + la a0, __textdata_base__ + la a1, __data_base__ + la a2, __data_end__ +dloop: + bge a1, a2, enddloop + lw a3, 0(a0) + sw a3, 0(a1) + addi a0, a0, 4 + addi a1, a1, 4 + j dloop +enddloop: +#endif + +#if CRT0_INIT_BSS == TRUE + /* BSS initialization. Note, it assumes that the DATA size + is a multiple of 4 so the linker file must ensure this.*/ + la a1, __bss_base__ + la a2, __bss_end__ +bloop: + bge a1, a2, endbloop + sw zero, 0(a1) + addi a1, a1, 4 + j bloop +endbloop: +#endif + +#if CRT0_INIT_RAM_AREAS == TRUE + /* RAM areas initialization.*/ + jal ra, __init_ram_areas +#endif + + /* Late initialization..*/ + jal ra, __late_init + +#if CRT0_CALL_CONSTRUCTORS == TRUE + /* Constructors invocation.*/ + la s1, __init_array_base__ + la t2, __init_array_end__ +initloop: + bge s1, t2, endinitloop + lw a0, 0(s1) + jalr ra, a0, 0 + addi s1, s1, 4 + j initloop +endinitloop: +#endif + + /* Main program invocation, r0 contains the returned value.*/ + jal ra, main + +#if CRT0_CALL_DESTRUCTORS == TRUE + /* Destructors invocation.*/ + la s1, __fini_array_base__ + la t2, __fini_array_end__ +finiloop: + bge s1, t2, endfiniloop + lw a0, 0(s1) + jalr ra, a0, 0 + addi s1, s1, 4 + j finiloop +endfiniloop: +#endif + + /* Branching to the defined exit handler.*/ + jal ra, __default_exit + +#endif + +/** @} */ diff --git a/os/common/startup/RISCV-CLIC/compilers/GCC/crt1.c b/os/common/startup/RISCV-CLIC/compilers/GCC/crt1.c new file mode 100644 index 0000000000..b26c936bc8 --- /dev/null +++ b/os/common/startup/RISCV-CLIC/compilers/GCC/crt1.c @@ -0,0 +1,212 @@ +/* + ChibiOS - Copyright (C) 2020 Patrick Seidel + ChibiOS - Copyright (C) 2021 Stefan Kerkmann + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file crt1.c + * @brief Startup stub functions. + * + * @addtogroup RISCV_ECLIC_STARTUP + * @{ + */ + +#include +#include + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +#if !defined(CRT1_AREAS_NUMBER) || defined(__DOXYGEN__) +#define CRT1_AREAS_NUMBER 8 +#endif + +#if (CRT1_AREAS_NUMBER < 0) || (CRT1_AREAS_NUMBER > 8) +#error "CRT1_AREAS_NUMBER must be within 0 and 8" +#endif + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/** + * @brief Type of an area to be initialized. + */ +typedef struct { + uint32_t *init_text_area; + uint32_t *init_area; + uint32_t *clear_area; + uint32_t *no_init_area; +} ram_init_area_t; + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +#if (CRT1_AREAS_NUMBER > 0) || defined(__DOXYGEN__) +extern uint32_t __ram0_init_text__, __ram0_init__, __ram0_clear__, __ram0_noinit__; +#endif +#if (CRT1_AREAS_NUMBER > 1) || defined(__DOXYGEN__) +extern uint32_t __ram1_init_text__, __ram1_init__, __ram1_clear__, __ram1_noinit__; +#endif +#if (CRT1_AREAS_NUMBER > 2) || defined(__DOXYGEN__) +extern uint32_t __ram2_init_text__, __ram2_init__, __ram2_clear__, __ram2_noinit__; +#endif +#if (CRT1_AREAS_NUMBER > 3) || defined(__DOXYGEN__) +extern uint32_t __ram3_init_text__, __ram3_init__, __ram3_clear__, __ram3_noinit__; +#endif +#if (CRT1_AREAS_NUMBER > 4) || defined(__DOXYGEN__) +extern uint32_t __ram4_init_text__, __ram4_init__, __ram4_clear__, __ram4_noinit__; +#endif +#if (CRT1_AREAS_NUMBER > 5) || defined(__DOXYGEN__) +extern uint32_t __ram5_init_text__, __ram5_init__, __ram5_clear__, __ram5_noinit__; +#endif +#if (CRT1_AREAS_NUMBER > 6) || defined(__DOXYGEN__) +extern uint32_t __ram6_init_text__, __ram6_init__, __ram6_clear__, __ram6_noinit__; +#endif +#if (CRT1_AREAS_NUMBER > 7) || defined(__DOXYGEN__) +extern uint32_t __ram7_init_text__, __ram7_init__, __ram7_clear__, __ram7_noinit__; +#endif + +/** + * @brief Static table of areas to be initialized. + */ +#if (CRT1_AREAS_NUMBER > 0) || defined(__DOXYGEN__) +static const ram_init_area_t ram_areas[CRT1_AREAS_NUMBER] = { + {&__ram0_init_text__, &__ram0_init__, &__ram0_clear__, &__ram0_noinit__}, +#if (CRT1_AREAS_NUMBER > 1) || defined(__DOXYGEN__) + {&__ram1_init_text__, &__ram1_init__, &__ram1_clear__, &__ram1_noinit__}, +#endif +#if (CRT1_AREAS_NUMBER > 2) || defined(__DOXYGEN__) + {&__ram2_init_text__, &__ram2_init__, &__ram2_clear__, &__ram2_noinit__}, +#endif +#if (CRT1_AREAS_NUMBER > 3) || defined(__DOXYGEN__) + {&__ram3_init_text__, &__ram3_init__, &__ram3_clear__, &__ram3_noinit__}, +#endif +#if (CRT1_AREAS_NUMBER > 4) || defined(__DOXYGEN__) + {&__ram4_init_text__, &__ram4_init__, &__ram4_clear__, &__ram4_noinit__}, +#endif +#if (CRT1_AREAS_NUMBER > 5) || defined(__DOXYGEN__) + {&__ram5_init_text__, &__ram5_init__, &__ram5_clear__, &__ram5_noinit__}, +#endif +#if (CRT1_AREAS_NUMBER > 6) || defined(__DOXYGEN__) + {&__ram6_init_text__, &__ram6_init__, &__ram6_clear__, &__ram6_noinit__}, +#endif +#if (CRT1_AREAS_NUMBER > 7) || defined(__DOXYGEN__) + {&__ram7_init_text__, &__ram7_init__, &__ram7_clear__, &__ram7_noinit__}, +#endif +}; +#endif + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +/** + * @brief Architecture-dependent core initialization. + * @details This hook is invoked immediately after the stack initialization + * and before the DATA and BSS segments initialization. + * @note This function is a weak symbol. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ +void __core_init(void) {} + +/** + * @brief Early initialization. + * @details This hook is invoked immediately after the stack initialization + * and before the DATA and BSS segments initialization. The + * default behavior is to do nothing. + * @note This function is a weak symbol. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ +void __early_init(void) {} +/*lint -restore*/ + +/** + * @brief Late initialization. + * @details This hook is invoked after the DATA and BSS segments + * initialization and before any static constructor. The + * default behavior is to do nothing. + * @note This function is a weak symbol. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ +void __late_init(void) {} +/*lint -restore*/ + +/** + * @brief Default @p main() function exit handler. + * @details This handler is invoked or the @p main() function exit. The + * default behavior is to enter an infinite loop. + * @note This function is a weak symbol. + */ +#if !defined(__DOXYGEN__) +__attribute__((noreturn, weak)) +#endif +/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ +void __default_exit(void) { +/*lint -restore*/ + + while (true) { + } +} + +/** + * @brief Performs the initialization of the various RAM areas. + */ +void __init_ram_areas(void) { +#if CRT1_AREAS_NUMBER > 0 + const ram_init_area_t *rap = ram_areas; + + do { + uint32_t *tp = rap->init_text_area; + uint32_t *p = rap->init_area; + + /* Copying initialization data.*/ + while (p < rap->clear_area) { + *p = *tp; + p++; + tp++; + } + + /* Zeroing clear area.*/ + while (p < rap->no_init_area) { + *p = 0; + p++; + } + rap++; + } + while (rap < &ram_areas[CRT1_AREAS_NUMBER]); +#endif +} + +/** @} */ diff --git a/os/common/startup/RISCV-CLIC/compilers/GCC/ld/ES32VF2264.ld b/os/common/startup/RISCV-CLIC/compilers/GCC/ld/ES32VF2264.ld new file mode 100644 index 0000000000..d86e5d27fc --- /dev/null +++ b/os/common/startup/RISCV-CLIC/compilers/GCC/ld/ES32VF2264.ld @@ -0,0 +1,89 @@ +/* + ChibiOS - Copyright (C) 2020 Patrick Seidel + ChibiOS - Copyright (C) 2021 Stefan Kerkmann + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * ES32VF2264 memory setup. + */ + +OUTPUT_ARCH( "riscv" ) + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 256k + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 32k + ram1 (wx) : org = 0x00000000, len = 0 + ram2 (wx) : org = 0x00000000, len = 0 + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x00000000, len = 0 + ram5 (wx) : org = 0x00000000, len = 0 + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld \ No newline at end of file diff --git a/os/common/startup/RISCV-CLIC/compilers/GCC/ld/rules.ld b/os/common/startup/RISCV-CLIC/compilers/GCC/ld/rules.ld new file mode 100644 index 0000000000..048c5b39e7 --- /dev/null +++ b/os/common/startup/RISCV-CLIC/compilers/GCC/ld/rules.ld @@ -0,0 +1,11 @@ +/* Stack rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld + +/* Memory rules inclusion.*/ +INCLUDE rules_memory.ld diff --git a/os/common/startup/RISCV-CLIC/compilers/GCC/ld/rules_code.ld b/os/common/startup/RISCV-CLIC/compilers/GCC/ld/rules_code.ld new file mode 100644 index 0000000000..36969fb3ae --- /dev/null +++ b/os/common/startup/RISCV-CLIC/compilers/GCC/ld/rules_code.ld @@ -0,0 +1,71 @@ +/* + ChibiOS - Copyright (C) 2020 Patrick Seidel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +ENTRY(_start) + +SECTIONS +{ + .vectors : ALIGN(4) + { + KEEP (*(SORT_NONE(.crt0))) + /* For 65 to 128 interrupts, the vector table must be 512 byte aligned. + * See: https://doc.nucleisys.com/nuclei_spec/isa/core_csr.html#mtvt */ + . = ALIGN(512); + KEEP (*(SORT_NONE(.vectors))) + } > VECTORS_FLASH AT > VECTORS_FLASH_LMA + + .xtors : ALIGN(4) + { + __init_array_base__ = .; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end__ = .; + __fini_array_base__ = .; + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + __fini_array_end__ = .; + } > XTORS_FLASH AT > XTORS_FLASH_LMA + + .text : ALIGN_WITH_INPUT + { + __text_base__ = .; + *(.text) + *(.text.*) + *(.gcc*) + __text_end__ = .; + } > TEXT_FLASH AT > TEXT_FLASH_LMA + + .rodata : ALIGN(4) + { + __rodata_base__ = .; + *(.rodata) + *(.rodata.*) + *(.srodata) + *(.srodata.*) + . = ALIGN(4); + __rodata_end__ = .; + } > RODATA_FLASH AT > RODATA_FLASH_LMA + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA +} diff --git a/os/common/startup/RISCV-CLIC/compilers/GCC/ld/rules_data.ld b/os/common/startup/RISCV-CLIC/compilers/GCC/ld/rules_data.ld new file mode 100644 index 0000000000..a8f4b382f5 --- /dev/null +++ b/os/common/startup/RISCV-CLIC/compilers/GCC/ld/rules_data.ld @@ -0,0 +1,49 @@ +/* + ChibiOS - Copyright (C) 2020 Patrick Seidel + ChibiOS - Copyright (C) 2021 Stefan Kerkmann + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +SECTIONS +{ + .data : ALIGN(4) + { + PROVIDE(_textdata = LOADADDR(.data)); + PROVIDE(_data = .); + __textdata_base__ = LOADADDR(.data); + __data_base__ = .; + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.* .sdata*) + *(.ramtext) + *(.gnu.linkonce.s.*) + PROVIDE(_edata = .); + __data_end__ = .; + } > DATA_RAM AT > DATA_RAM_LMA + + .bss (NOLOAD) : ALIGN(4) + { + __bss_base__ = .; + *(.sbss) + *(.sbss.*) + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + PROVIDE(end = .); + } > BSS_RAM +} diff --git a/os/common/startup/RISCV-CLIC/compilers/GCC/ld/rules_memory.ld b/os/common/startup/RISCV-CLIC/compilers/GCC/ld/rules_memory.ld new file mode 100644 index 0000000000..078ec3a1cd --- /dev/null +++ b/os/common/startup/RISCV-CLIC/compilers/GCC/ld/rules_memory.ld @@ -0,0 +1,317 @@ +/* + ChibiOS - Copyright (C) 2020 Patrick Seidel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +__ram0_base__ = ORIGIN(ram0); +__ram0_size__ = LENGTH(ram0); +__ram0_end__ = __ram0_base__ + __ram0_size__; +__ram1_base__ = ORIGIN(ram1); +__ram1_size__ = LENGTH(ram1); +__ram1_end__ = __ram1_base__ + __ram1_size__; +__ram2_base__ = ORIGIN(ram2); +__ram2_size__ = LENGTH(ram2); +__ram2_end__ = __ram2_base__ + __ram2_size__; +__ram3_base__ = ORIGIN(ram3); +__ram3_size__ = LENGTH(ram3); +__ram3_end__ = __ram3_base__ + __ram3_size__; +__ram4_base__ = ORIGIN(ram4); +__ram4_size__ = LENGTH(ram4); +__ram4_end__ = __ram4_base__ + __ram4_size__; +__ram5_base__ = ORIGIN(ram5); +__ram5_size__ = LENGTH(ram5); +__ram5_end__ = __ram5_base__ + __ram5_size__; +__ram6_base__ = ORIGIN(ram6); +__ram6_size__ = LENGTH(ram6); +__ram6_end__ = __ram6_base__ + __ram6_size__; +__ram7_base__ = ORIGIN(ram7); +__ram7_size__ = LENGTH(ram7); +__ram7_end__ = __ram7_base__ + __ram7_size__; + +__flash0_base__ = ORIGIN(flash0); +__flash0_size__ = LENGTH(flash0); +__flash0_end__ = __flash0_base__ + __flash0_size__; +__flash1_base__ = ORIGIN(flash1); +__flash1_size__ = LENGTH(flash1); +__flash1_end__ = __flash1_base__ + __flash1_size__; +__flash2_base__ = ORIGIN(flash2); +__flash2_size__ = LENGTH(flash2); +__flash2_end__ = __flash2_base__ + __flash2_size__; +__flash3_base__ = ORIGIN(flash3); +__flash3_size__ = LENGTH(flash3); +__flash3_end__ = __flash3_base__ + __flash3_size__; +__flash4_base__ = ORIGIN(flash4); +__flash4_size__ = LENGTH(flash4); +__flash4_end__ = __flash4_base__ + __flash4_size__; +__flash5_base__ = ORIGIN(flash5); +__flash5_size__ = LENGTH(flash5); +__flash5_end__ = __flash5_base__ + __flash5_size__; +__flash6_base__ = ORIGIN(flash6); +__flash6_size__ = LENGTH(flash6); +__flash6_end__ = __flash6_base__ + __flash6_size__; +__flash7_base__ = ORIGIN(flash7); +__flash7_size__ = LENGTH(flash7); +__flash7_end__ = __flash7_base__ + __flash7_size__; + +SECTIONS +{ + .ram0_init : ALIGN(4) + { + __ram0_init_text__ = LOADADDR(.ram0_init); + __ram0_init__ = .; + KEEP(*(.ram0_init)) + KEEP(*(.ram0_init.*)) + . = ALIGN(4); + } > ram0 AT > RAM_INIT_FLASH_LMA + + .ram0 (NOLOAD) : ALIGN(4) + { + __ram0_clear__ = .; + *(.ram0_clear) + *(.ram0_clear.*) + . = ALIGN(4); + __ram0_noinit__ = .; + *(.ram0) + *(.ram0.*) + . = ALIGN(4); + __ram0_free__ = .; + } > ram0 + + .ram1_init : ALIGN(4) + { + __ram1_init_text__ = LOADADDR(.ram1_init); + __ram1_init__ = .; + KEEP(*(.ram1_init)) + KEEP(*(.ram1_init.*)) + . = ALIGN(4); + } > ram1 AT > RAM_INIT_FLASH_LMA + + .ram1 (NOLOAD) : ALIGN(4) + { + __ram1_clear__ = .; + *(.ram1_clear) + *(.ram1_clear.*) + . = ALIGN(4); + __ram1_noinit__ = .; + *(.ram1) + *(.ram1.*) + . = ALIGN(4); + __ram1_free__ = .; + } > ram1 + + .ram2_init : ALIGN(4) + { + __ram2_init_text__ = LOADADDR(.ram2_init); + __ram2_init__ = .; + KEEP(*(.ram2_init)) + KEEP(*(.ram2_init.*)) + . = ALIGN(4); + } > ram2 AT > RAM_INIT_FLASH_LMA + + .ram2 (NOLOAD) : ALIGN(4) + { + __ram2_clear__ = .; + *(.ram2_clear) + *(.ram2_clear.*) + . = ALIGN(4); + __ram2_noinit__ = .; + *(.ram2) + *(.ram2.*) + . = ALIGN(4); + __ram2_free__ = .; + } > ram2 + + .ram3_init : ALIGN(4) + { + __ram3_init_text__ = LOADADDR(.ram3_init); + __ram3_init__ = .; + KEEP(*(.ram3_init)) + KEEP(*(.ram3_init.*)) + . = ALIGN(4); + } > ram3 AT > RAM_INIT_FLASH_LMA + + .ram3 (NOLOAD) : ALIGN(4) + { + __ram3_clear__ = .; + *(.ram3_clear) + *(.ram3_clear.*) + . = ALIGN(4); + __ram3_noinit__ = .; + *(.ram3) + *(.ram3.*) + . = ALIGN(4); + __ram3_free__ = .; + } > ram3 + + .ram4_init : ALIGN(4) + { + __ram4_init_text__ = LOADADDR(.ram4_init); + __ram4_init__ = .; + KEEP(*(.ram4_init)) + KEEP(*(.ram4_init.*)) + . = ALIGN(4); + } > ram4 AT > RAM_INIT_FLASH_LMA + + .ram4 (NOLOAD) : ALIGN(4) + { + __ram4_clear__ = .; + *(.ram4_clear) + *(.ram4_clear.*) + . = ALIGN(4); + __ram4_noinit__ = .; + *(.ram4) + *(.ram4.*) + . = ALIGN(4); + __ram4_free__ = .; + } > ram4 + + .ram5_init : ALIGN(4) + { + __ram5_init_text__ = LOADADDR(.ram5_init); + __ram5_init__ = .; + KEEP(*(.ram5_init)) + KEEP(*(.ram5_init.*)) + . = ALIGN(4); + } > ram5 AT > RAM_INIT_FLASH_LMA + + .ram5 (NOLOAD) : ALIGN(4) + { + __ram5_clear__ = .; + *(.ram5_clear) + *(.ram5_clear.*) + . = ALIGN(4); + __ram5_noinit__ = .; + *(.ram5) + *(.ram5.*) + . = ALIGN(4); + __ram5_free__ = .; + } > ram5 + + .ram6_init : ALIGN(4) + { + __ram6_init_text__ = LOADADDR(.ram6_init); + __ram6_init__ = .; + KEEP(*(.ram6_init)) + KEEP(*(.ram6_init.*)) + . = ALIGN(4); + } > ram6 AT > RAM_INIT_FLASH_LMA + + .ram6 (NOLOAD) : ALIGN(4) + { + __ram6_clear__ = .; + *(.ram6_clear) + *(.ram6_clear.*) + . = ALIGN(4); + __ram6_noinit__ = .; + *(.ram6) + *(.ram6.*) + . = ALIGN(4); + __ram6_free__ = .; + } > ram6 + + .ram7_init : ALIGN(4) + { + __ram7_init_text__ = LOADADDR(.ram7_init); + __ram7_init__ = .; + KEEP(*(.ram7_init)) + KEEP(*(.ram7_init.*)) + . = ALIGN(4); + } > ram7 AT > RAM_INIT_FLASH_LMA + + .ram7 (NOLOAD) : ALIGN(4) + { + __ram7_clear__ = .; + *(.ram7_clear) + *(.ram7_clear.*) + . = ALIGN(4); + __ram7_noinit__ = .; + *(.ram7) + *(.ram7.*) + . = ALIGN(4); + __ram7_free__ = .; + } > ram7 + + .flash0 : ALIGN(4) + { + __flash0_init__ = .; + KEEP(*(.flash0_init)) + KEEP(*(.flash0_init.*)) + __flash0_free__ = .; + } > flash0 + + .flash1 : ALIGN(4) + { + __flash1_init__ = .; + KEEP(*(.flash1_init)) + KEEP(*(.flash1_init.*)) + __flash1_free__ = .; + } > flash1 + + .flash2 : ALIGN(4) + { + __flash2_init__ = .; + KEEP(*(.flash2_init)) + KEEP(*(.flash2_init.*)) + __flash2_free__ = .; + } > flash2 + + .flash3 : ALIGN(4) + { + __flash3_init__ = .; + KEEP(*(.flash3_init)) + KEEP(*(.flash3_init.*)) + __flash3_free__ = .; + } > flash3 + + .flash4 : ALIGN(4) + { + __flash4_init__ = .; + KEEP(*(.flash4_init)) + KEEP(*(.flash4_init.*)) + __flash4_free__ = .; + } > flash4 + + .flash5 : ALIGN(4) + { + __flash5_init__ = .; + KEEP(*(.flash5_init)) + KEEP(*(.flash5_init.*)) + __flash5_free__ = .; + } > flash5 + + .flash6 : ALIGN(4) + { + __flash6_init__ = .; + KEEP(*(.flash6_init)) + KEEP(*(.flash6_init.*)) + __flash6_free__ = .; + } > flash6 + + .flash7 : ALIGN(4) + { + __flash7_init__ = .; + KEEP(*(.flash7_init)) + KEEP(*(.flash7_init.*)) + __flash7_free__ = .; + } > flash7 + + /* The default heap uses the (statically) unused part of a RAM section.*/ + .heap (NOLOAD) : + { + . = ALIGN(8); + __heap_base__ = .; + . = ORIGIN(HEAP_RAM) + LENGTH(HEAP_RAM); + __heap_end__ = .; + } > HEAP_RAM +} diff --git a/os/common/startup/RISCV-CLIC/compilers/GCC/ld/rules_stacks.ld b/os/common/startup/RISCV-CLIC/compilers/GCC/ld/rules_stacks.ld new file mode 100644 index 0000000000..b50062972a --- /dev/null +++ b/os/common/startup/RISCV-CLIC/compilers/GCC/ld/rules_stacks.ld @@ -0,0 +1,30 @@ +/* + ChibiOS - Copyright (C) 2020 Patrick Seidel + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +SECTIONS +{ + /* Special section for process stack.*/ + .pstack (NOLOAD) : + { + . = ALIGN(16); + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(16); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > PROCESS_STACK_RAM +} diff --git a/os/common/startup/RISCV-CLIC/compilers/GCC/mk/riscv64-unknown-elf.mk b/os/common/startup/RISCV-CLIC/compilers/GCC/mk/riscv64-unknown-elf.mk new file mode 100644 index 0000000000..0af62524a3 --- /dev/null +++ b/os/common/startup/RISCV-CLIC/compilers/GCC/mk/riscv64-unknown-elf.mk @@ -0,0 +1,23 @@ +############################################################################## +# Compiler settings +# + +TRGT = riscv64-unknown-elf- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# +# Compiler settings +############################################################################## diff --git a/os/common/startup/RISCV-CLIC/compilers/GCC/mk/rules.mk b/os/common/startup/RISCV-CLIC/compilers/GCC/mk/rules.mk new file mode 100644 index 0000000000..7b6967c270 --- /dev/null +++ b/os/common/startup/RISCV-CLIC/compilers/GCC/mk/rules.mk @@ -0,0 +1,266 @@ +# RISC-V common makefile scripts and rules. + +############################################################################## +# Processing options coming from the upper Makefile. +# + +# Compiler options +OPT := $(USE_OPT) +COPT := $(USE_COPT) +CPPOPT := $(USE_CPPOPT) + +# Garbage collection +ifeq ($(USE_LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections -fno-common + LDOPT := ,--gc-sections +else + LDOPT := +endif + +# Linker extra options +ifneq ($(USE_LDOPT),) + LDOPT := $(LDOPT),$(USE_LDOPT) +endif + +# Link time optimizations +ifeq ($(USE_LTO),yes) + OPT += -flto +endif + +# Process stack size +ifeq ($(USE_PROCESS_STACKSIZE),) + LDOPT := $(LDOPT),--defsym=__process_stack_size__=0x400 +else + LDOPT := $(LDOPT),--defsym=__process_stack_size__=$(USE_PROCESS_STACKSIZE) +endif + +# Output directory and files +ifeq ($(BUILDDIR),) + BUILDDIR = build +endif +ifeq ($(BUILDDIR),.) + BUILDDIR = build +endif + +# Dependencies directory +ifeq ($(DEPDIR),) + DEPDIR = .dep +endif +ifeq ($(DEPDIR),.) + DEPDIR = .dep +endif + +OUTFILES := $(BUILDDIR)/$(PROJECT).elf \ + $(BUILDDIR)/$(PROJECT).hex \ + $(BUILDDIR)/$(PROJECT).bin \ + $(BUILDDIR)/$(PROJECT).dmp \ + $(BUILDDIR)/$(PROJECT).list + +ifdef SREC + OUTFILES += $(BUILDDIR)/$(PROJECT).srec +endif + +# Source files groups and paths +TCSRC += $(CSRC) +TCPPSRC += $(CPPSRC) +TSRC := $(TCSRC) $(TCPPSRC) +SRCPATHS := $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(TSRC))) + +# Various directories +OBJDIR := $(BUILDDIR)/obj +LSTDIR := $(BUILDDIR)/lst + +# Object files groups +TCOBJS := $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o))) +#TCPPOBJS := $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o))) +TCPPOBJS := $(addprefix $(OBJDIR)/, $(notdir $(patsubst %.cpp, %.o, $(filter %.cpp, $(TCPPSRC))))) +TCCOBJS := $(addprefix $(OBJDIR)/, $(notdir $(patsubst %.cc, %.o, $(filter %.cc, $(TCPPSRC))))) +ASMOBJS := $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o))) +ASMXOBJS := $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o))) +#OBJS := $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) +OBJS := $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) $(TCCOBJS) + +# Paths +IINCDIR := $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) +LLIBDIR := $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) + +# Macros +DEFS := $(DDEFS) $(UDEFS) +ADEFS := $(DADEFS) $(UADEFS) + +# Libs +LIBS := $(DLIBS) $(ULIBS) + +# Various settings +MCFLAGS := -march=$(MCU_ARCH) -mabi=$(MCU_ABI) -mcmodel=$(MCU_CMODEL) +ODFLAGS = -x --syms +ASFLAGS = $(MCFLAGS) $(OPT) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) +ASXFLAGS = $(MCFLAGS) $(OPT) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS) +CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) +CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) +LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(STARTUPLD),--script=$(LDSCRIPT)$(LDOPT) + +# Generate dependency information +ASFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d +ASXFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d +CFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d +CPPFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d + +# Paths where to search for sources +VPATH = $(SRCPATHS) + +# +# Makefile rules +# + +all: PRE_MAKE_ALL_RULE_HOOK $(OBJS) $(OUTFILES) POST_MAKE_ALL_RULE_HOOK + +PRE_MAKE_ALL_RULE_HOOK: + +POST_MAKE_ALL_RULE_HOOK: + +$(OBJS): | PRE_MAKE_ALL_RULE_HOOK $(BUILDDIR) $(OBJDIR) $(LSTDIR) $(DEPDIR) + +$(BUILDDIR): +ifneq ($(USE_VERBOSE_COMPILE),yes) + @echo Compiler Options + @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o + @echo +endif + @mkdir -p $(BUILDDIR) + +$(OBJDIR): + @mkdir -p $(OBJDIR) + +$(LSTDIR): + @mkdir -p $(LSTDIR) + +$(DEPDIR): + @mkdir -p $(DEPDIR) + +$(TCPPOBJS) : $(OBJDIR)/%.o : %.cpp $(MAKEFILE_LIST) +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $( $@ + $(SZ) $< +else + @echo Creating $@ + @$(OD) $(ODFLAGS) $< > $@ + @echo + @$(SZ) $< +endif + +%.list: %.elf +ifeq ($(USE_VERBOSE_COMPILE),yes) + $(OD) -S $< > $@ +else + @echo Creating $@ + @$(OD) -S $< > $@ + @echo + @echo Done +endif + +lib: $(OBJS) $(BUILDDIR)/lib$(PROJECT).a + +$(BUILDDIR)/lib$(PROJECT).a: $(OBJS) + @$(AR) -r $@ $^ + @echo + @echo Done + +clean: CLEAN_RULE_HOOK + @echo Cleaning + @echo - $(DEPDIR) + @-rm -fR $(DEPDIR)/* $(BUILDDIR)/* 2>/dev/null + @-if [ -d "$(DEPDIR)" ]; then rmdir -p --ignore-fail-on-non-empty $(subst ./,,$(DEPDIR)) 2>/dev/null; fi + @echo - $(BUILDDIR) + @-if [ -d "$(BUILDDIR)" ]; then rmdir -p --ignore-fail-on-non-empty $(subst ./,,$(BUILDDIR)) 2>/dev/null; fi + @echo + @echo Done + +CLEAN_RULE_HOOK: + +# +# Include the dependency files, should be the last of the makefile +# +-include $(wildcard $(DEPDIR)/*) + +# *** EOF *** diff --git a/os/common/startup/RISCV-CLIC/compilers/GCC/mk/startup_es32vf2264.mk b/os/common/startup/RISCV-CLIC/compilers/GCC/mk/startup_es32vf2264.mk new file mode 100644 index 0000000000..36341b8af2 --- /dev/null +++ b/os/common/startup/RISCV-CLIC/compilers/GCC/mk/startup_es32vf2264.mk @@ -0,0 +1,40 @@ +# List of the ChibiOS generic FE310 startup files. +STARTUPSRC = $(CHIBIOS_CONTRIB)/os/common/startup/RISCV-CLIC/compilers/GCC/crt1.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_utils.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_crc.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_rmu.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_cmu.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_gpio.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_uart.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_spi.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_adc.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_i2c.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_pmu.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_timer.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_pis.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_iwdt.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_i2s.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_wwdt.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264/md/md_dma.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264/ald/ald_usb.c + +STARTUPASM = $(CHIBIOS_CONTRIB)/os/common/startup/RISCV-CLIC/compilers/GCC/crt0.S \ + $(CHIBIOS_CONTRIB)/os/common/startup/RISCV-CLIC/compilers/GCC/vectors.S + +STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \ + $(CHIBIOS_CONTRIB)/os/common/startup/RISCV-CLIC/compilers/GCC \ + $(CHIBIOS_CONTRIB)/os/common/startup/RISCV-CLIC/devices/ES32VF2264 \ + $(CHIBIOS_CONTRIB)/os/common/ext/NMSIS/Core/Include \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264 \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264/md \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264/ald \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/ES32VF2264/ES32VF2264 + +STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/RISCV-CLIC/compilers/GCC/ld +STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/RISCV-CLIC/compilers/GCC/ld + +# Shared variables +ALLXASMSRC += $(STARTUPASM) +ALLCSRC += $(STARTUPSRC) +ALLINC += $(STARTUPINC) + diff --git a/os/common/startup/RISCV-CLIC/compilers/GCC/vectors.S b/os/common/startup/RISCV-CLIC/compilers/GCC/vectors.S new file mode 100644 index 0000000000..1300662c7f --- /dev/null +++ b/os/common/startup/RISCV-CLIC/compilers/GCC/vectors.S @@ -0,0 +1,226 @@ +/* + ChibiOS - Copyright (C) 2021 Stefan Kerkmann + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file vectors.S + * @brief Interrupt vectors for RISC-V ECLIC devices. + * + * @defgroup RISCV_ECLIC_STARTUP + * @{ + */ + +#define _FROM_ASM_ + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Code section. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +.section .vectors, "a", %progbits +.globl vector_base +.type vector_base, %object +.option push +.option norelax +vector_base: + .word vector0 + .word vector1 + .word vector2 + .word vector3 + .word vector4 + .word vector5 + .word vector6 + .word vector7 + .word vector8 + .word vector9 + .word vector10 + .word vector11 + .word vector12 + .word vector13 + .word vector14 + .word vector15 + .word vector16 + .word vector17 + .word vector18 + .word vector19 + .word vector20 + .word vector21 + .word vector22 + .word vector23 + .word vector24 + .word vector25 + .word vector26 + .word vector27 + .word vector28 + .word vector29 + .word vector30 + .word vector31 + .word vector32 + .word vector33 + .word vector34 + .word vector35 + .word vector36 + .word vector37 + .word vector38 + .word vector39 + .word vector40 + .word vector41 + .word vector42 + .word vector43 + .word vector44 + .word vector45 + .word vector46 + .word vector47 + .word vector48 + .word vector49 + .word vector50 + .word vector51 + .word vector52 + .word vector53 + .word vector54 + .word vector55 + .word vector56 + .word vector57 + .word vector58 + .word vector59 + .word vector60 + .word vector61 + .word vector62 + .word vector63 + .word vector64 + .word vector65 + .word vector66 + .word vector67 + .word vector68 + .word vector69 + .word vector70 + .word vector71 + .word vector72 + .word vector73 + .word vector74 + .word vector75 + .word vector76 + .word vector77 + .word vector78 + .word vector79 + .word vector80 + .word vector81 + .word vector82 + .word vector83 + .word vector84 + .word vector85 + .word vector86 + .size vector_base, . - vector_base + .option pop + + .weak vector0 + .weak vector1 + .weak vector2 + .weak vector3 + .weak vector4 + .weak vector5 + .weak vector6 + .weak vector7 + .weak vector8 + .weak vector9 + .weak vector10 + .weak vector11 + .weak vector12 + .weak vector13 + .weak vector14 + .weak vector15 + .weak vector16 + .weak vector17 + .weak vector18 + .weak vector19 + .weak vector20 + .weak vector21 + .weak vector22 + .weak vector23 + .weak vector24 + .weak vector25 + .weak vector26 + .weak vector27 + .weak vector28 + .weak vector29 + .weak vector30 + .weak vector31 + .weak vector32 + .weak vector33 + .weak vector34 + .weak vector35 + .weak vector36 + .weak vector37 + .weak vector38 + .weak vector39 + .weak vector40 + .weak vector41 + .weak vector42 + .weak vector43 + .weak vector44 + .weak vector45 + .weak vector46 + .weak vector47 + .weak vector48 + .weak vector49 + .weak vector50 + .weak vector51 + .weak vector52 + .weak vector53 + .weak vector54 + .weak vector55 + .weak vector56 + .weak vector57 + .weak vector58 + .weak vector59 + .weak vector60 + .weak vector61 + .weak vector62 + .weak vector63 + .weak vector64 + .weak vector65 + .weak vector66 + .weak vector67 + .weak vector68 + .weak vector69 + .weak vector70 + .weak vector71 + .weak vector72 + .weak vector73 + .weak vector74 + .weak vector75 + .weak vector76 + .weak vector77 + .weak vector78 + .weak vector79 + .weak vector80 + .weak vector81 + .weak vector82 + .weak vector83 + .weak vector84 + .weak vector85 + .weak vector86 + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/common/startup/RISCV-CLIC/devices/ES32VF2264/eclic_parameters.h b/os/common/startup/RISCV-CLIC/devices/ES32VF2264/eclic_parameters.h new file mode 100644 index 0000000000..090aed9550 --- /dev/null +++ b/os/common/startup/RISCV-CLIC/devices/ES32VF2264/eclic_parameters.h @@ -0,0 +1,34 @@ +/* + ChibiOS - Copyright (C) 2021 Stefan Kerkmann + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file devices/ES32VF2264/eclic_parameters.h + * @brief ES32VF2264 ECLIC configuration. + * + * @addtogroup ES32VF2264 + * @{ + */ +/**@} */ +#ifndef _ECLIC_PARAMETERS_H_ +#define _ECLIC_PARAMETERS_H_ + +/* Not defined because FPU isn't present. GCC produces alot +of warnings if -Wundef is present, therefore this define. */ +#define __riscv_flen 0 + +#include "es32vf2264.h" + +#endif /* _ECLIC_PARAMETERS_H_ */ \ No newline at end of file diff --git a/os/hal/boards/ES32VF2264/board.c b/os/hal/boards/ES32VF2264/board.c new file mode 100644 index 0000000000..162df14f36 --- /dev/null +++ b/os/hal/boards/ES32VF2264/board.c @@ -0,0 +1,54 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "board.h" + +static int flag __attribute__((section(".flag"))) __attribute__((__used__)) = 0xAAAA5555; +extern void enter_bootloader_mode_if_requested(void); + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +#ifdef ES_INCLUDE_INFO_CONFIG_FILE +void __chibios_override___early_init(void) +#else +void __early_init(void) +#endif +{ + +} + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ + +#ifdef ES_INCLUDE_INFO_CONFIG_FILE +void __chibios_override_boardInit(void) +#else +void boardInit(void) +#endif +{ + +} diff --git a/os/hal/boards/ES32VF2264/board.h b/os/hal/boards/ES32VF2264/board.h new file mode 100644 index 0000000000..94614c7f56 --- /dev/null +++ b/os/hal/boards/ES32VF2264/board.h @@ -0,0 +1,42 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + +#include "es32vf2264.h" +#include "md_conf.h" +#include "ald_usb.h" + +#define ES32_HAS_GPIOA 1 +#define ES32_HAS_GPIOB 1 +#define ES32_HAS_GPIOC 1 +#define ES32_HAS_GPIOD 1 + + + void boardInit(void); + +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/ES32VF2264/board.mk b/os/hal/boards/ES32VF2264/board.mk new file mode 100644 index 0000000000..d71f040849 --- /dev/null +++ b/os/hal/boards/ES32VF2264/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/ES32VF2264/board.c + +# Required include directories +BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/ES32VF2264 + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) \ No newline at end of file diff --git a/os/hal/ports/ES32/ES32VF2264/es32_registry.h b/os/hal/ports/ES32/ES32VF2264/es32_registry.h new file mode 100644 index 0000000000..a7e0ba31dd --- /dev/null +++ b/os/hal/ports/ES32/ES32VF2264/es32_registry.h @@ -0,0 +1,120 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file ES32_registry.h + * @brief capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef ES32_REGISTRY_H +#define ES32_REGISTRY_H + +/** + * @brief Sub-family identifier. + */ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @brief Maximum system and core clock (f_SYS) frequency. + */ +#define ES32_SYSCLK_MAX 72000000L + +/** + * @brief Maximum bus clock (f_BUS) frequency. + */ +#define ES32_BUSCLK_MAX 72000000L + +/** + * @brief Maximum flash clock (f_FLASH) frequency. + */ +#define ES32_FLASHCLK_MAX 72000000L + +/** + * @name attributes + * @{ + */ + +/* GPIO attributes.*/ +#define ES32_NUM_GPIO 5 + +#define ES32_GPIO_INDEX_BITS 13 +#define ES32_CCR_PAEN CKCU_AHBCCR_PAEN + +/* EXTI attributes */ +#define ES32_HAS_EXTI TRUE +#define ES32_NUM_EXTI 16 +#define ES32_EVWUP_IRQ_VECTOR Vector58 +#define ES32_EXTI0_IRQ_VECTOR Vector60 +#define ES32_EXTI1_IRQ_VECTOR Vector64 +#define ES32_EXTI2_IRQ_VECTOR Vector68 +#define ES32_EXTI3_IRQ_VECTOR Vector6C +#define ES32_EXTI4_IRQ_VECTOR Vector70 +#define ES32_EXTI5_IRQ_VECTOR Vector74 +#define ES32_EXTI6_IRQ_VECTOR Vector78 +#define ES32_EXTI7_IRQ_VECTOR Vector7C +#define ES32_EXTI8_IRQ_VECTOR Vector80 +#define ES32_EXTI9_IRQ_VECTOR Vector84 +#define ES32_EXTI10_IRQ_VECTOR Vector88 +#define ES32_EXTI11_IRQ_VECTOR Vector8C +#define ES32_EXTI12_IRQ_VECTOR Vector90 +#define ES32_EXTI13_IRQ_VECTOR Vector94 +#define ES32_EXTI14_IRQ_VECTOR Vector98 +#define ES32_EXTI15_IRQ_VECTOR Vector9C + +/* I2C attributes.*/ +#define ES32_HAS_I2C0 TRUE +#define ES32_I2C0_IRQ_VECTOR VectorEC +#define ES32_HAS_I2C1 TRUE +#define ES32_I2C1_IRQ_VECTOR VectorF0 + +/* SPI attributes.*/ +#define ES32_HAS_SPI0 TRUE +#define ES32_SPI0_IRQ_VECTOR VectorF4 +#define ES32_HAS_SPI1 TRUE +#define ES32_SPI1_IRQ_VECTOR VectorF8 + +/* UART attributes.*/ +#define ES32_HAS_USART0 TRUE +#define ES32_USART0_IRQ_VECTOR VectorFC +#define ES32_HAS_USART1 TRUE +#define ES32_USART1_IRQ_VECTOR Vector100 +#define ES32_HAS_UART0 TRUE +#define ES32_UART0_IRQ_VECTOR Vector104 +#define ES32_HAS_UART1 TRUE +#define ES32_UART1_IRQ_VECTOR Vector108 + +/* USB attributes.*/ +#define ES32_HAS_USB TRUE +#define ES32_USB_IRQ_VECTOR Vector114 +#define ES32_USB0_IS_USBOTG FALSE +#define ES32_HAS_USB_CLOCK_RECOVERY FALSE + +/* BFTM attributes. */ +#define ES32_BFTM0_IRQ_VECTOR VectorE4 +#define ES32_BFTM1_IRQ_VECTOR VectorE8 + +/** @} */ + +#endif /* ES32_REGISTRY_H */ + +/** @} */ diff --git a/os/hal/ports/ES32/ES32VF2264/hal_lld.c b/os/hal/ports/ES32/ES32VF2264/hal_lld.c new file mode 100644 index 0000000000..8cb3bb2a3c --- /dev/null +++ b/os/hal/ports/ES32/ES32VF2264/hal_lld.c @@ -0,0 +1,96 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_lld.c + * @brief PLATFORM HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief update the value of SystemCoreClock after changing the system clock. + */ +unsigned int SystemCoreClock; +unsigned int SystemFrequency_SysClk; +unsigned int SystemFrequency_AHBClk; +unsigned int SystemFrequency_APBClk; +unsigned int HRC48Frequency; +unsigned int PLL0Frequency; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ +#if ES32_NO_INIT +__attribute__((weak)) void hal_lld_init(void) +{ + +} +#else + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) +{ + csi_vic_set_prio(MACHINE_MODE_SOFT_IRQn, 0); + csi_vic_enable_sirq(MACHINE_MODE_SOFT_IRQn); + CLIC->CLICINT[MACHINE_MODE_SOFT_IRQn].ATTR |= (3); + + md_cmu_pll_config(MD_CMU_PLL_INPUT_HRC4M, MD_CMU_PLL_OUTPUT_72M); + md_cmu_clock_config(MD_CMU_CLOCK_PLL, 72000000); + + MD_SYSCFG_UNLOCK(); + md_cmu_enable_perh_all(); + md_cmu_enable_usbck48();/*USB 48M使能*/ + md_csu_enable_auto(); + md_csu_enable_cnt(); + MD_SYSCFG_LOCK(); + + md_rmu_reset_periperal(MD_RMU_PERH_USB); + md_init_1ms_tick(); + __enable_irq(); +} +#endif + +/** @} */ diff --git a/os/hal/ports/ES32/ES32VF2264/hal_lld.h b/os/hal/ports/ES32/ES32VF2264/hal_lld.h new file mode 100644 index 0000000000..81e5300ab8 --- /dev/null +++ b/os/hal/ports/ES32/ES32VF2264/hal_lld.h @@ -0,0 +1,126 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_lld.h + * @brief ES32 HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "es32_registry.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Platform identification macros + * @{ + */ +#define PLATFORM_NAME "ES32" +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ +/** + * @brief Disables the PWR/RCC initialization in the HAL. + */ +#if !defined(ES32_NO_INIT) || defined(__DOXYGEN__) +#define ES32_NO_INIT FALSE +#endif + +/** + * @brief system_clk select. + */ +#if !defined(ES32_SYSCLK_SOURSE_SELECT) || defined(__DOXYGEN__) +#define ES32_SYSCLK_SOURSE_SELECT MD_RCU_SW_SYSCLK_HRC48 +#endif + +/** + * @brief external clk config. + */ +#if !defined(ES32_HOSC_CLK_EN) || defined(__DOXYGEN__) +#define ES32_HOSC_CLK_EN FALSE +#endif + +/** + * @brief pll clk config. + */ +#if !defined(ES32_PLL_CLK_EN) || defined(__DOXYGEN__) +#define ES32_PLL_CLK_EN FALSE +#endif + +#if !defined(ES32_PLL_SOURSE_SELECT) || defined(__DOXYGEN__) +#define ES32_PLL_SOURSE_SELECT MD_RCU_PLLSRC_HRC48 +#endif + +#if !defined(ES32_PLL_CLK_FREQ) || defined(__DOXYGEN__) +#define ES32_PLL_CLK_FREQ MD_RCU_PLLCLK_72M +#endif + +/** + * @brief bus clk config. + */ +#if !defined(ES32_BUS_DIV_HPRE) || defined(__DOXYGEN__) +#define ES32_BUS_DIV_HPRE MD_RCU_HPRE_SYSCLK_DIV_1 +#endif + +#if !defined(ES32_BUS_DIV_PPRE) || defined(__DOXYGEN__) +#define ES32_BUS_DIV_PPRE MD_RCU_PPRE_HCLK_DIV_1 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +void hal_lld_init(void); +void es32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/ES32/ES32VF2264/platform.mk b/os/hal/ports/ES32/ES32VF2264/platform.mk new file mode 100644 index 0000000000..7e3b97b490 --- /dev/null +++ b/os/hal/ports/ES32/ES32VF2264/platform.mk @@ -0,0 +1,38 @@ +# List of all the platform files. +PLATFORMSRC = ${CHIBIOS_CONTRIB}/os/hal/ports/common/RISCV-CLIC/eclic.c \ + $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/ES32VF2264/hal_lld.c + + +# Required include directories +PLATFORMINC = ${CHIBIOS_CONTRIB}/os/hal/ports/common/RISCV-CLIC \ + $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/ES32VF2264 + +# Optional platform files. +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(HALCONFDIR),) + ifeq ($(CONFDIR),) + HALCONFDIR = . + else + HALCONFDIR := $(CONFDIR) + endif +endif + +HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define")) +endif #ifeq ($(USE_SMART_BUILD), yes) + +# Drivers compatible with the platform. +include $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/ADCv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/I2Cv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/TIMv2/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/SPIv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/GPIOv2/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/USBv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/UARTv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/WDTv1/driver.mk + + +# Shared variables +ALLCSRC += $(PLATFORMSRC) +ALLINC += $(PLATFORMINC) diff --git a/os/hal/ports/ES32/LLD/ADCv1/hal_adc_lld.c b/os/hal/ports/ES32/LLD/ADCv1/hal_adc_lld.c index 63e0dfff90..cb05b36d6d 100644 --- a/os/hal/ports/ES32/LLD/ADCv1/hal_adc_lld.c +++ b/os/hal/ports/ES32/LLD/ADCv1/hal_adc_lld.c @@ -52,21 +52,13 @@ /*===========================================================================*/ #if ES32_ADC_USE_ADC1 || defined(__DOXYGEN__) -#if !defined(ES32_ADC1_HANDLER) - #error "ES32_ADC1_HANDLER not defined" -#endif + /** * @brief ADC interrupt handler. * * @isr */ -OSAL_IRQ_HANDLER(ES32_ADC1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - OSAL_IRQ_EPILOGUE(); -} #endif /*===========================================================================*/ diff --git a/os/hal/ports/ES32/LLD/ADCv1/hal_adc_lld.h b/os/hal/ports/ES32/LLD/ADCv1/hal_adc_lld.h index fd4c53cf3a..deea731119 100644 --- a/os/hal/ports/ES32/LLD/ADCv1/hal_adc_lld.h +++ b/os/hal/ports/ES32/LLD/ADCv1/hal_adc_lld.h @@ -91,16 +91,53 @@ typedef uint32_t adcerror_t; NOTE: The bits @p ADC_CFGR1_CONT or @p ADC_CFGR1_DISCEN must be \ specified in continuous more or if the buffer depth is \ greater than one.*/ \ - uint32_t cfgr1; \ - /* ADC TR register initialization data.*/ \ - uint32_t tr; \ - /* ADC SMPR register initialization data.*/ \ - uint32_t smpr; \ - /* ADC CHSELR register initialization data. \ - NOTE: The number of bits at logic level one in this register must \ - be equal to the number in the @p num_channels field.*/ \ - uint32_t chselr; - + uint32_t cr2; \ + uint32_t smpr1; \ + uint32_t smpr2; \ + uint32_t sqr3; \ + +#define ADC_COUNT 1 +#define USE_ADCV2 + +#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ +#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ +#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ +#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ +#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ +#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ + +#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ +#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ +#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ +#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ +#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ +#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ + +#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ +#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ +#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ +#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ + +#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ +#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ + +#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ + +#define ADC_SAMPLING_RATE 0 +#define ADC_CR2_SWSTART 0 /*===========================================================================*/ /* External declarations. */ diff --git a/os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.h b/os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.h index ec5e55ebb9..a67ebfa15e 100644 --- a/os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.h +++ b/os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.h @@ -126,6 +126,11 @@ */ #define PAL_MODE_OUTPUT_OPENDRAIN (PAL_ES32_MODE_OUTPUT | \ PAL_ES32_OT_OPENDRAIN) + +#define PAL_OUTPUT_TYPE_OPENDRAIN PAL_MODE_OUTPUT_OPENDRAIN +#define PAL_OUTPUT_TYPE_PUSHPULL PAL_MODE_OUTPUT_PUSHPULL +#define PAL_OUTPUT_SPEED_HIGHEST 0U + /** @} */ /*===========================================================================*/ /* I/O Ports Types and constants. */ diff --git a/os/hal/ports/ES32/LLD/GPIOv2/driver.mk b/os/hal/ports/ES32/LLD/GPIOv2/driver.mk new file mode 100644 index 0000000000..67906e432b --- /dev/null +++ b/os/hal/ports/ES32/LLD/GPIOv2/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/GPIOv2/hal_pal_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/GPIOv2/hal_pal_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/GPIOv2 diff --git a/os/hal/ports/ES32/LLD/GPIOv2/hal_pal_lld.c b/os/hal/ports/ES32/LLD/GPIOv2/hal_pal_lld.c new file mode 100644 index 0000000000..1b29faf48d --- /dev/null +++ b/os/hal/ports/ES32/LLD/GPIOv2/hal_pal_lld.c @@ -0,0 +1,202 @@ +/* + Copyright (C) 2020 + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_pal_lld.c + * @brief ES32 PAL subsystem low level driver source. + * + * @addtogroup PAL + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_PAL == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if (PAL_USE_WAIT == TRUE) || (PAL_USE_CALLBACKS == TRUE) || defined(__DOXYGEN__) +/** + * @brief Event records for the 16 GPIO EXTI channels. + */ +palevent_t _pal_events[16]; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief PAL driver initialization. + * + * @notapi + */ +void _pal_lld_init(void) { + +#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__) + unsigned i; + + for (i = 0; i < 16; i++) { + _pal_init_event(i); + } +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum + * speed. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) +{ + md_gpio_init_t gpio_config; + + gpio_config.mode = (mode & PAL_ES32_MODE_MASK) >> 0; + gpio_config.odos = (mode & PAL_ES32_OT_MASK) >> 2; + gpio_config.odrv = (mode & PAL_ES32_DS_MASK) >> 3; + gpio_config.pupd = (mode & PAL_ES32_PUD_MASK) >> 5; + gpio_config.flt = MD_GPIO_FILTER_DISABLE; + gpio_config.type = MD_GPIO_TYPE_CMOS; + gpio_config.func = MD_GPIO_FUNC_1; + + if(gpio_config.mode == PAL_ES32_MODE_ALTERNATE) + { + gpio_config.func = (mode & PAL_ES32_ALTERNATE_MASK) >> 7; + } + + md_gpio_init(port, mask, &gpio_config); +} + +#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__) +/** + * @brief Pad event enable. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad event mode + * + * @notapi + */ +void _pal_lld_enablepadevent(ioportid_t port, + iopadid_t pad, + ioeventmode_t mode) { + + uint32_t padmask, cridx, croff, crmask, portidx; + + /* Mask of the pad.*/ + padmask = 1U << (uint32_t)pad; + + if (pad & 3U) + NVIC_EnableIRQ((IRQn_Type) EXTI_0to1_IRQn); /* EXTI_0to1_IRQn interrupt */ + else if (pad & 0xCU) + NVIC_EnableIRQ((IRQn_Type) EXTI_2to3_IRQn); /* EXTI_2to3_IRQn interrupt */ + else if (pad & 0xFFF0U) + NVIC_EnableIRQ((IRQn_Type) EXTI_4to15_IRQn); /* EXTI_4to15_IRQn interrupt */ + + /* Clear pending interrupt flag before enable interrupt event */ + EXTI->ICR = EXTI_IFM; + + /* Programming edge registers.*/ + if (mode & PAL_EVENT_MODE_RISING_EDGE) + EXTI->RTS |= padmask; + else + EXTI->RTS &= ~padmask; + if (mode & PAL_EVENT_MODE_FALLING_EDGE) + EXTI->FTS |= padmask; + else + EXTI->FTS &= ~padmask; + + portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0x3U; + if (padmask < 8) + EXTI_ICFG1 = (uint32_t)portidx << (pad * 4U); + else + EXTI_ICFG2 = (uint32_t)portidx << (pad * 4U); + + EXTI_IER = padmask; +} + +/** + * @brief Pad event disable. + * @details This function disables previously programmed event callbacks. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) { + uint32_t padmask, rtsr1, ftsr1; + + rts = EXTI->RTS; + fts = EXTI->FTS; + + /* Mask of the pad.*/ + padmask = 1U << (uint32_t)pad; + + /* Clear pending interrupt flag before enable interrupt event */ + EXTI->ICR = EXTI_IFM; + EXTI->IDR = padmask; + + if (((pad & 3U) | (EXTI_IER & 3U)) == 0) + NVIC_DisableIRQ((IRQn_Type) EXTI_0to1_IRQn); /* EXTI_0to1_IRQn interrupt */ + else if (((pad & 0xCU) | (EXTI_IER & 0xCU)) == 0) + NVIC_DisableIRQ((IRQn_Type) EXTI_2to3_IRQn); /* EXTI_2to3_IRQn interrupt */ + else if ((pad & 0xFFF0U) | (EXTI_IER & 0xFFF0U) == 0) + NVIC_DisableIRQ((IRQn_Type) EXTI_4to15_IRQn); /* EXTI_4to15_IRQn interrupt */ + + /* Disabling channel.*/ + EXTI->RTS = rts & ~padmask; + EXTI->FTS = fts & ~padmask; + +#if PAL_USE_CALLBACKS || PAL_USE_WAIT + /* Callback cleared and/or thread reset.*/ + _pal_clear_event(pad); +#endif + } +} +#endif /* PAL_USE_CALLBACKS || PAL_USE_WAIT */ +#endif /* HAL_USE_PAL == TRUE */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/GPIOv2/hal_pal_lld.h b/os/hal/ports/ES32/LLD/GPIOv2/hal_pal_lld.h new file mode 100644 index 0000000000..13b8c2ea7f --- /dev/null +++ b/os/hal/ports/ES32/LLD/GPIOv2/hal_pal_lld.h @@ -0,0 +1,445 @@ +/* + Copyright (C) 2020 + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_pal_lld.h + * @brief ES32 PAL low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef HAL_PAL_LLD_H +#define HAL_PAL_LLD_H + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +/* Specifies palInit() without parameter, required until all platforms will + be updated to the new style.*/ +#define PAL_NEW_INIT + +#undef PAL_MODE_RESET +#undef PAL_MODE_UNCONNECTED +#undef PAL_MODE_INPUT +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_PUSHPULL +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/** + * @name ES32-specific I/O mode flags + * @{ + */ +#define PAL_ES32_MODE_MASK (3U << 0U) +#define PAL_ES32_MODE_INPUT (1U << 0U) +#define PAL_ES32_MODE_OUTPUT (2U << 0U) +#define PAL_ES32_MODE_ALTERNATE (3U << 0U) +#define PAL_ES32_MODE_ANALOG (0U << 0U) + +#define PAL_ES32_OT_MASK (1U << 2U) +#define PAL_ES32_OT_PUSHPULL (0U << 2U) +#define PAL_ES32_OT_OPENDRAIN (2U << 2U) + +#define PAL_ES32_DS_MASK (1U << 4U) +#define PAL_ES32_DS_8MA (0U << 4U) +#define PAL_ES32_DS_16MA (1U << 4U) + +#define PAL_ES32_PUD_MASK (3U << 5U) +#define PAL_ES32_PUD_FLOATING (0U << 5U) +#define PAL_ES32_PUD_PULLUP (1U << 5U) +#define PAL_ES32_PUD_PULLDOWN (2U << 5U) + +#define PAL_ES32_ALTERNATE_MASK (15U << 7U) +#define PAL_ES32_ALTERNATE(n) ((n) << 7U) + +/** + * @brief Alternate function. + * + * @param[in] n alternate function selector + */ +#define PAL_MODE_ALTERNATE(n) (PAL_ES32_MODE_ALTERNATE | \ + PAL_ES32_ALTERNATE(n)) +/** @} */ + +/** + * @name Standard I/O mode flags + * @{ + */ +/** + * @brief Implemented as input. + */ +#define PAL_MODE_RESET PAL_ES32_MODE_ANALOG + +/** + * @brief Implemented as input with pull-up. + */ +#define PAL_MODE_UNCONNECTED PAL_MODE_INPUT_PULLUP + +/** + * @brief Regular input high-Z pad. + */ +#define PAL_MODE_INPUT PAL_ES32_MODE_INPUT + +/** + * @brief Input pad with weak pull up resistor. + */ +#define PAL_MODE_INPUT_PULLUP (PAL_ES32_MODE_INPUT | \ + PAL_ES32_PUD_PULLUP) + +/** + * @brief Input pad with weak pull down resistor. + */ +#define PAL_MODE_INPUT_PULLDOWN (PAL_ES32_MODE_INPUT | \ + PAL_ES32_PUD_PULLDOWN) + +/** + * @brief Analog input mode. + */ +#define PAL_MODE_INPUT_ANALOG PAL_ES32_MODE_ANALOG + +/** + * @brief Push-pull output pad. + */ +#define PAL_MODE_OUTPUT_PUSHPULL (PAL_ES32_MODE_OUTPUT | \ + PAL_ES32_OT_PUSHPULL) + +/** + * @brief Open-drain output pad. + */ +#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_ES32_MODE_OUTPUT | \ + PAL_ES32_OT_OPENDRAIN) + +#define PAL_OUTPUT_TYPE_OPENDRAIN PAL_MODE_OUTPUT_OPENDRAIN +#define PAL_OUTPUT_TYPE_PUSHPULL PAL_MODE_OUTPUT_PUSHPULL +#define PAL_OUTPUT_SPEED_HIGHEST 0U + +/** @} */ +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @name Port related definitions + * @{ + */ +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 16U + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFU) +/** @} */ + +/** + * @name Line handling macros + * @{ + */ +/** + * @brief Forms a line identifier. + * @details A port/pad pair are encoded into an @p ioline_t type. The encoding + * of this type is platform-dependent. + * @note In this driver the pad number is encoded in the lower 4 bits of + * the GPIO address which are guaranteed to be zero. + */ +#define PAL_LINE(port, pad) \ + ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad))) + +/** + * @brief Decodes a port identifier from a line identifier. + */ +#define PAL_PORT(line) \ + ((GPIO_TypeDef *)(((uint32_t)(line)) & 0xFFFFFFF0U)) + +/** + * @brief Decodes a pad identifier from a line identifier. + */ +#define PAL_PAD(line) \ + ((uint32_t)((uint32_t)(line) & 0x0000000FU)) + +/** + * @brief Value identifying an invalid line. + */ +#define PAL_NOLINE 0U +/** @} */ + +/** + * @brief Type of digital I/O port sized unsigned integer. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Type of digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Type of an I/O line. + */ +typedef uint32_t ioline_t; + +/** + * @brief Type of an event mode. + */ +typedef uint32_t ioeventmode_t; + +/** + * @brief Type of a port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef GPIO_TypeDef * ioportid_t; + +/** + * @brief Type of an pad identifier. + */ +typedef uint32_t iopadid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/* The low level driver wraps the definitions already present in the ES32 */ +/* firmware library. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief GPIO ports subsystem initialization. + * + * @notapi + */ +#define pal_lld_init() _pal_lld_init() + +/** + * @brief Reads an I/O port. + * @details This function is implemented by reading the GPIO ID register, the + * implementation has no side effects. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((ioportmask_t)((port)->DIN)) + + +/** + * @brief Reads the output latch. + * @details This function is implemented by reading the GPIO OD register, the + * implementation has no side effects. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((ioportmask_t)((port)->OD)) + +/** + * @brief Writes on a I/O port. + * @details This function is implemented by writing the GPIO OD register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) \ + do { \ + (port)->OD = (uint32_t)(bits); \ + } while (false) + + +/** + * @brief Sets a bits mask on a I/O port. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) \ + do { \ + (port)->BSRR = (uint32_t)(bits); \ + } while (false) + + +/** + * @brief Clears a bits mask on a I/O port. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) \ + do { \ + (port)->BSRR = (uint32_t)(bits << 16); \ + } while (false) + +/** + * @brief Writes a group of bits. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset the group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group + * width are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits){ \ + uint32_t w = ((~(uint32_t)(bits) & (uint32_t)(mask)) << (16U + (offset))) | \ + ((uint32_t)(bits) & (uint32_t)(mask)) << (offset); \ + (port)->BSRR = w; \ +} + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) + +/** + * @brief Pad event enable. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad event mode + * + * @notapi + */ +#define pal_lld_enablepadevent(port, pad, mode) \ + _pal_lld_enablepadevent(port, pad, mode) + +/** + * @brief Pad event disable. + * @details This function disables previously programmed event callbacks. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_disablepadevent(port, pad) \ + _pal_lld_disablepadevent(port, pad) + +/** + * @brief Returns a PAL event structure associated to a pad. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_get_pad_event(port, pad) \ + &_pal_events[pad]; (void)(port) + +/** + * @brief Returns a PAL event structure associated to a line. + * + * @param[in] line line identifier + * + * @notapi + */ +#define pal_lld_get_line_event(line) \ + &_pal_events[PAL_PAD(line)] + +/** + * @brief Pad event enable check. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @return Pad event status. + * @retval false if the pad event is disabled. + * @retval true if the pad event is enabled. + * + * @notapi + */ +#define pal_lld_ispadeventenabled(port, pad) \ + (bool)((EXTI->IFM & (1U << (uint32_t)pad)) != 0U) + +#if !defined(__DOXYGEN__) +#if (PAL_USE_WAIT == TRUE) || (PAL_USE_CALLBACKS == TRUE) +extern palevent_t _pal_events[16]; +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(void); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); + void _pal_lld_enablepadevent(ioportid_t port, + iopadid_t pad, + ioeventmode_t mode); + void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL == TRUE */ + +#endif /* HAL_PAL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/I2Cv1/hal_i2c_lld.c b/os/hal/ports/ES32/LLD/I2Cv1/hal_i2c_lld.c index d987a957a5..6a117b7a42 100644 --- a/os/hal/ports/ES32/LLD/I2Cv1/hal_i2c_lld.c +++ b/os/hal/ports/ES32/LLD/I2Cv1/hal_i2c_lld.c @@ -55,6 +55,8 @@ /*===========================================================================*/ #if ES32_I2C_USE_I2C1 || defined(__DOXYGEN__) +I2CDriver I2CD1; + /** * @brief I2C1 event interrupt handler. * @@ -65,8 +67,6 @@ OSAL_IRQ_HANDLER(ES32_I2C1_EVENT_HANDLER) OSAL_IRQ_PROLOGUE(); - i2c_lld_serve_event_interrupt(&I2CD1); - OSAL_IRQ_EPILOGUE(); } @@ -92,8 +92,6 @@ OSAL_IRQ_HANDLER(ES32_I2C2_EVENT_HANDLER) OSAL_IRQ_PROLOGUE(); - i2c_lld_serve_event_interrupt(&I2CD2); - OSAL_IRQ_EPILOGUE(); } @@ -121,8 +119,6 @@ OSAL_IRQ_HANDLER(ES32_I2C3_EVENT_HANDLER) OSAL_IRQ_PROLOGUE(); - i2c_lld_serve_event_interrupt(&I2CD3); - OSAL_IRQ_EPILOGUE(); } diff --git a/os/hal/ports/ES32/LLD/I2Cv1/hal_i2c_lld.h b/os/hal/ports/ES32/LLD/I2Cv1/hal_i2c_lld.h index 7bc24fef35..0e85ee40b2 100644 --- a/os/hal/ports/ES32/LLD/I2Cv1/hal_i2c_lld.h +++ b/os/hal/ports/ES32/LLD/I2Cv1/hal_i2c_lld.h @@ -80,12 +80,9 @@ typedef enum { */ struct hal_i2c_config { /* End of the mandatory fields.*/ - i2copmode_t op_mode; /**< @brief Specifies the I2C mode. */ uint32_t clock_speed; /**< @brief Specifies the clock frequency. @note Must be set to a value lower than 400kHz. */ - i2cdutycycle_t duty_cycle; /**< @brief Specifies the I2C fast mode - duty cycle. */ }; /** @@ -171,6 +168,13 @@ struct hal_i2c_driver { /* External declarations. */ /*===========================================================================*/ +#if !defined(__DOXYGEN__) + +extern I2CDriver I2CD1; +extern I2CDriver I2CD2; + +#endif /* !defined(__DOXYGEN__) */ + #ifdef __cplusplus extern "C" { #endif diff --git a/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.c b/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.c index 408e6b7f53..d5f0d68755 100644 --- a/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.c +++ b/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.c @@ -37,12 +37,12 @@ /** @brief SPI1 driver identifier.*/ -#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__) +#if ES32_SPI_USE_SPI1 || defined(__DOXYGEN__) SPIDriver SPID1; #endif /** @brief SPI2 driver identifier.*/ -#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__) +#if ES32_SPI_USE_SPI2 || defined(__DOXYGEN__) SPIDriver SPID2; #endif @@ -56,75 +56,10 @@ SPIDriver SPID2; /*===========================================================================*/ #if (ES32_SPI_USE_SPI1 == TRUE) || (ES32_SPI_USE_SPI2 == TRUE) || defined(__DOXYGEN__) -static void spi_lld_rx(SPIDriver *const spip) -{ - uint32_t fd; - uint32_t sr; - - while (spip->rxcnt) - { - sr = spip->SPI->SR; - - if ((sr & SPI_SR_RXBNE) == 0) - return; - - fd = spip->SPI->DR; - - if (spip->rxptr) - { - *spip->rxptr++ = fd & 0xff; - } - - spip->rxcnt--; - } -} - -static void spi_lld_tx(SPIDriver *const spip) -{ - uint32_t fd; - uint32_t sr; - - while (spip->txcnt) - { - sr = spip->SPI->SR; - - // avoid write collision - if (spip->SPI->FCR & SPI_FCR_FIFOEN) - { - if ((sr & SPI_SR_TXBE) == 0) - return; - } - else - { - if ((sr & SPI_SR_TXE) == 0) - return; - } - - if (spip->txptr) - { - fd = *spip->txptr++; - } - else - { - fd = '\xff'; - } - - spip->SPI->DR = fd; - spip->txcnt--; - } -} static void spi_lld_handler(SPIDriver *const spip) { - //uint32_t sr = spip->SPI->SR; // & ((1U<<8)|spip->SPI->IER); - spi_lld_rx(spip); - spi_lld_tx(spip); - - if (spip->rxcnt == 0) - { - spip->SPI->IER = 0; - _spi_isr_code(spip); - } + } #endif @@ -183,35 +118,7 @@ void spi_lld_init(void) */ void spi_lld_start(SPIDriver *spip) { - if (spip->state == SPI_STOP) - { - /* Enables the peripheral.*/ -#if ES32_SPI_USE_SPI1 == TRUE - if (&SPID1 == spip) - { - md_rcu_enable_spi1(RCU); - nvicEnableVector(SPI1_IRQn, ES32_SPI1_IRQ_PRIORITY); - } - -#endif -#if ES32_SPI_USE_SPI2 == TRUE - - if (&SPID2 == spip) - { - md_rcu_enable_spi2(RCU); - nvicEnableVector(SPI2_IRQn, ES32_SPI2_IRQ_PRIORITY); - } - -#endif - } - - /* Configures the peripheral.*/ - spip->SPI->CR0 = spip->config->cr0; - spip->SPI->CR1 = spip->config->cr1; - spip->SPI->CPR = spip->config->cpr; - //spip->SPI->FCR = 0; //SPI_FCR_FIFOEN | (1U << 4) | (1U << 0); - spip->SPI->FCR = spip->config->fcr; - spip->SPI->CR0 |= SPI_CR0_SPIEN; + } /** @@ -223,25 +130,7 @@ void spi_lld_start(SPIDriver *spip) */ void spi_lld_stop(SPIDriver *spip) { - if (spip->state == SPI_READY) - { - /* Disables the peripheral.*/ -#if ES32_SPI_USE_SPI1 == TRUE - if (&SPID1 == spip) - { - nvicDisableVector(SPI1_IRQn); - } - -#endif -#if ES32_SPI_USE_SPI2 == TRUE - - if (&SPID2 == spip) - { - nvicDisableVector(SPI2_IRQn); - } - -#endif - } + } /** @@ -282,7 +171,7 @@ void spi_lld_unselect(SPIDriver *spip) */ void spi_lld_ignore(SPIDriver *spip, size_t n) { - spi_lld_exchange(spip, n, NULL, NULL); + } /** @@ -303,10 +192,7 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) void spi_lld_exchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf) { - spip->txptr = txbuf; - spip->rxptr = rxbuf; - spip->rxcnt = spip->txcnt = n; - spip->SPI->IER = SPI_IER_RXBNEIEN | SPI_IER_TXBEIEN | SPI_IER_TXEIEN; + } /** @@ -324,7 +210,7 @@ void spi_lld_exchange(SPIDriver *spip, size_t n, */ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { - spi_lld_exchange(spip, n, txbuf, NULL); + } /** @@ -342,7 +228,7 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) */ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { - spi_lld_exchange(spip, n, NULL, rxbuf); + } /** @@ -359,12 +245,7 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) */ uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { - spip->SPI->DR = frame; - - while ((spip->SPI->SR & SPI_SR_RXBNE) == 0) - ; - - return (spip->SPI->DR & 0xffff); + return 0; } #endif /* HAL_USE_SPI == TRUE */ diff --git a/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.h b/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.h index 44e7bca4be..8ee883ac95 100644 --- a/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.h +++ b/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.h @@ -39,13 +39,33 @@ * @name ES32 configuration options * @{ */ +#ifdef ES32VF2264 + +#define SPI_CR1_LSBFIRST SPI_CON1_LSBFST_MSK +#define SPI_CR1_CPHA SPI_CON1_CPHA_MSK +#define SPI_CR1_CPOL SPI_CON1_CPOL_MSK +#define SPI_CR1_BR_0 0U +#define SPI_CR1_BR_1 0U +#define SPI_CR1_BR_2 0U + +#else + +#define SPI_CR1_LSBFIRST SPI_CON1_LSBFST +#define SPI_CR1_CPHA SPI_CON1_CPHA +#define SPI_CR1_CPOL SPI_CON1_CPOL +#define SPI_CR1_BR_0 0U +#define SPI_CR1_BR_1 0U +#define SPI_CR1_BR_2 0U + +#endif + /** * @brief SPI1 driver enable switch. * @details If set to @p TRUE the support for SPI0 is included. * @note The default is @p FALSE. */ -#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI1 FALSE +#if !defined(ES32_SPI_USE_SPI1) || defined(__DOXYGEN__) +#define ES32_SPI_USE_SPI1 FALSE #endif /** @@ -53,8 +73,8 @@ * @details If set to @p TRUE the support for SPI2 is included. * @note The default is @p FALSE. */ -#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI2 FALSE +#if !defined(ES32_SPI_USE_SPI2) || defined(__DOXYGEN__) +#define ES32_SPI_USE_SPI2 FALSE #endif /** @} */ @@ -70,6 +90,10 @@ /** * @brief Low Level fields of the SPI driver structure. */ +#ifdef ES32VF2264 +#define SPI_TypeDef SPI_I2S_TypeDef +#endif + #define spi_lld_driver_fields \ SPI_TypeDef *SPI; \ uint8_t *rxptr; \ @@ -94,11 +118,11 @@ /* External declarations. */ /*===========================================================================*/ -#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__) +#if ES32_SPI_USE_SPI1 && !defined(__DOXYGEN__) extern SPIDriver SPID1; #endif -#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__) +#if ES32_SPI_USE_SPI2 && !defined(__DOXYGEN__) extern SPIDriver SPID2; #endif diff --git a/os/hal/ports/ES32/LLD/TIMv2/driver.mk b/os/hal/ports/ES32/LLD/TIMv2/driver.mk new file mode 100644 index 0000000000..6a39a6fe32 --- /dev/null +++ b/os/hal/ports/ES32/LLD/TIMv2/driver.mk @@ -0,0 +1,15 @@ +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/TIMv2/hal_st_lld.c + +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/TIMv2/hal_gpt_lld.c +endif +ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/TIMv2/hal_pwm_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/TIMv2/hal_gpt_lld.c +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/TIMv2/hal_pwm_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/ES32/LLD/TIMv2 diff --git a/os/hal/ports/ES32/LLD/TIMv2/hal_gpt_lld.c b/os/hal/ports/ES32/LLD/TIMv2/hal_gpt_lld.c new file mode 100644 index 0000000000..efb325057d --- /dev/null +++ b/os/hal/ports/ES32/LLD/TIMv2/hal_gpt_lld.c @@ -0,0 +1,238 @@ +/* + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_gpt_lld.c + * @brief PLATFORM GPT subsystem low level driver source. + * + * @addtogroup GPT + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_GPT == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief GPTD1 driver identifier. + */ +#if (ES32_GPT_USE_BFTM0 == TRUE) || defined(__DOXYGEN__) + GPTDriver GPTD_BFTM0; +#endif + +#if (ES32_GPT_USE_BFTM1 == TRUE) || defined(__DOXYGEN__) + GPTDriver GPTD_BFTM1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpt_lld_handler(GPTDriver *gptp) +{ + if (gptp->BFTM->SR & BFTM_SR_MIF) + { + gptp->BFTM->SR = 0; + + if (gptp->config->callback) + gptp->config->callback(gptp); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (ES32_GPT_USE_BFTM0 == TRUE) || defined(__DOXYGEN__) +#ifndef ES32_BFTM0_IRQ_VECTOR + #error "ES32_BFTM0_IRQ_VECTOR is not defined" +#endif +OSAL_IRQ_HANDLER(ES32_BFTM0_IRQ_VECTOR) +{ + OSAL_IRQ_PROLOGUE(); + gpt_lld_handler(&GPTD_BFTM0); + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if (ES32_GPT_USE_BFTM1 == TRUE) || defined(__DOXYGEN__) +OSAL_IRQ_HANDLER(ES32_BFTM1_IRQ_VECTOR) +{ + OSAL_IRQ_PROLOGUE(); + gpt_lld_handler(&GPTD_BFTM1); + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level GPT driver initialization. + * + * @notapi + */ +void gpt_lld_init(void) +{ + /* Driver initialization.*/ +#if ES32_GPT_USE_BFTM0 == TRUE + gptObjectInit(&GPTD_BFTM0); + GPTD_BFTM0.BFTM = BFTM0; +#endif +#if ES32_GPT_USE_BFTM1 == TRUE + gptObjectInit(&GPTD_BFTM1); + GPTD_BFTM1.BFTM = BFTM1; +#endif +} + +/** + * @brief Configures and activates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_start(GPTDriver *gptp) +{ + if (gptp->state == GPT_STOP) + { + /* Enables the peripheral.*/ +#if ES32_GPT_USE_BFTM0 == TRUE + if (&GPTD_BFTM0 == gptp) + { + CKCU->APBCCR1 |= CKCU_APBCCR1_BFTM0EN; + nvicEnableVector(BFTM0_IRQn, ES32_GPT_BFTM0_IRQ_PRIORITY); + } + +#endif +#if ES32_GPT_USE_BFTM1 == TRUE + + if (&GPTD_BFTM1 == gptp) + { + CKCU->APBCCR1 |= CKCU_APBCCR1_BFTM1EN; + nvicEnableVector(BFTM1_IRQn, ES32_GPT_BFTM1_IRQ_PRIORITY); + } + +#endif + } + + /* Configures the peripheral.*/ + gptp->BFTM->CR = 0; + // counter frequency depends on the AHB clock, we can't + // change anything here +} + +/** + * @brief Deactivates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop(GPTDriver *gptp) +{ + if (gptp->state == GPT_READY) + { + /* Resets the peripheral.*/ + /* Disables the peripheral.*/ +#if ES32_GPT_USE_BFTM0 == TRUE + if (&GPTD_BFTM0 == gptp) + { + RSTCU->APBPRSTR1 = RSTCU_APBPRSTR1_BFTM0RST; + CKCU->APBCCR1 &= ~CKCU_APBCCR1_BFTM0EN; + nvicDisableVector(BFTM0_IRQn); + } + +#endif +#if ES32_GPT_USE_BFTM1 == TRUE + + if (&GPTD_BFTM1 == gptp) + { + RSTCU->APBPRSTR1 = RSTCU_APBPRSTR1_BFTM1RST; + CKCU->APBCCR1 &= ~CKCU_APBCCR1_BFTM1EN; + nvicDisableVector(BFTM1_IRQn); + } + +#endif + } +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @notapi + */ +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) +{ + gptp->BFTM->SR = 0; + gptp->BFTM->CNTR = 0; + gptp->BFTM->CMP = (ES32_CK_AHB_FREQUENCY / gptp->config->frequency) * interval; + gptp->BFTM->CR = BFTM_CR_CEN | BFTM_CR_MIEN; +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop_timer(GPTDriver *gptp) +{ + gptp->BFTM->CR = 0; +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @notapi + */ +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) +{ + gptp->BFTM->SR = 0; + gptp->BFTM->CNTR = 0; + gptp->BFTM->CMP = (ES32_CK_AHB_FREQUENCY / gptp->config->frequency) * interval; + gptp->BFTM->CR = BFTM_CR_CEN | BFTM_CR_OSM; + + while (!(gptp->BFTM->SR & BFTM_SR_MIF)) + ; +} + +#endif /* HAL_USE_GPT == TRUE */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/TIMv2/hal_gpt_lld.h b/os/hal/ports/ES32/LLD/TIMv2/hal_gpt_lld.h new file mode 100644 index 0000000000..16676d44cb --- /dev/null +++ b/os/hal/ports/ES32/LLD/TIMv2/hal_gpt_lld.h @@ -0,0 +1,197 @@ +/* + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_gpt_lld.h + * @brief PLATFORM GPT subsystem low level driver header. + * + * @addtogroup GPT + * @{ + */ + +#ifndef HAL_GPT_LLD_H +#define HAL_GPT_LLD_H + +#if (HAL_USE_GPT == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ +/** + * @brief GPTD1 driver enable switch. + * @details If set to @p TRUE the support for GPTD1 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_GPT_USE_BFTM0) || defined(__DOXYGEN__) + #define ES32_GPT_USE_BFTM0 FALSE +#endif + +#if !defined(ES32_GPT_USE_BFTM1) || defined(__DOXYGEN__) + #define ES32_GPT_USE_BFTM1 FALSE +#endif + +/** + * @brief GPTD1 interrupt priority level setting. + */ +#if !defined(ES32_GPT_BFTM0_IRQ_PRIORITY) || defined(__DOXYGEN__) + #define ES32_GPT_BFTM0_IRQ_PRIORITY 7 +#endif + +#if !defined(ES32_GPT_BFTM1_IRQ_PRIORITY) || defined(__DOXYGEN__) + #define ES32_GPT_BFTM1_IRQ_PRIORITY 7 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPT frequency type. + */ +typedef uint32_t gptfreq_t; + +/** + * @brief GPT counter type. + */ +typedef uint16_t gptcnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct +{ + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + gptfreq_t frequency; + /** + * @brief Timer callback pointer. + * @note This callback is invoked on GPT counter events. + */ + gptcallback_t callback; + /* End of the mandatory fields.*/ +} GPTConfig; + +/** + * @brief Structure representing a GPT driver. + */ +struct GPTDriver +{ + /** + * @brief Driver state. + */ + gptstate_t state; + /** + * @brief Current configuration data. + */ + const GPTConfig *config; +#if defined(GPT_DRIVER_EXT_FIELDS) + GPT_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + BFTM_TypeDef *BFTM; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the interval of GPT peripheral. + * @details This function changes the interval of a running GPT unit. + * @pre The GPT unit must have been activated using @p gptStart(). + * @pre The GPT unit must have been running in continuous mode using + * @p gptStartContinuous(). + * @post The GPT unit interval is changed to the new value. + * @note The function has effect at the next cycle start. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @param[in] interval new cycle time in timer ticks + * @notapi + */ +#define gpt_lld_change_interval(gptp, interval) \ + ((gptp)->BFTM->CMP = (ES32_CK_AHB_FREQUENCY / (gptp)->config->frequency) * (interval)) + +/** + * @brief Returns the interval of GPT peripheral. + * @pre The GPT unit must be running in continuous mode. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @return The current interval. + * @notapi + */ +#define gpt_lld_get_interval(gptp) \ + ((gptcnt_t)(gptp)->BFTM->CMP / (ES32_CK_AHB_FREQUENCY / (gptp)->config->frequency)) + +/** + * @brief Returns the counter value of GPT peripheral. + * @pre The GPT unit must be running in continuous mode. + * @note The nature of the counter is not defined, it may count upward + * or downward, it could be continuously running or not. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @return The current counter value. + * @notapi + */ +#define gpt_lld_get_counter(gptp) \ + ((gptcnt_t)((gptp)->BFTM->CNTR / (ES32_CK_AHB_FREQUENCY / (gptp)->config->frequency))) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if (ES32_GPT_USE_BFTM0 == TRUE) && !defined(__DOXYGEN__) + extern GPTDriver GPTD_BFTM0; +#endif +#if (ES32_GPT_USE_BFTM1 == TRUE) && !defined(__DOXYGEN__) + extern GPTDriver GPTD_BFTM1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif +void gpt_lld_init(void); +void gpt_lld_start(GPTDriver *gptp); +void gpt_lld_stop(GPTDriver *gptp); +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval); +void gpt_lld_stop_timer(GPTDriver *gptp); +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT == TRUE */ + +#endif /* HAL_GPT_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/TIMv2/hal_pwm_lld.c b/os/hal/ports/ES32/LLD/TIMv2/hal_pwm_lld.c new file mode 100644 index 0000000000..b333b4c027 --- /dev/null +++ b/os/hal/ports/ES32/LLD/TIMv2/hal_pwm_lld.c @@ -0,0 +1,267 @@ +/* + Copyright (C) 2020 + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_pwm_lld.c + * @brief ES32 PWM subsystem low level driver source. + * + * @addtogroup PWM + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_PWM == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief PWM_AD16C4T1 driver identifier. + * @note The driver PWM_AD16C4T1 allocates the complex timer AD16C4T1 when enabled. + */ +#if ES32_PWM_USE_AD16C4T1 || defined(__DOXYGEN__) +PWMDriver PWM_AD16C4T1; +#endif + +/** + * @brief PWM_GP32C4T1 driver identifier. + * @note The driver PWM_GP32C4T1 allocates the timer GP32C4T1 when enabled. + */ +#if ES32_PWM_USE_GP32C4T1 || defined(__DOXYGEN__) +PWMDriver PWM_GP32C4T1; +#endif + +/** + * @brief PWM_GP16C4T1 driver identifier. + * @note The driver PWM_GP16C4T1 allocates the timer GP16C4T1 when enabled. + */ +#if ES32_PWM_USE_GP16C4T1 || defined(__DOXYGEN__) +PWMDriver PWM_GP16C4T1; +#endif + +/** + * @brief PWM_GP16C4T2 driver identifier. + * @note The driver PWM_GP16C4T2 allocates the timer GP16C4T2 when enabled. + */ +#if ES32_PWM_USE_GP16C4T2 || defined(__DOXYGEN__) +PWMDriver PWM_GP16C4T2; +#endif + +/** + * @brief PWM_GP16C4T3 driver identifier. + * @note The driver PWM_GP16C4T3 allocates the timer GP16C4T3 when enabled. + */ +#if ES32_PWM_USE_GP16C4T3 || defined(__DOXYGEN__) +PWMDriver PWM_GP16C4T3; +#endif + +/** + * @brief PWM_GP16C2T1 driver identifier. + * @note The driver PWM_GP16C2T1 allocates the timer GP16C2T1 when enabled. + */ +#if ES32_PWM_USE_GP16C2T1 || defined(__DOXYGEN__) +PWMDriver PWM_GP16C2T1; +#endif + +/** + * @brief PWM_GP16C2T2 driver identifier. + * @note The driver PWM_GP16C2T2 allocates the timer GP16C2T2 when enabled. + */ +#if ES32_PWM_USE_GP16C2T2 || defined(__DOXYGEN__) +PWMDriver PWM_GP16C2T2; +#endif + +/** + * @brief PWM_GP16C2T3 driver identifier. + * @note The driver PWM_GP16C2T3 allocates the timer GP16C2T3 when enabled. + */ +#if ES32_PWM_USE_GP16C2T3 || defined(__DOXYGEN__) +PWMDriver PWM_GP16C2T3; +#endif + +/** + * @brief PWM_GP16C2T4 driver identifier. + * @note The driver PWM_GP16C2T4 allocates the timer GP16C2T4 when enabled. + */ +#if ES32_PWM_USE_GP16C2T4 || defined(__DOXYGEN__) +PWMDriver PWM_GP16C2T4; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level PWM driver initialization. + * + * @notapi + */ +void pwm_lld_init(void) { + +} + +/** + * @brief Configures and activates the PWM peripheral. + * @note Starting a driver that is already in the @p PWM_READY state + * disables all the active channels. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_start(PWMDriver *pwmp) { + +} + +/** + * @brief Deactivates the PWM peripheral. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_stop(PWMDriver *pwmp) { + +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note The function has effect at the next cycle start. + * @note Channel notification is not enabled. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @notapi + */ +void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width) { + +} + +/** + * @brief Disables a PWM channel and its notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note The function has effect at the next cycle start. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { + +} + +/** + * @brief Enables the periodic activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @note If the notification is already enabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) { + +} + +/** + * @brief Disables the periodic activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @note If the notification is already disabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) { + +} + +/** + * @brief Enables a channel de-activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @pre The channel must have been activated using @p pwmEnableChannel(). + * @note If the notification is already enabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_enable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel) { + +} + +/** + * @brief Disables a channel de-activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @pre The channel must have been activated using @p pwmEnableChannel(). + * @note If the notification is already disabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_disable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel) { + +} + +/** + * @brief Common TIM2...TIM5,TIM9 IRQ handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_serve_interrupt(PWMDriver *pwmp) { + +} + +#endif /* HAL_USE_PWM == TRUE */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/TIMv2/hal_pwm_lld.h b/os/hal/ports/ES32/LLD/TIMv2/hal_pwm_lld.h new file mode 100644 index 0000000000..9f10a4d1aa --- /dev/null +++ b/os/hal/ports/ES32/LLD/TIMv2/hal_pwm_lld.h @@ -0,0 +1,609 @@ +/* + Copyright (C) 2020 + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_pwm_lld.h + * @brief ES32 PWM subsystem low level driver header. + * + * @addtogroup PWM + * @{ + */ + +#ifndef HAL_PWM_LLD_H +#define HAL_PWM_LLD_H + +#if (HAL_USE_PWM == TRUE) || defined(__DOXYGEN__) + + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Number of PWM channels per PWM driver. + */ +#define PWM_CHANNELS 4 + +/** + * @name ES32-specific PWM complementary output mode macros + * @{ + */ +/** + * @brief Complementary output modes mask. + * @note This is an ES32-specific setting. + */ +#define PWM_COMPLEMENTARY_OUTPUT_MASK 0xF0 + +/** + * @brief Complementary output not driven. + * @note This is an ES32-specific setting. + */ +#define PWM_COMPLEMENTARY_OUTPUT_DISABLED 0x00 + +/** + * @brief Complementary output, active is logic level one. + * @note This is an ES32-specific setting. + * @note This setting is only available if the timer supports the + * BDTR register. + */ +#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH 0x10 + +/** + * @brief Complementary output, active is logic level zero. + * @note This is an ES32-specific setting. + * @note This setting is only available if the timer supports the + * BDTR register. + */ +#define PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW 0x20 + + +#define PWM_COMPLEMENTARY_INTERRUPT_MASK (TIMER_IFM_UPD | TIMER_IFM_CH1 | \ + TIMER_IFM_CH2 | TIMER_IFM_CH3 | \ + TIMER_IFM_CH4 | TIMER_IFM_COM | \ + TIMER_IFM_TRGI | TIMER_IFM_BRK | \ + TIMER_IFM_CH1OV| TIMER_IFM_CH2OV| \ + TIMER_IFM_CH3OV| TIMER_IFM_CH4OV) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ + +/** + * @brief PWM_AD16C4T1 driver enable switch. + * @details If set to @p TRUE the support for PWM_AD16C4T1 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_PWM_USE_AD16C4T1) || defined(__DOXYGEN__) +#define ES32_PWM_USE_AD16C4T1 FALSE +#endif + +/** + * @brief PWM_GP32C4T1 driver enable switch. + * @details If set to @p TRUE the support for PWM_GP32C4T1 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_PWM_USE_GP32C4T1) || defined(__DOXYGEN__) +#define ES32_PWM_USE_GP32C4T1 FALSE +#endif + +/** + * @brief PWM_GP16C4T1 driver enable switch. + * @details If set to @p TRUE the support for PWM_GP16C4T1 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_PWM_USE_GP16C4T1) || defined(__DOXYGEN__) +#define ES32_PWM_USE_GP16C4T1 FALSE +#endif + +/** + * @brief PWM_GP16C4T2 driver enable switch. + * @details If set to @p TRUE the support for PWM_GP16C4T2 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_PWM_USE_GP16C4T2) || defined(__DOXYGEN__) +#define ES32_PWM_USE_GP16C4T2 FALSE +#endif + +/** + * @brief PWM_GP16C4T3 driver enable switch. + * @details If set to @p TRUE the support for PWM_GP16C4T3 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_PWM_USE_GP16C4T3) || defined(__DOXYGEN__) +#define ES32_PWM_USE_GP16C4T3 FALSE +#endif + +/** + * @brief PWM_GP16C2T1 driver enable switch. + * @details If set to @p TRUE the support for PWM_GP16C2T1 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_PWM_USE_GP16C2T1) || defined(__DOXYGEN__) +#define ES32_PWM_USE_GP16C2T1 FALSE +#endif + +/** + * @brief PWM_GP16C2T2 driver enable switch. + * @details If set to @p TRUE the support for PWM_GP16C2T2 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_PWM_USE_GP16C2T2) || defined(__DOXYGEN__) +#define ES32_PWM_USE_GP16C2T2 FALSE +#endif + +/** + * @brief PWM_GP16C2T3 driver enable switch. + * @details If set to @p TRUE the support for PWM_GP16C2T3 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_PWM_USE_GP16C2T3) || defined(__DOXYGEN__) +#define ES32_PWM_USE_GP16C2T3 FALSE +#endif + +/** + * @brief PWM_GP16C2T4 driver enable switch. + * @details If set to @p TRUE the support for PWM_GP16C2T4 is included. + * @note The default is @p FALSE. + */ +#if !defined(ES32_PWM_USE_GP16C2T4) || defined(__DOXYGEN__) +#define ES32_PWM_USE_GP16C2T4 FALSE +#endif + +/** + * @brief PWM_AD16C4T1 interrupt priority level setting. + */ +#if !defined(ES32_PWM_AD16C4T1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define ES32_PWM_AD16C4T1_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWM_GP32C4T1 interrupt priority level setting. + */ +#if !defined(ES32_PWM_GP32C4T1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define ES32_PWM_GP32C4T1_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWM_GP16C4T1 interrupt priority level setting. + */ +#if !defined(ES32_PWM_GP16C4T1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define ES32_PWM_GP16C4T1_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWM_GP16C4T2 interrupt priority level setting. + */ +#if !defined(ES32_PWM_GP16C4T2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define ES32_PWM_GP16C4T2_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWM_GP16C4T3 interrupt priority level setting. + */ +#if !defined(ES32_PWM_GP16C4T3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define ES32_PWM_GP16C4T3_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWM_GP16C2T1 interrupt priority level setting. + */ +#if !defined(ES32_PWM_GP16C2T1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define ES32_PWM_GP16C2T1_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWM_GP16C2T2 interrupt priority level setting. + */ +#if !defined(ES32_PWM_GP16C2T2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define ES32_PWM_GP16C2T2_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWM_GP16C2T3 interrupt priority level setting. + */ +#if !defined(ES32_PWM_GP16C2T3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define ES32_PWM_GP16C2T3_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWM_GP16C2T4 interrupt priority level setting. + */ +#if !defined(ES32_PWM_GP16C2T4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define ES32_PWM_GP16C2T4_IRQ_PRIORITY 7 +#endif + +/*===========================================================================*/ +/* Configuration checks. */ +/*===========================================================================*/ + +#if !defined(ES32_HAS_AD16C4T1) +#define ES32_HAS_AD16C4T1 TRUE +#endif + +#if !defined(ES32_HAS_GP32C4T1) +#define ES32_HAS_GP32C4T1 TRUE +#endif + +#if !defined(ES32_HAS_GP16C4T1) +#define ES32_HAS_GP16C4T1 TRUE +#endif + +#if !defined(ES32_HAS_GP16C4T2) +#define ES32_HAS_GP16C4T2 TRUE +#endif + +#if !defined(ES32_HAS_GP16C4T3) +#define ES32_HAS_GP16C4T3 TRUE +#endif + +#if !defined(ES32_HAS_GP16C2T1) +#define ES32_HAS_GP16C2T1 TRUE +#endif + +#if !defined(ES32_HAS_GP16C2T2) +#define ES32_HAS_GP16C2T2 TRUE +#endif + +#if !defined(ES32_HAS_GP16C2T3) +#define ES32_HAS_GP16C2T3 TRUE +#endif + +#if !defined(ES32_HAS_GP16C2T4) +#define ES32_HAS_GP16C2T4 TRUE +#endif + +#if ES32_PWM_USE_AD16C4T1 && !ES32_HAS_AD16C4T1 +#error "AD16C4T1 not present in the selected device" +#endif + +#if ES32_PWM_USE_GP32C4T1 && !ES32_HAS_GP32C4T1 +#error "GP32C4T1 not present in the selected device" +#endif + +#if ES32_PWM_USE_GP16C4T1 && !ES32_HAS_GP16C4T1 +#error "GP16C4T1 not present in the selected device" +#endif + +#if ES32_PWM_USE_GP16C4T2 && !ES32_HAS_GP16C4T2 +#error "GP16C4T2 not present in the selected device" +#endif + +#if ES32_PWM_USE_GP16C4T3 && !ES32_HAS_GP16C4T3 +#error "GP16C4T3 not present in the selected device" +#endif + +#if ES32_PWM_USE_GP16C2T1 && !ES32_HAS_GP16C2T1 +#error "GP16C2T1 not present in the selected device" +#endif + +#if ES32_PWM_USE_GP16C2T2 && !ES32_HAS_GP16C2T2 +#error "GP16C2T2 not present in the selected device" +#endif + +#if ES32_PWM_USE_GP16C2T3 && !ES32_HAS_GP16C2T3 +#error "GP16C2T3 not present in the selected device" +#endif + +#if ES32_PWM_USE_GP16C2T4 && !ES32_HAS_GP16C2T4 +#error "GP16C2T4 not present in the selected device" +#endif + +#if !ES32_PWM_USE_AD16C4T1 && !ES32_PWM_USE_GP32C4T1 && \ + !ES32_PWM_USE_GP16C4T1 && !ES32_PWM_USE_GP16C4T2 && \ + !ES32_PWM_USE_GP16C4T3 && !ES32_PWM_USE_GP16C2T1 && \ + !ES32_PWM_USE_GP16C2T2 && !ES32_PWM_USE_GP16C2T3 && \ + !ES32_PWM_USE_GP16C2T4 +#error "PWM driver activated but no TIM peripheral assigned" +#endif + +/* Checks on allocation of TIMx units.*/ +#if ES32_PWM_USE_AD16C4T1 +#if defined(ES32_AD16C4T1_IS_USED) +#error "PWM_AD16C4T1 requires AD16C4T1 but the timer is already used" +#else +#define ES32_AD16C4T1_IS_USED +#endif +#endif + +#if ES32_PWM_USE_GP32C4T1 +#if defined(ES32_GP32C4T1_IS_USED) +#error "PWM_GP32C4T1 requires GP32C4T1 but the timer is already used" +#else +#define ES32_GP32C4T1_IS_USED +#endif +#endif + +#if ES32_PWM_USE_GP16C4T1 +#if defined(ES32_GP16C4T1_IS_USED) +#error "PWM_GP16C4T1 requires GP16C4T1 but the timer is already used" +#else +#define ES32_GP16C4T1_IS_USED +#endif +#endif + +#if ES32_PWM_USE_GP16C4T2 +#if defined(ES32_GP16C4T2_IS_USED) +#error "PWM_GP16C4T2 requires GP16C4T2 but the timer is already used" +#else +#define ES32_GP16C4T2_IS_USED +#endif +#endif + +#if ES32_PWM_USE_GP16C4T3 +#if defined(ES32_GP16C4T3_IS_USED) +#error "PWM_GP16C4T3 requires GP16C4T3 but the timer is already used" +#else +#define ES32_GP16C4T3_IS_USED +#endif +#endif + +#if ES32_PWM_USE_GP16C2T1 +#if defined(ES32_GP16C2T1_IS_USED) +#error "PWM_GP16C2T1 requires GP16C2T1 but the timer is already used" +#else +#define ES32_GP16C2T1_IS_USED +#endif +#endif + +#if ES32_PWM_USE_GP16C2T2 +#if defined(ES32_GP16C2T2_IS_USED) +#error "PWM_GP16C2T2 requires GP16C2T2 but the timer is already used" +#else +#define ES32_GP16C2T2_IS_USED +#endif +#endif + +#if ES32_PWM_USE_GP16C2T3 +#if defined(ES32_GP16C2T3_IS_USED) +#error "PWM_GP16C2T3 requires GP16C2T3 but the timer is already used" +#else +#define ES32_GP16C2T3_IS_USED +#endif +#endif + +#if ES32_PWM_USE_GP16C2T4 +#if defined(ES32_GP16C2T4_IS_USED) +#error "PWM_GP16C2T4 requires GP16C2T4 but the timer is already used" +#else +#define ES32_GP16C2T4_IS_USED +#endif +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a PWM mode. + */ +typedef uint32_t pwmmode_t; + +/** + * @brief Type of a PWM channel. + */ +typedef uint8_t pwmchannel_t; + +/** + * @brief Type of a channels mask. + */ +typedef uint32_t pwmchnmsk_t; + +/** + * @brief Type of a PWM counter. + */ +typedef uint32_t pwmcnt_t; + +/** + * @brief Type of a PWM driver channel configuration structure. + */ +typedef struct { + /** + * @brief Channel active logic level. + */ + pwmmode_t mode; + /** + * @brief Channel callback pointer. + * @note This callback is invoked on the channel compare event. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /* End of the mandatory fields.*/ +} PWMChannelConfig; + +/** + * @brief Type of a PWM driver configuration structure. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + uint32_t frequency; + /** + * @brief PWM period in ticks. + * @note The low level can use assertions in order to catch invalid + * period specifications. + */ + pwmcnt_t period; + /** + * @brief Periodic callback pointer. + * @note This callback is invoked on PWM counter reset. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /** + * @brief Channels configurations. + */ + PWMChannelConfig channels[PWM_CHANNELS]; + /* End of the mandatory fields.*/ + /** + * @brief TIM CON2 register initialization data. + * @note The value of this field should normally be equal to zero. + */ + uint32_t con2; + /** + * @brief TIM BDCFG (break & dead-time) register initialization data. + * @note The value of this field should normally be equal to zero. + */ \ + uint32_t bdcfg; + /** + * @brief TIM DMAEN register initialization data. + * @note The value of this field should normally be equal to zero. + * @note Only the DMA-related bits can be specified in this field. + */ + uint32_t dmaen; +} PWMConfig; + +/** + * @brief Structure representing a PWM driver. + */ +struct PWMDriver { + /** + * @brief Driver state. + */ + pwmstate_t state; + /** + * @brief Current driver configuration data. + */ + const PWMConfig *config; + /** + * @brief Current PWM period in ticks. + */ + pwmcnt_t period; + /** + * @brief Mask of the enabled channels. + */ + pwmchnmsk_t enabled; + /** + * @brief Number of channels in this instance. + */ + pwmchannel_t channels; +#if defined(PWM_DRIVER_EXT_FIELDS) + PWM_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Timer base clock. + */ + /* + uint32_t clock; + */ + /** + * @brief Presence of BDCFG register. + */ + bool has_bdcfg; + /** + * @brief Pointer to the TIMx registers block. + */ + TIMER_TypeDef *tim; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note The function has effect at the next cycle start. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @notapi + */ +#define pwm_lld_change_period(pwmp, period) \ + ((pwmp)->tim->AR = ((period) - 1)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if ES32_PWM_USE_AD16C4T1 && !defined(__DOXYGEN__) +extern PWMDriver PWM_AD16C4T1; +#endif + +#if ES32_PWM_USE_GP32C4T1 && !defined(__DOXYGEN__) +extern PWMDriver PWM_GP32C4T1; +#endif + +#if ES32_PWM_USE_GP16C4T1 && !defined(__DOXYGEN__) +extern PWMDriver PWM_GP16C4T1; +#endif + +#if ES32_PWM_USE_GP16C4T2 && !defined(__DOXYGEN__) +extern PWMDriver PWM_GP16C4T2; +#endif + +#if ES32_PWM_USE_GP16C4T3 && !defined(__DOXYGEN__) +extern PWMDriver PWM_GP16C4T3; +#endif + +#if ES32_PWM_USE_GP16C2T1 && !defined(__DOXYGEN__) +extern PWMDriver PWM_GP16C2T1; +#endif + +#if ES32_PWM_USE_GP16C2T2 && !defined(__DOXYGEN__) +extern PWMDriver PWM_GP16C2T2; +#endif + +#if ES32_PWM_USE_GP16C2T3 && !defined(__DOXYGEN__) +extern PWMDriver PWM_GP16C2T3; +#endif + +#if ES32_PWM_USE_GP16C2T4 && !defined(__DOXYGEN__) +extern PWMDriver PWM_GP16C2T4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void pwm_lld_init(void); + void pwm_lld_start(PWMDriver *pwmp); + void pwm_lld_stop(PWMDriver *pwmp); + void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width); + void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); + void pwm_lld_enable_periodic_notification(PWMDriver *pwmp); + void pwm_lld_disable_periodic_notification(PWMDriver *pwmp); + void pwm_lld_enable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel); + void pwm_lld_disable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel); + void pwm_lld_serve_interrupt(PWMDriver *pwmp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PWM == TRUE */ + +#endif /* HAL_PWM_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/TIMv2/hal_st_lld.c b/os/hal/ports/ES32/LLD/TIMv2/hal_st_lld.c new file mode 100644 index 0000000000..3ad7cf1d62 --- /dev/null +++ b/os/hal/ports/ES32/LLD/TIMv2/hal_st_lld.c @@ -0,0 +1,93 @@ +/* + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_st_lld.c + * @brief PLATFORM ST subsystem low level driver source. + * + * @addtogroup ST + * @{ + */ + +#include "hal.h" + +#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__) +/** + * @brief System Timer vector. + * @details This interrupt is used for system tick in periodic mode. + * + * @isr + */ +OSAL_IRQ_HANDLER(vector7) +{ + csi_coret_clr((md_cmu_get_sys_clock()) / 1000, 0); + md_inc_tick(); + + osalOsTimerHandlerI(); + + if (chSchIsPreemptionRequired()) + { + chSchDoPreemption(); + } +} +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ST driver initialization. + * + * @notapi + */ +void st_lld_init(void) +{ +#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) + md_init_1ms_tick(); + +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ +} + +#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/TIMv2/hal_st_lld.h b/os/hal/ports/ES32/LLD/TIMv2/hal_st_lld.h new file mode 100644 index 0000000000..7ad6aaa86c --- /dev/null +++ b/os/hal/ports/ES32/LLD/TIMv2/hal_st_lld.h @@ -0,0 +1,151 @@ +/* + Copyright (C) 2020 Yaotian Feng + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under SYST_RVRthe License. +*/ + +/** + * @file hal_st_lld.h + * @brief PLATFORM ST subsystem low level driver header. + * @details This header is designed to be include-able without having to + * include other files from the HAL. + * + * @addtogroup ST + * @{ + */ + +#ifndef HAL_ST_LLD_H +#define HAL_ST_LLD_H + +#include "mcuconf.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +void st_lld_init(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Driver inline functions. */ +/*===========================================================================*/ + +#define SYST_CSR (*((volatile uint32_t*)0xE000E010)) +#define SYST_RVR (*((volatile uint32_t*)0xE000E014)) +#define SYST_CVR (*((volatile uint32_t*)0xE000E018)) +#define SYST_CALIB (*((volatile uint32_t*)0xE000E01C)) + +/** + * @brief Returns the time counter value. + * + * @return The counter value. + * + * @notapi + */ +static inline systime_t st_lld_get_counter(void) +{ + return 0;//(systime_t) SYST_CVR; +} + +/** + * @brief Starts the alarm. + * @note Makes sure that no spurious alarms are triggered after + * this call. + * + * @param[in] abstime the time to be set for the first alarm + * + * @notapi + */ +static inline void st_lld_start_alarm(systime_t abstime) +{ +// SYST_RVR = (uint32_t)abstime; +// SYST_CSR = 0b111; +// SYST_CVR = 0; // Trigger reload +} + +/** + * @brief Stops the alarm interrupt. + * + * @notapi + */ +static inline void st_lld_stop_alarm(void) +{ +// SYST_CVR &= ~((uint32_t)0b10); +} + +/** + * @brief Sets the alarm time. + * + * @param[in] abstime the time to be set for the next alarm + * + * @notapi + */ +static inline void st_lld_set_alarm(systime_t abstime) +{ +// SYST_RVR = (uint32_t)abstime; +} + +/** + * @brief Returns the current alarm time. + * + * @return The currently set alarm time. + * + * @notapi + */ +static inline systime_t st_lld_get_alarm(void) +{ + return 0;//(systime_t)SYST_RVR; +} + +/** + * @brief Determines if the alarm is active. + * + * @return The alarm status. + * @retval false if the alarm is not active. + * @retval true is the alarm is active + * + * @notapi + */ +static inline bool st_lld_is_alarm_active(void) +{ + return 0;//((SYST_CVR & 0b10) != 0); +} + +#endif /* HAL_ST_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.c b/os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.c index 50369d76e7..e5dc5df8ef 100644 --- a/os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.c +++ b/os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.c @@ -25,12 +25,11 @@ #include "hal.h" #include "ald_usb.h" +#include "string.h" #include "md_utils.h" #if (HAL_USE_USB == TRUE) || defined(__DOXYGEN__) -#define ES_USB_PERH_EP_MAX_INDEX (6U) - #define USB_CTRL_EP_MPS 64 #ifndef MIN @@ -442,7 +441,7 @@ int usbd_ep_start_write(const uint8_t ep, const uint8_t *data, uint32_t data_len old_ep_idx = musb_get_active_ep(); musb_set_active_ep(ep_idx); - if((USB->CSR0L_TXCSRL) & USB_TXCSRL_TXRDY_MSK) + if(es_usbd_ep_tx_ready_state(ep_idx)) { musb_set_active_ep(old_ep_idx); return -3; @@ -549,6 +548,11 @@ void handle_ep0(void) USB->CSR0L_TXCSRL = ALD_USB_CSR0L_SETENDC; } + if (g_musb_udc.dev_addr > 0) { + USB->FADDR = g_musb_udc.dev_addr; + g_musb_udc.dev_addr = 0; + } + switch (usb_ep0_state) { case USB_EP0_STATE_SETUP: if (ep0_status & ALD_USB_CSR0L_RXRDY) { @@ -642,7 +646,11 @@ const uint8_t __lowest_bit_bitmap[] = * @brief USB interrupt handler. * @isr */ +#ifdef ES32VF2264 +PORT_FAST_IRQ_HANDLER(vector27) +#else OSAL_IRQ_HANDLER(VectorBC) +#endif { volatile uint32_t i; uint8_t old_ep_idx; @@ -937,11 +945,11 @@ void usb_lld_reset(USBDriver *usbp) */ void usb_lld_set_address(USBDriver *usbp) { - volatile uint32_t i; - - for(i = 0;i < 9999;i++){} - - USB->FADDR = usbp->address; + if (usbp->address == 0) { + ald_usb_dev_set_addr(0); + } + + g_musb_udc.dev_addr = usbp->address; } /** diff --git a/os/hal/ports/common/RISCV-CLIC/eclic.c b/os/hal/ports/common/RISCV-CLIC/eclic.c new file mode 100644 index 0000000000..995ee89e3f --- /dev/null +++ b/os/hal/ports/common/RISCV-CLIC/eclic.c @@ -0,0 +1,85 @@ +/* + ChibiOS - Copyright (C) 2021 Stefan Kerkmann + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file common/RISCV-ECLIC/eclic.c + * @brief RISC-V ECLIC interrupt support code. + * + * @addtogroup COMMON_RISCV_ECLIC + * @{ + */ + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Sets the level and trigger of an interrupt handler and enables it. + * + * @param[in] n the interrupt number + * @param[in] level the interrupt level + * @param[in] trigger the interrupt trigger + */ +void eclicEnableVector(uint32_t n, uint32_t prio, uint32_t trigger) { + __ECLIC_SetLevelIRQ(n, prio); + __ECLIC_SetTrigIRQ(n, trigger); + __ECLIC_EnableIRQ(n); +} + +/** + * @brief Disables an interrupt handler. + * + * @param[in] n the interrupt number + */ +void eclicDisableVector(uint32_t n) { __ECLIC_DisableIRQ(n); } + +/** + * @brief Clears a pending interrupt source. + * + * @param[in] n the interrupt number + */ +void eclicClearPending(uint32_t n) { __ECLIC_ClearPendingIRQ(n); } + +/** + * @brief System Reset + */ +void __attribute__((noreturn)) eclicSystemReset(void) { + SysTimer_SoftwareReset(); + while(1); +} +/** @} */ diff --git a/os/hal/ports/common/RISCV-CLIC/eclic.h b/os/hal/ports/common/RISCV-CLIC/eclic.h new file mode 100644 index 0000000000..72f15591a6 --- /dev/null +++ b/os/hal/ports/common/RISCV-CLIC/eclic.h @@ -0,0 +1,66 @@ +/* + ChibiOS - Copyright (C) 2021 Stefan Kerkmann + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file common/RISCV-ECLIC/eclic.h + * @brief RISC-V ECLIC support macros and structures. + * + * @addtogroup COMMON_RISCV_ECLIC + * @{ + */ + +#ifndef ECLIC_H +#define ECLIC_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +void eclicInit(void); +void eclicEnableVector(uint32_t n, uint32_t level, uint32_t trigger); +void eclicDisableVector(uint32_t n); +void eclicClearPending(uint32_t n); +void eclicSystemReset(void); +#ifdef __cplusplus +} +#endif + +#endif /* ECLIC_H */ + +/** @} */